1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
119 (FPSCR_PR 524288) ;; 1 << 19
120 (FPSCR_SZ 1048576) ;; 1 << 20
121 (FPSCR_FR 2097152) ;; 1 << 21
124 (define_c_enum "unspec" [
125 ;; These are used with unspec.
164 ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT).
165 ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent.
168 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
170 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
173 UNSPEC_BUILTIN_STRLEN
176 (define_c_enum "unspecv" [
177 ;; These are used with unspec_volatile.
194 ;; -------------------------------------------------------------------------
196 ;; -------------------------------------------------------------------------
201 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5"
202 (const (symbol_ref "sh_cpu_attr")))
204 (define_attr "endian" "big,little"
205 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
206 (const_string "little") (const_string "big"))))
208 ;; Indicate if the default fpu mode is single precision.
209 (define_attr "fpu_single" "yes,no"
210 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
211 (const_string "yes") (const_string "no"))))
213 (define_attr "fmovd" "yes,no"
214 (const (if_then_else (symbol_ref "TARGET_FMOVD")
215 (const_string "yes") (const_string "no"))))
217 (define_attr "pipe_model" "sh1,sh4,sh5media"
219 (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media")
220 (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
221 (const_string "sh1"))))
223 ;; cbranch conditional branch instructions
224 ;; jump unconditional jumps
225 ;; arith ordinary arithmetic
226 ;; arith3 a compound insn that behaves similarly to a sequence of
227 ;; three insns of type arith
228 ;; arith3b like above, but might end with a redirected branch
230 ;; load_si Likewise, SImode variant for general register.
231 ;; fload Likewise, but load to fp register.
233 ;; fstore floating point register to memory
234 ;; move general purpose register to register
235 ;; movi8 8-bit immediate to general purpose register
236 ;; mt_group other sh4 mt instructions
237 ;; fmove register to register, floating point
238 ;; smpy word precision integer multiply
239 ;; dmpy longword or doublelongword precision integer multiply
241 ;; pload load of pr reg, which can't be put into delay slot of rts
242 ;; prset copy register to pr reg, ditto
243 ;; pstore store of pr reg, which can't be put into delay slot of jsr
244 ;; prget copy pr to register, ditto
245 ;; pcload pc relative load of constant value
246 ;; pcfload Likewise, but load to fp register.
247 ;; pcload_si Likewise, SImode variant for general register.
248 ;; rte return from exception
249 ;; sfunc special function call with known used registers
250 ;; call function call
252 ;; fpscr_toggle toggle a bit in the fpscr
253 ;; fdiv floating point divide (or square root)
254 ;; gp_fpul move from general purpose register to fpul
255 ;; fpul_gp move from fpul to general purpose register
256 ;; mac_gp move from mac[lh] to general purpose register
257 ;; gp_mac move from general purpose register to mac[lh]
258 ;; mac_mem move from mac[lh] to memory
259 ;; mem_mac move from memory to mac[lh]
260 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
261 ;; ftrc_s fix_truncsfsi2_i4
262 ;; dfdiv double precision floating point divide (or square root)
263 ;; cwb ic_invalidate_line_i
264 ;; movua SH4a unaligned load
265 ;; fsrra square root reciprocal approximate
266 ;; fsca sine and cosine approximate
267 ;; tls_load load TLS related address
268 ;; arith_media SHmedia arithmetic, logical, and shift instructions
269 ;; cbranch_media SHmedia conditional branch instructions
270 ;; cmp_media SHmedia compare instructions
271 ;; dfdiv_media SHmedia double precision divide and square root
272 ;; dfmul_media SHmedia double precision multiply instruction
273 ;; dfparith_media SHmedia double precision floating point arithmetic
274 ;; dfpconv_media SHmedia double precision floating point conversions
275 ;; dmpy_media SHmedia longword multiply
276 ;; fcmp_media SHmedia floating point compare instructions
277 ;; fdiv_media SHmedia single precision divide and square root
278 ;; fload_media SHmedia floating point register load instructions
279 ;; fmove_media SHmedia floating point register moves (inc. fabs and fneg)
280 ;; fparith_media SHmedia single precision floating point arithmetic
281 ;; fpconv_media SHmedia single precision floating point conversions
282 ;; fstore_media SHmedia floating point register store instructions
283 ;; gettr_media SHmedia gettr instruction
284 ;; invalidate_line_media SHmedia invalidate_line sequence
285 ;; jump_media SHmedia unconditional branch instructions
286 ;; load_media SHmedia general register load instructions
287 ;; pt_media SHmedia pt instruction (expanded by assembler)
288 ;; ptabs_media SHmedia ptabs instruction
289 ;; store_media SHmedia general register store instructions
290 ;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
291 ;; mac_media SHmedia mac-style fixed point operations
292 ;; d2mpy_media SHmedia: two 32-bit integer multiplies
293 ;; atrans_media SHmedia approximate transcendental functions
294 ;; ustore_media SHmedia unaligned stores
295 ;; nil no-op move, will be deleted.
298 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
299 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
300 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
301 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
302 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
303 arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,
304 dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,
305 fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,
306 jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,
307 d2mpy_media,atrans_media,ustore_media,nil,other"
308 (const_string "other"))
310 ;; We define a new attribute namely "insn_class".We use
311 ;; this for the DFA based pipeline description.
313 ;; mt_group SH4 "mt" group instructions.
315 ;; ex_group SH4 "ex" group instructions.
317 ;; ls_group SH4 "ls" group instructions.
319 (define_attr "insn_class"
320 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
321 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
322 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
323 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
324 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
325 (eq_attr "type" "cbranch,jump") (const_string "br_group")
326 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
327 (const_string "fe_group")
328 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
329 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
330 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
331 (const_string "none")))
333 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
334 ;; so these do not belong in an insn group, although they are modeled
335 ;; with their own define_insn_reservations.
337 ;; Indicate what precision must be selected in fpscr for this insn, if any.
338 (define_attr "fp_mode" "single,double,none" (const_string "none"))
340 ;; Indicate if the fpu mode is set by this instruction
341 ;; "unknown" must have the value as "none" in fp_mode, and means
342 ;; that the instruction/abi has left the processor in an unknown
344 ;; "none" means that nothing has changed and no mode is set.
345 ;; This attribute is only used for the Renesas ABI.
346 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
348 ; If a conditional branch destination is within -252..258 bytes away
349 ; from the instruction it can be 2 bytes long. Something in the
350 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
351 ; branches are initially assumed to be 16 bytes long.
352 ; In machine_dependent_reorg, we split all branches that are longer than
355 ;; The maximum range used for SImode constant pool entries is 1018. A final
356 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
357 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
358 ;; instruction around the pool table, 2 bytes of alignment before the table,
359 ;; and 30 bytes of alignment after the table. That gives a maximum total
360 ;; pool size of 1058 bytes.
361 ;; Worst case code/pool content size ratio is 1:2 (using asms).
362 ;; Thus, in the worst case, there is one instruction in front of a maximum
363 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
364 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
365 ;; If we have a forward branch, the initial table will be put after the
366 ;; unconditional branch.
368 ;; ??? We could do much better by keeping track of the actual pcloads within
369 ;; the branch range and in the pcload range in front of the branch range.
371 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
373 (define_attr "short_cbranch_p" "no,yes"
374 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
378 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
380 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
382 ] (const_string "no")))
384 (define_attr "med_branch_p" "no,yes"
385 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
388 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
390 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
393 ] (const_string "no")))
395 (define_attr "med_cbranch_p" "no,yes"
396 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
399 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
401 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
404 ] (const_string "no")))
406 (define_attr "braf_branch_p" "no,yes"
407 (cond [(match_test "! TARGET_SH2")
409 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
412 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
414 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
417 ] (const_string "no")))
419 (define_attr "braf_cbranch_p" "no,yes"
420 (cond [(match_test "! TARGET_SH2")
422 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
425 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
427 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
430 ] (const_string "no")))
432 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
433 ;; For wider ranges, we need a combination of a code and a data part.
434 ;; If we can get a scratch register for a long range jump, the code
435 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
436 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
437 ;; long; otherwise, it must be 6 bytes long.
439 ;; All other instructions are two bytes long by default.
441 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
442 ;; but getattrtab doesn't understand this.
443 (define_attr "length" ""
444 (cond [(eq_attr "type" "cbranch")
445 (cond [(eq_attr "short_cbranch_p" "yes")
447 (eq_attr "med_cbranch_p" "yes")
449 (eq_attr "braf_cbranch_p" "yes")
451 ;; ??? using pc is not computed transitively.
452 (ne (match_dup 0) (match_dup 0))
454 (match_test "flag_pic")
457 (eq_attr "type" "jump")
458 (cond [(eq_attr "med_branch_p" "yes")
460 (and (match_test "prev_nonnote_insn (insn)")
461 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
463 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
464 (symbol_ref "code_for_indirect_jump_scratch"))))
465 (cond [(eq_attr "braf_branch_p" "yes")
467 (not (match_test "flag_pic"))
469 (match_test "TARGET_SH2")
470 (const_int 10)] (const_int 18))
471 (eq_attr "braf_branch_p" "yes")
473 ;; ??? using pc is not computed transitively.
474 (ne (match_dup 0) (match_dup 0))
476 (match_test "flag_pic")
479 (eq_attr "type" "pt_media")
480 (if_then_else (match_test "TARGET_SHMEDIA64")
481 (const_int 20) (const_int 12))
482 (and (eq_attr "type" "jump_media")
483 (match_test "TARGET_SH5_CUT2_WORKAROUND"))
485 ] (if_then_else (match_test "TARGET_SHMEDIA")
489 ;; DFA descriptions for the pipelines
492 (include "shmedia.md")
495 (include "iterators.md")
496 (include "predicates.md")
497 (include "constraints.md")
499 ;; Definitions for filling delay slots
501 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
503 (define_attr "banked" "yes,no"
504 (cond [(match_test "sh_loads_bankedreg_p (insn)")
505 (const_string "yes")]
506 (const_string "no")))
508 ;; ??? This should be (nil) instead of (const_int 0)
509 (define_attr "hit_stack" "yes,no"
510 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
512 (const_string "yes")))
514 (define_attr "interrupt_function" "no,yes"
515 (const (symbol_ref "current_function_interrupt")))
517 (define_attr "in_delay_slot" "yes,no"
518 (cond [(eq_attr "type" "cbranch") (const_string "no")
519 (eq_attr "type" "pcload,pcload_si") (const_string "no")
520 (eq_attr "type" "fpscr_toggle") (const_string "no")
521 (eq_attr "needs_delay_slot" "yes") (const_string "no")
522 (eq_attr "length" "2") (const_string "yes")
523 ] (const_string "no")))
525 (define_attr "cond_delay_slot" "yes,no"
526 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
527 ] (const_string "no")))
529 (define_attr "is_sfunc" ""
530 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
532 (define_attr "is_mac_media" ""
533 (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0)))
535 (define_attr "branch_zero" "yes,no"
536 (cond [(eq_attr "type" "!cbranch") (const_string "no")
537 (ne (symbol_ref "(next_active_insn (insn)\
538 == (prev_active_insn\
539 (XEXP (SET_SRC (PATTERN (insn)), 1))))\
540 && get_attr_length (next_active_insn (insn)) == 2")
542 (const_string "yes")]
543 (const_string "no")))
545 ;; SH4 Double-precision computation with double-precision result -
546 ;; the two halves are ready at different times.
547 (define_attr "dfp_comp" "yes,no"
548 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
549 (const_string "no")))
551 ;; Insns for which the latency of a preceding fp insn is decreased by one.
552 (define_attr "late_fp_use" "yes,no" (const_string "no"))
553 ;; And feeding insns for which this relevant.
554 (define_attr "any_fp_comp" "yes,no"
555 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
556 (const_string "yes")]
557 (const_string "no")))
559 (define_attr "any_int_load" "yes,no"
560 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
561 (const_string "yes")]
562 (const_string "no")))
564 (define_attr "highpart" "user, ignore, extend, depend, must_split"
565 (const_string "user"))
568 (eq_attr "needs_delay_slot" "yes")
569 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
571 ;; Since a normal return (rts) implicitly uses the PR register,
572 ;; we can't allow PR register loads in an rts delay slot.
573 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
574 ;; stack, and thus we can't put a pop instruction in its delay slot.
575 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
576 ;; pop instruction can go in the delay slot, unless it references a banked
577 ;; register (the register bank is switched by rte).
579 (eq_attr "type" "return")
580 [(and (eq_attr "in_delay_slot" "yes")
581 (ior (and (eq_attr "interrupt_function" "no")
582 (eq_attr "type" "!pload,prset"))
583 (and (eq_attr "interrupt_function" "yes")
584 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
585 (eq_attr "banked" "no"))))
588 ;; Since a call implicitly uses the PR register, we can't allow
589 ;; a PR register store in a jsr delay slot.
592 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
593 [(and (eq_attr "in_delay_slot" "yes")
594 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
596 ;; Say that we have annulled true branches, since this gives smaller and
597 ;; faster code when branches are predicted as not taken.
599 ;; ??? The non-annulled condition should really be "in_delay_slot",
600 ;; but insns that can be filled in non-annulled get priority over insns
601 ;; that can only be filled in anulled.
604 (and (eq_attr "type" "cbranch")
605 (match_test "TARGET_SH2"))
606 ;; SH2e has a hardware bug that pretty much prohibits the use of
607 ;; annulled delay slots.
608 [(eq_attr "cond_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
609 (not (eq_attr "cpu" "sh2e"))) (nil)])
611 ;; -------------------------------------------------------------------------
612 ;; SImode signed integer comparisons
613 ;; -------------------------------------------------------------------------
615 ;; Various patterns to generate the TST #imm, R0 instruction.
616 ;; Although this adds some pressure on the R0 register, it can potentially
617 ;; result in faster code, even if the operand has to be moved to R0 first.
618 ;; This is because on SH4 TST #imm, R0 and MOV Rm, Rn are both MT group
619 ;; instructions and thus will be executed in parallel. On SH4A TST #imm, R0
620 ;; is an EX group instruction but still can be executed in parallel with the
621 ;; MT group MOV Rm, Rn instruction.
623 ;; Usual TST #imm, R0 patterns for SI, HI and QI
624 ;; This is usually used for bit patterns other than contiguous bits
626 (define_insn "tstsi_t"
628 (eq:SI (and:SI (match_operand:SI 0 "logical_operand" "%z,r")
629 (match_operand:SI 1 "logical_operand" "K08,r"))
633 [(set_attr "type" "mt_group")])
635 (define_insn "tsthi_t"
637 (eq:SI (subreg:SI (and:HI (match_operand:HI 0 "logical_operand" "%z")
638 (match_operand 1 "const_int_operand")) 0)
641 && CONST_OK_FOR_K08 (INTVAL (operands[1]))"
643 [(set_attr "type" "mt_group")])
645 (define_insn "tstqi_t"
647 (eq:SI (subreg:SI (and:QI (match_operand:QI 0 "logical_operand" "%z")
648 (match_operand 1 "const_int_operand")) 0)
651 && (CONST_OK_FOR_K08 (INTVAL (operands[1]))
652 || CONST_OK_FOR_I08 (INTVAL (operands[1])))"
654 operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
657 [(set_attr "type" "mt_group")])
659 ;; Test low QI subreg against zero.
660 ;; This avoids unnecessary zero extension before the test.
661 (define_insn "*tstqi_t_zero"
663 (eq:SI (match_operand:QI 0 "logical_operand" "z") (const_int 0)))]
666 [(set_attr "type" "mt_group")])
668 ;; This pattern might be risky because it also tests the upper bits and not
669 ;; only the subreg. However, it seems that combine will get to this only
670 ;; when testing sign/zero extended values. In this case the extended upper
671 ;; bits do not matter.
672 (define_insn "*tst<mode>_t_zero"
676 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
677 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_le>)
679 "TARGET_SH1 && TARGET_LITTLE_ENDIAN"
681 [(set_attr "type" "mt_group")])
683 (define_insn "*tst<mode>_t_zero"
687 (and:SI (match_operand:SI 0 "arith_reg_operand" "%r")
688 (match_operand:SI 1 "arith_reg_operand" "r")) <lowpart_be>)
690 "TARGET_SH1 && TARGET_BIG_ENDIAN"
692 [(set_attr "type" "mt_group")])
694 ;; Extract LSB, negate and store in T bit.
695 (define_insn "tstsi_t_and_not"
697 (and:SI (not:SI (match_operand:SI 0 "logical_operand" "z"))
701 [(set_attr "type" "mt_group")])
703 ;; Extract contiguous bits and compare them against zero.
704 (define_insn "tst<mode>_t_zero_extract_eq"
706 (eq:SI (zero_extract:SI (match_operand:QIHISIDI 0 "logical_operand" "z")
707 (match_operand:SI 1 "const_int_operand")
708 (match_operand:SI 2 "const_int_operand"))
711 && CONST_OK_FOR_K08 (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]))"
713 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
716 [(set_attr "type" "mt_group")])
718 ;; This split is required when testing bits in a QI subreg.
723 (zero_extract:SI (match_operand 0 "logical_operand")
724 (match_operand 1 "const_int_operand")
725 (match_operand 2 "const_int_operand"))
726 (match_operand 3 "const_int_operand")
730 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
731 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
732 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 3))
735 if (GET_MODE (operands[0]) == QImode)
736 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
739 ;; Extract single bit, negate and store it in the T bit.
740 ;; Not used for SH4A.
741 (define_insn "tstsi_t_zero_extract_xor"
743 (zero_extract:SI (xor:SI (match_operand:SI 0 "logical_operand" "z")
744 (match_operand:SI 3 "const_int_operand"))
745 (match_operand:SI 1 "const_int_operand")
746 (match_operand:SI 2 "const_int_operand")))]
748 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2]) == INTVAL (operands[3])
749 && CONST_OK_FOR_K08 (INTVAL (operands[3]))"
751 [(set_attr "type" "mt_group")])
753 ;; Extract single bit, negate and store it in the T bit.
754 ;; Used for SH4A little endian.
755 (define_insn "tstsi_t_zero_extract_subreg_xor_little"
758 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
759 (match_operand:SI 3 "const_int_operand")) 0)
760 (match_operand:SI 1 "const_int_operand")
761 (match_operand:SI 2 "const_int_operand")))]
762 "TARGET_SH1 && TARGET_LITTLE_ENDIAN
763 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
764 == (INTVAL (operands[3]) & 255)
765 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
767 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
770 [(set_attr "type" "mt_group")])
772 ;; Extract single bit, negate and store it in the T bit.
773 ;; Used for SH4A big endian.
774 (define_insn "tstsi_t_zero_extract_subreg_xor_big"
777 (subreg:QI (xor:SI (match_operand:SI 0 "logical_operand" "z")
778 (match_operand:SI 3 "const_int_operand")) 3)
779 (match_operand:SI 1 "const_int_operand")
780 (match_operand:SI 2 "const_int_operand")))]
781 "TARGET_SH1 && TARGET_BIG_ENDIAN
782 && ZERO_EXTRACT_ANDMASK (operands[1], operands[2])
783 == (INTVAL (operands[3]) & 255)
784 && CONST_OK_FOR_K08 (INTVAL (operands[3]) & 255)"
786 operands[3] = GEN_INT (INTVAL (operands[3]) & 255);
789 [(set_attr "type" "mt_group")])
791 (define_insn "cmpeqsi_t"
793 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
794 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
800 [(set_attr "type" "mt_group")])
802 ;; FIXME: For some reason, on SH4A and SH2A combine fails to simplify this
803 ;; pattern by itself. What this actually does is:
804 ;; x == 0: (1 >> 0-0) & 1 = 1
805 ;; x != 0: (1 >> 0-x) & 1 = 0
806 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
807 (define_insn_and_split "*cmpeqsi_t"
811 (neg:SI (match_operand:SI 0 "arith_reg_operand" "r")))
816 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))])
818 (define_insn "cmpgtsi_t"
820 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
821 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
826 [(set_attr "type" "mt_group")])
828 (define_insn "cmpgesi_t"
830 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
831 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
836 [(set_attr "type" "mt_group")])
838 ;; FIXME: This is actually wrong. There is no way to literally move a
839 ;; general reg to t reg. Luckily, it seems that this pattern will be only
840 ;; used when the general reg is known be either '0' or '1' during combine.
841 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
842 ;; Due to interactions with other patterns, combine fails to pick the latter
843 ;; and invert the dependent logic.
844 (define_insn "*negtstsi"
845 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
848 [(set_attr "type" "mt_group")])
850 ;; Some integer sign comparison patterns can be realized with the div0s insn.
851 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
852 (define_insn "cmp_div0s_0"
854 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
855 (match_operand:SI 1 "arith_reg_operand" "r"))
859 [(set_attr "type" "arith")])
861 (define_insn "cmp_div0s_1"
863 (lt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
864 (match_operand:SI 1 "arith_reg_operand" "r"))
868 [(set_attr "type" "arith")])
870 (define_insn_and_split "*cmp_div0s_0"
871 [(set (match_operand:SI 0 "arith_reg_dest" "")
872 (lshiftrt:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
873 (match_operand:SI 2 "arith_reg_operand" ""))
875 (clobber (reg:SI T_REG))]
880 (lshiftrt:SI (xor:SI (match_dup 1) (match_dup 2)) (const_int 31)))
881 (set (match_dup 0) (reg:SI T_REG))])
883 (define_insn "*cmp_div0s_0"
885 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand" "%r")
887 (ge:SI (match_operand:SI 1 "arith_reg_operand" "r")
891 [(set_attr "type" "arith")])
893 (define_insn_and_split "*cmp_div0s_1"
894 [(set (match_operand:SI 0 "arith_reg_dest" "")
895 (ge:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "")
896 (match_operand:SI 2 "arith_reg_operand" ""))
898 (clobber (reg:SI T_REG))]
901 "&& can_create_pseudo_p ()"
903 ;; We have to go through the movnegt expander here which will handle the
904 ;; SH2A vs non-SH2A cases.
906 emit_insn (gen_cmp_div0s_1 (operands[1], operands[2]));
907 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
911 (define_insn_and_split "*cmp_div0s_1"
913 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
914 (match_operand:SI 1 "arith_reg_operand" ""))
918 "&& can_create_pseudo_p ()"
919 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
921 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
923 (define_insn_and_split "*cmp_div0s_1"
925 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
927 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
931 "&& can_create_pseudo_p ()"
932 [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1))
934 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
936 ;; -------------------------------------------------------------------------
937 ;; SImode compare and branch
938 ;; -------------------------------------------------------------------------
940 (define_expand "cbranchsi4"
942 (if_then_else (match_operator 0 "comparison_operator"
943 [(match_operand:SI 1 "arith_operand" "")
944 (match_operand:SI 2 "arith_operand" "")])
945 (label_ref (match_operand 3 "" ""))
947 (clobber (reg:SI T_REG))]
951 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
952 operands[2], operands[3]));
954 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
959 ;; Combine patterns to invert compare and branch operations for which we
960 ;; don't have actual comparison insns. These patterns are used in cases
961 ;; which appear after the initial cbranchsi expansion, which also does
962 ;; some condition inversion.
965 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
966 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
967 (label_ref (match_operand 2))
969 (clobber (reg:SI T_REG))]
971 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
972 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
973 (label_ref (match_dup 2))
976 ;; FIXME: Similar to the *cmpeqsi_t pattern above, for some reason, on SH4A
977 ;; and SH2A combine fails to simplify this pattern by itself.
978 ;; What this actually does is:
979 ;; x == 0: (1 >> 0-0) & 1 = 1
980 ;; x != 0: (1 >> 0-x) & 1 = 0
981 ;; Without this the test pr51244-8.c fails on SH2A and SH4A.
985 (eq (and:SI (lshiftrt:SI
987 (neg:SI (match_operand:SI 0 "arith_reg_operand" "")))
990 (label_ref (match_operand 2))
992 (clobber (reg:SI T_REG))]
994 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))
995 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
996 (label_ref (match_dup 2))
999 ;; FIXME: These could probably use code iterators for the compare op.
1002 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1003 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1004 (label_ref (match_operand 2))
1006 (clobber (reg:SI T_REG))]
1008 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1009 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1010 (label_ref (match_dup 2))
1015 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1016 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1017 (label_ref (match_operand 2))
1019 (clobber (reg:SI T_REG))]
1021 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1022 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1023 (label_ref (match_dup 2))
1028 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1029 (match_operand:SI 1 "arith_reg_operand" ""))
1030 (label_ref (match_operand 2))
1032 (clobber (reg:SI T_REG))]
1034 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1035 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1036 (label_ref (match_dup 2))
1041 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1042 (match_operand:SI 1 "arith_reg_operand" ""))
1043 (label_ref (match_operand 2))
1045 (clobber (reg:SI T_REG))]
1047 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1048 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1049 (label_ref (match_dup 2))
1052 ;; Compare and branch combine patterns for div0s comparisons.
1053 (define_insn_and_split "*cbranch_div0s"
1055 (if_then_else (lt (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1056 (match_operand:SI 1 "arith_reg_operand" ""))
1058 (label_ref (match_operand 2))
1060 (clobber (reg:SI T_REG))]
1064 [(set (reg:SI T_REG)
1065 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1067 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1068 (label_ref (match_dup 2))
1071 (define_insn_and_split "*cbranch_div0s"
1073 (if_then_else (ge (xor:SI (match_operand:SI 0 "arith_reg_operand" "")
1074 (match_operand:SI 1 "arith_reg_operand" ""))
1076 (label_ref (match_operand 2))
1078 (clobber (reg:SI T_REG))]
1082 [(set (reg:SI T_REG)
1083 (lt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 0)))
1085 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1086 (label_ref (match_dup 2))
1089 ;; -------------------------------------------------------------------------
1090 ;; SImode unsigned integer comparisons
1091 ;; -------------------------------------------------------------------------
1093 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1094 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1095 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1096 ;; handled here, something else would just load a '0' into the second operand
1097 ;; and do the comparison. We can do slightly better by just setting the
1099 (define_insn_and_split "cmpgeusi_t"
1100 [(set (reg:SI T_REG)
1101 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1102 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1105 "&& satisfies_constraint_Z (operands[1])"
1106 [(set (reg:SI T_REG) (const_int 1))]
1108 [(set_attr "type" "mt_group")])
1110 (define_insn "cmpgtusi_t"
1111 [(set (reg:SI T_REG)
1112 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1113 (match_operand:SI 1 "arith_reg_operand" "r")))]
1116 [(set_attr "type" "mt_group")])
1118 ;; -------------------------------------------------------------------------
1119 ;; DImode compare and branch
1120 ;; -------------------------------------------------------------------------
1122 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1123 ;; Therefore, we aim to have a set of three branches that go straight to the
1124 ;; destination, i.e. only one of them is taken at any one time.
1125 ;; This mechanism should also be slightly better for the sh4-200.
1127 (define_expand "cbranchdi4"
1129 (if_then_else (match_operator 0 "comparison_operator"
1130 [(match_operand:DI 1 "arith_operand" "")
1131 (match_operand:DI 2 "arith_operand" "")])
1132 (label_ref (match_operand 3 "" ""))
1134 (clobber (match_dup 4))
1135 (clobber (reg:SI T_REG))]
1136 "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA"
1138 enum rtx_code comparison;
1142 emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1],
1143 operands[2], operands[3]));
1146 else if (!TARGET_CBRANCHDI4)
1148 sh_emit_compare_and_branch (operands, DImode);
1153 if (expand_cbranchdi4 (operands, LAST_AND_UNUSED_RTX_CODE))
1156 comparison = prepare_cbranch_operands (operands, DImode,
1157 LAST_AND_UNUSED_RTX_CODE);
1158 if (comparison != GET_CODE (operands[0]))
1160 = gen_rtx_fmt_ee (comparison, VOIDmode, operands[1], operands[2]);
1161 operands[4] = gen_rtx_SCRATCH (SImode);
1165 (define_insn_and_split "cbranchdi4_i"
1167 (if_then_else (match_operator 0 "comparison_operator"
1168 [(match_operand:DI 1 "arith_operand" "r,r")
1169 (match_operand:DI 2 "arith_operand" "rN,I08")])
1170 (label_ref (match_operand 3 "" ""))
1172 (clobber (match_scratch:SI 4 "=X,&r"))
1173 (clobber (reg:SI T_REG))]
1176 "&& reload_completed"
1179 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1184 ;; -------------------------------------------------------------------------
1185 ;; DImode signed integer comparisons
1186 ;; -------------------------------------------------------------------------
1189 [(set (reg:SI T_REG)
1190 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1191 (match_operand:DI 1 "arith_operand" "r"))
1195 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1198 [(set_attr "length" "6")
1199 (set_attr "type" "arith3b")])
1201 (define_insn "cmpeqdi_t"
1202 [(set (reg:SI T_REG)
1203 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1204 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1207 static const char* alt[] =
1214 "cmp/eq %S1,%S0" "\n"
1216 " cmp/eq %R1,%R0" "\n"
1219 return alt[which_alternative];
1221 [(set_attr "length" "6")
1222 (set_attr "type" "arith3b")])
1225 [(set (reg:SI T_REG)
1226 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1227 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1228 ;; If we applied this split when not optimizing, it would only be
1229 ;; applied during the machine-dependent reorg, when no new basic blocks
1231 "TARGET_SH1 && reload_completed && optimize"
1232 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1233 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1234 (label_ref (match_dup 6))
1236 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1239 operands[2] = gen_highpart (SImode, operands[0]);
1240 operands[3] = operands[1] == const0_rtx
1242 : gen_highpart (SImode, operands[1]);
1243 operands[4] = gen_lowpart (SImode, operands[0]);
1244 operands[5] = gen_lowpart (SImode, operands[1]);
1245 operands[6] = gen_label_rtx ();
1248 (define_insn "cmpgtdi_t"
1249 [(set (reg:SI T_REG)
1250 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1251 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1254 static const char* alt[] =
1256 "cmp/eq %S1,%S0" "\n"
1258 " cmp/gt %S1,%S0" "\n"
1259 " cmp/hi %R1,%R0" "\n"
1265 " cmp/hi %S0,%R0" "\n"
1268 return alt[which_alternative];
1270 [(set_attr "length" "8")
1271 (set_attr "type" "arith3")])
1273 (define_insn "cmpgedi_t"
1274 [(set (reg:SI T_REG)
1275 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1276 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1279 static const char* alt[] =
1281 "cmp/eq %S1,%S0" "\n"
1283 " cmp/ge %S1,%S0" "\n"
1284 " cmp/hs %R1,%R0" "\n"
1289 return alt[which_alternative];
1291 [(set_attr "length" "8,2")
1292 (set_attr "type" "arith3,mt_group")])
1294 ;; -------------------------------------------------------------------------
1295 ;; DImode unsigned integer comparisons
1296 ;; -------------------------------------------------------------------------
1298 (define_insn "cmpgeudi_t"
1299 [(set (reg:SI T_REG)
1300 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1301 (match_operand:DI 1 "arith_reg_operand" "r")))]
1304 return "cmp/eq %S1,%S0" "\n"
1306 " cmp/hs %S1,%S0" "\n"
1307 " cmp/hs %R1,%R0" "\n"
1310 [(set_attr "length" "8")
1311 (set_attr "type" "arith3")])
1313 (define_insn "cmpgtudi_t"
1314 [(set (reg:SI T_REG)
1315 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1316 (match_operand:DI 1 "arith_reg_operand" "r")))]
1319 return "cmp/eq %S1,%S0" "\n"
1321 " cmp/hi %S1,%S0" "\n"
1322 " cmp/hi %R1,%R0" "\n"
1325 [(set_attr "length" "8")
1326 (set_attr "type" "arith3")])
1328 (define_insn "cmpeqsi_media"
1329 [(set (match_operand:SI 0 "register_operand" "=r")
1330 (eq:SI (match_operand:SI 1 "logical_operand" "%r")
1331 (match_operand:SI 2 "cmp_operand" "Nr")))]
1334 [(set_attr "type" "cmp_media")])
1336 (define_insn "cmpeqdi_media"
1337 [(set (match_operand:SI 0 "register_operand" "=r")
1338 (eq:SI (match_operand:DI 1 "register_operand" "%r")
1339 (match_operand:DI 2 "cmp_operand" "Nr")))]
1342 [(set_attr "type" "cmp_media")])
1344 (define_insn "cmpgtsi_media"
1345 [(set (match_operand:SI 0 "register_operand" "=r")
1346 (gt:SI (match_operand:SI 1 "cmp_operand" "Nr")
1347 (match_operand:SI 2 "cmp_operand" "rN")))]
1349 "cmpgt %N1, %N2, %0"
1350 [(set_attr "type" "cmp_media")])
1352 (define_insn "cmpgtdi_media"
1353 [(set (match_operand:SI 0 "register_operand" "=r")
1354 (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1355 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1357 "cmpgt %N1, %N2, %0"
1358 [(set_attr "type" "cmp_media")])
1360 (define_insn "cmpgtusi_media"
1361 [(set (match_operand:SI 0 "register_operand" "=r")
1362 (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr")
1363 (match_operand:SI 2 "cmp_operand" "rN")))]
1365 "cmpgtu %N1, %N2, %0"
1366 [(set_attr "type" "cmp_media")])
1368 (define_insn "cmpgtudi_media"
1369 [(set (match_operand:SI 0 "register_operand" "=r")
1370 (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr")
1371 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))]
1373 "cmpgtu %N1, %N2, %0"
1374 [(set_attr "type" "cmp_media")])
1376 ; This pattern is for combine.
1377 (define_insn "*cmpne0sisi_media"
1378 [(set (match_operand:SI 0 "register_operand" "=r")
1379 (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))]
1382 [(set_attr "type" "cmp_media")])
1384 ;; -------------------------------------------------------------------------
1385 ;; Conditional move instructions
1386 ;; -------------------------------------------------------------------------
1388 ;; The insn names may seem reversed, but note that cmveq performs the move
1389 ;; if op1 == 0, and cmvne does it if op1 != 0.
1391 (define_insn "movdicc_false"
1392 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1393 (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r")
1395 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1396 (match_operand:DI 3 "arith_reg_operand" "0")))]
1399 [(set_attr "type" "arith_media")])
1401 (define_insn "movdicc_true"
1402 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1403 (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r")
1405 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")
1406 (match_operand:DI 3 "arith_reg_operand" "0")))]
1409 [(set_attr "type" "arith_media")])
1412 [(set (match_operand:DI 0 "arith_reg_dest" "")
1413 (if_then_else:DI (match_operator 3 "equality_comparison_operator"
1414 [(match_operand:DI 1 "arith_reg_operand" "")
1416 (match_operand:DI 2 "arith_reg_dest" "")
1418 (set (match_dup 2) (match_dup 0))]
1419 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1421 (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))]
1423 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1424 VOIDmode, operands[1], CONST0_RTX (DImode));
1428 [(set (match_operand:DI 0 "general_movdst_operand" "")
1429 (match_operand:DI 1 "arith_reg_or_0_operand" ""))
1430 (set (match_operand:DI 2 "arith_reg_dest" "")
1431 (if_then_else:DI (match_operator 4 "equality_comparison_operator"
1432 [(match_operand:DI 3 "arith_reg_operand" "")
1436 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1438 (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))]
1441 (define_expand "movdicc"
1442 [(set (match_operand:DI 0 "register_operand" "")
1443 (if_then_else:DI (match_operand 1 "comparison_operator" "")
1444 (match_operand:DI 2 "register_operand" "")
1445 (match_operand:DI 3 "register_operand" "")))]
1448 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1449 && GET_MODE (XEXP (operands[1], 0)) == DImode
1450 && XEXP (operands[1], 1) == const0_rtx)
1454 if (!can_create_pseudo_p ())
1457 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1458 GET_CODE (operands[1]),
1459 XEXP (operands[1], 0),
1460 XEXP (operands[1], 1));
1466 ;; Add SImode variants for cmveq / cmvne to compensate for not promoting
1467 ;; SImode to DImode.
1468 (define_insn "movsicc_false"
1469 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1470 (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r")
1472 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1473 (match_operand:SI 3 "arith_reg_operand" "0")))]
1476 [(set_attr "type" "arith_media")])
1478 (define_insn "movsicc_true"
1479 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1480 (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r")
1482 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1483 (match_operand:SI 3 "arith_reg_operand" "0")))]
1486 [(set_attr "type" "arith_media")])
1489 [(set (match_operand:SI 0 "arith_reg_dest" "")
1490 (if_then_else:SI (match_operator 3 "equality_comparison_operator"
1491 [(match_operand:SI 1 "arith_reg_operand" "")
1493 (match_operand:SI 2 "arith_reg_dest" "")
1495 (set (match_dup 2) (match_dup 0))]
1496 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])"
1498 (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))]
1500 operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])),
1501 VOIDmode, operands[1], CONST0_RTX (SImode));
1505 [(set (match_operand:SI 0 "general_movdst_operand" "")
1506 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1507 (set (match_operand:SI 2 "arith_reg_dest" "")
1508 (if_then_else:SI (match_operator 4 "equality_comparison_operator"
1509 [(match_operand:SI 3 "arith_reg_operand" "")
1513 "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
1514 && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
1516 (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
1518 replace_rtx (operands[4], operands[0], operands[1]);
1522 [(set (match_operand 0 "any_register_operand" "")
1523 (match_operand 1 "any_register_operand" ""))
1524 (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" ""))
1525 (set (match_operand 4 "" "") (match_operand 5 "" ""))]
1526 "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2]))
1527 <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0])))
1528 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])
1529 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0])
1530 && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2])
1531 && ! reg_overlap_mentioned_p (operands[0], operands[3])
1532 && ! reg_overlap_mentioned_p (operands[2], operands[0])
1533 && ! reg_overlap_mentioned_p (operands[0], operands[1])
1534 && (REGNO_REG_CLASS (REGNO (operands[0]))
1535 == REGNO_REG_CLASS (REGNO (operands[2])))
1536 && (REGNO_REG_CLASS (REGNO (operands[1]))
1537 == REGNO_REG_CLASS (REGNO (operands[0])))"
1538 [(set (match_dup 0) (match_dup 3))
1539 (set (match_dup 4) (match_dup 5))]
1542 rtx_insn *insn1, *insn2;
1543 rtx replacements[4];
1545 /* We want to replace occurrences of operands[0] with operands[1] and
1546 operands[2] with operands[0] in operands[4]/operands[5].
1547 Doing just two replace_rtx calls naively would result in the second
1548 replacement undoing all that the first did if operands[1] and operands[2]
1549 are identical, so we must do this simultaneously. */
1550 replacements[0] = operands[0];
1551 replacements[1] = operands[1];
1552 replacements[2] = operands[2];
1553 replacements[3] = operands[0];
1554 if (!replace_n_hard_rtx (operands[5], replacements, 2, 0)
1555 || !replace_n_hard_rtx (operands[4], replacements, 2, 0)
1556 || !replace_n_hard_rtx (operands[2], replacements, 2, 0))
1559 operands[5] = replace_n_hard_rtx (operands[5], replacements, 2, 1);
1560 replace_n_hard_rtx (operands[4], replacements, 2, 1);
1561 operands[2] = replace_n_hard_rtx (operands[2], replacements, 2, 1);
1562 /* The operands array is aliased to recog_data.operand, which gets
1563 clobbered by extract_insn, so finish with it now. */
1564 set1 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
1565 set2 = gen_rtx_SET (VOIDmode, operands[4], operands[5]);
1566 /* ??? The last insn might be a jump insn, but the generic peephole2 code
1567 always uses emit_insn. */
1568 /* Check that we don't violate matching constraints or earlyclobbers. */
1569 basic_block bb = BLOCK_FOR_INSN (peep2_next_insn (2));
1570 insn1 = emit_insn (set1);
1571 extract_insn (insn1);
1572 if (! constrain_operands (1, get_preferred_alternatives (insn1, bb)))
1574 insn2 = emit (set2);
1575 if (GET_CODE (insn2) == BARRIER)
1577 extract_insn (insn2);
1578 if (! constrain_operands (1, get_preferred_alternatives (insn2, bb)))
1581 std::swap (replacements[0], replacements[1]);
1582 std::swap (replacements[2], replacements[3]);
1583 replace_n_hard_rtx (SET_DEST (set1), replacements, 2, 1);
1584 replace_n_hard_rtx (SET_DEST (set2), replacements, 2, 1);
1585 replace_n_hard_rtx (SET_SRC (set2), replacements, 2, 1);
1591 ;; The register allocator is rather clumsy in handling multi-way conditional
1592 ;; moves, so allow the combiner to make them, and we split them up after
1594 (define_insn_and_split "*movsicc_umin"
1595 [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
1596 (umin:SI (if_then_else:SI
1597 (eq (match_operand:SI 1 "arith_reg_operand" "r")
1599 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")
1600 (match_operand:SI 3 "register_operand" "0"))
1601 (match_operand:SI 4 "arith_reg_or_0_operand" "r")))
1602 (clobber (match_scratch:SI 5 "=&r"))]
1603 "TARGET_SHMEDIA && !can_create_pseudo_p ()"
1605 "TARGET_SHMEDIA && reload_completed"
1608 emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2],
1610 emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0]));
1611 emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4],
1616 (define_insn "*movsicc_t_false"
1617 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1618 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1619 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1620 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1621 "TARGET_PRETEND_CMOVE
1622 && (arith_reg_operand (operands[1], SImode)
1623 || (immediate_operand (operands[1], SImode)
1624 && satisfies_constraint_I08 (operands[1])))"
1630 [(set_attr "type" "mt_group,arith") ;; poor approximation
1631 (set_attr "length" "4")])
1633 (define_insn "*movsicc_t_true"
1634 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1635 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1636 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1637 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1638 "TARGET_PRETEND_CMOVE
1639 && (arith_reg_operand (operands[1], SImode)
1640 || (immediate_operand (operands[1], SImode)
1641 && satisfies_constraint_I08 (operands[1])))"
1647 [(set_attr "type" "mt_group,arith") ;; poor approximation
1648 (set_attr "length" "4")])
1650 (define_expand "movsicc"
1651 [(set (match_operand:SI 0 "arith_reg_dest" "")
1652 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1653 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1654 (match_operand:SI 3 "arith_reg_operand" "")))]
1655 "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE"
1657 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
1658 && GET_MODE (XEXP (operands[1], 0)) == SImode
1660 || (REG_P (XEXP (operands[1], 0))
1661 && REGNO (XEXP (operands[1], 0)) == T_REG))
1662 && XEXP (operands[1], 1) == const0_rtx)
1665 else if (TARGET_PRETEND_CMOVE)
1667 enum rtx_code code = GET_CODE (operands[1]);
1668 enum rtx_code new_code = code;
1669 rtx op0 = XEXP (operands[1], 0);
1670 rtx op1 = XEXP (operands[1], 1);
1672 if (! currently_expanding_to_rtl)
1676 case LT: case LE: case LEU: case LTU:
1677 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1680 new_code = reverse_condition (code);
1682 case EQ: case GT: case GE: case GEU: case GTU:
1687 sh_emit_scc_to_t (new_code, op0, op1);
1688 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1689 gen_rtx_REG (SImode, T_REG), const0_rtx);
1693 if (!can_create_pseudo_p ())
1696 operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]),
1697 GET_CODE (operands[1]),
1698 XEXP (operands[1], 0),
1699 XEXP (operands[1], 1));
1705 (define_expand "movqicc"
1706 [(set (match_operand:QI 0 "register_operand" "")
1707 (if_then_else:QI (match_operand 1 "comparison_operator" "")
1708 (match_operand:QI 2 "register_operand" "")
1709 (match_operand:QI 3 "register_operand" "")))]
1712 operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0);
1713 operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
1714 operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0);
1715 emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3]));
1719 ;; -------------------------------------------------------------------------
1720 ;; Addition instructions
1721 ;; -------------------------------------------------------------------------
1723 (define_expand "adddi3"
1724 [(set (match_operand:DI 0 "arith_reg_operand")
1725 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1726 (match_operand:DI 2 "arith_operand")))]
1731 operands[2] = force_reg (DImode, operands[2]);
1732 emit_insn (gen_adddi3_compact (operands[0], operands[1], operands[2]));
1737 (define_insn "*adddi3_media"
1738 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
1739 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1740 (match_operand:DI 2 "arith_operand" "r,I10")))]
1745 [(set_attr "type" "arith_media")])
1747 (define_insn "*adddisi3_media"
1748 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0)
1749 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
1750 (match_operand:DI 2 "arith_operand" "r,I10")))]
1755 [(set_attr "type" "arith_media")
1756 (set_attr "highpart" "ignore")])
1758 (define_insn "adddi3z_media"
1759 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
1761 (plus:SI (match_operand:SI 1 "extend_reg_operand" "r")
1762 (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))]
1764 "addz.l %1, %N2, %0"
1765 [(set_attr "type" "arith_media")
1766 (set_attr "highpart" "ignore")])
1768 (define_insn_and_split "adddi3_compact"
1769 [(set (match_operand:DI 0 "arith_reg_dest")
1770 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1771 (match_operand:DI 2 "arith_reg_operand")))
1772 (clobber (reg:SI T_REG))]
1775 "&& can_create_pseudo_p ()"
1778 emit_insn (gen_clrt ());
1779 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1780 gen_lowpart (SImode, operands[1]),
1781 gen_lowpart (SImode, operands[2])));
1782 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1783 gen_highpart (SImode, operands[1]),
1784 gen_highpart (SImode, operands[2])));
1789 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1790 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1791 (match_operand:SI 2 "arith_reg_operand" "r"))
1794 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1797 [(set_attr "type" "arith")])
1799 ;; A simplified version of the addc insn, where the exact value of the
1800 ;; T bit doesn't matter. This is easier for combine to pick up.
1801 ;; We allow a reg or 0 for one of the operands in order to be able to
1802 ;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
1804 ;; FIXME: The load of constant 0 should be split out before reload, or else
1805 ;; it will be difficult to hoist or combine the constant load.
1806 (define_insn "*addc"
1807 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1808 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1809 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
1810 (match_operand:SI 3 "t_reg_operand" "")))
1811 (clobber (reg:SI T_REG))]
1814 [(set_attr "type" "arith")])
1816 ;; Split 'reg + reg + 1' into a sett addc sequence, as it can be scheduled
1817 ;; better, if the sett insn can be done early.
1818 (define_insn_and_split "*addc_r_r_1"
1819 [(set (match_operand:SI 0 "arith_reg_dest" "")
1820 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
1821 (match_operand:SI 2 "arith_reg_operand" ""))
1823 (clobber (reg:SI T_REG))]
1827 [(set (reg:SI T_REG) (const_int 1))
1828 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1830 (clobber (reg:SI T_REG))])])
1832 ;; Left shifts by one are usually done with an add insn to avoid T_REG
1833 ;; clobbers. Thus addc can also be used to do something like '(x << 1) + 1'.
1834 (define_insn_and_split "*addc_2r_1"
1835 [(set (match_operand:SI 0 "arith_reg_dest")
1836 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
1839 (clobber (reg:SI T_REG))]
1843 [(set (reg:SI T_REG) (const_int 1))
1844 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1846 (clobber (reg:SI T_REG))])])
1848 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1849 ;; matched. Split this up into a simple sub add sequence, as this will save
1850 ;; us one sett insn.
1851 (define_insn_and_split "*minus_plus_one"
1852 [(set (match_operand:SI 0 "arith_reg_dest" "")
1853 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1854 (match_operand:SI 2 "arith_reg_operand" ""))
1859 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1860 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1862 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1863 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1864 ;; operation, as opposed to sequences such as
1868 ;; Even if the constant is not CSE-ed, a sequence such as
1871 ;; can be scheduled much better since the load of the constant can be
1872 ;; done earlier, before any comparison insns that store the result in
1874 (define_insn_and_split "*addc_t_r"
1875 [(set (match_operand:SI 0 "arith_reg_dest")
1876 (plus:SI (match_operand:SI 1 "t_reg_operand")
1877 (match_operand:SI 2 "arith_reg_operand")))
1878 (clobber (reg:SI T_REG))]
1882 [(parallel [(set (match_dup 0)
1883 (plus:SI (plus:SI (match_dup 2) (const_int 0))
1885 (clobber (reg:SI T_REG))])])
1887 (define_insn_and_split "*addc_r_t"
1888 [(set (match_operand:SI 0 "arith_reg_dest")
1889 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1890 (match_operand:SI 2 "t_reg_operand")))
1891 (clobber (reg:SI T_REG))]
1895 [(parallel [(set (match_dup 0)
1896 (plus:SI (plus:SI (match_dup 1) (const_int 0))
1898 (clobber (reg:SI T_REG))])])
1900 ;; Use shlr-addc to do 'reg + (reg & 1)'.
1901 (define_insn_and_split "*addc_r_lsb"
1902 [(set (match_operand:SI 0 "arith_reg_dest")
1903 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1905 (match_operand:SI 2 "arith_reg_operand")))
1906 (clobber (reg:SI T_REG))]
1909 "&& can_create_pseudo_p ()"
1910 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
1911 (clobber (reg:SI T_REG))])]
1913 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1916 ;; Use shlr-addc to do 'reg + reg + (reg & 1)'.
1917 (define_insn_and_split "*addc_r_r_lsb"
1918 [(set (match_operand:SI 0 "arith_reg_dest")
1919 (plus:SI (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1921 (match_operand:SI 2 "arith_reg_operand"))
1922 (match_operand:SI 3 "arith_reg_operand")))
1923 (clobber (reg:SI T_REG))]
1926 "&& can_create_pseudo_p ()"
1927 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1929 (clobber (reg:SI T_REG))])]
1931 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[1]));
1934 ;; Canonicalize 'reg + (reg & 1) + reg' into 'reg + reg + (reg & 1)'.
1935 (define_insn_and_split "*addc_r_lsb_r"
1936 [(set (match_operand:SI 0 "arith_reg_dest")
1937 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1939 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1940 (match_operand:SI 3 "arith_reg_operand"))))
1941 (clobber (reg:SI T_REG))]
1944 "&& can_create_pseudo_p ()"
1945 [(parallel [(set (match_dup 0)
1946 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1949 (clobber (reg:SI T_REG))])])
1951 ;; Canonicalize '2 * reg + (reg & 1)' into 'reg + reg + (reg & 1)'.
1952 (define_insn_and_split "*addc_2r_lsb"
1953 [(set (match_operand:SI 0 "arith_reg_dest")
1954 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
1956 (mult:SI (match_operand:SI 2 "arith_reg_operand")
1958 (clobber (reg:SI T_REG))]
1961 "&& can_create_pseudo_p ()"
1962 [(parallel [(set (match_dup 0)
1963 (plus:SI (plus:SI (and:SI (match_dup 1) (const_int 1))
1966 (clobber (reg:SI T_REG))])])
1968 ;; Use shll-addc to do 'reg + ((unsigned int)reg >> 31)'.
1969 (define_insn_and_split "*addc_r_msb"
1970 [(set (match_operand:SI 0 "arith_reg_dest")
1971 (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1973 (match_operand:SI 2 "arith_reg_operand")))
1974 (clobber (reg:SI T_REG))]
1977 "&& can_create_pseudo_p ()"
1978 [(parallel [(set (match_dup 0) (plus:SI (reg:SI T_REG) (match_dup 2)))
1979 (clobber (reg:SI T_REG))])]
1981 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
1984 ;; Use shll-addc to do 'reg + reg + ((unsigned int)reg >> 31)'.
1985 (define_insn_and_split "*addc_r_r_msb"
1986 [(set (match_operand:SI 0 "arith_reg_dest")
1987 (plus:SI (plus:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1989 (match_operand:SI 2 "arith_reg_operand"))
1990 (match_operand:SI 3 "arith_reg_operand")))
1991 (clobber (reg:SI T_REG))]
1994 "&& can_create_pseudo_p ()"
1995 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1997 (clobber (reg:SI T_REG))])]
1999 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[1]));
2002 ;; Canonicalize '2 * reg + ((unsigned int)reg >> 31)'
2003 ;; into 'reg + reg + (reg & 1)'.
2004 (define_insn_and_split "*addc_2r_msb"
2005 [(set (match_operand:SI 0 "arith_reg_dest")
2006 (plus:SI (mult:SI (match_operand:SI 1 "arith_reg_operand")
2008 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
2010 (clobber (reg:SI T_REG))]
2013 "&& can_create_pseudo_p ()"
2014 [(parallel [(set (match_dup 0)
2015 (plus:SI (plus:SI (lshiftrt:SI (match_dup 2) (const_int 31))
2018 (clobber (reg:SI T_REG))])])
2020 (define_expand "addsi3"
2021 [(set (match_operand:SI 0 "arith_reg_operand" "")
2022 (plus:SI (match_operand:SI 1 "arith_operand" "")
2023 (match_operand:SI 2 "arith_operand" "")))]
2027 operands[1] = force_reg (SImode, operands[1]);
2030 (define_insn "addsi3_media"
2031 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
2032 (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r")
2033 (match_operand:SI 2 "arith_operand" "r,I10")))]
2038 [(set_attr "type" "arith_media")
2039 (set_attr "highpart" "ignore")])
2041 (define_insn "addsidi3_media"
2042 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
2043 (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand"
2045 (match_operand:SI 2 "arith_operand"
2051 [(set_attr "type" "arith_media")
2052 (set_attr "highpart" "ignore")])
2054 (define_insn "*addsi3_compact"
2055 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2056 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
2057 (match_operand:SI 2 "arith_operand" "rI08")))]
2060 [(set_attr "type" "arith")])
2062 ;; -------------------------------------------------------------------------
2063 ;; Subtraction instructions
2064 ;; -------------------------------------------------------------------------
2066 (define_expand "subdi3"
2067 [(set (match_operand:DI 0 "arith_reg_operand" "")
2068 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "")
2069 (match_operand:DI 2 "arith_reg_operand" "")))]
2074 operands[1] = force_reg (DImode, operands[1]);
2075 emit_insn (gen_subdi3_compact (operands[0], operands[1], operands[2]));
2080 (define_insn "*subdi3_media"
2081 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
2082 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2083 (match_operand:DI 2 "arith_reg_operand" "r")))]
2086 [(set_attr "type" "arith_media")])
2088 (define_insn "subdisi3_media"
2089 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
2090 (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN")
2091 (match_operand:DI 2 "arith_reg_operand" "r")))]
2094 [(set_attr "type" "arith_media")
2095 (set_attr "highpart" "ignore")])
2097 (define_insn_and_split "subdi3_compact"
2098 [(set (match_operand:DI 0 "arith_reg_dest")
2099 (minus:DI (match_operand:DI 1 "arith_reg_operand")
2100 (match_operand:DI 2 "arith_reg_operand")))
2101 (clobber (reg:SI T_REG))]
2104 "&& can_create_pseudo_p ()"
2107 emit_insn (gen_clrt ());
2108 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
2109 gen_lowpart (SImode, operands[1]),
2110 gen_lowpart (SImode, operands[2])));
2111 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
2112 gen_highpart (SImode, operands[1]),
2113 gen_highpart (SImode, operands[2])));
2118 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2119 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2120 (match_operand:SI 2 "arith_reg_operand" "r"))
2123 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
2128 [(set_attr "type" "arith")])
2130 ;; A simplified version of the subc insn, where the exact value of the
2131 ;; T bit doesn't matter. This is easier for combine to pick up.
2132 ;; We allow a reg or 0 for one of the operands in order to be able to
2133 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
2135 (define_insn "*subc"
2136 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2137 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2138 (match_operand:SI 2 "arith_reg_or_0_operand" "r"))
2139 (match_operand:SI 3 "t_reg_operand" "")))
2140 (clobber (reg:SI T_REG))]
2143 [(set_attr "type" "arith")])
2145 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2146 ;; better, if the sett insn can be done early.
2147 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2148 (define_insn_and_split "*subc"
2149 [(set (match_operand:SI 0 "arith_reg_dest" "")
2150 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2151 (match_operand:SI 2 "arith_reg_operand" "")))
2152 (clobber (reg:SI T_REG))]
2156 [(set (reg:SI T_REG) (const_int 1))
2157 (parallel [(set (match_dup 0)
2158 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2160 (clobber (reg:SI T_REG))])])
2162 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2163 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2164 ;; operation, as opposed to sequences such as
2168 ;; Even if the constant is not CSE-ed, a sequence such as
2171 ;; can be scheduled much better since the load of the constant can be
2172 ;; done earlier, before any comparison insns that store the result in
2174 (define_insn_and_split "*subc"
2175 [(set (match_operand:SI 0 "arith_reg_dest" "")
2176 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2177 (match_operand:SI 2 "t_reg_operand" "")))
2178 (clobber (reg:SI T_REG))]
2182 [(parallel [(set (match_dup 0)
2183 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2185 (clobber (reg:SI T_REG))])])
2187 (define_insn "*subsi3_internal"
2188 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2189 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2190 (match_operand:SI 2 "arith_reg_operand" "r")))]
2193 [(set_attr "type" "arith")])
2195 (define_insn_and_split "*subsi3_media"
2196 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2197 (minus:SI (match_operand:SI 1 "minuend_operand" "rN")
2198 (match_operand:SI 2 "extend_reg_operand" "r")))]
2200 && (operands[1] != constm1_rtx
2201 || (GET_CODE (operands[2]) != TRUNCATE
2202 && GET_CODE (operands[2]) != SUBREG))"
2204 "operands[1] == constm1_rtx"
2205 [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))]
2207 [(set_attr "type" "arith_media")
2208 (set_attr "highpart" "ignore")])
2211 [(set (match_operand:SI 0 "arith_reg_dest" "")
2212 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2213 "general_extend_operand"
2215 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
2216 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2217 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2221 [(set (match_operand:SI 0 "arith_reg_dest" "")
2222 (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1
2223 "general_extend_operand"
2225 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
2226 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
2227 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))]
2235 ;; since this will sometimes save one instruction.
2236 ;; Otherwise we might get a sequence like
2240 ;; if the source and dest regs are the same.
2241 (define_expand "subsi3"
2242 [(set (match_operand:SI 0 "arith_reg_operand" "")
2243 (minus:SI (match_operand:SI 1 "arith_operand" "")
2244 (match_operand:SI 2 "arith_reg_operand" "")))]
2247 if (TARGET_SH1 && CONST_INT_P (operands[1]))
2249 emit_insn (gen_negsi2 (operands[0], operands[2]));
2250 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2255 if (!can_create_pseudo_p ()
2256 && ! arith_reg_or_0_operand (operands[1], SImode))
2258 if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG)
2259 operands[1] = force_reg (SImode, operands[1]);
2263 ;; -------------------------------------------------------------------------
2264 ;; Division instructions
2265 ;; -------------------------------------------------------------------------
2267 ;; We take advantage of the library routines which don't clobber as many
2268 ;; registers as a normal function call would.
2270 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2271 ;; also has an effect on the register that holds the address of the sfunc.
2272 ;; To make this work, we have an extra dummy insn that shows the use
2273 ;; of this register for reorg.
2275 (define_insn "use_sfunc_addr"
2276 [(set (reg:SI PR_REG)
2277 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2278 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2280 [(set_attr "length" "0")])
2282 (define_insn "udivsi3_sh2a"
2283 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2284 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2285 (match_operand:SI 2 "arith_reg_operand" "z")))]
2288 [(set_attr "type" "arith")
2289 (set_attr "in_delay_slot" "no")])
2291 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2292 ;; hard register 0. If we used hard register 0, then the next instruction
2293 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2294 ;; gets allocated to a stack slot that needs its address reloaded, then
2295 ;; there is nothing to prevent reload from using r0 to reload the address.
2296 ;; This reload would clobber the value in r0 we are trying to store.
2297 ;; If we let reload allocate r0, then this problem can never happen.
2298 (define_insn "udivsi3_i1"
2299 [(set (match_operand:SI 0 "register_operand" "=z")
2300 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2301 (clobber (reg:SI T_REG))
2302 (clobber (reg:SI PR_REG))
2303 (clobber (reg:SI R1_REG))
2304 (clobber (reg:SI R4_REG))
2305 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2306 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2308 [(set_attr "type" "sfunc")
2309 (set_attr "needs_delay_slot" "yes")])
2311 ; Since shmedia-nofpu code could be linked against shcompact code, and
2312 ; the udivsi3 libcall has the same name, we must consider all registers
2313 ; clobbered that are in the union of the registers clobbered by the
2314 ; shmedia and the shcompact implementation. Note, if the shcompact
2315 ; implementation actually used shcompact code, we'd need to clobber
2316 ; also r23 and fr23.
2317 (define_insn "udivsi3_i1_media"
2318 [(set (match_operand:SI 0 "register_operand" "=z")
2319 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2320 (clobber (reg:SI T_MEDIA_REG))
2321 (clobber (reg:SI PR_MEDIA_REG))
2322 (clobber (reg:SI R20_REG))
2323 (clobber (reg:SI R21_REG))
2324 (clobber (reg:SI R22_REG))
2325 (clobber (reg:DI TR0_REG))
2326 (clobber (reg:DI TR1_REG))
2327 (clobber (reg:DI TR2_REG))
2328 (use (match_operand 1 "target_reg_operand" "b"))]
2329 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2331 [(set_attr "type" "sfunc")
2332 (set_attr "needs_delay_slot" "yes")])
2334 (define_expand "udivsi3_i4_media"
2336 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
2338 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
2339 (set (match_dup 5) (float:DF (match_dup 3)))
2340 (set (match_dup 6) (float:DF (match_dup 4)))
2341 (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6)))
2342 (set (match_dup 8) (fix:DI (match_dup 7)))
2343 (set (match_operand:SI 0 "register_operand" "")
2344 (truncate:SI (match_dup 8)))]
2345 "TARGET_SHMEDIA_FPU"
2347 operands[3] = gen_reg_rtx (DImode);
2348 operands[4] = gen_reg_rtx (DImode);
2349 operands[5] = gen_reg_rtx (DFmode);
2350 operands[6] = gen_reg_rtx (DFmode);
2351 operands[7] = gen_reg_rtx (DFmode);
2352 operands[8] = gen_reg_rtx (DImode);
2355 (define_insn "udivsi3_i4"
2356 [(set (match_operand:SI 0 "register_operand" "=y")
2357 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2358 (clobber (reg:SI T_REG))
2359 (clobber (reg:SI PR_REG))
2360 (clobber (reg:DF DR0_REG))
2361 (clobber (reg:DF DR2_REG))
2362 (clobber (reg:DF DR4_REG))
2363 (clobber (reg:SI R0_REG))
2364 (clobber (reg:SI R1_REG))
2365 (clobber (reg:SI R4_REG))
2366 (clobber (reg:SI R5_REG))
2367 (clobber (reg:SI FPSCR_STAT_REG))
2368 (use (reg:SI FPSCR_MODES_REG))
2369 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2370 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2372 [(set_attr "type" "sfunc")
2373 (set_attr "fp_mode" "double")
2374 (set_attr "needs_delay_slot" "yes")])
2376 (define_insn "udivsi3_i4_single"
2377 [(set (match_operand:SI 0 "register_operand" "=y")
2378 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2379 (clobber (reg:SI T_REG))
2380 (clobber (reg:SI PR_REG))
2381 (clobber (reg:DF DR0_REG))
2382 (clobber (reg:DF DR2_REG))
2383 (clobber (reg:DF DR4_REG))
2384 (clobber (reg:SI R0_REG))
2385 (clobber (reg:SI R1_REG))
2386 (clobber (reg:SI R4_REG))
2387 (clobber (reg:SI R5_REG))
2388 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2389 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2390 && TARGET_FPU_SINGLE"
2392 [(set_attr "type" "sfunc")
2393 (set_attr "needs_delay_slot" "yes")])
2395 (define_insn "udivsi3_i4_int"
2396 [(set (match_operand:SI 0 "register_operand" "=z")
2397 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2398 (clobber (reg:SI T_REG))
2399 (clobber (reg:SI R1_REG))
2400 (clobber (reg:SI PR_REG))
2401 (clobber (reg:SI MACH_REG))
2402 (clobber (reg:SI MACL_REG))
2403 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2406 [(set_attr "type" "sfunc")
2407 (set_attr "needs_delay_slot" "yes")])
2410 (define_expand "udivsi3"
2411 [(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
2412 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2413 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2414 (parallel [(set (match_operand:SI 0 "register_operand" "")
2415 (udiv:SI (reg:SI R4_REG)
2417 (clobber (reg:SI T_REG))
2418 (clobber (reg:SI PR_REG))
2419 (clobber (reg:SI R4_REG))
2420 (use (match_dup 3))])]
2425 operands[3] = gen_reg_rtx (Pmode);
2426 /* Emit the move of the address to a pseudo outside of the libcall. */
2427 if (TARGET_DIVIDE_CALL_TABLE)
2429 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2430 that causes problems when the divide code is supposed to come from a
2431 separate library. Division by zero is undefined, so dividing 1 can be
2432 implemented by comparing with the divisor. */
2433 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2435 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2436 emit_insn (gen_cstoresi4 (operands[0], test,
2437 operands[1], operands[2]));
2440 else if (operands[2] == const0_rtx)
2442 emit_move_insn (operands[0], operands[2]);
2445 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2446 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2448 else if (TARGET_DIVIDE_CALL_FP)
2450 function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
2451 if (TARGET_FPU_SINGLE)
2452 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2454 last = gen_udivsi3_i4 (operands[0], operands[3]);
2456 else if (TARGET_SHMEDIA_FPU)
2458 operands[1] = force_reg (SImode, operands[1]);
2459 operands[2] = force_reg (SImode, operands[2]);
2460 emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
2463 else if (TARGET_SH2A)
2465 operands[1] = force_reg (SImode, operands[1]);
2466 operands[2] = force_reg (SImode, operands[2]);
2467 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2470 else if (TARGET_SH5)
2472 function_symbol (operands[3],
2473 TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3",
2477 last = gen_udivsi3_i1_media (operands[0], operands[3]);
2478 else if (TARGET_FPU_ANY)
2479 last = gen_udivsi3_i4_single (operands[0], operands[3]);
2481 last = gen_udivsi3_i1 (operands[0], operands[3]);
2485 function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
2486 last = gen_udivsi3_i1 (operands[0], operands[3]);
2488 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2489 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2494 (define_insn "divsi3_sh2a"
2495 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2496 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2497 (match_operand:SI 2 "arith_reg_operand" "z")))]
2500 [(set_attr "type" "arith")
2501 (set_attr "in_delay_slot" "no")])
2503 (define_insn "divsi3_i1"
2504 [(set (match_operand:SI 0 "register_operand" "=z")
2505 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2506 (clobber (reg:SI T_REG))
2507 (clobber (reg:SI PR_REG))
2508 (clobber (reg:SI R1_REG))
2509 (clobber (reg:SI R2_REG))
2510 (clobber (reg:SI R3_REG))
2511 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2512 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2514 [(set_attr "type" "sfunc")
2515 (set_attr "needs_delay_slot" "yes")])
2517 (define_insn "divsi3_i1_media"
2518 [(set (match_operand:SI 0 "register_operand" "=z")
2519 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2520 (clobber (reg:SI T_MEDIA_REG))
2521 (clobber (reg:SI PR_MEDIA_REG))
2522 (clobber (reg:SI R1_REG))
2523 (clobber (reg:SI R20_REG))
2524 (clobber (reg:SI R21_REG))
2525 (clobber (reg:SI TR0_REG))
2526 (use (match_operand 1 "target_reg_operand" "b"))]
2527 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2529 [(set_attr "type" "sfunc")])
2531 (define_insn "divsi3_media_2"
2532 [(set (match_operand:SI 0 "register_operand" "=z")
2533 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2534 (clobber (reg:SI T_MEDIA_REG))
2535 (clobber (reg:SI PR_MEDIA_REG))
2536 (clobber (reg:SI R1_REG))
2537 (clobber (reg:SI R21_REG))
2538 (clobber (reg:SI TR0_REG))
2539 (use (reg:SI R20_REG))
2540 (use (match_operand 1 "target_reg_operand" "b"))]
2541 "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)"
2543 [(set_attr "type" "sfunc")])
2545 ;; This pattern acts as a placeholder for -mdiv=inv:call to carry
2546 ;; hard reg clobbers and data dependencies that we need when we want
2547 ;; to rematerialize the division into a call.
2548 (define_insn_and_split "divsi_inv_call"
2549 [(set (match_operand:SI 0 "register_operand" "=r")
2550 (div:SI (match_operand:SI 1 "register_operand" "r")
2551 (match_operand:SI 2 "register_operand" "r")))
2552 (clobber (reg:SI R4_REG))
2553 (clobber (reg:SI R5_REG))
2554 (clobber (reg:SI T_MEDIA_REG))
2555 (clobber (reg:SI PR_MEDIA_REG))
2556 (clobber (reg:SI R1_REG))
2557 (clobber (reg:SI R21_REG))
2558 (clobber (reg:SI TR0_REG))
2559 (clobber (reg:SI R20_REG))
2560 (use (match_operand:SI 3 "register_operand" "r"))]
2563 "&& (reload_in_progress || reload_completed)"
2564 [(set (match_dup 0) (match_dup 3))]
2566 [(set_attr "highpart" "must_split")])
2568 ;; This is the combiner pattern for -mdiv=inv:call .
2569 (define_insn_and_split "*divsi_inv_call_combine"
2570 [(set (match_operand:SI 0 "register_operand" "=z")
2571 (div:SI (match_operand:SI 1 "register_operand" "r")
2572 (match_operand:SI 2 "register_operand" "r")))
2573 (clobber (reg:SI R4_REG))
2574 (clobber (reg:SI R5_REG))
2575 (clobber (reg:SI T_MEDIA_REG))
2576 (clobber (reg:SI PR_MEDIA_REG))
2577 (clobber (reg:SI R1_REG))
2578 (clobber (reg:SI R21_REG))
2579 (clobber (reg:SI TR0_REG))
2580 (clobber (reg:SI R20_REG))
2581 (use (unspec:SI [(match_dup 1)
2582 (match_operand:SI 3 "" "")
2583 (unspec:SI [(match_operand:SI 4 "" "")
2585 (match_operand:DI 5 "" "")]
2587 (match_operand:DI 6 "" "")
2590 UNSPEC_DIV_INV_M3))]
2593 "&& (reload_in_progress || reload_completed)"
2596 const char *name = sh_divsi3_libfunc;
2597 enum sh_function_kind kind = SFUNC_GOT;
2600 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2601 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2602 while (TARGET_DIVIDE_INV_CALL2)
2604 rtx x = operands[3];
2606 if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1)
2608 x = XVECEXP (x, 0, 0);
2609 name = "__sdivsi3_2";
2610 kind = SFUNC_STATIC;
2611 emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
2614 sym = function_symbol (NULL, name, kind);
2615 emit_insn (gen_divsi3_media_2 (operands[0], sym));
2618 [(set_attr "highpart" "must_split")])
2620 (define_expand "divsi3_i4_media"
2621 [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
2622 (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
2623 (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
2624 (set (match_operand:SI 0 "register_operand" "=r")
2625 (fix:SI (match_dup 5)))]
2626 "TARGET_SHMEDIA_FPU"
2628 operands[3] = gen_reg_rtx (DFmode);
2629 operands[4] = gen_reg_rtx (DFmode);
2630 operands[5] = gen_reg_rtx (DFmode);
2633 (define_insn "divsi3_i4"
2634 [(set (match_operand:SI 0 "register_operand" "=y")
2635 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2636 (clobber (reg:SI PR_REG))
2637 (clobber (reg:DF DR0_REG))
2638 (clobber (reg:DF DR2_REG))
2639 (clobber (reg:SI FPSCR_STAT_REG))
2640 (use (reg:SI FPSCR_MODES_REG))
2641 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2642 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2644 [(set_attr "type" "sfunc")
2645 (set_attr "fp_mode" "double")
2646 (set_attr "needs_delay_slot" "yes")])
2648 (define_insn "divsi3_i4_single"
2649 [(set (match_operand:SI 0 "register_operand" "=y")
2650 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2651 (clobber (reg:SI PR_REG))
2652 (clobber (reg:DF DR0_REG))
2653 (clobber (reg:DF DR2_REG))
2654 (clobber (reg:SI R2_REG))
2655 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2656 "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
2657 && TARGET_FPU_SINGLE"
2659 [(set_attr "type" "sfunc")
2660 (set_attr "needs_delay_slot" "yes")])
2662 (define_insn "divsi3_i4_int"
2663 [(set (match_operand:SI 0 "register_operand" "=z")
2664 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2665 (clobber (reg:SI T_REG))
2666 (clobber (reg:SI PR_REG))
2667 (clobber (reg:SI R1_REG))
2668 (clobber (reg:SI MACH_REG))
2669 (clobber (reg:SI MACL_REG))
2670 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2673 [(set_attr "type" "sfunc")
2674 (set_attr "needs_delay_slot" "yes")])
2676 (define_expand "divsi3"
2677 [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
2678 (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
2679 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
2680 (parallel [(set (match_operand:SI 0 "register_operand" "")
2681 (div:SI (reg:SI R4_REG)
2683 (clobber (reg:SI T_REG))
2684 (clobber (reg:SI PR_REG))
2685 (clobber (reg:SI R1_REG))
2686 (clobber (reg:SI R2_REG))
2687 (clobber (reg:SI R3_REG))
2688 (use (match_dup 3))])]
2693 operands[3] = gen_reg_rtx (Pmode);
2694 /* Emit the move of the address to a pseudo outside of the libcall. */
2695 if (TARGET_DIVIDE_CALL_TABLE)
2697 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2698 last = gen_divsi3_i4_int (operands[0], operands[3]);
2700 else if (TARGET_DIVIDE_CALL_FP)
2702 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2703 if (TARGET_FPU_SINGLE)
2704 last = gen_divsi3_i4_single (operands[0], operands[3]);
2706 last = gen_divsi3_i4 (operands[0], operands[3]);
2708 else if (TARGET_SH2A)
2710 operands[1] = force_reg (SImode, operands[1]);
2711 operands[2] = force_reg (SImode, operands[2]);
2712 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2715 else if (TARGET_DIVIDE_INV)
2717 rtx dividend = operands[1];
2718 rtx divisor = operands[2];
2720 rtx nsb_res = gen_reg_rtx (DImode);
2721 rtx norm64 = gen_reg_rtx (DImode);
2722 rtx tab_ix = gen_reg_rtx (DImode);
2723 rtx norm32 = gen_reg_rtx (SImode);
2724 rtx i92 = force_reg (DImode, GEN_INT (92));
2725 rtx scratch0a = gen_reg_rtx (DImode);
2726 rtx scratch0b = gen_reg_rtx (DImode);
2727 rtx inv0 = gen_reg_rtx (SImode);
2728 rtx scratch1a = gen_reg_rtx (DImode);
2729 rtx scratch1b = gen_reg_rtx (DImode);
2730 rtx shift = gen_reg_rtx (DImode);
2732 rtx inv1 = gen_reg_rtx (SImode);
2733 rtx scratch2a = gen_reg_rtx (DImode);
2734 rtx scratch2b = gen_reg_rtx (SImode);
2735 rtx inv2 = gen_reg_rtx (SImode);
2736 rtx scratch3a = gen_reg_rtx (DImode);
2737 rtx scratch3b = gen_reg_rtx (DImode);
2738 rtx scratch3c = gen_reg_rtx (DImode);
2739 rtx scratch3d = gen_reg_rtx (SImode);
2740 rtx scratch3e = gen_reg_rtx (DImode);
2741 rtx result = gen_reg_rtx (SImode);
2743 if (! arith_reg_or_0_operand (dividend, SImode))
2744 dividend = force_reg (SImode, dividend);
2745 if (! arith_reg_operand (divisor, SImode))
2746 divisor = force_reg (SImode, divisor);
2747 if (flag_pic && Pmode != DImode)
2749 tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2750 tab_base = gen_datalabel_ref (tab_base);
2751 tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base));
2755 tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table");
2756 tab_base = gen_datalabel_ref (tab_base);
2757 tab_base = force_reg (DImode, tab_base);
2759 if (TARGET_DIVIDE_INV20U)
2760 i2p27 = force_reg (DImode, GEN_INT (-2 << 27));
2762 i2p27 = GEN_INT (0);
2763 if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)
2764 i43 = force_reg (DImode, GEN_INT (43));
2767 emit_insn (gen_nsbdi (nsb_res,
2768 simplify_gen_subreg (DImode, divisor, SImode, 0)));
2769 emit_insn (gen_ashldi3_media (norm64,
2770 gen_rtx_SUBREG (DImode, divisor, 0),
2772 emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58)));
2773 emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32)));
2774 emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32,
2775 inv0, scratch0a, scratch0b,
2776 scratch1a, scratch1b));
2777 emit_insn (gen_subdi3 (shift, i92, nsb_res));
2778 emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92,
2780 emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift,
2782 scratch3a, scratch3b, scratch3c,
2783 scratch2a, scratch2b, scratch3d, scratch3e));
2784 if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2)
2785 emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result));
2786 else if (TARGET_DIVIDE_INV_FP)
2787 emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result,
2788 gen_reg_rtx (SImode), gen_reg_rtx (SImode),
2789 gen_reg_rtx (DFmode), gen_reg_rtx (DFmode),
2790 gen_reg_rtx (DFmode)));
2792 emit_move_insn (operands[0], result);
2795 else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP)
2797 operands[1] = force_reg (SImode, operands[1]);
2798 operands[2] = force_reg (SImode, operands[2]);
2799 emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
2802 else if (TARGET_SH5)
2804 if (TARGET_DIVIDE_CALL2)
2806 rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table");
2807 tab_base = gen_datalabel_ref (tab_base);
2808 emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base);
2810 if (TARGET_FPU_ANY && TARGET_SH1)
2811 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
2812 else if (TARGET_DIVIDE_CALL2)
2813 function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC);
2815 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2818 last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
2819 (operands[0], operands[3]));
2820 else if (TARGET_FPU_ANY)
2821 last = gen_divsi3_i4_single (operands[0], operands[3]);
2823 last = gen_divsi3_i1 (operands[0], operands[3]);
2827 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2828 last = gen_divsi3_i1 (operands[0], operands[3]);
2830 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2831 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2836 ;; operands: scratch, tab_base, tab_ix
2837 ;; These are unspecs because we could generate an indexed addressing mode
2838 ;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would
2839 ;; confuse reload. See PR27117.
2840 (define_insn "divsi_inv_qitable"
2841 [(set (match_operand:DI 0 "register_operand" "=r")
2842 (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r")
2843 (match_operand:DI 2 "register_operand" "r")]
2844 UNSPEC_DIV_INV_TABLE)))]
2847 [(set_attr "type" "load_media")
2848 (set_attr "highpart" "user")])
2850 ;; operands: scratch, tab_base, tab_ix
2851 (define_insn "divsi_inv_hitable"
2852 [(set (match_operand:DI 0 "register_operand" "=r")
2853 (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r")
2854 (match_operand:DI 2 "register_operand" "r")]
2855 UNSPEC_DIV_INV_TABLE)))]
2858 [(set_attr "type" "load_media")
2859 (set_attr "highpart" "user")])
2861 ;; operands: inv0, tab_base, tab_ix, norm32
2862 ;; scratch equiv in sdivsi3_2: r19, r21
2863 (define_expand "divsi_inv_m0"
2864 [(set (match_operand:SI 0 "register_operand" "=r")
2865 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2866 (match_operand:DI 2 "register_operand" "r")
2867 (match_operand:SI 3 "register_operand" "r")]
2869 (clobber (match_operand:DI 4 "register_operand" "=r"))
2870 (clobber (match_operand:DI 5 "register_operand" "=r"))]
2877 ldx.ub r20, r21, r19 // u0.8
2879 muls.l r25, r19, r19 // s2.38
2880 ldx.w r20, r21, r21 // s2.14
2881 shari r19, 24, r19 // truncate to s2.14
2882 sub r21, r19, r19 // some 11 bit inverse in s1.14
2885 rtx inv0 = operands[0];
2886 rtx tab_base = operands[1];
2887 rtx tab_ix = operands[2];
2888 rtx norm32 = operands[3];
2889 rtx scratch0 = operands[4];
2890 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2891 rtx scratch1 = operands[5];
2893 emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix));
2894 emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1)));
2895 emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si));
2896 emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1));
2897 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24)));
2898 emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0));
2902 ;; operands: inv1, tab_base, tab_ix, norm32
2903 (define_insn_and_split "divsi_inv_m1"
2904 [(set (match_operand:SI 0 "register_operand" "=r")
2905 (unspec:SI [(match_operand:DI 1 "register_operand" "r")
2906 (match_operand:DI 2 "register_operand" "r")
2907 (match_operand:SI 3 "register_operand" "r")]
2909 (clobber (match_operand:SI 4 "register_operand" "=r"))
2910 (clobber (match_operand:DI 5 "register_operand" "=r"))
2911 (clobber (match_operand:DI 6 "register_operand" "=r"))
2912 (clobber (match_operand:DI 7 "register_operand" "=r"))
2913 (clobber (match_operand:DI 8 "register_operand" "=r"))]
2916 "&& !can_create_pseudo_p ()"
2920 muls.l r19, r19, r18 // u0.28
2921 muls.l r25, r18, r18 // s2.58
2922 shlli r19, 45, r0 // multiply by two and convert to s2.58
2924 shari r18, 28, r18 // some 18 bit inverse in s1.30
2927 rtx inv1 = operands[0];
2928 rtx tab_base = operands[1];
2929 rtx tab_ix = operands[2];
2930 rtx norm32 = operands[3];
2931 rtx inv0 = operands[4];
2932 rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0);
2933 rtx scratch0a = operands[5];
2934 rtx scratch0b = operands[6];
2935 rtx scratch0 = operands[7];
2936 rtx scratch1 = operands[8];
2937 rtx scratch1_si = gen_lowpart (SImode, scratch1);
2939 emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32,
2940 scratch0a, scratch0b));
2941 emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0));
2942 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
2943 emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45)));
2944 emit_insn (gen_subdi3 (scratch1, scratch0, scratch1));
2945 emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28)));
2949 ;; operands: inv2, norm32, inv1, i92
2950 (define_insn_and_split "divsi_inv_m2"
2951 [(set (match_operand:SI 0 "register_operand" "=r")
2952 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2953 (match_operand:SI 2 "register_operand" "r")
2954 (match_operand:DI 3 "register_operand" "r")]
2956 (clobber (match_operand:DI 4 "register_operand" "=r"))]
2959 "&& !can_create_pseudo_p ()"
2963 muls.l r18, r25, r0 // s2.60
2964 shari r0, 16, r0 // s-16.44
2966 muls.l r0, r18, r19 // s-16.74
2967 shari r19, 30, r19 // s-16.44
2969 rtx inv2 = operands[0];
2970 rtx norm32 = operands[1];
2971 rtx inv1 = operands[2];
2972 rtx i92 = operands[3];
2973 rtx scratch0 = operands[4];
2974 rtx scratch0_si = gen_lowpart (SImode, scratch0);
2976 emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32));
2977 emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16)));
2978 emit_insn (gen_subdi3 (scratch0, i92, scratch0));
2979 emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1));
2980 emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30)));
2984 (define_insn_and_split "divsi_inv_m3"
2985 [(set (match_operand:SI 0 "register_operand" "=r")
2986 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
2987 (match_operand:SI 2 "register_operand" "r")
2988 (match_operand:SI 3 "register_operand" "r")
2989 (match_operand:DI 4 "register_operand" "r")
2990 (match_operand:DI 5 "arith_reg_or_0_operand" "rN")
2991 (match_operand:DI 6 "arith_reg_or_0_operand" "rN")]
2993 (clobber (match_operand:DI 7 "register_operand" "=r"))
2994 (clobber (match_operand:DI 8 "register_operand" "=r"))
2995 (clobber (match_operand:DI 9 "register_operand" "=r"))
2996 (clobber (match_operand:DI 10 "register_operand" "=r"))
2997 (clobber (match_operand:SI 11 "register_operand" "=r"))
2998 (clobber (match_operand:SI 12 "register_operand" "=r"))
2999 (clobber (match_operand:DI 13 "register_operand" "=r"))]
3002 "&& !can_create_pseudo_p ()"
3006 r0: result r1: shift r4: dividend r18: inv1 r19: inv2
3007 r0: scratch0 r19: scratch1 r21: scratch2
3009 muls.l r18, r4, r25 // s32.30
3010 muls.l r19, r4, r19 // s15.30
3012 shari r19, 14, r19 // s18.-14
3018 rtx result = operands[0];
3019 rtx dividend = operands[1];
3020 rtx inv1 = operands[2];
3021 rtx inv2 = operands[3];
3022 rtx shift = operands[4];
3023 rtx scratch0 = operands[7];
3024 rtx scratch1 = operands[8];
3025 rtx scratch2 = operands[9];
3027 if (satisfies_constraint_N (dividend))
3029 emit_move_insn (result, dividend);
3033 emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend));
3034 emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend));
3035 emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63)));
3036 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14)));
3037 emit_insn (gen_adddi3 (scratch0, scratch0, scratch1));
3038 emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift));
3039 emit_insn (gen_subdisi3_media (result, scratch0, scratch2));
3043 ;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43
3044 ;; inv1: tab_base, tab_ix, norm32
3045 ;; inv2: norm32, inv1, i92
3046 (define_insn_and_split "divsi_inv_m1_3"
3047 [(set (match_operand:SI 0 "register_operand" "=r")
3048 (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
3049 (unspec:SI [(match_operand:DI 2 "register_operand" "r")
3050 (match_operand:DI 3 "register_operand" "r")
3051 (match_operand:SI 4 "register_operand" "r")]
3053 (unspec:SI [(match_dup 4)
3054 (unspec:SI [(match_dup 2)
3056 (match_dup 4)] UNSPEC_DIV_INV_M1)
3057 (match_operand:SI 5 "" "")]
3059 (match_operand:DI 6 "register_operand" "r")
3060 (match_operand:DI 7 "arith_reg_or_0_operand" "rN")
3061 (match_operand:DI 8 "arith_reg_or_0_operand" "rN")]
3063 (clobber (match_operand:DI 9 "register_operand" "=r"))
3064 (clobber (match_operand:DI 10 "register_operand" "=r"))
3065 (clobber (match_operand:DI 11 "register_operand" "=r"))
3066 (clobber (match_operand:DI 12 "register_operand" "=r"))
3067 (clobber (match_operand:SI 13 "register_operand" "=r"))
3068 (clobber (match_operand:SI 14 "register_operand" "=r"))
3069 (clobber (match_operand:DI 15 "register_operand" "=r"))]
3071 && (TARGET_DIVIDE_INV_MINLAT
3072 || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3074 "&& !can_create_pseudo_p ()"
3077 rtx result = operands[0];
3078 rtx dividend = operands[1];
3079 rtx tab_base = operands[2];
3080 rtx tab_ix = operands[3];
3081 rtx norm32 = operands[4];
3082 /* rtx i92 = operands[5]; */
3083 rtx shift = operands[6];
3084 rtx i2p27 = operands[7];
3085 rtx i43 = operands[8];
3086 rtx scratch0 = operands[9];
3087 rtx scratch0_si = gen_lowpart (SImode, scratch0);
3088 rtx scratch1 = operands[10];
3089 rtx scratch1_si = gen_lowpart (SImode, scratch1);
3090 rtx scratch2 = operands[11];
3091 rtx scratch3 = operands[12];
3092 rtx scratch4 = operands[13];
3093 rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0);
3094 rtx scratch5 = operands[14];
3095 rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0);
3096 rtx scratch6 = operands[15];
3098 emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32,
3099 scratch0, scratch1));
3100 /* inv0 == scratch4 */
3101 if (! TARGET_DIVIDE_INV20U)
3103 emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4));
3105 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si));
3109 emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4));
3110 emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si));
3112 emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45)));
3113 emit_insn (gen_subdi3 (scratch1, scratch2, scratch1));
3114 emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28)));
3115 /* inv1 == scratch4 */
3117 if (TARGET_DIVIDE_INV_MINLAT)
3119 emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32));
3120 emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4));
3121 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16)));
3122 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4));
3123 emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63)));
3124 emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14)));
3125 emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30)));
3126 emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5));
3127 emit_insn (gen_xordi3 (scratch0, scratch3, i2p27));
3128 emit_insn (gen_adddi3 (scratch2, scratch2, scratch0));
3129 emit_insn (gen_subdi3 (scratch2, scratch2, scratch1));
3133 rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
3134 /* Use separate scratch regs for nsb and sign to allow scheduling. */
3135 emit_insn (gen_nsbdi (scratch6,
3136 simplify_gen_subreg (DImode, dividend, SImode, 0)));
3137 emit_insn (gen_xorsi3 (scratch5, dividend, norm32));
3138 emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63)));
3139 emit_insn (gen_divsi_inv20 (scratch2,
3140 norm32, scratch4, dividend,
3141 scratch6, scratch3, i43,
3142 /* scratch0 may be shared with i2p27. */
3143 scratch0, scratch1, scratch5,
3144 label, label, i2p27));
3146 emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift));
3147 emit_insn (gen_subdisi3_media (result, scratch2, scratch3));
3151 (define_insn "divsi_inv20"
3152 [(set (match_operand:DI 0 "register_operand" "=&r")
3153 (unspec:DI [(match_operand:SI 1 "register_operand" "r")
3154 (match_operand:SI 2 "register_operand" "r")
3155 (match_operand:SI 3 "register_operand" "r")
3156 (match_operand:DI 4 "register_operand" "r")
3157 (match_operand:DI 5 "register_operand" "r")
3158 (match_operand:DI 6 "register_operand" "r")
3159 (match_operand:DI 12 "register_operand" "r")
3160 (match_operand 10 "target_operand" "b")
3161 (match_operand 11 "immediate_operand" "i")]
3163 (clobber (match_operand:DI 7 "register_operand" "=&r"))
3164 (clobber (match_operand:DI 8 "register_operand" "=&r"))
3165 (clobber (match_operand:SI 9 "register_operand" "=r"))]
3167 && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)"
3169 /* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend,
3170 %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27,
3171 %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si)
3172 %10 label (tr), %11 label (imm)
3174 muls.l inv1, norm32, scratch0 // s2.60
3175 muls.l inv1, dividend, result // s32.30
3176 xor i2p27, result_sign, round_scratch
3177 bge/u dividend_nsb, i43, tr.. (label)
3178 shari scratch0, 16, scratch0 // s-16.44
3179 muls.l sratch0_si, inv1, scratch0 // s-16.74
3180 sub result, round_scratch, result
3181 shari dividend, 14, scratch1 // s19.-14
3182 shari scratch0, 30, scratch0 // s-16.44
3183 muls.l scratch0, scratch1, round_scratch // s15.30
3185 sub result, round_scratch, result */
3187 const bool likely = TARGET_DIVIDE_INV20L;
3190 "muls.l %2, %3, %0" "\n"
3191 " xor %12, %5, %7" "\n"
3192 " bge/l %4, %6, %10" "\n"
3193 " muls.l %2, %1, %8" "\n"
3194 " shari %8, 16, %8" "\n"
3195 " muls.l %8, %2, %8" "\n"
3196 " shari %3, 14, %9" "\n"
3197 " shari %8, 30, %8" "\n"
3198 " muls.l %8, %9, %8" "\n"
3199 " sub %0, %8, %0" "\n"
3200 "%11: add %0, %7, %0";
3203 "muls.l %2, %1, %8" "\n"
3204 " muls.l %2, %3, %0" "\n"
3205 " xor %12, %5, %7" "\n"
3206 " bge/u %4, %6, %10" "\n"
3207 " shari %8, 16, %8" "\n"
3208 " muls.l %8, %2, %8" "\n"
3209 " sub %0, %7, %0" "\n"
3210 " shari %3, 14, %9" "\n"
3211 " shari %8, 30, %8" "\n"
3212 " muls.l %8, %9, %7" "\n"
3213 "%11: sub %0, %7, %0";
3216 (define_insn_and_split "divsi_inv_fp"
3217 [(set (match_operand:SI 0 "general_movdst_operand" "=rf")
3218 (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf")
3219 (match_operand:SI 2 "register_operand" "rf")))
3220 (use (match_operand:SI 3 "general_movsrc_operand" "r"))
3221 (clobber (match_operand:SI 4 "register_operand" "=r"))
3222 (clobber (match_operand:SI 5 "register_operand" "=r"))
3223 (clobber (match_operand:DF 6 "register_operand" "=r"))
3224 (clobber (match_operand:DF 7 "register_operand" "=r"))
3225 (clobber (match_operand:DF 8 "register_operand" "=r"))]
3226 "TARGET_SHMEDIA_FPU"
3228 "&& (reload_in_progress || reload_completed)"
3229 [(set (match_dup 0) (match_dup 3))]
3231 [(set_attr "highpart" "must_split")])
3233 ;; If a matching group of divide-by-inverse instructions is in the same
3234 ;; basic block after gcse & loop optimizations, we want to transform them
3235 ;; to a straight division using floating point for TARGET_DIVIDE_INV_FP.
3236 (define_insn_and_split "*divsi_inv_fp_combine"
3237 [(set (match_operand:SI 0 "register_operand" "=f")
3238 (div:SI (match_operand:SI 1 "register_operand" "f")
3239 (match_operand:SI 2 "register_operand" "f")))
3240 (use (unspec:SI [(match_dup 1)
3241 (match_operand:SI 3 "" "")
3242 (unspec:SI [(match_operand:SI 4 "" "")
3244 (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2)
3245 (match_operand:DI 6 "" "")
3247 (const_int 0)] UNSPEC_DIV_INV_M3))
3248 (clobber (match_operand:SI 7 "fp_arith_reg_operand" ""))
3249 (clobber (match_operand:SI 8 "fp_arith_reg_operand" ""))
3250 (clobber (match_operand:DF 9 "fp_arith_reg_operand" ""))
3251 (clobber (match_operand:DF 10 "fp_arith_reg_operand" ""))
3252 (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))]
3253 "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()"
3256 [(set (match_dup 9) (float:DF (match_dup 1)))
3257 (set (match_dup 10) (float:DF (match_dup 2)))
3258 (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10)))
3260 (fix:SI (match_dup 11)))
3261 (set (match_dup 0) (match_dup 8))]
3263 if (! fp_arith_reg_operand (operands[1], SImode))
3265 emit_move_insn (operands[7], operands[1]);
3266 operands[1] = operands[7];
3268 if (! fp_arith_reg_operand (operands[2], SImode))
3270 emit_move_insn (operands[8], operands[2]);
3271 operands[2] = operands[8];
3274 [(set_attr "highpart" "must_split")])
3276 ;; -------------------------------------------------------------------------
3277 ;; Multiplication instructions
3278 ;; -------------------------------------------------------------------------
3280 (define_insn "umulhisi3_i"
3281 [(set (reg:SI MACL_REG)
3282 (mult:SI (zero_extend:SI
3283 (match_operand:HI 0 "arith_reg_operand" "r"))
3285 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3288 [(set_attr "type" "smpy")])
3290 (define_insn "mulhisi3_i"
3291 [(set (reg:SI MACL_REG)
3292 (mult:SI (sign_extend:SI
3293 (match_operand:HI 0 "arith_reg_operand" "r"))
3295 (match_operand:HI 1 "arith_reg_operand" "r"))))]
3298 [(set_attr "type" "smpy")])
3300 (define_expand "mulhisi3"
3301 [(set (reg:SI MACL_REG)
3302 (mult:SI (sign_extend:SI
3303 (match_operand:HI 1 "arith_reg_operand" ""))
3305 (match_operand:HI 2 "arith_reg_operand" ""))))
3306 (set (match_operand:SI 0 "arith_reg_operand" "")
3313 macl = gen_rtx_REG (SImode, MACL_REG);
3315 emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
3316 insn = get_insns ();
3318 /* expand_binop can't find a suitable code in umul_widen_optab to
3319 make a REG_EQUAL note from, so make one here.
3320 See also smulsi3_highpart.
3321 ??? Alternatively, we could put this at the calling site of expand_binop,
3322 i.e. expand_expr. */
3323 /* Use emit_libcall_block for loop invariant code motion and to make
3324 a REG_EQUAL note. */
3325 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3330 (define_expand "umulhisi3"
3331 [(set (reg:SI MACL_REG)
3332 (mult:SI (zero_extend:SI
3333 (match_operand:HI 1 "arith_reg_operand" ""))
3335 (match_operand:HI 2 "arith_reg_operand" ""))))
3336 (set (match_operand:SI 0 "arith_reg_operand" "")
3343 macl = gen_rtx_REG (SImode, MACL_REG);
3345 emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
3346 insn = get_insns ();
3348 /* expand_binop can't find a suitable code in umul_widen_optab to
3349 make a REG_EQUAL note from, so make one here.
3350 See also smulsi3_highpart.
3351 ??? Alternatively, we could put this at the calling site of expand_binop,
3352 i.e. expand_expr. */
3353 /* Use emit_libcall_block for loop invariant code motion and to make
3354 a REG_EQUAL note. */
3355 emit_libcall_block (insn, operands[0], macl, SET_SRC (single_set (insn)));
3360 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
3361 ;; a call to a routine which clobbers known registers.
3363 [(set (match_operand:SI 1 "register_operand" "=z")
3364 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
3365 (clobber (reg:SI MACL_REG))
3366 (clobber (reg:SI T_REG))
3367 (clobber (reg:SI PR_REG))
3368 (clobber (reg:SI R3_REG))
3369 (clobber (reg:SI R2_REG))
3370 (clobber (reg:SI R1_REG))
3371 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
3374 [(set_attr "type" "sfunc")
3375 (set_attr "needs_delay_slot" "yes")])
3377 (define_expand "mulsi3_call"
3378 [(set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
3379 (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
3380 (parallel[(set (match_operand:SI 0 "register_operand" "")
3381 (mult:SI (reg:SI R4_REG)
3383 (clobber (reg:SI MACL_REG))
3384 (clobber (reg:SI T_REG))
3385 (clobber (reg:SI PR_REG))
3386 (clobber (reg:SI R3_REG))
3387 (clobber (reg:SI R2_REG))
3388 (clobber (reg:SI R1_REG))
3389 (use (match_operand:SI 3 "register_operand" ""))])]
3393 (define_insn "mul_r"
3394 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3395 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
3396 (match_operand:SI 2 "arith_reg_operand" "z")))]
3399 [(set_attr "type" "dmpy")])
3401 (define_insn "mul_l"
3402 [(set (reg:SI MACL_REG)
3403 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
3404 (match_operand:SI 1 "arith_reg_operand" "r")))]
3407 [(set_attr "type" "dmpy")])
3409 (define_expand "mulsi3"
3410 [(set (reg:SI MACL_REG)
3411 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
3412 (match_operand:SI 2 "arith_reg_operand" "")))
3413 (set (match_operand:SI 0 "arith_reg_operand" "")
3419 /* The address must be set outside the libcall,
3420 since it goes into a pseudo. */
3421 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
3422 rtx addr = force_reg (SImode, sym);
3423 rtx insns = gen_mulsi3_call (operands[0], operands[1],
3429 rtx macl = gen_rtx_REG (SImode, MACL_REG);
3431 emit_insn (gen_mul_l (operands[1], operands[2]));
3432 /* consec_sets_giv can only recognize the first insn that sets a
3433 giv as the giv insn. So we must tag this also with a REG_EQUAL
3435 emit_insn (gen_movsi_i ((operands[0]), macl));
3440 (define_insn "mulsidi3_i"
3441 [(set (reg:SI MACH_REG)
3445 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3446 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3448 (set (reg:SI MACL_REG)
3449 (mult:SI (match_dup 0)
3453 [(set_attr "type" "dmpy")])
3455 (define_expand "mulsidi3"
3456 [(set (match_operand:DI 0 "arith_reg_dest" "")
3457 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3458 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3459 "TARGET_SH2 || TARGET_SHMEDIA"
3463 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
3468 (define_insn "mulsidi3_media"
3469 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3470 (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3471 (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3474 [(set_attr "type" "dmpy_media")
3475 (set_attr "highpart" "ignore")])
3477 (define_insn_and_split "mulsidi3_compact"
3478 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3480 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3481 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3482 (clobber (reg:SI MACH_REG))
3483 (clobber (reg:SI MACL_REG))]
3489 rtx low_dst = gen_lowpart (SImode, operands[0]);
3490 rtx high_dst = gen_highpart (SImode, operands[0]);
3492 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
3494 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3495 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3496 /* We need something to tag the possible REG_EQUAL notes on to. */
3497 emit_move_insn (operands[0], operands[0]);
3501 (define_insn "umulsidi3_i"
3502 [(set (reg:SI MACH_REG)
3506 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3507 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3509 (set (reg:SI MACL_REG)
3510 (mult:SI (match_dup 0)
3514 [(set_attr "type" "dmpy")])
3516 (define_expand "umulsidi3"
3517 [(set (match_operand:DI 0 "arith_reg_dest" "")
3518 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3519 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
3520 "TARGET_SH2 || TARGET_SHMEDIA"
3524 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
3529 (define_insn "umulsidi3_media"
3530 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3531 (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r"))
3532 (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))]
3535 [(set_attr "type" "dmpy_media")
3536 (set_attr "highpart" "ignore")])
3538 (define_insn_and_split "umulsidi3_compact"
3539 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3541 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
3542 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
3543 (clobber (reg:SI MACH_REG))
3544 (clobber (reg:SI MACL_REG))]
3550 rtx low_dst = gen_lowpart (SImode, operands[0]);
3551 rtx high_dst = gen_highpart (SImode, operands[0]);
3553 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
3555 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
3556 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
3557 /* We need something to tag the possible REG_EQUAL notes on to. */
3558 emit_move_insn (operands[0], operands[0]);
3562 (define_insn "smulsi3_highpart_i"
3563 [(set (reg:SI MACH_REG)
3567 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3568 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3570 (clobber (reg:SI MACL_REG))]
3573 [(set_attr "type" "dmpy")])
3575 (define_expand "smulsi3_highpart"
3577 [(set (reg:SI MACH_REG)
3581 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3582 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3584 (clobber (reg:SI MACL_REG))])
3585 (set (match_operand:SI 0 "arith_reg_operand" "")
3592 mach = gen_rtx_REG (SImode, MACH_REG);
3594 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
3595 insn = get_insns ();
3597 /* expand_binop can't find a suitable code in mul_highpart_optab to
3598 make a REG_EQUAL note from, so make one here.
3599 See also {,u}mulhisi.
3600 ??? Alternatively, we could put this at the calling site of expand_binop,
3601 i.e. expand_mult_highpart. */
3602 /* Use emit_libcall_block for loop invariant code motion and to make
3603 a REG_EQUAL note. */
3604 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3609 (define_insn "umulsi3_highpart_i"
3610 [(set (reg:SI MACH_REG)
3614 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
3615 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
3617 (clobber (reg:SI MACL_REG))]
3620 [(set_attr "type" "dmpy")])
3622 (define_expand "umulsi3_highpart"
3624 [(set (reg:SI MACH_REG)
3628 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
3629 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
3631 (clobber (reg:SI MACL_REG))])
3632 (set (match_operand:SI 0 "arith_reg_operand" "")
3639 mach = gen_rtx_REG (SImode, MACH_REG);
3641 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
3642 insn = get_insns ();
3644 /* Use emit_libcall_block for loop invariant code motion and to make
3645 a REG_EQUAL note. */
3646 emit_libcall_block (insn, operands[0], mach, SET_SRC (single_set (insn)));
3651 (define_insn_and_split "muldi3"
3652 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3653 (mult:DI (match_operand:DI 1 "arith_reg_operand" "r")
3654 (match_operand:DI 2 "arith_reg_operand" "r")))
3655 (clobber (match_scratch:DI 3 "=&r"))
3656 (clobber (match_scratch:DI 4 "=r"))]
3662 rtx op3_v2si, op2_v2si;
3664 op3_v2si = operands[3];
3665 if (GET_CODE (op3_v2si) == SIGN_EXTEND)
3667 op3_v2si = XEXP (op3_v2si, 0);
3668 op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0);
3670 op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0);
3671 op2_v2si = operands[2];
3672 if (GET_CODE (op2_v2si) == SIGN_EXTEND)
3674 op2_v2si = XEXP (op2_v2si, 0);
3675 op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0);
3677 op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0);
3678 emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32)));
3679 emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si));
3680 emit_insn (gen_umulsidi3_media (operands[4],
3681 sh_gen_truncate (SImode, operands[1], 0),
3682 sh_gen_truncate (SImode, operands[2], 0)));
3683 emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL)));
3684 emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32)));
3685 emit_insn (gen_adddi3 (operands[0], operands[3], operands[0]));
3686 emit_insn (gen_adddi3 (operands[0], operands[4], operands[0]));
3690 ;; -------------------------------------------------------------------------
3691 ;; Logical operations
3692 ;; -------------------------------------------------------------------------
3694 (define_expand "andsi3"
3695 [(set (match_operand:SI 0 "arith_reg_operand" "")
3696 (and:SI (match_operand:SI 1 "logical_reg_operand" "")
3697 (match_operand:SI 2 "logical_and_operand" "")))]
3700 /* If it is possible to turn the and insn into a zero extension
3701 already, redundant zero extensions will be folded, which results
3703 Ideally the splitter of *andsi_compact would be enough, if redundant
3704 zero extensions were detected after the combine pass, which does not
3705 happen at the moment. */
3708 if (satisfies_constraint_Jmb (operands[2]))
3710 emit_insn (gen_zero_extendqisi2 (operands[0],
3711 gen_lowpart (QImode, operands[1])));
3714 else if (satisfies_constraint_Jmw (operands[2]))
3716 emit_insn (gen_zero_extendhisi2 (operands[0],
3717 gen_lowpart (HImode, operands[1])));
3723 (define_insn_and_split "*andsi_compact"
3724 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
3725 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
3726 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
3734 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
3736 if (satisfies_constraint_Jmb (operands[2]))
3737 operands[1] = gen_lowpart (QImode, operands[1]);
3738 else if (satisfies_constraint_Jmw (operands[2]))
3739 operands[1] = gen_lowpart (HImode, operands[1]);
3743 [(set_attr "type" "arith")])
3745 (define_insn "*andsi3_media"
3746 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3747 (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3748 (match_operand:SI 2 "logical_operand" "r,I10")))]
3753 [(set_attr "type" "arith_media")])
3755 (define_insn "*andsi3_bclr"
3756 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3757 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3758 (match_operand:SI 2 "const_int_operand" "Psz")))]
3759 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
3761 [(set_attr "type" "arith")])
3763 (define_insn_and_split "anddi3"
3764 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
3765 (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
3766 (match_operand:DI 2 "and_operand" "r,I10,J16")))]
3773 && ! logical_operand (operands[2], DImode)"
3776 if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff)
3777 emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode)));
3779 emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1]));
3782 [(set_attr "type" "arith_media")])
3784 (define_insn "andcsi3"
3785 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3786 (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
3787 (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3790 [(set_attr "type" "arith_media")])
3792 (define_insn "andcdi3"
3793 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3794 (and:DI (match_operand:DI 1 "arith_reg_operand" "r")
3795 (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))]
3798 [(set_attr "type" "arith_media")])
3800 (define_expand "iorsi3"
3801 [(set (match_operand:SI 0 "arith_reg_operand" "")
3802 (ior:SI (match_operand:SI 1 "logical_reg_operand" "")
3803 (match_operand:SI 2 "logical_operand" "")))]
3807 (define_insn "*iorsi3_compact"
3808 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
3809 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3810 (match_operand:SI 2 "logical_operand" "r,K08")))]
3812 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
3814 [(set_attr "type" "arith")])
3816 (define_insn "*iorsi3_media"
3817 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3818 (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3819 (match_operand:SI 2 "logical_operand" "r,I10")))]
3824 [(set_attr "type" "arith_media")])
3826 (define_insn "*iorsi3_bset"
3827 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3828 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
3829 (match_operand:SI 2 "const_int_operand" "Pso")))]
3830 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
3832 [(set_attr "type" "arith")])
3834 (define_insn "iordi3"
3835 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3836 (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3837 (match_operand:DI 2 "logical_operand" "r,I10")))]
3842 [(set_attr "type" "arith_media")])
3844 (define_insn_and_split "*logical_sidi3"
3845 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3846 (sign_extend:DI (match_operator:SI 3 "logical_operator"
3847 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3848 (match_operand:SI 2 "logical_operand" "r,I10")])))]
3851 "&& reload_completed"
3852 [(set (match_dup 0) (match_dup 3))]
3855 = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
3856 simplify_gen_subreg (DImode, operands[1], SImode, 0),
3857 simplify_gen_subreg (DImode, operands[2], SImode, 0));
3860 (define_insn_and_split "*logical_sidisi3"
3861 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3862 (truncate:SI (sign_extend:DI
3863 (match_operator:SI 3 "logical_operator"
3864 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3865 (match_operand:SI 2 "logical_operand" "r,I10")]))))]
3869 [(set (match_dup 0) (match_dup 3))])
3871 (define_insn_and_split "*logical_sidi3_2"
3872 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3873 (sign_extend:DI (truncate:SI (sign_extend:DI
3874 (match_operator:SI 3 "logical_operator"
3875 [(match_operand:SI 1 "arith_reg_operand" "%r,r")
3876 (match_operand:SI 2 "logical_operand" "r,I10")])))))]
3880 [(set (match_dup 0) (sign_extend:DI (match_dup 3)))])
3882 (define_expand "xorsi3"
3883 [(set (match_operand:SI 0 "arith_reg_operand" "")
3884 (xor:SI (match_operand:SI 1 "logical_reg_operand" "")
3885 (match_operand:SI 2 "xor_operand" "")))]
3889 (define_insn "*xorsi3_compact"
3890 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
3891 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
3892 (match_operand:SI 2 "logical_operand" "K08,r")))]
3895 [(set_attr "type" "arith")])
3897 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
3898 ;; of results where one of the inputs is a T bit store. Notice that this
3899 ;; pattern must not match during reload. If reload picks this pattern it
3900 ;; will be impossible to split it afterwards.
3901 (define_insn_and_split "*logical_op_t"
3902 [(set (match_operand:SI 0 "arith_reg_dest")
3903 (match_operator:SI 3 "logical_operator"
3904 [(match_operand:SI 1 "arith_reg_operand")
3905 (match_operand:SI 2 "t_reg_operand")]))]
3906 "TARGET_SH1 && can_create_pseudo_p ()"
3909 [(set (match_dup 4) (reg:SI T_REG))
3910 (set (match_dup 0) (match_dup 3))]
3912 operands[4] = gen_reg_rtx (SImode);
3913 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3914 operands[1], operands[4]);
3917 (define_insn "*xorsi3_media"
3918 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3919 (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r")
3920 (match_operand:SI 2 "xor_operand" "r,I06")))]
3925 [(set_attr "type" "arith_media")])
3927 (define_insn "xordi3"
3928 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
3929 (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
3930 (match_operand:DI 2 "xor_operand" "r,I06")))]
3935 [(set_attr "type" "arith_media")])
3937 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
3938 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
3940 [(set (match_operand:DI 0 "arith_reg_dest" "")
3941 (sign_extend:DI (match_operator 4 "binary_logical_operator"
3942 [(match_operand 1 "any_register_operand" "")
3943 (match_operand 2 "any_register_operand" "")])))]
3945 [(set (match_dup 5) (match_dup 4))
3946 (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
3948 machine_mode inmode = GET_MODE (operands[1]);
3951 if (GET_CODE (operands[0]) == SUBREG)
3953 offset = SUBREG_BYTE (operands[0]);
3954 operands[0] = SUBREG_REG (operands[0]);
3956 gcc_assert (REG_P (operands[0]));
3957 if (TARGET_BIG_ENDIAN)
3958 offset += 8 - GET_MODE_SIZE (inmode);
3959 operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
3962 ;; -------------------------------------------------------------------------
3963 ;; Shifts and rotates
3964 ;; -------------------------------------------------------------------------
3966 (define_expand "rotldi3"
3967 [(set (match_operand:DI 0 "arith_reg_dest" "")
3968 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
3969 (match_operand:HI 2 "mextr_bit_offset" "")))]
3972 if (! mextr_bit_offset (operands[2], HImode))
3976 (define_insn "rotldi3_mextr"
3977 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3978 (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r")
3979 (match_operand:HI 2 "mextr_bit_offset" "i")))]
3982 static char templ[16];
3983 sprintf (templ, "mextr%d %%1,%%1,%%0",
3984 8 - (int) (INTVAL (operands[2]) >> 3));
3987 [(set_attr "type" "arith_media")])
3989 (define_expand "rotrdi3"
3990 [(set (match_operand:DI 0 "arith_reg_dest" "")
3991 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
3992 (match_operand:HI 2 "mextr_bit_offset" "")))]
3995 if (! mextr_bit_offset (operands[2], HImode))
3999 (define_insn "rotrdi3_mextr"
4000 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4001 (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r")
4002 (match_operand:HI 2 "mextr_bit_offset" "i")))]
4005 static char templ[16];
4006 sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3);
4009 [(set_attr "type" "arith_media")])
4012 [(set (match_operand:DI 0 "arith_reg_dest" "")
4013 (ior:DI (zero_extend:DI (mem:QI (match_operand 1
4014 "ua_address_operand" "")))
4015 (ashift:DI (match_operand:DI 2 "arith_reg_operand" "")
4017 (clobber (match_operand:DI 3 "register_operand" ""))]
4019 [(match_dup 4) (match_dup 5)]
4021 operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q)
4022 (operands[3], operands[1]));
4023 operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2],
4024 GEN_INT (56), GEN_INT (8));
4027 (define_expand "rotrsi3"
4028 [(set (match_operand:SI 0 "arith_reg_dest")
4029 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
4030 (match_operand:SI 2 "const_int_operand")))]
4033 HOST_WIDE_INT ival = INTVAL (operands[2]);
4036 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
4043 (define_insn "rotrsi3_1"
4044 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4045 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4048 (and:SI (match_dup 1) (const_int 1)))]
4051 [(set_attr "type" "arith")])
4053 ;; A slimplified version of rotr for combine.
4054 (define_insn "*rotrsi3_1"
4055 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4056 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
4058 (clobber (reg:SI T_REG))]
4061 [(set_attr "type" "arith")])
4063 (define_insn "rotlsi3_1"
4064 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4065 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4068 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4071 [(set_attr "type" "arith")])
4073 ;; A simplified version of rotl for combine.
4074 (define_insn "*rotlsi3_1"
4075 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4076 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4078 (clobber (reg:SI T_REG))]
4081 [(set_attr "type" "arith")])
4083 (define_insn "rotlsi3_31"
4084 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4085 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
4087 (clobber (reg:SI T_REG))]
4090 [(set_attr "type" "arith")])
4092 (define_insn "rotlsi3_16"
4093 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4094 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
4098 [(set_attr "type" "arith")])
4100 (define_expand "rotlsi3"
4101 [(set (match_operand:SI 0 "arith_reg_dest")
4102 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
4103 (match_operand:SI 2 "const_int_operand")))]
4106 static const char rot_tab[] = {
4107 000, 000, 000, 000, 000, 000, 010, 001,
4108 001, 001, 011, 013, 003, 003, 003, 003,
4109 003, 003, 003, 003, 003, 013, 012, 002,
4110 002, 002, 010, 000, 000, 000, 000, 000,
4113 int count = INTVAL (operands[2]);
4114 int choice = rot_tab[count];
4115 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
4121 emit_move_insn (operands[0], operands[1]);
4122 count -= (count & 16) * 2;
4125 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
4132 parts[0] = gen_reg_rtx (SImode);
4133 parts[1] = gen_reg_rtx (SImode);
4134 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
4135 emit_move_insn (parts[choice-1], operands[1]);
4136 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
4137 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
4138 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
4139 count = (count & ~16) - 8;
4143 for (; count > 0; count--)
4144 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
4145 for (; count < 0; count++)
4146 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4151 (define_insn "rotlhi3_8"
4152 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4153 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
4157 [(set_attr "type" "arith")])
4159 (define_expand "rotlhi3"
4160 [(set (match_operand:HI 0 "arith_reg_operand")
4161 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
4162 (match_operand:HI 2 "const_int_operand")))]
4165 if (INTVAL (operands[2]) != 8)
4169 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
4170 ;; They can also be used to implement things like
4172 ;; int x0 = (y >> 1) | (t << 31); // rotcr
4173 ;; int x1 = (y << 1) | t; // rotcl
4174 (define_insn "rotcr"
4175 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4176 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4178 (ashift:SI (match_operand:SI 2 "t_reg_operand")
4181 (and:SI (match_dup 1) (const_int 1)))]
4184 [(set_attr "type" "arith")])
4186 (define_insn "rotcl"
4187 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4188 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4190 (match_operand:SI 2 "t_reg_operand")))
4192 (lshiftrt:SI (match_dup 1) (const_int 31)))]
4195 [(set_attr "type" "arith")])
4197 ;; Simplified rotcr version for combine, which allows arbitrary shift
4198 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
4199 ;; directly. Otherwise we have to insert a shift in between.
4200 (define_insn_and_split "*rotcr"
4201 [(set (match_operand:SI 0 "arith_reg_dest")
4202 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4203 (match_operand:SI 2 "const_int_operand"))
4204 (ashift:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4206 (clobber (reg:SI T_REG))]
4209 "&& can_create_pseudo_p ()"
4212 if (INTVAL (operands[2]) > 1)
4214 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4215 rtx prev_set_t_insn = NULL_RTX;
4216 rtx tmp_t_reg = NULL_RTX;
4218 /* If we're going to emit a shift sequence that clobbers the T_REG,
4219 try to find the previous insn that sets the T_REG and emit the
4220 shift insn before that insn, to remove the T_REG dependency.
4221 If the insn that sets the T_REG cannot be found, store the T_REG
4222 in a temporary reg and restore it after the shift. */
4223 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
4224 && ! sh_dynamicalize_shift_p (shift_count))
4226 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4228 /* Skip the nott insn, which was probably inserted by the splitter
4229 of *rotcr_neg_t. Don't use one of the recog functions
4230 here during insn splitting, since that causes problems in later
4232 if (prev_set_t_insn != NULL_RTX)
4234 rtx pat = PATTERN (prev_set_t_insn);
4235 if (GET_CODE (pat) == SET
4236 && t_reg_operand (XEXP (pat, 0), SImode)
4237 && negt_reg_operand (XEXP (pat, 1), SImode))
4238 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4241 if (! (prev_set_t_insn != NULL_RTX
4242 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4243 && ! reg_referenced_p (get_t_reg_rtx (),
4244 PATTERN (prev_set_t_insn))))
4246 prev_set_t_insn = NULL_RTX;
4247 tmp_t_reg = gen_reg_rtx (SImode);
4248 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4252 rtx shift_result = gen_reg_rtx (SImode);
4253 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
4254 operands[1] = shift_result;
4256 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4257 if (prev_set_t_insn != NULL_RTX)
4258 emit_insn_before (shift_insn, prev_set_t_insn);
4260 emit_insn (shift_insn);
4262 /* Restore T_REG if it has been saved before. */
4263 if (tmp_t_reg != NULL_RTX)
4264 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4267 /* For the rotcr insn to work, operands[3] must be in T_REG.
4268 If it is not we can get it there by shifting it right one bit.
4269 In this case T_REG is not an input for this insn, thus we don't have to
4270 pay attention as of where to insert the shlr insn. */
4271 if (! t_reg_operand (operands[3], SImode))
4273 /* We don't care about the shifted result here, only the T_REG. */
4274 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4275 operands[3] = get_t_reg_rtx ();
4278 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
4282 ;; If combine tries the same as above but with swapped operands, split
4283 ;; it so that it will try the pattern above.
4285 [(set (match_operand:SI 0 "arith_reg_dest")
4286 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4288 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4289 (match_operand:SI 3 "const_int_operand"))))]
4290 "TARGET_SH1 && can_create_pseudo_p ()"
4291 [(parallel [(set (match_dup 0)
4292 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4293 (ashift:SI (match_dup 1) (const_int 31))))
4294 (clobber (reg:SI T_REG))])])
4296 ;; Basically the same as the rotcr pattern above, but for rotcl.
4297 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
4298 (define_insn_and_split "*rotcl"
4299 [(set (match_operand:SI 0 "arith_reg_dest")
4300 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4301 (match_operand:SI 2 "const_int_operand"))
4302 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
4304 (clobber (reg:SI T_REG))]
4307 "&& can_create_pseudo_p ()"
4310 gcc_assert (INTVAL (operands[2]) > 0);
4312 if (INTVAL (operands[2]) > 1)
4314 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
4315 rtx prev_set_t_insn = NULL_RTX;
4316 rtx tmp_t_reg = NULL_RTX;
4318 /* If we're going to emit a shift sequence that clobbers the T_REG,
4319 try to find the previous insn that sets the T_REG and emit the
4320 shift insn before that insn, to remove the T_REG dependency.
4321 If the insn that sets the T_REG cannot be found, store the T_REG
4322 in a temporary reg and restore it after the shift. */
4323 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
4324 && ! sh_dynamicalize_shift_p (shift_count))
4326 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
4328 /* Skip the nott insn, which was probably inserted by the splitter
4329 of *rotcl_neg_t. Don't use one of the recog functions
4330 here during insn splitting, since that causes problems in later
4332 if (prev_set_t_insn != NULL_RTX)
4334 rtx pat = PATTERN (prev_set_t_insn);
4335 if (GET_CODE (pat) == SET
4336 && t_reg_operand (XEXP (pat, 0), SImode)
4337 && negt_reg_operand (XEXP (pat, 1), SImode))
4338 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
4341 if (! (prev_set_t_insn != NULL_RTX
4342 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
4343 && ! reg_referenced_p (get_t_reg_rtx (),
4344 PATTERN (prev_set_t_insn))))
4346 prev_set_t_insn = NULL_RTX;
4347 tmp_t_reg = gen_reg_rtx (SImode);
4348 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
4352 rtx shift_result = gen_reg_rtx (SImode);
4353 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
4354 operands[1] = shift_result;
4356 /* Emit the shift insn before the insn that sets T_REG, if possible. */
4357 if (prev_set_t_insn != NULL_RTX)
4358 emit_insn_before (shift_insn, prev_set_t_insn);
4360 emit_insn (shift_insn);
4362 /* Restore T_REG if it has been saved before. */
4363 if (tmp_t_reg != NULL_RTX)
4364 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
4367 /* For the rotcl insn to work, operands[3] must be in T_REG.
4368 If it is not we can get it there by shifting it right one bit.
4369 In this case T_REG is not an input for this insn, thus we don't have to
4370 pay attention as of where to insert the shlr insn. */
4371 if (! t_reg_operand (operands[3], SImode))
4373 /* We don't care about the shifted result here, only the T_REG. */
4374 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
4375 operands[3] = get_t_reg_rtx ();
4378 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
4382 ;; rotcl combine pattern variations
4383 (define_insn_and_split "*rotcl"
4384 [(set (match_operand:SI 0 "arith_reg_dest")
4385 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4386 (match_operand:SI 2 "const_int_operand"))
4387 (match_operand:SI 3 "t_reg_operand")))
4388 (clobber (reg:SI T_REG))]
4391 "&& can_create_pseudo_p ()"
4392 [(parallel [(set (match_dup 0)
4393 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4394 (and:SI (match_dup 3) (const_int 1))))
4395 (clobber (reg:SI T_REG))])])
4397 (define_insn_and_split "*rotcl"
4398 [(set (match_operand:SI 0 "arith_reg_dest")
4399 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
4401 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4402 (match_operand:SI 3 "const_int_operand"))))
4403 (clobber (reg:SI T_REG))]
4406 "&& can_create_pseudo_p ()"
4407 [(parallel [(set (match_dup 0)
4408 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4409 (and:SI (match_dup 1) (const_int 1))))
4410 (clobber (reg:SI T_REG))])])
4412 (define_insn_and_split "*rotcl"
4413 [(set (match_operand:SI 0 "arith_reg_dest")
4414 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4415 (match_operand:SI 2 "const_int_operand"))
4416 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4418 (clobber (reg:SI T_REG))]
4421 "&& can_create_pseudo_p ()"
4422 [(parallel [(set (match_dup 0)
4423 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4424 (and:SI (reg:SI T_REG) (const_int 1))))
4425 (clobber (reg:SI T_REG))])]
4427 /* We don't care about the result of the left shift, only the T_REG. */
4428 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4431 (define_insn_and_split "*rotcl"
4432 [(set (match_operand:SI 0 "arith_reg_dest")
4433 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
4435 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
4436 (match_operand:SI 2 "const_int_operand"))))
4437 (clobber (reg:SI T_REG))]
4440 "&& can_create_pseudo_p ()"
4441 [(parallel [(set (match_dup 0)
4442 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
4443 (and:SI (reg:SI T_REG) (const_int 1))))
4444 (clobber (reg:SI T_REG))])]
4446 /* We don't care about the result of the left shift, only the T_REG. */
4447 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
4450 ;; rotcr combine bridge pattern which will make combine try out more
4451 ;; complex patterns.
4452 (define_insn_and_split "*rotcr"
4453 [(set (match_operand:SI 0 "arith_reg_dest")
4454 (ashift:SI (match_operand:SI 1 "t_reg_operand") (const_int 31)))]
4458 [(set (match_dup 0) (match_dup 1))
4459 (parallel [(set (match_dup 0)
4460 (ior:SI (lshiftrt:SI (match_dup 0) (const_int 1))
4461 (ashift:SI (match_dup 1) (const_int 31))))
4463 (and:SI (match_dup 0) (const_int 1)))])])
4465 (define_insn_and_split "*rotcr"
4466 [(set (match_operand:SI 0 "arith_reg_dest")
4467 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
4468 (const_int -2147483648)) ;; 0xffffffff80000000
4469 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4471 (clobber (reg:SI T_REG))]
4474 "&& can_create_pseudo_p ()"
4477 rtx tmp = gen_reg_rtx (SImode);
4478 emit_insn (gen_shll (tmp, operands[1]));
4479 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
4483 ;; rotcr combine patterns for rotating in the negated T_REG value.
4484 (define_insn_and_split "*rotcr_neg_t"
4485 [(set (match_operand:SI 0 "arith_reg_dest")
4486 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
4487 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
4488 (match_operand:SI 3 "const_int_operand"))))
4489 (clobber (reg:SI T_REG))]
4492 "&& can_create_pseudo_p ()"
4493 [(parallel [(set (match_dup 0)
4494 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
4495 (ashift:SI (reg:SI T_REG) (const_int 31))))
4496 (clobber (reg:SI T_REG))])]
4498 emit_insn (gen_nott (get_t_reg_rtx ()));
4501 (define_insn_and_split "*rotcr_neg_t"
4502 [(set (match_operand:SI 0 "arith_reg_dest")
4503 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
4504 (match_operand:SI 2 "const_int_operand"))
4505 (match_operand:SI 3 "negt_reg_shl31_operand")))
4506 (clobber (reg:SI T_REG))]
4509 "&& can_create_pseudo_p ()"
4510 [(parallel [(set (match_dup 0)
4511 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4512 (ashift:SI (reg:SI T_REG) (const_int 31))))
4513 (clobber (reg:SI T_REG))])]
4515 emit_insn (gen_nott (get_t_reg_rtx ()));
4518 ;; rotcl combine patterns for rotating in the negated T_REG value.
4519 ;; For some strange reason these have to be specified as splits which combine
4520 ;; will pick up. If they are specified as insn_and_split like the
4521 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
4522 ;; but not emit them on non-SH2A targets.
4524 [(set (match_operand:SI 0 "arith_reg_dest")
4525 (ior:SI (match_operand:SI 1 "negt_reg_operand")
4526 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4527 (match_operand:SI 3 "const_int_operand"))))]
4529 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4530 (parallel [(set (match_dup 0)
4531 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4532 (and:SI (reg:SI T_REG) (const_int 1))))
4533 (clobber (reg:SI T_REG))])])
4536 [(set (match_operand:SI 0 "arith_reg_dest")
4537 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
4538 (match_operand:SI 3 "const_int_operand"))
4539 (match_operand:SI 1 "negt_reg_operand")))]
4541 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
4542 (parallel [(set (match_dup 0)
4543 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
4544 (and:SI (reg:SI T_REG) (const_int 1))))
4545 (clobber (reg:SI T_REG))])])
4547 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4548 ;; SImode shift left
4550 (define_expand "ashlsi3"
4551 [(set (match_operand:SI 0 "arith_reg_operand" "")
4552 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
4553 (match_operand:SI 2 "shift_count_operand" "")))]
4558 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4560 operands[2] = GEN_INT (-INTVAL (operands[2]));
4561 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4564 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4568 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
4569 operands[2] = force_reg (SImode, operands[2]);
4571 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
4573 if (CONST_INT_P (operands[2])
4574 && sh_ashlsi_clobbers_t_reg_p (operands[2])
4575 && ! sh_dynamicalize_shift_p (operands[2]))
4577 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
4582 /* Expand a library call for the dynamic shift. */
4583 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
4585 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
4586 rtx funcaddr = gen_reg_rtx (Pmode);
4587 function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
4588 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
4594 (define_insn "ashlsi3_k"
4595 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4596 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
4597 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
4602 [(set_attr "type" "arith")])
4604 (define_insn_and_split "ashlsi3_d"
4605 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4606 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4607 (match_operand:SI 2 "shift_count_operand" "r")))]
4610 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
4611 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4614 if (satisfies_constraint_P27 (operands[2]))
4616 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
4619 else if (! satisfies_constraint_P27 (operands[2]))
4621 /* This must happen before reload, otherwise the constant will be moved
4622 into a register due to the "r" constraint, after which this split
4623 cannot be done anymore.
4624 Unfortunately the move insn will not always be eliminated.
4625 Also, here we must not create a shift sequence that clobbers the
4627 emit_move_insn (operands[0], operands[1]);
4628 gen_shifty_op (ASHIFT, operands);
4634 [(set_attr "type" "dyn_shift")])
4636 ;; If dynamic shifts are not available use a library function.
4637 ;; By specifying the pattern we reduce the number of call clobbered regs.
4638 ;; In order to make combine understand the truncation of the shift amount
4639 ;; operand we have to allow it to use pseudo regs for the shift operands.
4640 (define_insn "ashlsi3_d_call"
4641 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4642 (ashift:SI (reg:SI R4_REG)
4643 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
4645 (use (match_operand:SI 2 "arith_reg_operand" "r"))
4646 (clobber (reg:SI T_REG))
4647 (clobber (reg:SI PR_REG))]
4648 "TARGET_SH1 && !TARGET_DYNSHIFT"
4650 [(set_attr "type" "sfunc")
4651 (set_attr "needs_delay_slot" "yes")])
4653 (define_insn_and_split "ashlsi3_n"
4654 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4655 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4656 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
4657 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
4659 "&& (reload_completed
4660 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4663 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4665 /* If this pattern was picked and dynamic shifts are supported, switch
4666 to dynamic shift pattern before reload. */
4667 operands[2] = force_reg (SImode, operands[2]);
4668 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4671 gen_shifty_op (ASHIFT, operands);
4676 (define_insn_and_split "ashlsi3_n_clobbers_t"
4677 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4678 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
4679 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
4680 (clobber (reg:SI T_REG))]
4681 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
4683 "&& (reload_completed || INTVAL (operands[2]) == 31
4684 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4687 if (INTVAL (operands[2]) == 31)
4689 /* If the shift amount is 31 we split into a different sequence before
4690 reload so that it gets a chance to allocate R0 for the sequence.
4691 If it fails to do so (due to pressure on R0), it will take one insn
4692 more for the and. */
4693 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
4694 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
4696 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4698 /* If this pattern was picked and dynamic shifts are supported, switch
4699 to dynamic shift pattern before reload. */
4700 operands[2] = force_reg (SImode, operands[2]);
4701 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
4704 gen_shifty_op (ASHIFT, operands);
4710 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4711 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
4713 (lt:SI (match_dup 1) (const_int 0)))]
4716 [(set_attr "type" "arith")])
4718 (define_insn "*ashlsi_c_void"
4719 [(set (reg:SI T_REG)
4720 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
4721 (clobber (match_scratch:SI 1 "=0"))]
4722 "TARGET_SH1 && cse_not_expected"
4724 [(set_attr "type" "arith")])
4727 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
4729 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
4731 && peep2_reg_dead_p (2, operands[0])
4732 && peep2_reg_dead_p (2, operands[1])"
4735 emit_insn (gen_shll (operands[1], operands[1]));
4739 (define_insn "ashlsi3_media"
4740 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4741 (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4742 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4747 [(set_attr "type" "arith_media")
4748 (set_attr "highpart" "ignore")])
4750 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4751 ;; HImode shift left
4753 (define_expand "ashlhi3"
4754 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
4755 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
4756 (match_operand:SI 2 "nonmemory_operand" "")))
4757 (clobber (reg:SI T_REG))])]
4760 if (!CONST_INT_P (operands[2]))
4762 /* It may be possible to call gen_ashlhi3 directly with more generic
4763 operands. Make sure operands[1] is a HImode register here. */
4764 if (!arith_reg_operand (operands[1], HImode))
4765 operands[1] = copy_to_mode_reg (HImode, operands[1]);
4768 (define_insn "ashlhi3_k"
4769 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
4770 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
4771 (match_operand:HI 2 "const_int_operand" "M,P27")))]
4772 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
4776 [(set_attr "type" "arith")])
4778 (define_insn_and_split "*ashlhi3_n"
4779 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4780 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
4781 (match_operand:HI 2 "const_int_operand" "n")))
4782 (clobber (reg:SI T_REG))]
4785 "&& reload_completed"
4786 [(use (reg:SI R0_REG))]
4788 gen_shifty_hi_op (ASHIFT, operands);
4792 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4793 ;; DImode shift left
4795 (define_expand "ashldi3"
4796 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4797 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
4798 (match_operand:DI 2 "immediate_operand" "")))
4799 (clobber (reg:SI T_REG))])]
4804 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4806 operands[2] = GEN_INT (-INTVAL (operands[2]));
4807 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
4810 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
4813 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
4815 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
4818 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
4820 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
4827 ;; Expander for DImode shift left with SImode operations.
4828 (define_expand "ashldi3_std"
4829 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4830 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4831 (match_operand:DI 2 "const_int_operand" "n")))]
4832 "TARGET_SH1 && INTVAL (operands[2]) < 32"
4834 rtx low_src = gen_lowpart (SImode, operands[1]);
4835 rtx high_src = gen_highpart (SImode, operands[1]);
4836 rtx dst = gen_reg_rtx (DImode);
4837 rtx low_dst = gen_lowpart (SImode, dst);
4838 rtx high_dst = gen_highpart (SImode, dst);
4839 rtx tmp0 = gen_reg_rtx (SImode);
4840 rtx tmp1 = gen_reg_rtx (SImode);
4842 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
4843 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
4844 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
4845 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
4846 emit_move_insn (operands[0], dst);
4850 (define_insn_and_split "ashldi3_k"
4851 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4852 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
4854 (clobber (reg:SI T_REG))]
4857 "&& reload_completed"
4860 rtx high = gen_highpart (SImode, operands[0]);
4861 rtx low = gen_lowpart (SImode, operands[0]);
4862 emit_insn (gen_shll (low, low));
4863 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
4867 (define_insn "ashldi3_media"
4868 [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
4869 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
4870 (match_operand:DI 2 "shift_count_operand" "r,n")))]
4875 [(set_attr "type" "arith_media")])
4877 (define_insn "*ashldisi3_media"
4878 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
4879 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
4880 (match_operand:DI 2 "const_int_operand" "n")))]
4881 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
4882 "shlli.l %1, %2, %0"
4883 [(set_attr "type" "arith_media")
4884 (set_attr "highpart" "ignore")])
4886 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4887 ;; SImode arithmetic shift right
4889 ;; We can't do HImode right shifts correctly unless we start out with an
4890 ;; explicit zero / sign extension; doing that would result in worse overall
4891 ;; code, so just let the machine independent code widen the mode.
4892 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
4894 (define_expand "ashrsi3"
4895 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
4896 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
4897 (match_operand:SI 2 "nonmemory_operand" "")))
4898 (clobber (reg:SI T_REG))])]
4903 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
4905 operands[2] = GEN_INT (-INTVAL (operands[2]));
4906 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
4909 emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2]));
4912 if (expand_ashiftrt (operands))
4919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4920 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4923 (and:SI (match_dup 1) (const_int 1)))]
4926 [(set_attr "type" "arith")])
4928 (define_insn "ashrsi3_k"
4929 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4930 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4931 (match_operand:SI 2 "const_int_operand" "M")))
4932 (clobber (reg:SI T_REG))]
4933 "TARGET_SH1 && INTVAL (operands[2]) == 1"
4935 [(set_attr "type" "arith")])
4937 (define_insn_and_split "ashrsi2_16"
4938 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4939 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
4944 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
4945 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
4947 operands[2] = gen_lowpart (HImode, operands[0]);
4950 (define_insn_and_split "ashrsi2_31"
4951 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4952 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4954 (clobber (reg:SI T_REG))]
4960 emit_insn (gen_shll (operands[0], operands[1]));
4961 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
4965 (define_insn "ashrsi3_d"
4966 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4967 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4968 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
4971 [(set_attr "type" "dyn_shift")])
4973 (define_insn "ashrsi3_n"
4974 [(set (reg:SI R4_REG)
4975 (ashiftrt:SI (reg:SI R4_REG)
4976 (match_operand:SI 0 "const_int_operand" "i")))
4977 (clobber (reg:SI T_REG))
4978 (clobber (reg:SI PR_REG))
4979 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
4982 [(set_attr "type" "sfunc")
4983 (set_attr "needs_delay_slot" "yes")])
4985 (define_insn "ashrsi3_media"
4986 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4987 (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
4988 (match_operand:SI 2 "shift_count_operand" "r,n")))]
4993 [(set_attr "type" "arith_media")
4994 (set_attr "highpart" "ignore")])
4996 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4997 ;; DImode arithmetic shift right
4999 (define_expand "ashrdi3"
5000 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5001 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5002 (match_operand:DI 2 "immediate_operand" "")))
5003 (clobber (reg:SI T_REG))])]
5008 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5010 operands[2] = GEN_INT (-INTVAL (operands[2]));
5011 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5014 emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
5017 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5021 (define_insn_and_split "ashrdi3_k"
5022 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5023 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5025 (clobber (reg:SI T_REG))]
5028 "&& reload_completed"
5031 rtx high = gen_highpart (SImode, operands[0]);
5032 rtx low = gen_lowpart (SImode, operands[0]);
5033 emit_insn (gen_shar (high, high));
5034 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5038 (define_insn "ashrdi3_media"
5039 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5040 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5041 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5043 && (arith_reg_dest (operands[0], DImode)
5044 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
5048 [(set_attr "type" "arith_media")])
5050 (define_insn "*ashrdisi3_media"
5051 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5052 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5053 (match_operand:DI 2 "const_int_operand" "n")))]
5054 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5055 "shari.l %1, %2, %0"
5056 [(set_attr "type" "arith_media")
5057 (set_attr "highpart" "ignore")])
5059 (define_insn "ashrdisi3_media_high"
5060 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5062 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5063 (match_operand:DI 2 "const_int_operand" "n"))))]
5064 "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32"
5066 [(set_attr "type" "arith_media")])
5068 (define_insn "ashrdisi3_media_opaque"
5069 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5070 (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r")
5071 (match_operand:DI 2 "const_int_operand" "n")]
5075 [(set_attr "type" "arith_media")])
5077 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5078 ;; SImode logical shift right
5080 (define_expand "lshrsi3"
5081 [(set (match_operand:SI 0 "arith_reg_dest" "")
5082 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
5083 (match_operand:SI 2 "shift_count_operand" "")))]
5088 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5090 operands[2] = GEN_INT (-INTVAL (operands[2]));
5091 emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
5094 emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
5098 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
5099 here, otherwise the pattern will never match due to the shift amount reg
5102 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
5104 rtx neg_count = force_reg (SImode,
5105 gen_int_mode (- INTVAL (operands[2]), SImode));
5106 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5110 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
5112 rtx neg_count = gen_reg_rtx (SImode);
5113 emit_insn (gen_negsi2 (neg_count, operands[2]));
5114 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
5118 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
5120 if (CONST_INT_P (operands[2])
5121 && sh_lshrsi_clobbers_t_reg_p (operands[2])
5122 && ! sh_dynamicalize_shift_p (operands[2]))
5124 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
5129 /* Expand a library call for the dynamic shift. */
5130 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
5132 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
5133 rtx funcaddr = gen_reg_rtx (Pmode);
5134 function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
5135 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
5140 (define_insn "lshrsi3_k"
5141 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5142 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5143 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
5146 [(set_attr "type" "arith")])
5148 (define_insn_and_split "lshrsi3_d"
5149 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5150 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5151 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
5154 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
5155 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5158 if (satisfies_constraint_P27 (operands[2]))
5160 /* This will not be done for a shift amount of 1, because it would
5161 clobber the T_REG. */
5162 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
5165 else if (! satisfies_constraint_P27 (operands[2]))
5167 /* This must happen before reload, otherwise the constant will be moved
5168 into a register due to the "r" constraint, after which this split
5169 cannot be done anymore.
5170 Unfortunately the move insn will not always be eliminated.
5171 Also, here we must not create a shift sequence that clobbers the
5173 emit_move_insn (operands[0], operands[1]);
5174 gen_shifty_op (LSHIFTRT, operands);
5180 [(set_attr "type" "dyn_shift")])
5182 ;; If dynamic shifts are not available use a library function.
5183 ;; By specifying the pattern we reduce the number of call clobbered regs.
5184 ;; In order to make combine understand the truncation of the shift amount
5185 ;; operand we have to allow it to use pseudo regs for the shift operands.
5186 (define_insn "lshrsi3_d_call"
5187 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
5188 (lshiftrt:SI (reg:SI R4_REG)
5189 (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
5191 (use (match_operand:SI 2 "arith_reg_operand" "r"))
5192 (clobber (reg:SI T_REG))
5193 (clobber (reg:SI PR_REG))]
5194 "TARGET_SH1 && !TARGET_DYNSHIFT"
5196 [(set_attr "type" "sfunc")
5197 (set_attr "needs_delay_slot" "yes")])
5199 (define_insn_and_split "lshrsi3_n"
5200 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5201 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5202 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
5203 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
5205 "&& (reload_completed
5206 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5209 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5211 /* If this pattern was picked and dynamic shifts are supported, switch
5212 to dynamic shift pattern before reload. */
5213 operands[2] = force_reg (SImode,
5214 gen_int_mode (- INTVAL (operands[2]), SImode));
5215 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5218 gen_shifty_op (LSHIFTRT, operands);
5223 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
5224 ;; the shlr pattern.
5225 (define_insn_and_split "lshrsi3_n_clobbers_t"
5226 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5227 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5228 (match_operand:SI 2 "not_p27_rshift_count_operand")))
5229 (clobber (reg:SI T_REG))]
5230 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
5232 "&& (reload_completed || INTVAL (operands[2]) == 31
5233 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
5236 if (INTVAL (operands[2]) == 31)
5238 emit_insn (gen_shll (operands[0], operands[1]));
5239 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
5241 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
5243 /* If this pattern was picked and dynamic shifts are supported, switch
5244 to dynamic shift pattern before reload. */
5245 operands[2] = force_reg (SImode,
5246 gen_int_mode (- INTVAL (operands[2]), SImode));
5247 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
5250 gen_shifty_op (LSHIFTRT, operands);
5256 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5257 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5260 (and:SI (match_dup 1) (const_int 1)))]
5263 [(set_attr "type" "arith")])
5265 (define_insn "lshrsi3_media"
5266 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5267 (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
5268 (match_operand:SI 2 "shift_count_operand" "r,n")))]
5273 [(set_attr "type" "arith_media")
5274 (set_attr "highpart" "ignore")])
5276 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5277 ;; DImode logical shift right
5279 (define_expand "lshrdi3"
5280 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
5281 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
5282 (match_operand:DI 2 "immediate_operand" "")))
5283 (clobber (reg:SI T_REG))])]
5288 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
5290 operands[2] = GEN_INT (-INTVAL (operands[2]));
5291 emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
5294 emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
5297 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
5301 (define_insn_and_split "lshrdi3_k"
5302 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5303 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
5305 (clobber (reg:SI T_REG))]
5308 "&& reload_completed"
5311 rtx high = gen_highpart (SImode, operands[0]);
5312 rtx low = gen_lowpart (SImode, operands[0]);
5313 emit_insn (gen_shlr (high, high));
5314 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
5318 (define_insn "lshrdi3_media"
5319 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
5320 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r")
5321 (match_operand:DI 2 "shift_count_operand" "r,n")))]
5323 && (arith_reg_dest (operands[0], DImode)
5324 || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
5328 [(set_attr "type" "arith_media")])
5330 (define_insn "*lshrdisi3_media"
5331 [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0)
5332 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
5333 (match_operand:DI 2 "const_int_operand" "n")))]
5334 "TARGET_SHMEDIA && INTVAL (operands[2]) < 32"
5335 "shlri.l %1, %2, %0"
5336 [(set_attr "type" "arith_media")
5337 (set_attr "highpart" "ignore")])
5339 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5340 ;; Combined left/right shifts
5343 [(set (match_operand:SI 0 "register_operand" "")
5344 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5345 (match_operand:SI 2 "const_int_operand" ""))
5346 (match_operand:SI 3 "const_int_operand" "")))]
5347 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5348 [(use (reg:SI R0_REG))]
5350 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5356 [(set (match_operand:SI 0 "register_operand" "")
5357 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
5358 (match_operand:SI 2 "const_int_operand" ""))
5359 (match_operand:SI 3 "const_int_operand" "")))
5360 (clobber (reg:SI T_REG))]
5361 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
5362 [(use (reg:SI R0_REG))]
5364 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
5370 [(set (match_operand:SI 0 "register_operand" "=r")
5371 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5372 (match_operand:SI 2 "const_int_operand" "n"))
5373 (match_operand:SI 3 "const_int_operand" "n")))
5374 (clobber (reg:SI T_REG))]
5375 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
5377 [(set (attr "length")
5378 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5380 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5382 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5384 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
5386 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
5388 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
5390 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
5391 (const_string "16")]
5392 (const_string "18")))
5393 (set_attr "type" "arith")])
5396 [(set (match_operand:SI 0 "register_operand" "=z")
5397 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
5398 (match_operand:SI 2 "const_int_operand" "n"))
5399 (match_operand:SI 3 "const_int_operand" "n")))
5400 (clobber (reg:SI T_REG))]
5401 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
5403 [(set (attr "length")
5404 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
5406 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
5408 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
5410 (const_string "10")))
5411 (set_attr "type" "arith")])
5413 ;; shift left / and combination with a scratch register: The combine pass
5414 ;; does not accept the individual instructions, even though they are
5415 ;; cheap. But it needs a precise description so that it is usable after
5417 (define_insn "and_shl_scratch"
5418 [(set (match_operand:SI 0 "register_operand" "=r,&r")
5422 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
5423 (match_operand:SI 2 "const_int_operand" "N,n"))
5424 (match_operand:SI 3 "" "0,r"))
5425 (match_operand:SI 4 "const_int_operand" "n,n"))
5426 (match_operand:SI 5 "const_int_operand" "n,n")))
5427 (clobber (reg:SI T_REG))]
5430 [(set (attr "length")
5431 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
5433 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
5435 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
5437 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
5438 (const_string "10")]
5439 (const_string "12")))
5440 (set_attr "type" "arith")])
5443 [(set (match_operand:SI 0 "register_operand" "")
5447 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
5448 (match_operand:SI 2 "const_int_operand" ""))
5449 (match_operand:SI 3 "register_operand" ""))
5450 (match_operand:SI 4 "const_int_operand" ""))
5451 (match_operand:SI 5 "const_int_operand" "")))
5452 (clobber (reg:SI T_REG))]
5454 [(use (reg:SI R0_REG))]
5456 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
5458 if (INTVAL (operands[2]))
5460 gen_shifty_op (LSHIFTRT, operands);
5462 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
5463 operands[2] = operands[4];
5464 gen_shifty_op (ASHIFT, operands);
5465 if (INTVAL (operands[5]))
5467 operands[2] = operands[5];
5468 gen_shifty_op (LSHIFTRT, operands);
5473 ;; signed left/right shift combination.
5475 [(set (match_operand:SI 0 "register_operand" "")
5477 (ashift:SI (match_operand:SI 1 "register_operand" "")
5478 (match_operand:SI 2 "const_int_operand" ""))
5479 (match_operand:SI 3 "const_int_operand" "")
5481 (clobber (reg:SI T_REG))]
5483 [(use (reg:SI R0_REG))]
5485 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
5490 (define_insn "shl_sext_ext"
5491 [(set (match_operand:SI 0 "register_operand" "=r")
5493 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5494 (match_operand:SI 2 "const_int_operand" "n"))
5495 (match_operand:SI 3 "const_int_operand" "n")
5497 (clobber (reg:SI T_REG))]
5498 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
5500 [(set (attr "length")
5501 (cond [(match_test "shl_sext_length (insn)")
5503 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
5505 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5507 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5509 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5511 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5513 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
5515 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
5516 (const_string "16")]
5517 (const_string "18")))
5518 (set_attr "type" "arith")])
5520 (define_insn "shl_sext_sub"
5521 [(set (match_operand:SI 0 "register_operand" "=z")
5523 (ashift:SI (match_operand:SI 1 "register_operand" "0")
5524 (match_operand:SI 2 "const_int_operand" "n"))
5525 (match_operand:SI 3 "const_int_operand" "n")
5527 (clobber (reg:SI T_REG))]
5528 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
5530 [(set (attr "length")
5531 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
5533 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
5535 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
5537 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
5538 (const_string "12")]
5539 (const_string "14")))
5540 (set_attr "type" "arith")])
5542 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
5543 ;; shifts by 16, and allow the xtrct instruction to be generated from C
5545 (define_insn "xtrct_left"
5546 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5547 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5549 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
5553 [(set_attr "type" "arith")])
5555 (define_insn "xtrct_right"
5556 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5557 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
5559 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
5563 [(set_attr "type" "arith")])
5565 ;; -------------------------------------------------------------------------
5567 ;; -------------------------------------------------------------------------
5570 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5571 (neg:SI (plus:SI (reg:SI T_REG)
5572 (match_operand:SI 1 "arith_reg_operand" "r"))))
5574 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
5578 [(set_attr "type" "arith")])
5580 ;; A simplified version of the negc insn, where the exact value of the
5581 ;; T bit doesn't matter. This is easier for combine to pick up.
5582 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
5583 ;; extra patterns for this case.
5584 (define_insn "*negc"
5585 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5586 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
5587 (match_operand:SI 2 "t_reg_operand" "")))
5588 (clobber (reg:SI T_REG))]
5591 [(set_attr "type" "arith")])
5593 (define_insn "*negdi_media"
5594 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5595 (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
5598 [(set_attr "type" "arith_media")])
5600 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
5602 (define_expand "negdi2"
5603 [(parallel [(set (match_operand:DI 0 "arith_reg_dest")
5604 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5605 (clobber (reg:SI T_REG))])]
5608 (define_insn_and_split "*negdi2"
5609 [(set (match_operand:DI 0 "arith_reg_dest")
5610 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
5611 (clobber (reg:SI T_REG))]
5614 "&& can_create_pseudo_p ()"
5617 emit_insn (gen_clrt ());
5618 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5619 gen_lowpart (SImode, operands[1])));
5620 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5621 gen_highpart (SImode, operands[1])));
5625 (define_insn "negsi2"
5626 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5627 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5630 [(set_attr "type" "arith")])
5632 (define_insn_and_split "one_cmplsi2"
5633 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5634 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
5637 "&& can_create_pseudo_p ()"
5638 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
5639 (set (match_dup 0) (reg:SI T_REG))]
5642 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
5645 (set (reg0) (not:SI (reg0) (reg1)))
5646 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
5647 (clobber (reg:SI T_REG))])
5649 ... match and combine the sequence manually in the split pass after the
5650 combine pass. Notice that combine does try the target pattern of this
5651 split, but if the pattern is added it interferes with other patterns, in
5652 particular with the div0s comparisons.
5653 This could also be done with a peephole but doing it here before register
5654 allocation can save one temporary.
5655 When we're here, the not:SI pattern obviously has been matched already
5656 and we only have to see whether the following insn is the left shift. */
5658 rtx i = next_nonnote_insn_bb (curr_insn);
5659 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
5662 rtx p = PATTERN (i);
5663 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
5666 rtx p0 = XVECEXP (p, 0, 0);
5667 rtx p1 = XVECEXP (p, 0, 1);
5669 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
5670 GET_CODE (p0) == SET
5671 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
5672 && REG_P (XEXP (XEXP (p0, 1), 0))
5673 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
5674 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
5675 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
5677 /* (clobber (reg:SI T_REG)) */
5678 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
5679 && REGNO (XEXP (p1, 0)) == T_REG)
5681 operands[0] = XEXP (p0, 0);
5682 set_insn_deleted (i);
5687 [(set_attr "type" "arith")])
5689 (define_expand "one_cmpldi2"
5690 [(set (match_operand:DI 0 "arith_reg_dest" "")
5691 (xor:DI (match_operand:DI 1 "arith_reg_operand" "")
5693 "TARGET_SHMEDIA" "")
5695 (define_expand "abs<mode>2"
5696 [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest")
5697 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5698 (clobber (reg:SI T_REG))])]
5701 (define_insn_and_split "*abs<mode>2"
5702 [(set (match_operand:SIDI 0 "arith_reg_dest")
5703 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
5704 (clobber (reg:SI T_REG))]
5707 "&& can_create_pseudo_p ()"
5710 if (<MODE>mode == SImode)
5711 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5714 rtx high_src = gen_highpart (SImode, operands[1]);
5715 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5718 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5723 (define_insn_and_split "*negabs<mode>2"
5724 [(set (match_operand:SIDI 0 "arith_reg_dest")
5725 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
5726 (clobber (reg:SI T_REG))]
5729 "&& can_create_pseudo_p ()"
5732 if (<MODE>mode == SImode)
5733 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
5736 rtx high_src = gen_highpart (SImode, operands[1]);
5737 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
5740 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
5745 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
5746 ;; This can be used as some kind of conditional execution, which is useful
5748 ;; Actually the instruction scheduling should decide whether to use a
5749 ;; zero-offset branch or not for any generic case involving a single
5750 ;; instruction on SH4 202.
5751 (define_insn_and_split "negsi_cond"
5752 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
5754 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
5755 (match_operand:SI 1 "arith_reg_operand" "0,0")
5756 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
5757 "TARGET_SH1 && TARGET_ZDCBRANCH"
5759 static const char* alt[] =
5769 return alt[which_alternative];
5771 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
5774 rtx skip_neg_label = gen_label_rtx ();
5776 emit_move_insn (operands[0], operands[1]);
5778 emit_jump_insn (INTVAL (operands[3])
5779 ? gen_branch_true (skip_neg_label)
5780 : gen_branch_false (skip_neg_label));
5782 emit_label_after (skip_neg_label,
5783 emit_insn (gen_negsi2 (operands[0], operands[1])));
5786 [(set_attr "type" "arith") ;; poor approximation
5787 (set_attr "length" "4")])
5789 (define_insn_and_split "negdi_cond"
5790 [(set (match_operand:DI 0 "arith_reg_dest")
5792 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
5793 (match_operand:DI 1 "arith_reg_operand")
5794 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
5795 (clobber (reg:SI T_REG))]
5798 "&& can_create_pseudo_p ()"
5801 rtx skip_neg_label = gen_label_rtx ();
5803 emit_move_insn (operands[0], operands[1]);
5805 emit_jump_insn (INTVAL (operands[3])
5806 ? gen_branch_true (skip_neg_label)
5807 : gen_branch_false (skip_neg_label));
5809 if (!INTVAL (operands[3]))
5810 emit_insn (gen_clrt ());
5812 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
5813 gen_lowpart (SImode, operands[1])));
5814 emit_label_after (skip_neg_label,
5815 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
5816 gen_highpart (SImode, operands[1]))));
5820 (define_expand "bswapsi2"
5821 [(set (match_operand:SI 0 "arith_reg_dest" "")
5822 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
5825 if (! can_create_pseudo_p ())
5829 rtx tmp0 = gen_reg_rtx (SImode);
5830 rtx tmp1 = gen_reg_rtx (SImode);
5832 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
5833 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
5834 emit_insn (gen_swapbsi2 (operands[0], tmp1));
5839 (define_insn "swapbsi2"
5840 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5841 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
5842 (const_int 4294901760))
5843 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5845 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5846 (const_int 255)))))]
5849 [(set_attr "type" "arith")])
5851 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
5852 ;; partial byte swap expressions such as...
5853 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
5854 ;; ...which are currently not handled by the tree optimizers.
5855 ;; The combine pass will not initially try to combine the full expression,
5856 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
5857 ;; pattern acts as an intermediate pattern that will eventually lead combine
5858 ;; to the swapbsi2 pattern above.
5859 ;; As a side effect this also improves code that does (x & 0xFF) << 8
5860 ;; or (x << 8) & 0xFF00.
5861 (define_insn_and_split "*swapbisi2_and_shl8"
5862 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5863 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5866 (match_operand:SI 2 "arith_reg_operand" "r")))]
5867 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5869 "&& can_create_pseudo_p ()"
5872 rtx tmp0 = gen_reg_rtx (SImode);
5873 rtx tmp1 = gen_reg_rtx (SImode);
5875 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
5876 emit_insn (gen_swapbsi2 (tmp1, tmp0));
5877 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
5881 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
5882 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
5883 (define_insn_and_split "*swapbhisi2"
5884 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5885 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
5888 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
5889 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
5891 "&& can_create_pseudo_p ()"
5894 rtx tmp = gen_reg_rtx (SImode);
5896 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
5897 emit_insn (gen_swapbsi2 (operands[0], tmp));
5901 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
5905 ;; which can be simplified to...
5908 [(set (match_operand:SI 0 "arith_reg_dest" "")
5909 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5910 (const_int 4294901760))
5911 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5913 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5915 (set (match_operand:SI 2 "arith_reg_dest" "")
5917 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
5919 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
5920 (const_int 4294901760))
5921 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
5923 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
5924 (const_int 255)))))])
5926 ;; -------------------------------------------------------------------------
5927 ;; Zero extension instructions
5928 ;; -------------------------------------------------------------------------
5930 (define_insn "zero_extendsidi2"
5931 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
5932 (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))]
5934 "addz.l %1, r63, %0"
5935 [(set_attr "type" "arith_media")
5936 (set_attr "highpart" "extend")])
5938 (define_insn "zero_extendhidi2"
5939 [(set (match_operand:DI 0 "register_operand" "=r,r")
5940 (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
5945 [(set_attr "type" "*,load_media")
5946 (set (attr "highpart")
5947 (cond [(match_test "sh_contains_memref_p (insn)")
5948 (const_string "user")]
5949 (const_string "ignore")))])
5952 [(set (match_operand:DI 0 "register_operand" "")
5953 (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
5954 "TARGET_SHMEDIA && reload_completed"
5955 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
5956 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
5958 if (GET_CODE (operands[1]) == TRUNCATE)
5959 operands[1] = XEXP (operands[1], 0);
5962 ;; ??? when a truncated input to a zero_extend is reloaded, reload will
5963 ;; reload the entire truncate expression.
5964 (define_insn_and_split "*loaddi_trunc"
5965 [(set (match_operand 0 "any_register_operand" "=r")
5966 (truncate (match_operand:DI 1 "memory_operand" "m")))]
5967 "TARGET_SHMEDIA && reload_completed"
5969 "TARGET_SHMEDIA && reload_completed"
5970 [(set (match_dup 0) (match_dup 1))]
5972 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
5975 (define_insn "zero_extendqidi2"
5976 [(set (match_operand:DI 0 "register_operand" "=r,r")
5977 (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
5982 [(set_attr "type" "arith_media,load_media")
5983 (set (attr "highpart")
5984 (cond [(match_test "sh_contains_memref_p (insn)")
5985 (const_string "user")]
5986 (const_string "ignore")))])
5988 (define_expand "zero_extend<mode>si2"
5989 [(set (match_operand:SI 0 "arith_reg_dest")
5990 (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
5992 (define_insn_and_split "*zero_extend<mode>si2_compact"
5993 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5994 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
5997 "&& can_create_pseudo_p ()"
5998 [(set (match_dup 0) (match_dup 2))]
6000 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6001 reg with a following zero extension. In the split pass after combine,
6002 try to figure out how the extended reg was set. If it originated from
6003 the T bit we can replace the zero extension with a reg move, which will
6004 be eliminated. Notice that this also helps the *cbranch_t splitter when
6005 it tries to post-combine tests and conditional branches, as it does not
6006 check for zero extensions. */
6007 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6008 if (operands[2] == NULL_RTX)
6011 [(set_attr "type" "arith")])
6013 (define_insn "*zero_extendhisi2_media"
6014 [(set (match_operand:SI 0 "register_operand" "=r,r")
6015 (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6020 [(set_attr "type" "arith_media,load_media")
6021 (set (attr "highpart")
6022 (cond [(match_test "sh_contains_memref_p (insn)")
6023 (const_string "user")]
6024 (const_string "ignore")))])
6027 [(set (match_operand:SI 0 "register_operand" "")
6028 (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6029 "TARGET_SHMEDIA && reload_completed"
6030 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6031 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
6033 rtx op1 = operands[1];
6035 if (GET_CODE (op1) == TRUNCATE)
6036 op1 = XEXP (op1, 0);
6038 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6039 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6042 (define_insn "*zero_extendqisi2_media"
6043 [(set (match_operand:SI 0 "register_operand" "=r,r")
6044 (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6049 [(set_attr "type" "arith_media,load_media")
6050 (set (attr "highpart")
6051 (cond [(match_test "sh_contains_memref_p (insn)")
6052 (const_string "user")]
6053 (const_string "ignore")))])
6055 (define_insn "zero_extendqihi2"
6056 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6057 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6060 [(set_attr "type" "arith")])
6062 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
6063 ;; They could also be used for simple memory addresses like @Rn by setting
6064 ;; the displacement value to zero. However, doing so too early results in
6065 ;; missed opportunities for other optimizations such as post-inc or index
6066 ;; addressing loads.
6067 ;; Although the 'zero_extend_movu_operand' predicate does not allow simple
6068 ;; register addresses (an address without a displacement, index, post-inc),
6069 ;; zero-displacement addresses might be generated during reload, wich are
6070 ;; simplified to simple register addresses in turn. Thus, we have to
6071 ;; provide the Sdd and Sra alternatives in the patterns.
6072 (define_insn "*zero_extend<mode>si2_disp_mem"
6073 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
6075 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
6079 movu.<bw> @(0,%t1),%0"
6080 [(set_attr "type" "load")
6081 (set_attr "length" "4")])
6083 ;; Convert the zero extending loads in sequences such as:
6084 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
6085 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6087 ;; back to sign extending loads like:
6088 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
6089 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
6091 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
6092 ;; is only 2 bytes in size if the displacement is {K04|K05}.
6093 ;; If the displacement is greater it doesn't matter, so we convert anyways.
6095 [(set (match_operand:SI 0 "arith_reg_dest" "")
6096 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
6097 (set (match_operand 2 "nonimmediate_operand" "")
6098 (match_operand 3 "arith_reg_operand" ""))]
6100 && REGNO (operands[0]) == REGNO (operands[3])
6101 && peep2_reg_dead_p (2, operands[0])
6102 && GET_MODE_SIZE (GET_MODE (operands[2]))
6103 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
6104 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
6105 (set (match_dup 2) (match_dup 3))])
6107 ;; Fold sequences such as
6111 ;; movu.b @(0,r3),r7
6112 ;; This does not reduce the code size but the number of instructions is
6113 ;; halved, which results in faster code.
6115 [(set (match_operand:SI 0 "arith_reg_dest" "")
6116 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
6117 (set (match_operand:SI 2 "arith_reg_dest" "")
6118 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
6120 && GET_MODE (operands[1]) == GET_MODE (operands[3])
6121 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
6122 && REGNO (operands[0]) == REGNO (operands[3])
6123 && (REGNO (operands[2]) == REGNO (operands[0])
6124 || peep2_reg_dead_p (2, operands[0]))"
6125 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
6128 = replace_equiv_address (operands[1],
6129 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
6133 ;; -------------------------------------------------------------------------
6134 ;; Sign extension instructions
6135 ;; -------------------------------------------------------------------------
6137 ;; ??? This should be a define expand.
6138 ;; ??? Or perhaps it should be dropped?
6140 ;; convert_move generates good code for SH[1-4].
6141 (define_insn "extendsidi2"
6142 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6143 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))]
6149 [(set_attr "type" "arith_media,load_media,fpconv_media")
6150 (set (attr "highpart")
6151 (cond [(match_test "sh_contains_memref_p (insn)")
6152 (const_string "user")]
6153 (const_string "extend")))])
6155 (define_insn "extendhidi2"
6156 [(set (match_operand:DI 0 "register_operand" "=r,r")
6157 (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6162 [(set_attr "type" "*,load_media")
6163 (set (attr "highpart")
6164 (cond [(match_test "sh_contains_memref_p (insn)")
6165 (const_string "user")]
6166 (const_string "ignore")))])
6169 [(set (match_operand:DI 0 "register_operand" "")
6170 (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
6171 "TARGET_SHMEDIA && reload_completed"
6172 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
6173 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
6175 if (GET_CODE (operands[1]) == TRUNCATE)
6176 operands[1] = XEXP (operands[1], 0);
6179 (define_insn "extendqidi2"
6180 [(set (match_operand:DI 0 "register_operand" "=r,r")
6181 (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6186 [(set_attr "type" "*,load_media")
6187 (set (attr "highpart")
6188 (cond [(match_test "sh_contains_memref_p (insn)")
6189 (const_string "user")]
6190 (const_string "ignore")))])
6193 [(set (match_operand:DI 0 "register_operand" "")
6194 (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
6195 "TARGET_SHMEDIA && reload_completed"
6196 [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
6197 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
6199 if (GET_CODE (operands[1]) == TRUNCATE)
6200 operands[1] = XEXP (operands[1], 0);
6203 (define_expand "extend<mode>si2"
6204 [(set (match_operand:SI 0 "arith_reg_dest")
6205 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
6207 (define_insn "*extendhisi2_media"
6208 [(set (match_operand:SI 0 "register_operand" "=r,r")
6209 (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))]
6214 [(set_attr "type" "arith_media,load_media")
6215 (set (attr "highpart")
6216 (cond [(match_test "sh_contains_memref_p (insn)")
6217 (const_string "user")]
6218 (const_string "ignore")))])
6221 [(set (match_operand:SI 0 "register_operand" "")
6222 (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
6223 "TARGET_SHMEDIA && reload_completed"
6224 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
6225 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
6227 rtx op1 = operands[1];
6228 if (GET_CODE (op1) == TRUNCATE)
6229 op1 = XEXP (op1, 0);
6231 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6232 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6235 (define_insn_and_split "*extend<mode>si2_compact_reg"
6236 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6237 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
6240 "&& can_create_pseudo_p ()"
6241 [(set (match_dup 0) (match_dup 2))]
6243 /* Sometimes combine fails to combine a T bit or negated T bit store to a
6244 reg with a following sign extension. In the split pass after combine,
6245 try to figure the extended reg was set. If it originated from the T
6246 bit we can replace the sign extension with a reg move, which will be
6248 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
6249 if (operands[2] == NULL_RTX)
6252 [(set_attr "type" "arith")])
6254 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
6256 (define_insn "*extend<mode>si2_compact_mem_disp"
6257 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
6261 (match_operand:SI 1 "arith_reg_operand" "%r,r")
6262 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
6263 "TARGET_SH1 && ! TARGET_SH2A
6264 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
6266 mov.<bw> @(%O2,%1),%0
6268 [(set_attr "type" "load")])
6270 (define_insn "*extend<mode>si2_compact_mem_disp"
6271 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
6275 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
6276 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
6277 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
6279 mov.<bw> @(%O2,%1),%0
6281 mov.<bw> @(%O2,%1),%0"
6282 [(set_attr "type" "load")
6283 (set_attr "length" "2,2,4")])
6285 ;; The *_snd patterns will take care of other QImode/HImode addressing
6286 ;; modes than displacement addressing. They must be defined _after_ the
6287 ;; displacement addressing patterns. Otherwise the displacement addressing
6288 ;; patterns will not be picked.
6289 (define_insn "*extend<mode>si2_compact_snd"
6290 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6292 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
6295 [(set_attr "type" "load")])
6297 (define_insn "*extendqisi2_media"
6298 [(set (match_operand:SI 0 "register_operand" "=r,r")
6299 (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))]
6304 [(set_attr "type" "arith_media,load_media")
6305 (set (attr "highpart")
6306 (cond [(match_test "sh_contains_memref_p (insn)")
6307 (const_string "user")]
6308 (const_string "ignore")))])
6311 [(set (match_operand:SI 0 "register_operand" "")
6312 (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
6313 "TARGET_SHMEDIA && reload_completed"
6314 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24)))
6315 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
6317 rtx op1 = operands[1];
6318 if (GET_CODE (op1) == TRUNCATE)
6319 op1 = XEXP (op1, 0);
6321 = simplify_gen_subreg (SImode, op1, GET_MODE (op1),
6322 subreg_lowpart_offset (SImode, GET_MODE (op1)));
6325 (define_expand "extendqihi2"
6326 [(set (match_operand:HI 0 "arith_reg_dest")
6327 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
6330 (define_insn "*extendqihi2_compact_reg"
6331 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
6332 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
6335 [(set_attr "type" "arith")])
6337 ;; It would seem useful to combine the truncXi patterns into the movXi
6338 ;; patterns, but unary operators are ignored when matching constraints,
6339 ;; so we need separate patterns.
6340 (define_insn "truncdisi2"
6341 [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f")
6342 (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))]
6351 [(set_attr "type" "arith_media,store_media,fstore_media,fload_media,
6352 fpconv_media,fmove_media")
6353 (set (attr "highpart")
6354 (cond [(match_test "sh_contains_memref_p (insn)")
6355 (const_string "user")]
6356 (const_string "extend")))])
6358 (define_insn "truncdihi2"
6359 [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m")
6360 (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))]
6363 static const char* alt[] =
6365 "shlli %1,48,%0" "\n"
6370 return alt[which_alternative];
6372 [(set_attr "type" "arith_media,store_media")
6373 (set_attr "length" "8,4")
6374 (set (attr "highpart")
6375 (cond [(match_test "sh_contains_memref_p (insn)")
6376 (const_string "user")]
6377 (const_string "extend")))])
6379 ; N.B. This should agree with LOAD_EXTEND_OP and movqi.
6380 ; Because we use zero extension, we can't provide signed QImode compares
6381 ; using a simple compare or conditional branch insn.
6382 (define_insn "truncdiqi2"
6383 [(set (match_operand:QI 0 "general_movdst_operand" "=r,m")
6384 (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))]
6389 [(set_attr "type" "arith_media,store")
6390 (set (attr "highpart")
6391 (cond [(match_test "sh_contains_memref_p (insn)")
6392 (const_string "user")]
6393 (const_string "extend")))])
6395 ;; -------------------------------------------------------------------------
6396 ;; Move instructions
6397 ;; -------------------------------------------------------------------------
6399 ;; define push and pop so it is easy for sh.c
6400 ;; We can't use push and pop on SHcompact because the stack must always
6401 ;; be 8-byte aligned.
6402 (define_expand "push"
6403 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6404 (match_operand:SI 0 "register_operand" "r,l,x"))]
6405 "TARGET_SH1 && ! TARGET_SH5"
6408 (define_expand "pop"
6409 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
6410 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
6411 "TARGET_SH1 && ! TARGET_SH5"
6414 (define_expand "push_e"
6415 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
6416 (match_operand:SF 0 "" ""))
6417 (use (reg:SI FPSCR_MODES_REG))
6418 (clobber (scratch:SI))])]
6419 "TARGET_SH1 && ! TARGET_SH5"
6422 (define_insn "push_fpul"
6423 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
6424 "TARGET_SH2E && ! TARGET_SH5"
6426 [(set_attr "type" "fstore")
6427 (set_attr "late_fp_use" "yes")
6428 (set_attr "hit_stack" "yes")])
6430 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
6432 (define_expand "push_4"
6433 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
6434 (match_operand:DF 0 "" ""))
6435 (use (reg:SI FPSCR_MODES_REG))
6436 (clobber (scratch:SI))])]
6437 "TARGET_SH1 && ! TARGET_SH5"
6440 (define_expand "pop_e"
6441 [(parallel [(set (match_operand:SF 0 "" "")
6442 (mem:SF (post_inc:SI (reg:SI SP_REG))))
6443 (use (reg:SI FPSCR_MODES_REG))
6444 (clobber (scratch:SI))])]
6445 "TARGET_SH1 && ! TARGET_SH5"
6448 (define_insn "pop_fpul"
6449 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
6450 "TARGET_SH2E && ! TARGET_SH5"
6452 [(set_attr "type" "load")
6453 (set_attr "hit_stack" "yes")])
6455 (define_expand "pop_4"
6456 [(parallel [(set (match_operand:DF 0 "" "")
6457 (mem:DF (post_inc:SI (reg:SI SP_REG))))
6458 (use (reg:SI FPSCR_MODES_REG))
6459 (clobber (scratch:SI))])]
6460 "TARGET_SH1 && ! TARGET_SH5"
6463 (define_expand "push_fpscr"
6470 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
6471 REG_INC, stack_pointer_rtx);
6475 (define_expand "pop_fpscr"
6482 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
6483 REG_INC, stack_pointer_rtx);
6487 ;; The clrt and sett patterns can happen as the result of optimization and
6489 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
6490 ;; In this case they might not disappear completely, because the T reg is
6491 ;; a fixed hard reg.
6492 ;; When DImode operations that use the T reg as carry/borrow are split into
6493 ;; individual SImode operations, the T reg is usually cleared before the
6494 ;; first SImode insn.
6496 [(set (reg:SI T_REG) (const_int 0))]
6499 [(set_attr "type" "mt_group")])
6502 [(set (reg:SI T_REG) (const_int 1))]
6505 [(set_attr "type" "mt_group")])
6507 ;; Use the combine pass to transform sequences such as
6511 ;; mov.l @(r0,r4),r0
6517 ;; See also PR 39423.
6518 ;; Notice that these patterns have a T_REG clobber, because the shift
6519 ;; sequence that will be split out might clobber the T_REG. Ideally, the
6520 ;; clobber would be added conditionally, depending on the result of
6521 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
6522 ;; through the ashlsi3 expander in order to get the right shift insn --
6523 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
6524 ;; FIXME: Combine never tries this kind of patterns for DImode.
6525 (define_insn_and_split "*movsi_index_disp_load"
6526 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
6527 (match_operand:SI 1 "mem_index_disp_operand" "m"))
6528 (clobber (reg:SI T_REG))]
6531 "&& can_create_pseudo_p ()"
6532 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6533 (set (match_dup 0) (match_dup 7))]
6535 rtx mem = operands[1];
6536 rtx plus0_rtx = XEXP (mem, 0);
6537 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6538 rtx mult_rtx = XEXP (plus1_rtx, 0);
6540 operands[1] = XEXP (mult_rtx, 0);
6541 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6542 operands[3] = XEXP (plus1_rtx, 1);
6543 operands[4] = XEXP (plus0_rtx, 1);
6544 operands[5] = gen_reg_rtx (SImode);
6545 operands[6] = gen_reg_rtx (SImode);
6547 replace_equiv_address (mem,
6548 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6550 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
6553 (define_insn_and_split "*movhi_index_disp_load"
6554 [(set (match_operand:SI 0 "arith_reg_dest")
6555 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
6556 (clobber (reg:SI T_REG))]
6559 "&& can_create_pseudo_p ()"
6562 rtx mem = operands[1];
6563 rtx plus0_rtx = XEXP (mem, 0);
6564 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6565 rtx mult_rtx = XEXP (plus1_rtx, 0);
6567 rtx op_1 = XEXP (mult_rtx, 0);
6568 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6569 rtx op_3 = XEXP (plus1_rtx, 1);
6570 rtx op_4 = XEXP (plus0_rtx, 1);
6571 rtx op_5 = gen_reg_rtx (SImode);
6572 rtx op_6 = gen_reg_rtx (SImode);
6573 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
6575 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
6576 emit_insn (gen_addsi3 (op_6, op_5, op_3));
6578 if (<CODE> == SIGN_EXTEND)
6580 emit_insn (gen_extendhisi2 (operands[0], op_7));
6583 else if (<CODE> == ZERO_EXTEND)
6585 /* On SH2A the movu.w insn can be used for zero extending loads. */
6587 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
6590 emit_insn (gen_extendhisi2 (operands[0], op_7));
6591 emit_insn (gen_zero_extendhisi2 (operands[0],
6592 gen_lowpart (HImode, operands[0])));
6600 (define_insn_and_split "*mov<mode>_index_disp_store"
6601 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
6602 (match_operand:HISI 1 "arith_reg_operand" "r"))
6603 (clobber (reg:SI T_REG))]
6606 "&& can_create_pseudo_p ()"
6607 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
6608 (set (match_dup 7) (match_dup 1))]
6610 rtx mem = operands[0];
6611 rtx plus0_rtx = XEXP (mem, 0);
6612 rtx plus1_rtx = XEXP (plus0_rtx, 0);
6613 rtx mult_rtx = XEXP (plus1_rtx, 0);
6615 operands[0] = XEXP (mult_rtx, 0);
6616 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
6617 operands[3] = XEXP (plus1_rtx, 1);
6618 operands[4] = XEXP (plus0_rtx, 1);
6619 operands[5] = gen_reg_rtx (SImode);
6620 operands[6] = gen_reg_rtx (SImode);
6622 replace_equiv_address (mem,
6623 gen_rtx_PLUS (SImode, operands[6], operands[4]));
6625 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
6628 ;; t/r must come after r/r, lest reload will try to reload stuff like
6629 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
6630 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
6631 (define_insn "movsi_i"
6632 [(set (match_operand:SI 0 "general_movdst_operand"
6633 "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
6634 (match_operand:SI 1 "general_movsrc_operand"
6635 "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
6639 && (register_operand (operands[0], SImode)
6640 || register_operand (operands[1], SImode))"
6656 [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,
6657 pstore,gp_mac,prset,mem_mac,pload,pcload_si")
6658 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
6660 ;; t/r must come after r/r, lest reload will try to reload stuff like
6661 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
6662 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
6663 ;; will require a reload.
6664 ;; ??? We can't include f/f because we need the proper FPSCR setting when
6665 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
6666 (define_insn "movsi_ie"
6667 [(set (match_operand:SI 0 "general_movdst_operand"
6668 "=r,r,r,r,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
6669 (match_operand:SI 1 "general_movsrc_operand"
6670 "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
6671 "(TARGET_SH2E || TARGET_SH2A)
6672 && ((register_operand (operands[0], SImode)
6673 && !fpscr_operand (operands[0], SImode))
6674 || (register_operand (operands[1], SImode)
6675 && !fpscr_operand (operands[1], SImode)))"
6700 ! move optimized away"
6701 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
6702 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
6703 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
6704 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
6705 (set_attr_alternative "length"
6712 (match_test "TARGET_SH2A")
6713 (const_int 4) (const_int 2))
6717 (match_test "TARGET_SH2A")
6718 (const_int 4) (const_int 2))
6735 (define_insn "movsi_i_lowpart"
6736 [(set (strict_low_part
6737 (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
6738 (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
6740 && (register_operand (operands[0], SImode)
6741 || register_operand (operands[1], SImode))"
6751 [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
6753 (define_insn_and_split "load_ra"
6754 [(set (match_operand:SI 0 "general_movdst_operand" "")
6755 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
6758 "&& ! currently_expanding_to_rtl"
6759 [(set (match_dup 0) (match_dup 1))]
6761 if (TARGET_SHCOMPACT && crtl->saves_all_registers)
6762 operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx);
6765 ;; The '?'s in the following constraints may not reflect the time taken
6766 ;; to perform the move. They are there to discourage the use of floating-
6767 ;; point registers for storing integer values.
6768 (define_insn "*movsi_media"
6769 [(set (match_operand:SI 0 "general_movdst_operand"
6770 "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b")
6771 (match_operand:SI 1 "general_movsrc_operand"
6772 "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
6774 && (register_operand (operands[0], SImode)
6775 || sh_register_operand (operands[1], SImode)
6776 || GET_CODE (operands[1]) == TRUNCATE)"
6791 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6792 fload_media,fstore_media,fload_media,fpconv_media,
6793 fmove_media,ptabs_media,gettr_media,pt_media")
6794 (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12")
6795 (set (attr "highpart")
6796 (cond [(match_test "sh_contains_memref_p (insn)")
6797 (const_string "user")]
6798 (const_string "ignore")))])
6800 (define_insn "*movsi_media_nofpu"
6801 [(set (match_operand:SI 0 "general_movdst_operand"
6802 "=r,r,r,r,m,*b,r,*b")
6803 (match_operand:SI 1 "general_movsrc_operand"
6804 "r,I16Css,nCpg,m,rZ,r,*b,Csy"))]
6806 && (register_operand (operands[0], SImode)
6807 || sh_register_operand (operands[1], SImode)
6808 || GET_CODE (operands[1]) == TRUNCATE)"
6818 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
6819 ptabs_media,gettr_media,pt_media")
6820 (set_attr "length" "4,4,8,4,4,4,4,12")
6821 (set (attr "highpart")
6822 (cond [(match_test "sh_contains_memref_p (insn)")
6823 (const_string "user")]
6824 (const_string "ignore")))])
6826 (define_expand "movsi_const"
6827 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6828 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6829 (const_int 16)] UNSPEC_EXTRACT_S16)))
6831 (ior:SI (ashift:SI (match_dup 0) (const_int 16))
6832 (const:SI (unspec:SI [(match_dup 1)
6833 (const_int 0)] UNSPEC_EXTRACT_U16))))]
6834 "TARGET_SHMEDIA && reload_completed
6835 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6837 if (GET_CODE (operands[1]) == LABEL_REF
6838 && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
6839 LABEL_NUSES (XEXP (operands[1], 0)) += 2;
6840 else if (GOTOFF_P (operands[1]))
6842 rtx unspec = XEXP (operands[1], 0);
6844 if (! UNSPEC_GOTOFF_P (unspec))
6846 unspec = XEXP (unspec, 0);
6847 if (! UNSPEC_GOTOFF_P (unspec))
6850 if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF
6851 && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL))
6852 LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2;
6856 (define_expand "movsi_const_16bit"
6857 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
6858 (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s")
6859 (const_int 0)] UNSPEC_EXTRACT_S16)))]
6860 "TARGET_SHMEDIA && flag_pic && reload_completed
6861 && GET_CODE (operands[1]) == SYMBOL_REF"
6865 [(set (match_operand:SI 0 "arith_reg_dest" "")
6866 (match_operand:SI 1 "immediate_operand" ""))]
6867 "TARGET_SHMEDIA && reload_completed
6868 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
6871 rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1]));
6873 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
6879 [(set (match_operand:SI 0 "register_operand" "")
6880 (match_operand:SI 1 "immediate_operand" ""))]
6881 "TARGET_SHMEDIA && reload_completed
6882 && ((CONST_INT_P (operands[1])
6883 && ! satisfies_constraint_I16 (operands[1]))
6884 || GET_CODE (operands[1]) == CONST_DOUBLE)"
6885 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
6887 (define_expand "movsi"
6888 [(set (match_operand:SI 0 "general_movdst_operand" "")
6889 (match_operand:SI 1 "general_movsrc_operand" ""))]
6892 prepare_move_operands (operands, SImode);
6895 (define_expand "ic_invalidate_line"
6896 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
6897 (match_dup 1)] UNSPEC_ICACHE)
6898 (clobber (scratch:SI))])]
6899 "TARGET_HARD_SH4 || TARGET_SH5"
6903 emit_insn (gen_ic_invalidate_line_media (operands[0]));
6906 else if (TARGET_SHCOMPACT)
6908 operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
6909 operands[1] = force_reg (Pmode, operands[1]);
6910 emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
6913 else if (TARGET_SH4A || TARGET_SH4_300)
6915 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
6918 operands[0] = force_reg (Pmode, operands[0]);
6919 operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008,
6923 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
6924 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
6925 ;; the requirement *1*00 for associative address writes. The alignment of
6926 ;; %0 implies that its least significant bit is cleared,
6927 ;; thus we clear the V bit of a matching entry if there is one.
6928 (define_insn "ic_invalidate_line_i"
6929 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
6930 (match_operand:SI 1 "register_operand" "r")]
6932 (clobber (match_scratch:SI 2 "=&r"))]
6935 return "ocbwb @%0" "\n"
6936 " extu.w %0,%2" "\n"
6940 [(set_attr "length" "8")
6941 (set_attr "type" "cwb")])
6943 (define_insn "ic_invalidate_line_sh4a"
6944 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
6946 "TARGET_SH4A || TARGET_SH4_300"
6948 return "ocbwb @%0" "\n"
6952 [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo.
6953 (set_attr "type" "cwb")])
6955 ;; ??? could make arg 0 an offsettable memory operand to allow to save
6956 ;; an add in the code that calculates the address.
6957 (define_insn "ic_invalidate_line_media"
6958 [(unspec_volatile [(match_operand 0 "any_register_operand" "r")]
6962 return "ocbwb %0,0" "\n"
6967 [(set_attr "length" "16")
6968 (set_attr "type" "invalidate_line_media")])
6970 (define_insn "ic_invalidate_line_compact"
6971 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
6972 (match_operand:SI 1 "register_operand" "r")]
6974 (clobber (reg:SI PR_REG))]
6977 [(set_attr "type" "sfunc")
6978 (set_attr "needs_delay_slot" "yes")])
6980 (define_expand "initialize_trampoline"
6981 [(match_operand:SI 0 "" "")
6982 (match_operand:SI 1 "" "")
6983 (match_operand:SI 2 "" "")]
6988 tramp = force_reg (Pmode, operands[0]);
6989 sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
6991 emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
6992 emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
6994 emit_insn (gen_initialize_trampoline_compact (tramp, sfun));
6998 (define_insn "initialize_trampoline_compact"
6999 [(unspec_volatile [(match_operand:SI 0 "register_operand" "z")
7000 (match_operand:SI 1 "register_operand" "r")
7001 (reg:SI R2_REG) (reg:SI R3_REG)]
7004 (clobber (reg:SI PR_REG))]
7007 [(set_attr "type" "sfunc")
7008 (set_attr "needs_delay_slot" "yes")])
7010 (define_expand "mov<mode>"
7011 [(set (match_operand:QIHI 0 "general_movdst_operand")
7012 (match_operand:QIHI 1 "general_movsrc_operand"))]
7015 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
7016 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
7018 rtx reg = gen_reg_rtx(SImode);
7019 emit_move_insn (reg, operands[1]);
7020 operands[1] = gen_lowpart (<MODE>mode, reg);
7023 prepare_move_operands (operands, <MODE>mode);
7026 ;; Specifying the displacement addressing load / store patterns separately
7027 ;; before the generic movqi / movhi pattern allows controlling the order
7028 ;; in which load / store insns are selected in a more fine grained way.
7029 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
7030 ;; "enabled" attribute as it is done in other targets.
7031 (define_insn "*mov<mode>_store_mem_disp04"
7033 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
7034 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
7035 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
7036 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
7038 mov.<bw> %2,@(%O1,%0)
7040 [(set_attr "type" "store")])
7042 (define_insn "*mov<mode>_store_mem_disp12"
7044 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
7045 (match_operand:SI 1 "const_int_operand" "<disp12>")))
7046 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
7047 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
7048 "mov.<bw> %2,@(%O1,%0)"
7049 [(set_attr "type" "store")
7050 (set_attr "length" "4")])
7052 (define_insn "*mov<mode>_load_mem_disp04"
7053 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
7055 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
7056 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
7057 "TARGET_SH1 && ! TARGET_SH2A
7058 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
7060 mov.<bw> @(%O2,%1),%0
7062 [(set_attr "type" "load")])
7064 (define_insn "*mov<mode>_load_mem_disp12"
7065 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
7068 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
7069 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
7070 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
7072 mov.<bw> @(%O2,%1),%0
7074 mov.<bw> @(%O2,%1),%0"
7075 [(set_attr "type" "load")
7076 (set_attr "length" "2,2,4")])
7078 ;; The order of the constraint alternatives is important here.
7079 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
7080 ;; placed into delay slots. Since there is no QImode PC relative load, the
7081 ;; Q constraint and general_movsrc_operand will reject it for QImode.
7082 ;; The Snd alternatives should come before Sdd in order to avoid a preference
7083 ;; of using r0 als the register operand for addressing modes other than
7084 ;; displacement addressing.
7085 ;; The Sdd alternatives allow only r0 as register operand, even though on
7086 ;; SH2A any register could be allowed by switching to a 32 bit insn.
7087 ;; Generally sticking to the r0 is preferrable, since it generates smaller
7088 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
7089 (define_insn "*mov<mode>"
7090 [(set (match_operand:QIHI 0 "general_movdst_operand"
7091 "=r,r,r,Snd,r, Sdd,z, r,l")
7092 (match_operand:QIHI 1 "general_movsrc_operand"
7093 "Q,r,i,r, Snd,z, Sdd,l,r"))]
7095 && (arith_reg_operand (operands[0], <MODE>mode)
7096 || arith_reg_operand (operands[1], <MODE>mode))"
7107 [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
7108 (set (attr "length")
7109 (cond [(and (match_operand 0 "displacement_mem_operand")
7110 (not (match_operand 0 "short_displacement_mem_operand")))
7112 (and (match_operand 1 "displacement_mem_operand")
7113 (not (match_operand 1 "short_displacement_mem_operand")))
7117 (define_insn "*movqi_media"
7118 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
7119 (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))]
7121 && (arith_reg_operand (operands[0], QImode)
7122 || extend_reg_or_0_operand (operands[1], QImode))"
7128 [(set_attr "type" "arith_media,arith_media,load_media,store_media")
7129 (set (attr "highpart")
7130 (cond [(match_test "sh_contains_memref_p (insn)")
7131 (const_string "user")]
7132 (const_string "ignore")))])
7134 (define_expand "reload_inqi"
7135 [(set (match_operand:SI 2 "" "=&r")
7136 (match_operand:QI 1 "inqhi_operand" ""))
7137 (set (match_operand:QI 0 "arith_reg_operand" "=r")
7138 (truncate:QI (match_dup 3)))]
7141 rtx inner = XEXP (operands[1], 0);
7142 int regno = REGNO (inner);
7144 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7145 operands[1] = gen_rtx_REG (SImode, regno);
7146 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7149 (define_insn "*movhi_media"
7150 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
7151 (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))]
7153 && (arith_reg_operand (operands[0], HImode)
7154 || arith_reg_or_0_operand (operands[1], HImode))"
7161 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
7162 (set (attr "highpart")
7163 (cond [(match_test "sh_contains_memref_p (insn)")
7164 (const_string "user")]
7165 (const_string "ignore")))])
7168 [(set (match_operand:HI 0 "register_operand" "")
7169 (match_operand:HI 1 "immediate_operand" ""))]
7170 "TARGET_SHMEDIA && reload_completed
7171 && ! satisfies_constraint_I16 (operands[1])"
7172 [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
7174 (define_expand "reload_inhi"
7175 [(set (match_operand:SI 2 "" "=&r")
7176 (match_operand:HI 1 "inqhi_operand" ""))
7177 (set (match_operand:HI 0 "arith_reg_operand" "=r")
7178 (truncate:HI (match_dup 3)))]
7181 rtx inner = XEXP (operands[1], 0);
7182 int regno = REGNO (inner);
7184 regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1;
7185 operands[1] = gen_rtx_REG (SImode, regno);
7186 operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
7189 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
7190 ;; compiled with -m2 -ml -O3 -funroll-loops
7191 (define_insn "*movdi_i"
7192 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
7193 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I08,i,x,r"))]
7195 && (arith_reg_operand (operands[0], DImode)
7196 || arith_reg_operand (operands[1], DImode))"
7198 return output_movedouble (insn, operands, DImode);
7200 [(set_attr "length" "4")
7201 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
7203 ;; If the output is a register and the input is memory or a register, we have
7204 ;; to be careful and see which word needs to be loaded first.
7206 [(set (match_operand:DI 0 "general_movdst_operand" "")
7207 (match_operand:DI 1 "general_movsrc_operand" ""))]
7208 "TARGET_SH1 && reload_completed"
7209 [(set (match_dup 2) (match_dup 3))
7210 (set (match_dup 4) (match_dup 5))]
7214 if ((MEM_P (operands[0])
7215 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
7216 || (MEM_P (operands[1])
7217 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
7220 switch (GET_CODE (operands[0]))
7223 regno = REGNO (operands[0]);
7226 regno = subreg_regno (operands[0]);
7236 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
7238 operands[2] = operand_subword (operands[0], 0, 0, DImode);
7239 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7240 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7241 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7245 operands[2] = operand_subword (operands[0], 1, 0, DImode);
7246 operands[3] = operand_subword (operands[1], 1, 0, DImode);
7247 operands[4] = operand_subword (operands[0], 0, 0, DImode);
7248 operands[5] = operand_subword (operands[1], 0, 0, DImode);
7251 if (operands[2] == 0 || operands[3] == 0
7252 || operands[4] == 0 || operands[5] == 0)
7256 ;; The '?'s in the following constraints may not reflect the time taken
7257 ;; to perform the move. They are there to discourage the use of floating-
7258 ;; point registers for storing integer values.
7259 (define_insn "*movdi_media"
7260 [(set (match_operand:DI 0 "general_movdst_operand"
7261 "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b")
7262 (match_operand:DI 1 "general_movsrc_operand"
7263 "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))]
7265 && (register_operand (operands[0], DImode)
7266 || sh_register_operand (operands[1], DImode))"
7281 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7282 fload_media,fstore_media,fload_media,dfpconv_media,
7283 fmove_media,ptabs_media,gettr_media,pt_media")
7284 (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")])
7286 (define_insn "*movdi_media_nofpu"
7287 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b");
7288 (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))]
7290 && (register_operand (operands[0], DImode)
7291 || sh_register_operand (operands[1], DImode))"
7301 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media,
7302 ptabs_media,gettr_media,pt_media")
7303 (set_attr "length" "4,4,16,4,4,4,4,*")])
7305 (define_insn "*movdi_media_I16"
7306 [(set (match_operand:DI 0 "ext_dest_operand" "=r")
7307 (match_operand:DI 1 "const_int_operand" "I16"))]
7308 "TARGET_SHMEDIA && reload_completed"
7310 [(set_attr "type" "arith_media")
7311 (set_attr "length" "4")])
7314 [(set (match_operand:DI 0 "arith_reg_dest" "")
7315 (match_operand:DI 1 "immediate_operand" ""))]
7316 "TARGET_SHMEDIA && reload_completed
7317 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7318 [(set (match_dup 0) (match_dup 1))]
7322 if (TARGET_SHMEDIA64)
7323 insn = emit_insn (gen_movdi_const (operands[0], operands[1]));
7325 insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1]));
7327 set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1]));
7332 (define_expand "movdi_const"
7333 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7334 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7335 (const_int 48)] UNSPEC_EXTRACT_S16)))
7337 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7338 (const:DI (unspec:DI [(match_dup 1)
7339 (const_int 32)] UNSPEC_EXTRACT_U16))))
7341 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7342 (const:DI (unspec:DI [(match_dup 1)
7343 (const_int 16)] UNSPEC_EXTRACT_U16))))
7345 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7346 (const:DI (unspec:DI [(match_dup 1)
7347 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7348 "TARGET_SHMEDIA64 && reload_completed
7349 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7351 sh_mark_label (operands[1], 4);
7354 (define_expand "movdi_const_32bit"
7355 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7356 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7357 (const_int 16)] UNSPEC_EXTRACT_S16)))
7359 (ior:DI (ashift:DI (match_dup 0) (const_int 16))
7360 (const:DI (unspec:DI [(match_dup 1)
7361 (const_int 0)] UNSPEC_EXTRACT_U16))))]
7362 "TARGET_SHMEDIA32 && reload_completed
7363 && MOVI_SHORI_BASE_OPERAND_P (operands[1])"
7365 sh_mark_label (operands[1], 2);
7368 (define_expand "movdi_const_16bit"
7369 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
7370 (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")
7371 (const_int 0)] UNSPEC_EXTRACT_S16)))]
7372 "TARGET_SHMEDIA && flag_pic && reload_completed
7373 && GET_CODE (operands[1]) == SYMBOL_REF"
7377 [(set (match_operand:DI 0 "ext_dest_operand" "")
7378 (match_operand:DI 1 "immediate_operand" ""))]
7379 "TARGET_SHMEDIA && reload_completed
7380 && CONST_INT_P (operands[1])
7381 && ! satisfies_constraint_I16 (operands[1])"
7382 [(set (match_dup 0) (match_dup 2))
7385 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
7386 unsigned HOST_WIDE_INT low = val;
7387 unsigned HOST_WIDE_INT high = val;
7388 unsigned HOST_WIDE_INT sign;
7389 unsigned HOST_WIDE_INT val2 = val ^ (val-1);
7391 /* Zero-extend the 16 least-significant bits. */
7394 /* Arithmetic shift right the word by 16 bits. */
7396 if (GET_CODE (operands[0]) == SUBREG
7397 && GET_MODE (SUBREG_REG (operands[0])) == SImode)
7406 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7412 /* If we can't generate the constant with a two-insn movi / shori
7413 sequence, try some other strategies. */
7414 if (! CONST_OK_FOR_I16 (high))
7416 /* Try constant load / left shift. We know VAL != 0. */
7417 val2 = val ^ (val-1);
7420 int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15;
7422 if (CONST_OK_FOR_I16 (val >> trailing_zeroes)
7423 || (! CONST_OK_FOR_I16 (high >> 16)
7424 && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16))))
7426 val2 = (HOST_WIDE_INT) val >> trailing_zeroes;
7427 operands[1] = gen_ashldi3_media (operands[0], operands[0],
7428 GEN_INT (trailing_zeroes));
7432 /* Try constant load / right shift. */
7433 val2 = (val >> 15) + 1;
7434 if (val2 == (val2 & -val2))
7436 int shift = 49 - exact_log2 (val2);
7438 val2 = trunc_int_for_mode (val << shift, DImode);
7439 if (CONST_OK_FOR_I16 (val2))
7441 operands[1] = gen_lshrdi3_media (operands[0], operands[0],
7447 val2 = val & 0xffff;
7448 if ((val >> 16 & 0xffff) == val2
7449 && (val >> 32 & 0xffff) == val2
7450 && (val >> 48 & 0xffff) == val2)
7452 val2 = (HOST_WIDE_INT) val >> 48;
7453 operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
7454 operands[1] = gen_mperm_w0 (operands[1], operands[1]);
7457 /* Try movi / mshflo.l */
7458 val2 = (HOST_WIDE_INT) val >> 32;
7459 if (val2 == ((unsigned HOST_WIDE_INT)
7460 trunc_int_for_mode (val, SImode)))
7462 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7466 /* Try movi / mshflo.l w/ r63. */
7467 val2 = val + ((HOST_WIDE_INT) -1 << 32);
7468 if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2))
7470 operands[1] = gen_mshflo_l_di (operands[0], operands[0],
7476 operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low));
7479 operands[2] = GEN_INT (val2);
7483 [(set (match_operand:DI 0 "ext_dest_operand" "")
7484 (match_operand:DI 1 "immediate_operand" ""))]
7485 "TARGET_SHMEDIA && reload_completed
7486 && GET_CODE (operands[1]) == CONST_DOUBLE"
7487 [(set (match_dup 0) (match_dup 2))
7489 (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))]
7491 unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
7492 unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
7493 unsigned HOST_WIDE_INT val = low;
7494 unsigned HOST_WIDE_INT sign;
7496 /* Zero-extend the 16 least-significant bits. */
7498 operands[1] = GEN_INT (val);
7500 /* Arithmetic shift right the double-word by 16 bits. */
7502 low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16);
7505 sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1);
7509 /* This will only be true if high is a sign-extension of low, i.e.,
7510 it must be either 0 or (unsigned)-1, and be zero iff the
7511 most-significant bit of low is set. */
7512 if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0)
7513 operands[2] = GEN_INT (low);
7515 operands[2] = immed_double_const (low, high, DImode);
7518 (define_insn "shori_media"
7519 [(set (match_operand:DI 0 "ext_dest_operand" "=r,r")
7520 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0")
7522 (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))]
7523 "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))"
7527 [(set_attr "type" "arith_media,*")])
7529 (define_insn "*shori_media_si"
7530 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
7531 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
7533 (match_operand:SI 2 "immediate_operand" "K16Csu")))]
7537 (define_expand "movdi"
7538 [(set (match_operand:DI 0 "general_movdst_operand" "")
7539 (match_operand:DI 1 "general_movsrc_operand" ""))]
7542 prepare_move_operands (operands, DImode);
7545 (define_insn "movdf_media"
7546 [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
7547 (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
7549 && (register_operand (operands[0], DFmode)
7550 || sh_register_operand (operands[1], DFmode))"
7561 [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,
7562 fload_media,fstore_media,load_media,store_media")])
7564 (define_insn "movdf_media_nofpu"
7565 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7566 (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))]
7568 && (register_operand (operands[0], DFmode)
7569 || sh_register_operand (operands[1], DFmode))"
7575 [(set_attr "type" "arith_media,*,load_media,store_media")])
7578 [(set (match_operand:DF 0 "arith_reg_dest" "")
7579 (match_operand:DF 1 "immediate_operand" ""))]
7580 "TARGET_SHMEDIA && reload_completed"
7581 [(set (match_dup 3) (match_dup 2))]
7583 int endian = WORDS_BIG_ENDIAN ? 1 : 0;
7585 REAL_VALUE_TYPE value;
7587 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
7588 REAL_VALUE_TO_TARGET_DOUBLE (value, values);
7590 if (HOST_BITS_PER_WIDE_INT >= 64)
7591 operands[2] = immed_double_const ((unsigned long) values[endian]
7592 | ((HOST_WIDE_INT) values[1 - endian]
7596 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
7597 operands[2] = immed_double_const (values[endian], values[1 - endian],
7601 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
7604 ;; FIXME: This should be a define_insn_and_split.
7605 (define_insn "movdf_k"
7606 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
7607 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
7609 && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
7610 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
7611 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
7612 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
7613 && (arith_reg_operand (operands[0], DFmode)
7614 || arith_reg_operand (operands[1], DFmode))"
7616 return output_movedouble (insn, operands, DFmode);
7618 [(set_attr "length" "4")
7619 (set_attr "type" "move,pcload,load,store")])
7621 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
7622 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
7623 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
7624 ;; the d/m/c/X alternative, which is split later into single-precision
7625 ;; instructions. And when not optimizing, no splits are done before fixing
7626 ;; up pcloads, so we need usable length information for that.
7627 (define_insn "movdf_i4"
7628 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
7629 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
7630 (use (reg:SI FPSCR_MODES_REG))
7631 (clobber (match_scratch:SI 2 "=X,X,&z,X,X,X,X,X,X,X"))]
7632 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7633 && (arith_reg_operand (operands[0], DFmode)
7634 || arith_reg_operand (operands[1], DFmode))"
7636 switch (which_alternative)
7640 return "fmov %1,%0";
7641 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
7642 return "fmov %R1,%R0" "\n"
7645 return "fmov %S1,%S0" "\n"
7649 return "fmov.d %1,%0";
7654 [(set_attr_alternative "length"
7655 [(if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
7657 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7658 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7659 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
7661 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
7662 ;; We can't use 4-byte push/pop on SHcompact, so we have to
7663 ;; increment or decrement r15 explicitly.
7665 (match_test "TARGET_SHCOMPACT")
7666 (const_int 10) (const_int 8))
7668 (match_test "TARGET_SHCOMPACT")
7669 (const_int 10) (const_int 8))])
7670 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload")
7671 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
7672 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
7673 (const_string "double")
7674 (const_string "none")))])
7676 ;; Moving DFmode between fp/general registers through memory
7677 ;; (the top of the stack) is faster than moving through fpul even for
7678 ;; little endian. Because the type of an instruction is important for its
7679 ;; scheduling, it is beneficial to split these operations, rather than
7680 ;; emitting them in one single chunk, even if this will expose a stack
7681 ;; use that will prevent scheduling of other stack accesses beyond this
7684 [(set (match_operand:DF 0 "register_operand")
7685 (match_operand:DF 1 "register_operand"))
7686 (use (reg:SI FPSCR_MODES_REG))
7687 (clobber (match_scratch:SI 2))]
7688 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
7689 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
7694 if (TARGET_SH5 && true_regnum (operands[1]) < 16)
7696 emit_move_insn (stack_pointer_rtx,
7697 plus_constant (Pmode, stack_pointer_rtx, -8));
7698 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7701 tos = gen_tmp_stack_mem (DFmode,
7702 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
7703 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
7704 if (! (TARGET_SH5 && true_regnum (operands[1]) < 16))
7705 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7706 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7707 tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx);
7709 tos = gen_tmp_stack_mem (DFmode,
7710 gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
7711 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
7712 if (TARGET_SH5 && true_regnum (operands[0]) < 16)
7713 emit_move_insn (stack_pointer_rtx,
7714 plus_constant (Pmode, stack_pointer_rtx, 8));
7716 add_reg_note (insn, REG_INC, stack_pointer_rtx);
7720 ;; local-alloc sometimes allocates scratch registers even when not required,
7721 ;; so we must be prepared to handle these.
7723 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
7725 [(set (match_operand:DF 0 "general_movdst_operand" "")
7726 (match_operand:DF 1 "general_movsrc_operand" ""))
7727 (use (reg:SI FPSCR_MODES_REG))
7728 (clobber (match_scratch:SI 2))]
7729 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
7731 && true_regnum (operands[0]) < 16
7732 && true_regnum (operands[1]) < 16"
7733 [(set (match_dup 0) (match_dup 1))]
7735 /* If this was a reg <-> mem operation with base + index reg addressing,
7736 we have to handle this in a special way. */
7737 rtx mem = operands[0];
7739 if (! memory_operand (mem, DFmode))
7744 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
7745 mem = SUBREG_REG (mem);
7748 rtx addr = XEXP (mem, 0);
7749 if (GET_CODE (addr) == PLUS
7750 && REG_P (XEXP (addr, 0))
7751 && REG_P (XEXP (addr, 1)))
7754 rtx reg0 = gen_rtx_REG (Pmode, 0);
7755 rtx regop = operands[store_p], word0 ,word1;
7757 if (GET_CODE (regop) == SUBREG)
7758 alter_subreg (®op, true);
7759 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
7763 mem = copy_rtx (mem);
7764 PUT_MODE (mem, SImode);
7765 word0 = gen_rtx_SUBREG (SImode, regop, 0);
7766 alter_subreg (&word0, true);
7767 word1 = gen_rtx_SUBREG (SImode, regop, 4);
7768 alter_subreg (&word1, true);
7769 if (store_p || ! refers_to_regno_p (REGNO (word0),
7770 REGNO (word0) + 1, addr, 0))
7773 ? gen_movsi_ie (mem, word0)
7774 : gen_movsi_ie (word0, mem));
7775 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7776 mem = copy_rtx (mem);
7778 ? gen_movsi_ie (mem, word1)
7779 : gen_movsi_ie (word1, mem));
7780 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7784 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
7785 emit_insn (gen_movsi_ie (word1, mem));
7786 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
7787 mem = copy_rtx (mem);
7788 emit_insn (gen_movsi_ie (word0, mem));
7795 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
7797 [(set (match_operand:DF 0 "register_operand" "")
7798 (match_operand:DF 1 "memory_operand" ""))
7799 (use (reg:SI FPSCR_MODES_REG))
7800 (clobber (reg:SI R0_REG))]
7801 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
7802 [(parallel [(set (match_dup 0) (match_dup 1))
7803 (use (reg:SI FPSCR_MODES_REG))
7804 (clobber (scratch:SI))])]
7807 (define_expand "reload_indf__frn"
7808 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
7809 (match_operand:DF 1 "immediate_operand" "FQ"))
7810 (use (reg:SI FPSCR_MODES_REG))
7811 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
7815 (define_expand "reload_outdf__RnFRm"
7816 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
7817 (match_operand:DF 1 "register_operand" "af,r"))
7818 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
7822 ;; Simplify no-op moves.
7824 [(set (match_operand:SF 0 "register_operand" "")
7825 (match_operand:SF 1 "register_operand" ""))
7826 (use (reg:SI FPSCR_MODES_REG))
7827 (clobber (match_scratch:SI 2))]
7828 "TARGET_SH2E && reload_completed
7829 && true_regnum (operands[0]) == true_regnum (operands[1])"
7830 [(set (match_dup 0) (match_dup 0))]
7833 ;; fmovd substitute post-reload splits
7835 [(set (match_operand:DF 0 "register_operand" "")
7836 (match_operand:DF 1 "register_operand" ""))
7837 (use (reg:SI FPSCR_MODES_REG))
7838 (clobber (match_scratch:SI 2))]
7839 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
7840 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7841 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7844 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
7845 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
7846 gen_rtx_REG (SFmode, src)));
7847 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
7848 gen_rtx_REG (SFmode, src + 1)));
7853 [(set (match_operand:DF 0 "register_operand" "")
7854 (mem:DF (match_operand:SI 1 "register_operand" "")))
7855 (use (reg:SI FPSCR_MODES_REG))
7856 (clobber (match_scratch:SI 2))]
7857 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7858 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
7859 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
7862 int regno = true_regnum (operands[0]);
7864 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
7866 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
7867 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7868 regno + SH_REG_MSW_OFFSET),
7870 add_reg_note (insn, REG_INC, operands[1]);
7871 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
7872 regno + SH_REG_LSW_OFFSET),
7873 change_address (mem, SFmode, NULL_RTX)));
7878 [(set (match_operand:DF 0 "register_operand" "")
7879 (match_operand:DF 1 "memory_operand" ""))
7880 (use (reg:SI FPSCR_MODES_REG))
7881 (clobber (match_scratch:SI 2))]
7882 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7883 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
7886 int regno = true_regnum (operands[0]);
7888 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
7889 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7890 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7892 operands[1] = copy_rtx (mem2);
7893 addr = XEXP (mem2, 0);
7895 switch (GET_CODE (addr))
7898 /* This is complicated. If the register is an arithmetic register
7899 we can just fall through to the REG+DISP case below. Otherwise
7900 we have to use a combination of POST_INC and REG addressing... */
7901 if (! arith_reg_operand (operands[1], SFmode))
7903 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
7904 insn = emit_insn (gen_movsf_ie (reg0, mem2));
7905 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7907 emit_insn (gen_movsf_ie (reg1, operands[1]));
7909 /* If we have modified the stack pointer, the value that we have
7910 read with post-increment might be modified by an interrupt,
7911 so write it back. */
7912 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
7913 emit_insn (gen_push_e (reg0));
7915 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
7922 emit_insn (gen_movsf_ie (reg0, operands[1]));
7923 operands[1] = copy_rtx (operands[1]);
7924 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
7925 emit_insn (gen_movsf_ie (reg1, operands[1]));
7929 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
7930 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7932 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
7933 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7945 [(set (match_operand:DF 0 "memory_operand" "")
7946 (match_operand:DF 1 "register_operand" ""))
7947 (use (reg:SI FPSCR_MODES_REG))
7948 (clobber (match_scratch:SI 2))]
7949 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
7950 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
7953 int regno = true_regnum (operands[1]);
7955 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
7956 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
7958 operands[0] = copy_rtx (operands[0]);
7959 PUT_MODE (operands[0], SFmode);
7960 addr = XEXP (operands[0], 0);
7962 switch (GET_CODE (addr))
7965 /* This is complicated. If the register is an arithmetic register
7966 we can just fall through to the REG+DISP case below. Otherwise
7967 we have to use a combination of REG and PRE_DEC addressing... */
7968 if (! arith_reg_operand (operands[0], SFmode))
7970 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
7971 emit_insn (gen_movsf_ie (operands[0], reg1));
7973 operands[0] = copy_rtx (operands[0]);
7974 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
7976 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
7977 add_reg_note (insn, REG_INC, XEXP (addr, 0));
7983 /* Since REG+DISP addressing has already been decided upon by gcc
7984 we can rely upon it having chosen an arithmetic register as the
7985 register component of the address. Just emit the lower numbered
7986 register first, to the lower address, then the higher numbered
7987 register to the higher address. */
7988 emit_insn (gen_movsf_ie (operands[0], reg0));
7990 operands[0] = copy_rtx (operands[0]);
7991 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
7993 emit_insn (gen_movsf_ie (operands[0], reg1));
7997 /* This is easy. Output the word to go to the higher address
7998 first (ie the word in the higher numbered register) then the
7999 word to go to the lower address. */
8001 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
8002 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8004 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
8005 add_reg_note (insn, REG_INC, XEXP (addr, 0));
8017 ;; If the output is a register and the input is memory or a register, we have
8018 ;; to be careful and see which word needs to be loaded first.
8020 [(set (match_operand:DF 0 "general_movdst_operand" "")
8021 (match_operand:DF 1 "general_movsrc_operand" ""))]
8022 "TARGET_SH1 && reload_completed"
8023 [(set (match_dup 2) (match_dup 3))
8024 (set (match_dup 4) (match_dup 5))]
8028 if ((MEM_P (operands[0])
8029 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
8030 || (MEM_P (operands[1])
8031 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
8034 switch (GET_CODE (operands[0]))
8037 regno = REGNO (operands[0]);
8040 regno = subreg_regno (operands[0]);
8050 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
8052 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
8053 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
8054 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
8055 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
8059 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
8060 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
8061 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
8062 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
8065 if (operands[2] == 0 || operands[3] == 0
8066 || operands[4] == 0 || operands[5] == 0)
8070 (define_expand "movdf"
8071 [(set (match_operand:DF 0 "general_movdst_operand" "")
8072 (match_operand:DF 1 "general_movsrc_operand" ""))]
8075 prepare_move_operands (operands, DFmode);
8078 if (TARGET_SHMEDIA_FPU)
8079 emit_insn (gen_movdf_media (operands[0], operands[1]));
8081 emit_insn (gen_movdf_media_nofpu (operands[0], operands[1]));
8084 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
8086 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
8091 ;;This is incompatible with the way gcc uses subregs.
8092 ;;(define_insn "movv2sf_i"
8093 ;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m")
8094 ;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))]
8095 ;; "TARGET_SHMEDIA_FPU
8096 ;; && (fp_arith_reg_operand (operands[0], V2SFmode)
8097 ;; || fp_arith_reg_operand (operands[1], V2SFmode))"
8101 ;; fst%M0.p %m0, %1"
8102 ;; [(set_attr "type" "*,fload_media,fstore_media")])
8103 (define_insn_and_split "movv2sf_i"
8104 [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8105 (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8106 "TARGET_SHMEDIA_FPU"
8108 "TARGET_SHMEDIA_FPU && reload_completed"
8109 [(set (match_dup 0) (match_dup 1))]
8111 operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0);
8112 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0);
8115 (define_expand "movv2sf"
8116 [(set (match_operand:V2SF 0 "general_movdst_operand" "")
8117 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
8118 "TARGET_SHMEDIA_FPU"
8120 prepare_move_operands (operands, V2SFmode);
8123 (define_expand "addv2sf3"
8124 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8125 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8126 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8127 "TARGET_SHMEDIA_FPU"
8129 sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]);
8133 (define_expand "subv2sf3"
8134 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8135 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8136 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8137 "TARGET_SHMEDIA_FPU"
8139 sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]);
8143 (define_expand "mulv2sf3"
8144 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8145 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8146 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8147 "TARGET_SHMEDIA_FPU"
8149 sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]);
8153 (define_expand "divv2sf3"
8154 [(match_operand:V2SF 0 "fp_arith_reg_operand" "")
8155 (match_operand:V2SF 1 "fp_arith_reg_operand" "")
8156 (match_operand:V2SF 2 "fp_arith_reg_operand" "")]
8157 "TARGET_SHMEDIA_FPU"
8159 sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]);
8163 (define_insn_and_split "*movv4sf_i"
8164 [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf")
8165 (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))]
8166 "TARGET_SHMEDIA_FPU"
8168 "&& reload_completed"
8171 for (int i = 0; i < 4/2; i++)
8175 if (MEM_P (operands[0]))
8176 x = adjust_address (operands[0], V2SFmode,
8177 i * GET_MODE_SIZE (V2SFmode));
8179 x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
8181 if (MEM_P (operands[1]))
8182 y = adjust_address (operands[1], V2SFmode,
8183 i * GET_MODE_SIZE (V2SFmode));
8185 y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8);
8187 emit_insn (gen_movv2sf_i (x, y));
8192 [(set_attr "length" "8")])
8194 (define_expand "movv4sf"
8195 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
8196 (match_operand:V4SF 1 "general_operand" ""))]
8197 "TARGET_SHMEDIA_FPU"
8199 prepare_move_operands (operands, V4SFmode);
8202 (define_insn_and_split "*movv16sf_i"
8203 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8204 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8205 "TARGET_SHMEDIA_FPU"
8207 "&& reload_completed"
8210 for (int i = 0; i < 16/2; i++)
8214 if (MEM_P (operands[0]))
8215 x = adjust_address (operands[0], V2SFmode,
8216 i * GET_MODE_SIZE (V2SFmode));
8219 x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8);
8220 alter_subreg (&x, true);
8223 if (MEM_P (operands[1]))
8224 y = adjust_address (operands[1], V2SFmode,
8225 i * GET_MODE_SIZE (V2SFmode));
8228 y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8);
8229 alter_subreg (&y, true);
8232 emit_insn (gen_movv2sf_i (x, y));
8237 [(set_attr "length" "32")])
8239 (define_expand "movv16sf"
8240 [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m")
8241 (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))]
8242 "TARGET_SHMEDIA_FPU"
8244 prepare_move_operands (operands, V16SFmode);
8247 (define_insn "movsf_media"
8248 [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
8249 (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))]
8251 && (register_operand (operands[0], SFmode)
8252 || sh_register_operand (operands[1], SFmode))"
8263 [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")
8264 (set (attr "highpart")
8265 (cond [(match_test "sh_contains_memref_p (insn)")
8266 (const_string "user")]
8267 (const_string "ignore")))])
8269 (define_insn "movsf_media_nofpu"
8270 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
8271 (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))]
8273 && (register_operand (operands[0], SFmode)
8274 || sh_register_operand (operands[1], SFmode))"
8280 [(set_attr "type" "arith_media,*,load_media,store_media")
8281 (set (attr "highpart")
8282 (cond [(match_test "sh_contains_memref_p (insn)")
8283 (const_string "user")]
8284 (const_string "ignore")))])
8287 [(set (match_operand:SF 0 "arith_reg_dest" "")
8288 (match_operand:SF 1 "immediate_operand" ""))]
8289 "TARGET_SHMEDIA && reload_completed
8290 && ! FP_REGISTER_P (true_regnum (operands[0]))"
8291 [(set (match_dup 3) (match_dup 2))]
8294 REAL_VALUE_TYPE value;
8296 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
8297 REAL_VALUE_TO_TARGET_SINGLE (value, values);
8298 operands[2] = GEN_INT (values);
8300 operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0]));
8303 (define_insn "movsf_i"
8304 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
8305 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
8308 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
8309 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
8310 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
8311 && (arith_reg_operand (operands[0], SFmode)
8312 || arith_reg_operand (operands[1], SFmode))"
8321 [(set_attr "type" "move,move,pcload,load,store,move,move")])
8323 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
8324 ;; update_flow_info would not know where to put REG_EQUAL notes
8325 ;; when the destination changes mode.
8326 (define_insn "movsf_ie"
8327 [(set (match_operand:SF 0 "general_movdst_operand"
8328 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,<,y,y")
8329 (match_operand:SF 1 "general_movsrc_operand"
8330 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
8331 (use (reg:SI FPSCR_MODES_REG))
8332 (clobber (match_scratch:SI 2 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
8334 && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode)
8335 || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode)
8336 || arith_reg_operand (operands[2], SImode))"
8356 ! move optimized away"
8357 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
8358 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
8359 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
8360 (set_attr_alternative "length"
8367 (match_test "TARGET_SH2A")
8368 (const_int 4) (const_int 2))
8370 (match_test "TARGET_SH2A")
8371 (const_int 4) (const_int 2))
8374 (match_test "TARGET_SH2A")
8375 (const_int 4) (const_int 2))
8377 (match_test "TARGET_SH2A")
8378 (const_int 4) (const_int 2))
8388 (set_attr_alternative "fp_mode"
8389 [(if_then_else (eq_attr "fmovd" "yes")
8390 (const_string "single") (const_string "none"))
8391 (const_string "none")
8392 (const_string "single")
8393 (const_string "single")
8394 (const_string "none")
8395 (if_then_else (eq_attr "fmovd" "yes")
8396 (const_string "single") (const_string "none"))
8397 (if_then_else (eq_attr "fmovd" "yes")
8398 (const_string "single") (const_string "none"))
8399 (const_string "none")
8400 (const_string "none")
8401 (const_string "none")
8402 (const_string "none")
8403 (const_string "none")
8404 (const_string "none")
8405 (const_string "none")
8406 (const_string "none")
8407 (const_string "none")
8408 (const_string "none")
8409 (const_string "none")
8410 (const_string "none")])])
8413 [(set (match_operand:SF 0 "register_operand" "")
8414 (match_operand:SF 1 "register_operand" ""))
8415 (use (reg:SI FPSCR_MODES_REG))
8416 (clobber (reg:SI FPUL_REG))]
8418 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
8419 (use (reg:SI FPSCR_MODES_REG))
8420 (clobber (scratch:SI))])
8421 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
8422 (use (reg:SI FPSCR_MODES_REG))
8423 (clobber (scratch:SI))])]
8426 (define_expand "movsf"
8427 [(set (match_operand:SF 0 "general_movdst_operand" "")
8428 (match_operand:SF 1 "general_movsrc_operand" ""))]
8431 prepare_move_operands (operands, SFmode);
8434 if (TARGET_SHMEDIA_FPU)
8435 emit_insn (gen_movsf_media (operands[0], operands[1]));
8437 emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
8442 emit_insn (gen_movsf_ie (operands[0], operands[1]));
8447 (define_insn "mov_nop"
8448 [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
8451 [(set_attr "length" "0")
8452 (set_attr "type" "nil")])
8454 (define_expand "reload_insf__frn"
8455 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
8456 (match_operand:SF 1 "immediate_operand" "FQ"))
8457 (use (reg:SI FPSCR_MODES_REG))
8458 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8462 (define_expand "reload_insi__i_fpul"
8463 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
8464 (match_operand:SI 1 "immediate_operand" "i"))
8465 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
8469 (define_expand "ptabs"
8470 [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))]
8473 if (!TARGET_PT_FIXED)
8475 rtx eq = operands[1];
8477 /* ??? For canonical RTL we really should remove any CONST from EQ
8478 before wrapping it in the AND, and finally wrap the EQ into a
8479 const if is constant. However, for reload we must expose the
8480 input register or symbolic constant, and we can't have
8481 different insn structures outside of the operands for different
8482 alternatives of the same pattern. */
8483 eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)),
8486 = (gen_rtx_IF_THEN_ELSE
8489 gen_rtx_MEM (PDImode, operands[1]),
8490 gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE,
8491 PDImode, operands[1])));
8495 ;; expanded by ptabs expander.
8496 (define_insn "*extendsipdi_media"
8497 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8498 (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand"
8502 (mem:PDI (match_dup 1))
8503 (sign_extend:PDI (match_dup 1))))]
8504 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8508 [(set_attr "type" "ptabs_media,pt_media")
8509 (set_attr "length" "4,*")])
8511 (define_insn "*truncdipdi_media"
8512 [(set (match_operand:PDI 0 "target_reg_operand" "=b,b");
8513 (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand"
8517 (mem:PDI (match_dup 1))
8518 (truncate:PDI (match_dup 1))))]
8519 "TARGET_SHMEDIA && !TARGET_PT_FIXED"
8523 [(set_attr "type" "ptabs_media,pt_media")
8524 (set_attr "length" "4,*")])
8526 (define_insn "*movsi_y"
8527 [(set (match_operand:SI 0 "register_operand" "=y,y")
8528 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
8529 (clobber (match_scratch:SI 2 "=&z,r"))]
8531 && (reload_in_progress || reload_completed)"
8533 [(set_attr "length" "4")
8534 (set_attr "type" "pcload,move")])
8537 [(set (match_operand:SI 0 "register_operand" "")
8538 (match_operand:SI 1 "immediate_operand" ""))
8539 (clobber (match_operand:SI 2 "register_operand" ""))]
8541 [(set (match_dup 2) (match_dup 1))
8542 (set (match_dup 0) (match_dup 2))]
8545 ;; ------------------------------------------------------------------------
8546 ;; Define the real conditional branch instructions.
8547 ;; ------------------------------------------------------------------------
8549 (define_expand "branch_true"
8550 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
8551 (label_ref (match_operand 0))
8555 (define_expand "branch_false"
8556 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8557 (label_ref (match_operand 0))
8561 (define_insn_and_split "*cbranch_t"
8562 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
8563 (label_ref (match_operand 0))
8567 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
8572 /* Try to canonicalize the branch condition if it is not one of:
8573 (ne (reg:SI T_REG) (const_int 0))
8574 (eq (reg:SI T_REG) (const_int 0))
8576 Instead of splitting out a new insn, we modify the current insn's
8577 operands as needed. This preserves things such as REG_DEAD notes. */
8579 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
8580 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
8581 && XEXP (operands[1], 1) == const0_rtx)
8584 int branch_cond = sh_eval_treg_value (operands[1]);
8585 rtx new_cond_rtx = NULL_RTX;
8587 if (branch_cond == 0)
8588 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
8589 else if (branch_cond == 1)
8590 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
8592 if (new_cond_rtx != NULL_RTX)
8593 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
8594 new_cond_rtx, false);
8597 [(set_attr "type" "cbranch")])
8599 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
8600 ;; which destination is too far away.
8601 ;; The const_int_operand is distinct for each branch target; it avoids
8602 ;; unwanted matches with redundant_insn.
8603 (define_insn "block_branch_redirect"
8604 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
8607 [(set_attr "length" "0")])
8609 ;; This one has the additional purpose to record a possible scratch register
8610 ;; for the following branch.
8611 ;; ??? Unfortunately, just setting the scratch register is not good enough,
8612 ;; because the insn then might be deemed dead and deleted. And we can't
8613 ;; make the use in the jump insn explicit because that would disable
8614 ;; delay slot scheduling from the target.
8615 (define_insn "indirect_jump_scratch"
8616 [(set (match_operand:SI 0 "register_operand" "=r")
8617 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
8618 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
8621 [(set_attr "length" "0")])
8623 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
8624 ;; being pulled into the delay slot of a condbranch that has been made to
8625 ;; jump around the unconditional jump because it was out of range.
8626 (define_insn "stuff_delay_slot"
8628 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
8629 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
8632 [(set_attr "length" "0")
8633 (set_attr "cond_delay_slot" "yes")])
8635 ;; Conditional branch insns
8637 (define_expand "cbranchint4_media"
8639 (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator"
8640 [(match_operand 1 "" "")
8641 (match_operand 2 "" "")])
8642 (match_operand 3 "" "")
8646 machine_mode mode = GET_MODE (operands[1]);
8647 if (mode == VOIDmode)
8648 mode = GET_MODE (operands[2]);
8649 if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
8651 operands[1] = force_reg (mode, operands[1]);
8652 if (CONSTANT_P (operands[2])
8653 && (! satisfies_constraint_I06 (operands[2])))
8654 operands[2] = force_reg (mode, operands[2]);
8658 if (operands[1] != const0_rtx)
8659 operands[1] = force_reg (mode, operands[1]);
8660 if (operands[2] != const0_rtx)
8661 operands[2] = force_reg (mode, operands[2]);
8663 switch (GET_CODE (operands[0]))
8669 operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])),
8670 VOIDmode, operands[2], operands[1]);
8671 operands[1] = XEXP (operands[0], 0);
8672 operands[2] = XEXP (operands[0], 1);
8675 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
8676 VOIDmode, operands[1], operands[2]);
8679 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8682 (define_expand "cbranchfp4_media"
8684 (if_then_else (match_operator 0 "sh_float_comparison_operator"
8685 [(match_operand 1 "" "")
8686 (match_operand 2 "" "")])
8687 (match_operand 3 "" "")
8691 rtx tmp = gen_reg_rtx (SImode);
8693 if (GET_CODE (operands[0]) == NE)
8694 cmp = gen_rtx_EQ (SImode, operands[1], operands[2]);
8696 cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode,
8697 operands[1], operands[2]);
8699 emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2]));
8701 if (GET_CODE (cmp) == GET_CODE (operands[0]))
8702 operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
8704 operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8706 operands[2] = const0_rtx;
8707 operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]);
8710 (define_insn "*beq_media_i"
8712 (if_then_else (match_operator 3 "equality_comparison_operator"
8713 [(match_operand:DI 1 "arith_reg_operand" "r,r")
8714 (match_operand:DI 2 "arith_operand" "r,I06")])
8715 (match_operand 0 "target_operand" "b,b")
8720 b%o3i%' %1, %2, %0%>"
8721 [(set_attr "type" "cbranch_media")])
8723 (define_insn "*beq_media_i32"
8725 (if_then_else (match_operator 3 "equality_comparison_operator"
8726 [(match_operand:SI 1 "arith_reg_operand" "r,r")
8727 (match_operand:SI 2 "arith_operand" "r,I06")])
8728 (match_operand 0 "target_operand" "b,b")
8733 b%o3i%' %1, %2, %0%>"
8734 [(set_attr "type" "cbranch_media")])
8736 (define_insn "*bgt_media_i"
8738 (if_then_else (match_operator 3 "greater_comparison_operator"
8739 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8740 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8741 (match_operand 0 "target_operand" "b")
8744 "b%o3%' %N1, %N2, %0%>"
8745 [(set_attr "type" "cbranch_media")])
8747 (define_insn "*bgt_media_i32"
8749 (if_then_else (match_operator 3 "greater_comparison_operator"
8750 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8751 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8752 (match_operand 0 "target_operand" "b")
8755 "b%o3%' %N1, %N2, %0%>"
8756 [(set_attr "type" "cbranch_media")])
8758 ;; These are only needed to make invert_jump() happy - otherwise, jump
8759 ;; optimization will be silently disabled.
8760 (define_insn "*blt_media_i"
8762 (if_then_else (match_operator 3 "less_comparison_operator"
8763 [(match_operand:DI 1 "arith_reg_or_0_operand" "rN")
8764 (match_operand:DI 2 "arith_reg_or_0_operand" "rN")])
8765 (match_operand 0 "target_operand" "b")
8768 "b%o3%' %N2, %N1, %0%>"
8769 [(set_attr "type" "cbranch_media")])
8771 (define_insn "*blt_media_i32"
8773 (if_then_else (match_operator 3 "less_comparison_operator"
8774 [(match_operand:SI 1 "arith_reg_or_0_operand" "rN")
8775 (match_operand:SI 2 "arith_reg_or_0_operand" "rN")])
8776 (match_operand 0 "target_operand" "b")
8779 "b%o3%' %N2, %N1, %0%>"
8780 [(set_attr "type" "cbranch_media")])
8782 ;; combiner splitter for test-and-branch on single bit in register. This
8783 ;; is endian dependent because the non-paradoxical subreg looks different
8788 (match_operator 3 "equality_comparison_operator"
8791 (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0)
8793 (match_operand 2 "const_int_operand" "")) 0)
8795 (match_operand 0 "target_operand" "")
8797 (clobber (match_operand:SI 4 "arith_reg_dest" ""))]
8798 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
8799 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5)))
8800 (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))]
8802 operands[5] = GEN_INT (31 - INTVAL (operands[2]));
8803 operands[6] = (GET_CODE (operands[3]) == EQ
8804 ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx)
8805 : gen_rtx_GT (VOIDmode, const0_rtx, operands[4]));
8808 ; operand 0 is the loop count pseudo register
8809 ; operand 1 is the label to jump to at the top of the loop
8810 (define_expand "doloop_end"
8811 [(parallel [(set (pc)
8812 (if_then_else (ne:SI (match_operand:SI 0 "" "")
8814 (label_ref (match_operand 1 "" ""))
8817 (plus:SI (match_dup 0) (const_int -1)))
8818 (clobber (reg:SI T_REG))])]
8821 if (GET_MODE (operands[0]) != SImode)
8823 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
8827 (define_insn_and_split "doloop_end_split"
8829 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
8831 (label_ref (match_operand 1 "" ""))
8833 (set (match_operand:SI 0 "arith_reg_dest" "=r")
8834 (plus:SI (match_dup 2) (const_int -1)))
8835 (clobber (reg:SI T_REG))]
8839 [(parallel [(set (reg:SI T_REG)
8840 (eq:SI (match_dup 2) (const_int 1)))
8841 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
8842 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
8843 (label_ref (match_dup 1))
8846 [(set_attr "type" "cbranch")])
8848 ;; ------------------------------------------------------------------------
8849 ;; Jump and linkage insns
8850 ;; ------------------------------------------------------------------------
8852 (define_insn "jump_compact"
8854 (label_ref (match_operand 0 "" "")))]
8855 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
8857 /* The length is 16 if the delay slot is unfilled. */
8858 if (get_attr_length(insn) > 4)
8859 return output_far_jump(insn, operands[0]);
8863 [(set_attr "type" "jump")
8864 (set_attr "needs_delay_slot" "yes")])
8866 ;; ??? It would be much saner to explicitly use the scratch register
8867 ;; in the jump insn, and have indirect_jump_scratch only set it,
8868 ;; but fill_simple_delay_slots would refuse to do delay slot filling
8869 ;; from the target then, as it uses simplejump_p.
8870 ;;(define_insn "jump_compact_far"
8872 ;; (label_ref (match_operand 0 "" "")))
8873 ;; (use (match_operand 1 "register_operand" "r")]
8875 ;; "* return output_far_jump(insn, operands[0], operands[1]);"
8876 ;; [(set_attr "type" "jump")
8877 ;; (set_attr "needs_delay_slot" "yes")])
8879 (define_insn "jump_media"
8881 (match_operand 0 "target_operand" "b"))]
8884 [(set_attr "type" "jump_media")])
8886 (define_expand "jump"
8888 (label_ref (match_operand 0 "" "")))]
8892 emit_jump_insn (gen_jump_compact (operands[0]));
8893 else if (TARGET_SHMEDIA)
8895 if (reload_in_progress || reload_completed)
8897 emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0])));
8902 (define_insn "force_mode_for_call"
8903 [(use (reg:SI FPSCR_MODES_REG))]
8906 [(set_attr "length" "0")
8907 (set (attr "fp_mode")
8908 (if_then_else (eq_attr "fpu_single" "yes")
8909 (const_string "single") (const_string "double")))])
8911 (define_insn "calli"
8912 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8913 (match_operand 1 "" ""))
8914 (use (reg:SI FPSCR_MODES_REG))
8915 (clobber (reg:SI PR_REG))]
8918 if (TARGET_SH2A && (dbr_sequence_length () == 0))
8923 [(set_attr "type" "call")
8924 (set (attr "fp_mode")
8925 (if_then_else (eq_attr "fpu_single" "yes")
8926 (const_string "single") (const_string "double")))
8927 (set_attr "needs_delay_slot" "yes")
8928 (set_attr "fp_set" "unknown")])
8930 ;; This is TBR relative jump instruction for SH2A architecture.
8931 ;; Its use is enabled by assigning an attribute "function_vector"
8932 ;; and the vector number to a function during its declaration.
8933 (define_insn "calli_tbr_rel"
8934 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
8935 (match_operand 1 "" ""))
8936 (use (reg:SI FPSCR_MODES_REG))
8937 (clobber (reg:SI PR_REG))]
8938 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
8940 unsigned HOST_WIDE_INT vect_num;
8941 vect_num = sh2a_get_function_vector_number (operands[0]);
8942 operands[2] = GEN_INT (vect_num * 4);
8944 return "jsr/n @@(%O2,tbr)";
8946 [(set_attr "type" "call")
8947 (set (attr "fp_mode")
8948 (if_then_else (eq_attr "fpu_single" "yes")
8949 (const_string "single") (const_string "double")))
8950 (set_attr "needs_delay_slot" "no")
8951 (set_attr "fp_set" "unknown")])
8953 ;; This is a pc-rel call, using bsrf, for use with PIC.
8954 (define_insn "calli_pcrel"
8955 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
8956 (match_operand 1 "" ""))
8957 (use (reg:SI FPSCR_MODES_REG))
8958 (use (reg:SI PIC_REG))
8959 (use (match_operand 2 "" ""))
8960 (clobber (reg:SI PR_REG))]
8963 return "bsrf %0" "\n"
8966 [(set_attr "type" "call")
8967 (set (attr "fp_mode")
8968 (if_then_else (eq_attr "fpu_single" "yes")
8969 (const_string "single") (const_string "double")))
8970 (set_attr "needs_delay_slot" "yes")
8971 (set_attr "fp_set" "unknown")])
8973 (define_insn_and_split "call_pcrel"
8974 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
8975 (match_operand 1 "" ""))
8976 (use (reg:SI FPSCR_MODES_REG))
8977 (use (reg:SI PIC_REG))
8978 (clobber (reg:SI PR_REG))
8979 (clobber (match_scratch:SI 2 "=r"))]
8985 rtx lab = PATTERN (gen_call_site ());
8987 if (SYMBOL_REF_LOCAL_P (operands[0]))
8988 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
8990 emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
8991 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
8994 [(set_attr "type" "call")
8995 (set (attr "fp_mode")
8996 (if_then_else (eq_attr "fpu_single" "yes")
8997 (const_string "single") (const_string "double")))
8998 (set_attr "needs_delay_slot" "yes")
8999 (set_attr "fp_set" "unknown")])
9001 (define_insn "call_compact"
9002 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9003 (match_operand 1 "" ""))
9004 (match_operand 2 "immediate_operand" "n")
9005 (use (reg:SI R0_REG))
9006 (use (reg:SI R1_REG))
9007 (use (reg:SI FPSCR_MODES_REG))
9008 (clobber (reg:SI PR_REG))]
9009 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9011 [(set_attr "type" "call")
9012 (set (attr "fp_mode")
9013 (if_then_else (eq_attr "fpu_single" "yes")
9014 (const_string "single") (const_string "double")))
9015 (set_attr "needs_delay_slot" "yes")])
9017 (define_insn "call_compact_rettramp"
9018 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9019 (match_operand 1 "" ""))
9020 (match_operand 2 "immediate_operand" "n")
9021 (use (reg:SI R0_REG))
9022 (use (reg:SI R1_REG))
9023 (use (reg:SI FPSCR_MODES_REG))
9024 (clobber (reg:SI R10_REG))
9025 (clobber (reg:SI PR_REG))]
9026 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9028 [(set_attr "type" "call")
9029 (set (attr "fp_mode")
9030 (if_then_else (eq_attr "fpu_single" "yes")
9031 (const_string "single") (const_string "double")))
9032 (set_attr "needs_delay_slot" "yes")])
9034 (define_insn "call_media"
9035 [(call (mem:DI (match_operand 0 "target_reg_operand" "b"))
9036 (match_operand 1 "" ""))
9037 (clobber (reg:DI PR_MEDIA_REG))]
9040 [(set_attr "type" "jump_media")])
9042 (define_insn "call_valuei"
9043 [(set (match_operand 0 "" "=rf")
9044 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9045 (match_operand 2 "" "")))
9046 (use (reg:SI FPSCR_MODES_REG))
9047 (clobber (reg:SI PR_REG))]
9050 if (TARGET_SH2A && (dbr_sequence_length () == 0))
9055 [(set_attr "type" "call")
9056 (set (attr "fp_mode")
9057 (if_then_else (eq_attr "fpu_single" "yes")
9058 (const_string "single") (const_string "double")))
9059 (set_attr "needs_delay_slot" "yes")
9060 (set_attr "fp_set" "unknown")])
9062 ;; This is TBR relative jump instruction for SH2A architecture.
9063 ;; Its use is enabled by assigning an attribute "function_vector"
9064 ;; and the vector number to a function during its declaration.
9065 (define_insn "call_valuei_tbr_rel"
9066 [(set (match_operand 0 "" "=rf")
9067 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9068 (match_operand 2 "" "")))
9069 (use (reg:SI FPSCR_MODES_REG))
9070 (clobber (reg:SI PR_REG))]
9071 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
9073 unsigned HOST_WIDE_INT vect_num;
9074 vect_num = sh2a_get_function_vector_number (operands[1]);
9075 operands[3] = GEN_INT (vect_num * 4);
9077 return "jsr/n @@(%O3,tbr)";
9079 [(set_attr "type" "call")
9080 (set (attr "fp_mode")
9081 (if_then_else (eq_attr "fpu_single" "yes")
9082 (const_string "single") (const_string "double")))
9083 (set_attr "needs_delay_slot" "no")
9084 (set_attr "fp_set" "unknown")])
9086 (define_insn "call_valuei_pcrel"
9087 [(set (match_operand 0 "" "=rf")
9088 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9089 (match_operand 2 "" "")))
9090 (use (reg:SI FPSCR_MODES_REG))
9091 (use (reg:SI PIC_REG))
9092 (use (match_operand 3 "" ""))
9093 (clobber (reg:SI PR_REG))]
9096 return "bsrf %1" "\n"
9099 [(set_attr "type" "call")
9100 (set (attr "fp_mode")
9101 (if_then_else (eq_attr "fpu_single" "yes")
9102 (const_string "single") (const_string "double")))
9103 (set_attr "needs_delay_slot" "yes")
9104 (set_attr "fp_set" "unknown")])
9106 (define_insn_and_split "call_value_pcrel"
9107 [(set (match_operand 0 "" "=rf")
9108 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9109 (match_operand 2 "" "")))
9110 (use (reg:SI FPSCR_MODES_REG))
9111 (use (reg:SI PIC_REG))
9112 (clobber (reg:SI PR_REG))
9113 (clobber (match_scratch:SI 3 "=r"))]
9119 rtx lab = PATTERN (gen_call_site ());
9121 if (SYMBOL_REF_LOCAL_P (operands[1]))
9122 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9124 emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
9125 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
9126 operands[2], copy_rtx (lab)));
9129 [(set_attr "type" "call")
9130 (set (attr "fp_mode")
9131 (if_then_else (eq_attr "fpu_single" "yes")
9132 (const_string "single") (const_string "double")))
9133 (set_attr "needs_delay_slot" "yes")
9134 (set_attr "fp_set" "unknown")])
9136 (define_insn "call_value_compact"
9137 [(set (match_operand 0 "" "=rf")
9138 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9139 (match_operand 2 "" "")))
9140 (match_operand 3 "immediate_operand" "n")
9141 (use (reg:SI R0_REG))
9142 (use (reg:SI R1_REG))
9143 (use (reg:SI FPSCR_MODES_REG))
9144 (clobber (reg:SI PR_REG))]
9145 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9147 [(set_attr "type" "call")
9148 (set (attr "fp_mode")
9149 (if_then_else (eq_attr "fpu_single" "yes")
9150 (const_string "single") (const_string "double")))
9151 (set_attr "needs_delay_slot" "yes")])
9153 (define_insn "call_value_compact_rettramp"
9154 [(set (match_operand 0 "" "=rf")
9155 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9156 (match_operand 2 "" "")))
9157 (match_operand 3 "immediate_operand" "n")
9158 (use (reg:SI R0_REG))
9159 (use (reg:SI R1_REG))
9160 (use (reg:SI FPSCR_MODES_REG))
9161 (clobber (reg:SI R10_REG))
9162 (clobber (reg:SI PR_REG))]
9163 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9165 [(set_attr "type" "call")
9166 (set (attr "fp_mode")
9167 (if_then_else (eq_attr "fpu_single" "yes")
9168 (const_string "single") (const_string "double")))
9169 (set_attr "needs_delay_slot" "yes")])
9171 (define_insn "call_value_media"
9172 [(set (match_operand 0 "" "=rf")
9173 (call (mem:DI (match_operand 1 "target_reg_operand" "b"))
9174 (match_operand 2 "" "")))
9175 (clobber (reg:DI PR_MEDIA_REG))]
9178 [(set_attr "type" "jump_media")])
9180 (define_expand "call"
9181 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9182 (match_operand 1 "" ""))
9183 (match_operand 2 "" "")
9184 (use (reg:SI FPSCR_MODES_REG))
9185 (clobber (reg:SI PR_REG))])]
9190 operands[0] = shmedia_prepare_call_address (operands[0], 0);
9191 emit_call_insn (gen_call_media (operands[0], operands[1]));
9194 else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2]))
9196 rtx cookie_rtx = operands[2];
9197 long cookie = INTVAL (cookie_rtx);
9198 rtx func = XEXP (operands[0], 0);
9203 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9205 rtx reg = gen_reg_rtx (Pmode);
9207 emit_insn (gen_symGOTPLT2reg (reg, func));
9211 func = legitimize_pic_address (func, Pmode, 0);
9214 r0 = gen_rtx_REG (SImode, R0_REG);
9215 r1 = gen_rtx_REG (SImode, R1_REG);
9217 /* Since such a call function may use all call-clobbered
9218 registers, we force a mode switch earlier, so that we don't
9219 run out of registers when adjusting fpscr for the call. */
9220 emit_insn (gen_force_mode_for_call ());
9223 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9224 operands[0] = force_reg (SImode, operands[0]);
9226 emit_move_insn (r0, func);
9227 emit_move_insn (r1, cookie_rtx);
9229 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9230 emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1],
9233 emit_call_insn (gen_call_compact (operands[0], operands[1],
9238 else if (TARGET_SHCOMPACT && flag_pic
9239 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9240 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9242 rtx reg = gen_reg_rtx (Pmode);
9244 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0)));
9245 XEXP (operands[0], 0) = reg;
9247 if (!flag_pic && TARGET_SH2A
9248 && MEM_P (operands[0])
9249 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9251 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
9253 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
9258 if (flag_pic && TARGET_SH2
9259 && MEM_P (operands[0])
9260 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
9262 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
9267 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9268 operands[1] = operands[2];
9271 emit_call_insn (gen_calli (operands[0], operands[1]));
9275 (define_insn "call_pop_compact"
9276 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9277 (match_operand 1 "" ""))
9278 (match_operand 2 "immediate_operand" "n")
9279 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9280 (match_operand 3 "immediate_operand" "n")))
9281 (use (reg:SI R0_REG))
9282 (use (reg:SI R1_REG))
9283 (use (reg:SI FPSCR_MODES_REG))
9284 (clobber (reg:SI PR_REG))]
9285 "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9287 [(set_attr "type" "call")
9288 (set (attr "fp_mode")
9289 (if_then_else (eq_attr "fpu_single" "yes")
9290 (const_string "single") (const_string "double")))
9291 (set_attr "needs_delay_slot" "yes")])
9293 (define_insn "call_pop_compact_rettramp"
9294 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
9295 (match_operand 1 "" ""))
9296 (match_operand 2 "immediate_operand" "n")
9297 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9298 (match_operand 3 "immediate_operand" "n")))
9299 (use (reg:SI R0_REG))
9300 (use (reg:SI R1_REG))
9301 (use (reg:SI FPSCR_MODES_REG))
9302 (clobber (reg:SI R10_REG))
9303 (clobber (reg:SI PR_REG))]
9304 "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))"
9306 [(set_attr "type" "call")
9307 (set (attr "fp_mode")
9308 (if_then_else (eq_attr "fpu_single" "yes")
9309 (const_string "single") (const_string "double")))
9310 (set_attr "needs_delay_slot" "yes")])
9312 (define_expand "call_pop"
9313 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9314 (match_operand 1 "" ""))
9315 (match_operand 2 "" "")
9316 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9317 (match_operand 3 "" "")))])]
9325 gcc_assert (operands[2] && INTVAL (operands[2]));
9326 cookie_rtx = operands[2];
9327 cookie = INTVAL (cookie_rtx);
9328 func = XEXP (operands[0], 0);
9332 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9334 rtx reg = gen_reg_rtx (Pmode);
9335 emit_insn (gen_symGOTPLT2reg (reg, func));
9339 func = legitimize_pic_address (func, Pmode, 0);
9342 r0 = gen_rtx_REG (SImode, R0_REG);
9343 r1 = gen_rtx_REG (SImode, R1_REG);
9345 /* Since such a call function may use all call-clobbered
9346 registers, we force a mode switch earlier, so that we don't
9347 run out of registers when adjusting fpscr for the call. */
9348 emit_insn (gen_force_mode_for_call ());
9350 operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9352 operands[0] = force_reg (SImode, operands[0]);
9354 emit_move_insn (r0, func);
9355 emit_move_insn (r1, cookie_rtx);
9357 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9358 emit_call_insn (gen_call_pop_compact_rettramp
9359 (operands[0], operands[1], operands[2], operands[3]));
9361 emit_call_insn (gen_call_pop_compact
9362 (operands[0], operands[1], operands[2], operands[3]));
9367 (define_expand "call_value"
9368 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9369 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9370 (match_operand 2 "" "")))
9371 (match_operand 3 "" "")
9372 (use (reg:SI FPSCR_MODES_REG))
9373 (clobber (reg:SI PR_REG))])]
9378 operands[1] = shmedia_prepare_call_address (operands[1], 0);
9379 emit_call_insn (gen_call_value_media (operands[0], operands[1],
9383 else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]))
9385 rtx cookie_rtx = operands[3];
9386 long cookie = INTVAL (cookie_rtx);
9387 rtx func = XEXP (operands[1], 0);
9392 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9394 rtx reg = gen_reg_rtx (Pmode);
9396 emit_insn (gen_symGOTPLT2reg (reg, func));
9400 func = legitimize_pic_address (func, Pmode, 0);
9403 r0 = gen_rtx_REG (SImode, R0_REG);
9404 r1 = gen_rtx_REG (SImode, R1_REG);
9406 /* Since such a call function may use all call-clobbered
9407 registers, we force a mode switch earlier, so that we don't
9408 run out of registers when adjusting fpscr for the call. */
9409 emit_insn (gen_force_mode_for_call ());
9412 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9413 operands[1] = force_reg (SImode, operands[1]);
9415 emit_move_insn (r0, func);
9416 emit_move_insn (r1, cookie_rtx);
9418 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9419 emit_call_insn (gen_call_value_compact_rettramp (operands[0],
9424 emit_call_insn (gen_call_value_compact (operands[0], operands[1],
9425 operands[2], operands[3]));
9429 else if (TARGET_SHCOMPACT && flag_pic
9430 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9431 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9433 rtx reg = gen_reg_rtx (Pmode);
9435 emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0)));
9436 XEXP (operands[1], 0) = reg;
9438 if (!flag_pic && TARGET_SH2A
9439 && MEM_P (operands[1])
9440 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9442 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
9444 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
9445 XEXP (operands[1], 0), operands[2]));
9449 if (flag_pic && TARGET_SH2
9450 && MEM_P (operands[1])
9451 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
9453 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
9458 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9460 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
9464 (define_insn "sibcalli"
9465 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
9466 (match_operand 1 "" ""))
9467 (use (reg:SI FPSCR_MODES_REG))
9471 [(set_attr "needs_delay_slot" "yes")
9472 (set (attr "fp_mode")
9473 (if_then_else (eq_attr "fpu_single" "yes")
9474 (const_string "single") (const_string "double")))
9475 (set_attr "type" "jump_ind")])
9477 (define_insn "sibcalli_pcrel"
9478 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
9479 (match_operand 1 "" ""))
9480 (use (match_operand 2 "" ""))
9481 (use (reg:SI FPSCR_MODES_REG))
9485 return "braf %0" "\n"
9488 [(set_attr "needs_delay_slot" "yes")
9489 (set (attr "fp_mode")
9490 (if_then_else (eq_attr "fpu_single" "yes")
9491 (const_string "single") (const_string "double")))
9492 (set_attr "type" "jump_ind")])
9494 ;; This uses an unspec to describe that the symbol_ref is very close.
9495 (define_insn "sibcalli_thunk"
9496 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
9498 (match_operand 1 "" ""))
9499 (use (reg:SI FPSCR_MODES_REG))
9503 [(set_attr "needs_delay_slot" "yes")
9504 (set (attr "fp_mode")
9505 (if_then_else (eq_attr "fpu_single" "yes")
9506 (const_string "single") (const_string "double")))
9507 (set_attr "type" "jump")
9508 (set_attr "length" "2")])
9510 (define_insn_and_split "sibcall_pcrel"
9511 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
9512 (match_operand 1 "" ""))
9513 (use (reg:SI FPSCR_MODES_REG))
9514 (clobber (match_scratch:SI 2 "=k"))
9521 rtx lab = PATTERN (gen_call_site ());
9524 emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
9525 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
9527 SIBLING_CALL_P (call_insn) = 1;
9530 [(set_attr "needs_delay_slot" "yes")
9531 (set (attr "fp_mode")
9532 (if_then_else (eq_attr "fpu_single" "yes")
9533 (const_string "single") (const_string "double")))
9534 (set_attr "type" "jump_ind")])
9536 (define_insn "sibcall_compact"
9537 [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
9538 (match_operand 1 "" ""))
9540 (use (match_operand:SI 2 "register_operand" "z,x"))
9541 (use (reg:SI R1_REG))
9542 (use (reg:SI FPSCR_MODES_REG))
9543 ;; We want to make sure the `x' above will only match MACH_REG
9544 ;; because sibcall_epilogue may clobber MACL_REG.
9545 (clobber (reg:SI MACL_REG))]
9548 static const char* alt[] =
9555 return alt[which_alternative];
9557 [(set_attr "needs_delay_slot" "yes,no")
9558 (set_attr "length" "2,4")
9559 (set (attr "fp_mode") (const_string "single"))
9560 (set_attr "type" "jump_ind")])
9562 (define_insn "sibcall_media"
9563 [(call (mem:DI (match_operand 0 "target_reg_operand" "k"))
9564 (match_operand 1 "" ""))
9565 (use (reg:SI PR_MEDIA_REG))
9569 [(set_attr "type" "jump_media")])
9571 (define_expand "sibcall"
9573 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
9574 (match_operand 1 "" ""))
9575 (match_operand 2 "" "")
9576 (use (reg:SI FPSCR_MODES_REG))
9582 operands[0] = shmedia_prepare_call_address (operands[0], 1);
9583 emit_call_insn (gen_sibcall_media (operands[0], operands[1]));
9586 else if (TARGET_SHCOMPACT && operands[2]
9587 && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9589 rtx cookie_rtx = operands[2];
9590 long cookie = INTVAL (cookie_rtx);
9591 rtx func = XEXP (operands[0], 0);
9596 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9598 rtx reg = gen_reg_rtx (Pmode);
9600 emit_insn (gen_symGOT2reg (reg, func));
9604 func = legitimize_pic_address (func, Pmode, 0);
9607 /* FIXME: if we could tell whether all argument registers are
9608 already taken, we could decide whether to force the use of
9609 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9610 simple way to tell. We could use the CALL_COOKIE, but we
9611 can't currently tell a register used for regular argument
9612 passing from one that is unused. If we leave it up to reload
9613 to decide which register to use, it seems to always choose
9614 R0_REG, which leaves no available registers in SIBCALL_REGS
9615 to hold the address of the trampoline. */
9616 mach = gen_rtx_REG (SImode, MACH_REG);
9617 r1 = gen_rtx_REG (SImode, R1_REG);
9619 /* Since such a call function may use all call-clobbered
9620 registers, we force a mode switch earlier, so that we don't
9621 run out of registers when adjusting fpscr for the call. */
9622 emit_insn (gen_force_mode_for_call ());
9625 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9626 operands[0] = force_reg (SImode, operands[0]);
9628 /* We don't need a return trampoline, since the callee will
9629 return directly to the upper caller. */
9630 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9632 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9633 cookie_rtx = GEN_INT (cookie);
9636 emit_move_insn (mach, func);
9637 emit_move_insn (r1, cookie_rtx);
9639 emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach));
9642 else if (TARGET_SHCOMPACT && flag_pic
9643 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9644 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9646 rtx reg = gen_reg_rtx (Pmode);
9648 emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0)));
9649 XEXP (operands[0], 0) = reg;
9651 if (flag_pic && TARGET_SH2
9652 && MEM_P (operands[0])
9653 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9654 /* The PLT needs the PIC register, but the epilogue would have
9655 to restore it, so we can only use PC-relative PIC calls for
9656 static functions. */
9657 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
9659 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
9663 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
9665 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
9669 (define_insn "sibcall_valuei"
9670 [(set (match_operand 0 "" "=rf")
9671 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
9672 (match_operand 2 "" "")))
9673 (use (reg:SI FPSCR_MODES_REG))
9677 [(set_attr "needs_delay_slot" "yes")
9678 (set (attr "fp_mode")
9679 (if_then_else (eq_attr "fpu_single" "yes")
9680 (const_string "single") (const_string "double")))
9681 (set_attr "type" "jump_ind")])
9683 (define_insn "sibcall_valuei_pcrel"
9684 [(set (match_operand 0 "" "=rf")
9685 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
9686 (match_operand 2 "" "")))
9687 (use (match_operand 3 "" ""))
9688 (use (reg:SI FPSCR_MODES_REG))
9692 return "braf %1" "\n"
9695 [(set_attr "needs_delay_slot" "yes")
9696 (set (attr "fp_mode")
9697 (if_then_else (eq_attr "fpu_single" "yes")
9698 (const_string "single") (const_string "double")))
9699 (set_attr "type" "jump_ind")])
9701 (define_insn_and_split "sibcall_value_pcrel"
9702 [(set (match_operand 0 "" "=rf")
9703 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
9704 (match_operand 2 "" "")))
9705 (use (reg:SI FPSCR_MODES_REG))
9706 (clobber (match_scratch:SI 3 "=k"))
9713 rtx lab = PATTERN (gen_call_site ());
9716 emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
9717 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
9721 SIBLING_CALL_P (call_insn) = 1;
9724 [(set_attr "needs_delay_slot" "yes")
9725 (set (attr "fp_mode")
9726 (if_then_else (eq_attr "fpu_single" "yes")
9727 (const_string "single") (const_string "double")))
9728 (set_attr "type" "jump_ind")])
9730 (define_insn "sibcall_value_compact"
9731 [(set (match_operand 0 "" "=rf,rf")
9732 (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
9733 (match_operand 2 "" "")))
9735 (use (match_operand:SI 3 "register_operand" "z,x"))
9736 (use (reg:SI R1_REG))
9737 (use (reg:SI FPSCR_MODES_REG))
9738 ;; We want to make sure the `x' above will only match MACH_REG
9739 ;; because sibcall_epilogue may clobber MACL_REG.
9740 (clobber (reg:SI MACL_REG))]
9743 static const char* alt[] =
9750 return alt[which_alternative];
9752 [(set_attr "needs_delay_slot" "yes,no")
9753 (set_attr "length" "2,4")
9754 (set (attr "fp_mode") (const_string "single"))
9755 (set_attr "type" "jump_ind")])
9757 (define_insn "sibcall_value_media"
9758 [(set (match_operand 0 "" "=rf")
9759 (call (mem:DI (match_operand 1 "target_reg_operand" "k"))
9760 (match_operand 2 "" "")))
9761 (use (reg:SI PR_MEDIA_REG))
9765 [(set_attr "type" "jump_media")])
9767 (define_expand "sibcall_value"
9769 [(set (match_operand 0 "arith_reg_operand" "")
9770 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9771 (match_operand 2 "" "")))
9772 (match_operand 3 "" "")
9773 (use (reg:SI FPSCR_MODES_REG))
9779 operands[1] = shmedia_prepare_call_address (operands[1], 1);
9780 emit_call_insn (gen_sibcall_value_media (operands[0], operands[1],
9784 else if (TARGET_SHCOMPACT && operands[3]
9785 && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1)))
9787 rtx cookie_rtx = operands[3];
9788 long cookie = INTVAL (cookie_rtx);
9789 rtx func = XEXP (operands[1], 0);
9794 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9796 rtx reg = gen_reg_rtx (Pmode);
9798 emit_insn (gen_symGOT2reg (reg, func));
9802 func = legitimize_pic_address (func, Pmode, 0);
9805 /* FIXME: if we could tell whether all argument registers are
9806 already taken, we could decide whether to force the use of
9807 MACH_REG or to stick to R0_REG. Unfortunately, there's no
9808 simple way to tell. We could use the CALL_COOKIE, but we
9809 can't currently tell a register used for regular argument
9810 passing from one that is unused. If we leave it up to reload
9811 to decide which register to use, it seems to always choose
9812 R0_REG, which leaves no available registers in SIBCALL_REGS
9813 to hold the address of the trampoline. */
9814 mach = gen_rtx_REG (SImode, MACH_REG);
9815 r1 = gen_rtx_REG (SImode, R1_REG);
9817 /* Since such a call function may use all call-clobbered
9818 registers, we force a mode switch earlier, so that we don't
9819 run out of registers when adjusting fpscr for the call. */
9820 emit_insn (gen_force_mode_for_call ());
9823 = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
9824 operands[1] = force_reg (SImode, operands[1]);
9826 /* We don't need a return trampoline, since the callee will
9827 return directly to the upper caller. */
9828 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9830 cookie &= ~ CALL_COOKIE_RET_TRAMP (1);
9831 cookie_rtx = GEN_INT (cookie);
9834 emit_move_insn (mach, func);
9835 emit_move_insn (r1, cookie_rtx);
9837 emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1],
9838 operands[2], mach));
9841 else if (TARGET_SHCOMPACT && flag_pic
9842 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9843 && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9845 rtx reg = gen_reg_rtx (Pmode);
9847 emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0)));
9848 XEXP (operands[1], 0) = reg;
9850 if (flag_pic && TARGET_SH2
9851 && MEM_P (operands[1])
9852 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
9853 /* The PLT needs the PIC register, but the epilogue would have
9854 to restore it, so we can only use PC-relative PIC calls for
9855 static functions. */
9856 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
9858 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
9859 XEXP (operands[1], 0),
9864 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
9866 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
9870 (define_insn "call_value_pop_compact"
9871 [(set (match_operand 0 "" "=rf")
9872 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9873 (match_operand 2 "" "")))
9874 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9875 (match_operand 4 "immediate_operand" "n")))
9876 (match_operand 3 "immediate_operand" "n")
9877 (use (reg:SI R0_REG))
9878 (use (reg:SI R1_REG))
9879 (use (reg:SI FPSCR_MODES_REG))
9880 (clobber (reg:SI PR_REG))]
9881 "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9883 [(set_attr "type" "call")
9884 (set (attr "fp_mode")
9885 (if_then_else (eq_attr "fpu_single" "yes")
9886 (const_string "single") (const_string "double")))
9887 (set_attr "needs_delay_slot" "yes")])
9889 (define_insn "call_value_pop_compact_rettramp"
9890 [(set (match_operand 0 "" "=rf")
9891 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
9892 (match_operand 2 "" "")))
9893 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9894 (match_operand 4 "immediate_operand" "n")))
9895 (match_operand 3 "immediate_operand" "n")
9896 (use (reg:SI R0_REG))
9897 (use (reg:SI R1_REG))
9898 (use (reg:SI FPSCR_MODES_REG))
9899 (clobber (reg:SI R10_REG))
9900 (clobber (reg:SI PR_REG))]
9901 "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))"
9903 [(set_attr "type" "call")
9904 (set (attr "fp_mode")
9905 (if_then_else (eq_attr "fpu_single" "yes")
9906 (const_string "single") (const_string "double")))
9907 (set_attr "needs_delay_slot" "yes")])
9909 (define_expand "call_value_pop"
9910 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
9911 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
9912 (match_operand 2 "" "")))
9913 (match_operand 3 "" "")
9914 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
9915 (match_operand 4 "" "")))])]
9923 gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3]));
9924 cookie_rtx = operands[3];
9925 cookie = INTVAL (cookie_rtx);
9926 func = XEXP (operands[1], 0);
9930 if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func))
9932 rtx reg = gen_reg_rtx (Pmode);
9934 emit_insn (gen_symGOTPLT2reg (reg, func));
9938 func = legitimize_pic_address (func, Pmode, 0);
9941 r0 = gen_rtx_REG (SImode, R0_REG);
9942 r1 = gen_rtx_REG (SImode, R1_REG);
9944 /* Since such a call function may use all call-clobbered
9945 registers, we force a mode switch earlier, so that we don't
9946 run out of registers when adjusting fpscr for the call. */
9947 emit_insn (gen_force_mode_for_call ());
9949 operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
9951 operands[1] = force_reg (SImode, operands[1]);
9953 emit_move_insn (r0, func);
9954 emit_move_insn (r1, cookie_rtx);
9956 if (cookie & CALL_COOKIE_RET_TRAMP (1))
9957 emit_call_insn (gen_call_value_pop_compact_rettramp
9958 (operands[0], operands[1], operands[2],
9959 operands[3], operands[4]));
9961 emit_call_insn (gen_call_value_pop_compact
9962 (operands[0], operands[1], operands[2],
9963 operands[3], operands[4]));
9968 (define_expand "sibcall_epilogue"
9972 sh_expand_epilogue (true);
9973 if (TARGET_SHCOMPACT)
9978 /* If epilogue clobbers r0, preserve it in macl. */
9979 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9980 if ((set = single_set (insn))
9981 && REG_P (SET_DEST (set))
9982 && REGNO (SET_DEST (set)) == R0_REG)
9984 rtx r0 = gen_rtx_REG (SImode, R0_REG);
9985 rtx tmp = gen_rtx_REG (SImode, MACL_REG);
9987 /* We can't tell at this point whether the sibcall is a
9988 sibcall_compact and, if it is, whether it uses r0 or
9989 mach as operand 2, so let the instructions that
9990 preserve r0 be optimized away if r0 turns out to be
9992 emit_insn_before (gen_rtx_SET (SImode, tmp, r0), insn);
9993 emit_move_insn (r0, tmp);
10000 (define_insn "indirect_jump_compact"
10002 (match_operand:SI 0 "arith_reg_operand" "r"))]
10005 [(set_attr "needs_delay_slot" "yes")
10006 (set_attr "type" "jump_ind")])
10008 (define_expand "indirect_jump"
10010 (match_operand 0 "register_operand" ""))]
10013 if (GET_MODE (operands[0]) != Pmode)
10014 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
10017 ;; The use of operand 1 / 2 helps us distinguish case table jumps
10018 ;; which can be present in structured code from indirect jumps which can not
10019 ;; be present in structured code. This allows -fprofile-arcs to work.
10021 ;; For SH1 processors.
10022 (define_insn "casesi_jump_1"
10024 (match_operand:SI 0 "register_operand" "r"))
10025 (use (label_ref (match_operand 1 "" "")))]
10028 [(set_attr "needs_delay_slot" "yes")
10029 (set_attr "type" "jump_ind")])
10031 ;; For all later processors.
10032 (define_insn "casesi_jump_2"
10033 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
10034 (label_ref (match_operand 1 "" ""))))
10035 (use (label_ref (match_operand 2 "" "")))]
10037 && (! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn)"
10039 [(set_attr "needs_delay_slot" "yes")
10040 (set_attr "type" "jump_ind")])
10042 (define_insn "casesi_jump_media"
10043 [(set (pc) (match_operand 0 "target_reg_operand" "b"))
10044 (use (label_ref (match_operand 1 "" "")))]
10047 [(set_attr "type" "jump_media")])
10049 ;; Call subroutine returning any type.
10050 ;; ??? This probably doesn't work.
10051 (define_expand "untyped_call"
10052 [(parallel [(call (match_operand 0 "" "")
10054 (match_operand 1 "" "")
10055 (match_operand 2 "" "")])]
10056 "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA"
10058 if (! TARGET_SHMEDIA)
10060 /* RA does not know that the call sets the function value registers.
10061 We avoid problems by claiming that those registers are clobbered
10063 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10065 rtx set = XVECEXP (operands[2], 0, i);
10066 emit_clobber (SET_SRC (set));
10070 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
10072 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
10074 rtx set = XVECEXP (operands[2], 0, i);
10075 emit_move_insn (SET_DEST (set), SET_SRC (set));
10078 /* The optimizer does not know that the call sets the function value
10079 registers we stored in the result block. We avoid problems by
10080 claiming that all hard registers are used and clobbered at this
10082 emit_insn (gen_blockage ());
10087 ;; ------------------------------------------------------------------------
10089 ;; ------------------------------------------------------------------------
10091 (define_insn "dect"
10092 [(set (reg:SI T_REG)
10093 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
10094 (set (match_operand:SI 0 "arith_reg_dest" "=r")
10095 (plus:SI (match_dup 1) (const_int -1)))]
10098 [(set_attr "type" "arith")])
10105 ;; Load address of a label. This is only generated by the casesi expand,
10106 ;; and by machine_dependent_reorg (fixing up fp moves).
10107 ;; This must use unspec, because this only works for labels that are
10109 (define_insn "mova"
10110 [(set (reg:SI R0_REG)
10111 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
10114 [(set_attr "in_delay_slot" "no")
10115 (set_attr "type" "arith")])
10117 ;; machine_dependent_reorg will make this a `mova'.
10118 (define_insn "mova_const"
10119 [(set (reg:SI R0_REG)
10120 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
10123 [(set_attr "in_delay_slot" "no")
10124 (set_attr "type" "arith")])
10126 (define_expand "GOTaddr2picreg"
10127 [(set (reg:SI R0_REG)
10128 (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
10130 (set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
10131 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10134 if (TARGET_VXWORKS_RTP)
10136 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
10137 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
10138 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
10142 operands[0] = gen_rtx_REG (Pmode, PIC_REG);
10143 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
10145 if (TARGET_SHMEDIA)
10147 rtx tr = gen_rtx_REG (Pmode, TR0_REG);
10148 rtx pic = operands[0];
10149 rtx lab = PATTERN (gen_call_site ());
10152 equiv = operands[1];
10153 operands[1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[1], lab),
10154 UNSPEC_PCREL_SYMOFF);
10155 operands[1] = gen_rtx_CONST (Pmode, operands[1]);
10157 if (Pmode == SImode)
10159 emit_insn (gen_movsi_const (pic, operands[1]));
10160 emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab)));
10164 emit_insn (gen_movdi_const (pic, operands[1]));
10165 emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab)));
10168 insn = emit_move_insn (operands[0], tr);
10170 set_unique_reg_note (insn, REG_EQUAL, equiv);
10176 ;; A helper for GOTaddr2picreg to finish up the initialization of the
10178 (define_expand "vxworks_picreg"
10179 [(set (reg:SI PIC_REG)
10180 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
10181 (set (reg:SI R0_REG)
10182 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
10183 (set (reg:SI PIC_REG)
10184 (mem:SI (reg:SI PIC_REG)))
10185 (set (reg:SI PIC_REG)
10186 (mem:SI (plus:SI (reg:SI PIC_REG)
10187 (reg:SI R0_REG))))]
10188 "TARGET_VXWORKS_RTP")
10190 (define_insn "*ptb"
10191 [(set (match_operand 0 "target_reg_operand" "=b")
10192 (const (unspec [(match_operand 1 "" "Csy")]
10193 UNSPEC_DATALABEL)))]
10194 "TARGET_SHMEDIA && flag_pic
10195 && satisfies_constraint_Csy (operands[1])"
10196 "ptb/u datalabel %1, %0"
10197 [(set_attr "type" "ptabs_media")
10198 (set_attr "length" "*")])
10200 (define_insn "ptrel_si"
10201 [(set (match_operand:SI 0 "target_reg_operand" "=b")
10202 (plus:SI (match_operand:SI 1 "register_operand" "r")
10204 (match_operand:SI 2 "" "")]
10206 "%O2: ptrel/u %1, %0"
10207 [(set_attr "type" "ptabs_media")])
10209 (define_insn "ptrel_di"
10210 [(set (match_operand:DI 0 "target_reg_operand" "=b")
10211 (plus:DI (match_operand:DI 1 "register_operand" "r")
10213 (match_operand:DI 2 "" "")]
10215 "%O2: ptrel/u %1, %0"
10216 [(set_attr "type" "ptabs_media")])
10218 (define_expand "builtin_setjmp_receiver"
10219 [(match_operand 0 "" "")]
10222 emit_insn (gen_GOTaddr2picreg ());
10226 (define_expand "call_site"
10227 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
10230 static HOST_WIDE_INT i = 0;
10231 operands[0] = GEN_INT (i);
10235 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
10236 ;; in symGOT_load expand.
10237 (define_insn_and_split "chk_guard_add"
10238 [(set (match_operand:SI 0 "register_operand" "=&r")
10239 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
10244 "TARGET_SH1 && reload_completed"
10245 [(set (match_dup 0) (reg:SI PIC_REG))
10246 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
10248 [(set_attr "type" "arith")])
10250 (define_expand "sym_label2reg"
10251 [(set (match_operand:SI 0 "" "")
10252 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
10253 (const (plus:SI (match_operand:SI 2 "" "")
10258 (define_expand "symGOT_load"
10259 [(set (match_dup 2) (match_operand 1 "" ""))
10260 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
10261 (set (match_operand 0 "" "") (mem (match_dup 3)))]
10266 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10267 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
10269 if (TARGET_SHMEDIA)
10271 rtx reg = operands[2];
10273 if (Pmode == DImode)
10276 emit_insn (gen_movdi_const_32bit (reg, operands[1]));
10278 emit_insn (gen_movdi_const_16bit (reg, operands[1]));
10283 emit_insn (gen_movsi_const (reg, operands[1]));
10285 emit_insn (gen_movsi_const_16bit (reg, operands[1]));
10289 emit_move_insn (operands[2], operands[1]);
10291 /* When stack protector inserts codes after the result is set to
10292 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
10293 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
10294 when rX is a GOT address for the guard symbol. Ugly but doesn't
10295 matter because this is a rare situation. */
10296 if (!TARGET_SHMEDIA
10297 && flag_stack_protect
10298 && GET_CODE (operands[1]) == CONST
10299 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
10300 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
10301 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
10302 "__stack_chk_guard") == 0)
10303 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
10305 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
10306 gen_rtx_REG (Pmode, PIC_REG)));
10308 /* N.B. This is not constant for a GOTPLT relocation. */
10309 mem = gen_rtx_MEM (Pmode, operands[3]);
10310 MEM_NOTRAP_P (mem) = 1;
10311 /* ??? Should we have a special alias set for the GOT? */
10312 emit_move_insn (operands[0], mem);
10317 (define_expand "sym2GOT"
10318 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
10322 (define_expand "symGOT2reg"
10323 [(match_operand 0 "" "") (match_operand 1 "" "")]
10328 gotsym = gen_sym2GOT (operands[1]);
10329 PUT_MODE (gotsym, Pmode);
10330 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
10332 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
10337 (define_expand "symGOTPLT2reg"
10338 [(match_operand 0 "" "") (match_operand 1 "" "")]
10341 rtx pltsym = gen_rtx_CONST (Pmode,
10342 gen_rtx_UNSPEC (Pmode,
10343 gen_rtvec (1, operands[1]),
10345 emit_insn (gen_symGOT_load (operands[0], pltsym));
10349 (define_expand "sym2GOTOFF"
10350 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
10354 (define_expand "symGOTOFF2reg"
10355 [(match_operand 0 "" "") (match_operand 1 "" "")]
10358 rtx gotoffsym, insn;
10359 rtx t = (!can_create_pseudo_p ()
10361 : gen_reg_rtx (GET_MODE (operands[0])));
10363 gotoffsym = gen_sym2GOTOFF (operands[1]);
10364 PUT_MODE (gotoffsym, Pmode);
10365 emit_move_insn (t, gotoffsym);
10366 insn = emit_move_insn (operands[0],
10367 gen_rtx_PLUS (Pmode, t,
10368 gen_rtx_REG (Pmode, PIC_REG)));
10370 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
10375 (define_expand "symPLT_label2reg"
10376 [(set (match_operand:SI 0 "" "")
10379 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
10380 (const:SI (plus:SI (match_operand:SI 2 "" "")
10381 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
10382 ;; Even though the PIC register is not really used by the call
10383 ;; sequence in which this is expanded, the PLT code assumes the PIC
10384 ;; register is set, so we must not skip its initialization. Since
10385 ;; we only use this expand as part of calling sequences, and never
10386 ;; to take the address of a function, this is the best point to
10387 ;; insert the (use). Using the PLT to take the address of a
10388 ;; function would be wrong, not only because the PLT entry could
10389 ;; then be called from a function that doesn't initialize the PIC
10390 ;; register to the proper GOT, but also because pointers to the
10391 ;; same function might not compare equal, should they be set by
10392 ;; different shared libraries.
10393 (use (reg:SI PIC_REG))]
10397 (define_expand "sym2PIC"
10398 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
10402 ;; -------------------------------------------------------------------------
10403 ;; TLS code generation.
10405 ;; FIXME: The multi-insn asm blocks should be converted to use
10406 ;; define_insn_and_split.
10407 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
10408 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
10411 (define_insn "tls_global_dynamic"
10412 [(set (match_operand:SI 0 "register_operand" "=&z")
10413 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10416 (use (reg:SI FPSCR_MODES_REG))
10417 (use (reg:SI PIC_REG))
10418 (clobber (reg:SI PR_REG))
10419 (clobber (scratch:SI))]
10422 return "mov.l 1f,r4" "\n"
10424 " mov.l 2f,r1" "\n"
10431 "1: .long %a1@TLSGD" "\n"
10432 "2: .long __tls_get_addr@PLT" "\n"
10435 [(set_attr "type" "tls_load")
10436 (set_attr "length" "26")])
10438 (define_insn "tls_local_dynamic"
10439 [(set (match_operand:SI 0 "register_operand" "=&z")
10440 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
10443 (use (reg:SI FPSCR_MODES_REG))
10444 (use (reg:SI PIC_REG))
10445 (clobber (reg:SI PR_REG))
10446 (clobber (scratch:SI))]
10449 return "mov.l 1f,r4" "\n"
10451 " mov.l 2f,r1" "\n"
10458 "1: .long %a1@TLSLDM" "\n"
10459 "2: .long __tls_get_addr@PLT" "\n"
10462 [(set_attr "type" "tls_load")
10463 (set_attr "length" "26")])
10465 (define_expand "sym2DTPOFF"
10466 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
10470 (define_expand "symDTPOFF2reg"
10471 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
10475 rtx t = (!can_create_pseudo_p ()
10477 : gen_reg_rtx (GET_MODE (operands[0])));
10479 dtpoffsym = gen_sym2DTPOFF (operands[1]);
10480 PUT_MODE (dtpoffsym, Pmode);
10481 emit_move_insn (t, dtpoffsym);
10482 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
10486 (define_expand "sym2GOTTPOFF"
10487 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
10491 (define_insn "tls_initial_exec"
10492 [(set (match_operand:SI 0 "register_operand" "=&r")
10493 (unspec:SI [(match_operand:SI 1 "" "")]
10495 (use (reg:SI GBR_REG))
10496 (use (reg:SI PIC_REG))
10497 (clobber (reg:SI R0_REG))]
10500 return "mov.l 1f,r0" "\n"
10502 " mov.l @(r0,r12),r0" "\n"
10506 "1: .long %a1" "\n"
10509 [(set_attr "type" "tls_load")
10510 (set_attr "length" "16")])
10512 (define_expand "sym2TPOFF"
10513 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
10517 (define_expand "symTPOFF2reg"
10518 [(match_operand 0 "" "") (match_operand 1 "" "")]
10523 tpoffsym = gen_sym2TPOFF (operands[1]);
10524 PUT_MODE (tpoffsym, Pmode);
10525 emit_move_insn (operands[0], tpoffsym);
10529 ;;------------------------------------------------------------------------------
10530 ;; Thread pointer getter and setter.
10532 ;; On SH the thread pointer is kept in the GBR.
10533 ;; These patterns are usually expanded from the respective built-in functions.
10534 (define_expand "get_thread_pointersi"
10535 [(set (match_operand:SI 0 "register_operand") (reg:SI GBR_REG))]
10538 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
10539 (define_insn "store_gbr"
10540 [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GBR_REG))]
10543 [(set_attr "type" "tls_load")])
10545 (define_expand "set_thread_pointersi"
10546 [(set (reg:SI GBR_REG)
10547 (unspec_volatile:SI [(match_operand:SI 0 "register_operand")]
10551 (define_insn "load_gbr"
10552 [(set (reg:SI GBR_REG)
10553 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
10557 [(set_attr "type" "move")])
10559 ;;------------------------------------------------------------------------------
10560 ;; Thread pointer relative memory loads and stores.
10562 ;; On SH there are GBR displacement address modes which can be utilized to
10563 ;; access memory behind the thread pointer.
10564 ;; Since we do not allow using GBR for general purpose memory accesses, these
10565 ;; GBR addressing modes are formed by the combine pass.
10566 ;; This could be done with fewer patterns than below by using a mem predicate
10567 ;; for the GBR mem, but then reload would try to reload addresses with a
10568 ;; zero displacement for some strange reason.
10570 (define_insn "*mov<mode>_gbr_load"
10571 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10572 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10573 (match_operand:QIHISI 1 "gbr_displacement"))))]
10575 "mov.<bwl> @(%O1,gbr),%0"
10576 [(set_attr "type" "load")])
10578 (define_insn "*mov<mode>_gbr_load"
10579 [(set (match_operand:QIHISI 0 "register_operand" "=z")
10580 (mem:QIHISI (reg:SI GBR_REG)))]
10582 "mov.<bwl> @(0,gbr),%0"
10583 [(set_attr "type" "load")])
10585 (define_insn "*mov<mode>_gbr_load"
10586 [(set (match_operand:SI 0 "register_operand" "=z")
10588 (mem:QIHI (plus:SI (reg:SI GBR_REG)
10589 (match_operand:QIHI 1 "gbr_displacement")))))]
10591 "mov.<bw> @(%O1,gbr),%0"
10592 [(set_attr "type" "load")])
10594 (define_insn "*mov<mode>_gbr_load"
10595 [(set (match_operand:SI 0 "register_operand" "=z")
10596 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
10598 "mov.<bw> @(0,gbr),%0"
10599 [(set_attr "type" "load")])
10601 (define_insn "*mov<mode>_gbr_store"
10602 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
10603 (match_operand:QIHISI 0 "gbr_displacement")))
10604 (match_operand:QIHISI 1 "register_operand" "z"))]
10606 "mov.<bwl> %1,@(%O0,gbr)"
10607 [(set_attr "type" "store")])
10609 (define_insn "*mov<mode>_gbr_store"
10610 [(set (mem:QIHISI (reg:SI GBR_REG))
10611 (match_operand:QIHISI 0 "register_operand" "z"))]
10613 "mov.<bwl> %0,@(0,gbr)"
10614 [(set_attr "type" "store")])
10616 ;; DImode memory accesses have to be split in two SImode accesses.
10617 ;; Split them before reload, so that it gets a better chance to figure out
10618 ;; how to deal with the R0 restriction for the individual SImode accesses.
10619 ;; Do not match this insn during or after reload because it can't be split
10621 (define_insn_and_split "*movdi_gbr_load"
10622 [(set (match_operand:DI 0 "register_operand")
10623 (match_operand:DI 1 "gbr_address_mem"))]
10624 "TARGET_SH1 && can_create_pseudo_p ()"
10627 [(set (match_dup 3) (match_dup 5))
10628 (set (match_dup 4) (match_dup 6))]
10630 /* Swap low/high part load order on little endian, so that the result reg
10631 of the second load can be used better. */
10632 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
10633 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10634 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10635 operands[4 - off] = gen_highpart (SImode, operands[0]);
10636 operands[6 - off] = gen_highpart (SImode, operands[1]);
10639 (define_insn_and_split "*movdi_gbr_store"
10640 [(set (match_operand:DI 0 "gbr_address_mem")
10641 (match_operand:DI 1 "register_operand"))]
10642 "TARGET_SH1 && can_create_pseudo_p ()"
10645 [(set (match_dup 3) (match_dup 5))
10646 (set (match_dup 4) (match_dup 6))]
10648 /* Swap low/high part store order on big endian, so that stores of function
10649 call results can save a reg copy. */
10650 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
10651 operands[3 + off] = gen_lowpart (SImode, operands[0]);
10652 operands[5 + off] = gen_lowpart (SImode, operands[1]);
10653 operands[4 - off] = gen_highpart (SImode, operands[0]);
10654 operands[6 - off] = gen_highpart (SImode, operands[1]);
10657 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
10658 ;; in particular when the displacements are in the range of the regular move
10659 ;; insns. Thus, in the first split pass after the combine pass we search
10660 ;; for missed opportunities and try to fix them up ourselves.
10661 ;; If an equivalent GBR address can be determined the load / store is split
10662 ;; into one of the GBR load / store patterns.
10663 ;; All of that must happen before reload (GBR address modes use R0 as the
10664 ;; other operand) and there's no point of doing it if the GBR is not
10665 ;; referenced in a function at all.
10667 [(set (match_operand:QIHISIDI 0 "register_operand")
10668 (match_operand:QIHISIDI 1 "memory_operand"))]
10669 "TARGET_SH1 && !reload_in_progress && !reload_completed
10670 && df_regs_ever_live_p (GBR_REG)"
10671 [(set (match_dup 0) (match_dup 1))]
10673 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10674 if (gbr_mem != NULL_RTX)
10675 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10681 [(set (match_operand:SI 0 "register_operand")
10682 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10683 "TARGET_SH1 && !reload_in_progress && !reload_completed
10684 && df_regs_ever_live_p (GBR_REG)"
10685 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
10687 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10688 if (gbr_mem != NULL_RTX)
10689 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10694 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
10695 ;; Split those so that a GBR load can be used.
10697 [(set (match_operand:SI 0 "register_operand")
10698 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
10699 "TARGET_SH2A && !reload_in_progress && !reload_completed
10700 && df_regs_ever_live_p (GBR_REG)"
10701 [(set (match_dup 2) (match_dup 1))
10702 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
10704 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
10705 if (gbr_mem != NULL_RTX)
10707 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
10708 operands[1] = replace_equiv_address (operands[1], gbr_mem);
10715 [(set (match_operand:QIHISIDI 0 "memory_operand")
10716 (match_operand:QIHISIDI 1 "register_operand"))]
10717 "TARGET_SH1 && !reload_in_progress && !reload_completed
10718 && df_regs_ever_live_p (GBR_REG)"
10719 [(set (match_dup 0) (match_dup 1))]
10721 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
10722 if (gbr_mem != NULL_RTX)
10723 operands[0] = replace_equiv_address (operands[0], gbr_mem);
10728 ;;------------------------------------------------------------------------------
10729 ;; case instruction for switch statements.
10731 ;; operand 0 is index
10732 ;; operand 1 is the minimum bound
10733 ;; operand 2 is the maximum bound - minimum bound + 1
10734 ;; operand 3 is CODE_LABEL for the table;
10735 ;; operand 4 is the CODE_LABEL to go to if index out of range.
10736 (define_expand "casesi"
10737 [(match_operand:SI 0 "arith_reg_operand" "")
10738 (match_operand:SI 1 "arith_reg_operand" "")
10739 (match_operand:SI 2 "arith_reg_operand" "")
10740 (match_operand 3 "" "") (match_operand 4 "" "")]
10743 rtx reg = gen_reg_rtx (SImode);
10744 rtx reg2 = gen_reg_rtx (SImode);
10745 if (TARGET_SHMEDIA)
10747 rtx reg = gen_reg_rtx (DImode);
10748 rtx reg2 = gen_reg_rtx (DImode);
10749 rtx reg3 = gen_reg_rtx (Pmode);
10750 rtx reg4 = gen_reg_rtx (Pmode);
10751 rtx reg5 = gen_reg_rtx (Pmode);
10754 operands[0] = convert_modes (DImode, SImode, operands[0], 0);
10755 operands[1] = convert_modes (DImode, SImode, operands[1], 0);
10756 operands[2] = convert_modes (DImode, SImode, operands[2], 1);
10758 test = gen_rtx_GT (VOIDmode, operands[1], operands[0]);
10759 emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0],
10761 emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1]));
10762 test = gen_rtx_GTU (VOIDmode, reg, operands[2]);
10763 emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4]));
10764 emit_insn (gen_casesi_shift_media (reg2, reg, operands[3]));
10765 emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF
10766 (Pmode, operands[3])));
10767 /* Messy: can we subreg to clean this up? */
10768 if (Pmode == DImode)
10769 load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]);
10771 load = gen_casesi_load_media (reg4,
10772 gen_rtx_SUBREG (DImode, reg3, 0),
10773 reg2, operands[3]);
10774 PUT_MODE (SET_SRC (load), Pmode);
10776 /* ??? The following add could be eliminated if we used ptrel. */
10777 emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4));
10778 emit_jump_insn (gen_casesi_jump_media (reg5, operands[3]));
10782 operands[1] = copy_to_mode_reg (SImode, operands[1]);
10783 operands[2] = copy_to_mode_reg (SImode, operands[2]);
10784 /* If optimizing, casesi_worker depends on the mode of the instruction
10785 before label it 'uses' - operands[3]. */
10786 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
10788 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
10790 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
10792 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
10793 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
10794 operands[3], but to lab. We will fix this up in
10795 machine_dependent_reorg. */
10800 (define_expand "casesi_0"
10801 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
10802 (set (match_dup 4) (minus:SI (match_dup 4)
10803 (match_operand:SI 1 "arith_operand" "")))
10804 (set (reg:SI T_REG)
10805 (gtu:SI (match_dup 4)
10806 (match_operand:SI 2 "arith_reg_operand" "")))
10808 (if_then_else (ne (reg:SI T_REG)
10810 (label_ref (match_operand 3 "" ""))
10815 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
10816 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
10817 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
10818 (define_insn "casesi_worker_0"
10819 [(set (match_operand:SI 0 "register_operand" "=r,r")
10820 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
10821 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10822 (clobber (match_scratch:SI 3 "=X,1"))
10823 (clobber (match_scratch:SI 4 "=&z,z"))]
10828 [(set (match_operand:SI 0 "register_operand" "")
10829 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10830 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10831 (clobber (match_scratch:SI 3 ""))
10832 (clobber (match_scratch:SI 4 ""))]
10833 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
10834 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10835 (parallel [(set (match_dup 0)
10836 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10837 (label_ref (match_dup 2))] UNSPEC_CASESI))
10838 (clobber (match_dup 3))])
10839 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
10841 if (GET_CODE (operands[2]) == CODE_LABEL)
10842 LABEL_NUSES (operands[2])++;
10846 [(set (match_operand:SI 0 "register_operand" "")
10847 (unspec:SI [(match_operand:SI 1 "register_operand" "")
10848 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10849 (clobber (match_scratch:SI 3 ""))
10850 (clobber (match_scratch:SI 4 ""))]
10851 "TARGET_SH2 && reload_completed"
10852 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
10853 (parallel [(set (match_dup 0)
10854 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
10855 (label_ref (match_dup 2))] UNSPEC_CASESI))
10856 (clobber (match_dup 3))])]
10858 if (GET_CODE (operands[2]) == CODE_LABEL)
10859 LABEL_NUSES (operands[2])++;
10862 (define_insn "casesi_worker_1"
10863 [(set (match_operand:SI 0 "register_operand" "=r,r")
10864 (unspec:SI [(reg:SI R0_REG)
10865 (match_operand:SI 1 "register_operand" "0,r")
10866 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
10867 (clobber (match_scratch:SI 3 "=X,1"))]
10870 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
10872 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10874 switch (GET_MODE (diff_vec))
10877 return "shll2 %1" "\n"
10878 " mov.l @(r0,%1),%0";
10880 return "add %1,%1" "\n"
10881 " mov.w @(r0,%1),%0";
10883 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10884 return "mov.b @(r0,%1),%0" "\n"
10887 return "mov.b @(r0,%1),%0";
10890 gcc_unreachable ();
10893 [(set_attr "length" "4")])
10895 (define_insn "casesi_worker_2"
10896 [(set (match_operand:SI 0 "register_operand" "=r,r")
10897 (unspec:SI [(reg:SI R0_REG)
10898 (match_operand:SI 1 "register_operand" "0,r")
10899 (label_ref (match_operand 2 "" ""))
10900 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
10901 (clobber (match_operand:SI 4 "" "=X,1"))]
10902 "TARGET_SH2 && reload_completed && flag_pic"
10904 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
10905 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10907 switch (GET_MODE (diff_vec))
10910 return "shll2 %1" "\n"
10912 " mova %O3,r0" "\n"
10913 " mov.l @(r0,%1),%0";
10915 return "add %1,%1" "\n"
10917 " mova %O3,r0" "\n"
10918 " mov.w @(r0,%1),%0";
10920 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10921 return "add r0,%1" "\n"
10922 " mova %O3,r0" "\n"
10923 " mov.b @(r0,%1),%0" "\n"
10926 return "add r0,%1" "\n"
10927 " mova %O3,r0" "\n"
10928 " mov.b @(r0,%1),%0";
10930 gcc_unreachable ();
10933 [(set_attr "length" "8")])
10935 (define_insn "casesi_shift_media"
10936 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
10937 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
10938 (unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
10942 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
10944 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10946 switch (GET_MODE (diff_vec))
10949 return "shlli %1, 2, %0";
10951 return "shlli %1, 1, %0";
10953 if (rtx_equal_p (operands[0], operands[1]))
10955 return "add %1, r63, %0";
10957 gcc_unreachable ();
10960 [(set_attr "type" "arith_media")])
10962 (define_insn "casesi_load_media"
10963 [(set (match_operand 0 "any_arith_reg_dest" "=r")
10964 (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r")
10965 (match_operand:DI 2 "arith_reg_operand" "r")
10966 (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))]
10969 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[3])));
10971 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
10973 switch (GET_MODE (diff_vec))
10976 return "ldx.l %1, %2, %0";
10979 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10980 return "ldx.uw %1, %2, %0";
10982 return "ldx.w %1, %2, %0";
10984 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
10985 return "ldx.ub %1, %2, %0";
10986 return "ldx.b %1, %2, %0";
10988 gcc_unreachable ();
10991 [(set_attr "type" "load_media")])
10993 (define_expand "simple_return"
10995 "sh_can_use_simple_return_p ()")
10997 (define_expand "return"
10999 "reload_completed && epilogue_completed"
11001 if (TARGET_SHMEDIA)
11003 emit_jump_insn (gen_return_media ());
11007 if (TARGET_SHCOMPACT
11008 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))
11010 emit_jump_insn (gen_shcompact_return_tramp ());
11015 (define_insn "*<code>_i"
11017 "TARGET_SH1 && ! (TARGET_SHCOMPACT
11018 && (crtl->args.info.call_cookie
11019 & CALL_COOKIE_RET_TRAMP (1)))
11020 && reload_completed
11021 && ! sh_cfun_trap_exit_p ()"
11023 if (TARGET_SH2A && (dbr_sequence_length () == 0)
11024 && !current_function_interrupt)
11029 [(set_attr "type" "return")
11030 (set_attr "needs_delay_slot" "yes")])
11032 ;; trapa has no delay slot.
11033 (define_insn "*return_trapa"
11035 "TARGET_SH1 && !TARGET_SHCOMPACT
11036 && reload_completed"
11038 [(set_attr "type" "return")])
11040 (define_expand "shcompact_return_tramp"
11043 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11045 rtx reg = gen_rtx_REG (Pmode, R0_REG);
11047 function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC);
11048 emit_jump_insn (gen_shcompact_return_tramp_i ());
11052 (define_insn "shcompact_return_tramp_i"
11053 [(parallel [(return) (use (reg:SI R0_REG))])]
11055 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))"
11057 [(set_attr "type" "jump_ind")
11058 (set_attr "needs_delay_slot" "yes")])
11060 (define_insn "return_media_i"
11061 [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])]
11062 "TARGET_SHMEDIA && reload_completed"
11064 [(set_attr "type" "jump_media")])
11066 (define_insn "return_media_rte"
11068 "TARGET_SHMEDIA && reload_completed && current_function_interrupt"
11070 [(set_attr "type" "jump_media")])
11072 (define_expand "return_media"
11074 "TARGET_SHMEDIA && reload_completed"
11076 int tr_regno = sh_media_register_for_return ();
11079 if (current_function_interrupt)
11081 emit_jump_insn (gen_return_media_rte ());
11086 rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG);
11088 gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]);
11089 tr_regno = TR0_REG;
11090 tr = gen_rtx_REG (Pmode, tr_regno);
11091 emit_move_insn (tr, r18);
11094 tr = gen_rtx_REG (Pmode, tr_regno);
11096 emit_jump_insn (gen_return_media_i (tr));
11100 (define_insn "shcompact_preserve_incoming_args"
11101 [(set (match_operand:SI 0 "register_operand" "+r")
11102 (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
11105 [(set_attr "length" "0")])
11107 (define_insn "shcompact_incoming_args"
11108 [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
11109 (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
11110 (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
11111 (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
11112 (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
11113 (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
11114 (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
11115 (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
11116 (set (mem:BLK (reg:SI MACL_REG))
11117 (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
11118 (use (reg:SI R0_REG))
11119 (clobber (reg:SI R0_REG))
11120 (clobber (reg:SI MACL_REG))
11121 (clobber (reg:SI MACH_REG))
11122 (clobber (reg:SI PR_REG))]
11125 [(set_attr "needs_delay_slot" "yes")])
11127 (define_insn "shmedia_save_restore_regs_compact"
11128 [(set (reg:SI SP_REG)
11129 (plus:SI (reg:SI SP_REG)
11130 (match_operand:SI 0 "immediate_operand" "i")))
11131 (use (reg:SI R0_REG))
11132 (clobber (reg:SI PR_REG))]
11134 && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST ()
11135 || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())"
11137 [(set_attr "needs_delay_slot" "yes")])
11139 (define_expand "prologue"
11143 sh_expand_prologue ();
11147 (define_expand "epilogue"
11151 sh_expand_epilogue (false);
11153 || (TARGET_SHCOMPACT
11154 && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))))
11156 emit_jump_insn (gen_return ());
11161 (define_expand "eh_return"
11162 [(use (match_operand 0 "register_operand" ""))]
11165 rtx ra = operands[0];
11167 if (TARGET_SHMEDIA64)
11168 emit_insn (gen_eh_set_ra_di (ra));
11170 emit_insn (gen_eh_set_ra_si (ra));
11175 ;; Clobber the return address on the stack. We can't expand this
11176 ;; until we know where it will be put in the stack frame.
11178 (define_insn "eh_set_ra_si"
11179 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
11181 (clobber (match_scratch:SI 1 "=&r"))]
11182 "! TARGET_SHMEDIA64"
11185 (define_insn "eh_set_ra_di"
11186 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
11188 (clobber (match_scratch:DI 1 "=&r"))]
11193 [(unspec_volatile [(match_operand 0 "register_operand" "")]
11195 (clobber (match_scratch 1 ""))]
11199 sh_set_return_address (operands[0], operands[1]);
11203 (define_insn "blockage"
11204 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
11207 [(set_attr "length" "0")])
11209 ;; Define movml instructions for SH2A target. Currently they are
11210 ;; used to push and pop all banked registers only.
11212 (define_insn "movml_push_banked"
11213 [(set (match_operand:SI 0 "register_operand" "=r")
11214 (plus (match_dup 0) (const_int -32)))
11215 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
11216 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
11217 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
11218 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
11219 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
11220 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
11221 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
11222 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
11223 "TARGET_SH2A && REGNO (operands[0]) == 15"
11225 [(set_attr "in_delay_slot" "no")])
11227 (define_insn "movml_pop_banked"
11228 [(set (match_operand:SI 0 "register_operand" "=r")
11229 (plus (match_dup 0) (const_int 32)))
11230 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
11231 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
11232 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
11233 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
11234 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
11235 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
11236 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
11237 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
11238 "TARGET_SH2A && REGNO (operands[0]) == 15"
11240 [(set_attr "in_delay_slot" "no")])
11242 ;; ------------------------------------------------------------------------
11243 ;; Scc instructions
11244 ;; ------------------------------------------------------------------------
11246 (define_insn "movt"
11247 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11248 (match_operand:SI 1 "t_reg_operand"))]
11251 [(set_attr "type" "arith")])
11253 (define_insn "movrt"
11254 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11255 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11258 [(set_attr "type" "arith")])
11260 (define_expand "cstore4_media"
11261 [(set (match_operand:SI 0 "register_operand" "=r")
11262 (match_operator:SI 1 "sh_float_comparison_operator"
11263 [(match_operand 2 "logical_operand" "")
11264 (match_operand 3 "cmp_operand" "")]))]
11267 machine_mode mode = GET_MODE (operands[2]);
11268 enum rtx_code code = GET_CODE (operands[1]);
11270 if (mode == VOIDmode)
11271 mode = GET_MODE (operands[3]);
11272 if (operands[2] == const0_rtx)
11274 if (code == EQ || code == NE)
11275 operands[2] = operands[3], operands[3] = const0_rtx;
11278 operands[2] = force_reg (mode, operands[2]);
11279 if (operands[3] != const0_rtx)
11280 operands[3] = force_reg (mode, operands[3]);
11286 swap = invert = !FLOAT_MODE_P (mode);
11291 swap = FLOAT_MODE_P (mode), invert = !swap;
11296 swap = true, invert = false;
11303 swap = invert = false;
11307 swap = invert = true;
11311 gcc_unreachable ();
11316 std::swap (operands[2], operands[3]);
11317 code = swap_condition (code);
11322 rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
11323 code = reverse_condition (code);
11324 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11325 emit_insn (gen_cstore4_media (tem, operands[1],
11326 operands[2], operands[3]));
11329 operands[3] = const0_rtx;
11332 operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]);
11335 (define_expand "cstoresi4"
11336 [(set (match_operand:SI 0 "register_operand" "=r")
11337 (match_operator:SI 1 "comparison_operator"
11338 [(match_operand:SI 2 "cmpsi_operand" "")
11339 (match_operand:SI 3 "arith_operand" "")]))]
11340 "TARGET_SH1 || TARGET_SHMEDIA"
11342 if (TARGET_SHMEDIA)
11344 emit_insn (gen_cstore4_media (operands[0], operands[1],
11345 operands[2], operands[3]));
11349 if (sh_expand_t_scc (operands))
11352 if (! currently_expanding_to_rtl)
11355 sh_emit_compare_and_set (operands, SImode);
11359 (define_expand "cstoredi4"
11360 [(set (match_operand:SI 0 "register_operand" "=r")
11361 (match_operator:SI 1 "comparison_operator"
11362 [(match_operand:DI 2 "arith_operand" "")
11363 (match_operand:DI 3 "arith_operand" "")]))]
11364 "TARGET_SH2 || TARGET_SHMEDIA"
11366 if (TARGET_SHMEDIA)
11368 emit_insn (gen_cstore4_media (operands[0], operands[1],
11369 operands[2], operands[3]));
11373 if (sh_expand_t_scc (operands))
11376 if (! currently_expanding_to_rtl)
11379 sh_emit_compare_and_set (operands, DImode);
11383 ;; Move the complement of the T reg to a reg.
11384 ;; On SH2A the movrt insn can be used.
11385 ;; On anything else than SH2A this has to be done with multiple instructions.
11386 ;; One obvious way would be:
11391 ;; However, this puts pressure on r0 in most cases and thus the following is
11397 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
11398 ;; becomes a one instruction operation. Moreover, care must be taken that
11399 ;; the insn can still be combined with inverted compare and branch code
11400 ;; around it. On the other hand, if a function returns the complement of
11401 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
11402 ;; lead to better code.
11403 (define_expand "movnegt"
11404 [(set (match_operand:SI 0 "arith_reg_dest" "")
11405 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
11409 emit_insn (gen_movrt (operands[0], operands[1]));
11412 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
11413 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
11418 (define_insn_and_split "movrt_negc"
11419 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11420 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11421 (set (reg:SI T_REG) (const_int 1))
11422 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
11428 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
11433 [(set_attr "type" "arith")])
11435 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
11436 ;; pattern can be used by the combine pass. Using a scratch reg for the
11437 ;; -1 constant results in slightly better register allocations compared to
11438 ;; generating a pseudo reg before reload.
11439 (define_insn_and_split "*movrt_negc"
11440 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11441 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11442 (clobber (match_scratch:SI 2 "=r"))
11443 (clobber (reg:SI T_REG))]
11444 "TARGET_SH1 && ! TARGET_SH2A"
11449 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
11451 else if (reload_completed)
11453 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
11454 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
11461 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
11462 ;; clobber the T bit, which is useful when storing the T bit and the
11463 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
11464 ;; Usually we don't want this insn to be matched, except for cases where the
11465 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
11466 (define_insn_and_split "movrt_xor"
11467 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
11468 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
11469 (use (reg:SI T_REG))]
11472 "&& reload_completed"
11473 [(set (match_dup 0) (reg:SI T_REG))
11474 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
11476 ;; Use negc to store the T bit in a MSB of a reg in the following way:
11477 ;; T = 1: 0x80000000 -> reg
11478 ;; T = 0: 0x7FFFFFFF -> reg
11479 ;; This works because 0 - 0x80000000 = 0x80000000.
11481 ;; This insn must not match again after it has been split into the constant
11482 ;; load and negc. This is accomplished by the special negc insn that
11483 ;; has a use on the operand.
11484 (define_insn_and_split "*mov_t_msb_neg"
11485 [(set (match_operand:SI 0 "arith_reg_dest")
11486 (minus:SI (const_int -2147483648) ;; 0x80000000
11487 (match_operand 1 "t_reg_operand")))
11488 (clobber (reg:SI T_REG))]
11491 "&& can_create_pseudo_p ()"
11492 [(set (match_dup 2) (const_int -2147483648))
11493 (parallel [(set (match_dup 0) (minus:SI (neg:SI (match_dup 2))
11495 (clobber (reg:SI T_REG))
11496 (use (match_dup 2))])]
11498 operands[2] = gen_reg_rtx (SImode);
11501 (define_insn "*mov_t_msb_neg_negc"
11502 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11503 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
11504 (match_operand:SI 2 "t_reg_operand")))
11505 (clobber (reg:SI T_REG))
11506 (use (match_dup 1))]
11509 [(set_attr "type" "arith")])
11511 ;; These are essentially the same as above, but with the inverted T bit.
11512 ;; Combine recognizes the split patterns, but does not take them sometimes
11513 ;; if the T_REG clobber is specified. Instead it tries to split out the
11514 ;; T bit negation. Since these splits are supposed to be taken only by
11515 ;; combine, it will see the T_REG clobber of the *mov_t_msb_neg insn, so this
11518 [(set (match_operand:SI 0 "arith_reg_dest")
11519 (plus:SI (match_operand 1 "negt_reg_operand")
11520 (const_int 2147483647)))] ;; 0x7fffffff
11521 "TARGET_SH1 && can_create_pseudo_p ()"
11522 [(parallel [(set (match_dup 0)
11523 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11524 (clobber (reg:SI T_REG))])])
11527 [(set (match_operand:SI 0 "arith_reg_dest")
11528 (if_then_else:SI (match_operand 1 "t_reg_operand")
11529 (const_int 2147483647) ;; 0x7fffffff
11530 (const_int -2147483648)))] ;; 0x80000000
11531 "TARGET_SH1 && can_create_pseudo_p ()"
11532 [(parallel [(set (match_dup 0)
11533 (minus:SI (const_int -2147483648) (reg:SI T_REG)))
11534 (clobber (reg:SI T_REG))])])
11536 ;; The *negnegt pattern helps the combine pass to figure out how to fold
11537 ;; an explicit double T bit negation.
11538 (define_insn_and_split "*negnegt"
11539 [(set (reg:SI T_REG)
11540 (eq:SI (match_operand 0 "negt_reg_operand" "") (const_int 0)))]
11546 ;; Store T bit as all zeros or ones in a reg.
11547 (define_insn "mov_neg_si_t"
11548 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11549 (neg:SI (match_operand 1 "t_reg_operand" "")))]
11552 [(set_attr "type" "arith")])
11554 ;; Store negated T bit as all zeros or ones in a reg.
11555 ;; Use the following sequence:
11556 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
11557 ;; not Rn,Rn ! Rn = 0 - Rn
11559 [(set (match_operand:SI 0 "arith_reg_dest" "")
11560 (neg:SI (match_operand 1 "negt_reg_operand" "")))]
11562 [(set (match_dup 0) (neg:SI (reg:SI T_REG)))
11563 (set (match_dup 0) (not:SI (match_dup 0)))])
11565 ;; The *movtt pattern eliminates redundant T bit to T bit moves / tests.
11566 (define_insn_and_split "*movtt"
11567 [(set (reg:SI T_REG)
11568 (eq:SI (match_operand 0 "t_reg_operand" "") (const_int 1)))]
11574 ;; Invert the T bit.
11575 ;; On SH2A we can use the nott insn. On anything else this must be done with
11576 ;; multiple insns like:
11579 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
11580 ;; pass will look for this insn. Disallow using it if pseudos can't be
11582 (define_insn_and_split "nott"
11583 [(set (reg:SI T_REG)
11584 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
11585 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
11587 gcc_assert (TARGET_SH2A);
11590 "! TARGET_SH2A && can_create_pseudo_p ()"
11591 [(set (match_dup 0) (reg:SI T_REG))
11592 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
11594 operands[0] = gen_reg_rtx (SImode);
11597 ;; Store T bit as MSB in a reg.
11598 ;; T = 0: 0x00000000 -> reg
11599 ;; T = 1: 0x80000000 -> reg
11600 (define_insn_and_split "*movt_msb"
11601 [(set (match_operand:SI 0 "arith_reg_dest")
11602 (mult:SI (match_operand:SI 1 "t_reg_operand")
11603 (const_int -2147483648))) ;; 0xffffffff80000000
11604 (clobber (reg:SI T_REG))]
11608 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
11610 ;; Store inverted T bit as MSB in a reg.
11611 ;; T = 0: 0x80000000 -> reg
11612 ;; T = 1: 0x00000000 -> reg
11613 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
11614 ;; On non SH2A we resort to the following sequence:
11618 ;; The T bit value will be modified during the sequence, but the rotcr insn
11619 ;; will restore its original value.
11620 (define_insn_and_split "*negt_msb"
11621 [(set (match_operand:SI 0 "arith_reg_dest")
11622 (match_operand:SI 1 "negt_reg_shl31_operand"))]
11625 "&& can_create_pseudo_p ()"
11628 rtx tmp = gen_reg_rtx (SImode);
11632 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
11633 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
11637 emit_move_insn (tmp, get_t_reg_rtx ());
11638 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
11639 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
11644 ;; The *cset_zero patterns convert optimizations such as
11645 ;; "if (test) x = 0;"
11647 ;; "x &= -(test == 0);"
11648 ;; back to conditional branch sequences if zero-displacement branches
11650 ;; FIXME: These patterns can be removed when conditional execution patterns
11651 ;; are implemented, since ifcvt will not perform these optimizations if
11652 ;; conditional execution is supported.
11653 (define_insn "*cset_zero"
11654 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11655 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
11657 (match_operand:SI 2 "arith_reg_operand" "0")))]
11658 "TARGET_SH1 && TARGET_ZDCBRANCH"
11660 return "bf 0f" "\n"
11664 [(set_attr "type" "arith") ;; poor approximation
11665 (set_attr "length" "4")])
11667 (define_insn "*cset_zero"
11668 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11669 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
11670 (match_operand:SI 2 "arith_reg_operand" "0")
11672 "TARGET_SH1 && TARGET_ZDCBRANCH"
11674 int tval = sh_eval_treg_value (operands[1]);
11676 return "bt 0f" "\n"
11679 else if (tval == false)
11680 return "bf 0f" "\n"
11684 gcc_unreachable ();
11686 [(set_attr "type" "arith") ;; poor approximation
11687 (set_attr "length" "4")])
11689 (define_expand "cstoresf4"
11690 [(set (match_operand:SI 0 "register_operand" "=r")
11691 (match_operator:SI 1 "sh_float_comparison_operator"
11692 [(match_operand:SF 2 "arith_operand" "")
11693 (match_operand:SF 3 "arith_operand" "")]))]
11694 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
11696 if (TARGET_SHMEDIA)
11698 emit_insn (gen_cstore4_media (operands[0], operands[1],
11699 operands[2], operands[3]));
11703 if (! currently_expanding_to_rtl)
11706 sh_emit_compare_and_set (operands, SFmode);
11710 (define_expand "cstoredf4"
11711 [(set (match_operand:SI 0 "register_operand" "=r")
11712 (match_operator:SI 1 "sh_float_comparison_operator"
11713 [(match_operand:DF 2 "arith_operand" "")
11714 (match_operand:DF 3 "arith_operand" "")]))]
11715 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
11717 if (TARGET_SHMEDIA)
11719 emit_insn (gen_cstore4_media (operands[0], operands[1],
11720 operands[2], operands[3]));
11724 if (! currently_expanding_to_rtl)
11727 sh_emit_compare_and_set (operands, DFmode);
11731 ;; -------------------------------------------------------------------------
11732 ;; Instructions to cope with inline literal tables
11733 ;; -------------------------------------------------------------------------
11735 ;; 2 byte integer in line
11736 (define_insn "consttable_2"
11737 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11738 (match_operand 1 "" "")]
11742 if (operands[1] != const0_rtx)
11743 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
11746 [(set_attr "length" "2")
11747 (set_attr "in_delay_slot" "no")])
11749 ;; 4 byte integer in line
11750 (define_insn "consttable_4"
11751 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11752 (match_operand 1 "" "")]
11756 if (operands[1] != const0_rtx)
11758 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
11759 mark_symbol_refs_as_used (operands[0]);
11763 [(set_attr "length" "4")
11764 (set_attr "in_delay_slot" "no")])
11766 ;; 8 byte integer in line
11767 (define_insn "consttable_8"
11768 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
11769 (match_operand 1 "" "")]
11773 if (operands[1] != const0_rtx)
11774 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
11777 [(set_attr "length" "8")
11778 (set_attr "in_delay_slot" "no")])
11780 ;; 4 byte floating point
11781 (define_insn "consttable_sf"
11782 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
11783 (match_operand 1 "" "")]
11787 if (operands[1] != const0_rtx)
11790 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11791 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
11795 [(set_attr "length" "4")
11796 (set_attr "in_delay_slot" "no")])
11798 ;; 8 byte floating point
11799 (define_insn "consttable_df"
11800 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
11801 (match_operand 1 "" "")]
11805 if (operands[1] != const0_rtx)
11808 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
11809 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
11813 [(set_attr "length" "8")
11814 (set_attr "in_delay_slot" "no")])
11816 ;; Alignment is needed for some constant tables; it may also be added for
11817 ;; Instructions at the start of loops, or after unconditional branches.
11818 ;; ??? We would get more accurate lengths if we did instruction
11819 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
11820 ;; here is too conservative.
11822 ;; align to a two byte boundary
11823 (define_expand "align_2"
11824 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
11828 ;; Align to a four byte boundary.
11829 ;; align_4 and align_log are instructions for the starts of loops, or
11830 ;; after unconditional branches, which may take up extra room.
11831 (define_expand "align_4"
11832 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
11836 ;; Align to a cache line boundary.
11837 (define_insn "align_log"
11838 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
11841 [(set_attr "length" "0")
11842 (set_attr "in_delay_slot" "no")])
11844 ;; Emitted at the end of the literal table, used to emit the
11845 ;; 32bit branch labels if needed.
11846 (define_insn "consttable_end"
11847 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
11850 return output_jump_label_table ();
11852 [(set_attr "in_delay_slot" "no")])
11854 ;; Emitted at the end of the window in the literal table.
11855 (define_insn "consttable_window_end"
11856 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
11859 [(set_attr "length" "0")
11860 (set_attr "in_delay_slot" "no")])
11862 ;; -------------------------------------------------------------------------
11863 ;; Minimum / maximum operations.
11864 ;; -------------------------------------------------------------------------
11866 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
11867 ;; and smax standard name patterns are defined, they will be used during
11868 ;; initial expansion and combine will then be able to form the actual min-max
11870 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
11871 ;; clipped, but there is currently no way of making use of this information.
11872 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11873 (define_expand "<code>si3"
11874 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
11875 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11876 (match_operand 2 "const_int_operand")))
11877 (clobber (reg:SI T_REG))])]
11880 /* Force the comparison value into a register, because greater-than
11881 comparisons can work only on registers. Combine will be able to pick up
11882 the constant value from the REG_EQUAL note when trying to form a min-max
11884 operands[2] = force_reg (SImode, operands[2]);
11888 ;; smax (smin (...))
11890 ;; smin (smax (...))
11891 (define_insn_and_split "*clips"
11892 [(set (match_operand:SI 0 "arith_reg_dest")
11893 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
11894 (match_operand 2 "clips_max_const_int"))
11895 (match_operand 3 "clips_min_const_int")))]
11899 [(set (match_dup 0)
11900 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
11902 (define_insn "*clips"
11903 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11904 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
11905 (match_operand 2 "clips_min_const_int"))
11906 (match_operand 3 "clips_max_const_int")))]
11909 if (INTVAL (operands[3]) == 127)
11910 return "clips.b %0";
11911 else if (INTVAL (operands[3]) == 32767)
11912 return "clips.w %0";
11914 gcc_unreachable ();
11916 [(set_attr "type" "arith")])
11918 ;; If the expanded smin or smax patterns were not combined, split them into
11919 ;; a compare and branch sequence, because there are no real smin or smax
11921 (define_insn_and_split "*<code>si3"
11922 [(set (match_operand:SI 0 "arith_reg_dest")
11923 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
11924 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
11925 (clobber (reg:SI T_REG))]
11926 "TARGET_SH2A && can_create_pseudo_p ()"
11931 rtx skip_label = gen_label_rtx ();
11932 emit_move_insn (operands[0], operands[1]);
11934 rtx cmp_val = operands[2];
11935 if (satisfies_constraint_M (cmp_val))
11936 cmp_val = const0_rtx;
11938 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
11939 emit_jump_insn (<CODE> == SMIN
11940 ? gen_branch_false (skip_label)
11941 : gen_branch_true (skip_label));
11943 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
11947 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
11948 ;; with a register and a constant.
11949 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
11950 ;; clipped, but there is currently no way of making use of this information.
11951 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
11952 (define_expand "uminsi3"
11953 [(set (match_operand:SI 0 "arith_reg_dest")
11954 (umin:SI (match_operand:SI 1 "arith_reg_operand")
11955 (match_operand 2 "const_int_operand")))]
11958 if (INTVAL (operands[2]) == 1)
11960 emit_insn (gen_clipu_one (operands[0], operands[1]));
11963 else if (! clipu_max_const_int (operands[2], VOIDmode))
11967 (define_insn "*clipu"
11968 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
11969 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
11970 (match_operand 2 "clipu_max_const_int")))]
11973 if (INTVAL (operands[2]) == 255)
11974 return "clipu.b %0";
11975 else if (INTVAL (operands[2]) == 65535)
11976 return "clipu.w %0";
11978 gcc_unreachable ();
11980 [(set_attr "type" "arith")])
11982 (define_insn_and_split "clipu_one"
11983 [(set (match_operand:SI 0 "arith_reg_dest")
11984 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
11985 (clobber (reg:SI T_REG))]
11988 "&& can_create_pseudo_p ()"
11991 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
11992 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
11996 ;; -------------------------------------------------------------------------
11998 ;; -------------------------------------------------------------------------
12000 ;; String/block move insn.
12002 (define_expand "movmemsi"
12003 [(parallel [(set (mem:BLK (match_operand:BLK 0))
12004 (mem:BLK (match_operand:BLK 1)))
12005 (use (match_operand:SI 2 "nonmemory_operand"))
12006 (use (match_operand:SI 3 "immediate_operand"))
12007 (clobber (reg:SI PR_REG))
12008 (clobber (reg:SI R4_REG))
12009 (clobber (reg:SI R5_REG))
12010 (clobber (reg:SI R0_REG))])]
12011 "TARGET_SH1 && ! TARGET_SH5"
12013 if (expand_block_move (operands))
12019 (define_insn "block_move_real"
12020 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12021 (mem:BLK (reg:SI R5_REG)))
12022 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12023 (clobber (reg:SI PR_REG))
12024 (clobber (reg:SI R0_REG))])]
12025 "TARGET_SH1 && ! TARGET_HARD_SH4"
12027 [(set_attr "type" "sfunc")
12028 (set_attr "needs_delay_slot" "yes")])
12030 (define_insn "block_lump_real"
12031 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12032 (mem:BLK (reg:SI R5_REG)))
12033 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12034 (use (reg:SI R6_REG))
12035 (clobber (reg:SI PR_REG))
12036 (clobber (reg:SI T_REG))
12037 (clobber (reg:SI R4_REG))
12038 (clobber (reg:SI R5_REG))
12039 (clobber (reg:SI R6_REG))
12040 (clobber (reg:SI R0_REG))])]
12041 "TARGET_SH1 && ! TARGET_HARD_SH4"
12043 [(set_attr "type" "sfunc")
12044 (set_attr "needs_delay_slot" "yes")])
12046 (define_insn "block_move_real_i4"
12047 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12048 (mem:BLK (reg:SI R5_REG)))
12049 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12050 (clobber (reg:SI PR_REG))
12051 (clobber (reg:SI R0_REG))
12052 (clobber (reg:SI R1_REG))
12053 (clobber (reg:SI R2_REG))])]
12056 [(set_attr "type" "sfunc")
12057 (set_attr "needs_delay_slot" "yes")])
12059 (define_insn "block_lump_real_i4"
12060 [(parallel [(set (mem:BLK (reg:SI R4_REG))
12061 (mem:BLK (reg:SI R5_REG)))
12062 (use (match_operand:SI 0 "arith_reg_operand" "r"))
12063 (use (reg:SI R6_REG))
12064 (clobber (reg:SI PR_REG))
12065 (clobber (reg:SI T_REG))
12066 (clobber (reg:SI R4_REG))
12067 (clobber (reg:SI R5_REG))
12068 (clobber (reg:SI R6_REG))
12069 (clobber (reg:SI R0_REG))
12070 (clobber (reg:SI R1_REG))
12071 (clobber (reg:SI R2_REG))
12072 (clobber (reg:SI R3_REG))])]
12075 [(set_attr "type" "sfunc")
12076 (set_attr "needs_delay_slot" "yes")])
12078 ;; byte compare pattern
12080 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
12081 (define_insn "cmpstr_t"
12082 [(set (reg:SI T_REG)
12087 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
12088 (match_operand:SI 1 "arith_reg_operand" "r"))
12089 (const_int 8) (const_int 0))
12090 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12091 (const_int 8) (const_int 8)))
12092 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12093 (const_int 8) (const_int 16)))
12094 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
12095 (const_int 8) (const_int 24)))
12099 [(set_attr "type" "mt_group")])
12101 (define_expand "cmpstrsi"
12102 [(set (match_operand:SI 0 "register_operand")
12103 (compare:SI (match_operand:BLK 1 "memory_operand")
12104 (match_operand:BLK 2 "memory_operand")))
12105 (use (match_operand 3 "immediate_operand"))]
12106 "TARGET_SH1 && optimize"
12108 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
12114 (define_expand "cmpstrnsi"
12115 [(set (match_operand:SI 0 "register_operand")
12116 (compare:SI (match_operand:BLK 1 "memory_operand")
12117 (match_operand:BLK 2 "memory_operand")))
12118 (use (match_operand:SI 3 "immediate_operand"))
12119 (use (match_operand:SI 4 "immediate_operand"))]
12120 "TARGET_SH1 && optimize"
12122 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
12128 (define_expand "strlensi"
12129 [(set (match_operand:SI 0 "register_operand")
12130 (unspec:SI [(match_operand:BLK 1 "memory_operand")
12131 (match_operand:SI 2 "immediate_operand")
12132 (match_operand:SI 3 "immediate_operand")]
12133 UNSPEC_BUILTIN_STRLEN))]
12134 "TARGET_SH1 && optimize"
12136 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
12142 (define_expand "setmemqi"
12143 [(parallel [(set (match_operand:BLK 0 "memory_operand")
12144 (match_operand 2 "const_int_operand"))
12145 (use (match_operand:QI 1 "const_int_operand"))
12146 (use (match_operand:QI 3 "const_int_operand"))])]
12147 "TARGET_SH1 && optimize"
12149 if (optimize_insn_for_size_p ())
12152 sh_expand_setmem (operands);
12157 ;; -------------------------------------------------------------------------
12158 ;; Floating point instructions.
12159 ;; -------------------------------------------------------------------------
12161 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
12162 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
12163 ;; This avoids problems with reload. As a consequence, user initiated fpscr
12164 ;; stores to memory will always be ferried through a general register.
12165 ;; User initiated fpscr loads always have to undergo bit masking to preserve
12166 ;; the current fpu mode settings for the compiler generated code. Thus such
12167 ;; fpscr loads will always have to go through general registers anyways.
12168 (define_insn "lds_fpscr"
12169 [(set (reg:SI FPSCR_REG)
12170 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
12171 (set (reg:SI FPSCR_STAT_REG)
12172 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
12173 (set (reg:SI FPSCR_MODES_REG)
12174 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12179 [(set_attr "type" "gp_fpscr,mem_fpscr")])
12181 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
12183 (define_insn "sts_fpscr"
12184 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
12185 (reg:SI FPSCR_REG))
12186 (use (reg:SI FPSCR_STAT_REG))
12187 (use (reg:SI FPSCR_MODES_REG))]
12192 [(set_attr "type" "mac_gp,fstore")])
12194 (define_expand "set_fpscr"
12195 [(parallel [(set (reg:SI FPSCR_REG)
12196 (match_operand:SI 0 "general_operand"))
12197 (set (reg:SI FPSCR_STAT_REG)
12198 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
12201 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
12202 get the current FPSCR value first.
12203 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
12205 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
12207 rtx a = force_reg (SImode, operands[0]);
12209 rtx b = gen_reg_rtx (SImode);
12210 emit_insn (gen_sts_fpscr (b));
12212 rtx a_xor_b = gen_reg_rtx (SImode);
12213 emit_insn (gen_xorsi3 (a_xor_b, a, b));
12215 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
12216 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
12218 rtx r = gen_reg_rtx (SImode);
12219 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
12220 emit_insn (gen_lds_fpscr (r));
12225 ;; ??? This uses the fp unit, but has no type indicating that.
12226 ;; If we did that, this would either give a bogus latency or introduce
12227 ;; a bogus FIFO constraint.
12228 ;; Since this insn is currently only used for prologues/epilogues,
12229 ;; it is probably best to claim no function unit, which matches the
12230 ;; current setting.
12231 (define_insn "toggle_sz"
12232 [(set (reg:SI FPSCR_REG)
12233 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
12234 (set (reg:SI FPSCR_MODES_REG)
12235 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12236 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12238 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
12240 ;; Toggle FPU precision PR mode.
12242 (define_insn "toggle_pr"
12243 [(set (reg:SI FPSCR_REG)
12244 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
12245 (set (reg:SI FPSCR_MODES_REG)
12246 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
12249 [(set_attr "type" "fpscr_toggle")])
12251 (define_expand "addsf3"
12252 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12253 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
12254 (match_operand:SF 2 "fp_arith_reg_operand")))]
12255 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12259 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
12264 (define_insn "*addsf3_media"
12265 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12266 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12267 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12268 "TARGET_SHMEDIA_FPU"
12269 "fadd.s %1, %2, %0"
12270 [(set_attr "type" "fparith_media")])
12272 (define_insn_and_split "unary_sf_op"
12273 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12278 (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))]))
12279 (match_operator:SF 2 "unary_float_operator"
12280 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12281 (parallel [(match_operand 4
12282 "const_int_operand" "n")]))]))
12283 (parallel [(not:BI (match_dup 3)) (match_dup 3)])))]
12284 "TARGET_SHMEDIA_FPU"
12286 "TARGET_SHMEDIA_FPU && reload_completed"
12287 [(set (match_dup 5) (match_dup 6))]
12289 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12290 rtx op1 = gen_rtx_REG (SFmode,
12291 (true_regnum (operands[1])
12292 + (INTVAL (operands[4]) ^ endian)));
12294 operands[7] = gen_rtx_REG (SFmode,
12295 (true_regnum (operands[0])
12296 + (INTVAL (operands[3]) ^ endian)));
12297 operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1);
12299 [(set_attr "type" "fparith_media")])
12301 (define_insn_and_split "binary_sf_op0"
12302 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12304 (match_operator:SF 3 "binary_float_operator"
12305 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12306 (parallel [(const_int 0)]))
12307 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12308 (parallel [(const_int 0)]))])
12311 (parallel [(const_int 1)]))))]
12312 "TARGET_SHMEDIA_FPU"
12314 "&& reload_completed"
12315 [(set (match_dup 4) (match_dup 5))]
12317 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12318 rtx op1 = gen_rtx_REG (SFmode,
12319 true_regnum (operands[1]) + endian);
12320 rtx op2 = gen_rtx_REG (SFmode,
12321 true_regnum (operands[2]) + endian);
12323 operands[4] = gen_rtx_REG (SFmode,
12324 true_regnum (operands[0]) + endian);
12325 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12327 [(set_attr "type" "fparith_media")])
12329 (define_insn_and_split "binary_sf_op1"
12330 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12334 (parallel [(const_int 0)]))
12335 (match_operator:SF 3 "binary_float_operator"
12336 [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
12337 (parallel [(const_int 1)]))
12338 (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
12339 (parallel [(const_int 1)]))])))]
12340 "TARGET_SHMEDIA_FPU"
12342 "&& reload_completed"
12343 [(set (match_dup 4) (match_dup 5))]
12345 int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
12346 rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian));
12347 rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian));
12349 operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian));
12350 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2);
12352 [(set_attr "type" "fparith_media")])
12354 (define_insn "addsf3_i"
12355 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12356 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12357 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12358 (clobber (reg:SI FPSCR_STAT_REG))
12359 (use (reg:SI FPSCR_MODES_REG))]
12362 [(set_attr "type" "fp")
12363 (set_attr "fp_mode" "single")])
12365 (define_expand "subsf3"
12366 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12367 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12368 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12369 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12373 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
12378 (define_insn "*subsf3_media"
12379 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12380 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12381 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12382 "TARGET_SHMEDIA_FPU"
12383 "fsub.s %1, %2, %0"
12384 [(set_attr "type" "fparith_media")])
12386 (define_insn "subsf3_i"
12387 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12388 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12389 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12390 (clobber (reg:SI FPSCR_STAT_REG))
12391 (use (reg:SI FPSCR_MODES_REG))]
12394 [(set_attr "type" "fp")
12395 (set_attr "fp_mode" "single")])
12397 (define_expand "mulsf3"
12398 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12399 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
12400 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
12401 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12405 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
12410 (define_insn "*mulsf3_media"
12411 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12412 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12413 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12414 "TARGET_SHMEDIA_FPU"
12415 "fmul.s %1, %2, %0"
12416 [(set_attr "type" "fparith_media")])
12418 (define_insn "mulsf3_i"
12419 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12420 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
12421 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12422 (clobber (reg:SI FPSCR_STAT_REG))
12423 (use (reg:SI FPSCR_MODES_REG))]
12426 [(set_attr "type" "fp")
12427 (set_attr "fp_mode" "single")])
12429 ;; FMA (fused multiply-add) patterns
12430 (define_expand "fmasf4"
12431 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12432 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
12433 (match_operand:SF 2 "fp_arith_reg_operand")
12434 (match_operand:SF 3 "fp_arith_reg_operand")))]
12435 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12439 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2],
12445 (define_insn "fmasf4_i"
12446 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12447 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
12448 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12449 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
12450 (clobber (reg:SI FPSCR_STAT_REG))
12451 (use (reg:SI FPSCR_MODES_REG))]
12454 [(set_attr "type" "fp")
12455 (set_attr "fp_mode" "single")])
12457 (define_insn "fmasf4_media"
12458 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12459 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12460 (match_operand:SF 2 "fp_arith_reg_operand" "f")
12461 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12462 "TARGET_SHMEDIA_FPU"
12463 "fmac.s %1, %2, %0"
12464 [(set_attr "type" "fparith_media")])
12466 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
12467 ;; previous transformations. If FMA is generally allowed, let the combine
12468 ;; pass utilize it.
12469 (define_insn_and_split "*fmasf4"
12470 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12471 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
12472 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12473 (match_operand:SF 3 "arith_reg_operand" "0")))
12474 (clobber (reg:SI FPSCR_STAT_REG))
12475 (use (reg:SI FPSCR_MODES_REG))]
12476 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
12478 "&& can_create_pseudo_p ()"
12479 [(parallel [(set (match_dup 0)
12480 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
12481 (clobber (reg:SI FPSCR_STAT_REG))
12482 (use (reg:SI FPSCR_MODES_REG))])]
12484 /* Change 'b * a + a' into 'a * b + a'.
12485 This is better for register allocation. */
12486 if (REGNO (operands[2]) == REGNO (operands[3]))
12487 std::swap (operands[1], operands[2]);
12489 [(set_attr "type" "fp")
12490 (set_attr "fp_mode" "single")])
12492 (define_insn "*fmasf4_media"
12493 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12494 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f")
12495 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
12496 (match_operand:SF 3 "fp_arith_reg_operand" "0")))]
12497 "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF"
12498 "fmac.s %1, %2, %0"
12499 [(set_attr "type" "fparith_media")])
12501 (define_expand "divsf3"
12502 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12503 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
12504 (match_operand:SF 2 "fp_arith_reg_operand")))]
12505 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12509 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
12514 (define_insn "*divsf3_media"
12515 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12516 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")
12517 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12518 "TARGET_SHMEDIA_FPU"
12519 "fdiv.s %1, %2, %0"
12520 [(set_attr "type" "fdiv_media")])
12522 (define_insn "divsf3_i"
12523 [(set (match_operand:SF 0 "fp_arith_reg_dest" "=f")
12524 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
12525 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
12526 (clobber (reg:SI FPSCR_STAT_REG))
12527 (use (reg:SI FPSCR_MODES_REG))]
12530 [(set_attr "type" "fdiv")
12531 (set_attr "fp_mode" "single")])
12533 (define_insn "floatdisf2"
12534 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12535 (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12536 "TARGET_SHMEDIA_FPU"
12538 [(set_attr "type" "fpconv_media")])
12540 (define_expand "floatsisf2"
12541 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12542 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
12543 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12545 if (!TARGET_SHMEDIA_FPU)
12547 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
12552 (define_insn "*floatsisf2_media"
12553 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12554 (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12555 "TARGET_SHMEDIA_FPU"
12557 [(set_attr "type" "fpconv_media")])
12559 (define_insn "floatsisf2_i4"
12560 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12561 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
12562 (clobber (reg:SI FPSCR_STAT_REG))
12563 (use (reg:SI FPSCR_MODES_REG))]
12566 [(set_attr "type" "fp")
12567 (set_attr "fp_mode" "single")])
12569 (define_insn "fix_truncsfdi2"
12570 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12571 (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12572 "TARGET_SHMEDIA_FPU"
12574 [(set_attr "type" "fpconv_media")])
12576 (define_expand "fix_truncsfsi2"
12577 [(set (match_operand:SI 0 "fpul_operand" "=y")
12578 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12579 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12581 if (!TARGET_SHMEDIA_FPU)
12583 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
12588 (define_insn "*fix_truncsfsi2_media"
12589 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
12590 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12591 "TARGET_SHMEDIA_FPU"
12593 [(set_attr "type" "fpconv_media")])
12595 (define_insn "fix_truncsfsi2_i4"
12596 [(set (match_operand:SI 0 "fpul_operand" "=y")
12597 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12598 (clobber (reg:SI FPSCR_STAT_REG))
12599 (use (reg:SI FPSCR_MODES_REG))]
12602 [(set_attr "type" "ftrc_s")
12603 (set_attr "fp_mode" "single")])
12605 (define_insn "cmpgtsf_t"
12606 [(set (reg:SI T_REG)
12607 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12608 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12609 (clobber (reg:SI FPSCR_STAT_REG))
12610 (use (reg:SI FPSCR_MODES_REG))]
12611 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
12613 [(set_attr "type" "fp_cmp")
12614 (set_attr "fp_mode" "single")])
12616 (define_insn "cmpeqsf_t"
12617 [(set (reg:SI T_REG)
12618 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12619 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
12620 (clobber (reg:SI FPSCR_STAT_REG))
12621 (use (reg:SI FPSCR_MODES_REG))]
12622 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
12624 [(set_attr "type" "fp_cmp")
12625 (set_attr "fp_mode" "single")])
12627 (define_insn "ieee_ccmpeqsf_t"
12628 [(set (reg:SI T_REG)
12629 (ior:SI (reg:SI T_REG)
12630 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
12631 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
12632 (clobber (reg:SI FPSCR_STAT_REG))
12633 (use (reg:SI FPSCR_MODES_REG))]
12634 "TARGET_IEEE && TARGET_SH2E"
12636 return output_ieee_ccmpeq (insn, operands);
12638 [(set_attr "length" "4")
12639 (set_attr "fp_mode" "single")])
12641 (define_insn "cmpeqsf_media"
12642 [(set (match_operand:SI 0 "register_operand" "=r")
12643 (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12644 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12645 "TARGET_SHMEDIA_FPU"
12646 "fcmpeq.s %1, %2, %0"
12647 [(set_attr "type" "fcmp_media")])
12649 (define_insn "cmpgtsf_media"
12650 [(set (match_operand:SI 0 "register_operand" "=r")
12651 (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12652 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12653 "TARGET_SHMEDIA_FPU"
12654 "fcmpgt.s %1, %2, %0"
12655 [(set_attr "type" "fcmp_media")])
12657 (define_insn "cmpgesf_media"
12658 [(set (match_operand:SI 0 "register_operand" "=r")
12659 (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12660 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12661 "TARGET_SHMEDIA_FPU"
12662 "fcmpge.s %1, %2, %0"
12663 [(set_attr "type" "fcmp_media")])
12665 (define_insn "cmpunsf_media"
12666 [(set (match_operand:SI 0 "register_operand" "=r")
12667 (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")
12668 (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
12669 "TARGET_SHMEDIA_FPU"
12670 "fcmpun.s %1, %2, %0"
12671 [(set_attr "type" "fcmp_media")])
12673 (define_expand "cbranchsf4"
12675 (if_then_else (match_operator 0 "sh_float_comparison_operator"
12676 [(match_operand:SF 1 "arith_operand" "")
12677 (match_operand:SF 2 "arith_operand" "")])
12678 (match_operand 3 "" "")
12680 "TARGET_SH2E || TARGET_SHMEDIA_FPU"
12682 if (TARGET_SHMEDIA)
12683 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
12686 sh_emit_compare_and_branch (operands, SFmode);
12690 (define_expand "negsf2"
12691 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12692 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
12693 "TARGET_SH2E || TARGET_SHMEDIA_FPU")
12695 (define_insn "*negsf2_media"
12696 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12697 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12698 "TARGET_SHMEDIA_FPU"
12700 [(set_attr "type" "fmove_media")])
12702 (define_insn "*negsf2_i"
12703 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12704 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
12707 [(set_attr "type" "fmove")])
12709 (define_expand "sqrtsf2"
12710 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
12711 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
12712 "TARGET_SH3E || TARGET_SHMEDIA_FPU"
12716 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
12721 (define_insn "*sqrtsf2_media"
12722 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12723 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12724 "TARGET_SHMEDIA_FPU"
12726 [(set_attr "type" "fdiv_media")])
12728 (define_insn "sqrtsf2_i"
12729 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12730 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
12731 (clobber (reg:SI FPSCR_STAT_REG))
12732 (use (reg:SI FPSCR_MODES_REG))]
12735 [(set_attr "type" "fdiv")
12736 (set_attr "fp_mode" "single")])
12738 (define_insn "rsqrtsf2"
12739 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12740 (div:SF (match_operand:SF 1 "immediate_operand" "i")
12741 (sqrt:SF (match_operand:SF 2 "fp_arith_reg_operand" "0"))))
12742 (clobber (reg:SI FPSCR_STAT_REG))
12743 (use (reg:SI FPSCR_MODES_REG))]
12744 "TARGET_FPU_ANY && TARGET_FSRRA
12745 && operands[1] == CONST1_RTX (SFmode)"
12747 [(set_attr "type" "fsrra")
12748 (set_attr "fp_mode" "single")])
12750 ;; When the sincos pattern is defined, the builtin functions sin and cos
12751 ;; will be expanded to the sincos pattern and one of the output values will
12753 (define_expand "sincossf3"
12754 [(set (match_operand:SF 0 "nonimmediate_operand")
12755 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
12756 (set (match_operand:SF 1 "nonimmediate_operand")
12757 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
12758 "TARGET_FPU_ANY && TARGET_FSCA"
12760 rtx scaled = gen_reg_rtx (SFmode);
12761 rtx truncated = gen_reg_rtx (SImode);
12762 rtx fsca = gen_reg_rtx (V2SFmode);
12763 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
12765 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
12766 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
12767 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
12769 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
12770 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
12774 (define_insn_and_split "fsca"
12775 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
12777 (unspec:SF [(mult:SF
12778 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
12779 (match_operand:SF 2 "fsca_scale_factor" "i"))
12781 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
12783 (clobber (reg:SI FPSCR_STAT_REG))
12784 (use (reg:SI FPSCR_MODES_REG))]
12785 "TARGET_FPU_ANY && TARGET_FSCA"
12787 "&& !fpul_operand (operands[1], SImode)"
12790 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
12791 to a simple reg, otherwise reload will have trouble reloading the
12792 pseudo into fpul. */
12793 rtx x = XEXP (operands[1], 0);
12794 while (x != NULL_RTX && !fpul_operand (x, SImode))
12796 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
12799 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
12800 emit_insn (gen_fsca (operands[0], x, operands[2]));
12803 [(set_attr "type" "fsca")
12804 (set_attr "fp_mode" "single")])
12806 (define_expand "abssf2"
12807 [(set (match_operand:SF 0 "fp_arith_reg_operand")
12808 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
12809 "TARGET_SH2E || TARGET_SHMEDIA_FPU")
12811 (define_insn "*abssf2_media"
12812 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12813 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
12814 "TARGET_SHMEDIA_FPU"
12816 [(set_attr "type" "fmove_media")])
12818 (define_insn "*abssf2_i"
12819 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
12820 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
12823 [(set_attr "type" "fmove")])
12825 (define_expand "adddf3"
12826 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12827 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12828 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12829 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12831 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12833 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
12838 (define_insn "*adddf3_media"
12839 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12840 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12841 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12842 "TARGET_SHMEDIA_FPU"
12843 "fadd.d %1, %2, %0"
12844 [(set_attr "type" "dfparith_media")])
12846 (define_insn "adddf3_i"
12847 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12848 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12849 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12850 (clobber (reg:SI FPSCR_STAT_REG))
12851 (use (reg:SI FPSCR_MODES_REG))]
12852 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12854 [(set_attr "type" "dfp_arith")
12855 (set_attr "fp_mode" "double")])
12857 (define_expand "subdf3"
12858 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12859 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12860 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12861 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12863 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12865 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
12870 (define_insn "*subdf3_media"
12871 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12872 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12873 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12874 "TARGET_SHMEDIA_FPU"
12875 "fsub.d %1, %2, %0"
12876 [(set_attr "type" "dfparith_media")])
12878 (define_insn "subdf3_i"
12879 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12880 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
12881 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12882 (clobber (reg:SI FPSCR_STAT_REG))
12883 (use (reg:SI FPSCR_MODES_REG))]
12884 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12886 [(set_attr "type" "dfp_arith")
12887 (set_attr "fp_mode" "double")])
12889 (define_expand "muldf3"
12890 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12891 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12892 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12893 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12895 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12897 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
12902 (define_insn "*muldf3_media"
12903 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12904 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f")
12905 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12906 "TARGET_SHMEDIA_FPU"
12907 "fmul.d %1, %2, %0"
12908 [(set_attr "type" "dfmul_media")])
12910 (define_insn "muldf3_i"
12911 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12912 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
12913 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12914 (clobber (reg:SI FPSCR_STAT_REG))
12915 (use (reg:SI FPSCR_MODES_REG))]
12916 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12918 [(set_attr "type" "dfp_mul")
12919 (set_attr "fp_mode" "double")])
12921 (define_expand "divdf3"
12922 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12923 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
12924 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
12925 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12927 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12929 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
12934 (define_insn "*divdf3_media"
12935 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12936 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")
12937 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
12938 "TARGET_SHMEDIA_FPU"
12939 "fdiv.d %1, %2, %0"
12940 [(set_attr "type" "dfdiv_media")])
12942 (define_insn "divdf3_i"
12943 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12944 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
12945 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
12946 (clobber (reg:SI FPSCR_STAT_REG))
12947 (use (reg:SI FPSCR_MODES_REG))]
12948 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12950 [(set_attr "type" "dfdiv")
12951 (set_attr "fp_mode" "double")])
12953 (define_insn "floatdidf2"
12954 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12955 (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))]
12956 "TARGET_SHMEDIA_FPU"
12958 [(set_attr "type" "dfpconv_media")])
12960 (define_expand "floatsidf2"
12961 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
12962 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
12963 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
12965 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
12967 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
12972 (define_insn "*floatsidf2_media"
12973 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12974 (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))]
12975 "TARGET_SHMEDIA_FPU"
12977 [(set_attr "type" "dfpconv_media")])
12979 (define_insn "floatsidf2_i"
12980 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
12981 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
12982 (clobber (reg:SI FPSCR_STAT_REG))
12983 (use (reg:SI FPSCR_MODES_REG))]
12984 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
12986 [(set_attr "type" "dfp_conv")
12987 (set_attr "fp_mode" "double")])
12989 (define_insn "fix_truncdfdi2"
12990 [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f")
12991 (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
12992 "TARGET_SHMEDIA_FPU"
12994 [(set_attr "type" "dfpconv_media")])
12996 (define_expand "fix_truncdfsi2"
12997 [(set (match_operand:SI 0 "fpul_operand" "")
12998 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
12999 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13001 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13003 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
13008 (define_insn "*fix_truncdfsi2_media"
13009 [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f")
13010 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13011 "TARGET_SHMEDIA_FPU"
13013 [(set_attr "type" "dfpconv_media")])
13015 (define_insn "fix_truncdfsi2_i"
13016 [(set (match_operand:SI 0 "fpul_operand" "=y")
13017 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13018 (clobber (reg:SI FPSCR_STAT_REG))
13019 (use (reg:SI FPSCR_MODES_REG))]
13020 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13022 [(set_attr "type" "dfp_conv")
13023 (set_attr "dfp_comp" "no")
13024 (set_attr "fp_mode" "double")])
13026 (define_insn "cmpgtdf_t"
13027 [(set (reg:SI T_REG)
13028 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13029 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13030 (clobber (reg:SI FPSCR_STAT_REG))
13031 (use (reg:SI FPSCR_MODES_REG))]
13032 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13034 [(set_attr "type" "dfp_cmp")
13035 (set_attr "fp_mode" "double")])
13037 (define_insn "cmpeqdf_t"
13038 [(set (reg:SI T_REG)
13039 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13040 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13041 (clobber (reg:SI FPSCR_STAT_REG))
13042 (use (reg:SI FPSCR_MODES_REG))]
13043 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13045 [(set_attr "type" "dfp_cmp")
13046 (set_attr "fp_mode" "double")])
13048 (define_insn "*ieee_ccmpeqdf_t"
13049 [(set (reg:SI T_REG)
13050 (ior:SI (reg:SI T_REG)
13051 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
13052 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
13053 (clobber (reg:SI FPSCR_STAT_REG))
13054 (use (reg:SI FPSCR_MODES_REG))]
13055 "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13057 return output_ieee_ccmpeq (insn, operands);
13059 [(set_attr "length" "4")
13060 (set_attr "fp_mode" "double")])
13062 (define_insn "cmpeqdf_media"
13063 [(set (match_operand:SI 0 "register_operand" "=r")
13064 (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13065 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13066 "TARGET_SHMEDIA_FPU"
13067 "fcmpeq.d %1,%2,%0"
13068 [(set_attr "type" "fcmp_media")])
13070 (define_insn "cmpgtdf_media"
13071 [(set (match_operand:SI 0 "register_operand" "=r")
13072 (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13073 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13074 "TARGET_SHMEDIA_FPU"
13075 "fcmpgt.d %1,%2,%0"
13076 [(set_attr "type" "fcmp_media")])
13078 (define_insn "cmpgedf_media"
13079 [(set (match_operand:SI 0 "register_operand" "=r")
13080 (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13081 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13082 "TARGET_SHMEDIA_FPU"
13083 "fcmpge.d %1,%2,%0"
13084 [(set_attr "type" "fcmp_media")])
13086 (define_insn "cmpundf_media"
13087 [(set (match_operand:SI 0 "register_operand" "=r")
13088 (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")
13089 (match_operand:DF 2 "fp_arith_reg_operand" "f")))]
13090 "TARGET_SHMEDIA_FPU"
13091 "fcmpun.d %1,%2,%0"
13092 [(set_attr "type" "fcmp_media")])
13094 (define_expand "cbranchdf4"
13096 (if_then_else (match_operator 0 "sh_float_comparison_operator"
13097 [(match_operand:DF 1 "arith_operand" "")
13098 (match_operand:DF 2 "arith_operand" "")])
13099 (match_operand 3 "" "")
13101 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13103 if (TARGET_SHMEDIA)
13104 emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2],
13107 sh_emit_compare_and_branch (operands, DFmode);
13111 (define_expand "negdf2"
13112 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13113 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13114 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU")
13116 (define_insn "*negdf2_media"
13117 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13118 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13119 "TARGET_SHMEDIA_FPU"
13121 [(set_attr "type" "fmove_media")])
13123 (define_insn "*negdf2_i"
13124 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13125 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
13126 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13128 [(set_attr "type" "fmove")])
13130 (define_expand "sqrtdf2"
13131 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13132 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13133 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13135 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13137 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
13142 (define_insn "*sqrtdf2_media"
13143 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13144 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13145 "TARGET_SHMEDIA_FPU"
13147 [(set_attr "type" "dfdiv_media")])
13149 (define_insn "sqrtdf2_i"
13150 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13151 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
13152 (clobber (reg:SI FPSCR_STAT_REG))
13153 (use (reg:SI FPSCR_MODES_REG))]
13154 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13156 [(set_attr "type" "dfdiv")
13157 (set_attr "fp_mode" "double")])
13159 (define_expand "absdf2"
13160 [(set (match_operand:DF 0 "fp_arith_reg_operand")
13161 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
13162 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU")
13164 (define_insn "*absdf2_media"
13165 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13166 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13167 "TARGET_SHMEDIA_FPU"
13169 [(set_attr "type" "fmove_media")])
13171 (define_insn "*absdf2_i"
13172 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13173 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
13174 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13176 [(set_attr "type" "fmove")])
13178 (define_expand "extendsfdf2"
13179 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
13180 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
13181 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13183 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13185 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
13190 (define_insn "*extendsfdf2_media"
13191 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13192 (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
13193 "TARGET_SHMEDIA_FPU"
13195 [(set_attr "type" "dfpconv_media")])
13197 (define_insn "extendsfdf2_i4"
13198 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
13199 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
13200 (clobber (reg:SI FPSCR_STAT_REG))
13201 (use (reg:SI FPSCR_MODES_REG))]
13202 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13204 [(set_attr "type" "fp")
13205 (set_attr "fp_mode" "double")])
13207 (define_expand "truncdfsf2"
13208 [(set (match_operand:SF 0 "fpul_operand" "")
13209 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
13210 "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU"
13212 if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
13214 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
13219 (define_insn "*truncdfsf2_media"
13220 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
13221 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))]
13222 "TARGET_SHMEDIA_FPU"
13224 [(set_attr "type" "dfpconv_media")])
13226 (define_insn "truncdfsf2_i4"
13227 [(set (match_operand:SF 0 "fpul_operand" "=y")
13228 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
13229 (clobber (reg:SI FPSCR_STAT_REG))
13230 (use (reg:SI FPSCR_MODES_REG))]
13231 "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
13233 [(set_attr "type" "fp")
13234 (set_attr "fp_mode" "double")])
13236 ;; -------------------------------------------------------------------------
13237 ;; Bit field extract patterns.
13238 ;; -------------------------------------------------------------------------
13240 ;; These give better code for packed bitfields, because they allow
13241 ;; auto-increment addresses to be generated.
13243 (define_expand "insv"
13244 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
13245 (match_operand:SI 1 "immediate_operand" "")
13246 (match_operand:SI 2 "immediate_operand" ""))
13247 (match_operand:SI 3 "general_operand" ""))]
13248 "TARGET_SH1 && TARGET_BIG_ENDIAN"
13250 rtx addr_target, orig_address, shift_reg, qi_val;
13251 HOST_WIDE_INT bitsize, size, v = 0;
13252 rtx x = operands[3];
13254 if (TARGET_SH2A && TARGET_BITOPS
13255 && (satisfies_constraint_Sbw (operands[0])
13256 || satisfies_constraint_Sbv (operands[0]))
13257 && satisfies_constraint_M (operands[1])
13258 && satisfies_constraint_K03 (operands[2]))
13260 if (satisfies_constraint_N (operands[3]))
13262 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
13265 else if (satisfies_constraint_M (operands[3]))
13267 emit_insn (gen_bset_m2a (operands[0], operands[2]));
13270 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
13271 && satisfies_constraint_M (operands[1]))
13273 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13276 else if (REG_P (operands[3])
13277 && satisfies_constraint_M (operands[1]))
13279 emit_insn (gen_bld_reg (operands[3], const0_rtx));
13280 emit_insn (gen_bst_m2a (operands[0], operands[2]));
13284 /* ??? expmed doesn't care for non-register predicates. */
13285 if (! memory_operand (operands[0], VOIDmode)
13286 || ! immediate_operand (operands[1], VOIDmode)
13287 || ! immediate_operand (operands[2], VOIDmode)
13288 || ! general_operand (x, VOIDmode))
13290 /* If this isn't a 16 / 24 / 32 bit field, or if
13291 it doesn't start on a byte boundary, then fail. */
13292 bitsize = INTVAL (operands[1]);
13293 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
13294 || (INTVAL (operands[2]) % 8) != 0)
13297 size = bitsize / 8;
13298 orig_address = XEXP (operands[0], 0);
13299 shift_reg = gen_reg_rtx (SImode);
13300 if (CONST_INT_P (x))
13303 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
13307 emit_insn (gen_movsi (shift_reg, operands[3]));
13308 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13310 addr_target = copy_addr_to_reg (plus_constant (Pmode,
13311 orig_address, size - 1));
13313 operands[0] = replace_equiv_address (operands[0], addr_target);
13314 emit_insn (gen_movqi (operands[0], qi_val));
13318 if (CONST_INT_P (x))
13320 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
13323 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
13324 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
13326 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
13327 emit_insn (gen_movqi (operands[0], qi_val));
13333 (define_insn "movua"
13334 [(set (match_operand:SI 0 "register_operand" "=z")
13335 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
13339 [(set_attr "type" "movua")])
13341 ;; We shouldn't need this, but cse replaces increments with references
13342 ;; to other regs before flow has a chance to create post_inc
13343 ;; addressing modes, and only postreload's cse_move2add brings the
13344 ;; increments back to a usable form.
13346 [(set (match_operand:SI 0 "register_operand" "")
13347 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
13348 (const_int 32) (const_int 0)))
13349 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13350 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
13351 [(set (match_operand:SI 0 "register_operand" "")
13352 (sign_extract:SI (mem:SI (post_inc:SI
13353 (match_operand:SI 1 "register_operand" "")))
13354 (const_int 32) (const_int 0)))]
13357 (define_expand "extv"
13358 [(set (match_operand:SI 0 "register_operand" "")
13359 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13360 (match_operand 2 "const_int_operand" "")
13361 (match_operand 3 "const_int_operand" "")))]
13362 "TARGET_SH4A || TARGET_SH2A"
13364 if (TARGET_SH2A && TARGET_BITOPS
13365 && (satisfies_constraint_Sbw (operands[1])
13366 || satisfies_constraint_Sbv (operands[1]))
13367 && satisfies_constraint_M (operands[2])
13368 && satisfies_constraint_K03 (operands[3]))
13370 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
13371 if (REGNO (operands[0]) != T_REG)
13372 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13376 && INTVAL (operands[2]) == 32
13377 && INTVAL (operands[3]) == 0
13378 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13380 rtx src = adjust_address (operands[1], BLKmode, 0);
13381 set_mem_size (src, 4);
13382 emit_insn (gen_movua (operands[0], src));
13389 (define_expand "extzv"
13390 [(set (match_operand:SI 0 "register_operand" "")
13391 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
13392 (match_operand 2 "const_int_operand" "")
13393 (match_operand 3 "const_int_operand" "")))]
13394 "TARGET_SH4A || TARGET_SH2A"
13396 if (TARGET_SH2A && TARGET_BITOPS
13397 && (satisfies_constraint_Sbw (operands[1])
13398 || satisfies_constraint_Sbv (operands[1]))
13399 && satisfies_constraint_M (operands[2])
13400 && satisfies_constraint_K03 (operands[3]))
13402 emit_insn (gen_bld_m2a (operands[1], operands[3]));
13403 if (REGNO (operands[0]) != T_REG)
13404 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
13408 && INTVAL (operands[2]) == 32
13409 && INTVAL (operands[3]) == 0
13410 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
13412 rtx src = adjust_address (operands[1], BLKmode, 0);
13413 set_mem_size (src, 4);
13414 emit_insn (gen_movua (operands[0], src));
13421 ;; SH2A instructions for bitwise operations.
13422 ;; FIXME: Convert multiple instruction insns to insn_and_split.
13423 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
13425 ;; Clear a bit in a memory location.
13426 (define_insn "bclr_m2a"
13427 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13429 (not:QI (ashift:QI (const_int 1)
13430 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13432 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13435 bclr.b %1,@(0,%t0)"
13436 [(set_attr "length" "4,4")])
13438 (define_insn "bclrmem_m2a"
13439 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13440 (and:QI (match_dup 0)
13441 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
13442 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
13445 bclr.b %W1,@(0,%t0)"
13446 [(set_attr "length" "4,4")])
13448 ;; Set a bit in a memory location.
13449 (define_insn "bset_m2a"
13450 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13452 (ashift:QI (const_int 1)
13453 (match_operand:QI 1 "const_int_operand" "K03,K03"))
13455 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13458 bset.b %1,@(0,%t0)"
13459 [(set_attr "length" "4,4")])
13461 (define_insn "bsetmem_m2a"
13462 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
13463 (ior:QI (match_dup 0)
13464 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
13465 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
13468 bset.b %V1,@(0,%t0)"
13469 [(set_attr "length" "4,4")])
13471 ;;; Transfer the contents of the T bit to a specified bit of memory.
13472 (define_insn "bst_m2a"
13473 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
13474 (if_then_else (eq (reg:SI T_REG) (const_int 0))
13476 (not:QI (ashift:QI (const_int 1)
13477 (match_operand:QI 1 "const_int_operand" "K03,K03")))
13480 (ashift:QI (const_int 1) (match_dup 1))
13482 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13486 [(set_attr "length" "4")])
13488 ;; Store a specified bit of memory in the T bit.
13489 (define_insn "bld_m2a"
13490 [(set (reg:SI T_REG)
13492 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
13494 (match_operand 1 "const_int_operand" "K03,K03")))]
13495 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13499 [(set_attr "length" "4,4")])
13501 ;; Store a specified bit of memory in the T bit.
13502 (define_insn "bldsign_m2a"
13503 [(set (reg:SI T_REG)
13505 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13507 (match_operand 1 "const_int_operand" "K03,K03")))]
13508 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13512 [(set_attr "length" "4,4")])
13514 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
13515 (define_insn "bld_reg"
13516 [(set (reg:SI T_REG)
13517 (zero_extract:SI (match_operand:SI 0 "arith_reg_operand" "r")
13519 (match_operand 1 "const_int_operand" "K03")))]
13520 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13523 (define_insn "*bld_regqi"
13524 [(set (reg:SI T_REG)
13525 (zero_extract:SI (match_operand:QI 0 "arith_reg_operand" "r")
13527 (match_operand 1 "const_int_operand" "K03")))]
13528 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
13531 ;; Take logical and of a specified bit of memory with the T bit and
13532 ;; store its result in the T bit.
13533 (define_insn "band_m2a"
13534 [(set (reg:SI T_REG)
13535 (and:SI (reg:SI T_REG)
13537 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13539 (match_operand 1 "const_int_operand" "K03,K03"))))]
13540 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13543 band.b %1,@(0,%t0)"
13544 [(set_attr "length" "4,4")])
13546 (define_insn "bandreg_m2a"
13547 [(set (match_operand:SI 0 "register_operand" "=r,r")
13548 (and:SI (zero_extract:SI
13549 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13551 (match_operand 2 "const_int_operand" "K03,K03"))
13552 (match_operand:SI 3 "register_operand" "r,r")))]
13553 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13555 static const char* alt[] =
13557 "band.b %2,%1" "\n"
13560 "band.b %2,@(0,%t1)" "\n"
13563 return alt[which_alternative];
13565 [(set_attr "length" "6,6")])
13567 ;; Take logical or of a specified bit of memory with the T bit and
13568 ;; store its result in the T bit.
13569 (define_insn "bor_m2a"
13570 [(set (reg:SI T_REG)
13571 (ior:SI (reg:SI T_REG)
13573 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13575 (match_operand 1 "const_int_operand" "K03,K03"))))]
13576 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13580 [(set_attr "length" "4,4")])
13582 (define_insn "borreg_m2a"
13583 [(set (match_operand:SI 0 "register_operand" "=r,r")
13584 (ior:SI (zero_extract:SI
13585 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13587 (match_operand 2 "const_int_operand" "K03,K03"))
13588 (match_operand:SI 3 "register_operand" "=r,r")))]
13589 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13591 static const char* alt[] =
13596 "bor.b %2,@(0,%t1)" "\n"
13599 return alt[which_alternative];
13601 [(set_attr "length" "6,6")])
13603 ;; Take exclusive or of a specified bit of memory with the T bit and
13604 ;; store its result in the T bit.
13605 (define_insn "bxor_m2a"
13606 [(set (reg:SI T_REG)
13607 (xor:SI (reg:SI T_REG)
13609 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
13611 (match_operand 1 "const_int_operand" "K03,K03"))))]
13612 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
13615 bxor.b %1,@(0,%t0)"
13616 [(set_attr "length" "4,4")])
13618 (define_insn "bxorreg_m2a"
13619 [(set (match_operand:SI 0 "register_operand" "=r,r")
13620 (xor:SI (zero_extract:SI
13621 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
13623 (match_operand 2 "const_int_operand" "K03,K03"))
13624 (match_operand:SI 3 "register_operand" "=r,r")))]
13625 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
13627 static const char* alt[] =
13629 "bxor.b %2,%1" "\n"
13632 "bxor.b %2,@(0,%t1)" "\n"
13635 return alt[which_alternative];
13637 [(set_attr "length" "6,6")])
13639 ;; -------------------------------------------------------------------------
13641 ;; -------------------------------------------------------------------------
13642 ;; This matches cases where the bit in a memory location is set.
13644 [(set (match_operand:SI 0 "register_operand")
13645 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13647 (ior:SI (match_dup 0)
13648 (match_operand:SI 2 "const_int_operand")))
13650 (match_operand 3 "arith_reg_operand"))]
13651 "TARGET_SH2A && TARGET_BITOPS
13652 && satisfies_constraint_Pso (operands[2])
13653 && REGNO (operands[0]) == REGNO (operands[3])"
13654 [(set (match_dup 1)
13655 (ior:QI (match_dup 1) (match_dup 2)))]
13658 ;; This matches cases where the bit in a memory location is cleared.
13660 [(set (match_operand:SI 0 "register_operand")
13661 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
13663 (and:SI (match_dup 0)
13664 (match_operand:SI 2 "const_int_operand")))
13666 (match_operand 3 "arith_reg_operand"))]
13667 "TARGET_SH2A && TARGET_BITOPS
13668 && satisfies_constraint_Psz (operands[2])
13669 && REGNO (operands[0]) == REGNO (operands[3])"
13670 [(set (match_dup 1)
13671 (and:QI (match_dup 1) (match_dup 2)))]
13674 ;; This matches cases where a stack pointer increment at the start of the
13675 ;; epilogue combines with a stack slot read loading the return value.
13677 [(set (match_operand:SI 0 "arith_reg_operand" "")
13678 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
13679 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
13680 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
13683 ;; See the comment on the dt combiner pattern above.
13685 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
13686 (plus:SI (match_dup 0)
13688 (set (reg:SI T_REG)
13689 (eq:SI (match_dup 0) (const_int 0)))]
13693 ;; The following peepholes fold load sequences for which reload was not
13694 ;; able to generate a displacement addressing move insn.
13695 ;; This can happen when reload has to transform a move insn
13696 ;; without displacement into one with displacement. Or when reload can't
13697 ;; fit a displacement into the insn's constraints. In the latter case, the
13698 ;; load destination reg remains at r0, which reload compensates by inserting
13699 ;; another mov insn.
13703 ;; mov.{b,w} @(r0,r15),r0
13706 ;; mov.{b,w} @(54,r15),r3
13709 [(set (match_operand:SI 0 "arith_reg_dest" "")
13710 (match_operand:SI 1 "const_int_operand" ""))
13711 (set (match_operand:SI 2 "arith_reg_dest" "")
13713 (mem:QI (plus:SI (match_dup 0)
13714 (match_operand:SI 3 "arith_reg_operand" "")))))
13715 (set (match_operand:QI 4 "arith_reg_dest" "")
13716 (match_operand:QI 5 "arith_reg_operand" ""))]
13718 && sh_legitimate_index_p (QImode, operands[1], true, true)
13719 && REGNO (operands[2]) == REGNO (operands[5])
13720 && peep2_reg_dead_p (3, operands[5])"
13721 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
13725 [(set (match_operand:SI 0 "arith_reg_dest" "")
13726 (match_operand:SI 1 "const_int_operand" ""))
13727 (set (match_operand:SI 2 "arith_reg_dest" "")
13729 (mem:HI (plus:SI (match_dup 0)
13730 (match_operand:SI 3 "arith_reg_operand" "")))))
13731 (set (match_operand:HI 4 "arith_reg_dest" "")
13732 (match_operand:HI 5 "arith_reg_operand" ""))]
13734 && sh_legitimate_index_p (HImode, operands[1], true, true)
13735 && REGNO (operands[2]) == REGNO (operands[5])
13736 && peep2_reg_dead_p (3, operands[5])"
13737 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
13742 ;; mov.{b,w} @(r0,r15),r1
13744 ;; mov.{b,w} @(54,r15),r1
13747 [(set (match_operand:SI 0 "arith_reg_dest" "")
13748 (match_operand:SI 1 "const_int_operand" ""))
13749 (set (match_operand:SI 2 "arith_reg_dest" "")
13751 (mem:QI (plus:SI (match_dup 0)
13752 (match_operand:SI 3 "arith_reg_operand" "")))))]
13754 && sh_legitimate_index_p (QImode, operands[1], true, true)
13755 && (peep2_reg_dead_p (2, operands[0])
13756 || REGNO (operands[0]) == REGNO (operands[2]))"
13757 [(set (match_dup 2)
13758 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
13762 [(set (match_operand:SI 0 "arith_reg_dest" "")
13763 (match_operand:SI 1 "const_int_operand" ""))
13764 (set (match_operand:SI 2 "arith_reg_dest" "")
13766 (mem:HI (plus:SI (match_dup 0)
13767 (match_operand:SI 3 "arith_reg_operand" "")))))]
13769 && sh_legitimate_index_p (HImode, operands[1], true, true)
13770 && (peep2_reg_dead_p (2, operands[0])
13771 || REGNO (operands[0]) == REGNO (operands[2]))"
13772 [(set (match_dup 2)
13773 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
13777 ;; mov.{b,w} @(r0,r15),r0
13780 ;; mov.{b,w} @(r0,r15),r3
13782 ;; This can happen when initially a displacement address is picked, where
13783 ;; the destination reg is fixed to r0, and then the address is transformed
13784 ;; into 'r0 + reg'.
13786 [(set (match_operand:SI 0 "arith_reg_dest" "")
13788 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13789 (match_operand:SI 2 "arith_reg_operand" "")))))
13790 (set (match_operand:QI 3 "arith_reg_dest" "")
13791 (match_operand:QI 4 "arith_reg_operand" ""))]
13793 && REGNO (operands[0]) == REGNO (operands[4])
13794 && peep2_reg_dead_p (2, operands[0])"
13795 [(set (match_dup 3)
13796 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
13800 [(set (match_operand:SI 0 "arith_reg_dest" "")
13802 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
13803 (match_operand:SI 2 "arith_reg_operand" "")))))
13804 (set (match_operand:HI 3 "arith_reg_dest" "")
13805 (match_operand:HI 4 "arith_reg_operand" ""))]
13807 && REGNO (operands[0]) == REGNO (operands[4])
13808 && peep2_reg_dead_p (2, operands[0])"
13809 [(set (match_dup 3)
13810 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
13814 [(set (match_operand:SI 0 "register_operand" "=r")
13815 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13816 (set (mem:SF (match_dup 0))
13817 (match_operand:SF 2 "general_movsrc_operand" ""))]
13818 "TARGET_SH1 && REGNO (operands[0]) == 0
13819 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13820 || (GET_CODE (operands[2]) == SUBREG
13821 && REGNO (SUBREG_REG (operands[2])) < 16))
13822 && reg_unused_after (operands[0], insn)"
13823 "mov.l %2,@(%0,%1)")
13826 [(set (match_operand:SI 0 "register_operand" "=r")
13827 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13828 (set (match_operand:SF 2 "general_movdst_operand" "")
13830 (mem:SF (match_dup 0)))]
13831 "TARGET_SH1 && REGNO (operands[0]) == 0
13832 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
13833 || (GET_CODE (operands[2]) == SUBREG
13834 && REGNO (SUBREG_REG (operands[2])) < 16))
13835 && reg_unused_after (operands[0], insn)"
13836 "mov.l @(%0,%1),%2")
13839 [(set (match_operand:SI 0 "register_operand" "=r")
13840 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13841 (set (mem:SF (match_dup 0))
13842 (match_operand:SF 2 "general_movsrc_operand" ""))]
13843 "TARGET_SH2E && REGNO (operands[0]) == 0
13844 && ((REG_P (operands[2])
13845 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13846 || (GET_CODE (operands[2]) == SUBREG
13847 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13848 && reg_unused_after (operands[0], insn)"
13849 "fmov{.s|} %2,@(%0,%1)")
13852 [(set (match_operand:SI 0 "register_operand" "=r")
13853 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
13854 (set (match_operand:SF 2 "general_movdst_operand" "")
13856 (mem:SF (match_dup 0)))]
13857 "TARGET_SH2E && REGNO (operands[0]) == 0
13858 && ((REG_P (operands[2])
13859 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
13860 || (GET_CODE (operands[2]) == SUBREG
13861 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
13862 && reg_unused_after (operands[0], insn)"
13863 "fmov{.s|} @(%0,%1),%2")
13865 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
13866 (define_insn "sp_switch_1"
13867 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
13868 UNSPECV_SP_SWITCH_B))]
13871 return "mov.l r0,@-r15" "\n"
13872 " mov.l %0,r0" "\n"
13873 " mov.l @r0,r0" "\n"
13874 " mov.l r15,@-r0" "\n"
13877 [(set_attr "length" "10")])
13879 ;; Switch back to the original stack for interrupt functions with the
13880 ;; sp_switch attribute.
13881 (define_insn "sp_switch_2"
13882 [(unspec_volatile [(const_int 0)]
13883 UNSPECV_SP_SWITCH_E)]
13886 return "mov.l @r15,r15" "\n"
13889 [(set_attr "length" "4")])
13891 ;; -------------------------------------------------------------------------
13892 ;; Integer vector moves
13893 ;; -------------------------------------------------------------------------
13895 (define_expand "movv8qi"
13896 [(set (match_operand:V8QI 0 "general_movdst_operand" "")
13897 (match_operand:V8QI 1 "general_movsrc_operand" ""))]
13900 prepare_move_operands (operands, V8QImode);
13903 (define_insn "movv8qi_i"
13904 [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
13905 (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
13907 && (register_operand (operands[0], V8QImode)
13908 || sh_register_operand (operands[1], V8QImode))"
13915 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
13916 (set_attr "length" "4,4,16,4,4")])
13919 [(set (match_operand:V8QI 0 "arith_reg_dest" "")
13920 (subreg:V8QI (const_int 0) 0))]
13922 [(set (match_dup 0)
13923 (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0)
13924 (const_int 0) (const_int 0) (const_int 0)
13925 (const_int 0) (const_int 0)]))])
13928 [(set (match_operand 0 "arith_reg_dest" "")
13929 (match_operand 1 "sh_rep_vec" ""))]
13930 "TARGET_SHMEDIA && reload_completed
13931 && GET_MODE (operands[0]) == GET_MODE (operands[1])
13932 && sh_vector_mode_supported_p (GET_MODE (operands[0]))
13933 && GET_MODE_SIZE (GET_MODE (operands[0])) == 8
13934 && (XVECEXP (operands[1], 0, 0) != const0_rtx
13935 || XVECEXP (operands[1], 0, 1) != const0_rtx)
13936 && (XVECEXP (operands[1], 0, 0) != constm1_rtx
13937 || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
13938 [(set (match_dup 0) (match_dup 1))
13941 int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1]));
13942 rtx elt1 = XVECEXP (operands[1], 0, 1);
13945 operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]);
13949 operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0]));
13950 operands[2] = gen_mperm_w0 (operands[0], operands[0]);
13952 operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0]));
13953 operands[1] = XVECEXP (operands[1], 0, 0);
13956 if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
13958 = GEN_INT (TARGET_LITTLE_ENDIAN
13959 ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
13960 : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff));
13963 operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0]));
13965 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1));
13971 [(set (match_operand 0 "arith_reg_dest" "")
13972 (match_operand 1 "sh_const_vec" ""))]
13973 "TARGET_SHMEDIA && reload_completed
13974 && GET_MODE (operands[0]) == GET_MODE (operands[1])
13975 && sh_vector_mode_supported_p (GET_MODE (operands[0]))"
13976 [(set (match_dup 0) (match_dup 1))]
13978 rtx v = operands[1];
13979 machine_mode new_mode
13980 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0);
13982 operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0]));
13984 = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0);
13987 (define_expand "movv2hi"
13988 [(set (match_operand:V2HI 0 "general_movdst_operand" "")
13989 (match_operand:V2HI 1 "general_movsrc_operand" ""))]
13992 prepare_move_operands (operands, V2HImode);
13995 (define_insn "movv2hi_i"
13996 [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
13997 (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
13999 && (register_operand (operands[0], V2HImode)
14000 || sh_register_operand (operands[1], V2HImode))"
14007 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14008 (set_attr "length" "4,4,16,4,4")
14009 (set (attr "highpart")
14010 (cond [(match_test "sh_contains_memref_p (insn)")
14011 (const_string "user")]
14012 (const_string "ignore")))])
14014 (define_expand "movv4hi"
14015 [(set (match_operand:V4HI 0 "general_movdst_operand" "")
14016 (match_operand:V4HI 1 "general_movsrc_operand" ""))]
14019 prepare_move_operands (operands, V4HImode);
14022 (define_insn "movv4hi_i"
14023 [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
14024 (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14026 && (register_operand (operands[0], V4HImode)
14027 || sh_register_operand (operands[1], V4HImode))"
14034 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14035 (set_attr "length" "4,4,16,4,4")
14036 (set_attr "highpart" "depend")])
14038 (define_expand "movv2si"
14039 [(set (match_operand:V2SI 0 "general_movdst_operand" "")
14040 (match_operand:V2SI 1 "general_movsrc_operand" ""))]
14043 prepare_move_operands (operands, V2SImode);
14046 (define_insn "movv2si_i"
14047 [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
14048 (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))]
14050 && (register_operand (operands[0], V2SImode)
14051 || sh_register_operand (operands[1], V2SImode))"
14058 [(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
14059 (set_attr "length" "4,4,16,4,4")
14060 (set_attr "highpart" "depend")])
14062 ;; -------------------------------------------------------------------------
14063 ;; Multimedia Intrinsics
14064 ;; -------------------------------------------------------------------------
14066 (define_insn "absv2si2"
14067 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14068 (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))]
14071 [(set_attr "type" "mcmp_media")
14072 (set_attr "highpart" "depend")])
14074 (define_insn "absv4hi2"
14075 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14076 (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))]
14079 [(set_attr "type" "mcmp_media")
14080 (set_attr "highpart" "depend")])
14082 (define_insn "addv2si3"
14083 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14084 (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14085 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14087 "madd.l %1, %2, %0"
14088 [(set_attr "type" "arith_media")
14089 (set_attr "highpart" "depend")])
14091 (define_insn "addv4hi3"
14092 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14093 (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14094 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14096 "madd.w %1, %2, %0"
14097 [(set_attr "type" "arith_media")
14098 (set_attr "highpart" "depend")])
14100 (define_insn_and_split "addv2hi3"
14101 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
14102 (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r")
14103 (match_operand:V2HI 2 "extend_reg_operand" "r")))]
14109 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
14110 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
14111 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
14112 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
14113 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
14115 emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1));
14116 emit_insn (gen_truncdisi2 (si_dst, di_dst));
14119 [(set_attr "highpart" "must_split")])
14121 (define_insn "ssaddv2si3"
14122 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14123 (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r")
14124 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14126 "madds.l %1, %2, %0"
14127 [(set_attr "type" "mcmp_media")
14128 (set_attr "highpart" "depend")])
14130 (define_insn "usaddv8qi3"
14131 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14132 (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r")
14133 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
14135 "madds.ub %1, %2, %0"
14136 [(set_attr "type" "mcmp_media")
14137 (set_attr "highpart" "depend")])
14139 (define_insn "ssaddv4hi3"
14140 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14141 (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r")
14142 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14144 "madds.w %1, %2, %0"
14145 [(set_attr "type" "mcmp_media")
14146 (set_attr "highpart" "depend")])
14148 (define_insn "negcmpeqv8qi"
14149 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14151 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14152 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14154 "mcmpeq.b %N1, %N2, %0"
14155 [(set_attr "type" "mcmp_media")
14156 (set_attr "highpart" "depend")])
14158 (define_insn "negcmpeqv2si"
14159 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14161 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14162 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14164 "mcmpeq.l %N1, %N2, %0"
14165 [(set_attr "type" "mcmp_media")
14166 (set_attr "highpart" "depend")])
14168 (define_insn "negcmpeqv4hi"
14169 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14171 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14172 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14174 "mcmpeq.w %N1, %N2, %0"
14175 [(set_attr "type" "mcmp_media")
14176 (set_attr "highpart" "depend")])
14178 (define_insn "negcmpgtuv8qi"
14179 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14180 (neg:V8QI (gtu:V8QI
14181 (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ")
14182 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))]
14184 "mcmpgt.ub %N1, %N2, %0"
14185 [(set_attr "type" "mcmp_media")
14186 (set_attr "highpart" "depend")])
14188 (define_insn "negcmpgtv2si"
14189 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14191 (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ")
14192 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14194 "mcmpgt.l %N1, %N2, %0"
14195 [(set_attr "type" "mcmp_media")
14196 (set_attr "highpart" "depend")])
14198 (define_insn "negcmpgtv4hi"
14199 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14201 (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ")
14202 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14204 "mcmpgt.w %N1, %N2, %0"
14205 [(set_attr "type" "mcmp_media")
14206 (set_attr "highpart" "depend")])
14208 (define_insn "mcmv"
14209 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14210 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14211 (match_operand:DI 2 "arith_reg_operand" "r"))
14212 (and:DI (match_operand:DI 3 "arith_reg_operand" "0")
14213 (not:DI (match_dup 2)))))]
14216 [(set_attr "type" "arith_media")
14217 (set_attr "highpart" "depend")])
14219 (define_insn "mcnvs_lw"
14220 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14222 (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ"))
14224 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))]
14226 "mcnvs.lw %N1, %N2, %0"
14227 [(set_attr "type" "mcmp_media")])
14229 (define_insn "mcnvs_wb"
14230 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14232 (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14234 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14236 "mcnvs.wb %N1, %N2, %0"
14237 [(set_attr "type" "mcmp_media")])
14239 (define_insn "mcnvs_wub"
14240 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
14242 (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ"))
14244 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))]
14246 "mcnvs.wub %N1, %N2, %0"
14247 [(set_attr "type" "mcmp_media")])
14249 (define_insn "mextr_rl"
14250 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14251 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14252 (match_operand:HI 3 "mextr_bit_offset" "i"))
14253 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14254 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14255 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14257 static char templ[21];
14258 sprintf (templ, "mextr%d %%N1, %%N2, %%0",
14259 (int) INTVAL (operands[3]) >> 3);
14262 [(set_attr "type" "arith_media")])
14264 (define_insn "*mextr_lr"
14265 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14266 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14267 (match_operand:HI 3 "mextr_bit_offset" "i"))
14268 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14269 (match_operand:HI 4 "mextr_bit_offset" "i"))))]
14270 "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
14272 static char templ[21];
14273 sprintf (templ, "mextr%d %%N2, %%N1, %%0",
14274 (int) INTVAL (operands[4]) >> 3);
14277 [(set_attr "type" "arith_media")])
14279 ; mextrN can be modelled with vec_select / vec_concat, but the selection
14280 ; vector then varies depending on endianness.
14281 (define_expand "mextr1"
14282 [(match_operand:DI 0 "arith_reg_dest" "")
14283 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14284 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14287 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14288 GEN_INT (1 * 8), GEN_INT (7 * 8)));
14292 (define_expand "mextr2"
14293 [(match_operand:DI 0 "arith_reg_dest" "")
14294 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14295 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14298 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14299 GEN_INT (2 * 8), GEN_INT (6 * 8)));
14303 (define_expand "mextr3"
14304 [(match_operand:DI 0 "arith_reg_dest" "")
14305 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14306 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14309 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14310 GEN_INT (3 * 8), GEN_INT (5 * 8)));
14314 (define_expand "mextr4"
14315 [(match_operand:DI 0 "arith_reg_dest" "")
14316 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14317 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14320 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14321 GEN_INT (4 * 8), GEN_INT (4 * 8)));
14325 (define_expand "mextr5"
14326 [(match_operand:DI 0 "arith_reg_dest" "")
14327 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14328 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14331 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14332 GEN_INT (5 * 8), GEN_INT (3 * 8)));
14336 (define_expand "mextr6"
14337 [(match_operand:DI 0 "arith_reg_dest" "")
14338 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14339 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14342 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14343 GEN_INT (6 * 8), GEN_INT (2 * 8)));
14347 (define_expand "mextr7"
14348 [(match_operand:DI 0 "arith_reg_dest" "")
14349 (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14350 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")]
14353 emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2],
14354 GEN_INT (7 * 8), GEN_INT (1 * 8)));
14358 (define_expand "mmacfx_wl"
14359 [(match_operand:V2SI 0 "arith_reg_dest" "")
14360 (match_operand:V2HI 1 "extend_reg_operand" "")
14361 (match_operand:V2HI 2 "extend_reg_operand" "")
14362 (match_operand:V2SI 3 "arith_reg_operand" "")]
14365 emit_insn (gen_mmacfx_wl_i (operands[0], operands[3],
14366 operands[1], operands[2]));
14370 ;; This could be highpart ignore if it only had inputs 2 or 3, but input 1
14372 (define_insn "mmacfx_wl_i"
14373 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14375 (match_operand:V2SI 1 "arith_reg_operand" "0")
14380 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14381 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14384 "mmacfx.wl %2, %3, %0"
14385 [(set_attr "type" "mac_media")
14386 (set_attr "highpart" "depend")])
14388 (define_expand "mmacnfx_wl"
14389 [(match_operand:V2SI 0 "arith_reg_dest" "")
14390 (match_operand:V2HI 1 "extend_reg_operand" "")
14391 (match_operand:V2HI 2 "extend_reg_operand" "")
14392 (match_operand:V2SI 3 "arith_reg_operand" "")]
14395 emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3],
14396 operands[1], operands[2]));
14400 (define_insn "mmacnfx_wl_i"
14401 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14403 (match_operand:V2SI 1 "arith_reg_operand" "0")
14408 (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r"))
14409 (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r"))))
14412 "mmacnfx.wl %2, %3, %0"
14413 [(set_attr "type" "mac_media")
14414 (set_attr "highpart" "depend")])
14416 (define_insn "mulv2si3"
14417 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14418 (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14419 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
14421 "mmul.l %1, %2, %0"
14422 [(set_attr "type" "d2mpy_media")
14423 (set_attr "highpart" "depend")])
14425 (define_insn "mulv4hi3"
14426 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14427 (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14428 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
14430 "mmul.w %1, %2, %0"
14431 [(set_attr "type" "dmpy_media")
14432 (set_attr "highpart" "depend")])
14434 (define_insn "mmulfx_l"
14435 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14439 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14440 (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r")))
14443 "mmulfx.l %1, %2, %0"
14444 [(set_attr "type" "d2mpy_media")
14445 (set_attr "highpart" "depend")])
14447 (define_insn "mmulfx_w"
14448 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14452 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14453 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14456 "mmulfx.w %1, %2, %0"
14457 [(set_attr "type" "dmpy_media")
14458 (set_attr "highpart" "depend")])
14460 (define_insn "mmulfxrp_w"
14461 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14466 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14467 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14471 "mmulfxrp.w %1, %2, %0"
14472 [(set_attr "type" "dmpy_media")
14473 (set_attr "highpart" "depend")])
14476 (define_expand "mmulhi_wl"
14477 [(match_operand:V2SI 0 "arith_reg_dest" "")
14478 (match_operand:V4HI 1 "arith_reg_operand" "")
14479 (match_operand:V4HI 2 "arith_reg_operand" "")]
14482 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl)
14483 (operands[0], operands[1], operands[2]));
14487 (define_expand "mmullo_wl"
14488 [(match_operand:V2SI 0 "arith_reg_dest" "")
14489 (match_operand:V4HI 1 "arith_reg_operand" "")
14490 (match_operand:V4HI 2 "arith_reg_operand" "")]
14493 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl)
14494 (operands[0], operands[1], operands[2]));
14498 (define_insn "mmul23_wl"
14499 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14502 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14503 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14504 (parallel [(const_int 2) (const_int 3)])))]
14507 return (TARGET_LITTLE_ENDIAN
14508 ? "mmulhi.wl %1, %2, %0"
14509 : "mmullo.wl %1, %2, %0");
14511 [(set_attr "type" "dmpy_media")
14512 (set (attr "highpart")
14513 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14514 (const_string "user")))])
14516 (define_insn "mmul01_wl"
14517 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14520 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14521 (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r")))
14522 (parallel [(const_int 0) (const_int 1)])))]
14525 return (TARGET_LITTLE_ENDIAN
14526 ? "mmullo.wl %1, %2, %0"
14527 : "mmulhi.wl %1, %2, %0");
14529 [(set_attr "type" "dmpy_media")
14530 (set (attr "highpart")
14531 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14532 (const_string "user")))])
14535 (define_expand "mmulsum_wq"
14536 [(match_operand:DI 0 "arith_reg_dest" "")
14537 (match_operand:V4HI 1 "arith_reg_operand" "")
14538 (match_operand:V4HI 2 "arith_reg_operand" "")
14539 (match_operand:DI 3 "arith_reg_operand" "")]
14542 emit_insn (gen_mmulsum_wq_i (operands[0], operands[3],
14543 operands[1], operands[2]));
14547 (define_insn "mmulsum_wq_i"
14548 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14549 (plus:DI (match_operand:DI 1 "arith_reg_operand" "0")
14554 (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r"))
14555 (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r")))
14556 (parallel [(const_int 0)]))
14557 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14558 (sign_extend:V4DI (match_dup 3)))
14559 (parallel [(const_int 1)])))
14561 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14562 (sign_extend:V4DI (match_dup 3)))
14563 (parallel [(const_int 2)]))
14564 (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2))
14565 (sign_extend:V4DI (match_dup 3)))
14566 (parallel [(const_int 3)]))))))]
14568 "mmulsum.wq %2, %3, %0"
14569 [(set_attr "type" "mac_media")])
14571 (define_expand "mperm_w"
14572 [(match_operand:V4HI 0 "arith_reg_dest" "=r")
14573 (match_operand:V4HI 1 "arith_reg_operand" "r")
14574 (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")]
14577 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big)
14578 (operands[0], operands[1], operands[2]));
14582 ; This use of vec_select isn't exactly correct according to rtl.texi
14583 ; (because not constant), but it seems a straightforward extension.
14584 (define_insn "mperm_w_little"
14585 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14587 (match_operand:V4HI 1 "arith_reg_operand" "r")
14589 [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")
14590 (const_int 2) (const_int 0))
14591 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2))
14592 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4))
14593 (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))]
14594 "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN"
14595 "mperm.w %1, %N2, %0"
14596 [(set_attr "type" "arith_media")])
14598 (define_insn "mperm_w_big"
14599 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14601 (match_operand:V4HI 1 "arith_reg_operand" "r")
14603 [(zero_extract:QI (not:QI (match_operand:QI 2
14604 "extend_reg_or_0_operand" "rZ"))
14605 (const_int 2) (const_int 0))
14606 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2))
14607 (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4))
14608 (zero_extract:QI (not:QI (match_dup 2))
14609 (const_int 2) (const_int 6))])))]
14610 "TARGET_SHMEDIA && TARGET_BIG_ENDIAN"
14611 "mperm.w %1, %N2, %0"
14612 [(set_attr "type" "arith_media")])
14614 (define_insn "mperm_w0"
14615 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14616 (vec_duplicate:V4HI (truncate:HI (match_operand 1
14617 "trunc_hi_operand" "r"))))]
14619 "mperm.w %1, r63, %0"
14620 [(set_attr "type" "arith_media")
14621 (set_attr "highpart" "ignore")])
14623 (define_expand "msad_ubq"
14624 [(match_operand:DI 0 "arith_reg_dest" "")
14625 (match_operand:V8QI 1 "arith_reg_or_0_operand" "")
14626 (match_operand:V8QI 2 "arith_reg_or_0_operand" "")
14627 (match_operand:DI 3 "arith_reg_operand" "")]
14630 emit_insn (gen_msad_ubq_i (operands[0], operands[3],
14631 operands[1], operands[2]));
14635 (define_insn "msad_ubq_i"
14636 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14641 (match_operand:DI 1 "arith_reg_operand" "0")
14642 (abs:DI (vec_select:DI
14645 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14647 (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ")))
14648 (parallel [(const_int 0)]))))
14649 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14650 (zero_extend:V8DI (match_dup 3)))
14651 (parallel [(const_int 1)]))))
14653 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14654 (zero_extend:V8DI (match_dup 3)))
14655 (parallel [(const_int 2)])))
14656 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14657 (zero_extend:V8DI (match_dup 3)))
14658 (parallel [(const_int 3)])))))
14661 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14662 (zero_extend:V8DI (match_dup 3)))
14663 (parallel [(const_int 4)])))
14664 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14665 (zero_extend:V8DI (match_dup 3)))
14666 (parallel [(const_int 5)]))))
14668 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14669 (zero_extend:V8DI (match_dup 3)))
14670 (parallel [(const_int 6)])))
14671 (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2))
14672 (zero_extend:V8DI (match_dup 3)))
14673 (parallel [(const_int 7)])))))))]
14675 "msad.ubq %N2, %N3, %0"
14676 [(set_attr "type" "mac_media")])
14678 (define_insn "mshalds_l"
14679 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14682 (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r"))
14683 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14684 (const_int 31)))))]
14686 "mshalds.l %1, %2, %0"
14687 [(set_attr "type" "mcmp_media")
14688 (set_attr "highpart" "depend")])
14690 (define_insn "mshalds_w"
14691 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14694 (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r"))
14695 (and:DI (match_operand:DI 2 "arith_reg_operand" "r")
14696 (const_int 15)))))]
14698 "mshalds.w %1, %2, %0"
14699 [(set_attr "type" "mcmp_media")
14700 (set_attr "highpart" "depend")])
14702 (define_insn "ashrv2si3"
14703 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14704 (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
14705 (match_operand:DI 2 "arith_reg_operand" "r")))]
14707 "mshard.l %1, %2, %0"
14708 [(set_attr "type" "arith_media")
14709 (set_attr "highpart" "depend")])
14711 (define_insn "ashrv4hi3"
14712 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14713 (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
14714 (match_operand:DI 2 "arith_reg_operand" "r")))]
14716 "mshard.w %1, %2, %0"
14717 [(set_attr "type" "arith_media")
14718 (set_attr "highpart" "depend")])
14720 (define_insn "mshards_q"
14721 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
14723 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r")
14724 (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))]
14726 "mshards.q %1, %N2, %0"
14727 [(set_attr "type" "mcmp_media")])
14729 (define_expand "mshfhi_b"
14730 [(match_operand:V8QI 0 "arith_reg_dest" "")
14731 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14732 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14735 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b)
14736 (operands[0], operands[1], operands[2]));
14740 (define_expand "mshflo_b"
14741 [(match_operand:V8QI 0 "arith_reg_dest" "")
14742 (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14743 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")]
14746 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b)
14747 (operands[0], operands[1], operands[2]));
14751 (define_insn "mshf4_b"
14753 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14755 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14756 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14757 (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13)
14758 (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))]
14761 return (TARGET_LITTLE_ENDIAN
14762 ? "mshfhi.b %N1, %N2, %0"
14763 : "mshflo.b %N1, %N2, %0");
14765 [(set_attr "type" "arith_media")
14766 (set (attr "highpart")
14767 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14768 (const_string "user")))])
14770 (define_insn "mshf0_b"
14772 (match_operand:V8QI 0 "arith_reg_dest" "=r")
14774 (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
14775 (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))
14776 (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9)
14777 (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))]
14780 return (TARGET_LITTLE_ENDIAN
14781 ? "mshflo.b %N1, %N2, %0"
14782 : "mshfhi.b %N1, %N2, %0");
14784 [(set_attr "type" "arith_media")
14785 (set (attr "highpart")
14786 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14787 (const_string "user")))])
14789 (define_expand "mshfhi_l"
14790 [(match_operand:V2SI 0 "arith_reg_dest" "")
14791 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14792 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14795 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l)
14796 (operands[0], operands[1], operands[2]));
14800 (define_expand "mshflo_l"
14801 [(match_operand:V2SI 0 "arith_reg_dest" "")
14802 (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14803 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")]
14806 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l)
14807 (operands[0], operands[1], operands[2]));
14811 (define_insn "mshf4_l"
14812 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14814 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14815 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14816 (parallel [(const_int 1) (const_int 3)])))]
14819 return (TARGET_LITTLE_ENDIAN
14820 ? "mshfhi.l %N1, %N2, %0"
14821 : "mshflo.l %N1, %N2, %0");
14823 [(set_attr "type" "arith_media")
14824 (set (attr "highpart")
14825 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14826 (const_string "user")))])
14828 (define_insn "mshf0_l"
14829 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
14831 (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
14832 (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))
14833 (parallel [(const_int 0) (const_int 2)])))]
14836 return (TARGET_LITTLE_ENDIAN
14837 ? "mshflo.l %N1, %N2, %0"
14838 : "mshfhi.l %N1, %N2, %0");
14840 [(set_attr "type" "arith_media")
14841 (set (attr "highpart")
14842 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14843 (const_string "user")))])
14845 (define_expand "mshfhi_w"
14846 [(match_operand:V4HI 0 "arith_reg_dest" "")
14847 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14848 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14851 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w)
14852 (operands[0], operands[1], operands[2]));
14856 (define_expand "mshflo_w"
14857 [(match_operand:V4HI 0 "arith_reg_dest" "")
14858 (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14859 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")]
14862 emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w)
14863 (operands[0], operands[1], operands[2]));
14867 (define_insn "mshf4_w"
14868 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14870 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14871 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
14872 (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))]
14875 return (TARGET_LITTLE_ENDIAN
14876 ? "mshfhi.w %N1, %N2, %0"
14877 : "mshflo.w %N1, %N2, %0");
14879 [(set_attr "type" "arith_media")
14880 (set (attr "highpart")
14881 (cond [(eq_attr "endian" "big") (const_string "ignore")]
14882 (const_string "user")))])
14884 (define_insn "mshf0_w"
14885 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14887 (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
14888 (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))
14889 (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))]
14892 return (TARGET_LITTLE_ENDIAN
14893 ? "mshflo.w %N1, %N2, %0"
14894 : "mshfhi.w %N1, %N2, %0");
14896 [(set_attr "type" "arith_media")
14897 (set (attr "highpart")
14898 (cond [(eq_attr "endian" "little") (const_string "ignore")]
14899 (const_string "user")))])
14901 (define_insn "mshflo_w_x"
14902 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
14904 (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ")
14905 (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ"))
14906 (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
14908 "mshflo.w %N1, %N2, %0"
14909 [(set_attr "type" "arith_media")
14910 (set_attr "highpart" "ignore")])
14912 ;; These are useful to expand ANDs and as combiner patterns.
14913 (define_insn_and_split "mshfhi_l_di"
14914 [(set (match_operand:DI 0 "arith_reg_dest" "=r,f")
14915 (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")
14917 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f")
14918 (const_int -4294967296))))]
14921 mshfhi.l %N1, %N2, %0
14923 "TARGET_SHMEDIA && reload_completed
14924 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
14925 [(set (match_dup 3) (match_dup 4))
14926 (set (match_dup 5) (match_dup 6))]
14928 operands[3] = gen_lowpart (SImode, operands[0]);
14929 operands[4] = gen_highpart (SImode, operands[1]);
14930 operands[5] = gen_highpart (SImode, operands[0]);
14931 operands[6] = gen_highpart (SImode, operands[2]);
14933 [(set_attr "type" "arith_media")])
14935 (define_insn "*mshfhi_l_di_rev"
14936 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14937 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14938 (const_int -4294967296))
14939 (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14942 "mshfhi.l %N2, %N1, %0"
14943 [(set_attr "type" "arith_media")])
14946 [(set (match_operand:DI 0 "arith_reg_dest" "")
14947 (ior:DI (zero_extend:DI (match_operand:SI 1
14948 "extend_reg_or_0_operand" ""))
14949 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "")
14950 (const_int -4294967296))))
14951 (clobber (match_operand:DI 3 "arith_reg_dest" ""))]
14955 emit_insn (gen_ashldi3_media (operands[3],
14956 simplify_gen_subreg (DImode, operands[1],
14959 emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2]));
14963 (define_insn "mshflo_l_di"
14964 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14965 (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14966 (const_int 4294967295))
14967 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14971 "mshflo.l %N1, %N2, %0"
14972 [(set_attr "type" "arith_media")
14973 (set_attr "highpart" "ignore")])
14975 (define_insn "*mshflo_l_di_rev"
14976 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14977 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
14979 (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
14980 (const_int 4294967295))))]
14983 "mshflo.l %N2, %N1, %0"
14984 [(set_attr "type" "arith_media")
14985 (set_attr "highpart" "ignore")])
14987 ;; Combiner pattern for trampoline initialization.
14988 (define_insn_and_split "*double_shori"
14989 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
14990 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
14992 (match_operand:DI 2 "const_int_operand" "n")))]
14994 && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)"
14996 "rtx_equal_p (operands[0], operands[1])"
14999 HOST_WIDE_INT v = INTVAL (operands[2]);
15001 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16)));
15002 emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535)));
15005 [(set_attr "highpart" "ignore")])
15007 (define_insn "*mshflo_l_di_x"
15008 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15009 (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand"
15011 (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")
15014 "mshflo.l %N1, %N2, %0"
15015 [(set_attr "type" "arith_media")
15016 (set_attr "highpart" "ignore")])
15018 (define_insn_and_split "concat_v2sf"
15019 [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?")
15020 ;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f")
15021 (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f")
15022 (match_operand:SF 2 "register_operand" "rZ,f,f")))]
15025 mshflo.l %N1, %N2, %0
15028 "TARGET_SHMEDIA && reload_completed
15029 && ! GENERAL_REGISTER_P (true_regnum (operands[0]))"
15030 [(set (match_dup 3) (match_dup 1))
15031 (set (match_dup 4) (match_dup 2))]
15033 operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0);
15034 operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4);
15036 [(set_attr "type" "arith_media")
15037 (set_attr "highpart" "ignore")])
15039 (define_insn "*mshflo_l_di_x_rev"
15040 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15041 (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ")
15044 (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))]
15046 "mshflo.l %N2, %N1, %0"
15047 [(set_attr "type" "arith_media")
15048 (set_attr "highpart" "ignore")])
15050 (define_insn "ashlv2si3"
15051 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15052 (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15053 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15055 "mshlld.l %1, %2, %0"
15056 [(set_attr "type" "arith_media")
15057 (set_attr "highpart" "depend")])
15060 [(set (match_operand 0 "any_register_operand" "")
15061 (match_operator 3 "shift_operator"
15062 [(match_operand 1 "any_register_operand" "")
15063 (match_operand 2 "shift_count_reg_operand" "")]))]
15064 "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)"
15065 [(set (match_dup 0) (match_dup 3))]
15067 rtx count = operands[2];
15068 machine_mode outer_mode = GET_MODE (operands[2]), inner_mode;
15070 while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND
15071 || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0)
15072 || GET_CODE (count) == TRUNCATE)
15073 count = XEXP (count, 0);
15074 inner_mode = GET_MODE (count);
15075 count = simplify_gen_subreg (outer_mode, count, inner_mode,
15076 subreg_lowpart_offset (outer_mode, inner_mode));
15077 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]),
15078 operands[1], count);
15081 (define_insn "ashlv4hi3"
15082 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15083 (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15084 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15086 "mshlld.w %1, %2, %0"
15087 [(set_attr "type" "arith_media")
15088 (set_attr "highpart" "depend")])
15090 (define_insn "lshrv2si3"
15091 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15092 (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")
15093 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15095 "mshlrd.l %1, %2, %0"
15096 [(set_attr "type" "arith_media")
15097 (set_attr "highpart" "depend")])
15099 (define_insn "lshrv4hi3"
15100 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15101 (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")
15102 (match_operand:DI 2 "shift_count_reg_operand" "r")))]
15104 "mshlrd.w %1, %2, %0"
15105 [(set_attr "type" "arith_media")
15106 (set_attr "highpart" "depend")])
15108 (define_insn "subv2si3"
15109 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15110 (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15111 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15113 "msub.l %N1, %2, %0"
15114 [(set_attr "type" "arith_media")
15115 (set_attr "highpart" "depend")])
15117 (define_insn "subv4hi3"
15118 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15119 (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15120 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15122 "msub.w %N1, %2, %0"
15123 [(set_attr "type" "arith_media")
15124 (set_attr "highpart" "depend")])
15126 (define_insn_and_split "subv2hi3"
15127 [(set (match_operand:V2HI 0 "arith_reg_dest" "=r")
15128 (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ")
15129 (match_operand:V2HI 2 "arith_reg_operand" "r")))]
15135 rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0);
15136 rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0);
15137 rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0);
15138 rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0);
15139 rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0);
15141 emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1));
15142 emit_insn (gen_truncdisi2 (si_dst, di_dst));
15145 [(set_attr "highpart" "must_split")])
15147 (define_insn "sssubv2si3"
15148 [(set (match_operand:V2SI 0 "arith_reg_dest" "=r")
15149 (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")
15150 (match_operand:V2SI 2 "arith_reg_operand" "r")))]
15152 "msubs.l %N1, %2, %0"
15153 [(set_attr "type" "mcmp_media")
15154 (set_attr "highpart" "depend")])
15156 (define_insn "ussubv8qi3"
15157 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15158 (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ")
15159 (match_operand:V8QI 2 "arith_reg_operand" "r")))]
15161 "msubs.ub %N1, %2, %0"
15162 [(set_attr "type" "mcmp_media")
15163 (set_attr "highpart" "depend")])
15165 (define_insn "sssubv4hi3"
15166 [(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
15167 (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")
15168 (match_operand:V4HI 2 "arith_reg_operand" "r")))]
15170 "msubs.w %N1, %2, %0"
15171 [(set_attr "type" "mcmp_media")
15172 (set_attr "highpart" "depend")])
15174 ;; -------------------------------------------------------------------------
15175 ;; Floating Point Intrinsics
15176 ;; -------------------------------------------------------------------------
15178 (define_insn "fcosa_s"
15179 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15180 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15184 [(set_attr "type" "atrans_media")])
15186 (define_insn "fsina_s"
15187 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15188 (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")]
15192 [(set_attr "type" "atrans_media")])
15194 (define_insn "fipr"
15195 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15196 (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1
15197 "fp_arith_reg_operand" "f")
15198 (match_operand:V4SF 2
15199 "fp_arith_reg_operand" "f"))
15200 (parallel [(const_int 0)]))
15201 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15202 (parallel [(const_int 1)])))
15203 (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15204 (parallel [(const_int 2)]))
15205 (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2))
15206 (parallel [(const_int 3)])))))]
15208 "fipr.s %1, %2, %0"
15209 [(set_attr "type" "fparith_media")])
15211 (define_insn "fsrra_s"
15212 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
15213 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")]
15217 [(set_attr "type" "atrans_media")])
15219 (define_insn "ftrv"
15220 [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f")
15224 (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f")
15225 (parallel [(const_int 0) (const_int 5)
15226 (const_int 10) (const_int 15)]))
15227 (match_operand:V4SF 2 "fp_arith_reg_operand" "f"))
15229 (vec_select:V4SF (match_dup 1)
15230 (parallel [(const_int 4) (const_int 9)
15231 (const_int 14) (const_int 3)]))
15232 (vec_select:V4SF (match_dup 2)
15233 (parallel [(const_int 1) (const_int 2)
15234 (const_int 3) (const_int 0)]))))
15237 (vec_select:V4SF (match_dup 1)
15238 (parallel [(const_int 8) (const_int 13)
15239 (const_int 2) (const_int 7)]))
15240 (vec_select:V4SF (match_dup 2)
15241 (parallel [(const_int 2) (const_int 3)
15242 (const_int 0) (const_int 1)])))
15244 (vec_select:V4SF (match_dup 1)
15245 (parallel [(const_int 12) (const_int 1)
15246 (const_int 6) (const_int 11)]))
15247 (vec_select:V4SF (match_dup 2)
15248 (parallel [(const_int 3) (const_int 0)
15249 (const_int 1) (const_int 2)]))))))]
15251 "ftrv.s %1, %2, %0"
15252 [(set_attr "type" "fparith_media")])
15254 (define_insn "ldhi_l"
15255 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15257 (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15260 (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1))
15264 [(set_attr "type" "load_media")])
15266 (define_insn "ldhi_q"
15267 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15269 (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p")
15272 (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1))
15276 [(set_attr "type" "load_media")])
15278 (define_insn_and_split "*ldhi_q_comb0"
15279 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15281 (mem:DI (plus:SI (ior:SI (plus:SI
15282 (match_operand:SI 1 "register_operand" "r")
15283 (match_operand:SI 2 "ua_offset" "I06"))
15286 (plus:SI (and:SI (match_dup 1) (const_int 7))
15289 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15294 emit_insn (gen_ldhi_q (operands[0],
15295 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15299 (define_insn_and_split "*ldhi_q_comb1"
15300 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15302 (mem:DI (plus:SI (ior:SI (plus:SI
15303 (match_operand:SI 1 "register_operand" "r")
15304 (match_operand:SI 2 "ua_offset" "I06"))
15307 (plus:SI (and:SI (plus:SI (match_dup 1)
15308 (match_operand:SI 3 "ua_offset" "I06"))
15312 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15313 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15318 emit_insn (gen_ldhi_q (operands[0],
15319 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15323 (define_insn "ldlo_l"
15324 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15326 (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15328 (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3)))
15329 (and:SI (match_dup 1) (const_int 3))))]
15332 [(set_attr "type" "load_media")])
15334 (define_insn "ldlo_q"
15335 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15337 (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p")
15339 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15340 (and:SI (match_dup 1) (const_int 7))))]
15343 [(set_attr "type" "load_media")])
15345 (define_insn_and_split "*ldlo_q_comb0"
15346 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15348 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15349 (match_operand:SI 2 "ua_offset" "I06"))
15351 (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7)))
15352 (and:SI (match_dup 1) (const_int 7))))]
15353 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0"
15358 emit_insn (gen_ldlo_q (operands[0],
15359 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15363 (define_insn_and_split "*ldlo_q_comb1"
15364 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15366 (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
15367 (match_operand:SI 2 "ua_offset" "I06"))
15369 (minus:SI (const_int 8)
15370 (and:SI (plus:SI (match_dup 1)
15371 (match_operand:SI 3 "ua_offset" "I06"))
15373 (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))]
15374 "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8)
15375 && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])"
15380 emit_insn (gen_ldlo_q (operands[0],
15381 gen_rtx_PLUS (SImode, operands[1], operands[2])));
15385 (define_insn "sthi_l"
15386 [(set (zero_extract:SI
15387 (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15390 (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1))
15392 (match_operand:SI 1 "arith_reg_operand" "r"))]
15395 [(set_attr "type" "ustore_media")])
15397 ;; All unaligned stores are considered to be 'narrow' because they typically
15398 ;; operate on less that a quadword, and when they operate on a full quadword,
15399 ;; the vanilla store high / store low sequence will cause a stall if not
15400 ;; scheduled apart.
15401 (define_insn "sthi_q"
15402 [(set (zero_extract:DI
15403 (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p")
15406 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15408 (match_operand:DI 1 "arith_reg_operand" "r"))]
15411 [(set_attr "type" "ustore_media")])
15413 (define_insn_and_split "*sthi_q_comb0"
15414 [(set (zero_extract:DI
15415 (mem:DI (plus:SI (ior:SI (plus:SI
15416 (match_operand:SI 0 "register_operand" "r")
15417 (match_operand:SI 1 "ua_offset" "I06"))
15420 (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1))
15422 (match_operand:DI 2 "arith_reg_operand" "r"))]
15423 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15428 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15433 (define_insn_and_split "*sthi_q_comb1"
15434 [(set (zero_extract:DI
15435 (mem:DI (plus:SI (ior:SI (plus:SI
15436 (match_operand:SI 0 "register_operand" "r")
15437 (match_operand:SI 1 "ua_offset" "I06"))
15440 (plus:SI (and:SI (plus:SI (match_dup 0)
15441 (match_operand:SI 2 "ua_offset" "I06"))
15445 (match_operand:DI 3 "arith_reg_operand" "r"))]
15446 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8)
15447 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15452 emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15457 ;; This is highpart user because the address is used as full 64 bit.
15458 (define_insn "stlo_l"
15459 [(set (zero_extract:SI
15460 (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15462 (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3)))
15463 (and:SI (match_dup 0) (const_int 3)))
15464 (match_operand:SI 1 "arith_reg_operand" "r"))]
15467 [(set_attr "type" "ustore_media")])
15469 (define_insn "stlo_q"
15470 [(set (zero_extract:DI
15471 (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p")
15473 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15474 (and:SI (match_dup 0) (const_int 7)))
15475 (match_operand:DI 1 "arith_reg_operand" "r"))]
15478 [(set_attr "type" "ustore_media")])
15480 (define_insn_and_split "*stlo_q_comb0"
15481 [(set (zero_extract:DI
15482 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15483 (match_operand:SI 1 "ua_offset" "I06"))
15485 (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7)))
15486 (and:SI (match_dup 0) (const_int 7)))
15487 (match_operand:DI 2 "arith_reg_operand" "r"))]
15488 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0"
15493 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15498 (define_insn_and_split "*stlo_q_comb1"
15499 [(set (zero_extract:DI
15500 (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
15501 (match_operand:SI 1 "ua_offset" "I06"))
15503 (minus:SI (const_int 8)
15504 (and:SI (plus:SI (match_dup 0)
15505 (match_operand:SI 2 "ua_offset" "I06"))
15507 (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7)))
15508 (match_operand:DI 3 "arith_reg_operand" "r"))]
15509 "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])"
15514 emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]),
15519 (define_insn "ldhi_l64"
15520 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15522 (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15525 (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1))
15529 [(set_attr "type" "load_media")])
15531 (define_insn "ldhi_q64"
15532 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15534 (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p")
15537 (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1))
15541 [(set_attr "type" "load_media")])
15543 (define_insn "ldlo_l64"
15544 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15546 (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15548 (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3)))
15549 (and:DI (match_dup 1) (const_int 3))))]
15552 [(set_attr "type" "load_media")])
15554 (define_insn "ldlo_q64"
15555 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15557 (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p")
15559 (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7)))
15560 (and:DI (match_dup 1) (const_int 7))))]
15563 [(set_attr "type" "load_media")])
15565 (define_insn "sthi_l64"
15566 [(set (zero_extract:SI
15567 (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15570 (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1))
15572 (match_operand:SI 1 "arith_reg_operand" "r"))]
15575 [(set_attr "type" "ustore_media")])
15577 (define_insn "sthi_q64"
15578 [(set (zero_extract:DI
15579 (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p")
15582 (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1))
15584 (match_operand:DI 1 "arith_reg_operand" "r"))]
15587 [(set_attr "type" "ustore_media")])
15589 (define_insn "stlo_l64"
15590 [(set (zero_extract:SI
15591 (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15593 (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3)))
15594 (and:DI (match_dup 0) (const_int 3)))
15595 (match_operand:SI 1 "arith_reg_operand" "r"))]
15598 [(set_attr "type" "ustore_media")])
15600 (define_insn "stlo_q64"
15601 [(set (zero_extract:DI
15602 (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p")
15604 (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7)))
15605 (and:DI (match_dup 0) (const_int 7)))
15606 (match_operand:DI 1 "arith_reg_operand" "r"))]
15609 [(set_attr "type" "ustore_media")])
15612 [(set (match_operand:QI 0 "arith_reg_dest" "=r")
15613 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15617 [(set_attr "type" "arith_media")])
15619 (define_insn "nsbsi"
15620 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
15622 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15626 [(set_attr "type" "arith_media")])
15628 (define_insn "nsbdi"
15629 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
15631 (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")]
15635 [(set_attr "type" "arith_media")])
15637 (define_expand "ffsdi2"
15638 [(set (match_operand:DI 0 "arith_reg_dest" "")
15639 (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))]
15642 rtx scratch = gen_reg_rtx (DImode);
15645 emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx));
15646 emit_insn (gen_xordi3 (scratch, operands[1], scratch));
15647 emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx));
15648 emit_insn (gen_nsbdi (scratch, scratch));
15649 emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64)));
15650 emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch));
15651 last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch));
15652 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0]));
15657 (define_expand "ffssi2"
15658 [(set (match_operand:SI 0 "arith_reg_dest" "")
15659 (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))]
15662 rtx scratch = gen_reg_rtx (SImode);
15663 rtx discratch = gen_reg_rtx (DImode);
15666 emit_insn (gen_adddi3 (discratch,
15667 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15669 emit_insn (gen_andcdi3 (discratch,
15670 simplify_gen_subreg (DImode, operands[1], SImode, 0),
15672 emit_insn (gen_nsbsi (scratch, discratch));
15673 last = emit_insn (gen_subsi3 (operands[0],
15674 force_reg (SImode, GEN_INT (63)), scratch));
15675 set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0]));
15680 (define_insn "byterev"
15681 [(set (match_operand:V8QI 0 "arith_reg_dest" "=r")
15682 (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r")
15683 (parallel [(const_int 7) (const_int 6) (const_int 5)
15684 (const_int 4) (const_int 3) (const_int 2)
15685 (const_int 1) (const_int 0)])))]
15688 [(set_attr "type" "arith_media")])
15690 ;; In user mode, the "pref" instruction will raise a RADDERR exception
15691 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
15692 ;; implementation of __builtin_prefetch for VxWorks RTPs.
15693 (define_expand "prefetch"
15694 [(prefetch (match_operand 0 "address_operand" "")
15695 (match_operand:SI 1 "const_int_operand" "")
15696 (match_operand:SI 2 "const_int_operand" ""))]
15697 "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
15698 && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
15700 (define_insn "*prefetch"
15701 [(prefetch (match_operand:SI 0 "register_operand" "r")
15702 (match_operand:SI 1 "const_int_operand" "n")
15703 (match_operand:SI 2 "const_int_operand" "n"))]
15704 "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
15706 [(set_attr "type" "other")])
15708 (define_insn "*prefetch_media"
15709 [(prefetch (match_operand:QI 0 "address_operand" "p")
15710 (match_operand:SI 1 "const_int_operand" "n")
15711 (match_operand:SI 2 "const_int_operand" "n"))]
15714 operands[0] = gen_rtx_MEM (QImode, operands[0]);
15715 output_asm_insn ("ld%M0.b %m0,r63", operands);
15718 [(set_attr "type" "other")])
15720 (define_insn "alloco_i"
15721 [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
15722 (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
15727 if (GET_CODE (operands[0]) == PLUS)
15729 xops[0] = XEXP (operands[0], 0);
15730 xops[1] = XEXP (operands[0], 1);
15734 xops[0] = operands[0];
15735 xops[1] = const0_rtx;
15737 output_asm_insn ("alloco %0, %1", xops);
15740 [(set_attr "type" "other")])
15743 [(set (match_operand 0 "any_register_operand" "")
15744 (match_operand 1 "" ""))]
15745 "TARGET_SHMEDIA && reload_completed"
15746 [(set (match_dup 0) (match_dup 1))]
15748 if (!shmedia_cleanup_truncate (operands[1]))
15752 ;; -------------------------------------------------------------------------
15753 ;; Stack Protector Patterns
15754 ;; -------------------------------------------------------------------------
15756 (define_expand "stack_protect_set"
15757 [(set (match_operand 0 "memory_operand" "")
15758 (match_operand 1 "memory_operand" ""))]
15761 if (TARGET_SHMEDIA)
15763 if (TARGET_SHMEDIA64)
15764 emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1]));
15766 emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1]));
15769 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
15774 (define_insn "stack_protect_set_si"
15775 [(set (match_operand:SI 0 "memory_operand" "=m")
15776 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15777 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15780 return "mov.l %1,%2" "\n"
15781 " mov.l %2,%0" "\n"
15784 [(set_attr "type" "other")
15785 (set_attr "length" "6")])
15787 (define_insn "stack_protect_set_si_media"
15788 [(set (match_operand:SI 0 "memory_operand" "=m")
15789 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15790 (set (match_scratch:SI 2 "=&r") (const_int 0))]
15793 return "ld%M1.l %m1,%2" "\n"
15794 " st%M0.l %m0,%2" "\n"
15797 [(set_attr "type" "other")
15798 (set_attr "length" "12")])
15800 (define_insn "stack_protect_set_di_media"
15801 [(set (match_operand:DI 0 "memory_operand" "=m")
15802 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
15803 (set (match_scratch:DI 2 "=&r") (const_int 0))]
15806 return "ld%M1.q %m1,%2" "\n"
15807 " st%M0.q %m0,%2" "\n"
15810 [(set_attr "type" "other")
15811 (set_attr "length" "12")])
15813 (define_expand "stack_protect_test"
15814 [(match_operand 0 "memory_operand" "")
15815 (match_operand 1 "memory_operand" "")
15816 (match_operand 2 "" "")]
15819 if (TARGET_SHMEDIA)
15821 rtx tmp = gen_reg_rtx (GET_MODE (operands[0]));
15824 test = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15825 if (TARGET_SHMEDIA64)
15827 emit_insn (gen_stack_protect_test_di_media (tmp, operands[0],
15829 emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2]));
15833 emit_insn (gen_stack_protect_test_si_media (tmp, operands[0],
15835 emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2]));
15840 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
15841 emit_jump_insn (gen_branch_true (operands[2]));
15847 (define_insn "stack_protect_test_si"
15848 [(set (reg:SI T_REG)
15849 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
15850 (match_operand:SI 1 "memory_operand" "m")]
15852 (set (match_scratch:SI 2 "=&r") (const_int 0))
15853 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15856 return "mov.l %0,%2" "\n"
15857 " mov.l %1,%3" "\n"
15858 " cmp/eq %2,%3" "\n"
15862 [(set_attr "type" "other")
15863 (set_attr "length" "10")])
15865 (define_insn "stack_protect_test_si_media"
15866 [(set (match_operand:SI 0 "register_operand" "=&r")
15867 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
15868 (match_operand:SI 2 "memory_operand" "m")]
15870 (set (match_scratch:SI 3 "=&r") (const_int 0))]
15873 return "ld%M1.l %m1,%0" "\n"
15874 " ld%M2.l %m2,%3" "\n"
15875 " cmpeq %0,%3,%0" "\n"
15878 [(set_attr "type" "other")
15879 (set_attr "length" "16")])
15881 (define_insn "stack_protect_test_di_media"
15882 [(set (match_operand:DI 0 "register_operand" "=&r")
15883 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
15884 (match_operand:DI 2 "memory_operand" "m")]
15886 (set (match_scratch:DI 3 "=&r") (const_int 0))]
15889 return "ld%M1.q %m1,%0" "\n"
15890 " ld%M2.q %m2,%3" "\n"
15891 " cmpeq %0,%3,%0" "\n"
15894 [(set_attr "type" "other")
15895 (set_attr "length" "16")])
15897 ;; -------------------------------------------------------------------------
15898 ;; Atomic operations
15899 ;; -------------------------------------------------------------------------
15901 (include "sync.md")