1 ;; Predicate definitions for Renesas / SuperH SH.
2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; TODO: Add a comment here.
21 (define_predicate "trapping_target_operand"
22 (match_code "if_then_else")
24 rtx cond, mem, res, tar, and_expr;
26 if (GET_MODE (op) != PDImode)
32 || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
35 if (!rtx_equal_p (XEXP (mem, 0), tar)
36 || GET_MODE (tar) != Pmode)
38 if (GET_CODE (cond) == CONST)
40 cond = XEXP (cond, 0);
41 if (!satisfies_constraint_Csy (tar))
43 if (GET_CODE (tar) == CONST)
46 else if (!arith_reg_operand (tar, VOIDmode)
47 && ! satisfies_constraint_Csy (tar))
49 if (GET_CODE (cond) != EQ)
51 and_expr = XEXP (cond, 0);
52 return (GET_CODE (and_expr) == AND
53 && rtx_equal_p (XEXP (and_expr, 0), tar)
54 && CONST_INT_P (XEXP (and_expr, 1))
55 && CONST_INT_P (XEXP (cond, 1))
56 && INTVAL (XEXP (and_expr, 1)) == 3
57 && INTVAL (XEXP (cond, 1)) == 3);
60 ;; A logical operand that can be used in an shmedia and insn.
61 (define_predicate "and_operand"
62 (match_code "subreg,reg,const_int")
64 if (logical_operand (op, mode))
67 /* Check mshflo.l / mshflhi.l opportunities. */
70 && satisfies_constraint_J16 (op))
76 ;; Like arith_reg_dest, but this predicate is defined with
77 ;; define_special_predicate, not define_predicate.
78 (define_special_predicate "any_arith_reg_dest"
79 (match_code "subreg,reg")
81 return arith_reg_dest (op, mode);
84 ;; Like register_operand, but this predicate is defined with
85 ;; define_special_predicate, not define_predicate.
86 (define_special_predicate "any_register_operand"
87 (match_code "subreg,reg")
89 return register_operand (op, mode);
92 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
93 (define_predicate "arith_operand"
94 (match_code "subreg,reg,const_int,truncate")
96 if (arith_reg_operand (op, mode))
101 /* FIXME: We should be checking whether the CONST_INT fits in a
102 signed 16-bit here, but this causes reload_cse to crash when
103 attempting to transform a sequence of two 64-bit sets of the
104 same register from literal constants into a set and an add,
105 when the difference is too wide for an add. */
107 || satisfies_constraint_Css (op))
109 else if (GET_CODE (op) == TRUNCATE
110 && REG_P (XEXP (op, 0))
111 && ! system_reg_operand (XEXP (op, 0), VOIDmode)
112 && (mode == VOIDmode || mode == GET_MODE (op))
113 && (GET_MODE_SIZE (GET_MODE (op))
114 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
115 && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
116 || GET_MODE_SIZE (GET_MODE (op)) == 4))
117 return register_operand (XEXP (op, 0), VOIDmode);
121 else if (satisfies_constraint_I08 (op))
127 ;; Like above, but for DImode destinations: forbid paradoxical DImode
128 ;; subregs, because this would lead to missing sign extensions when
129 ;; truncating from DImode to SImode.
130 (define_predicate "arith_reg_dest"
131 (match_code "subreg,reg")
133 if (mode == DImode && GET_CODE (op) == SUBREG
134 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
137 return arith_reg_operand (op, mode);
140 ;; Returns 1 if OP is a normal arithmetic register.
141 (define_predicate "arith_reg_operand"
142 (match_code "subreg,reg,sign_extend")
144 if (register_operand (op, mode))
150 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
151 regno = REGNO (SUBREG_REG (op));
155 return (regno != T_REG && regno != PR_REG
156 && ! TARGET_REGISTER_P (regno)
157 && regno != FPUL_REG && regno != FPSCR_REG
158 && regno != MACH_REG && regno != MACL_REG);
160 /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
161 We allow SImode here, as not using an FP register is just a matter of
162 proper register allocation. */
164 && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
165 && GET_MODE (XEXP (op, 0)) == SImode
166 && GET_CODE (XEXP (op, 0)) != SUBREG)
167 return register_operand (XEXP (op, 0), VOIDmode);
168 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
169 if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
170 && GET_MODE (XEXP (op, 0)) == HImode
171 && REG_P (XEXP (op, 0))
172 && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
173 return register_operand (XEXP (op, 0), VOIDmode);
175 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
176 && GET_CODE (op) == SUBREG
177 && GET_MODE (SUBREG_REG (op)) == DImode
178 && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
179 && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
180 && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
181 return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
185 ;; Returns 1 if OP is a valid source operand for a compare insn.
186 (define_predicate "arith_reg_or_0_operand"
187 (match_code "subreg,reg,const_int,const_vector")
189 if (arith_reg_operand (op, mode))
192 if (satisfies_constraint_Z (op))
198 ;; Returns true if OP is either a register or constant 0 or constant 1.
199 (define_predicate "arith_reg_or_0_or_1_operand"
200 (match_code "subreg,reg,const_int,const_vector")
202 return arith_reg_or_0_operand (op, mode) || satisfies_constraint_M (op);
205 ;; Returns true if OP is a suitable constant for the minimum value of a
206 ;; clips.b or clips.w insn.
207 (define_predicate "clips_min_const_int"
208 (and (match_code "const_int")
209 (ior (match_test "INTVAL (op) == -128")
210 (match_test "INTVAL (op) == -32768"))))
212 ;; Returns true if OP is a suitable constant for the maximum value of a
213 ;; clips.b or clips.w insn.
214 (define_predicate "clips_max_const_int"
215 (and (match_code "const_int")
216 (ior (match_test "INTVAL (op) == 127")
217 (match_test "INTVAL (op) == 32767"))))
219 ;; Returns true if OP is a suitable constant for the maximum value of a
220 ;; clipu.b or clipu.w insn.
221 (define_predicate "clipu_max_const_int"
222 (and (match_code "const_int")
223 (ior (match_test "INTVAL (op) == 255")
224 (match_test "INTVAL (op) == 65535"))))
226 ;; Returns 1 if OP is a floating point operator with two operands.
227 (define_predicate "binary_float_operator"
228 (and (match_code "plus,minus,mult,div")
229 (match_test "GET_MODE (op) == mode")))
231 ;; Returns 1 if OP is a logical operator with two operands.
232 (define_predicate "binary_logical_operator"
233 (and (match_code "and,ior,xor")
234 (match_test "GET_MODE (op) == mode")))
236 ;; Return 1 if OP is an address suitable for a cache manipulation operation.
237 ;; MODE has the meaning as in address_operand.
238 (define_special_predicate "cache_address_operand"
239 (match_code "plus,reg")
241 if (GET_CODE (op) == PLUS)
243 if (!REG_P (XEXP (op, 0)))
245 if (!CONST_INT_P (XEXP (op, 1))
246 || (INTVAL (XEXP (op, 1)) & 31))
249 else if (!REG_P (op))
251 return address_operand (op, mode);
254 ;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
255 (define_predicate "cmp_operand"
256 (match_code "subreg,reg,const_int")
258 if (satisfies_constraint_N (op))
261 && mode != DImode && GET_CODE (op) == SUBREG
262 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
264 return arith_reg_operand (op, mode);
267 ;; Returns true if OP is an operand that can be used as the first operand in
268 ;; the cstoresi4 expander pattern.
269 (define_predicate "cmpsi_operand"
270 (match_code "subreg,reg,const_int")
272 if (REG_P (op) && REGNO (op) == T_REG
273 && GET_MODE (op) == SImode
276 return arith_operand (op, mode);
279 ;; Returns true if OP is a comutative float operator.
280 ;; This predicate is currently unused.
281 ;;(define_predicate "commutative_float_operator"
282 ;; (and (match_code "plus,mult")
283 ;; (match_test "GET_MODE (op) == mode")))
285 ;; Returns true if OP is a equal or not equal operator.
286 (define_predicate "equality_comparison_operator"
287 (match_code "eq,ne"))
289 ;; Returns true if OP is an arithmetic operand that is zero extended during
291 (define_predicate "extend_reg_operand"
292 (match_code "subreg,reg,truncate")
294 return (GET_CODE (op) == TRUNCATE
296 : arith_reg_operand) (op, mode);
299 ;; Like extend_reg_operand, but also allow a constant 0.
300 (define_predicate "extend_reg_or_0_operand"
301 (match_code "subreg,reg,truncate,const_int")
303 return (GET_CODE (op) == TRUNCATE
305 : arith_reg_or_0_operand) (op, mode);
308 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
309 (define_predicate "ext_dest_operand"
310 (match_code "subreg,reg")
312 return arith_reg_operand (op, mode);
315 ;; Returns true if OP can be used as a destination register for shmedia floating
316 ;; point to integer conversions.
317 (define_predicate "fp_arith_reg_dest"
318 (match_code "subreg,reg")
320 if (mode == DImode && GET_CODE (op) == SUBREG
321 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
323 return fp_arith_reg_operand (op, mode);
326 ;; Returns true if OP is a floating point register that can be used in floating
327 ;; point arithmetic operations.
328 (define_predicate "fp_arith_reg_operand"
329 (match_code "subreg,reg")
331 if (register_operand (op, mode))
337 else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
338 regno = REGNO (SUBREG_REG (op));
342 return (regno >= FIRST_PSEUDO_REGISTER
343 || FP_REGISTER_P (regno));
348 ;; Returns true if OP is the FPSCR.
349 (define_predicate "fpscr_operand"
350 (and (match_code "reg")
351 (match_test "REGNO (op) == FPSCR_REG")))
353 ;; Returns true if OP is a valid source operand for a FPSCR move insn.
354 (define_predicate "fpscr_movsrc_operand"
355 (match_code "reg,subreg,mem")
357 if (arith_reg_operand (op, mode))
360 return MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC;
363 ;; Returns true if OP is a valid destination operand for a FPSCR move insn.
364 (define_predicate "fpscr_movdst_operand"
365 (match_code "reg,subreg,mem")
367 if (arith_reg_dest (op, mode))
370 return MEM_P (op) && GET_CODE (XEXP (op, 0)) == PRE_DEC;
373 ;; Returns true if OP is an operand that is either the fpul hard reg or
374 ;; a pseudo. This prevents combine from propagating function arguments
375 ;; in hard regs into insns that need the operand in fpul. If it's a pseudo
376 ;; reload can fix it up.
377 (define_predicate "fpul_operand"
381 return fp_arith_reg_operand (op, mode);
384 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
385 && GET_MODE (op) == mode);
388 ;; Returns true if OP is a valid fpul input operand for the fsca insn.
389 ;; The value in fpul is a fixed-point value and its scaling is described
390 ;; in the fsca insn by a mult:SF. To allow pre-scaled fixed-point inputs
391 ;; in fpul we have to permit things like
393 ;; (fix:SF (float:SF (reg:SI)))
394 (define_predicate "fpul_fsca_operand"
395 (match_code "fix,reg")
397 if (fpul_operand (op, SImode))
399 if (GET_CODE (op) == FIX && GET_MODE (op) == SImode
400 && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode)
401 return fpul_fsca_operand (XEXP (XEXP (op, 0), 0),
402 GET_MODE (XEXP (XEXP (op, 0), 0)));
406 ;; Returns true if OP is a valid constant scale factor for the fsca insn.
407 (define_predicate "fsca_scale_factor"
408 (and (match_code "const_double")
409 (match_test "op == sh_fsca_int2sf ()")))
411 ;; Returns true if OP is an operand that is zero extended during an operation.
412 (define_predicate "general_extend_operand"
413 (match_code "subreg,reg,mem,truncate")
415 if (reload_completed && GET_CODE (op) == TRUNCATE)
416 return arith_operand (op, mode);
418 if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))
419 return general_movsrc_operand (op, mode);
421 return nonimmediate_operand (op, mode);
424 ;; Returns 1 if OP is a simple register address.
425 (define_predicate "simple_mem_operand"
426 (and (match_code "mem")
427 (match_test "arith_reg_operand (XEXP (op, 0), SImode)")))
429 ;; Returns 1 if OP is a valid displacement address.
430 (define_predicate "displacement_mem_operand"
431 (and (match_code "mem")
432 (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
433 (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)")
434 (match_test "sh_legitimate_index_p (GET_MODE (op),
435 XEXP (XEXP (op, 0), 1),
436 TARGET_SH2A, true)")))
438 ;; Returns true if OP is a displacement address that can fit into a
439 ;; 16 bit (non-SH2A) memory load / store insn.
440 (define_predicate "short_displacement_mem_operand"
441 (match_test "sh_disp_addr_displacement (op)
442 <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))
444 ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
445 (define_predicate "zero_extend_movu_operand"
446 (and (match_operand 0 "displacement_mem_operand")
447 (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode")))
449 ;; Returns 1 if the operand can be used in a zero_extend.
450 (define_predicate "zero_extend_operand"
451 (ior (and (match_test "TARGET_SHMEDIA")
452 (match_operand 0 "general_extend_operand"))
453 (and (match_test "! TARGET_SHMEDIA")
454 (match_operand 0 "arith_reg_operand"))
455 (and (match_test "TARGET_SH2A")
456 (match_operand 0 "zero_extend_movu_operand"))))
458 ;; Returns 1 if OP can be source of a simple move operation. Same as
459 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
460 ;; are subregs of system registers.
461 (define_predicate "general_movsrc_operand"
462 (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,
465 if (t_reg_operand (op, mode))
468 if (fpscr_operand (op, mode))
471 /* Disallow PC relative QImode loads, since these is no insn to do that
472 and an imm8 load should be used instead. */
473 if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode)
478 rtx inside = XEXP (op, 0);
480 /* Disallow mems with GBR address here. They have to go through
481 separate special patterns. */
482 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
483 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
484 && REGNO (XEXP (inside, 0)) == GBR_REG))
487 if (GET_CODE (inside) == CONST)
488 inside = XEXP (inside, 0);
490 if (GET_CODE (inside) == LABEL_REF)
493 if (GET_CODE (inside) == PLUS
494 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
495 && CONST_INT_P (XEXP (inside, 1)))
498 /* Only post inc allowed. */
499 if (GET_CODE (inside) == PRE_DEC)
503 if (mode == GET_MODE (op)
504 && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
506 rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
507 rtx x = XEXP (mem_rtx, 0);
509 if (! ALLOW_INDEXED_ADDRESS
510 && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
513 if (GET_CODE (x) == PLUS)
518 && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
522 && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
523 && ! CONST_INT_P (y))
527 /* LRA will try to satisfy the constraints for the memory displacements
528 and thus we must not reject invalid displacements in the predicate,
529 or else LRA will bail out.
530 FIXME: maybe remove this check completely? */
531 if (!lra_in_progress && (mode == QImode || mode == HImode)
532 && GET_CODE (x) == PLUS
533 && REG_P (XEXP (x, 0))
534 && CONST_INT_P (XEXP (x, 1)))
535 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
537 /* Allow reg+reg addressing here without validating the register
538 numbers. Usually one of the regs must be R0 or a pseudo reg.
539 In some cases it can happen that arguments from hard regs are
540 propagated directly into address expressions. In this cases reload
541 will have to fix it up later. However, allow this only for native
542 1, 2 or 4 byte addresses. */
543 if (can_create_pseudo_p () && GET_CODE (x) == PLUS
544 && GET_MODE_SIZE (mode) <= 4
545 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
548 /* 'general_operand' does not allow volatile mems during RTL expansion to
549 avoid matching arithmetic that operates on mems, it seems.
550 On SH this leads to redundant sign extensions for QImode or HImode
551 loads. Thus we mimic the behavior but allow volatile mems. */
552 if (memory_address_addr_space_p (GET_MODE (mem_rtx), x,
553 MEM_ADDR_SPACE (mem_rtx)))
558 && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
559 && sh_rep_vec (op, mode))
561 if (TARGET_SHMEDIA && 1
562 && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
563 && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
564 /* FIXME */ abort (); /* return 1; */
566 return general_operand (op, mode);
569 ;; Returns 1 if OP is a MEM that does not use displacement addressing.
570 (define_predicate "movsrc_no_disp_mem_operand"
573 return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
576 ;; Returns 1 if OP can be a destination of a move. Same as
577 ;; general_operand, but no preinc allowed.
578 (define_predicate "general_movdst_operand"
579 (match_code "subreg,reg,mem")
581 if (t_reg_operand (op, mode))
584 if (fpscr_operand (op, mode))
589 rtx inside = XEXP (op, 0);
590 /* Disallow mems with GBR address here. They have to go through
591 separate special patterns. */
592 if ((REG_P (inside) && REGNO (inside) == GBR_REG)
593 || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
594 && REGNO (XEXP (inside, 0)) == GBR_REG))
598 /* Only pre dec allowed. */
599 if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
601 if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
602 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
603 && ! (reload_in_progress || reload_completed))
606 if (mode == GET_MODE (op)
607 && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
609 rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
610 rtx x = XEXP (mem_rtx, 0);
612 if (! ALLOW_INDEXED_ADDRESS
613 && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
616 if (GET_CODE (x) == PLUS)
621 && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
625 && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
626 && ! CONST_INT_P (y))
630 /* LRA will try to satisfy the constraints for the memory displacements
631 and thus we must not reject invalid displacements in the predicate,
632 or else LRA will bail out.
633 FIXME: maybe remove this check completely? */
634 if (!lra_in_progress && (mode == QImode || mode == HImode)
635 && GET_CODE (x) == PLUS
636 && REG_P (XEXP (x, 0))
637 && CONST_INT_P (XEXP (x, 1)))
638 return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
640 /* Allow reg+reg addressing here without validating the register
641 numbers. Usually one of the regs must be R0 or a pseudo reg.
642 In some cases it can happen that arguments from hard regs are
643 propagated directly into address expressions. In this cases reload
644 will have to fix it up later. However, allow this only for native
645 1, 2 or 4 byte addresses. */
646 if (can_create_pseudo_p () && GET_CODE (x) == PLUS
647 && GET_MODE_SIZE (mode) <= 4
648 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
651 /* 'general_operand' does not allow volatile mems during RTL expansion to
652 avoid matching arithmetic that operates on mems, it seems.
653 On SH this leads to redundant sign extensions for QImode or HImode
654 stores. Thus we mimic the behavior but allow volatile mems. */
655 if (memory_address_addr_space_p (GET_MODE (mem_rtx), x,
656 MEM_ADDR_SPACE (mem_rtx)))
660 return general_operand (op, mode);
663 ;; Returns 1 if OP is a POST_INC on stack pointer register.
664 (define_predicate "sh_no_delay_pop_operand"
668 inside = XEXP (op, 0);
670 if (GET_CODE (op) == MEM && GET_MODE (op) == SImode
671 && GET_CODE (inside) == POST_INC
672 && GET_CODE (XEXP (inside, 0)) == REG
673 && REGNO (XEXP (inside, 0)) == SP_REG)
679 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
680 (define_predicate "unaligned_load_operand"
685 if (!MEM_P (op) || GET_MODE (op) != mode)
688 inside = XEXP (op, 0);
690 if (GET_CODE (inside) == POST_INC)
691 inside = XEXP (inside, 0);
699 ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner
701 (define_predicate "mem_index_disp_operand"
704 rtx plus0_rtx, plus1_rtx, mult_rtx;
706 plus0_rtx = XEXP (op, 0);
707 if (GET_CODE (plus0_rtx) != PLUS)
710 plus1_rtx = XEXP (plus0_rtx, 0);
711 if (GET_CODE (plus1_rtx) != PLUS)
713 if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1))))
716 mult_rtx = XEXP (plus1_rtx, 0);
717 if (GET_CODE (mult_rtx) != MULT)
719 if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0)))
720 || ! CONST_INT_P (XEXP (mult_rtx, 1)))
723 return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0
724 && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
727 ;; Returns true if OP is some kind of greater comparision.
728 (define_predicate "greater_comparison_operator"
729 (match_code "gt,ge,gtu,geu"))
731 ;; Returns true if OP is an operand suitable for shmedia reload_inqi and
732 ;; reload_inhi insns.
733 (define_predicate "inqhi_operand"
734 (match_code "truncate")
736 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
739 /* Can't use true_regnum here because copy_cost wants to know about
740 SECONDARY_INPUT_RELOAD_CLASS. */
741 return REG_P (op) && FP_REGISTER_P (REGNO (op));
744 ;; Returns true if OP is a general purpose integer register.
745 ;; This predicate is currently unused.
746 ;;(define_special_predicate "int_gpr_dest"
747 ;; (match_code "subreg,reg")
749 ;; machine_mode op_mode = GET_MODE (op);
751 ;; if (GET_MODE_CLASS (op_mode) != MODE_INT
752 ;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
754 ;; if (! reload_completed)
756 ;; return true_regnum (op) <= LAST_GENERAL_REG;
759 ;; Returns true if OP is some kind of less comparison.
760 (define_predicate "less_comparison_operator"
761 (match_code "lt,le,ltu,leu"))
763 ;; Returns 1 if OP is a valid source operand for a logical operation.
764 (define_predicate "logical_operand"
765 (match_code "subreg,reg,const_int")
768 && mode != DImode && GET_CODE (op) == SUBREG
769 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
772 if (arith_reg_operand (op, mode))
777 if (satisfies_constraint_I10 (op))
782 else if (satisfies_constraint_K08 (op))
788 ;; Like logical_operand but allows additional constant values which can be
789 ;; done with zero extensions. Used for the second operand of and insns.
790 (define_predicate "logical_and_operand"
791 (match_code "subreg,reg,const_int")
793 if (logical_operand (op, mode))
797 && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op)))
803 ;; Returns true if OP is a logical operator.
804 (define_predicate "logical_operator"
805 (match_code "and,ior,xor"))
807 ;; Like arith_reg_operand, but for register source operands of narrow
808 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
809 (define_predicate "logical_reg_operand"
810 (match_code "subreg,reg")
813 && GET_CODE (op) == SUBREG
814 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
817 return arith_reg_operand (op, mode);
820 ;; Returns true if OP is a valid bit offset value for the shmedia mextr insns.
821 (define_predicate "mextr_bit_offset"
822 (match_code "const_int")
826 if (!CONST_INT_P (op))
829 return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
832 ;; Returns true if OP is a constant -1, 0 or an zero extended register that
833 ;; can be used as an operator in the *subsi3_media insn.
834 (define_predicate "minuend_operand"
835 (match_code "subreg,reg,truncate,const_int")
837 return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
840 ;; Returns true if OP is a noncommutative floating point operator.
841 ;; This predicate is currently unused.
842 ;;(define_predicate "noncommutative_float_operator"
843 ;; (and (match_code "minus,div")
844 ;; (match_test "GET_MODE (op) == mode")))
846 ;; UNORDERED is only supported on SHMEDIA.
848 (define_predicate "sh_float_comparison_operator"
849 (ior (match_operand 0 "ordered_comparison_operator")
850 (and (match_test "TARGET_SHMEDIA")
851 (match_code "unordered"))))
853 (define_predicate "shmedia_cbranch_comparison_operator"
854 (ior (match_operand 0 "equality_comparison_operator")
855 (match_operand 0 "greater_comparison_operator")))
857 ;; Returns true if OP is a constant vector.
858 (define_predicate "sh_const_vec"
859 (match_code "const_vector")
863 if (GET_CODE (op) != CONST_VECTOR
864 || (GET_MODE (op) != mode && mode != VOIDmode))
866 i = XVECLEN (op, 0) - 1;
868 if (!CONST_INT_P (XVECEXP (op, 0, i)))
873 ;; Determine if OP is a constant vector matching MODE with only one
874 ;; element that is not a sign extension. Two byte-sized elements
876 (define_predicate "sh_1el_vec"
877 (match_code "const_vector")
880 int i, last, least, sign_ix;
883 if (GET_CODE (op) != CONST_VECTOR
884 || (GET_MODE (op) != mode && mode != VOIDmode))
886 /* Determine numbers of last and of least significant elements. */
887 last = XVECLEN (op, 0) - 1;
888 least = TARGET_LITTLE_ENDIAN ? 0 : last;
889 if (!CONST_INT_P (XVECEXP (op, 0, least)))
892 if (GET_MODE_UNIT_SIZE (mode) == 1)
893 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
894 if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
896 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
897 sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
898 ? constm1_rtx : const0_rtx);
899 i = XVECLEN (op, 0) - 1;
901 if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
907 ;; Like register_operand, but take into account that SHMEDIA can use
908 ;; the constant zero like a general register.
909 (define_predicate "sh_register_operand"
910 (match_code "reg,subreg,const_int,const_double")
912 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
914 return register_operand (op, mode);
917 ;; Returns true if OP is a vector which is composed of one element that is
919 (define_predicate "sh_rep_vec"
920 (match_code "const_vector,parallel")
925 if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
926 || (GET_MODE (op) != mode && mode != VOIDmode))
928 i = XVECLEN (op, 0) - 2;
929 x = XVECEXP (op, 0, i + 1);
930 if (GET_MODE_UNIT_SIZE (mode) == 1)
932 y = XVECEXP (op, 0, i);
933 for (i -= 2; i >= 0; i -= 2)
934 if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
935 || ! rtx_equal_p (XVECEXP (op, 0, i), y))
940 if (XVECEXP (op, 0, i) != x)
945 ;; Returns true if OP is a valid shift count operand for shift operations.
946 (define_predicate "shift_count_operand"
947 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,
948 zero_extend,sign_extend")
950 /* Allow T_REG as shift count for dynamic shifts, although it is not
951 really possible. It will then be copied to a general purpose reg. */
952 if (! TARGET_SHMEDIA)
953 return const_int_operand (op, mode) || arith_reg_operand (op, mode)
954 || (TARGET_DYNSHIFT && t_reg_operand (op, mode));
956 return (CONSTANT_P (op)
958 ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
959 : nonmemory_operand (op, mode))
960 : shift_count_reg_operand (op, mode));
963 ;; Returns true if OP is a valid shift count operand in a register which can
964 ;; be used by shmedia shift insns.
965 (define_predicate "shift_count_reg_operand"
966 (match_code "subreg,reg,zero_extend,sign_extend")
968 if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
969 || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
970 && (mode == VOIDmode || mode == GET_MODE (op))
971 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
972 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
977 while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
978 || GET_CODE (op) == TRUNCATE)
979 && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
980 && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
983 return arith_reg_operand (op, mode);
986 ;; Predicates for matching operands that are constant shift
987 ;; amounts 1, 2, 8, 16.
988 (define_predicate "p27_shift_count_operand"
989 (and (match_code "const_int")
990 (match_test "satisfies_constraint_P27 (op)")))
992 (define_predicate "not_p27_shift_count_operand"
993 (and (match_code "const_int")
994 (match_test "! satisfies_constraint_P27 (op)")))
996 ;; For right shifts the constant 1 is a special case because the shlr insn
997 ;; clobbers the T_REG and is handled by the T_REG clobbering version of the
998 ;; insn, which is also used for non-P27 shift sequences.
999 (define_predicate "p27_rshift_count_operand"
1000 (and (match_code "const_int")
1001 (match_test "satisfies_constraint_P27 (op)")
1002 (match_test "! satisfies_constraint_M (op)")))
1004 (define_predicate "not_p27_rshift_count_operand"
1005 (and (match_code "const_int")
1006 (ior (match_test "! satisfies_constraint_P27 (op)")
1007 (match_test "satisfies_constraint_M (op)"))))
1009 ;; Returns true if OP is some kind of a shift operator.
1010 (define_predicate "shift_operator"
1011 (match_code "ashift,ashiftrt,lshiftrt"))
1013 ;; Returns true if OP is a symbol reference.
1014 (define_predicate "symbol_ref_operand"
1015 (match_code "symbol_ref"))
1017 ;; Same as target_reg_operand, except that label_refs and symbol_refs
1018 ;; are accepted before reload.
1019 (define_special_predicate "target_operand"
1020 (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
1022 if (mode != VOIDmode && mode != Pmode)
1025 if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
1026 && satisfies_constraint_Csy (op))
1027 return ! reload_completed;
1029 return target_reg_operand (op, mode);
1032 ;; A predicate that accepts pseudos and branch target registers.
1033 (define_special_predicate "target_reg_operand"
1034 (match_code "subreg,reg")
1036 if (mode == VOIDmode
1037 ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
1038 : mode != GET_MODE (op))
1041 if (GET_CODE (op) == SUBREG)
1047 /* We must protect ourselves from matching pseudos that are virtual
1048 register, because they will eventually be replaced with hardware
1049 registers that aren't branch-target registers. */
1050 if (REGNO (op) > LAST_VIRTUAL_REGISTER
1051 || TARGET_REGISTER_P (REGNO (op)))
1057 ;; Returns true if OP is a valid operand for the shmedia mperm.w insn.
1058 (define_special_predicate "trunc_hi_operand"
1059 (match_code "subreg,reg,truncate")
1061 machine_mode op_mode = GET_MODE (op);
1063 if (op_mode != SImode && op_mode != DImode
1064 && op_mode != V4HImode && op_mode != V2SImode)
1066 return extend_reg_operand (op, mode);
1069 ;; Returns true if OP is an address suitable for an unaligned access
1071 (define_special_predicate "ua_address_operand"
1072 (match_code "subreg,reg,plus")
1074 if (GET_CODE (op) == PLUS
1075 && (! satisfies_constraint_I06 (XEXP (op, 1))))
1077 return address_operand (op, QImode);
1080 ;; Returns true if OP is a valid offset for an unaligned memory address.
1081 (define_predicate "ua_offset"
1082 (match_code "const_int")
1084 return satisfies_constraint_I06 (op);
1087 ;; Returns true if OP is a floating point operator with one operand.
1088 (define_predicate "unary_float_operator"
1089 (and (match_code "abs,neg,sqrt")
1090 (match_test "GET_MODE (op) == mode")))
1092 ;; Return 1 if OP is a valid source operand for xor.
1093 (define_predicate "xor_operand"
1094 (match_code "subreg,reg,const_int")
1096 if (CONST_INT_P (op))
1097 return (TARGET_SHMEDIA
1098 ? (satisfies_constraint_I06 (op)
1099 || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
1100 : satisfies_constraint_K08 (op));
1102 && mode != DImode && GET_CODE (op) == SUBREG
1103 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
1105 return arith_reg_operand (op, mode);
1108 (define_predicate "bitwise_memory_operand"
1113 if (REG_P (XEXP (op, 0)))
1116 if (GET_CODE (XEXP (op, 0)) == PLUS
1117 && REG_P (XEXP (XEXP (op, 0), 0))
1118 && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))
1124 ;; The atomic_* operand predicates are used for the atomic patterns.
1125 ;; Depending on the particular pattern some operands can be immediate
1126 ;; values. Using these predicates avoids the usage of 'force_reg' in the
1128 (define_predicate "atomic_arith_operand"
1129 (ior (match_code "subreg,reg")
1130 (and (match_test "satisfies_constraint_I08 (op)")
1131 (match_test "mode != QImode")
1132 (match_test "mode != HImode")
1133 (match_test "TARGET_SH4A"))))
1135 (define_predicate "atomic_logical_operand"
1136 (ior (match_code "subreg,reg")
1137 (and (match_test "satisfies_constraint_K08 (op)")
1138 (match_test "mode != QImode")
1139 (match_test "mode != HImode")
1140 (match_test "TARGET_SH4A"))))
1142 ;; A predicate describing the T bit register in any form.
1143 (define_predicate "t_reg_operand"
1144 (match_code "reg,subreg,sign_extend,zero_extend")
1146 switch (GET_CODE (op))
1149 return REGNO (op) == T_REG;
1152 return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG;
1156 if (REG_P (XEXP (op, 0)) && REGNO (XEXP (op, 0)) == T_REG)
1158 return GET_CODE (XEXP (op, 0)) == SUBREG
1159 && REG_P (SUBREG_REG (XEXP (op, 0)))
1160 && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
1167 ;; A predicate describing a negated T bit register.
1168 (define_predicate "negt_reg_operand"
1169 (match_code "subreg,xor")
1171 switch (GET_CODE (op))
1174 return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))
1175 && satisfies_constraint_M (XEXP (op, 1));
1178 return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)));
1185 ;; A predicate that returns true if OP is a valid construct around the T bit
1186 ;; that can be used as an operand for conditional branches.
1187 (define_predicate "cbranch_treg_value"
1188 (and (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
1189 (match_test "sh_eval_treg_value (op) >= 0")))
1191 ;; Returns true if OP is arith_reg_operand or t_reg_operand.
1192 (define_predicate "arith_reg_or_t_reg_operand"
1193 (ior (match_operand 0 "arith_reg_operand")
1194 (match_operand 0 "t_reg_operand")))
1196 ;; A predicate describing the negated value of the T bit register shifted
1198 (define_predicate "negt_reg_shl31_operand"
1199 (match_code "plus,minus,if_then_else")
1201 /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000
1202 (ashift:SI (match_operand:SI 1 "t_reg_operand")
1205 if (GET_CODE (op) == MINUS && satisfies_constraint_Jhb (XEXP (op, 0))
1206 && GET_CODE (XEXP (op, 1)) == ASHIFT
1207 && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1208 && CONST_INT_P (XEXP (XEXP (op, 1), 1))
1209 && INTVAL (XEXP (XEXP (op, 1), 1)) == 31)
1212 /* (plus:SI (ashift:SI (match_operand:SI 1 "t_reg_operand")
1214 (const_int -2147483648)) ;; 0xffffffff80000000
1216 if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1217 && GET_CODE (XEXP (op, 0)) == ASHIFT
1218 && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1219 && CONST_INT_P (XEXP (XEXP (op, 0), 1))
1220 && INTVAL (XEXP (XEXP (op, 0), 1)) == 31)
1223 /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand")
1224 (const_int -2147483648)) ;; 0xffffffff80000000
1225 (const_int -2147483648))
1227 if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1228 && GET_CODE (XEXP (op, 0)) == MULT
1229 && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1230 && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1)))
1233 /* (minus:SI (const_int -2147483648) ;; 0xffffffff80000000
1234 (mult:SI (match_operand:SI 1 "t_reg_operand")
1235 (const_int -2147483648)))
1237 if (GET_CODE (op) == MINUS
1238 && satisfies_constraint_Jhb (XEXP (op, 0))
1239 && GET_CODE (XEXP (op, 1)) == MULT
1240 && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1241 && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1)))
1244 /* (if_then_else:SI (match_operand:SI 1 "t_reg_operand")
1246 (const_int -2147483648)) ;; 0xffffffff80000000
1248 if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode)
1249 && satisfies_constraint_Z (XEXP (op, 1))
1250 && satisfies_constraint_Jhb (XEXP (op, 2)))
1256 ;; A predicate that determines whether a given constant is a valid
1257 ;; displacement for a GBR load/store of the specified mode.
1258 (define_predicate "gbr_displacement"
1259 (match_code "const_int")
1261 const int mode_sz = GET_MODE_SIZE (mode);
1262 const int move_sz = mode_sz > GET_MODE_SIZE (SImode)
1263 ? GET_MODE_SIZE (SImode)
1265 int max_disp = 255 * move_sz;
1266 if (mode_sz > move_sz)
1267 max_disp -= mode_sz - move_sz;
1269 return INTVAL (op) >= 0 && INTVAL (op) <= max_disp;
1272 ;; A predicate that determines whether OP is a valid GBR addressing mode
1273 ;; memory reference.
1274 (define_predicate "gbr_address_mem"
1277 rtx addr = XEXP (op, 0);
1279 if (REG_P (addr) && REGNO (addr) == GBR_REG)
1281 if (GET_CODE (addr) == PLUS
1282 && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG
1283 && gbr_displacement (XEXP (addr, 1), mode))