1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 /* Forward definitions of types. */
53 typedef struct minipool_node Mnode
;
54 typedef struct minipool_fixup Mfix
;
56 /* In order to improve the layout of the prototypes below
57 some short type abbreviations are defined here. */
58 #define Hint HOST_WIDE_INT
59 #define Mmode enum machine_mode
60 #define Ulong unsigned long
61 #define Ccstar const char *
63 /* Forward function declarations. */
64 static void arm_add_gc_roots
PARAMS ((void));
65 static int arm_gen_constant
PARAMS ((enum rtx_code
, Mmode
, Hint
, rtx
, rtx
, int, int));
66 static Ulong bit_count
PARAMS ((signed int));
67 static int const_ok_for_op
PARAMS ((Hint
, enum rtx_code
));
68 static int eliminate_lr2ip
PARAMS ((rtx
*));
69 static rtx emit_multi_reg_push
PARAMS ((int));
70 static rtx emit_sfm
PARAMS ((int, int));
71 static Ccstar fp_const_from_val
PARAMS ((REAL_VALUE_TYPE
*));
72 static arm_cc get_arm_condition_code
PARAMS ((rtx
));
73 static void init_fpa_table
PARAMS ((void));
74 static Hint int_log2
PARAMS ((Hint
));
75 static rtx is_jump_table
PARAMS ((rtx
));
76 static Ccstar output_multi_immediate
PARAMS ((rtx
*, Ccstar
, Ccstar
, int, Hint
));
77 static void print_multi_reg
PARAMS ((FILE *, Ccstar
, int, int));
78 static Mmode select_dominance_cc_mode
PARAMS ((rtx
, rtx
, Hint
));
79 static Ccstar shift_op
PARAMS ((rtx
, Hint
*));
80 static void arm_init_machine_status
PARAMS ((struct function
*));
81 static void arm_mark_machine_status
PARAMS ((struct function
*));
82 static void arm_free_machine_status
PARAMS ((struct function
*));
83 static int number_of_first_bit_set
PARAMS ((int));
84 static void replace_symbols_in_block
PARAMS ((tree
, rtx
, rtx
));
85 static void thumb_exit
PARAMS ((FILE *, int, rtx
));
86 static void thumb_pushpop
PARAMS ((FILE *, int, int));
87 static Ccstar thumb_condition_code
PARAMS ((rtx
, int));
88 static rtx is_jump_table
PARAMS ((rtx
));
89 static Hint get_jump_table_size
PARAMS ((rtx
));
90 static Mnode
* move_minipool_fix_forward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
91 static Mnode
* add_minipool_forward_ref
PARAMS ((Mfix
*));
92 static Mnode
* move_minipool_fix_backward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
93 static Mnode
* add_minipool_backward_ref
PARAMS ((Mfix
*));
94 static void assign_minipool_offsets
PARAMS ((Mfix
*));
95 static void arm_print_value
PARAMS ((FILE *, rtx
));
96 static void dump_minipool
PARAMS ((rtx
));
97 static int arm_barrier_cost
PARAMS ((rtx
));
98 static Mfix
* create_fix_barrier
PARAMS ((Mfix
*, Hint
));
99 static void push_minipool_barrier
PARAMS ((rtx
, Hint
));
100 static void push_minipool_fix
PARAMS ((rtx
, Hint
, rtx
*, Mmode
, rtx
));
101 static void note_invalid_constants
PARAMS ((rtx
, Hint
));
102 static int current_file_function_operand
PARAMS ((rtx
));
103 static Ulong arm_compute_save_reg_mask
PARAMS ((void));
104 static Ulong arm_isr_value
PARAMS ((tree
));
105 static Ulong arm_compute_func_type
PARAMS ((void));
106 static tree arm_handle_fndecl_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
107 static tree arm_handle_isr_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
108 const struct attribute_spec arm_attribute_table
[];
109 static void arm_output_function_epilogue
PARAMS ((FILE *,
111 static void arm_output_function_prologue
PARAMS ((FILE *,
113 static void thumb_output_function_prologue
PARAMS ((FILE *,
115 static int arm_comp_type_attributes
PARAMS ((tree
, tree
));
116 static void arm_set_default_type_attributes
PARAMS ((tree
));
117 static void arm_elf_asm_named_section
PARAMS ((const char *,
119 static int arm_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
126 /* Initialize the GCC target structure. */
127 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
128 #undef TARGET_MERGE_DECL_ATTRIBUTES
129 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
132 #undef TARGET_ATTRIBUTE_TABLE
133 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
135 #undef TARGET_ASM_FUNCTION_PROLOGUE
136 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
138 #undef TARGET_ASM_FUNCTION_EPILOGUE
139 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
141 #undef TARGET_COMP_TYPE_ATTRIBUTES
142 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
144 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
145 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
147 #undef TARGET_INIT_BUILTINS
148 #define TARGET_INIT_BUILTINS arm_init_builtins
150 #undef TARGET_EXPAND_BUILTIN
151 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
153 #undef TARGET_SCHED_ADJUST_COST
154 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
156 struct gcc_target targetm
= TARGET_INITIALIZER
;
158 /* Obstack for minipool constant handling. */
159 static struct obstack minipool_obstack
;
160 static char *minipool_startobj
;
162 #define obstack_chunk_alloc xmalloc
163 #define obstack_chunk_free free
165 /* The maximum number of insns skipped which will be conditionalised if
167 static int max_insns_skipped
= 5;
169 extern FILE * asm_out_file
;
171 /* True if we are currently building a constant table. */
172 int making_const_table
;
174 /* Define the information needed to generate branch insns. This is
175 stored from the compare operation. */
176 rtx arm_compare_op0
, arm_compare_op1
;
178 /* What type of floating point are we tuning for? */
179 enum floating_point_type arm_fpu
;
181 /* What type of floating point instructions are available? */
182 enum floating_point_type arm_fpu_arch
;
184 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
185 enum prog_mode_type arm_prgmode
;
187 /* Set by the -mfp=... option. */
188 const char * target_fp_name
= NULL
;
190 /* Used to parse -mstructure_size_boundary command line option. */
191 const char * structure_size_string
= NULL
;
192 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
194 /* Bit values used to identify processor capabilities. */
195 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
196 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
197 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
198 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
199 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
200 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
201 #define FL_THUMB (1 << 6) /* Thumb aware */
202 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
203 #define FL_STRONG (1 << 8) /* StrongARM */
204 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
205 #define FL_XSCALE (1 << 10) /* XScale */
207 /* The bits in this mask specify which instructions we are
208 allowed to generate. */
209 static int insn_flags
= 0;
211 /* The bits in this mask specify which instruction scheduling options should
212 be used. Note - there is an overlap with the FL_FAST_MULT. For some
213 hardware we want to be able to generate the multiply instructions, but to
214 tune as if they were not present in the architecture. */
215 static int tune_flags
= 0;
217 /* The following are used in the arm.md file as equivalents to bits
218 in the above two flag variables. */
220 /* Nonzero if this is an "M" variant of the processor. */
221 int arm_fast_multiply
= 0;
223 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
226 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
229 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
232 /* Nonzero if this chip can benefit from load scheduling. */
233 int arm_ld_sched
= 0;
235 /* Nonzero if this chip is a StrongARM. */
236 int arm_is_strong
= 0;
238 /* Nonzero if this chip is an XScale. */
239 int arm_is_xscale
= 0;
241 /* Nonzero if this chip is a an ARM6 or an ARM7. */
242 int arm_is_6_or_7
= 0;
244 /* Nonzero if generating Thumb instructions. */
247 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
248 must report the mode of the memory reference from PRINT_OPERAND to
249 PRINT_OPERAND_ADDRESS. */
250 enum machine_mode output_memory_reference_mode
;
252 /* Nonzero if the prologue must setup `fp'. */
253 int current_function_anonymous_args
;
255 /* The register number to be used for the PIC offset register. */
256 const char * arm_pic_register_string
= NULL
;
257 int arm_pic_register
= 9;
259 /* Set to 1 when a return insn is output, this means that the epilogue
261 int return_used_this_function
;
263 /* Set to 1 after arm_reorg has started. Reset to start at the start of
264 the next function. */
265 static int after_arm_reorg
= 0;
267 /* The maximum number of insns to be used when loading a constant. */
268 static int arm_constant_limit
= 3;
270 /* For an explanation of these variables, see final_prescan_insn below. */
272 enum arm_cond_code arm_current_cc
;
274 int arm_target_label
;
276 /* The condition codes of the ARM, and the inverse function. */
277 static const char *const arm_condition_codes
[] =
279 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
280 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
283 #define streq(string1, string2) (strcmp (string1, string2) == 0)
285 /* Initialization code. */
289 const char *const name
;
290 const unsigned int flags
;
293 /* Not all of these give usefully different compilation alternatives,
294 but there is no simple way of generalizing them. */
295 static const struct processors all_cores
[] =
299 {"arm2", FL_CO_PROC
| FL_MODE26
},
300 {"arm250", FL_CO_PROC
| FL_MODE26
},
301 {"arm3", FL_CO_PROC
| FL_MODE26
},
302 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
303 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
304 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
305 {"arm610", FL_MODE26
| FL_MODE32
},
306 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
307 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
308 /* arm7m doesn't exist on its own, but only with D, (and I), but
309 those don't alter the code, so arm7m is sometimes used. */
310 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
311 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
312 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
313 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
314 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
315 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
316 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
317 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
318 {"arm710", FL_MODE26
| FL_MODE32
},
319 {"arm710t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
320 {"arm720", FL_MODE26
| FL_MODE32
},
321 {"arm720t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
322 {"arm740t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
323 {"arm710c", FL_MODE26
| FL_MODE32
},
324 {"arm7100", FL_MODE26
| FL_MODE32
},
325 {"arm7500", FL_MODE26
| FL_MODE32
},
326 /* Doesn't have an external co-proc, but does have embedded fpu. */
327 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
328 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
329 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
330 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
331 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
332 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
333 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
334 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
335 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
336 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
337 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
338 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
339 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
340 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
341 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
342 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
343 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
348 static const struct processors all_architectures
[] =
350 /* ARM Architectures */
352 { "armv2", FL_CO_PROC
| FL_MODE26
},
353 { "armv2a", FL_CO_PROC
| FL_MODE26
},
354 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
355 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
356 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
357 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
358 implementations that support it, so we will leave it out for now. */
359 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
360 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
361 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
362 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
366 /* This is a magic stucture. The 'string' field is magically filled in
367 with a pointer to the value specified by the user on the command line
368 assuming that the user has specified such a value. */
370 struct arm_cpu_select arm_select
[] =
372 /* string name processors */
373 { NULL
, "-mcpu=", all_cores
},
374 { NULL
, "-march=", all_architectures
},
375 { NULL
, "-mtune=", all_cores
}
378 /* Return the number of bits set in value' */
383 unsigned long count
= 0;
387 value
&= ~(value
& -value
);
394 /* Fix up any incompatible options that the user has specified.
395 This has now turned into a maze. */
397 arm_override_options ()
401 /* Set up the flags based on the cpu/architecture selected by the user. */
402 for (i
= ARRAY_SIZE (arm_select
); i
--;)
404 struct arm_cpu_select
* ptr
= arm_select
+ i
;
406 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
408 const struct processors
* sel
;
410 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
411 if (streq (ptr
->string
, sel
->name
))
414 tune_flags
= sel
->flags
;
417 /* If we have been given an architecture and a processor
418 make sure that they are compatible. We only generate
419 a warning though, and we prefer the CPU over the
421 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
422 warning ("switch -mcpu=%s conflicts with -march= switch",
425 insn_flags
= sel
->flags
;
431 if (sel
->name
== NULL
)
432 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
436 /* If the user did not specify a processor, choose one for them. */
439 const struct processors
* sel
;
441 static const struct cpu_default
444 const char *const name
;
448 { TARGET_CPU_arm2
, "arm2" },
449 { TARGET_CPU_arm6
, "arm6" },
450 { TARGET_CPU_arm610
, "arm610" },
451 { TARGET_CPU_arm710
, "arm710" },
452 { TARGET_CPU_arm7m
, "arm7m" },
453 { TARGET_CPU_arm7500fe
, "arm7500fe" },
454 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
455 { TARGET_CPU_arm8
, "arm8" },
456 { TARGET_CPU_arm810
, "arm810" },
457 { TARGET_CPU_arm9
, "arm9" },
458 { TARGET_CPU_strongarm
, "strongarm" },
459 { TARGET_CPU_xscale
, "xscale" },
460 { TARGET_CPU_generic
, "arm" },
463 const struct cpu_default
* def
;
465 /* Find the default. */
466 for (def
= cpu_defaults
; def
->name
; def
++)
467 if (def
->cpu
== TARGET_CPU_DEFAULT
)
470 /* Make sure we found the default CPU. */
471 if (def
->name
== NULL
)
474 /* Find the default CPU's flags. */
475 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
476 if (streq (def
->name
, sel
->name
))
479 if (sel
->name
== NULL
)
482 insn_flags
= sel
->flags
;
484 /* Now check to see if the user has specified some command line
485 switch that require certain abilities from the cpu. */
488 if (TARGET_INTERWORK
|| TARGET_THUMB
)
490 sought
|= (FL_THUMB
| FL_MODE32
);
492 /* Force apcs-32 to be used for interworking. */
493 target_flags
|= ARM_FLAG_APCS_32
;
495 /* There are no ARM processors that support both APCS-26 and
496 interworking. Therefore we force FL_MODE26 to be removed
497 from insn_flags here (if it was set), so that the search
498 below will always be able to find a compatible processor. */
499 insn_flags
&= ~FL_MODE26
;
501 else if (!TARGET_APCS_32
)
504 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
506 /* Try to locate a CPU type that supports all of the abilities
507 of the default CPU, plus the extra abilities requested by
509 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
510 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
513 if (sel
->name
== NULL
)
515 unsigned int current_bit_count
= 0;
516 const struct processors
* best_fit
= NULL
;
518 /* Ideally we would like to issue an error message here
519 saying that it was not possible to find a CPU compatible
520 with the default CPU, but which also supports the command
521 line options specified by the programmer, and so they
522 ought to use the -mcpu=<name> command line option to
523 override the default CPU type.
525 Unfortunately this does not work with multilibing. We
526 need to be able to support multilibs for -mapcs-26 and for
527 -mthumb-interwork and there is no CPU that can support both
528 options. Instead if we cannot find a cpu that has both the
529 characteristics of the default cpu and the given command line
530 options we scan the array again looking for a best match. */
531 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
532 if ((sel
->flags
& sought
) == sought
)
536 count
= bit_count (sel
->flags
& insn_flags
);
538 if (count
>= current_bit_count
)
541 current_bit_count
= count
;
545 if (best_fit
== NULL
)
551 insn_flags
= sel
->flags
;
555 /* If tuning has not been specified, tune for whichever processor or
556 architecture has been selected. */
558 tune_flags
= insn_flags
;
560 /* Make sure that the processor choice does not conflict with any of the
561 other command line choices. */
562 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
564 /* If APCS-32 was not the default then it must have been set by the
565 user, so issue a warning message. If the user has specified
566 "-mapcs-32 -mcpu=arm2" then we loose here. */
567 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
568 warning ("target CPU does not support APCS-32" );
569 target_flags
&= ~ARM_FLAG_APCS_32
;
571 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
573 warning ("target CPU does not support APCS-26" );
574 target_flags
|= ARM_FLAG_APCS_32
;
577 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
579 warning ("target CPU does not support interworking" );
580 target_flags
&= ~ARM_FLAG_INTERWORK
;
583 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
585 warning ("target CPU does not support THUMB instructions.");
586 target_flags
&= ~ARM_FLAG_THUMB
;
589 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
591 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
592 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
595 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
596 from here where no function is being compiled currently. */
597 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
599 warning ("enabling backtrace support is only meaningful when compiling for the Thumb.");
601 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
602 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
604 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
605 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
607 /* If interworking is enabled then APCS-32 must be selected as well. */
608 if (TARGET_INTERWORK
)
611 warning ("interworking forces APCS-32 to be used" );
612 target_flags
|= ARM_FLAG_APCS_32
;
615 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
617 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
618 target_flags
|= ARM_FLAG_APCS_FRAME
;
621 if (TARGET_POKE_FUNCTION_NAME
)
622 target_flags
|= ARM_FLAG_APCS_FRAME
;
624 if (TARGET_APCS_REENT
&& flag_pic
)
625 error ("-fpic and -mapcs-reent are incompatible");
627 if (TARGET_APCS_REENT
)
628 warning ("APCS reentrant code not supported. Ignored");
630 /* If this target is normally configured to use APCS frames, warn if they
631 are turned off and debugging is turned on. */
633 && write_symbols
!= NO_DEBUG
634 && !TARGET_APCS_FRAME
635 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
636 warning ("-g with -mno-apcs-frame may not give sensible debugging");
638 /* If stack checking is disabled, we can use r10 as the PIC register,
639 which keeps r9 available. */
640 if (flag_pic
&& !TARGET_APCS_STACK
)
641 arm_pic_register
= 10;
643 if (TARGET_APCS_FLOAT
)
644 warning ("Passing floating point arguments in fp regs not yet supported");
646 /* Initialise boolean versions of the flags, for use in the arm.md file. */
647 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
648 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
649 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
650 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
651 arm_is_xscale
= (insn_flags
& FL_XSCALE
) != 0;
653 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
654 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
655 thumb_code
= (TARGET_ARM
== 0);
656 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
657 && !(tune_flags
& FL_ARCH4
))) != 0;
659 /* Default value for floating point code... if no co-processor
660 bus, then schedule for emulated floating point. Otherwise,
661 assume the user has an FPA.
662 Note: this does not prevent use of floating point instructions,
663 -msoft-float does that. */
664 arm_fpu
= (tune_flags
& FL_CO_PROC
) ? FP_HARD
: FP_SOFT3
;
668 if (streq (target_fp_name
, "2"))
669 arm_fpu_arch
= FP_SOFT2
;
670 else if (streq (target_fp_name
, "3"))
671 arm_fpu_arch
= FP_SOFT3
;
673 error ("Invalid floating point emulation option: -mfpe-%s",
677 arm_fpu_arch
= FP_DEFAULT
;
679 if (TARGET_FPE
&& arm_fpu
!= FP_HARD
)
682 /* For arm2/3 there is no need to do any scheduling if there is only
683 a floating point emulator, or we are doing software floating-point. */
684 if ((TARGET_SOFT_FLOAT
|| arm_fpu
!= FP_HARD
)
685 && (tune_flags
& FL_MODE32
) == 0)
686 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
688 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
690 if (structure_size_string
!= NULL
)
692 int size
= strtol (structure_size_string
, NULL
, 0);
694 if (size
== 8 || size
== 32)
695 arm_structure_size_boundary
= size
;
697 warning ("Structure size boundary can only be set to 8 or 32");
700 if (arm_pic_register_string
!= NULL
)
705 warning ("-mpic-register= is useless without -fpic");
707 pic_register
= decode_reg_name (arm_pic_register_string
);
709 /* Prevent the user from choosing an obviously stupid PIC register. */
710 if (pic_register
< 0 || call_used_regs
[pic_register
]
711 || pic_register
== HARD_FRAME_POINTER_REGNUM
712 || pic_register
== STACK_POINTER_REGNUM
713 || pic_register
>= PC_REGNUM
)
714 error ("Unable to use '%s' for PIC register", arm_pic_register_string
);
716 arm_pic_register
= pic_register
;
719 if (TARGET_THUMB
&& flag_schedule_insns
)
721 /* Don't warn since it's on by default in -O2. */
722 flag_schedule_insns
= 0;
725 /* If optimizing for space, don't synthesize constants.
726 For processors with load scheduling, it never costs more than 2 cycles
727 to load a constant, and the load scheduler may well reduce that to 1. */
728 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
729 arm_constant_limit
= 1;
732 arm_constant_limit
= 2;
734 /* If optimizing for size, bump the number of instructions that we
735 are prepared to conditionally execute (even on a StrongARM).
736 Otherwise for the StrongARM, which has early execution of branches,
737 a sequence that is worth skipping is shorter. */
739 max_insns_skipped
= 6;
740 else if (arm_is_strong
)
741 max_insns_skipped
= 3;
743 /* Register global variables with the garbage collector. */
750 ggc_add_rtx_root (&arm_compare_op0
, 1);
751 ggc_add_rtx_root (&arm_compare_op1
, 1);
752 ggc_add_rtx_root (&arm_target_insn
, 1); /* Not sure this is really a root. */
754 gcc_obstack_init(&minipool_obstack
);
755 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
758 /* A table of known ARM exception types.
759 For use with the interrupt function attribute. */
763 const char *const arg
;
764 const unsigned long return_value
;
768 static const isr_attribute_arg isr_attribute_args
[] =
770 { "IRQ", ARM_FT_ISR
},
771 { "irq", ARM_FT_ISR
},
772 { "FIQ", ARM_FT_FIQ
},
773 { "fiq", ARM_FT_FIQ
},
774 { "ABORT", ARM_FT_ISR
},
775 { "abort", ARM_FT_ISR
},
776 { "ABORT", ARM_FT_ISR
},
777 { "abort", ARM_FT_ISR
},
778 { "UNDEF", ARM_FT_EXCEPTION
},
779 { "undef", ARM_FT_EXCEPTION
},
780 { "SWI", ARM_FT_EXCEPTION
},
781 { "swi", ARM_FT_EXCEPTION
},
782 { NULL
, ARM_FT_NORMAL
}
785 /* Returns the (interrupt) function type of the current
786 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
789 arm_isr_value (argument
)
792 const isr_attribute_arg
* ptr
;
795 /* No argument - default to IRQ. */
796 if (argument
== NULL_TREE
)
799 /* Get the value of the argument. */
800 if (TREE_VALUE (argument
) == NULL_TREE
801 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
802 return ARM_FT_UNKNOWN
;
804 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
806 /* Check it against the list of known arguments. */
807 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
808 if (strcmp (arg
, ptr
->arg
) == 0)
809 return ptr
->return_value
;
811 /* An unrecognised interrupt type. */
812 return ARM_FT_UNKNOWN
;
815 /* Computes the type of the current function. */
818 arm_compute_func_type ()
820 unsigned long type
= ARM_FT_UNKNOWN
;
824 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
827 /* Decide if the current function is volatile. Such functions
828 never return, and many memory cycles can be saved by not storing
829 register values that will never be needed again. This optimization
830 was added to speed up context switching in a kernel application. */
832 && current_function_nothrow
833 && TREE_THIS_VOLATILE (current_function_decl
))
834 type
|= ARM_FT_VOLATILE
;
836 if (current_function_needs_context
)
837 type
|= ARM_FT_NESTED
;
839 attr
= DECL_ATTRIBUTES (current_function_decl
);
841 a
= lookup_attribute ("naked", attr
);
843 type
|= ARM_FT_NAKED
;
845 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
846 type
|= ARM_FT_EXCEPTION_HANDLER
;
849 a
= lookup_attribute ("isr", attr
);
851 a
= lookup_attribute ("interrupt", attr
);
854 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
856 type
|= arm_isr_value (TREE_VALUE (a
));
862 /* Returns the type of the current function. */
865 arm_current_func_type ()
867 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
868 cfun
->machine
->func_type
= arm_compute_func_type ();
870 return cfun
->machine
->func_type
;
873 /* Return 1 if it is possible to return using a single instruction. */
876 use_return_insn (iscond
)
880 unsigned int func_type
;
882 /* Never use a return instruction before reload has run. */
883 if (!reload_completed
)
886 func_type
= arm_current_func_type ();
888 /* Naked functions, volatile functiond and interrupt
889 functions all need special consideration. */
890 if (func_type
& (ARM_FT_INTERRUPT
| ARM_FT_VOLATILE
| ARM_FT_NAKED
))
893 /* As do variadic functions. */
894 if (current_function_pretend_args_size
895 || current_function_anonymous_args
896 /* Of if the function calls __builtin_eh_return () */
897 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
898 /* Or if there is no frame pointer and there is a stack adjustment. */
899 || ((get_frame_size () + current_function_outgoing_args_size
!= 0)
900 && !frame_pointer_needed
))
903 /* Can't be done if interworking with Thumb, and any registers have been
904 stacked. Similarly, on StrongARM, conditional returns are expensive
905 if they aren't taken and registers have been stacked. */
906 if (iscond
&& arm_is_strong
&& frame_pointer_needed
)
909 if ((iscond
&& arm_is_strong
)
912 for (regno
= 0; regno
<= LAST_ARM_REGNUM
; regno
++)
913 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
916 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
920 /* Can't be done if any of the FPU regs are pushed,
921 since this also requires an insn. */
922 if (TARGET_HARD_FLOAT
)
923 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
924 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
930 /* Return TRUE if int I is a valid immediate ARM constant. */
936 unsigned HOST_WIDE_INT mask
= ~HOST_UINT (0xFF);
938 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
939 be all zero, or all one. */
940 if ((i
& ~HOST_UINT (0xffffffff)) != 0
941 && ((i
& ~HOST_UINT (0xffffffff))
943 & ~HOST_UINT (0xffffffff))))
946 /* Fast return for 0 and powers of 2 */
947 if ((i
& (i
- 1)) == 0)
952 if ((i
& mask
& HOST_UINT (0xffffffff)) == 0)
955 (mask
<< 2) | ((mask
& HOST_UINT (0xffffffff))
956 >> (32 - 2)) | ~(HOST_UINT (0xffffffff));
957 } while (mask
!= ~HOST_UINT (0xFF));
962 /* Return true if I is a valid constant for the operation CODE. */
964 const_ok_for_op (i
, code
)
968 if (const_ok_for_arm (i
))
974 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
976 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
982 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
989 /* Emit a sequence of insns to handle a large constant.
990 CODE is the code of the operation required, it can be any of SET, PLUS,
991 IOR, AND, XOR, MINUS;
992 MODE is the mode in which the operation is being performed;
993 VAL is the integer to operate on;
994 SOURCE is the other operand (a register, or a null-pointer for SET);
995 SUBTARGETS means it is safe to create scratch registers if that will
996 either produce a simpler sequence, or we will want to cse the values.
997 Return value is the number of insns emitted. */
1000 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
1002 enum machine_mode mode
;
1008 if (subtargets
|| code
== SET
1009 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1010 && REGNO (target
) != REGNO (source
)))
1012 /* After arm_reorg has been called, we can't fix up expensive
1013 constants by pushing them into memory so we must synthesise
1014 them in-line, regardless of the cost. This is only likely to
1015 be more costly on chips that have load delay slots and we are
1016 compiling without running the scheduler (so no splitting
1017 occurred before the final instruction emission).
1019 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1021 if (!after_arm_reorg
1022 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1023 > arm_constant_limit
+ (code
!= SET
)))
1027 /* Currently SET is the only monadic value for CODE, all
1028 the rest are diadic. */
1029 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1034 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1036 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1037 /* For MINUS, the value is subtracted from, since we never
1038 have subtraction of a constant. */
1040 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1041 gen_rtx_MINUS (mode
, temp
, source
)));
1043 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1044 gen_rtx (code
, mode
, source
, temp
)));
1050 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1054 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1056 HOST_WIDE_INT temp1
;
1064 if (remainder
& (3 << (i
- 2)))
1069 temp1
= remainder
& ((0x0ff << end
)
1070 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1071 remainder
&= ~temp1
;
1076 } while (remainder
);
1080 /* As above, but extra parameter GENERATE which, if clear, suppresses
1083 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
1085 enum machine_mode mode
;
1094 int can_negate_initial
= 0;
1097 int num_bits_set
= 0;
1098 int set_sign_bit_copies
= 0;
1099 int clear_sign_bit_copies
= 0;
1100 int clear_zero_bit_copies
= 0;
1101 int set_zero_bit_copies
= 0;
1103 unsigned HOST_WIDE_INT temp1
, temp2
;
1104 unsigned HOST_WIDE_INT remainder
= val
& HOST_UINT (0xffffffff);
1106 /* Find out which operations are safe for a given CODE. Also do a quick
1107 check for degenerate cases; these can occur when DImode operations
1119 can_negate_initial
= 1;
1123 if (remainder
== HOST_UINT (0xffffffff))
1126 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1127 GEN_INT (ARM_SIGN_EXTEND (val
))));
1132 if (reload_completed
&& rtx_equal_p (target
, source
))
1135 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1144 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1147 if (remainder
== HOST_UINT (0xffffffff))
1149 if (reload_completed
&& rtx_equal_p (target
, source
))
1152 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1161 if (reload_completed
&& rtx_equal_p (target
, source
))
1164 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1167 if (remainder
== HOST_UINT (0xffffffff))
1170 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1171 gen_rtx_NOT (mode
, source
)));
1175 /* We don't know how to handle this yet below. */
1179 /* We treat MINUS as (val - source), since (source - val) is always
1180 passed as (source + (-val)). */
1184 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1185 gen_rtx_NEG (mode
, source
)));
1188 if (const_ok_for_arm (val
))
1191 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1192 gen_rtx_MINUS (mode
, GEN_INT (val
),
1204 /* If we can do it in one insn get out quickly. */
1205 if (const_ok_for_arm (val
)
1206 || (can_negate_initial
&& const_ok_for_arm (-val
))
1207 || (can_invert
&& const_ok_for_arm (~val
)))
1210 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1211 (source
? gen_rtx (code
, mode
, source
,
1217 /* Calculate a few attributes that may be useful for specific
1219 for (i
= 31; i
>= 0; i
--)
1221 if ((remainder
& (1 << i
)) == 0)
1222 clear_sign_bit_copies
++;
1227 for (i
= 31; i
>= 0; i
--)
1229 if ((remainder
& (1 << i
)) != 0)
1230 set_sign_bit_copies
++;
1235 for (i
= 0; i
<= 31; i
++)
1237 if ((remainder
& (1 << i
)) == 0)
1238 clear_zero_bit_copies
++;
1243 for (i
= 0; i
<= 31; i
++)
1245 if ((remainder
& (1 << i
)) != 0)
1246 set_zero_bit_copies
++;
1254 /* See if we can do this by sign_extending a constant that is known
1255 to be negative. This is a good, way of doing it, since the shift
1256 may well merge into a subsequent insn. */
1257 if (set_sign_bit_copies
> 1)
1259 if (const_ok_for_arm
1260 (temp1
= ARM_SIGN_EXTEND (remainder
1261 << (set_sign_bit_copies
- 1))))
1265 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1266 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1268 emit_insn (gen_ashrsi3 (target
, new_src
,
1269 GEN_INT (set_sign_bit_copies
- 1)));
1273 /* For an inverted constant, we will need to set the low bits,
1274 these will be shifted out of harm's way. */
1275 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1276 if (const_ok_for_arm (~temp1
))
1280 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1281 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1283 emit_insn (gen_ashrsi3 (target
, new_src
,
1284 GEN_INT (set_sign_bit_copies
- 1)));
1290 /* See if we can generate this by setting the bottom (or the top)
1291 16 bits, and then shifting these into the other half of the
1292 word. We only look for the simplest cases, to do more would cost
1293 too much. Be careful, however, not to generate this when the
1294 alternative would take fewer insns. */
1295 if (val
& HOST_UINT (0xffff0000))
1297 temp1
= remainder
& HOST_UINT (0xffff0000);
1298 temp2
= remainder
& 0x0000ffff;
1300 /* Overlaps outside this range are best done using other methods. */
1301 for (i
= 9; i
< 24; i
++)
1303 if ((((temp2
| (temp2
<< i
))
1304 & HOST_UINT (0xffffffff)) == remainder
)
1305 && !const_ok_for_arm (temp2
))
1307 rtx new_src
= (subtargets
1308 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1310 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1311 source
, subtargets
, generate
);
1314 emit_insn (gen_rtx_SET
1317 gen_rtx_ASHIFT (mode
, source
,
1324 /* Don't duplicate cases already considered. */
1325 for (i
= 17; i
< 24; i
++)
1327 if (((temp1
| (temp1
>> i
)) == remainder
)
1328 && !const_ok_for_arm (temp1
))
1330 rtx new_src
= (subtargets
1331 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1333 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1334 source
, subtargets
, generate
);
1338 (gen_rtx_SET (VOIDmode
, target
,
1341 gen_rtx_LSHIFTRT (mode
, source
,
1352 /* If we have IOR or XOR, and the constant can be loaded in a
1353 single instruction, and we can find a temporary to put it in,
1354 then this can be done in two instructions instead of 3-4. */
1356 /* TARGET can't be NULL if SUBTARGETS is 0 */
1357 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1359 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1363 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1365 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1366 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1367 gen_rtx (code
, mode
, source
, sub
)));
1376 if (set_sign_bit_copies
> 8
1377 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1381 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1382 rtx shift
= GEN_INT (set_sign_bit_copies
);
1384 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1386 gen_rtx_ASHIFT (mode
,
1389 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1391 gen_rtx_LSHIFTRT (mode
, sub
,
1397 if (set_zero_bit_copies
> 8
1398 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1402 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1403 rtx shift
= GEN_INT (set_zero_bit_copies
);
1405 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1407 gen_rtx_LSHIFTRT (mode
,
1410 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1412 gen_rtx_ASHIFT (mode
, sub
,
1418 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1422 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1423 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1424 gen_rtx_NOT (mode
, source
)));
1427 sub
= gen_reg_rtx (mode
);
1428 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1429 gen_rtx_AND (mode
, source
,
1431 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1432 gen_rtx_NOT (mode
, sub
)));
1439 /* See if two shifts will do 2 or more insn's worth of work. */
1440 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1442 HOST_WIDE_INT shift_mask
= (((HOST_UINT (0xffffffff))
1443 << (32 - clear_sign_bit_copies
))
1444 & HOST_UINT (0xffffffff));
1446 if ((remainder
| shift_mask
) != HOST_UINT (0xffffffff))
1450 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1451 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1452 new_src
, source
, subtargets
, 1);
1457 rtx targ
= subtargets
? NULL_RTX
: target
;
1458 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1459 targ
, source
, subtargets
, 0);
1465 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1466 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1468 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1469 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1475 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1477 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1479 if ((remainder
| shift_mask
) != HOST_UINT (0xffffffff))
1483 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1485 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1486 new_src
, source
, subtargets
, 1);
1491 rtx targ
= subtargets
? NULL_RTX
: target
;
1493 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1494 targ
, source
, subtargets
, 0);
1500 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1501 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1503 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1504 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1516 for (i
= 0; i
< 32; i
++)
1517 if (remainder
& (1 << i
))
1520 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1521 remainder
= (~remainder
) & HOST_UINT (0xffffffff);
1522 else if (code
== PLUS
&& num_bits_set
> 16)
1523 remainder
= (-remainder
) & HOST_UINT (0xffffffff);
1530 /* Now try and find a way of doing the job in either two or three
1532 We start by looking for the largest block of zeros that are aligned on
1533 a 2-bit boundary, we then fill up the temps, wrapping around to the
1534 top of the word when we drop off the bottom.
1535 In the worst case this code should produce no more than four insns. */
1538 int best_consecutive_zeros
= 0;
1540 for (i
= 0; i
< 32; i
+= 2)
1542 int consecutive_zeros
= 0;
1544 if (!(remainder
& (3 << i
)))
1546 while ((i
< 32) && !(remainder
& (3 << i
)))
1548 consecutive_zeros
+= 2;
1551 if (consecutive_zeros
> best_consecutive_zeros
)
1553 best_consecutive_zeros
= consecutive_zeros
;
1554 best_start
= i
- consecutive_zeros
;
1560 /* So long as it won't require any more insns to do so, it's
1561 desirable to emit a small constant (in bits 0...9) in the last
1562 insn. This way there is more chance that it can be combined with
1563 a later addressing insn to form a pre-indexed load or store
1564 operation. Consider:
1566 *((volatile int *)0xe0000100) = 1;
1567 *((volatile int *)0xe0000110) = 2;
1569 We want this to wind up as:
1573 str rB, [rA, #0x100]
1575 str rB, [rA, #0x110]
1577 rather than having to synthesize both large constants from scratch.
1579 Therefore, we calculate how many insns would be required to emit
1580 the constant starting from `best_start', and also starting from
1581 zero (ie with bit 31 first to be output). If `best_start' doesn't
1582 yield a shorter sequence, we may as well use zero. */
1584 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1585 && (count_insns_for_constant (remainder
, 0) <=
1586 count_insns_for_constant (remainder
, best_start
)))
1589 /* Now start emitting the insns. */
1597 if (remainder
& (3 << (i
- 2)))
1602 temp1
= remainder
& ((0x0ff << end
)
1603 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1604 remainder
&= ~temp1
;
1611 emit_insn (gen_rtx_SET (VOIDmode
,
1612 new_src
= (subtargets
1613 ? gen_reg_rtx (mode
)
1616 ? ~temp1
: temp1
)));
1617 else if (code
== MINUS
)
1618 emit_insn (gen_rtx_SET (VOIDmode
,
1619 new_src
= (subtargets
1620 ? gen_reg_rtx (mode
)
1622 gen_rtx (code
, mode
, GEN_INT (temp1
),
1625 emit_insn (gen_rtx_SET (VOIDmode
,
1626 new_src
= (remainder
1628 ? gen_reg_rtx (mode
)
1631 gen_rtx (code
, mode
, source
,
1632 GEN_INT (can_invert
? ~temp1
1644 else if (code
== MINUS
)
1651 } while (remainder
);
1656 /* Canonicalize a comparison so that we are more likely to recognize it.
1657 This can be done for a few constant compares, where we can make the
1658 immediate value easier to load. */
1660 arm_canonicalize_comparison (code
, op1
)
1664 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1674 if (i
!= (((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1675 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1677 *op1
= GEN_INT (i
+ 1);
1678 return code
== GT
? GE
: LT
;
1684 if (i
!= ((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT
- 1))
1685 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1687 *op1
= GEN_INT (i
- 1);
1688 return code
== GE
? GT
: LE
;
1694 if (i
!= ~(HOST_UINT (0))
1695 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1697 *op1
= GEN_INT (i
+ 1);
1698 return code
== GTU
? GEU
: LTU
;
1705 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1707 *op1
= GEN_INT (i
- 1);
1708 return code
== GEU
? GTU
: LEU
;
1719 /* Decide whether a type should be returned in memory (true)
1720 or in a register (false). This is called by the macro
1721 RETURN_IN_MEMORY. */
1723 arm_return_in_memory (type
)
1726 if (!AGGREGATE_TYPE_P (type
))
1727 /* All simple types are returned in registers. */
1730 /* For the arm-wince targets we choose to be compitable with Microsoft's
1731 ARM and Thumb compilers, which always return aggregates in memory. */
1734 if (int_size_in_bytes (type
) > 4)
1735 /* All structures/unions bigger than one word are returned in memory. */
1738 if (TREE_CODE (type
) == RECORD_TYPE
)
1742 /* For a struct the APCS says that we only return in a register
1743 if the type is 'integer like' and every addressable element
1744 has an offset of zero. For practical purposes this means
1745 that the structure can have at most one non bit-field element
1746 and that this element must be the first one in the structure. */
1748 /* Find the first field, ignoring non FIELD_DECL things which will
1749 have been created by C++. */
1750 for (field
= TYPE_FIELDS (type
);
1751 field
&& TREE_CODE (field
) != FIELD_DECL
;
1752 field
= TREE_CHAIN (field
))
1756 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1758 /* Check that the first field is valid for returning in a register. */
1760 /* ... Floats are not allowed */
1761 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1764 /* ... Aggregates that are not themselves valid for returning in
1765 a register are not allowed. */
1766 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1769 /* Now check the remaining fields, if any. Only bitfields are allowed,
1770 since they are not addressable. */
1771 for (field
= TREE_CHAIN (field
);
1773 field
= TREE_CHAIN (field
))
1775 if (TREE_CODE (field
) != FIELD_DECL
)
1778 if (!DECL_BIT_FIELD_TYPE (field
))
1785 if (TREE_CODE (type
) == UNION_TYPE
)
1789 /* Unions can be returned in registers if every element is
1790 integral, or can be returned in an integer register. */
1791 for (field
= TYPE_FIELDS (type
);
1793 field
= TREE_CHAIN (field
))
1795 if (TREE_CODE (field
) != FIELD_DECL
)
1798 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1801 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1807 #endif /* not ARM_WINCE */
1809 /* Return all other types in memory. */
1813 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1814 for a call to a function whose data type is FNTYPE.
1815 For a library call, FNTYPE is NULL. */
1817 arm_init_cumulative_args (pcum
, fntype
, libname
, indirect
)
1818 CUMULATIVE_ARGS
* pcum
;
1820 rtx libname ATTRIBUTE_UNUSED
;
1821 int indirect ATTRIBUTE_UNUSED
;
1823 /* On the ARM, the offset starts at 0. */
1824 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
))) ? 1 : 0);
1826 pcum
->call_cookie
= CALL_NORMAL
;
1828 if (TARGET_LONG_CALLS
)
1829 pcum
->call_cookie
= CALL_LONG
;
1831 /* Check for long call/short call attributes. The attributes
1832 override any command line option. */
1835 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1836 pcum
->call_cookie
= CALL_SHORT
;
1837 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1838 pcum
->call_cookie
= CALL_LONG
;
1842 /* Determine where to put an argument to a function.
1843 Value is zero to push the argument on the stack,
1844 or a hard register in which to store the argument.
1846 MODE is the argument's machine mode.
1847 TYPE is the data type of the argument (as a tree).
1848 This is null for libcalls where that information may
1850 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1851 the preceding args and about the function being called.
1852 NAMED is nonzero if this argument is a named parameter
1853 (otherwise it is an extra parameter matching an ellipsis). */
1855 arm_function_arg (pcum
, mode
, type
, named
)
1856 CUMULATIVE_ARGS
* pcum
;
1857 enum machine_mode mode
;
1858 tree type ATTRIBUTE_UNUSED
;
1861 if (mode
== VOIDmode
)
1862 /* Compute operand 2 of the call insn. */
1863 return GEN_INT (pcum
->call_cookie
);
1865 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
1868 return gen_rtx_REG (mode
, pcum
->nregs
);
1871 /* Encode the current state of the #pragma [no_]long_calls. */
1874 OFF
, /* No #pramgma [no_]long_calls is in effect. */
1875 LONG
, /* #pragma long_calls is in effect. */
1876 SHORT
/* #pragma no_long_calls is in effect. */
1879 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
1882 arm_pr_long_calls (pfile
)
1883 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
1885 arm_pragma_long_calls
= LONG
;
1889 arm_pr_no_long_calls (pfile
)
1890 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
1892 arm_pragma_long_calls
= SHORT
;
1896 arm_pr_long_calls_off (pfile
)
1897 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
1899 arm_pragma_long_calls
= OFF
;
1903 /* Table of machine attributes. */
1904 const struct attribute_spec arm_attribute_table
[] =
1906 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1907 /* Function calls made to this symbol must be done indirectly, because
1908 it may lie outside of the 26 bit addressing range of a normal function
1910 { "long_call", 0, 0, false, true, true, NULL
},
1911 /* Whereas these functions are always known to reside within the 26 bit
1912 addressing range. */
1913 { "short_call", 0, 0, false, true, true, NULL
},
1914 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1915 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
1916 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
1917 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
1919 /* ARM/PE has three new attributes:
1921 dllexport - for exporting a function/variable that will live in a dll
1922 dllimport - for importing a function/variable from a dll
1924 Microsoft allows multiple declspecs in one __declspec, separating
1925 them with spaces. We do NOT support this. Instead, use __declspec
1928 { "dllimport", 0, 0, true, false, false, NULL
},
1929 { "dllexport", 0, 0, true, false, false, NULL
},
1930 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
1932 { NULL
, 0, 0, false, false, false, NULL
}
1935 /* Handle an attribute requiring a FUNCTION_DECL;
1936 arguments as in struct attribute_spec.handler. */
1938 arm_handle_fndecl_attribute (node
, name
, args
, flags
, no_add_attrs
)
1941 tree args ATTRIBUTE_UNUSED
;
1942 int flags ATTRIBUTE_UNUSED
;
1945 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1947 warning ("`%s' attribute only applies to functions",
1948 IDENTIFIER_POINTER (name
));
1949 *no_add_attrs
= true;
1955 /* Handle an "interrupt" or "isr" attribute;
1956 arguments as in struct attribute_spec.handler. */
1958 arm_handle_isr_attribute (node
, name
, args
, flags
, no_add_attrs
)
1967 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1969 warning ("`%s' attribute only applies to functions",
1970 IDENTIFIER_POINTER (name
));
1971 *no_add_attrs
= true;
1973 /* FIXME: the argument if any is checked for type attributes;
1974 should it be checked for decl ones? */
1978 if (TREE_CODE (*node
) == FUNCTION_TYPE
1979 || TREE_CODE (*node
) == METHOD_TYPE
)
1981 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
1983 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
1984 *no_add_attrs
= true;
1987 else if (TREE_CODE (*node
) == POINTER_TYPE
1988 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
1989 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
1990 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
1992 *node
= build_type_copy (*node
);
1993 TREE_TYPE (*node
) = build_type_attribute_variant (TREE_TYPE (*node
),
1996 TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
1997 *no_add_attrs
= true;
2001 /* Possibly pass this attribute on from the type to a decl. */
2002 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2003 | (int) ATTR_FLAG_FUNCTION_NEXT
2004 | (int) ATTR_FLAG_ARRAY_NEXT
))
2006 *no_add_attrs
= true;
2007 return tree_cons (name
, args
, NULL_TREE
);
2011 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2019 /* Return 0 if the attributes for two types are incompatible, 1 if they
2020 are compatible, and 2 if they are nearly compatible (which causes a
2021 warning to be generated). */
2023 arm_comp_type_attributes (type1
, type2
)
2029 /* Check for mismatch of non-default calling convention. */
2030 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2033 /* Check for mismatched call attributes. */
2034 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2035 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2036 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2037 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2039 /* Only bother to check if an attribute is defined. */
2040 if (l1
| l2
| s1
| s2
)
2042 /* If one type has an attribute, the other must have the same attribute. */
2043 if ((l1
!= l2
) || (s1
!= s2
))
2046 /* Disallow mixed attributes. */
2047 if ((l1
& s2
) || (l2
& s1
))
2051 /* Check for mismatched ISR attribute. */
2052 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2054 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2055 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2057 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2064 /* Encode long_call or short_call attribute by prefixing
2065 symbol name in DECL with a special character FLAG. */
2067 arm_encode_call_attribute (decl
, flag
)
2071 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2072 int len
= strlen (str
);
2075 if (TREE_CODE (decl
) != FUNCTION_DECL
)
2078 /* Do not allow weak functions to be treated as short call. */
2079 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2082 newstr
= alloca (len
+ 2);
2084 strcpy (newstr
+ 1, str
);
2086 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2087 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2090 /* Assigns default attributes to newly defined type. This is used to
2091 set short_call/long_call attributes for function types of
2092 functions defined inside corresponding #pragma scopes. */
2094 arm_set_default_type_attributes (type
)
2097 /* Add __attribute__ ((long_call)) to all functions, when
2098 inside #pragma long_calls or __attribute__ ((short_call)),
2099 when inside #pragma no_long_calls. */
2100 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2102 tree type_attr_list
, attr_name
;
2103 type_attr_list
= TYPE_ATTRIBUTES (type
);
2105 if (arm_pragma_long_calls
== LONG
)
2106 attr_name
= get_identifier ("long_call");
2107 else if (arm_pragma_long_calls
== SHORT
)
2108 attr_name
= get_identifier ("short_call");
2112 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2113 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2117 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2118 defined within the current compilation unit. If this caanot be
2119 determined, then 0 is returned. */
2121 current_file_function_operand (sym_ref
)
2124 /* This is a bit of a fib. A function will have a short call flag
2125 applied to its name if it has the short call attribute, or it has
2126 already been defined within the current compilation unit. */
2127 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2130 /* The current function is always defined within the current compilation
2131 unit. if it s a weak defintion however, then this may not be the real
2132 defintion of the function, and so we have to say no. */
2133 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2134 && !DECL_WEAK (current_function_decl
))
2137 /* We cannot make the determination - default to returning 0. */
2141 /* Return non-zero if a 32 bit "long_call" should be generated for
2142 this call. We generate a long_call if the function:
2144 a. has an __attribute__((long call))
2145 or b. is within the scope of a #pragma long_calls
2146 or c. the -mlong-calls command line switch has been specified
2148 However we do not generate a long call if the function:
2150 d. has an __attribute__ ((short_call))
2151 or e. is inside the scope of a #pragma no_long_calls
2152 or f. has an __attribute__ ((section))
2153 or g. is defined within the current compilation unit.
2155 This function will be called by C fragments contained in the machine
2156 description file. CALL_REF and CALL_COOKIE correspond to the matched
2157 rtl operands. CALL_SYMBOL is used to distinguish between
2158 two different callers of the function. It is set to 1 in the
2159 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2160 and "call_value" patterns. This is because of the difference in the
2161 SYM_REFs passed by these patterns. */
2163 arm_is_longcall_p (sym_ref
, call_cookie
, call_symbol
)
2170 if (GET_CODE (sym_ref
) != MEM
)
2173 sym_ref
= XEXP (sym_ref
, 0);
2176 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2179 if (call_cookie
& CALL_SHORT
)
2182 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2185 if (current_file_function_operand (sym_ref
))
2188 return (call_cookie
& CALL_LONG
)
2189 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2190 || TARGET_LONG_CALLS
;
2193 /* Return non-zero if it is ok to make a tail-call to DECL. */
2195 arm_function_ok_for_sibcall (decl
)
2198 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2200 /* Never tailcall something for which we have no decl, or if we
2201 are in Thumb mode. */
2202 if (decl
== NULL
|| TARGET_THUMB
)
2205 /* Get the calling method. */
2206 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2207 call_type
= CALL_SHORT
;
2208 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2209 call_type
= CALL_LONG
;
2211 /* Cannot tail-call to long calls, since these are out of range of
2212 a branch instruction. However, if not compiling PIC, we know
2213 we can reach the symbol if it is in this compilation unit. */
2214 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2217 /* If we are interworking and the function is not declared static
2218 then we can't tail-call it unless we know that it exists in this
2219 compilation unit (since it might be a Thumb routine). */
2220 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2223 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2224 if (IS_INTERRUPT (arm_current_func_type ()))
2227 /* Everything else is ok. */
2233 legitimate_pic_operand_p (x
)
2238 && (GET_CODE (x
) == SYMBOL_REF
2239 || (GET_CODE (x
) == CONST
2240 && GET_CODE (XEXP (x
, 0)) == PLUS
2241 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2248 legitimize_pic_address (orig
, mode
, reg
)
2250 enum machine_mode mode
;
2253 if (GET_CODE (orig
) == SYMBOL_REF
)
2255 rtx pic_ref
, address
;
2264 reg
= gen_reg_rtx (Pmode
);
2269 #ifdef AOF_ASSEMBLER
2270 /* The AOF assembler can generate relocations for these directly, and
2271 understands that the PIC register has to be added into the offset. */
2272 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2275 address
= gen_reg_rtx (Pmode
);
2280 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2282 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2284 pic_ref
= gen_rtx_MEM (Pmode
,
2285 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2287 RTX_UNCHANGING_P (pic_ref
) = 1;
2288 insn
= emit_move_insn (reg
, pic_ref
);
2290 current_function_uses_pic_offset_table
= 1;
2291 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2293 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2297 else if (GET_CODE (orig
) == CONST
)
2301 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2302 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2310 reg
= gen_reg_rtx (Pmode
);
2313 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2315 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2316 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2317 base
== reg
? 0 : reg
);
2322 if (GET_CODE (offset
) == CONST_INT
)
2324 /* The base register doesn't really matter, we only want to
2325 test the index for the appropriate mode. */
2326 ARM_GO_IF_LEGITIMATE_INDEX (mode
, 0, offset
, win
);
2328 if (!no_new_pseudos
)
2329 offset
= force_reg (Pmode
, offset
);
2334 if (GET_CODE (offset
) == CONST_INT
)
2335 return plus_constant (base
, INTVAL (offset
));
2338 if (GET_MODE_SIZE (mode
) > 4
2339 && (GET_MODE_CLASS (mode
) == MODE_INT
2340 || TARGET_SOFT_FLOAT
))
2342 emit_insn (gen_addsi3 (reg
, base
, offset
));
2346 return gen_rtx_PLUS (Pmode
, base
, offset
);
2348 else if (GET_CODE (orig
) == LABEL_REF
)
2350 current_function_uses_pic_offset_table
= 1;
2354 rtx pic_ref
, address
= gen_reg_rtx (Pmode
);
2357 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2359 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2361 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2363 emit_move_insn (address
, pic_ref
);
2371 /* Generate code to load the PIC register. PROLOGUE is true if
2372 called from arm_expand_prologue (in which case we want the
2373 generated insns at the start of the function); false if called
2374 by an exception receiver that needs the PIC register reloaded
2375 (in which case the insns are just dumped at the current location). */
2378 arm_finalize_pic (prologue
)
2381 #ifndef AOF_ASSEMBLER
2382 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2383 rtx global_offset_table
;
2385 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2392 l1
= gen_label_rtx ();
2394 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2395 /* On the ARM the PC register contains 'dot + 8' at the time of the
2396 addition, on the Thumb it is 'dot + 4'. */
2397 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2399 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2400 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2402 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2404 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2408 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2409 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2413 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2414 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2417 seq
= gen_sequence ();
2420 emit_insn_after (seq
, get_insns ());
2424 /* Need to emit this whether or not we obey regdecls,
2425 since setjmp/longjmp can cause life info to screw up. */
2426 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2427 #endif /* AOF_ASSEMBLER */
2430 #define REG_OR_SUBREG_REG(X) \
2431 (GET_CODE (X) == REG \
2432 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2434 #define REG_OR_SUBREG_RTX(X) \
2435 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2437 #ifndef COSTS_N_INSNS
2438 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2442 arm_rtx_costs (x
, code
, outer
)
2445 enum rtx_code outer
;
2447 enum machine_mode mode
= GET_MODE (x
);
2448 enum rtx_code subcode
;
2464 return COSTS_N_INSNS (1);
2467 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2470 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
2477 return COSTS_N_INSNS (2) + cycles
;
2479 return COSTS_N_INSNS (1) + 16;
2482 return (COSTS_N_INSNS (1)
2483 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
2484 + GET_CODE (SET_DEST (x
)) == MEM
));
2489 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2491 if (thumb_shiftable_const (INTVAL (x
)))
2492 return COSTS_N_INSNS (2);
2493 return COSTS_N_INSNS (3);
2495 else if (outer
== PLUS
2496 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
2498 else if (outer
== COMPARE
2499 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2501 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
2502 || outer
== LSHIFTRT
)
2504 return COSTS_N_INSNS (2);
2510 return COSTS_N_INSNS (3);
2529 /* XXX another guess. */
2530 /* Memory costs quite a lot for the first word, but subsequent words
2531 load at the equivalent of a single insn each. */
2532 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2533 + (CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
2537 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2542 /* XXX still guessing. */
2543 switch (GET_MODE (XEXP (x
, 0)))
2546 return (1 + (mode
== DImode
? 4 : 0)
2547 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2550 return (4 + (mode
== DImode
? 4 : 0)
2551 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2554 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2568 fprintf (stderr
, "unexpected code for thumb in rtx_costs: %s\n",
2578 /* Memory costs quite a lot for the first word, but subsequent words
2579 load at the equivalent of a single insn each. */
2580 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2581 + (CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
2588 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
2595 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
2597 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
2598 + ((GET_CODE (XEXP (x
, 0)) == REG
2599 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2600 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2602 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
2603 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2604 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2606 + ((GET_CODE (XEXP (x
, 1)) == REG
2607 || (GET_CODE (XEXP (x
, 1)) == SUBREG
2608 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
2609 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
2614 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
2615 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2616 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
2617 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
2620 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2621 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2622 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2623 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2625 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2626 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
2627 && const_double_rtx_ok_for_fpu (XEXP (x
, 0))))
2630 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
2631 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
2632 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
2633 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
2634 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
2635 || subcode
== ROTATE
|| subcode
== ROTATERT
2637 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2638 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
2639 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
2640 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
2641 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
2642 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
2643 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
2648 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2649 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2650 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2651 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2652 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2656 case AND
: case XOR
: case IOR
:
2659 /* Normally the frame registers will be spilt into reg+const during
2660 reload, so it is a bad idea to combine them with other instructions,
2661 since then they might not be moved outside of loops. As a compromise
2662 we allow integration with ops that have a constant as their second
2664 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2665 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
2666 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2667 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
2668 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
2672 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2673 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2674 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2675 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2678 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
2679 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
2680 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2681 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2682 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2685 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
2686 return (1 + extra_cost
2687 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
2688 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
2689 || subcode
== ROTATE
|| subcode
== ROTATERT
2691 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2692 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
2693 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
2694 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
2695 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
2696 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
2702 /* There is no point basing this on the tuning, since it is always the
2703 fast variant if it exists at all. */
2704 if (arm_fast_multiply
&& mode
== DImode
2705 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
2706 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2707 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
2710 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
2714 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2716 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
2717 & HOST_UINT (0xffffffff));
2718 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
2721 /* Tune as appropriate. */
2722 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
2724 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
2726 i
>>= booth_unit_size
;
2733 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
2734 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
2735 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
2738 if (arm_fast_multiply
&& mode
== SImode
2739 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2740 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2741 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
2742 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
2743 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
2744 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
2749 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2750 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
2754 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2756 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2759 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2767 return 4 + (mode
== DImode
? 4 : 0);
2770 if (GET_MODE (XEXP (x
, 0)) == QImode
)
2771 return (4 + (mode
== DImode
? 4 : 0)
2772 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2775 switch (GET_MODE (XEXP (x
, 0)))
2778 return (1 + (mode
== DImode
? 4 : 0)
2779 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2782 return (4 + (mode
== DImode
? 4 : 0)
2783 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2786 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2794 if (const_ok_for_arm (INTVAL (x
)))
2795 return outer
== SET
? 2 : -1;
2796 else if (outer
== AND
2797 && const_ok_for_arm (~INTVAL (x
)))
2799 else if ((outer
== COMPARE
2800 || outer
== PLUS
|| outer
== MINUS
)
2801 && const_ok_for_arm (-INTVAL (x
)))
2812 if (const_double_rtx_ok_for_fpu (x
))
2813 return outer
== SET
? 2 : -1;
2814 else if ((outer
== COMPARE
|| outer
== PLUS
)
2815 && neg_const_double_rtx_ok_for_fpu (x
))
2825 arm_adjust_cost (insn
, link
, dep
, cost
)
2833 /* Some true dependencies can have a higher cost depending
2834 on precisely how certain input operands are used. */
2836 && REG_NOTE_KIND (link
) == 0
2837 && recog_memoized (insn
) < 0
2838 && recog_memoized (dep
) < 0)
2840 int shift_opnum
= get_attr_shift (insn
);
2841 enum attr_type attr_type
= get_attr_type (dep
);
2843 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2844 operand for INSN. If we have a shifted input operand and the
2845 instruction we depend on is another ALU instruction, then we may
2846 have to account for an additional stall. */
2847 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
2849 rtx shifted_operand
;
2852 /* Get the shifted operand. */
2853 extract_insn (insn
);
2854 shifted_operand
= recog_data
.operand
[shift_opnum
];
2856 /* Iterate over all the operands in DEP. If we write an operand
2857 that overlaps with SHIFTED_OPERAND, then we have increase the
2858 cost of this dependency. */
2860 preprocess_constraints ();
2861 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2863 /* We can ignore strict inputs. */
2864 if (recog_data
.operand_type
[opno
] == OP_IN
)
2867 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
2874 /* XXX This is not strictly true for the FPA. */
2875 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
2876 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
2879 /* Call insns don't incur a stall, even if they follow a load. */
2880 if (REG_NOTE_KIND (link
) == 0
2881 && GET_CODE (insn
) == CALL_INSN
)
2884 if ((i_pat
= single_set (insn
)) != NULL
2885 && GET_CODE (SET_SRC (i_pat
)) == MEM
2886 && (d_pat
= single_set (dep
)) != NULL
2887 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
2889 /* This is a load after a store, there is no conflict if the load reads
2890 from a cached area. Assume that loads from the stack, and from the
2891 constant pool are cached, and that others will miss. This is a
2894 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat
), 0))
2895 || reg_mentioned_p (stack_pointer_rtx
, XEXP (SET_SRC (i_pat
), 0))
2896 || reg_mentioned_p (frame_pointer_rtx
, XEXP (SET_SRC (i_pat
), 0))
2897 || reg_mentioned_p (hard_frame_pointer_rtx
,
2898 XEXP (SET_SRC (i_pat
), 0)))
2905 /* This code has been fixed for cross compilation. */
2907 static int fpa_consts_inited
= 0;
2909 static const char *const strings_fpa
[8] =
2912 "4", "5", "0.5", "10"
2915 static REAL_VALUE_TYPE values_fpa
[8];
2923 for (i
= 0; i
< 8; i
++)
2925 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
2929 fpa_consts_inited
= 1;
2932 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2935 const_double_rtx_ok_for_fpu (x
)
2941 if (!fpa_consts_inited
)
2944 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2945 if (REAL_VALUE_MINUS_ZERO (r
))
2948 for (i
= 0; i
< 8; i
++)
2949 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
2955 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2958 neg_const_double_rtx_ok_for_fpu (x
)
2964 if (!fpa_consts_inited
)
2967 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2968 r
= REAL_VALUE_NEGATE (r
);
2969 if (REAL_VALUE_MINUS_ZERO (r
))
2972 for (i
= 0; i
< 8; i
++)
2973 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
2979 /* Predicates for `match_operand' and `match_operator'. */
2981 /* s_register_operand is the same as register_operand, but it doesn't accept
2984 This function exists because at the time it was put in it led to better
2985 code. SUBREG(MEM) always needs a reload in the places where
2986 s_register_operand is used, and this seemed to lead to excessive
2990 s_register_operand (op
, mode
)
2992 enum machine_mode mode
;
2994 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
2997 if (GET_CODE (op
) == SUBREG
)
2998 op
= SUBREG_REG (op
);
3000 /* We don't consider registers whose class is NO_REGS
3001 to be a register operand. */
3002 /* XXX might have to check for lo regs only for thumb ??? */
3003 return (GET_CODE (op
) == REG
3004 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3005 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3008 /* A hard register operand (even before reload. */
3010 arm_hard_register_operand (op
, mode
)
3012 enum machine_mode mode
;
3014 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3017 return (GET_CODE (op
) == REG
3018 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3021 /* Only accept reg, subreg(reg), const_int. */
3024 reg_or_int_operand (op
, mode
)
3026 enum machine_mode mode
;
3028 if (GET_CODE (op
) == CONST_INT
)
3031 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3034 if (GET_CODE (op
) == SUBREG
)
3035 op
= SUBREG_REG (op
);
3037 /* We don't consider registers whose class is NO_REGS
3038 to be a register operand. */
3039 return (GET_CODE (op
) == REG
3040 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3041 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3044 /* Return 1 if OP is an item in memory, given that we are in reload. */
3047 arm_reload_memory_operand (op
, mode
)
3049 enum machine_mode mode ATTRIBUTE_UNUSED
;
3051 int regno
= true_regnum (op
);
3053 return (!CONSTANT_P (op
)
3055 || (GET_CODE (op
) == REG
3056 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3059 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3060 memory access (architecture V4).
3061 MODE is QImode if called when computing contraints, or VOIDmode when
3062 emitting patterns. In this latter case we cannot use memory_operand()
3063 because it will fail on badly formed MEMs, which is precisly what we are
3066 bad_signed_byte_operand (op
, mode
)
3068 enum machine_mode mode ATTRIBUTE_UNUSED
;
3071 if ((mode
== QImode
&& !memory_operand (op
, mode
)) || GET_CODE (op
) != MEM
)
3074 if (GET_CODE (op
) != MEM
)
3079 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3080 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3081 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3082 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3083 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3086 /* Big constants are also bad. */
3087 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3088 && (INTVAL (XEXP (op
, 1)) > 0xff
3089 || -INTVAL (XEXP (op
, 1)) > 0xff))
3092 /* Everything else is good, or can will automatically be made so. */
3096 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3099 arm_rhs_operand (op
, mode
)
3101 enum machine_mode mode
;
3103 return (s_register_operand (op
, mode
)
3104 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3107 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
3111 arm_rhsm_operand (op
, mode
)
3113 enum machine_mode mode
;
3115 return (s_register_operand (op
, mode
)
3116 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3117 || memory_operand (op
, mode
));
3120 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3121 constant that is valid when negated. */
3124 arm_add_operand (op
, mode
)
3126 enum machine_mode mode
;
3129 return thumb_cmp_operand (op
, mode
);
3131 return (s_register_operand (op
, mode
)
3132 || (GET_CODE (op
) == CONST_INT
3133 && (const_ok_for_arm (INTVAL (op
))
3134 || const_ok_for_arm (-INTVAL (op
)))));
3138 arm_not_operand (op
, mode
)
3140 enum machine_mode mode
;
3142 return (s_register_operand (op
, mode
)
3143 || (GET_CODE (op
) == CONST_INT
3144 && (const_ok_for_arm (INTVAL (op
))
3145 || const_ok_for_arm (~INTVAL (op
)))));
3148 /* Return TRUE if the operand is a memory reference which contains an
3149 offsettable address. */
3151 offsettable_memory_operand (op
, mode
)
3153 enum machine_mode mode
;
3155 if (mode
== VOIDmode
)
3156 mode
= GET_MODE (op
);
3158 return (mode
== GET_MODE (op
)
3159 && GET_CODE (op
) == MEM
3160 && offsettable_address_p (reload_completed
| reload_in_progress
,
3161 mode
, XEXP (op
, 0)));
3164 /* Return TRUE if the operand is a memory reference which is, or can be
3165 made word aligned by adjusting the offset. */
3167 alignable_memory_operand (op
, mode
)
3169 enum machine_mode mode
;
3173 if (mode
== VOIDmode
)
3174 mode
= GET_MODE (op
);
3176 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3181 return ((GET_CODE (reg
= op
) == REG
3182 || (GET_CODE (op
) == SUBREG
3183 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3184 || (GET_CODE (op
) == PLUS
3185 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3186 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3187 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3188 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3189 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3192 /* Similar to s_register_operand, but does not allow hard integer
3195 f_register_operand (op
, mode
)
3197 enum machine_mode mode
;
3199 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3202 if (GET_CODE (op
) == SUBREG
)
3203 op
= SUBREG_REG (op
);
3205 /* We don't consider registers whose class is NO_REGS
3206 to be a register operand. */
3207 return (GET_CODE (op
) == REG
3208 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3209 || REGNO_REG_CLASS (REGNO (op
)) == FPU_REGS
));
3212 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3215 fpu_rhs_operand (op
, mode
)
3217 enum machine_mode mode
;
3219 if (s_register_operand (op
, mode
))
3222 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3225 if (GET_CODE (op
) == CONST_DOUBLE
)
3226 return const_double_rtx_ok_for_fpu (op
);
3232 fpu_add_operand (op
, mode
)
3234 enum machine_mode mode
;
3236 if (s_register_operand (op
, mode
))
3239 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3242 if (GET_CODE (op
) == CONST_DOUBLE
)
3243 return (const_double_rtx_ok_for_fpu (op
)
3244 || neg_const_double_rtx_ok_for_fpu (op
));
3249 /* Return nonzero if OP is a constant power of two. */
3252 power_of_two_operand (op
, mode
)
3254 enum machine_mode mode ATTRIBUTE_UNUSED
;
3256 if (GET_CODE (op
) == CONST_INT
)
3258 HOST_WIDE_INT value
= INTVAL (op
);
3259 return value
!= 0 && (value
& (value
- 1)) == 0;
3264 /* Return TRUE for a valid operand of a DImode operation.
3265 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3266 Note that this disallows MEM(REG+REG), but allows
3267 MEM(PRE/POST_INC/DEC(REG)). */
3270 di_operand (op
, mode
)
3272 enum machine_mode mode
;
3274 if (s_register_operand (op
, mode
))
3277 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3280 if (GET_CODE (op
) == SUBREG
)
3281 op
= SUBREG_REG (op
);
3283 switch (GET_CODE (op
))
3290 return memory_address_p (DImode
, XEXP (op
, 0));
3297 /* Like di_operand, but don't accept constants. */
3299 nonimmediate_di_operand (op
, mode
)
3301 enum machine_mode mode
;
3303 if (s_register_operand (op
, mode
))
3306 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3309 if (GET_CODE (op
) == SUBREG
)
3310 op
= SUBREG_REG (op
);
3312 if (GET_CODE (op
) == MEM
)
3313 return memory_address_p (DImode
, XEXP (op
, 0));
3318 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3319 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3320 Note that this disallows MEM(REG+REG), but allows
3321 MEM(PRE/POST_INC/DEC(REG)). */
3324 soft_df_operand (op
, mode
)
3326 enum machine_mode mode
;
3328 if (s_register_operand (op
, mode
))
3331 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3334 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
3337 if (GET_CODE (op
) == SUBREG
)
3338 op
= SUBREG_REG (op
);
3340 switch (GET_CODE (op
))
3346 return memory_address_p (DFmode
, XEXP (op
, 0));
3353 /* Like soft_df_operand, but don't accept constants. */
3355 nonimmediate_soft_df_operand (op
, mode
)
3357 enum machine_mode mode
;
3359 if (s_register_operand (op
, mode
))
3362 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3365 if (GET_CODE (op
) == SUBREG
)
3366 op
= SUBREG_REG (op
);
3368 if (GET_CODE (op
) == MEM
)
3369 return memory_address_p (DFmode
, XEXP (op
, 0));
3373 /* Return TRUE for valid index operands. */
3375 index_operand (op
, mode
)
3377 enum machine_mode mode
;
3379 return (s_register_operand (op
, mode
)
3380 || (immediate_operand (op
, mode
)
3381 && (GET_CODE (op
) != CONST_INT
3382 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
3385 /* Return TRUE for valid shifts by a constant. This also accepts any
3386 power of two on the (somewhat overly relaxed) assumption that the
3387 shift operator in this case was a mult. */
3390 const_shift_operand (op
, mode
)
3392 enum machine_mode mode
;
3394 return (power_of_two_operand (op
, mode
)
3395 || (immediate_operand (op
, mode
)
3396 && (GET_CODE (op
) != CONST_INT
3397 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
3400 /* Return TRUE for arithmetic operators which can be combined with a multiply
3404 shiftable_operator (x
, mode
)
3406 enum machine_mode mode
;
3408 if (GET_MODE (x
) != mode
)
3412 enum rtx_code code
= GET_CODE (x
);
3414 return (code
== PLUS
|| code
== MINUS
3415 || code
== IOR
|| code
== XOR
|| code
== AND
);
3419 /* Return TRUE for binary logical operators. */
3422 logical_binary_operator (x
, mode
)
3424 enum machine_mode mode
;
3426 if (GET_MODE (x
) != mode
)
3430 enum rtx_code code
= GET_CODE (x
);
3432 return (code
== IOR
|| code
== XOR
|| code
== AND
);
3436 /* Return TRUE for shift operators. */
3439 shift_operator (x
, mode
)
3441 enum machine_mode mode
;
3443 if (GET_MODE (x
) != mode
)
3447 enum rtx_code code
= GET_CODE (x
);
3450 return power_of_two_operand (XEXP (x
, 1), mode
);
3452 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
3453 || code
== ROTATERT
);
3457 /* Return TRUE if x is EQ or NE. */
3459 equality_operator (x
, mode
)
3461 enum machine_mode mode ATTRIBUTE_UNUSED
;
3463 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
3466 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3468 arm_comparison_operator (x
, mode
)
3470 enum machine_mode mode
;
3472 return (comparison_operator (x
, mode
)
3473 && GET_CODE (x
) != LTGT
3474 && GET_CODE (x
) != UNEQ
);
3477 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3479 minmax_operator (x
, mode
)
3481 enum machine_mode mode
;
3483 enum rtx_code code
= GET_CODE (x
);
3485 if (GET_MODE (x
) != mode
)
3488 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
3491 /* Return TRUE if this is the condition code register, if we aren't given
3492 a mode, accept any class CCmode register. */
3494 cc_register (x
, mode
)
3496 enum machine_mode mode
;
3498 if (mode
== VOIDmode
)
3500 mode
= GET_MODE (x
);
3502 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3506 if ( GET_MODE (x
) == mode
3507 && GET_CODE (x
) == REG
3508 && REGNO (x
) == CC_REGNUM
)
3514 /* Return TRUE if this is the condition code register, if we aren't given
3515 a mode, accept any class CCmode register which indicates a dominance
3518 dominant_cc_register (x
, mode
)
3520 enum machine_mode mode
;
3522 if (mode
== VOIDmode
)
3524 mode
= GET_MODE (x
);
3526 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3530 if ( mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
3531 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
3532 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
3533 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
3534 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
3537 return cc_register (x
, mode
);
3540 /* Return TRUE if X references a SYMBOL_REF. */
3542 symbol_mentioned_p (x
)
3545 register const char * fmt
;
3548 if (GET_CODE (x
) == SYMBOL_REF
)
3551 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3553 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3559 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3560 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
3563 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
3570 /* Return TRUE if X references a LABEL_REF. */
3572 label_mentioned_p (x
)
3575 register const char * fmt
;
3578 if (GET_CODE (x
) == LABEL_REF
)
3581 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3582 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3588 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3589 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
3592 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
3603 enum rtx_code code
= GET_CODE (x
);
3607 else if (code
== SMIN
)
3609 else if (code
== UMIN
)
3611 else if (code
== UMAX
)
3617 /* Return 1 if memory locations are adjacent. */
3619 adjacent_mem_locations (a
, b
)
3622 int val0
= 0, val1
= 0;
3625 if ((GET_CODE (XEXP (a
, 0)) == REG
3626 || (GET_CODE (XEXP (a
, 0)) == PLUS
3627 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
3628 && (GET_CODE (XEXP (b
, 0)) == REG
3629 || (GET_CODE (XEXP (b
, 0)) == PLUS
3630 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
3632 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
3634 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
3635 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
3638 reg0
= REGNO (XEXP (a
, 0));
3639 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
3641 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
3642 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
3645 reg1
= REGNO (XEXP (b
, 0));
3646 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
3651 /* Return 1 if OP is a load multiple operation. It is known to be
3652 parallel and the first section will be tested. */
3654 load_multiple_operation (op
, mode
)
3656 enum machine_mode mode ATTRIBUTE_UNUSED
;
3658 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3661 HOST_WIDE_INT i
= 1, base
= 0;
3665 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3668 /* Check to see if this might be a write-back. */
3669 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3674 /* Now check it more carefully. */
3675 if (GET_CODE (SET_DEST (elt
)) != REG
3676 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3677 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3678 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3679 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3683 /* Perform a quick check so we don't blow up below. */
3685 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3686 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
3687 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
3690 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
3691 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
3693 for (; i
< count
; i
++)
3695 elt
= XVECEXP (op
, 0, i
);
3697 if (GET_CODE (elt
) != SET
3698 || GET_CODE (SET_DEST (elt
)) != REG
3699 || GET_MODE (SET_DEST (elt
)) != SImode
3700 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
3701 || GET_CODE (SET_SRC (elt
)) != MEM
3702 || GET_MODE (SET_SRC (elt
)) != SImode
3703 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
3704 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
3705 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
3706 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
3713 /* Return 1 if OP is a store multiple operation. It is known to be
3714 parallel and the first section will be tested. */
3716 store_multiple_operation (op
, mode
)
3718 enum machine_mode mode ATTRIBUTE_UNUSED
;
3720 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3723 HOST_WIDE_INT i
= 1, base
= 0;
3727 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3730 /* Check to see if this might be a write-back. */
3731 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3736 /* Now check it more carefully. */
3737 if (GET_CODE (SET_DEST (elt
)) != REG
3738 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3739 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3740 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3741 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3745 /* Perform a quick check so we don't blow up below. */
3747 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3748 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
3749 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
3752 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
3753 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
3755 for (; i
< count
; i
++)
3757 elt
= XVECEXP (op
, 0, i
);
3759 if (GET_CODE (elt
) != SET
3760 || GET_CODE (SET_SRC (elt
)) != REG
3761 || GET_MODE (SET_SRC (elt
)) != SImode
3762 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
3763 || GET_CODE (SET_DEST (elt
)) != MEM
3764 || GET_MODE (SET_DEST (elt
)) != SImode
3765 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
3766 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
3767 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
3768 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
3776 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
3781 HOST_WIDE_INT
* load_offset
;
3783 int unsorted_regs
[4];
3784 HOST_WIDE_INT unsorted_offsets
[4];
3789 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3790 extended if required. */
3791 if (nops
< 2 || nops
> 4)
3794 /* Loop over the operands and check that the memory references are
3795 suitable (ie immediate offsets from the same base register). At
3796 the same time, extract the target register, and the memory
3798 for (i
= 0; i
< nops
; i
++)
3803 /* Convert a subreg of a mem into the mem itself. */
3804 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
3805 operands
[nops
+ i
] = alter_subreg (operands
[nops
+ i
]);
3807 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
3810 /* Don't reorder volatile memory references; it doesn't seem worth
3811 looking for the case where the order is ok anyway. */
3812 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
3815 offset
= const0_rtx
;
3817 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
3818 || (GET_CODE (reg
) == SUBREG
3819 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3820 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
3821 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
3823 || (GET_CODE (reg
) == SUBREG
3824 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3825 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
3830 base_reg
= REGNO (reg
);
3831 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
3832 ? REGNO (operands
[i
])
3833 : REGNO (SUBREG_REG (operands
[i
])));
3838 if (base_reg
!= (int) REGNO (reg
))
3839 /* Not addressed from the same base register. */
3842 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
3843 ? REGNO (operands
[i
])
3844 : REGNO (SUBREG_REG (operands
[i
])));
3845 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
3849 /* If it isn't an integer register, or if it overwrites the
3850 base register but isn't the last insn in the list, then
3851 we can't do this. */
3852 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
3853 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
3856 unsorted_offsets
[i
] = INTVAL (offset
);
3859 /* Not a suitable memory address. */
3863 /* All the useful information has now been extracted from the
3864 operands into unsorted_regs and unsorted_offsets; additionally,
3865 order[0] has been set to the lowest numbered register in the
3866 list. Sort the registers into order, and check that the memory
3867 offsets are ascending and adjacent. */
3869 for (i
= 1; i
< nops
; i
++)
3873 order
[i
] = order
[i
- 1];
3874 for (j
= 0; j
< nops
; j
++)
3875 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3876 && (order
[i
] == order
[i
- 1]
3877 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3880 /* Have we found a suitable register? if not, one must be used more
3882 if (order
[i
] == order
[i
- 1])
3885 /* Is the memory address adjacent and ascending? */
3886 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3894 for (i
= 0; i
< nops
; i
++)
3895 regs
[i
] = unsorted_regs
[order
[i
]];
3897 *load_offset
= unsorted_offsets
[order
[0]];
3900 if (unsorted_offsets
[order
[0]] == 0)
3901 return 1; /* ldmia */
3903 if (unsorted_offsets
[order
[0]] == 4)
3904 return 2; /* ldmib */
3906 if (unsorted_offsets
[order
[nops
- 1]] == 0)
3907 return 3; /* ldmda */
3909 if (unsorted_offsets
[order
[nops
- 1]] == -4)
3910 return 4; /* ldmdb */
3912 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3913 if the offset isn't small enough. The reason 2 ldrs are faster
3914 is because these ARMs are able to do more than one cache access
3915 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3916 whilst the ARM8 has a double bandwidth cache. This means that
3917 these cores can do both an instruction fetch and a data fetch in
3918 a single cycle, so the trick of calculating the address into a
3919 scratch register (one of the result regs) and then doing a load
3920 multiple actually becomes slower (and no smaller in code size).
3921 That is the transformation
3923 ldr rd1, [rbase + offset]
3924 ldr rd2, [rbase + offset + 4]
3928 add rd1, rbase, offset
3929 ldmia rd1, {rd1, rd2}
3931 produces worse code -- '3 cycles + any stalls on rd2' instead of
3932 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3933 access per cycle, the first sequence could never complete in less
3934 than 6 cycles, whereas the ldm sequence would only take 5 and
3935 would make better use of sequential accesses if not hitting the
3938 We cheat here and test 'arm_ld_sched' which we currently know to
3939 only be true for the ARM8, ARM9 and StrongARM. If this ever
3940 changes, then the test below needs to be reworked. */
3941 if (nops
== 2 && arm_ld_sched
)
3944 /* Can't do it without setting up the offset, only do this if it takes
3945 no more than one insn. */
3946 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
3947 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
3951 emit_ldm_seq (operands
, nops
)
3957 HOST_WIDE_INT offset
;
3961 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
3964 strcpy (buf
, "ldm%?ia\t");
3968 strcpy (buf
, "ldm%?ib\t");
3972 strcpy (buf
, "ldm%?da\t");
3976 strcpy (buf
, "ldm%?db\t");
3981 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
3982 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
3985 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
3986 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
3988 output_asm_insn (buf
, operands
);
3990 strcpy (buf
, "ldm%?ia\t");
3997 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
3998 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4000 for (i
= 1; i
< nops
; i
++)
4001 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4002 reg_names
[regs
[i
]]);
4004 strcat (buf
, "}\t%@ phole ldm");
4006 output_asm_insn (buf
, operands
);
4011 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
4016 HOST_WIDE_INT
* load_offset
;
4018 int unsorted_regs
[4];
4019 HOST_WIDE_INT unsorted_offsets
[4];
4024 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4025 extended if required. */
4026 if (nops
< 2 || nops
> 4)
4029 /* Loop over the operands and check that the memory references are
4030 suitable (ie immediate offsets from the same base register). At
4031 the same time, extract the target register, and the memory
4033 for (i
= 0; i
< nops
; i
++)
4038 /* Convert a subreg of a mem into the mem itself. */
4039 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4040 operands
[nops
+ i
] = alter_subreg (operands
[nops
+ i
]);
4042 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4045 /* Don't reorder volatile memory references; it doesn't seem worth
4046 looking for the case where the order is ok anyway. */
4047 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4050 offset
= const0_rtx
;
4052 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4053 || (GET_CODE (reg
) == SUBREG
4054 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4055 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4056 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4058 || (GET_CODE (reg
) == SUBREG
4059 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4060 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4065 base_reg
= REGNO (reg
);
4066 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4067 ? REGNO (operands
[i
])
4068 : REGNO (SUBREG_REG (operands
[i
])));
4073 if (base_reg
!= (int) REGNO (reg
))
4074 /* Not addressed from the same base register. */
4077 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4078 ? REGNO (operands
[i
])
4079 : REGNO (SUBREG_REG (operands
[i
])));
4080 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4084 /* If it isn't an integer register, then we can't do this. */
4085 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
4088 unsorted_offsets
[i
] = INTVAL (offset
);
4091 /* Not a suitable memory address. */
4095 /* All the useful information has now been extracted from the
4096 operands into unsorted_regs and unsorted_offsets; additionally,
4097 order[0] has been set to the lowest numbered register in the
4098 list. Sort the registers into order, and check that the memory
4099 offsets are ascending and adjacent. */
4101 for (i
= 1; i
< nops
; i
++)
4105 order
[i
] = order
[i
- 1];
4106 for (j
= 0; j
< nops
; j
++)
4107 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4108 && (order
[i
] == order
[i
- 1]
4109 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4112 /* Have we found a suitable register? if not, one must be used more
4114 if (order
[i
] == order
[i
- 1])
4117 /* Is the memory address adjacent and ascending? */
4118 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4126 for (i
= 0; i
< nops
; i
++)
4127 regs
[i
] = unsorted_regs
[order
[i
]];
4129 *load_offset
= unsorted_offsets
[order
[0]];
4132 if (unsorted_offsets
[order
[0]] == 0)
4133 return 1; /* stmia */
4135 if (unsorted_offsets
[order
[0]] == 4)
4136 return 2; /* stmib */
4138 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4139 return 3; /* stmda */
4141 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4142 return 4; /* stmdb */
4148 emit_stm_seq (operands
, nops
)
4154 HOST_WIDE_INT offset
;
4158 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4161 strcpy (buf
, "stm%?ia\t");
4165 strcpy (buf
, "stm%?ib\t");
4169 strcpy (buf
, "stm%?da\t");
4173 strcpy (buf
, "stm%?db\t");
4180 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4181 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4183 for (i
= 1; i
< nops
; i
++)
4184 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4185 reg_names
[regs
[i
]]);
4187 strcat (buf
, "}\t%@ phole stm");
4189 output_asm_insn (buf
, operands
);
4194 multi_register_push (op
, mode
)
4196 enum machine_mode mode ATTRIBUTE_UNUSED
;
4198 if (GET_CODE (op
) != PARALLEL
4199 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4200 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
4201 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
4207 /* Routines for use in generating RTL. */
4209 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
4210 in_struct_p
, scalar_p
)
4222 int sign
= up
? 1 : -1;
4225 /* XScale has load-store double instructions, but they have stricter
4226 alignment requirements than load-store multiple, so we can not
4229 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4230 the pipeline until completion.
4238 An ldr instruction takes 1-3 cycles, but does not block the
4247 Best case ldr will always win. However, the more ldr instructions
4248 we issue, the less likely we are to be able to schedule them well.
4249 Using ldr instructions also increases code size.
4251 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4252 for counts of 3 or 4 regs. */
4253 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4259 for (i
= 0; i
< count
; i
++)
4261 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
4262 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4263 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4264 MEM_SCALAR_P (mem
) = scalar_p
;
4265 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
4269 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
4271 seq
= gen_sequence ();
4277 result
= gen_rtx_PARALLEL (VOIDmode
,
4278 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4281 XVECEXP (result
, 0, 0)
4282 = gen_rtx_SET (GET_MODE (from
), from
,
4283 plus_constant (from
, count
* 4 * sign
));
4288 for (j
= 0; i
< count
; i
++, j
++)
4290 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
4291 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4292 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4293 MEM_SCALAR_P (mem
) = scalar_p
;
4294 XVECEXP (result
, 0, i
)
4295 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
4302 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
4303 in_struct_p
, scalar_p
)
4315 int sign
= up
? 1 : -1;
4318 /* See arm_gen_load_multiple for discussion of
4319 the pros/cons of ldm/stm usage for XScale. */
4320 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4326 for (i
= 0; i
< count
; i
++)
4328 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
4329 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4330 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4331 MEM_SCALAR_P (mem
) = scalar_p
;
4332 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
4336 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
4338 seq
= gen_sequence ();
4344 result
= gen_rtx_PARALLEL (VOIDmode
,
4345 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4348 XVECEXP (result
, 0, 0)
4349 = gen_rtx_SET (GET_MODE (to
), to
,
4350 plus_constant (to
, count
* 4 * sign
));
4355 for (j
= 0; i
< count
; i
++, j
++)
4357 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
4358 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4359 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4360 MEM_SCALAR_P (mem
) = scalar_p
;
4362 XVECEXP (result
, 0, i
)
4363 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
4370 arm_gen_movstrqi (operands
)
4373 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
4376 rtx st_src
, st_dst
, fin_src
, fin_dst
;
4377 rtx part_bytes_reg
= NULL
;
4379 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
4380 int dst_scalar_p
, src_scalar_p
;
4382 if (GET_CODE (operands
[2]) != CONST_INT
4383 || GET_CODE (operands
[3]) != CONST_INT
4384 || INTVAL (operands
[2]) > 64
4385 || INTVAL (operands
[3]) & 3)
4388 st_dst
= XEXP (operands
[0], 0);
4389 st_src
= XEXP (operands
[1], 0);
4391 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
4392 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
4393 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
4394 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
4395 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
4396 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
4398 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
4399 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
4401 in_words_to_go
= NUM_INTS (INTVAL (operands
[2]));
4402 out_words_to_go
= INTVAL (operands
[2]) / 4;
4403 last_bytes
= INTVAL (operands
[2]) & 3;
4405 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
4406 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
4408 for (i
= 0; in_words_to_go
>= 2; i
+=4)
4410 if (in_words_to_go
> 4)
4411 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
4416 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
4417 FALSE
, src_unchanging_p
,
4418 src_in_struct_p
, src_scalar_p
));
4420 if (out_words_to_go
)
4422 if (out_words_to_go
> 4)
4423 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
4427 else if (out_words_to_go
!= 1)
4428 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
4437 mem
= gen_rtx_MEM (SImode
, dst
);
4438 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4439 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4440 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4441 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
4442 if (last_bytes
!= 0)
4443 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
4447 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
4448 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
4451 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4452 if (out_words_to_go
)
4456 mem
= gen_rtx_MEM (SImode
, src
);
4457 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4458 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4459 MEM_SCALAR_P (mem
) = src_scalar_p
;
4460 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
4461 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
4463 mem
= gen_rtx_MEM (SImode
, dst
);
4464 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4465 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4466 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4467 emit_move_insn (mem
, sreg
);
4468 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
4471 if (in_words_to_go
) /* Sanity check */
4477 if (in_words_to_go
< 0)
4480 mem
= gen_rtx_MEM (SImode
, src
);
4481 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4482 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4483 MEM_SCALAR_P (mem
) = src_scalar_p
;
4484 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
4487 if (last_bytes
&& part_bytes_reg
== NULL
)
4490 if (BYTES_BIG_ENDIAN
&& last_bytes
)
4492 rtx tmp
= gen_reg_rtx (SImode
);
4494 /* The bytes we want are in the top end of the word. */
4495 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
4496 GEN_INT (8 * (4 - last_bytes
))));
4497 part_bytes_reg
= tmp
;
4501 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
4502 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4503 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4504 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4505 emit_move_insn (mem
, gen_rtx_SUBREG (QImode
, part_bytes_reg
, 0));
4509 tmp
= gen_reg_rtx (SImode
);
4510 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
4511 part_bytes_reg
= tmp
;
4520 mem
= gen_rtx_MEM (HImode
, dst
);
4521 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4522 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4523 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4524 emit_move_insn (mem
, gen_rtx_SUBREG (HImode
, part_bytes_reg
, 0));
4528 rtx tmp
= gen_reg_rtx (SImode
);
4530 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
4531 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
4532 part_bytes_reg
= tmp
;
4538 mem
= gen_rtx_MEM (QImode
, dst
);
4539 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4540 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4541 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4542 emit_move_insn (mem
, gen_rtx_SUBREG (QImode
, part_bytes_reg
, 0));
4549 /* Generate a memory reference for a half word, such that it will be loaded
4550 into the top 16 bits of the word. We can assume that the address is
4551 known to be alignable and of the form reg, or plus (reg, const). */
4553 arm_gen_rotated_half_load (memref
)
4556 HOST_WIDE_INT offset
= 0;
4557 rtx base
= XEXP (memref
, 0);
4559 if (GET_CODE (base
) == PLUS
)
4561 offset
= INTVAL (XEXP (base
, 1));
4562 base
= XEXP (base
, 0);
4565 /* If we aren't allowed to generate unaligned addresses, then fail. */
4566 if (TARGET_MMU_TRAPS
4567 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
4570 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
4572 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
4575 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
4578 /* Select a dominance comparison mode if possible. We support three forms.
4579 COND_OR == 0 => (X && Y)
4580 COND_OR == 1 => ((! X( || Y)
4581 COND_OR == 2 => (X || Y)
4582 If we are unable to support a dominance comparsison we return CC mode.
4583 This will then fail to match for the RTL expressions that generate this
4586 static enum machine_mode
4587 select_dominance_cc_mode (x
, y
, cond_or
)
4590 HOST_WIDE_INT cond_or
;
4592 enum rtx_code cond1
, cond2
;
4595 /* Currently we will probably get the wrong result if the individual
4596 comparisons are not simple. This also ensures that it is safe to
4597 reverse a comparison if necessary. */
4598 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
4600 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
4604 /* The if_then_else variant of this tests the second condition if the
4605 first passes, but is true if the first fails. Reverse the first
4606 condition to get a true "inclusive-or" expression. */
4608 cond1
= reverse_condition (cond1
);
4610 /* If the comparisons are not equal, and one doesn't dominate the other,
4611 then we can't do this. */
4613 && !comparison_dominates_p (cond1
, cond2
)
4614 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
4619 enum rtx_code temp
= cond1
;
4627 if (cond2
== EQ
|| !cond_or
)
4632 case LE
: return CC_DLEmode
;
4633 case LEU
: return CC_DLEUmode
;
4634 case GE
: return CC_DGEmode
;
4635 case GEU
: return CC_DGEUmode
;
4642 if (cond2
== LT
|| !cond_or
)
4651 if (cond2
== GT
|| !cond_or
)
4660 if (cond2
== LTU
|| !cond_or
)
4669 if (cond2
== GTU
|| !cond_or
)
4677 /* The remaining cases only occur when both comparisons are the
4702 arm_select_cc_mode (op
, x
, y
)
4707 /* All floating point compares return CCFP if it is an equality
4708 comparison, and CCFPE otherwise. */
4709 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4736 /* A compare with a shifted operand. Because of canonicalization, the
4737 comparison will have to be swapped when we emit the assembler. */
4738 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
4739 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4740 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
4741 || GET_CODE (x
) == ROTATERT
))
4744 /* This is a special case that is used by combine to allow a
4745 comparison of a shifted byte load to be split into a zero-extend
4746 followed by a comparison of the shifted integer (only valid for
4747 equalities and unsigned inequalities). */
4748 if (GET_MODE (x
) == SImode
4749 && GET_CODE (x
) == ASHIFT
4750 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
4751 && GET_CODE (XEXP (x
, 0)) == SUBREG
4752 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
4753 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
4754 && (op
== EQ
|| op
== NE
4755 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
4756 && GET_CODE (y
) == CONST_INT
)
4759 /* A construct for a conditional compare, if the false arm contains
4760 0, then both conditions must be true, otherwise either condition
4761 must be true. Not all conditions are possible, so CCmode is
4762 returned if it can't be done. */
4763 if (GET_CODE (x
) == IF_THEN_ELSE
4764 && (XEXP (x
, 2) == const0_rtx
4765 || XEXP (x
, 2) == const1_rtx
)
4766 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4767 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4768 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
4769 INTVAL (XEXP (x
, 2)));
4771 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4772 if (GET_CODE (x
) == AND
4773 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4774 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4775 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 0);
4777 if (GET_CODE (x
) == IOR
4778 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4779 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4780 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 2);
4782 /* An operation that sets the condition codes as a side-effect, the
4783 V flag is not set correctly, so we can only use comparisons where
4784 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4786 if (GET_MODE (x
) == SImode
4788 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
4789 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
4790 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
4791 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
4792 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
4793 || GET_CODE (x
) == LSHIFTRT
4794 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4795 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
4798 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
4801 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
4802 && GET_CODE (x
) == PLUS
4803 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
4809 /* X and Y are two things to compare using CODE. Emit the compare insn and
4810 return the rtx for register 0 in the proper mode. FP means this is a
4811 floating point compare: I don't think that it is needed on the arm. */
4814 arm_gen_compare_reg (code
, x
, y
)
4818 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
4819 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
4821 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4822 gen_rtx_COMPARE (mode
, x
, y
)));
4828 arm_reload_in_hi (operands
)
4831 rtx ref
= operands
[1];
4833 HOST_WIDE_INT offset
= 0;
4835 if (GET_CODE (ref
) == SUBREG
)
4837 offset
= SUBREG_BYTE (ref
);
4838 ref
= SUBREG_REG (ref
);
4841 if (GET_CODE (ref
) == REG
)
4843 /* We have a pseudo which has been spilt onto the stack; there
4844 are two cases here: the first where there is a simple
4845 stack-slot replacement and a second where the stack-slot is
4846 out of range, or is used as a subreg. */
4847 if (reg_equiv_mem
[REGNO (ref
)])
4849 ref
= reg_equiv_mem
[REGNO (ref
)];
4850 base
= find_replacement (&XEXP (ref
, 0));
4853 /* The slot is out of range, or was dressed up in a SUBREG. */
4854 base
= reg_equiv_address
[REGNO (ref
)];
4857 base
= find_replacement (&XEXP (ref
, 0));
4859 /* Handle the case where the address is too complex to be offset by 1. */
4860 if (GET_CODE (base
) == MINUS
4861 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
4863 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4865 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
4868 else if (GET_CODE (base
) == PLUS
)
4870 /* The addend must be CONST_INT, or we would have dealt with it above. */
4871 HOST_WIDE_INT hi
, lo
;
4873 offset
+= INTVAL (XEXP (base
, 1));
4874 base
= XEXP (base
, 0);
4876 /* Rework the address into a legal sequence of insns. */
4877 /* Valid range for lo is -4095 -> 4095 */
4880 : -((-offset
) & 0xfff));
4882 /* Corner case, if lo is the max offset then we would be out of range
4883 once we have added the additional 1 below, so bump the msb into the
4884 pre-loading insn(s). */
4888 hi
= ((((offset
- lo
) & HOST_INT (0xffffffff))
4889 ^ HOST_INT (0x80000000))
4890 - HOST_INT (0x80000000));
4892 if (hi
+ lo
!= offset
)
4897 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4899 /* Get the base address; addsi3 knows how to handle constants
4900 that require more than one insn. */
4901 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
4907 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
4908 emit_insn (gen_zero_extendqisi2 (scratch
,
4909 gen_rtx_MEM (QImode
,
4910 plus_constant (base
,
4912 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
4913 gen_rtx_MEM (QImode
,
4914 plus_constant (base
,
4916 if (!BYTES_BIG_ENDIAN
)
4917 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
4918 gen_rtx_IOR (SImode
,
4921 gen_rtx_SUBREG (SImode
, operands
[0], 0),
4925 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
4926 gen_rtx_IOR (SImode
,
4927 gen_rtx_ASHIFT (SImode
, scratch
,
4929 gen_rtx_SUBREG (SImode
, operands
[0],
4933 /* Handle storing a half-word to memory during reload by synthesising as two
4934 byte stores. Take care not to clobber the input values until after we
4935 have moved them somewhere safe. This code assumes that if the DImode
4936 scratch in operands[2] overlaps either the input value or output address
4937 in some way, then that value must die in this insn (we absolutely need
4938 two scratch registers for some corner cases). */
4940 arm_reload_out_hi (operands
)
4943 rtx ref
= operands
[0];
4944 rtx outval
= operands
[1];
4946 HOST_WIDE_INT offset
= 0;
4948 if (GET_CODE (ref
) == SUBREG
)
4950 offset
= SUBREG_BYTE (ref
);
4951 ref
= SUBREG_REG (ref
);
4955 if (GET_CODE (ref
) == REG
)
4957 /* We have a pseudo which has been spilt onto the stack; there
4958 are two cases here: the first where there is a simple
4959 stack-slot replacement and a second where the stack-slot is
4960 out of range, or is used as a subreg. */
4961 if (reg_equiv_mem
[REGNO (ref
)])
4963 ref
= reg_equiv_mem
[REGNO (ref
)];
4964 base
= find_replacement (&XEXP (ref
, 0));
4967 /* The slot is out of range, or was dressed up in a SUBREG. */
4968 base
= reg_equiv_address
[REGNO (ref
)];
4971 base
= find_replacement (&XEXP (ref
, 0));
4973 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
4975 /* Handle the case where the address is too complex to be offset by 1. */
4976 if (GET_CODE (base
) == MINUS
4977 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
4979 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4981 /* Be careful not to destroy OUTVAL. */
4982 if (reg_overlap_mentioned_p (base_plus
, outval
))
4984 /* Updating base_plus might destroy outval, see if we can
4985 swap the scratch and base_plus. */
4986 if (!reg_overlap_mentioned_p (scratch
, outval
))
4989 scratch
= base_plus
;
4994 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
4996 /* Be conservative and copy OUTVAL into the scratch now,
4997 this should only be necessary if outval is a subreg
4998 of something larger than a word. */
4999 /* XXX Might this clobber base? I can't see how it can,
5000 since scratch is known to overlap with OUTVAL, and
5001 must be wider than a word. */
5002 emit_insn (gen_movhi (scratch_hi
, outval
));
5003 outval
= scratch_hi
;
5007 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5010 else if (GET_CODE (base
) == PLUS
)
5012 /* The addend must be CONST_INT, or we would have dealt with it above. */
5013 HOST_WIDE_INT hi
, lo
;
5015 offset
+= INTVAL (XEXP (base
, 1));
5016 base
= XEXP (base
, 0);
5018 /* Rework the address into a legal sequence of insns. */
5019 /* Valid range for lo is -4095 -> 4095 */
5022 : -((-offset
) & 0xfff));
5024 /* Corner case, if lo is the max offset then we would be out of range
5025 once we have added the additional 1 below, so bump the msb into the
5026 pre-loading insn(s). */
5030 hi
= ((((offset
- lo
) & HOST_INT (0xffffffff))
5031 ^ HOST_INT (0x80000000))
5032 - HOST_INT (0x80000000));
5034 if (hi
+ lo
!= offset
)
5039 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5041 /* Be careful not to destroy OUTVAL. */
5042 if (reg_overlap_mentioned_p (base_plus
, outval
))
5044 /* Updating base_plus might destroy outval, see if we
5045 can swap the scratch and base_plus. */
5046 if (!reg_overlap_mentioned_p (scratch
, outval
))
5049 scratch
= base_plus
;
5054 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5056 /* Be conservative and copy outval into scratch now,
5057 this should only be necessary if outval is a
5058 subreg of something larger than a word. */
5059 /* XXX Might this clobber base? I can't see how it
5060 can, since scratch is known to overlap with
5062 emit_insn (gen_movhi (scratch_hi
, outval
));
5063 outval
= scratch_hi
;
5067 /* Get the base address; addsi3 knows how to handle constants
5068 that require more than one insn. */
5069 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5075 if (BYTES_BIG_ENDIAN
)
5077 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5078 plus_constant (base
, offset
+ 1)),
5079 gen_rtx_SUBREG (QImode
, outval
, 0)));
5080 emit_insn (gen_lshrsi3 (scratch
,
5081 gen_rtx_SUBREG (SImode
, outval
, 0),
5083 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5084 gen_rtx_SUBREG (QImode
, scratch
, 0)));
5088 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5089 gen_rtx_SUBREG (QImode
, outval
, 0)));
5090 emit_insn (gen_lshrsi3 (scratch
,
5091 gen_rtx_SUBREG (SImode
, outval
, 0),
5093 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5094 plus_constant (base
, offset
+ 1)),
5095 gen_rtx_SUBREG (QImode
, scratch
, 0)));
5099 /* Print a symbolic form of X to the debug file, F. */
5101 arm_print_value (f
, x
)
5105 switch (GET_CODE (x
))
5108 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
5112 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
5116 fprintf (f
, "\"%s\"", XSTR (x
, 0));
5120 fprintf (f
, "`%s'", XSTR (x
, 0));
5124 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
5128 arm_print_value (f
, XEXP (x
, 0));
5132 arm_print_value (f
, XEXP (x
, 0));
5134 arm_print_value (f
, XEXP (x
, 1));
5142 fprintf (f
, "????");
5147 /* Routines for manipulation of the constant pool. */
5149 /* Arm instructions cannot load a large constant directly into a
5150 register; they have to come from a pc relative load. The constant
5151 must therefore be placed in the addressable range of the pc
5152 relative load. Depending on the precise pc relative load
5153 instruction the range is somewhere between 256 bytes and 4k. This
5154 means that we often have to dump a constant inside a function, and
5155 generate code to branch around it.
5157 It is important to minimize this, since the branches will slow
5158 things down and make the code larger.
5160 Normally we can hide the table after an existing unconditional
5161 branch so that there is no interruption of the flow, but in the
5162 worst case the code looks like this:
5180 We fix this by performing a scan after scheduling, which notices
5181 which instructions need to have their operands fetched from the
5182 constant table and builds the table.
5184 The algorithm starts by building a table of all the constants that
5185 need fixing up and all the natural barriers in the function (places
5186 where a constant table can be dropped without breaking the flow).
5187 For each fixup we note how far the pc-relative replacement will be
5188 able to reach and the offset of the instruction into the function.
5190 Having built the table we then group the fixes together to form
5191 tables that are as large as possible (subject to addressing
5192 constraints) and emit each table of constants after the last
5193 barrier that is within range of all the instructions in the group.
5194 If a group does not contain a barrier, then we forcibly create one
5195 by inserting a jump instruction into the flow. Once the table has
5196 been inserted, the insns are then modified to reference the
5197 relevant entry in the pool.
5199 Possible enhancements to the algorithm (not implemented) are:
5201 1) For some processors and object formats, there may be benefit in
5202 aligning the pools to the start of cache lines; this alignment
5203 would need to be taken into account when calculating addressability
5206 /* These typedefs are located at the start of this file, so that
5207 they can be used in the prototypes there. This comment is to
5208 remind readers of that fact so that the following structures
5209 can be understood more easily.
5211 typedef struct minipool_node Mnode;
5212 typedef struct minipool_fixup Mfix; */
5214 struct minipool_node
5216 /* Doubly linked chain of entries. */
5219 /* The maximum offset into the code that this entry can be placed. While
5220 pushing fixes for forward references, all entries are sorted in order
5221 of increasing max_address. */
5222 HOST_WIDE_INT max_address
;
5223 /* Similarly for a entry inserted for a backwards ref. */
5224 HOST_WIDE_INT min_address
;
5225 /* The number of fixes referencing this entry. This can become zero
5226 if we "unpush" an entry. In this case we ignore the entry when we
5227 come to emit the code. */
5229 /* The offset from the start of the minipool. */
5230 HOST_WIDE_INT offset
;
5231 /* The value in table. */
5233 /* The mode of value. */
5234 enum machine_mode mode
;
5238 struct minipool_fixup
5242 HOST_WIDE_INT address
;
5244 enum machine_mode mode
;
5248 HOST_WIDE_INT forwards
;
5249 HOST_WIDE_INT backwards
;
5252 /* Fixes less than a word need padding out to a word boundary. */
5253 #define MINIPOOL_FIX_SIZE(mode) \
5254 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5256 static Mnode
* minipool_vector_head
;
5257 static Mnode
* minipool_vector_tail
;
5258 static rtx minipool_vector_label
;
5260 /* The linked list of all minipool fixes required for this function. */
5261 Mfix
* minipool_fix_head
;
5262 Mfix
* minipool_fix_tail
;
5263 /* The fix entry for the current minipool, once it has been placed. */
5264 Mfix
* minipool_barrier
;
5266 /* Determines if INSN is the start of a jump table. Returns the end
5267 of the TABLE or NULL_RTX. */
5269 is_jump_table (insn
)
5274 if (GET_CODE (insn
) == JUMP_INSN
5275 && JUMP_LABEL (insn
) != NULL
5276 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
5277 == next_real_insn (insn
))
5279 && GET_CODE (table
) == JUMP_INSN
5280 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
5281 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
5287 static HOST_WIDE_INT
5288 get_jump_table_size (insn
)
5291 rtx body
= PATTERN (insn
);
5292 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
5294 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
5297 /* Move a minipool fix MP from its current location to before MAX_MP.
5298 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5299 contrains may need updating. */
5301 move_minipool_fix_forward_ref (mp
, max_mp
, max_address
)
5304 HOST_WIDE_INT max_address
;
5306 /* This should never be true and the code below assumes these are
5313 if (max_address
< mp
->max_address
)
5314 mp
->max_address
= max_address
;
5318 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5319 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5321 mp
->max_address
= max_address
;
5323 /* Unlink MP from its current position. Since max_mp is non-null,
5324 mp->prev must be non-null. */
5325 mp
->prev
->next
= mp
->next
;
5326 if (mp
->next
!= NULL
)
5327 mp
->next
->prev
= mp
->prev
;
5329 minipool_vector_tail
= mp
->prev
;
5331 /* Re-insert it before MAX_MP. */
5333 mp
->prev
= max_mp
->prev
;
5336 if (mp
->prev
!= NULL
)
5337 mp
->prev
->next
= mp
;
5339 minipool_vector_head
= mp
;
5342 /* Save the new entry. */
5345 /* Scan over the preceeding entries and adjust their addresses as
5347 while (mp
->prev
!= NULL
5348 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5350 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5357 /* Add a constant to the minipool for a forward reference. Returns the
5358 node added or NULL if the constant will not fit in this pool. */
5360 add_minipool_forward_ref (fix
)
5363 /* If set, max_mp is the first pool_entry that has a lower
5364 constraint than the one we are trying to add. */
5365 Mnode
* max_mp
= NULL
;
5366 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
5369 /* If this fix's address is greater than the address of the first
5370 entry, then we can't put the fix in this pool. We subtract the
5371 size of the current fix to ensure that if the table is fully
5372 packed we still have enough room to insert this value by suffling
5373 the other fixes forwards. */
5374 if (minipool_vector_head
&&
5375 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
5378 /* Scan the pool to see if a constant with the same value has
5379 already been added. While we are doing this, also note the
5380 location where we must insert the constant if it doesn't already
5382 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5384 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5385 && fix
->mode
== mp
->mode
5386 && (GET_CODE (fix
->value
) != CODE_LABEL
5387 || (CODE_LABEL_NUMBER (fix
->value
)
5388 == CODE_LABEL_NUMBER (mp
->value
)))
5389 && rtx_equal_p (fix
->value
, mp
->value
))
5391 /* More than one fix references this entry. */
5393 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
5396 /* Note the insertion point if necessary. */
5398 && mp
->max_address
> max_address
)
5402 /* The value is not currently in the minipool, so we need to create
5403 a new entry for it. If MAX_MP is NULL, the entry will be put on
5404 the end of the list since the placement is less constrained than
5405 any existing entry. Otherwise, we insert the new fix before
5406 MAX_MP and, if neceesary, adjust the constraints on the other
5408 mp
= xmalloc (sizeof (* mp
));
5409 mp
->fix_size
= fix
->fix_size
;
5410 mp
->mode
= fix
->mode
;
5411 mp
->value
= fix
->value
;
5413 /* Not yet required for a backwards ref. */
5414 mp
->min_address
= -65536;
5418 mp
->max_address
= max_address
;
5420 mp
->prev
= minipool_vector_tail
;
5422 if (mp
->prev
== NULL
)
5424 minipool_vector_head
= mp
;
5425 minipool_vector_label
= gen_label_rtx ();
5428 mp
->prev
->next
= mp
;
5430 minipool_vector_tail
= mp
;
5434 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5435 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5437 mp
->max_address
= max_address
;
5440 mp
->prev
= max_mp
->prev
;
5442 if (mp
->prev
!= NULL
)
5443 mp
->prev
->next
= mp
;
5445 minipool_vector_head
= mp
;
5448 /* Save the new entry. */
5451 /* Scan over the preceeding entries and adjust their addresses as
5453 while (mp
->prev
!= NULL
5454 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5456 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5464 move_minipool_fix_backward_ref (mp
, min_mp
, min_address
)
5467 HOST_WIDE_INT min_address
;
5469 HOST_WIDE_INT offset
;
5471 /* This should never be true, and the code below assumes these are
5478 if (min_address
> mp
->min_address
)
5479 mp
->min_address
= min_address
;
5483 /* We will adjust this below if it is too loose. */
5484 mp
->min_address
= min_address
;
5486 /* Unlink MP from its current position. Since min_mp is non-null,
5487 mp->next must be non-null. */
5488 mp
->next
->prev
= mp
->prev
;
5489 if (mp
->prev
!= NULL
)
5490 mp
->prev
->next
= mp
->next
;
5492 minipool_vector_head
= mp
->next
;
5494 /* Reinsert it after MIN_MP. */
5496 mp
->next
= min_mp
->next
;
5498 if (mp
->next
!= NULL
)
5499 mp
->next
->prev
= mp
;
5501 minipool_vector_tail
= mp
;
5507 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5509 mp
->offset
= offset
;
5510 if (mp
->refcount
> 0)
5511 offset
+= mp
->fix_size
;
5513 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5514 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5520 /* Add a constant to the minipool for a backward reference. Returns the
5521 node added or NULL if the constant will not fit in this pool.
5523 Note that the code for insertion for a backwards reference can be
5524 somewhat confusing because the calculated offsets for each fix do
5525 not take into account the size of the pool (which is still under
5528 add_minipool_backward_ref (fix
)
5531 /* If set, min_mp is the last pool_entry that has a lower constraint
5532 than the one we are trying to add. */
5533 Mnode
* min_mp
= NULL
;
5534 /* This can be negative, since it is only a constraint. */
5535 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
5538 /* If we can't reach the current pool from this insn, or if we can't
5539 insert this entry at the end of the pool without pushing other
5540 fixes out of range, then we don't try. This ensures that we
5541 can't fail later on. */
5542 if (min_address
>= minipool_barrier
->address
5543 || (minipool_vector_tail
->min_address
+ fix
->fix_size
5544 >= minipool_barrier
->address
))
5547 /* Scan the pool to see if a constant with the same value has
5548 already been added. While we are doing this, also note the
5549 location where we must insert the constant if it doesn't already
5551 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
5553 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5554 && fix
->mode
== mp
->mode
5555 && (GET_CODE (fix
->value
) != CODE_LABEL
5556 || (CODE_LABEL_NUMBER (fix
->value
)
5557 == CODE_LABEL_NUMBER (mp
->value
)))
5558 && rtx_equal_p (fix
->value
, mp
->value
)
5559 /* Check that there is enough slack to move this entry to the
5560 end of the table (this is conservative). */
5562 > (minipool_barrier
->address
5563 + minipool_vector_tail
->offset
5564 + minipool_vector_tail
->fix_size
)))
5567 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
5571 mp
->min_address
+= fix
->fix_size
;
5574 /* Note the insertion point if necessary. */
5575 if (mp
->min_address
< min_address
)
5577 else if (mp
->max_address
5578 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
5580 /* Inserting before this entry would push the fix beyond
5581 its maximum address (which can happen if we have
5582 re-located a forwards fix); force the new fix to come
5585 min_address
= mp
->min_address
+ fix
->fix_size
;
5590 /* We need to create a new entry. */
5591 mp
= xmalloc (sizeof (* mp
));
5592 mp
->fix_size
= fix
->fix_size
;
5593 mp
->mode
= fix
->mode
;
5594 mp
->value
= fix
->value
;
5596 mp
->max_address
= minipool_barrier
->address
+ 65536;
5598 mp
->min_address
= min_address
;
5603 mp
->next
= minipool_vector_head
;
5605 if (mp
->next
== NULL
)
5607 minipool_vector_tail
= mp
;
5608 minipool_vector_label
= gen_label_rtx ();
5611 mp
->next
->prev
= mp
;
5613 minipool_vector_head
= mp
;
5617 mp
->next
= min_mp
->next
;
5621 if (mp
->next
!= NULL
)
5622 mp
->next
->prev
= mp
;
5624 minipool_vector_tail
= mp
;
5627 /* Save the new entry. */
5635 /* Scan over the following entries and adjust their offsets. */
5636 while (mp
->next
!= NULL
)
5638 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5639 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5642 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
5644 mp
->next
->offset
= mp
->offset
;
5653 assign_minipool_offsets (barrier
)
5656 HOST_WIDE_INT offset
= 0;
5659 minipool_barrier
= barrier
;
5661 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5663 mp
->offset
= offset
;
5665 if (mp
->refcount
> 0)
5666 offset
+= mp
->fix_size
;
5670 /* Output the literal table */
5672 dump_minipool (scan
)
5679 fprintf (rtl_dump_file
,
5680 ";; Emitting minipool after insn %u; address %ld\n",
5681 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
);
5683 scan
= emit_label_after (gen_label_rtx (), scan
);
5684 scan
= emit_insn_after (gen_align_4 (), scan
);
5685 scan
= emit_label_after (minipool_vector_label
, scan
);
5687 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
5689 if (mp
->refcount
> 0)
5693 fprintf (rtl_dump_file
,
5694 ";; Offset %u, min %ld, max %ld ",
5695 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
5696 (unsigned long) mp
->max_address
);
5697 arm_print_value (rtl_dump_file
, mp
->value
);
5698 fputc ('\n', rtl_dump_file
);
5701 switch (mp
->fix_size
)
5703 #ifdef HAVE_consttable_1
5705 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
5709 #ifdef HAVE_consttable_2
5711 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
5715 #ifdef HAVE_consttable_4
5717 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
5721 #ifdef HAVE_consttable_8
5723 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
5737 minipool_vector_head
= minipool_vector_tail
= NULL
;
5738 scan
= emit_insn_after (gen_consttable_end (), scan
);
5739 scan
= emit_barrier_after (scan
);
5742 /* Return the cost of forcibly inserting a barrier after INSN. */
5744 arm_barrier_cost (insn
)
5747 /* Basing the location of the pool on the loop depth is preferable,
5748 but at the moment, the basic block information seems to be
5749 corrupt by this stage of the compilation. */
5751 rtx next
= next_nonnote_insn (insn
);
5753 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
5756 switch (GET_CODE (insn
))
5759 /* It will always be better to place the table before the label, rather
5768 return base_cost
- 10;
5771 return base_cost
+ 10;
5775 /* Find the best place in the insn stream in the range
5776 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5777 Create the barrier by inserting a jump and add a new fix entry for
5780 create_fix_barrier (fix
, max_address
)
5782 HOST_WIDE_INT max_address
;
5784 HOST_WIDE_INT count
= 0;
5786 rtx from
= fix
->insn
;
5787 rtx selected
= from
;
5789 HOST_WIDE_INT selected_address
;
5791 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
5792 rtx label
= gen_label_rtx ();
5794 selected_cost
= arm_barrier_cost (from
);
5795 selected_address
= fix
->address
;
5797 while (from
&& count
< max_count
)
5802 /* This code shouldn't have been called if there was a natural barrier
5804 if (GET_CODE (from
) == BARRIER
)
5807 /* Count the length of this insn. */
5808 count
+= get_attr_length (from
);
5810 /* If there is a jump table, add its length. */
5811 tmp
= is_jump_table (from
);
5814 count
+= get_jump_table_size (tmp
);
5816 /* Jump tables aren't in a basic block, so base the cost on
5817 the dispatch insn. If we select this location, we will
5818 still put the pool after the table. */
5819 new_cost
= arm_barrier_cost (from
);
5821 if (count
< max_count
&& new_cost
<= selected_cost
)
5824 selected_cost
= new_cost
;
5825 selected_address
= fix
->address
+ count
;
5828 /* Continue after the dispatch table. */
5829 from
= NEXT_INSN (tmp
);
5833 new_cost
= arm_barrier_cost (from
);
5835 if (count
< max_count
&& new_cost
<= selected_cost
)
5838 selected_cost
= new_cost
;
5839 selected_address
= fix
->address
+ count
;
5842 from
= NEXT_INSN (from
);
5845 /* Create a new JUMP_INSN that branches around a barrier. */
5846 from
= emit_jump_insn_after (gen_jump (label
), selected
);
5847 JUMP_LABEL (from
) = label
;
5848 barrier
= emit_barrier_after (from
);
5849 emit_label_after (label
, barrier
);
5851 /* Create a minipool barrier entry for the new barrier. */
5852 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
5853 new_fix
->insn
= barrier
;
5854 new_fix
->address
= selected_address
;
5855 new_fix
->next
= fix
->next
;
5856 fix
->next
= new_fix
;
5861 /* Record that there is a natural barrier in the insn stream at
5864 push_minipool_barrier (insn
, address
)
5866 HOST_WIDE_INT address
;
5868 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
5871 fix
->address
= address
;
5874 if (minipool_fix_head
!= NULL
)
5875 minipool_fix_tail
->next
= fix
;
5877 minipool_fix_head
= fix
;
5879 minipool_fix_tail
= fix
;
5882 /* Record INSN, which will need fixing up to load a value from the
5883 minipool. ADDRESS is the offset of the insn since the start of the
5884 function; LOC is a pointer to the part of the insn which requires
5885 fixing; VALUE is the constant that must be loaded, which is of type
5888 push_minipool_fix (insn
, address
, loc
, mode
, value
)
5890 HOST_WIDE_INT address
;
5892 enum machine_mode mode
;
5895 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
5897 #ifdef AOF_ASSEMBLER
5898 /* PIC symbol refereneces need to be converted into offsets into the
5900 /* XXX This shouldn't be done here. */
5901 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
5902 value
= aof_pic_entry (value
);
5903 #endif /* AOF_ASSEMBLER */
5906 fix
->address
= address
;
5909 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
5911 fix
->forwards
= get_attr_pool_range (insn
);
5912 fix
->backwards
= get_attr_neg_pool_range (insn
);
5913 fix
->minipool
= NULL
;
5915 /* If an insn doesn't have a range defined for it, then it isn't
5916 expecting to be reworked by this code. Better to abort now than
5917 to generate duff assembly code. */
5918 if (fix
->forwards
== 0 && fix
->backwards
== 0)
5923 fprintf (rtl_dump_file
,
5924 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
5925 GET_MODE_NAME (mode
),
5926 INSN_UID (insn
), (unsigned long) address
,
5927 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
5928 arm_print_value (rtl_dump_file
, fix
->value
);
5929 fprintf (rtl_dump_file
, "\n");
5932 /* Add it to the chain of fixes. */
5935 if (minipool_fix_head
!= NULL
)
5936 minipool_fix_tail
->next
= fix
;
5938 minipool_fix_head
= fix
;
5940 minipool_fix_tail
= fix
;
5943 /* Scan INSN and note any of its operands that need fixing. */
5945 note_invalid_constants (insn
, address
)
5947 HOST_WIDE_INT address
;
5951 extract_insn (insn
);
5953 if (!constrain_operands (1))
5954 fatal_insn_not_found (insn
);
5956 /* Fill in recog_op_alt with information about the constraints of this
5958 preprocess_constraints ();
5960 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5962 /* Things we need to fix can only occur in inputs. */
5963 if (recog_data
.operand_type
[opno
] != OP_IN
)
5966 /* If this alternative is a memory reference, then any mention
5967 of constants in this alternative is really to fool reload
5968 into allowing us to accept one there. We need to fix them up
5969 now so that we output the right code. */
5970 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
5972 rtx op
= recog_data
.operand
[opno
];
5974 if (CONSTANT_P (op
))
5975 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
5976 recog_data
.operand_mode
[opno
], op
);
5978 /* RWE: Now we look correctly at the operands for the insn,
5979 this shouldn't be needed any more. */
5980 #ifndef AOF_ASSEMBLER
5981 /* XXX Is this still needed? */
5982 else if (GET_CODE (op
) == UNSPEC
&& XINT (op
, 1) == UNSPEC_PIC_SYM
)
5983 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
5984 recog_data
.operand_mode
[opno
],
5985 XVECEXP (op
, 0, 0));
5988 else if (GET_CODE (op
) == MEM
5989 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
5990 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
5991 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
5992 recog_data
.operand_mode
[opno
],
5993 get_pool_constant (XEXP (op
, 0)));
6003 HOST_WIDE_INT address
= 0;
6006 minipool_fix_head
= minipool_fix_tail
= NULL
;
6008 /* The first insn must always be a note, or the code below won't
6009 scan it properly. */
6010 if (GET_CODE (first
) != NOTE
)
6013 /* Scan all the insns and record the operands that will need fixing. */
6014 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
6016 if (GET_CODE (insn
) == BARRIER
)
6017 push_minipool_barrier (insn
, address
);
6018 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
6019 || GET_CODE (insn
) == JUMP_INSN
)
6023 note_invalid_constants (insn
, address
);
6024 address
+= get_attr_length (insn
);
6026 /* If the insn is a vector jump, add the size of the table
6027 and skip the table. */
6028 if ((table
= is_jump_table (insn
)) != NULL
)
6030 address
+= get_jump_table_size (table
);
6036 fix
= minipool_fix_head
;
6038 /* Now scan the fixups and perform the required changes. */
6043 Mfix
* last_added_fix
;
6044 Mfix
* last_barrier
= NULL
;
6047 /* Skip any further barriers before the next fix. */
6048 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
6051 /* No more fixes. */
6055 last_added_fix
= NULL
;
6057 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
6059 if (GET_CODE (ftmp
->insn
) == BARRIER
)
6061 if (ftmp
->address
>= minipool_vector_head
->max_address
)
6064 last_barrier
= ftmp
;
6066 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
6069 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
6072 /* If we found a barrier, drop back to that; any fixes that we
6073 could have reached but come after the barrier will now go in
6074 the next mini-pool. */
6075 if (last_barrier
!= NULL
)
6077 /* Reduce the refcount for those fixes that won't go into this
6079 for (fdel
= last_barrier
->next
;
6080 fdel
&& fdel
!= ftmp
;
6083 fdel
->minipool
->refcount
--;
6084 fdel
->minipool
= NULL
;
6087 ftmp
= last_barrier
;
6091 /* ftmp is first fix that we can't fit into this pool and
6092 there no natural barriers that we could use. Insert a
6093 new barrier in the code somewhere between the previous
6094 fix and this one, and arrange to jump around it. */
6095 HOST_WIDE_INT max_address
;
6097 /* The last item on the list of fixes must be a barrier, so
6098 we can never run off the end of the list of fixes without
6099 last_barrier being set. */
6103 max_address
= minipool_vector_head
->max_address
;
6104 /* Check that there isn't another fix that is in range that
6105 we couldn't fit into this pool because the pool was
6106 already too large: we need to put the pool before such an
6108 if (ftmp
->address
< max_address
)
6109 max_address
= ftmp
->address
;
6111 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
6114 assign_minipool_offsets (last_barrier
);
6118 if (GET_CODE (ftmp
->insn
) != BARRIER
6119 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
6126 /* Scan over the fixes we have identified for this pool, fixing them
6127 up and adding the constants to the pool itself. */
6128 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
6129 this_fix
= this_fix
->next
)
6130 if (GET_CODE (this_fix
->insn
) != BARRIER
)
6133 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
6134 minipool_vector_label
),
6135 this_fix
->minipool
->offset
);
6136 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
6139 dump_minipool (last_barrier
->insn
);
6143 /* From now on we must synthesize any constants that we can't handle
6144 directly. This can happen if the RTL gets split during final
6145 instruction generation. */
6146 after_arm_reorg
= 1;
6148 /* Free the minipool memory. */
6149 obstack_free (&minipool_obstack
, minipool_startobj
);
6152 /* Routines to output assembly language. */
6154 /* If the rtx is the correct value then return the string of the number.
6155 In this way we can ensure that valid double constants are generated even
6156 when cross compiling. */
6158 fp_immediate_constant (x
)
6164 if (!fpa_consts_inited
)
6167 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6168 for (i
= 0; i
< 8; i
++)
6169 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
6170 return strings_fpa
[i
];
6175 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6177 fp_const_from_val (r
)
6178 REAL_VALUE_TYPE
* r
;
6182 if (!fpa_consts_inited
)
6185 for (i
= 0; i
< 8; i
++)
6186 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
6187 return strings_fpa
[i
];
6192 /* Output the operands of a LDM/STM instruction to STREAM.
6193 MASK is the ARM register set mask of which only bits 0-15 are important.
6194 REG is the base register, either the frame pointer or the stack pointer,
6195 INSTR is the possibly suffixed load or store instruction. */
6198 print_multi_reg (stream
, instr
, reg
, mask
)
6205 int not_first
= FALSE
;
6207 fputc ('\t', stream
);
6208 asm_fprintf (stream
, instr
, reg
);
6209 fputs (", {", stream
);
6211 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
6212 if (mask
& (1 << i
))
6215 fprintf (stream
, ", ");
6217 asm_fprintf (stream
, "%r", i
);
6221 fprintf (stream
, "}%s\n", TARGET_APCS_32
? "" : "^");
6224 /* Output a 'call' insn. */
6227 output_call (operands
)
6230 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6232 if (REGNO (operands
[0]) == LR_REGNUM
)
6234 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
6235 output_asm_insn ("mov%?\t%0, %|lr", operands
);
6238 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6240 if (TARGET_INTERWORK
)
6241 output_asm_insn ("bx%?\t%0", operands
);
6243 output_asm_insn ("mov%?\t%|pc, %0", operands
);
6252 int something_changed
= 0;
6254 int code
= GET_CODE (x0
);
6256 register const char * fmt
;
6261 if (REGNO (x0
) == LR_REGNUM
)
6263 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
6268 /* Scan through the sub-elements and change any references there. */
6269 fmt
= GET_RTX_FORMAT (code
);
6271 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6273 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
6274 else if (fmt
[i
] == 'E')
6275 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
6276 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
6278 return something_changed
;
6282 /* Output a 'call' insn that is a reference in memory. */
6285 output_call_mem (operands
)
6288 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful. */
6289 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6290 if (eliminate_lr2ip (&operands
[0]))
6291 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
6293 if (TARGET_INTERWORK
)
6295 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
6296 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6297 output_asm_insn ("bx%?\t%|ip", operands
);
6301 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6302 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
6309 /* Output a move from arm registers to an fpu registers.
6310 OPERANDS[0] is an fpu register.
6311 OPERANDS[1] is the first registers of an arm register pair. */
6314 output_mov_long_double_fpu_from_arm (operands
)
6317 int arm_reg0
= REGNO (operands
[1]);
6320 if (arm_reg0
== IP_REGNUM
)
6323 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6324 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6325 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6327 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6328 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
6333 /* Output a move from an fpu register to arm registers.
6334 OPERANDS[0] is the first registers of an arm register pair.
6335 OPERANDS[1] is an fpu register. */
6338 output_mov_long_double_arm_from_fpu (operands
)
6341 int arm_reg0
= REGNO (operands
[0]);
6344 if (arm_reg0
== IP_REGNUM
)
6347 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6348 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6349 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6351 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
6352 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6356 /* Output a move from arm registers to arm registers of a long double
6357 OPERANDS[0] is the destination.
6358 OPERANDS[1] is the source. */
6360 output_mov_long_double_arm_from_arm (operands
)
6363 /* We have to be careful here because the two might overlap. */
6364 int dest_start
= REGNO (operands
[0]);
6365 int src_start
= REGNO (operands
[1]);
6369 if (dest_start
< src_start
)
6371 for (i
= 0; i
< 3; i
++)
6373 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6374 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6375 output_asm_insn ("mov%?\t%0, %1", ops
);
6380 for (i
= 2; i
>= 0; i
--)
6382 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6383 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6384 output_asm_insn ("mov%?\t%0, %1", ops
);
6392 /* Output a move from arm registers to an fpu registers.
6393 OPERANDS[0] is an fpu register.
6394 OPERANDS[1] is the first registers of an arm register pair. */
6397 output_mov_double_fpu_from_arm (operands
)
6400 int arm_reg0
= REGNO (operands
[1]);
6403 if (arm_reg0
== IP_REGNUM
)
6406 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6407 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6408 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
6409 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
6413 /* Output a move from an fpu register to arm registers.
6414 OPERANDS[0] is the first registers of an arm register pair.
6415 OPERANDS[1] is an fpu register. */
6418 output_mov_double_arm_from_fpu (operands
)
6421 int arm_reg0
= REGNO (operands
[0]);
6424 if (arm_reg0
== IP_REGNUM
)
6427 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6428 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6429 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
6430 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
6434 /* Output a move between double words.
6435 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6436 or MEM<-REG and all MEMs must be offsettable addresses. */
6439 output_move_double (operands
)
6442 enum rtx_code code0
= GET_CODE (operands
[0]);
6443 enum rtx_code code1
= GET_CODE (operands
[1]);
6448 int reg0
= REGNO (operands
[0]);
6450 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
6454 int reg1
= REGNO (operands
[1]);
6455 if (reg1
== IP_REGNUM
)
6458 /* Ensure the second source is not overwritten. */
6459 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
6460 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
6462 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
6464 else if (code1
== CONST_DOUBLE
)
6466 if (GET_MODE (operands
[1]) == DFmode
)
6469 union real_extract u
;
6471 memcpy (&u
, &CONST_DOUBLE_LOW (operands
[1]), sizeof (u
));
6472 REAL_VALUE_TO_TARGET_DOUBLE (u
.d
, l
);
6473 otherops
[1] = GEN_INT (l
[1]);
6474 operands
[1] = GEN_INT (l
[0]);
6476 else if (GET_MODE (operands
[1]) != VOIDmode
)
6478 else if (WORDS_BIG_ENDIAN
)
6481 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6482 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6487 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6488 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6491 output_mov_immediate (operands
);
6492 output_mov_immediate (otherops
);
6494 else if (code1
== CONST_INT
)
6496 #if HOST_BITS_PER_WIDE_INT > 32
6497 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6498 what the upper word is. */
6499 if (WORDS_BIG_ENDIAN
)
6501 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6502 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6506 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6507 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6510 /* Sign extend the intval into the high-order word. */
6511 if (WORDS_BIG_ENDIAN
)
6513 otherops
[1] = operands
[1];
6514 operands
[1] = (INTVAL (operands
[1]) < 0
6515 ? constm1_rtx
: const0_rtx
);
6518 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
6520 output_mov_immediate (otherops
);
6521 output_mov_immediate (operands
);
6523 else if (code1
== MEM
)
6525 switch (GET_CODE (XEXP (operands
[1], 0)))
6528 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
6532 abort (); /* Should never happen now. */
6536 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
6540 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
6544 abort (); /* Should never happen now. */
6549 output_asm_insn ("adr%?\t%0, %1", operands
);
6550 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
6554 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
6555 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
6557 otherops
[0] = operands
[0];
6558 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
6559 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
6560 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
6562 if (GET_CODE (otherops
[2]) == CONST_INT
)
6564 switch (INTVAL (otherops
[2]))
6567 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
6570 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
6573 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
6576 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
6577 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
6579 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6582 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6585 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
6587 return "ldm%?ia\t%0, %M0";
6591 otherops
[1] = adjust_address (operands
[1], VOIDmode
, 4);
6592 /* Take care of overlapping base/data reg. */
6593 if (reg_mentioned_p (operands
[0], operands
[1]))
6595 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6596 output_asm_insn ("ldr%?\t%0, %1", operands
);
6600 output_asm_insn ("ldr%?\t%0, %1", operands
);
6601 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6607 abort (); /* Constraints should prevent this. */
6609 else if (code0
== MEM
&& code1
== REG
)
6611 if (REGNO (operands
[1]) == IP_REGNUM
)
6614 switch (GET_CODE (XEXP (operands
[0], 0)))
6617 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
6621 abort (); /* Should never happen now. */
6625 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
6629 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
6633 abort (); /* Should never happen now. */
6637 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
6639 switch (INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
6642 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
6646 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
6650 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
6657 otherops
[0] = adjust_address (operands
[0], VOIDmode
, 4);
6658 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
6659 output_asm_insn ("str%?\t%1, %0", operands
);
6660 output_asm_insn ("str%?\t%1, %0", otherops
);
6664 abort (); /* Constraints should prevent this */
6670 /* Output an arbitrary MOV reg, #n.
6671 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6674 output_mov_immediate (operands
)
6677 HOST_WIDE_INT n
= INTVAL (operands
[1]);
6681 /* Try to use one MOV */
6682 if (const_ok_for_arm (n
))
6684 output_asm_insn ("mov%?\t%0, %1", operands
);
6688 /* Try to use one MVN */
6689 if (const_ok_for_arm (~n
))
6691 operands
[1] = GEN_INT (~n
);
6692 output_asm_insn ("mvn%?\t%0, %1", operands
);
6696 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6698 for (i
=0; i
< 32; i
++)
6702 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
6703 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n
);
6705 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
6711 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6712 adding zero to one register, output nothing. */
6715 output_add_immediate (operands
)
6718 HOST_WIDE_INT n
= INTVAL (operands
[2]);
6720 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
6723 output_multi_immediate (operands
,
6724 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6727 output_multi_immediate (operands
,
6728 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6735 /* Output a multiple immediate operation.
6736 OPERANDS is the vector of operands referred to in the output patterns.
6737 INSTR1 is the output pattern to use for the first constant.
6738 INSTR2 is the output pattern to use for subsequent constants.
6739 IMMED_OP is the index of the constant slot in OPERANDS.
6740 N is the constant value. */
6743 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
6745 const char * instr1
;
6746 const char * instr2
;
6750 #if HOST_BITS_PER_WIDE_INT > 32
6751 n
&= HOST_UINT (0xffffffff);
6756 operands
[immed_op
] = const0_rtx
;
6757 output_asm_insn (instr1
, operands
); /* Quick and easy output. */
6762 const char * instr
= instr1
;
6764 /* Note that n is never zero here (which would give no output). */
6765 for (i
= 0; i
< 32; i
+= 2)
6769 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
6770 output_asm_insn (instr
, operands
);
6781 /* Return the appropriate ARM instruction for the operation code.
6782 The returned result should not be overwritten. OP is the rtx of the
6783 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6787 arithmetic_instr (op
, shift_first_arg
)
6789 int shift_first_arg
;
6791 switch (GET_CODE (op
))
6797 return shift_first_arg
? "rsb" : "sub";
6814 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6815 for the operation code. The returned result should not be overwritten.
6816 OP is the rtx code of the shift.
6817 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6821 shift_op (op
, amountp
)
6823 HOST_WIDE_INT
*amountp
;
6826 enum rtx_code code
= GET_CODE (op
);
6828 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
6830 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6831 *amountp
= INTVAL (XEXP (op
, 1));
6854 /* We never have to worry about the amount being other than a
6855 power of 2, since this case can never be reloaded from a reg. */
6857 *amountp
= int_log2 (*amountp
);
6868 /* This is not 100% correct, but follows from the desire to merge
6869 multiplication by a power of 2 with the recognizer for a
6870 shift. >=32 is not a valid shift for "asl", so we must try and
6871 output a shift that produces the correct arithmetical result.
6872 Using lsr #32 is identical except for the fact that the carry bit
6873 is not set correctly if we set the flags; but we never use the
6874 carry bit from such an operation, so we can ignore that. */
6875 if (code
== ROTATERT
)
6876 *amountp
&= 31; /* Rotate is just modulo 32 */
6877 else if (*amountp
!= (*amountp
& 31))
6884 /* Shifts of 0 are no-ops. */
6893 /* Obtain the shift from the POWER of two. */
6894 static HOST_WIDE_INT
6896 HOST_WIDE_INT power
;
6898 HOST_WIDE_INT shift
= 0;
6900 while ((((HOST_INT (1)) << shift
) & power
) == 0)
6910 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6911 /bin/as is horribly restrictive. */
6912 #define MAX_ASCII_LEN 51
6915 output_ascii_pseudo_op (stream
, p
, len
)
6917 const unsigned char * p
;
6923 fputs ("\t.ascii\t\"", stream
);
6925 for (i
= 0; i
< len
; i
++)
6927 register int c
= p
[i
];
6929 if (len_so_far
>= MAX_ASCII_LEN
)
6931 fputs ("\"\n\t.ascii\t\"", stream
);
6938 fputs ("\\t", stream
);
6943 fputs ("\\f", stream
);
6948 fputs ("\\b", stream
);
6953 fputs ("\\r", stream
);
6957 case TARGET_NEWLINE
:
6958 fputs ("\\n", stream
);
6960 if ((c
>= ' ' && c
<= '~')
6962 /* This is a good place for a line break. */
6963 len_so_far
= MAX_ASCII_LEN
;
6970 putc ('\\', stream
);
6975 if (c
>= ' ' && c
<= '~')
6982 fprintf (stream
, "\\%03o", c
);
6989 fputs ("\"\n", stream
);
6992 /* Compute a bit mask of which registers need to be
6993 saved on the stack for the current function. */
6995 static unsigned long
6996 arm_compute_save_reg_mask ()
6998 unsigned int save_reg_mask
= 0;
7000 unsigned long func_type
= arm_current_func_type ();
7002 if (IS_NAKED (func_type
))
7003 /* This should never really happen. */
7006 /* If we are creating a stack frame, then we must save the frame pointer,
7007 IP (which will hold the old stack pointer), LR and the PC. */
7008 if (frame_pointer_needed
)
7010 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
7015 /* Volatile functions do not return, so there
7016 is no need to save any other registers. */
7017 if (IS_VOLATILE (func_type
))
7018 return save_reg_mask
;
7020 if (IS_INTERRUPT (func_type
))
7022 unsigned int max_reg
;
7024 /* Interrupt functions must not corrupt any registers,
7025 even call clobbered ones. If this is a leaf function
7026 we can just examine the registers used by the RTL, but
7027 otherwise we have to assume that whatever function is
7028 called might clobber anything, and so we have to save
7029 all the call-clobbered registers as well. */
7030 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
7031 /* FIQ handlers have registers r8 - r12 banked, so
7032 we only need to check r0 - r7, Normal ISRs only
7033 bank r14 and r15, so ew must check up to r12.
7034 r13 is the stack pointer which is always preserved,
7035 so we do not need to consider it here. */
7040 for (reg
= 0; reg
<= max_reg
; reg
++)
7041 if (regs_ever_live
[reg
]
7042 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
7043 save_reg_mask
|= (1 << reg
);
7047 /* In the normal case we only need to save those registers
7048 which are call saved and which are used by this function. */
7049 for (reg
= 0; reg
<= 10; reg
++)
7050 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7051 save_reg_mask
|= (1 << reg
);
7053 /* Handle the frame pointer as a special case. */
7054 if (! TARGET_APCS_FRAME
7055 && ! frame_pointer_needed
7056 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7057 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7058 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
7060 /* If we aren't loading the PIC register,
7061 don't stack it even though it may be live. */
7063 && ! TARGET_SINGLE_PIC_BASE
7064 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7065 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
7068 /* Decide if we need to save the link register.
7069 Interrupt routines have their own banked link register,
7070 so they never need to save it.
7071 Otheriwse if we do not use the link register we do not need to save
7072 it. If we are pushing other registers onto the stack however, we
7073 can save an instruction in the epilogue by pushing the link register
7074 now and then popping it back into the PC. This incurs extra memory
7075 accesses though, so we only do it when optimising for size, and only
7076 if we know that we will not need a fancy return sequence. */
7077 if (! IS_INTERRUPT (func_type
)
7078 && (regs_ever_live
[LR_REGNUM
]
7081 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)))
7082 save_reg_mask
|= 1 << LR_REGNUM
;
7084 if (cfun
->machine
->lr_save_eliminated
)
7085 save_reg_mask
&= ~ (1 << LR_REGNUM
);
7087 return save_reg_mask
;
7090 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7091 everything bar the final return instruction. */
7094 output_return_instruction (operand
, really_return
, reverse
)
7099 char conditional
[10];
7102 unsigned long live_regs_mask
;
7103 unsigned long func_type
;
7105 func_type
= arm_current_func_type ();
7107 if (IS_NAKED (func_type
))
7110 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7112 /* If this function was declared non-returning, and we have found a tail
7113 call, then we have to trust that the called function won't return. */
7118 /* Otherwise, trap an attempted return by aborting. */
7120 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
7122 assemble_external_libcall (ops
[1]);
7123 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
7129 if (current_function_calls_alloca
&& !really_return
)
7132 /* Construct the conditional part of the instruction(s) to be emitted. */
7133 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
7135 return_used_this_function
= 1;
7137 live_regs_mask
= arm_compute_save_reg_mask ();
7139 /* On some ARM architectures it is faster to use LDR rather than LDM to
7140 load a single register. On other architectures, the cost is the same.
7141 In 26 bit mode we have to use LDM in order to be able to restore the CPSR. */
7142 if ((live_regs_mask
== (1 << LR_REGNUM
))
7143 && ! TARGET_INTERWORK
7144 && ! IS_INTERRUPT (func_type
)
7145 && (! really_return
|| TARGET_APCS_32
))
7147 if (! really_return
)
7148 sprintf (instr
, "ldr%s\t%%|lr, [%%|sp], #4", conditional
);
7150 sprintf (instr
, "ldr%s\t%%|pc, [%%|sp], #4", conditional
);
7152 else if (live_regs_mask
)
7154 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
7155 /* There are two possible reasons for the IP register being saved.
7156 Either a stack frame was created, in which case IP contains the
7157 old stack pointer, or an ISR routine corrupted it. If this in an
7158 ISR routine then just restore IP, otherwise restore IP into SP. */
7159 if (! IS_INTERRUPT (func_type
))
7161 live_regs_mask
&= ~ (1 << IP_REGNUM
);
7162 live_regs_mask
|= (1 << SP_REGNUM
);
7165 /* Generate the load multiple instruction to restore the registers. */
7166 if (frame_pointer_needed
)
7167 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
7169 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
7171 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
7172 if (live_regs_mask
& (1 << reg
))
7174 strcat (instr
, "%|");
7175 strcat (instr
, reg_names
[reg
]);
7176 strcat (instr
, ", ");
7179 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
7181 /* If we are not restoring the LR register then we will
7182 have added one too many commas to the list above.
7183 Replace it with a closing brace. */
7184 instr
[strlen (instr
) - 2] = '}';
7188 strcat (instr
, "%|");
7190 /* At this point there should only be one or two registers left in
7191 live_regs_mask: always LR, and possibly PC if we created a stack
7192 frame. LR contains the return address. If we do not have any
7193 special requirements for function exit (eg interworking, or ISR)
7194 then we can load this value directly into the PC and save an
7196 if (! TARGET_INTERWORK
7197 && ! IS_INTERRUPT (func_type
)
7199 strcat (instr
, reg_names
[PC_REGNUM
]);
7201 strcat (instr
, reg_names
[LR_REGNUM
]);
7203 strcat (instr
, (TARGET_APCS_32
|| !really_return
) ? "}" : "}^");
7208 /* See if we need to generate an extra instruction to
7209 perform the actual function return. */
7210 switch ((int) ARM_FUNC_TYPE (func_type
))
7214 output_asm_insn (instr
, & operand
);
7216 strcpy (instr
, "sub");
7217 strcat (instr
, conditional
);
7218 strcat (instr
, "s\t%|pc, %|lr, #4");
7221 case ARM_FT_EXCEPTION
:
7222 output_asm_insn (instr
, & operand
);
7224 strcpy (instr
, "mov");
7225 strcat (instr
, conditional
);
7226 strcat (instr
, "s\t%|pc, %|lr");
7229 case ARM_FT_INTERWORKED
:
7230 output_asm_insn (instr
, & operand
);
7232 strcpy (instr
, "bx");
7233 strcat (instr
, conditional
);
7234 strcat (instr
, "\t%|lr");
7238 /* The return has already been handled
7239 by loading the LR into the PC. */
7240 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
7242 output_asm_insn (instr
, & operand
);
7244 strcpy (instr
, "mov");
7245 strcat (instr
, conditional
);
7246 if (! TARGET_APCS_32
)
7247 strcat (instr
, "s");
7248 strcat (instr
, "\t%|pc, %|lr");
7254 else if (really_return
)
7256 switch ((int) ARM_FUNC_TYPE (func_type
))
7260 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
7263 case ARM_FT_INTERWORKED
:
7264 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7267 case ARM_FT_EXCEPTION
:
7268 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
7272 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
7273 conditional
, TARGET_APCS_32
? "" : "s");
7278 /* Nothing to load off the stack, and
7279 no return instruction to generate. */
7282 output_asm_insn (instr
, & operand
);
7287 /* Write the function name into the code section, directly preceding
7288 the function prologue.
7290 Code will be output similar to this:
7292 .ascii "arm_poke_function_name", 0
7295 .word 0xff000000 + (t1 - t0)
7296 arm_poke_function_name
7298 stmfd sp!, {fp, ip, lr, pc}
7301 When performing a stack backtrace, code can inspect the value
7302 of 'pc' stored at 'fp' + 0. If the trace function then looks
7303 at location pc - 12 and the top 8 bits are set, then we know
7304 that there is a function name embedded immediately preceding this
7305 location and has length ((pc[-3]) & 0xff000000).
7307 We assume that pc is declared as a pointer to an unsigned long.
7309 It is of no benefit to output the function name if we are assembling
7310 a leaf function. These function types will not contain a stack
7311 backtrace structure, therefore it is not possible to determine the
7315 arm_poke_function_name (stream
, name
)
7319 unsigned long alignlength
;
7320 unsigned long length
;
7323 length
= strlen (name
) + 1;
7324 alignlength
= ROUND_UP (length
);
7326 ASM_OUTPUT_ASCII (stream
, name
, length
);
7327 ASM_OUTPUT_ALIGN (stream
, 2);
7328 x
= GEN_INT (HOST_UINT(0xff000000) + alignlength
);
7329 ASM_OUTPUT_INT (stream
, x
);
7332 /* Place some comments into the assembler stream
7333 describing the current function. */
7336 arm_output_function_prologue (f
, frame_size
)
7338 HOST_WIDE_INT frame_size
;
7340 unsigned long func_type
;
7344 thumb_output_function_prologue (f
, frame_size
);
7349 if (arm_ccfsm_state
|| arm_target_insn
)
7352 func_type
= arm_current_func_type ();
7354 switch ((int) ARM_FUNC_TYPE (func_type
))
7359 case ARM_FT_INTERWORKED
:
7360 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
7362 case ARM_FT_EXCEPTION_HANDLER
:
7363 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
7366 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
7369 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
7371 case ARM_FT_EXCEPTION
:
7372 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
7376 if (IS_NAKED (func_type
))
7377 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7379 if (IS_VOLATILE (func_type
))
7380 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
7382 if (IS_NESTED (func_type
))
7383 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
7385 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
7386 current_function_args_size
,
7387 current_function_pretend_args_size
, frame_size
);
7389 asm_fprintf (f
, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
7390 frame_pointer_needed
,
7391 current_function_anonymous_args
);
7393 if (cfun
->machine
->lr_save_eliminated
)
7394 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
7396 #ifdef AOF_ASSEMBLER
7398 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
7401 return_used_this_function
= 0;
7405 arm_output_epilogue (really_return
)
7409 unsigned long saved_regs_mask
;
7410 unsigned long func_type
;
7411 /* If we need this, then it will always be at least this much. */
7412 int floats_offset
= 12;
7414 int frame_size
= get_frame_size ();
7415 FILE * f
= asm_out_file
;
7416 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
7418 /* If we have already generated the return instruction
7419 then it is futile to generate anything else. */
7420 if (use_return_insn (FALSE
) && return_used_this_function
)
7423 func_type
= arm_current_func_type ();
7425 if (IS_NAKED (func_type
))
7426 /* Naked functions don't have epilogues. */
7429 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7433 /* A volatile function should never return. Call abort. */
7434 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
7435 assemble_external_libcall (op
);
7436 output_asm_insn ("bl\t%a0", &op
);
7441 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
7443 /* If we are throwing an exception, then we really must
7444 be doing a return, so we can't tail-call. */
7447 saved_regs_mask
= arm_compute_save_reg_mask ();
7449 /* Compute how far away the floats will be. */
7450 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7451 if (saved_regs_mask
& (1 << reg
))
7454 if (frame_pointer_needed
)
7456 if (arm_fpu_arch
== FP_SOFT2
)
7458 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7459 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7461 floats_offset
+= 12;
7462 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
7463 reg
, FP_REGNUM
, floats_offset
);
7468 int start_reg
= LAST_ARM_FP_REGNUM
;
7470 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7472 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7474 floats_offset
+= 12;
7476 /* We can't unstack more than four registers at once. */
7477 if (start_reg
- reg
== 3)
7479 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
7480 reg
, FP_REGNUM
, floats_offset
);
7481 start_reg
= reg
- 1;
7486 if (reg
!= start_reg
)
7487 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7488 reg
+ 1, start_reg
- reg
,
7489 FP_REGNUM
, floats_offset
);
7490 start_reg
= reg
- 1;
7494 /* Just in case the last register checked also needs unstacking. */
7495 if (reg
!= start_reg
)
7496 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7497 reg
+ 1, start_reg
- reg
,
7498 FP_REGNUM
, floats_offset
);
7501 /* saved_regs_mask should contain the IP, which at the time of stack
7502 frame generation actually contains the old stack pointer. So a
7503 quick way to unwind the stack is just pop the IP register directly
7504 into the stack pointer. */
7505 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
7507 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
7508 saved_regs_mask
|= (1 << SP_REGNUM
);
7510 /* There are two registers left in saved_regs_mask - LR and PC. We
7511 only need to restore the LR register (the return address), but to
7512 save time we can load it directly into the PC, unless we need a
7513 special function exit sequence, or we are not really returning. */
7514 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
7515 /* Delete the LR from the register mask, so that the LR on
7516 the stack is loaded into the PC in the register mask. */
7517 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7519 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
7521 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
7523 if (IS_INTERRUPT (func_type
))
7524 /* Interrupt handlers will have pushed the
7525 IP onto the stack, so restore it now. */
7526 print_multi_reg (f
, "ldmea\t%r", SP_REGNUM
, 1 << IP_REGNUM
);
7530 /* Restore stack pointer if necessary. */
7531 if (frame_size
+ current_function_outgoing_args_size
!= 0)
7533 operands
[0] = operands
[1] = stack_pointer_rtx
;
7534 operands
[2] = GEN_INT (frame_size
7535 + current_function_outgoing_args_size
);
7536 output_add_immediate (operands
);
7539 if (arm_fpu_arch
== FP_SOFT2
)
7541 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7542 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7543 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
7548 int start_reg
= FIRST_ARM_FP_REGNUM
;
7550 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7552 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7554 if (reg
- start_reg
== 3)
7556 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
7557 start_reg
, SP_REGNUM
);
7558 start_reg
= reg
+ 1;
7563 if (reg
!= start_reg
)
7564 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7565 start_reg
, reg
- start_reg
,
7568 start_reg
= reg
+ 1;
7572 /* Just in case the last register checked also needs unstacking. */
7573 if (reg
!= start_reg
)
7574 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7575 start_reg
, reg
- start_reg
, SP_REGNUM
);
7578 /* If we can, restore the LR into the PC. */
7579 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7581 && current_function_pretend_args_size
== 0
7582 && saved_regs_mask
& (1 << LR_REGNUM
))
7584 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7585 saved_regs_mask
|= (1 << PC_REGNUM
);
7588 /* Load the registers off the stack. If we only have one register
7589 to load use the LDR instruction - it is faster. */
7590 if (saved_regs_mask
== (1 << LR_REGNUM
))
7592 /* The excpetion handler ignores the LR, so we do
7593 not really need to load it off the stack. */
7595 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
7597 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
7599 else if (saved_regs_mask
)
7600 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
7602 if (current_function_pretend_args_size
)
7604 /* Unwind the pre-pushed regs. */
7605 operands
[0] = operands
[1] = stack_pointer_rtx
;
7606 operands
[2] = GEN_INT (current_function_pretend_args_size
);
7607 output_add_immediate (operands
);
7612 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
)
7613 /* Adjust the stack to remove the exception handler stuff. */
7614 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
7618 if (! really_return
)
7621 /* Generate the return instruction. */
7622 switch ((int) ARM_FUNC_TYPE (func_type
))
7624 case ARM_FT_EXCEPTION_HANDLER
:
7625 /* Even in 26-bit mode we do a mov (rather than a movs)
7626 because we don't have the PSR bits set in the address. */
7627 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
7632 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
7635 case ARM_FT_EXCEPTION
:
7636 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7639 case ARM_FT_INTERWORKED
:
7640 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
7644 if (frame_pointer_needed
)
7645 /* If we used the frame pointer then the return adddress
7646 will have been loaded off the stack directly into the
7647 PC, so there is no need to issue a MOV instruction
7650 else if (current_function_pretend_args_size
== 0
7651 && (saved_regs_mask
& (1 << LR_REGNUM
)))
7652 /* Similarly we may have been able to load LR into the PC
7653 even if we did not create a stack frame. */
7655 else if (TARGET_APCS_32
)
7656 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7658 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7666 arm_output_function_epilogue (file
, frame_size
)
7667 FILE *file ATTRIBUTE_UNUSED
;
7668 HOST_WIDE_INT frame_size
;
7672 /* ??? Probably not safe to set this here, since it assumes that a
7673 function will be emitted as assembly immediately after we generate
7674 RTL for it. This does not happen for inline functions. */
7675 return_used_this_function
= 0;
7679 if (use_return_insn (FALSE
)
7680 && return_used_this_function
7681 && (frame_size
+ current_function_outgoing_args_size
) != 0
7682 && !frame_pointer_needed
)
7685 /* Reset the ARM-specific per-function variables. */
7686 current_function_anonymous_args
= 0;
7687 after_arm_reorg
= 0;
7691 /* Generate and emit an insn that we will recognize as a push_multi.
7692 Unfortunately, since this insn does not reflect very well the actual
7693 semantics of the operation, we need to annotate the insn for the benefit
7694 of DWARF2 frame unwind information. */
7697 emit_multi_reg_push (mask
)
7705 int dwarf_par_index
;
7708 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7709 if (mask
& (1 << i
))
7712 if (num_regs
== 0 || num_regs
> 16)
7715 /* We don't record the PC in the dwarf frame information. */
7716 num_dwarf_regs
= num_regs
;
7717 if (mask
& (1 << PC_REGNUM
))
7720 /* For the body of the insn we are going to generate an UNSPEC in
7721 parallel with several USEs. This allows the insn to be recognised
7722 by the push_multi pattern in the arm.md file. The insn looks
7723 something like this:
7726 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7727 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7728 (use (reg:SI 11 fp))
7729 (use (reg:SI 12 ip))
7730 (use (reg:SI 14 lr))
7731 (use (reg:SI 15 pc))
7734 For the frame note however, we try to be more explicit and actually
7735 show each register being stored into the stack frame, plus a (single)
7736 decrement of the stack pointer. We do it this way in order to be
7737 friendly to the stack unwinding code, which only wants to see a single
7738 stack decrement per instruction. The RTL we generate for the note looks
7739 something like this:
7742 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7743 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7744 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7745 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7746 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7749 This sequence is used both by the code to support stack unwinding for
7750 exceptions handlers and the code to generate dwarf2 frame debugging. */
7752 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
7753 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
7754 RTX_FRAME_RELATED_P (dwarf
) = 1;
7755 dwarf_par_index
= 1;
7757 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7759 if (mask
& (1 << i
))
7761 reg
= gen_rtx_REG (SImode
, i
);
7764 = gen_rtx_SET (VOIDmode
,
7765 gen_rtx_MEM (BLKmode
,
7766 gen_rtx_PRE_DEC (BLKmode
,
7767 stack_pointer_rtx
)),
7768 gen_rtx_UNSPEC (BLKmode
,
7774 tmp
= gen_rtx_SET (VOIDmode
,
7775 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
7777 RTX_FRAME_RELATED_P (tmp
) = 1;
7778 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
7786 for (j
= 1, i
++; j
< num_regs
; i
++)
7788 if (mask
& (1 << i
))
7790 reg
= gen_rtx_REG (SImode
, i
);
7792 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
7796 tmp
= gen_rtx_SET (VOIDmode
,
7797 gen_rtx_MEM (SImode
,
7798 plus_constant (stack_pointer_rtx
,
7801 RTX_FRAME_RELATED_P (tmp
) = 1;
7802 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
7809 par
= emit_insn (par
);
7811 tmp
= gen_rtx_SET (SImode
,
7813 gen_rtx_PLUS (SImode
,
7815 GEN_INT (-4 * num_regs
)));
7816 RTX_FRAME_RELATED_P (tmp
) = 1;
7817 XVECEXP (dwarf
, 0, 0) = tmp
;
7819 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7825 emit_sfm (base_reg
, count
)
7834 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7835 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7836 RTX_FRAME_RELATED_P (dwarf
) = 1;
7838 reg
= gen_rtx_REG (XFmode
, base_reg
++);
7841 = gen_rtx_SET (VOIDmode
,
7842 gen_rtx_MEM (BLKmode
,
7843 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7844 gen_rtx_UNSPEC (BLKmode
,
7848 = gen_rtx_SET (VOIDmode
,
7849 gen_rtx_MEM (XFmode
,
7850 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7852 RTX_FRAME_RELATED_P (tmp
) = 1;
7853 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
7855 for (i
= 1; i
< count
; i
++)
7857 reg
= gen_rtx_REG (XFmode
, base_reg
++);
7858 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
7860 tmp
= gen_rtx_SET (VOIDmode
,
7861 gen_rtx_MEM (XFmode
,
7862 gen_rtx_PRE_DEC (BLKmode
,
7863 stack_pointer_rtx
)),
7865 RTX_FRAME_RELATED_P (tmp
) = 1;
7866 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
7869 par
= emit_insn (par
);
7870 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7875 /* Compute the distance from register FROM to register TO.
7876 These can be the arg pointer (26), the soft frame pointer (25),
7877 the stack pointer (13) or the hard frame pointer (11).
7878 Typical stack layout looks like this:
7880 old stack pointer -> | |
7883 | | saved arguments for
7884 | | vararg functions
7887 hard FP & arg pointer -> | | \
7895 soft frame pointer -> | | /
7905 current stack pointer -> | | /
7908 For a given funciton some or all of these stack compomnents
7909 may not be needed, giving rise to the possibility of
7910 eliminating some of the registers.
7912 The values returned by this function must reflect the behaviour
7913 of arm_expand_prologue() and arm_compute_save_reg_mask().
7915 The sign of the number returned reflects the direction of stack
7916 growth, so the values are positive for all eliminations except
7917 from the soft frame pointer to the hard frame pointer. */
7920 arm_compute_initial_elimination_offset (from
, to
)
7924 unsigned int local_vars
= (get_frame_size () + 3) & ~3;
7925 unsigned int outgoing_args
= current_function_outgoing_args_size
;
7926 unsigned int stack_frame
;
7927 unsigned int call_saved_registers
;
7928 unsigned long func_type
;
7930 func_type
= arm_current_func_type ();
7932 /* Volatile functions never return, so there is
7933 no need to save call saved registers. */
7934 call_saved_registers
= 0;
7935 if (! IS_VOLATILE (func_type
))
7939 /* In theory we should check all of the hard registers to
7940 see if they will be saved onto the stack. In practice
7941 registers 11 upwards have special meanings and need to
7942 be check individually. */
7943 for (reg
= 0; reg
<= 10; reg
++)
7944 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7945 call_saved_registers
+= 4;
7947 /* Determine if register 11 will be clobbered. */
7948 if (! TARGET_APCS_FRAME
7949 && ! frame_pointer_needed
7950 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7951 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7952 call_saved_registers
+= 4;
7954 /* The PIC register is fixed, so if the function will
7955 corrupt it, it has to be saved onto the stack. */
7956 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7957 call_saved_registers
+= 4;
7959 if (regs_ever_live
[LR_REGNUM
]
7960 /* If a stack frame is going to be created, the LR will
7961 be saved as part of that, so we do not need to allow
7963 && ! frame_pointer_needed
)
7964 call_saved_registers
+= 4;
7966 /* If the hard floating point registers are going to be
7967 used then they must be saved on the stack as well.
7968 Each register occupies 12 bytes of stack space. */
7969 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7970 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7971 call_saved_registers
+= 12;
7974 /* The stack frame contains 4 registers - the old frame pointer,
7975 the old stack pointer, the return address and PC of the start
7977 stack_frame
= frame_pointer_needed
? 16 : 0;
7979 /* OK, now we have enough information to compute the distances.
7980 There must be an entry in these switch tables for each pair
7981 of registers in ELIMINABLE_REGS, even if some of the entries
7982 seem to be redundant or useless. */
7985 case ARG_POINTER_REGNUM
:
7988 case THUMB_HARD_FRAME_POINTER_REGNUM
:
7991 case FRAME_POINTER_REGNUM
:
7992 /* This is the reverse of the soft frame pointer
7993 to hard frame pointer elimination below. */
7994 if (call_saved_registers
== 0 && stack_frame
== 0)
7996 return (call_saved_registers
+ stack_frame
- 4);
7998 case ARM_HARD_FRAME_POINTER_REGNUM
:
7999 /* If there is no stack frame then the hard
8000 frame pointer and the arg pointer coincide. */
8001 if (stack_frame
== 0 && call_saved_registers
!= 0)
8003 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8004 return (frame_pointer_needed
8005 && current_function_needs_context
8006 && ! current_function_anonymous_args
) ? 4 : 0;
8008 case STACK_POINTER_REGNUM
:
8009 /* If nothing has been pushed on the stack at all
8010 then this will return -4. This *is* correct! */
8011 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
8018 case FRAME_POINTER_REGNUM
:
8021 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8024 case ARM_HARD_FRAME_POINTER_REGNUM
:
8025 /* The hard frame pointer points to the top entry in the
8026 stack frame. The soft frame pointer to the bottom entry
8027 in the stack frame. If there is no stack frame at all,
8028 then they are identical. */
8029 if (call_saved_registers
== 0 && stack_frame
== 0)
8031 return - (call_saved_registers
+ stack_frame
- 4);
8033 case STACK_POINTER_REGNUM
:
8034 return local_vars
+ outgoing_args
;
8042 /* You cannot eliminate from the stack pointer.
8043 In theory you could eliminate from the hard frame
8044 pointer to the stack pointer, but this will never
8045 happen, since if a stack frame is not needed the
8046 hard frame pointer will never be used. */
8051 /* Generate the prologue instructions for entry into an ARM function. */
8054 arm_expand_prologue ()
8060 unsigned long live_regs_mask
;
8061 unsigned long func_type
;
8063 int saved_pretend_args
= 0;
8064 unsigned int args_to_push
;
8066 func_type
= arm_current_func_type ();
8068 /* Naked functions don't have prologues. */
8069 if (IS_NAKED (func_type
))
8072 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
8073 args_to_push
= current_function_pretend_args_size
;
8075 /* Compute which register we will have to save onto the stack. */
8076 live_regs_mask
= arm_compute_save_reg_mask ();
8078 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
8080 if (frame_pointer_needed
)
8082 if (IS_INTERRUPT (func_type
))
8084 /* Interrupt functions must not corrupt any registers.
8085 Creating a frame pointer however, corrupts the IP
8086 register, so we must push it first. */
8087 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
8088 RTX_FRAME_RELATED_P (insn
) = 1;
8090 else if (IS_NESTED (func_type
))
8092 /* The Static chain register is the same as the IP register
8093 used as a scratch register during stack frame creation.
8094 To get around this need to find somewhere to store IP
8095 whilst the frame is being created. We try the following
8098 1. The last argument register.
8099 2. A slot on the stack above the frame. (This only
8100 works if the function is not a varargs function).
8101 3. Register r3, after pushing the argument registers
8104 Note - we only need to tell the dwarf2 backend about the SP
8105 adjustment in the second variant; the static chain register
8106 doesn't need to be unwound, as it doesn't contain a value
8107 inherited from the caller. */
8109 if (regs_ever_live
[3] == 0)
8111 insn
= gen_rtx_REG (SImode
, 3);
8112 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8113 insn
= emit_insn (insn
);
8115 else if (args_to_push
== 0)
8118 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
8119 insn
= gen_rtx_MEM (SImode
, insn
);
8120 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
8121 insn
= emit_insn (insn
);
8125 /* Just tell the dwarf backend that we adjusted SP. */
8126 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8127 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8128 GEN_INT (-fp_offset
)));
8129 RTX_FRAME_RELATED_P (insn
) = 1;
8130 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8131 dwarf
, REG_NOTES (insn
));
8135 /* Store the args on the stack. */
8136 if (current_function_anonymous_args
)
8137 insn
= emit_multi_reg_push
8138 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8141 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8142 GEN_INT (- args_to_push
)));
8144 RTX_FRAME_RELATED_P (insn
) = 1;
8146 saved_pretend_args
= 1;
8147 fp_offset
= args_to_push
;
8150 /* Now reuse r3 to preserve IP. */
8151 insn
= gen_rtx_REG (SImode
, 3);
8152 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8153 (void) emit_insn (insn
);
8159 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
8160 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
8163 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
8165 insn
= emit_insn (insn
);
8166 RTX_FRAME_RELATED_P (insn
) = 1;
8171 /* Push the argument registers, or reserve space for them. */
8172 if (current_function_anonymous_args
)
8173 insn
= emit_multi_reg_push
8174 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8177 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8178 GEN_INT (- args_to_push
)));
8179 RTX_FRAME_RELATED_P (insn
) = 1;
8184 insn
= emit_multi_reg_push (live_regs_mask
);
8185 RTX_FRAME_RELATED_P (insn
) = 1;
8188 if (! IS_VOLATILE (func_type
))
8190 /* Save any floating point call-saved registers used by this function. */
8191 if (arm_fpu_arch
== FP_SOFT2
)
8193 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8194 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8196 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
8197 insn
= gen_rtx_MEM (XFmode
, insn
);
8198 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
8199 gen_rtx_REG (XFmode
, reg
)));
8200 RTX_FRAME_RELATED_P (insn
) = 1;
8205 int start_reg
= LAST_ARM_FP_REGNUM
;
8207 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8209 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8211 if (start_reg
- reg
== 3)
8213 insn
= emit_sfm (reg
, 4);
8214 RTX_FRAME_RELATED_P (insn
) = 1;
8215 start_reg
= reg
- 1;
8220 if (start_reg
!= reg
)
8222 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8223 RTX_FRAME_RELATED_P (insn
) = 1;
8225 start_reg
= reg
- 1;
8229 if (start_reg
!= reg
)
8231 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8232 RTX_FRAME_RELATED_P (insn
) = 1;
8237 if (frame_pointer_needed
)
8239 /* Create the new frame pointer. */
8240 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
8241 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
8242 RTX_FRAME_RELATED_P (insn
) = 1;
8244 if (IS_NESTED (func_type
))
8246 /* Recover the static chain register. */
8247 if (regs_ever_live
[3] == 0
8248 || saved_pretend_args
)
8250 insn
= gen_rtx_REG (SImode
, 3);
8251 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
8252 (void) emit_insn (insn
);
8254 else /* if (current_function_pretend_args_size == 0) */
8256 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
, GEN_INT (4));
8257 insn
= gen_rtx_MEM (SImode
, insn
);
8258 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
8259 (void) emit_insn (insn
);
8264 amount
= GEN_INT (-(get_frame_size ()
8265 + current_function_outgoing_args_size
));
8267 if (amount
!= const0_rtx
)
8269 /* This add can produce multiple insns for a large constant, so we
8270 need to get tricky. */
8271 rtx last
= get_last_insn ();
8272 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8276 last
= last
? NEXT_INSN (last
) : get_insns ();
8277 RTX_FRAME_RELATED_P (last
) = 1;
8279 while (last
!= insn
);
8281 /* If the frame pointer is needed, emit a special barrier that
8282 will prevent the scheduler from moving stores to the frame
8283 before the stack adjustment. */
8284 if (frame_pointer_needed
)
8286 rtx unspec
= gen_rtx_UNSPEC (SImode
,
8287 gen_rtvec (2, stack_pointer_rtx
,
8288 hard_frame_pointer_rtx
),
8291 insn
= emit_insn (gen_rtx_CLOBBER (VOIDmode
,
8292 gen_rtx_MEM (BLKmode
, unspec
)));
8296 /* If we are profiling, make sure no instructions are scheduled before
8297 the call to mcount. Similarly if the user has requested no
8298 scheduling in the prolog. */
8299 if (profile_flag
|| profile_block_flag
|| TARGET_NO_SCHED_PRO
)
8300 emit_insn (gen_blockage ());
8302 /* If the link register is being kept alive, with the return address in it,
8303 then make sure that it does not get reused by the ce2 pass. */
8304 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
8306 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
8307 cfun
->machine
->lr_save_eliminated
= 1;
8311 /* If CODE is 'd', then the X is a condition operand and the instruction
8312 should only be executed if the condition is true.
8313 if CODE is 'D', then the X is a condition operand and the instruction
8314 should only be executed if the condition is false: however, if the mode
8315 of the comparison is CCFPEmode, then always execute the instruction -- we
8316 do this because in these circumstances !GE does not necessarily imply LT;
8317 in these cases the instruction pattern will take care to make sure that
8318 an instruction containing %d will follow, thereby undoing the effects of
8319 doing this instruction unconditionally.
8320 If CODE is 'N' then X is a floating point operand that must be negated
8322 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8323 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8326 arm_print_operand (stream
, x
, code
)
8334 fputs (ASM_COMMENT_START
, stream
);
8338 fputs (user_label_prefix
, stream
);
8342 fputs (REGISTER_PREFIX
, stream
);
8346 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
8348 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
8351 fputs (arm_condition_codes
[arm_current_cc
], stream
);
8353 else if (current_insn_predicate
)
8355 enum arm_cond_code code
;
8360 code
= get_arm_condition_code (current_insn_predicate
);
8361 fputs (arm_condition_codes
[code
], stream
);
8368 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8369 r
= REAL_VALUE_NEGATE (r
);
8370 fprintf (stream
, "%s", fp_const_from_val (&r
));
8375 if (GET_CODE (x
) == CONST_INT
)
8378 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
8379 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8384 output_addr_const (stream
, x
);
8389 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
8393 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
8399 const char * shift
= shift_op (x
, &val
);
8403 fprintf (stream
, ", %s ", shift_op (x
, &val
));
8405 arm_print_operand (stream
, XEXP (x
, 1), 0);
8408 fputc ('#', stream
);
8409 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8415 /* An explanation of the 'Q', 'R' and 'H' register operands:
8417 In a pair of registers containing a DI or DF value the 'Q'
8418 operand returns the register number of the register containing
8419 the least signficant part of the value. The 'R' operand returns
8420 the register number of the register containing the most
8421 significant part of the value.
8423 The 'H' operand returns the higher of the two register numbers.
8424 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8425 same as the 'Q' operand, since the most signficant part of the
8426 value is held in the lower number register. The reverse is true
8427 on systems where WORDS_BIG_ENDIAN is false.
8429 The purpose of these operands is to distinguish between cases
8430 where the endian-ness of the values is important (for example
8431 when they are added together), and cases where the endian-ness
8432 is irrelevant, but the order of register operations is important.
8433 For example when loading a value from memory into a register
8434 pair, the endian-ness does not matter. Provided that the value
8435 from the lower memory address is put into the lower numbered
8436 register, and the value from the higher address is put into the
8437 higher numbered register, the load will work regardless of whether
8438 the value being loaded is big-wordian or little-wordian. The
8439 order of the two register loads can matter however, if the address
8440 of the memory location is actually held in one of the registers
8441 being overwritten by the load. */
8443 if (REGNO (x
) > LAST_ARM_REGNUM
)
8445 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
8449 if (REGNO (x
) > LAST_ARM_REGNUM
)
8451 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
8455 if (REGNO (x
) > LAST_ARM_REGNUM
)
8457 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
8461 asm_fprintf (stream
, "%r",
8462 GET_CODE (XEXP (x
, 0)) == REG
8463 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
8467 asm_fprintf (stream
, "{%r-%r}",
8469 REGNO (x
) + NUM_REGS (GET_MODE (x
)) - 1);
8477 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
8480 fputs (thumb_condition_code (x
, 0), stream
);
8488 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
8489 (get_arm_condition_code (x
))],
8492 fputs (thumb_condition_code (x
, 1), stream
);
8499 if (GET_CODE (x
) == REG
)
8500 asm_fprintf (stream
, "%r", REGNO (x
));
8501 else if (GET_CODE (x
) == MEM
)
8503 output_memory_reference_mode
= GET_MODE (x
);
8504 output_address (XEXP (x
, 0));
8506 else if (GET_CODE (x
) == CONST_DOUBLE
)
8507 fprintf (stream
, "#%s", fp_immediate_constant (x
));
8508 else if (GET_CODE (x
) == NEG
)
8509 abort (); /* This should never happen now. */
8512 fputc ('#', stream
);
8513 output_addr_const (stream
, x
);
8518 /* A finite state machine takes care of noticing whether or not instructions
8519 can be conditionally executed, and thus decrease execution time and code
8520 size by deleting branch instructions. The fsm is controlled by
8521 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8523 /* The state of the fsm controlling condition codes are:
8524 0: normal, do nothing special
8525 1: make ASM_OUTPUT_OPCODE not output this instruction
8526 2: make ASM_OUTPUT_OPCODE not output this instruction
8527 3: make instructions conditional
8528 4: make instructions conditional
8530 State transitions (state->state by whom under condition):
8531 0 -> 1 final_prescan_insn if the `target' is a label
8532 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8533 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8534 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8535 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8536 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8537 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8538 (the target insn is arm_target_insn).
8540 If the jump clobbers the conditions then we use states 2 and 4.
8542 A similar thing can be done with conditional return insns.
8544 XXX In case the `target' is an unconditional branch, this conditionalising
8545 of the instructions always reduces code size, but not always execution
8546 time. But then, I want to reduce the code size to somewhere near what
8547 /bin/cc produces. */
8549 /* Returns the index of the ARM condition code string in
8550 `arm_condition_codes'. COMPARISON should be an rtx like
8551 `(eq (...) (...))'. */
8553 static enum arm_cond_code
8554 get_arm_condition_code (comparison
)
8557 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
8559 register enum rtx_code comp_code
= GET_CODE (comparison
);
8561 if (GET_MODE_CLASS (mode
) != MODE_CC
)
8562 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
8563 XEXP (comparison
, 1));
8567 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
8568 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
8569 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
8570 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
8571 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
8572 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
8573 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
8574 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
8575 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
8576 case CC_DLTUmode
: code
= ARM_CC
;
8579 if (comp_code
!= EQ
&& comp_code
!= NE
)
8582 if (comp_code
== EQ
)
8583 return ARM_INVERSE_CONDITION_CODE (code
);
8589 case NE
: return ARM_NE
;
8590 case EQ
: return ARM_EQ
;
8591 case GE
: return ARM_PL
;
8592 case LT
: return ARM_MI
;
8599 case NE
: return ARM_NE
;
8600 case EQ
: return ARM_EQ
;
8606 /* These encodings assume that AC=1 in the FPA system control
8607 byte. This allows us to handle all cases except UNEQ and
8611 case GE
: return ARM_GE
;
8612 case GT
: return ARM_GT
;
8613 case LE
: return ARM_LS
;
8614 case LT
: return ARM_MI
;
8615 case NE
: return ARM_NE
;
8616 case EQ
: return ARM_EQ
;
8617 case ORDERED
: return ARM_VC
;
8618 case UNORDERED
: return ARM_VS
;
8619 case UNLT
: return ARM_LT
;
8620 case UNLE
: return ARM_LE
;
8621 case UNGT
: return ARM_HI
;
8622 case UNGE
: return ARM_PL
;
8623 /* UNEQ and LTGT do not have a representation. */
8624 case UNEQ
: /* Fall through. */
8625 case LTGT
: /* Fall through. */
8632 case NE
: return ARM_NE
;
8633 case EQ
: return ARM_EQ
;
8634 case GE
: return ARM_LE
;
8635 case GT
: return ARM_LT
;
8636 case LE
: return ARM_GE
;
8637 case LT
: return ARM_GT
;
8638 case GEU
: return ARM_LS
;
8639 case GTU
: return ARM_CC
;
8640 case LEU
: return ARM_CS
;
8641 case LTU
: return ARM_HI
;
8648 case LTU
: return ARM_CS
;
8649 case GEU
: return ARM_CC
;
8656 case NE
: return ARM_NE
;
8657 case EQ
: return ARM_EQ
;
8658 case GE
: return ARM_GE
;
8659 case GT
: return ARM_GT
;
8660 case LE
: return ARM_LE
;
8661 case LT
: return ARM_LT
;
8662 case GEU
: return ARM_CS
;
8663 case GTU
: return ARM_HI
;
8664 case LEU
: return ARM_LS
;
8665 case LTU
: return ARM_CC
;
8677 arm_final_prescan_insn (insn
)
8680 /* BODY will hold the body of INSN. */
8681 register rtx body
= PATTERN (insn
);
8683 /* This will be 1 if trying to repeat the trick, and things need to be
8684 reversed if it appears to fail. */
8687 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8688 taken are clobbered, even if the rtl suggests otherwise. It also
8689 means that we have to grub around within the jump expression to find
8690 out what the conditions are when the jump isn't taken. */
8691 int jump_clobbers
= 0;
8693 /* If we start with a return insn, we only succeed if we find another one. */
8694 int seeking_return
= 0;
8696 /* START_INSN will hold the insn from where we start looking. This is the
8697 first insn after the following code_label if REVERSE is true. */
8698 rtx start_insn
= insn
;
8700 /* If in state 4, check if the target branch is reached, in order to
8701 change back to state 0. */
8702 if (arm_ccfsm_state
== 4)
8704 if (insn
== arm_target_insn
)
8706 arm_target_insn
= NULL
;
8707 arm_ccfsm_state
= 0;
8712 /* If in state 3, it is possible to repeat the trick, if this insn is an
8713 unconditional branch to a label, and immediately following this branch
8714 is the previous target label which is only used once, and the label this
8715 branch jumps to is not too far off. */
8716 if (arm_ccfsm_state
== 3)
8718 if (simplejump_p (insn
))
8720 start_insn
= next_nonnote_insn (start_insn
);
8721 if (GET_CODE (start_insn
) == BARRIER
)
8723 /* XXX Isn't this always a barrier? */
8724 start_insn
= next_nonnote_insn (start_insn
);
8726 if (GET_CODE (start_insn
) == CODE_LABEL
8727 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8728 && LABEL_NUSES (start_insn
) == 1)
8733 else if (GET_CODE (body
) == RETURN
)
8735 start_insn
= next_nonnote_insn (start_insn
);
8736 if (GET_CODE (start_insn
) == BARRIER
)
8737 start_insn
= next_nonnote_insn (start_insn
);
8738 if (GET_CODE (start_insn
) == CODE_LABEL
8739 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8740 && LABEL_NUSES (start_insn
) == 1)
8752 if (arm_ccfsm_state
!= 0 && !reverse
)
8754 if (GET_CODE (insn
) != JUMP_INSN
)
8757 /* This jump might be paralleled with a clobber of the condition codes
8758 the jump should always come first */
8759 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
8760 body
= XVECEXP (body
, 0, 0);
8763 /* If this is a conditional return then we don't want to know */
8764 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8765 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
8766 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
8767 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
8772 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8773 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
8776 int fail
= FALSE
, succeed
= FALSE
;
8777 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8778 int then_not_else
= TRUE
;
8779 rtx this_insn
= start_insn
, label
= 0;
8781 /* If the jump cannot be done with one instruction, we cannot
8782 conditionally execute the instruction in the inverse case. */
8783 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
8789 /* Register the insn jumped to. */
8792 if (!seeking_return
)
8793 label
= XEXP (SET_SRC (body
), 0);
8795 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
8796 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
8797 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
8799 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
8800 then_not_else
= FALSE
;
8802 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
8804 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
8807 then_not_else
= FALSE
;
8812 /* See how many insns this branch skips, and what kind of insns. If all
8813 insns are okay, and the label or unconditional branch to the same
8814 label is not too far away, succeed. */
8815 for (insns_skipped
= 0;
8816 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
8820 this_insn
= next_nonnote_insn (this_insn
);
8824 switch (GET_CODE (this_insn
))
8827 /* Succeed if it is the target label, otherwise fail since
8828 control falls in from somewhere else. */
8829 if (this_insn
== label
)
8833 arm_ccfsm_state
= 2;
8834 this_insn
= next_nonnote_insn (this_insn
);
8837 arm_ccfsm_state
= 1;
8845 /* Succeed if the following insn is the target label.
8847 If return insns are used then the last insn in a function
8848 will be a barrier. */
8849 this_insn
= next_nonnote_insn (this_insn
);
8850 if (this_insn
&& this_insn
== label
)
8854 arm_ccfsm_state
= 2;
8855 this_insn
= next_nonnote_insn (this_insn
);
8858 arm_ccfsm_state
= 1;
8866 /* If using 32-bit addresses the cc is not preserved over
8870 /* Succeed if the following insn is the target label,
8871 or if the following two insns are a barrier and
8872 the target label. */
8873 this_insn
= next_nonnote_insn (this_insn
);
8874 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
8875 this_insn
= next_nonnote_insn (this_insn
);
8877 if (this_insn
&& this_insn
== label
8878 && insns_skipped
< max_insns_skipped
)
8882 arm_ccfsm_state
= 2;
8883 this_insn
= next_nonnote_insn (this_insn
);
8886 arm_ccfsm_state
= 1;
8895 /* If this is an unconditional branch to the same label, succeed.
8896 If it is to another label, do nothing. If it is conditional,
8898 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8900 scanbody
= PATTERN (this_insn
);
8901 if (GET_CODE (scanbody
) == SET
8902 && GET_CODE (SET_DEST (scanbody
)) == PC
)
8904 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
8905 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
8907 arm_ccfsm_state
= 2;
8910 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
8913 /* Fail if a conditional return is undesirable (eg on a
8914 StrongARM), but still allow this if optimizing for size. */
8915 else if (GET_CODE (scanbody
) == RETURN
8916 && !use_return_insn (TRUE
)
8919 else if (GET_CODE (scanbody
) == RETURN
8922 arm_ccfsm_state
= 2;
8925 else if (GET_CODE (scanbody
) == PARALLEL
)
8927 switch (get_attr_conds (this_insn
))
8937 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
8942 /* Instructions using or affecting the condition codes make it
8944 scanbody
= PATTERN (this_insn
);
8945 if (!(GET_CODE (scanbody
) == SET
8946 || GET_CODE (scanbody
) == PARALLEL
)
8947 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
8957 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
8958 arm_target_label
= CODE_LABEL_NUMBER (label
);
8959 else if (seeking_return
|| arm_ccfsm_state
== 2)
8961 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
8963 this_insn
= next_nonnote_insn (this_insn
);
8964 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
8965 || GET_CODE (this_insn
) == CODE_LABEL
))
8970 /* Oh, dear! we ran off the end.. give up */
8971 recog (PATTERN (insn
), insn
, NULL
);
8972 arm_ccfsm_state
= 0;
8973 arm_target_insn
= NULL
;
8976 arm_target_insn
= this_insn
;
8985 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
8987 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
8988 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
8989 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
8990 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
8994 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8997 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
9001 if (reverse
|| then_not_else
)
9002 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9005 /* Restore recog_data (getting the attributes of other insns can
9006 destroy this array, but final.c assumes that it remains intact
9007 across this call; since the insn has been recognized already we
9008 call recog direct). */
9009 recog (PATTERN (insn
), insn
, NULL
);
9014 arm_regno_class (regno
)
9019 if (regno
== STACK_POINTER_REGNUM
)
9021 if (regno
== CC_REGNUM
)
9028 if ( regno
<= LAST_ARM_REGNUM
9029 || regno
== FRAME_POINTER_REGNUM
9030 || regno
== ARG_POINTER_REGNUM
)
9031 return GENERAL_REGS
;
9033 if (regno
== CC_REGNUM
)
9039 /* Handle a special case when computing the offset
9040 of an argument from the frame pointer. */
9042 arm_debugger_arg_offset (value
, addr
)
9048 /* We are only interested if dbxout_parms() failed to compute the offset. */
9052 /* We can only cope with the case where the address is held in a register. */
9053 if (GET_CODE (addr
) != REG
)
9056 /* If we are using the frame pointer to point at the argument, then
9057 an offset of 0 is correct. */
9058 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
9061 /* If we are using the stack pointer to point at the
9062 argument, then an offset of 0 is correct. */
9063 if ((TARGET_THUMB
|| !frame_pointer_needed
)
9064 && REGNO (addr
) == SP_REGNUM
)
9067 /* Oh dear. The argument is pointed to by a register rather
9068 than being held in a register, or being stored at a known
9069 offset from the frame pointer. Since GDB only understands
9070 those two kinds of argument we must translate the address
9071 held in the register into an offset from the frame pointer.
9072 We do this by searching through the insns for the function
9073 looking to see where this register gets its value. If the
9074 register is initialised from the frame pointer plus an offset
9075 then we are in luck and we can continue, otherwise we give up.
9077 This code is exercised by producing debugging information
9078 for a function with arguments like this:
9080 double func (double a, double b, int c, double d) {return d;}
9082 Without this code the stab for parameter 'd' will be set to
9083 an offset of 0 from the frame pointer, rather than 8. */
9085 /* The if() statement says:
9087 If the insn is a normal instruction
9088 and if the insn is setting the value in a register
9089 and if the register being set is the register holding the address of the argument
9090 and if the address is computing by an addition
9091 that involves adding to a register
9092 which is the frame pointer
9097 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9099 if ( GET_CODE (insn
) == INSN
9100 && GET_CODE (PATTERN (insn
)) == SET
9101 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
9102 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
9103 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
9104 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
9105 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
9108 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
9117 warning ("Unable to compute real location of stacked parameter");
9118 value
= 8; /* XXX magic hack */
9124 #define def_builtin(NAME, TYPE, CODE) \
9125 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL)
9128 arm_init_builtins ()
9130 tree endlink
= void_list_node
;
9131 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
9132 tree pchar_type_node
= build_pointer_type (char_type_node
);
9134 tree int_ftype_int
, void_ftype_pchar
;
9136 /* void func (void *) */
9138 = build_function_type (void_type_node
,
9139 tree_cons (NULL_TREE
, pchar_type_node
, endlink
));
9141 /* int func (int) */
9143 = build_function_type (integer_type_node
, int_endlink
);
9145 /* Initialize arm V5 builtins. */
9147 def_builtin ("__builtin_clz", int_ftype_int
, ARM_BUILTIN_CLZ
);
9149 /* Initialize arm V5E builtins. */
9151 def_builtin ("__builtin_prefetch", void_ftype_pchar
,
9152 ARM_BUILTIN_PREFETCH
);
9155 /* Expand an expression EXP that calls a built-in function,
9156 with result going to TARGET if that's convenient
9157 (and in mode MODE if that's convenient).
9158 SUBTARGET may be used as the target for computing one of EXP's operands.
9159 IGNORE is nonzero if the value is to be ignored. */
9162 arm_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
9165 rtx subtarget ATTRIBUTE_UNUSED
;
9166 enum machine_mode mode ATTRIBUTE_UNUSED
;
9167 int ignore ATTRIBUTE_UNUSED
;
9169 enum insn_code icode
;
9170 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9171 tree arglist
= TREE_OPERAND (exp
, 1);
9174 enum machine_mode tmode
, mode0
;
9175 int fcode
= DECL_FUNCTION_CODE (fndecl
);
9182 case ARM_BUILTIN_CLZ
:
9183 icode
= CODE_FOR_clz
;
9184 arg0
= TREE_VALUE (arglist
);
9185 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
9186 tmode
= insn_data
[icode
].operand
[0].mode
;
9187 mode0
= insn_data
[icode
].operand
[1].mode
;
9189 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9190 op0
= copy_to_mode_reg (mode0
, op0
);
9192 || GET_MODE (target
) != tmode
9193 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9194 target
= gen_reg_rtx (tmode
);
9195 pat
= GEN_FCN (icode
) (target
, op0
);
9201 case ARM_BUILTIN_PREFETCH
:
9202 icode
= CODE_FOR_prefetch
;
9203 arg0
= TREE_VALUE (arglist
);
9204 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
9206 op0
= gen_rtx_MEM (SImode
, copy_to_mode_reg (Pmode
, op0
));
9208 pat
= GEN_FCN (icode
) (op0
);
9215 /* @@@ Should really do something sensible here. */
9219 /* Recursively search through all of the blocks in a function
9220 checking to see if any of the variables created in that
9221 function match the RTX called 'orig'. If they do then
9222 replace them with the RTX called 'new'. */
9225 replace_symbols_in_block (block
, orig
, new)
9230 for (; block
; block
= BLOCK_CHAIN (block
))
9234 if (!TREE_USED (block
))
9237 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
9239 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
9240 || DECL_IGNORED_P (sym
)
9241 || TREE_CODE (sym
) != VAR_DECL
9242 || DECL_EXTERNAL (sym
)
9243 || !rtx_equal_p (DECL_RTL (sym
), orig
)
9247 SET_DECL_RTL (sym
, new);
9250 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
9254 /* Return the number (counting from 0) of the least significant set
9260 number_of_first_bit_set (mask
)
9266 (mask
& (1 << bit
)) == 0;
9273 /* Generate code to return from a thumb function.
9274 If 'reg_containing_return_addr' is -1, then the return address is
9275 actually on the stack, at the stack pointer. */
9277 thumb_exit (f
, reg_containing_return_addr
, eh_ofs
)
9279 int reg_containing_return_addr
;
9282 unsigned regs_available_for_popping
;
9283 unsigned regs_to_pop
;
9289 int restore_a4
= FALSE
;
9291 /* Compute the registers we need to pop. */
9295 /* There is an assumption here, that if eh_ofs is not NULL, the
9296 normal return address will have been pushed. */
9297 if (reg_containing_return_addr
== -1 || eh_ofs
)
9299 /* When we are generating a return for __builtin_eh_return,
9300 reg_containing_return_addr must specify the return regno. */
9301 if (eh_ofs
&& reg_containing_return_addr
== -1)
9304 regs_to_pop
|= 1 << LR_REGNUM
;
9308 if (TARGET_BACKTRACE
)
9310 /* Restore the (ARM) frame pointer and stack pointer. */
9311 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
9315 /* If there is nothing to pop then just emit the BX instruction and
9317 if (pops_needed
== 0)
9320 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9322 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9325 /* Otherwise if we are not supporting interworking and we have not created
9326 a backtrace structure and the function was not entered in ARM mode then
9327 just pop the return address straight into the PC. */
9328 else if (!TARGET_INTERWORK
9329 && !TARGET_BACKTRACE
9330 && !is_called_in_ARM_mode (current_function_decl
))
9334 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
9335 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9336 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9339 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
9344 /* Find out how many of the (return) argument registers we can corrupt. */
9345 regs_available_for_popping
= 0;
9347 /* If returning via __builtin_eh_return, the bottom three registers
9348 all contain information needed for the return. */
9354 /* If we can deduce the registers used from the function's
9355 return value. This is more reliable that examining
9356 regs_ever_live[] because that will be set if the register is
9357 ever used in the function, not just if the register is used
9358 to hold a return value. */
9360 if (current_function_return_rtx
!= 0)
9361 mode
= GET_MODE (current_function_return_rtx
);
9364 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9366 size
= GET_MODE_SIZE (mode
);
9370 /* In a void function we can use any argument register.
9371 In a function that returns a structure on the stack
9372 we can use the second and third argument registers. */
9373 if (mode
== VOIDmode
)
9374 regs_available_for_popping
=
9375 (1 << ARG_REGISTER (1))
9376 | (1 << ARG_REGISTER (2))
9377 | (1 << ARG_REGISTER (3));
9379 regs_available_for_popping
=
9380 (1 << ARG_REGISTER (2))
9381 | (1 << ARG_REGISTER (3));
9384 regs_available_for_popping
=
9385 (1 << ARG_REGISTER (2))
9386 | (1 << ARG_REGISTER (3));
9388 regs_available_for_popping
=
9389 (1 << ARG_REGISTER (3));
9392 /* Match registers to be popped with registers into which we pop them. */
9393 for (available
= regs_available_for_popping
,
9394 required
= regs_to_pop
;
9395 required
!= 0 && available
!= 0;
9396 available
&= ~(available
& - available
),
9397 required
&= ~(required
& - required
))
9400 /* If we have any popping registers left over, remove them. */
9402 regs_available_for_popping
&= ~available
;
9404 /* Otherwise if we need another popping register we can use
9405 the fourth argument register. */
9406 else if (pops_needed
)
9408 /* If we have not found any free argument registers and
9409 reg a4 contains the return address, we must move it. */
9410 if (regs_available_for_popping
== 0
9411 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
9413 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9414 reg_containing_return_addr
= LR_REGNUM
;
9418 /* Register a4 is being used to hold part of the return value,
9419 but we have dire need of a free, low register. */
9422 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
9425 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
9427 /* The fourth argument register is available. */
9428 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
9434 /* Pop as many registers as we can. */
9435 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9437 /* Process the registers we popped. */
9438 if (reg_containing_return_addr
== -1)
9440 /* The return address was popped into the lowest numbered register. */
9441 regs_to_pop
&= ~(1 << LR_REGNUM
);
9443 reg_containing_return_addr
=
9444 number_of_first_bit_set (regs_available_for_popping
);
9446 /* Remove this register for the mask of available registers, so that
9447 the return address will not be corrupted by futher pops. */
9448 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
9451 /* If we popped other registers then handle them here. */
9452 if (regs_available_for_popping
)
9456 /* Work out which register currently contains the frame pointer. */
9457 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9459 /* Move it into the correct place. */
9460 asm_fprintf (f
, "\tmov\t%r, %r\n",
9461 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
9463 /* (Temporarily) remove it from the mask of popped registers. */
9464 regs_available_for_popping
&= ~(1 << frame_pointer
);
9465 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
9467 if (regs_available_for_popping
)
9471 /* We popped the stack pointer as well,
9472 find the register that contains it. */
9473 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9475 /* Move it into the stack register. */
9476 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
9478 /* At this point we have popped all necessary registers, so
9479 do not worry about restoring regs_available_for_popping
9480 to its correct value:
9482 assert (pops_needed == 0)
9483 assert (regs_available_for_popping == (1 << frame_pointer))
9484 assert (regs_to_pop == (1 << STACK_POINTER)) */
9488 /* Since we have just move the popped value into the frame
9489 pointer, the popping register is available for reuse, and
9490 we know that we still have the stack pointer left to pop. */
9491 regs_available_for_popping
|= (1 << frame_pointer
);
9495 /* If we still have registers left on the stack, but we no longer have
9496 any registers into which we can pop them, then we must move the return
9497 address into the link register and make available the register that
9499 if (regs_available_for_popping
== 0 && pops_needed
> 0)
9501 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
9503 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
9504 reg_containing_return_addr
);
9506 reg_containing_return_addr
= LR_REGNUM
;
9509 /* If we have registers left on the stack then pop some more.
9510 We know that at most we will want to pop FP and SP. */
9511 if (pops_needed
> 0)
9516 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9518 /* We have popped either FP or SP.
9519 Move whichever one it is into the correct register. */
9520 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9521 move_to
= number_of_first_bit_set (regs_to_pop
);
9523 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
9525 regs_to_pop
&= ~(1 << move_to
);
9530 /* If we still have not popped everything then we must have only
9531 had one register available to us and we are now popping the SP. */
9532 if (pops_needed
> 0)
9536 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9538 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9540 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
9542 assert (regs_to_pop == (1 << STACK_POINTER))
9543 assert (pops_needed == 1)
9547 /* If necessary restore the a4 register. */
9550 if (reg_containing_return_addr
!= LR_REGNUM
)
9552 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9553 reg_containing_return_addr
= LR_REGNUM
;
9556 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
9560 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9562 /* Return to caller. */
9563 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9566 /* Emit code to push or pop registers to or from the stack. */
9568 thumb_pushpop (f
, mask
, push
)
9574 int lo_mask
= mask
& 0xFF;
9576 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
9578 /* Special case. Do not generate a POP PC statement here, do it in
9580 thumb_exit (f
, -1, NULL_RTX
);
9584 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
9586 /* Look at the low registers first. */
9587 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
9591 asm_fprintf (f
, "%r", regno
);
9593 if ((lo_mask
& ~1) != 0)
9598 if (push
&& (mask
& (1 << LR_REGNUM
)))
9600 /* Catch pushing the LR. */
9604 asm_fprintf (f
, "%r", LR_REGNUM
);
9606 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
9608 /* Catch popping the PC. */
9609 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
9611 /* The PC is never poped directly, instead
9612 it is popped into r3 and then BX is used. */
9615 thumb_exit (f
, -1, NULL_RTX
);
9624 asm_fprintf (f
, "%r", PC_REGNUM
);
9632 thumb_final_prescan_insn (insn
)
9635 if (flag_print_asm_name
)
9636 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
9637 INSN_ADDRESSES (INSN_UID (insn
)));
9641 thumb_shiftable_const (val
)
9642 unsigned HOST_WIDE_INT val
;
9644 unsigned HOST_WIDE_INT mask
= 0xff;
9647 if (val
== 0) /* XXX */
9650 for (i
= 0; i
< 25; i
++)
9651 if ((val
& (mask
<< i
)) == val
)
9657 /* Returns non-zero if the current function contains,
9658 or might contain a far jump. */
9660 thumb_far_jump_used_p (int in_prologue
)
9664 /* This test is only important for leaf functions. */
9665 /* assert (!leaf_function_p ()); */
9667 /* If we have already decided that far jumps may be used,
9668 do not bother checking again, and always return true even if
9669 it turns out that they are not being used. Once we have made
9670 the decision that far jumps are present (and that hence the link
9671 register will be pushed onto the stack) we cannot go back on it. */
9672 if (cfun
->machine
->far_jump_used
)
9675 /* If this function is not being called from the prologue/epilogue
9676 generation code then it must be being called from the
9677 INITIAL_ELIMINATION_OFFSET macro. */
9680 /* In this case we know that we are being asked about the elimination
9681 of the arg pointer register. If that register is not being used,
9682 then there are no arguments on the stack, and we do not have to
9683 worry that a far jump might force the prologue to push the link
9684 register, changing the stack offsets. In this case we can just
9685 return false, since the presence of far jumps in the function will
9686 not affect stack offsets.
9688 If the arg pointer is live (or if it was live, but has now been
9689 eliminated and so set to dead) then we do have to test to see if
9690 the function might contain a far jump. This test can lead to some
9691 false negatives, since before reload is completed, then length of
9692 branch instructions is not known, so gcc defaults to returning their
9693 longest length, which in turn sets the far jump attribute to true.
9695 A false negative will not result in bad code being generated, but it
9696 will result in a needless push and pop of the link register. We
9697 hope that this does not occur too often. */
9698 if (regs_ever_live
[ARG_POINTER_REGNUM
])
9699 cfun
->machine
->arg_pointer_live
= 1;
9700 else if (!cfun
->machine
->arg_pointer_live
)
9704 /* Check to see if the function contains a branch
9705 insn with the far jump attribute set. */
9706 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9708 if (GET_CODE (insn
) == JUMP_INSN
9709 /* Ignore tablejump patterns. */
9710 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
9711 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
9712 && get_attr_far_jump (insn
) == FAR_JUMP_YES
9715 /* Record the fact that we have decied that
9716 the function does use far jumps. */
9717 cfun
->machine
->far_jump_used
= 1;
9725 /* Return non-zero if FUNC must be entered in ARM mode. */
9727 is_called_in_ARM_mode (func
)
9730 if (TREE_CODE (func
) != FUNCTION_DECL
)
9733 /* Ignore the problem about functions whoes address is taken. */
9734 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
9738 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
9744 /* The bits which aren't usefully expanded as rtl. */
9747 thumb_unexpanded_epilogue ()
9750 int live_regs_mask
= 0;
9751 int high_regs_pushed
= 0;
9752 int leaf_function
= leaf_function_p ();
9754 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
9756 if (return_used_this_function
)
9759 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
9760 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
9761 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
9762 live_regs_mask
|= 1 << regno
;
9764 for (regno
= 8; regno
< 13; regno
++)
9766 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
9767 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
9771 /* The prolog may have pushed some high registers to use as
9772 work registers. eg the testuite file:
9773 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9774 compiles to produce:
9775 push {r4, r5, r6, r7, lr}
9779 as part of the prolog. We have to undo that pushing here. */
9781 if (high_regs_pushed
)
9783 int mask
= live_regs_mask
;
9789 /* If we can deduce the registers used from the function's return value.
9790 This is more reliable that examining regs_ever_live[] because that
9791 will be set if the register is ever used in the function, not just if
9792 the register is used to hold a return value. */
9794 if (current_function_return_rtx
!= 0)
9795 mode
= GET_MODE (current_function_return_rtx
);
9798 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9800 size
= GET_MODE_SIZE (mode
);
9802 /* Unless we are returning a type of size > 12 register r3 is
9808 /* Oh dear! We have no low registers into which we can pop
9811 ("no low registers available for popping high registers");
9813 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
9814 if (regs_ever_live
[next_hi_reg
] && !call_used_regs
[next_hi_reg
]
9815 && !(TARGET_SINGLE_PIC_BASE
&& (next_hi_reg
== arm_pic_register
)))
9818 while (high_regs_pushed
)
9820 /* Find lo register(s) into which the high register(s) can
9822 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
9824 if (mask
& (1 << regno
))
9826 if (high_regs_pushed
== 0)
9830 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
9832 /* Pop the values into the low register(s). */
9833 thumb_pushpop (asm_out_file
, mask
, 0);
9835 /* Move the value(s) into the high registers. */
9836 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
9838 if (mask
& (1 << regno
))
9840 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
9843 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
9844 if (regs_ever_live
[next_hi_reg
]
9845 && !call_used_regs
[next_hi_reg
]
9846 && !(TARGET_SINGLE_PIC_BASE
9847 && (next_hi_reg
== arm_pic_register
)))
9854 had_to_push_lr
= (live_regs_mask
|| !leaf_function
9855 || thumb_far_jump_used_p (1));
9857 if (TARGET_BACKTRACE
9858 && ((live_regs_mask
& 0xFF) == 0)
9859 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
9861 /* The stack backtrace structure creation code had to
9862 push R7 in order to get a work register, so we pop
9864 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
9867 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
9870 && !is_called_in_ARM_mode (current_function_decl
)
9872 live_regs_mask
|= 1 << PC_REGNUM
;
9874 /* Either no argument registers were pushed or a backtrace
9875 structure was created which includes an adjusted stack
9876 pointer, so just pop everything. */
9878 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
9881 thumb_exit (asm_out_file
, 2, eh_ofs
);
9882 /* We have either just popped the return address into the
9883 PC or it is was kept in LR for the entire function or
9884 it is still on the stack because we do not want to
9885 return by doing a pop {pc}. */
9886 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
9887 thumb_exit (asm_out_file
,
9889 && is_called_in_ARM_mode (current_function_decl
)) ?
9890 -1 : LR_REGNUM
, NULL_RTX
);
9894 /* Pop everything but the return address. */
9895 live_regs_mask
&= ~(1 << PC_REGNUM
);
9898 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
9901 /* Get the return address into a temporary register. */
9902 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
9904 /* Remove the argument registers that were pushed onto the stack. */
9905 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
9906 SP_REGNUM
, SP_REGNUM
,
9907 current_function_pretend_args_size
);
9910 thumb_exit (asm_out_file
, 2, eh_ofs
);
9912 thumb_exit (asm_out_file
,
9913 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
9919 /* Functions to save and restore machine-specific function data. */
9922 arm_mark_machine_status (p
)
9923 struct function
* p
;
9925 machine_function
*machine
= p
->machine
;
9928 ggc_mark_rtx (machine
->eh_epilogue_sp_ofs
);
9932 arm_init_machine_status (p
)
9933 struct function
* p
;
9936 (machine_function
*) xcalloc (1, sizeof (machine_function
));
9938 #if ARM_FT_UNKNOWWN != 0
9939 ((machine_function
*) p
->machine
)->func_type
= ARM_FT_UNKNOWN
;
9944 arm_free_machine_status (p
)
9945 struct function
* p
;
9954 /* Return an RTX indicating where the return address to the
9955 calling function can be found. */
9957 arm_return_addr (count
, frame
)
9959 rtx frame ATTRIBUTE_UNUSED
;
9965 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
9968 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
9969 GEN_INT (RETURN_ADDR_MASK26
));
9970 return get_func_hard_reg_initial_val (cfun
, lr
);
9974 /* Do anything needed before RTL is emitted for each function. */
9976 arm_init_expanders ()
9978 /* Arrange to initialize and mark the machine per-function status. */
9979 init_machine_status
= arm_init_machine_status
;
9980 mark_machine_status
= arm_mark_machine_status
;
9981 free_machine_status
= arm_free_machine_status
;
9984 /* Generate the rest of a function's prologue. */
9986 thumb_expand_prologue ()
9988 HOST_WIDE_INT amount
= (get_frame_size ()
9989 + current_function_outgoing_args_size
);
9990 unsigned long func_type
;
9992 func_type
= arm_current_func_type ();
9994 /* Naked functions don't have prologues. */
9995 if (IS_NAKED (func_type
))
9998 if (IS_INTERRUPT (func_type
))
10000 error ("Interrupt Service Routines cannot be coded in Thumb mode.");
10004 if (frame_pointer_needed
)
10005 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
10009 amount
= ROUND_UP (amount
);
10012 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10013 GEN_INT (-amount
)));
10019 /* The stack decrement is too big for an immediate value in a single
10020 insn. In theory we could issue multiple subtracts, but after
10021 three of them it becomes more space efficient to place the full
10022 value in the constant pool and load into a register. (Also the
10023 ARM debugger really likes to see only one stack decrement per
10024 function). So instead we look for a scratch register into which
10025 we can load the decrement, and then we subtract this from the
10026 stack pointer. Unfortunately on the thumb the only available
10027 scratch registers are the argument registers, and we cannot use
10028 these as they may hold arguments to the function. Instead we
10029 attempt to locate a call preserved register which is used by this
10030 function. If we can find one, then we know that it will have
10031 been pushed at the start of the prologue and so we can corrupt
10033 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
10034 if (regs_ever_live
[regno
]
10035 && !call_used_regs
[regno
] /* Paranoia */
10036 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
))
10037 && !(frame_pointer_needed
10038 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
10041 if (regno
> LAST_LO_REGNUM
) /* Very unlikely */
10043 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
10045 /* Choose an arbitary, non-argument low register. */
10046 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
10048 /* Save it by copying it into a high, scratch register. */
10049 emit_insn (gen_movsi (spare
, reg
));
10051 /* Decrement the stack. */
10052 emit_insn (gen_movsi (reg
, GEN_INT (-amount
)));
10053 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10056 /* Restore the low register's original value. */
10057 emit_insn (gen_movsi (reg
, spare
));
10059 /* Emit a USE of the restored scratch register, so that flow
10060 analysis will not consider the restore redundant. The
10061 register won't be used again in this function and isn't
10062 restored by the epilogue. */
10063 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
10067 reg
= gen_rtx (REG
, SImode
, regno
);
10069 emit_insn (gen_movsi (reg
, GEN_INT (-amount
)));
10070 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10076 if (profile_flag
|| profile_block_flag
|| TARGET_NO_SCHED_PRO
)
10077 emit_insn (gen_blockage ());
10081 thumb_expand_epilogue ()
10083 HOST_WIDE_INT amount
= (get_frame_size ()
10084 + current_function_outgoing_args_size
);
10086 /* Naked functions don't have prologues. */
10087 if (IS_NAKED (arm_current_func_type ()))
10090 if (frame_pointer_needed
)
10091 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
10094 amount
= ROUND_UP (amount
);
10097 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10098 GEN_INT (amount
)));
10101 /* r3 is always free in the epilogue. */
10102 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
10104 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
10105 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
10109 /* Emit a USE (stack_pointer_rtx), so that
10110 the stack adjustment will not be deleted. */
10111 emit_insn (gen_rtx_USE (VOIDmode
, stack_pointer_rtx
));
10113 if (profile_flag
|| profile_block_flag
|| TARGET_NO_SCHED_PRO
)
10114 emit_insn (gen_blockage ());
10118 thumb_output_function_prologue (f
, size
)
10120 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
10122 int live_regs_mask
= 0;
10123 int high_regs_pushed
= 0;
10126 if (IS_NAKED (arm_current_func_type ()))
10129 if (is_called_in_ARM_mode (current_function_decl
))
10133 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
10135 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
10137 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10139 /* Generate code sequence to switch us into Thumb mode. */
10140 /* The .code 32 directive has already been emitted by
10141 ASM_DECLARE_FUNCTION_NAME. */
10142 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
10143 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
10145 /* Generate a label, so that the debugger will notice the
10146 change in instruction sets. This label is also used by
10147 the assembler to bypass the ARM code when this function
10148 is called from a Thumb encoded function elsewhere in the
10149 same file. Hence the definition of STUB_NAME here must
10150 agree with the definition in gas/config/tc-arm.c */
10152 #define STUB_NAME ".real_start_of"
10154 asm_fprintf (f
, "\t.code\t16\n");
10156 if (arm_dllexport_name_p (name
))
10157 name
= arm_strip_name_encoding (name
);
10159 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
10160 asm_fprintf (f
, "\t.thumb_func\n");
10161 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
10164 if (current_function_pretend_args_size
)
10166 if (current_function_anonymous_args
)
10170 asm_fprintf (f
, "\tpush\t{");
10172 num_pushes
= NUM_INTS (current_function_pretend_args_size
);
10174 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
10175 regno
<= LAST_ARG_REGNUM
;
10177 asm_fprintf (f
, "%r%s", regno
,
10178 regno
== LAST_ARG_REGNUM
? "" : ", ");
10180 asm_fprintf (f
, "}\n");
10183 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
10184 SP_REGNUM
, SP_REGNUM
,
10185 current_function_pretend_args_size
);
10188 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10189 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
10190 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
10191 live_regs_mask
|= 1 << regno
;
10193 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
10194 live_regs_mask
|= 1 << LR_REGNUM
;
10196 if (TARGET_BACKTRACE
)
10199 int work_register
= 0;
10202 /* We have been asked to create a stack backtrace structure.
10203 The code looks like this:
10207 0 sub SP, #16 Reserve space for 4 registers.
10208 2 push {R7} Get a work register.
10209 4 add R7, SP, #20 Get the stack pointer before the push.
10210 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10211 8 mov R7, PC Get hold of the start of this code plus 12.
10212 10 str R7, [SP, #16] Store it.
10213 12 mov R7, FP Get hold of the current frame pointer.
10214 14 str R7, [SP, #4] Store it.
10215 16 mov R7, LR Get hold of the current return address.
10216 18 str R7, [SP, #12] Store it.
10217 20 add R7, SP, #16 Point at the start of the backtrace structure.
10218 22 mov FP, R7 Put this value into the frame pointer. */
10220 if ((live_regs_mask
& 0xFF) == 0)
10222 /* See if the a4 register is free. */
10224 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
10225 work_register
= LAST_ARG_REGNUM
;
10226 else /* We must push a register of our own */
10227 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10230 if (work_register
== 0)
10232 /* Select a register from the list that will be pushed to
10233 use as our work register. */
10234 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
10235 if ((1 << work_register
) & live_regs_mask
)
10240 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10241 SP_REGNUM
, SP_REGNUM
);
10243 if (live_regs_mask
)
10244 thumb_pushpop (f
, live_regs_mask
, 1);
10246 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
10247 if (wr
& live_regs_mask
)
10250 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10251 offset
+ 16 + current_function_pretend_args_size
);
10253 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10256 /* Make sure that the instruction fetching the PC is in the right place
10257 to calculate "start of backtrace creation code + 12". */
10258 if (live_regs_mask
)
10260 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10261 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10263 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10264 ARM_HARD_FRAME_POINTER_REGNUM
);
10265 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10270 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10271 ARM_HARD_FRAME_POINTER_REGNUM
);
10272 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10274 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10275 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10279 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
10280 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10282 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10284 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10285 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
10287 else if (live_regs_mask
)
10288 thumb_pushpop (f
, live_regs_mask
, 1);
10290 for (regno
= 8; regno
< 13; regno
++)
10292 if (regs_ever_live
[regno
] && !call_used_regs
[regno
]
10293 && !(TARGET_SINGLE_PIC_BASE
&& (regno
== arm_pic_register
)))
10294 high_regs_pushed
++;
10297 if (high_regs_pushed
)
10299 int pushable_regs
= 0;
10300 int mask
= live_regs_mask
& 0xff;
10303 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
10305 if (regs_ever_live
[next_hi_reg
] && !call_used_regs
[next_hi_reg
]
10306 && !(TARGET_SINGLE_PIC_BASE
10307 && (next_hi_reg
== arm_pic_register
)))
10311 pushable_regs
= mask
;
10313 if (pushable_regs
== 0)
10315 /* Desperation time -- this probably will never happen. */
10316 if (regs_ever_live
[LAST_ARG_REGNUM
]
10317 || !call_used_regs
[LAST_ARG_REGNUM
])
10318 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
10319 mask
= 1 << LAST_ARG_REGNUM
;
10322 while (high_regs_pushed
> 0)
10324 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
10326 if (mask
& (1 << regno
))
10328 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
10330 high_regs_pushed
--;
10332 if (high_regs_pushed
)
10333 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
10336 if (regs_ever_live
[next_hi_reg
]
10337 && !call_used_regs
[next_hi_reg
]
10338 && !(TARGET_SINGLE_PIC_BASE
10339 && (next_hi_reg
== arm_pic_register
)))
10344 mask
&= ~((1 << regno
) - 1);
10350 thumb_pushpop (f
, mask
, 1);
10353 if (pushable_regs
== 0
10354 && (regs_ever_live
[LAST_ARG_REGNUM
]
10355 || !call_used_regs
[LAST_ARG_REGNUM
]))
10356 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
10360 /* Handle the case of a double word load into a low register from
10361 a computed memory address. The computed address may involve a
10362 register which is overwritten by the load. */
10365 thumb_load_double_from_address (operands
)
10374 if (GET_CODE (operands
[0]) != REG
)
10377 if (GET_CODE (operands
[1]) != MEM
)
10380 /* Get the memory address. */
10381 addr
= XEXP (operands
[1], 0);
10383 /* Work out how the memory address is computed. */
10384 switch (GET_CODE (addr
))
10387 operands
[2] = gen_rtx (MEM
, SImode
,
10388 plus_constant (XEXP (operands
[1], 0), 4));
10390 if (REGNO (operands
[0]) == REGNO (addr
))
10392 output_asm_insn ("ldr\t%H0, %2", operands
);
10393 output_asm_insn ("ldr\t%0, %1", operands
);
10397 output_asm_insn ("ldr\t%0, %1", operands
);
10398 output_asm_insn ("ldr\t%H0, %2", operands
);
10403 /* Compute <address> + 4 for the high order load. */
10404 operands
[2] = gen_rtx (MEM
, SImode
,
10405 plus_constant (XEXP (operands
[1], 0), 4));
10407 output_asm_insn ("ldr\t%0, %1", operands
);
10408 output_asm_insn ("ldr\t%H0, %2", operands
);
10412 arg1
= XEXP (addr
, 0);
10413 arg2
= XEXP (addr
, 1);
10415 if (CONSTANT_P (arg1
))
10416 base
= arg2
, offset
= arg1
;
10418 base
= arg1
, offset
= arg2
;
10420 if (GET_CODE (base
) != REG
)
10423 /* Catch the case of <address> = <reg> + <reg> */
10424 if (GET_CODE (offset
) == REG
)
10426 int reg_offset
= REGNO (offset
);
10427 int reg_base
= REGNO (base
);
10428 int reg_dest
= REGNO (operands
[0]);
10430 /* Add the base and offset registers together into the
10431 higher destination register. */
10432 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
10433 reg_dest
+ 1, reg_base
, reg_offset
);
10435 /* Load the lower destination register from the address in
10436 the higher destination register. */
10437 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
10438 reg_dest
, reg_dest
+ 1);
10440 /* Load the higher destination register from its own address
10442 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
10443 reg_dest
+ 1, reg_dest
+ 1);
10447 /* Compute <address> + 4 for the high order load. */
10448 operands
[2] = gen_rtx (MEM
, SImode
,
10449 plus_constant (XEXP (operands
[1], 0), 4));
10451 /* If the computed address is held in the low order register
10452 then load the high order register first, otherwise always
10453 load the low order register first. */
10454 if (REGNO (operands
[0]) == REGNO (base
))
10456 output_asm_insn ("ldr\t%H0, %2", operands
);
10457 output_asm_insn ("ldr\t%0, %1", operands
);
10461 output_asm_insn ("ldr\t%0, %1", operands
);
10462 output_asm_insn ("ldr\t%H0, %2", operands
);
10468 /* With no registers to worry about we can just load the value
10470 operands
[2] = gen_rtx (MEM
, SImode
,
10471 plus_constant (XEXP (operands
[1], 0), 4));
10473 output_asm_insn ("ldr\t%H0, %2", operands
);
10474 output_asm_insn ("ldr\t%0, %1", operands
);
10487 thumb_output_move_mem_multiple (n
, operands
)
10496 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10499 operands
[4] = operands
[5];
10502 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
10503 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
10507 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10510 operands
[4] = operands
[5];
10513 if (REGNO (operands
[5]) > REGNO (operands
[6]))
10516 operands
[5] = operands
[6];
10519 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10522 operands
[4] = operands
[5];
10526 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
10527 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
10537 /* Routines for generating rtl */
10540 thumb_expand_movstrqi (operands
)
10543 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
10544 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
10545 HOST_WIDE_INT len
= INTVAL (operands
[2]);
10546 HOST_WIDE_INT offset
= 0;
10550 emit_insn (gen_movmem12b (out
, in
, out
, in
));
10556 emit_insn (gen_movmem8b (out
, in
, out
, in
));
10562 rtx reg
= gen_reg_rtx (SImode
);
10563 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
10564 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
10571 rtx reg
= gen_reg_rtx (HImode
);
10572 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
10573 plus_constant (in
, offset
))));
10574 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
10582 rtx reg
= gen_reg_rtx (QImode
);
10583 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
10584 plus_constant (in
, offset
))));
10585 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
10591 thumb_cmp_operand (op
, mode
)
10593 enum machine_mode mode
;
10595 return ((GET_CODE (op
) == CONST_INT
10596 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
10597 || register_operand (op
, mode
));
10600 static const char *
10601 thumb_condition_code (x
, invert
)
10605 static const char *const conds
[] =
10607 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10608 "hi", "ls", "ge", "lt", "gt", "le"
10612 switch (GET_CODE (x
))
10614 case EQ
: val
= 0; break;
10615 case NE
: val
= 1; break;
10616 case GEU
: val
= 2; break;
10617 case LTU
: val
= 3; break;
10618 case GTU
: val
= 8; break;
10619 case LEU
: val
= 9; break;
10620 case GE
: val
= 10; break;
10621 case LT
: val
= 11; break;
10622 case GT
: val
= 12; break;
10623 case LE
: val
= 13; break;
10628 return conds
[val
^ invert
];
10631 /* Handle storing a half-word to memory during reload. */
10633 thumb_reload_out_hi (operands
)
10636 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
10639 /* Handle storing a half-word to memory during reload. */
10641 thumb_reload_in_hi (operands
)
10642 rtx
* operands ATTRIBUTE_UNUSED
;
10647 /* Return the length of a function name prefix
10648 that starts with the character 'c'. */
10650 arm_get_strip_length (char c
)
10654 ARM_NAME_ENCODING_LENGTHS
10659 /* Return a pointer to a function's name with any
10660 and all prefix encodings stripped from it. */
10662 arm_strip_name_encoding (const char * name
)
10666 while ((skip
= arm_get_strip_length (* name
)))
10672 #ifdef AOF_ASSEMBLER
10673 /* Special functions only needed when producing AOF syntax assembler. */
10675 rtx aof_pic_label
= NULL_RTX
;
10678 struct pic_chain
* next
;
10682 static struct pic_chain
* aof_pic_chain
= NULL
;
10688 struct pic_chain
** chainp
;
10691 if (aof_pic_label
== NULL_RTX
)
10693 /* We mark this here and not in arm_add_gc_roots() to avoid
10694 polluting even more code with ifdefs, and because it never
10695 contains anything useful until we assign to it here. */
10696 ggc_add_rtx_root (&aof_pic_label
, 1);
10697 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
10700 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
10701 offset
+= 4, chainp
= &(*chainp
)->next
)
10702 if ((*chainp
)->symname
== XSTR (x
, 0))
10703 return plus_constant (aof_pic_label
, offset
);
10705 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
10706 (*chainp
)->next
= NULL
;
10707 (*chainp
)->symname
= XSTR (x
, 0);
10708 return plus_constant (aof_pic_label
, offset
);
10712 aof_dump_pic_table (f
)
10715 struct pic_chain
* chain
;
10717 if (aof_pic_chain
== NULL
)
10720 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
10721 PIC_OFFSET_TABLE_REGNUM
,
10722 PIC_OFFSET_TABLE_REGNUM
);
10723 fputs ("|x$adcons|\n", f
);
10725 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
10727 fputs ("\tDCD\t", f
);
10728 assemble_name (f
, chain
->symname
);
10733 int arm_text_section_count
= 1;
10736 aof_text_section ()
10738 static char buf
[100];
10739 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
10740 arm_text_section_count
++);
10742 strcat (buf
, ", PIC, REENTRANT");
10746 static int arm_data_section_count
= 1;
10749 aof_data_section ()
10751 static char buf
[100];
10752 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
10756 /* The AOF assembler is religiously strict about declarations of
10757 imported and exported symbols, so that it is impossible to declare
10758 a function as imported near the beginning of the file, and then to
10759 export it later on. It is, however, possible to delay the decision
10760 until all the functions in the file have been compiled. To get
10761 around this, we maintain a list of the imports and exports, and
10762 delete from it any that are subsequently defined. At the end of
10763 compilation we spit the remainder of the list out before the END
10768 struct import
* next
;
10772 static struct import
* imports_list
= NULL
;
10775 aof_add_import (name
)
10778 struct import
* new;
10780 for (new = imports_list
; new; new = new->next
)
10781 if (new->name
== name
)
10784 new = (struct import
*) xmalloc (sizeof (struct import
));
10785 new->next
= imports_list
;
10786 imports_list
= new;
10791 aof_delete_import (name
)
10794 struct import
** old
;
10796 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
10798 if ((*old
)->name
== name
)
10800 *old
= (*old
)->next
;
10806 int arm_main_function
= 0;
10809 aof_dump_imports (f
)
10812 /* The AOF assembler needs this to cause the startup code to be extracted
10813 from the library. Brining in __main causes the whole thing to work
10815 if (arm_main_function
)
10818 fputs ("\tIMPORT __main\n", f
);
10819 fputs ("\tDCD __main\n", f
);
10822 /* Now dump the remaining imports. */
10823 while (imports_list
)
10825 fprintf (f
, "\tIMPORT\t");
10826 assemble_name (f
, imports_list
->name
);
10828 imports_list
= imports_list
->next
;
10831 #endif /* AOF_ASSEMBLER */
10833 /* Switch to an arbitrary section NAME with attributes as specified
10834 by FLAGS. ALIGN specifies any known alignment requirements for
10835 the section; 0 if the default should be used.
10837 Differs from the default elf version only in the prefix character
10838 used before the section type. */
10841 arm_elf_asm_named_section (name
, flags
)
10843 unsigned int flags
;
10845 char flagchars
[8], *f
= flagchars
;
10848 if (!(flags
& SECTION_DEBUG
))
10850 if (flags
& SECTION_WRITE
)
10852 if (flags
& SECTION_CODE
)
10854 if (flags
& SECTION_SMALL
)
10856 if (flags
& SECTION_MERGE
)
10858 if (flags
& SECTION_STRINGS
)
10862 if (flags
& SECTION_BSS
)
10867 if (flags
& SECTION_ENTSIZE
)
10868 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",%%%s,%d\n",
10869 name
, flagchars
, type
, flags
& SECTION_ENTSIZE
);
10871 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",%%%s\n",
10872 name
, flagchars
, type
);