1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2016 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "stringpool.h"
39 #include "diagnostic-core.h"
40 #include "insn-attr.h"
43 #include "fold-const.h"
44 #include "stor-layout.h"
46 #include "print-tree.h"
52 #include "common/common-target.h"
53 #include "langhooks.h"
55 #include "sched-int.h"
57 #include "gimple-iterator.h"
58 #include "gimple-walk.h"
61 #include "tm-constrs.h"
62 #include "tree-vectorizer.h"
63 #include "target-globals.h"
66 #include "tree-pass.h"
68 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
71 #include "gstab.h" /* for N_SLINE */
73 #include "case-cfn-macros.h"
75 /* This file should be included last. */
76 #include "target-def.h"
78 #ifndef TARGET_NO_PROTOTYPE
79 #define TARGET_NO_PROTOTYPE 0
82 #define min(A,B) ((A) < (B) ? (A) : (B))
83 #define max(A,B) ((A) > (B) ? (A) : (B))
85 /* Structure used to define the rs6000 stack */
86 typedef struct rs6000_stack
{
87 int reload_completed
; /* stack info won't change from here on */
88 int first_gp_reg_save
; /* first callee saved GP register used */
89 int first_fp_reg_save
; /* first callee saved FP register used */
90 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
91 int lr_save_p
; /* true if the link reg needs to be saved */
92 int cr_save_p
; /* true if the CR reg needs to be saved */
93 unsigned int vrsave_mask
; /* mask of vec registers to save */
94 int push_p
; /* true if we need to allocate stack space */
95 int calls_p
; /* true if the function makes any calls */
96 int world_save_p
; /* true if we're saving *everything*:
97 r13-r31, cr, f14-f31, vrsave, v20-v31 */
98 enum rs6000_abi abi
; /* which ABI to use */
99 int gp_save_offset
; /* offset to save GP regs from initial SP */
100 int fp_save_offset
; /* offset to save FP regs from initial SP */
101 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
102 int lr_save_offset
; /* offset to save LR from initial SP */
103 int cr_save_offset
; /* offset to save CR from initial SP */
104 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
105 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
106 int varargs_save_offset
; /* offset to save the varargs registers */
107 int ehrd_offset
; /* offset to EH return data */
108 int ehcr_offset
; /* offset to EH CR field data */
109 int reg_size
; /* register size (4 or 8) */
110 HOST_WIDE_INT vars_size
; /* variable save area size */
111 int parm_size
; /* outgoing parameter size */
112 int save_size
; /* save area size */
113 int fixed_size
; /* fixed size of stack frame */
114 int gp_size
; /* size of saved GP registers */
115 int fp_size
; /* size of saved FP registers */
116 int altivec_size
; /* size of saved AltiVec registers */
117 int cr_size
; /* size to hold CR if not in fixed area */
118 int vrsave_size
; /* size to hold VRSAVE */
119 int altivec_padding_size
; /* size of altivec alignment padding */
120 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
121 int spe_padding_size
;
122 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
123 int spe_64bit_regs_used
;
127 /* A C structure for machine-specific, per-function data.
128 This is added to the cfun structure. */
129 typedef struct GTY(()) machine_function
131 /* Whether the instruction chain has been scanned already. */
132 int insn_chain_scanned_p
;
133 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
134 int ra_needs_full_frame
;
135 /* Flags if __builtin_return_address (0) was used. */
137 /* Cache lr_save_p after expansion of builtin_eh_return. */
139 /* Whether we need to save the TOC to the reserved stack location in the
140 function prologue. */
141 bool save_toc_in_prologue
;
142 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
143 varargs save area. */
144 HOST_WIDE_INT varargs_save_offset
;
145 /* Temporary stack slot to use for SDmode copies. This slot is
146 64-bits wide and is allocated early enough so that the offset
147 does not overflow the 16-bit load/store offset field. */
148 rtx sdmode_stack_slot
;
149 /* Alternative internal arg pointer for -fsplit-stack. */
150 rtx split_stack_arg_pointer
;
151 bool split_stack_argp_used
;
152 /* Flag if r2 setup is needed with ELFv2 ABI. */
153 bool r2_setup_needed
;
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load
;
159 /* Set to nonzero once AIX common-mode calls have been defined. */
160 static GTY(()) int common_mode_defined
;
162 /* Label number of label created for -mrelocatable, to call to so we can
163 get the address of the GOT section */
164 static int rs6000_pic_labelno
;
167 /* Counter for labels which are to be placed in .fixup. */
168 int fixuplabelno
= 0;
171 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
174 /* Specify the machine mode that pointers have. After generation of rtl, the
175 compiler makes no further distinction between pointers and any other objects
176 of this machine mode. The type is unsigned since not all things that
177 include rs6000.h also include machmode.h. */
178 unsigned rs6000_pmode
;
180 /* Width in bits of a pointer. */
181 unsigned rs6000_pointer_size
;
183 #ifdef HAVE_AS_GNU_ATTRIBUTE
184 /* Flag whether floating point values have been passed/returned. */
185 static bool rs6000_passes_float
;
186 /* Flag whether vector values have been passed/returned. */
187 static bool rs6000_passes_vector
;
188 /* Flag whether small (<= 8 byte) structures have been returned. */
189 static bool rs6000_returns_struct
;
192 /* Value is TRUE if register/mode pair is acceptable. */
193 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
195 /* Maximum number of registers needed for a given register class and mode. */
196 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
198 /* How many registers are needed for a given register and mode. */
199 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
201 /* Map register number to register class. */
202 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
204 static int dbg_cost_ctrl
;
206 /* Built in types. */
207 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
208 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
210 /* Flag to say the TOC is initialized */
212 char toc_label_name
[10];
214 /* Cached value of rs6000_variable_issue. This is cached in
215 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
216 static short cached_can_issue_more
;
218 static GTY(()) section
*read_only_data_section
;
219 static GTY(()) section
*private_data_section
;
220 static GTY(()) section
*tls_data_section
;
221 static GTY(()) section
*tls_private_data_section
;
222 static GTY(()) section
*read_only_private_data_section
;
223 static GTY(()) section
*sdata2_section
;
224 static GTY(()) section
*toc_section
;
226 struct builtin_description
228 const HOST_WIDE_INT mask
;
229 const enum insn_code icode
;
230 const char *const name
;
231 const enum rs6000_builtins code
;
234 /* Describe the vector unit used for modes. */
235 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
236 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
238 /* Register classes for various constraints that are based on the target
240 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
242 /* Describe the alignment of a vector. */
243 int rs6000_vector_align
[NUM_MACHINE_MODES
];
245 /* Map selected modes to types for builtins. */
246 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
248 /* What modes to automatically generate reciprocal divide estimate (fre) and
249 reciprocal sqrt (frsqrte) for. */
250 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
252 /* Masks to determine which reciprocal esitmate instructions to generate
254 enum rs6000_recip_mask
{
255 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
256 RECIP_DF_DIV
= 0x002,
257 RECIP_V4SF_DIV
= 0x004,
258 RECIP_V2DF_DIV
= 0x008,
260 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
261 RECIP_DF_RSQRT
= 0x020,
262 RECIP_V4SF_RSQRT
= 0x040,
263 RECIP_V2DF_RSQRT
= 0x080,
265 /* Various combination of flags for -mrecip=xxx. */
267 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
268 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
269 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
271 RECIP_HIGH_PRECISION
= RECIP_ALL
,
273 /* On low precision machines like the power5, don't enable double precision
274 reciprocal square root estimate, since it isn't accurate enough. */
275 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
278 /* -mrecip options. */
281 const char *string
; /* option name */
282 unsigned int mask
; /* mask bits to set */
283 } recip_options
[] = {
284 { "all", RECIP_ALL
},
285 { "none", RECIP_NONE
},
286 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
288 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
289 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
290 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
291 | RECIP_V2DF_RSQRT
) },
292 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
293 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
296 /* Pointer to function (in rs6000-c.c) that can define or undefine target
297 macros that have changed. Languages that don't support the preprocessor
298 don't link in rs6000-c.c, so we can't call it directly. */
299 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
301 /* Simplfy register classes into simpler classifications. We assume
302 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
303 check for standard register classes (gpr/floating/altivec/vsx) and
304 floating/vector classes (float/altivec/vsx). */
306 enum rs6000_reg_type
{
319 /* Map register class to register type. */
320 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
322 /* First/last register type for the 'normal' register types (i.e. general
323 purpose, floating point, altivec, and VSX registers). */
324 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
326 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
329 /* Register classes we care about in secondary reload or go if legitimate
330 address. We only need to worry about GPR, FPR, and Altivec registers here,
331 along an ANY field that is the OR of the 3 register classes. */
333 enum rs6000_reload_reg_type
{
334 RELOAD_REG_GPR
, /* General purpose registers. */
335 RELOAD_REG_FPR
, /* Traditional floating point regs. */
336 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
337 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
341 /* For setting up register classes, loop through the 3 register classes mapping
342 into real registers, and skip the ANY class, which is just an OR of the
344 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
345 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
347 /* Map reload register type to a register in the register class. */
348 struct reload_reg_map_type
{
349 const char *name
; /* Register class name. */
350 int reg
; /* Register in the register class. */
353 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
354 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
355 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
356 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
357 { "Any", -1 }, /* RELOAD_REG_ANY. */
360 /* Mask bits for each register class, indexed per mode. Historically the
361 compiler has been more restrictive which types can do PRE_MODIFY instead of
362 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
363 typedef unsigned char addr_mask_type
;
365 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
366 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
367 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
368 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
369 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
370 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
371 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
373 /* Register type masks based on the type, of valid addressing modes. */
374 struct rs6000_reg_addr
{
375 enum insn_code reload_load
; /* INSN to reload for loading. */
376 enum insn_code reload_store
; /* INSN to reload for storing. */
377 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
378 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
379 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
380 enum insn_code fusion_gpr_ld
; /* INSN for fusing gpr ADDIS/loads. */
381 /* INSNs for fusing addi with loads
382 or stores for each reg. class. */
383 enum insn_code fusion_addi_ld
[(int)N_RELOAD_REG
];
384 enum insn_code fusion_addi_st
[(int)N_RELOAD_REG
];
385 /* INSNs for fusing addis with loads
386 or stores for each reg. class. */
387 enum insn_code fusion_addis_ld
[(int)N_RELOAD_REG
];
388 enum insn_code fusion_addis_st
[(int)N_RELOAD_REG
];
389 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
390 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
391 bool fused_toc
; /* Mode supports TOC fusion. */
394 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
396 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
398 mode_supports_pre_incdec_p (machine_mode mode
)
400 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
404 /* Helper function to say whether a mode supports PRE_MODIFY. */
406 mode_supports_pre_modify_p (machine_mode mode
)
408 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
412 /* Return true if we have D-form addressing in altivec registers. */
414 mode_supports_vmx_dform (machine_mode mode
)
416 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_OFFSET
) != 0);
420 /* Target cpu costs. */
422 struct processor_costs
{
423 const int mulsi
; /* cost of SImode multiplication. */
424 const int mulsi_const
; /* cost of SImode multiplication by constant. */
425 const int mulsi_const9
; /* cost of SImode mult by short constant. */
426 const int muldi
; /* cost of DImode multiplication. */
427 const int divsi
; /* cost of SImode division. */
428 const int divdi
; /* cost of DImode division. */
429 const int fp
; /* cost of simple SFmode and DFmode insns. */
430 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
431 const int sdiv
; /* cost of SFmode division (fdivs). */
432 const int ddiv
; /* cost of DFmode division (fdiv). */
433 const int cache_line_size
; /* cache line size in bytes. */
434 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
435 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
436 const int simultaneous_prefetches
; /* number of parallel prefetch
438 const int sfdf_convert
; /* cost of SF->DF conversion. */
441 const struct processor_costs
*rs6000_cost
;
443 /* Processor costs (relative to an add) */
445 /* Instruction size costs on 32bit processors. */
447 struct processor_costs size32_cost
= {
448 COSTS_N_INSNS (1), /* mulsi */
449 COSTS_N_INSNS (1), /* mulsi_const */
450 COSTS_N_INSNS (1), /* mulsi_const9 */
451 COSTS_N_INSNS (1), /* muldi */
452 COSTS_N_INSNS (1), /* divsi */
453 COSTS_N_INSNS (1), /* divdi */
454 COSTS_N_INSNS (1), /* fp */
455 COSTS_N_INSNS (1), /* dmul */
456 COSTS_N_INSNS (1), /* sdiv */
457 COSTS_N_INSNS (1), /* ddiv */
458 32, /* cache line size */
462 0, /* SF->DF convert */
465 /* Instruction size costs on 64bit processors. */
467 struct processor_costs size64_cost
= {
468 COSTS_N_INSNS (1), /* mulsi */
469 COSTS_N_INSNS (1), /* mulsi_const */
470 COSTS_N_INSNS (1), /* mulsi_const9 */
471 COSTS_N_INSNS (1), /* muldi */
472 COSTS_N_INSNS (1), /* divsi */
473 COSTS_N_INSNS (1), /* divdi */
474 COSTS_N_INSNS (1), /* fp */
475 COSTS_N_INSNS (1), /* dmul */
476 COSTS_N_INSNS (1), /* sdiv */
477 COSTS_N_INSNS (1), /* ddiv */
478 128, /* cache line size */
482 0, /* SF->DF convert */
485 /* Instruction costs on RS64A processors. */
487 struct processor_costs rs64a_cost
= {
488 COSTS_N_INSNS (20), /* mulsi */
489 COSTS_N_INSNS (12), /* mulsi_const */
490 COSTS_N_INSNS (8), /* mulsi_const9 */
491 COSTS_N_INSNS (34), /* muldi */
492 COSTS_N_INSNS (65), /* divsi */
493 COSTS_N_INSNS (67), /* divdi */
494 COSTS_N_INSNS (4), /* fp */
495 COSTS_N_INSNS (4), /* dmul */
496 COSTS_N_INSNS (31), /* sdiv */
497 COSTS_N_INSNS (31), /* ddiv */
498 128, /* cache line size */
502 0, /* SF->DF convert */
505 /* Instruction costs on MPCCORE processors. */
507 struct processor_costs mpccore_cost
= {
508 COSTS_N_INSNS (2), /* mulsi */
509 COSTS_N_INSNS (2), /* mulsi_const */
510 COSTS_N_INSNS (2), /* mulsi_const9 */
511 COSTS_N_INSNS (2), /* muldi */
512 COSTS_N_INSNS (6), /* divsi */
513 COSTS_N_INSNS (6), /* divdi */
514 COSTS_N_INSNS (4), /* fp */
515 COSTS_N_INSNS (5), /* dmul */
516 COSTS_N_INSNS (10), /* sdiv */
517 COSTS_N_INSNS (17), /* ddiv */
518 32, /* cache line size */
522 0, /* SF->DF convert */
525 /* Instruction costs on PPC403 processors. */
527 struct processor_costs ppc403_cost
= {
528 COSTS_N_INSNS (4), /* mulsi */
529 COSTS_N_INSNS (4), /* mulsi_const */
530 COSTS_N_INSNS (4), /* mulsi_const9 */
531 COSTS_N_INSNS (4), /* muldi */
532 COSTS_N_INSNS (33), /* divsi */
533 COSTS_N_INSNS (33), /* divdi */
534 COSTS_N_INSNS (11), /* fp */
535 COSTS_N_INSNS (11), /* dmul */
536 COSTS_N_INSNS (11), /* sdiv */
537 COSTS_N_INSNS (11), /* ddiv */
538 32, /* cache line size */
542 0, /* SF->DF convert */
545 /* Instruction costs on PPC405 processors. */
547 struct processor_costs ppc405_cost
= {
548 COSTS_N_INSNS (5), /* mulsi */
549 COSTS_N_INSNS (4), /* mulsi_const */
550 COSTS_N_INSNS (3), /* mulsi_const9 */
551 COSTS_N_INSNS (5), /* muldi */
552 COSTS_N_INSNS (35), /* divsi */
553 COSTS_N_INSNS (35), /* divdi */
554 COSTS_N_INSNS (11), /* fp */
555 COSTS_N_INSNS (11), /* dmul */
556 COSTS_N_INSNS (11), /* sdiv */
557 COSTS_N_INSNS (11), /* ddiv */
558 32, /* cache line size */
562 0, /* SF->DF convert */
565 /* Instruction costs on PPC440 processors. */
567 struct processor_costs ppc440_cost
= {
568 COSTS_N_INSNS (3), /* mulsi */
569 COSTS_N_INSNS (2), /* mulsi_const */
570 COSTS_N_INSNS (2), /* mulsi_const9 */
571 COSTS_N_INSNS (3), /* muldi */
572 COSTS_N_INSNS (34), /* divsi */
573 COSTS_N_INSNS (34), /* divdi */
574 COSTS_N_INSNS (5), /* fp */
575 COSTS_N_INSNS (5), /* dmul */
576 COSTS_N_INSNS (19), /* sdiv */
577 COSTS_N_INSNS (33), /* ddiv */
578 32, /* cache line size */
582 0, /* SF->DF convert */
585 /* Instruction costs on PPC476 processors. */
587 struct processor_costs ppc476_cost
= {
588 COSTS_N_INSNS (4), /* mulsi */
589 COSTS_N_INSNS (4), /* mulsi_const */
590 COSTS_N_INSNS (4), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (11), /* divsi */
593 COSTS_N_INSNS (11), /* divdi */
594 COSTS_N_INSNS (6), /* fp */
595 COSTS_N_INSNS (6), /* dmul */
596 COSTS_N_INSNS (19), /* sdiv */
597 COSTS_N_INSNS (33), /* ddiv */
598 32, /* l1 cache line size */
602 0, /* SF->DF convert */
605 /* Instruction costs on PPC601 processors. */
607 struct processor_costs ppc601_cost
= {
608 COSTS_N_INSNS (5), /* mulsi */
609 COSTS_N_INSNS (5), /* mulsi_const */
610 COSTS_N_INSNS (5), /* mulsi_const9 */
611 COSTS_N_INSNS (5), /* muldi */
612 COSTS_N_INSNS (36), /* divsi */
613 COSTS_N_INSNS (36), /* divdi */
614 COSTS_N_INSNS (4), /* fp */
615 COSTS_N_INSNS (5), /* dmul */
616 COSTS_N_INSNS (17), /* sdiv */
617 COSTS_N_INSNS (31), /* ddiv */
618 32, /* cache line size */
622 0, /* SF->DF convert */
625 /* Instruction costs on PPC603 processors. */
627 struct processor_costs ppc603_cost
= {
628 COSTS_N_INSNS (5), /* mulsi */
629 COSTS_N_INSNS (3), /* mulsi_const */
630 COSTS_N_INSNS (2), /* mulsi_const9 */
631 COSTS_N_INSNS (5), /* muldi */
632 COSTS_N_INSNS (37), /* divsi */
633 COSTS_N_INSNS (37), /* divdi */
634 COSTS_N_INSNS (3), /* fp */
635 COSTS_N_INSNS (4), /* dmul */
636 COSTS_N_INSNS (18), /* sdiv */
637 COSTS_N_INSNS (33), /* ddiv */
638 32, /* cache line size */
642 0, /* SF->DF convert */
645 /* Instruction costs on PPC604 processors. */
647 struct processor_costs ppc604_cost
= {
648 COSTS_N_INSNS (4), /* mulsi */
649 COSTS_N_INSNS (4), /* mulsi_const */
650 COSTS_N_INSNS (4), /* mulsi_const9 */
651 COSTS_N_INSNS (4), /* muldi */
652 COSTS_N_INSNS (20), /* divsi */
653 COSTS_N_INSNS (20), /* divdi */
654 COSTS_N_INSNS (3), /* fp */
655 COSTS_N_INSNS (3), /* dmul */
656 COSTS_N_INSNS (18), /* sdiv */
657 COSTS_N_INSNS (32), /* ddiv */
658 32, /* cache line size */
662 0, /* SF->DF convert */
665 /* Instruction costs on PPC604e processors. */
667 struct processor_costs ppc604e_cost
= {
668 COSTS_N_INSNS (2), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (2), /* muldi */
672 COSTS_N_INSNS (20), /* divsi */
673 COSTS_N_INSNS (20), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (18), /* sdiv */
677 COSTS_N_INSNS (32), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction costs on PPC620 processors. */
687 struct processor_costs ppc620_cost
= {
688 COSTS_N_INSNS (5), /* mulsi */
689 COSTS_N_INSNS (4), /* mulsi_const */
690 COSTS_N_INSNS (3), /* mulsi_const9 */
691 COSTS_N_INSNS (7), /* muldi */
692 COSTS_N_INSNS (21), /* divsi */
693 COSTS_N_INSNS (37), /* divdi */
694 COSTS_N_INSNS (3), /* fp */
695 COSTS_N_INSNS (3), /* dmul */
696 COSTS_N_INSNS (18), /* sdiv */
697 COSTS_N_INSNS (32), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on PPC630 processors. */
707 struct processor_costs ppc630_cost
= {
708 COSTS_N_INSNS (5), /* mulsi */
709 COSTS_N_INSNS (4), /* mulsi_const */
710 COSTS_N_INSNS (3), /* mulsi_const9 */
711 COSTS_N_INSNS (7), /* muldi */
712 COSTS_N_INSNS (21), /* divsi */
713 COSTS_N_INSNS (37), /* divdi */
714 COSTS_N_INSNS (3), /* fp */
715 COSTS_N_INSNS (3), /* dmul */
716 COSTS_N_INSNS (17), /* sdiv */
717 COSTS_N_INSNS (21), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on Cell processor. */
726 /* COSTS_N_INSNS (1) ~ one add. */
728 struct processor_costs ppccell_cost
= {
729 COSTS_N_INSNS (9/2)+2, /* mulsi */
730 COSTS_N_INSNS (6/2), /* mulsi_const */
731 COSTS_N_INSNS (6/2), /* mulsi_const9 */
732 COSTS_N_INSNS (15/2)+2, /* muldi */
733 COSTS_N_INSNS (38/2), /* divsi */
734 COSTS_N_INSNS (70/2), /* divdi */
735 COSTS_N_INSNS (10/2), /* fp */
736 COSTS_N_INSNS (10/2), /* dmul */
737 COSTS_N_INSNS (74/2), /* sdiv */
738 COSTS_N_INSNS (74/2), /* ddiv */
739 128, /* cache line size */
743 0, /* SF->DF convert */
746 /* Instruction costs on PPC750 and PPC7400 processors. */
748 struct processor_costs ppc750_cost
= {
749 COSTS_N_INSNS (5), /* mulsi */
750 COSTS_N_INSNS (3), /* mulsi_const */
751 COSTS_N_INSNS (2), /* mulsi_const9 */
752 COSTS_N_INSNS (5), /* muldi */
753 COSTS_N_INSNS (17), /* divsi */
754 COSTS_N_INSNS (17), /* divdi */
755 COSTS_N_INSNS (3), /* fp */
756 COSTS_N_INSNS (3), /* dmul */
757 COSTS_N_INSNS (17), /* sdiv */
758 COSTS_N_INSNS (31), /* ddiv */
759 32, /* cache line size */
763 0, /* SF->DF convert */
766 /* Instruction costs on PPC7450 processors. */
768 struct processor_costs ppc7450_cost
= {
769 COSTS_N_INSNS (4), /* mulsi */
770 COSTS_N_INSNS (3), /* mulsi_const */
771 COSTS_N_INSNS (3), /* mulsi_const9 */
772 COSTS_N_INSNS (4), /* muldi */
773 COSTS_N_INSNS (23), /* divsi */
774 COSTS_N_INSNS (23), /* divdi */
775 COSTS_N_INSNS (5), /* fp */
776 COSTS_N_INSNS (5), /* dmul */
777 COSTS_N_INSNS (21), /* sdiv */
778 COSTS_N_INSNS (35), /* ddiv */
779 32, /* cache line size */
783 0, /* SF->DF convert */
786 /* Instruction costs on PPC8540 processors. */
788 struct processor_costs ppc8540_cost
= {
789 COSTS_N_INSNS (4), /* mulsi */
790 COSTS_N_INSNS (4), /* mulsi_const */
791 COSTS_N_INSNS (4), /* mulsi_const9 */
792 COSTS_N_INSNS (4), /* muldi */
793 COSTS_N_INSNS (19), /* divsi */
794 COSTS_N_INSNS (19), /* divdi */
795 COSTS_N_INSNS (4), /* fp */
796 COSTS_N_INSNS (4), /* dmul */
797 COSTS_N_INSNS (29), /* sdiv */
798 COSTS_N_INSNS (29), /* ddiv */
799 32, /* cache line size */
802 1, /* prefetch streams /*/
803 0, /* SF->DF convert */
806 /* Instruction costs on E300C2 and E300C3 cores. */
808 struct processor_costs ppce300c2c3_cost
= {
809 COSTS_N_INSNS (4), /* mulsi */
810 COSTS_N_INSNS (4), /* mulsi_const */
811 COSTS_N_INSNS (4), /* mulsi_const9 */
812 COSTS_N_INSNS (4), /* muldi */
813 COSTS_N_INSNS (19), /* divsi */
814 COSTS_N_INSNS (19), /* divdi */
815 COSTS_N_INSNS (3), /* fp */
816 COSTS_N_INSNS (4), /* dmul */
817 COSTS_N_INSNS (18), /* sdiv */
818 COSTS_N_INSNS (33), /* ddiv */
822 1, /* prefetch streams /*/
823 0, /* SF->DF convert */
826 /* Instruction costs on PPCE500MC processors. */
828 struct processor_costs ppce500mc_cost
= {
829 COSTS_N_INSNS (4), /* mulsi */
830 COSTS_N_INSNS (4), /* mulsi_const */
831 COSTS_N_INSNS (4), /* mulsi_const9 */
832 COSTS_N_INSNS (4), /* muldi */
833 COSTS_N_INSNS (14), /* divsi */
834 COSTS_N_INSNS (14), /* divdi */
835 COSTS_N_INSNS (8), /* fp */
836 COSTS_N_INSNS (10), /* dmul */
837 COSTS_N_INSNS (36), /* sdiv */
838 COSTS_N_INSNS (66), /* ddiv */
839 64, /* cache line size */
842 1, /* prefetch streams /*/
843 0, /* SF->DF convert */
846 /* Instruction costs on PPCE500MC64 processors. */
848 struct processor_costs ppce500mc64_cost
= {
849 COSTS_N_INSNS (4), /* mulsi */
850 COSTS_N_INSNS (4), /* mulsi_const */
851 COSTS_N_INSNS (4), /* mulsi_const9 */
852 COSTS_N_INSNS (4), /* muldi */
853 COSTS_N_INSNS (14), /* divsi */
854 COSTS_N_INSNS (14), /* divdi */
855 COSTS_N_INSNS (4), /* fp */
856 COSTS_N_INSNS (10), /* dmul */
857 COSTS_N_INSNS (36), /* sdiv */
858 COSTS_N_INSNS (66), /* ddiv */
859 64, /* cache line size */
862 1, /* prefetch streams /*/
863 0, /* SF->DF convert */
866 /* Instruction costs on PPCE5500 processors. */
868 struct processor_costs ppce5500_cost
= {
869 COSTS_N_INSNS (5), /* mulsi */
870 COSTS_N_INSNS (5), /* mulsi_const */
871 COSTS_N_INSNS (4), /* mulsi_const9 */
872 COSTS_N_INSNS (5), /* muldi */
873 COSTS_N_INSNS (14), /* divsi */
874 COSTS_N_INSNS (14), /* divdi */
875 COSTS_N_INSNS (7), /* fp */
876 COSTS_N_INSNS (10), /* dmul */
877 COSTS_N_INSNS (36), /* sdiv */
878 COSTS_N_INSNS (66), /* ddiv */
879 64, /* cache line size */
882 1, /* prefetch streams /*/
883 0, /* SF->DF convert */
886 /* Instruction costs on PPCE6500 processors. */
888 struct processor_costs ppce6500_cost
= {
889 COSTS_N_INSNS (5), /* mulsi */
890 COSTS_N_INSNS (5), /* mulsi_const */
891 COSTS_N_INSNS (4), /* mulsi_const9 */
892 COSTS_N_INSNS (5), /* muldi */
893 COSTS_N_INSNS (14), /* divsi */
894 COSTS_N_INSNS (14), /* divdi */
895 COSTS_N_INSNS (7), /* fp */
896 COSTS_N_INSNS (10), /* dmul */
897 COSTS_N_INSNS (36), /* sdiv */
898 COSTS_N_INSNS (66), /* ddiv */
899 64, /* cache line size */
902 1, /* prefetch streams /*/
903 0, /* SF->DF convert */
906 /* Instruction costs on AppliedMicro Titan processors. */
908 struct processor_costs titan_cost
= {
909 COSTS_N_INSNS (5), /* mulsi */
910 COSTS_N_INSNS (5), /* mulsi_const */
911 COSTS_N_INSNS (5), /* mulsi_const9 */
912 COSTS_N_INSNS (5), /* muldi */
913 COSTS_N_INSNS (18), /* divsi */
914 COSTS_N_INSNS (18), /* divdi */
915 COSTS_N_INSNS (10), /* fp */
916 COSTS_N_INSNS (10), /* dmul */
917 COSTS_N_INSNS (46), /* sdiv */
918 COSTS_N_INSNS (72), /* ddiv */
919 32, /* cache line size */
922 1, /* prefetch streams /*/
923 0, /* SF->DF convert */
926 /* Instruction costs on POWER4 and POWER5 processors. */
928 struct processor_costs power4_cost
= {
929 COSTS_N_INSNS (3), /* mulsi */
930 COSTS_N_INSNS (2), /* mulsi_const */
931 COSTS_N_INSNS (2), /* mulsi_const9 */
932 COSTS_N_INSNS (4), /* muldi */
933 COSTS_N_INSNS (18), /* divsi */
934 COSTS_N_INSNS (34), /* divdi */
935 COSTS_N_INSNS (3), /* fp */
936 COSTS_N_INSNS (3), /* dmul */
937 COSTS_N_INSNS (17), /* sdiv */
938 COSTS_N_INSNS (17), /* ddiv */
939 128, /* cache line size */
942 8, /* prefetch streams /*/
943 0, /* SF->DF convert */
946 /* Instruction costs on POWER6 processors. */
948 struct processor_costs power6_cost
= {
949 COSTS_N_INSNS (8), /* mulsi */
950 COSTS_N_INSNS (8), /* mulsi_const */
951 COSTS_N_INSNS (8), /* mulsi_const9 */
952 COSTS_N_INSNS (8), /* muldi */
953 COSTS_N_INSNS (22), /* divsi */
954 COSTS_N_INSNS (28), /* divdi */
955 COSTS_N_INSNS (3), /* fp */
956 COSTS_N_INSNS (3), /* dmul */
957 COSTS_N_INSNS (13), /* sdiv */
958 COSTS_N_INSNS (16), /* ddiv */
959 128, /* cache line size */
962 16, /* prefetch streams */
963 0, /* SF->DF convert */
966 /* Instruction costs on POWER7 processors. */
968 struct processor_costs power7_cost
= {
969 COSTS_N_INSNS (2), /* mulsi */
970 COSTS_N_INSNS (2), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (2), /* muldi */
973 COSTS_N_INSNS (18), /* divsi */
974 COSTS_N_INSNS (34), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (13), /* sdiv */
978 COSTS_N_INSNS (16), /* ddiv */
979 128, /* cache line size */
982 12, /* prefetch streams */
983 COSTS_N_INSNS (3), /* SF->DF convert */
986 /* Instruction costs on POWER8 processors. */
988 struct processor_costs power8_cost
= {
989 COSTS_N_INSNS (3), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (3), /* muldi */
993 COSTS_N_INSNS (19), /* divsi */
994 COSTS_N_INSNS (35), /* divdi */
995 COSTS_N_INSNS (3), /* fp */
996 COSTS_N_INSNS (3), /* dmul */
997 COSTS_N_INSNS (14), /* sdiv */
998 COSTS_N_INSNS (17), /* ddiv */
999 128, /* cache line size */
1002 12, /* prefetch streams */
1003 COSTS_N_INSNS (3), /* SF->DF convert */
1006 /* Instruction costs on POWER9 processors. */
1008 struct processor_costs power9_cost
= {
1009 COSTS_N_INSNS (3), /* mulsi */
1010 COSTS_N_INSNS (3), /* mulsi_const */
1011 COSTS_N_INSNS (3), /* mulsi_const9 */
1012 COSTS_N_INSNS (3), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (35), /* divdi */
1015 COSTS_N_INSNS (3), /* fp */
1016 COSTS_N_INSNS (3), /* dmul */
1017 COSTS_N_INSNS (14), /* sdiv */
1018 COSTS_N_INSNS (17), /* ddiv */
1019 128, /* cache line size */
1022 12, /* prefetch streams */
1023 COSTS_N_INSNS (3), /* SF->DF convert */
1026 /* Instruction costs on POWER A2 processors. */
1028 struct processor_costs ppca2_cost
= {
1029 COSTS_N_INSNS (16), /* mulsi */
1030 COSTS_N_INSNS (16), /* mulsi_const */
1031 COSTS_N_INSNS (16), /* mulsi_const9 */
1032 COSTS_N_INSNS (16), /* muldi */
1033 COSTS_N_INSNS (22), /* divsi */
1034 COSTS_N_INSNS (28), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (3), /* dmul */
1037 COSTS_N_INSNS (59), /* sdiv */
1038 COSTS_N_INSNS (72), /* ddiv */
1041 2048, /* l2 cache */
1042 16, /* prefetch streams */
1043 0, /* SF->DF convert */
1047 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1048 #undef RS6000_BUILTIN_1
1049 #undef RS6000_BUILTIN_2
1050 #undef RS6000_BUILTIN_3
1051 #undef RS6000_BUILTIN_A
1052 #undef RS6000_BUILTIN_D
1053 #undef RS6000_BUILTIN_E
1054 #undef RS6000_BUILTIN_H
1055 #undef RS6000_BUILTIN_P
1056 #undef RS6000_BUILTIN_Q
1057 #undef RS6000_BUILTIN_S
1058 #undef RS6000_BUILTIN_X
1060 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1061 { NAME, ICODE, MASK, ATTR },
1063 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1064 { NAME, ICODE, MASK, ATTR },
1066 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1067 { NAME, ICODE, MASK, ATTR },
1069 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1070 { NAME, ICODE, MASK, ATTR },
1072 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1073 { NAME, ICODE, MASK, ATTR },
1075 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1076 { NAME, ICODE, MASK, ATTR },
1078 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1079 { NAME, ICODE, MASK, ATTR },
1081 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1082 { NAME, ICODE, MASK, ATTR },
1084 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1085 { NAME, ICODE, MASK, ATTR },
1087 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1088 { NAME, ICODE, MASK, ATTR },
1090 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1091 { NAME, ICODE, MASK, ATTR },
1093 struct rs6000_builtin_info_type
{
1095 const enum insn_code icode
;
1096 const HOST_WIDE_INT mask
;
1097 const unsigned attr
;
1100 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1102 #include "rs6000-builtin.def"
1105 #undef RS6000_BUILTIN_1
1106 #undef RS6000_BUILTIN_2
1107 #undef RS6000_BUILTIN_3
1108 #undef RS6000_BUILTIN_A
1109 #undef RS6000_BUILTIN_D
1110 #undef RS6000_BUILTIN_E
1111 #undef RS6000_BUILTIN_H
1112 #undef RS6000_BUILTIN_P
1113 #undef RS6000_BUILTIN_Q
1114 #undef RS6000_BUILTIN_S
1115 #undef RS6000_BUILTIN_X
1117 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1118 static tree (*rs6000_veclib_handler
) (combined_fn
, tree
, tree
);
1121 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1122 static bool spe_func_has_64bit_regs_p (void);
1123 static struct machine_function
* rs6000_init_machine_status (void);
1124 static int rs6000_ra_ever_killed (void);
1125 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1126 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1127 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1128 static tree
rs6000_builtin_vectorized_libmass (combined_fn
, tree
, tree
);
1129 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1130 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1131 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1132 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1134 static int rs6000_debug_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
1135 static bool is_microcoded_insn (rtx_insn
*);
1136 static bool is_nonpipeline_insn (rtx_insn
*);
1137 static bool is_cracked_insn (rtx_insn
*);
1138 static bool is_load_insn (rtx
, rtx
*);
1139 static bool is_store_insn (rtx
, rtx
*);
1140 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1141 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1142 static bool insn_must_be_first_in_group (rtx_insn
*);
1143 static bool insn_must_be_last_in_group (rtx_insn
*);
1144 static void altivec_init_builtins (void);
1145 static tree
builtin_function_type (machine_mode
, machine_mode
,
1146 machine_mode
, machine_mode
,
1147 enum rs6000_builtins
, const char *name
);
1148 static void rs6000_common_init_builtins (void);
1149 static void paired_init_builtins (void);
1150 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1151 static void spe_init_builtins (void);
1152 static void htm_init_builtins (void);
1153 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1154 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1155 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1156 static rs6000_stack_t
*rs6000_stack_info (void);
1157 static void is_altivec_return_reg (rtx
, void *);
1158 int easy_vector_constant (rtx
, machine_mode
);
1159 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1160 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1161 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1164 static void macho_branch_islands (void);
1166 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1168 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1170 static bool rs6000_mode_dependent_address (const_rtx
);
1171 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1172 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1174 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1177 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1178 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1180 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1182 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1185 static bool rs6000_cannot_change_mode_class (machine_mode
,
1188 static bool rs6000_debug_cannot_change_mode_class (machine_mode
,
1191 static bool rs6000_save_toc_in_prologue_p (void);
1192 static rtx
rs6000_internal_arg_pointer (void);
1194 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1196 = rs6000_legitimize_reload_address
;
1198 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1199 = rs6000_mode_dependent_address
;
1201 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1203 = rs6000_secondary_reload_class
;
1205 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1206 = rs6000_preferred_reload_class
;
1208 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1210 = rs6000_secondary_memory_needed
;
1212 bool (*rs6000_cannot_change_mode_class_ptr
) (machine_mode
,
1215 = rs6000_cannot_change_mode_class
;
1217 const int INSN_NOT_AVAILABLE
= -1;
1219 static void rs6000_print_isa_options (FILE *, int, const char *,
1221 static void rs6000_print_builtin_options (FILE *, int, const char *,
1224 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1225 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1226 enum rs6000_reg_type
,
1228 secondary_reload_info
*,
1230 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1232 /* Hash table stuff for keeping track of TOC entries. */
1234 struct GTY((for_user
)) toc_hash_struct
1236 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1237 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1239 machine_mode key_mode
;
1243 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1245 static hashval_t
hash (toc_hash_struct
*);
1246 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1249 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1251 /* Hash table to keep track of the argument types for builtin functions. */
1253 struct GTY((for_user
)) builtin_hash_struct
1256 machine_mode mode
[4]; /* return value + 3 arguments. */
1257 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1260 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1262 static hashval_t
hash (builtin_hash_struct
*);
1263 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1266 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1269 /* Default register names. */
1270 char rs6000_reg_names
[][8] =
1272 "0", "1", "2", "3", "4", "5", "6", "7",
1273 "8", "9", "10", "11", "12", "13", "14", "15",
1274 "16", "17", "18", "19", "20", "21", "22", "23",
1275 "24", "25", "26", "27", "28", "29", "30", "31",
1276 "0", "1", "2", "3", "4", "5", "6", "7",
1277 "8", "9", "10", "11", "12", "13", "14", "15",
1278 "16", "17", "18", "19", "20", "21", "22", "23",
1279 "24", "25", "26", "27", "28", "29", "30", "31",
1280 "mq", "lr", "ctr","ap",
1281 "0", "1", "2", "3", "4", "5", "6", "7",
1283 /* AltiVec registers. */
1284 "0", "1", "2", "3", "4", "5", "6", "7",
1285 "8", "9", "10", "11", "12", "13", "14", "15",
1286 "16", "17", "18", "19", "20", "21", "22", "23",
1287 "24", "25", "26", "27", "28", "29", "30", "31",
1289 /* SPE registers. */
1290 "spe_acc", "spefscr",
1291 /* Soft frame pointer. */
1293 /* HTM SPR registers. */
1294 "tfhar", "tfiar", "texasr",
1295 /* SPE High registers. */
1296 "0", "1", "2", "3", "4", "5", "6", "7",
1297 "8", "9", "10", "11", "12", "13", "14", "15",
1298 "16", "17", "18", "19", "20", "21", "22", "23",
1299 "24", "25", "26", "27", "28", "29", "30", "31"
1302 #ifdef TARGET_REGNAMES
1303 static const char alt_reg_names
[][8] =
1305 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1306 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1307 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1308 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1309 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1310 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1311 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1312 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1313 "mq", "lr", "ctr", "ap",
1314 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1316 /* AltiVec registers. */
1317 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1318 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1319 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1320 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1322 /* SPE registers. */
1323 "spe_acc", "spefscr",
1324 /* Soft frame pointer. */
1326 /* HTM SPR registers. */
1327 "tfhar", "tfiar", "texasr",
1328 /* SPE High registers. */
1329 "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
1330 "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
1331 "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
1332 "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
1336 /* Table of valid machine attributes. */
1338 static const struct attribute_spec rs6000_attribute_table
[] =
1340 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1341 affects_type_identity } */
1342 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1344 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1346 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1348 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1350 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1352 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1353 SUBTARGET_ATTRIBUTE_TABLE
,
1355 { NULL
, 0, 0, false, false, false, NULL
, false }
1358 #ifndef TARGET_PROFILE_KERNEL
1359 #define TARGET_PROFILE_KERNEL 0
1362 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1363 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1365 /* Initialize the GCC target structure. */
1366 #undef TARGET_ATTRIBUTE_TABLE
1367 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1368 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1369 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1370 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1371 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1373 #undef TARGET_ASM_ALIGNED_DI_OP
1374 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1376 /* Default unaligned ops are only provided for ELF. Find the ops needed
1377 for non-ELF systems. */
1378 #ifndef OBJECT_FORMAT_ELF
1380 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1382 #undef TARGET_ASM_UNALIGNED_HI_OP
1383 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1384 #undef TARGET_ASM_UNALIGNED_SI_OP
1385 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1386 #undef TARGET_ASM_UNALIGNED_DI_OP
1387 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1390 #undef TARGET_ASM_UNALIGNED_HI_OP
1391 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1392 #undef TARGET_ASM_UNALIGNED_SI_OP
1393 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1394 #undef TARGET_ASM_UNALIGNED_DI_OP
1395 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1396 #undef TARGET_ASM_ALIGNED_DI_OP
1397 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1401 /* This hook deals with fixups for relocatable code and DI-mode objects
1403 #undef TARGET_ASM_INTEGER
1404 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1406 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1407 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1408 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1411 #undef TARGET_SET_UP_BY_PROLOGUE
1412 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1414 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1415 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1417 #undef TARGET_INTERNAL_ARG_POINTER
1418 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1420 #undef TARGET_HAVE_TLS
1421 #define TARGET_HAVE_TLS HAVE_AS_TLS
1423 #undef TARGET_CANNOT_FORCE_CONST_MEM
1424 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1426 #undef TARGET_DELEGITIMIZE_ADDRESS
1427 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1429 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1430 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1432 #undef TARGET_ASM_FUNCTION_PROLOGUE
1433 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1434 #undef TARGET_ASM_FUNCTION_EPILOGUE
1435 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1437 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1438 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1440 #undef TARGET_LEGITIMIZE_ADDRESS
1441 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1443 #undef TARGET_SCHED_VARIABLE_ISSUE
1444 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1446 #undef TARGET_SCHED_ISSUE_RATE
1447 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1448 #undef TARGET_SCHED_ADJUST_COST
1449 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1450 #undef TARGET_SCHED_ADJUST_PRIORITY
1451 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1452 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1453 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1454 #undef TARGET_SCHED_INIT
1455 #define TARGET_SCHED_INIT rs6000_sched_init
1456 #undef TARGET_SCHED_FINISH
1457 #define TARGET_SCHED_FINISH rs6000_sched_finish
1458 #undef TARGET_SCHED_REORDER
1459 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1460 #undef TARGET_SCHED_REORDER2
1461 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1463 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1464 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1466 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1467 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1469 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1470 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1471 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1472 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1473 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1474 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1475 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1476 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1478 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1479 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1480 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1481 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1482 rs6000_builtin_support_vector_misalignment
1483 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1484 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1485 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1486 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1487 rs6000_builtin_vectorization_cost
1488 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1489 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1490 rs6000_preferred_simd_mode
1491 #undef TARGET_VECTORIZE_INIT_COST
1492 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1493 #undef TARGET_VECTORIZE_ADD_STMT_COST
1494 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1495 #undef TARGET_VECTORIZE_FINISH_COST
1496 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1497 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1498 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1500 #undef TARGET_INIT_BUILTINS
1501 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1502 #undef TARGET_BUILTIN_DECL
1503 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1505 #undef TARGET_EXPAND_BUILTIN
1506 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1508 #undef TARGET_MANGLE_TYPE
1509 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1511 #undef TARGET_INIT_LIBFUNCS
1512 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1515 #undef TARGET_BINDS_LOCAL_P
1516 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1519 #undef TARGET_MS_BITFIELD_LAYOUT_P
1520 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1522 #undef TARGET_ASM_OUTPUT_MI_THUNK
1523 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1525 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1526 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1528 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1529 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1531 #undef TARGET_REGISTER_MOVE_COST
1532 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1533 #undef TARGET_MEMORY_MOVE_COST
1534 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1535 #undef TARGET_CANNOT_COPY_INSN_P
1536 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1537 #undef TARGET_RTX_COSTS
1538 #define TARGET_RTX_COSTS rs6000_rtx_costs
1539 #undef TARGET_ADDRESS_COST
1540 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1542 #undef TARGET_DWARF_REGISTER_SPAN
1543 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1545 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1546 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1548 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1549 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1551 #undef TARGET_PROMOTE_FUNCTION_MODE
1552 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1554 #undef TARGET_RETURN_IN_MEMORY
1555 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1557 #undef TARGET_RETURN_IN_MSB
1558 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1560 #undef TARGET_SETUP_INCOMING_VARARGS
1561 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1563 /* Always strict argument naming on rs6000. */
1564 #undef TARGET_STRICT_ARGUMENT_NAMING
1565 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1566 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1567 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1568 #undef TARGET_SPLIT_COMPLEX_ARG
1569 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1570 #undef TARGET_MUST_PASS_IN_STACK
1571 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1572 #undef TARGET_PASS_BY_REFERENCE
1573 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1574 #undef TARGET_ARG_PARTIAL_BYTES
1575 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1576 #undef TARGET_FUNCTION_ARG_ADVANCE
1577 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1578 #undef TARGET_FUNCTION_ARG
1579 #define TARGET_FUNCTION_ARG rs6000_function_arg
1580 #undef TARGET_FUNCTION_ARG_BOUNDARY
1581 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1583 #undef TARGET_BUILD_BUILTIN_VA_LIST
1584 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1586 #undef TARGET_EXPAND_BUILTIN_VA_START
1587 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1589 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1590 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1592 #undef TARGET_EH_RETURN_FILTER_MODE
1593 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1595 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1596 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1598 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1599 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1601 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1602 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1604 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1605 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1607 #undef TARGET_MD_ASM_ADJUST
1608 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1610 #undef TARGET_OPTION_OVERRIDE
1611 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1613 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1614 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1615 rs6000_builtin_vectorized_function
1617 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1618 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1619 rs6000_builtin_md_vectorized_function
1622 #undef TARGET_STACK_PROTECT_FAIL
1623 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1627 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1628 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1631 /* Use a 32-bit anchor range. This leads to sequences like:
1633 addis tmp,anchor,high
1636 where tmp itself acts as an anchor, and can be shared between
1637 accesses to the same 64k page. */
1638 #undef TARGET_MIN_ANCHOR_OFFSET
1639 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1640 #undef TARGET_MAX_ANCHOR_OFFSET
1641 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1642 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1643 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1644 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1645 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1647 #undef TARGET_BUILTIN_RECIPROCAL
1648 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1650 #undef TARGET_EXPAND_TO_RTL_HOOK
1651 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1653 #undef TARGET_INSTANTIATE_DECLS
1654 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1656 #undef TARGET_SECONDARY_RELOAD
1657 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1659 #undef TARGET_LEGITIMATE_ADDRESS_P
1660 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1662 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1663 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1666 #define TARGET_LRA_P rs6000_lra_p
1668 #undef TARGET_CAN_ELIMINATE
1669 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1671 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1672 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1674 #undef TARGET_TRAMPOLINE_INIT
1675 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1677 #undef TARGET_FUNCTION_VALUE
1678 #define TARGET_FUNCTION_VALUE rs6000_function_value
1680 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1681 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1683 #undef TARGET_OPTION_SAVE
1684 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1686 #undef TARGET_OPTION_RESTORE
1687 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1689 #undef TARGET_OPTION_PRINT
1690 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1692 #undef TARGET_CAN_INLINE_P
1693 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1695 #undef TARGET_SET_CURRENT_FUNCTION
1696 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1698 #undef TARGET_LEGITIMATE_CONSTANT_P
1699 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1701 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1702 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1704 #undef TARGET_CAN_USE_DOLOOP_P
1705 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1707 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1708 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1710 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1711 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1712 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1713 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1714 #undef TARGET_UNWIND_WORD_MODE
1715 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1717 #undef TARGET_OFFLOAD_OPTIONS
1718 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1720 #undef TARGET_C_MODE_FOR_SUFFIX
1721 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1723 #undef TARGET_INVALID_BINARY_OP
1724 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1726 #undef TARGET_OPTAB_SUPPORTED_P
1727 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1730 /* Processor table. */
1733 const char *const name
; /* Canonical processor name. */
1734 const enum processor_type processor
; /* Processor type enum value. */
1735 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1738 static struct rs6000_ptt
const processor_target_table
[] =
1740 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1741 #include "rs6000-cpus.def"
1745 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1749 rs6000_cpu_name_lookup (const char *name
)
1755 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1756 if (! strcmp (name
, processor_target_table
[i
].name
))
1764 /* Return number of consecutive hard regs needed starting at reg REGNO
1765 to hold something of mode MODE.
1766 This is ordinarily the length in words of a value of mode MODE
1767 but can be less for certain modes in special long registers.
1769 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1770 scalar instructions. The upper 32 bits are only available to the
1773 POWER and PowerPC GPRs hold 32 bits worth;
1774 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1777 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
1779 unsigned HOST_WIDE_INT reg_size
;
1781 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
1782 128-bit floating point that can go in vector registers, which has VSX
1783 memory addressing. */
1784 if (FP_REGNO_P (regno
))
1785 reg_size
= (VECTOR_MEM_VSX_P (mode
)
1786 ? UNITS_PER_VSX_WORD
1787 : UNITS_PER_FP_WORD
);
1789 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1790 reg_size
= UNITS_PER_SPE_WORD
;
1792 else if (ALTIVEC_REGNO_P (regno
))
1793 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1795 /* The value returned for SCmode in the E500 double case is 2 for
1796 ABI compatibility; storing an SCmode value in a single register
1797 would require function_arg and rs6000_spe_function_arg to handle
1798 SCmode so as to pass the value correctly in a pair of
1800 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1801 && !DECIMAL_FLOAT_MODE_P (mode
) && SPE_SIMD_REGNO_P (regno
))
1802 reg_size
= UNITS_PER_FP_WORD
;
1805 reg_size
= UNITS_PER_WORD
;
1807 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1810 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1813 rs6000_hard_regno_mode_ok (int regno
, machine_mode mode
)
1815 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1817 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1818 register combinations, and use PTImode where we need to deal with quad
1819 word memory operations. Don't allow quad words in the argument or frame
1820 pointer registers, just registers 0..31. */
1821 if (mode
== PTImode
)
1822 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1823 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1824 && ((regno
& 1) == 0));
1826 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1827 implementations. Don't allow an item to be split between a FP register
1828 and an Altivec register. Allow TImode in all VSX registers if the user
1830 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1831 && (VECTOR_MEM_VSX_P (mode
)
1832 || FLOAT128_VECTOR_P (mode
)
1833 || reg_addr
[mode
].scalar_in_vmx_p
1834 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1835 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1837 if (FP_REGNO_P (regno
))
1838 return FP_REGNO_P (last_regno
);
1840 if (ALTIVEC_REGNO_P (regno
))
1842 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
1845 return ALTIVEC_REGNO_P (last_regno
);
1849 /* The GPRs can hold any mode, but values bigger than one register
1850 cannot go past R31. */
1851 if (INT_REGNO_P (regno
))
1852 return INT_REGNO_P (last_regno
);
1854 /* The float registers (except for VSX vector modes) can only hold floating
1855 modes and DImode. */
1856 if (FP_REGNO_P (regno
))
1858 if (FLOAT128_VECTOR_P (mode
))
1861 if (SCALAR_FLOAT_MODE_P (mode
)
1862 && (mode
!= TDmode
|| (regno
% 2) == 0)
1863 && FP_REGNO_P (last_regno
))
1866 if (GET_MODE_CLASS (mode
) == MODE_INT
1867 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1870 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1871 && PAIRED_VECTOR_MODE (mode
))
1877 /* The CR register can only hold CC modes. */
1878 if (CR_REGNO_P (regno
))
1879 return GET_MODE_CLASS (mode
) == MODE_CC
;
1881 if (CA_REGNO_P (regno
))
1882 return mode
== Pmode
|| mode
== SImode
;
1884 /* AltiVec only in AldyVec registers. */
1885 if (ALTIVEC_REGNO_P (regno
))
1886 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1887 || mode
== V1TImode
);
1889 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1890 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1893 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1894 and it must be able to fit within the register set. */
1896 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1899 /* Print interesting facts about registers. */
1901 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1905 for (r
= first_regno
; r
<= last_regno
; ++r
)
1907 const char *comma
= "";
1910 if (first_regno
== last_regno
)
1911 fprintf (stderr
, "%s:\t", reg_name
);
1913 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1916 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1917 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1921 fprintf (stderr
, ",\n\t");
1926 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1927 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1928 rs6000_hard_regno_nregs
[m
][r
]);
1930 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1935 if (call_used_regs
[r
])
1939 fprintf (stderr
, ",\n\t");
1944 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1952 fprintf (stderr
, ",\n\t");
1957 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1963 fprintf (stderr
, ",\n\t");
1967 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1968 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1973 fprintf (stderr
, ",\n\t");
1977 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1982 rs6000_debug_vector_unit (enum rs6000_vector v
)
1988 case VECTOR_NONE
: ret
= "none"; break;
1989 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1990 case VECTOR_VSX
: ret
= "vsx"; break;
1991 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1992 case VECTOR_PAIRED
: ret
= "paired"; break;
1993 case VECTOR_SPE
: ret
= "spe"; break;
1994 case VECTOR_OTHER
: ret
= "other"; break;
1995 default: ret
= "unknown"; break;
2001 /* Inner function printing just the address mask for a particular reload
2003 DEBUG_FUNCTION
char *
2004 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
2009 if ((mask
& RELOAD_REG_VALID
) != 0)
2011 else if (keep_spaces
)
2014 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
2016 else if (keep_spaces
)
2019 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2021 else if (keep_spaces
)
2024 if ((mask
& RELOAD_REG_OFFSET
) != 0)
2026 else if (keep_spaces
)
2029 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2031 else if (keep_spaces
)
2034 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2036 else if (keep_spaces
)
2039 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2041 else if (keep_spaces
)
2049 /* Print the address masks in a human readble fashion. */
2051 rs6000_debug_print_mode (ssize_t m
)
2057 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2058 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2059 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2060 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2062 if ((reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2063 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
2064 fprintf (stderr
, " Reload=%c%c",
2065 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2066 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
2068 spaces
+= sizeof (" Reload=sl") - 1;
2070 if (reg_addr
[m
].scalar_in_vmx_p
)
2072 fprintf (stderr
, "%*s Upper=y", spaces
, "");
2076 spaces
+= sizeof (" Upper=y") - 1;
2078 fuse_extra_p
= ((reg_addr
[m
].fusion_gpr_ld
!= CODE_FOR_nothing
)
2079 || reg_addr
[m
].fused_toc
);
2082 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2084 if (rc
!= RELOAD_REG_ANY
)
2086 if (reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
2087 || reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
2088 || reg_addr
[m
].fusion_addi_st
[rc
] != CODE_FOR_nothing
2089 || reg_addr
[m
].fusion_addis_ld
[rc
] != CODE_FOR_nothing
2090 || reg_addr
[m
].fusion_addis_st
[rc
] != CODE_FOR_nothing
)
2092 fuse_extra_p
= true;
2101 fprintf (stderr
, "%*s Fuse:", spaces
, "");
2104 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2106 if (rc
!= RELOAD_REG_ANY
)
2110 if (reg_addr
[m
].fusion_addis_ld
[rc
] != CODE_FOR_nothing
)
2112 else if (reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
)
2117 if (reg_addr
[m
].fusion_addis_st
[rc
] != CODE_FOR_nothing
)
2119 else if (reg_addr
[m
].fusion_addi_st
[rc
] != CODE_FOR_nothing
)
2124 if (load
== '-' && store
== '-')
2128 fprintf (stderr
, "%*s%c=%c%c", (spaces
+ 1), "",
2129 reload_reg_map
[rc
].name
[0], load
, store
);
2135 if (reg_addr
[m
].fusion_gpr_ld
!= CODE_FOR_nothing
)
2137 fprintf (stderr
, "%*sP8gpr", (spaces
+ 1), "");
2141 spaces
+= sizeof (" P8gpr") - 1;
2143 if (reg_addr
[m
].fused_toc
)
2145 fprintf (stderr
, "%*sToc", (spaces
+ 1), "");
2149 spaces
+= sizeof (" Toc") - 1;
2152 spaces
+= sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2154 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2155 || rs6000_vector_mem
[m
] != VECTOR_NONE
)
2157 fprintf (stderr
, "%*s vector: arith=%-10s mem=%s",
2159 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2160 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]));
2163 fputs ("\n", stderr
);
2166 #define DEBUG_FMT_ID "%-32s= "
2167 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2168 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2169 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2171 /* Print various interesting information with -mdebug=reg. */
2173 rs6000_debug_reg_global (void)
2175 static const char *const tf
[2] = { "false", "true" };
2176 const char *nl
= (const char *)0;
2179 char costly_num
[20];
2181 char flags_buffer
[40];
2182 const char *costly_str
;
2183 const char *nop_str
;
2184 const char *trace_str
;
2185 const char *abi_str
;
2186 const char *cmodel_str
;
2187 struct cl_target_option cl_opts
;
2189 /* Modes we want tieable information on. */
2190 static const machine_mode print_tieable_modes
[] = {
2228 /* Virtual regs we are interested in. */
2229 const static struct {
2230 int regno
; /* register number. */
2231 const char *name
; /* register name. */
2232 } virtual_regs
[] = {
2233 { STACK_POINTER_REGNUM
, "stack pointer:" },
2234 { TOC_REGNUM
, "toc: " },
2235 { STATIC_CHAIN_REGNUM
, "static chain: " },
2236 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2237 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2238 { ARG_POINTER_REGNUM
, "arg pointer: " },
2239 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2240 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2241 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2242 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2243 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2244 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2245 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2246 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2247 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2248 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2251 fputs ("\nHard register information:\n", stderr
);
2252 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2253 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2254 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2257 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2258 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2259 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2260 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2261 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2262 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2263 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2264 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2266 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2267 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2268 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2272 "d reg_class = %s\n"
2273 "f reg_class = %s\n"
2274 "v reg_class = %s\n"
2275 "wa reg_class = %s\n"
2276 "wb reg_class = %s\n"
2277 "wd reg_class = %s\n"
2278 "we reg_class = %s\n"
2279 "wf reg_class = %s\n"
2280 "wg reg_class = %s\n"
2281 "wh reg_class = %s\n"
2282 "wi reg_class = %s\n"
2283 "wj reg_class = %s\n"
2284 "wk reg_class = %s\n"
2285 "wl reg_class = %s\n"
2286 "wm reg_class = %s\n"
2287 "wo reg_class = %s\n"
2288 "wp reg_class = %s\n"
2289 "wq reg_class = %s\n"
2290 "wr reg_class = %s\n"
2291 "ws reg_class = %s\n"
2292 "wt reg_class = %s\n"
2293 "wu reg_class = %s\n"
2294 "wv reg_class = %s\n"
2295 "ww reg_class = %s\n"
2296 "wx reg_class = %s\n"
2297 "wy reg_class = %s\n"
2298 "wz reg_class = %s\n"
2300 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2301 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2302 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2303 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2304 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wb
]],
2305 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2306 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_we
]],
2307 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2308 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2309 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2310 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2311 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2312 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2313 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2314 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2315 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wo
]],
2316 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2317 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2318 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2319 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2320 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2321 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2322 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2323 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2324 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2325 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2326 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2329 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2330 rs6000_debug_print_mode (m
);
2332 fputs ("\n", stderr
);
2334 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2336 machine_mode mode1
= print_tieable_modes
[m1
];
2337 bool first_time
= true;
2339 nl
= (const char *)0;
2340 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2342 machine_mode mode2
= print_tieable_modes
[m2
];
2343 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2347 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2352 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2357 fputs ("\n", stderr
);
2363 if (rs6000_recip_control
)
2365 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2367 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2368 if (rs6000_recip_bits
[m
])
2371 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2373 (RS6000_RECIP_AUTO_RE_P (m
)
2375 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2376 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2378 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2381 fputs ("\n", stderr
);
2384 if (rs6000_cpu_index
>= 0)
2386 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2388 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2390 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2391 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2394 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2396 if (rs6000_tune_index
>= 0)
2398 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2400 = processor_target_table
[rs6000_tune_index
].target_enable
;
2402 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2403 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2406 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2408 cl_target_option_save (&cl_opts
, &global_options
);
2409 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2412 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2413 rs6000_isa_flags_explicit
);
2415 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2416 rs6000_builtin_mask
);
2418 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2420 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2421 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2423 switch (rs6000_sched_costly_dep
)
2425 case max_dep_latency
:
2426 costly_str
= "max_dep_latency";
2430 costly_str
= "no_dep_costly";
2433 case all_deps_costly
:
2434 costly_str
= "all_deps_costly";
2437 case true_store_to_load_dep_costly
:
2438 costly_str
= "true_store_to_load_dep_costly";
2441 case store_to_load_dep_costly
:
2442 costly_str
= "store_to_load_dep_costly";
2446 costly_str
= costly_num
;
2447 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2451 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2453 switch (rs6000_sched_insert_nops
)
2455 case sched_finish_regroup_exact
:
2456 nop_str
= "sched_finish_regroup_exact";
2459 case sched_finish_pad_groups
:
2460 nop_str
= "sched_finish_pad_groups";
2463 case sched_finish_none
:
2464 nop_str
= "sched_finish_none";
2469 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2473 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2475 switch (rs6000_sdata
)
2482 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2486 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2490 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2495 switch (rs6000_traceback
)
2497 case traceback_default
: trace_str
= "default"; break;
2498 case traceback_none
: trace_str
= "none"; break;
2499 case traceback_part
: trace_str
= "part"; break;
2500 case traceback_full
: trace_str
= "full"; break;
2501 default: trace_str
= "unknown"; break;
2504 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2506 switch (rs6000_current_cmodel
)
2508 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2509 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2510 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2511 default: cmodel_str
= "unknown"; break;
2514 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2516 switch (rs6000_current_abi
)
2518 case ABI_NONE
: abi_str
= "none"; break;
2519 case ABI_AIX
: abi_str
= "aix"; break;
2520 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2521 case ABI_V4
: abi_str
= "V4"; break;
2522 case ABI_DARWIN
: abi_str
= "darwin"; break;
2523 default: abi_str
= "unknown"; break;
2526 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2528 if (rs6000_altivec_abi
)
2529 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2532 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2534 if (rs6000_darwin64_abi
)
2535 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2537 if (rs6000_float_gprs
)
2538 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2540 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2541 (TARGET_FPRS
? "true" : "false"));
2543 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2544 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2546 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2547 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2549 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2550 (TARGET_SOFT_FLOAT
? "true" : "false"));
2552 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2553 (TARGET_E500_SINGLE
? "true" : "false"));
2555 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2556 (TARGET_E500_DOUBLE
? "true" : "false"));
2558 if (TARGET_LINK_STACK
)
2559 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2561 if (targetm
.lra_p ())
2562 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2564 if (TARGET_P8_FUSION
)
2568 strcpy (options
, (TARGET_P9_FUSION
) ? "power9" : "power8");
2569 if (TARGET_TOC_FUSION
)
2570 strcat (options
, ", toc");
2572 if (TARGET_P8_FUSION_SIGN
)
2573 strcat (options
, ", sign");
2575 fprintf (stderr
, DEBUG_FMT_S
, "fusion", options
);
2578 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2579 TARGET_SECURE_PLT
? "secure" : "bss");
2580 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2581 aix_struct_return
? "aix" : "sysv");
2582 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2583 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2584 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2585 tf
[!!rs6000_align_branch_targets
]);
2586 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2587 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2588 rs6000_long_double_type_size
);
2589 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2590 (int)rs6000_sched_restricted_insns_priority
);
2591 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2593 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2594 (int)RS6000_BUILTIN_COUNT
);
2597 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2598 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2600 if (TARGET_DIRECT_MOVE_128
)
2601 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit mfvsrld element",
2602 (int)VECTOR_ELEMENT_MFVSRLD_64BIT
);
2606 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2607 legitimate address support to figure out the appropriate addressing to
2611 rs6000_setup_reg_addr_masks (void)
2613 ssize_t rc
, reg
, m
, nregs
;
2614 addr_mask_type any_addr_mask
, addr_mask
;
2616 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2618 machine_mode m2
= (machine_mode
)m
;
2619 unsigned short msize
= GET_MODE_SIZE (m2
);
2621 /* SDmode is special in that we want to access it only via REG+REG
2622 addressing on power7 and above, since we want to use the LFIWZX and
2623 STFIWZX instructions to load it. */
2624 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2627 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2630 reg
= reload_reg_map
[rc
].reg
;
2632 /* Can mode values go in the GPR/FPR/Altivec registers? */
2633 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2635 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2636 addr_mask
|= RELOAD_REG_VALID
;
2638 /* Indicate if the mode takes more than 1 physical register. If
2639 it takes a single register, indicate it can do REG+REG
2641 if (nregs
> 1 || m
== BLKmode
)
2642 addr_mask
|= RELOAD_REG_MULTIPLE
;
2644 addr_mask
|= RELOAD_REG_INDEXED
;
2646 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2647 addressing. Restrict addressing on SPE for 64-bit types
2648 because of the SUBREG hackery used to address 64-bit floats in
2649 '32-bit' GPRs. If we allow scalars into Altivec registers,
2650 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
2653 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2655 && !VECTOR_MODE_P (m2
)
2656 && !FLOAT128_VECTOR_P (m2
)
2657 && !COMPLEX_MODE_P (m2
)
2658 && (m2
!= DFmode
|| !TARGET_UPPER_REGS_DF
)
2659 && (m2
!= SFmode
|| !TARGET_UPPER_REGS_SF
)
2660 && !(TARGET_E500_DOUBLE
&& msize
== 8))
2662 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2664 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2665 we don't allow PRE_MODIFY for some multi-register
2670 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2674 if (TARGET_POWERPC64
)
2675 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2681 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2687 /* GPR and FPR registers can do REG+OFFSET addressing, except
2688 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form
2689 addressing for scalars to altivec registers. */
2690 if ((addr_mask
!= 0) && !indexed_only_p
2692 && (rc
== RELOAD_REG_GPR
2693 || rc
== RELOAD_REG_FPR
2694 || (rc
== RELOAD_REG_VMX
2696 && (m2
== DFmode
|| m2
== SFmode
))))
2697 addr_mask
|= RELOAD_REG_OFFSET
;
2699 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2700 addressing on 128-bit types. */
2701 if (rc
== RELOAD_REG_VMX
&& msize
== 16
2702 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2703 addr_mask
|= RELOAD_REG_AND_M16
;
2705 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2706 any_addr_mask
|= addr_mask
;
2709 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2714 /* Initialize the various global tables that are based on register size. */
2716 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2722 /* Precalculate REGNO_REG_CLASS. */
2723 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2724 for (r
= 1; r
< 32; ++r
)
2725 rs6000_regno_regclass
[r
] = BASE_REGS
;
2727 for (r
= 32; r
< 64; ++r
)
2728 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2730 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2731 rs6000_regno_regclass
[r
] = NO_REGS
;
2733 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2734 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2736 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2737 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2738 rs6000_regno_regclass
[r
] = CR_REGS
;
2740 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2741 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2742 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
2743 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2744 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2745 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2746 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2747 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2748 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2749 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2750 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2751 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2753 /* Precalculate register class to simpler reload register class. We don't
2754 need all of the register classes that are combinations of different
2755 classes, just the simple ones that have constraint letters. */
2756 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2757 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2759 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2760 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2761 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2762 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2763 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2764 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2765 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2766 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2767 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2768 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2769 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2770 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2774 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2775 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2779 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2780 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2783 /* Precalculate the valid memory formats as well as the vector information,
2784 this must be set up before the rs6000_hard_regno_nregs_internal calls
2786 gcc_assert ((int)VECTOR_NONE
== 0);
2787 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2788 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2790 gcc_assert ((int)CODE_FOR_nothing
== 0);
2791 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2793 gcc_assert ((int)NO_REGS
== 0);
2794 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2796 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2797 believes it can use native alignment or still uses 128-bit alignment. */
2798 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2809 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
2810 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
2811 if (TARGET_FLOAT128
)
2813 rs6000_vector_mem
[KFmode
] = VECTOR_VSX
;
2814 rs6000_vector_align
[KFmode
] = 128;
2816 if (FLOAT128_IEEE_P (TFmode
))
2818 rs6000_vector_mem
[TFmode
] = VECTOR_VSX
;
2819 rs6000_vector_align
[TFmode
] = 128;
2823 /* V2DF mode, VSX only. */
2826 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2827 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2828 rs6000_vector_align
[V2DFmode
] = align64
;
2831 /* V4SF mode, either VSX or Altivec. */
2834 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2835 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2836 rs6000_vector_align
[V4SFmode
] = align32
;
2838 else if (TARGET_ALTIVEC
)
2840 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2841 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2842 rs6000_vector_align
[V4SFmode
] = align32
;
2845 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2849 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2850 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2851 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2852 rs6000_vector_align
[V4SImode
] = align32
;
2853 rs6000_vector_align
[V8HImode
] = align32
;
2854 rs6000_vector_align
[V16QImode
] = align32
;
2858 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2859 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2860 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2864 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2865 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2866 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2870 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2871 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2874 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2875 rs6000_vector_unit
[V2DImode
]
2876 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2877 rs6000_vector_align
[V2DImode
] = align64
;
2879 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2880 rs6000_vector_unit
[V1TImode
]
2881 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2882 rs6000_vector_align
[V1TImode
] = 128;
2885 /* DFmode, see if we want to use the VSX unit. Memory is handled
2886 differently, so don't set rs6000_vector_mem. */
2887 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2889 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2890 rs6000_vector_align
[DFmode
] = 64;
2893 /* SFmode, see if we want to use the VSX unit. */
2894 if (TARGET_P8_VECTOR
&& TARGET_VSX_SCALAR_FLOAT
)
2896 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
2897 rs6000_vector_align
[SFmode
] = 32;
2900 /* Allow TImode in VSX register and set the VSX memory macros. */
2901 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2903 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2904 rs6000_vector_align
[TImode
] = align64
;
2907 /* TODO add SPE and paired floating point vector support. */
2909 /* Register class constraints for the constraints that depend on compile
2910 switches. When the VSX code was added, different constraints were added
2911 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2912 of the VSX registers are used. The register classes for scalar floating
2913 point types is set, based on whether we allow that type into the upper
2914 (Altivec) registers. GCC has register classes to target the Altivec
2915 registers for load/store operations, to select using a VSX memory
2916 operation instead of the traditional floating point operation. The
2919 d - Register class to use with traditional DFmode instructions.
2920 f - Register class to use with traditional SFmode instructions.
2921 v - Altivec register.
2922 wa - Any VSX register.
2923 wc - Reserved to represent individual CR bits (used in LLVM).
2924 wd - Preferred register class for V2DFmode.
2925 wf - Preferred register class for V4SFmode.
2926 wg - Float register for power6x move insns.
2927 wh - FP register for direct move instructions.
2928 wi - FP or VSX register to hold 64-bit integers for VSX insns.
2929 wj - FP or VSX register to hold 64-bit integers for direct moves.
2930 wk - FP or VSX register to hold 64-bit doubles for direct moves.
2931 wl - Float register if we can do 32-bit signed int loads.
2932 wm - VSX register for ISA 2.07 direct move operations.
2933 wn - always NO_REGS.
2934 wr - GPR if 64-bit mode is permitted.
2935 ws - Register class to do ISA 2.06 DF operations.
2936 wt - VSX register for TImode in VSX registers.
2937 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2938 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2939 ww - Register class to do SF conversions in with VSX operations.
2940 wx - Float register if we can do 32-bit int stores.
2941 wy - Register class to do ISA 2.07 SF operations.
2942 wz - Float register if we can do 32-bit unsigned int loads. */
2944 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2945 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
2947 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2948 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
2952 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2953 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
2954 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
2955 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = FLOAT_REGS
; /* DImode */
2957 if (TARGET_VSX_TIMODE
)
2958 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
2960 if (TARGET_UPPER_REGS_DF
) /* DFmode */
2962 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2963 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2966 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2969 /* Add conditional constraints based on various options, to allow us to
2970 collapse multiple insn patterns. */
2972 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2974 if (TARGET_MFPGPR
) /* DFmode */
2975 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2978 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
2980 if (TARGET_DIRECT_MOVE
)
2982 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
2983 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
2984 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
2985 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
2986 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
2987 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2990 if (TARGET_POWERPC64
)
2991 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2993 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
) /* SFmode */
2995 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2996 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2997 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2999 else if (TARGET_P8_VECTOR
)
3001 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
3002 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3004 else if (TARGET_VSX
)
3005 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3008 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
3011 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
3013 if (TARGET_FLOAT128
)
3015 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
3016 if (FLOAT128_IEEE_P (TFmode
))
3017 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
3020 /* Support for new D-form instructions. */
3021 if (TARGET_P9_DFORM
)
3022 rs6000_constraints
[RS6000_CONSTRAINT_wb
] = ALTIVEC_REGS
;
3024 /* Support for ISA 3.0 (power9) vectors. */
3025 if (TARGET_P9_VECTOR
)
3026 rs6000_constraints
[RS6000_CONSTRAINT_wo
] = VSX_REGS
;
3028 /* Support for new direct moves (ISA 3.0 + 64bit). */
3029 if (TARGET_DIRECT_MOVE_128
)
3030 rs6000_constraints
[RS6000_CONSTRAINT_we
] = VSX_REGS
;
3032 /* Set up the reload helper and direct move functions. */
3033 if (TARGET_VSX
|| TARGET_ALTIVEC
)
3037 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
3038 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
3039 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
3040 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
3041 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
3042 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
3043 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
3044 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
3045 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
3046 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
3047 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
3048 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
3049 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
3050 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
3051 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_di_store
;
3052 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_di_load
;
3053 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
3054 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
3055 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
3056 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
3057 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
3058 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
3060 if (FLOAT128_IEEE_P (TFmode
))
3062 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_di_store
;
3063 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_di_load
;
3066 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3068 if (TARGET_NO_SDMODE_STACK
)
3070 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
3071 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
3074 if (TARGET_VSX_TIMODE
)
3076 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
3077 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
3080 if (TARGET_DIRECT_MOVE
&& !TARGET_DIRECT_MOVE_128
)
3082 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
3083 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
3084 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
3085 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
3086 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
3087 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
3088 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
3089 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
3090 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
3092 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
3093 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
3094 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
3095 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
3096 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
3097 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
3098 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
3099 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
3100 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
3105 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
3106 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
3107 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
3108 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
3109 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
3110 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
3111 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
3112 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
3113 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
3114 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
3115 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
3116 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
3117 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
3118 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
3119 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_si_store
;
3120 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_si_load
;
3121 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
3122 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
3123 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
3124 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
3125 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
3126 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
3128 if (FLOAT128_IEEE_P (TFmode
))
3130 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_si_store
;
3131 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_si_load
;
3134 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3136 if (TARGET_NO_SDMODE_STACK
)
3138 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
3139 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
3142 if (TARGET_VSX_TIMODE
)
3144 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
3145 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
3148 if (TARGET_DIRECT_MOVE
)
3150 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
3151 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
3152 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
3156 if (TARGET_UPPER_REGS_DF
)
3157 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
3159 if (TARGET_UPPER_REGS_SF
)
3160 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
3163 /* Setup the fusion operations. */
3164 if (TARGET_P8_FUSION
)
3166 reg_addr
[QImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_qi
;
3167 reg_addr
[HImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_hi
;
3168 reg_addr
[SImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_si
;
3170 reg_addr
[DImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_di
;
3173 if (TARGET_P9_FUSION
)
3176 enum machine_mode mode
; /* mode of the fused type. */
3177 enum machine_mode pmode
; /* pointer mode. */
3178 enum rs6000_reload_reg_type rtype
; /* register type. */
3179 enum insn_code load
; /* load insn. */
3180 enum insn_code store
; /* store insn. */
3183 static const struct fuse_insns addis_insns
[] = {
3184 { SFmode
, DImode
, RELOAD_REG_FPR
,
3185 CODE_FOR_fusion_fpr_di_sf_load
,
3186 CODE_FOR_fusion_fpr_di_sf_store
},
3188 { SFmode
, SImode
, RELOAD_REG_FPR
,
3189 CODE_FOR_fusion_fpr_si_sf_load
,
3190 CODE_FOR_fusion_fpr_si_sf_store
},
3192 { DFmode
, DImode
, RELOAD_REG_FPR
,
3193 CODE_FOR_fusion_fpr_di_df_load
,
3194 CODE_FOR_fusion_fpr_di_df_store
},
3196 { DFmode
, SImode
, RELOAD_REG_FPR
,
3197 CODE_FOR_fusion_fpr_si_df_load
,
3198 CODE_FOR_fusion_fpr_si_df_store
},
3200 { DImode
, DImode
, RELOAD_REG_FPR
,
3201 CODE_FOR_fusion_fpr_di_di_load
,
3202 CODE_FOR_fusion_fpr_di_di_store
},
3204 { DImode
, SImode
, RELOAD_REG_FPR
,
3205 CODE_FOR_fusion_fpr_si_di_load
,
3206 CODE_FOR_fusion_fpr_si_di_store
},
3208 { QImode
, DImode
, RELOAD_REG_GPR
,
3209 CODE_FOR_fusion_gpr_di_qi_load
,
3210 CODE_FOR_fusion_gpr_di_qi_store
},
3212 { QImode
, SImode
, RELOAD_REG_GPR
,
3213 CODE_FOR_fusion_gpr_si_qi_load
,
3214 CODE_FOR_fusion_gpr_si_qi_store
},
3216 { HImode
, DImode
, RELOAD_REG_GPR
,
3217 CODE_FOR_fusion_gpr_di_hi_load
,
3218 CODE_FOR_fusion_gpr_di_hi_store
},
3220 { HImode
, SImode
, RELOAD_REG_GPR
,
3221 CODE_FOR_fusion_gpr_si_hi_load
,
3222 CODE_FOR_fusion_gpr_si_hi_store
},
3224 { SImode
, DImode
, RELOAD_REG_GPR
,
3225 CODE_FOR_fusion_gpr_di_si_load
,
3226 CODE_FOR_fusion_gpr_di_si_store
},
3228 { SImode
, SImode
, RELOAD_REG_GPR
,
3229 CODE_FOR_fusion_gpr_si_si_load
,
3230 CODE_FOR_fusion_gpr_si_si_store
},
3232 { SFmode
, DImode
, RELOAD_REG_GPR
,
3233 CODE_FOR_fusion_gpr_di_sf_load
,
3234 CODE_FOR_fusion_gpr_di_sf_store
},
3236 { SFmode
, SImode
, RELOAD_REG_GPR
,
3237 CODE_FOR_fusion_gpr_si_sf_load
,
3238 CODE_FOR_fusion_gpr_si_sf_store
},
3240 { DImode
, DImode
, RELOAD_REG_GPR
,
3241 CODE_FOR_fusion_gpr_di_di_load
,
3242 CODE_FOR_fusion_gpr_di_di_store
},
3244 { DFmode
, DImode
, RELOAD_REG_GPR
,
3245 CODE_FOR_fusion_gpr_di_df_load
,
3246 CODE_FOR_fusion_gpr_di_df_store
},
3249 enum machine_mode cur_pmode
= Pmode
;
3252 for (i
= 0; i
< ARRAY_SIZE (addis_insns
); i
++)
3254 enum machine_mode xmode
= addis_insns
[i
].mode
;
3255 enum rs6000_reload_reg_type rtype
= addis_insns
[i
].rtype
;
3257 if (addis_insns
[i
].pmode
!= cur_pmode
)
3260 if (rtype
== RELOAD_REG_FPR
3261 && (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
))
3264 reg_addr
[xmode
].fusion_addis_ld
[rtype
] = addis_insns
[i
].load
;
3265 reg_addr
[xmode
].fusion_addis_st
[rtype
] = addis_insns
[i
].store
;
3269 /* Note which types we support fusing TOC setup plus memory insn. We only do
3270 fused TOCs for medium/large code models. */
3271 if (TARGET_P8_FUSION
&& TARGET_TOC_FUSION
&& TARGET_POWERPC64
3272 && (TARGET_CMODEL
!= CMODEL_SMALL
))
3274 reg_addr
[QImode
].fused_toc
= true;
3275 reg_addr
[HImode
].fused_toc
= true;
3276 reg_addr
[SImode
].fused_toc
= true;
3277 reg_addr
[DImode
].fused_toc
= true;
3278 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3280 if (TARGET_SINGLE_FLOAT
)
3281 reg_addr
[SFmode
].fused_toc
= true;
3282 if (TARGET_DOUBLE_FLOAT
)
3283 reg_addr
[DFmode
].fused_toc
= true;
3287 /* Precalculate HARD_REGNO_NREGS. */
3288 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3289 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3290 rs6000_hard_regno_nregs
[m
][r
]
3291 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
3293 /* Precalculate HARD_REGNO_MODE_OK. */
3294 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3295 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3296 if (rs6000_hard_regno_mode_ok (r
, (machine_mode
)m
))
3297 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
3299 /* Precalculate CLASS_MAX_NREGS sizes. */
3300 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3304 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3305 reg_size
= UNITS_PER_VSX_WORD
;
3307 else if (c
== ALTIVEC_REGS
)
3308 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3310 else if (c
== FLOAT_REGS
)
3311 reg_size
= UNITS_PER_FP_WORD
;
3314 reg_size
= UNITS_PER_WORD
;
3316 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3318 machine_mode m2
= (machine_mode
)m
;
3319 int reg_size2
= reg_size
;
3321 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3323 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3324 reg_size2
= UNITS_PER_FP_WORD
;
3326 rs6000_class_max_nregs
[m
][c
]
3327 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3331 if (TARGET_E500_DOUBLE
)
3332 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
3334 /* Calculate which modes to automatically generate code to use a the
3335 reciprocal divide and square root instructions. In the future, possibly
3336 automatically generate the instructions even if the user did not specify
3337 -mrecip. The older machines double precision reciprocal sqrt estimate is
3338 not accurate enough. */
3339 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3341 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3343 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3344 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3345 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3346 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3347 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3349 if (TARGET_FRSQRTES
)
3350 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3352 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3353 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3354 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3355 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3356 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3358 if (rs6000_recip_control
)
3360 if (!flag_finite_math_only
)
3361 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
3362 if (flag_trapping_math
)
3363 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
3364 if (!flag_reciprocal_math
)
3365 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
3366 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3368 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3369 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3370 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3372 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3373 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3374 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3376 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3377 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3378 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3380 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3381 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3382 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3384 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3385 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3386 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3388 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3389 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3390 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3392 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3393 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3394 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3396 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3397 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3398 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3402 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3403 legitimate address support to figure out the appropriate addressing to
3405 rs6000_setup_reg_addr_masks ();
3407 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3409 if (TARGET_DEBUG_REG
)
3410 rs6000_debug_reg_global ();
3412 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3414 "SImode variable mult cost = %d\n"
3415 "SImode constant mult cost = %d\n"
3416 "SImode short constant mult cost = %d\n"
3417 "DImode multipliciation cost = %d\n"
3418 "SImode division cost = %d\n"
3419 "DImode division cost = %d\n"
3420 "Simple fp operation cost = %d\n"
3421 "DFmode multiplication cost = %d\n"
3422 "SFmode division cost = %d\n"
3423 "DFmode division cost = %d\n"
3424 "cache line size = %d\n"
3425 "l1 cache size = %d\n"
3426 "l2 cache size = %d\n"
3427 "simultaneous prefetches = %d\n"
3430 rs6000_cost
->mulsi_const
,
3431 rs6000_cost
->mulsi_const9
,
3439 rs6000_cost
->cache_line_size
,
3440 rs6000_cost
->l1_cache_size
,
3441 rs6000_cost
->l2_cache_size
,
3442 rs6000_cost
->simultaneous_prefetches
);
3447 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3450 darwin_rs6000_override_options (void)
3452 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3454 rs6000_altivec_abi
= 1;
3455 TARGET_ALTIVEC_VRSAVE
= 1;
3456 rs6000_current_abi
= ABI_DARWIN
;
3458 if (DEFAULT_ABI
== ABI_DARWIN
3460 darwin_one_byte_bool
= 1;
3462 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3464 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3465 warning (0, "-m64 requires PowerPC64 architecture, enabling");
3469 rs6000_default_long_calls
= 1;
3470 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3473 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3475 if (!flag_mkernel
&& !flag_apple_kext
3477 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3478 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3480 /* Unless the user (not the configurer) has explicitly overridden
3481 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3482 G4 unless targeting the kernel. */
3485 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3486 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3487 && ! global_options_set
.x_rs6000_cpu_index
)
3489 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3494 /* If not otherwise specified by a target, make 'long double' equivalent to
3497 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3498 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3501 /* Return the builtin mask of the various options used that could affect which
3502 builtins were used. In the past we used target_flags, but we've run out of
3503 bits, and some options like SPE and PAIRED are no longer in
3507 rs6000_builtin_mask_calculate (void)
3509 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3510 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3511 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3512 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3513 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3514 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3515 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3516 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3517 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3518 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3519 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3520 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3521 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3522 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3523 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3524 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0));
3527 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3528 to clobber the XER[CA] bit because clobbering that bit without telling
3529 the compiler worked just fine with versions of GCC before GCC 5, and
3530 breaking a lot of older code in ways that are hard to track down is
3531 not such a great idea. */
3534 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3535 vec
<const char *> &/*constraints*/,
3536 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3538 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3539 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3543 /* Override command line options. Mostly we process the processor type and
3544 sometimes adjust other TARGET_ options. */
3547 rs6000_option_override_internal (bool global_init_p
)
3550 bool have_cpu
= false;
3552 /* The default cpu requested at configure time, if any. */
3553 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3555 HOST_WIDE_INT set_masks
;
3558 struct cl_target_option
*main_target_opt
3559 = ((global_init_p
|| target_option_default_node
== NULL
)
3560 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3562 /* Print defaults. */
3563 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3564 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3566 /* Remember the explicit arguments. */
3568 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3570 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3571 library functions, so warn about it. The flag may be useful for
3572 performance studies from time to time though, so don't disable it
3574 if (global_options_set
.x_rs6000_alignment_flags
3575 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3576 && DEFAULT_ABI
== ABI_DARWIN
3578 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3579 " it is incompatible with the installed C and C++ libraries");
3581 /* Numerous experiment shows that IRA based loop pressure
3582 calculation works better for RTL loop invariant motion on targets
3583 with enough (>= 32) registers. It is an expensive optimization.
3584 So it is on only for peak performance. */
3585 if (optimize
>= 3 && global_init_p
3586 && !global_options_set
.x_flag_ira_loop_pressure
)
3587 flag_ira_loop_pressure
= 1;
3589 /* Set the pointer size. */
3592 rs6000_pmode
= (int)DImode
;
3593 rs6000_pointer_size
= 64;
3597 rs6000_pmode
= (int)SImode
;
3598 rs6000_pointer_size
= 32;
3601 /* Some OSs don't support saving the high part of 64-bit registers on context
3602 switch. Other OSs don't support saving Altivec registers. On those OSs,
3603 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3604 if the user wants either, the user must explicitly specify them and we
3605 won't interfere with the user's specification. */
3607 set_masks
= POWERPC_MASKS
;
3608 #ifdef OS_MISSING_POWERPC64
3609 if (OS_MISSING_POWERPC64
)
3610 set_masks
&= ~OPTION_MASK_POWERPC64
;
3612 #ifdef OS_MISSING_ALTIVEC
3613 if (OS_MISSING_ALTIVEC
)
3614 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3617 /* Don't override by the processor default if given explicitly. */
3618 set_masks
&= ~rs6000_isa_flags_explicit
;
3620 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3621 the cpu in a target attribute or pragma, but did not specify a tuning
3622 option, use the cpu for the tuning option rather than the option specified
3623 with -mtune on the command line. Process a '--with-cpu' configuration
3624 request as an implicit --cpu. */
3625 if (rs6000_cpu_index
>= 0)
3627 cpu_index
= rs6000_cpu_index
;
3630 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3632 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3635 else if (implicit_cpu
)
3637 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3642 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3643 const char *default_cpu
= ((!TARGET_POWERPC64
)
3645 : ((BYTES_BIG_ENDIAN
)
3649 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3653 gcc_assert (cpu_index
>= 0);
3655 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3656 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3657 with those from the cpu, except for options that were explicitly set. If
3658 we don't have a cpu, do not override the target bits set in
3662 rs6000_isa_flags
&= ~set_masks
;
3663 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3668 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3669 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3670 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3671 to using rs6000_isa_flags, we need to do the initialization here.
3673 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3674 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3675 HOST_WIDE_INT flags
= ((TARGET_DEFAULT
) ? TARGET_DEFAULT
3676 : processor_target_table
[cpu_index
].target_enable
);
3677 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3680 if (rs6000_tune_index
>= 0)
3681 tune_index
= rs6000_tune_index
;
3684 /* Until power9 tuning is available, use power8 tuning if -mcpu=power9. */
3685 if (processor_target_table
[cpu_index
].processor
!= PROCESSOR_POWER9
)
3686 rs6000_tune_index
= tune_index
= cpu_index
;
3691 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3692 if (processor_target_table
[i
].processor
== PROCESSOR_POWER8
)
3694 rs6000_tune_index
= tune_index
= i
;
3702 enum processor_type tune_proc
3703 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3706 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3707 if (processor_target_table
[i
].processor
== tune_proc
)
3709 rs6000_tune_index
= tune_index
= i
;
3714 gcc_assert (tune_index
>= 0);
3715 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3717 /* Pick defaults for SPE related control flags. Do this early to make sure
3718 that the TARGET_ macros are representative ASAP. */
3720 int spe_capable_cpu
=
3721 (rs6000_cpu
== PROCESSOR_PPC8540
3722 || rs6000_cpu
== PROCESSOR_PPC8548
);
3724 if (!global_options_set
.x_rs6000_spe_abi
)
3725 rs6000_spe_abi
= spe_capable_cpu
;
3727 if (!global_options_set
.x_rs6000_spe
)
3728 rs6000_spe
= spe_capable_cpu
;
3730 if (!global_options_set
.x_rs6000_float_gprs
)
3732 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3733 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3737 if (global_options_set
.x_rs6000_spe_abi
3740 error ("not configured for SPE ABI");
3742 if (global_options_set
.x_rs6000_spe
3745 error ("not configured for SPE instruction set");
3747 if (main_target_opt
!= NULL
3748 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3749 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3750 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3751 error ("target attribute or pragma changes SPE ABI");
3753 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3754 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3755 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3758 error ("AltiVec not supported in this target");
3760 error ("SPE not supported in this target");
3762 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3765 error ("SPE not supported in this target");
3768 /* Disable Cell microcode if we are optimizing for the Cell
3769 and not optimizing for size. */
3770 if (rs6000_gen_cell_microcode
== -1)
3771 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3774 /* If we are optimizing big endian systems for space and it's OK to
3775 use instructions that would be microcoded on the Cell, use the
3776 load/store multiple and string instructions. */
3777 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3778 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3779 | OPTION_MASK_STRING
);
3781 /* Don't allow -mmultiple or -mstring on little endian systems
3782 unless the cpu is a 750, because the hardware doesn't support the
3783 instructions used in little endian mode, and causes an alignment
3784 trap. The 750 does not cause an alignment trap (except when the
3785 target is unaligned). */
3787 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3789 if (TARGET_MULTIPLE
)
3791 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3792 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3793 warning (0, "-mmultiple is not supported on little endian systems");
3798 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3799 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3800 warning (0, "-mstring is not supported on little endian systems");
3804 /* If little-endian, default to -mstrict-align on older processors.
3805 Testing for htm matches power8 and later. */
3806 if (!BYTES_BIG_ENDIAN
3807 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3808 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3810 /* -maltivec={le,be} implies -maltivec. */
3811 if (rs6000_altivec_element_order
!= 0)
3812 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3814 /* Disallow -maltivec=le in big endian mode for now. This is not
3815 known to be useful for anyone. */
3816 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3818 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3819 rs6000_altivec_element_order
= 0;
3822 /* Add some warnings for VSX. */
3825 const char *msg
= NULL
;
3826 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3827 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3829 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3830 msg
= N_("-mvsx requires hardware floating point");
3833 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3834 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3837 else if (TARGET_PAIRED_FLOAT
)
3838 msg
= N_("-mvsx and -mpaired are incompatible");
3839 else if (TARGET_AVOID_XFORM
> 0)
3840 msg
= N_("-mvsx needs indexed addressing");
3841 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3842 & OPTION_MASK_ALTIVEC
))
3844 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3845 msg
= N_("-mvsx and -mno-altivec are incompatible");
3847 msg
= N_("-mno-altivec disables vsx");
3853 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3854 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3858 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3859 the -mcpu setting to enable options that conflict. */
3860 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3861 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3862 | OPTION_MASK_ALTIVEC
3863 | OPTION_MASK_VSX
)) != 0)
3864 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3865 | OPTION_MASK_DIRECT_MOVE
)
3866 & ~rs6000_isa_flags_explicit
);
3868 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3869 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3871 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3872 unless the user explicitly used the -mno-<option> to disable the code. */
3873 if (TARGET_P9_VECTOR
|| TARGET_MODULO
|| TARGET_P9_DFORM
|| TARGET_P9_MINMAX
)
3874 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3875 else if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3876 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3877 else if (TARGET_VSX
)
3878 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3879 else if (TARGET_POPCNTD
)
3880 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3881 else if (TARGET_DFP
)
3882 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3883 else if (TARGET_CMPB
)
3884 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3885 else if (TARGET_FPRND
)
3886 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3887 else if (TARGET_POPCNTB
)
3888 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3889 else if (TARGET_ALTIVEC
)
3890 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3892 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3894 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3895 error ("-mcrypto requires -maltivec");
3896 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3899 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3901 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3902 error ("-mdirect-move requires -mvsx");
3903 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3906 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3908 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3909 error ("-mpower8-vector requires -maltivec");
3910 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3913 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3915 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3916 error ("-mpower8-vector requires -mvsx");
3917 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3920 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3922 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3923 error ("-mvsx-timode requires -mvsx");
3924 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3927 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
3929 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
3930 error ("-mhard-dfp requires -mhard-float");
3931 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
3934 /* Allow an explicit -mupper-regs to set both -mupper-regs-df and
3935 -mupper-regs-sf, depending on the cpu, unless the user explicitly also set
3936 the individual option. */
3937 if (TARGET_UPPER_REGS
> 0)
3940 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
3942 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_DF
;
3943 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
3945 if (TARGET_P8_VECTOR
3946 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
3948 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_SF
;
3949 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
3952 else if (TARGET_UPPER_REGS
== 0)
3955 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
3957 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
3958 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
3960 if (TARGET_P8_VECTOR
3961 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
3963 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
3964 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
3968 if (TARGET_UPPER_REGS_DF
&& !TARGET_VSX
)
3970 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
3971 error ("-mupper-regs-df requires -mvsx");
3972 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
3975 if (TARGET_UPPER_REGS_SF
&& !TARGET_P8_VECTOR
)
3977 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
)
3978 error ("-mupper-regs-sf requires -mpower8-vector");
3979 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
3982 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3983 silently turn off quad memory mode. */
3984 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3986 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3987 warning (0, N_("-mquad-memory requires 64-bit mode"));
3989 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3990 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3992 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3993 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3996 /* Non-atomic quad memory load/store are disabled for little endian, since
3997 the words are reversed, but atomic operations can still be done by
3998 swapping the words. */
3999 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
4001 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4002 warning (0, N_("-mquad-memory is not available in little endian mode"));
4004 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
4007 /* Assume if the user asked for normal quad memory instructions, they want
4008 the atomic versions as well, unless they explicity told us not to use quad
4009 word atomic instructions. */
4010 if (TARGET_QUAD_MEMORY
4011 && !TARGET_QUAD_MEMORY_ATOMIC
4012 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
4013 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
4015 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4016 generating power8 instructions. */
4017 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
4018 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4019 & OPTION_MASK_P8_FUSION
);
4021 /* Setting additional fusion flags turns on base fusion. */
4022 if (!TARGET_P8_FUSION
&& (TARGET_P8_FUSION_SIGN
|| TARGET_TOC_FUSION
))
4024 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4026 if (TARGET_P8_FUSION_SIGN
)
4027 error ("-mpower8-fusion-sign requires -mpower8-fusion");
4029 if (TARGET_TOC_FUSION
)
4030 error ("-mtoc-fusion requires -mpower8-fusion");
4032 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4035 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4038 /* Power9 fusion is a superset over power8 fusion. */
4039 if (TARGET_P9_FUSION
&& !TARGET_P8_FUSION
)
4041 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4043 error ("-mpower9-fusion requires -mpower8-fusion");
4044 rs6000_isa_flags
&= ~OPTION_MASK_P9_FUSION
;
4047 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4050 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4051 generating power9 instructions. */
4052 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_FUSION
))
4053 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4054 & OPTION_MASK_P9_FUSION
);
4056 /* Power8 does not fuse sign extended loads with the addis. If we are
4057 optimizing at high levels for speed, convert a sign extended load into a
4058 zero extending load, and an explicit sign extension. */
4059 if (TARGET_P8_FUSION
4060 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
4061 && optimize_function_for_speed_p (cfun
)
4063 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
4065 /* TOC fusion requires 64-bit and medium/large code model. */
4066 if (TARGET_TOC_FUSION
&& !TARGET_POWERPC64
)
4068 rs6000_isa_flags
&= ~OPTION_MASK_TOC_FUSION
;
4069 if ((rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
) != 0)
4070 warning (0, N_("-mtoc-fusion requires 64-bit"));
4073 if (TARGET_TOC_FUSION
&& (TARGET_CMODEL
== CMODEL_SMALL
))
4075 rs6000_isa_flags
&= ~OPTION_MASK_TOC_FUSION
;
4076 if ((rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
) != 0)
4077 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4080 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4082 if (TARGET_P8_FUSION
&& !TARGET_TOC_FUSION
&& TARGET_POWERPC64
4083 && (TARGET_CMODEL
!= CMODEL_SMALL
)
4084 && !(rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
))
4085 rs6000_isa_flags
|= OPTION_MASK_TOC_FUSION
;
4087 /* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
4088 if (TARGET_P9_DFORM
&& !TARGET_P9_VECTOR
)
4090 if (rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
)
4091 error ("-mpower9-dform requires -mpower9-vector");
4092 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM
;
4095 if (TARGET_P9_DFORM
&& !TARGET_UPPER_REGS_DF
)
4097 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
4098 error ("-mpower9-dform requires -mupper-regs-df");
4099 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM
;
4102 if (TARGET_P9_DFORM
&& !TARGET_UPPER_REGS_SF
)
4104 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
)
4105 error ("-mpower9-dform requires -mupper-regs-sf");
4106 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM
;
4109 /* ISA 3.0 vector instructions include ISA 2.07. */
4110 if (TARGET_P9_VECTOR
&& !TARGET_P8_VECTOR
)
4112 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4113 error ("-mpower9-vector requires -mpower8-vector");
4114 rs6000_isa_flags
&= ~OPTION_MASK_P9_VECTOR
;
4117 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4118 support. If we only have ISA 2.06 support, and the user did not specify
4119 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4120 but we don't enable the full vectorization support */
4121 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
4122 TARGET_ALLOW_MOVMISALIGN
= 1;
4124 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
4126 if (TARGET_ALLOW_MOVMISALIGN
> 0)
4127 error ("-mallow-movmisalign requires -mvsx");
4129 TARGET_ALLOW_MOVMISALIGN
= 0;
4132 /* Determine when unaligned vector accesses are permitted, and when
4133 they are preferred over masked Altivec loads. Note that if
4134 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4135 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4137 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4141 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4142 error ("-mefficient-unaligned-vsx requires -mvsx");
4144 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4147 else if (!TARGET_ALLOW_MOVMISALIGN
)
4149 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4150 error ("-mefficient-unaligned-vsx requires -mallow-movmisalign");
4152 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4156 /* __float128 requires VSX support. */
4157 if (TARGET_FLOAT128
&& !TARGET_VSX
)
4159 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128
) != 0)
4160 error ("-mfloat128 requires VSX support");
4162 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128
| OPTION_MASK_FLOAT128_HW
);
4165 /* IEEE 128-bit floating point hardware instructions imply enabling
4167 if (TARGET_FLOAT128_HW
4168 && (rs6000_isa_flags
& (OPTION_MASK_P9_VECTOR
4169 | OPTION_MASK_DIRECT_MOVE
4170 | OPTION_MASK_UPPER_REGS_DF
4171 | OPTION_MASK_UPPER_REGS_SF
)) == 0)
4173 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4174 error ("-mfloat128-hardware requires full ISA 3.0 support");
4176 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4179 else if (TARGET_P9_VECTOR
&& !TARGET_FLOAT128_HW
4180 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) == 0)
4181 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_HW
;
4183 if (TARGET_FLOAT128_HW
4184 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128
) == 0)
4185 rs6000_isa_flags
|= OPTION_MASK_FLOAT128
;
4187 /* Print the options after updating the defaults. */
4188 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4189 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
4191 /* E500mc does "better" if we inline more aggressively. Respect the
4192 user's opinion, though. */
4193 if (rs6000_block_move_inline_limit
== 0
4194 && (rs6000_cpu
== PROCESSOR_PPCE500MC
4195 || rs6000_cpu
== PROCESSOR_PPCE500MC64
4196 || rs6000_cpu
== PROCESSOR_PPCE5500
4197 || rs6000_cpu
== PROCESSOR_PPCE6500
))
4198 rs6000_block_move_inline_limit
= 128;
4200 /* store_one_arg depends on expand_block_move to handle at least the
4201 size of reg_parm_stack_space. */
4202 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
4203 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
4207 /* If the appropriate debug option is enabled, replace the target hooks
4208 with debug versions that call the real version and then prints
4209 debugging information. */
4210 if (TARGET_DEBUG_COST
)
4212 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
4213 targetm
.address_cost
= rs6000_debug_address_cost
;
4214 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
4217 if (TARGET_DEBUG_ADDR
)
4219 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
4220 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
4221 rs6000_secondary_reload_class_ptr
4222 = rs6000_debug_secondary_reload_class
;
4223 rs6000_secondary_memory_needed_ptr
4224 = rs6000_debug_secondary_memory_needed
;
4225 rs6000_cannot_change_mode_class_ptr
4226 = rs6000_debug_cannot_change_mode_class
;
4227 rs6000_preferred_reload_class_ptr
4228 = rs6000_debug_preferred_reload_class
;
4229 rs6000_legitimize_reload_address_ptr
4230 = rs6000_debug_legitimize_reload_address
;
4231 rs6000_mode_dependent_address_ptr
4232 = rs6000_debug_mode_dependent_address
;
4235 if (rs6000_veclibabi_name
)
4237 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
4238 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
4241 error ("unknown vectorization library ABI type (%s) for "
4242 "-mveclibabi= switch", rs6000_veclibabi_name
);
4248 if (!global_options_set
.x_rs6000_long_double_type_size
)
4250 if (main_target_opt
!= NULL
4251 && (main_target_opt
->x_rs6000_long_double_type_size
4252 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
4253 error ("target attribute or pragma changes long double size");
4255 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
4258 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
4259 if (!global_options_set
.x_rs6000_ieeequad
)
4260 rs6000_ieeequad
= 1;
4263 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4264 target attribute or pragma which automatically enables both options,
4265 unless the altivec ABI was set. This is set by default for 64-bit, but
4267 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4268 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
4269 | OPTION_MASK_FLOAT128
)
4270 & ~rs6000_isa_flags_explicit
);
4272 /* Enable Altivec ABI for AIX -maltivec. */
4273 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
4275 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4276 error ("target attribute or pragma changes AltiVec ABI");
4278 rs6000_altivec_abi
= 1;
4281 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4282 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4283 be explicitly overridden in either case. */
4286 if (!global_options_set
.x_rs6000_altivec_abi
4287 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
4289 if (main_target_opt
!= NULL
&&
4290 !main_target_opt
->x_rs6000_altivec_abi
)
4291 error ("target attribute or pragma changes AltiVec ABI");
4293 rs6000_altivec_abi
= 1;
4297 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4298 So far, the only darwin64 targets are also MACH-O. */
4300 && DEFAULT_ABI
== ABI_DARWIN
4303 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
4304 error ("target attribute or pragma changes darwin64 ABI");
4307 rs6000_darwin64_abi
= 1;
4308 /* Default to natural alignment, for better performance. */
4309 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
4313 /* Place FP constants in the constant pool instead of TOC
4314 if section anchors enabled. */
4315 if (flag_section_anchors
4316 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
4317 TARGET_NO_FP_IN_TOC
= 1;
4319 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4320 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
4322 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4323 SUBTARGET_OVERRIDE_OPTIONS
;
4325 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4326 SUBSUBTARGET_OVERRIDE_OPTIONS
;
4328 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4329 SUB3TARGET_OVERRIDE_OPTIONS
;
4332 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4333 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
4335 /* For the E500 family of cores, reset the single/double FP flags to let us
4336 check that they remain constant across attributes or pragmas. Also,
4337 clear a possible request for string instructions, not supported and which
4338 we might have silently queried above for -Os.
4340 For other families, clear ISEL in case it was set implicitly.
4345 case PROCESSOR_PPC8540
:
4346 case PROCESSOR_PPC8548
:
4347 case PROCESSOR_PPCE500MC
:
4348 case PROCESSOR_PPCE500MC64
:
4349 case PROCESSOR_PPCE5500
:
4350 case PROCESSOR_PPCE6500
:
4352 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
4353 rs6000_double_float
= TARGET_E500_DOUBLE
;
4355 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
4361 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
4362 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
4367 if (main_target_opt
)
4369 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
4370 error ("target attribute or pragma changes single precision floating "
4372 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
4373 error ("target attribute or pragma changes double precision floating "
4377 /* Detect invalid option combinations with E500. */
4380 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
4381 && rs6000_cpu
!= PROCESSOR_POWER5
4382 && rs6000_cpu
!= PROCESSOR_POWER6
4383 && rs6000_cpu
!= PROCESSOR_POWER7
4384 && rs6000_cpu
!= PROCESSOR_POWER8
4385 && rs6000_cpu
!= PROCESSOR_POWER9
4386 && rs6000_cpu
!= PROCESSOR_PPCA2
4387 && rs6000_cpu
!= PROCESSOR_CELL
4388 && rs6000_cpu
!= PROCESSOR_PPC476
);
4389 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
4390 || rs6000_cpu
== PROCESSOR_POWER5
4391 || rs6000_cpu
== PROCESSOR_POWER7
4392 || rs6000_cpu
== PROCESSOR_POWER8
4393 || rs6000_cpu
== PROCESSOR_POWER9
);
4394 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
4395 || rs6000_cpu
== PROCESSOR_POWER5
4396 || rs6000_cpu
== PROCESSOR_POWER6
4397 || rs6000_cpu
== PROCESSOR_POWER7
4398 || rs6000_cpu
== PROCESSOR_POWER8
4399 || rs6000_cpu
== PROCESSOR_POWER9
4400 || rs6000_cpu
== PROCESSOR_PPCE500MC
4401 || rs6000_cpu
== PROCESSOR_PPCE500MC64
4402 || rs6000_cpu
== PROCESSOR_PPCE5500
4403 || rs6000_cpu
== PROCESSOR_PPCE6500
);
4405 /* Allow debug switches to override the above settings. These are set to -1
4406 in rs6000.opt to indicate the user hasn't directly set the switch. */
4407 if (TARGET_ALWAYS_HINT
>= 0)
4408 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
4410 if (TARGET_SCHED_GROUPS
>= 0)
4411 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
4413 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
4414 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
4416 rs6000_sched_restricted_insns_priority
4417 = (rs6000_sched_groups
? 1 : 0);
4419 /* Handle -msched-costly-dep option. */
4420 rs6000_sched_costly_dep
4421 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
4423 if (rs6000_sched_costly_dep_str
)
4425 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
4426 rs6000_sched_costly_dep
= no_dep_costly
;
4427 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
4428 rs6000_sched_costly_dep
= all_deps_costly
;
4429 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
4430 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
4431 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
4432 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4434 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4435 atoi (rs6000_sched_costly_dep_str
));
4438 /* Handle -minsert-sched-nops option. */
4439 rs6000_sched_insert_nops
4440 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4442 if (rs6000_sched_insert_nops_str
)
4444 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4445 rs6000_sched_insert_nops
= sched_finish_none
;
4446 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4447 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4448 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4449 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4451 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4452 atoi (rs6000_sched_insert_nops_str
));
4457 #ifdef TARGET_REGNAMES
4458 /* If the user desires alternate register names, copy in the
4459 alternate names now. */
4460 if (TARGET_REGNAMES
)
4461 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
4464 /* Set aix_struct_return last, after the ABI is determined.
4465 If -maix-struct-return or -msvr4-struct-return was explicitly
4466 used, don't override with the ABI default. */
4467 if (!global_options_set
.x_aix_struct_return
)
4468 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
4471 /* IBM XL compiler defaults to unsigned bitfields. */
4472 if (TARGET_XL_COMPAT
)
4473 flag_signed_bitfields
= 0;
4476 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
4477 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
4480 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
4482 /* We can only guarantee the availability of DI pseudo-ops when
4483 assembling for 64-bit targets. */
4486 targetm
.asm_out
.aligned_op
.di
= NULL
;
4487 targetm
.asm_out
.unaligned_op
.di
= NULL
;
4491 /* Set branch target alignment, if not optimizing for size. */
4494 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4495 aligned 8byte to avoid misprediction by the branch predictor. */
4496 if (rs6000_cpu
== PROCESSOR_TITAN
4497 || rs6000_cpu
== PROCESSOR_CELL
)
4499 if (align_functions
<= 0)
4500 align_functions
= 8;
4501 if (align_jumps
<= 0)
4503 if (align_loops
<= 0)
4506 if (rs6000_align_branch_targets
)
4508 if (align_functions
<= 0)
4509 align_functions
= 16;
4510 if (align_jumps
<= 0)
4512 if (align_loops
<= 0)
4514 can_override_loop_align
= 1;
4518 if (align_jumps_max_skip
<= 0)
4519 align_jumps_max_skip
= 15;
4520 if (align_loops_max_skip
<= 0)
4521 align_loops_max_skip
= 15;
4524 /* Arrange to save and restore machine status around nested functions. */
4525 init_machine_status
= rs6000_init_machine_status
;
4527 /* We should always be splitting complex arguments, but we can't break
4528 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4529 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4530 targetm
.calls
.split_complex_arg
= NULL
;
4533 /* Initialize rs6000_cost with the appropriate target costs. */
4535 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4539 case PROCESSOR_RS64A
:
4540 rs6000_cost
= &rs64a_cost
;
4543 case PROCESSOR_MPCCORE
:
4544 rs6000_cost
= &mpccore_cost
;
4547 case PROCESSOR_PPC403
:
4548 rs6000_cost
= &ppc403_cost
;
4551 case PROCESSOR_PPC405
:
4552 rs6000_cost
= &ppc405_cost
;
4555 case PROCESSOR_PPC440
:
4556 rs6000_cost
= &ppc440_cost
;
4559 case PROCESSOR_PPC476
:
4560 rs6000_cost
= &ppc476_cost
;
4563 case PROCESSOR_PPC601
:
4564 rs6000_cost
= &ppc601_cost
;
4567 case PROCESSOR_PPC603
:
4568 rs6000_cost
= &ppc603_cost
;
4571 case PROCESSOR_PPC604
:
4572 rs6000_cost
= &ppc604_cost
;
4575 case PROCESSOR_PPC604e
:
4576 rs6000_cost
= &ppc604e_cost
;
4579 case PROCESSOR_PPC620
:
4580 rs6000_cost
= &ppc620_cost
;
4583 case PROCESSOR_PPC630
:
4584 rs6000_cost
= &ppc630_cost
;
4587 case PROCESSOR_CELL
:
4588 rs6000_cost
= &ppccell_cost
;
4591 case PROCESSOR_PPC750
:
4592 case PROCESSOR_PPC7400
:
4593 rs6000_cost
= &ppc750_cost
;
4596 case PROCESSOR_PPC7450
:
4597 rs6000_cost
= &ppc7450_cost
;
4600 case PROCESSOR_PPC8540
:
4601 case PROCESSOR_PPC8548
:
4602 rs6000_cost
= &ppc8540_cost
;
4605 case PROCESSOR_PPCE300C2
:
4606 case PROCESSOR_PPCE300C3
:
4607 rs6000_cost
= &ppce300c2c3_cost
;
4610 case PROCESSOR_PPCE500MC
:
4611 rs6000_cost
= &ppce500mc_cost
;
4614 case PROCESSOR_PPCE500MC64
:
4615 rs6000_cost
= &ppce500mc64_cost
;
4618 case PROCESSOR_PPCE5500
:
4619 rs6000_cost
= &ppce5500_cost
;
4622 case PROCESSOR_PPCE6500
:
4623 rs6000_cost
= &ppce6500_cost
;
4626 case PROCESSOR_TITAN
:
4627 rs6000_cost
= &titan_cost
;
4630 case PROCESSOR_POWER4
:
4631 case PROCESSOR_POWER5
:
4632 rs6000_cost
= &power4_cost
;
4635 case PROCESSOR_POWER6
:
4636 rs6000_cost
= &power6_cost
;
4639 case PROCESSOR_POWER7
:
4640 rs6000_cost
= &power7_cost
;
4643 case PROCESSOR_POWER8
:
4644 rs6000_cost
= &power8_cost
;
4647 case PROCESSOR_POWER9
:
4648 rs6000_cost
= &power9_cost
;
4651 case PROCESSOR_PPCA2
:
4652 rs6000_cost
= &ppca2_cost
;
4661 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
4662 rs6000_cost
->simultaneous_prefetches
,
4663 global_options
.x_param_values
,
4664 global_options_set
.x_param_values
);
4665 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
4666 global_options
.x_param_values
,
4667 global_options_set
.x_param_values
);
4668 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
4669 rs6000_cost
->cache_line_size
,
4670 global_options
.x_param_values
,
4671 global_options_set
.x_param_values
);
4672 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
4673 global_options
.x_param_values
,
4674 global_options_set
.x_param_values
);
4676 /* Increase loop peeling limits based on performance analysis. */
4677 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
4678 global_options
.x_param_values
,
4679 global_options_set
.x_param_values
);
4680 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
4681 global_options
.x_param_values
,
4682 global_options_set
.x_param_values
);
4684 /* If using typedef char *va_list, signal that
4685 __builtin_va_start (&ap, 0) can be optimized to
4686 ap = __builtin_next_arg (0). */
4687 if (DEFAULT_ABI
!= ABI_V4
)
4688 targetm
.expand_builtin_va_start
= NULL
;
4691 /* Set up single/double float flags.
4692 If TARGET_HARD_FLOAT is set, but neither single or double is set,
4693 then set both flags. */
4694 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4695 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
4696 rs6000_single_float
= rs6000_double_float
= 1;
4698 /* If not explicitly specified via option, decide whether to generate indexed
4699 load/store instructions. */
4700 if (TARGET_AVOID_XFORM
== -1)
4701 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4702 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4703 need indexed accesses and the type used is the scalar type of the element
4704 being loaded or stored. */
4705 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
4706 && !TARGET_ALTIVEC
);
4708 /* Set the -mrecip options. */
4709 if (rs6000_recip_name
)
4711 char *p
= ASTRDUP (rs6000_recip_name
);
4713 unsigned int mask
, i
;
4716 while ((q
= strtok (p
, ",")) != NULL
)
4727 if (!strcmp (q
, "default"))
4728 mask
= ((TARGET_RECIP_PRECISION
)
4729 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4732 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4733 if (!strcmp (q
, recip_options
[i
].string
))
4735 mask
= recip_options
[i
].mask
;
4739 if (i
== ARRAY_SIZE (recip_options
))
4741 error ("unknown option for -mrecip=%s", q
);
4749 rs6000_recip_control
&= ~mask
;
4751 rs6000_recip_control
|= mask
;
4755 /* Set the builtin mask of the various options used that could affect which
4756 builtins were used. In the past we used target_flags, but we've run out
4757 of bits, and some options like SPE and PAIRED are no longer in
4759 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4760 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4761 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
4762 rs6000_builtin_mask
);
4764 /* Initialize all of the registers. */
4765 rs6000_init_hard_regno_mode_ok (global_init_p
);
4767 /* Save the initial options in case the user does function specific options */
4769 target_option_default_node
= target_option_current_node
4770 = build_target_option_node (&global_options
);
4772 /* If not explicitly specified via option, decide whether to generate the
4773 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4774 if (TARGET_LINK_STACK
== -1)
4775 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4780 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4781 define the target cpu type. */
4784 rs6000_option_override (void)
4786 (void) rs6000_option_override_internal (true);
4788 /* Register machine-specific passes. This needs to be done at start-up.
4789 It's convenient to do it here (like i386 does). */
4790 opt_pass
*pass_analyze_swaps
= make_pass_analyze_swaps (g
);
4792 struct register_pass_info analyze_swaps_info
4793 = { pass_analyze_swaps
, "cse1", 1, PASS_POS_INSERT_BEFORE
};
4795 register_pass (&analyze_swaps_info
);
4799 /* Implement targetm.vectorize.builtin_mask_for_load. */
4801 rs6000_builtin_mask_for_load (void)
4803 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4804 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
4805 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
4806 return altivec_builtin_mask_for_load
;
4811 /* Implement LOOP_ALIGN. */
4813 rs6000_loop_align (rtx label
)
4818 /* Don't override loop alignment if -falign-loops was specified. */
4819 if (!can_override_loop_align
)
4820 return align_loops_log
;
4822 bb
= BLOCK_FOR_INSN (label
);
4823 ninsns
= num_loop_insns(bb
->loop_father
);
4825 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4826 if (ninsns
> 4 && ninsns
<= 8
4827 && (rs6000_cpu
== PROCESSOR_POWER4
4828 || rs6000_cpu
== PROCESSOR_POWER5
4829 || rs6000_cpu
== PROCESSOR_POWER6
4830 || rs6000_cpu
== PROCESSOR_POWER7
4831 || rs6000_cpu
== PROCESSOR_POWER8
4832 || rs6000_cpu
== PROCESSOR_POWER9
))
4835 return align_loops_log
;
4838 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4840 rs6000_loop_align_max_skip (rtx_insn
*label
)
4842 return (1 << rs6000_loop_align (label
)) - 1;
4845 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4846 after applying N number of iterations. This routine does not determine
4847 how may iterations are required to reach desired alignment. */
4850 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4857 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4860 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4870 /* Assuming that all other types are naturally aligned. CHECKME! */
4875 /* Return true if the vector misalignment factor is supported by the
4878 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
4885 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4888 /* Return if movmisalign pattern is not supported for this mode. */
4889 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4892 if (misalignment
== -1)
4894 /* Misalignment factor is unknown at compile time but we know
4895 it's word aligned. */
4896 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4898 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4900 if (element_size
== 64 || element_size
== 32)
4907 /* VSX supports word-aligned vector. */
4908 if (misalignment
% 4 == 0)
4914 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4916 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4917 tree vectype
, int misalign
)
4922 switch (type_of_cost
)
4932 case cond_branch_not_taken
:
4941 case vec_promote_demote
:
4947 case cond_branch_taken
:
4950 case unaligned_load
:
4951 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4954 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4956 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4958 /* Double word aligned. */
4966 /* Double word aligned. */
4970 /* Unknown misalignment. */
4983 /* Misaligned loads are not supported. */
4988 case unaligned_store
:
4989 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4992 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4994 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4996 /* Double word aligned. */
5004 /* Double word aligned. */
5008 /* Unknown misalignment. */
5021 /* Misaligned stores are not supported. */
5027 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5028 elem_type
= TREE_TYPE (vectype
);
5029 /* 32-bit vectors loaded into registers are stored as double
5030 precision, so we need n/2 converts in addition to the usual
5031 n/2 merges to construct a vector of short floats from them. */
5032 if (SCALAR_FLOAT_TYPE_P (elem_type
)
5033 && TYPE_PRECISION (elem_type
) == 32)
5034 return elements
+ 1;
5036 return elements
/ 2 + 1;
5043 /* Implement targetm.vectorize.preferred_simd_mode. */
5046 rs6000_preferred_simd_mode (machine_mode mode
)
5055 if (TARGET_ALTIVEC
|| TARGET_VSX
)
5081 if (TARGET_PAIRED_FLOAT
5087 typedef struct _rs6000_cost_data
5089 struct loop
*loop_info
;
5093 /* Test for likely overcommitment of vector hardware resources. If a
5094 loop iteration is relatively large, and too large a percentage of
5095 instructions in the loop are vectorized, the cost model may not
5096 adequately reflect delays from unavailable vector resources.
5097 Penalize the loop body cost for this case. */
5100 rs6000_density_test (rs6000_cost_data
*data
)
5102 const int DENSITY_PCT_THRESHOLD
= 85;
5103 const int DENSITY_SIZE_THRESHOLD
= 70;
5104 const int DENSITY_PENALTY
= 10;
5105 struct loop
*loop
= data
->loop_info
;
5106 basic_block
*bbs
= get_loop_body (loop
);
5107 int nbbs
= loop
->num_nodes
;
5108 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
5111 for (i
= 0; i
< nbbs
; i
++)
5113 basic_block bb
= bbs
[i
];
5114 gimple_stmt_iterator gsi
;
5116 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
5118 gimple
*stmt
= gsi_stmt (gsi
);
5119 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
5121 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
5122 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
5128 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
5130 if (density_pct
> DENSITY_PCT_THRESHOLD
5131 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
5133 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
5134 if (dump_enabled_p ())
5135 dump_printf_loc (MSG_NOTE
, vect_location
,
5136 "density %d%%, cost %d exceeds threshold, penalizing "
5137 "loop body cost by %d%%", density_pct
,
5138 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
5142 /* Implement targetm.vectorize.init_cost. */
5145 rs6000_init_cost (struct loop
*loop_info
)
5147 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
5148 data
->loop_info
= loop_info
;
5149 data
->cost
[vect_prologue
] = 0;
5150 data
->cost
[vect_body
] = 0;
5151 data
->cost
[vect_epilogue
] = 0;
5155 /* Implement targetm.vectorize.add_stmt_cost. */
5158 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
5159 struct _stmt_vec_info
*stmt_info
, int misalign
,
5160 enum vect_cost_model_location where
)
5162 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5163 unsigned retval
= 0;
5165 if (flag_vect_cost_model
)
5167 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
5168 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
5170 /* Statements in an inner loop relative to the loop being
5171 vectorized are weighted more heavily. The value here is
5172 arbitrary and could potentially be improved with analysis. */
5173 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
5174 count
*= 50; /* FIXME. */
5176 retval
= (unsigned) (count
* stmt_cost
);
5177 cost_data
->cost
[where
] += retval
;
5183 /* Implement targetm.vectorize.finish_cost. */
5186 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
5187 unsigned *body_cost
, unsigned *epilogue_cost
)
5189 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5191 if (cost_data
->loop_info
)
5192 rs6000_density_test (cost_data
);
5194 *prologue_cost
= cost_data
->cost
[vect_prologue
];
5195 *body_cost
= cost_data
->cost
[vect_body
];
5196 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
5199 /* Implement targetm.vectorize.destroy_cost_data. */
5202 rs6000_destroy_cost_data (void *data
)
5207 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5208 library with vectorized intrinsics. */
5211 rs6000_builtin_vectorized_libmass (combined_fn fn
, tree type_out
,
5215 const char *suffix
= NULL
;
5216 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
5219 machine_mode el_mode
, in_mode
;
5222 /* Libmass is suitable for unsafe math only as it does not correctly support
5223 parts of IEEE with the required precision such as denormals. Only support
5224 it if we have VSX to use the simd d2 or f4 functions.
5225 XXX: Add variable length support. */
5226 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
5229 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5230 n
= TYPE_VECTOR_SUBPARTS (type_out
);
5231 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5232 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5233 if (el_mode
!= in_mode
5269 if (el_mode
== DFmode
&& n
== 2)
5271 bdecl
= mathfn_built_in (double_type_node
, fn
);
5272 suffix
= "d2"; /* pow -> powd2 */
5274 else if (el_mode
== SFmode
&& n
== 4)
5276 bdecl
= mathfn_built_in (float_type_node
, fn
);
5277 suffix
= "4"; /* powf -> powf4 */
5289 gcc_assert (suffix
!= NULL
);
5290 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
5294 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
5295 strcat (name
, suffix
);
5298 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
5299 else if (n_args
== 2)
5300 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
5304 /* Build a function declaration for the vectorized function. */
5305 new_fndecl
= build_decl (BUILTINS_LOCATION
,
5306 FUNCTION_DECL
, get_identifier (name
), fntype
);
5307 TREE_PUBLIC (new_fndecl
) = 1;
5308 DECL_EXTERNAL (new_fndecl
) = 1;
5309 DECL_IS_NOVOPS (new_fndecl
) = 1;
5310 TREE_READONLY (new_fndecl
) = 1;
5315 /* Returns a function decl for a vectorized version of the builtin function
5316 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5317 if it is not available. */
5320 rs6000_builtin_vectorized_function (unsigned int fn
, tree type_out
,
5323 machine_mode in_mode
, out_mode
;
5326 if (TARGET_DEBUG_BUILTIN
)
5327 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5328 combined_fn_name (combined_fn (fn
)),
5329 GET_MODE_NAME (TYPE_MODE (type_out
)),
5330 GET_MODE_NAME (TYPE_MODE (type_in
)));
5332 if (TREE_CODE (type_out
) != VECTOR_TYPE
5333 || TREE_CODE (type_in
) != VECTOR_TYPE
5334 || !TARGET_VECTORIZE_BUILTINS
)
5337 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5338 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5339 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5340 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5345 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5346 && out_mode
== DFmode
&& out_n
== 2
5347 && in_mode
== DFmode
&& in_n
== 2)
5348 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
5349 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5350 && out_mode
== SFmode
&& out_n
== 4
5351 && in_mode
== SFmode
&& in_n
== 4)
5352 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
5353 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5354 && out_mode
== SFmode
&& out_n
== 4
5355 && in_mode
== SFmode
&& in_n
== 4)
5356 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
5359 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5360 && out_mode
== DFmode
&& out_n
== 2
5361 && in_mode
== DFmode
&& in_n
== 2)
5362 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5363 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5364 && out_mode
== SFmode
&& out_n
== 4
5365 && in_mode
== SFmode
&& in_n
== 4)
5366 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5367 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5368 && out_mode
== SFmode
&& out_n
== 4
5369 && in_mode
== SFmode
&& in_n
== 4)
5370 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5373 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5374 && out_mode
== DFmode
&& out_n
== 2
5375 && in_mode
== DFmode
&& in_n
== 2)
5376 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5377 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5378 && out_mode
== SFmode
&& out_n
== 4
5379 && in_mode
== SFmode
&& in_n
== 4)
5380 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5381 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5382 && out_mode
== SFmode
&& out_n
== 4
5383 && in_mode
== SFmode
&& in_n
== 4)
5384 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5387 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5388 && out_mode
== DFmode
&& out_n
== 2
5389 && in_mode
== DFmode
&& in_n
== 2)
5390 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5391 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5392 && out_mode
== SFmode
&& out_n
== 4
5393 && in_mode
== SFmode
&& in_n
== 4)
5394 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5395 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5396 && out_mode
== SFmode
&& out_n
== 4
5397 && in_mode
== SFmode
&& in_n
== 4)
5398 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5401 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5402 && out_mode
== DFmode
&& out_n
== 2
5403 && in_mode
== DFmode
&& in_n
== 2)
5404 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5405 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5406 && out_mode
== SFmode
&& out_n
== 4
5407 && in_mode
== SFmode
&& in_n
== 4)
5408 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5409 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5410 && out_mode
== SFmode
&& out_n
== 4
5411 && in_mode
== SFmode
&& in_n
== 4)
5412 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5415 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5416 && flag_unsafe_math_optimizations
5417 && out_mode
== DFmode
&& out_n
== 2
5418 && in_mode
== DFmode
&& in_n
== 2)
5419 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5420 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5421 && flag_unsafe_math_optimizations
5422 && out_mode
== SFmode
&& out_n
== 4
5423 && in_mode
== SFmode
&& in_n
== 4)
5424 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5427 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5428 && !flag_trapping_math
5429 && out_mode
== DFmode
&& out_n
== 2
5430 && in_mode
== DFmode
&& in_n
== 2)
5431 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5432 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5433 && !flag_trapping_math
5434 && out_mode
== SFmode
&& out_n
== 4
5435 && in_mode
== SFmode
&& in_n
== 4)
5436 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5442 /* Generate calls to libmass if appropriate. */
5443 if (rs6000_veclib_handler
)
5444 return rs6000_veclib_handler (combined_fn (fn
), type_out
, type_in
);
5449 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5452 rs6000_builtin_md_vectorized_function (tree fndecl
, tree type_out
,
5455 machine_mode in_mode
, out_mode
;
5458 if (TARGET_DEBUG_BUILTIN
)
5459 fprintf (stderr
, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5460 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
5461 GET_MODE_NAME (TYPE_MODE (type_out
)),
5462 GET_MODE_NAME (TYPE_MODE (type_in
)));
5464 if (TREE_CODE (type_out
) != VECTOR_TYPE
5465 || TREE_CODE (type_in
) != VECTOR_TYPE
5466 || !TARGET_VECTORIZE_BUILTINS
)
5469 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5470 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5471 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5472 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5474 enum rs6000_builtins fn
5475 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
5478 case RS6000_BUILTIN_RSQRTF
:
5479 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5480 && out_mode
== SFmode
&& out_n
== 4
5481 && in_mode
== SFmode
&& in_n
== 4)
5482 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5484 case RS6000_BUILTIN_RSQRT
:
5485 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5486 && out_mode
== DFmode
&& out_n
== 2
5487 && in_mode
== DFmode
&& in_n
== 2)
5488 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5490 case RS6000_BUILTIN_RECIPF
:
5491 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5492 && out_mode
== SFmode
&& out_n
== 4
5493 && in_mode
== SFmode
&& in_n
== 4)
5494 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5496 case RS6000_BUILTIN_RECIP
:
5497 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5498 && out_mode
== DFmode
&& out_n
== 2
5499 && in_mode
== DFmode
&& in_n
== 2)
5500 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5508 /* Default CPU string for rs6000*_file_start functions. */
5509 static const char *rs6000_default_cpu
;
5511 /* Do anything needed at the start of the asm file. */
5514 rs6000_file_start (void)
5517 const char *start
= buffer
;
5518 FILE *file
= asm_out_file
;
5520 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5522 default_file_start ();
5524 if (flag_verbose_asm
)
5526 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5528 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5530 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5534 if (global_options_set
.x_rs6000_cpu_index
)
5536 fprintf (file
, "%s -mcpu=%s", start
,
5537 processor_target_table
[rs6000_cpu_index
].name
);
5541 if (global_options_set
.x_rs6000_tune_index
)
5543 fprintf (file
, "%s -mtune=%s", start
,
5544 processor_target_table
[rs6000_tune_index
].name
);
5548 if (PPC405_ERRATUM77
)
5550 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5554 #ifdef USING_ELFOS_H
5555 switch (rs6000_sdata
)
5557 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5558 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5559 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5560 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5563 if (rs6000_sdata
&& g_switch_value
)
5565 fprintf (file
, "%s -G %d", start
,
5575 #ifdef USING_ELFOS_H
5576 if (rs6000_default_cpu
== 0 || rs6000_default_cpu
[0] == '\0'
5577 || !global_options_set
.x_rs6000_cpu_index
)
5579 fputs ("\t.machine ", asm_out_file
);
5580 if ((rs6000_isa_flags
& OPTION_MASK_MODULO
) != 0)
5581 fputs ("power9\n", asm_out_file
);
5582 else if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5583 fputs ("power8\n", asm_out_file
);
5584 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5585 fputs ("power7\n", asm_out_file
);
5586 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5587 fputs ("power6\n", asm_out_file
);
5588 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5589 fputs ("power5\n", asm_out_file
);
5590 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5591 fputs ("power4\n", asm_out_file
);
5592 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5593 fputs ("ppc64\n", asm_out_file
);
5595 fputs ("ppc\n", asm_out_file
);
5599 if (DEFAULT_ABI
== ABI_ELFv2
)
5600 fprintf (file
, "\t.abiversion 2\n");
5602 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
5603 || (TARGET_ELF
&& flag_pic
== 2))
5605 switch_to_section (toc_section
);
5606 switch_to_section (text_section
);
5611 /* Return nonzero if this function is known to have a null epilogue. */
5614 direct_return (void)
5616 if (reload_completed
)
5618 rs6000_stack_t
*info
= rs6000_stack_info ();
5620 if (info
->first_gp_reg_save
== 32
5621 && info
->first_fp_reg_save
== 64
5622 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
5623 && ! info
->lr_save_p
5624 && ! info
->cr_save_p
5625 && info
->vrsave_size
== 0
5633 /* Return the number of instructions it takes to form a constant in an
5634 integer register. */
5637 num_insns_constant_wide (HOST_WIDE_INT value
)
5639 /* signed constant loadable with addi */
5640 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
5643 /* constant loadable with addis */
5644 else if ((value
& 0xffff) == 0
5645 && (value
>> 31 == -1 || value
>> 31 == 0))
5648 else if (TARGET_POWERPC64
)
5650 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
5651 HOST_WIDE_INT high
= value
>> 31;
5653 if (high
== 0 || high
== -1)
5659 return num_insns_constant_wide (high
) + 1;
5661 return num_insns_constant_wide (low
) + 1;
5663 return (num_insns_constant_wide (high
)
5664 + num_insns_constant_wide (low
) + 1);
5672 num_insns_constant (rtx op
, machine_mode mode
)
5674 HOST_WIDE_INT low
, high
;
5676 switch (GET_CODE (op
))
5679 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
5680 && rs6000_is_valid_and_mask (op
, mode
))
5683 return num_insns_constant_wide (INTVAL (op
));
5685 case CONST_WIDE_INT
:
5688 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
5689 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5690 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
5695 if (mode
== SFmode
|| mode
== SDmode
)
5699 if (DECIMAL_FLOAT_MODE_P (mode
))
5700 REAL_VALUE_TO_TARGET_DECIMAL32
5701 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5703 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5704 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5708 if (DECIMAL_FLOAT_MODE_P (mode
))
5709 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5711 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
5712 high
= l
[WORDS_BIG_ENDIAN
== 0];
5713 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5716 return (num_insns_constant_wide (low
)
5717 + num_insns_constant_wide (high
));
5720 if ((high
== 0 && low
>= 0)
5721 || (high
== -1 && low
< 0))
5722 return num_insns_constant_wide (low
);
5724 else if (rs6000_is_valid_and_mask (op
, mode
))
5728 return num_insns_constant_wide (high
) + 1;
5731 return (num_insns_constant_wide (high
)
5732 + num_insns_constant_wide (low
) + 1);
5740 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5741 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5742 corresponding element of the vector, but for V4SFmode and V2SFmode,
5743 the corresponding "float" is interpreted as an SImode integer. */
5746 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5750 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5751 gcc_assert (GET_MODE (op
) != V2DImode
5752 && GET_MODE (op
) != V2DFmode
);
5754 tmp
= CONST_VECTOR_ELT (op
, elt
);
5755 if (GET_MODE (op
) == V4SFmode
5756 || GET_MODE (op
) == V2SFmode
)
5757 tmp
= gen_lowpart (SImode
, tmp
);
5758 return INTVAL (tmp
);
5761 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5762 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5763 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5764 all items are set to the same value and contain COPIES replicas of the
5765 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5766 operand and the others are set to the value of the operand's msb. */
5769 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5771 machine_mode mode
= GET_MODE (op
);
5772 machine_mode inner
= GET_MODE_INNER (mode
);
5780 HOST_WIDE_INT splat_val
;
5781 HOST_WIDE_INT msb_val
;
5783 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5786 nunits
= GET_MODE_NUNITS (mode
);
5787 bitsize
= GET_MODE_BITSIZE (inner
);
5788 mask
= GET_MODE_MASK (inner
);
5790 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5792 msb_val
= val
>= 0 ? 0 : -1;
5794 /* Construct the value to be splatted, if possible. If not, return 0. */
5795 for (i
= 2; i
<= copies
; i
*= 2)
5797 HOST_WIDE_INT small_val
;
5799 small_val
= splat_val
>> bitsize
;
5801 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5803 splat_val
= small_val
;
5806 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5807 if (EASY_VECTOR_15 (splat_val
))
5810 /* Also check if we can splat, and then add the result to itself. Do so if
5811 the value is positive, of if the splat instruction is using OP's mode;
5812 for splat_val < 0, the splat and the add should use the same mode. */
5813 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5814 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5817 /* Also check if are loading up the most significant bit which can be done by
5818 loading up -1 and shifting the value left by -1. */
5819 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5825 /* Check if VAL is present in every STEP-th element, and the
5826 other elements are filled with its most significant bit. */
5827 for (i
= 1; i
< nunits
; ++i
)
5829 HOST_WIDE_INT desired_val
;
5830 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5831 if ((i
& (step
- 1)) == 0)
5834 desired_val
= msb_val
;
5836 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5843 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
5844 instruction, filling in the bottom elements with 0 or -1.
5846 Return 0 if the constant cannot be generated with VSLDOI. Return positive
5847 for the number of zeroes to shift in, or negative for the number of 0xff
5850 OP is a CONST_VECTOR. */
5853 vspltis_shifted (rtx op
)
5855 machine_mode mode
= GET_MODE (op
);
5856 machine_mode inner
= GET_MODE_INNER (mode
);
5864 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
5867 /* We need to create pseudo registers to do the shift, so don't recognize
5868 shift vector constants after reload. */
5869 if (!can_create_pseudo_p ())
5872 nunits
= GET_MODE_NUNITS (mode
);
5873 mask
= GET_MODE_MASK (inner
);
5875 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
5877 /* Check if the value can really be the operand of a vspltis[bhw]. */
5878 if (EASY_VECTOR_15 (val
))
5881 /* Also check if we are loading up the most significant bit which can be done
5882 by loading up -1 and shifting the value left by -1. */
5883 else if (EASY_VECTOR_MSB (val
, inner
))
5889 /* Check if VAL is present in every STEP-th element until we find elements
5890 that are 0 or all 1 bits. */
5891 for (i
= 1; i
< nunits
; ++i
)
5893 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
5894 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
5896 /* If the value isn't the splat value, check for the remaining elements
5902 for (j
= i
+1; j
< nunits
; ++j
)
5904 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
5905 if (const_vector_elt_as_int (op
, elt2
) != 0)
5909 return (nunits
- i
) * GET_MODE_SIZE (inner
);
5912 else if ((elt_val
& mask
) == mask
)
5914 for (j
= i
+1; j
< nunits
; ++j
)
5916 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
5917 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
5921 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
5929 /* If all elements are equal, we don't need to do VLSDOI. */
5934 /* Return true if OP is of the given MODE and can be synthesized
5935 with a vspltisb, vspltish or vspltisw. */
5938 easy_altivec_constant (rtx op
, machine_mode mode
)
5940 unsigned step
, copies
;
5942 if (mode
== VOIDmode
)
5943 mode
= GET_MODE (op
);
5944 else if (mode
!= GET_MODE (op
))
5947 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5949 if (mode
== V2DFmode
)
5950 return zero_constant (op
, mode
);
5952 else if (mode
== V2DImode
)
5954 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5955 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5958 if (zero_constant (op
, mode
))
5961 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5962 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5968 /* V1TImode is a special container for TImode. Ignore for now. */
5969 else if (mode
== V1TImode
)
5972 /* Start with a vspltisw. */
5973 step
= GET_MODE_NUNITS (mode
) / 4;
5976 if (vspltis_constant (op
, step
, copies
))
5979 /* Then try with a vspltish. */
5985 if (vspltis_constant (op
, step
, copies
))
5988 /* And finally a vspltisb. */
5994 if (vspltis_constant (op
, step
, copies
))
5997 if (vspltis_shifted (op
) != 0)
6003 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6004 result is OP. Abort if it is not possible. */
6007 gen_easy_altivec_constant (rtx op
)
6009 machine_mode mode
= GET_MODE (op
);
6010 int nunits
= GET_MODE_NUNITS (mode
);
6011 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6012 unsigned step
= nunits
/ 4;
6013 unsigned copies
= 1;
6015 /* Start with a vspltisw. */
6016 if (vspltis_constant (op
, step
, copies
))
6017 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
6019 /* Then try with a vspltish. */
6025 if (vspltis_constant (op
, step
, copies
))
6026 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
6028 /* And finally a vspltisb. */
6034 if (vspltis_constant (op
, step
, copies
))
6035 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
6041 output_vec_const_move (rtx
*operands
)
6043 int cst
, cst2
, shift
;
6049 mode
= GET_MODE (dest
);
6053 if (zero_constant (vec
, mode
))
6054 return "xxlxor %x0,%x0,%x0";
6056 if (TARGET_P8_VECTOR
&& vec
== CONSTM1_RTX (mode
))
6057 return "xxlorc %x0,%x0,%x0";
6059 if ((mode
== V2DImode
|| mode
== V1TImode
)
6060 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
6061 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
6062 return (TARGET_P8_VECTOR
) ? "xxlorc %x0,%x0,%x0" : "vspltisw %0,-1";
6068 if (zero_constant (vec
, mode
))
6069 return "vxor %0,%0,%0";
6071 /* Do we need to construct a value using VSLDOI? */
6072 shift
= vspltis_shifted (vec
);
6076 splat_vec
= gen_easy_altivec_constant (vec
);
6077 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
6078 operands
[1] = XEXP (splat_vec
, 0);
6079 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
6082 switch (GET_MODE (splat_vec
))
6085 return "vspltisw %0,%1";
6088 return "vspltish %0,%1";
6091 return "vspltisb %0,%1";
6098 gcc_assert (TARGET_SPE
);
6100 /* Vector constant 0 is handled as a splitter of V2SI, and in the
6101 pattern of V1DI, V4HI, and V2SF.
6103 FIXME: We should probably return # and add post reload
6104 splitters for these, but this way is so easy ;-). */
6105 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
6106 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
6107 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
6108 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
6110 return "li %0,%1\n\tevmergelo %0,%0,%0";
6111 else if (WORDS_BIG_ENDIAN
)
6112 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
6114 return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
6117 /* Initialize TARGET of vector PAIRED to VALS. */
6120 paired_expand_vector_init (rtx target
, rtx vals
)
6122 machine_mode mode
= GET_MODE (target
);
6123 int n_elts
= GET_MODE_NUNITS (mode
);
6125 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
6128 for (i
= 0; i
< n_elts
; ++i
)
6130 x
= XVECEXP (vals
, 0, i
);
6131 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6136 /* Load from constant pool. */
6137 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
6143 /* The vector is initialized only with non-constants. */
6144 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
6145 XVECEXP (vals
, 0, 1));
6147 emit_move_insn (target
, new_rtx
);
6151 /* One field is non-constant and the other one is a constant. Load the
6152 constant from the constant pool and use ps_merge instruction to
6153 construct the whole vector. */
6154 op1
= XVECEXP (vals
, 0, 0);
6155 op2
= XVECEXP (vals
, 0, 1);
6157 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
6159 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
6160 emit_move_insn (tmp
, constant_op
);
6162 if (CONSTANT_P (op1
))
6163 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
6165 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
6167 emit_move_insn (target
, new_rtx
);
6171 paired_expand_vector_move (rtx operands
[])
6173 rtx op0
= operands
[0], op1
= operands
[1];
6175 emit_move_insn (op0
, op1
);
6178 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6179 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6180 operands for the relation operation COND. This is a recursive
6184 paired_emit_vector_compare (enum rtx_code rcode
,
6185 rtx dest
, rtx op0
, rtx op1
,
6186 rtx cc_op0
, rtx cc_op1
)
6188 rtx tmp
= gen_reg_rtx (V2SFmode
);
6191 gcc_assert (TARGET_PAIRED_FLOAT
);
6192 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
6198 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6202 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
6203 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
6207 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
6210 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6213 tmp1
= gen_reg_rtx (V2SFmode
);
6214 max
= gen_reg_rtx (V2SFmode
);
6215 min
= gen_reg_rtx (V2SFmode
);
6216 gen_reg_rtx (V2SFmode
);
6218 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
6219 emit_insn (gen_selv2sf4
6220 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
6221 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
6222 emit_insn (gen_selv2sf4
6223 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
6224 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
6225 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
6228 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6231 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6234 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6237 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6240 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6249 /* Emit vector conditional expression.
6250 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6251 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6254 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
6255 rtx cond
, rtx cc_op0
, rtx cc_op1
)
6257 enum rtx_code rcode
= GET_CODE (cond
);
6259 if (!TARGET_PAIRED_FLOAT
)
6262 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
6267 /* Initialize vector TARGET to VALS. */
6270 rs6000_expand_vector_init (rtx target
, rtx vals
)
6272 machine_mode mode
= GET_MODE (target
);
6273 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6274 int n_elts
= GET_MODE_NUNITS (mode
);
6275 int n_var
= 0, one_var
= -1;
6276 bool all_same
= true, all_const_zero
= true;
6280 for (i
= 0; i
< n_elts
; ++i
)
6282 x
= XVECEXP (vals
, 0, i
);
6283 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6284 ++n_var
, one_var
= i
;
6285 else if (x
!= CONST0_RTX (inner_mode
))
6286 all_const_zero
= false;
6288 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6294 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
6295 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
6296 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
6298 /* Zero register. */
6299 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (mode
, target
, target
)));
6302 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
6304 /* Splat immediate. */
6305 emit_insn (gen_rtx_SET (target
, const_vec
));
6310 /* Load from constant pool. */
6311 emit_move_insn (target
, const_vec
);
6316 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6317 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6319 rtx op0
= XVECEXP (vals
, 0, 0);
6320 rtx op1
= XVECEXP (vals
, 0, 1);
6323 if (!MEM_P (op0
) && !REG_P (op0
))
6324 op0
= force_reg (inner_mode
, op0
);
6325 if (mode
== V2DFmode
)
6326 emit_insn (gen_vsx_splat_v2df (target
, op0
));
6328 emit_insn (gen_vsx_splat_v2di (target
, op0
));
6332 op0
= force_reg (inner_mode
, op0
);
6333 op1
= force_reg (inner_mode
, op1
);
6334 if (mode
== V2DFmode
)
6335 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
6337 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
6342 /* With single precision floating point on VSX, know that internally single
6343 precision is actually represented as a double, and either make 2 V2DF
6344 vectors, and convert these vectors to single precision, or do one
6345 conversion, and splat the result to the other elements. */
6346 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
6350 rtx freg
= gen_reg_rtx (V4SFmode
);
6351 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
6352 rtx cvt
= ((TARGET_XSCVDPSPN
)
6353 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
6354 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
6357 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
6361 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
6362 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
6363 rtx flt_even
= gen_reg_rtx (V4SFmode
);
6364 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
6365 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
6366 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
6367 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
6368 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
6370 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
6371 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
6372 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6373 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6374 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
6379 /* Store value to stack temp. Load vector element. Splat. However, splat
6380 of 64-bit items is not supported on Altivec. */
6381 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
6383 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6384 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
6385 XVECEXP (vals
, 0, 0));
6386 x
= gen_rtx_UNSPEC (VOIDmode
,
6387 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6388 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6390 gen_rtx_SET (target
, mem
),
6392 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
6393 gen_rtx_PARALLEL (VOIDmode
,
6394 gen_rtvec (1, const0_rtx
)));
6395 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
6399 /* One field is non-constant. Load constant then overwrite
6403 rtx copy
= copy_rtx (vals
);
6405 /* Load constant part of vector, substitute neighboring value for
6407 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
6408 rs6000_expand_vector_init (target
, copy
);
6410 /* Insert variable. */
6411 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
6415 /* Construct the vector in memory one field at a time
6416 and load the whole vector. */
6417 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6418 for (i
= 0; i
< n_elts
; i
++)
6419 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
6420 i
* GET_MODE_SIZE (inner_mode
)),
6421 XVECEXP (vals
, 0, i
));
6422 emit_move_insn (target
, mem
);
6425 /* Set field ELT of TARGET to VAL. */
6428 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
6430 machine_mode mode
= GET_MODE (target
);
6431 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6432 rtx reg
= gen_reg_rtx (mode
);
6434 int width
= GET_MODE_SIZE (inner_mode
);
6437 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6439 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
6440 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
6441 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
6445 /* Simplify setting single element vectors like V1TImode. */
6446 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
6448 emit_move_insn (target
, gen_lowpart (mode
, val
));
6452 /* Load single variable value. */
6453 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6454 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
6455 x
= gen_rtx_UNSPEC (VOIDmode
,
6456 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6457 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6459 gen_rtx_SET (reg
, mem
),
6462 /* Linear sequence. */
6463 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
6464 for (i
= 0; i
< 16; ++i
)
6465 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
6467 /* Set permute mask to insert element into target. */
6468 for (i
= 0; i
< width
; ++i
)
6469 XVECEXP (mask
, 0, elt
*width
+ i
)
6470 = GEN_INT (i
+ 0x10);
6471 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
6473 if (BYTES_BIG_ENDIAN
)
6474 x
= gen_rtx_UNSPEC (mode
,
6475 gen_rtvec (3, target
, reg
,
6476 force_reg (V16QImode
, x
)),
6480 /* Invert selector. We prefer to generate VNAND on P8 so
6481 that future fusion opportunities can kick in, but must
6482 generate VNOR elsewhere. */
6483 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
6484 rtx iorx
= (TARGET_P8_VECTOR
6485 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
6486 : gen_rtx_AND (V16QImode
, notx
, notx
));
6487 rtx tmp
= gen_reg_rtx (V16QImode
);
6488 emit_insn (gen_rtx_SET (tmp
, iorx
));
6490 /* Permute with operands reversed and adjusted selector. */
6491 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
6495 emit_insn (gen_rtx_SET (target
, x
));
6498 /* Extract field ELT from VEC into TARGET. */
6501 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
6503 machine_mode mode
= GET_MODE (vec
);
6504 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6507 if (VECTOR_MEM_VSX_P (mode
))
6514 gcc_assert (elt
== 0 && inner_mode
== TImode
);
6515 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6518 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
6521 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
6524 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
6529 /* Allocate mode-sized buffer. */
6530 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6532 emit_move_insn (mem
, vec
);
6534 /* Add offset to field within buffer matching vector element. */
6535 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
6537 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
6540 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
6543 invalid_e500_subreg (rtx op
, machine_mode mode
)
6545 if (TARGET_E500_DOUBLE
)
6547 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
6548 subreg:TI and reg:TF. Decimal float modes are like integer
6549 modes (only low part of each register used) for this
6551 if (GET_CODE (op
) == SUBREG
6552 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
6553 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
6554 && REG_P (SUBREG_REG (op
))
6555 && (GET_MODE (SUBREG_REG (op
)) == DFmode
6556 || GET_MODE (SUBREG_REG (op
)) == TFmode
6557 || GET_MODE (SUBREG_REG (op
)) == IFmode
6558 || GET_MODE (SUBREG_REG (op
)) == KFmode
))
6561 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
6563 if (GET_CODE (op
) == SUBREG
6564 && (mode
== DFmode
|| mode
== TFmode
|| mode
== IFmode
6566 && REG_P (SUBREG_REG (op
))
6567 && (GET_MODE (SUBREG_REG (op
)) == DImode
6568 || GET_MODE (SUBREG_REG (op
)) == TImode
6569 || GET_MODE (SUBREG_REG (op
)) == PTImode
6570 || GET_MODE (SUBREG_REG (op
)) == DDmode
6571 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
6576 && GET_CODE (op
) == SUBREG
6578 && REG_P (SUBREG_REG (op
))
6579 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
6585 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
6586 selects whether the alignment is abi mandated, optional, or
6587 both abi and optional alignment. */
6590 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
6592 if (how
!= align_opt
)
6594 if (TREE_CODE (type
) == VECTOR_TYPE
)
6596 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
6597 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
6602 else if (align
< 128)
6605 else if (TARGET_E500_DOUBLE
6606 && TREE_CODE (type
) == REAL_TYPE
6607 && TYPE_MODE (type
) == DFmode
)
6614 if (how
!= align_abi
)
6616 if (TREE_CODE (type
) == ARRAY_TYPE
6617 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
6619 if (align
< BITS_PER_WORD
)
6620 align
= BITS_PER_WORD
;
6627 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
6630 rs6000_special_adjust_field_align_p (tree field
, unsigned int computed
)
6632 if (TARGET_ALTIVEC
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6634 if (computed
!= 128)
6637 if (!warned
&& warn_psabi
)
6640 inform (input_location
,
6641 "the layout of aggregates containing vectors with"
6642 " %d-byte alignment has changed in GCC 5",
6643 computed
/ BITS_PER_UNIT
);
6646 /* In current GCC there is no special case. */
6653 /* AIX increases natural record alignment to doubleword if the first
6654 field is an FP double while the FP fields remain word aligned. */
6657 rs6000_special_round_type_align (tree type
, unsigned int computed
,
6658 unsigned int specified
)
6660 unsigned int align
= MAX (computed
, specified
);
6661 tree field
= TYPE_FIELDS (type
);
6663 /* Skip all non field decls */
6664 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
6665 field
= DECL_CHAIN (field
);
6667 if (field
!= NULL
&& field
!= type
)
6669 type
= TREE_TYPE (field
);
6670 while (TREE_CODE (type
) == ARRAY_TYPE
)
6671 type
= TREE_TYPE (type
);
6673 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
6674 align
= MAX (align
, 64);
6680 /* Darwin increases record alignment to the natural alignment of
6684 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
6685 unsigned int specified
)
6687 unsigned int align
= MAX (computed
, specified
);
6689 if (TYPE_PACKED (type
))
6692 /* Find the first field, looking down into aggregates. */
6694 tree field
= TYPE_FIELDS (type
);
6695 /* Skip all non field decls */
6696 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
6697 field
= DECL_CHAIN (field
);
6700 /* A packed field does not contribute any extra alignment. */
6701 if (DECL_PACKED (field
))
6703 type
= TREE_TYPE (field
);
6704 while (TREE_CODE (type
) == ARRAY_TYPE
)
6705 type
= TREE_TYPE (type
);
6706 } while (AGGREGATE_TYPE_P (type
));
6708 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
6709 align
= MAX (align
, TYPE_ALIGN (type
));
6714 /* Return 1 for an operand in small memory on V.4/eabi. */
6717 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
6718 machine_mode mode ATTRIBUTE_UNUSED
)
6723 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
6726 if (DEFAULT_ABI
!= ABI_V4
)
6729 /* Vector and float memory instructions have a limited offset on the
6730 SPE, so using a vector or float variable directly as an operand is
6733 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
6736 if (GET_CODE (op
) == SYMBOL_REF
)
6739 else if (GET_CODE (op
) != CONST
6740 || GET_CODE (XEXP (op
, 0)) != PLUS
6741 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
6742 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
6747 rtx sum
= XEXP (op
, 0);
6748 HOST_WIDE_INT summand
;
6750 /* We have to be careful here, because it is the referenced address
6751 that must be 32k from _SDA_BASE_, not just the symbol. */
6752 summand
= INTVAL (XEXP (sum
, 1));
6753 if (summand
< 0 || summand
> g_switch_value
)
6756 sym_ref
= XEXP (sum
, 0);
6759 return SYMBOL_REF_SMALL_P (sym_ref
);
6765 /* Return true if either operand is a general purpose register. */
6768 gpr_or_gpr_p (rtx op0
, rtx op1
)
6770 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
6771 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
6774 /* Return true if this is a move direct operation between GPR registers and
6775 floating point/VSX registers. */
6778 direct_move_p (rtx op0
, rtx op1
)
6782 if (!REG_P (op0
) || !REG_P (op1
))
6785 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
6788 regno0
= REGNO (op0
);
6789 regno1
= REGNO (op1
);
6790 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
6793 if (INT_REGNO_P (regno0
))
6794 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
6796 else if (INT_REGNO_P (regno1
))
6798 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
6801 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
6808 /* Return true if this is a load or store quad operation. This function does
6809 not handle the atomic quad memory instructions. */
6812 quad_load_store_p (rtx op0
, rtx op1
)
6816 if (!TARGET_QUAD_MEMORY
)
6819 else if (REG_P (op0
) && MEM_P (op1
))
6820 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6821 && quad_memory_operand (op1
, GET_MODE (op1
))
6822 && !reg_overlap_mentioned_p (op0
, op1
));
6824 else if (MEM_P (op0
) && REG_P (op1
))
6825 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6826 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6831 if (TARGET_DEBUG_ADDR
)
6833 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6834 ret
? "true" : "false");
6835 debug_rtx (gen_rtx_SET (op0
, op1
));
6841 /* Given an address, return a constant offset term if one exists. */
6844 address_offset (rtx op
)
6846 if (GET_CODE (op
) == PRE_INC
6847 || GET_CODE (op
) == PRE_DEC
)
6849 else if (GET_CODE (op
) == PRE_MODIFY
6850 || GET_CODE (op
) == LO_SUM
)
6853 if (GET_CODE (op
) == CONST
)
6856 if (GET_CODE (op
) == PLUS
)
6859 if (CONST_INT_P (op
))
6865 /* Return true if the MEM operand is a memory operand suitable for use
6866 with a (full width, possibly multiple) gpr load/store. On
6867 powerpc64 this means the offset must be divisible by 4.
6868 Implements 'Y' constraint.
6870 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6871 a constraint function we know the operand has satisfied a suitable
6872 memory predicate. Also accept some odd rtl generated by reload
6873 (see rs6000_legitimize_reload_address for various forms). It is
6874 important that reload rtl be accepted by appropriate constraints
6875 but not by the operand predicate.
6877 Offsetting a lo_sum should not be allowed, except where we know by
6878 alignment that a 32k boundary is not crossed, but see the ???
6879 comment in rs6000_legitimize_reload_address. Note that by
6880 "offsetting" here we mean a further offset to access parts of the
6881 MEM. It's fine to have a lo_sum where the inner address is offset
6882 from a sym, since the same sym+offset will appear in the high part
6883 of the address calculation. */
6886 mem_operand_gpr (rtx op
, machine_mode mode
)
6888 unsigned HOST_WIDE_INT offset
;
6890 rtx addr
= XEXP (op
, 0);
6892 op
= address_offset (addr
);
6896 offset
= INTVAL (op
);
6897 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6900 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6904 if (GET_CODE (addr
) == LO_SUM
)
6905 /* For lo_sum addresses, we must allow any offset except one that
6906 causes a wrap, so test only the low 16 bits. */
6907 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6909 return offset
+ 0x8000 < 0x10000u
- extra
;
6912 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6915 reg_offset_addressing_ok_p (machine_mode mode
)
6929 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6930 TImode is not a vector mode, if we want to use the VSX registers to
6931 move it around, we need to restrict ourselves to reg+reg addressing.
6932 Similarly for IEEE 128-bit floating point that is passed in a single
6934 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6942 /* Paired vector modes. Only reg+reg addressing is valid. */
6943 if (TARGET_PAIRED_FLOAT
)
6948 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6949 addressing for the LFIWZX and STFIWX instructions. */
6950 if (TARGET_NO_SDMODE_STACK
)
6962 virtual_stack_registers_memory_p (rtx op
)
6966 if (GET_CODE (op
) == REG
)
6967 regnum
= REGNO (op
);
6969 else if (GET_CODE (op
) == PLUS
6970 && GET_CODE (XEXP (op
, 0)) == REG
6971 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6972 regnum
= REGNO (XEXP (op
, 0));
6977 return (regnum
>= FIRST_VIRTUAL_REGISTER
6978 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6981 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6982 is known to not straddle a 32k boundary. This function is used
6983 to determine whether -mcmodel=medium code can use TOC pointer
6984 relative addressing for OP. This means the alignment of the TOC
6985 pointer must also be taken into account, and unfortunately that is
6988 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
6989 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
6993 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6997 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6999 if (GET_CODE (op
) != SYMBOL_REF
)
7002 dsize
= GET_MODE_SIZE (mode
);
7003 decl
= SYMBOL_REF_DECL (op
);
7009 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7010 replacing memory addresses with an anchor plus offset. We
7011 could find the decl by rummaging around in the block->objects
7012 VEC for the given offset but that seems like too much work. */
7013 dalign
= BITS_PER_UNIT
;
7014 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
7015 && SYMBOL_REF_ANCHOR_P (op
)
7016 && SYMBOL_REF_BLOCK (op
) != NULL
)
7018 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
7020 dalign
= block
->alignment
;
7021 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
7023 else if (CONSTANT_POOL_ADDRESS_P (op
))
7025 /* It would be nice to have get_pool_align().. */
7026 machine_mode cmode
= get_pool_mode (op
);
7028 dalign
= GET_MODE_ALIGNMENT (cmode
);
7031 else if (DECL_P (decl
))
7033 dalign
= DECL_ALIGN (decl
);
7037 /* Allow BLKmode when the entire object is known to not
7038 cross a 32k boundary. */
7039 if (!DECL_SIZE_UNIT (decl
))
7042 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
7045 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
7049 dalign
/= BITS_PER_UNIT
;
7050 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7051 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7052 return dalign
>= dsize
;
7058 /* Find how many bits of the alignment we know for this access. */
7059 dalign
/= BITS_PER_UNIT
;
7060 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
7061 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
7063 lsb
= offset
& -offset
;
7067 return dalign
>= dsize
;
7071 constant_pool_expr_p (rtx op
)
7075 split_const (op
, &base
, &offset
);
7076 return (GET_CODE (base
) == SYMBOL_REF
7077 && CONSTANT_POOL_ADDRESS_P (base
)
7078 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
7081 static const_rtx tocrel_base
, tocrel_offset
;
7083 /* Return true if OP is a toc pointer relative address (the output
7084 of create_TOC_reference). If STRICT, do not match high part or
7085 non-split -mcmodel=large/medium toc pointer relative addresses. */
7088 toc_relative_expr_p (const_rtx op
, bool strict
)
7093 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7095 /* Only match the low part. */
7096 if (GET_CODE (op
) == LO_SUM
7097 && REG_P (XEXP (op
, 0))
7098 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
7105 tocrel_offset
= const0_rtx
;
7106 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
7108 tocrel_base
= XEXP (op
, 0);
7109 tocrel_offset
= XEXP (op
, 1);
7112 return (GET_CODE (tocrel_base
) == UNSPEC
7113 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
7116 /* Return true if X is a constant pool address, and also for cmodel=medium
7117 if X is a toc-relative address known to be offsettable within MODE. */
7120 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
7123 return (toc_relative_expr_p (x
, strict
)
7124 && (TARGET_CMODEL
!= CMODEL_MEDIUM
7125 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
7127 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
7128 INTVAL (tocrel_offset
), mode
)));
7132 legitimate_small_data_p (machine_mode mode
, rtx x
)
7134 return (DEFAULT_ABI
== ABI_V4
7135 && !flag_pic
&& !TARGET_TOC
7136 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
7137 && small_data_operand (x
, mode
));
7140 /* SPE offset addressing is limited to 5-bits worth of double words. */
7141 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
7144 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
7145 bool strict
, bool worst_case
)
7147 unsigned HOST_WIDE_INT offset
;
7150 if (GET_CODE (x
) != PLUS
)
7152 if (!REG_P (XEXP (x
, 0)))
7154 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
7156 if (!reg_offset_addressing_ok_p (mode
))
7157 return virtual_stack_registers_memory_p (x
);
7158 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
7160 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
7163 offset
= INTVAL (XEXP (x
, 1));
7171 /* SPE vector modes. */
7172 return SPE_CONST_OFFSET_OK (offset
);
7177 /* On e500v2, we may have:
7179 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
7181 Which gets addressed with evldd instructions. */
7182 if (TARGET_E500_DOUBLE
)
7183 return SPE_CONST_OFFSET_OK (offset
);
7185 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7187 if (VECTOR_MEM_VSX_P (mode
))
7192 if (!TARGET_POWERPC64
)
7194 else if (offset
& 3)
7201 if (TARGET_E500_DOUBLE
)
7202 return (SPE_CONST_OFFSET_OK (offset
)
7203 && SPE_CONST_OFFSET_OK (offset
+ 8));
7212 if (!TARGET_POWERPC64
)
7214 else if (offset
& 3)
7223 return offset
< 0x10000 - extra
;
7227 legitimate_indexed_address_p (rtx x
, int strict
)
7231 if (GET_CODE (x
) != PLUS
)
7237 /* Recognize the rtl generated by reload which we know will later be
7238 replaced with proper base and index regs. */
7240 && reload_in_progress
7241 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
7245 return (REG_P (op0
) && REG_P (op1
)
7246 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
7247 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
7248 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
7249 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
7253 avoiding_indexed_address_p (machine_mode mode
)
7255 /* Avoid indexed addressing for modes that have non-indexed
7256 load/store instruction forms. */
7257 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
7261 legitimate_indirect_address_p (rtx x
, int strict
)
7263 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
7267 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
7269 if (!TARGET_MACHO
|| !flag_pic
7270 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
7274 if (GET_CODE (x
) != LO_SUM
)
7276 if (GET_CODE (XEXP (x
, 0)) != REG
)
7278 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
7282 return CONSTANT_P (x
);
7286 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
7288 if (GET_CODE (x
) != LO_SUM
)
7290 if (GET_CODE (XEXP (x
, 0)) != REG
)
7292 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
7294 /* Restrict addressing for DI because of our SUBREG hackery. */
7295 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7299 if (TARGET_ELF
|| TARGET_MACHO
)
7303 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
7305 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
7306 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
7307 recognizes some LO_SUM addresses as valid although this
7308 function says opposite. In most cases, LRA through different
7309 transformations can generate correct code for address reloads.
7310 It can not manage only some LO_SUM cases. So we need to add
7311 code analogous to one in rs6000_legitimize_reload_address for
7312 LOW_SUM here saying that some addresses are still valid. */
7313 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
7314 && small_toc_ref (x
, VOIDmode
));
7315 if (TARGET_TOC
&& ! large_toc_ok
)
7317 if (GET_MODE_NUNITS (mode
) != 1)
7319 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7320 && !(/* ??? Assume floating point reg based on mode? */
7321 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
7322 && (mode
== DFmode
|| mode
== DDmode
)))
7325 return CONSTANT_P (x
) || large_toc_ok
;
7332 /* Try machine-dependent ways of modifying an illegitimate address
7333 to be legitimate. If we find one, return the new, valid address.
7334 This is used from only one place: `memory_address' in explow.c.
7336 OLDX is the address as it was before break_out_memory_refs was
7337 called. In some cases it is useful to look at this to decide what
7340 It is always safe for this function to do nothing. It exists to
7341 recognize opportunities to optimize the output.
7343 On RS/6000, first check for the sum of a register with a constant
7344 integer that is out of range. If so, generate code to add the
7345 constant with the low-order 16 bits masked to the register and force
7346 this result into another register (this can be done with `cau').
7347 Then generate an address of REG+(CONST&0xffff), allowing for the
7348 possibility of bit 16 being a one.
7350 Then check for the sum of a register and something not constant, try to
7351 load the other things into a register and return the sum. */
7354 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
7359 if (!reg_offset_addressing_ok_p (mode
))
7361 if (virtual_stack_registers_memory_p (x
))
7364 /* In theory we should not be seeing addresses of the form reg+0,
7365 but just in case it is generated, optimize it away. */
7366 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
7367 return force_reg (Pmode
, XEXP (x
, 0));
7369 /* For TImode with load/store quad, restrict addresses to just a single
7370 pointer, so it works with both GPRs and VSX registers. */
7371 /* Make sure both operands are registers. */
7372 else if (GET_CODE (x
) == PLUS
7373 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
7374 return gen_rtx_PLUS (Pmode
,
7375 force_reg (Pmode
, XEXP (x
, 0)),
7376 force_reg (Pmode
, XEXP (x
, 1)));
7378 return force_reg (Pmode
, x
);
7380 if (GET_CODE (x
) == SYMBOL_REF
)
7382 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
7384 return rs6000_legitimize_tls_address (x
, model
);
7396 /* As in legitimate_offset_address_p we do not assume
7397 worst-case. The mode here is just a hint as to the registers
7398 used. A TImode is usually in gprs, but may actually be in
7399 fprs. Leave worst-case scenario for reload to handle via
7400 insn constraints. PTImode is only GPRs. */
7407 if (GET_CODE (x
) == PLUS
7408 && GET_CODE (XEXP (x
, 0)) == REG
7409 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7410 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
7412 && !(SPE_VECTOR_MODE (mode
)
7413 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
7415 HOST_WIDE_INT high_int
, low_int
;
7417 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
7418 if (low_int
>= 0x8000 - extra
)
7420 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
7421 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
7422 GEN_INT (high_int
)), 0);
7423 return plus_constant (Pmode
, sum
, low_int
);
7425 else if (GET_CODE (x
) == PLUS
7426 && GET_CODE (XEXP (x
, 0)) == REG
7427 && GET_CODE (XEXP (x
, 1)) != CONST_INT
7428 && GET_MODE_NUNITS (mode
) == 1
7429 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
7430 || (/* ??? Assume floating point reg based on mode? */
7431 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7432 && (mode
== DFmode
|| mode
== DDmode
)))
7433 && !avoiding_indexed_address_p (mode
))
7435 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
7436 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
7438 else if (SPE_VECTOR_MODE (mode
)
7439 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
7443 /* We accept [reg + reg] and [reg + OFFSET]. */
7445 if (GET_CODE (x
) == PLUS
)
7447 rtx op1
= XEXP (x
, 0);
7448 rtx op2
= XEXP (x
, 1);
7451 op1
= force_reg (Pmode
, op1
);
7453 if (GET_CODE (op2
) != REG
7454 && (GET_CODE (op2
) != CONST_INT
7455 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
7456 || (GET_MODE_SIZE (mode
) > 8
7457 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
7458 op2
= force_reg (Pmode
, op2
);
7460 /* We can't always do [reg + reg] for these, because [reg +
7461 reg + offset] is not a legitimate addressing mode. */
7462 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
7464 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
7465 return force_reg (Pmode
, y
);
7470 return force_reg (Pmode
, x
);
7472 else if ((TARGET_ELF
7474 || !MACHO_DYNAMIC_NO_PIC_P
7480 && GET_CODE (x
) != CONST_INT
7481 && GET_CODE (x
) != CONST_WIDE_INT
7482 && GET_CODE (x
) != CONST_DOUBLE
7484 && GET_MODE_NUNITS (mode
) == 1
7485 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
7486 || (/* ??? Assume floating point reg based on mode? */
7487 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7488 && (mode
== DFmode
|| mode
== DDmode
))))
7490 rtx reg
= gen_reg_rtx (Pmode
);
7492 emit_insn (gen_elf_high (reg
, x
));
7494 emit_insn (gen_macho_high (reg
, x
));
7495 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
7498 && GET_CODE (x
) == SYMBOL_REF
7499 && constant_pool_expr_p (x
)
7500 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
7501 return create_TOC_reference (x
, NULL_RTX
);
7506 /* Debug version of rs6000_legitimize_address. */
7508 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
7514 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
7515 insns
= get_insns ();
7521 "\nrs6000_legitimize_address: mode %s, old code %s, "
7522 "new code %s, modified\n",
7523 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
7524 GET_RTX_NAME (GET_CODE (ret
)));
7526 fprintf (stderr
, "Original address:\n");
7529 fprintf (stderr
, "oldx:\n");
7532 fprintf (stderr
, "New address:\n");
7537 fprintf (stderr
, "Insns added:\n");
7538 debug_rtx_list (insns
, 20);
7544 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
7545 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
7556 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7557 We need to emit DTP-relative relocations. */
7559 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
7561 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7566 fputs ("\t.long\t", file
);
7569 fputs (DOUBLE_INT_ASM_OP
, file
);
7574 output_addr_const (file
, x
);
7576 fputs ("@dtprel+0x8000", file
);
7577 else if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
)
7579 switch (SYMBOL_REF_TLS_MODEL (x
))
7583 case TLS_MODEL_LOCAL_EXEC
:
7584 fputs ("@le", file
);
7586 case TLS_MODEL_INITIAL_EXEC
:
7587 fputs ("@ie", file
);
7589 case TLS_MODEL_GLOBAL_DYNAMIC
:
7590 case TLS_MODEL_LOCAL_DYNAMIC
:
7599 /* Return true if X is a symbol that refers to real (rather than emulated)
7603 rs6000_real_tls_symbol_ref_p (rtx x
)
7605 return (GET_CODE (x
) == SYMBOL_REF
7606 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
7609 /* In the name of slightly smaller debug output, and to cater to
7610 general assembler lossage, recognize various UNSPEC sequences
7611 and turn them back into a direct symbol reference. */
7614 rs6000_delegitimize_address (rtx orig_x
)
7618 orig_x
= delegitimize_mem_from_attrs (orig_x
);
7624 if (TARGET_CMODEL
!= CMODEL_SMALL
7625 && GET_CODE (y
) == LO_SUM
)
7629 if (GET_CODE (y
) == PLUS
7630 && GET_MODE (y
) == Pmode
7631 && CONST_INT_P (XEXP (y
, 1)))
7633 offset
= XEXP (y
, 1);
7637 if (GET_CODE (y
) == UNSPEC
7638 && XINT (y
, 1) == UNSPEC_TOCREL
)
7640 y
= XVECEXP (y
, 0, 0);
7643 /* Do not associate thread-local symbols with the original
7644 constant pool symbol. */
7646 && GET_CODE (y
) == SYMBOL_REF
7647 && CONSTANT_POOL_ADDRESS_P (y
)
7648 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
7652 if (offset
!= NULL_RTX
)
7653 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
7654 if (!MEM_P (orig_x
))
7657 return replace_equiv_address_nv (orig_x
, y
);
7661 && GET_CODE (orig_x
) == LO_SUM
7662 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
7664 y
= XEXP (XEXP (orig_x
, 1), 0);
7665 if (GET_CODE (y
) == UNSPEC
7666 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
7667 return XVECEXP (y
, 0, 0);
7673 /* Return true if X shouldn't be emitted into the debug info.
7674 The linker doesn't like .toc section references from
7675 .debug_* sections, so reject .toc section symbols. */
7678 rs6000_const_not_ok_for_debug_p (rtx x
)
7680 if (GET_CODE (x
) == SYMBOL_REF
7681 && CONSTANT_POOL_ADDRESS_P (x
))
7683 rtx c
= get_pool_constant (x
);
7684 machine_mode cmode
= get_pool_mode (x
);
7685 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
7692 /* Construct the SYMBOL_REF for the tls_get_addr function. */
7694 static GTY(()) rtx rs6000_tls_symbol
;
7696 rs6000_tls_get_addr (void)
7698 if (!rs6000_tls_symbol
)
7699 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
7701 return rs6000_tls_symbol
;
7704 /* Construct the SYMBOL_REF for TLS GOT references. */
7706 static GTY(()) rtx rs6000_got_symbol
;
7708 rs6000_got_sym (void)
7710 if (!rs6000_got_symbol
)
7712 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7713 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
7714 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
7717 return rs6000_got_symbol
;
7720 /* AIX Thread-Local Address support. */
7723 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
7725 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
7729 name
= XSTR (addr
, 0);
7730 /* Append TLS CSECT qualifier, unless the symbol already is qualified
7731 or the symbol will be in TLS private data section. */
7732 if (name
[strlen (name
) - 1] != ']'
7733 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
7734 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
7736 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
7737 strcpy (tlsname
, name
);
7739 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
7740 tlsaddr
= copy_rtx (addr
);
7741 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
7746 /* Place addr into TOC constant pool. */
7747 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
7749 /* Output the TOC entry and create the MEM referencing the value. */
7750 if (constant_pool_expr_p (XEXP (sym
, 0))
7751 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
7753 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
7754 mem
= gen_const_mem (Pmode
, tocref
);
7755 set_mem_alias_set (mem
, get_TOC_alias_set ());
7760 /* Use global-dynamic for local-dynamic. */
7761 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
7762 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
7764 /* Create new TOC reference for @m symbol. */
7765 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
7766 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
7767 strcpy (tlsname
, "*LCM");
7768 strcat (tlsname
, name
+ 3);
7769 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
7770 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
7771 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
7772 rtx modmem
= gen_const_mem (Pmode
, tocref
);
7773 set_mem_alias_set (modmem
, get_TOC_alias_set ());
7775 rtx modreg
= gen_reg_rtx (Pmode
);
7776 emit_insn (gen_rtx_SET (modreg
, modmem
));
7778 tmpreg
= gen_reg_rtx (Pmode
);
7779 emit_insn (gen_rtx_SET (tmpreg
, mem
));
7781 dest
= gen_reg_rtx (Pmode
);
7783 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
7785 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
7788 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7789 else if (TARGET_32BIT
)
7791 tlsreg
= gen_reg_rtx (SImode
);
7792 emit_insn (gen_tls_get_tpointer (tlsreg
));
7795 tlsreg
= gen_rtx_REG (DImode
, 13);
7797 /* Load the TOC value into temporary register. */
7798 tmpreg
= gen_reg_rtx (Pmode
);
7799 emit_insn (gen_rtx_SET (tmpreg
, mem
));
7800 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
7801 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
7803 /* Add TOC symbol value to TLS pointer. */
7804 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
7809 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7810 this (thread-local) address. */
7813 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
7818 return rs6000_legitimize_tls_address_aix (addr
, model
);
7820 dest
= gen_reg_rtx (Pmode
);
7821 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7827 tlsreg
= gen_rtx_REG (Pmode
, 13);
7828 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7832 tlsreg
= gen_rtx_REG (Pmode
, 2);
7833 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7837 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7841 tmp
= gen_reg_rtx (Pmode
);
7844 tlsreg
= gen_rtx_REG (Pmode
, 13);
7845 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7849 tlsreg
= gen_rtx_REG (Pmode
, 2);
7850 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7854 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7856 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7861 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7863 /* We currently use relocations like @got@tlsgd for tls, which
7864 means the linker will handle allocation of tls entries, placing
7865 them in the .got section. So use a pointer to the .got section,
7866 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7867 or to secondary GOT sections used by 32-bit -fPIC. */
7869 got
= gen_rtx_REG (Pmode
, 2);
7873 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7876 rtx gsym
= rs6000_got_sym ();
7877 got
= gen_reg_rtx (Pmode
);
7879 rs6000_emit_move (got
, gsym
, Pmode
);
7884 tmp1
= gen_reg_rtx (Pmode
);
7885 tmp2
= gen_reg_rtx (Pmode
);
7886 mem
= gen_const_mem (Pmode
, tmp1
);
7887 lab
= gen_label_rtx ();
7888 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7889 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7890 if (TARGET_LINK_STACK
)
7891 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7892 emit_move_insn (tmp2
, mem
);
7893 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7894 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7899 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7901 tga
= rs6000_tls_get_addr ();
7902 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7903 1, const0_rtx
, Pmode
);
7905 r3
= gen_rtx_REG (Pmode
, 3);
7906 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7909 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7911 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7913 else if (DEFAULT_ABI
== ABI_V4
)
7914 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7917 call_insn
= last_call_insn ();
7918 PATTERN (call_insn
) = insn
;
7919 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7920 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7921 pic_offset_table_rtx
);
7923 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7925 tga
= rs6000_tls_get_addr ();
7926 tmp1
= gen_reg_rtx (Pmode
);
7927 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7928 1, const0_rtx
, Pmode
);
7930 r3
= gen_rtx_REG (Pmode
, 3);
7931 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7934 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7936 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7938 else if (DEFAULT_ABI
== ABI_V4
)
7939 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7942 call_insn
= last_call_insn ();
7943 PATTERN (call_insn
) = insn
;
7944 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7945 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7946 pic_offset_table_rtx
);
7948 if (rs6000_tls_size
== 16)
7951 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7953 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7955 else if (rs6000_tls_size
== 32)
7957 tmp2
= gen_reg_rtx (Pmode
);
7959 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7961 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7964 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7966 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7970 tmp2
= gen_reg_rtx (Pmode
);
7972 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7974 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7976 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7982 /* IE, or 64-bit offset LE. */
7983 tmp2
= gen_reg_rtx (Pmode
);
7985 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7987 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7990 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7992 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
8000 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8003 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
8005 if (GET_CODE (x
) == HIGH
8006 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
8009 /* A TLS symbol in the TOC cannot contain a sum. */
8010 if (GET_CODE (x
) == CONST
8011 && GET_CODE (XEXP (x
, 0)) == PLUS
8012 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
8013 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
8016 /* Do not place an ELF TLS symbol in the constant pool. */
8017 return TARGET_ELF
&& tls_referenced_p (x
);
8020 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8021 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8022 can be addressed relative to the toc pointer. */
8025 use_toc_relative_ref (rtx sym
, machine_mode mode
)
8027 return ((constant_pool_expr_p (sym
)
8028 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
8029 get_pool_mode (sym
)))
8030 || (TARGET_CMODEL
== CMODEL_MEDIUM
8031 && SYMBOL_REF_LOCAL_P (sym
)
8032 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
8035 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
8036 replace the input X, or the original X if no replacement is called for.
8037 The output parameter *WIN is 1 if the calling macro should goto WIN,
8040 For RS/6000, we wish to handle large displacements off a base
8041 register by splitting the addend across an addiu/addis and the mem insn.
8042 This cuts number of extra insns needed from 3 to 1.
8044 On Darwin, we use this to generate code for floating point constants.
8045 A movsf_low is generated so we wind up with 2 instructions rather than 3.
8046 The Darwin code is inside #if TARGET_MACHO because only then are the
8047 machopic_* functions defined. */
8049 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
8050 int opnum
, int type
,
8051 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
8053 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
8055 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
8056 DFmode/DImode MEM. */
8059 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
8060 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
8061 reg_offset_p
= false;
8063 /* We must recognize output that we have already generated ourselves. */
8064 if (GET_CODE (x
) == PLUS
8065 && GET_CODE (XEXP (x
, 0)) == PLUS
8066 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
8067 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
8068 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8070 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8071 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8072 opnum
, (enum reload_type
) type
);
8077 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
8078 if (GET_CODE (x
) == LO_SUM
8079 && GET_CODE (XEXP (x
, 0)) == HIGH
)
8081 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8082 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8083 opnum
, (enum reload_type
) type
);
8089 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
8090 && GET_CODE (x
) == LO_SUM
8091 && GET_CODE (XEXP (x
, 0)) == PLUS
8092 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
8093 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
8094 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
8095 && machopic_operand_p (XEXP (x
, 1)))
8097 /* Result of previous invocation of this function on Darwin
8098 floating point constant. */
8099 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8100 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8101 opnum
, (enum reload_type
) type
);
8107 if (TARGET_CMODEL
!= CMODEL_SMALL
8109 && small_toc_ref (x
, VOIDmode
))
8111 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
8112 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
8113 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8114 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8115 opnum
, (enum reload_type
) type
);
8120 if (GET_CODE (x
) == PLUS
8121 && GET_CODE (XEXP (x
, 0)) == REG
8122 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
8123 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
8124 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8126 && !SPE_VECTOR_MODE (mode
)
8127 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
8128 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
8130 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
8131 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
8133 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8135 /* Check for 32-bit overflow. */
8136 if (high
+ low
!= val
)
8142 /* Reload the high part into a base reg; leave the low part
8143 in the mem directly. */
8145 x
= gen_rtx_PLUS (GET_MODE (x
),
8146 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
8150 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8151 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
8152 opnum
, (enum reload_type
) type
);
8157 if (GET_CODE (x
) == SYMBOL_REF
8159 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
8160 && !SPE_VECTOR_MODE (mode
)
8162 && DEFAULT_ABI
== ABI_DARWIN
8163 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
8164 && machopic_symbol_defined_p (x
)
8166 && DEFAULT_ABI
== ABI_V4
8169 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
8170 The same goes for DImode without 64-bit gprs and DFmode and DDmode
8172 ??? Assume floating point reg based on mode? This assumption is
8173 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
8174 where reload ends up doing a DFmode load of a constant from
8175 mem using two gprs. Unfortunately, at this point reload
8176 hasn't yet selected regs so poking around in reload data
8177 won't help and even if we could figure out the regs reliably,
8178 we'd still want to allow this transformation when the mem is
8179 naturally aligned. Since we say the address is good here, we
8180 can't disable offsets from LO_SUMs in mem_operand_gpr.
8181 FIXME: Allow offset from lo_sum for other modes too, when
8182 mem is sufficiently aligned.
8184 Also disallow this if the type can go in VMX/Altivec registers, since
8185 those registers do not have d-form (reg+offset) address modes. */
8186 && !reg_addr
[mode
].scalar_in_vmx_p
8191 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
8193 && (mode
!= DImode
|| TARGET_POWERPC64
)
8194 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
8195 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
8200 rtx offset
= machopic_gen_offset (x
);
8201 x
= gen_rtx_LO_SUM (GET_MODE (x
),
8202 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
8203 gen_rtx_HIGH (Pmode
, offset
)), offset
);
8207 x
= gen_rtx_LO_SUM (GET_MODE (x
),
8208 gen_rtx_HIGH (Pmode
, x
), x
);
8210 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8211 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8212 opnum
, (enum reload_type
) type
);
8217 /* Reload an offset address wrapped by an AND that represents the
8218 masking of the lower bits. Strip the outer AND and let reload
8219 convert the offset address into an indirect address. For VSX,
8220 force reload to create the address with an AND in a separate
8221 register, because we can't guarantee an altivec register will
8223 if (VECTOR_MEM_ALTIVEC_P (mode
)
8224 && GET_CODE (x
) == AND
8225 && GET_CODE (XEXP (x
, 0)) == PLUS
8226 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
8227 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
8228 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8229 && INTVAL (XEXP (x
, 1)) == -16)
8238 && GET_CODE (x
) == SYMBOL_REF
8239 && use_toc_relative_ref (x
, mode
))
8241 x
= create_TOC_reference (x
, NULL_RTX
);
8242 if (TARGET_CMODEL
!= CMODEL_SMALL
)
8243 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
8244 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
8245 opnum
, (enum reload_type
) type
);
8253 /* Debug version of rs6000_legitimize_reload_address. */
8255 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
8256 int opnum
, int type
,
8257 int ind_levels
, int *win
)
8259 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
8262 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
8263 "type = %d, ind_levels = %d, win = %d, original addr:\n",
8264 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
8268 fprintf (stderr
, "Same address returned\n");
8270 fprintf (stderr
, "NULL returned\n");
8273 fprintf (stderr
, "New address:\n");
8280 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
8281 that is a valid memory address for an instruction.
8282 The MODE argument is the machine mode for the MEM expression
8283 that wants to use this address.
8285 On the RS/6000, there are four valid address: a SYMBOL_REF that
8286 refers to a constant pool entry of an address (or the sum of it
8287 plus a constant), a short (16-bit signed) constant plus a register,
8288 the sum of two registers, or a register indirect, possibly with an
8289 auto-increment. For DFmode, DDmode and DImode with a constant plus
8290 register, we must ensure that both words are addressable or PowerPC64
8291 with offset word aligned.
8293 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
8294 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
8295 because adjacent memory cells are accessed by adding word-sized offsets
8296 during assembly output. */
8298 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
8300 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
8302 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
8303 if (VECTOR_MEM_ALTIVEC_P (mode
)
8304 && GET_CODE (x
) == AND
8305 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8306 && INTVAL (XEXP (x
, 1)) == -16)
8309 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
8311 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
8314 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
8315 && mode_supports_pre_incdec_p (mode
)
8316 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
8318 if (virtual_stack_registers_memory_p (x
))
8320 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
8323 && legitimate_constant_pool_address_p (x
, mode
,
8324 reg_ok_strict
|| lra_in_progress
))
8326 if (reg_offset_p
&& reg_addr
[mode
].fused_toc
&& toc_fusion_mem_wrapped (x
, mode
))
8328 /* For TImode, if we have load/store quad and TImode in VSX registers, only
8329 allow register indirect addresses. This will allow the values to go in
8330 either GPRs or VSX registers without reloading. The vector types would
8331 tend to go into VSX registers, so we allow REG+REG, while TImode seems
8332 somewhat split, in that some uses are GPR based, and some VSX based. */
8333 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
8335 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
8338 && GET_CODE (x
) == PLUS
8339 && GET_CODE (XEXP (x
, 0)) == REG
8340 && (XEXP (x
, 0) == virtual_stack_vars_rtx
8341 || XEXP (x
, 0) == arg_pointer_rtx
)
8342 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8344 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
8346 if (!FLOAT128_2REG_P (mode
)
8347 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
8349 || (mode
!= DFmode
&& mode
!= DDmode
)
8350 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
8351 && (TARGET_POWERPC64
|| mode
!= DImode
)
8352 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
8354 && !avoiding_indexed_address_p (mode
)
8355 && legitimate_indexed_address_p (x
, reg_ok_strict
))
8357 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
8358 && mode_supports_pre_modify_p (mode
)
8359 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
8360 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
8361 reg_ok_strict
, false)
8362 || (!avoiding_indexed_address_p (mode
)
8363 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
8364 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
8366 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
8371 /* Debug version of rs6000_legitimate_address_p. */
8373 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
8376 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
8378 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8379 "strict = %d, reload = %s, code = %s\n",
8380 ret
? "true" : "false",
8381 GET_MODE_NAME (mode
),
8385 : (reload_in_progress
? "progress" : "before")),
8386 GET_RTX_NAME (GET_CODE (x
)));
8392 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8395 rs6000_mode_dependent_address_p (const_rtx addr
,
8396 addr_space_t as ATTRIBUTE_UNUSED
)
8398 return rs6000_mode_dependent_address_ptr (addr
);
8401 /* Go to LABEL if ADDR (a legitimate address expression)
8402 has an effect that depends on the machine mode it is used for.
8404 On the RS/6000 this is true of all integral offsets (since AltiVec
8405 and VSX modes don't allow them) or is a pre-increment or decrement.
8407 ??? Except that due to conceptual problems in offsettable_address_p
8408 we can't really report the problems of integral offsets. So leave
8409 this assuming that the adjustable offset must be valid for the
8410 sub-words of a TFmode operand, which is what we had before. */
8413 rs6000_mode_dependent_address (const_rtx addr
)
8415 switch (GET_CODE (addr
))
8418 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
8419 is considered a legitimate address before reload, so there
8420 are no offset restrictions in that case. Note that this
8421 condition is safe in strict mode because any address involving
8422 virtual_stack_vars_rtx or arg_pointer_rtx would already have
8423 been rejected as illegitimate. */
8424 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
8425 && XEXP (addr
, 0) != arg_pointer_rtx
8426 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
8428 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
8429 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
8434 /* Anything in the constant pool is sufficiently aligned that
8435 all bytes have the same high part address. */
8436 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
8438 /* Auto-increment cases are now treated generically in recog.c. */
8440 return TARGET_UPDATE
;
8442 /* AND is only allowed in Altivec loads. */
8453 /* Debug version of rs6000_mode_dependent_address. */
8455 rs6000_debug_mode_dependent_address (const_rtx addr
)
8457 bool ret
= rs6000_mode_dependent_address (addr
);
8459 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
8460 ret
? "true" : "false");
8466 /* Implement FIND_BASE_TERM. */
8469 rs6000_find_base_term (rtx op
)
8474 if (GET_CODE (base
) == CONST
)
8475 base
= XEXP (base
, 0);
8476 if (GET_CODE (base
) == PLUS
)
8477 base
= XEXP (base
, 0);
8478 if (GET_CODE (base
) == UNSPEC
)
8479 switch (XINT (base
, 1))
8482 case UNSPEC_MACHOPIC_OFFSET
:
8483 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
8484 for aliasing purposes. */
8485 return XVECEXP (base
, 0, 0);
8491 /* More elaborate version of recog's offsettable_memref_p predicate
8492 that works around the ??? note of rs6000_mode_dependent_address.
8493 In particular it accepts
8495 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
8497 in 32-bit mode, that the recog predicate rejects. */
8500 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
)
8507 /* First mimic offsettable_memref_p. */
8508 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
8511 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
8512 the latter predicate knows nothing about the mode of the memory
8513 reference and, therefore, assumes that it is the largest supported
8514 mode (TFmode). As a consequence, legitimate offsettable memory
8515 references are rejected. rs6000_legitimate_offset_address_p contains
8516 the correct logic for the PLUS case of rs6000_mode_dependent_address,
8517 at least with a little bit of help here given that we know the
8518 actual registers used. */
8519 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
8520 || GET_MODE_SIZE (reg_mode
) == 4);
8521 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
8525 /* Change register usage conditional on target flags. */
8527 rs6000_conditional_register_usage (void)
8531 if (TARGET_DEBUG_TARGET
)
8532 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
8534 /* Set MQ register fixed (already call_used) so that it will not be
8538 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
8540 fixed_regs
[13] = call_used_regs
[13]
8541 = call_really_used_regs
[13] = 1;
8543 /* Conditionally disable FPRs. */
8544 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
8545 for (i
= 32; i
< 64; i
++)
8546 fixed_regs
[i
] = call_used_regs
[i
]
8547 = call_really_used_regs
[i
] = 1;
8549 /* The TOC register is not killed across calls in a way that is
8550 visible to the compiler. */
8551 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
8552 call_really_used_regs
[2] = 0;
8554 if (DEFAULT_ABI
== ABI_V4
8555 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
8557 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8559 if (DEFAULT_ABI
== ABI_V4
8560 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
8562 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8563 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8564 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8566 if (DEFAULT_ABI
== ABI_DARWIN
8567 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
8568 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8569 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8570 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8572 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
8573 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8574 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8578 global_regs
[SPEFSCR_REGNO
] = 1;
8579 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
8580 registers in prologues and epilogues. We no longer use r14
8581 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
8582 pool for link-compatibility with older versions of GCC. Once
8583 "old" code has died out, we can return r14 to the allocation
8586 = call_used_regs
[14]
8587 = call_really_used_regs
[14] = 1;
8590 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
8592 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
8593 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8594 call_really_used_regs
[VRSAVE_REGNO
] = 1;
8597 if (TARGET_ALTIVEC
|| TARGET_VSX
)
8598 global_regs
[VSCR_REGNO
] = 1;
8600 if (TARGET_ALTIVEC_ABI
)
8602 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
8603 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8605 /* AIX reserves VR20:31 in non-extended ABI mode. */
8607 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
8608 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8613 /* Output insns to set DEST equal to the constant SOURCE as a series of
8614 lis, ori and shl instructions and return TRUE. */
8617 rs6000_emit_set_const (rtx dest
, rtx source
)
8619 machine_mode mode
= GET_MODE (dest
);
8624 gcc_checking_assert (CONST_INT_P (source
));
8625 c
= INTVAL (source
);
8630 emit_insn (gen_rtx_SET (dest
, source
));
8634 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
8636 emit_insn (gen_rtx_SET (copy_rtx (temp
),
8637 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
8638 emit_insn (gen_rtx_SET (dest
,
8639 gen_rtx_IOR (SImode
, copy_rtx (temp
),
8640 GEN_INT (c
& 0xffff))));
8644 if (!TARGET_POWERPC64
)
8648 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
8650 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
8652 emit_move_insn (hi
, GEN_INT (c
>> 32));
8653 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
8654 emit_move_insn (lo
, GEN_INT (c
));
8657 rs6000_emit_set_long_const (dest
, c
);
8664 insn
= get_last_insn ();
8665 set
= single_set (insn
);
8666 if (! CONSTANT_P (SET_SRC (set
)))
8667 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
8672 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
8673 Output insns to set DEST equal to the constant C as a series of
8674 lis, ori and shl instructions. */
8677 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
8680 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
8690 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
8691 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
8692 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
8694 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
8695 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
8697 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8699 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8700 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8702 emit_move_insn (dest
,
8703 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8706 else if (ud3
== 0 && ud4
== 0)
8708 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8710 gcc_assert (ud2
& 0x8000);
8711 emit_move_insn (copy_rtx (temp
),
8712 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8714 emit_move_insn (copy_rtx (temp
),
8715 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8717 emit_move_insn (dest
,
8718 gen_rtx_ZERO_EXTEND (DImode
,
8719 gen_lowpart (SImode
,
8722 else if ((ud4
== 0xffff && (ud3
& 0x8000))
8723 || (ud4
== 0 && ! (ud3
& 0x8000)))
8725 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8727 emit_move_insn (copy_rtx (temp
),
8728 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
8730 emit_move_insn (copy_rtx (temp
),
8731 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8733 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8734 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8737 emit_move_insn (dest
,
8738 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8743 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8745 emit_move_insn (copy_rtx (temp
),
8746 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
8748 emit_move_insn (copy_rtx (temp
),
8749 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8752 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
8753 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8756 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8757 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8758 GEN_INT (ud2
<< 16)));
8760 emit_move_insn (dest
,
8761 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8766 /* Helper for the following. Get rid of [r+r] memory refs
8767 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8770 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
8772 if (reload_in_progress
)
8775 if (GET_CODE (operands
[0]) == MEM
8776 && GET_CODE (XEXP (operands
[0], 0)) != REG
8777 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
8778 GET_MODE (operands
[0]), false))
8780 = replace_equiv_address (operands
[0],
8781 copy_addr_to_reg (XEXP (operands
[0], 0)));
8783 if (GET_CODE (operands
[1]) == MEM
8784 && GET_CODE (XEXP (operands
[1], 0)) != REG
8785 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
8786 GET_MODE (operands
[1]), false))
8788 = replace_equiv_address (operands
[1],
8789 copy_addr_to_reg (XEXP (operands
[1], 0)));
8792 /* Generate a vector of constants to permute MODE for a little-endian
8793 storage operation by swapping the two halves of a vector. */
8795 rs6000_const_vec (machine_mode mode
)
8823 v
= rtvec_alloc (subparts
);
8825 for (i
= 0; i
< subparts
/ 2; ++i
)
8826 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8827 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8828 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8833 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8834 for a VSX load or store operation. */
8836 rs6000_gen_le_vsx_permute (rtx source
, machine_mode mode
)
8838 /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point, and
8839 128-bit integers if they are allowed in VSX registers. */
8840 if (FLOAT128_VECTOR_P (mode
) || mode
== TImode
)
8841 return gen_rtx_ROTATE (mode
, source
, GEN_INT (64));
8844 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8845 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8849 /* Emit a little-endian load from vector memory location SOURCE to VSX
8850 register DEST in mode MODE. The load is done with two permuting
8851 insn's that represent an lxvd2x and xxpermdi. */
8853 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
8855 rtx tmp
, permute_mem
, permute_reg
;
8857 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8859 if (mode
== TImode
|| mode
== V1TImode
)
8862 dest
= gen_lowpart (V2DImode
, dest
);
8863 source
= adjust_address (source
, V2DImode
, 0);
8866 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8867 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8868 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8869 emit_insn (gen_rtx_SET (tmp
, permute_mem
));
8870 emit_insn (gen_rtx_SET (dest
, permute_reg
));
8873 /* Emit a little-endian store to vector memory location DEST from VSX
8874 register SOURCE in mode MODE. The store is done with two permuting
8875 insn's that represent an xxpermdi and an stxvd2x. */
8877 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
8879 rtx tmp
, permute_src
, permute_tmp
;
8881 /* This should never be called during or after reload, because it does
8882 not re-permute the source register. It is intended only for use
8884 gcc_assert (!reload_in_progress
&& !lra_in_progress
&& !reload_completed
);
8886 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
8888 if (mode
== TImode
|| mode
== V1TImode
)
8891 dest
= adjust_address (dest
, V2DImode
, 0);
8892 source
= gen_lowpart (V2DImode
, source
);
8895 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8896 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8897 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8898 emit_insn (gen_rtx_SET (tmp
, permute_src
));
8899 emit_insn (gen_rtx_SET (dest
, permute_tmp
));
8902 /* Emit a sequence representing a little-endian VSX load or store,
8903 moving data from SOURCE to DEST in mode MODE. This is done
8904 separately from rs6000_emit_move to ensure it is called only
8905 during expand. LE VSX loads and stores introduced later are
8906 handled with a split. The expand-time RTL generation allows
8907 us to optimize away redundant pairs of register-permutes. */
8909 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
8911 gcc_assert (!BYTES_BIG_ENDIAN
8912 && VECTOR_MEM_VSX_P (mode
)
8913 && !TARGET_P9_VECTOR
8914 && !gpr_or_gpr_p (dest
, source
)
8915 && (MEM_P (source
) ^ MEM_P (dest
)));
8919 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8920 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8924 if (!REG_P (source
))
8925 source
= force_reg (mode
, source
);
8926 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8930 /* Emit a move from SOURCE to DEST in mode MODE. */
8932 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
8936 operands
[1] = source
;
8938 if (TARGET_DEBUG_ADDR
)
8941 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8942 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8943 GET_MODE_NAME (mode
),
8946 can_create_pseudo_p ());
8948 fprintf (stderr
, "source:\n");
8952 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8953 if (CONST_WIDE_INT_P (operands
[1])
8954 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8956 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8960 /* Check if GCC is setting up a block move that will end up using FP
8961 registers as temporaries. We must make sure this is acceptable. */
8962 if (GET_CODE (operands
[0]) == MEM
8963 && GET_CODE (operands
[1]) == MEM
8965 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8966 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8967 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8968 ? 32 : MEM_ALIGN (operands
[0])))
8969 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8971 : MEM_ALIGN (operands
[1]))))
8972 && ! MEM_VOLATILE_P (operands
[0])
8973 && ! MEM_VOLATILE_P (operands
[1]))
8975 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8976 adjust_address (operands
[1], SImode
, 0));
8977 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8978 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8982 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8983 && !gpc_reg_operand (operands
[1], mode
))
8984 operands
[1] = force_reg (mode
, operands
[1]);
8986 /* Recognize the case where operand[1] is a reference to thread-local
8987 data and load its address to a register. */
8988 if (tls_referenced_p (operands
[1]))
8990 enum tls_model model
;
8991 rtx tmp
= operands
[1];
8994 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8996 addend
= XEXP (XEXP (tmp
, 0), 1);
8997 tmp
= XEXP (XEXP (tmp
, 0), 0);
9000 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
9001 model
= SYMBOL_REF_TLS_MODEL (tmp
);
9002 gcc_assert (model
!= 0);
9004 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
9007 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
9008 tmp
= force_operand (tmp
, operands
[0]);
9013 /* Handle the case where reload calls us with an invalid address. */
9014 if (reload_in_progress
&& mode
== Pmode
9015 && (! general_operand (operands
[1], mode
)
9016 || ! nonimmediate_operand (operands
[0], mode
)))
9019 /* 128-bit constant floating-point values on Darwin should really be loaded
9020 as two parts. However, this premature splitting is a problem when DFmode
9021 values can go into Altivec registers. */
9022 if (FLOAT128_IBM_P (mode
) && !reg_addr
[DFmode
].scalar_in_vmx_p
9023 && GET_CODE (operands
[1]) == CONST_DOUBLE
)
9025 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
9026 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
9028 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
9029 GET_MODE_SIZE (DFmode
)),
9030 simplify_gen_subreg (DFmode
, operands
[1], mode
,
9031 GET_MODE_SIZE (DFmode
)),
9036 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
9037 cfun
->machine
->sdmode_stack_slot
=
9038 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
9041 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9042 p1:SD) if p1 is not of floating point class and p0 is spilled as
9043 we can have no analogous movsd_store for this. */
9044 if (lra_in_progress
&& mode
== DDmode
9045 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
9046 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
9047 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
9048 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
9051 int regno
= REGNO (SUBREG_REG (operands
[1]));
9053 if (regno
>= FIRST_PSEUDO_REGISTER
)
9055 cl
= reg_preferred_class (regno
);
9056 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
9058 if (regno
>= 0 && ! FP_REGNO_P (regno
))
9061 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
9062 operands
[1] = SUBREG_REG (operands
[1]);
9067 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
9068 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
9069 && (REG_P (operands
[1])
9070 || (GET_CODE (operands
[1]) == SUBREG
9071 && REG_P (SUBREG_REG (operands
[1])))))
9073 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
9074 ? SUBREG_REG (operands
[1]) : operands
[1]);
9077 if (regno
>= FIRST_PSEUDO_REGISTER
)
9079 cl
= reg_preferred_class (regno
);
9080 gcc_assert (cl
!= NO_REGS
);
9081 regno
= ira_class_hard_regs
[cl
][0];
9083 if (FP_REGNO_P (regno
))
9085 if (GET_MODE (operands
[0]) != DDmode
)
9086 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
9087 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
9089 else if (INT_REGNO_P (regno
))
9090 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
9095 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
9096 p:DD)) if p0 is not of floating point class and p1 is spilled as
9097 we can have no analogous movsd_load for this. */
9098 if (lra_in_progress
&& mode
== DDmode
9099 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
9100 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
9101 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
9102 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
9105 int regno
= REGNO (SUBREG_REG (operands
[0]));
9107 if (regno
>= FIRST_PSEUDO_REGISTER
)
9109 cl
= reg_preferred_class (regno
);
9110 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
9112 if (regno
>= 0 && ! FP_REGNO_P (regno
))
9115 operands
[0] = SUBREG_REG (operands
[0]);
9116 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
9121 && (REG_P (operands
[0])
9122 || (GET_CODE (operands
[0]) == SUBREG
9123 && REG_P (SUBREG_REG (operands
[0]))))
9124 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
9125 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
9127 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
9128 ? SUBREG_REG (operands
[0]) : operands
[0]);
9131 if (regno
>= FIRST_PSEUDO_REGISTER
)
9133 cl
= reg_preferred_class (regno
);
9134 gcc_assert (cl
!= NO_REGS
);
9135 regno
= ira_class_hard_regs
[cl
][0];
9137 if (FP_REGNO_P (regno
))
9139 if (GET_MODE (operands
[1]) != DDmode
)
9140 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
9141 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
9143 else if (INT_REGNO_P (regno
))
9144 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
9150 if (reload_in_progress
9152 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
9153 && MEM_P (operands
[0])
9154 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
9155 && REG_P (operands
[1]))
9157 if (FP_REGNO_P (REGNO (operands
[1])))
9159 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
9160 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
9161 emit_insn (gen_movsd_store (mem
, operands
[1]));
9163 else if (INT_REGNO_P (REGNO (operands
[1])))
9165 rtx mem
= operands
[0];
9166 if (BYTES_BIG_ENDIAN
)
9167 mem
= adjust_address_nv (mem
, mode
, 4);
9168 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
9169 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
9175 if (reload_in_progress
9177 && REG_P (operands
[0])
9178 && MEM_P (operands
[1])
9179 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
9180 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
9182 if (FP_REGNO_P (REGNO (operands
[0])))
9184 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
9185 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
9186 emit_insn (gen_movsd_load (operands
[0], mem
));
9188 else if (INT_REGNO_P (REGNO (operands
[0])))
9190 rtx mem
= operands
[1];
9191 if (BYTES_BIG_ENDIAN
)
9192 mem
= adjust_address_nv (mem
, mode
, 4);
9193 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
9194 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
9201 /* FIXME: In the long term, this switch statement should go away
9202 and be replaced by a sequence of tests based on things like
9208 if (CONSTANT_P (operands
[1])
9209 && GET_CODE (operands
[1]) != CONST_INT
)
9210 operands
[1] = force_const_mem (mode
, operands
[1]);
9217 if (FLOAT128_2REG_P (mode
))
9218 rs6000_eliminate_indexed_memrefs (operands
);
9225 if (CONSTANT_P (operands
[1])
9226 && ! easy_fp_constant (operands
[1], mode
))
9227 operands
[1] = force_const_mem (mode
, operands
[1]);
9241 if (CONSTANT_P (operands
[1])
9242 && !easy_vector_constant (operands
[1], mode
))
9243 operands
[1] = force_const_mem (mode
, operands
[1]);
9248 /* Use default pattern for address of ELF small data */
9251 && DEFAULT_ABI
== ABI_V4
9252 && (GET_CODE (operands
[1]) == SYMBOL_REF
9253 || GET_CODE (operands
[1]) == CONST
)
9254 && small_data_operand (operands
[1], mode
))
9256 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
9260 if (DEFAULT_ABI
== ABI_V4
9261 && mode
== Pmode
&& mode
== SImode
9262 && flag_pic
== 1 && got_operand (operands
[1], mode
))
9264 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
9268 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
9272 && CONSTANT_P (operands
[1])
9273 && GET_CODE (operands
[1]) != HIGH
9274 && GET_CODE (operands
[1]) != CONST_INT
)
9276 rtx target
= (!can_create_pseudo_p ()
9278 : gen_reg_rtx (mode
));
9280 /* If this is a function address on -mcall-aixdesc,
9281 convert it to the address of the descriptor. */
9282 if (DEFAULT_ABI
== ABI_AIX
9283 && GET_CODE (operands
[1]) == SYMBOL_REF
9284 && XSTR (operands
[1], 0)[0] == '.')
9286 const char *name
= XSTR (operands
[1], 0);
9288 while (*name
== '.')
9290 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
9291 CONSTANT_POOL_ADDRESS_P (new_ref
)
9292 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
9293 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
9294 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
9295 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
9296 operands
[1] = new_ref
;
9299 if (DEFAULT_ABI
== ABI_DARWIN
)
9302 if (MACHO_DYNAMIC_NO_PIC_P
)
9304 /* Take care of any required data indirection. */
9305 operands
[1] = rs6000_machopic_legitimize_pic_address (
9306 operands
[1], mode
, operands
[0]);
9307 if (operands
[0] != operands
[1])
9308 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
9312 emit_insn (gen_macho_high (target
, operands
[1]));
9313 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
9317 emit_insn (gen_elf_high (target
, operands
[1]));
9318 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
9322 /* If this is a SYMBOL_REF that refers to a constant pool entry,
9323 and we have put it in the TOC, we just need to make a TOC-relative
9326 && GET_CODE (operands
[1]) == SYMBOL_REF
9327 && use_toc_relative_ref (operands
[1], mode
))
9328 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
9329 else if (mode
== Pmode
9330 && CONSTANT_P (operands
[1])
9331 && GET_CODE (operands
[1]) != HIGH
9332 && ((GET_CODE (operands
[1]) != CONST_INT
9333 && ! easy_fp_constant (operands
[1], mode
))
9334 || (GET_CODE (operands
[1]) == CONST_INT
9335 && (num_insns_constant (operands
[1], mode
)
9336 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
9337 || (GET_CODE (operands
[0]) == REG
9338 && FP_REGNO_P (REGNO (operands
[0]))))
9339 && !toc_relative_expr_p (operands
[1], false)
9340 && (TARGET_CMODEL
== CMODEL_SMALL
9341 || can_create_pseudo_p ()
9342 || (REG_P (operands
[0])
9343 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
9347 /* Darwin uses a special PIC legitimizer. */
9348 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
9351 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
9353 if (operands
[0] != operands
[1])
9354 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
9359 /* If we are to limit the number of things we put in the TOC and
9360 this is a symbol plus a constant we can add in one insn,
9361 just put the symbol in the TOC and add the constant. Don't do
9362 this if reload is in progress. */
9363 if (GET_CODE (operands
[1]) == CONST
9364 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
9365 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
9366 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
9367 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
9368 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
9369 && ! side_effects_p (operands
[0]))
9372 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
9373 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
9375 sym
= force_reg (mode
, sym
);
9376 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
9380 operands
[1] = force_const_mem (mode
, operands
[1]);
9383 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
9384 && constant_pool_expr_p (XEXP (operands
[1], 0))
9385 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
9386 get_pool_constant (XEXP (operands
[1], 0)),
9387 get_pool_mode (XEXP (operands
[1], 0))))
9389 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
9391 operands
[1] = gen_const_mem (mode
, tocref
);
9392 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
9398 if (!VECTOR_MEM_VSX_P (TImode
))
9399 rs6000_eliminate_indexed_memrefs (operands
);
9403 rs6000_eliminate_indexed_memrefs (operands
);
9407 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
9410 /* Above, we may have called force_const_mem which may have returned
9411 an invalid address. If we can, fix this up; otherwise, reload will
9412 have to deal with it. */
9413 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
9414 operands
[1] = validize_mem (operands
[1]);
9417 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
9420 /* Return true if a structure, union or array containing FIELD should be
9421 accessed using `BLKMODE'.
9423 For the SPE, simd types are V2SI, and gcc can be tempted to put the
9424 entire thing in a DI and use subregs to access the internals.
9425 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
9426 back-end. Because a single GPR can hold a V2SI, but not a DI, the
9427 best thing to do is set structs to BLKmode and avoid Severe Tire
9430 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
9431 fit into 1, whereas DI still needs two. */
9434 rs6000_member_type_forces_blk (const_tree field
, machine_mode mode
)
9436 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
9437 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
9440 /* Nonzero if we can use a floating-point register to pass this arg. */
9441 #define USE_FP_FOR_ARG_P(CUM,MODE) \
9442 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
9443 && (CUM)->fregno <= FP_ARG_MAX_REG \
9444 && TARGET_HARD_FLOAT && TARGET_FPRS)
9446 /* Nonzero if we can use an AltiVec register to pass this arg. */
9447 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
9448 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
9449 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
9450 && TARGET_ALTIVEC_ABI \
9453 /* Walk down the type tree of TYPE counting consecutive base elements.
9454 If *MODEP is VOIDmode, then set it to the first valid floating point
9455 or vector type. If a non-floating point or vector type is found, or
9456 if a floating point or vector type that doesn't match a non-VOIDmode
9457 *MODEP is found, then return -1, otherwise return the count in the
9461 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
9466 switch (TREE_CODE (type
))
9469 mode
= TYPE_MODE (type
);
9470 if (!SCALAR_FLOAT_MODE_P (mode
))
9473 if (*modep
== VOIDmode
)
9482 mode
= TYPE_MODE (TREE_TYPE (type
));
9483 if (!SCALAR_FLOAT_MODE_P (mode
))
9486 if (*modep
== VOIDmode
)
9495 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
9498 /* Use V4SImode as representative of all 128-bit vector types. */
9499 size
= int_size_in_bytes (type
);
9509 if (*modep
== VOIDmode
)
9512 /* Vector modes are considered to be opaque: two vectors are
9513 equivalent for the purposes of being homogeneous aggregates
9514 if they are the same size. */
9523 tree index
= TYPE_DOMAIN (type
);
9525 /* Can't handle incomplete types nor sizes that are not
9527 if (!COMPLETE_TYPE_P (type
)
9528 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9531 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
9534 || !TYPE_MAX_VALUE (index
)
9535 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
9536 || !TYPE_MIN_VALUE (index
)
9537 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
9541 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
9542 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
9544 /* There must be no padding. */
9545 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9557 /* Can't handle incomplete types nor sizes that are not
9559 if (!COMPLETE_TYPE_P (type
)
9560 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9563 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
9565 if (TREE_CODE (field
) != FIELD_DECL
)
9568 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
9574 /* There must be no padding. */
9575 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9582 case QUAL_UNION_TYPE
:
9584 /* These aren't very interesting except in a degenerate case. */
9589 /* Can't handle incomplete types nor sizes that are not
9591 if (!COMPLETE_TYPE_P (type
)
9592 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9595 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
9597 if (TREE_CODE (field
) != FIELD_DECL
)
9600 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
9603 count
= count
> sub_count
? count
: sub_count
;
9606 /* There must be no padding. */
9607 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9620 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
9621 float or vector aggregate that shall be passed in FP/vector registers
9622 according to the ELFv2 ABI, return the homogeneous element mode in
9623 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
9625 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
9628 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
9629 machine_mode
*elt_mode
,
9632 /* Note that we do not accept complex types at the top level as
9633 homogeneous aggregates; these types are handled via the
9634 targetm.calls.split_complex_arg mechanism. Complex types
9635 can be elements of homogeneous aggregates, however. */
9636 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
9638 machine_mode field_mode
= VOIDmode
;
9639 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
9641 if (field_count
> 0)
9643 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
) ?
9644 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
9646 /* The ELFv2 ABI allows homogeneous aggregates to occupy
9647 up to AGGR_ARG_NUM_REG registers. */
9648 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
9651 *elt_mode
= field_mode
;
9653 *n_elts
= field_count
;
9666 /* Return a nonzero value to say to return the function value in
9667 memory, just as large structures are always returned. TYPE will be
9668 the data type of the value, and FNTYPE will be the type of the
9669 function doing the returning, or @code{NULL} for libcalls.
9671 The AIX ABI for the RS/6000 specifies that all structures are
9672 returned in memory. The Darwin ABI does the same.
9674 For the Darwin 64 Bit ABI, a function result can be returned in
9675 registers or in memory, depending on the size of the return data
9676 type. If it is returned in registers, the value occupies the same
9677 registers as it would if it were the first and only function
9678 argument. Otherwise, the function places its result in memory at
9679 the location pointed to by GPR3.
9681 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
9682 but a draft put them in memory, and GCC used to implement the draft
9683 instead of the final standard. Therefore, aix_struct_return
9684 controls this instead of DEFAULT_ABI; V.4 targets needing backward
9685 compatibility can change DRAFT_V4_STRUCT_RET to override the
9686 default, and -m switches get the final word. See
9687 rs6000_option_override_internal for more details.
9689 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
9690 long double support is enabled. These values are returned in memory.
9692 int_size_in_bytes returns -1 for variable size objects, which go in
9693 memory always. The cast to unsigned makes -1 > 8. */
9696 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
9698 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
9700 && rs6000_darwin64_abi
9701 && TREE_CODE (type
) == RECORD_TYPE
9702 && int_size_in_bytes (type
) > 0)
9704 CUMULATIVE_ARGS valcum
;
9708 valcum
.fregno
= FP_ARG_MIN_REG
;
9709 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
9710 /* Do a trial code generation as if this were going to be passed
9711 as an argument; if any part goes in memory, we return NULL. */
9712 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
9715 /* Otherwise fall through to more conventional ABI rules. */
9718 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
9719 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
9723 /* The ELFv2 ABI returns aggregates up to 16B in registers */
9724 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
9725 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
9728 if (AGGREGATE_TYPE_P (type
)
9729 && (aix_struct_return
9730 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
9733 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9734 modes only exist for GCC vector types if -maltivec. */
9735 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
9736 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9739 /* Return synthetic vectors in memory. */
9740 if (TREE_CODE (type
) == VECTOR_TYPE
9741 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9743 static bool warned_for_return_big_vectors
= false;
9744 if (!warned_for_return_big_vectors
)
9746 warning (0, "GCC vector returned by reference: "
9747 "non-standard ABI extension with no compatibility guarantee");
9748 warned_for_return_big_vectors
= true;
9753 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
9754 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
9760 /* Specify whether values returned in registers should be at the most
9761 significant end of a register. We want aggregates returned by
9762 value to match the way aggregates are passed to functions. */
9765 rs6000_return_in_msb (const_tree valtype
)
9767 return (DEFAULT_ABI
== ABI_ELFv2
9769 && AGGREGATE_TYPE_P (valtype
)
9770 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
9773 #ifdef HAVE_AS_GNU_ATTRIBUTE
9774 /* Return TRUE if a call to function FNDECL may be one that
9775 potentially affects the function calling ABI of the object file. */
9778 call_ABI_of_interest (tree fndecl
)
9780 if (symtab
->state
== EXPANSION
)
9782 struct cgraph_node
*c_node
;
9784 /* Libcalls are always interesting. */
9785 if (fndecl
== NULL_TREE
)
9788 /* Any call to an external function is interesting. */
9789 if (DECL_EXTERNAL (fndecl
))
9792 /* Interesting functions that we are emitting in this object file. */
9793 c_node
= cgraph_node::get (fndecl
);
9794 c_node
= c_node
->ultimate_alias_target ();
9795 return !c_node
->only_called_directly_p ();
9801 /* Initialize a variable CUM of type CUMULATIVE_ARGS
9802 for a call to a function whose data type is FNTYPE.
9803 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
9805 For incoming args we set the number of arguments in the prototype large
9806 so we never return a PARALLEL. */
9809 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
9810 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
9811 int libcall
, int n_named_args
,
9812 tree fndecl ATTRIBUTE_UNUSED
,
9813 machine_mode return_mode ATTRIBUTE_UNUSED
)
9815 static CUMULATIVE_ARGS zero_cumulative
;
9817 *cum
= zero_cumulative
;
9819 cum
->fregno
= FP_ARG_MIN_REG
;
9820 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
9821 cum
->prototype
= (fntype
&& prototype_p (fntype
));
9822 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
9823 ? CALL_LIBCALL
: CALL_NORMAL
);
9824 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
9825 cum
->stdarg
= stdarg_p (fntype
);
9826 cum
->libcall
= libcall
;
9828 cum
->nargs_prototype
= 0;
9829 if (incoming
|| cum
->prototype
)
9830 cum
->nargs_prototype
= n_named_args
;
9832 /* Check for a longcall attribute. */
9833 if ((!fntype
&& rs6000_default_long_calls
)
9835 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
9836 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
9837 cum
->call_cookie
|= CALL_LONG
;
9839 if (TARGET_DEBUG_ARG
)
9841 fprintf (stderr
, "\ninit_cumulative_args:");
9844 tree ret_type
= TREE_TYPE (fntype
);
9845 fprintf (stderr
, " ret code = %s,",
9846 get_tree_code_name (TREE_CODE (ret_type
)));
9849 if (cum
->call_cookie
& CALL_LONG
)
9850 fprintf (stderr
, " longcall,");
9852 fprintf (stderr
, " proto = %d, nargs = %d\n",
9853 cum
->prototype
, cum
->nargs_prototype
);
9856 #ifdef HAVE_AS_GNU_ATTRIBUTE
9857 if (DEFAULT_ABI
== ABI_V4
)
9859 cum
->escapes
= call_ABI_of_interest (fndecl
);
9866 return_type
= TREE_TYPE (fntype
);
9867 return_mode
= TYPE_MODE (return_type
);
9870 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9872 if (return_type
!= NULL
)
9874 if (TREE_CODE (return_type
) == RECORD_TYPE
9875 && TYPE_TRANSPARENT_AGGR (return_type
))
9877 return_type
= TREE_TYPE (first_field (return_type
));
9878 return_mode
= TYPE_MODE (return_type
);
9880 if (AGGREGATE_TYPE_P (return_type
)
9881 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9883 rs6000_returns_struct
= true;
9885 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (return_mode
))
9886 rs6000_passes_float
= true;
9887 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9888 || SPE_VECTOR_MODE (return_mode
))
9889 rs6000_passes_vector
= true;
9896 && TARGET_ALTIVEC_ABI
9897 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9899 error ("cannot return value in vector register because"
9900 " altivec instructions are disabled, use -maltivec"
9905 /* The mode the ABI uses for a word. This is not the same as word_mode
9906 for -m32 -mpowerpc64. This is used to implement various target hooks. */
9909 rs6000_abi_word_mode (void)
9911 return TARGET_32BIT
? SImode
: DImode
;
9914 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
9916 rs6000_offload_options (void)
9919 return xstrdup ("-foffload-abi=lp64");
9921 return xstrdup ("-foffload-abi=ilp32");
9924 /* On rs6000, function arguments are promoted, as are function return
9928 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
9930 int *punsignedp ATTRIBUTE_UNUSED
,
9933 PROMOTE_MODE (mode
, *punsignedp
, type
);
9938 /* Return true if TYPE must be passed on the stack and not in registers. */
9941 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
9943 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9944 return must_pass_in_stack_var_size (mode
, type
);
9946 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9949 /* If defined, a C expression which determines whether, and in which
9950 direction, to pad out an argument with extra space. The value
9951 should be of type `enum direction': either `upward' to pad above
9952 the argument, `downward' to pad below, or `none' to inhibit
9955 For the AIX ABI structs are always stored left shifted in their
9959 function_arg_padding (machine_mode mode
, const_tree type
)
9961 #ifndef AGGREGATE_PADDING_FIXED
9962 #define AGGREGATE_PADDING_FIXED 0
9964 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9965 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9968 if (!AGGREGATE_PADDING_FIXED
)
9970 /* GCC used to pass structures of the same size as integer types as
9971 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9972 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9973 passed padded downward, except that -mstrict-align further
9974 muddied the water in that multi-component structures of 2 and 4
9975 bytes in size were passed padded upward.
9977 The following arranges for best compatibility with previous
9978 versions of gcc, but removes the -mstrict-align dependency. */
9979 if (BYTES_BIG_ENDIAN
)
9981 HOST_WIDE_INT size
= 0;
9983 if (mode
== BLKmode
)
9985 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9986 size
= int_size_in_bytes (type
);
9989 size
= GET_MODE_SIZE (mode
);
9991 if (size
== 1 || size
== 2 || size
== 4)
9997 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9999 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
10003 /* Fall back to the default. */
10004 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
10007 /* If defined, a C expression that gives the alignment boundary, in bits,
10008 of an argument with the specified mode and type. If it is not defined,
10009 PARM_BOUNDARY is used for all arguments.
10011 V.4 wants long longs and doubles to be double word aligned. Just
10012 testing the mode size is a boneheaded way to do this as it means
10013 that other types such as complex int are also double word aligned.
10014 However, we're stuck with this because changing the ABI might break
10015 existing library interfaces.
10017 Doubleword align SPE vectors.
10018 Quadword align Altivec/VSX vectors.
10019 Quadword align large synthetic vector types. */
10021 static unsigned int
10022 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
10024 machine_mode elt_mode
;
10027 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10029 if (DEFAULT_ABI
== ABI_V4
10030 && (GET_MODE_SIZE (mode
) == 8
10031 || (TARGET_HARD_FLOAT
10033 && FLOAT128_2REG_P (mode
))))
10035 else if (FLOAT128_VECTOR_P (mode
))
10037 else if (SPE_VECTOR_MODE (mode
)
10038 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10039 && int_size_in_bytes (type
) >= 8
10040 && int_size_in_bytes (type
) < 16))
10042 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
10043 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10044 && int_size_in_bytes (type
) >= 16))
10047 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10048 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10049 -mcompat-align-parm is used. */
10050 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
10051 || DEFAULT_ABI
== ABI_ELFv2
)
10052 && type
&& TYPE_ALIGN (type
) > 64)
10054 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10055 or homogeneous float/vector aggregates here. We already handled
10056 vector aggregates above, but still need to check for float here. */
10057 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
10058 && !SCALAR_FLOAT_MODE_P (elt_mode
));
10060 /* We used to check for BLKmode instead of the above aggregate type
10061 check. Warn when this results in any difference to the ABI. */
10062 if (aggregate_p
!= (mode
== BLKmode
))
10064 static bool warned
;
10065 if (!warned
&& warn_psabi
)
10068 inform (input_location
,
10069 "the ABI of passing aggregates with %d-byte alignment"
10070 " has changed in GCC 5",
10071 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
10079 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10080 implement the "aggregate type" check as a BLKmode check here; this
10081 means certain aggregate types are in fact not aligned. */
10082 if (TARGET_MACHO
&& rs6000_darwin64_abi
10084 && type
&& TYPE_ALIGN (type
) > 64)
10087 return PARM_BOUNDARY
;
10090 /* The offset in words to the start of the parameter save area. */
10092 static unsigned int
10093 rs6000_parm_offset (void)
10095 return (DEFAULT_ABI
== ABI_V4
? 2
10096 : DEFAULT_ABI
== ABI_ELFv2
? 4
10100 /* For a function parm of MODE and TYPE, return the starting word in
10101 the parameter area. NWORDS of the parameter area are already used. */
10103 static unsigned int
10104 rs6000_parm_start (machine_mode mode
, const_tree type
,
10105 unsigned int nwords
)
10107 unsigned int align
;
10109 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
10110 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
10113 /* Compute the size (in words) of a function argument. */
10115 static unsigned long
10116 rs6000_arg_size (machine_mode mode
, const_tree type
)
10118 unsigned long size
;
10120 if (mode
!= BLKmode
)
10121 size
= GET_MODE_SIZE (mode
);
10123 size
= int_size_in_bytes (type
);
10126 return (size
+ 3) >> 2;
10128 return (size
+ 7) >> 3;
10131 /* Use this to flush pending int fields. */
10134 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
10135 HOST_WIDE_INT bitpos
, int final
)
10137 unsigned int startbit
, endbit
;
10138 int intregs
, intoffset
;
10141 /* Handle the situations where a float is taking up the first half
10142 of the GPR, and the other half is empty (typically due to
10143 alignment restrictions). We can detect this by a 8-byte-aligned
10144 int field, or by seeing that this is the final flush for this
10145 argument. Count the word and continue on. */
10146 if (cum
->floats_in_gpr
== 1
10147 && (cum
->intoffset
% 64 == 0
10148 || (cum
->intoffset
== -1 && final
)))
10151 cum
->floats_in_gpr
= 0;
10154 if (cum
->intoffset
== -1)
10157 intoffset
= cum
->intoffset
;
10158 cum
->intoffset
= -1;
10159 cum
->floats_in_gpr
= 0;
10161 if (intoffset
% BITS_PER_WORD
!= 0)
10163 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
10165 if (mode
== BLKmode
)
10167 /* We couldn't find an appropriate mode, which happens,
10168 e.g., in packed structs when there are 3 bytes to load.
10169 Back intoffset back to the beginning of the word in this
10171 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
10175 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
10176 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
10177 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
10178 cum
->words
+= intregs
;
10179 /* words should be unsigned. */
10180 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
10182 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
10187 /* The darwin64 ABI calls for us to recurse down through structs,
10188 looking for elements passed in registers. Unfortunately, we have
10189 to track int register count here also because of misalignments
10190 in powerpc alignment mode. */
10193 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
10195 HOST_WIDE_INT startbitpos
)
10199 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
10200 if (TREE_CODE (f
) == FIELD_DECL
)
10202 HOST_WIDE_INT bitpos
= startbitpos
;
10203 tree ftype
= TREE_TYPE (f
);
10205 if (ftype
== error_mark_node
)
10207 mode
= TYPE_MODE (ftype
);
10209 if (DECL_SIZE (f
) != 0
10210 && tree_fits_uhwi_p (bit_position (f
)))
10211 bitpos
+= int_bit_position (f
);
10213 /* ??? FIXME: else assume zero offset. */
10215 if (TREE_CODE (ftype
) == RECORD_TYPE
)
10216 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
10217 else if (USE_FP_FOR_ARG_P (cum
, mode
))
10219 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
10220 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
10221 cum
->fregno
+= n_fpregs
;
10222 /* Single-precision floats present a special problem for
10223 us, because they are smaller than an 8-byte GPR, and so
10224 the structure-packing rules combined with the standard
10225 varargs behavior mean that we want to pack float/float
10226 and float/int combinations into a single register's
10227 space. This is complicated by the arg advance flushing,
10228 which works on arbitrarily large groups of int-type
10230 if (mode
== SFmode
)
10232 if (cum
->floats_in_gpr
== 1)
10234 /* Two floats in a word; count the word and reset
10235 the float count. */
10237 cum
->floats_in_gpr
= 0;
10239 else if (bitpos
% 64 == 0)
10241 /* A float at the beginning of an 8-byte word;
10242 count it and put off adjusting cum->words until
10243 we see if a arg advance flush is going to do it
10245 cum
->floats_in_gpr
++;
10249 /* The float is at the end of a word, preceded
10250 by integer fields, so the arg advance flush
10251 just above has already set cum->words and
10252 everything is taken care of. */
10256 cum
->words
+= n_fpregs
;
10258 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
10260 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
10264 else if (cum
->intoffset
== -1)
10265 cum
->intoffset
= bitpos
;
10269 /* Check for an item that needs to be considered specially under the darwin 64
10270 bit ABI. These are record types where the mode is BLK or the structure is
10271 8 bytes in size. */
10273 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
10275 return rs6000_darwin64_abi
10276 && ((mode
== BLKmode
10277 && TREE_CODE (type
) == RECORD_TYPE
10278 && int_size_in_bytes (type
) > 0)
10279 || (type
&& TREE_CODE (type
) == RECORD_TYPE
10280 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
10283 /* Update the data in CUM to advance over an argument
10284 of mode MODE and data type TYPE.
10285 (TYPE is null for libcalls where that information may not be available.)
10287 Note that for args passed by reference, function_arg will be called
10288 with MODE and TYPE set to that of the pointer to the arg, not the arg
10292 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
10293 const_tree type
, bool named
, int depth
)
10295 machine_mode elt_mode
;
10298 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10300 /* Only tick off an argument if we're not recursing. */
10302 cum
->nargs_prototype
--;
10304 #ifdef HAVE_AS_GNU_ATTRIBUTE
10305 if (DEFAULT_ABI
== ABI_V4
10308 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
))
10309 rs6000_passes_float
= true;
10310 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
10311 rs6000_passes_vector
= true;
10312 else if (SPE_VECTOR_MODE (mode
)
10314 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
10315 rs6000_passes_vector
= true;
10319 if (TARGET_ALTIVEC_ABI
10320 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
10321 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10322 && int_size_in_bytes (type
) == 16)))
10324 bool stack
= false;
10326 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10328 cum
->vregno
+= n_elts
;
10330 if (!TARGET_ALTIVEC
)
10331 error ("cannot pass argument in vector register because"
10332 " altivec instructions are disabled, use -maltivec"
10333 " to enable them");
10335 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
10336 even if it is going to be passed in a vector register.
10337 Darwin does the same for variable-argument functions. */
10338 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10340 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
10350 /* Vector parameters must be 16-byte aligned. In 32-bit
10351 mode this means we need to take into account the offset
10352 to the parameter save area. In 64-bit mode, they just
10353 have to start on an even word, since the parameter save
10354 area is 16-byte aligned. */
10356 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10358 align
= cum
->words
& 1;
10359 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
10361 if (TARGET_DEBUG_ARG
)
10363 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
10364 cum
->words
, align
);
10365 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
10366 cum
->nargs_prototype
, cum
->prototype
,
10367 GET_MODE_NAME (mode
));
10371 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
10373 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
10374 cum
->sysv_gregno
++;
10376 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10378 int size
= int_size_in_bytes (type
);
10379 /* Variable sized types have size == -1 and are
10380 treated as if consisting entirely of ints.
10381 Pad to 16 byte boundary if needed. */
10382 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
10383 && (cum
->words
% 2) != 0)
10385 /* For varargs, we can just go up by the size of the struct. */
10387 cum
->words
+= (size
+ 7) / 8;
10390 /* It is tempting to say int register count just goes up by
10391 sizeof(type)/8, but this is wrong in a case such as
10392 { int; double; int; } [powerpc alignment]. We have to
10393 grovel through the fields for these too. */
10394 cum
->intoffset
= 0;
10395 cum
->floats_in_gpr
= 0;
10396 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
10397 rs6000_darwin64_record_arg_advance_flush (cum
,
10398 size
* BITS_PER_UNIT
, 1);
10400 if (TARGET_DEBUG_ARG
)
10402 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
10403 cum
->words
, TYPE_ALIGN (type
), size
);
10405 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
10406 cum
->nargs_prototype
, cum
->prototype
,
10407 GET_MODE_NAME (mode
));
10410 else if (DEFAULT_ABI
== ABI_V4
)
10412 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10413 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10414 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10415 || FLOAT128_2REG_P (mode
)
10416 || DECIMAL_FLOAT_MODE_P (mode
)))
10418 /* _Decimal128 must use an even/odd register pair. This assumes
10419 that the register number is odd when fregno is odd. */
10420 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10423 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
10424 <= FP_ARG_V4_MAX_REG
)
10425 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
10428 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
10429 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
10430 || mode
== DDmode
|| mode
== TDmode
)
10431 cum
->words
+= cum
->words
& 1;
10432 cum
->words
+= rs6000_arg_size (mode
, type
);
10437 int n_words
= rs6000_arg_size (mode
, type
);
10438 int gregno
= cum
->sysv_gregno
;
10440 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10441 (r7,r8) or (r9,r10). As does any other 2 word item such
10442 as complex int due to a historical mistake. */
10444 gregno
+= (1 - gregno
) & 1;
10446 /* Multi-reg args are not split between registers and stack. */
10447 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10449 /* Long long and SPE vectors are aligned on the stack.
10450 So are other 2 word items such as complex int due to
10451 a historical mistake. */
10453 cum
->words
+= cum
->words
& 1;
10454 cum
->words
+= n_words
;
10457 /* Note: continuing to accumulate gregno past when we've started
10458 spilling to the stack indicates the fact that we've started
10459 spilling to the stack to expand_builtin_saveregs. */
10460 cum
->sysv_gregno
= gregno
+ n_words
;
10463 if (TARGET_DEBUG_ARG
)
10465 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
10466 cum
->words
, cum
->fregno
);
10467 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
10468 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
10469 fprintf (stderr
, "mode = %4s, named = %d\n",
10470 GET_MODE_NAME (mode
), named
);
10475 int n_words
= rs6000_arg_size (mode
, type
);
10476 int start_words
= cum
->words
;
10477 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
10479 cum
->words
= align_words
+ n_words
;
10481 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10483 /* _Decimal128 must be passed in an even/odd float register pair.
10484 This assumes that the register number is odd when fregno is
10486 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10488 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
10491 if (TARGET_DEBUG_ARG
)
10493 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
10494 cum
->words
, cum
->fregno
);
10495 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
10496 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
10497 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
10498 named
, align_words
- start_words
, depth
);
10504 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
10505 const_tree type
, bool named
)
10507 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
10512 spe_build_register_parallel (machine_mode mode
, int gregno
)
10514 rtx r1
, r3
, r5
, r7
;
10519 r1
= gen_rtx_REG (DImode
, gregno
);
10520 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10521 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
10525 r1
= gen_rtx_REG (DImode
, gregno
);
10526 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10527 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
10528 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
10529 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
10532 r1
= gen_rtx_REG (DImode
, gregno
);
10533 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10534 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
10535 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
10536 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
10537 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
10538 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
10539 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
10540 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
10543 gcc_unreachable ();
10547 /* Determine where to put a SIMD argument on the SPE. */
10549 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, machine_mode mode
,
10552 int gregno
= cum
->sysv_gregno
;
10554 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
10555 are passed and returned in a pair of GPRs for ABI compatibility. */
10556 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
10557 || mode
== DCmode
|| mode
== TCmode
))
10559 int n_words
= rs6000_arg_size (mode
, type
);
10561 /* Doubles go in an odd/even register pair (r5/r6, etc). */
10562 if (mode
== DFmode
)
10563 gregno
+= (1 - gregno
) & 1;
10565 /* Multi-reg args are not split between registers and stack. */
10566 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10569 return spe_build_register_parallel (mode
, gregno
);
10573 int n_words
= rs6000_arg_size (mode
, type
);
10575 /* SPE vectors are put in odd registers. */
10576 if (n_words
== 2 && (gregno
& 1) == 0)
10579 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
10582 machine_mode m
= SImode
;
10584 r1
= gen_rtx_REG (m
, gregno
);
10585 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
10586 r2
= gen_rtx_REG (m
, gregno
+ 1);
10587 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
10588 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
10595 if (gregno
<= GP_ARG_MAX_REG
)
10596 return gen_rtx_REG (mode
, gregno
);
10602 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
10603 structure between cum->intoffset and bitpos to integer registers. */
10606 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
10607 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
10610 unsigned int regno
;
10611 unsigned int startbit
, endbit
;
10612 int this_regno
, intregs
, intoffset
;
10615 if (cum
->intoffset
== -1)
10618 intoffset
= cum
->intoffset
;
10619 cum
->intoffset
= -1;
10621 /* If this is the trailing part of a word, try to only load that
10622 much into the register. Otherwise load the whole register. Note
10623 that in the latter case we may pick up unwanted bits. It's not a
10624 problem at the moment but may wish to revisit. */
10626 if (intoffset
% BITS_PER_WORD
!= 0)
10628 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
10630 if (mode
== BLKmode
)
10632 /* We couldn't find an appropriate mode, which happens,
10633 e.g., in packed structs when there are 3 bytes to load.
10634 Back intoffset back to the beginning of the word in this
10636 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
10643 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
10644 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
10645 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
10646 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
10648 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
10649 cum
->use_stack
= 1;
10651 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
10655 intoffset
/= BITS_PER_UNIT
;
10658 regno
= GP_ARG_MIN_REG
+ this_regno
;
10659 reg
= gen_rtx_REG (mode
, regno
);
10661 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
10664 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
10668 while (intregs
> 0);
10671 /* Recursive workhorse for the following. */
10674 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
10675 HOST_WIDE_INT startbitpos
, rtx rvec
[],
10680 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
10681 if (TREE_CODE (f
) == FIELD_DECL
)
10683 HOST_WIDE_INT bitpos
= startbitpos
;
10684 tree ftype
= TREE_TYPE (f
);
10686 if (ftype
== error_mark_node
)
10688 mode
= TYPE_MODE (ftype
);
10690 if (DECL_SIZE (f
) != 0
10691 && tree_fits_uhwi_p (bit_position (f
)))
10692 bitpos
+= int_bit_position (f
);
10694 /* ??? FIXME: else assume zero offset. */
10696 if (TREE_CODE (ftype
) == RECORD_TYPE
)
10697 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
10698 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
10700 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
10704 case SCmode
: mode
= SFmode
; break;
10705 case DCmode
: mode
= DFmode
; break;
10706 case TCmode
: mode
= TFmode
; break;
10710 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
10711 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
10713 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
10714 && (mode
== TFmode
|| mode
== TDmode
));
10715 /* Long double or _Decimal128 split over regs and memory. */
10716 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
10720 = gen_rtx_EXPR_LIST (VOIDmode
,
10721 gen_rtx_REG (mode
, cum
->fregno
++),
10722 GEN_INT (bitpos
/ BITS_PER_UNIT
));
10723 if (FLOAT128_2REG_P (mode
))
10726 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
10728 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
10730 = gen_rtx_EXPR_LIST (VOIDmode
,
10731 gen_rtx_REG (mode
, cum
->vregno
++),
10732 GEN_INT (bitpos
/ BITS_PER_UNIT
));
10734 else if (cum
->intoffset
== -1)
10735 cum
->intoffset
= bitpos
;
10739 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
10740 the register(s) to be used for each field and subfield of a struct
10741 being passed by value, along with the offset of where the
10742 register's value may be found in the block. FP fields go in FP
10743 register, vector fields go in vector registers, and everything
10744 else goes in int registers, packed as in memory.
10746 This code is also used for function return values. RETVAL indicates
10747 whether this is the case.
10749 Much of this is taken from the SPARC V9 port, which has a similar
10750 calling convention. */
10753 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
10754 bool named
, bool retval
)
10756 rtx rvec
[FIRST_PSEUDO_REGISTER
];
10757 int k
= 1, kbase
= 1;
10758 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
10759 /* This is a copy; modifications are not visible to our caller. */
10760 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
10761 CUMULATIVE_ARGS
*cum
= ©_cum
;
10763 /* Pad to 16 byte boundary if needed. */
10764 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
10765 && (cum
->words
% 2) != 0)
10768 cum
->intoffset
= 0;
10769 cum
->use_stack
= 0;
10770 cum
->named
= named
;
10772 /* Put entries into rvec[] for individual FP and vector fields, and
10773 for the chunks of memory that go in int regs. Note we start at
10774 element 1; 0 is reserved for an indication of using memory, and
10775 may or may not be filled in below. */
10776 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
10777 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
10779 /* If any part of the struct went on the stack put all of it there.
10780 This hack is because the generic code for
10781 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
10782 parts of the struct are not at the beginning. */
10783 if (cum
->use_stack
)
10786 return NULL_RTX
; /* doesn't go in registers at all */
10788 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10790 if (k
> 1 || cum
->use_stack
)
10791 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
10796 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
10799 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
10804 rtx rvec
[GP_ARG_NUM_REG
+ 1];
10806 if (align_words
>= GP_ARG_NUM_REG
)
10809 n_units
= rs6000_arg_size (mode
, type
);
10811 /* Optimize the simple case where the arg fits in one gpr, except in
10812 the case of BLKmode due to assign_parms assuming that registers are
10813 BITS_PER_WORD wide. */
10815 || (n_units
== 1 && mode
!= BLKmode
))
10816 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10819 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
10820 /* Not all of the arg fits in gprs. Say that it goes in memory too,
10821 using a magic NULL_RTX component.
10822 This is not strictly correct. Only some of the arg belongs in
10823 memory, not all of it. However, the normal scheme using
10824 function_arg_partial_nregs can result in unusual subregs, eg.
10825 (subreg:SI (reg:DF) 4), which are not handled well. The code to
10826 store the whole arg to memory is often more efficient than code
10827 to store pieces, and we know that space is available in the right
10828 place for the whole arg. */
10829 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10834 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
10835 rtx off
= GEN_INT (i
++ * 4);
10836 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10838 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
10840 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10843 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
10844 but must also be copied into the parameter save area starting at
10845 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
10846 to the GPRs and/or memory. Return the number of elements used. */
10849 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
10850 int align_words
, rtx
*rvec
)
10854 if (align_words
< GP_ARG_NUM_REG
)
10856 int n_words
= rs6000_arg_size (mode
, type
);
10858 if (align_words
+ n_words
> GP_ARG_NUM_REG
10860 || (TARGET_32BIT
&& TARGET_POWERPC64
))
10862 /* If this is partially on the stack, then we only
10863 include the portion actually in registers here. */
10864 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10867 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10869 /* Not all of the arg fits in gprs. Say that it goes in memory
10870 too, using a magic NULL_RTX component. Also see comment in
10871 rs6000_mixed_function_arg for why the normal
10872 function_arg_partial_nregs scheme doesn't work in this case. */
10873 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10878 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10879 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
10880 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10882 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10886 /* The whole arg fits in gprs. */
10887 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10888 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
10893 /* It's entirely in memory. */
10894 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10900 /* RVEC is a vector of K components of an argument of mode MODE.
10901 Construct the final function_arg return value from it. */
10904 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
10906 gcc_assert (k
>= 1);
10908 /* Avoid returning a PARALLEL in the trivial cases. */
10911 if (XEXP (rvec
[0], 0) == NULL_RTX
)
10914 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
10915 return XEXP (rvec
[0], 0);
10918 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10921 /* Determine where to put an argument to a function.
10922 Value is zero to push the argument on the stack,
10923 or a hard register in which to store the argument.
10925 MODE is the argument's machine mode.
10926 TYPE is the data type of the argument (as a tree).
10927 This is null for libcalls where that information may
10929 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10930 the preceding args and about the function being called. It is
10931 not modified in this routine.
10932 NAMED is nonzero if this argument is a named parameter
10933 (otherwise it is an extra parameter matching an ellipsis).
10935 On RS/6000 the first eight words of non-FP are normally in registers
10936 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10937 Under V.4, the first 8 FP args are in registers.
10939 If this is floating-point and no prototype is specified, we use
10940 both an FP and integer register (or possibly FP reg and stack). Library
10941 functions (when CALL_LIBCALL is set) always have the proper types for args,
10942 so we can pass the FP value just in one register. emit_library_function
10943 doesn't support PARALLEL anyway.
10945 Note that for args passed by reference, function_arg will be called
10946 with MODE and TYPE set to that of the pointer to the arg, not the arg
10950 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
10951 const_tree type
, bool named
)
10953 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10954 enum rs6000_abi abi
= DEFAULT_ABI
;
10955 machine_mode elt_mode
;
10958 /* Return a marker to indicate whether CR1 needs to set or clear the
10959 bit that V.4 uses to say fp args were passed in registers.
10960 Assume that we don't need the marker for software floating point,
10961 or compiler generated library calls. */
10962 if (mode
== VOIDmode
)
10965 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10967 || (cum
->nargs_prototype
< 0
10968 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10970 /* For the SPE, we need to crxor CR6 always. */
10971 if (TARGET_SPE_ABI
)
10972 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10973 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10974 return GEN_INT (cum
->call_cookie
10975 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10976 ? CALL_V4_SET_FP_ARGS
10977 : CALL_V4_CLEAR_FP_ARGS
));
10980 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10983 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10985 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10987 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10988 if (rslt
!= NULL_RTX
)
10990 /* Else fall through to usual handling. */
10993 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10995 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10999 /* Do we also need to pass this argument in the parameter save area?
11000 Library support functions for IEEE 128-bit are assumed to not need the
11001 value passed both in GPRs and in vector registers. */
11002 if (TARGET_64BIT
&& !cum
->prototype
11003 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
11005 int align_words
= ROUND_UP (cum
->words
, 2);
11006 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11009 /* Describe where this argument goes in the vector registers. */
11010 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
11012 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
11013 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11014 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11017 return rs6000_finish_function_arg (mode
, rvec
, k
);
11019 else if (TARGET_ALTIVEC_ABI
11020 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
11021 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11022 && int_size_in_bytes (type
) == 16)))
11024 if (named
|| abi
== ABI_V4
)
11028 /* Vector parameters to varargs functions under AIX or Darwin
11029 get passed in memory and possibly also in GPRs. */
11030 int align
, align_words
, n_words
;
11031 machine_mode part_mode
;
11033 /* Vector parameters must be 16-byte aligned. In 32-bit
11034 mode this means we need to take into account the offset
11035 to the parameter save area. In 64-bit mode, they just
11036 have to start on an even word, since the parameter save
11037 area is 16-byte aligned. */
11039 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11041 align
= cum
->words
& 1;
11042 align_words
= cum
->words
+ align
;
11044 /* Out of registers? Memory, then. */
11045 if (align_words
>= GP_ARG_NUM_REG
)
11048 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11049 return rs6000_mixed_function_arg (mode
, type
, align_words
);
11051 /* The vector value goes in GPRs. Only the part of the
11052 value in GPRs is reported here. */
11054 n_words
= rs6000_arg_size (mode
, type
);
11055 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
11056 /* Fortunately, there are only two possibilities, the value
11057 is either wholly in GPRs or half in GPRs and half not. */
11058 part_mode
= DImode
;
11060 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
11063 else if (TARGET_SPE_ABI
&& TARGET_SPE
11064 && (SPE_VECTOR_MODE (mode
)
11065 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
11068 || mode
== TCmode
))))
11069 return rs6000_spe_function_arg (cum
, mode
, type
);
11071 else if (abi
== ABI_V4
)
11073 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11074 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
11075 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
11076 || FLOAT128_2REG_P (mode
)
11077 || DECIMAL_FLOAT_MODE_P (mode
)))
11079 /* _Decimal128 must use an even/odd register pair. This assumes
11080 that the register number is odd when fregno is odd. */
11081 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11084 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11085 <= FP_ARG_V4_MAX_REG
)
11086 return gen_rtx_REG (mode
, cum
->fregno
);
11092 int n_words
= rs6000_arg_size (mode
, type
);
11093 int gregno
= cum
->sysv_gregno
;
11095 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
11096 (r7,r8) or (r9,r10). As does any other 2 word item such
11097 as complex int due to a historical mistake. */
11099 gregno
+= (1 - gregno
) & 1;
11101 /* Multi-reg args are not split between registers and stack. */
11102 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11105 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11106 return rs6000_mixed_function_arg (mode
, type
,
11107 gregno
- GP_ARG_MIN_REG
);
11108 return gen_rtx_REG (mode
, gregno
);
11113 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
11115 /* _Decimal128 must be passed in an even/odd float register pair.
11116 This assumes that the register number is odd when fregno is odd. */
11117 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11120 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
11122 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
11125 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
11128 /* Do we also need to pass this argument in the parameter
11130 if (type
&& (cum
->nargs_prototype
<= 0
11131 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11132 && TARGET_XL_COMPAT
11133 && align_words
>= GP_ARG_NUM_REG
)))
11134 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
11136 /* Describe where this argument goes in the fprs. */
11137 for (i
= 0; i
< n_elts
11138 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
11140 /* Check if the argument is split over registers and memory.
11141 This can only ever happen for long double or _Decimal128;
11142 complex types are handled via split_complex_arg. */
11143 machine_mode fmode
= elt_mode
;
11144 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
11146 gcc_assert (FLOAT128_2REG_P (fmode
));
11147 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
11150 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
11151 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
11152 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11155 /* If there were not enough FPRs to hold the argument, the rest
11156 usually goes into memory. However, if the current position
11157 is still within the register parameter area, a portion may
11158 actually have to go into GPRs.
11160 Note that it may happen that the portion of the argument
11161 passed in the first "half" of the first GPR was already
11162 passed in the last FPR as well.
11164 For unnamed arguments, we already set up GPRs to cover the
11165 whole argument in rs6000_psave_function_arg, so there is
11166 nothing further to do at this point. */
11167 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
11168 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
11169 && cum
->nargs_prototype
> 0)
11171 static bool warned
;
11173 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
11174 int n_words
= rs6000_arg_size (mode
, type
);
11176 align_words
+= fpr_words
;
11177 n_words
-= fpr_words
;
11181 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
11182 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
11183 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
11185 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
11187 if (!warned
&& warn_psabi
)
11190 inform (input_location
,
11191 "the ABI of passing homogeneous float aggregates"
11192 " has changed in GCC 5");
11196 return rs6000_finish_function_arg (mode
, rvec
, k
);
11198 else if (align_words
< GP_ARG_NUM_REG
)
11200 if (TARGET_32BIT
&& TARGET_POWERPC64
)
11201 return rs6000_mixed_function_arg (mode
, type
, align_words
);
11203 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
11210 /* For an arg passed partly in registers and partly in memory, this is
11211 the number of bytes passed in registers. For args passed entirely in
11212 registers or entirely in memory, zero. When an arg is described by a
11213 PARALLEL, perhaps using more than one register type, this function
11214 returns the number of bytes used by the first element of the PARALLEL. */
11217 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
11218 tree type
, bool named
)
11220 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11221 bool passed_in_gprs
= true;
11224 machine_mode elt_mode
;
11227 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11229 if (DEFAULT_ABI
== ABI_V4
)
11232 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11234 /* If we are passing this arg in the fixed parameter save area (gprs or
11235 memory) as well as VRs, we do not use the partial bytes mechanism;
11236 instead, rs6000_function_arg will return a PARALLEL including a memory
11237 element as necessary. Library support functions for IEEE 128-bit are
11238 assumed to not need the value passed both in GPRs and in vector
11240 if (TARGET_64BIT
&& !cum
->prototype
11241 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
11244 /* Otherwise, we pass in VRs only. Check for partial copies. */
11245 passed_in_gprs
= false;
11246 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
11247 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
11250 /* In this complicated case we just disable the partial_nregs code. */
11251 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11254 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
11256 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
11258 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
11260 /* If we are passing this arg in the fixed parameter save area
11261 (gprs or memory) as well as FPRs, we do not use the partial
11262 bytes mechanism; instead, rs6000_function_arg will return a
11263 PARALLEL including a memory element as necessary. */
11265 && (cum
->nargs_prototype
<= 0
11266 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11267 && TARGET_XL_COMPAT
11268 && align_words
>= GP_ARG_NUM_REG
)))
11271 /* Otherwise, we pass in FPRs only. Check for partial copies. */
11272 passed_in_gprs
= false;
11273 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
11275 /* Compute number of bytes / words passed in FPRs. If there
11276 is still space available in the register parameter area
11277 *after* that amount, a part of the argument will be passed
11278 in GPRs. In that case, the total amount passed in any
11279 registers is equal to the amount that would have been passed
11280 in GPRs if everything were passed there, so we fall back to
11281 the GPR code below to compute the appropriate value. */
11282 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
11283 * MIN (8, GET_MODE_SIZE (elt_mode
)));
11284 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
11286 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
11287 passed_in_gprs
= true;
11294 && align_words
< GP_ARG_NUM_REG
11295 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
11296 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
11298 if (ret
!= 0 && TARGET_DEBUG_ARG
)
11299 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
11304 /* A C expression that indicates when an argument must be passed by
11305 reference. If nonzero for an argument, a copy of that argument is
11306 made in memory and a pointer to the argument is passed instead of
11307 the argument itself. The pointer is passed in whatever way is
11308 appropriate for passing a pointer to that type.
11310 Under V.4, aggregates and long double are passed by reference.
11312 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
11313 reference unless the AltiVec vector extension ABI is in force.
11315 As an extension to all ABIs, variable sized types are passed by
11319 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
11320 machine_mode mode
, const_tree type
,
11321 bool named ATTRIBUTE_UNUSED
)
11326 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
11327 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
11329 if (TARGET_DEBUG_ARG
)
11330 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
11334 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
11336 if (TARGET_DEBUG_ARG
)
11337 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
11341 if (int_size_in_bytes (type
) < 0)
11343 if (TARGET_DEBUG_ARG
)
11344 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
11348 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11349 modes only exist for GCC vector types if -maltivec. */
11350 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
11352 if (TARGET_DEBUG_ARG
)
11353 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
11357 /* Pass synthetic vectors in memory. */
11358 if (TREE_CODE (type
) == VECTOR_TYPE
11359 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
11361 static bool warned_for_pass_big_vectors
= false;
11362 if (TARGET_DEBUG_ARG
)
11363 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
11364 if (!warned_for_pass_big_vectors
)
11366 warning (0, "GCC vector passed by reference: "
11367 "non-standard ABI extension with no compatibility guarantee");
11368 warned_for_pass_big_vectors
= true;
11376 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
11377 already processes. Return true if the parameter must be passed
11378 (fully or partially) on the stack. */
11381 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
11387 /* Catch errors. */
11388 if (type
== NULL
|| type
== error_mark_node
)
11391 /* Handle types with no storage requirement. */
11392 if (TYPE_MODE (type
) == VOIDmode
)
11395 /* Handle complex types. */
11396 if (TREE_CODE (type
) == COMPLEX_TYPE
)
11397 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
11398 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
11400 /* Handle transparent aggregates. */
11401 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
11402 && TYPE_TRANSPARENT_AGGR (type
))
11403 type
= TREE_TYPE (first_field (type
));
11405 /* See if this arg was passed by invisible reference. */
11406 if (pass_by_reference (get_cumulative_args (args_so_far
),
11407 TYPE_MODE (type
), type
, true))
11408 type
= build_pointer_type (type
);
11410 /* Find mode as it is passed by the ABI. */
11411 unsignedp
= TYPE_UNSIGNED (type
);
11412 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
11414 /* If we must pass in stack, we need a stack. */
11415 if (rs6000_must_pass_in_stack (mode
, type
))
11418 /* If there is no incoming register, we need a stack. */
11419 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
11420 if (entry_parm
== NULL
)
11423 /* Likewise if we need to pass both in registers and on the stack. */
11424 if (GET_CODE (entry_parm
) == PARALLEL
11425 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
11428 /* Also true if we're partially in registers and partially not. */
11429 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
11432 /* Update info on where next arg arrives in registers. */
11433 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
11437 /* Return true if FUN has no prototype, has a variable argument
11438 list, or passes any parameter in memory. */
11441 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
11443 tree fntype
, result
;
11444 CUMULATIVE_ARGS args_so_far_v
;
11445 cumulative_args_t args_so_far
;
11448 /* Must be a libcall, all of which only use reg parms. */
11453 fntype
= TREE_TYPE (fun
);
11455 /* Varargs functions need the parameter save area. */
11456 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
11459 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
11460 args_so_far
= pack_cumulative_args (&args_so_far_v
);
11462 /* When incoming, we will have been passed the function decl.
11463 It is necessary to use the decl to handle K&R style functions,
11464 where TYPE_ARG_TYPES may not be available. */
11467 gcc_assert (DECL_P (fun
));
11468 result
= DECL_RESULT (fun
);
11471 result
= TREE_TYPE (fntype
);
11473 if (result
&& aggregate_value_p (result
, fntype
))
11475 if (!TYPE_P (result
))
11476 result
= TREE_TYPE (result
);
11477 result
= build_pointer_type (result
);
11478 rs6000_parm_needs_stack (args_so_far
, result
);
11485 for (parm
= DECL_ARGUMENTS (fun
);
11486 parm
&& parm
!= void_list_node
;
11487 parm
= TREE_CHAIN (parm
))
11488 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
11493 function_args_iterator args_iter
;
11496 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
11497 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
11504 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
11505 usually a constant depending on the ABI. However, in the ELFv2 ABI
11506 the register parameter area is optional when calling a function that
11507 has a prototype is scope, has no variable argument list, and passes
11508 all parameters in registers. */
11511 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
11513 int reg_parm_stack_space
;
11515 switch (DEFAULT_ABI
)
11518 reg_parm_stack_space
= 0;
11523 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
11527 /* ??? Recomputing this every time is a bit expensive. Is there
11528 a place to cache this information? */
11529 if (rs6000_function_parms_need_stack (fun
, incoming
))
11530 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
11532 reg_parm_stack_space
= 0;
11536 return reg_parm_stack_space
;
11540 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
11543 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
11548 for (i
= 0; i
< nregs
; i
++)
11550 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
11551 if (reload_completed
)
11553 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
11556 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
11557 i
* GET_MODE_SIZE (reg_mode
));
11560 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
11564 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
11568 /* Perform any needed actions needed for a function that is receiving a
11569 variable number of arguments.
11573 MODE and TYPE are the mode and type of the current parameter.
11575 PRETEND_SIZE is a variable that should be set to the amount of stack
11576 that must be pushed by the prolog to pretend that our caller pushed
11579 Normally, this macro will push all remaining incoming registers on the
11580 stack and set PRETEND_SIZE to the length of the registers pushed. */
11583 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
11584 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
11587 CUMULATIVE_ARGS next_cum
;
11588 int reg_size
= TARGET_32BIT
? 4 : 8;
11589 rtx save_area
= NULL_RTX
, mem
;
11590 int first_reg_offset
;
11591 alias_set_type set
;
11593 /* Skip the last named argument. */
11594 next_cum
= *get_cumulative_args (cum
);
11595 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
11597 if (DEFAULT_ABI
== ABI_V4
)
11599 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
11603 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
11604 HOST_WIDE_INT offset
= 0;
11606 /* Try to optimize the size of the varargs save area.
11607 The ABI requires that ap.reg_save_area is doubleword
11608 aligned, but we don't need to allocate space for all
11609 the bytes, only those to which we actually will save
11611 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
11612 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
11613 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11614 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
11615 && cfun
->va_list_fpr_size
)
11618 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
11619 * UNITS_PER_FP_WORD
;
11620 if (cfun
->va_list_fpr_size
11621 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
11622 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
11624 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
11625 * UNITS_PER_FP_WORD
;
11629 offset
= -((first_reg_offset
* reg_size
) & ~7);
11630 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
11632 gpr_reg_num
= cfun
->va_list_gpr_size
;
11633 if (reg_size
== 4 && (first_reg_offset
& 1))
11636 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
11639 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
11640 * UNITS_PER_FP_WORD
11641 - (int) (GP_ARG_NUM_REG
* reg_size
);
11643 if (gpr_size
+ fpr_size
)
11646 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
11647 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
11648 reg_save_area
= XEXP (reg_save_area
, 0);
11649 if (GET_CODE (reg_save_area
) == PLUS
)
11651 gcc_assert (XEXP (reg_save_area
, 0)
11652 == virtual_stack_vars_rtx
);
11653 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
11654 offset
+= INTVAL (XEXP (reg_save_area
, 1));
11657 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
11660 cfun
->machine
->varargs_save_offset
= offset
;
11661 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
11666 first_reg_offset
= next_cum
.words
;
11667 save_area
= crtl
->args
.internal_arg_pointer
;
11669 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
11670 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
11673 set
= get_varargs_alias_set ();
11674 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
11675 && cfun
->va_list_gpr_size
)
11677 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
11679 if (va_list_gpr_counter_field
)
11680 /* V4 va_list_gpr_size counts number of registers needed. */
11681 n_gpr
= cfun
->va_list_gpr_size
;
11683 /* char * va_list instead counts number of bytes needed. */
11684 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
11689 mem
= gen_rtx_MEM (BLKmode
,
11690 plus_constant (Pmode
, save_area
,
11691 first_reg_offset
* reg_size
));
11692 MEM_NOTRAP_P (mem
) = 1;
11693 set_mem_alias_set (mem
, set
);
11694 set_mem_align (mem
, BITS_PER_WORD
);
11696 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
11700 /* Save FP registers if needed. */
11701 if (DEFAULT_ABI
== ABI_V4
11702 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11704 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
11705 && cfun
->va_list_fpr_size
)
11707 int fregno
= next_cum
.fregno
, nregs
;
11708 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
11709 rtx lab
= gen_label_rtx ();
11710 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
11711 * UNITS_PER_FP_WORD
);
11714 (gen_rtx_SET (pc_rtx
,
11715 gen_rtx_IF_THEN_ELSE (VOIDmode
,
11716 gen_rtx_NE (VOIDmode
, cr1
,
11718 gen_rtx_LABEL_REF (VOIDmode
, lab
),
11722 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
11723 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
11725 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11727 plus_constant (Pmode
, save_area
, off
));
11728 MEM_NOTRAP_P (mem
) = 1;
11729 set_mem_alias_set (mem
, set
);
11730 set_mem_align (mem
, GET_MODE_ALIGNMENT (
11731 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11732 ? DFmode
: SFmode
));
11733 emit_move_insn (mem
, gen_rtx_REG (
11734 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11735 ? DFmode
: SFmode
, fregno
));
11742 /* Create the va_list data type. */
11745 rs6000_build_builtin_va_list (void)
11747 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
11749 /* For AIX, prefer 'char *' because that's what the system
11750 header files like. */
11751 if (DEFAULT_ABI
!= ABI_V4
)
11752 return build_pointer_type (char_type_node
);
11754 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
11755 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
11756 get_identifier ("__va_list_tag"), record
);
11758 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
11759 unsigned_char_type_node
);
11760 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
11761 unsigned_char_type_node
);
11762 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
11763 every user file. */
11764 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11765 get_identifier ("reserved"), short_unsigned_type_node
);
11766 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11767 get_identifier ("overflow_arg_area"),
11769 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11770 get_identifier ("reg_save_area"),
11773 va_list_gpr_counter_field
= f_gpr
;
11774 va_list_fpr_counter_field
= f_fpr
;
11776 DECL_FIELD_CONTEXT (f_gpr
) = record
;
11777 DECL_FIELD_CONTEXT (f_fpr
) = record
;
11778 DECL_FIELD_CONTEXT (f_res
) = record
;
11779 DECL_FIELD_CONTEXT (f_ovf
) = record
;
11780 DECL_FIELD_CONTEXT (f_sav
) = record
;
11782 TYPE_STUB_DECL (record
) = type_decl
;
11783 TYPE_NAME (record
) = type_decl
;
11784 TYPE_FIELDS (record
) = f_gpr
;
11785 DECL_CHAIN (f_gpr
) = f_fpr
;
11786 DECL_CHAIN (f_fpr
) = f_res
;
11787 DECL_CHAIN (f_res
) = f_ovf
;
11788 DECL_CHAIN (f_ovf
) = f_sav
;
11790 layout_type (record
);
11792 /* The correct type is an array type of one element. */
11793 return build_array_type (record
, build_index_type (size_zero_node
));
11796 /* Implement va_start. */
11799 rs6000_va_start (tree valist
, rtx nextarg
)
11801 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
11802 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11803 tree gpr
, fpr
, ovf
, sav
, t
;
11805 /* Only SVR4 needs something special. */
11806 if (DEFAULT_ABI
!= ABI_V4
)
11808 std_expand_builtin_va_start (valist
, nextarg
);
11812 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11813 f_fpr
= DECL_CHAIN (f_gpr
);
11814 f_res
= DECL_CHAIN (f_fpr
);
11815 f_ovf
= DECL_CHAIN (f_res
);
11816 f_sav
= DECL_CHAIN (f_ovf
);
11818 valist
= build_simple_mem_ref (valist
);
11819 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11820 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11822 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11824 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11827 /* Count number of gp and fp argument registers used. */
11828 words
= crtl
->args
.info
.words
;
11829 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
11831 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
11834 if (TARGET_DEBUG_ARG
)
11835 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
11836 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
11837 words
, n_gpr
, n_fpr
);
11839 if (cfun
->va_list_gpr_size
)
11841 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
11842 build_int_cst (NULL_TREE
, n_gpr
));
11843 TREE_SIDE_EFFECTS (t
) = 1;
11844 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11847 if (cfun
->va_list_fpr_size
)
11849 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
11850 build_int_cst (NULL_TREE
, n_fpr
));
11851 TREE_SIDE_EFFECTS (t
) = 1;
11852 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11854 #ifdef HAVE_AS_GNU_ATTRIBUTE
11855 if (call_ABI_of_interest (cfun
->decl
))
11856 rs6000_passes_float
= true;
11860 /* Find the overflow area. */
11861 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
11863 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
11864 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
11865 TREE_SIDE_EFFECTS (t
) = 1;
11866 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11868 /* If there were no va_arg invocations, don't set up the register
11870 if (!cfun
->va_list_gpr_size
11871 && !cfun
->va_list_fpr_size
11872 && n_gpr
< GP_ARG_NUM_REG
11873 && n_fpr
< FP_ARG_V4_MAX_REG
)
11876 /* Find the register save area. */
11877 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
11878 if (cfun
->machine
->varargs_save_offset
)
11879 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
11880 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
11881 TREE_SIDE_EFFECTS (t
) = 1;
11882 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11885 /* Implement va_arg. */
11888 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
11889 gimple_seq
*post_p
)
11891 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11892 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
11893 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
11894 tree lab_false
, lab_over
, addr
;
11896 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
11900 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
11902 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
11903 return build_va_arg_indirect_ref (t
);
11906 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
11907 earlier version of gcc, with the property that it always applied alignment
11908 adjustments to the va-args (even for zero-sized types). The cheapest way
11909 to deal with this is to replicate the effect of the part of
11910 std_gimplify_va_arg_expr that carries out the align adjust, for the case
11912 We don't need to check for pass-by-reference because of the test above.
11913 We can return a simplifed answer, since we know there's no offset to add. */
11916 && rs6000_darwin64_abi
)
11917 || DEFAULT_ABI
== ABI_ELFv2
11918 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
11919 && integer_zerop (TYPE_SIZE (type
)))
11921 unsigned HOST_WIDE_INT align
, boundary
;
11922 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
11923 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
11924 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
11925 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
11926 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
11927 boundary
/= BITS_PER_UNIT
;
11928 if (boundary
> align
)
11931 /* This updates arg ptr by the amount that would be necessary
11932 to align the zero-sized (but not zero-alignment) item. */
11933 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11934 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
11935 gimplify_and_add (t
, pre_p
);
11937 t
= fold_convert (sizetype
, valist_tmp
);
11938 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11939 fold_convert (TREE_TYPE (valist
),
11940 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
11941 size_int (-boundary
))));
11942 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
11943 gimplify_and_add (t
, pre_p
);
11945 /* Since it is zero-sized there's no increment for the item itself. */
11946 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
11947 return build_va_arg_indirect_ref (valist_tmp
);
11950 if (DEFAULT_ABI
!= ABI_V4
)
11952 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
11954 tree elem_type
= TREE_TYPE (type
);
11955 machine_mode elem_mode
= TYPE_MODE (elem_type
);
11956 int elem_size
= GET_MODE_SIZE (elem_mode
);
11958 if (elem_size
< UNITS_PER_WORD
)
11960 tree real_part
, imag_part
;
11961 gimple_seq post
= NULL
;
11963 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11965 /* Copy the value into a temporary, lest the formal temporary
11966 be reused out from under us. */
11967 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
11968 gimple_seq_add_seq (pre_p
, post
);
11970 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11973 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
11977 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
11980 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11981 f_fpr
= DECL_CHAIN (f_gpr
);
11982 f_res
= DECL_CHAIN (f_fpr
);
11983 f_ovf
= DECL_CHAIN (f_res
);
11984 f_sav
= DECL_CHAIN (f_ovf
);
11986 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11987 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11989 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11991 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11994 size
= int_size_in_bytes (type
);
11995 rsize
= (size
+ 3) / 4;
11998 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11999 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
12000 || (TARGET_DOUBLE_FLOAT
12001 && (TYPE_MODE (type
) == DFmode
12002 || FLOAT128_2REG_P (TYPE_MODE (type
))
12003 || DECIMAL_FLOAT_MODE_P (TYPE_MODE (type
))))))
12005 /* FP args go in FP registers, if present. */
12007 n_reg
= (size
+ 7) / 8;
12008 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
12009 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
12010 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
12015 /* Otherwise into GP registers. */
12024 /* Pull the value out of the saved registers.... */
12027 addr
= create_tmp_var (ptr_type_node
, "addr");
12029 /* AltiVec vectors never go in registers when -mabi=altivec. */
12030 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
12034 lab_false
= create_artificial_label (input_location
);
12035 lab_over
= create_artificial_label (input_location
);
12037 /* Long long and SPE vectors are aligned in the registers.
12038 As are any other 2 gpr item such as complex int due to a
12039 historical mistake. */
12041 if (n_reg
== 2 && reg
== gpr
)
12044 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12045 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
12046 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
12047 unshare_expr (reg
), u
);
12049 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12050 reg number is 0 for f1, so we want to make it odd. */
12051 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
12053 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12054 build_int_cst (TREE_TYPE (reg
), 1));
12055 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
12058 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
12059 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
12060 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
12061 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
12062 gimplify_and_add (t
, pre_p
);
12066 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
12068 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
12069 build_int_cst (TREE_TYPE (reg
), n_reg
));
12070 u
= fold_convert (sizetype
, u
);
12071 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
12072 t
= fold_build_pointer_plus (t
, u
);
12074 /* _Decimal32 varargs are located in the second word of the 64-bit
12075 FP register for 32-bit binaries. */
12077 && TARGET_HARD_FLOAT
&& TARGET_FPRS
12078 && TYPE_MODE (type
) == SDmode
)
12079 t
= fold_build_pointer_plus_hwi (t
, size
);
12081 gimplify_assign (addr
, t
, pre_p
);
12083 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
12085 stmt
= gimple_build_label (lab_false
);
12086 gimple_seq_add_stmt (pre_p
, stmt
);
12088 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
12090 /* Ensure that we don't find any more args in regs.
12091 Alignment has taken care of for special cases. */
12092 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
12096 /* ... otherwise out of the overflow area. */
12098 /* Care for on-stack alignment if needed. */
12102 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
12103 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
12104 build_int_cst (TREE_TYPE (t
), -align
));
12106 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
12108 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
12110 t
= fold_build_pointer_plus_hwi (t
, size
);
12111 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
12115 stmt
= gimple_build_label (lab_over
);
12116 gimple_seq_add_stmt (pre_p
, stmt
);
12119 if (STRICT_ALIGNMENT
12120 && (TYPE_ALIGN (type
)
12121 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
12123 /* The value (of type complex double, for example) may not be
12124 aligned in memory in the saved registers, so copy via a
12125 temporary. (This is the same code as used for SPARC.) */
12126 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
12127 tree dest_addr
= build_fold_addr_expr (tmp
);
12129 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
12130 3, dest_addr
, addr
, size_int (rsize
* 4));
12132 gimplify_and_add (copy
, pre_p
);
12136 addr
= fold_convert (ptrtype
, addr
);
12137 return build_va_arg_indirect_ref (addr
);
12143 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
12146 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
12147 const char *attr_string
= "";
12149 gcc_assert (name
!= NULL
);
12150 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
12152 if (rs6000_builtin_decls
[(int)code
])
12153 fatal_error (input_location
,
12154 "internal error: builtin function %s already processed", name
);
12156 rs6000_builtin_decls
[(int)code
] = t
=
12157 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
12159 /* Set any special attributes. */
12160 if ((classify
& RS6000_BTC_CONST
) != 0)
12162 /* const function, function only depends on the inputs. */
12163 TREE_READONLY (t
) = 1;
12164 TREE_NOTHROW (t
) = 1;
12165 attr_string
= ", pure";
12167 else if ((classify
& RS6000_BTC_PURE
) != 0)
12169 /* pure function, function can read global memory, but does not set any
12171 DECL_PURE_P (t
) = 1;
12172 TREE_NOTHROW (t
) = 1;
12173 attr_string
= ", const";
12175 else if ((classify
& RS6000_BTC_FP
) != 0)
12177 /* Function is a math function. If rounding mode is on, then treat the
12178 function as not reading global memory, but it can have arbitrary side
12179 effects. If it is off, then assume the function is a const function.
12180 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12181 builtin-attribute.def that is used for the math functions. */
12182 TREE_NOTHROW (t
) = 1;
12183 if (flag_rounding_math
)
12185 DECL_PURE_P (t
) = 1;
12186 DECL_IS_NOVOPS (t
) = 1;
12187 attr_string
= ", fp, pure";
12191 TREE_READONLY (t
) = 1;
12192 attr_string
= ", fp, const";
12195 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
12196 gcc_unreachable ();
12198 if (TARGET_DEBUG_BUILTIN
)
12199 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
12200 (int)code
, name
, attr_string
);
12203 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12205 #undef RS6000_BUILTIN_1
12206 #undef RS6000_BUILTIN_2
12207 #undef RS6000_BUILTIN_3
12208 #undef RS6000_BUILTIN_A
12209 #undef RS6000_BUILTIN_D
12210 #undef RS6000_BUILTIN_E
12211 #undef RS6000_BUILTIN_H
12212 #undef RS6000_BUILTIN_P
12213 #undef RS6000_BUILTIN_Q
12214 #undef RS6000_BUILTIN_S
12215 #undef RS6000_BUILTIN_X
12217 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12218 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12219 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
12220 { MASK, ICODE, NAME, ENUM },
12222 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12223 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12224 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12225 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12226 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12227 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12228 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12229 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12231 static const struct builtin_description bdesc_3arg
[] =
12233 #include "rs6000-builtin.def"
12236 /* DST operations: void foo (void *, const int, const char). */
12238 #undef RS6000_BUILTIN_1
12239 #undef RS6000_BUILTIN_2
12240 #undef RS6000_BUILTIN_3
12241 #undef RS6000_BUILTIN_A
12242 #undef RS6000_BUILTIN_D
12243 #undef RS6000_BUILTIN_E
12244 #undef RS6000_BUILTIN_H
12245 #undef RS6000_BUILTIN_P
12246 #undef RS6000_BUILTIN_Q
12247 #undef RS6000_BUILTIN_S
12248 #undef RS6000_BUILTIN_X
12250 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12251 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12252 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12253 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12254 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
12255 { MASK, ICODE, NAME, ENUM },
12257 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12258 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12259 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12260 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12261 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12262 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12264 static const struct builtin_description bdesc_dst
[] =
12266 #include "rs6000-builtin.def"
12269 /* Simple binary operations: VECc = foo (VECa, VECb). */
12271 #undef RS6000_BUILTIN_1
12272 #undef RS6000_BUILTIN_2
12273 #undef RS6000_BUILTIN_3
12274 #undef RS6000_BUILTIN_A
12275 #undef RS6000_BUILTIN_D
12276 #undef RS6000_BUILTIN_E
12277 #undef RS6000_BUILTIN_H
12278 #undef RS6000_BUILTIN_P
12279 #undef RS6000_BUILTIN_Q
12280 #undef RS6000_BUILTIN_S
12281 #undef RS6000_BUILTIN_X
12283 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
12285 { MASK, ICODE, NAME, ENUM },
12287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12288 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12289 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12290 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12291 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12292 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12293 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12294 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12295 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12297 static const struct builtin_description bdesc_2arg
[] =
12299 #include "rs6000-builtin.def"
12302 #undef RS6000_BUILTIN_1
12303 #undef RS6000_BUILTIN_2
12304 #undef RS6000_BUILTIN_3
12305 #undef RS6000_BUILTIN_A
12306 #undef RS6000_BUILTIN_D
12307 #undef RS6000_BUILTIN_E
12308 #undef RS6000_BUILTIN_H
12309 #undef RS6000_BUILTIN_P
12310 #undef RS6000_BUILTIN_Q
12311 #undef RS6000_BUILTIN_S
12312 #undef RS6000_BUILTIN_X
12314 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12315 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12316 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12317 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12318 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12319 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12320 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12321 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
12322 { MASK, ICODE, NAME, ENUM },
12324 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12325 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12326 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12328 /* AltiVec predicates. */
12330 static const struct builtin_description bdesc_altivec_preds
[] =
12332 #include "rs6000-builtin.def"
12335 /* SPE predicates. */
12336 #undef RS6000_BUILTIN_1
12337 #undef RS6000_BUILTIN_2
12338 #undef RS6000_BUILTIN_3
12339 #undef RS6000_BUILTIN_A
12340 #undef RS6000_BUILTIN_D
12341 #undef RS6000_BUILTIN_E
12342 #undef RS6000_BUILTIN_H
12343 #undef RS6000_BUILTIN_P
12344 #undef RS6000_BUILTIN_Q
12345 #undef RS6000_BUILTIN_S
12346 #undef RS6000_BUILTIN_X
12348 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12349 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12350 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12351 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12352 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12353 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12354 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12355 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12356 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12357 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
12358 { MASK, ICODE, NAME, ENUM },
12360 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12362 static const struct builtin_description bdesc_spe_predicates
[] =
12364 #include "rs6000-builtin.def"
12367 /* SPE evsel predicates. */
12368 #undef RS6000_BUILTIN_1
12369 #undef RS6000_BUILTIN_2
12370 #undef RS6000_BUILTIN_3
12371 #undef RS6000_BUILTIN_A
12372 #undef RS6000_BUILTIN_D
12373 #undef RS6000_BUILTIN_E
12374 #undef RS6000_BUILTIN_H
12375 #undef RS6000_BUILTIN_P
12376 #undef RS6000_BUILTIN_Q
12377 #undef RS6000_BUILTIN_S
12378 #undef RS6000_BUILTIN_X
12380 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12381 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12382 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12383 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12384 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12385 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
12386 { MASK, ICODE, NAME, ENUM },
12388 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12389 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12390 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12391 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12392 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12394 static const struct builtin_description bdesc_spe_evsel
[] =
12396 #include "rs6000-builtin.def"
12399 /* PAIRED predicates. */
12400 #undef RS6000_BUILTIN_1
12401 #undef RS6000_BUILTIN_2
12402 #undef RS6000_BUILTIN_3
12403 #undef RS6000_BUILTIN_A
12404 #undef RS6000_BUILTIN_D
12405 #undef RS6000_BUILTIN_E
12406 #undef RS6000_BUILTIN_H
12407 #undef RS6000_BUILTIN_P
12408 #undef RS6000_BUILTIN_Q
12409 #undef RS6000_BUILTIN_S
12410 #undef RS6000_BUILTIN_X
12412 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12413 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12414 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12415 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12416 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12417 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12418 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12419 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12420 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
12421 { MASK, ICODE, NAME, ENUM },
12423 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12424 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12426 static const struct builtin_description bdesc_paired_preds
[] =
12428 #include "rs6000-builtin.def"
12431 /* ABS* operations. */
12433 #undef RS6000_BUILTIN_1
12434 #undef RS6000_BUILTIN_2
12435 #undef RS6000_BUILTIN_3
12436 #undef RS6000_BUILTIN_A
12437 #undef RS6000_BUILTIN_D
12438 #undef RS6000_BUILTIN_E
12439 #undef RS6000_BUILTIN_H
12440 #undef RS6000_BUILTIN_P
12441 #undef RS6000_BUILTIN_Q
12442 #undef RS6000_BUILTIN_S
12443 #undef RS6000_BUILTIN_X
12445 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12446 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12447 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12448 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12449 { MASK, ICODE, NAME, ENUM },
12451 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12452 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12453 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12454 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12455 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12456 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12457 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12459 static const struct builtin_description bdesc_abs
[] =
12461 #include "rs6000-builtin.def"
12464 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12467 #undef RS6000_BUILTIN_1
12468 #undef RS6000_BUILTIN_2
12469 #undef RS6000_BUILTIN_3
12470 #undef RS6000_BUILTIN_A
12471 #undef RS6000_BUILTIN_D
12472 #undef RS6000_BUILTIN_E
12473 #undef RS6000_BUILTIN_H
12474 #undef RS6000_BUILTIN_P
12475 #undef RS6000_BUILTIN_Q
12476 #undef RS6000_BUILTIN_S
12477 #undef RS6000_BUILTIN_X
12479 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12480 { MASK, ICODE, NAME, ENUM },
12482 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12483 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12484 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12485 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12486 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12487 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12488 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12489 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12490 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12491 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12493 static const struct builtin_description bdesc_1arg
[] =
12495 #include "rs6000-builtin.def"
12498 /* HTM builtins. */
12499 #undef RS6000_BUILTIN_1
12500 #undef RS6000_BUILTIN_2
12501 #undef RS6000_BUILTIN_3
12502 #undef RS6000_BUILTIN_A
12503 #undef RS6000_BUILTIN_D
12504 #undef RS6000_BUILTIN_E
12505 #undef RS6000_BUILTIN_H
12506 #undef RS6000_BUILTIN_P
12507 #undef RS6000_BUILTIN_Q
12508 #undef RS6000_BUILTIN_S
12509 #undef RS6000_BUILTIN_X
12511 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12512 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12513 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12514 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12515 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12516 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12517 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12518 { MASK, ICODE, NAME, ENUM },
12520 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12521 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12522 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12523 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12525 static const struct builtin_description bdesc_htm
[] =
12527 #include "rs6000-builtin.def"
12530 #undef RS6000_BUILTIN_1
12531 #undef RS6000_BUILTIN_2
12532 #undef RS6000_BUILTIN_3
12533 #undef RS6000_BUILTIN_A
12534 #undef RS6000_BUILTIN_D
12535 #undef RS6000_BUILTIN_E
12536 #undef RS6000_BUILTIN_H
12537 #undef RS6000_BUILTIN_P
12538 #undef RS6000_BUILTIN_Q
12539 #undef RS6000_BUILTIN_S
12541 /* Return true if a builtin function is overloaded. */
12543 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
12545 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
12548 /* Expand an expression EXP that calls a builtin without arguments. */
12550 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
12553 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12555 if (icode
== CODE_FOR_nothing
)
12556 /* Builtin not supported on this processor. */
12560 || GET_MODE (target
) != tmode
12561 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12562 target
= gen_reg_rtx (tmode
);
12564 pat
= GEN_FCN (icode
) (target
);
12574 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
12577 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12578 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12579 rtx op0
= expand_normal (arg0
);
12580 rtx op1
= expand_normal (arg1
);
12581 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12582 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12584 if (icode
== CODE_FOR_nothing
)
12585 /* Builtin not supported on this processor. */
12588 /* If we got invalid arguments bail out before generating bad rtl. */
12589 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12592 if (GET_CODE (op0
) != CONST_INT
12593 || INTVAL (op0
) > 255
12594 || INTVAL (op0
) < 0)
12596 error ("argument 1 must be an 8-bit field value");
12600 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12601 op0
= copy_to_mode_reg (mode0
, op0
);
12603 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12604 op1
= copy_to_mode_reg (mode1
, op1
);
12606 pat
= GEN_FCN (icode
) (op0
, op1
);
12616 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12619 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12620 rtx op0
= expand_normal (arg0
);
12621 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12622 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12624 if (icode
== CODE_FOR_nothing
)
12625 /* Builtin not supported on this processor. */
12628 /* If we got invalid arguments bail out before generating bad rtl. */
12629 if (arg0
== error_mark_node
)
12632 if (icode
== CODE_FOR_altivec_vspltisb
12633 || icode
== CODE_FOR_altivec_vspltish
12634 || icode
== CODE_FOR_altivec_vspltisw
12635 || icode
== CODE_FOR_spe_evsplatfi
12636 || icode
== CODE_FOR_spe_evsplati
)
12638 /* Only allow 5-bit *signed* literals. */
12639 if (GET_CODE (op0
) != CONST_INT
12640 || INTVAL (op0
) > 15
12641 || INTVAL (op0
) < -16)
12643 error ("argument 1 must be a 5-bit signed literal");
12649 || GET_MODE (target
) != tmode
12650 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12651 target
= gen_reg_rtx (tmode
);
12653 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12654 op0
= copy_to_mode_reg (mode0
, op0
);
12656 pat
= GEN_FCN (icode
) (target
, op0
);
12665 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
12667 rtx pat
, scratch1
, scratch2
;
12668 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12669 rtx op0
= expand_normal (arg0
);
12670 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12671 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12673 /* If we have invalid arguments, bail out before generating bad rtl. */
12674 if (arg0
== error_mark_node
)
12678 || GET_MODE (target
) != tmode
12679 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12680 target
= gen_reg_rtx (tmode
);
12682 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12683 op0
= copy_to_mode_reg (mode0
, op0
);
12685 scratch1
= gen_reg_rtx (mode0
);
12686 scratch2
= gen_reg_rtx (mode0
);
12688 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
12697 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12700 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12701 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12702 rtx op0
= expand_normal (arg0
);
12703 rtx op1
= expand_normal (arg1
);
12704 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12705 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12706 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12708 if (icode
== CODE_FOR_nothing
)
12709 /* Builtin not supported on this processor. */
12712 /* If we got invalid arguments bail out before generating bad rtl. */
12713 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12716 if (icode
== CODE_FOR_altivec_vcfux
12717 || icode
== CODE_FOR_altivec_vcfsx
12718 || icode
== CODE_FOR_altivec_vctsxs
12719 || icode
== CODE_FOR_altivec_vctuxs
12720 || icode
== CODE_FOR_altivec_vspltb
12721 || icode
== CODE_FOR_altivec_vsplth
12722 || icode
== CODE_FOR_altivec_vspltw
12723 || icode
== CODE_FOR_spe_evaddiw
12724 || icode
== CODE_FOR_spe_evldd
12725 || icode
== CODE_FOR_spe_evldh
12726 || icode
== CODE_FOR_spe_evldw
12727 || icode
== CODE_FOR_spe_evlhhesplat
12728 || icode
== CODE_FOR_spe_evlhhossplat
12729 || icode
== CODE_FOR_spe_evlhhousplat
12730 || icode
== CODE_FOR_spe_evlwhe
12731 || icode
== CODE_FOR_spe_evlwhos
12732 || icode
== CODE_FOR_spe_evlwhou
12733 || icode
== CODE_FOR_spe_evlwhsplat
12734 || icode
== CODE_FOR_spe_evlwwsplat
12735 || icode
== CODE_FOR_spe_evrlwi
12736 || icode
== CODE_FOR_spe_evslwi
12737 || icode
== CODE_FOR_spe_evsrwis
12738 || icode
== CODE_FOR_spe_evsubifw
12739 || icode
== CODE_FOR_spe_evsrwiu
)
12741 /* Only allow 5-bit unsigned literals. */
12743 if (TREE_CODE (arg1
) != INTEGER_CST
12744 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
12746 error ("argument 2 must be a 5-bit unsigned literal");
12752 || GET_MODE (target
) != tmode
12753 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12754 target
= gen_reg_rtx (tmode
);
12756 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12757 op0
= copy_to_mode_reg (mode0
, op0
);
12758 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12759 op1
= copy_to_mode_reg (mode1
, op1
);
12761 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12770 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12773 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
12774 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12775 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12776 rtx op0
= expand_normal (arg0
);
12777 rtx op1
= expand_normal (arg1
);
12778 machine_mode tmode
= SImode
;
12779 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12780 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12783 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
12785 error ("argument 1 of __builtin_altivec_predicate must be a constant");
12789 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
12791 gcc_assert (mode0
== mode1
);
12793 /* If we have invalid arguments, bail out before generating bad rtl. */
12794 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12798 || GET_MODE (target
) != tmode
12799 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12800 target
= gen_reg_rtx (tmode
);
12802 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12803 op0
= copy_to_mode_reg (mode0
, op0
);
12804 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12805 op1
= copy_to_mode_reg (mode1
, op1
);
12807 scratch
= gen_reg_rtx (mode0
);
12809 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12814 /* The vec_any* and vec_all* predicates use the same opcodes for two
12815 different operations, but the bits in CR6 will be different
12816 depending on what information we want. So we have to play tricks
12817 with CR6 to get the right bits out.
12819 If you think this is disgusting, look at the specs for the
12820 AltiVec predicates. */
12822 switch (cr6_form_int
)
12825 emit_insn (gen_cr6_test_for_zero (target
));
12828 emit_insn (gen_cr6_test_for_zero_reverse (target
));
12831 emit_insn (gen_cr6_test_for_lt (target
));
12834 emit_insn (gen_cr6_test_for_lt_reverse (target
));
12837 error ("argument 1 of __builtin_altivec_predicate is out of range");
12845 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
12848 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12849 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12850 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12851 machine_mode mode0
= Pmode
;
12852 machine_mode mode1
= Pmode
;
12853 rtx op0
= expand_normal (arg0
);
12854 rtx op1
= expand_normal (arg1
);
12856 if (icode
== CODE_FOR_nothing
)
12857 /* Builtin not supported on this processor. */
12860 /* If we got invalid arguments bail out before generating bad rtl. */
12861 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12865 || GET_MODE (target
) != tmode
12866 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12867 target
= gen_reg_rtx (tmode
);
12869 op1
= copy_to_mode_reg (mode1
, op1
);
12871 if (op0
== const0_rtx
)
12873 addr
= gen_rtx_MEM (tmode
, op1
);
12877 op0
= copy_to_mode_reg (mode0
, op0
);
12878 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12881 pat
= GEN_FCN (icode
) (target
, addr
);
12890 /* Return a constant vector for use as a little-endian permute control vector
12891 to reverse the order of elements of the given vector mode. */
12893 swap_selector_for_mode (machine_mode mode
)
12895 /* These are little endian vectors, so their elements are reversed
12896 from what you would normally expect for a permute control vector. */
12897 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
12898 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
12899 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
12900 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
12901 unsigned int *swaparray
, i
;
12918 swaparray
= swap16
;
12921 gcc_unreachable ();
12924 for (i
= 0; i
< 16; ++i
)
12925 perm
[i
] = GEN_INT (swaparray
[i
]);
12927 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
12930 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
12931 with -maltivec=be specified. Issue the load followed by an element-reversing
12934 altivec_expand_lvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12936 rtx tmp
= gen_reg_rtx (mode
);
12937 rtx load
= gen_rtx_SET (tmp
, op1
);
12938 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12939 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
12940 rtx sel
= swap_selector_for_mode (mode
);
12941 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
12943 gcc_assert (REG_P (op0
));
12945 emit_insn (gen_rtx_SET (op0
, vperm
));
12948 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
12949 with -maltivec=be specified. Issue the store preceded by an element-reversing
12952 altivec_expand_stvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12954 rtx tmp
= gen_reg_rtx (mode
);
12955 rtx store
= gen_rtx_SET (op0
, tmp
);
12956 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12957 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
12958 rtx sel
= swap_selector_for_mode (mode
);
12961 gcc_assert (REG_P (op1
));
12962 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12963 emit_insn (gen_rtx_SET (tmp
, vperm
));
12967 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
12968 specified. Issue the store preceded by an element-reversing permute. */
12970 altivec_expand_stvex_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12972 machine_mode inner_mode
= GET_MODE_INNER (mode
);
12973 rtx tmp
= gen_reg_rtx (mode
);
12974 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
12975 rtx sel
= swap_selector_for_mode (mode
);
12978 gcc_assert (REG_P (op1
));
12979 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12980 emit_insn (gen_rtx_SET (tmp
, vperm
));
12981 emit_insn (gen_rtx_SET (op0
, stvx
));
12985 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
12988 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12989 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12990 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12991 machine_mode mode0
= Pmode
;
12992 machine_mode mode1
= Pmode
;
12993 rtx op0
= expand_normal (arg0
);
12994 rtx op1
= expand_normal (arg1
);
12996 if (icode
== CODE_FOR_nothing
)
12997 /* Builtin not supported on this processor. */
13000 /* If we got invalid arguments bail out before generating bad rtl. */
13001 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13005 || GET_MODE (target
) != tmode
13006 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13007 target
= gen_reg_rtx (tmode
);
13009 op1
= copy_to_mode_reg (mode1
, op1
);
13011 if (op0
== const0_rtx
)
13013 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
13017 op0
= copy_to_mode_reg (mode0
, op0
);
13018 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
13021 pat
= GEN_FCN (icode
) (target
, addr
);
13031 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
13033 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13034 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13035 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13036 rtx op0
= expand_normal (arg0
);
13037 rtx op1
= expand_normal (arg1
);
13038 rtx op2
= expand_normal (arg2
);
13040 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13041 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13042 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
13044 /* Invalid arguments. Bail before doing anything stoopid! */
13045 if (arg0
== error_mark_node
13046 || arg1
== error_mark_node
13047 || arg2
== error_mark_node
)
13050 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
13051 op0
= copy_to_mode_reg (mode2
, op0
);
13052 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
13053 op1
= copy_to_mode_reg (mode0
, op1
);
13054 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13055 op2
= copy_to_mode_reg (mode1
, op2
);
13057 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
13064 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
13066 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13067 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13068 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13069 rtx op0
= expand_normal (arg0
);
13070 rtx op1
= expand_normal (arg1
);
13071 rtx op2
= expand_normal (arg2
);
13073 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13074 machine_mode mode1
= Pmode
;
13075 machine_mode mode2
= Pmode
;
13077 /* Invalid arguments. Bail before doing anything stoopid! */
13078 if (arg0
== error_mark_node
13079 || arg1
== error_mark_node
13080 || arg2
== error_mark_node
)
13083 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
13084 op0
= copy_to_mode_reg (tmode
, op0
);
13086 op2
= copy_to_mode_reg (mode2
, op2
);
13088 if (op1
== const0_rtx
)
13090 addr
= gen_rtx_MEM (tmode
, op2
);
13094 op1
= copy_to_mode_reg (mode1
, op1
);
13095 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
13098 pat
= GEN_FCN (icode
) (addr
, op0
);
13105 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
13107 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13108 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13109 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13110 rtx op0
= expand_normal (arg0
);
13111 rtx op1
= expand_normal (arg1
);
13112 rtx op2
= expand_normal (arg2
);
13114 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13115 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
13116 machine_mode mode1
= Pmode
;
13117 machine_mode mode2
= Pmode
;
13119 /* Invalid arguments. Bail before doing anything stoopid! */
13120 if (arg0
== error_mark_node
13121 || arg1
== error_mark_node
13122 || arg2
== error_mark_node
)
13125 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
13126 op0
= copy_to_mode_reg (smode
, op0
);
13128 op2
= copy_to_mode_reg (mode2
, op2
);
13130 if (op1
== const0_rtx
)
13132 addr
= gen_rtx_MEM (tmode
, op2
);
13136 op1
= copy_to_mode_reg (mode1
, op1
);
13137 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
13140 pat
= GEN_FCN (icode
) (addr
, op0
);
13146 /* Return the appropriate SPR number associated with the given builtin. */
13147 static inline HOST_WIDE_INT
13148 htm_spr_num (enum rs6000_builtins code
)
13150 if (code
== HTM_BUILTIN_GET_TFHAR
13151 || code
== HTM_BUILTIN_SET_TFHAR
)
13153 else if (code
== HTM_BUILTIN_GET_TFIAR
13154 || code
== HTM_BUILTIN_SET_TFIAR
)
13156 else if (code
== HTM_BUILTIN_GET_TEXASR
13157 || code
== HTM_BUILTIN_SET_TEXASR
)
13159 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
13160 || code
== HTM_BUILTIN_SET_TEXASRU
);
13161 return TEXASRU_SPR
;
13164 /* Return the appropriate SPR regno associated with the given builtin. */
13165 static inline HOST_WIDE_INT
13166 htm_spr_regno (enum rs6000_builtins code
)
13168 if (code
== HTM_BUILTIN_GET_TFHAR
13169 || code
== HTM_BUILTIN_SET_TFHAR
)
13170 return TFHAR_REGNO
;
13171 else if (code
== HTM_BUILTIN_GET_TFIAR
13172 || code
== HTM_BUILTIN_SET_TFIAR
)
13173 return TFIAR_REGNO
;
13174 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
13175 || code
== HTM_BUILTIN_SET_TEXASR
13176 || code
== HTM_BUILTIN_GET_TEXASRU
13177 || code
== HTM_BUILTIN_SET_TEXASRU
);
13178 return TEXASR_REGNO
;
13181 /* Return the correct ICODE value depending on whether we are
13182 setting or reading the HTM SPRs. */
13183 static inline enum insn_code
13184 rs6000_htm_spr_icode (bool nonvoid
)
13187 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
13189 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
13192 /* Expand the HTM builtin in EXP and store the result in TARGET.
13193 Store true in *EXPANDEDP if we found a builtin to expand. */
13195 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13197 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13198 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
13199 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13200 const struct builtin_description
*d
;
13205 if (!TARGET_POWERPC64
13206 && (fcode
== HTM_BUILTIN_TABORTDC
13207 || fcode
== HTM_BUILTIN_TABORTDCI
))
13209 size_t uns_fcode
= (size_t)fcode
;
13210 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
13211 error ("builtin %s is only valid in 64-bit mode", name
);
13215 /* Expand the HTM builtins. */
13217 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
13218 if (d
->code
== fcode
)
13220 rtx op
[MAX_HTM_OPERANDS
], pat
;
13223 call_expr_arg_iterator iter
;
13224 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
13225 enum insn_code icode
= d
->icode
;
13226 const struct insn_operand_data
*insn_op
;
13227 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
13231 icode
= rs6000_htm_spr_icode (nonvoid
);
13232 insn_op
= &insn_data
[icode
].operand
[0];
13236 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: SImode
;
13238 || GET_MODE (target
) != tmode
13239 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
13240 target
= gen_reg_rtx (tmode
);
13242 op
[nopnds
++] = target
;
13245 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
13247 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
13250 insn_op
= &insn_data
[icode
].operand
[nopnds
];
13252 op
[nopnds
] = expand_normal (arg
);
13254 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
13256 if (!strcmp (insn_op
->constraint
, "n"))
13258 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
13259 if (!CONST_INT_P (op
[nopnds
]))
13260 error ("argument %d must be an unsigned literal", arg_num
);
13262 error ("argument %d is an unsigned literal that is "
13263 "out of range", arg_num
);
13266 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
13272 /* Handle the builtins for extended mnemonics. These accept
13273 no arguments, but map to builtins that take arguments. */
13276 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
13277 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
13278 op
[nopnds
++] = GEN_INT (1);
13280 attr
|= RS6000_BTC_UNARY
;
13282 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
13283 op
[nopnds
++] = GEN_INT (0);
13285 attr
|= RS6000_BTC_UNARY
;
13291 /* If this builtin accesses SPRs, then pass in the appropriate
13292 SPR number and SPR regno as the last two operands. */
13295 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
13296 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
13297 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
13299 /* If this builtin accesses a CR, then pass in a scratch
13300 CR as the last operand. */
13301 else if (attr
& RS6000_BTC_CR
)
13302 { cr
= gen_reg_rtx (CCmode
);
13308 int expected_nopnds
= 0;
13309 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
13310 expected_nopnds
= 1;
13311 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
13312 expected_nopnds
= 2;
13313 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
13314 expected_nopnds
= 3;
13315 if (!(attr
& RS6000_BTC_VOID
))
13316 expected_nopnds
+= 1;
13318 expected_nopnds
+= 2;
13320 gcc_assert (nopnds
== expected_nopnds
13321 && nopnds
<= MAX_HTM_OPERANDS
);
13327 pat
= GEN_FCN (icode
) (op
[0]);
13330 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
13333 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
13336 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
13339 gcc_unreachable ();
13345 if (attr
& RS6000_BTC_CR
)
13347 if (fcode
== HTM_BUILTIN_TBEGIN
)
13349 /* Emit code to set TARGET to true or false depending on
13350 whether the tbegin. instruction successfully or failed
13351 to start a transaction. We do this by placing the 1's
13352 complement of CR's EQ bit into TARGET. */
13353 rtx scratch
= gen_reg_rtx (SImode
);
13354 emit_insn (gen_rtx_SET (scratch
,
13355 gen_rtx_EQ (SImode
, cr
,
13357 emit_insn (gen_rtx_SET (target
,
13358 gen_rtx_XOR (SImode
, scratch
,
13363 /* Emit code to copy the 4-bit condition register field
13364 CR into the least significant end of register TARGET. */
13365 rtx scratch1
= gen_reg_rtx (SImode
);
13366 rtx scratch2
= gen_reg_rtx (SImode
);
13367 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
13368 emit_insn (gen_movcc (subreg
, cr
));
13369 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
13370 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
13379 *expandedp
= false;
13384 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
13387 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13388 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13389 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13390 rtx op0
= expand_normal (arg0
);
13391 rtx op1
= expand_normal (arg1
);
13392 rtx op2
= expand_normal (arg2
);
13393 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13394 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13395 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13396 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
13398 if (icode
== CODE_FOR_nothing
)
13399 /* Builtin not supported on this processor. */
13402 /* If we got invalid arguments bail out before generating bad rtl. */
13403 if (arg0
== error_mark_node
13404 || arg1
== error_mark_node
13405 || arg2
== error_mark_node
)
13408 /* Check and prepare argument depending on the instruction code.
13410 Note that a switch statement instead of the sequence of tests
13411 would be incorrect as many of the CODE_FOR values could be
13412 CODE_FOR_nothing and that would yield multiple alternatives
13413 with identical values. We'd never reach here at runtime in
13415 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
13416 || icode
== CODE_FOR_altivec_vsldoi_v4si
13417 || icode
== CODE_FOR_altivec_vsldoi_v8hi
13418 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
13420 /* Only allow 4-bit unsigned literals. */
13422 if (TREE_CODE (arg2
) != INTEGER_CST
13423 || TREE_INT_CST_LOW (arg2
) & ~0xf)
13425 error ("argument 3 must be a 4-bit unsigned literal");
13429 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
13430 || icode
== CODE_FOR_vsx_xxpermdi_v2di
13431 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
13432 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
13433 || icode
== CODE_FOR_vsx_xxsldwi_v4si
13434 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
13435 || icode
== CODE_FOR_vsx_xxsldwi_v2di
13436 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
13438 /* Only allow 2-bit unsigned literals. */
13440 if (TREE_CODE (arg2
) != INTEGER_CST
13441 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13443 error ("argument 3 must be a 2-bit unsigned literal");
13447 else if (icode
== CODE_FOR_vsx_set_v2df
13448 || icode
== CODE_FOR_vsx_set_v2di
13449 || icode
== CODE_FOR_bcdadd
13450 || icode
== CODE_FOR_bcdadd_lt
13451 || icode
== CODE_FOR_bcdadd_eq
13452 || icode
== CODE_FOR_bcdadd_gt
13453 || icode
== CODE_FOR_bcdsub
13454 || icode
== CODE_FOR_bcdsub_lt
13455 || icode
== CODE_FOR_bcdsub_eq
13456 || icode
== CODE_FOR_bcdsub_gt
)
13458 /* Only allow 1-bit unsigned literals. */
13460 if (TREE_CODE (arg2
) != INTEGER_CST
13461 || TREE_INT_CST_LOW (arg2
) & ~0x1)
13463 error ("argument 3 must be a 1-bit unsigned literal");
13467 else if (icode
== CODE_FOR_dfp_ddedpd_dd
13468 || icode
== CODE_FOR_dfp_ddedpd_td
)
13470 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
13472 if (TREE_CODE (arg0
) != INTEGER_CST
13473 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13475 error ("argument 1 must be 0 or 2");
13479 else if (icode
== CODE_FOR_dfp_denbcd_dd
13480 || icode
== CODE_FOR_dfp_denbcd_td
)
13482 /* Only allow 1-bit unsigned literals. */
13484 if (TREE_CODE (arg0
) != INTEGER_CST
13485 || TREE_INT_CST_LOW (arg0
) & ~0x1)
13487 error ("argument 1 must be a 1-bit unsigned literal");
13491 else if (icode
== CODE_FOR_dfp_dscli_dd
13492 || icode
== CODE_FOR_dfp_dscli_td
13493 || icode
== CODE_FOR_dfp_dscri_dd
13494 || icode
== CODE_FOR_dfp_dscri_td
)
13496 /* Only allow 6-bit unsigned literals. */
13498 if (TREE_CODE (arg1
) != INTEGER_CST
13499 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
13501 error ("argument 2 must be a 6-bit unsigned literal");
13505 else if (icode
== CODE_FOR_crypto_vshasigmaw
13506 || icode
== CODE_FOR_crypto_vshasigmad
)
13508 /* Check whether the 2nd and 3rd arguments are integer constants and in
13509 range and prepare arguments. */
13511 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
13513 error ("argument 2 must be 0 or 1");
13518 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
13520 error ("argument 3 must be in the range 0..15");
13526 || GET_MODE (target
) != tmode
13527 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13528 target
= gen_reg_rtx (tmode
);
13530 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13531 op0
= copy_to_mode_reg (mode0
, op0
);
13532 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13533 op1
= copy_to_mode_reg (mode1
, op1
);
13534 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13535 op2
= copy_to_mode_reg (mode2
, op2
);
13537 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
13538 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
13540 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13548 /* Expand the lvx builtins. */
13550 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
13552 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13553 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13555 machine_mode tmode
, mode0
;
13557 enum insn_code icode
;
13561 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
13562 icode
= CODE_FOR_vector_altivec_load_v16qi
;
13564 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
13565 icode
= CODE_FOR_vector_altivec_load_v8hi
;
13567 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
13568 icode
= CODE_FOR_vector_altivec_load_v4si
;
13570 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
13571 icode
= CODE_FOR_vector_altivec_load_v4sf
;
13573 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
13574 icode
= CODE_FOR_vector_altivec_load_v2df
;
13576 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
13577 icode
= CODE_FOR_vector_altivec_load_v2di
;
13578 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
13579 icode
= CODE_FOR_vector_altivec_load_v1ti
;
13582 *expandedp
= false;
13588 arg0
= CALL_EXPR_ARG (exp
, 0);
13589 op0
= expand_normal (arg0
);
13590 tmode
= insn_data
[icode
].operand
[0].mode
;
13591 mode0
= insn_data
[icode
].operand
[1].mode
;
13594 || GET_MODE (target
) != tmode
13595 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13596 target
= gen_reg_rtx (tmode
);
13598 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13599 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13601 pat
= GEN_FCN (icode
) (target
, op0
);
13608 /* Expand the stvx builtins. */
13610 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
13613 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13614 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13616 machine_mode mode0
, mode1
;
13618 enum insn_code icode
;
13622 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
13623 icode
= CODE_FOR_vector_altivec_store_v16qi
;
13625 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
13626 icode
= CODE_FOR_vector_altivec_store_v8hi
;
13628 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
13629 icode
= CODE_FOR_vector_altivec_store_v4si
;
13631 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
13632 icode
= CODE_FOR_vector_altivec_store_v4sf
;
13634 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
13635 icode
= CODE_FOR_vector_altivec_store_v2df
;
13637 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
13638 icode
= CODE_FOR_vector_altivec_store_v2di
;
13639 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
13640 icode
= CODE_FOR_vector_altivec_store_v1ti
;
13643 *expandedp
= false;
13647 arg0
= CALL_EXPR_ARG (exp
, 0);
13648 arg1
= CALL_EXPR_ARG (exp
, 1);
13649 op0
= expand_normal (arg0
);
13650 op1
= expand_normal (arg1
);
13651 mode0
= insn_data
[icode
].operand
[0].mode
;
13652 mode1
= insn_data
[icode
].operand
[1].mode
;
13654 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13655 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13656 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13657 op1
= copy_to_mode_reg (mode1
, op1
);
13659 pat
= GEN_FCN (icode
) (op0
, op1
);
13667 /* Expand the dst builtins. */
13669 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
13672 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13673 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13674 tree arg0
, arg1
, arg2
;
13675 machine_mode mode0
, mode1
;
13676 rtx pat
, op0
, op1
, op2
;
13677 const struct builtin_description
*d
;
13680 *expandedp
= false;
13682 /* Handle DST variants. */
13684 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
13685 if (d
->code
== fcode
)
13687 arg0
= CALL_EXPR_ARG (exp
, 0);
13688 arg1
= CALL_EXPR_ARG (exp
, 1);
13689 arg2
= CALL_EXPR_ARG (exp
, 2);
13690 op0
= expand_normal (arg0
);
13691 op1
= expand_normal (arg1
);
13692 op2
= expand_normal (arg2
);
13693 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13694 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13696 /* Invalid arguments, bail out before generating bad rtl. */
13697 if (arg0
== error_mark_node
13698 || arg1
== error_mark_node
13699 || arg2
== error_mark_node
)
13704 if (TREE_CODE (arg2
) != INTEGER_CST
13705 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13707 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
13711 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
13712 op0
= copy_to_mode_reg (Pmode
, op0
);
13713 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
13714 op1
= copy_to_mode_reg (mode1
, op1
);
13716 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
13726 /* Expand vec_init builtin. */
13728 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
13730 machine_mode tmode
= TYPE_MODE (type
);
13731 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
13732 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
13734 gcc_assert (VECTOR_MODE_P (tmode
));
13735 gcc_assert (n_elt
== call_expr_nargs (exp
));
13737 if (!target
|| !register_operand (target
, tmode
))
13738 target
= gen_reg_rtx (tmode
);
13740 /* If we have a vector compromised of a single element, such as V1TImode, do
13741 the initialization directly. */
13742 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
13744 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
13745 emit_move_insn (target
, gen_lowpart (tmode
, x
));
13749 rtvec v
= rtvec_alloc (n_elt
);
13751 for (i
= 0; i
< n_elt
; ++i
)
13753 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
13754 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
13757 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
13763 /* Return the integer constant in ARG. Constrain it to be in the range
13764 of the subparts of VEC_TYPE; issue an error if not. */
13767 get_element_number (tree vec_type
, tree arg
)
13769 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
13771 if (!tree_fits_uhwi_p (arg
)
13772 || (elt
= tree_to_uhwi (arg
), elt
> max
))
13774 error ("selector must be an integer constant in the range 0..%wi", max
);
13781 /* Expand vec_set builtin. */
13783 altivec_expand_vec_set_builtin (tree exp
)
13785 machine_mode tmode
, mode1
;
13786 tree arg0
, arg1
, arg2
;
13790 arg0
= CALL_EXPR_ARG (exp
, 0);
13791 arg1
= CALL_EXPR_ARG (exp
, 1);
13792 arg2
= CALL_EXPR_ARG (exp
, 2);
13794 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
13795 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13796 gcc_assert (VECTOR_MODE_P (tmode
));
13798 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
13799 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
13800 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
13802 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
13803 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
13805 op0
= force_reg (tmode
, op0
);
13806 op1
= force_reg (mode1
, op1
);
13808 rs6000_expand_vector_set (op0
, op1
, elt
);
13813 /* Expand vec_ext builtin. */
13815 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
13817 machine_mode tmode
, mode0
;
13822 arg0
= CALL_EXPR_ARG (exp
, 0);
13823 arg1
= CALL_EXPR_ARG (exp
, 1);
13825 op0
= expand_normal (arg0
);
13826 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
13828 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13829 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
13830 gcc_assert (VECTOR_MODE_P (mode0
));
13832 op0
= force_reg (mode0
, op0
);
13834 if (optimize
|| !target
|| !register_operand (target
, tmode
))
13835 target
= gen_reg_rtx (tmode
);
13837 rs6000_expand_vector_extract (target
, op0
, elt
);
13842 /* Expand the builtin in EXP and store the result in TARGET. Store
13843 true in *EXPANDEDP if we found a builtin to expand. */
13845 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13847 const struct builtin_description
*d
;
13849 enum insn_code icode
;
13850 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13853 machine_mode tmode
, mode0
;
13854 enum rs6000_builtins fcode
13855 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13857 if (rs6000_overloaded_builtin_p (fcode
))
13860 error ("unresolved overload for Altivec builtin %qF", fndecl
);
13862 /* Given it is invalid, just generate a normal call. */
13863 return expand_call (exp
, target
, false);
13866 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
13870 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
13874 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
13882 case ALTIVEC_BUILTIN_STVX_V2DF
:
13883 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
13884 case ALTIVEC_BUILTIN_STVX_V2DI
:
13885 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
13886 case ALTIVEC_BUILTIN_STVX_V4SF
:
13887 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
13888 case ALTIVEC_BUILTIN_STVX
:
13889 case ALTIVEC_BUILTIN_STVX_V4SI
:
13890 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
13891 case ALTIVEC_BUILTIN_STVX_V8HI
:
13892 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
13893 case ALTIVEC_BUILTIN_STVX_V16QI
:
13894 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
13895 case ALTIVEC_BUILTIN_STVEBX
:
13896 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
13897 case ALTIVEC_BUILTIN_STVEHX
:
13898 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
13899 case ALTIVEC_BUILTIN_STVEWX
:
13900 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
13901 case ALTIVEC_BUILTIN_STVXL_V2DF
:
13902 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
13903 case ALTIVEC_BUILTIN_STVXL_V2DI
:
13904 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
13905 case ALTIVEC_BUILTIN_STVXL_V4SF
:
13906 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
13907 case ALTIVEC_BUILTIN_STVXL
:
13908 case ALTIVEC_BUILTIN_STVXL_V4SI
:
13909 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
13910 case ALTIVEC_BUILTIN_STVXL_V8HI
:
13911 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
13912 case ALTIVEC_BUILTIN_STVXL_V16QI
:
13913 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
13915 case ALTIVEC_BUILTIN_STVLX
:
13916 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
13917 case ALTIVEC_BUILTIN_STVLXL
:
13918 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
13919 case ALTIVEC_BUILTIN_STVRX
:
13920 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
13921 case ALTIVEC_BUILTIN_STVRXL
:
13922 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
13924 case VSX_BUILTIN_STXVD2X_V1TI
:
13925 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
13926 case VSX_BUILTIN_STXVD2X_V2DF
:
13927 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
13928 case VSX_BUILTIN_STXVD2X_V2DI
:
13929 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
13930 case VSX_BUILTIN_STXVW4X_V4SF
:
13931 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
13932 case VSX_BUILTIN_STXVW4X_V4SI
:
13933 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
13934 case VSX_BUILTIN_STXVW4X_V8HI
:
13935 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
13936 case VSX_BUILTIN_STXVW4X_V16QI
:
13937 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
13939 case ALTIVEC_BUILTIN_MFVSCR
:
13940 icode
= CODE_FOR_altivec_mfvscr
;
13941 tmode
= insn_data
[icode
].operand
[0].mode
;
13944 || GET_MODE (target
) != tmode
13945 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13946 target
= gen_reg_rtx (tmode
);
13948 pat
= GEN_FCN (icode
) (target
);
13954 case ALTIVEC_BUILTIN_MTVSCR
:
13955 icode
= CODE_FOR_altivec_mtvscr
;
13956 arg0
= CALL_EXPR_ARG (exp
, 0);
13957 op0
= expand_normal (arg0
);
13958 mode0
= insn_data
[icode
].operand
[0].mode
;
13960 /* If we got invalid arguments bail out before generating bad rtl. */
13961 if (arg0
== error_mark_node
)
13964 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13965 op0
= copy_to_mode_reg (mode0
, op0
);
13967 pat
= GEN_FCN (icode
) (op0
);
13972 case ALTIVEC_BUILTIN_DSSALL
:
13973 emit_insn (gen_altivec_dssall ());
13976 case ALTIVEC_BUILTIN_DSS
:
13977 icode
= CODE_FOR_altivec_dss
;
13978 arg0
= CALL_EXPR_ARG (exp
, 0);
13980 op0
= expand_normal (arg0
);
13981 mode0
= insn_data
[icode
].operand
[0].mode
;
13983 /* If we got invalid arguments bail out before generating bad rtl. */
13984 if (arg0
== error_mark_node
)
13987 if (TREE_CODE (arg0
) != INTEGER_CST
13988 || TREE_INT_CST_LOW (arg0
) & ~0x3)
13990 error ("argument to dss must be a 2-bit unsigned literal");
13994 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13995 op0
= copy_to_mode_reg (mode0
, op0
);
13997 emit_insn (gen_altivec_dss (op0
));
14000 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
14001 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
14002 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
14003 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
14004 case VSX_BUILTIN_VEC_INIT_V2DF
:
14005 case VSX_BUILTIN_VEC_INIT_V2DI
:
14006 case VSX_BUILTIN_VEC_INIT_V1TI
:
14007 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
14009 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
14010 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
14011 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
14012 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
14013 case VSX_BUILTIN_VEC_SET_V2DF
:
14014 case VSX_BUILTIN_VEC_SET_V2DI
:
14015 case VSX_BUILTIN_VEC_SET_V1TI
:
14016 return altivec_expand_vec_set_builtin (exp
);
14018 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
14019 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
14020 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
14021 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
14022 case VSX_BUILTIN_VEC_EXT_V2DF
:
14023 case VSX_BUILTIN_VEC_EXT_V2DI
:
14024 case VSX_BUILTIN_VEC_EXT_V1TI
:
14025 return altivec_expand_vec_ext_builtin (exp
, target
);
14029 /* Fall through. */
14032 /* Expand abs* operations. */
14034 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14035 if (d
->code
== fcode
)
14036 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
14038 /* Expand the AltiVec predicates. */
14039 d
= bdesc_altivec_preds
;
14040 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14041 if (d
->code
== fcode
)
14042 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
14044 /* LV* are funky. We initialized them differently. */
14047 case ALTIVEC_BUILTIN_LVSL
:
14048 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
14049 exp
, target
, false);
14050 case ALTIVEC_BUILTIN_LVSR
:
14051 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
14052 exp
, target
, false);
14053 case ALTIVEC_BUILTIN_LVEBX
:
14054 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
14055 exp
, target
, false);
14056 case ALTIVEC_BUILTIN_LVEHX
:
14057 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
14058 exp
, target
, false);
14059 case ALTIVEC_BUILTIN_LVEWX
:
14060 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
14061 exp
, target
, false);
14062 case ALTIVEC_BUILTIN_LVXL_V2DF
:
14063 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
14064 exp
, target
, false);
14065 case ALTIVEC_BUILTIN_LVXL_V2DI
:
14066 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
14067 exp
, target
, false);
14068 case ALTIVEC_BUILTIN_LVXL_V4SF
:
14069 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
14070 exp
, target
, false);
14071 case ALTIVEC_BUILTIN_LVXL
:
14072 case ALTIVEC_BUILTIN_LVXL_V4SI
:
14073 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
14074 exp
, target
, false);
14075 case ALTIVEC_BUILTIN_LVXL_V8HI
:
14076 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
14077 exp
, target
, false);
14078 case ALTIVEC_BUILTIN_LVXL_V16QI
:
14079 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
14080 exp
, target
, false);
14081 case ALTIVEC_BUILTIN_LVX_V2DF
:
14082 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
14083 exp
, target
, false);
14084 case ALTIVEC_BUILTIN_LVX_V2DI
:
14085 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
14086 exp
, target
, false);
14087 case ALTIVEC_BUILTIN_LVX_V4SF
:
14088 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
14089 exp
, target
, false);
14090 case ALTIVEC_BUILTIN_LVX
:
14091 case ALTIVEC_BUILTIN_LVX_V4SI
:
14092 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
14093 exp
, target
, false);
14094 case ALTIVEC_BUILTIN_LVX_V8HI
:
14095 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
14096 exp
, target
, false);
14097 case ALTIVEC_BUILTIN_LVX_V16QI
:
14098 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
14099 exp
, target
, false);
14100 case ALTIVEC_BUILTIN_LVLX
:
14101 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
14102 exp
, target
, true);
14103 case ALTIVEC_BUILTIN_LVLXL
:
14104 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
14105 exp
, target
, true);
14106 case ALTIVEC_BUILTIN_LVRX
:
14107 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
14108 exp
, target
, true);
14109 case ALTIVEC_BUILTIN_LVRXL
:
14110 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
14111 exp
, target
, true);
14112 case VSX_BUILTIN_LXVD2X_V1TI
:
14113 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
14114 exp
, target
, false);
14115 case VSX_BUILTIN_LXVD2X_V2DF
:
14116 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
14117 exp
, target
, false);
14118 case VSX_BUILTIN_LXVD2X_V2DI
:
14119 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
14120 exp
, target
, false);
14121 case VSX_BUILTIN_LXVW4X_V4SF
:
14122 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
14123 exp
, target
, false);
14124 case VSX_BUILTIN_LXVW4X_V4SI
:
14125 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
14126 exp
, target
, false);
14127 case VSX_BUILTIN_LXVW4X_V8HI
:
14128 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
14129 exp
, target
, false);
14130 case VSX_BUILTIN_LXVW4X_V16QI
:
14131 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
14132 exp
, target
, false);
14136 /* Fall through. */
14139 *expandedp
= false;
14143 /* Expand the builtin in EXP and store the result in TARGET. Store
14144 true in *EXPANDEDP if we found a builtin to expand. */
14146 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
14148 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14149 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14150 const struct builtin_description
*d
;
14157 case PAIRED_BUILTIN_STX
:
14158 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
14159 case PAIRED_BUILTIN_LX
:
14160 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
14163 /* Fall through. */
14166 /* Expand the paired predicates. */
14167 d
= bdesc_paired_preds
;
14168 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
14169 if (d
->code
== fcode
)
14170 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
14172 *expandedp
= false;
14176 /* Binops that need to be initialized manually, but can be expanded
14177 automagically by rs6000_expand_binop_builtin. */
14178 static const struct builtin_description bdesc_2arg_spe
[] =
14180 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
14181 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
14182 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
14183 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
14184 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
14185 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
14186 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
14187 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
14188 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
14189 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
14190 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
14191 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
14192 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
14193 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
14194 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
14195 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
14196 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
14197 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
14198 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
14199 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
14200 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
14201 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
14204 /* Expand the builtin in EXP and store the result in TARGET. Store
14205 true in *EXPANDEDP if we found a builtin to expand.
14207 This expands the SPE builtins that are not simple unary and binary
14210 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
14212 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14214 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14215 enum insn_code icode
;
14216 machine_mode tmode
, mode0
;
14218 const struct builtin_description
*d
;
14223 /* Syntax check for a 5-bit unsigned immediate. */
14226 case SPE_BUILTIN_EVSTDD
:
14227 case SPE_BUILTIN_EVSTDH
:
14228 case SPE_BUILTIN_EVSTDW
:
14229 case SPE_BUILTIN_EVSTWHE
:
14230 case SPE_BUILTIN_EVSTWHO
:
14231 case SPE_BUILTIN_EVSTWWE
:
14232 case SPE_BUILTIN_EVSTWWO
:
14233 arg1
= CALL_EXPR_ARG (exp
, 2);
14234 if (TREE_CODE (arg1
) != INTEGER_CST
14235 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
14237 error ("argument 2 must be a 5-bit unsigned literal");
14245 /* The evsplat*i instructions are not quite generic. */
14248 case SPE_BUILTIN_EVSPLATFI
:
14249 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
14251 case SPE_BUILTIN_EVSPLATI
:
14252 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
14258 d
= bdesc_2arg_spe
;
14259 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
14260 if (d
->code
== fcode
)
14261 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
14263 d
= bdesc_spe_predicates
;
14264 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
14265 if (d
->code
== fcode
)
14266 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
14268 d
= bdesc_spe_evsel
;
14269 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
14270 if (d
->code
== fcode
)
14271 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
14275 case SPE_BUILTIN_EVSTDDX
:
14276 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
14277 case SPE_BUILTIN_EVSTDHX
:
14278 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
14279 case SPE_BUILTIN_EVSTDWX
:
14280 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
14281 case SPE_BUILTIN_EVSTWHEX
:
14282 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
14283 case SPE_BUILTIN_EVSTWHOX
:
14284 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
14285 case SPE_BUILTIN_EVSTWWEX
:
14286 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
14287 case SPE_BUILTIN_EVSTWWOX
:
14288 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
14289 case SPE_BUILTIN_EVSTDD
:
14290 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
14291 case SPE_BUILTIN_EVSTDH
:
14292 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
14293 case SPE_BUILTIN_EVSTDW
:
14294 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
14295 case SPE_BUILTIN_EVSTWHE
:
14296 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
14297 case SPE_BUILTIN_EVSTWHO
:
14298 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
14299 case SPE_BUILTIN_EVSTWWE
:
14300 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
14301 case SPE_BUILTIN_EVSTWWO
:
14302 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
14303 case SPE_BUILTIN_MFSPEFSCR
:
14304 icode
= CODE_FOR_spe_mfspefscr
;
14305 tmode
= insn_data
[icode
].operand
[0].mode
;
14308 || GET_MODE (target
) != tmode
14309 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14310 target
= gen_reg_rtx (tmode
);
14312 pat
= GEN_FCN (icode
) (target
);
14317 case SPE_BUILTIN_MTSPEFSCR
:
14318 icode
= CODE_FOR_spe_mtspefscr
;
14319 arg0
= CALL_EXPR_ARG (exp
, 0);
14320 op0
= expand_normal (arg0
);
14321 mode0
= insn_data
[icode
].operand
[0].mode
;
14323 if (arg0
== error_mark_node
)
14326 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
14327 op0
= copy_to_mode_reg (mode0
, op0
);
14329 pat
= GEN_FCN (icode
) (op0
);
14337 *expandedp
= false;
14342 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
14344 rtx pat
, scratch
, tmp
;
14345 tree form
= CALL_EXPR_ARG (exp
, 0);
14346 tree arg0
= CALL_EXPR_ARG (exp
, 1);
14347 tree arg1
= CALL_EXPR_ARG (exp
, 2);
14348 rtx op0
= expand_normal (arg0
);
14349 rtx op1
= expand_normal (arg1
);
14350 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14351 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14353 enum rtx_code code
;
14355 if (TREE_CODE (form
) != INTEGER_CST
)
14357 error ("argument 1 of __builtin_paired_predicate must be a constant");
14361 form_int
= TREE_INT_CST_LOW (form
);
14363 gcc_assert (mode0
== mode1
);
14365 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14369 || GET_MODE (target
) != SImode
14370 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
14371 target
= gen_reg_rtx (SImode
);
14372 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14373 op0
= copy_to_mode_reg (mode0
, op0
);
14374 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14375 op1
= copy_to_mode_reg (mode1
, op1
);
14377 scratch
= gen_reg_rtx (CCFPmode
);
14379 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14401 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
14404 error ("argument 1 of __builtin_paired_predicate is out of range");
14408 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
14409 emit_move_insn (target
, tmp
);
14414 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
14416 rtx pat
, scratch
, tmp
;
14417 tree form
= CALL_EXPR_ARG (exp
, 0);
14418 tree arg0
= CALL_EXPR_ARG (exp
, 1);
14419 tree arg1
= CALL_EXPR_ARG (exp
, 2);
14420 rtx op0
= expand_normal (arg0
);
14421 rtx op1
= expand_normal (arg1
);
14422 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14423 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14425 enum rtx_code code
;
14427 if (TREE_CODE (form
) != INTEGER_CST
)
14429 error ("argument 1 of __builtin_spe_predicate must be a constant");
14433 form_int
= TREE_INT_CST_LOW (form
);
14435 gcc_assert (mode0
== mode1
);
14437 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14441 || GET_MODE (target
) != SImode
14442 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
14443 target
= gen_reg_rtx (SImode
);
14445 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14446 op0
= copy_to_mode_reg (mode0
, op0
);
14447 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14448 op1
= copy_to_mode_reg (mode1
, op1
);
14450 scratch
= gen_reg_rtx (CCmode
);
14452 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14457 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
14458 _lower_. We use one compare, but look in different bits of the
14459 CR for each variant.
14461 There are 2 elements in each SPE simd type (upper/lower). The CR
14462 bits are set as follows:
14464 BIT0 | BIT 1 | BIT 2 | BIT 3
14465 U | L | (U | L) | (U & L)
14467 So, for an "all" relationship, BIT 3 would be set.
14468 For an "any" relationship, BIT 2 would be set. Etc.
14470 Following traditional nomenclature, these bits map to:
14472 BIT0 | BIT 1 | BIT 2 | BIT 3
14475 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
14480 /* All variant. OV bit. */
14482 /* We need to get to the OV bit, which is the ORDERED bit. We
14483 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
14484 that's ugly and will make validate_condition_mode die.
14485 So let's just use another pattern. */
14486 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
14488 /* Any variant. EQ bit. */
14492 /* Upper variant. LT bit. */
14496 /* Lower variant. GT bit. */
14501 error ("argument 1 of __builtin_spe_predicate is out of range");
14505 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
14506 emit_move_insn (target
, tmp
);
14511 /* The evsel builtins look like this:
14513 e = __builtin_spe_evsel_OP (a, b, c, d);
14515 and work like this:
14517 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
14518 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
14522 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
14525 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14526 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14527 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14528 tree arg3
= CALL_EXPR_ARG (exp
, 3);
14529 rtx op0
= expand_normal (arg0
);
14530 rtx op1
= expand_normal (arg1
);
14531 rtx op2
= expand_normal (arg2
);
14532 rtx op3
= expand_normal (arg3
);
14533 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14534 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14536 gcc_assert (mode0
== mode1
);
14538 if (arg0
== error_mark_node
|| arg1
== error_mark_node
14539 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
14543 || GET_MODE (target
) != mode0
14544 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
14545 target
= gen_reg_rtx (mode0
);
14547 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14548 op0
= copy_to_mode_reg (mode0
, op0
);
14549 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
14550 op1
= copy_to_mode_reg (mode0
, op1
);
14551 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
14552 op2
= copy_to_mode_reg (mode0
, op2
);
14553 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
14554 op3
= copy_to_mode_reg (mode0
, op3
);
14556 /* Generate the compare. */
14557 scratch
= gen_reg_rtx (CCmode
);
14558 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14563 if (mode0
== V2SImode
)
14564 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
14566 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
14571 /* Raise an error message for a builtin function that is called without the
14572 appropriate target options being set. */
14575 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
14577 size_t uns_fncode
= (size_t)fncode
;
14578 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
14579 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
14581 gcc_assert (name
!= NULL
);
14582 if ((fnmask
& RS6000_BTM_CELL
) != 0)
14583 error ("Builtin function %s is only valid for the cell processor", name
);
14584 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
14585 error ("Builtin function %s requires the -mvsx option", name
);
14586 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
14587 error ("Builtin function %s requires the -mhtm option", name
);
14588 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
14589 error ("Builtin function %s requires the -maltivec option", name
);
14590 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
14591 error ("Builtin function %s requires the -mpaired option", name
);
14592 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
14593 error ("Builtin function %s requires the -mspe option", name
);
14594 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
14595 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
14596 error ("Builtin function %s requires the -mhard-dfp and"
14597 " -mpower8-vector options", name
);
14598 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
14599 error ("Builtin function %s requires the -mhard-dfp option", name
);
14600 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
14601 error ("Builtin function %s requires the -mpower8-vector option", name
);
14602 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
14603 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
14604 error ("Builtin function %s requires the -mhard-float and"
14605 " -mlong-double-128 options", name
);
14606 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
14607 error ("Builtin function %s requires the -mhard-float option", name
);
14609 error ("Builtin function %s is not supported with the current options",
14613 /* Expand an expression EXP that calls a built-in function,
14614 with result going to TARGET if that's convenient
14615 (and in mode MODE if that's convenient).
14616 SUBTARGET may be used as the target for computing one of EXP's operands.
14617 IGNORE is nonzero if the value is to be ignored. */
14620 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14621 machine_mode mode ATTRIBUTE_UNUSED
,
14622 int ignore ATTRIBUTE_UNUSED
)
14624 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14625 enum rs6000_builtins fcode
14626 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
14627 size_t uns_fcode
= (size_t)fcode
;
14628 const struct builtin_description
*d
;
14632 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
14633 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
14635 if (TARGET_DEBUG_BUILTIN
)
14637 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
14638 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
14639 const char *name2
= ((icode
!= CODE_FOR_nothing
)
14640 ? get_insn_name ((int)icode
)
14644 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
14646 default: name3
= "unknown"; break;
14647 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
14648 case RS6000_BTC_UNARY
: name3
= "unary"; break;
14649 case RS6000_BTC_BINARY
: name3
= "binary"; break;
14650 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
14651 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
14652 case RS6000_BTC_ABS
: name3
= "abs"; break;
14653 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
14654 case RS6000_BTC_DST
: name3
= "dst"; break;
14659 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
14660 (name1
) ? name1
: "---", fcode
,
14661 (name2
) ? name2
: "---", (int)icode
,
14663 func_valid_p
? "" : ", not valid");
14668 rs6000_invalid_builtin (fcode
);
14670 /* Given it is invalid, just generate a normal call. */
14671 return expand_call (exp
, target
, ignore
);
14676 case RS6000_BUILTIN_RECIP
:
14677 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
14679 case RS6000_BUILTIN_RECIPF
:
14680 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
14682 case RS6000_BUILTIN_RSQRTF
:
14683 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
14685 case RS6000_BUILTIN_RSQRT
:
14686 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
14688 case POWER7_BUILTIN_BPERMD
:
14689 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
14690 ? CODE_FOR_bpermd_di
14691 : CODE_FOR_bpermd_si
), exp
, target
);
14693 case RS6000_BUILTIN_GET_TB
:
14694 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
14697 case RS6000_BUILTIN_MFTB
:
14698 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
14699 ? CODE_FOR_rs6000_mftb_di
14700 : CODE_FOR_rs6000_mftb_si
),
14703 case RS6000_BUILTIN_MFFS
:
14704 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
14706 case RS6000_BUILTIN_MTFSF
:
14707 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
14709 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
14710 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
14712 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
14713 : (int) CODE_FOR_altivec_lvsl_direct
);
14714 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14715 machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
14719 gcc_assert (TARGET_ALTIVEC
);
14721 arg
= CALL_EXPR_ARG (exp
, 0);
14722 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
14723 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
14724 addr
= memory_address (mode
, op
);
14725 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
14729 /* For the load case need to negate the address. */
14730 op
= gen_reg_rtx (GET_MODE (addr
));
14731 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
14733 op
= gen_rtx_MEM (mode
, op
);
14736 || GET_MODE (target
) != tmode
14737 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14738 target
= gen_reg_rtx (tmode
);
14740 pat
= GEN_FCN (icode
) (target
, op
);
14748 case ALTIVEC_BUILTIN_VCFUX
:
14749 case ALTIVEC_BUILTIN_VCFSX
:
14750 case ALTIVEC_BUILTIN_VCTUXS
:
14751 case ALTIVEC_BUILTIN_VCTSXS
:
14752 /* FIXME: There's got to be a nicer way to handle this case than
14753 constructing a new CALL_EXPR. */
14754 if (call_expr_nargs (exp
) == 1)
14756 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
14757 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
14765 if (TARGET_ALTIVEC
)
14767 ret
= altivec_expand_builtin (exp
, target
, &success
);
14774 ret
= spe_expand_builtin (exp
, target
, &success
);
14779 if (TARGET_PAIRED_FLOAT
)
14781 ret
= paired_expand_builtin (exp
, target
, &success
);
14788 ret
= htm_expand_builtin (exp
, target
, &success
);
14794 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
14795 gcc_assert (attr
== RS6000_BTC_UNARY
14796 || attr
== RS6000_BTC_BINARY
14797 || attr
== RS6000_BTC_TERNARY
);
14799 /* Handle simple unary operations. */
14801 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14802 if (d
->code
== fcode
)
14803 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
14805 /* Handle simple binary operations. */
14807 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14808 if (d
->code
== fcode
)
14809 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
14811 /* Handle simple ternary operations. */
14813 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14814 if (d
->code
== fcode
)
14815 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
14817 gcc_unreachable ();
14821 rs6000_init_builtins (void)
14827 if (TARGET_DEBUG_BUILTIN
)
14828 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
14829 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
14830 (TARGET_SPE
) ? ", spe" : "",
14831 (TARGET_ALTIVEC
) ? ", altivec" : "",
14832 (TARGET_VSX
) ? ", vsx" : "");
14834 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
14835 V2SF_type_node
= build_vector_type (float_type_node
, 2);
14836 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
14837 V2DF_type_node
= build_vector_type (double_type_node
, 2);
14838 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
14839 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
14840 V4SF_type_node
= build_vector_type (float_type_node
, 4);
14841 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
14842 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
14844 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
14845 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
14846 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
14847 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
14849 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
14850 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
14851 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
14852 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
14854 /* We use V1TI mode as a special container to hold __int128_t items that
14855 must live in VSX registers. */
14856 if (intTI_type_node
)
14858 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
14859 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
14862 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
14863 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
14864 'vector unsigned short'. */
14866 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
14867 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14868 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
14869 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
14870 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14872 long_integer_type_internal_node
= long_integer_type_node
;
14873 long_unsigned_type_internal_node
= long_unsigned_type_node
;
14874 long_long_integer_type_internal_node
= long_long_integer_type_node
;
14875 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
14876 intQI_type_internal_node
= intQI_type_node
;
14877 uintQI_type_internal_node
= unsigned_intQI_type_node
;
14878 intHI_type_internal_node
= intHI_type_node
;
14879 uintHI_type_internal_node
= unsigned_intHI_type_node
;
14880 intSI_type_internal_node
= intSI_type_node
;
14881 uintSI_type_internal_node
= unsigned_intSI_type_node
;
14882 intDI_type_internal_node
= intDI_type_node
;
14883 uintDI_type_internal_node
= unsigned_intDI_type_node
;
14884 intTI_type_internal_node
= intTI_type_node
;
14885 uintTI_type_internal_node
= unsigned_intTI_type_node
;
14886 float_type_internal_node
= float_type_node
;
14887 double_type_internal_node
= double_type_node
;
14888 long_double_type_internal_node
= long_double_type_node
;
14889 dfloat64_type_internal_node
= dfloat64_type_node
;
14890 dfloat128_type_internal_node
= dfloat128_type_node
;
14891 void_type_internal_node
= void_type_node
;
14893 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
14894 IFmode is the IBM extended 128-bit format that is a pair of doubles.
14895 TFmode will be either IEEE 128-bit floating point or the IBM double-double
14896 format that uses a pair of doubles, depending on the switches and
14898 if (TARGET_FLOAT128
)
14900 ibm128_float_type_node
= make_node (REAL_TYPE
);
14901 TYPE_PRECISION (ibm128_float_type_node
) = 128;
14902 layout_type (ibm128_float_type_node
);
14903 SET_TYPE_MODE (ibm128_float_type_node
, IFmode
);
14905 ieee128_float_type_node
= make_node (REAL_TYPE
);
14906 TYPE_PRECISION (ieee128_float_type_node
) = 128;
14907 layout_type (ieee128_float_type_node
);
14908 SET_TYPE_MODE (ieee128_float_type_node
, KFmode
);
14910 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
14913 lang_hooks
.types
.register_builtin_type (ibm128_float_type_node
,
14917 /* Initialize the modes for builtin_function_type, mapping a machine mode to
14919 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
14920 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
14921 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
14922 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
14923 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
14924 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
14925 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
14926 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
14927 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
14928 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
14929 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
14930 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
14931 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
14932 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
14933 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
14934 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
14935 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
14936 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
14937 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
14938 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
14939 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
14940 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
14941 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
14942 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
14943 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
14944 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
14945 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
14946 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
14947 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
14948 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
14950 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
14951 TYPE_NAME (bool_char_type_node
) = tdecl
;
14953 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
14954 TYPE_NAME (bool_short_type_node
) = tdecl
;
14956 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
14957 TYPE_NAME (bool_int_type_node
) = tdecl
;
14959 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
14960 TYPE_NAME (pixel_type_node
) = tdecl
;
14962 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
14963 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
14964 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
14965 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
14966 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
14968 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
14969 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
14971 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
14972 TYPE_NAME (V16QI_type_node
) = tdecl
;
14974 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
14975 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
14977 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
14978 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
14980 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
14981 TYPE_NAME (V8HI_type_node
) = tdecl
;
14983 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
14984 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
14986 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
14987 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
14989 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
14990 TYPE_NAME (V4SI_type_node
) = tdecl
;
14992 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
14993 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
14995 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
14996 TYPE_NAME (V4SF_type_node
) = tdecl
;
14998 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
14999 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
15001 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
15002 TYPE_NAME (V2DF_type_node
) = tdecl
;
15004 if (TARGET_POWERPC64
)
15006 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
15007 TYPE_NAME (V2DI_type_node
) = tdecl
;
15009 tdecl
= add_builtin_type ("__vector unsigned long",
15010 unsigned_V2DI_type_node
);
15011 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
15013 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
15014 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
15018 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
15019 TYPE_NAME (V2DI_type_node
) = tdecl
;
15021 tdecl
= add_builtin_type ("__vector unsigned long long",
15022 unsigned_V2DI_type_node
);
15023 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
15025 tdecl
= add_builtin_type ("__vector __bool long long",
15026 bool_V2DI_type_node
);
15027 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
15030 if (V1TI_type_node
)
15032 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
15033 TYPE_NAME (V1TI_type_node
) = tdecl
;
15035 tdecl
= add_builtin_type ("__vector unsigned __int128",
15036 unsigned_V1TI_type_node
);
15037 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
15040 /* Paired and SPE builtins are only available if you build a compiler with
15041 the appropriate options, so only create those builtins with the
15042 appropriate compiler option. Create Altivec and VSX builtins on machines
15043 with at least the general purpose extensions (970 and newer) to allow the
15044 use of the target attribute. */
15045 if (TARGET_PAIRED_FLOAT
)
15046 paired_init_builtins ();
15048 spe_init_builtins ();
15049 if (TARGET_EXTRA_BUILTINS
)
15050 altivec_init_builtins ();
15052 htm_init_builtins ();
15054 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
15055 rs6000_common_init_builtins ();
15057 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
15058 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
15059 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
15061 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
15062 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
15063 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
15065 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
15066 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
15067 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
15069 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
15070 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
15071 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
15073 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
15074 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
15075 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
15076 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
15078 ftype
= build_function_type_list (unsigned_intDI_type_node
,
15080 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
15083 ftype
= build_function_type_list (unsigned_intDI_type_node
,
15086 ftype
= build_function_type_list (unsigned_intSI_type_node
,
15088 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
15090 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
15091 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
15093 ftype
= build_function_type_list (void_type_node
,
15094 intSI_type_node
, double_type_node
,
15096 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
15099 /* AIX libm provides clog as __clog. */
15100 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
15101 set_user_assembler_name (tdecl
, "__clog");
15104 #ifdef SUBTARGET_INIT_BUILTINS
15105 SUBTARGET_INIT_BUILTINS
;
15109 /* Returns the rs6000 builtin decl for CODE. */
15112 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
15114 HOST_WIDE_INT fnmask
;
15116 if (code
>= RS6000_BUILTIN_COUNT
)
15117 return error_mark_node
;
15119 fnmask
= rs6000_builtin_info
[code
].mask
;
15120 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
15122 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
15123 return error_mark_node
;
15126 return rs6000_builtin_decls
[code
];
15130 spe_init_builtins (void)
15132 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
15133 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
15134 const struct builtin_description
*d
;
15137 tree v2si_ftype_4_v2si
15138 = build_function_type_list (opaque_V2SI_type_node
,
15139 opaque_V2SI_type_node
,
15140 opaque_V2SI_type_node
,
15141 opaque_V2SI_type_node
,
15142 opaque_V2SI_type_node
,
15145 tree v2sf_ftype_4_v2sf
15146 = build_function_type_list (opaque_V2SF_type_node
,
15147 opaque_V2SF_type_node
,
15148 opaque_V2SF_type_node
,
15149 opaque_V2SF_type_node
,
15150 opaque_V2SF_type_node
,
15153 tree int_ftype_int_v2si_v2si
15154 = build_function_type_list (integer_type_node
,
15156 opaque_V2SI_type_node
,
15157 opaque_V2SI_type_node
,
15160 tree int_ftype_int_v2sf_v2sf
15161 = build_function_type_list (integer_type_node
,
15163 opaque_V2SF_type_node
,
15164 opaque_V2SF_type_node
,
15167 tree void_ftype_v2si_puint_int
15168 = build_function_type_list (void_type_node
,
15169 opaque_V2SI_type_node
,
15174 tree void_ftype_v2si_puint_char
15175 = build_function_type_list (void_type_node
,
15176 opaque_V2SI_type_node
,
15181 tree void_ftype_v2si_pv2si_int
15182 = build_function_type_list (void_type_node
,
15183 opaque_V2SI_type_node
,
15184 opaque_p_V2SI_type_node
,
15188 tree void_ftype_v2si_pv2si_char
15189 = build_function_type_list (void_type_node
,
15190 opaque_V2SI_type_node
,
15191 opaque_p_V2SI_type_node
,
15195 tree void_ftype_int
15196 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
15198 tree int_ftype_void
15199 = build_function_type_list (integer_type_node
, NULL_TREE
);
15201 tree v2si_ftype_pv2si_int
15202 = build_function_type_list (opaque_V2SI_type_node
,
15203 opaque_p_V2SI_type_node
,
15207 tree v2si_ftype_puint_int
15208 = build_function_type_list (opaque_V2SI_type_node
,
15213 tree v2si_ftype_pushort_int
15214 = build_function_type_list (opaque_V2SI_type_node
,
15219 tree v2si_ftype_signed_char
15220 = build_function_type_list (opaque_V2SI_type_node
,
15221 signed_char_type_node
,
15224 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
15226 /* Initialize irregular SPE builtins. */
15228 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
15229 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
15230 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
15231 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
15232 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
15233 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
15234 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
15235 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
15236 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
15237 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
15238 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
15239 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
15240 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
15241 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
15242 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
15243 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
15244 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
15245 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
15248 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
15249 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
15250 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
15251 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
15252 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
15253 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
15254 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
15255 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
15256 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
15257 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
15258 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
15259 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
15260 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
15261 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
15262 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
15263 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
15264 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
15265 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
15266 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
15267 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
15268 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
15269 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
15272 d
= bdesc_spe_predicates
;
15273 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
15277 switch (insn_data
[d
->icode
].operand
[1].mode
)
15280 type
= int_ftype_int_v2si_v2si
;
15283 type
= int_ftype_int_v2sf_v2sf
;
15286 gcc_unreachable ();
15289 def_builtin (d
->name
, type
, d
->code
);
15292 /* Evsel predicates. */
15293 d
= bdesc_spe_evsel
;
15294 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
15298 switch (insn_data
[d
->icode
].operand
[1].mode
)
15301 type
= v2si_ftype_4_v2si
;
15304 type
= v2sf_ftype_4_v2sf
;
15307 gcc_unreachable ();
15310 def_builtin (d
->name
, type
, d
->code
);
15315 paired_init_builtins (void)
15317 const struct builtin_description
*d
;
15320 tree int_ftype_int_v2sf_v2sf
15321 = build_function_type_list (integer_type_node
,
15326 tree pcfloat_type_node
=
15327 build_pointer_type (build_qualified_type
15328 (float_type_node
, TYPE_QUAL_CONST
));
15330 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
15331 long_integer_type_node
,
15334 tree void_ftype_v2sf_long_pcfloat
=
15335 build_function_type_list (void_type_node
,
15337 long_integer_type_node
,
15342 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
15343 PAIRED_BUILTIN_LX
);
15346 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
15347 PAIRED_BUILTIN_STX
);
15350 d
= bdesc_paired_preds
;
15351 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
15355 if (TARGET_DEBUG_BUILTIN
)
15356 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
15357 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
15358 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
15360 switch (insn_data
[d
->icode
].operand
[1].mode
)
15363 type
= int_ftype_int_v2sf_v2sf
;
15366 gcc_unreachable ();
15369 def_builtin (d
->name
, type
, d
->code
);
15374 altivec_init_builtins (void)
15376 const struct builtin_description
*d
;
15381 tree pvoid_type_node
= build_pointer_type (void_type_node
);
15383 tree pcvoid_type_node
15384 = build_pointer_type (build_qualified_type (void_type_node
,
15387 tree int_ftype_opaque
15388 = build_function_type_list (integer_type_node
,
15389 opaque_V4SI_type_node
, NULL_TREE
);
15390 tree opaque_ftype_opaque
15391 = build_function_type_list (integer_type_node
, NULL_TREE
);
15392 tree opaque_ftype_opaque_int
15393 = build_function_type_list (opaque_V4SI_type_node
,
15394 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
15395 tree opaque_ftype_opaque_opaque_int
15396 = build_function_type_list (opaque_V4SI_type_node
,
15397 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
15398 integer_type_node
, NULL_TREE
);
15399 tree int_ftype_int_opaque_opaque
15400 = build_function_type_list (integer_type_node
,
15401 integer_type_node
, opaque_V4SI_type_node
,
15402 opaque_V4SI_type_node
, NULL_TREE
);
15403 tree int_ftype_int_v4si_v4si
15404 = build_function_type_list (integer_type_node
,
15405 integer_type_node
, V4SI_type_node
,
15406 V4SI_type_node
, NULL_TREE
);
15407 tree int_ftype_int_v2di_v2di
15408 = build_function_type_list (integer_type_node
,
15409 integer_type_node
, V2DI_type_node
,
15410 V2DI_type_node
, NULL_TREE
);
15411 tree void_ftype_v4si
15412 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
15413 tree v8hi_ftype_void
15414 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
15415 tree void_ftype_void
15416 = build_function_type_list (void_type_node
, NULL_TREE
);
15417 tree void_ftype_int
15418 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
15420 tree opaque_ftype_long_pcvoid
15421 = build_function_type_list (opaque_V4SI_type_node
,
15422 long_integer_type_node
, pcvoid_type_node
,
15424 tree v16qi_ftype_long_pcvoid
15425 = build_function_type_list (V16QI_type_node
,
15426 long_integer_type_node
, pcvoid_type_node
,
15428 tree v8hi_ftype_long_pcvoid
15429 = build_function_type_list (V8HI_type_node
,
15430 long_integer_type_node
, pcvoid_type_node
,
15432 tree v4si_ftype_long_pcvoid
15433 = build_function_type_list (V4SI_type_node
,
15434 long_integer_type_node
, pcvoid_type_node
,
15436 tree v4sf_ftype_long_pcvoid
15437 = build_function_type_list (V4SF_type_node
,
15438 long_integer_type_node
, pcvoid_type_node
,
15440 tree v2df_ftype_long_pcvoid
15441 = build_function_type_list (V2DF_type_node
,
15442 long_integer_type_node
, pcvoid_type_node
,
15444 tree v2di_ftype_long_pcvoid
15445 = build_function_type_list (V2DI_type_node
,
15446 long_integer_type_node
, pcvoid_type_node
,
15449 tree void_ftype_opaque_long_pvoid
15450 = build_function_type_list (void_type_node
,
15451 opaque_V4SI_type_node
, long_integer_type_node
,
15452 pvoid_type_node
, NULL_TREE
);
15453 tree void_ftype_v4si_long_pvoid
15454 = build_function_type_list (void_type_node
,
15455 V4SI_type_node
, long_integer_type_node
,
15456 pvoid_type_node
, NULL_TREE
);
15457 tree void_ftype_v16qi_long_pvoid
15458 = build_function_type_list (void_type_node
,
15459 V16QI_type_node
, long_integer_type_node
,
15460 pvoid_type_node
, NULL_TREE
);
15461 tree void_ftype_v8hi_long_pvoid
15462 = build_function_type_list (void_type_node
,
15463 V8HI_type_node
, long_integer_type_node
,
15464 pvoid_type_node
, NULL_TREE
);
15465 tree void_ftype_v4sf_long_pvoid
15466 = build_function_type_list (void_type_node
,
15467 V4SF_type_node
, long_integer_type_node
,
15468 pvoid_type_node
, NULL_TREE
);
15469 tree void_ftype_v2df_long_pvoid
15470 = build_function_type_list (void_type_node
,
15471 V2DF_type_node
, long_integer_type_node
,
15472 pvoid_type_node
, NULL_TREE
);
15473 tree void_ftype_v2di_long_pvoid
15474 = build_function_type_list (void_type_node
,
15475 V2DI_type_node
, long_integer_type_node
,
15476 pvoid_type_node
, NULL_TREE
);
15477 tree int_ftype_int_v8hi_v8hi
15478 = build_function_type_list (integer_type_node
,
15479 integer_type_node
, V8HI_type_node
,
15480 V8HI_type_node
, NULL_TREE
);
15481 tree int_ftype_int_v16qi_v16qi
15482 = build_function_type_list (integer_type_node
,
15483 integer_type_node
, V16QI_type_node
,
15484 V16QI_type_node
, NULL_TREE
);
15485 tree int_ftype_int_v4sf_v4sf
15486 = build_function_type_list (integer_type_node
,
15487 integer_type_node
, V4SF_type_node
,
15488 V4SF_type_node
, NULL_TREE
);
15489 tree int_ftype_int_v2df_v2df
15490 = build_function_type_list (integer_type_node
,
15491 integer_type_node
, V2DF_type_node
,
15492 V2DF_type_node
, NULL_TREE
);
15493 tree v2di_ftype_v2di
15494 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
15495 tree v4si_ftype_v4si
15496 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
15497 tree v8hi_ftype_v8hi
15498 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
15499 tree v16qi_ftype_v16qi
15500 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
15501 tree v4sf_ftype_v4sf
15502 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
15503 tree v2df_ftype_v2df
15504 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
15505 tree void_ftype_pcvoid_int_int
15506 = build_function_type_list (void_type_node
,
15507 pcvoid_type_node
, integer_type_node
,
15508 integer_type_node
, NULL_TREE
);
15510 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
15511 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
15512 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
15513 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
15514 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
15515 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
15516 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
15517 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
15518 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
15519 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
15520 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
15521 ALTIVEC_BUILTIN_LVXL_V2DF
);
15522 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
15523 ALTIVEC_BUILTIN_LVXL_V2DI
);
15524 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
15525 ALTIVEC_BUILTIN_LVXL_V4SF
);
15526 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
15527 ALTIVEC_BUILTIN_LVXL_V4SI
);
15528 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
15529 ALTIVEC_BUILTIN_LVXL_V8HI
);
15530 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
15531 ALTIVEC_BUILTIN_LVXL_V16QI
);
15532 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
15533 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
15534 ALTIVEC_BUILTIN_LVX_V2DF
);
15535 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
15536 ALTIVEC_BUILTIN_LVX_V2DI
);
15537 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
15538 ALTIVEC_BUILTIN_LVX_V4SF
);
15539 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
15540 ALTIVEC_BUILTIN_LVX_V4SI
);
15541 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
15542 ALTIVEC_BUILTIN_LVX_V8HI
);
15543 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
15544 ALTIVEC_BUILTIN_LVX_V16QI
);
15545 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
15546 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
15547 ALTIVEC_BUILTIN_STVX_V2DF
);
15548 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
15549 ALTIVEC_BUILTIN_STVX_V2DI
);
15550 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
15551 ALTIVEC_BUILTIN_STVX_V4SF
);
15552 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
15553 ALTIVEC_BUILTIN_STVX_V4SI
);
15554 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
15555 ALTIVEC_BUILTIN_STVX_V8HI
);
15556 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
15557 ALTIVEC_BUILTIN_STVX_V16QI
);
15558 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
15559 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
15560 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
15561 ALTIVEC_BUILTIN_STVXL_V2DF
);
15562 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
15563 ALTIVEC_BUILTIN_STVXL_V2DI
);
15564 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
15565 ALTIVEC_BUILTIN_STVXL_V4SF
);
15566 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
15567 ALTIVEC_BUILTIN_STVXL_V4SI
);
15568 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
15569 ALTIVEC_BUILTIN_STVXL_V8HI
);
15570 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
15571 ALTIVEC_BUILTIN_STVXL_V16QI
);
15572 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
15573 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
15574 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
15575 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
15576 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
15577 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
15578 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
15579 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
15580 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
15581 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
15582 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
15583 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
15584 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
15585 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
15586 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
15587 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
15589 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
15590 VSX_BUILTIN_LXVD2X_V2DF
);
15591 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
15592 VSX_BUILTIN_LXVD2X_V2DI
);
15593 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
15594 VSX_BUILTIN_LXVW4X_V4SF
);
15595 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
15596 VSX_BUILTIN_LXVW4X_V4SI
);
15597 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
15598 VSX_BUILTIN_LXVW4X_V8HI
);
15599 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
15600 VSX_BUILTIN_LXVW4X_V16QI
);
15601 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
15602 VSX_BUILTIN_STXVD2X_V2DF
);
15603 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
15604 VSX_BUILTIN_STXVD2X_V2DI
);
15605 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
15606 VSX_BUILTIN_STXVW4X_V4SF
);
15607 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
15608 VSX_BUILTIN_STXVW4X_V4SI
);
15609 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
15610 VSX_BUILTIN_STXVW4X_V8HI
);
15611 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
15612 VSX_BUILTIN_STXVW4X_V16QI
);
15613 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
15614 VSX_BUILTIN_VEC_LD
);
15615 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
15616 VSX_BUILTIN_VEC_ST
);
15618 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
15619 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
15620 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
15622 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
15623 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
15624 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
15625 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
15626 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
15627 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
15628 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
15629 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
15630 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
15631 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
15632 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
15633 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
15635 /* Cell builtins. */
15636 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
15637 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
15638 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
15639 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
15641 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
15642 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
15643 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
15644 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
15646 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
15647 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
15648 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
15649 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
15651 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
15652 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
15653 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
15654 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
15656 /* Add the DST variants. */
15658 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
15659 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
15661 /* Initialize the predicates. */
15662 d
= bdesc_altivec_preds
;
15663 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
15665 machine_mode mode1
;
15668 if (rs6000_overloaded_builtin_p (d
->code
))
15671 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
15676 type
= int_ftype_int_opaque_opaque
;
15679 type
= int_ftype_int_v2di_v2di
;
15682 type
= int_ftype_int_v4si_v4si
;
15685 type
= int_ftype_int_v8hi_v8hi
;
15688 type
= int_ftype_int_v16qi_v16qi
;
15691 type
= int_ftype_int_v4sf_v4sf
;
15694 type
= int_ftype_int_v2df_v2df
;
15697 gcc_unreachable ();
15700 def_builtin (d
->name
, type
, d
->code
);
15703 /* Initialize the abs* operators. */
15705 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
15707 machine_mode mode0
;
15710 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
15715 type
= v2di_ftype_v2di
;
15718 type
= v4si_ftype_v4si
;
15721 type
= v8hi_ftype_v8hi
;
15724 type
= v16qi_ftype_v16qi
;
15727 type
= v4sf_ftype_v4sf
;
15730 type
= v2df_ftype_v2df
;
15733 gcc_unreachable ();
15736 def_builtin (d
->name
, type
, d
->code
);
15739 /* Initialize target builtin that implements
15740 targetm.vectorize.builtin_mask_for_load. */
15742 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
15743 v16qi_ftype_long_pcvoid
,
15744 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
15745 BUILT_IN_MD
, NULL
, NULL_TREE
);
15746 TREE_READONLY (decl
) = 1;
15747 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
15748 altivec_builtin_mask_for_load
= decl
;
15750 /* Access to the vec_init patterns. */
15751 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
15752 integer_type_node
, integer_type_node
,
15753 integer_type_node
, NULL_TREE
);
15754 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
15756 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
15757 short_integer_type_node
,
15758 short_integer_type_node
,
15759 short_integer_type_node
,
15760 short_integer_type_node
,
15761 short_integer_type_node
,
15762 short_integer_type_node
,
15763 short_integer_type_node
, NULL_TREE
);
15764 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
15766 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
15767 char_type_node
, char_type_node
,
15768 char_type_node
, char_type_node
,
15769 char_type_node
, char_type_node
,
15770 char_type_node
, char_type_node
,
15771 char_type_node
, char_type_node
,
15772 char_type_node
, char_type_node
,
15773 char_type_node
, char_type_node
,
15774 char_type_node
, NULL_TREE
);
15775 def_builtin ("__builtin_vec_init_v16qi", ftype
,
15776 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
15778 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
15779 float_type_node
, float_type_node
,
15780 float_type_node
, NULL_TREE
);
15781 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
15783 /* VSX builtins. */
15784 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
15785 double_type_node
, NULL_TREE
);
15786 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
15788 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
15789 intDI_type_node
, NULL_TREE
);
15790 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
15792 /* Access to the vec_set patterns. */
15793 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
15795 integer_type_node
, NULL_TREE
);
15796 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
15798 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
15800 integer_type_node
, NULL_TREE
);
15801 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
15803 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
15805 integer_type_node
, NULL_TREE
);
15806 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
15808 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
15810 integer_type_node
, NULL_TREE
);
15811 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
15813 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
15815 integer_type_node
, NULL_TREE
);
15816 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
15818 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
15820 integer_type_node
, NULL_TREE
);
15821 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
15823 /* Access to the vec_extract patterns. */
15824 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
15825 integer_type_node
, NULL_TREE
);
15826 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
15828 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
15829 integer_type_node
, NULL_TREE
);
15830 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
15832 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
15833 integer_type_node
, NULL_TREE
);
15834 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
15836 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
15837 integer_type_node
, NULL_TREE
);
15838 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
15840 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
15841 integer_type_node
, NULL_TREE
);
15842 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
15844 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
15845 integer_type_node
, NULL_TREE
);
15846 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
15849 if (V1TI_type_node
)
15851 tree v1ti_ftype_long_pcvoid
15852 = build_function_type_list (V1TI_type_node
,
15853 long_integer_type_node
, pcvoid_type_node
,
15855 tree void_ftype_v1ti_long_pvoid
15856 = build_function_type_list (void_type_node
,
15857 V1TI_type_node
, long_integer_type_node
,
15858 pvoid_type_node
, NULL_TREE
);
15859 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
15860 VSX_BUILTIN_LXVD2X_V1TI
);
15861 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
15862 VSX_BUILTIN_STXVD2X_V1TI
);
15863 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
15864 NULL_TREE
, NULL_TREE
);
15865 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
15866 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
15868 integer_type_node
, NULL_TREE
);
15869 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
15870 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
15871 integer_type_node
, NULL_TREE
);
15872 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
15878 htm_init_builtins (void)
15880 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15881 const struct builtin_description
*d
;
15885 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
15887 tree op
[MAX_HTM_OPERANDS
], type
;
15888 HOST_WIDE_INT mask
= d
->mask
;
15889 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
15890 bool void_func
= (attr
& RS6000_BTC_VOID
);
15891 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
15893 tree gpr_type_node
;
15897 if (TARGET_32BIT
&& TARGET_POWERPC64
)
15898 gpr_type_node
= long_long_unsigned_type_node
;
15900 gpr_type_node
= long_unsigned_type_node
;
15902 if (attr
& RS6000_BTC_SPR
)
15904 rettype
= gpr_type_node
;
15905 argtype
= gpr_type_node
;
15907 else if (d
->code
== HTM_BUILTIN_TABORTDC
15908 || d
->code
== HTM_BUILTIN_TABORTDCI
)
15910 rettype
= unsigned_type_node
;
15911 argtype
= gpr_type_node
;
15915 rettype
= unsigned_type_node
;
15916 argtype
= unsigned_type_node
;
15919 if ((mask
& builtin_mask
) != mask
)
15921 if (TARGET_DEBUG_BUILTIN
)
15922 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
15928 if (TARGET_DEBUG_BUILTIN
)
15929 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
15930 (long unsigned) i
);
15934 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
15936 if (attr_args
== RS6000_BTC_UNARY
)
15937 op
[nopnds
++] = argtype
;
15938 else if (attr_args
== RS6000_BTC_BINARY
)
15940 op
[nopnds
++] = argtype
;
15941 op
[nopnds
++] = argtype
;
15943 else if (attr_args
== RS6000_BTC_TERNARY
)
15945 op
[nopnds
++] = argtype
;
15946 op
[nopnds
++] = argtype
;
15947 op
[nopnds
++] = argtype
;
15953 type
= build_function_type_list (op
[0], NULL_TREE
);
15956 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
15959 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
15962 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
15966 gcc_unreachable ();
15969 def_builtin (d
->name
, type
, d
->code
);
15973 /* Hash function for builtin functions with up to 3 arguments and a return
15976 builtin_hasher::hash (builtin_hash_struct
*bh
)
15981 for (i
= 0; i
< 4; i
++)
15983 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
15984 ret
= (ret
* 2) + bh
->uns_p
[i
];
15990 /* Compare builtin hash entries H1 and H2 for equivalence. */
15992 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
15994 return ((p1
->mode
[0] == p2
->mode
[0])
15995 && (p1
->mode
[1] == p2
->mode
[1])
15996 && (p1
->mode
[2] == p2
->mode
[2])
15997 && (p1
->mode
[3] == p2
->mode
[3])
15998 && (p1
->uns_p
[0] == p2
->uns_p
[0])
15999 && (p1
->uns_p
[1] == p2
->uns_p
[1])
16000 && (p1
->uns_p
[2] == p2
->uns_p
[2])
16001 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
16004 /* Map types for builtin functions with an explicit return type and up to 3
16005 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
16006 of the argument. */
16008 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
16009 machine_mode mode_arg1
, machine_mode mode_arg2
,
16010 enum rs6000_builtins builtin
, const char *name
)
16012 struct builtin_hash_struct h
;
16013 struct builtin_hash_struct
*h2
;
16016 tree ret_type
= NULL_TREE
;
16017 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
16019 /* Create builtin_hash_table. */
16020 if (builtin_hash_table
== NULL
)
16021 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
16023 h
.type
= NULL_TREE
;
16024 h
.mode
[0] = mode_ret
;
16025 h
.mode
[1] = mode_arg0
;
16026 h
.mode
[2] = mode_arg1
;
16027 h
.mode
[3] = mode_arg2
;
16033 /* If the builtin is a type that produces unsigned results or takes unsigned
16034 arguments, and it is returned as a decl for the vectorizer (such as
16035 widening multiplies, permute), make sure the arguments and return value
16036 are type correct. */
16039 /* unsigned 1 argument functions. */
16040 case CRYPTO_BUILTIN_VSBOX
:
16041 case P8V_BUILTIN_VGBBD
:
16042 case MISC_BUILTIN_CDTBCD
:
16043 case MISC_BUILTIN_CBCDTD
:
16048 /* unsigned 2 argument functions. */
16049 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
16050 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
16051 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
16052 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
16053 case CRYPTO_BUILTIN_VCIPHER
:
16054 case CRYPTO_BUILTIN_VCIPHERLAST
:
16055 case CRYPTO_BUILTIN_VNCIPHER
:
16056 case CRYPTO_BUILTIN_VNCIPHERLAST
:
16057 case CRYPTO_BUILTIN_VPMSUMB
:
16058 case CRYPTO_BUILTIN_VPMSUMH
:
16059 case CRYPTO_BUILTIN_VPMSUMW
:
16060 case CRYPTO_BUILTIN_VPMSUMD
:
16061 case CRYPTO_BUILTIN_VPMSUM
:
16062 case MISC_BUILTIN_ADDG6S
:
16063 case MISC_BUILTIN_DIVWEU
:
16064 case MISC_BUILTIN_DIVWEUO
:
16065 case MISC_BUILTIN_DIVDEU
:
16066 case MISC_BUILTIN_DIVDEUO
:
16072 /* unsigned 3 argument functions. */
16073 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
16074 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
16075 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
16076 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
16077 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
16078 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
16079 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
16080 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
16081 case VSX_BUILTIN_VPERM_16QI_UNS
:
16082 case VSX_BUILTIN_VPERM_8HI_UNS
:
16083 case VSX_BUILTIN_VPERM_4SI_UNS
:
16084 case VSX_BUILTIN_VPERM_2DI_UNS
:
16085 case VSX_BUILTIN_XXSEL_16QI_UNS
:
16086 case VSX_BUILTIN_XXSEL_8HI_UNS
:
16087 case VSX_BUILTIN_XXSEL_4SI_UNS
:
16088 case VSX_BUILTIN_XXSEL_2DI_UNS
:
16089 case CRYPTO_BUILTIN_VPERMXOR
:
16090 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
16091 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
16092 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
16093 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
16094 case CRYPTO_BUILTIN_VSHASIGMAW
:
16095 case CRYPTO_BUILTIN_VSHASIGMAD
:
16096 case CRYPTO_BUILTIN_VSHASIGMA
:
16103 /* signed permute functions with unsigned char mask. */
16104 case ALTIVEC_BUILTIN_VPERM_16QI
:
16105 case ALTIVEC_BUILTIN_VPERM_8HI
:
16106 case ALTIVEC_BUILTIN_VPERM_4SI
:
16107 case ALTIVEC_BUILTIN_VPERM_4SF
:
16108 case ALTIVEC_BUILTIN_VPERM_2DI
:
16109 case ALTIVEC_BUILTIN_VPERM_2DF
:
16110 case VSX_BUILTIN_VPERM_16QI
:
16111 case VSX_BUILTIN_VPERM_8HI
:
16112 case VSX_BUILTIN_VPERM_4SI
:
16113 case VSX_BUILTIN_VPERM_4SF
:
16114 case VSX_BUILTIN_VPERM_2DI
:
16115 case VSX_BUILTIN_VPERM_2DF
:
16119 /* unsigned args, signed return. */
16120 case VSX_BUILTIN_XVCVUXDDP_UNS
:
16121 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
16125 /* signed args, unsigned return. */
16126 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
16127 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
16128 case MISC_BUILTIN_UNPACK_TD
:
16129 case MISC_BUILTIN_UNPACK_V1TI
:
16133 /* unsigned arguments for 128-bit pack instructions. */
16134 case MISC_BUILTIN_PACK_TD
:
16135 case MISC_BUILTIN_PACK_V1TI
:
16144 /* Figure out how many args are present. */
16145 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
16149 fatal_error (input_location
,
16150 "internal error: builtin function %s had no type", name
);
16152 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
16153 if (!ret_type
&& h
.uns_p
[0])
16154 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
16157 fatal_error (input_location
,
16158 "internal error: builtin function %s had an unexpected "
16159 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
16161 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
16162 arg_type
[i
] = NULL_TREE
;
16164 for (i
= 0; i
< num_args
; i
++)
16166 int m
= (int) h
.mode
[i
+1];
16167 int uns_p
= h
.uns_p
[i
+1];
16169 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
16170 if (!arg_type
[i
] && uns_p
)
16171 arg_type
[i
] = builtin_mode_to_type
[m
][0];
16174 fatal_error (input_location
,
16175 "internal error: builtin function %s, argument %d "
16176 "had unexpected argument type %s", name
, i
,
16177 GET_MODE_NAME (m
));
16180 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
16181 if (*found
== NULL
)
16183 h2
= ggc_alloc
<builtin_hash_struct
> ();
16187 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
16188 arg_type
[2], NULL_TREE
);
16191 return (*found
)->type
;
16195 rs6000_common_init_builtins (void)
16197 const struct builtin_description
*d
;
16200 tree opaque_ftype_opaque
= NULL_TREE
;
16201 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
16202 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
16203 tree v2si_ftype_qi
= NULL_TREE
;
16204 tree v2si_ftype_v2si_qi
= NULL_TREE
;
16205 tree v2si_ftype_int_qi
= NULL_TREE
;
16206 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
16208 if (!TARGET_PAIRED_FLOAT
)
16210 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
16211 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
16214 /* Paired and SPE builtins are only available if you build a compiler with
16215 the appropriate options, so only create those builtins with the
16216 appropriate compiler option. Create Altivec and VSX builtins on machines
16217 with at least the general purpose extensions (970 and newer) to allow the
16218 use of the target attribute.. */
16220 if (TARGET_EXTRA_BUILTINS
)
16221 builtin_mask
|= RS6000_BTM_COMMON
;
16223 /* Add the ternary operators. */
16225 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
16228 HOST_WIDE_INT mask
= d
->mask
;
16230 if ((mask
& builtin_mask
) != mask
)
16232 if (TARGET_DEBUG_BUILTIN
)
16233 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
16237 if (rs6000_overloaded_builtin_p (d
->code
))
16239 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
16240 type
= opaque_ftype_opaque_opaque_opaque
16241 = build_function_type_list (opaque_V4SI_type_node
,
16242 opaque_V4SI_type_node
,
16243 opaque_V4SI_type_node
,
16244 opaque_V4SI_type_node
,
16249 enum insn_code icode
= d
->icode
;
16252 if (TARGET_DEBUG_BUILTIN
)
16253 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
16259 if (icode
== CODE_FOR_nothing
)
16261 if (TARGET_DEBUG_BUILTIN
)
16262 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
16268 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
16269 insn_data
[icode
].operand
[1].mode
,
16270 insn_data
[icode
].operand
[2].mode
,
16271 insn_data
[icode
].operand
[3].mode
,
16275 def_builtin (d
->name
, type
, d
->code
);
16278 /* Add the binary operators. */
16280 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16282 machine_mode mode0
, mode1
, mode2
;
16284 HOST_WIDE_INT mask
= d
->mask
;
16286 if ((mask
& builtin_mask
) != mask
)
16288 if (TARGET_DEBUG_BUILTIN
)
16289 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
16293 if (rs6000_overloaded_builtin_p (d
->code
))
16295 if (! (type
= opaque_ftype_opaque_opaque
))
16296 type
= opaque_ftype_opaque_opaque
16297 = build_function_type_list (opaque_V4SI_type_node
,
16298 opaque_V4SI_type_node
,
16299 opaque_V4SI_type_node
,
16304 enum insn_code icode
= d
->icode
;
16307 if (TARGET_DEBUG_BUILTIN
)
16308 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
16314 if (icode
== CODE_FOR_nothing
)
16316 if (TARGET_DEBUG_BUILTIN
)
16317 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
16323 mode0
= insn_data
[icode
].operand
[0].mode
;
16324 mode1
= insn_data
[icode
].operand
[1].mode
;
16325 mode2
= insn_data
[icode
].operand
[2].mode
;
16327 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
16329 if (! (type
= v2si_ftype_v2si_qi
))
16330 type
= v2si_ftype_v2si_qi
16331 = build_function_type_list (opaque_V2SI_type_node
,
16332 opaque_V2SI_type_node
,
16337 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
16338 && mode2
== QImode
)
16340 if (! (type
= v2si_ftype_int_qi
))
16341 type
= v2si_ftype_int_qi
16342 = build_function_type_list (opaque_V2SI_type_node
,
16349 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
16353 def_builtin (d
->name
, type
, d
->code
);
16356 /* Add the simple unary operators. */
16358 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
16360 machine_mode mode0
, mode1
;
16362 HOST_WIDE_INT mask
= d
->mask
;
16364 if ((mask
& builtin_mask
) != mask
)
16366 if (TARGET_DEBUG_BUILTIN
)
16367 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
16371 if (rs6000_overloaded_builtin_p (d
->code
))
16373 if (! (type
= opaque_ftype_opaque
))
16374 type
= opaque_ftype_opaque
16375 = build_function_type_list (opaque_V4SI_type_node
,
16376 opaque_V4SI_type_node
,
16381 enum insn_code icode
= d
->icode
;
16384 if (TARGET_DEBUG_BUILTIN
)
16385 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
16391 if (icode
== CODE_FOR_nothing
)
16393 if (TARGET_DEBUG_BUILTIN
)
16394 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
16400 mode0
= insn_data
[icode
].operand
[0].mode
;
16401 mode1
= insn_data
[icode
].operand
[1].mode
;
16403 if (mode0
== V2SImode
&& mode1
== QImode
)
16405 if (! (type
= v2si_ftype_qi
))
16406 type
= v2si_ftype_qi
16407 = build_function_type_list (opaque_V2SI_type_node
,
16413 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
16417 def_builtin (d
->name
, type
, d
->code
);
16421 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
16423 init_float128_ibm (machine_mode mode
)
16425 if (!TARGET_XL_COMPAT
)
16427 set_optab_libfunc (add_optab
, mode
, "__gcc_qadd");
16428 set_optab_libfunc (sub_optab
, mode
, "__gcc_qsub");
16429 set_optab_libfunc (smul_optab
, mode
, "__gcc_qmul");
16430 set_optab_libfunc (sdiv_optab
, mode
, "__gcc_qdiv");
16432 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
16434 set_optab_libfunc (neg_optab
, mode
, "__gcc_qneg");
16435 set_optab_libfunc (eq_optab
, mode
, "__gcc_qeq");
16436 set_optab_libfunc (ne_optab
, mode
, "__gcc_qne");
16437 set_optab_libfunc (gt_optab
, mode
, "__gcc_qgt");
16438 set_optab_libfunc (ge_optab
, mode
, "__gcc_qge");
16439 set_optab_libfunc (lt_optab
, mode
, "__gcc_qlt");
16440 set_optab_libfunc (le_optab
, mode
, "__gcc_qle");
16442 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__gcc_stoq");
16443 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__gcc_dtoq");
16444 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__gcc_qtos");
16445 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__gcc_qtod");
16446 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__gcc_qtoi");
16447 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__gcc_qtou");
16448 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__gcc_itoq");
16449 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__gcc_utoq");
16452 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
16453 set_optab_libfunc (unord_optab
, mode
, "__gcc_qunord");
16457 set_optab_libfunc (add_optab
, mode
, "_xlqadd");
16458 set_optab_libfunc (sub_optab
, mode
, "_xlqsub");
16459 set_optab_libfunc (smul_optab
, mode
, "_xlqmul");
16460 set_optab_libfunc (sdiv_optab
, mode
, "_xlqdiv");
16463 /* Add various conversions for IFmode to use the traditional TFmode
16465 if (mode
== IFmode
)
16467 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdtf2");
16468 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddtf2");
16469 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctftd2");
16470 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunctfsd2");
16471 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunctfdd2");
16472 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtdtf2");
16474 if (TARGET_POWERPC64
)
16476 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixtfti");
16477 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunstfti");
16478 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattitf");
16479 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntitf");
16484 /* Set up IEEE 128-bit floating point routines. Use different names if the
16485 arguments can be passed in a vector register. The historical PowerPC
16486 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
16487 continue to use that if we aren't using vector registers to pass IEEE
16488 128-bit floating point. */
16491 init_float128_ieee (machine_mode mode
)
16493 if (FLOAT128_VECTOR_P (mode
))
16495 set_optab_libfunc (add_optab
, mode
, "__addkf3");
16496 set_optab_libfunc (sub_optab
, mode
, "__subkf3");
16497 set_optab_libfunc (neg_optab
, mode
, "__negkf2");
16498 set_optab_libfunc (smul_optab
, mode
, "__mulkf3");
16499 set_optab_libfunc (sdiv_optab
, mode
, "__divkf3");
16500 set_optab_libfunc (sqrt_optab
, mode
, "__sqrtkf2");
16501 set_optab_libfunc (abs_optab
, mode
, "__abstkf2");
16503 set_optab_libfunc (eq_optab
, mode
, "__eqkf2");
16504 set_optab_libfunc (ne_optab
, mode
, "__nekf2");
16505 set_optab_libfunc (gt_optab
, mode
, "__gtkf2");
16506 set_optab_libfunc (ge_optab
, mode
, "__gekf2");
16507 set_optab_libfunc (lt_optab
, mode
, "__ltkf2");
16508 set_optab_libfunc (le_optab
, mode
, "__lekf2");
16509 set_optab_libfunc (unord_optab
, mode
, "__unordkf2");
16511 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__extendsfkf2");
16512 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__extenddfkf2");
16513 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__trunckfsf2");
16514 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__trunckfdf2");
16516 set_conv_libfunc (sext_optab
, mode
, IFmode
, "__extendtfkf2");
16517 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
16518 set_conv_libfunc (sext_optab
, mode
, TFmode
, "__extendtfkf2");
16520 set_conv_libfunc (trunc_optab
, IFmode
, mode
, "__trunckftf2");
16521 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
16522 set_conv_libfunc (trunc_optab
, TFmode
, mode
, "__trunckftf2");
16524 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdkf2");
16525 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddkf2");
16526 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunckftd2");
16527 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunckfsd2");
16528 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunckfdd2");
16529 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtdkf2");
16531 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__fixkfsi");
16532 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__fixunskfsi");
16533 set_conv_libfunc (sfix_optab
, DImode
, mode
, "__fixkfdi");
16534 set_conv_libfunc (ufix_optab
, DImode
, mode
, "__fixunskfdi");
16536 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__floatsikf");
16537 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__floatunsikf");
16538 set_conv_libfunc (sfloat_optab
, mode
, DImode
, "__floatdikf");
16539 set_conv_libfunc (ufloat_optab
, mode
, DImode
, "__floatundikf");
16541 if (TARGET_POWERPC64
)
16543 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixkfti");
16544 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunskfti");
16545 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattikf");
16546 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntikf");
16552 set_optab_libfunc (add_optab
, mode
, "_q_add");
16553 set_optab_libfunc (sub_optab
, mode
, "_q_sub");
16554 set_optab_libfunc (neg_optab
, mode
, "_q_neg");
16555 set_optab_libfunc (smul_optab
, mode
, "_q_mul");
16556 set_optab_libfunc (sdiv_optab
, mode
, "_q_div");
16557 if (TARGET_PPC_GPOPT
)
16558 set_optab_libfunc (sqrt_optab
, mode
, "_q_sqrt");
16560 set_optab_libfunc (eq_optab
, mode
, "_q_feq");
16561 set_optab_libfunc (ne_optab
, mode
, "_q_fne");
16562 set_optab_libfunc (gt_optab
, mode
, "_q_fgt");
16563 set_optab_libfunc (ge_optab
, mode
, "_q_fge");
16564 set_optab_libfunc (lt_optab
, mode
, "_q_flt");
16565 set_optab_libfunc (le_optab
, mode
, "_q_fle");
16567 set_conv_libfunc (sext_optab
, mode
, SFmode
, "_q_stoq");
16568 set_conv_libfunc (sext_optab
, mode
, DFmode
, "_q_dtoq");
16569 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "_q_qtos");
16570 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "_q_qtod");
16571 set_conv_libfunc (sfix_optab
, SImode
, mode
, "_q_qtoi");
16572 set_conv_libfunc (ufix_optab
, SImode
, mode
, "_q_qtou");
16573 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "_q_itoq");
16574 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "_q_utoq");
16579 rs6000_init_libfuncs (void)
16581 /* __float128 support. */
16582 if (TARGET_FLOAT128
)
16584 init_float128_ibm (IFmode
);
16585 init_float128_ieee (KFmode
);
16588 /* AIX/Darwin/64-bit Linux quad floating point routines. */
16589 if (TARGET_LONG_DOUBLE_128
)
16591 if (!TARGET_IEEEQUAD
)
16592 init_float128_ibm (TFmode
);
16594 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
16596 init_float128_ieee (TFmode
);
16601 /* Expand a block clear operation, and return 1 if successful. Return 0
16602 if we should let the compiler generate normal code.
16604 operands[0] is the destination
16605 operands[1] is the length
16606 operands[3] is the alignment */
16609 expand_block_clear (rtx operands
[])
16611 rtx orig_dest
= operands
[0];
16612 rtx bytes_rtx
= operands
[1];
16613 rtx align_rtx
= operands
[3];
16614 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
16615 HOST_WIDE_INT align
;
16616 HOST_WIDE_INT bytes
;
16621 /* If this is not a fixed size move, just call memcpy */
16625 /* This must be a fixed size alignment */
16626 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
16627 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
16629 /* Anything to clear? */
16630 bytes
= INTVAL (bytes_rtx
);
16634 /* Use the builtin memset after a point, to avoid huge code bloat.
16635 When optimize_size, avoid any significant code bloat; calling
16636 memset is about 4 instructions, so allow for one instruction to
16637 load zero and three to do clearing. */
16638 if (TARGET_ALTIVEC
&& align
>= 128)
16640 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
16642 else if (TARGET_SPE
&& align
>= 64)
16647 if (optimize_size
&& bytes
> 3 * clear_step
)
16649 if (! optimize_size
&& bytes
> 8 * clear_step
)
16652 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
16654 machine_mode mode
= BLKmode
;
16657 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
16662 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
16667 else if (bytes
>= 8 && TARGET_POWERPC64
16668 && (align
>= 64 || !STRICT_ALIGNMENT
))
16672 if (offset
== 0 && align
< 64)
16676 /* If the address form is reg+offset with offset not a
16677 multiple of four, reload into reg indirect form here
16678 rather than waiting for reload. This way we get one
16679 reload, not one per store. */
16680 addr
= XEXP (orig_dest
, 0);
16681 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16682 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16683 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16685 addr
= copy_addr_to_reg (addr
);
16686 orig_dest
= replace_equiv_address (orig_dest
, addr
);
16690 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
16691 { /* move 4 bytes */
16695 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
16696 { /* move 2 bytes */
16700 else /* move 1 byte at a time */
16706 dest
= adjust_address (orig_dest
, mode
, offset
);
16708 emit_move_insn (dest
, CONST0_RTX (mode
));
16715 /* Expand a block move operation, and return 1 if successful. Return 0
16716 if we should let the compiler generate normal code.
16718 operands[0] is the destination
16719 operands[1] is the source
16720 operands[2] is the length
16721 operands[3] is the alignment */
16723 #define MAX_MOVE_REG 4
16726 expand_block_move (rtx operands
[])
16728 rtx orig_dest
= operands
[0];
16729 rtx orig_src
= operands
[1];
16730 rtx bytes_rtx
= operands
[2];
16731 rtx align_rtx
= operands
[3];
16732 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
16737 rtx stores
[MAX_MOVE_REG
];
16740 /* If this is not a fixed size move, just call memcpy */
16744 /* This must be a fixed size alignment */
16745 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
16746 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
16748 /* Anything to move? */
16749 bytes
= INTVAL (bytes_rtx
);
16753 if (bytes
> rs6000_block_move_inline_limit
)
16756 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
16759 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
16760 rtx (*mov
) (rtx
, rtx
);
16762 machine_mode mode
= BLKmode
;
16765 /* Altivec first, since it will be faster than a string move
16766 when it applies, and usually not significantly larger. */
16767 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
16771 gen_func
.mov
= gen_movv4si
;
16773 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
16777 gen_func
.mov
= gen_movv2si
;
16779 else if (TARGET_STRING
16780 && bytes
> 24 /* move up to 32 bytes at a time */
16786 && ! fixed_regs
[10]
16787 && ! fixed_regs
[11]
16788 && ! fixed_regs
[12])
16790 move_bytes
= (bytes
> 32) ? 32 : bytes
;
16791 gen_func
.movmemsi
= gen_movmemsi_8reg
;
16793 else if (TARGET_STRING
16794 && bytes
> 16 /* move up to 24 bytes at a time */
16800 && ! fixed_regs
[10])
16802 move_bytes
= (bytes
> 24) ? 24 : bytes
;
16803 gen_func
.movmemsi
= gen_movmemsi_6reg
;
16805 else if (TARGET_STRING
16806 && bytes
> 8 /* move up to 16 bytes at a time */
16810 && ! fixed_regs
[8])
16812 move_bytes
= (bytes
> 16) ? 16 : bytes
;
16813 gen_func
.movmemsi
= gen_movmemsi_4reg
;
16815 else if (bytes
>= 8 && TARGET_POWERPC64
16816 && (align
>= 64 || !STRICT_ALIGNMENT
))
16820 gen_func
.mov
= gen_movdi
;
16821 if (offset
== 0 && align
< 64)
16825 /* If the address form is reg+offset with offset not a
16826 multiple of four, reload into reg indirect form here
16827 rather than waiting for reload. This way we get one
16828 reload, not one per load and/or store. */
16829 addr
= XEXP (orig_dest
, 0);
16830 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16831 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16832 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16834 addr
= copy_addr_to_reg (addr
);
16835 orig_dest
= replace_equiv_address (orig_dest
, addr
);
16837 addr
= XEXP (orig_src
, 0);
16838 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16839 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16840 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16842 addr
= copy_addr_to_reg (addr
);
16843 orig_src
= replace_equiv_address (orig_src
, addr
);
16847 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
16848 { /* move up to 8 bytes at a time */
16849 move_bytes
= (bytes
> 8) ? 8 : bytes
;
16850 gen_func
.movmemsi
= gen_movmemsi_2reg
;
16852 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
16853 { /* move 4 bytes */
16856 gen_func
.mov
= gen_movsi
;
16858 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
16859 { /* move 2 bytes */
16862 gen_func
.mov
= gen_movhi
;
16864 else if (TARGET_STRING
&& bytes
> 1)
16865 { /* move up to 4 bytes at a time */
16866 move_bytes
= (bytes
> 4) ? 4 : bytes
;
16867 gen_func
.movmemsi
= gen_movmemsi_1reg
;
16869 else /* move 1 byte at a time */
16873 gen_func
.mov
= gen_movqi
;
16876 src
= adjust_address (orig_src
, mode
, offset
);
16877 dest
= adjust_address (orig_dest
, mode
, offset
);
16879 if (mode
!= BLKmode
)
16881 rtx tmp_reg
= gen_reg_rtx (mode
);
16883 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
16884 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
16887 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
16890 for (i
= 0; i
< num_reg
; i
++)
16891 emit_insn (stores
[i
]);
16895 if (mode
== BLKmode
)
16897 /* Move the address into scratch registers. The movmemsi
16898 patterns require zero offset. */
16899 if (!REG_P (XEXP (src
, 0)))
16901 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
16902 src
= replace_equiv_address (src
, src_reg
);
16904 set_mem_size (src
, move_bytes
);
16906 if (!REG_P (XEXP (dest
, 0)))
16908 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
16909 dest
= replace_equiv_address (dest
, dest_reg
);
16911 set_mem_size (dest
, move_bytes
);
16913 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
16914 GEN_INT (move_bytes
& 31),
16923 /* Return a string to perform a load_multiple operation.
16924 operands[0] is the vector.
16925 operands[1] is the source address.
16926 operands[2] is the first destination register. */
16929 rs6000_output_load_multiple (rtx operands
[3])
16931 /* We have to handle the case where the pseudo used to contain the address
16932 is assigned to one of the output registers. */
16934 int words
= XVECLEN (operands
[0], 0);
16937 if (XVECLEN (operands
[0], 0) == 1)
16938 return "lwz %2,0(%1)";
16940 for (i
= 0; i
< words
; i
++)
16941 if (refers_to_regno_p (REGNO (operands
[2]) + i
, operands
[1]))
16945 xop
[0] = GEN_INT (4 * (words
-1));
16946 xop
[1] = operands
[1];
16947 xop
[2] = operands
[2];
16948 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
16953 xop
[0] = GEN_INT (4 * (words
-1));
16954 xop
[1] = operands
[1];
16955 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16956 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
16961 for (j
= 0; j
< words
; j
++)
16964 xop
[0] = GEN_INT (j
* 4);
16965 xop
[1] = operands
[1];
16966 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
16967 output_asm_insn ("lwz %2,%0(%1)", xop
);
16969 xop
[0] = GEN_INT (i
* 4);
16970 xop
[1] = operands
[1];
16971 output_asm_insn ("lwz %1,%0(%1)", xop
);
16976 return "lswi %2,%1,%N0";
16980 /* A validation routine: say whether CODE, a condition code, and MODE
16981 match. The other alternatives either don't make sense or should
16982 never be generated. */
16985 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
16987 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
16988 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
16989 && GET_MODE_CLASS (mode
) == MODE_CC
);
16991 /* These don't make sense. */
16992 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
16993 || mode
!= CCUNSmode
);
16995 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
16996 || mode
== CCUNSmode
);
16998 gcc_assert (mode
== CCFPmode
16999 || (code
!= ORDERED
&& code
!= UNORDERED
17000 && code
!= UNEQ
&& code
!= LTGT
17001 && code
!= UNGT
&& code
!= UNLT
17002 && code
!= UNGE
&& code
!= UNLE
));
17004 /* These should never be generated except for
17005 flag_finite_math_only. */
17006 gcc_assert (mode
!= CCFPmode
17007 || flag_finite_math_only
17008 || (code
!= LE
&& code
!= GE
17009 && code
!= UNEQ
&& code
!= LTGT
17010 && code
!= UNGT
&& code
!= UNLT
));
17012 /* These are invalid; the information is not there. */
17013 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
17017 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
17018 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
17019 not zero, store there the bit offset (counted from the right) where
17020 the single stretch of 1 bits begins; and similarly for B, the bit
17021 offset where it ends. */
17024 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
17026 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
17027 unsigned HOST_WIDE_INT bit
;
17029 int n
= GET_MODE_PRECISION (mode
);
17031 if (mode
!= DImode
&& mode
!= SImode
)
17034 if (INTVAL (mask
) >= 0)
17037 ne
= exact_log2 (bit
);
17038 nb
= exact_log2 (val
+ bit
);
17040 else if (val
+ 1 == 0)
17049 nb
= exact_log2 (bit
);
17050 ne
= exact_log2 (val
+ bit
);
17055 ne
= exact_log2 (bit
);
17056 if (val
+ bit
== 0)
17064 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
17075 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
17076 or rldicr instruction, to implement an AND with it in mode MODE. */
17079 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
17083 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
17086 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
17088 if (mode
== DImode
)
17089 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
17091 /* For SImode, rlwinm can do everything. */
17092 if (mode
== SImode
)
17093 return (nb
< 32 && ne
< 32);
17098 /* Return the instruction template for an AND with mask in mode MODE, with
17099 operands OPERANDS. If DOT is true, make it a record-form instruction. */
17102 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
17106 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
17107 gcc_unreachable ();
17109 if (mode
== DImode
&& ne
== 0)
17111 operands
[3] = GEN_INT (63 - nb
);
17113 return "rldicl. %0,%1,0,%3";
17114 return "rldicl %0,%1,0,%3";
17117 if (mode
== DImode
&& nb
== 63)
17119 operands
[3] = GEN_INT (63 - ne
);
17121 return "rldicr. %0,%1,0,%3";
17122 return "rldicr %0,%1,0,%3";
17125 if (nb
< 32 && ne
< 32)
17127 operands
[3] = GEN_INT (31 - nb
);
17128 operands
[4] = GEN_INT (31 - ne
);
17130 return "rlwinm. %0,%1,0,%3,%4";
17131 return "rlwinm %0,%1,0,%3,%4";
17134 gcc_unreachable ();
17137 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
17138 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
17139 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
17142 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
17146 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
17149 int n
= GET_MODE_PRECISION (mode
);
17152 if (CONST_INT_P (XEXP (shift
, 1)))
17154 sh
= INTVAL (XEXP (shift
, 1));
17155 if (sh
< 0 || sh
>= n
)
17159 rtx_code code
= GET_CODE (shift
);
17161 /* Convert any shift by 0 to a rotate, to simplify below code. */
17165 /* Convert rotate to simple shift if we can, to make analysis simpler. */
17166 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
17168 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
17174 /* DImode rotates need rld*. */
17175 if (mode
== DImode
&& code
== ROTATE
)
17176 return (nb
== 63 || ne
== 0 || ne
== sh
);
17178 /* SImode rotates need rlw*. */
17179 if (mode
== SImode
&& code
== ROTATE
)
17180 return (nb
< 32 && ne
< 32 && sh
< 32);
17182 /* Wrap-around masks are only okay for rotates. */
17186 /* Variable shifts are only okay for rotates. */
17190 /* Don't allow ASHIFT if the mask is wrong for that. */
17191 if (code
== ASHIFT
&& ne
< sh
)
17194 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
17195 if the mask is wrong for that. */
17196 if (nb
< 32 && ne
< 32 && sh
< 32
17197 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
17200 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
17201 if the mask is wrong for that. */
17202 if (code
== LSHIFTRT
)
17204 if (nb
== 63 || ne
== 0 || ne
== sh
)
17205 return !(code
== LSHIFTRT
&& nb
>= sh
);
17210 /* Return the instruction template for a shift with mask in mode MODE, with
17211 operands OPERANDS. If DOT is true, make it a record-form instruction. */
17214 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
17218 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
17219 gcc_unreachable ();
17221 if (mode
== DImode
&& ne
== 0)
17223 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
17224 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
17225 operands
[3] = GEN_INT (63 - nb
);
17227 return "rld%I2cl. %0,%1,%2,%3";
17228 return "rld%I2cl %0,%1,%2,%3";
17231 if (mode
== DImode
&& nb
== 63)
17233 operands
[3] = GEN_INT (63 - ne
);
17235 return "rld%I2cr. %0,%1,%2,%3";
17236 return "rld%I2cr %0,%1,%2,%3";
17240 && GET_CODE (operands
[4]) != LSHIFTRT
17241 && CONST_INT_P (operands
[2])
17242 && ne
== INTVAL (operands
[2]))
17244 operands
[3] = GEN_INT (63 - nb
);
17246 return "rld%I2c. %0,%1,%2,%3";
17247 return "rld%I2c %0,%1,%2,%3";
17250 if (nb
< 32 && ne
< 32)
17252 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
17253 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
17254 operands
[3] = GEN_INT (31 - nb
);
17255 operands
[4] = GEN_INT (31 - ne
);
17257 return "rlw%I2nm. %0,%1,%2,%3,%4";
17258 return "rlw%I2nm %0,%1,%2,%3,%4";
17261 gcc_unreachable ();
17264 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
17265 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
17266 ASHIFT, or LSHIFTRT) in mode MODE. */
17269 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
17273 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
17276 int n
= GET_MODE_PRECISION (mode
);
17278 int sh
= INTVAL (XEXP (shift
, 1));
17279 if (sh
< 0 || sh
>= n
)
17282 rtx_code code
= GET_CODE (shift
);
17284 /* Convert any shift by 0 to a rotate, to simplify below code. */
17288 /* Convert rotate to simple shift if we can, to make analysis simpler. */
17289 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
17291 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
17297 /* DImode rotates need rldimi. */
17298 if (mode
== DImode
&& code
== ROTATE
)
17301 /* SImode rotates need rlwimi. */
17302 if (mode
== SImode
&& code
== ROTATE
)
17303 return (nb
< 32 && ne
< 32 && sh
< 32);
17305 /* Wrap-around masks are only okay for rotates. */
17309 /* Don't allow ASHIFT if the mask is wrong for that. */
17310 if (code
== ASHIFT
&& ne
< sh
)
17313 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
17314 if the mask is wrong for that. */
17315 if (nb
< 32 && ne
< 32 && sh
< 32
17316 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
17319 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
17320 if the mask is wrong for that. */
17321 if (code
== LSHIFTRT
)
17324 return !(code
== LSHIFTRT
&& nb
>= sh
);
17329 /* Return the instruction template for an insert with mask in mode MODE, with
17330 operands OPERANDS. If DOT is true, make it a record-form instruction. */
17333 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
17337 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
17338 gcc_unreachable ();
17340 /* Prefer rldimi because rlwimi is cracked. */
17341 if (TARGET_POWERPC64
17342 && (!dot
|| mode
== DImode
)
17343 && GET_CODE (operands
[4]) != LSHIFTRT
17344 && ne
== INTVAL (operands
[2]))
17346 operands
[3] = GEN_INT (63 - nb
);
17348 return "rldimi. %0,%1,%2,%3";
17349 return "rldimi %0,%1,%2,%3";
17352 if (nb
< 32 && ne
< 32)
17354 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
17355 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
17356 operands
[3] = GEN_INT (31 - nb
);
17357 operands
[4] = GEN_INT (31 - ne
);
17359 return "rlwimi. %0,%1,%2,%3,%4";
17360 return "rlwimi %0,%1,%2,%3,%4";
17363 gcc_unreachable ();
17366 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
17367 using two machine instructions. */
17370 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
17372 /* There are two kinds of AND we can handle with two insns:
17373 1) those we can do with two rl* insn;
17376 We do not handle that last case yet. */
17378 /* If there is just one stretch of ones, we can do it. */
17379 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
17382 /* Otherwise, fill in the lowest "hole"; if we can do the result with
17383 one insn, we can do the whole thing with two. */
17384 unsigned HOST_WIDE_INT val
= INTVAL (c
);
17385 unsigned HOST_WIDE_INT bit1
= val
& -val
;
17386 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
17387 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
17388 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
17389 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
17392 /* Emit a potentially record-form instruction, setting DST from SRC.
17393 If DOT is 0, that is all; otherwise, set CCREG to the result of the
17394 signed comparison of DST with zero. If DOT is 1, the generated RTL
17395 doesn't care about the DST result; if DOT is 2, it does. If CCREG
17396 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
17397 a separate COMPARE. */
17400 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
17404 emit_move_insn (dst
, src
);
17408 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
17410 emit_move_insn (dst
, src
);
17411 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
17415 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
17418 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
17419 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
17423 rtx set
= gen_rtx_SET (dst
, src
);
17424 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
17428 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
17429 If EXPAND is true, split rotate-and-mask instructions we generate to
17430 their constituent parts as well (this is used during expand); if DOT
17431 is 1, make the last insn a record-form instruction clobbering the
17432 destination GPR and setting the CC reg (from operands[3]); if 2, set
17433 that GPR as well as the CC reg. */
17436 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
17438 gcc_assert (!(expand
&& dot
));
17440 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
17442 /* If it is one stretch of ones, it is DImode; shift left, mask, then
17443 shift right. This generates better code than doing the masks without
17444 shifts, or shifting first right and then left. */
17446 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
17448 gcc_assert (mode
== DImode
);
17450 int shift
= 63 - nb
;
17453 rtx tmp1
= gen_reg_rtx (DImode
);
17454 rtx tmp2
= gen_reg_rtx (DImode
);
17455 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
17456 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
17457 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
17461 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
17462 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
17463 emit_move_insn (operands
[0], tmp
);
17464 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
17465 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
17470 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
17471 that does the rest. */
17472 unsigned HOST_WIDE_INT bit1
= val
& -val
;
17473 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
17474 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
17475 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
17477 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
17478 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
17480 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
17482 /* Two "no-rotate"-and-mask instructions, for SImode. */
17483 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
17485 gcc_assert (mode
== SImode
);
17487 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
17488 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
17489 emit_move_insn (reg
, tmp
);
17490 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
17491 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
17495 gcc_assert (mode
== DImode
);
17497 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
17498 insns; we have to do the first in SImode, because it wraps. */
17499 if (mask2
<= 0xffffffff
17500 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
17502 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
17503 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
17505 rtx reg_low
= gen_lowpart (SImode
, reg
);
17506 emit_move_insn (reg_low
, tmp
);
17507 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
17508 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
17512 /* Two rld* insns: rotate, clear the hole in the middle (which now is
17513 at the top end), rotate back and clear the other hole. */
17514 int right
= exact_log2 (bit3
);
17515 int left
= 64 - right
;
17517 /* Rotate the mask too. */
17518 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
17522 rtx tmp1
= gen_reg_rtx (DImode
);
17523 rtx tmp2
= gen_reg_rtx (DImode
);
17524 rtx tmp3
= gen_reg_rtx (DImode
);
17525 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
17526 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
17527 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
17528 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
17532 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
17533 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
17534 emit_move_insn (operands
[0], tmp
);
17535 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
17536 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
17537 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
17541 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
17542 for lfq and stfq insns iff the registers are hard registers. */
17545 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
17547 /* We might have been passed a SUBREG. */
17548 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
17551 /* We might have been passed non floating point registers. */
17552 if (!FP_REGNO_P (REGNO (reg1
))
17553 || !FP_REGNO_P (REGNO (reg2
)))
17556 return (REGNO (reg1
) == REGNO (reg2
) - 1);
17559 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
17560 addr1 and addr2 must be in consecutive memory locations
17561 (addr2 == addr1 + 8). */
17564 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
17567 unsigned int reg1
, reg2
;
17568 int offset1
, offset2
;
17570 /* The mems cannot be volatile. */
17571 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
17574 addr1
= XEXP (mem1
, 0);
17575 addr2
= XEXP (mem2
, 0);
17577 /* Extract an offset (if used) from the first addr. */
17578 if (GET_CODE (addr1
) == PLUS
)
17580 /* If not a REG, return zero. */
17581 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
17585 reg1
= REGNO (XEXP (addr1
, 0));
17586 /* The offset must be constant! */
17587 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
17589 offset1
= INTVAL (XEXP (addr1
, 1));
17592 else if (GET_CODE (addr1
) != REG
)
17596 reg1
= REGNO (addr1
);
17597 /* This was a simple (mem (reg)) expression. Offset is 0. */
17601 /* And now for the second addr. */
17602 if (GET_CODE (addr2
) == PLUS
)
17604 /* If not a REG, return zero. */
17605 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
17609 reg2
= REGNO (XEXP (addr2
, 0));
17610 /* The offset must be constant. */
17611 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
17613 offset2
= INTVAL (XEXP (addr2
, 1));
17616 else if (GET_CODE (addr2
) != REG
)
17620 reg2
= REGNO (addr2
);
17621 /* This was a simple (mem (reg)) expression. Offset is 0. */
17625 /* Both of these must have the same base register. */
17629 /* The offset for the second addr must be 8 more than the first addr. */
17630 if (offset2
!= offset1
+ 8)
17633 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
17640 rs6000_secondary_memory_needed_rtx (machine_mode mode
)
17642 static bool eliminated
= false;
17645 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
17646 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
17649 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
17650 gcc_assert (mem
!= NULL_RTX
);
17654 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
17655 cfun
->machine
->sdmode_stack_slot
= mem
;
17661 if (TARGET_DEBUG_ADDR
)
17663 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
17664 GET_MODE_NAME (mode
));
17666 fprintf (stderr
, "\tNULL_RTX\n");
17674 /* Return the mode to be used for memory when a secondary memory
17675 location is needed. For SDmode values we need to use DDmode, in
17676 all other cases we can use the same mode. */
17678 rs6000_secondary_memory_needed_mode (machine_mode mode
)
17680 if (lra_in_progress
&& mode
== SDmode
)
17686 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
17688 /* Don't walk into types. */
17689 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
17691 *walk_subtrees
= 0;
17695 switch (TREE_CODE (*tp
))
17704 case VIEW_CONVERT_EXPR
:
17705 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
17715 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
17716 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
17717 only work on the traditional altivec registers, note if an altivec register
17720 static enum rs6000_reg_type
17721 register_to_reg_type (rtx reg
, bool *is_altivec
)
17723 HOST_WIDE_INT regno
;
17724 enum reg_class rclass
;
17726 if (GET_CODE (reg
) == SUBREG
)
17727 reg
= SUBREG_REG (reg
);
17730 return NO_REG_TYPE
;
17732 regno
= REGNO (reg
);
17733 if (regno
>= FIRST_PSEUDO_REGISTER
)
17735 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
17736 return PSEUDO_REG_TYPE
;
17738 regno
= true_regnum (reg
);
17739 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
17740 return PSEUDO_REG_TYPE
;
17743 gcc_assert (regno
>= 0);
17745 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
17746 *is_altivec
= true;
17748 rclass
= rs6000_regno_regclass
[regno
];
17749 return reg_class_to_reg_type
[(int)rclass
];
17752 /* Helper function to return the cost of adding a TOC entry address. */
17755 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
17759 if (TARGET_CMODEL
!= CMODEL_SMALL
)
17760 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
17763 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
17768 /* Helper function for rs6000_secondary_reload to determine whether the memory
17769 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
17770 needs reloading. Return negative if the memory is not handled by the memory
17771 helper functions and to try a different reload method, 0 if no additional
17772 instructions are need, and positive to give the extra cost for the
17776 rs6000_secondary_reload_memory (rtx addr
,
17777 enum reg_class rclass
,
17780 int extra_cost
= 0;
17781 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
17782 addr_mask_type addr_mask
;
17783 const char *type
= NULL
;
17784 const char *fail_msg
= NULL
;
17786 if (GPR_REG_CLASS_P (rclass
))
17787 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
17789 else if (rclass
== FLOAT_REGS
)
17790 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
17792 else if (rclass
== ALTIVEC_REGS
)
17793 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
17795 /* For the combined VSX_REGS, turn off Altivec AND -16. */
17796 else if (rclass
== VSX_REGS
)
17797 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
17798 & ~RELOAD_REG_AND_M16
);
17802 if (TARGET_DEBUG_ADDR
)
17804 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
17805 "class is not GPR, FPR, VMX\n",
17806 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
17811 /* If the register isn't valid in this register class, just return now. */
17812 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
17814 if (TARGET_DEBUG_ADDR
)
17816 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
17817 "not valid in class\n",
17818 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
17823 switch (GET_CODE (addr
))
17825 /* Does the register class supports auto update forms for this mode? We
17826 don't need a scratch register, since the powerpc only supports
17827 PRE_INC, PRE_DEC, and PRE_MODIFY. */
17830 reg
= XEXP (addr
, 0);
17831 if (!base_reg_operand (addr
, GET_MODE (reg
)))
17833 fail_msg
= "no base register #1";
17837 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
17845 reg
= XEXP (addr
, 0);
17846 plus_arg1
= XEXP (addr
, 1);
17847 if (!base_reg_operand (reg
, GET_MODE (reg
))
17848 || GET_CODE (plus_arg1
) != PLUS
17849 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
17851 fail_msg
= "bad PRE_MODIFY";
17855 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
17862 /* Do we need to simulate AND -16 to clear the bottom address bits used
17863 in VMX load/stores? Only allow the AND for vector sizes. */
17865 and_arg
= XEXP (addr
, 0);
17866 if (GET_MODE_SIZE (mode
) != 16
17867 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
17868 || INTVAL (XEXP (addr
, 1)) != -16)
17870 fail_msg
= "bad Altivec AND #1";
17874 if (rclass
!= ALTIVEC_REGS
)
17876 if (legitimate_indirect_address_p (and_arg
, false))
17879 else if (legitimate_indexed_address_p (and_arg
, false))
17884 fail_msg
= "bad Altivec AND #2";
17892 /* If this is an indirect address, make sure it is a base register. */
17895 if (!legitimate_indirect_address_p (addr
, false))
17902 /* If this is an indexed address, make sure the register class can handle
17903 indexed addresses for this mode. */
17905 plus_arg0
= XEXP (addr
, 0);
17906 plus_arg1
= XEXP (addr
, 1);
17908 /* (plus (plus (reg) (constant)) (constant)) is generated during
17909 push_reload processing, so handle it now. */
17910 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
17912 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17919 /* (plus (plus (reg) (constant)) (reg)) is also generated during
17920 push_reload processing, so handle it now. */
17921 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
17923 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
17926 type
= "indexed #2";
17930 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
17932 fail_msg
= "no base register #2";
17936 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
17938 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
17939 || !legitimate_indexed_address_p (addr
, false))
17946 /* Make sure the register class can handle offset addresses. */
17947 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
17949 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17958 fail_msg
= "bad PLUS";
17965 if (!legitimate_lo_sum_address_p (mode
, addr
, false))
17967 fail_msg
= "bad LO_SUM";
17971 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17978 /* Static addresses need to create a TOC entry. */
17983 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
17986 /* TOC references look like offsetable memory. */
17988 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
17990 fail_msg
= "bad UNSPEC";
17994 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17997 type
= "toc reference";
18003 fail_msg
= "bad address";
18008 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
18010 if (extra_cost
< 0)
18012 "rs6000_secondary_reload_memory error: mode = %s, "
18013 "class = %s, addr_mask = '%s', %s\n",
18014 GET_MODE_NAME (mode
),
18015 reg_class_names
[rclass
],
18016 rs6000_debug_addr_mask (addr_mask
, false),
18017 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
18021 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18022 "addr_mask = '%s', extra cost = %d, %s\n",
18023 GET_MODE_NAME (mode
),
18024 reg_class_names
[rclass
],
18025 rs6000_debug_addr_mask (addr_mask
, false),
18027 (type
) ? type
: "<none>");
18035 /* Helper function for rs6000_secondary_reload to return true if a move to a
18036 different register classe is really a simple move. */
18039 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
18040 enum rs6000_reg_type from_type
,
18045 /* Add support for various direct moves available. In this function, we only
18046 look at cases where we don't need any extra registers, and one or more
18047 simple move insns are issued. At present, 32-bit integers are not allowed
18048 in FPR/VSX registers. Single precision binary floating is not a simple
18049 move because we need to convert to the single precision memory layout.
18050 The 4-byte SDmode can be moved. */
18051 size
= GET_MODE_SIZE (mode
);
18052 if (TARGET_DIRECT_MOVE
18053 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
18054 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
18055 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
18058 else if (TARGET_DIRECT_MOVE_128
&& size
== 16
18059 && ((to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
18060 || (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)))
18063 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
18064 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
18065 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
18068 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
18069 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
18070 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
18076 /* Direct move helper function for rs6000_secondary_reload, handle all of the
18077 special direct moves that involve allocating an extra register, return the
18078 insn code of the helper function if there is such a function or
18079 CODE_FOR_nothing if not. */
18082 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
18083 enum rs6000_reg_type from_type
,
18085 secondary_reload_info
*sri
,
18089 enum insn_code icode
= CODE_FOR_nothing
;
18091 int size
= GET_MODE_SIZE (mode
);
18093 if (TARGET_POWERPC64
)
18097 /* Handle moving 128-bit values from GPRs to VSX point registers on
18098 ISA 2.07 (power8, power9) when running in 64-bit mode using
18099 XXPERMDI to glue the two 64-bit values back together. */
18100 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
18102 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
18103 icode
= reg_addr
[mode
].reload_vsx_gpr
;
18106 /* Handle moving 128-bit values from VSX point registers to GPRs on
18107 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
18108 bottom 64-bit value. */
18109 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
18111 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
18112 icode
= reg_addr
[mode
].reload_gpr_vsx
;
18116 else if (mode
== SFmode
)
18118 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
18120 cost
= 3; /* xscvdpspn, mfvsrd, and. */
18121 icode
= reg_addr
[mode
].reload_gpr_vsx
;
18124 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
18126 cost
= 2; /* mtvsrz, xscvspdpn. */
18127 icode
= reg_addr
[mode
].reload_vsx_gpr
;
18132 if (TARGET_POWERPC64
&& size
== 16)
18134 /* Handle moving 128-bit values from GPRs to VSX point registers on
18135 ISA 2.07 when running in 64-bit mode using XXPERMDI to glue the two
18136 64-bit values back together. */
18137 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
18139 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
18140 icode
= reg_addr
[mode
].reload_vsx_gpr
;
18143 /* Handle moving 128-bit values from VSX point registers to GPRs on
18144 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
18145 bottom 64-bit value. */
18146 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
18148 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
18149 icode
= reg_addr
[mode
].reload_gpr_vsx
;
18153 else if (!TARGET_POWERPC64
&& size
== 8)
18155 /* Handle moving 64-bit values from GPRs to floating point registers on
18156 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
18157 32-bit values back together. Altivec register classes must be handled
18158 specially since a different instruction is used, and the secondary
18159 reload support requires a single instruction class in the scratch
18160 register constraint. However, right now TFmode is not allowed in
18161 Altivec registers, so the pattern will never match. */
18162 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
18164 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
18165 icode
= reg_addr
[mode
].reload_fpr_gpr
;
18169 if (icode
!= CODE_FOR_nothing
)
18174 sri
->icode
= icode
;
18175 sri
->extra_cost
= cost
;
18182 /* Return whether a move between two register classes can be done either
18183 directly (simple move) or via a pattern that uses a single extra temporary
18184 (using ISA 2.07's direct move in this case. */
18187 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
18188 enum rs6000_reg_type from_type
,
18190 secondary_reload_info
*sri
,
18193 /* Fall back to load/store reloads if either type is not a register. */
18194 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
18197 /* If we haven't allocated registers yet, assume the move can be done for the
18198 standard register types. */
18199 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
18200 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
18201 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
18204 /* Moves to the same set of registers is a simple move for non-specialized
18206 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
18209 /* Check whether a simple move can be done directly. */
18210 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
18214 sri
->icode
= CODE_FOR_nothing
;
18215 sri
->extra_cost
= 0;
18220 /* Now check if we can do it in a few steps. */
18221 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
18225 /* Inform reload about cases where moving X with a mode MODE to a register in
18226 RCLASS requires an extra scratch or immediate register. Return the class
18227 needed for the immediate register.
18229 For VSX and Altivec, we may need a register to convert sp+offset into
18232 For misaligned 64-bit gpr loads and stores we need a register to
18233 convert an offset address to indirect. */
18236 rs6000_secondary_reload (bool in_p
,
18238 reg_class_t rclass_i
,
18240 secondary_reload_info
*sri
)
18242 enum reg_class rclass
= (enum reg_class
) rclass_i
;
18243 reg_class_t ret
= ALL_REGS
;
18244 enum insn_code icode
;
18245 bool default_p
= false;
18246 bool done_p
= false;
18248 /* Allow subreg of memory before/during reload. */
18249 bool memory_p
= (MEM_P (x
)
18250 || (!reload_completed
&& GET_CODE (x
) == SUBREG
18251 && MEM_P (SUBREG_REG (x
))));
18253 sri
->icode
= CODE_FOR_nothing
;
18254 sri
->extra_cost
= 0;
18256 ? reg_addr
[mode
].reload_load
18257 : reg_addr
[mode
].reload_store
);
18259 if (REG_P (x
) || register_operand (x
, mode
))
18261 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
18262 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
18263 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
18267 enum rs6000_reg_type exchange
= to_type
;
18268 to_type
= from_type
;
18269 from_type
= exchange
;
18272 /* Can we do a direct move of some sort? */
18273 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
18276 icode
= (enum insn_code
)sri
->icode
;
18283 /* Make sure 0.0 is not reloaded or forced into memory. */
18284 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
18291 /* If this is a scalar floating point value and we want to load it into the
18292 traditional Altivec registers, do it via a move via a traditional floating
18293 point register, unless we have D-form addressing. Also make sure that
18294 non-zero constants use a FPR. */
18295 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
18296 && !mode_supports_vmx_dform (mode
)
18297 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
18298 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
18305 /* Handle reload of load/stores if we have reload helper functions. */
18306 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
18308 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
18311 if (extra_cost
>= 0)
18315 if (extra_cost
> 0)
18317 sri
->extra_cost
= extra_cost
;
18318 sri
->icode
= icode
;
18323 /* Handle unaligned loads and stores of integer registers. */
18324 if (!done_p
&& TARGET_POWERPC64
18325 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
18327 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
18329 rtx addr
= XEXP (x
, 0);
18330 rtx off
= address_offset (addr
);
18332 if (off
!= NULL_RTX
)
18334 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
18335 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
18337 /* We need a secondary reload when our legitimate_address_p
18338 says the address is good (as otherwise the entire address
18339 will be reloaded), and the offset is not a multiple of
18340 four or we have an address wrap. Address wrap will only
18341 occur for LO_SUMs since legitimate_offset_address_p
18342 rejects addresses for 16-byte mems that will wrap. */
18343 if (GET_CODE (addr
) == LO_SUM
18344 ? (1 /* legitimate_address_p allows any offset for lo_sum */
18345 && ((offset
& 3) != 0
18346 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
18347 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
18348 && (offset
& 3) != 0))
18350 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
18352 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
18353 : CODE_FOR_reload_di_load
);
18355 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
18356 : CODE_FOR_reload_di_store
);
18357 sri
->extra_cost
= 2;
18368 if (!done_p
&& !TARGET_POWERPC64
18369 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
18371 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
18373 rtx addr
= XEXP (x
, 0);
18374 rtx off
= address_offset (addr
);
18376 if (off
!= NULL_RTX
)
18378 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
18379 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
18381 /* We need a secondary reload when our legitimate_address_p
18382 says the address is good (as otherwise the entire address
18383 will be reloaded), and we have a wrap.
18385 legitimate_lo_sum_address_p allows LO_SUM addresses to
18386 have any offset so test for wrap in the low 16 bits.
18388 legitimate_offset_address_p checks for the range
18389 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
18390 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
18391 [0x7ff4,0x7fff] respectively, so test for the
18392 intersection of these ranges, [0x7ffc,0x7fff] and
18393 [0x7ff4,0x7ff7] respectively.
18395 Note that the address we see here may have been
18396 manipulated by legitimize_reload_address. */
18397 if (GET_CODE (addr
) == LO_SUM
18398 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
18399 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
18402 sri
->icode
= CODE_FOR_reload_si_load
;
18404 sri
->icode
= CODE_FOR_reload_si_store
;
18405 sri
->extra_cost
= 2;
18420 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
18422 gcc_assert (ret
!= ALL_REGS
);
18424 if (TARGET_DEBUG_ADDR
)
18427 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
18429 reg_class_names
[ret
],
18430 in_p
? "true" : "false",
18431 reg_class_names
[rclass
],
18432 GET_MODE_NAME (mode
));
18434 if (reload_completed
)
18435 fputs (", after reload", stderr
);
18438 fputs (", done_p not set", stderr
);
18441 fputs (", default secondary reload", stderr
);
18443 if (sri
->icode
!= CODE_FOR_nothing
)
18444 fprintf (stderr
, ", reload func = %s, extra cost = %d",
18445 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
18447 fputs ("\n", stderr
);
18454 /* Better tracing for rs6000_secondary_reload_inner. */
18457 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
18462 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
18464 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
18465 store_p
? "store" : "load");
18468 set
= gen_rtx_SET (mem
, reg
);
18470 set
= gen_rtx_SET (reg
, mem
);
18472 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
18473 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
18476 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
18477 ATTRIBUTE_NORETURN
;
18480 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
18483 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
18484 gcc_unreachable ();
18487 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
18488 reload helper functions. These were identified in
18489 rs6000_secondary_reload_memory, and if reload decided to use the secondary
18490 reload, it calls the insns:
18491 reload_<RELOAD:mode>_<P:mptrsize>_store
18492 reload_<RELOAD:mode>_<P:mptrsize>_load
18494 which in turn calls this function, to do whatever is necessary to create
18495 valid addresses. */
18498 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
18500 int regno
= true_regnum (reg
);
18501 machine_mode mode
= GET_MODE (reg
);
18502 addr_mask_type addr_mask
;
18505 rtx op_reg
, op0
, op1
;
18510 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
18511 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
18512 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18514 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
18515 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
18517 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
18518 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
18520 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
18521 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
18524 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18526 /* Make sure the mode is valid in this register class. */
18527 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
18528 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18530 if (TARGET_DEBUG_ADDR
)
18531 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
18533 new_addr
= addr
= XEXP (mem
, 0);
18534 switch (GET_CODE (addr
))
18536 /* Does the register class support auto update forms for this mode? If
18537 not, do the update now. We don't need a scratch register, since the
18538 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
18541 op_reg
= XEXP (addr
, 0);
18542 if (!base_reg_operand (op_reg
, Pmode
))
18543 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18545 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
18547 emit_insn (gen_add2_insn (op_reg
, GEN_INT (GET_MODE_SIZE (mode
))));
18553 op0
= XEXP (addr
, 0);
18554 op1
= XEXP (addr
, 1);
18555 if (!base_reg_operand (op0
, Pmode
)
18556 || GET_CODE (op1
) != PLUS
18557 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
18558 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18560 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
18562 emit_insn (gen_rtx_SET (op0
, op1
));
18567 /* Do we need to simulate AND -16 to clear the bottom address bits used
18568 in VMX load/stores? */
18570 op0
= XEXP (addr
, 0);
18571 op1
= XEXP (addr
, 1);
18572 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
18574 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
18577 else if (GET_CODE (op1
) == PLUS
)
18579 emit_insn (gen_rtx_SET (scratch
, op1
));
18584 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18586 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
18587 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
18588 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
18589 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
18590 new_addr
= scratch
;
18594 /* If this is an indirect address, make sure it is a base register. */
18597 if (!base_reg_operand (addr
, GET_MODE (addr
)))
18599 emit_insn (gen_rtx_SET (scratch
, addr
));
18600 new_addr
= scratch
;
18604 /* If this is an indexed address, make sure the register class can handle
18605 indexed addresses for this mode. */
18607 op0
= XEXP (addr
, 0);
18608 op1
= XEXP (addr
, 1);
18609 if (!base_reg_operand (op0
, Pmode
))
18610 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18612 else if (int_reg_operand (op1
, Pmode
))
18614 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
18616 emit_insn (gen_rtx_SET (scratch
, addr
));
18617 new_addr
= scratch
;
18621 /* Make sure the register class can handle offset addresses. */
18622 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
18624 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
18626 emit_insn (gen_rtx_SET (scratch
, addr
));
18627 new_addr
= scratch
;
18632 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18637 op0
= XEXP (addr
, 0);
18638 op1
= XEXP (addr
, 1);
18639 if (!base_reg_operand (op0
, Pmode
))
18640 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18642 else if (int_reg_operand (op1
, Pmode
))
18644 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
18646 emit_insn (gen_rtx_SET (scratch
, addr
));
18647 new_addr
= scratch
;
18651 /* Make sure the register class can handle offset addresses. */
18652 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
18654 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
18656 emit_insn (gen_rtx_SET (scratch
, addr
));
18657 new_addr
= scratch
;
18662 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18669 rs6000_emit_move (scratch
, addr
, Pmode
);
18670 new_addr
= scratch
;
18674 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18677 /* Adjust the address if it changed. */
18678 if (addr
!= new_addr
)
18680 mem
= replace_equiv_address_nv (mem
, new_addr
);
18681 if (TARGET_DEBUG_ADDR
)
18682 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
18685 /* Now create the move. */
18687 emit_insn (gen_rtx_SET (mem
, reg
));
18689 emit_insn (gen_rtx_SET (reg
, mem
));
18694 /* Convert reloads involving 64-bit gprs and misaligned offset
18695 addressing, or multiple 32-bit gprs and offsets that are too large,
18696 to use indirect addressing. */
18699 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
18701 int regno
= true_regnum (reg
);
18702 enum reg_class rclass
;
18704 rtx scratch_or_premodify
= scratch
;
18706 if (TARGET_DEBUG_ADDR
)
18708 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
18709 store_p
? "store" : "load");
18710 fprintf (stderr
, "reg:\n");
18712 fprintf (stderr
, "mem:\n");
18714 fprintf (stderr
, "scratch:\n");
18715 debug_rtx (scratch
);
18718 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
18719 gcc_assert (GET_CODE (mem
) == MEM
);
18720 rclass
= REGNO_REG_CLASS (regno
);
18721 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
18722 addr
= XEXP (mem
, 0);
18724 if (GET_CODE (addr
) == PRE_MODIFY
)
18726 gcc_assert (REG_P (XEXP (addr
, 0))
18727 && GET_CODE (XEXP (addr
, 1)) == PLUS
18728 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
18729 scratch_or_premodify
= XEXP (addr
, 0);
18730 if (!HARD_REGISTER_P (scratch_or_premodify
))
18731 /* If we have a pseudo here then reload will have arranged
18732 to have it replaced, but only in the original insn.
18733 Use the replacement here too. */
18734 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
18736 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
18737 expressions from the original insn, without unsharing them.
18738 Any RTL that points into the original insn will of course
18739 have register replacements applied. That is why we don't
18740 need to look for replacements under the PLUS. */
18741 addr
= XEXP (addr
, 1);
18743 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
18745 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
18747 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
18749 /* Now create the move. */
18751 emit_insn (gen_rtx_SET (mem
, reg
));
18753 emit_insn (gen_rtx_SET (reg
, mem
));
18758 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
18759 this function has any SDmode references. If we are on a power7 or later, we
18760 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
18761 can load/store the value. */
18764 rs6000_alloc_sdmode_stack_slot (void)
18768 gimple_stmt_iterator gsi
;
18770 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
18771 /* We use a different approach for dealing with the secondary
18776 if (TARGET_NO_SDMODE_STACK
)
18779 FOR_EACH_BB_FN (bb
, cfun
)
18780 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
18782 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
18785 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
18786 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
18792 /* Check for any SDmode parameters of the function. */
18793 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
18795 if (TREE_TYPE (t
) == error_mark_node
)
18798 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
18799 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
18801 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
18802 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
18810 rs6000_instantiate_decls (void)
18812 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
18813 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
18816 /* Given an rtx X being reloaded into a reg required to be
18817 in class CLASS, return the class of reg to actually use.
18818 In general this is just CLASS; but on some machines
18819 in some cases it is preferable to use a more restrictive class.
18821 On the RS/6000, we have to return NO_REGS when we want to reload a
18822 floating-point CONST_DOUBLE to force it to be copied to memory.
18824 We also don't want to reload integer values into floating-point
18825 registers if we can at all help it. In fact, this can
18826 cause reload to die, if it tries to generate a reload of CTR
18827 into a FP register and discovers it doesn't have the memory location
18830 ??? Would it be a good idea to have reload do the converse, that is
18831 try to reload floating modes into FP registers if possible?
18834 static enum reg_class
18835 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
18837 machine_mode mode
= GET_MODE (x
);
18838 bool is_constant
= CONSTANT_P (x
);
18840 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
18841 the reloading of address expressions using PLUS into floating point
18843 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
18847 /* Zero is always allowed in all VSX registers. */
18848 if (x
== CONST0_RTX (mode
))
18851 /* If this is a vector constant that can be formed with a few Altivec
18852 instructions, we want altivec registers. */
18853 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
18854 return ALTIVEC_REGS
;
18856 /* Force constant to memory. */
18860 /* D-form addressing can easily reload the value. */
18861 if (mode_supports_vmx_dform (mode
))
18864 /* If this is a scalar floating point value and we don't have D-form
18865 addressing, prefer the traditional floating point registers so that we
18866 can use D-form (register+offset) addressing. */
18867 if (GET_MODE_SIZE (mode
) < 16 && rclass
== VSX_REGS
)
18870 /* Prefer the Altivec registers if Altivec is handling the vector
18871 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
18873 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
18874 || mode
== V1TImode
)
18875 return ALTIVEC_REGS
;
18880 if (is_constant
|| GET_CODE (x
) == PLUS
)
18882 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
18883 return GENERAL_REGS
;
18884 if (reg_class_subset_p (BASE_REGS
, rclass
))
18889 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
18890 return GENERAL_REGS
;
18895 /* Debug version of rs6000_preferred_reload_class. */
18896 static enum reg_class
18897 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
18899 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
18902 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
18904 reg_class_names
[ret
], reg_class_names
[rclass
],
18905 GET_MODE_NAME (GET_MODE (x
)));
18911 /* If we are copying between FP or AltiVec registers and anything else, we need
18912 a memory location. The exception is when we are targeting ppc64 and the
18913 move to/from fpr to gpr instructions are available. Also, under VSX, you
18914 can copy vector registers from the FP register set to the Altivec register
18915 set and vice versa. */
18918 rs6000_secondary_memory_needed (enum reg_class from_class
,
18919 enum reg_class to_class
,
18922 enum rs6000_reg_type from_type
, to_type
;
18923 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
18924 || (to_class
== ALTIVEC_REGS
));
18926 /* If a simple/direct move is available, we don't need secondary memory */
18927 from_type
= reg_class_to_reg_type
[(int)from_class
];
18928 to_type
= reg_class_to_reg_type
[(int)to_class
];
18930 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
18931 (secondary_reload_info
*)0, altivec_p
))
18934 /* If we have a floating point or vector register class, we need to use
18935 memory to transfer the data. */
18936 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
18942 /* Debug version of rs6000_secondary_memory_needed. */
18944 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
18945 enum reg_class to_class
,
18948 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
18951 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
18952 "to_class = %s, mode = %s\n",
18953 ret
? "true" : "false",
18954 reg_class_names
[from_class
],
18955 reg_class_names
[to_class
],
18956 GET_MODE_NAME (mode
));
18961 /* Return the register class of a scratch register needed to copy IN into
18962 or out of a register in RCLASS in MODE. If it can be done directly,
18963 NO_REGS is returned. */
18965 static enum reg_class
18966 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
18971 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
18973 && MACHOPIC_INDIRECT
18977 /* We cannot copy a symbolic operand directly into anything
18978 other than BASE_REGS for TARGET_ELF. So indicate that a
18979 register from BASE_REGS is needed as an intermediate
18982 On Darwin, pic addresses require a load from memory, which
18983 needs a base register. */
18984 if (rclass
!= BASE_REGS
18985 && (GET_CODE (in
) == SYMBOL_REF
18986 || GET_CODE (in
) == HIGH
18987 || GET_CODE (in
) == LABEL_REF
18988 || GET_CODE (in
) == CONST
))
18992 if (GET_CODE (in
) == REG
)
18994 regno
= REGNO (in
);
18995 if (regno
>= FIRST_PSEUDO_REGISTER
)
18997 regno
= true_regnum (in
);
18998 if (regno
>= FIRST_PSEUDO_REGISTER
)
19002 else if (GET_CODE (in
) == SUBREG
)
19004 regno
= true_regnum (in
);
19005 if (regno
>= FIRST_PSEUDO_REGISTER
)
19011 /* If we have VSX register moves, prefer moving scalar values between
19012 Altivec registers and GPR by going via an FPR (and then via memory)
19013 instead of reloading the secondary memory address for Altivec moves. */
19015 && GET_MODE_SIZE (mode
) < 16
19016 && !mode_supports_vmx_dform (mode
)
19017 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
19018 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
19019 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
19020 && (regno
>= 0 && INT_REGNO_P (regno
)))))
19023 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
19025 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
19026 || (regno
>= 0 && INT_REGNO_P (regno
)))
19029 /* Constants, memory, and VSX registers can go into VSX registers (both the
19030 traditional floating point and the altivec registers). */
19031 if (rclass
== VSX_REGS
19032 && (regno
== -1 || VSX_REGNO_P (regno
)))
19035 /* Constants, memory, and FP registers can go into FP registers. */
19036 if ((regno
== -1 || FP_REGNO_P (regno
))
19037 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
19038 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
19040 /* Memory, and AltiVec registers can go into AltiVec registers. */
19041 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
19042 && rclass
== ALTIVEC_REGS
)
19045 /* We can copy among the CR registers. */
19046 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
19047 && regno
>= 0 && CR_REGNO_P (regno
))
19050 /* Otherwise, we need GENERAL_REGS. */
19051 return GENERAL_REGS
;
19054 /* Debug version of rs6000_secondary_reload_class. */
19055 static enum reg_class
19056 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
19057 machine_mode mode
, rtx in
)
19059 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
19061 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
19062 "mode = %s, input rtx:\n",
19063 reg_class_names
[ret
], reg_class_names
[rclass
],
19064 GET_MODE_NAME (mode
));
19070 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
19073 rs6000_cannot_change_mode_class (machine_mode from
,
19075 enum reg_class rclass
)
19077 unsigned from_size
= GET_MODE_SIZE (from
);
19078 unsigned to_size
= GET_MODE_SIZE (to
);
19080 if (from_size
!= to_size
)
19082 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
19084 if (reg_classes_intersect_p (xclass
, rclass
))
19086 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
19087 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
19088 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
19089 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
19091 /* Don't allow 64-bit types to overlap with 128-bit types that take a
19092 single register under VSX because the scalar part of the register
19093 is in the upper 64-bits, and not the lower 64-bits. Types like
19094 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
19095 IEEE floating point can't overlap, and neither can small
19098 if (to_float128_vector_p
&& from_float128_vector_p
)
19101 else if (to_float128_vector_p
|| from_float128_vector_p
)
19104 /* TDmode in floating-mode registers must always go into a register
19105 pair with the most significant word in the even-numbered register
19106 to match ISA requirements. In little-endian mode, this does not
19107 match subreg numbering, so we cannot allow subregs. */
19108 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
19111 if (from_size
< 8 || to_size
< 8)
19114 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
19117 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
19126 if (TARGET_E500_DOUBLE
19127 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
19128 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
19129 || (((to
) == IFmode
) + ((from
) == IFmode
)) == 1
19130 || (((to
) == KFmode
) + ((from
) == KFmode
)) == 1
19131 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
19132 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
19133 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
19136 /* Since the VSX register set includes traditional floating point registers
19137 and altivec registers, just check for the size being different instead of
19138 trying to check whether the modes are vector modes. Otherwise it won't
19139 allow say DF and DI to change classes. For types like TFmode and TDmode
19140 that take 2 64-bit registers, rather than a single 128-bit register, don't
19141 allow subregs of those types to other 128 bit types. */
19142 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
19144 unsigned num_regs
= (from_size
+ 15) / 16;
19145 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
19146 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
19149 return (from_size
!= 8 && from_size
!= 16);
19152 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
19153 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
19156 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
19157 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
19163 /* Debug version of rs6000_cannot_change_mode_class. */
19165 rs6000_debug_cannot_change_mode_class (machine_mode from
,
19167 enum reg_class rclass
)
19169 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
19172 "rs6000_cannot_change_mode_class, return %s, from = %s, "
19173 "to = %s, rclass = %s\n",
19174 ret
? "true" : "false",
19175 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
19176 reg_class_names
[rclass
]);
19181 /* Return a string to do a move operation of 128 bits of data. */
19184 rs6000_output_move_128bit (rtx operands
[])
19186 rtx dest
= operands
[0];
19187 rtx src
= operands
[1];
19188 machine_mode mode
= GET_MODE (dest
);
19191 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
19192 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
19196 dest_regno
= REGNO (dest
);
19197 dest_gpr_p
= INT_REGNO_P (dest_regno
);
19198 dest_fp_p
= FP_REGNO_P (dest_regno
);
19199 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
19200 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
19205 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
19210 src_regno
= REGNO (src
);
19211 src_gpr_p
= INT_REGNO_P (src_regno
);
19212 src_fp_p
= FP_REGNO_P (src_regno
);
19213 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
19214 src_vsx_p
= src_fp_p
| src_vmx_p
;
19219 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
19222 /* Register moves. */
19223 if (dest_regno
>= 0 && src_regno
>= 0)
19230 if (TARGET_DIRECT_MOVE_128
&& src_vsx_p
)
19231 return (WORDS_BIG_ENDIAN
19232 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
19233 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
19235 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
19239 else if (TARGET_VSX
&& dest_vsx_p
)
19242 return "xxlor %x0,%x1,%x1";
19244 else if (TARGET_DIRECT_MOVE_128
&& src_gpr_p
)
19245 return (WORDS_BIG_ENDIAN
19246 ? "mtvsrdd %x0,%1,%L1"
19247 : "mtvsrdd %x0,%L1,%1");
19249 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
19253 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
19254 return "vor %0,%1,%1";
19256 else if (dest_fp_p
&& src_fp_p
)
19261 else if (dest_regno
>= 0 && MEM_P (src
))
19265 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
19271 else if (TARGET_ALTIVEC
&& dest_vmx_p
19272 && altivec_indexed_or_indirect_operand (src
, mode
))
19273 return "lvx %0,%y1";
19275 else if (TARGET_VSX
&& dest_vsx_p
)
19277 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
19278 return "lxvw4x %x0,%y1";
19280 return "lxvd2x %x0,%y1";
19283 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
19284 return "lvx %0,%y1";
19286 else if (dest_fp_p
)
19291 else if (src_regno
>= 0 && MEM_P (dest
))
19295 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
19296 return "stq %1,%0";
19301 else if (TARGET_ALTIVEC
&& src_vmx_p
19302 && altivec_indexed_or_indirect_operand (src
, mode
))
19303 return "stvx %1,%y0";
19305 else if (TARGET_VSX
&& src_vsx_p
)
19307 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
19308 return "stxvw4x %x1,%y0";
19310 return "stxvd2x %x1,%y0";
19313 else if (TARGET_ALTIVEC
&& src_vmx_p
)
19314 return "stvx %1,%y0";
19321 else if (dest_regno
>= 0
19322 && (GET_CODE (src
) == CONST_INT
19323 || GET_CODE (src
) == CONST_WIDE_INT
19324 || GET_CODE (src
) == CONST_DOUBLE
19325 || GET_CODE (src
) == CONST_VECTOR
))
19330 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
19331 return "xxlxor %x0,%x0,%x0";
19333 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
19334 return output_vec_const_move (operands
);
19337 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
19340 /* Validate a 128-bit move. */
19342 rs6000_move_128bit_ok_p (rtx operands
[])
19344 machine_mode mode
= GET_MODE (operands
[0]);
19345 return (gpc_reg_operand (operands
[0], mode
)
19346 || gpc_reg_operand (operands
[1], mode
));
19349 /* Return true if a 128-bit move needs to be split. */
19351 rs6000_split_128bit_ok_p (rtx operands
[])
19353 if (!reload_completed
)
19356 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
19359 if (quad_load_store_p (operands
[0], operands
[1]))
19366 /* Given a comparison operation, return the bit number in CCR to test. We
19367 know this is a valid comparison.
19369 SCC_P is 1 if this is for an scc. That means that %D will have been
19370 used instead of %C, so the bits will be in different places.
19372 Return -1 if OP isn't a valid comparison for some reason. */
19375 ccr_bit (rtx op
, int scc_p
)
19377 enum rtx_code code
= GET_CODE (op
);
19378 machine_mode cc_mode
;
19383 if (!COMPARISON_P (op
))
19386 reg
= XEXP (op
, 0);
19388 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
19390 cc_mode
= GET_MODE (reg
);
19391 cc_regnum
= REGNO (reg
);
19392 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
19394 validate_condition_mode (code
, cc_mode
);
19396 /* When generating a sCOND operation, only positive conditions are
19399 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
19400 || code
== GTU
|| code
== LTU
);
19405 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
19407 return base_bit
+ 2;
19408 case GT
: case GTU
: case UNLE
:
19409 return base_bit
+ 1;
19410 case LT
: case LTU
: case UNGE
:
19412 case ORDERED
: case UNORDERED
:
19413 return base_bit
+ 3;
19416 /* If scc, we will have done a cror to put the bit in the
19417 unordered position. So test that bit. For integer, this is ! LT
19418 unless this is an scc insn. */
19419 return scc_p
? base_bit
+ 3 : base_bit
;
19422 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
19425 gcc_unreachable ();
19429 /* Return the GOT register. */
19432 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
19434 /* The second flow pass currently (June 1999) can't update
19435 regs_ever_live without disturbing other parts of the compiler, so
19436 update it here to make the prolog/epilogue code happy. */
19437 if (!can_create_pseudo_p ()
19438 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
19439 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
19441 crtl
->uses_pic_offset_table
= 1;
19443 return pic_offset_table_rtx
;
19446 static rs6000_stack_t stack_info
;
19448 /* Function to init struct machine_function.
19449 This will be called, via a pointer variable,
19450 from push_function_context. */
19452 static struct machine_function
*
19453 rs6000_init_machine_status (void)
19455 stack_info
.reload_completed
= 0;
19456 return ggc_cleared_alloc
<machine_function
> ();
19459 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
19461 /* Write out a function code label. */
19464 rs6000_output_function_entry (FILE *file
, const char *fname
)
19466 if (fname
[0] != '.')
19468 switch (DEFAULT_ABI
)
19471 gcc_unreachable ();
19477 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
19487 RS6000_OUTPUT_BASENAME (file
, fname
);
19490 /* Print an operand. Recognize special options, documented below. */
19493 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
19494 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
19496 #define SMALL_DATA_RELOC "sda21"
19497 #define SMALL_DATA_REG 0
19501 print_operand (FILE *file
, rtx x
, int code
)
19504 unsigned HOST_WIDE_INT uval
;
19508 /* %a is output_address. */
19510 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
19514 /* Like 'J' but get to the GT bit only. */
19515 gcc_assert (REG_P (x
));
19517 /* Bit 1 is GT bit. */
19518 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
19520 /* Add one for shift count in rlinm for scc. */
19521 fprintf (file
, "%d", i
+ 1);
19525 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
19528 output_operand_lossage ("invalid %%e value");
19533 if ((uval
& 0xffff) == 0 && uval
!= 0)
19538 /* X is a CR register. Print the number of the EQ bit of the CR */
19539 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19540 output_operand_lossage ("invalid %%E value");
19542 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
19546 /* X is a CR register. Print the shift count needed to move it
19547 to the high-order four bits. */
19548 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19549 output_operand_lossage ("invalid %%f value");
19551 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
19555 /* Similar, but print the count for the rotate in the opposite
19557 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19558 output_operand_lossage ("invalid %%F value");
19560 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
19564 /* X is a constant integer. If it is negative, print "m",
19565 otherwise print "z". This is to make an aze or ame insn. */
19566 if (GET_CODE (x
) != CONST_INT
)
19567 output_operand_lossage ("invalid %%G value");
19568 else if (INTVAL (x
) >= 0)
19575 /* If constant, output low-order five bits. Otherwise, write
19578 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
19580 print_operand (file
, x
, 0);
19584 /* If constant, output low-order six bits. Otherwise, write
19587 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
19589 print_operand (file
, x
, 0);
19593 /* Print `i' if this is a constant, else nothing. */
19599 /* Write the bit number in CCR for jump. */
19600 i
= ccr_bit (x
, 0);
19602 output_operand_lossage ("invalid %%j code");
19604 fprintf (file
, "%d", i
);
19608 /* Similar, but add one for shift count in rlinm for scc and pass
19609 scc flag to `ccr_bit'. */
19610 i
= ccr_bit (x
, 1);
19612 output_operand_lossage ("invalid %%J code");
19614 /* If we want bit 31, write a shift count of zero, not 32. */
19615 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
19619 /* X must be a constant. Write the 1's complement of the
19622 output_operand_lossage ("invalid %%k value");
19624 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
19628 /* X must be a symbolic constant on ELF. Write an
19629 expression suitable for an 'addi' that adds in the low 16
19630 bits of the MEM. */
19631 if (GET_CODE (x
) == CONST
)
19633 if (GET_CODE (XEXP (x
, 0)) != PLUS
19634 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
19635 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
19636 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
19637 output_operand_lossage ("invalid %%K value");
19639 print_operand_address (file
, x
);
19640 fputs ("@l", file
);
19643 /* %l is output_asm_label. */
19646 /* Write second word of DImode or DFmode reference. Works on register
19647 or non-indexed memory only. */
19649 fputs (reg_names
[REGNO (x
) + 1], file
);
19650 else if (MEM_P (x
))
19652 machine_mode mode
= GET_MODE (x
);
19653 /* Handle possible auto-increment. Since it is pre-increment and
19654 we have already done it, we can just use an offset of word. */
19655 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19656 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19657 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
19659 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19660 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
19663 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
,
19667 if (small_data_operand (x
, GET_MODE (x
)))
19668 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19669 reg_names
[SMALL_DATA_REG
]);
19674 /* Write the number of elements in the vector times 4. */
19675 if (GET_CODE (x
) != PARALLEL
)
19676 output_operand_lossage ("invalid %%N value");
19678 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
19682 /* Similar, but subtract 1 first. */
19683 if (GET_CODE (x
) != PARALLEL
)
19684 output_operand_lossage ("invalid %%O value");
19686 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
19690 /* X is a CONST_INT that is a power of two. Output the logarithm. */
19693 || (i
= exact_log2 (INTVAL (x
))) < 0)
19694 output_operand_lossage ("invalid %%p value");
19696 fprintf (file
, "%d", i
);
19700 /* The operand must be an indirect memory reference. The result
19701 is the register name. */
19702 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
19703 || REGNO (XEXP (x
, 0)) >= 32)
19704 output_operand_lossage ("invalid %%P value");
19706 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
19710 /* This outputs the logical code corresponding to a boolean
19711 expression. The expression may have one or both operands
19712 negated (if one, only the first one). For condition register
19713 logical operations, it will also treat the negated
19714 CR codes as NOTs, but not handle NOTs of them. */
19716 const char *const *t
= 0;
19718 enum rtx_code code
= GET_CODE (x
);
19719 static const char * const tbl
[3][3] = {
19720 { "and", "andc", "nor" },
19721 { "or", "orc", "nand" },
19722 { "xor", "eqv", "xor" } };
19726 else if (code
== IOR
)
19728 else if (code
== XOR
)
19731 output_operand_lossage ("invalid %%q value");
19733 if (GET_CODE (XEXP (x
, 0)) != NOT
)
19737 if (GET_CODE (XEXP (x
, 1)) == NOT
)
19748 if (! TARGET_MFCRF
)
19754 /* X is a CR register. Print the mask for `mtcrf'. */
19755 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19756 output_operand_lossage ("invalid %%R value");
19758 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
19762 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
19763 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
19765 /* Bit 3 is OV bit. */
19766 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
19768 /* If we want bit 31, write a shift count of zero, not 32. */
19769 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
19773 /* Print the symbolic name of a branch target register. */
19774 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
19775 && REGNO (x
) != CTR_REGNO
))
19776 output_operand_lossage ("invalid %%T value");
19777 else if (REGNO (x
) == LR_REGNO
)
19778 fputs ("lr", file
);
19780 fputs ("ctr", file
);
19784 /* High-order or low-order 16 bits of constant, whichever is non-zero,
19785 for use in unsigned operand. */
19788 output_operand_lossage ("invalid %%u value");
19793 if ((uval
& 0xffff) == 0)
19796 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
19800 /* High-order 16 bits of constant for use in signed operand. */
19802 output_operand_lossage ("invalid %%v value");
19804 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
19805 (INTVAL (x
) >> 16) & 0xffff);
19809 /* Print `u' if this has an auto-increment or auto-decrement. */
19811 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
19812 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
19813 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
19818 /* Print the trap code for this operand. */
19819 switch (GET_CODE (x
))
19822 fputs ("eq", file
); /* 4 */
19825 fputs ("ne", file
); /* 24 */
19828 fputs ("lt", file
); /* 16 */
19831 fputs ("le", file
); /* 20 */
19834 fputs ("gt", file
); /* 8 */
19837 fputs ("ge", file
); /* 12 */
19840 fputs ("llt", file
); /* 2 */
19843 fputs ("lle", file
); /* 6 */
19846 fputs ("lgt", file
); /* 1 */
19849 fputs ("lge", file
); /* 5 */
19852 gcc_unreachable ();
19857 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
19860 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
19861 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
19863 print_operand (file
, x
, 0);
19867 /* X is a FPR or Altivec register used in a VSX context. */
19868 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
19869 output_operand_lossage ("invalid %%x value");
19872 int reg
= REGNO (x
);
19873 int vsx_reg
= (FP_REGNO_P (reg
)
19875 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
19877 #ifdef TARGET_REGNAMES
19878 if (TARGET_REGNAMES
)
19879 fprintf (file
, "%%vs%d", vsx_reg
);
19882 fprintf (file
, "%d", vsx_reg
);
19888 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
19889 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
19890 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
19895 /* Like 'L', for third word of TImode/PTImode */
19897 fputs (reg_names
[REGNO (x
) + 2], file
);
19898 else if (MEM_P (x
))
19900 machine_mode mode
= GET_MODE (x
);
19901 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19902 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19903 output_address (mode
, plus_constant (Pmode
,
19904 XEXP (XEXP (x
, 0), 0), 8));
19905 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19906 output_address (mode
, plus_constant (Pmode
,
19907 XEXP (XEXP (x
, 0), 0), 8));
19909 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 8), 0));
19910 if (small_data_operand (x
, GET_MODE (x
)))
19911 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19912 reg_names
[SMALL_DATA_REG
]);
19917 /* X is a SYMBOL_REF. Write out the name preceded by a
19918 period and without any trailing data in brackets. Used for function
19919 names. If we are configured for System V (or the embedded ABI) on
19920 the PowerPC, do not emit the period, since those systems do not use
19921 TOCs and the like. */
19922 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
19924 /* For macho, check to see if we need a stub. */
19927 const char *name
= XSTR (x
, 0);
19929 if (darwin_emit_branch_islands
19930 && MACHOPIC_INDIRECT
19931 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
19932 name
= machopic_indirection_name (x
, /*stub_p=*/true);
19934 assemble_name (file
, name
);
19936 else if (!DOT_SYMBOLS
)
19937 assemble_name (file
, XSTR (x
, 0));
19939 rs6000_output_function_entry (file
, XSTR (x
, 0));
19943 /* Like 'L', for last word of TImode/PTImode. */
19945 fputs (reg_names
[REGNO (x
) + 3], file
);
19946 else if (MEM_P (x
))
19948 machine_mode mode
= GET_MODE (x
);
19949 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19950 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19951 output_address (mode
, plus_constant (Pmode
,
19952 XEXP (XEXP (x
, 0), 0), 12));
19953 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19954 output_address (mode
, plus_constant (Pmode
,
19955 XEXP (XEXP (x
, 0), 0), 12));
19957 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 12), 0));
19958 if (small_data_operand (x
, GET_MODE (x
)))
19959 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19960 reg_names
[SMALL_DATA_REG
]);
19964 /* Print AltiVec or SPE memory operand. */
19969 gcc_assert (MEM_P (x
));
19973 /* Ugly hack because %y is overloaded. */
19974 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
19975 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
19976 || FLOAT128_2REG_P (GET_MODE (x
))
19977 || GET_MODE (x
) == TImode
19978 || GET_MODE (x
) == PTImode
))
19980 /* Handle [reg]. */
19983 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
19986 /* Handle [reg+UIMM]. */
19987 else if (GET_CODE (tmp
) == PLUS
&&
19988 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
19992 gcc_assert (REG_P (XEXP (tmp
, 0)));
19994 x
= INTVAL (XEXP (tmp
, 1));
19995 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
19999 /* Fall through. Must be [reg+reg]. */
20001 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
20002 && GET_CODE (tmp
) == AND
20003 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
20004 && INTVAL (XEXP (tmp
, 1)) == -16)
20005 tmp
= XEXP (tmp
, 0);
20006 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
20007 && GET_CODE (tmp
) == PRE_MODIFY
)
20008 tmp
= XEXP (tmp
, 1);
20010 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
20013 if (GET_CODE (tmp
) != PLUS
20014 || !REG_P (XEXP (tmp
, 0))
20015 || !REG_P (XEXP (tmp
, 1)))
20017 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
20021 if (REGNO (XEXP (tmp
, 0)) == 0)
20022 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
20023 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
20025 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
20026 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
20033 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
20034 else if (MEM_P (x
))
20036 /* We need to handle PRE_INC and PRE_DEC here, since we need to
20037 know the width from the mode. */
20038 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
20039 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
20040 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
20041 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
20042 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
20043 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
20044 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
20045 output_address (GET_MODE (x
), XEXP (XEXP (x
, 0), 1));
20047 output_address (GET_MODE (x
), XEXP (x
, 0));
20051 if (toc_relative_expr_p (x
, false))
20052 /* This hack along with a corresponding hack in
20053 rs6000_output_addr_const_extra arranges to output addends
20054 where the assembler expects to find them. eg.
20055 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
20056 without this hack would be output as "x@toc+4". We
20058 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
20060 output_addr_const (file
, x
);
20065 if (const char *name
= get_some_local_dynamic_name ())
20066 assemble_name (file
, name
);
20068 output_operand_lossage ("'%%&' used without any "
20069 "local dynamic TLS references");
20073 output_operand_lossage ("invalid %%xn code");
20077 /* Print the address of an operand. */
20080 print_operand_address (FILE *file
, rtx x
)
20083 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
20084 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
20085 || GET_CODE (x
) == LABEL_REF
)
20087 output_addr_const (file
, x
);
20088 if (small_data_operand (x
, GET_MODE (x
)))
20089 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
20090 reg_names
[SMALL_DATA_REG
]);
20092 gcc_assert (!TARGET_TOC
);
20094 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
20095 && REG_P (XEXP (x
, 1)))
20097 if (REGNO (XEXP (x
, 0)) == 0)
20098 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
20099 reg_names
[ REGNO (XEXP (x
, 0)) ]);
20101 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
20102 reg_names
[ REGNO (XEXP (x
, 1)) ]);
20104 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
20105 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
20106 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
20107 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
20109 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
20110 && CONSTANT_P (XEXP (x
, 1)))
20112 fprintf (file
, "lo16(");
20113 output_addr_const (file
, XEXP (x
, 1));
20114 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
20118 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
20119 && CONSTANT_P (XEXP (x
, 1)))
20121 output_addr_const (file
, XEXP (x
, 1));
20122 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
20125 else if (toc_relative_expr_p (x
, false))
20127 /* This hack along with a corresponding hack in
20128 rs6000_output_addr_const_extra arranges to output addends
20129 where the assembler expects to find them. eg.
20131 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
20132 without this hack would be output as "x@toc+8@l(9)". We
20133 want "x+8@toc@l(9)". */
20134 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
20135 if (GET_CODE (x
) == LO_SUM
)
20136 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
20138 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
20141 gcc_unreachable ();
20144 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
20147 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
20149 if (GET_CODE (x
) == UNSPEC
)
20150 switch (XINT (x
, 1))
20152 case UNSPEC_TOCREL
:
20153 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
20154 && REG_P (XVECEXP (x
, 0, 1))
20155 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
20156 output_addr_const (file
, XVECEXP (x
, 0, 0));
20157 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
20159 if (INTVAL (tocrel_offset
) >= 0)
20160 fprintf (file
, "+");
20161 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
20163 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
20166 assemble_name (file
, toc_label_name
);
20168 else if (TARGET_ELF
)
20169 fputs ("@toc", file
);
20173 case UNSPEC_MACHOPIC_OFFSET
:
20174 output_addr_const (file
, XVECEXP (x
, 0, 0));
20176 machopic_output_function_base_name (file
);
20183 /* Target hook for assembling integer objects. The PowerPC version has
20184 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
20185 is defined. It also needs to handle DI-mode objects on 64-bit
20189 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
20191 #ifdef RELOCATABLE_NEEDS_FIXUP
20192 /* Special handling for SI values. */
20193 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
20195 static int recurse
= 0;
20197 /* For -mrelocatable, we mark all addresses that need to be fixed up in
20198 the .fixup section. Since the TOC section is already relocated, we
20199 don't need to mark it here. We used to skip the text section, but it
20200 should never be valid for relocated addresses to be placed in the text
20202 if (TARGET_RELOCATABLE
20203 && in_section
!= toc_section
20205 && !CONST_SCALAR_INT_P (x
)
20211 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
20213 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
20214 fprintf (asm_out_file
, "\t.long\t(");
20215 output_addr_const (asm_out_file
, x
);
20216 fprintf (asm_out_file
, ")@fixup\n");
20217 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
20218 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
20219 fprintf (asm_out_file
, "\t.long\t");
20220 assemble_name (asm_out_file
, buf
);
20221 fprintf (asm_out_file
, "\n\t.previous\n");
20225 /* Remove initial .'s to turn a -mcall-aixdesc function
20226 address into the address of the descriptor, not the function
20228 else if (GET_CODE (x
) == SYMBOL_REF
20229 && XSTR (x
, 0)[0] == '.'
20230 && DEFAULT_ABI
== ABI_AIX
)
20232 const char *name
= XSTR (x
, 0);
20233 while (*name
== '.')
20236 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
20240 #endif /* RELOCATABLE_NEEDS_FIXUP */
20241 return default_assemble_integer (x
, size
, aligned_p
);
20244 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
20245 /* Emit an assembler directive to set symbol visibility for DECL to
20246 VISIBILITY_TYPE. */
20249 rs6000_assemble_visibility (tree decl
, int vis
)
20254 /* Functions need to have their entry point symbol visibility set as
20255 well as their descriptor symbol visibility. */
20256 if (DEFAULT_ABI
== ABI_AIX
20258 && TREE_CODE (decl
) == FUNCTION_DECL
)
20260 static const char * const visibility_types
[] = {
20261 NULL
, "internal", "hidden", "protected"
20264 const char *name
, *type
;
20266 name
= ((* targetm
.strip_name_encoding
)
20267 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
20268 type
= visibility_types
[vis
];
20270 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
20271 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
20274 default_assemble_visibility (decl
, vis
);
20279 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
20281 /* Reversal of FP compares takes care -- an ordered compare
20282 becomes an unordered compare and vice versa. */
20283 if (mode
== CCFPmode
20284 && (!flag_finite_math_only
20285 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
20286 || code
== UNEQ
|| code
== LTGT
))
20287 return reverse_condition_maybe_unordered (code
);
20289 return reverse_condition (code
);
20292 /* Generate a compare for CODE. Return a brand-new rtx that
20293 represents the result of the compare. */
20296 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
20298 machine_mode comp_mode
;
20299 rtx compare_result
;
20300 enum rtx_code code
= GET_CODE (cmp
);
20301 rtx op0
= XEXP (cmp
, 0);
20302 rtx op1
= XEXP (cmp
, 1);
20304 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
20305 comp_mode
= CCmode
;
20306 else if (FLOAT_MODE_P (mode
))
20307 comp_mode
= CCFPmode
;
20308 else if (code
== GTU
|| code
== LTU
20309 || code
== GEU
|| code
== LEU
)
20310 comp_mode
= CCUNSmode
;
20311 else if ((code
== EQ
|| code
== NE
)
20312 && unsigned_reg_p (op0
)
20313 && (unsigned_reg_p (op1
)
20314 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
20315 /* These are unsigned values, perhaps there will be a later
20316 ordering compare that can be shared with this one. */
20317 comp_mode
= CCUNSmode
;
20319 comp_mode
= CCmode
;
20321 /* If we have an unsigned compare, make sure we don't have a signed value as
20323 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
20324 && INTVAL (op1
) < 0)
20326 op0
= copy_rtx_if_shared (op0
);
20327 op1
= force_reg (GET_MODE (op0
), op1
);
20328 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
20331 /* First, the compare. */
20332 compare_result
= gen_reg_rtx (comp_mode
);
20334 /* E500 FP compare instructions on the GPRs. Yuck! */
20335 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
20336 && FLOAT_MODE_P (mode
))
20338 rtx cmp
, or_result
, compare_result2
;
20339 machine_mode op_mode
= GET_MODE (op0
);
20342 if (op_mode
== VOIDmode
)
20343 op_mode
= GET_MODE (op1
);
20345 /* First reverse the condition codes that aren't directly supported. */
20353 code
= reverse_condition_maybe_unordered (code
);
20366 gcc_unreachable ();
20369 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
20370 This explains the following mess. */
20378 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20379 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
20380 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
20384 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20385 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
20386 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
20392 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20393 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
20394 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
20398 gcc_unreachable ();
20407 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20408 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
20409 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
20413 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20414 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
20415 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
20421 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20422 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
20423 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
20427 gcc_unreachable ();
20436 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20437 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
20438 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
20442 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20443 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
20444 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
20450 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20451 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
20452 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
20456 gcc_unreachable ();
20461 gcc_unreachable ();
20464 /* Synthesize LE and GE from LT/GT || EQ. */
20465 if (code
== LE
|| code
== GE
)
20469 compare_result2
= gen_reg_rtx (CCFPmode
);
20475 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20476 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
20477 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
20481 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20482 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
20483 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
20489 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
20490 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
20491 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
20495 gcc_unreachable ();
20500 /* OR them together. */
20501 or_result
= gen_reg_rtx (CCFPmode
);
20502 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
20504 compare_result
= or_result
;
20507 code
= reverse_p
? NE
: EQ
;
20512 /* IEEE 128-bit support in VSX registers when we do not have hardware
20514 else if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
20516 rtx libfunc
= NULL_RTX
;
20517 bool uneq_or_ltgt
= false;
20518 rtx dest
= gen_reg_rtx (SImode
);
20524 libfunc
= optab_libfunc (eq_optab
, mode
);
20529 libfunc
= optab_libfunc (ge_optab
, mode
);
20534 libfunc
= optab_libfunc (le_optab
, mode
);
20539 libfunc
= optab_libfunc (unord_optab
, mode
);
20540 code
= (code
== UNORDERED
) ? NE
: EQ
;
20545 libfunc
= optab_libfunc (le_optab
, mode
);
20546 code
= (code
== UNGE
) ? GE
: GT
;
20551 libfunc
= optab_libfunc (ge_optab
, mode
);
20552 code
= (code
== UNLE
) ? LE
: LT
;
20557 libfunc
= optab_libfunc (le_optab
, mode
);
20558 uneq_or_ltgt
= true;
20559 code
= (code
= UNEQ
) ? NE
: EQ
;
20563 gcc_unreachable ();
20566 gcc_assert (libfunc
);
20567 dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
20568 SImode
, 2, op0
, mode
, op1
, mode
);
20570 /* If this is UNEQ or LTGT, we call __lekf2, which returns -1 for less
20571 than, 0 for equal, +1 for greater, and +2 for nan. We add 1, to give
20572 a value of 0..3, and then do and AND immediate of 1 to isolate whether
20573 it is 0/Nan (i.e. bottom bit is 0), or less than/greater than
20574 (i.e. bottom bit is 1). */
20577 rtx add_result
= gen_reg_rtx (SImode
);
20578 rtx and_result
= gen_reg_rtx (SImode
);
20579 emit_insn (gen_addsi3 (add_result
, dest
, GEN_INT (1)));
20580 emit_insn (gen_andsi3 (and_result
, add_result
, GEN_INT (1)));
20584 emit_insn (gen_rtx_SET (compare_result
,
20585 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
20590 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
20591 CLOBBERs to match cmptf_internal2 pattern. */
20592 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
20593 && FLOAT128_IBM_P (GET_MODE (op0
))
20594 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
20595 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
20597 gen_rtx_SET (compare_result
,
20598 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
20599 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20600 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20601 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20602 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20603 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20604 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20605 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20606 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20607 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
20608 else if (GET_CODE (op1
) == UNSPEC
20609 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
20611 rtx op1b
= XVECEXP (op1
, 0, 0);
20612 comp_mode
= CCEQmode
;
20613 compare_result
= gen_reg_rtx (CCEQmode
);
20615 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
20617 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
20620 emit_insn (gen_rtx_SET (compare_result
,
20621 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
20624 /* Some kinds of FP comparisons need an OR operation;
20625 under flag_finite_math_only we don't bother. */
20626 if (FLOAT_MODE_P (mode
)
20627 && (!FLOAT128_IEEE_P (mode
) || TARGET_FLOAT128_HW
)
20628 && !flag_finite_math_only
20629 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
20630 && (code
== LE
|| code
== GE
20631 || code
== UNEQ
|| code
== LTGT
20632 || code
== UNGT
|| code
== UNLT
))
20634 enum rtx_code or1
, or2
;
20635 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
20636 rtx or_result
= gen_reg_rtx (CCEQmode
);
20640 case LE
: or1
= LT
; or2
= EQ
; break;
20641 case GE
: or1
= GT
; or2
= EQ
; break;
20642 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
20643 case LTGT
: or1
= LT
; or2
= GT
; break;
20644 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
20645 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
20646 default: gcc_unreachable ();
20648 validate_condition_mode (or1
, comp_mode
);
20649 validate_condition_mode (or2
, comp_mode
);
20650 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
20651 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
20652 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
20653 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
20655 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
20657 compare_result
= or_result
;
20661 validate_condition_mode (code
, GET_MODE (compare_result
));
20663 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
20667 /* Return the diagnostic message string if the binary operation OP is
20668 not permitted on TYPE1 and TYPE2, NULL otherwise. */
20671 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED
,
20675 enum machine_mode mode1
= TYPE_MODE (type1
);
20676 enum machine_mode mode2
= TYPE_MODE (type2
);
20678 /* For complex modes, use the inner type. */
20679 if (COMPLEX_MODE_P (mode1
))
20680 mode1
= GET_MODE_INNER (mode1
);
20682 if (COMPLEX_MODE_P (mode2
))
20683 mode2
= GET_MODE_INNER (mode2
);
20685 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
20686 double to intermix unless -mfloat128-convert. */
20687 if (mode1
== mode2
)
20690 if (!TARGET_FLOAT128_CVT
)
20692 if ((mode1
== KFmode
&& mode2
== IFmode
)
20693 || (mode1
== IFmode
&& mode2
== KFmode
))
20694 return N_("__float128 and __ibm128 cannot be used in the same "
20697 if (TARGET_IEEEQUAD
20698 && ((mode1
== IFmode
&& mode2
== TFmode
)
20699 || (mode1
== TFmode
&& mode2
== IFmode
)))
20700 return N_("__ibm128 and long double cannot be used in the same "
20703 if (!TARGET_IEEEQUAD
20704 && ((mode1
== KFmode
&& mode2
== TFmode
)
20705 || (mode1
== TFmode
&& mode2
== KFmode
)))
20706 return N_("__float128 and long double cannot be used in the same "
20714 /* Expand floating point conversion to/from __float128 and __ibm128. */
20717 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
20719 machine_mode dest_mode
= GET_MODE (dest
);
20720 machine_mode src_mode
= GET_MODE (src
);
20721 convert_optab cvt
= unknown_optab
;
20722 bool do_move
= false;
20723 rtx libfunc
= NULL_RTX
;
20725 typedef rtx (*rtx_2func_t
) (rtx
, rtx
);
20726 rtx_2func_t hw_convert
= (rtx_2func_t
)0;
20730 rtx_2func_t from_df
;
20731 rtx_2func_t from_sf
;
20732 rtx_2func_t from_si_sign
;
20733 rtx_2func_t from_si_uns
;
20734 rtx_2func_t from_di_sign
;
20735 rtx_2func_t from_di_uns
;
20738 rtx_2func_t to_si_sign
;
20739 rtx_2func_t to_si_uns
;
20740 rtx_2func_t to_di_sign
;
20741 rtx_2func_t to_di_uns
;
20742 } hw_conversions
[2] = {
20743 /* convertions to/from KFmode */
20745 gen_extenddfkf2_hw
, /* KFmode <- DFmode. */
20746 gen_extendsfkf2_hw
, /* KFmode <- SFmode. */
20747 gen_float_kfsi2_hw
, /* KFmode <- SImode (signed). */
20748 gen_floatuns_kfsi2_hw
, /* KFmode <- SImode (unsigned). */
20749 gen_float_kfdi2_hw
, /* KFmode <- DImode (signed). */
20750 gen_floatuns_kfdi2_hw
, /* KFmode <- DImode (unsigned). */
20751 gen_trunckfdf2_hw
, /* DFmode <- KFmode. */
20752 gen_trunckfsf2_hw
, /* SFmode <- KFmode. */
20753 gen_fix_kfsi2_hw
, /* SImode <- KFmode (signed). */
20754 gen_fixuns_kfsi2_hw
, /* SImode <- KFmode (unsigned). */
20755 gen_fix_kfdi2_hw
, /* DImode <- KFmode (signed). */
20756 gen_fixuns_kfdi2_hw
, /* DImode <- KFmode (unsigned). */
20759 /* convertions to/from TFmode */
20761 gen_extenddftf2_hw
, /* TFmode <- DFmode. */
20762 gen_extendsftf2_hw
, /* TFmode <- SFmode. */
20763 gen_float_tfsi2_hw
, /* TFmode <- SImode (signed). */
20764 gen_floatuns_tfsi2_hw
, /* TFmode <- SImode (unsigned). */
20765 gen_float_tfdi2_hw
, /* TFmode <- DImode (signed). */
20766 gen_floatuns_tfdi2_hw
, /* TFmode <- DImode (unsigned). */
20767 gen_trunctfdf2_hw
, /* DFmode <- TFmode. */
20768 gen_trunctfsf2_hw
, /* SFmode <- TFmode. */
20769 gen_fix_tfsi2_hw
, /* SImode <- TFmode (signed). */
20770 gen_fixuns_tfsi2_hw
, /* SImode <- TFmode (unsigned). */
20771 gen_fix_tfdi2_hw
, /* DImode <- TFmode (signed). */
20772 gen_fixuns_tfdi2_hw
, /* DImode <- TFmode (unsigned). */
20776 if (dest_mode
== src_mode
)
20777 gcc_unreachable ();
20779 /* Eliminate memory operations. */
20781 src
= force_reg (src_mode
, src
);
20785 rtx tmp
= gen_reg_rtx (dest_mode
);
20786 rs6000_expand_float128_convert (tmp
, src
, unsigned_p
);
20787 rs6000_emit_move (dest
, tmp
, dest_mode
);
20791 /* Convert to IEEE 128-bit floating point. */
20792 if (FLOAT128_IEEE_P (dest_mode
))
20794 if (dest_mode
== KFmode
)
20796 else if (dest_mode
== TFmode
)
20799 gcc_unreachable ();
20805 hw_convert
= hw_conversions
[kf_or_tf
].from_df
;
20810 hw_convert
= hw_conversions
[kf_or_tf
].from_sf
;
20816 if (FLOAT128_IBM_P (src_mode
))
20825 cvt
= ufloat_optab
;
20826 hw_convert
= hw_conversions
[kf_or_tf
].from_si_uns
;
20830 cvt
= sfloat_optab
;
20831 hw_convert
= hw_conversions
[kf_or_tf
].from_si_sign
;
20838 cvt
= ufloat_optab
;
20839 hw_convert
= hw_conversions
[kf_or_tf
].from_di_uns
;
20843 cvt
= sfloat_optab
;
20844 hw_convert
= hw_conversions
[kf_or_tf
].from_di_sign
;
20849 gcc_unreachable ();
20853 /* Convert from IEEE 128-bit floating point. */
20854 else if (FLOAT128_IEEE_P (src_mode
))
20856 if (src_mode
== KFmode
)
20858 else if (src_mode
== TFmode
)
20861 gcc_unreachable ();
20867 hw_convert
= hw_conversions
[kf_or_tf
].to_df
;
20872 hw_convert
= hw_conversions
[kf_or_tf
].to_sf
;
20878 if (FLOAT128_IBM_P (dest_mode
))
20888 hw_convert
= hw_conversions
[kf_or_tf
].to_si_uns
;
20893 hw_convert
= hw_conversions
[kf_or_tf
].to_si_sign
;
20901 hw_convert
= hw_conversions
[kf_or_tf
].to_di_uns
;
20906 hw_convert
= hw_conversions
[kf_or_tf
].to_di_sign
;
20911 gcc_unreachable ();
20915 /* Both IBM format. */
20916 else if (FLOAT128_IBM_P (dest_mode
) && FLOAT128_IBM_P (src_mode
))
20920 gcc_unreachable ();
20922 /* Handle conversion between TFmode/KFmode. */
20924 emit_move_insn (dest
, gen_lowpart (dest_mode
, src
));
20926 /* Handle conversion if we have hardware support. */
20927 else if (TARGET_FLOAT128_HW
&& hw_convert
)
20928 emit_insn ((hw_convert
) (dest
, src
));
20930 /* Call an external function to do the conversion. */
20931 else if (cvt
!= unknown_optab
)
20933 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
20934 gcc_assert (libfunc
!= NULL_RTX
);
20936 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
, 1, src
,
20939 gcc_assert (dest2
!= NULL_RTX
);
20940 if (!rtx_equal_p (dest
, dest2
))
20941 emit_move_insn (dest
, dest2
);
20945 gcc_unreachable ();
20950 /* Split a conversion from __float128 to an integer type into separate insns.
20951 OPERANDS points to the destination, source, and V2DI temporary
20952 register. CODE is either FIX or UNSIGNED_FIX. */
20955 convert_float128_to_int (rtx
*operands
, enum rtx_code code
)
20957 rtx dest
= operands
[0];
20958 rtx src
= operands
[1];
20959 rtx tmp
= operands
[2];
20966 if (GET_CODE (tmp
) == SCRATCH
)
20967 tmp
= gen_reg_rtx (V2DImode
);
20970 dest
= rs6000_address_for_fpconvert (dest
);
20972 /* Generate the actual convert insn of the form:
20973 (set (tmp) (unspec:V2DI [(fix:SI (reg:KF))] UNSPEC_IEEE128_CONVERT)). */
20974 cvt
= gen_rtx_fmt_e (code
, GET_MODE (dest
), src
);
20975 cvt_vec
= gen_rtvec (1, cvt
);
20976 cvt_unspec
= gen_rtx_UNSPEC (V2DImode
, cvt_vec
, UNSPEC_IEEE128_CONVERT
);
20977 emit_insn (gen_rtx_SET (tmp
, cvt_unspec
));
20979 /* Generate the move insn of the form:
20980 (set (dest:SI) (unspec:SI [(tmp:V2DI))] UNSPEC_IEEE128_MOVE)). */
20981 move_vec
= gen_rtvec (1, tmp
);
20982 move_unspec
= gen_rtx_UNSPEC (GET_MODE (dest
), move_vec
, UNSPEC_IEEE128_MOVE
);
20983 emit_insn (gen_rtx_SET (dest
, move_unspec
));
20986 /* Split a conversion from an integer type to __float128 into separate insns.
20987 OPERANDS points to the destination, source, and V2DI temporary
20988 register. CODE is either FLOAT or UNSIGNED_FLOAT. */
20991 convert_int_to_float128 (rtx
*operands
, enum rtx_code code
)
20993 rtx dest
= operands
[0];
20994 rtx src
= operands
[1];
20995 rtx tmp
= operands
[2];
21003 if (GET_CODE (tmp
) == SCRATCH
)
21004 tmp
= gen_reg_rtx (V2DImode
);
21007 src
= rs6000_address_for_fpconvert (src
);
21009 /* Generate the move of the integer into the Altivec register of the form:
21010 (set (tmp:V2DI) (unspec:V2DI [(src:SI)
21011 (const_int 0)] UNSPEC_IEEE128_MOVE)).
21014 (set (tmp:V2DI) (unspec:V2DI [(src:DI)] UNSPEC_IEEE128_MOVE)). */
21016 if (GET_MODE (src
) == SImode
)
21018 unsigned_flag
= (code
== UNSIGNED_FLOAT
) ? const1_rtx
: const0_rtx
;
21019 move_vec
= gen_rtvec (2, src
, unsigned_flag
);
21022 move_vec
= gen_rtvec (1, src
);
21024 move_unspec
= gen_rtx_UNSPEC (V2DImode
, move_vec
, UNSPEC_IEEE128_MOVE
);
21025 emit_insn (gen_rtx_SET (tmp
, move_unspec
));
21027 /* Generate the actual convert insn of the form:
21028 (set (dest:KF) (float:KF (unspec:DI [(tmp:V2DI)]
21029 UNSPEC_IEEE128_CONVERT))). */
21030 cvt_vec
= gen_rtvec (1, tmp
);
21031 cvt_unspec
= gen_rtx_UNSPEC (DImode
, cvt_vec
, UNSPEC_IEEE128_CONVERT
);
21032 cvt
= gen_rtx_fmt_e (code
, GET_MODE (dest
), cvt_unspec
);
21033 emit_insn (gen_rtx_SET (dest
, cvt
));
21037 /* Emit the RTL for an sISEL pattern. */
21040 rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
21042 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
21045 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
21046 can be used as that dest register. Return the dest register. */
21049 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
21051 if (op2
== const0_rtx
)
21054 if (GET_CODE (scratch
) == SCRATCH
)
21055 scratch
= gen_reg_rtx (mode
);
21057 if (logical_operand (op2
, mode
))
21058 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
21060 emit_insn (gen_rtx_SET (scratch
,
21061 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
21067 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
21070 machine_mode op_mode
;
21071 enum rtx_code cond_code
;
21072 rtx result
= operands
[0];
21074 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
21075 cond_code
= GET_CODE (condition_rtx
);
21077 if (FLOAT_MODE_P (mode
)
21078 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
21082 PUT_MODE (condition_rtx
, SImode
);
21083 t
= XEXP (condition_rtx
, 0);
21085 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
21087 if (cond_code
== NE
)
21088 emit_insn (gen_e500_flip_gt_bit (t
, t
));
21090 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
21094 if (cond_code
== NE
21095 || cond_code
== GE
|| cond_code
== LE
21096 || cond_code
== GEU
|| cond_code
== LEU
21097 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
21099 rtx not_result
= gen_reg_rtx (CCEQmode
);
21100 rtx not_op
, rev_cond_rtx
;
21101 machine_mode cc_mode
;
21103 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
21105 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
21106 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
21107 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
21108 emit_insn (gen_rtx_SET (not_result
, not_op
));
21109 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
21112 op_mode
= GET_MODE (XEXP (operands
[1], 0));
21113 if (op_mode
== VOIDmode
)
21114 op_mode
= GET_MODE (XEXP (operands
[1], 1));
21116 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
21118 PUT_MODE (condition_rtx
, DImode
);
21119 convert_move (result
, condition_rtx
, 0);
21123 PUT_MODE (condition_rtx
, SImode
);
21124 emit_insn (gen_rtx_SET (result
, condition_rtx
));
21128 /* Emit a branch of kind CODE to location LOC. */
21131 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
21133 rtx condition_rtx
, loc_ref
;
21135 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
21136 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
21137 emit_jump_insn (gen_rtx_SET (pc_rtx
,
21138 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
21139 loc_ref
, pc_rtx
)));
21142 /* Return the string to output a conditional branch to LABEL, which is
21143 the operand template of the label, or NULL if the branch is really a
21144 conditional return.
21146 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
21147 condition code register and its mode specifies what kind of
21148 comparison we made.
21150 REVERSED is nonzero if we should reverse the sense of the comparison.
21152 INSN is the insn. */
21155 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
21157 static char string
[64];
21158 enum rtx_code code
= GET_CODE (op
);
21159 rtx cc_reg
= XEXP (op
, 0);
21160 machine_mode mode
= GET_MODE (cc_reg
);
21161 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
21162 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
21163 int really_reversed
= reversed
^ need_longbranch
;
21169 validate_condition_mode (code
, mode
);
21171 /* Work out which way this really branches. We could use
21172 reverse_condition_maybe_unordered here always but this
21173 makes the resulting assembler clearer. */
21174 if (really_reversed
)
21176 /* Reversal of FP compares takes care -- an ordered compare
21177 becomes an unordered compare and vice versa. */
21178 if (mode
== CCFPmode
)
21179 code
= reverse_condition_maybe_unordered (code
);
21181 code
= reverse_condition (code
);
21184 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
21186 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
21191 /* Opposite of GT. */
21200 gcc_unreachable ();
21206 /* Not all of these are actually distinct opcodes, but
21207 we distinguish them for clarity of the resulting assembler. */
21208 case NE
: case LTGT
:
21209 ccode
= "ne"; break;
21210 case EQ
: case UNEQ
:
21211 ccode
= "eq"; break;
21213 ccode
= "ge"; break;
21214 case GT
: case GTU
: case UNGT
:
21215 ccode
= "gt"; break;
21217 ccode
= "le"; break;
21218 case LT
: case LTU
: case UNLT
:
21219 ccode
= "lt"; break;
21220 case UNORDERED
: ccode
= "un"; break;
21221 case ORDERED
: ccode
= "nu"; break;
21222 case UNGE
: ccode
= "nl"; break;
21223 case UNLE
: ccode
= "ng"; break;
21225 gcc_unreachable ();
21228 /* Maybe we have a guess as to how likely the branch is. */
21230 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
21231 if (note
!= NULL_RTX
)
21233 /* PROB is the difference from 50%. */
21234 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
21236 /* Only hint for highly probable/improbable branches on newer
21237 cpus as static prediction overrides processor dynamic
21238 prediction. For older cpus we may as well always hint, but
21239 assume not taken for branches that are very close to 50% as a
21240 mispredicted taken branch is more expensive than a
21241 mispredicted not-taken branch. */
21242 if (rs6000_always_hint
21243 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
21244 && br_prob_note_reliable_p (note
)))
21246 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
21247 && ((prob
> 0) ^ need_longbranch
))
21255 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
21257 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
21259 /* We need to escape any '%' characters in the reg_names string.
21260 Assume they'd only be the first character.... */
21261 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
21263 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
21267 /* If the branch distance was too far, we may have to use an
21268 unconditional branch to go the distance. */
21269 if (need_longbranch
)
21270 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
21272 s
+= sprintf (s
, ",%s", label
);
21278 /* Return the string to flip the GT bit on a CR. */
21280 output_e500_flip_gt_bit (rtx dst
, rtx src
)
21282 static char string
[64];
21285 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
21286 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
21289 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
21290 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
21292 sprintf (string
, "crnot %d,%d", a
, b
);
21296 /* Return insn for VSX or Altivec comparisons. */
21299 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
21302 machine_mode mode
= GET_MODE (op0
);
21310 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
21320 mask
= gen_reg_rtx (mode
);
21321 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
21328 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
21329 DMODE is expected destination mode. This is a recursive function. */
21332 rs6000_emit_vector_compare (enum rtx_code rcode
,
21334 machine_mode dmode
)
21337 bool swap_operands
= false;
21338 bool try_again
= false;
21340 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
21341 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
21343 /* See if the comparison works as is. */
21344 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
21352 swap_operands
= true;
21357 swap_operands
= true;
21365 /* Invert condition and try again.
21366 e.g., A != B becomes ~(A==B). */
21368 enum rtx_code rev_code
;
21369 enum insn_code nor_code
;
21372 rev_code
= reverse_condition_maybe_unordered (rcode
);
21373 if (rev_code
== UNKNOWN
)
21376 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
21377 if (nor_code
== CODE_FOR_nothing
)
21380 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
21384 mask
= gen_reg_rtx (dmode
);
21385 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
21393 /* Try GT/GTU/LT/LTU OR EQ */
21396 enum insn_code ior_code
;
21397 enum rtx_code new_code
;
21418 gcc_unreachable ();
21421 ior_code
= optab_handler (ior_optab
, dmode
);
21422 if (ior_code
== CODE_FOR_nothing
)
21425 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
21429 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
21433 mask
= gen_reg_rtx (dmode
);
21434 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
21445 std::swap (op0
, op1
);
21447 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
21452 /* You only get two chances. */
21456 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
21457 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
21458 operands for the relation operation COND. */
21461 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
21462 rtx cond
, rtx cc_op0
, rtx cc_op1
)
21464 machine_mode dest_mode
= GET_MODE (dest
);
21465 machine_mode mask_mode
= GET_MODE (cc_op0
);
21466 enum rtx_code rcode
= GET_CODE (cond
);
21467 machine_mode cc_mode
= CCmode
;
21471 bool invert_move
= false;
21473 if (VECTOR_UNIT_NONE_P (dest_mode
))
21476 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
21477 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
21481 /* Swap operands if we can, and fall back to doing the operation as
21482 specified, and doing a NOR to invert the test. */
21488 /* Invert condition and try again.
21489 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
21490 invert_move
= true;
21491 rcode
= reverse_condition_maybe_unordered (rcode
);
21492 if (rcode
== UNKNOWN
)
21496 /* Mark unsigned tests with CCUNSmode. */
21501 cc_mode
= CCUNSmode
;
21508 /* Get the vector mask for the given relational operations. */
21509 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
21517 op_true
= op_false
;
21521 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
21522 CONST0_RTX (dest_mode
));
21523 emit_insn (gen_rtx_SET (dest
,
21524 gen_rtx_IF_THEN_ELSE (dest_mode
,
21531 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
21532 operands of the last comparison is nonzero/true, FALSE_COND if it
21533 is zero/false. Return 0 if the hardware has no such operation. */
21536 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
21538 enum rtx_code code
= GET_CODE (op
);
21539 rtx op0
= XEXP (op
, 0);
21540 rtx op1
= XEXP (op
, 1);
21541 machine_mode compare_mode
= GET_MODE (op0
);
21542 machine_mode result_mode
= GET_MODE (dest
);
21544 bool is_against_zero
;
21546 /* These modes should always match. */
21547 if (GET_MODE (op1
) != compare_mode
21548 /* In the isel case however, we can use a compare immediate, so
21549 op1 may be a small constant. */
21550 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
21552 if (GET_MODE (true_cond
) != result_mode
)
21554 if (GET_MODE (false_cond
) != result_mode
)
21557 /* Don't allow using floating point comparisons for integer results for
21559 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
21562 /* First, work out if the hardware can do this at all, or
21563 if it's too slow.... */
21564 if (!FLOAT_MODE_P (compare_mode
))
21567 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
21570 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
21571 && SCALAR_FLOAT_MODE_P (compare_mode
))
21574 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
21576 /* A floating-point subtract might overflow, underflow, or produce
21577 an inexact result, thus changing the floating-point flags, so it
21578 can't be generated if we care about that. It's safe if one side
21579 of the construct is zero, since then no subtract will be
21581 if (SCALAR_FLOAT_MODE_P (compare_mode
)
21582 && flag_trapping_math
&& ! is_against_zero
)
21585 /* Eliminate half of the comparisons by switching operands, this
21586 makes the remaining code simpler. */
21587 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
21588 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
21590 code
= reverse_condition_maybe_unordered (code
);
21592 true_cond
= false_cond
;
21596 /* UNEQ and LTGT take four instructions for a comparison with zero,
21597 it'll probably be faster to use a branch here too. */
21598 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
21601 /* We're going to try to implement comparisons by performing
21602 a subtract, then comparing against zero. Unfortunately,
21603 Inf - Inf is NaN which is not zero, and so if we don't
21604 know that the operand is finite and the comparison
21605 would treat EQ different to UNORDERED, we can't do it. */
21606 if (HONOR_INFINITIES (compare_mode
)
21607 && code
!= GT
&& code
!= UNGE
21608 && (GET_CODE (op1
) != CONST_DOUBLE
21609 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1
)))
21610 /* Constructs of the form (a OP b ? a : b) are safe. */
21611 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
21612 || (! rtx_equal_p (op0
, true_cond
)
21613 && ! rtx_equal_p (op1
, true_cond
))))
21616 /* At this point we know we can use fsel. */
21618 /* Reduce the comparison to a comparison against zero. */
21619 if (! is_against_zero
)
21621 temp
= gen_reg_rtx (compare_mode
);
21622 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
21624 op1
= CONST0_RTX (compare_mode
);
21627 /* If we don't care about NaNs we can reduce some of the comparisons
21628 down to faster ones. */
21629 if (! HONOR_NANS (compare_mode
))
21635 true_cond
= false_cond
;
21648 /* Now, reduce everything down to a GE. */
21655 temp
= gen_reg_rtx (compare_mode
);
21656 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
21661 temp
= gen_reg_rtx (compare_mode
);
21662 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
21667 temp
= gen_reg_rtx (compare_mode
);
21668 emit_insn (gen_rtx_SET (temp
,
21669 gen_rtx_NEG (compare_mode
,
21670 gen_rtx_ABS (compare_mode
, op0
))));
21675 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
21676 temp
= gen_reg_rtx (result_mode
);
21677 emit_insn (gen_rtx_SET (temp
,
21678 gen_rtx_IF_THEN_ELSE (result_mode
,
21679 gen_rtx_GE (VOIDmode
,
21681 true_cond
, false_cond
)));
21682 false_cond
= true_cond
;
21685 temp
= gen_reg_rtx (compare_mode
);
21686 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
21691 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
21692 temp
= gen_reg_rtx (result_mode
);
21693 emit_insn (gen_rtx_SET (temp
,
21694 gen_rtx_IF_THEN_ELSE (result_mode
,
21695 gen_rtx_GE (VOIDmode
,
21697 true_cond
, false_cond
)));
21698 true_cond
= false_cond
;
21701 temp
= gen_reg_rtx (compare_mode
);
21702 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
21707 gcc_unreachable ();
21710 emit_insn (gen_rtx_SET (dest
,
21711 gen_rtx_IF_THEN_ELSE (result_mode
,
21712 gen_rtx_GE (VOIDmode
,
21714 true_cond
, false_cond
)));
21718 /* Same as above, but for ints (isel). */
21721 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
21723 rtx condition_rtx
, cr
;
21724 machine_mode mode
= GET_MODE (dest
);
21725 enum rtx_code cond_code
;
21726 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
21729 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
21732 /* We still have to do the compare, because isel doesn't do a
21733 compare, it just looks at the CRx bits set by a previous compare
21735 condition_rtx
= rs6000_generate_compare (op
, mode
);
21736 cond_code
= GET_CODE (condition_rtx
);
21737 cr
= XEXP (condition_rtx
, 0);
21738 signedp
= GET_MODE (cr
) == CCmode
;
21740 isel_func
= (mode
== SImode
21741 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
21742 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
21746 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
21747 /* isel handles these directly. */
21751 /* We need to swap the sense of the comparison. */
21753 std::swap (false_cond
, true_cond
);
21754 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
21759 false_cond
= force_reg (mode
, false_cond
);
21760 if (true_cond
!= const0_rtx
)
21761 true_cond
= force_reg (mode
, true_cond
);
21763 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
21769 output_isel (rtx
*operands
)
21771 enum rtx_code code
;
21773 code
= GET_CODE (operands
[1]);
21775 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
21777 gcc_assert (GET_CODE (operands
[2]) == REG
21778 && GET_CODE (operands
[3]) == REG
);
21779 PUT_CODE (operands
[1], reverse_condition (code
));
21780 return "isel %0,%3,%2,%j1";
21783 return "isel %0,%2,%3,%j1";
21787 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
21789 machine_mode mode
= GET_MODE (op0
);
21793 /* VSX/altivec have direct min/max insns. */
21794 if ((code
== SMAX
|| code
== SMIN
)
21795 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
21796 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
21798 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
21802 if (code
== SMAX
|| code
== SMIN
)
21807 if (code
== SMAX
|| code
== UMAX
)
21808 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
21809 op0
, op1
, mode
, 0);
21811 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
21812 op1
, op0
, mode
, 0);
21813 gcc_assert (target
);
21814 if (target
!= dest
)
21815 emit_move_insn (dest
, target
);
21818 /* A subroutine of the atomic operation splitters. Jump to LABEL if
21819 COND is true. Mark the jump as unlikely to be taken. */
21822 emit_unlikely_jump (rtx cond
, rtx label
)
21824 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
21827 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
21828 x
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
21829 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
21832 /* A subroutine of the atomic operation splitters. Emit a load-locked
21833 instruction in MODE. For QI/HImode, possibly use a pattern than includes
21834 the zero_extend operation. */
21837 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
21839 rtx (*fn
) (rtx
, rtx
) = NULL
;
21844 fn
= gen_load_lockedqi
;
21847 fn
= gen_load_lockedhi
;
21850 if (GET_MODE (mem
) == QImode
)
21851 fn
= gen_load_lockedqi_si
;
21852 else if (GET_MODE (mem
) == HImode
)
21853 fn
= gen_load_lockedhi_si
;
21855 fn
= gen_load_lockedsi
;
21858 fn
= gen_load_lockeddi
;
21861 fn
= gen_load_lockedti
;
21864 gcc_unreachable ();
21866 emit_insn (fn (reg
, mem
));
21869 /* A subroutine of the atomic operation splitters. Emit a store-conditional
21870 instruction in MODE. */
21873 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
21875 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
21880 fn
= gen_store_conditionalqi
;
21883 fn
= gen_store_conditionalhi
;
21886 fn
= gen_store_conditionalsi
;
21889 fn
= gen_store_conditionaldi
;
21892 fn
= gen_store_conditionalti
;
21895 gcc_unreachable ();
21898 /* Emit sync before stwcx. to address PPC405 Erratum. */
21899 if (PPC405_ERRATUM77
)
21900 emit_insn (gen_hwsync ());
21902 emit_insn (fn (res
, mem
, val
));
21905 /* Expand barriers before and after a load_locked/store_cond sequence. */
21908 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
21910 rtx addr
= XEXP (mem
, 0);
21911 int strict_p
= (reload_in_progress
|| reload_completed
);
21913 if (!legitimate_indirect_address_p (addr
, strict_p
)
21914 && !legitimate_indexed_address_p (addr
, strict_p
))
21916 addr
= force_reg (Pmode
, addr
);
21917 mem
= replace_equiv_address_nv (mem
, addr
);
21922 case MEMMODEL_RELAXED
:
21923 case MEMMODEL_CONSUME
:
21924 case MEMMODEL_ACQUIRE
:
21926 case MEMMODEL_RELEASE
:
21927 case MEMMODEL_ACQ_REL
:
21928 emit_insn (gen_lwsync ());
21930 case MEMMODEL_SEQ_CST
:
21931 emit_insn (gen_hwsync ());
21934 gcc_unreachable ();
21940 rs6000_post_atomic_barrier (enum memmodel model
)
21944 case MEMMODEL_RELAXED
:
21945 case MEMMODEL_CONSUME
:
21946 case MEMMODEL_RELEASE
:
21948 case MEMMODEL_ACQUIRE
:
21949 case MEMMODEL_ACQ_REL
:
21950 case MEMMODEL_SEQ_CST
:
21951 emit_insn (gen_isync ());
21954 gcc_unreachable ();
21958 /* A subroutine of the various atomic expanders. For sub-word operations,
21959 we must adjust things to operate on SImode. Given the original MEM,
21960 return a new aligned memory. Also build and return the quantities by
21961 which to shift and mask. */
21964 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
21966 rtx addr
, align
, shift
, mask
, mem
;
21967 HOST_WIDE_INT shift_mask
;
21968 machine_mode mode
= GET_MODE (orig_mem
);
21970 /* For smaller modes, we have to implement this via SImode. */
21971 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
21973 addr
= XEXP (orig_mem
, 0);
21974 addr
= force_reg (GET_MODE (addr
), addr
);
21976 /* Aligned memory containing subword. Generate a new memory. We
21977 do not want any of the existing MEM_ATTR data, as we're now
21978 accessing memory outside the original object. */
21979 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
21980 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21981 mem
= gen_rtx_MEM (SImode
, align
);
21982 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
21983 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
21984 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
21986 /* Shift amount for subword relative to aligned word. */
21987 shift
= gen_reg_rtx (SImode
);
21988 addr
= gen_lowpart (SImode
, addr
);
21989 rtx tmp
= gen_reg_rtx (SImode
);
21990 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
21991 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
21992 if (BYTES_BIG_ENDIAN
)
21993 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
21994 shift
, 1, OPTAB_LIB_WIDEN
);
21997 /* Mask for insertion. */
21998 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
21999 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22005 /* A subroutine of the various atomic expanders. For sub-word operands,
22006 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
22009 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
22013 x
= gen_reg_rtx (SImode
);
22014 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
22015 gen_rtx_NOT (SImode
, mask
),
22018 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
22023 /* A subroutine of the various atomic expanders. For sub-word operands,
22024 extract WIDE to NARROW via SHIFT. */
22027 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
22029 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
22030 wide
, 1, OPTAB_LIB_WIDEN
);
22031 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
22034 /* Expand an atomic compare and swap operation. */
22037 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
22039 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
22040 rtx label1
, label2
, x
, mask
, shift
;
22041 machine_mode mode
, orig_mode
;
22042 enum memmodel mod_s
, mod_f
;
22045 boolval
= operands
[0];
22046 retval
= operands
[1];
22048 oldval
= operands
[3];
22049 newval
= operands
[4];
22050 is_weak
= (INTVAL (operands
[5]) != 0);
22051 mod_s
= memmodel_base (INTVAL (operands
[6]));
22052 mod_f
= memmodel_base (INTVAL (operands
[7]));
22053 orig_mode
= mode
= GET_MODE (mem
);
22055 mask
= shift
= NULL_RTX
;
22056 if (mode
== QImode
|| mode
== HImode
)
22058 /* Before power8, we didn't have access to lbarx/lharx, so generate a
22059 lwarx and shift/mask operations. With power8, we need to do the
22060 comparison in SImode, but the store is still done in QI/HImode. */
22061 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
22063 if (!TARGET_SYNC_HI_QI
)
22065 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
22067 /* Shift and mask OLDVAL into position with the word. */
22068 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
22069 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22071 /* Shift and mask NEWVAL into position within the word. */
22072 newval
= convert_modes (SImode
, mode
, newval
, 1);
22073 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
22074 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22077 /* Prepare to adjust the return value. */
22078 retval
= gen_reg_rtx (SImode
);
22081 else if (reg_overlap_mentioned_p (retval
, oldval
))
22082 oldval
= copy_to_reg (oldval
);
22084 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
22089 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
22090 emit_label (XEXP (label1
, 0));
22092 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
22094 emit_load_locked (mode
, retval
, mem
);
22099 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
22100 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22103 cond
= gen_reg_rtx (CCmode
);
22104 /* If we have TImode, synthesize a comparison. */
22105 if (mode
!= TImode
)
22106 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
22109 rtx xor1_result
= gen_reg_rtx (DImode
);
22110 rtx xor2_result
= gen_reg_rtx (DImode
);
22111 rtx or_result
= gen_reg_rtx (DImode
);
22112 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
22113 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
22114 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
22115 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
22117 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
22118 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
22119 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
22120 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
22123 emit_insn (gen_rtx_SET (cond
, x
));
22125 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
22126 emit_unlikely_jump (x
, label2
);
22130 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
22132 emit_store_conditional (orig_mode
, cond
, mem
, x
);
22136 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
22137 emit_unlikely_jump (x
, label1
);
22140 if (!is_mm_relaxed (mod_f
))
22141 emit_label (XEXP (label2
, 0));
22143 rs6000_post_atomic_barrier (mod_s
);
22145 if (is_mm_relaxed (mod_f
))
22146 emit_label (XEXP (label2
, 0));
22149 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
22150 else if (mode
!= GET_MODE (operands
[1]))
22151 convert_move (operands
[1], retval
, 1);
22153 /* In all cases, CR0 contains EQ on success, and NE on failure. */
22154 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
22155 emit_insn (gen_rtx_SET (boolval
, x
));
22158 /* Expand an atomic exchange operation. */
22161 rs6000_expand_atomic_exchange (rtx operands
[])
22163 rtx retval
, mem
, val
, cond
;
22165 enum memmodel model
;
22166 rtx label
, x
, mask
, shift
;
22168 retval
= operands
[0];
22171 model
= memmodel_base (INTVAL (operands
[3]));
22172 mode
= GET_MODE (mem
);
22174 mask
= shift
= NULL_RTX
;
22175 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
22177 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
22179 /* Shift and mask VAL into position with the word. */
22180 val
= convert_modes (SImode
, mode
, val
, 1);
22181 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
22182 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22184 /* Prepare to adjust the return value. */
22185 retval
= gen_reg_rtx (SImode
);
22189 mem
= rs6000_pre_atomic_barrier (mem
, model
);
22191 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
22192 emit_label (XEXP (label
, 0));
22194 emit_load_locked (mode
, retval
, mem
);
22198 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
22200 cond
= gen_reg_rtx (CCmode
);
22201 emit_store_conditional (mode
, cond
, mem
, x
);
22203 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
22204 emit_unlikely_jump (x
, label
);
22206 rs6000_post_atomic_barrier (model
);
22209 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
22212 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
22213 to perform. MEM is the memory on which to operate. VAL is the second
22214 operand of the binary operator. BEFORE and AFTER are optional locations to
22215 return the value of MEM either before of after the operation. MODEL_RTX
22216 is a CONST_INT containing the memory model to use. */
22219 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
22220 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
22222 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
22223 machine_mode mode
= GET_MODE (mem
);
22224 machine_mode store_mode
= mode
;
22225 rtx label
, x
, cond
, mask
, shift
;
22226 rtx before
= orig_before
, after
= orig_after
;
22228 mask
= shift
= NULL_RTX
;
22229 /* On power8, we want to use SImode for the operation. On previous systems,
22230 use the operation in a subword and shift/mask to get the proper byte or
22232 if (mode
== QImode
|| mode
== HImode
)
22234 if (TARGET_SYNC_HI_QI
)
22236 val
= convert_modes (SImode
, mode
, val
, 1);
22238 /* Prepare to adjust the return value. */
22239 before
= gen_reg_rtx (SImode
);
22241 after
= gen_reg_rtx (SImode
);
22246 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
22248 /* Shift and mask VAL into position with the word. */
22249 val
= convert_modes (SImode
, mode
, val
, 1);
22250 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
22251 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22257 /* We've already zero-extended VAL. That is sufficient to
22258 make certain that it does not affect other bits. */
22263 /* If we make certain that all of the other bits in VAL are
22264 set, that will be sufficient to not affect other bits. */
22265 x
= gen_rtx_NOT (SImode
, mask
);
22266 x
= gen_rtx_IOR (SImode
, x
, val
);
22267 emit_insn (gen_rtx_SET (val
, x
));
22274 /* These will all affect bits outside the field and need
22275 adjustment via MASK within the loop. */
22279 gcc_unreachable ();
22282 /* Prepare to adjust the return value. */
22283 before
= gen_reg_rtx (SImode
);
22285 after
= gen_reg_rtx (SImode
);
22286 store_mode
= mode
= SImode
;
22290 mem
= rs6000_pre_atomic_barrier (mem
, model
);
22292 label
= gen_label_rtx ();
22293 emit_label (label
);
22294 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
22296 if (before
== NULL_RTX
)
22297 before
= gen_reg_rtx (mode
);
22299 emit_load_locked (mode
, before
, mem
);
22303 x
= expand_simple_binop (mode
, AND
, before
, val
,
22304 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22305 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
22309 after
= expand_simple_binop (mode
, code
, before
, val
,
22310 after
, 1, OPTAB_LIB_WIDEN
);
22316 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
22317 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
22318 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
22320 else if (store_mode
!= mode
)
22321 x
= convert_modes (store_mode
, mode
, x
, 1);
22323 cond
= gen_reg_rtx (CCmode
);
22324 emit_store_conditional (store_mode
, cond
, mem
, x
);
22326 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
22327 emit_unlikely_jump (x
, label
);
22329 rs6000_post_atomic_barrier (model
);
22333 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
22334 then do the calcuations in a SImode register. */
22336 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
22338 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
22340 else if (store_mode
!= mode
)
22342 /* QImode/HImode on machines with lbarx/lharx where we do the native
22343 operation and then do the calcuations in a SImode register. */
22345 convert_move (orig_before
, before
, 1);
22347 convert_move (orig_after
, after
, 1);
22349 else if (orig_after
&& after
!= orig_after
)
22350 emit_move_insn (orig_after
, after
);
22353 /* Emit instructions to move SRC to DST. Called by splitters for
22354 multi-register moves. It will emit at most one instruction for
22355 each register that is accessed; that is, it won't emit li/lis pairs
22356 (or equivalent for 64-bit code). One of SRC or DST must be a hard
22360 rs6000_split_multireg_move (rtx dst
, rtx src
)
22362 /* The register number of the first register being moved. */
22364 /* The mode that is to be moved. */
22366 /* The mode that the move is being done in, and its size. */
22367 machine_mode reg_mode
;
22369 /* The number of registers that will be moved. */
22372 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
22373 mode
= GET_MODE (dst
);
22374 nregs
= hard_regno_nregs
[reg
][mode
];
22375 if (FP_REGNO_P (reg
))
22376 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
22377 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
22378 else if (ALTIVEC_REGNO_P (reg
))
22379 reg_mode
= V16QImode
;
22380 else if (TARGET_E500_DOUBLE
&& FLOAT128_2REG_P (mode
))
22383 reg_mode
= word_mode
;
22384 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
22386 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
22388 /* TDmode residing in FP registers is special, since the ISA requires that
22389 the lower-numbered word of a register pair is always the most significant
22390 word, even in little-endian mode. This does not match the usual subreg
22391 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
22392 the appropriate constituent registers "by hand" in little-endian mode.
22394 Note we do not need to check for destructive overlap here since TDmode
22395 can only reside in even/odd register pairs. */
22396 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
22401 for (i
= 0; i
< nregs
; i
++)
22403 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
22404 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
22406 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
22407 i
* reg_mode_size
);
22409 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
22410 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
22412 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
22413 i
* reg_mode_size
);
22415 emit_insn (gen_rtx_SET (p_dst
, p_src
));
22421 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
22423 /* Move register range backwards, if we might have destructive
22426 for (i
= nregs
- 1; i
>= 0; i
--)
22427 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
22428 i
* reg_mode_size
),
22429 simplify_gen_subreg (reg_mode
, src
, mode
,
22430 i
* reg_mode_size
)));
22436 bool used_update
= false;
22437 rtx restore_basereg
= NULL_RTX
;
22439 if (MEM_P (src
) && INT_REGNO_P (reg
))
22443 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
22444 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
22447 breg
= XEXP (XEXP (src
, 0), 0);
22448 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
22449 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
22450 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
22451 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
22452 src
= replace_equiv_address (src
, breg
);
22454 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
22456 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
22458 rtx basereg
= XEXP (XEXP (src
, 0), 0);
22461 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
22462 emit_insn (gen_rtx_SET (ndst
,
22463 gen_rtx_MEM (reg_mode
,
22465 used_update
= true;
22468 emit_insn (gen_rtx_SET (basereg
,
22469 XEXP (XEXP (src
, 0), 1)));
22470 src
= replace_equiv_address (src
, basereg
);
22474 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
22475 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
22476 src
= replace_equiv_address (src
, basereg
);
22480 breg
= XEXP (src
, 0);
22481 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
22482 breg
= XEXP (breg
, 0);
22484 /* If the base register we are using to address memory is
22485 also a destination reg, then change that register last. */
22487 && REGNO (breg
) >= REGNO (dst
)
22488 && REGNO (breg
) < REGNO (dst
) + nregs
)
22489 j
= REGNO (breg
) - REGNO (dst
);
22491 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
22495 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
22496 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
22499 breg
= XEXP (XEXP (dst
, 0), 0);
22500 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
22501 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
22502 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
22504 /* We have to update the breg before doing the store.
22505 Use store with update, if available. */
22509 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
22510 emit_insn (TARGET_32BIT
22511 ? (TARGET_POWERPC64
22512 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
22513 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
22514 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
22515 used_update
= true;
22518 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
22519 dst
= replace_equiv_address (dst
, breg
);
22521 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
22522 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
22524 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
22526 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
22529 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
22530 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
22533 used_update
= true;
22536 emit_insn (gen_rtx_SET (basereg
,
22537 XEXP (XEXP (dst
, 0), 1)));
22538 dst
= replace_equiv_address (dst
, basereg
);
22542 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
22543 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
22544 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
22546 && REG_P (offsetreg
)
22547 && REGNO (basereg
) != REGNO (offsetreg
));
22548 if (REGNO (basereg
) == 0)
22550 rtx tmp
= offsetreg
;
22551 offsetreg
= basereg
;
22554 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
22555 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
22556 dst
= replace_equiv_address (dst
, basereg
);
22559 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
22560 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
22563 for (i
= 0; i
< nregs
; i
++)
22565 /* Calculate index to next subword. */
22570 /* If compiler already emitted move of first word by
22571 store with update, no need to do anything. */
22572 if (j
== 0 && used_update
)
22575 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
22576 j
* reg_mode_size
),
22577 simplify_gen_subreg (reg_mode
, src
, mode
,
22578 j
* reg_mode_size
)));
22580 if (restore_basereg
!= NULL_RTX
)
22581 emit_insn (restore_basereg
);
22586 /* This page contains routines that are used to determine what the
22587 function prologue and epilogue code will do and write them out. */
22592 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
22595 /* Determine whether the gp REG is really used. */
22598 rs6000_reg_live_or_pic_offset_p (int reg
)
22600 /* We need to mark the PIC offset register live for the same conditions
22601 as it is set up, or otherwise it won't be saved before we clobber it. */
22603 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
&& !TARGET_SINGLE_PIC_BASE
)
22605 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
22606 && (crtl
->calls_eh_return
22607 || df_regs_ever_live_p (reg
)
22608 || get_pool_size ()))
22611 if ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
22616 /* If the function calls eh_return, claim used all the registers that would
22617 be checked for liveness otherwise. */
22619 return ((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22620 && !call_used_regs
[reg
]);
22623 /* Return the first fixed-point register that is required to be
22624 saved. 32 if none. */
22627 first_reg_to_save (void)
22631 /* Find lowest numbered live register. */
22632 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
22633 if (save_reg_p (first_reg
))
22636 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
22637 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22638 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
22639 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
22640 && rs6000_reg_live_or_pic_offset_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
22641 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
22645 && crtl
->uses_pic_offset_table
22646 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
22647 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
22653 /* Similar, for FP regs. */
22656 first_fp_reg_to_save (void)
22660 /* Find lowest numbered live register. */
22661 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
22662 if (save_reg_p (first_reg
))
22668 /* Similar, for AltiVec regs. */
22671 first_altivec_reg_to_save (void)
22675 /* Stack frame remains as is unless we are in AltiVec ABI. */
22676 if (! TARGET_ALTIVEC_ABI
)
22677 return LAST_ALTIVEC_REGNO
+ 1;
22679 /* On Darwin, the unwind routines are compiled without
22680 TARGET_ALTIVEC, and use save_world to save/restore the
22681 altivec registers when necessary. */
22682 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
22683 && ! TARGET_ALTIVEC
)
22684 return FIRST_ALTIVEC_REGNO
+ 20;
22686 /* Find lowest numbered live register. */
22687 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22688 if (save_reg_p (i
))
22694 /* Return a 32-bit mask of the AltiVec registers we need to set in
22695 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
22696 the 32-bit word is 0. */
22698 static unsigned int
22699 compute_vrsave_mask (void)
22701 unsigned int i
, mask
= 0;
22703 /* On Darwin, the unwind routines are compiled without
22704 TARGET_ALTIVEC, and use save_world to save/restore the
22705 call-saved altivec registers when necessary. */
22706 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
22707 && ! TARGET_ALTIVEC
)
22710 /* First, find out if we use _any_ altivec registers. */
22711 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22712 if (df_regs_ever_live_p (i
))
22713 mask
|= ALTIVEC_REG_BIT (i
);
22718 /* Next, remove the argument registers from the set. These must
22719 be in the VRSAVE mask set by the caller, so we don't need to add
22720 them in again. More importantly, the mask we compute here is
22721 used to generate CLOBBERs in the set_vrsave insn, and we do not
22722 wish the argument registers to die. */
22723 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
22724 mask
&= ~ALTIVEC_REG_BIT (i
);
22726 /* Similarly, remove the return value from the set. */
22729 diddle_return_value (is_altivec_return_reg
, &yes
);
22731 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
22737 /* For a very restricted set of circumstances, we can cut down the
22738 size of prologues/epilogues by calling our own save/restore-the-world
22742 compute_save_world_info (rs6000_stack_t
*info_ptr
)
22744 info_ptr
->world_save_p
= 1;
22745 info_ptr
->world_save_p
22746 = (WORLD_SAVE_P (info_ptr
)
22747 && DEFAULT_ABI
== ABI_DARWIN
22748 && !cfun
->has_nonlocal_label
22749 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
22750 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
22751 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
22752 && info_ptr
->cr_save_p
);
22754 /* This will not work in conjunction with sibcalls. Make sure there
22755 are none. (This check is expensive, but seldom executed.) */
22756 if (WORLD_SAVE_P (info_ptr
))
22759 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
22760 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
22762 info_ptr
->world_save_p
= 0;
22767 if (WORLD_SAVE_P (info_ptr
))
22769 /* Even if we're not touching VRsave, make sure there's room on the
22770 stack for it, if it looks like we're calling SAVE_WORLD, which
22771 will attempt to save it. */
22772 info_ptr
->vrsave_size
= 4;
22774 /* If we are going to save the world, we need to save the link register too. */
22775 info_ptr
->lr_save_p
= 1;
22777 /* "Save" the VRsave register too if we're saving the world. */
22778 if (info_ptr
->vrsave_mask
== 0)
22779 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
22781 /* Because the Darwin register save/restore routines only handle
22782 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
22784 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
22785 && (info_ptr
->first_altivec_reg_save
22786 >= FIRST_SAVED_ALTIVEC_REGNO
));
22793 is_altivec_return_reg (rtx reg
, void *xyes
)
22795 bool *yes
= (bool *) xyes
;
22796 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
22801 /* Look for user-defined global regs in the range FIRST to LAST-1.
22802 We should not restore these, and so cannot use lmw or out-of-line
22803 restore functions if there are any. We also can't save them
22804 (well, emit frame notes for them), because frame unwinding during
22805 exception handling will restore saved registers. */
22808 global_regs_p (unsigned first
, unsigned last
)
22810 while (first
< last
)
22811 if (global_regs
[first
++])
22816 /* Determine the strategy for savings/restoring registers. */
22819 SAVRES_MULTIPLE
= 0x1,
22820 SAVE_INLINE_FPRS
= 0x2,
22821 SAVE_INLINE_GPRS
= 0x4,
22822 REST_INLINE_FPRS
= 0x8,
22823 REST_INLINE_GPRS
= 0x10,
22824 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
22825 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
22826 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
22827 SAVE_INLINE_VRS
= 0x100,
22828 REST_INLINE_VRS
= 0x200
22832 rs6000_savres_strategy (rs6000_stack_t
*info
,
22833 bool using_static_chain_p
)
22838 if (TARGET_MULTIPLE
22839 && !TARGET_POWERPC64
22840 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
22841 && info
->first_gp_reg_save
< 31
22842 && !global_regs_p (info
->first_gp_reg_save
, 32))
22843 strategy
|= SAVRES_MULTIPLE
;
22845 if (crtl
->calls_eh_return
22846 || cfun
->machine
->ra_need_lr
)
22847 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
22848 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
22849 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
22851 if (info
->first_fp_reg_save
== 64
22852 /* The out-of-line FP routines use double-precision stores;
22853 we can't use those routines if we don't have such stores. */
22854 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
22855 || global_regs_p (info
->first_fp_reg_save
, 64))
22856 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22858 if (info
->first_gp_reg_save
== 32
22859 || (!(strategy
& SAVRES_MULTIPLE
)
22860 && global_regs_p (info
->first_gp_reg_save
, 32)))
22861 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22863 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
22864 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
22865 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22867 /* Define cutoff for using out-of-line functions to save registers. */
22868 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
22870 if (!optimize_size
)
22872 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22873 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22874 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22878 /* Prefer out-of-line restore if it will exit. */
22879 if (info
->first_fp_reg_save
> 61)
22880 strategy
|= SAVE_INLINE_FPRS
;
22881 if (info
->first_gp_reg_save
> 29)
22883 if (info
->first_fp_reg_save
== 64)
22884 strategy
|= SAVE_INLINE_GPRS
;
22886 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22888 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
22889 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22892 else if (DEFAULT_ABI
== ABI_DARWIN
)
22894 if (info
->first_fp_reg_save
> 60)
22895 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22896 if (info
->first_gp_reg_save
> 29)
22897 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22898 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22902 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
22903 if (info
->first_fp_reg_save
> 61)
22904 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22905 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22906 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22909 /* Don't bother to try to save things out-of-line if r11 is occupied
22910 by the static chain. It would require too much fiddling and the
22911 static chain is rarely used anyway. FPRs are saved w.r.t the stack
22912 pointer on Darwin, and AIX uses r1 or r12. */
22913 if (using_static_chain_p
22914 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
22915 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
22917 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
22919 /* We can only use the out-of-line routines to restore if we've
22920 saved all the registers from first_fp_reg_save in the prologue.
22921 Otherwise, we risk loading garbage. */
22922 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
22926 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
22927 if (!save_reg_p (i
))
22929 strategy
|= REST_INLINE_FPRS
;
22934 /* If we are going to use store multiple, then don't even bother
22935 with the out-of-line routines, since the store-multiple
22936 instruction will always be smaller. */
22937 if ((strategy
& SAVRES_MULTIPLE
))
22938 strategy
|= SAVE_INLINE_GPRS
;
22940 /* info->lr_save_p isn't yet set if the only reason lr needs to be
22941 saved is an out-of-line save or restore. Set up the value for
22942 the next test (excluding out-of-line gpr restore). */
22943 lr_save_p
= (info
->lr_save_p
22944 || !(strategy
& SAVE_INLINE_GPRS
)
22945 || !(strategy
& SAVE_INLINE_FPRS
)
22946 || !(strategy
& SAVE_INLINE_VRS
)
22947 || !(strategy
& REST_INLINE_FPRS
)
22948 || !(strategy
& REST_INLINE_VRS
));
22950 /* The situation is more complicated with load multiple. We'd
22951 prefer to use the out-of-line routines for restores, since the
22952 "exit" out-of-line routines can handle the restore of LR and the
22953 frame teardown. However if doesn't make sense to use the
22954 out-of-line routine if that is the only reason we'd need to save
22955 LR, and we can't use the "exit" out-of-line gpr restore if we
22956 have saved some fprs; In those cases it is advantageous to use
22957 load multiple when available. */
22958 if ((strategy
& SAVRES_MULTIPLE
)
22960 || info
->first_fp_reg_save
!= 64))
22961 strategy
|= REST_INLINE_GPRS
;
22963 /* Saving CR interferes with the exit routines used on the SPE, so
22966 && info
->spe_64bit_regs_used
22967 && info
->cr_save_p
)
22968 strategy
|= REST_INLINE_GPRS
;
22970 /* We can only use load multiple or the out-of-line routines to
22971 restore if we've used store multiple or out-of-line routines
22972 in the prologue, i.e. if we've saved all the registers from
22973 first_gp_reg_save. Otherwise, we risk loading garbage. */
22974 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
22975 == SAVE_INLINE_GPRS
)
22979 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
22980 if (!save_reg_p (i
))
22982 strategy
|= REST_INLINE_GPRS
;
22987 if (TARGET_ELF
&& TARGET_64BIT
)
22989 if (!(strategy
& SAVE_INLINE_FPRS
))
22990 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
22991 else if (!(strategy
& SAVE_INLINE_GPRS
)
22992 && info
->first_fp_reg_save
== 64)
22993 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
22995 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
22996 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
22998 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
22999 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
23004 /* Calculate the stack information for the current function. This is
23005 complicated by having two separate calling sequences, the AIX calling
23006 sequence and the V.4 calling sequence.
23008 AIX (and Darwin/Mac OS X) stack frames look like:
23010 SP----> +---------------------------------------+
23011 | back chain to caller | 0 0
23012 +---------------------------------------+
23013 | saved CR | 4 8 (8-11)
23014 +---------------------------------------+
23016 +---------------------------------------+
23017 | reserved for compilers | 12 24
23018 +---------------------------------------+
23019 | reserved for binders | 16 32
23020 +---------------------------------------+
23021 | saved TOC pointer | 20 40
23022 +---------------------------------------+
23023 | Parameter save area (P) | 24 48
23024 +---------------------------------------+
23025 | Alloca space (A) | 24+P etc.
23026 +---------------------------------------+
23027 | Local variable space (L) | 24+P+A
23028 +---------------------------------------+
23029 | Float/int conversion temporary (X) | 24+P+A+L
23030 +---------------------------------------+
23031 | Save area for AltiVec registers (W) | 24+P+A+L+X
23032 +---------------------------------------+
23033 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
23034 +---------------------------------------+
23035 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
23036 +---------------------------------------+
23037 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
23038 +---------------------------------------+
23039 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
23040 +---------------------------------------+
23041 old SP->| back chain to caller's caller |
23042 +---------------------------------------+
23044 The required alignment for AIX configurations is two words (i.e., 8
23047 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
23049 SP----> +---------------------------------------+
23050 | Back chain to caller | 0
23051 +---------------------------------------+
23052 | Save area for CR | 8
23053 +---------------------------------------+
23055 +---------------------------------------+
23056 | Saved TOC pointer | 24
23057 +---------------------------------------+
23058 | Parameter save area (P) | 32
23059 +---------------------------------------+
23060 | Alloca space (A) | 32+P
23061 +---------------------------------------+
23062 | Local variable space (L) | 32+P+A
23063 +---------------------------------------+
23064 | Save area for AltiVec registers (W) | 32+P+A+L
23065 +---------------------------------------+
23066 | AltiVec alignment padding (Y) | 32+P+A+L+W
23067 +---------------------------------------+
23068 | Save area for GP registers (G) | 32+P+A+L+W+Y
23069 +---------------------------------------+
23070 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
23071 +---------------------------------------+
23072 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
23073 +---------------------------------------+
23076 V.4 stack frames look like:
23078 SP----> +---------------------------------------+
23079 | back chain to caller | 0
23080 +---------------------------------------+
23081 | caller's saved LR | 4
23082 +---------------------------------------+
23083 | Parameter save area (P) | 8
23084 +---------------------------------------+
23085 | Alloca space (A) | 8+P
23086 +---------------------------------------+
23087 | Varargs save area (V) | 8+P+A
23088 +---------------------------------------+
23089 | Local variable space (L) | 8+P+A+V
23090 +---------------------------------------+
23091 | Float/int conversion temporary (X) | 8+P+A+V+L
23092 +---------------------------------------+
23093 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
23094 +---------------------------------------+
23095 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
23096 +---------------------------------------+
23097 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
23098 +---------------------------------------+
23099 | SPE: area for 64-bit GP registers |
23100 +---------------------------------------+
23101 | SPE alignment padding |
23102 +---------------------------------------+
23103 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
23104 +---------------------------------------+
23105 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
23106 +---------------------------------------+
23107 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
23108 +---------------------------------------+
23109 old SP->| back chain to caller's caller |
23110 +---------------------------------------+
23112 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
23113 given. (But note below and in sysv4.h that we require only 8 and
23114 may round up the size of our stack frame anyways. The historical
23115 reason is early versions of powerpc-linux which didn't properly
23116 align the stack at program startup. A happy side-effect is that
23117 -mno-eabi libraries can be used with -meabi programs.)
23119 The EABI configuration defaults to the V.4 layout. However,
23120 the stack alignment requirements may differ. If -mno-eabi is not
23121 given, the required stack alignment is 8 bytes; if -mno-eabi is
23122 given, the required alignment is 16 bytes. (But see V.4 comment
23125 #ifndef ABI_STACK_BOUNDARY
23126 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
23129 static rs6000_stack_t
*
23130 rs6000_stack_info (void)
23132 /* We should never be called for thunks, we are not set up for that. */
23133 gcc_assert (!cfun
->is_thunk
);
23135 rs6000_stack_t
*info_ptr
= &stack_info
;
23136 int reg_size
= TARGET_32BIT
? 4 : 8;
23141 HOST_WIDE_INT non_fixed_size
;
23142 bool using_static_chain_p
;
23144 if (reload_completed
&& info_ptr
->reload_completed
)
23147 memset (info_ptr
, 0, sizeof (*info_ptr
));
23148 info_ptr
->reload_completed
= reload_completed
;
23152 /* Cache value so we don't rescan instruction chain over and over. */
23153 if (cfun
->machine
->insn_chain_scanned_p
== 0)
23154 cfun
->machine
->insn_chain_scanned_p
23155 = spe_func_has_64bit_regs_p () + 1;
23156 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
23159 /* Select which calling sequence. */
23160 info_ptr
->abi
= DEFAULT_ABI
;
23162 /* Calculate which registers need to be saved & save area size. */
23163 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
23164 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
23165 even if it currently looks like we won't. Reload may need it to
23166 get at a constant; if so, it will have already created a constant
23167 pool entry for it. */
23168 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
23169 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
23170 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
23171 && crtl
->uses_const_pool
23172 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
23173 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
23175 first_gp
= info_ptr
->first_gp_reg_save
;
23177 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
23179 /* For the SPE, we have an additional upper 32-bits on each GPR.
23180 Ideally we should save the entire 64-bits only when the upper
23181 half is used in SIMD instructions. Since we only record
23182 registers live (not the size they are used in), this proves
23183 difficult because we'd have to traverse the instruction chain at
23184 the right time, taking reload into account. This is a real pain,
23185 so we opt to save the GPRs in 64-bits always if but one register
23186 gets used in 64-bits. Otherwise, all the registers in the frame
23187 get saved in 32-bits.
23189 So... since when we save all GPRs (except the SP) in 64-bits, the
23190 traditional GP save area will be empty. */
23191 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
23192 info_ptr
->gp_size
= 0;
23194 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
23195 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
23197 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
23198 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
23199 - info_ptr
->first_altivec_reg_save
);
23201 /* Does this function call anything? */
23202 info_ptr
->calls_p
= (! crtl
->is_leaf
23203 || cfun
->machine
->ra_needs_full_frame
);
23205 /* Determine if we need to save the condition code registers. */
23206 if (df_regs_ever_live_p (CR2_REGNO
)
23207 || df_regs_ever_live_p (CR3_REGNO
)
23208 || df_regs_ever_live_p (CR4_REGNO
))
23210 info_ptr
->cr_save_p
= 1;
23211 if (DEFAULT_ABI
== ABI_V4
)
23212 info_ptr
->cr_size
= reg_size
;
23215 /* If the current function calls __builtin_eh_return, then we need
23216 to allocate stack space for registers that will hold data for
23217 the exception handler. */
23218 if (crtl
->calls_eh_return
)
23221 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
23224 /* SPE saves EH registers in 64-bits. */
23225 ehrd_size
= i
* (TARGET_SPE_ABI
23226 && info_ptr
->spe_64bit_regs_used
!= 0
23227 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
23232 /* In the ELFv2 ABI, we also need to allocate space for separate
23233 CR field save areas if the function calls __builtin_eh_return. */
23234 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23236 /* This hard-codes that we have three call-saved CR fields. */
23237 ehcr_size
= 3 * reg_size
;
23238 /* We do *not* use the regular CR save mechanism. */
23239 info_ptr
->cr_save_p
= 0;
23244 /* Determine various sizes. */
23245 info_ptr
->reg_size
= reg_size
;
23246 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
23247 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
23248 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
23249 TARGET_ALTIVEC
? 16 : 8);
23250 if (FRAME_GROWS_DOWNWARD
)
23251 info_ptr
->vars_size
23252 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
23253 + info_ptr
->parm_size
,
23254 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
23255 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
23256 + info_ptr
->parm_size
);
23258 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
23259 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
23261 info_ptr
->spe_gp_size
= 0;
23263 if (TARGET_ALTIVEC_ABI
)
23264 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
23266 info_ptr
->vrsave_mask
= 0;
23268 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
23269 info_ptr
->vrsave_size
= 4;
23271 info_ptr
->vrsave_size
= 0;
23273 compute_save_world_info (info_ptr
);
23275 /* Calculate the offsets. */
23276 switch (DEFAULT_ABI
)
23280 gcc_unreachable ();
23285 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
23286 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
23288 if (TARGET_ALTIVEC_ABI
)
23290 info_ptr
->vrsave_save_offset
23291 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
23293 /* Align stack so vector save area is on a quadword boundary.
23294 The padding goes above the vectors. */
23295 if (info_ptr
->altivec_size
!= 0)
23296 info_ptr
->altivec_padding_size
23297 = info_ptr
->vrsave_save_offset
& 0xF;
23299 info_ptr
->altivec_padding_size
= 0;
23301 info_ptr
->altivec_save_offset
23302 = info_ptr
->vrsave_save_offset
23303 - info_ptr
->altivec_padding_size
23304 - info_ptr
->altivec_size
;
23305 gcc_assert (info_ptr
->altivec_size
== 0
23306 || info_ptr
->altivec_save_offset
% 16 == 0);
23308 /* Adjust for AltiVec case. */
23309 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
23312 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
23314 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
23315 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
23316 info_ptr
->lr_save_offset
= 2*reg_size
;
23320 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
23321 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
23322 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
23324 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
23326 /* Align stack so SPE GPR save area is aligned on a
23327 double-word boundary. */
23328 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
23329 info_ptr
->spe_padding_size
23330 = 8 - (-info_ptr
->cr_save_offset
% 8);
23332 info_ptr
->spe_padding_size
= 0;
23334 info_ptr
->spe_gp_save_offset
23335 = info_ptr
->cr_save_offset
23336 - info_ptr
->spe_padding_size
23337 - info_ptr
->spe_gp_size
;
23339 /* Adjust for SPE case. */
23340 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
23342 else if (TARGET_ALTIVEC_ABI
)
23344 info_ptr
->vrsave_save_offset
23345 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
23347 /* Align stack so vector save area is on a quadword boundary. */
23348 if (info_ptr
->altivec_size
!= 0)
23349 info_ptr
->altivec_padding_size
23350 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
23352 info_ptr
->altivec_padding_size
= 0;
23354 info_ptr
->altivec_save_offset
23355 = info_ptr
->vrsave_save_offset
23356 - info_ptr
->altivec_padding_size
23357 - info_ptr
->altivec_size
;
23359 /* Adjust for AltiVec case. */
23360 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
23363 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
23364 info_ptr
->ehrd_offset
-= ehrd_size
;
23365 info_ptr
->lr_save_offset
= reg_size
;
23369 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
23370 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
23371 + info_ptr
->gp_size
23372 + info_ptr
->altivec_size
23373 + info_ptr
->altivec_padding_size
23374 + info_ptr
->spe_gp_size
23375 + info_ptr
->spe_padding_size
23378 + info_ptr
->cr_size
23379 + info_ptr
->vrsave_size
,
23382 non_fixed_size
= (info_ptr
->vars_size
23383 + info_ptr
->parm_size
23384 + info_ptr
->save_size
);
23386 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
23387 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
23389 /* Determine if we need to save the link register. */
23390 if (info_ptr
->calls_p
23391 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23393 && !TARGET_PROFILE_KERNEL
)
23394 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
23395 #ifdef TARGET_RELOCATABLE
23396 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
23398 || rs6000_ra_ever_killed ())
23399 info_ptr
->lr_save_p
= 1;
23401 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
23402 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
23403 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
23404 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
23405 using_static_chain_p
);
23407 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
23408 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
23409 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
23410 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
23411 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
23412 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
23413 info_ptr
->lr_save_p
= 1;
23415 if (info_ptr
->lr_save_p
)
23416 df_set_regs_ever_live (LR_REGNO
, true);
23418 /* Determine if we need to allocate any stack frame:
23420 For AIX we need to push the stack if a frame pointer is needed
23421 (because the stack might be dynamically adjusted), if we are
23422 debugging, if we make calls, or if the sum of fp_save, gp_save,
23423 and local variables are more than the space needed to save all
23424 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
23425 + 18*8 = 288 (GPR13 reserved).
23427 For V.4 we don't have the stack cushion that AIX uses, but assume
23428 that the debugger can handle stackless frames. */
23430 if (info_ptr
->calls_p
)
23431 info_ptr
->push_p
= 1;
23433 else if (DEFAULT_ABI
== ABI_V4
)
23434 info_ptr
->push_p
= non_fixed_size
!= 0;
23436 else if (frame_pointer_needed
)
23437 info_ptr
->push_p
= 1;
23439 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
23440 info_ptr
->push_p
= 1;
23443 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
23448 /* Return true if the current function uses any GPRs in 64-bit SIMD
23452 spe_func_has_64bit_regs_p (void)
23454 rtx_insn
*insns
, *insn
;
23456 /* Functions that save and restore all the call-saved registers will
23457 need to save/restore the registers in 64-bits. */
23458 if (crtl
->calls_eh_return
23459 || cfun
->calls_setjmp
23460 || crtl
->has_nonlocal_goto
)
23463 insns
= get_insns ();
23465 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
23471 /* FIXME: This should be implemented with attributes...
23473 (set_attr "spe64" "true")....then,
23474 if (get_spe64(insn)) return true;
23476 It's the only reliable way to do the stuff below. */
23478 i
= PATTERN (insn
);
23479 if (GET_CODE (i
) == SET
)
23481 machine_mode mode
= GET_MODE (SET_SRC (i
));
23483 if (SPE_VECTOR_MODE (mode
))
23485 if (TARGET_E500_DOUBLE
23486 && (mode
== DFmode
|| FLOAT128_2REG_P (mode
)))
23496 debug_stack_info (rs6000_stack_t
*info
)
23498 const char *abi_string
;
23501 info
= rs6000_stack_info ();
23503 fprintf (stderr
, "\nStack information for function %s:\n",
23504 ((current_function_decl
&& DECL_NAME (current_function_decl
))
23505 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
23510 default: abi_string
= "Unknown"; break;
23511 case ABI_NONE
: abi_string
= "NONE"; break;
23512 case ABI_AIX
: abi_string
= "AIX"; break;
23513 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
23514 case ABI_DARWIN
: abi_string
= "Darwin"; break;
23515 case ABI_V4
: abi_string
= "V.4"; break;
23518 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
23520 if (TARGET_ALTIVEC_ABI
)
23521 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
23523 if (TARGET_SPE_ABI
)
23524 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
23526 if (info
->first_gp_reg_save
!= 32)
23527 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
23529 if (info
->first_fp_reg_save
!= 64)
23530 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
23532 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
23533 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
23534 info
->first_altivec_reg_save
);
23536 if (info
->lr_save_p
)
23537 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
23539 if (info
->cr_save_p
)
23540 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
23542 if (info
->vrsave_mask
)
23543 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
23546 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
23549 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
23552 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
23555 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
23557 if (info
->altivec_size
)
23558 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
23559 info
->altivec_save_offset
);
23561 if (info
->spe_gp_size
)
23562 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
23563 info
->spe_gp_save_offset
);
23565 if (info
->vrsave_size
)
23566 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
23567 info
->vrsave_save_offset
);
23569 if (info
->lr_save_p
)
23570 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
23572 if (info
->cr_save_p
)
23573 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
23575 if (info
->varargs_save_offset
)
23576 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
23578 if (info
->total_size
)
23579 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
23582 if (info
->vars_size
)
23583 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
23586 if (info
->parm_size
)
23587 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
23589 if (info
->fixed_size
)
23590 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
23593 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
23595 if (info
->spe_gp_size
)
23596 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
23599 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
23601 if (info
->altivec_size
)
23602 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
23604 if (info
->vrsave_size
)
23605 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
23607 if (info
->altivec_padding_size
)
23608 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
23609 info
->altivec_padding_size
);
23611 if (info
->spe_padding_size
)
23612 fprintf (stderr
, "\tspe_padding_size = %5d\n",
23613 info
->spe_padding_size
);
23616 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
23618 if (info
->save_size
)
23619 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
23621 if (info
->reg_size
!= 4)
23622 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
23624 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
23626 fprintf (stderr
, "\n");
23630 rs6000_return_addr (int count
, rtx frame
)
23632 /* Currently we don't optimize very well between prolog and body
23633 code and for PIC code the code can be actually quite bad, so
23634 don't try to be too clever here. */
23636 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
23638 cfun
->machine
->ra_needs_full_frame
= 1;
23645 plus_constant (Pmode
,
23647 (gen_rtx_MEM (Pmode
,
23648 memory_address (Pmode
, frame
))),
23649 RETURN_ADDRESS_OFFSET
)));
23652 cfun
->machine
->ra_need_lr
= 1;
23653 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
23656 /* Say whether a function is a candidate for sibcall handling or not. */
23659 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
23664 fntype
= TREE_TYPE (decl
);
23666 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
23668 /* We can't do it if the called function has more vector parameters
23669 than the current function; there's nowhere to put the VRsave code. */
23670 if (TARGET_ALTIVEC_ABI
23671 && TARGET_ALTIVEC_VRSAVE
23672 && !(decl
&& decl
== current_function_decl
))
23674 function_args_iterator args_iter
;
23678 /* Functions with vector parameters are required to have a
23679 prototype, so the argument type info must be available
23681 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
23682 if (TREE_CODE (type
) == VECTOR_TYPE
23683 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
23686 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
23687 if (TREE_CODE (type
) == VECTOR_TYPE
23688 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
23695 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
23696 functions, because the callee may have a different TOC pointer to
23697 the caller and there's no way to ensure we restore the TOC when
23698 we return. With the secure-plt SYSV ABI we can't make non-local
23699 calls when -fpic/PIC because the plt call stubs use r30. */
23700 if (DEFAULT_ABI
== ABI_DARWIN
23701 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23703 && !DECL_EXTERNAL (decl
)
23704 && !DECL_WEAK (decl
)
23705 && (*targetm
.binds_local_p
) (decl
))
23706 || (DEFAULT_ABI
== ABI_V4
23707 && (!TARGET_SECURE_PLT
23710 && (*targetm
.binds_local_p
) (decl
)))))
23712 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
23714 if (!lookup_attribute ("longcall", attr_list
)
23715 || lookup_attribute ("shortcall", attr_list
))
23723 rs6000_ra_ever_killed (void)
23729 if (cfun
->is_thunk
)
23732 if (cfun
->machine
->lr_save_state
)
23733 return cfun
->machine
->lr_save_state
- 1;
23735 /* regs_ever_live has LR marked as used if any sibcalls are present,
23736 but this should not force saving and restoring in the
23737 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
23738 clobbers LR, so that is inappropriate. */
23740 /* Also, the prologue can generate a store into LR that
23741 doesn't really count, like this:
23744 bcl to set PIC register
23748 When we're called from the epilogue, we need to avoid counting
23749 this as a store. */
23751 push_topmost_sequence ();
23752 top
= get_insns ();
23753 pop_topmost_sequence ();
23754 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
23756 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
23762 if (!SIBLING_CALL_P (insn
))
23765 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
23767 else if (set_of (reg
, insn
) != NULL_RTX
23768 && !prologue_epilogue_contains (insn
))
23775 /* Emit instructions needed to load the TOC register.
23776 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
23777 a constant pool; or for SVR4 -fpic. */
23780 rs6000_emit_load_toc_table (int fromprolog
)
23783 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
23785 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
23788 rtx lab
, tmp1
, tmp2
, got
;
23790 lab
= gen_label_rtx ();
23791 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
23792 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
23794 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
23796 got
= rs6000_got_sym ();
23797 tmp1
= tmp2
= dest
;
23800 tmp1
= gen_reg_rtx (Pmode
);
23801 tmp2
= gen_reg_rtx (Pmode
);
23803 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
23804 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
23805 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
23806 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
23808 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
23810 emit_insn (gen_load_toc_v4_pic_si ());
23811 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
23813 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
23816 rtx temp0
= (fromprolog
23817 ? gen_rtx_REG (Pmode
, 0)
23818 : gen_reg_rtx (Pmode
));
23824 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
23825 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
23827 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
23828 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
23830 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
23831 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
23832 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
23838 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
23839 lab
= gen_label_rtx ();
23840 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
23841 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
23842 if (TARGET_LINK_STACK
)
23843 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
23844 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
23846 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
23848 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
23850 /* This is for AIX code running in non-PIC ELF32. */
23853 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
23854 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
23856 emit_insn (gen_elf_high (dest
, realsym
));
23857 emit_insn (gen_elf_low (dest
, dest
, realsym
));
23861 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23864 emit_insn (gen_load_toc_aix_si (dest
));
23866 emit_insn (gen_load_toc_aix_di (dest
));
23870 /* Emit instructions to restore the link register after determining where
23871 its value has been stored. */
23874 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
23876 rs6000_stack_t
*info
= rs6000_stack_info ();
23879 operands
[0] = source
;
23880 operands
[1] = scratch
;
23882 if (info
->lr_save_p
)
23884 rtx frame_rtx
= stack_pointer_rtx
;
23885 HOST_WIDE_INT sp_offset
= 0;
23888 if (frame_pointer_needed
23889 || cfun
->calls_alloca
23890 || info
->total_size
> 32767)
23892 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
23893 emit_move_insn (operands
[1], tmp
);
23894 frame_rtx
= operands
[1];
23896 else if (info
->push_p
)
23897 sp_offset
= info
->total_size
;
23899 tmp
= plus_constant (Pmode
, frame_rtx
,
23900 info
->lr_save_offset
+ sp_offset
);
23901 tmp
= gen_frame_mem (Pmode
, tmp
);
23902 emit_move_insn (tmp
, operands
[0]);
23905 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
23907 /* Freeze lr_save_p. We've just emitted rtl that depends on the
23908 state of lr_save_p so any change from here on would be a bug. In
23909 particular, stop rs6000_ra_ever_killed from considering the SET
23910 of lr we may have added just above. */
23911 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
23914 static GTY(()) alias_set_type set
= -1;
23917 get_TOC_alias_set (void)
23920 set
= new_alias_set ();
23924 /* This returns nonzero if the current function uses the TOC. This is
23925 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
23926 is generated by the ABI_V4 load_toc_* patterns. */
23933 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
23936 rtx pat
= PATTERN (insn
);
23939 if (GET_CODE (pat
) == PARALLEL
)
23940 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
23942 rtx sub
= XVECEXP (pat
, 0, i
);
23943 if (GET_CODE (sub
) == USE
)
23945 sub
= XEXP (sub
, 0);
23946 if (GET_CODE (sub
) == UNSPEC
23947 && XINT (sub
, 1) == UNSPEC_TOC
)
23957 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
23959 rtx tocrel
, tocreg
, hi
;
23961 if (TARGET_DEBUG_ADDR
)
23963 if (GET_CODE (symbol
) == SYMBOL_REF
)
23964 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
23968 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
23969 GET_RTX_NAME (GET_CODE (symbol
)));
23970 debug_rtx (symbol
);
23974 if (!can_create_pseudo_p ())
23975 df_set_regs_ever_live (TOC_REGISTER
, true);
23977 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
23978 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
23979 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
23982 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
23983 if (largetoc_reg
!= NULL
)
23985 emit_move_insn (largetoc_reg
, hi
);
23988 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
23991 /* Issue assembly directives that create a reference to the given DWARF
23992 FRAME_TABLE_LABEL from the current function section. */
23994 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
23996 fprintf (asm_out_file
, "\t.ref %s\n",
23997 (* targetm
.strip_name_encoding
) (frame_table_label
));
24000 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
24001 and the change to the stack pointer. */
24004 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
24011 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
24012 if (hard_frame_needed
)
24013 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
24014 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
24015 || (hard_frame_needed
24016 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
24019 p
= rtvec_alloc (i
);
24022 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
24023 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
24026 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
24029 /* Emit the correct code for allocating stack space, as insns.
24030 If COPY_REG, make sure a copy of the old frame is left there.
24031 The generated code may use hard register 0 as a temporary. */
24034 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
24037 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
24038 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
24039 rtx todec
= gen_int_mode (-size
, Pmode
);
24042 if (INTVAL (todec
) != -size
)
24044 warning (0, "stack frame too large");
24045 emit_insn (gen_trap ());
24049 if (crtl
->limit_stack
)
24051 if (REG_P (stack_limit_rtx
)
24052 && REGNO (stack_limit_rtx
) > 1
24053 && REGNO (stack_limit_rtx
) <= 31)
24055 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
24056 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
24059 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
24061 && DEFAULT_ABI
== ABI_V4
)
24063 rtx toload
= gen_rtx_CONST (VOIDmode
,
24064 gen_rtx_PLUS (Pmode
,
24068 emit_insn (gen_elf_high (tmp_reg
, toload
));
24069 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
24070 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
24074 warning (0, "stack limit expression is not supported");
24080 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
24082 emit_move_insn (copy_reg
, stack_reg
);
24087 /* Need a note here so that try_split doesn't get confused. */
24088 if (get_last_insn () == NULL_RTX
)
24089 emit_note (NOTE_INSN_DELETED
);
24090 insn
= emit_move_insn (tmp_reg
, todec
);
24091 try_split (PATTERN (insn
), insn
, 0);
24095 insn
= emit_insn (TARGET_32BIT
24096 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
24098 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
24099 todec
, stack_reg
));
24100 /* Since we didn't use gen_frame_mem to generate the MEM, grab
24101 it now and set the alias set/attributes. The above gen_*_update
24102 calls will generate a PARALLEL with the MEM set being the first
24104 par
= PATTERN (insn
);
24105 gcc_assert (GET_CODE (par
) == PARALLEL
);
24106 set
= XVECEXP (par
, 0, 0);
24107 gcc_assert (GET_CODE (set
) == SET
);
24108 mem
= SET_DEST (set
);
24109 gcc_assert (MEM_P (mem
));
24110 MEM_NOTRAP_P (mem
) = 1;
24111 set_mem_alias_set (mem
, get_frame_alias_set ());
24113 RTX_FRAME_RELATED_P (insn
) = 1;
24114 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
24115 gen_rtx_SET (stack_reg
, gen_rtx_PLUS (Pmode
, stack_reg
,
24116 GEN_INT (-size
))));
24120 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
24122 #if PROBE_INTERVAL > 32768
24123 #error Cannot use indexed addressing mode for stack probing
24126 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
24127 inclusive. These are offsets from the current stack pointer. */
24130 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
24132 /* See if we have a constant small number of probes to generate. If so,
24133 that's the easy case. */
24134 if (first
+ size
<= 32768)
24138 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
24139 it exceeds SIZE. If only one probe is needed, this will not
24140 generate any code. Then probe at FIRST + SIZE. */
24141 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
24142 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
24145 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
24149 /* Otherwise, do the same as above, but in a loop. Note that we must be
24150 extra careful with variables wrapping around because we might be at
24151 the very top (or the very bottom) of the address space and we have
24152 to be able to handle this case properly; in particular, we use an
24153 equality test for the loop condition. */
24156 HOST_WIDE_INT rounded_size
;
24157 rtx r12
= gen_rtx_REG (Pmode
, 12);
24158 rtx r0
= gen_rtx_REG (Pmode
, 0);
24160 /* Sanity check for the addressing mode we're going to use. */
24161 gcc_assert (first
<= 32768);
24163 /* Step 1: round SIZE to the previous multiple of the interval. */
24165 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
24168 /* Step 2: compute initial and final value of the loop counter. */
24170 /* TEST_ADDR = SP + FIRST. */
24171 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
24174 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
24175 if (rounded_size
> 32768)
24177 emit_move_insn (r0
, GEN_INT (-rounded_size
));
24178 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
24181 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
24185 /* Step 3: the loop
24189 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
24192 while (TEST_ADDR != LAST_ADDR)
24194 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
24195 until it is equal to ROUNDED_SIZE. */
24198 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
24200 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
24203 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
24204 that SIZE is equal to ROUNDED_SIZE. */
24206 if (size
!= rounded_size
)
24207 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
24211 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
24212 absolute addresses. */
24215 output_probe_stack_range (rtx reg1
, rtx reg2
)
24217 static int labelno
= 0;
24221 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
24224 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
24226 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
24228 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
24229 output_asm_insn ("addi %0,%0,%1", xops
);
24231 /* Probe at TEST_ADDR. */
24232 xops
[1] = gen_rtx_REG (Pmode
, 0);
24233 output_asm_insn ("stw %1,0(%0)", xops
);
24235 /* Test if TEST_ADDR == LAST_ADDR. */
24238 output_asm_insn ("cmpd 0,%0,%1", xops
);
24240 output_asm_insn ("cmpw 0,%0,%1", xops
);
24243 fputs ("\tbne 0,", asm_out_file
);
24244 assemble_name_raw (asm_out_file
, loop_lab
);
24245 fputc ('\n', asm_out_file
);
24250 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
24251 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
24252 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
24253 deduce these equivalences by itself so it wasn't necessary to hold
24254 its hand so much. Don't be tempted to always supply d2_f_d_e with
24255 the actual cfa register, ie. r31 when we are using a hard frame
24256 pointer. That fails when saving regs off r1, and sched moves the
24257 r31 setup past the reg saves. */
24260 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
24261 rtx reg2
, rtx rreg
)
24265 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
24267 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
24270 gcc_checking_assert (val
== 0);
24271 real
= PATTERN (insn
);
24272 if (GET_CODE (real
) == PARALLEL
)
24273 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
24274 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
24276 rtx set
= XVECEXP (real
, 0, i
);
24278 RTX_FRAME_RELATED_P (set
) = 1;
24280 RTX_FRAME_RELATED_P (insn
) = 1;
24284 /* copy_rtx will not make unique copies of registers, so we need to
24285 ensure we don't have unwanted sharing here. */
24287 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
24290 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
24292 real
= copy_rtx (PATTERN (insn
));
24294 if (reg2
!= NULL_RTX
)
24295 real
= replace_rtx (real
, reg2
, rreg
);
24297 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
24298 gcc_checking_assert (val
== 0);
24300 real
= replace_rtx (real
, reg
,
24301 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
24302 STACK_POINTER_REGNUM
),
24305 /* We expect that 'real' is either a SET or a PARALLEL containing
24306 SETs (and possibly other stuff). In a PARALLEL, all the SETs
24307 are important so they all have to be marked RTX_FRAME_RELATED_P. */
24309 if (GET_CODE (real
) == SET
)
24313 temp
= simplify_rtx (SET_SRC (set
));
24315 SET_SRC (set
) = temp
;
24316 temp
= simplify_rtx (SET_DEST (set
));
24318 SET_DEST (set
) = temp
;
24319 if (GET_CODE (SET_DEST (set
)) == MEM
)
24321 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
24323 XEXP (SET_DEST (set
), 0) = temp
;
24330 gcc_assert (GET_CODE (real
) == PARALLEL
);
24331 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
24332 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
24334 rtx set
= XVECEXP (real
, 0, i
);
24336 temp
= simplify_rtx (SET_SRC (set
));
24338 SET_SRC (set
) = temp
;
24339 temp
= simplify_rtx (SET_DEST (set
));
24341 SET_DEST (set
) = temp
;
24342 if (GET_CODE (SET_DEST (set
)) == MEM
)
24344 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
24346 XEXP (SET_DEST (set
), 0) = temp
;
24348 RTX_FRAME_RELATED_P (set
) = 1;
24352 RTX_FRAME_RELATED_P (insn
) = 1;
24353 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
24358 /* Returns an insn that has a vrsave set operation with the
24359 appropriate CLOBBERs. */
24362 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
24365 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
24366 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
24369 = gen_rtx_SET (vrsave
,
24370 gen_rtx_UNSPEC_VOLATILE (SImode
,
24371 gen_rtvec (2, reg
, vrsave
),
24372 UNSPECV_SET_VRSAVE
));
24376 /* We need to clobber the registers in the mask so the scheduler
24377 does not move sets to VRSAVE before sets of AltiVec registers.
24379 However, if the function receives nonlocal gotos, reload will set
24380 all call saved registers live. We will end up with:
24382 (set (reg 999) (mem))
24383 (parallel [ (set (reg vrsave) (unspec blah))
24384 (clobber (reg 999))])
24386 The clobber will cause the store into reg 999 to be dead, and
24387 flow will attempt to delete an epilogue insn. In this case, we
24388 need an unspec use/set of the register. */
24390 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24391 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24393 if (!epiloguep
|| call_used_regs
[i
])
24394 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
24395 gen_rtx_REG (V4SImode
, i
));
24398 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24401 = gen_rtx_SET (reg
,
24402 gen_rtx_UNSPEC (V4SImode
,
24403 gen_rtvec (1, reg
), 27));
24407 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
24409 for (i
= 0; i
< nclobs
; ++i
)
24410 XVECEXP (insn
, 0, i
) = clobs
[i
];
24416 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
24420 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
24421 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
24422 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
24426 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
24428 return gen_frame_set (reg
, frame_reg
, offset
, false);
24432 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
24434 return gen_frame_set (reg
, frame_reg
, offset
, true);
24437 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
24438 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
24441 emit_frame_save (rtx frame_reg
, machine_mode mode
,
24442 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
24446 /* Some cases that need register indexed addressing. */
24447 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
24448 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
24449 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
24451 && SPE_VECTOR_MODE (mode
)
24452 && !SPE_CONST_OFFSET_OK (offset
))));
24454 reg
= gen_rtx_REG (mode
, regno
);
24455 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
24456 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
24457 NULL_RTX
, NULL_RTX
);
24460 /* Emit an offset memory reference suitable for a frame store, while
24461 converting to a valid addressing mode. */
24464 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
24466 rtx int_rtx
, offset_rtx
;
24468 int_rtx
= GEN_INT (offset
);
24470 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
24471 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
24473 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
24474 emit_move_insn (offset_rtx
, int_rtx
);
24477 offset_rtx
= int_rtx
;
24479 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
24482 #ifndef TARGET_FIX_AND_CONTINUE
24483 #define TARGET_FIX_AND_CONTINUE 0
24486 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
24487 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
24488 #define LAST_SAVRES_REGISTER 31
24489 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
24500 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
24502 /* Temporary holding space for an out-of-line register save/restore
24504 static char savres_routine_name
[30];
24506 /* Return the name for an out-of-line register save/restore routine.
24507 We are saving/restoring GPRs if GPR is true. */
24510 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
24512 const char *prefix
= "";
24513 const char *suffix
= "";
24515 /* Different targets are supposed to define
24516 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
24517 routine name could be defined with:
24519 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
24521 This is a nice idea in practice, but in reality, things are
24522 complicated in several ways:
24524 - ELF targets have save/restore routines for GPRs.
24526 - SPE targets use different prefixes for 32/64-bit registers, and
24527 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
24529 - PPC64 ELF targets have routines for save/restore of GPRs that
24530 differ in what they do with the link register, so having a set
24531 prefix doesn't work. (We only use one of the save routines at
24532 the moment, though.)
24534 - PPC32 elf targets have "exit" versions of the restore routines
24535 that restore the link register and can save some extra space.
24536 These require an extra suffix. (There are also "tail" versions
24537 of the restore routines and "GOT" versions of the save routines,
24538 but we don't generate those at present. Same problems apply,
24541 We deal with all this by synthesizing our own prefix/suffix and
24542 using that for the simple sprintf call shown above. */
24545 /* No floating point saves on the SPE. */
24546 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
24548 if ((sel
& SAVRES_SAVE
))
24549 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
24551 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
24553 if ((sel
& SAVRES_LR
))
24556 else if (DEFAULT_ABI
== ABI_V4
)
24561 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
24562 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
24563 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
24564 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
24565 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
24566 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
24570 if ((sel
& SAVRES_LR
))
24573 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24575 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
24576 /* No out-of-line save/restore routines for GPRs on AIX. */
24577 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
24581 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
24582 prefix
= ((sel
& SAVRES_SAVE
)
24583 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
24584 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
24585 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
24587 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
24588 if ((sel
& SAVRES_LR
))
24589 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
24593 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
24594 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
24597 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
24598 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
24603 if (DEFAULT_ABI
== ABI_DARWIN
)
24605 /* The Darwin approach is (slightly) different, in order to be
24606 compatible with code generated by the system toolchain. There is a
24607 single symbol for the start of save sequence, and the code here
24608 embeds an offset into that code on the basis of the first register
24610 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
24611 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
24612 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
24613 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
24614 (regno
- 13) * 4, prefix
, regno
);
24615 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
24616 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
24617 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
24618 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
24619 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
24620 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
24625 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
24627 return savres_routine_name
;
24630 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
24631 We are saving/restoring GPRs if GPR is true. */
24634 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
24636 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
24637 ? info
->first_gp_reg_save
24638 : (sel
& SAVRES_REG
) == SAVRES_FPR
24639 ? info
->first_fp_reg_save
- 32
24640 : (sel
& SAVRES_REG
) == SAVRES_VR
24641 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
24646 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
24647 versions of the gpr routines. */
24648 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
24649 && info
->spe_64bit_regs_used
)
24650 select
^= SAVRES_FPR
^ SAVRES_GPR
;
24652 /* Don't generate bogus routine names. */
24653 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
24654 && regno
<= LAST_SAVRES_REGISTER
24655 && select
>= 0 && select
<= 12);
24657 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
24663 name
= rs6000_savres_routine_name (info
, regno
, sel
);
24665 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
24666 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
24667 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
24673 /* Emit a sequence of insns, including a stack tie if needed, for
24674 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
24675 reset the stack pointer, but move the base of the frame into
24676 reg UPDT_REGNO for use by out-of-line register restore routines. */
24679 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
24680 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
24681 unsigned updt_regno
)
24685 /* This blockage is needed so that sched doesn't decide to move
24686 the sp change before the register restores. */
24687 if (DEFAULT_ABI
== ABI_V4
24689 && info
->spe_64bit_regs_used
!= 0
24690 && info
->first_gp_reg_save
!= 32))
24691 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
24693 /* If we are restoring registers out-of-line, we will be using the
24694 "exit" variants of the restore routines, which will reset the
24695 stack for us. But we do need to point updt_reg into the
24696 right place for those routines. */
24697 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
24699 if (frame_off
!= 0)
24700 return emit_insn (gen_add3_insn (updt_reg_rtx
,
24701 frame_reg_rtx
, GEN_INT (frame_off
)));
24702 else if (REGNO (frame_reg_rtx
) != updt_regno
)
24703 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
24708 /* Return the register number used as a pointer by out-of-line
24709 save/restore functions. */
24711 static inline unsigned
24712 ptr_regno_for_savres (int sel
)
24714 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24715 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
24716 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
24719 /* Construct a parallel rtx describing the effect of a call to an
24720 out-of-line register save/restore routine, and emit the insn
24721 or jump_insn as appropriate. */
24724 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
24725 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
24726 machine_mode reg_mode
, int sel
)
24729 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
24730 int reg_size
= GET_MODE_SIZE (reg_mode
);
24736 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
24737 ? info
->first_gp_reg_save
24738 : (sel
& SAVRES_REG
) == SAVRES_FPR
24739 ? info
->first_fp_reg_save
24740 : (sel
& SAVRES_REG
) == SAVRES_VR
24741 ? info
->first_altivec_reg_save
24743 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
24745 : (sel
& SAVRES_REG
) == SAVRES_FPR
24747 : (sel
& SAVRES_REG
) == SAVRES_VR
24748 ? LAST_ALTIVEC_REGNO
+ 1
24750 n_regs
= end_reg
- start_reg
;
24751 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
24752 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
24755 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
24756 RTVEC_ELT (p
, offset
++) = ret_rtx
;
24758 RTVEC_ELT (p
, offset
++)
24759 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
24761 sym
= rs6000_savres_routine_sym (info
, sel
);
24762 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
24764 use_reg
= ptr_regno_for_savres (sel
);
24765 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
24767 /* Vector regs are saved/restored using [reg+reg] addressing. */
24768 RTVEC_ELT (p
, offset
++)
24769 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
24770 RTVEC_ELT (p
, offset
++)
24771 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
24774 RTVEC_ELT (p
, offset
++)
24775 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
24777 for (i
= 0; i
< end_reg
- start_reg
; i
++)
24778 RTVEC_ELT (p
, i
+ offset
)
24779 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
24780 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
24781 (sel
& SAVRES_SAVE
) != 0);
24783 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
24784 RTVEC_ELT (p
, i
+ offset
)
24785 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
24787 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
24789 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
24791 insn
= emit_jump_insn (par
);
24792 JUMP_LABEL (insn
) = ret_rtx
;
24795 insn
= emit_insn (par
);
24799 /* Emit code to store CR fields that need to be saved into REG. */
24802 rs6000_emit_move_from_cr (rtx reg
)
24804 /* Only the ELFv2 ABI allows storing only selected fields. */
24805 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
24807 int i
, cr_reg
[8], count
= 0;
24809 /* Collect CR fields that must be saved. */
24810 for (i
= 0; i
< 8; i
++)
24811 if (save_reg_p (CR0_REGNO
+ i
))
24812 cr_reg
[count
++] = i
;
24814 /* If it's just a single one, use mfcrf. */
24817 rtvec p
= rtvec_alloc (1);
24818 rtvec r
= rtvec_alloc (2);
24819 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
24820 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
24822 = gen_rtx_SET (reg
,
24823 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
24825 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24829 /* ??? It might be better to handle count == 2 / 3 cases here
24830 as well, using logical operations to combine the values. */
24833 emit_insn (gen_movesi_from_cr (reg
));
24836 /* Return whether the split-stack arg pointer (r12) is used. */
24839 split_stack_arg_pointer_used_p (void)
24841 /* If the pseudo holding the arg pointer is no longer a pseudo,
24842 then the arg pointer is used. */
24843 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
24844 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
24845 || (REGNO (cfun
->machine
->split_stack_arg_pointer
)
24846 < FIRST_PSEUDO_REGISTER
)))
24849 /* Unfortunately we also need to do some code scanning, since
24850 r12 may have been substituted for the pseudo. */
24852 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
24853 FOR_BB_INSNS (bb
, insn
)
24854 if (NONDEBUG_INSN_P (insn
))
24856 /* A call destroys r12. */
24861 FOR_EACH_INSN_USE (use
, insn
)
24863 rtx x
= DF_REF_REG (use
);
24864 if (REG_P (x
) && REGNO (x
) == 12)
24868 FOR_EACH_INSN_DEF (def
, insn
)
24870 rtx x
= DF_REF_REG (def
);
24871 if (REG_P (x
) && REGNO (x
) == 12)
24875 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
24878 /* Return whether we need to emit an ELFv2 global entry point prologue. */
24881 rs6000_global_entry_point_needed_p (void)
24883 /* Only needed for the ELFv2 ABI. */
24884 if (DEFAULT_ABI
!= ABI_ELFv2
)
24887 /* With -msingle-pic-base, we assume the whole program shares the same
24888 TOC, so no global entry point prologues are needed anywhere. */
24889 if (TARGET_SINGLE_PIC_BASE
)
24892 /* Ensure we have a global entry point for thunks. ??? We could
24893 avoid that if the target routine doesn't need a global entry point,
24894 but we do not know whether this is the case at this point. */
24895 if (cfun
->is_thunk
)
24898 /* For regular functions, rs6000_emit_prologue sets this flag if the
24899 routine ever uses the TOC pointer. */
24900 return cfun
->machine
->r2_setup_needed
;
24903 /* Emit function prologue as insns. */
24906 rs6000_emit_prologue (void)
24908 rs6000_stack_t
*info
= rs6000_stack_info ();
24909 machine_mode reg_mode
= Pmode
;
24910 int reg_size
= TARGET_32BIT
? 4 : 8;
24911 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
24912 rtx frame_reg_rtx
= sp_reg_rtx
;
24913 unsigned int cr_save_regno
;
24914 rtx cr_save_rtx
= NULL_RTX
;
24917 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
24918 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
24919 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
24920 int using_split_stack
= (flag_split_stack
24921 && (lookup_attribute ("no_split_stack",
24922 DECL_ATTRIBUTES (cfun
->decl
))
24925 /* Offset to top of frame for frame_reg and sp respectively. */
24926 HOST_WIDE_INT frame_off
= 0;
24927 HOST_WIDE_INT sp_off
= 0;
24928 /* sp_adjust is the stack adjusting instruction, tracked so that the
24929 insn setting up the split-stack arg pointer can be emitted just
24930 prior to it, when r12 is not used here for other purposes. */
24931 rtx_insn
*sp_adjust
= 0;
24934 /* Track and check usage of r0, r11, r12. */
24935 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
24936 #define START_USE(R) do \
24938 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
24939 reg_inuse |= 1 << (R); \
24941 #define END_USE(R) do \
24943 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
24944 reg_inuse &= ~(1 << (R)); \
24946 #define NOT_INUSE(R) do \
24948 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
24951 #define START_USE(R) do {} while (0)
24952 #define END_USE(R) do {} while (0)
24953 #define NOT_INUSE(R) do {} while (0)
24956 if (DEFAULT_ABI
== ABI_ELFv2
24957 && !TARGET_SINGLE_PIC_BASE
)
24959 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
24961 /* With -mminimal-toc we may generate an extra use of r2 below. */
24962 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
24963 cfun
->machine
->r2_setup_needed
= true;
24967 if (flag_stack_usage_info
)
24968 current_function_static_stack_size
= info
->total_size
;
24970 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
24972 HOST_WIDE_INT size
= info
->total_size
;
24974 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
24976 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
24977 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
24978 size
- STACK_CHECK_PROTECT
);
24981 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
24984 if (TARGET_FIX_AND_CONTINUE
)
24986 /* gdb on darwin arranges to forward a function from the old
24987 address by modifying the first 5 instructions of the function
24988 to branch to the overriding function. This is necessary to
24989 permit function pointers that point to the old function to
24990 actually forward to the new function. */
24991 emit_insn (gen_nop ());
24992 emit_insn (gen_nop ());
24993 emit_insn (gen_nop ());
24994 emit_insn (gen_nop ());
24995 emit_insn (gen_nop ());
24998 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
25000 reg_mode
= V2SImode
;
25004 /* Handle world saves specially here. */
25005 if (WORLD_SAVE_P (info
))
25012 /* save_world expects lr in r0. */
25013 reg0
= gen_rtx_REG (Pmode
, 0);
25014 if (info
->lr_save_p
)
25016 insn
= emit_move_insn (reg0
,
25017 gen_rtx_REG (Pmode
, LR_REGNO
));
25018 RTX_FRAME_RELATED_P (insn
) = 1;
25021 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
25022 assumptions about the offsets of various bits of the stack
25024 gcc_assert (info
->gp_save_offset
== -220
25025 && info
->fp_save_offset
== -144
25026 && info
->lr_save_offset
== 8
25027 && info
->cr_save_offset
== 4
25030 && (!crtl
->calls_eh_return
25031 || info
->ehrd_offset
== -432)
25032 && info
->vrsave_save_offset
== -224
25033 && info
->altivec_save_offset
== -416);
25035 treg
= gen_rtx_REG (SImode
, 11);
25036 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
25038 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
25039 in R11. It also clobbers R12, so beware! */
25041 /* Preserve CR2 for save_world prologues */
25043 sz
+= 32 - info
->first_gp_reg_save
;
25044 sz
+= 64 - info
->first_fp_reg_save
;
25045 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
25046 p
= rtvec_alloc (sz
);
25048 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
25049 gen_rtx_REG (SImode
,
25051 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
25052 gen_rtx_SYMBOL_REF (Pmode
,
25054 /* We do floats first so that the instruction pattern matches
25056 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
25058 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
25060 info
->first_fp_reg_save
+ i
),
25062 info
->fp_save_offset
+ frame_off
+ 8 * i
);
25063 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
25065 = gen_frame_store (gen_rtx_REG (V4SImode
,
25066 info
->first_altivec_reg_save
+ i
),
25068 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
25069 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25071 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
25073 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
25075 /* CR register traditionally saved as CR2. */
25077 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
25078 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
25079 /* Explain about use of R0. */
25080 if (info
->lr_save_p
)
25082 = gen_frame_store (reg0
,
25083 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
25084 /* Explain what happens to the stack pointer. */
25086 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
25087 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
25090 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25091 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
25092 treg
, GEN_INT (-info
->total_size
));
25093 sp_off
= frame_off
= info
->total_size
;
25096 strategy
= info
->savres_strategy
;
25098 /* For V.4, update stack before we do any saving and set back pointer. */
25099 if (! WORLD_SAVE_P (info
)
25101 && (DEFAULT_ABI
== ABI_V4
25102 || crtl
->calls_eh_return
))
25104 bool need_r11
= (TARGET_SPE
25105 ? (!(strategy
& SAVE_INLINE_GPRS
)
25106 && info
->spe_64bit_regs_used
== 0)
25107 : (!(strategy
& SAVE_INLINE_FPRS
)
25108 || !(strategy
& SAVE_INLINE_GPRS
)
25109 || !(strategy
& SAVE_INLINE_VRS
)));
25110 int ptr_regno
= -1;
25111 rtx ptr_reg
= NULL_RTX
;
25114 if (info
->total_size
< 32767)
25115 frame_off
= info
->total_size
;
25118 else if (info
->cr_save_p
25120 || info
->first_fp_reg_save
< 64
25121 || info
->first_gp_reg_save
< 32
25122 || info
->altivec_size
!= 0
25123 || info
->vrsave_size
!= 0
25124 || crtl
->calls_eh_return
)
25128 /* The prologue won't be saving any regs so there is no need
25129 to set up a frame register to access any frame save area.
25130 We also won't be using frame_off anywhere below, but set
25131 the correct value anyway to protect against future
25132 changes to this function. */
25133 frame_off
= info
->total_size
;
25135 if (ptr_regno
!= -1)
25137 /* Set up the frame offset to that needed by the first
25138 out-of-line save function. */
25139 START_USE (ptr_regno
);
25140 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
25141 frame_reg_rtx
= ptr_reg
;
25142 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
25143 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
25144 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
25145 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
25146 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
25147 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
25148 frame_off
= -ptr_off
;
25150 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
25152 if (REGNO (frame_reg_rtx
) == 12)
25154 sp_off
= info
->total_size
;
25155 if (frame_reg_rtx
!= sp_reg_rtx
)
25156 rs6000_emit_stack_tie (frame_reg_rtx
, false);
25159 /* If we use the link register, get it into r0. */
25160 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
25162 rtx addr
, reg
, mem
;
25164 reg
= gen_rtx_REG (Pmode
, 0);
25166 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
25167 RTX_FRAME_RELATED_P (insn
) = 1;
25169 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
25170 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
25172 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
25173 GEN_INT (info
->lr_save_offset
+ frame_off
));
25174 mem
= gen_rtx_MEM (Pmode
, addr
);
25175 /* This should not be of rs6000_sr_alias_set, because of
25176 __builtin_return_address. */
25178 insn
= emit_move_insn (mem
, reg
);
25179 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
25180 NULL_RTX
, NULL_RTX
);
25185 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
25186 r12 will be needed by out-of-line gpr restore. */
25187 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25188 && !(strategy
& (SAVE_INLINE_GPRS
25189 | SAVE_NOINLINE_GPRS_SAVES_LR
))
25191 if (!WORLD_SAVE_P (info
)
25193 && REGNO (frame_reg_rtx
) != cr_save_regno
25194 && !(using_static_chain_p
&& cr_save_regno
== 11)
25195 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
25197 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
25198 START_USE (cr_save_regno
);
25199 rs6000_emit_move_from_cr (cr_save_rtx
);
25202 /* Do any required saving of fpr's. If only one or two to save, do
25203 it ourselves. Otherwise, call function. */
25204 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
25207 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
25208 if (save_reg_p (info
->first_fp_reg_save
+ i
))
25209 emit_frame_save (frame_reg_rtx
,
25210 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
25211 ? DFmode
: SFmode
),
25212 info
->first_fp_reg_save
+ i
,
25213 info
->fp_save_offset
+ frame_off
+ 8 * i
,
25214 sp_off
- frame_off
);
25216 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
25218 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
25219 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25220 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
25221 rtx ptr_reg
= frame_reg_rtx
;
25223 if (REGNO (frame_reg_rtx
) == ptr_regno
)
25224 gcc_checking_assert (frame_off
== 0);
25227 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
25228 NOT_INUSE (ptr_regno
);
25229 emit_insn (gen_add3_insn (ptr_reg
,
25230 frame_reg_rtx
, GEN_INT (frame_off
)));
25232 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
25233 info
->fp_save_offset
,
25234 info
->lr_save_offset
,
25236 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
25237 NULL_RTX
, NULL_RTX
);
25242 /* Save GPRs. This is done as a PARALLEL if we are using
25243 the store-multiple instructions. */
25244 if (!WORLD_SAVE_P (info
)
25246 && info
->spe_64bit_regs_used
!= 0
25247 && info
->first_gp_reg_save
!= 32)
25250 rtx spe_save_area_ptr
;
25251 HOST_WIDE_INT save_off
;
25252 int ool_adjust
= 0;
25254 /* Determine whether we can address all of the registers that need
25255 to be saved with an offset from frame_reg_rtx that fits in
25256 the small const field for SPE memory instructions. */
25257 int spe_regs_addressable
25258 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
25259 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
25260 && (strategy
& SAVE_INLINE_GPRS
));
25262 if (spe_regs_addressable
)
25264 spe_save_area_ptr
= frame_reg_rtx
;
25265 save_off
= frame_off
;
25269 /* Make r11 point to the start of the SPE save area. We need
25270 to be careful here if r11 is holding the static chain. If
25271 it is, then temporarily save it in r0. */
25272 HOST_WIDE_INT offset
;
25274 if (!(strategy
& SAVE_INLINE_GPRS
))
25275 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
25276 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
25277 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
25278 save_off
= frame_off
- offset
;
25280 if (using_static_chain_p
)
25282 rtx r0
= gen_rtx_REG (Pmode
, 0);
25285 gcc_assert (info
->first_gp_reg_save
> 11);
25287 emit_move_insn (r0
, spe_save_area_ptr
);
25289 else if (REGNO (frame_reg_rtx
) != 11)
25292 emit_insn (gen_addsi3 (spe_save_area_ptr
,
25293 frame_reg_rtx
, GEN_INT (offset
)));
25294 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
25295 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
25298 if ((strategy
& SAVE_INLINE_GPRS
))
25300 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25301 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
25302 emit_frame_save (spe_save_area_ptr
, reg_mode
,
25303 info
->first_gp_reg_save
+ i
,
25304 (info
->spe_gp_save_offset
+ save_off
25306 sp_off
- save_off
);
25310 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
25311 info
->spe_gp_save_offset
+ save_off
,
25313 SAVRES_SAVE
| SAVRES_GPR
);
25315 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
25316 NULL_RTX
, NULL_RTX
);
25319 /* Move the static chain pointer back. */
25320 if (!spe_regs_addressable
)
25322 if (using_static_chain_p
)
25324 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
25327 else if (REGNO (frame_reg_rtx
) != 11)
25331 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
25333 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
25334 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
25335 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
25336 rtx ptr_reg
= frame_reg_rtx
;
25337 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
25338 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
25341 if (ptr_regno
== 12)
25344 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
25346 /* Need to adjust r11 (r12) if we saved any FPRs. */
25347 if (end_save
+ frame_off
!= 0)
25349 rtx offset
= GEN_INT (end_save
+ frame_off
);
25352 frame_off
= -end_save
;
25354 NOT_INUSE (ptr_regno
);
25355 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
25357 else if (!ptr_set_up
)
25359 NOT_INUSE (ptr_regno
);
25360 emit_move_insn (ptr_reg
, frame_reg_rtx
);
25362 ptr_off
= -end_save
;
25363 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
25364 info
->gp_save_offset
+ ptr_off
,
25365 info
->lr_save_offset
+ ptr_off
,
25367 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
25368 NULL_RTX
, NULL_RTX
);
25372 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
25376 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
25377 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25379 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
25381 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
25382 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25383 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
25384 NULL_RTX
, NULL_RTX
);
25386 else if (!WORLD_SAVE_P (info
))
25389 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25390 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
25391 emit_frame_save (frame_reg_rtx
, reg_mode
,
25392 info
->first_gp_reg_save
+ i
,
25393 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
25394 sp_off
- frame_off
);
25397 if (crtl
->calls_eh_return
)
25404 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
25405 if (regno
== INVALID_REGNUM
)
25409 p
= rtvec_alloc (i
);
25413 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
25414 if (regno
== INVALID_REGNUM
)
25418 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
25420 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
25421 RTVEC_ELT (p
, i
) = insn
;
25422 RTX_FRAME_RELATED_P (insn
) = 1;
25425 insn
= emit_insn (gen_blockage ());
25426 RTX_FRAME_RELATED_P (insn
) = 1;
25427 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
25430 /* In AIX ABI we need to make sure r2 is really saved. */
25431 if (TARGET_AIX
&& crtl
->calls_eh_return
)
25433 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
25434 rtx save_insn
, join_insn
, note
;
25435 long toc_restore_insn
;
25437 tmp_reg
= gen_rtx_REG (Pmode
, 11);
25438 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
25439 if (using_static_chain_p
)
25442 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
25446 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
25447 /* Peek at instruction to which this function returns. If it's
25448 restoring r2, then we know we've already saved r2. We can't
25449 unconditionally save r2 because the value we have will already
25450 be updated if we arrived at this function via a plt call or
25451 toc adjusting stub. */
25452 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
25453 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
25454 + RS6000_TOC_SAVE_SLOT
);
25455 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
25456 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
25457 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
25458 validate_condition_mode (EQ
, CCUNSmode
);
25459 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
25460 emit_insn (gen_rtx_SET (compare_result
,
25461 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
25462 toc_save_done
= gen_label_rtx ();
25463 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
25464 gen_rtx_EQ (VOIDmode
, compare_result
,
25466 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
25468 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
25469 JUMP_LABEL (jump
) = toc_save_done
;
25470 LABEL_NUSES (toc_save_done
) += 1;
25472 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
25473 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
25474 sp_off
- frame_off
);
25476 emit_label (toc_save_done
);
25478 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
25479 have a CFG that has different saves along different paths.
25480 Move the note to a dummy blockage insn, which describes that
25481 R2 is unconditionally saved after the label. */
25482 /* ??? An alternate representation might be a special insn pattern
25483 containing both the branch and the store. That might let the
25484 code that minimizes the number of DW_CFA_advance opcodes better
25485 freedom in placing the annotations. */
25486 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
25488 remove_note (save_insn
, note
);
25490 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
25491 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
25492 RTX_FRAME_RELATED_P (save_insn
) = 0;
25494 join_insn
= emit_insn (gen_blockage ());
25495 REG_NOTES (join_insn
) = note
;
25496 RTX_FRAME_RELATED_P (join_insn
) = 1;
25498 if (using_static_chain_p
)
25500 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
25507 /* Save CR if we use any that must be preserved. */
25508 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
25510 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
25511 GEN_INT (info
->cr_save_offset
+ frame_off
));
25512 rtx mem
= gen_frame_mem (SImode
, addr
);
25514 /* If we didn't copy cr before, do so now using r0. */
25515 if (cr_save_rtx
== NULL_RTX
)
25518 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
25519 rs6000_emit_move_from_cr (cr_save_rtx
);
25522 /* Saving CR requires a two-instruction sequence: one instruction
25523 to move the CR to a general-purpose register, and a second
25524 instruction that stores the GPR to memory.
25526 We do not emit any DWARF CFI records for the first of these,
25527 because we cannot properly represent the fact that CR is saved in
25528 a register. One reason is that we cannot express that multiple
25529 CR fields are saved; another reason is that on 64-bit, the size
25530 of the CR register in DWARF (4 bytes) differs from the size of
25531 a general-purpose register.
25533 This means if any intervening instruction were to clobber one of
25534 the call-saved CR fields, we'd have incorrect CFI. To prevent
25535 this from happening, we mark the store to memory as a use of
25536 those CR fields, which prevents any such instruction from being
25537 scheduled in between the two instructions. */
25542 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
25543 for (i
= 0; i
< 8; i
++)
25544 if (save_reg_p (CR0_REGNO
+ i
))
25545 crsave_v
[n_crsave
++]
25546 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
25548 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
25549 gen_rtvec_v (n_crsave
, crsave_v
)));
25550 END_USE (REGNO (cr_save_rtx
));
25552 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
25553 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
25554 so we need to construct a frame expression manually. */
25555 RTX_FRAME_RELATED_P (insn
) = 1;
25557 /* Update address to be stack-pointer relative, like
25558 rs6000_frame_related would do. */
25559 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
25560 GEN_INT (info
->cr_save_offset
+ sp_off
));
25561 mem
= gen_frame_mem (SImode
, addr
);
25563 if (DEFAULT_ABI
== ABI_ELFv2
)
25565 /* In the ELFv2 ABI we generate separate CFI records for each
25566 CR field that was actually saved. They all point to the
25567 same 32-bit stack slot. */
25571 for (i
= 0; i
< 8; i
++)
25572 if (save_reg_p (CR0_REGNO
+ i
))
25575 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
25577 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
25581 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25582 gen_rtx_PARALLEL (VOIDmode
,
25583 gen_rtvec_v (n_crframe
, crframe
)));
25587 /* In other ABIs, by convention, we use a single CR regnum to
25588 represent the fact that all call-saved CR fields are saved.
25589 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
25590 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
25591 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
25595 /* In the ELFv2 ABI we need to save all call-saved CR fields into
25596 *separate* slots if the routine calls __builtin_eh_return, so
25597 that they can be independently restored by the unwinder. */
25598 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
25600 int i
, cr_off
= info
->ehcr_offset
;
25603 /* ??? We might get better performance by using multiple mfocrf
25605 crsave
= gen_rtx_REG (SImode
, 0);
25606 emit_insn (gen_movesi_from_cr (crsave
));
25608 for (i
= 0; i
< 8; i
++)
25609 if (!call_used_regs
[CR0_REGNO
+ i
])
25611 rtvec p
= rtvec_alloc (2);
25613 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
25615 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
25617 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25619 RTX_FRAME_RELATED_P (insn
) = 1;
25620 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
25621 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
25622 sp_reg_rtx
, cr_off
+ sp_off
));
25624 cr_off
+= reg_size
;
25628 /* Update stack and set back pointer unless this is V.4,
25629 for which it was done previously. */
25630 if (!WORLD_SAVE_P (info
) && info
->push_p
25631 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
25633 rtx ptr_reg
= NULL
;
25636 /* If saving altivec regs we need to be able to address all save
25637 locations using a 16-bit offset. */
25638 if ((strategy
& SAVE_INLINE_VRS
) == 0
25639 || (info
->altivec_size
!= 0
25640 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
25641 + info
->total_size
- frame_off
) > 32767)
25642 || (info
->vrsave_size
!= 0
25643 && (info
->vrsave_save_offset
25644 + info
->total_size
- frame_off
) > 32767))
25646 int sel
= SAVRES_SAVE
| SAVRES_VR
;
25647 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
25649 if (using_static_chain_p
25650 && ptr_regno
== STATIC_CHAIN_REGNUM
)
25652 if (REGNO (frame_reg_rtx
) != ptr_regno
)
25653 START_USE (ptr_regno
);
25654 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
25655 frame_reg_rtx
= ptr_reg
;
25656 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
25657 frame_off
= -ptr_off
;
25659 else if (REGNO (frame_reg_rtx
) == 1)
25660 frame_off
= info
->total_size
;
25661 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
25663 if (REGNO (frame_reg_rtx
) == 12)
25665 sp_off
= info
->total_size
;
25666 if (frame_reg_rtx
!= sp_reg_rtx
)
25667 rs6000_emit_stack_tie (frame_reg_rtx
, false);
25670 /* Set frame pointer, if needed. */
25671 if (frame_pointer_needed
)
25673 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
25675 RTX_FRAME_RELATED_P (insn
) = 1;
25678 /* Save AltiVec registers if needed. Save here because the red zone does
25679 not always include AltiVec registers. */
25680 if (!WORLD_SAVE_P (info
)
25681 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
25683 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
25685 /* Oddly, the vector save/restore functions point r0 at the end
25686 of the save area, then use r11 or r12 to load offsets for
25687 [reg+reg] addressing. */
25688 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
25689 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
25690 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
25692 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
25694 if (scratch_regno
== 12)
25696 if (end_save
+ frame_off
!= 0)
25698 rtx offset
= GEN_INT (end_save
+ frame_off
);
25700 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
25703 emit_move_insn (ptr_reg
, frame_reg_rtx
);
25705 ptr_off
= -end_save
;
25706 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
25707 info
->altivec_save_offset
+ ptr_off
,
25708 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
25709 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
25710 NULL_RTX
, NULL_RTX
);
25711 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
25713 /* The oddity mentioned above clobbered our frame reg. */
25714 emit_move_insn (frame_reg_rtx
, ptr_reg
);
25715 frame_off
= ptr_off
;
25718 else if (!WORLD_SAVE_P (info
)
25719 && info
->altivec_size
!= 0)
25723 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25724 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25726 rtx areg
, savereg
, mem
;
25729 offset
= (info
->altivec_save_offset
+ frame_off
25730 + 16 * (i
- info
->first_altivec_reg_save
));
25732 savereg
= gen_rtx_REG (V4SImode
, i
);
25735 areg
= gen_rtx_REG (Pmode
, 0);
25736 emit_move_insn (areg
, GEN_INT (offset
));
25738 /* AltiVec addressing mode is [reg+reg]. */
25739 mem
= gen_frame_mem (V4SImode
,
25740 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
25742 /* Rather than emitting a generic move, force use of the stvx
25743 instruction, which we always want. In particular we don't
25744 want xxpermdi/stxvd2x for little endian. */
25745 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
25747 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
25748 areg
, GEN_INT (offset
));
25752 /* VRSAVE is a bit vector representing which AltiVec registers
25753 are used. The OS uses this to determine which vector
25754 registers to save on a context switch. We need to save
25755 VRSAVE on the stack frame, add whatever AltiVec registers we
25756 used in this function, and do the corresponding magic in the
25759 if (!WORLD_SAVE_P (info
)
25760 && info
->vrsave_size
!= 0)
25766 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
25767 be using r12 as frame_reg_rtx and r11 as the static chain
25768 pointer for nested functions. */
25770 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25771 && !using_static_chain_p
)
25773 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
25776 if (using_static_chain_p
)
25780 NOT_INUSE (save_regno
);
25781 reg
= gen_rtx_REG (SImode
, save_regno
);
25782 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
25784 emit_insn (gen_get_vrsave_internal (reg
));
25786 emit_insn (gen_rtx_SET (reg
, vrsave
));
25789 offset
= info
->vrsave_save_offset
+ frame_off
;
25790 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
25792 /* Include the registers in the mask. */
25793 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
25795 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
25798 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
25799 if (!TARGET_SINGLE_PIC_BASE
25800 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
25801 || (DEFAULT_ABI
== ABI_V4
25802 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
25803 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
25805 /* If emit_load_toc_table will use the link register, we need to save
25806 it. We use R12 for this purpose because emit_load_toc_table
25807 can use register 0. This allows us to use a plain 'blr' to return
25808 from the procedure more often. */
25809 int save_LR_around_toc_setup
= (TARGET_ELF
25810 && DEFAULT_ABI
== ABI_V4
25812 && ! info
->lr_save_p
25813 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
25814 if (save_LR_around_toc_setup
)
25816 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
25817 rtx tmp
= gen_rtx_REG (Pmode
, 12);
25820 insn
= emit_move_insn (tmp
, lr
);
25821 RTX_FRAME_RELATED_P (insn
) = 1;
25823 rs6000_emit_load_toc_table (TRUE
);
25825 insn
= emit_move_insn (lr
, tmp
);
25826 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
25827 RTX_FRAME_RELATED_P (insn
) = 1;
25830 rs6000_emit_load_toc_table (TRUE
);
25834 if (!TARGET_SINGLE_PIC_BASE
25835 && DEFAULT_ABI
== ABI_DARWIN
25836 && flag_pic
&& crtl
->uses_pic_offset_table
)
25838 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
25839 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
25841 /* Save and restore LR locally around this call (in R0). */
25842 if (!info
->lr_save_p
)
25843 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
25845 emit_insn (gen_load_macho_picbase (src
));
25847 emit_move_insn (gen_rtx_REG (Pmode
,
25848 RS6000_PIC_OFFSET_TABLE_REGNUM
),
25851 if (!info
->lr_save_p
)
25852 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
25856 /* If we need to, save the TOC register after doing the stack setup.
25857 Do not emit eh frame info for this save. The unwinder wants info,
25858 conceptually attached to instructions in this function, about
25859 register values in the caller of this function. This R2 may have
25860 already been changed from the value in the caller.
25861 We don't attempt to write accurate DWARF EH frame info for R2
25862 because code emitted by gcc for a (non-pointer) function call
25863 doesn't save and restore R2. Instead, R2 is managed out-of-line
25864 by a linker generated plt call stub when the function resides in
25865 a shared library. This behaviour is costly to describe in DWARF,
25866 both in terms of the size of DWARF info and the time taken in the
25867 unwinder to interpret it. R2 changes, apart from the
25868 calls_eh_return case earlier in this function, are handled by
25869 linux-unwind.h frob_update_context. */
25870 if (rs6000_save_toc_in_prologue_p ())
25872 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
25873 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
25876 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
25878 /* Set up the arg pointer (r12) for -fsplit-stack code. If
25879 __morestack was called, it left the arg pointer to the old
25880 stack in r29. Otherwise, the arg pointer is the top of the
25882 cfun
->machine
->split_stack_argp_used
= true;
25885 rtx r12
= gen_rtx_REG (Pmode
, 12);
25886 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
25887 emit_insn_before (set_r12
, sp_adjust
);
25889 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
25891 rtx r12
= gen_rtx_REG (Pmode
, 12);
25892 if (frame_off
== 0)
25893 emit_move_insn (r12
, frame_reg_rtx
);
25895 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
25899 rtx r12
= gen_rtx_REG (Pmode
, 12);
25900 rtx r29
= gen_rtx_REG (Pmode
, 29);
25901 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
25902 rtx not_more
= gen_label_rtx ();
25905 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
25906 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
25907 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
25909 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
25910 JUMP_LABEL (jump
) = not_more
;
25911 LABEL_NUSES (not_more
) += 1;
25912 emit_move_insn (r12
, r29
);
25913 emit_label (not_more
);
25918 /* Output .extern statements for the save/restore routines we use. */
25921 rs6000_output_savres_externs (FILE *file
)
25923 rs6000_stack_t
*info
= rs6000_stack_info ();
25925 if (TARGET_DEBUG_STACK
)
25926 debug_stack_info (info
);
25928 /* Write .extern for any function we will call to save and restore
25930 if (info
->first_fp_reg_save
< 64
25935 int regno
= info
->first_fp_reg_save
- 32;
25937 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
25939 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
25940 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25941 name
= rs6000_savres_routine_name (info
, regno
, sel
);
25942 fprintf (file
, "\t.extern %s\n", name
);
25944 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
25946 bool lr
= (info
->savres_strategy
25947 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
25948 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25949 name
= rs6000_savres_routine_name (info
, regno
, sel
);
25950 fprintf (file
, "\t.extern %s\n", name
);
25955 /* Write function prologue. */
25958 rs6000_output_function_prologue (FILE *file
,
25959 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
25961 if (!cfun
->is_thunk
)
25962 rs6000_output_savres_externs (file
);
25964 /* ELFv2 ABI r2 setup code and local entry point. This must follow
25965 immediately after the global entry point label. */
25966 if (rs6000_global_entry_point_needed_p ())
25968 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
25970 (*targetm
.asm_out
.internal_label
) (file
, "LCF", rs6000_pic_labelno
);
25972 if (TARGET_CMODEL
!= CMODEL_LARGE
)
25974 /* In the small and medium code models, we assume the TOC is less
25975 2 GB away from the text section, so it can be computed via the
25976 following two-instruction sequence. */
25979 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
25980 fprintf (file
, "0:\taddis 2,12,.TOC.-");
25981 assemble_name (file
, buf
);
25982 fprintf (file
, "@ha\n");
25983 fprintf (file
, "\taddi 2,2,.TOC.-");
25984 assemble_name (file
, buf
);
25985 fprintf (file
, "@l\n");
25989 /* In the large code model, we allow arbitrary offsets between the
25990 TOC and the text section, so we have to load the offset from
25991 memory. The data field is emitted directly before the global
25992 entry point in rs6000_elf_declare_function_name. */
25995 #ifdef HAVE_AS_ENTRY_MARKERS
25996 /* If supported by the linker, emit a marker relocation. If the
25997 total code size of the final executable or shared library
25998 happens to fit into 2 GB after all, the linker will replace
25999 this code sequence with the sequence for the small or medium
26001 fprintf (file
, "\t.reloc .,R_PPC64_ENTRY\n");
26003 fprintf (file
, "\tld 2,");
26004 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
26005 assemble_name (file
, buf
);
26006 fprintf (file
, "-");
26007 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
26008 assemble_name (file
, buf
);
26009 fprintf (file
, "(12)\n");
26010 fprintf (file
, "\tadd 2,2,12\n");
26013 fputs ("\t.localentry\t", file
);
26014 assemble_name (file
, name
);
26015 fputs (",.-", file
);
26016 assemble_name (file
, name
);
26017 fputs ("\n", file
);
26020 /* Output -mprofile-kernel code. This needs to be done here instead of
26021 in output_function_profile since it must go after the ELFv2 ABI
26022 local entry point. */
26023 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
26025 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
26026 gcc_assert (!TARGET_32BIT
);
26028 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
26030 /* In the ELFv2 ABI we have no compiler stack word. It must be
26031 the resposibility of _mcount to preserve the static chain
26032 register if required. */
26033 if (DEFAULT_ABI
!= ABI_ELFv2
26034 && cfun
->static_chain_decl
!= NULL
)
26036 asm_fprintf (file
, "\tstd %s,24(%s)\n",
26037 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
26038 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
26039 asm_fprintf (file
, "\tld %s,24(%s)\n",
26040 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
26043 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
26046 rs6000_pic_labelno
++;
26049 /* Non-zero if vmx regs are restored before the frame pop, zero if
26050 we restore after the pop when possible. */
26051 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
26053 /* Restoring cr is a two step process: loading a reg from the frame
26054 save, then moving the reg to cr. For ABI_V4 we must let the
26055 unwinder know that the stack location is no longer valid at or
26056 before the stack deallocation, but we can't emit a cfa_restore for
26057 cr at the stack deallocation like we do for other registers.
26058 The trouble is that it is possible for the move to cr to be
26059 scheduled after the stack deallocation. So say exactly where cr
26060 is located on each of the two insns. */
26063 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
26065 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
26066 rtx reg
= gen_rtx_REG (SImode
, regno
);
26067 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
26069 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
26071 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
26072 rtx set
= gen_rtx_SET (reg
, cr
);
26074 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
26075 RTX_FRAME_RELATED_P (insn
) = 1;
26080 /* Reload CR from REG. */
26083 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
26088 if (using_mfcr_multiple
)
26090 for (i
= 0; i
< 8; i
++)
26091 if (save_reg_p (CR0_REGNO
+ i
))
26093 gcc_assert (count
);
26096 if (using_mfcr_multiple
&& count
> 1)
26102 p
= rtvec_alloc (count
);
26105 for (i
= 0; i
< 8; i
++)
26106 if (save_reg_p (CR0_REGNO
+ i
))
26108 rtvec r
= rtvec_alloc (2);
26109 RTVEC_ELT (r
, 0) = reg
;
26110 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
26111 RTVEC_ELT (p
, ndx
) =
26112 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
26113 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
26116 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26117 gcc_assert (ndx
== count
);
26119 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
26120 CR field separately. */
26121 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
26123 for (i
= 0; i
< 8; i
++)
26124 if (save_reg_p (CR0_REGNO
+ i
))
26125 add_reg_note (insn
, REG_CFA_RESTORE
,
26126 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
26128 RTX_FRAME_RELATED_P (insn
) = 1;
26132 for (i
= 0; i
< 8; i
++)
26133 if (save_reg_p (CR0_REGNO
+ i
))
26135 rtx insn
= emit_insn (gen_movsi_to_cr_one
26136 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
26138 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
26139 CR field separately, attached to the insn that in fact
26140 restores this particular CR field. */
26141 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
26143 add_reg_note (insn
, REG_CFA_RESTORE
,
26144 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
26146 RTX_FRAME_RELATED_P (insn
) = 1;
26150 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
26151 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
26152 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
26154 rtx_insn
*insn
= get_last_insn ();
26155 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
26157 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
26158 RTX_FRAME_RELATED_P (insn
) = 1;
26162 /* Like cr, the move to lr instruction can be scheduled after the
26163 stack deallocation, but unlike cr, its stack frame save is still
26164 valid. So we only need to emit the cfa_restore on the correct
26168 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
26170 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
26171 rtx reg
= gen_rtx_REG (Pmode
, regno
);
26173 emit_move_insn (reg
, mem
);
26177 restore_saved_lr (int regno
, bool exit_func
)
26179 rtx reg
= gen_rtx_REG (Pmode
, regno
);
26180 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
26181 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
26183 if (!exit_func
&& flag_shrink_wrap
)
26185 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
26186 RTX_FRAME_RELATED_P (insn
) = 1;
26191 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
26193 if (DEFAULT_ABI
== ABI_ELFv2
)
26196 for (i
= 0; i
< 8; i
++)
26197 if (save_reg_p (CR0_REGNO
+ i
))
26199 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
26200 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
26204 else if (info
->cr_save_p
)
26205 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
26206 gen_rtx_REG (SImode
, CR2_REGNO
),
26209 if (info
->lr_save_p
)
26210 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
26211 gen_rtx_REG (Pmode
, LR_REGNO
),
26213 return cfa_restores
;
26216 /* Return true if OFFSET from stack pointer can be clobbered by signals.
26217 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
26218 below stack pointer not cloberred by signals. */
26221 offset_below_red_zone_p (HOST_WIDE_INT offset
)
26223 return offset
< (DEFAULT_ABI
== ABI_V4
26225 : TARGET_32BIT
? -220 : -288);
26228 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
26231 emit_cfa_restores (rtx cfa_restores
)
26233 rtx_insn
*insn
= get_last_insn ();
26234 rtx
*loc
= ®_NOTES (insn
);
26237 loc
= &XEXP (*loc
, 1);
26238 *loc
= cfa_restores
;
26239 RTX_FRAME_RELATED_P (insn
) = 1;
26242 /* Emit function epilogue as insns. */
26245 rs6000_emit_epilogue (int sibcall
)
26247 rs6000_stack_t
*info
;
26248 int restoring_GPRs_inline
;
26249 int restoring_FPRs_inline
;
26250 int using_load_multiple
;
26251 int using_mtcr_multiple
;
26252 int use_backchain_to_restore_sp
;
26255 HOST_WIDE_INT frame_off
= 0;
26256 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
26257 rtx frame_reg_rtx
= sp_reg_rtx
;
26258 rtx cfa_restores
= NULL_RTX
;
26260 rtx cr_save_reg
= NULL_RTX
;
26261 machine_mode reg_mode
= Pmode
;
26262 int reg_size
= TARGET_32BIT
? 4 : 8;
26265 unsigned ptr_regno
;
26267 info
= rs6000_stack_info ();
26269 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
26271 reg_mode
= V2SImode
;
26275 strategy
= info
->savres_strategy
;
26276 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
26277 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
26278 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
26279 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
26280 || rs6000_cpu
== PROCESSOR_PPC603
26281 || rs6000_cpu
== PROCESSOR_PPC750
26283 /* Restore via the backchain when we have a large frame, since this
26284 is more efficient than an addis, addi pair. The second condition
26285 here will not trigger at the moment; We don't actually need a
26286 frame pointer for alloca, but the generic parts of the compiler
26287 give us one anyway. */
26288 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
26289 ? info
->lr_save_offset
26291 || (cfun
->calls_alloca
26292 && !frame_pointer_needed
));
26293 restore_lr
= (info
->lr_save_p
26294 && (restoring_FPRs_inline
26295 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
26296 && (restoring_GPRs_inline
26297 || info
->first_fp_reg_save
< 64));
26299 if (WORLD_SAVE_P (info
))
26303 const char *alloc_rname
;
26306 /* eh_rest_world_r10 will return to the location saved in the LR
26307 stack slot (which is not likely to be our caller.)
26308 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
26309 rest_world is similar, except any R10 parameter is ignored.
26310 The exception-handling stuff that was here in 2.95 is no
26311 longer necessary. */
26315 + 32 - info
->first_gp_reg_save
26316 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
26317 + 63 + 1 - info
->first_fp_reg_save
);
26319 strcpy (rname
, ((crtl
->calls_eh_return
) ?
26320 "*eh_rest_world_r10" : "*rest_world"));
26321 alloc_rname
= ggc_strdup (rname
);
26324 RTVEC_ELT (p
, j
++) = ret_rtx
;
26325 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
26326 gen_rtx_REG (Pmode
,
26329 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
26330 /* The instruction pattern requires a clobber here;
26331 it is shared with the restVEC helper. */
26333 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
26336 /* CR register traditionally saved as CR2. */
26337 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
26339 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
26340 if (flag_shrink_wrap
)
26342 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
26343 gen_rtx_REG (Pmode
, LR_REGNO
),
26345 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26349 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26351 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
26353 = gen_frame_load (reg
,
26354 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
26355 if (flag_shrink_wrap
)
26356 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26358 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
26360 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
26362 = gen_frame_load (reg
,
26363 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
26364 if (flag_shrink_wrap
)
26365 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26367 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
26369 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
26370 ? DFmode
: SFmode
),
26371 info
->first_fp_reg_save
+ i
);
26373 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
26374 if (flag_shrink_wrap
)
26375 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26378 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
26380 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
26382 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
26384 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
26386 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
26387 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26389 if (flag_shrink_wrap
)
26391 REG_NOTES (insn
) = cfa_restores
;
26392 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
26393 RTX_FRAME_RELATED_P (insn
) = 1;
26398 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
26400 frame_off
= info
->total_size
;
26402 /* Restore AltiVec registers if we must do so before adjusting the
26404 if (info
->altivec_size
!= 0
26405 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
26406 || (DEFAULT_ABI
!= ABI_V4
26407 && offset_below_red_zone_p (info
->altivec_save_offset
))))
26410 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
26412 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
26413 if (use_backchain_to_restore_sp
)
26415 int frame_regno
= 11;
26417 if ((strategy
& REST_INLINE_VRS
) == 0)
26419 /* Of r11 and r12, select the one not clobbered by an
26420 out-of-line restore function for the frame register. */
26421 frame_regno
= 11 + 12 - scratch_regno
;
26423 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
26424 emit_move_insn (frame_reg_rtx
,
26425 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
26428 else if (frame_pointer_needed
)
26429 frame_reg_rtx
= hard_frame_pointer_rtx
;
26431 if ((strategy
& REST_INLINE_VRS
) == 0)
26433 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
26435 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
26436 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
26438 if (end_save
+ frame_off
!= 0)
26440 rtx offset
= GEN_INT (end_save
+ frame_off
);
26442 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
26445 emit_move_insn (ptr_reg
, frame_reg_rtx
);
26447 ptr_off
= -end_save
;
26448 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
26449 info
->altivec_save_offset
+ ptr_off
,
26450 0, V4SImode
, SAVRES_VR
);
26454 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
26455 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
26457 rtx addr
, areg
, mem
, reg
;
26459 areg
= gen_rtx_REG (Pmode
, 0);
26461 (areg
, GEN_INT (info
->altivec_save_offset
26463 + 16 * (i
- info
->first_altivec_reg_save
)));
26465 /* AltiVec addressing mode is [reg+reg]. */
26466 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
26467 mem
= gen_frame_mem (V4SImode
, addr
);
26469 reg
= gen_rtx_REG (V4SImode
, i
);
26470 /* Rather than emitting a generic move, force use of the
26471 lvx instruction, which we always want. In particular
26472 we don't want lxvd2x/xxpermdi for little endian. */
26473 (void) emit_insn (gen_altivec_lvx_v4si_internal (reg
, mem
));
26477 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
26478 if (((strategy
& REST_INLINE_VRS
) == 0
26479 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
26480 && (flag_shrink_wrap
26481 || (offset_below_red_zone_p
26482 (info
->altivec_save_offset
26483 + 16 * (i
- info
->first_altivec_reg_save
)))))
26485 rtx reg
= gen_rtx_REG (V4SImode
, i
);
26486 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26490 /* Restore VRSAVE if we must do so before adjusting the stack. */
26491 if (info
->vrsave_size
!= 0
26492 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
26493 || (DEFAULT_ABI
!= ABI_V4
26494 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
26498 if (frame_reg_rtx
== sp_reg_rtx
)
26500 if (use_backchain_to_restore_sp
)
26502 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
26503 emit_move_insn (frame_reg_rtx
,
26504 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
26507 else if (frame_pointer_needed
)
26508 frame_reg_rtx
= hard_frame_pointer_rtx
;
26511 reg
= gen_rtx_REG (SImode
, 12);
26512 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
26513 info
->vrsave_save_offset
+ frame_off
));
26515 emit_insn (generate_set_vrsave (reg
, info
, 1));
26519 /* If we have a large stack frame, restore the old stack pointer
26520 using the backchain. */
26521 if (use_backchain_to_restore_sp
)
26523 if (frame_reg_rtx
== sp_reg_rtx
)
26525 /* Under V.4, don't reset the stack pointer until after we're done
26526 loading the saved registers. */
26527 if (DEFAULT_ABI
== ABI_V4
)
26528 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
26530 insn
= emit_move_insn (frame_reg_rtx
,
26531 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
26534 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
26535 && DEFAULT_ABI
== ABI_V4
)
26536 /* frame_reg_rtx has been set up by the altivec restore. */
26540 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
26541 frame_reg_rtx
= sp_reg_rtx
;
26544 /* If we have a frame pointer, we can restore the old stack pointer
26546 else if (frame_pointer_needed
)
26548 frame_reg_rtx
= sp_reg_rtx
;
26549 if (DEFAULT_ABI
== ABI_V4
)
26550 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
26551 /* Prevent reordering memory accesses against stack pointer restore. */
26552 else if (cfun
->calls_alloca
26553 || offset_below_red_zone_p (-info
->total_size
))
26554 rs6000_emit_stack_tie (frame_reg_rtx
, true);
26556 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
26557 GEN_INT (info
->total_size
)));
26560 else if (info
->push_p
26561 && DEFAULT_ABI
!= ABI_V4
26562 && !crtl
->calls_eh_return
)
26564 /* Prevent reordering memory accesses against stack pointer restore. */
26565 if (cfun
->calls_alloca
26566 || offset_below_red_zone_p (-info
->total_size
))
26567 rs6000_emit_stack_tie (frame_reg_rtx
, false);
26568 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
26569 GEN_INT (info
->total_size
)));
26572 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
26576 REG_NOTES (insn
) = cfa_restores
;
26577 cfa_restores
= NULL_RTX
;
26579 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
26580 RTX_FRAME_RELATED_P (insn
) = 1;
26583 /* Restore AltiVec registers if we have not done so already. */
26584 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
26585 && info
->altivec_size
!= 0
26586 && (DEFAULT_ABI
== ABI_V4
26587 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
26591 if ((strategy
& REST_INLINE_VRS
) == 0)
26593 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
26595 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
26596 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
26597 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
26599 if (end_save
+ frame_off
!= 0)
26601 rtx offset
= GEN_INT (end_save
+ frame_off
);
26603 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
26606 emit_move_insn (ptr_reg
, frame_reg_rtx
);
26608 ptr_off
= -end_save
;
26609 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
26610 info
->altivec_save_offset
+ ptr_off
,
26611 0, V4SImode
, SAVRES_VR
);
26612 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
26614 /* Frame reg was clobbered by out-of-line save. Restore it
26615 from ptr_reg, and if we are calling out-of-line gpr or
26616 fpr restore set up the correct pointer and offset. */
26617 unsigned newptr_regno
= 1;
26618 if (!restoring_GPRs_inline
)
26620 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
26621 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
26622 newptr_regno
= ptr_regno_for_savres (sel
);
26623 end_save
= info
->gp_save_offset
+ info
->gp_size
;
26625 else if (!restoring_FPRs_inline
)
26627 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
26628 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
26629 newptr_regno
= ptr_regno_for_savres (sel
);
26630 end_save
= info
->fp_save_offset
+ info
->fp_size
;
26633 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
26634 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
26636 if (end_save
+ ptr_off
!= 0)
26638 rtx offset
= GEN_INT (end_save
+ ptr_off
);
26640 frame_off
= -end_save
;
26642 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
26645 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
26650 frame_off
= ptr_off
;
26651 emit_move_insn (frame_reg_rtx
, ptr_reg
);
26657 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
26658 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
26660 rtx addr
, areg
, mem
, reg
;
26662 areg
= gen_rtx_REG (Pmode
, 0);
26664 (areg
, GEN_INT (info
->altivec_save_offset
26666 + 16 * (i
- info
->first_altivec_reg_save
)));
26668 /* AltiVec addressing mode is [reg+reg]. */
26669 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
26670 mem
= gen_frame_mem (V4SImode
, addr
);
26672 reg
= gen_rtx_REG (V4SImode
, i
);
26673 /* Rather than emitting a generic move, force use of the
26674 lvx instruction, which we always want. In particular
26675 we don't want lxvd2x/xxpermdi for little endian. */
26676 (void) emit_insn (gen_altivec_lvx_v4si_internal (reg
, mem
));
26680 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
26681 if (((strategy
& REST_INLINE_VRS
) == 0
26682 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
26683 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
26685 rtx reg
= gen_rtx_REG (V4SImode
, i
);
26686 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26690 /* Restore VRSAVE if we have not done so already. */
26691 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
26692 && info
->vrsave_size
!= 0
26693 && (DEFAULT_ABI
== ABI_V4
26694 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
26698 reg
= gen_rtx_REG (SImode
, 12);
26699 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
26700 info
->vrsave_save_offset
+ frame_off
));
26702 emit_insn (generate_set_vrsave (reg
, info
, 1));
26705 /* If we exit by an out-of-line restore function on ABI_V4 then that
26706 function will deallocate the stack, so we don't need to worry
26707 about the unwinder restoring cr from an invalid stack frame
26709 exit_func
= (!restoring_FPRs_inline
26710 || (!restoring_GPRs_inline
26711 && info
->first_fp_reg_save
== 64));
26713 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
26714 *separate* slots if the routine calls __builtin_eh_return, so
26715 that they can be independently restored by the unwinder. */
26716 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
26718 int i
, cr_off
= info
->ehcr_offset
;
26720 for (i
= 0; i
< 8; i
++)
26721 if (!call_used_regs
[CR0_REGNO
+ i
])
26723 rtx reg
= gen_rtx_REG (SImode
, 0);
26724 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
26725 cr_off
+ frame_off
));
26727 insn
= emit_insn (gen_movsi_to_cr_one
26728 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
26730 if (!exit_func
&& flag_shrink_wrap
)
26732 add_reg_note (insn
, REG_CFA_RESTORE
,
26733 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
26735 RTX_FRAME_RELATED_P (insn
) = 1;
26738 cr_off
+= reg_size
;
26742 /* Get the old lr if we saved it. If we are restoring registers
26743 out-of-line, then the out-of-line routines can do this for us. */
26744 if (restore_lr
&& restoring_GPRs_inline
)
26745 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
26747 /* Get the old cr if we saved it. */
26748 if (info
->cr_save_p
)
26750 unsigned cr_save_regno
= 12;
26752 if (!restoring_GPRs_inline
)
26754 /* Ensure we don't use the register used by the out-of-line
26755 gpr register restore below. */
26756 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
26757 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
26758 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
26760 if (gpr_ptr_regno
== 12)
26761 cr_save_regno
= 11;
26762 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
26764 else if (REGNO (frame_reg_rtx
) == 12)
26765 cr_save_regno
= 11;
26767 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
26768 info
->cr_save_offset
+ frame_off
,
26772 /* Set LR here to try to overlap restores below. */
26773 if (restore_lr
&& restoring_GPRs_inline
)
26774 restore_saved_lr (0, exit_func
);
26776 /* Load exception handler data registers, if needed. */
26777 if (crtl
->calls_eh_return
)
26779 unsigned int i
, regno
;
26783 rtx reg
= gen_rtx_REG (reg_mode
, 2);
26784 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
26785 frame_off
+ RS6000_TOC_SAVE_SLOT
));
26792 regno
= EH_RETURN_DATA_REGNO (i
);
26793 if (regno
== INVALID_REGNUM
)
26796 /* Note: possible use of r0 here to address SPE regs. */
26797 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
26798 info
->ehrd_offset
+ frame_off
26799 + reg_size
* (int) i
);
26801 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
26805 /* Restore GPRs. This is done as a PARALLEL if we are using
26806 the load-multiple instructions. */
26808 && info
->spe_64bit_regs_used
26809 && info
->first_gp_reg_save
!= 32)
26811 /* Determine whether we can address all of the registers that need
26812 to be saved with an offset from frame_reg_rtx that fits in
26813 the small const field for SPE memory instructions. */
26814 int spe_regs_addressable
26815 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
26816 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
26817 && restoring_GPRs_inline
);
26819 if (!spe_regs_addressable
)
26821 int ool_adjust
= 0;
26822 rtx old_frame_reg_rtx
= frame_reg_rtx
;
26823 /* Make r11 point to the start of the SPE save area. We worried about
26824 not clobbering it when we were saving registers in the prologue.
26825 There's no need to worry here because the static chain is passed
26826 anew to every function. */
26828 if (!restoring_GPRs_inline
)
26829 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
26830 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
26831 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
26832 GEN_INT (info
->spe_gp_save_offset
26835 /* Keep the invariant that frame_reg_rtx + frame_off points
26836 at the top of the stack frame. */
26837 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
26840 if (restoring_GPRs_inline
)
26842 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
26844 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26845 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
26847 rtx offset
, addr
, mem
, reg
;
26849 /* We're doing all this to ensure that the immediate offset
26850 fits into the immediate field of 'evldd'. */
26851 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
26853 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
26854 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
26855 mem
= gen_rtx_MEM (V2SImode
, addr
);
26856 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
26858 emit_move_insn (reg
, mem
);
26862 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
26863 info
->spe_gp_save_offset
+ frame_off
,
26864 info
->lr_save_offset
+ frame_off
,
26866 SAVRES_GPR
| SAVRES_LR
);
26868 else if (!restoring_GPRs_inline
)
26870 /* We are jumping to an out-of-line function. */
26872 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
26873 bool can_use_exit
= end_save
== 0;
26874 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
26877 /* Emit stack reset code if we need it. */
26878 ptr_regno
= ptr_regno_for_savres (sel
);
26879 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26881 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
26882 else if (end_save
+ frame_off
!= 0)
26883 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
26884 GEN_INT (end_save
+ frame_off
)));
26885 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
26886 emit_move_insn (ptr_reg
, frame_reg_rtx
);
26887 if (REGNO (frame_reg_rtx
) == ptr_regno
)
26888 frame_off
= -end_save
;
26890 if (can_use_exit
&& info
->cr_save_p
)
26891 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
26893 ptr_off
= -end_save
;
26894 rs6000_emit_savres_rtx (info
, ptr_reg
,
26895 info
->gp_save_offset
+ ptr_off
,
26896 info
->lr_save_offset
+ ptr_off
,
26899 else if (using_load_multiple
)
26902 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
26903 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26905 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26907 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
26908 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26912 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26913 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
26914 emit_insn (gen_frame_load
26915 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26917 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
26920 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
26922 /* If the frame pointer was used then we can't delay emitting
26923 a REG_CFA_DEF_CFA note. This must happen on the insn that
26924 restores the frame pointer, r31. We may have already emitted
26925 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
26926 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
26927 be harmless if emitted. */
26928 if (frame_pointer_needed
)
26930 insn
= get_last_insn ();
26931 add_reg_note (insn
, REG_CFA_DEF_CFA
,
26932 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
26933 RTX_FRAME_RELATED_P (insn
) = 1;
26936 /* Set up cfa_restores. We always need these when
26937 shrink-wrapping. If not shrink-wrapping then we only need
26938 the cfa_restore when the stack location is no longer valid.
26939 The cfa_restores must be emitted on or before the insn that
26940 invalidates the stack, and of course must not be emitted
26941 before the insn that actually does the restore. The latter
26942 is why it is a bad idea to emit the cfa_restores as a group
26943 on the last instruction here that actually does a restore:
26944 That insn may be reordered with respect to others doing
26946 if (flag_shrink_wrap
26947 && !restoring_GPRs_inline
26948 && info
->first_fp_reg_save
== 64)
26949 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
26951 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
26952 if (!restoring_GPRs_inline
26953 || using_load_multiple
26954 || rs6000_reg_live_or_pic_offset_p (i
))
26956 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26958 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26962 if (!restoring_GPRs_inline
26963 && info
->first_fp_reg_save
== 64)
26965 /* We are jumping to an out-of-line function. */
26967 emit_cfa_restores (cfa_restores
);
26971 if (restore_lr
&& !restoring_GPRs_inline
)
26973 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
26974 restore_saved_lr (0, exit_func
);
26977 /* Restore fpr's if we need to do it without calling a function. */
26978 if (restoring_FPRs_inline
)
26979 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
26980 if (save_reg_p (info
->first_fp_reg_save
+ i
))
26982 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
26983 ? DFmode
: SFmode
),
26984 info
->first_fp_reg_save
+ i
);
26985 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
26986 info
->fp_save_offset
+ frame_off
+ 8 * i
));
26987 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
26988 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26991 /* If we saved cr, restore it here. Just those that were used. */
26992 if (info
->cr_save_p
)
26993 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
26995 /* If this is V.4, unwind the stack pointer after all of the loads
26996 have been done, or set up r11 if we are restoring fp out of line. */
26998 if (!restoring_FPRs_inline
)
27000 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
27001 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
27002 ptr_regno
= ptr_regno_for_savres (sel
);
27005 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
27006 if (REGNO (frame_reg_rtx
) == ptr_regno
)
27009 if (insn
&& restoring_FPRs_inline
)
27013 REG_NOTES (insn
) = cfa_restores
;
27014 cfa_restores
= NULL_RTX
;
27016 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
27017 RTX_FRAME_RELATED_P (insn
) = 1;
27020 if (crtl
->calls_eh_return
)
27022 rtx sa
= EH_RETURN_STACKADJ_RTX
;
27023 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
27029 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
27030 if (! restoring_FPRs_inline
)
27032 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
27033 RTVEC_ELT (p
, 0) = ret_rtx
;
27039 /* We can't hang the cfa_restores off a simple return,
27040 since the shrink-wrap code sometimes uses an existing
27041 return. This means there might be a path from
27042 pre-prologue code to this return, and dwarf2cfi code
27043 wants the eh_frame unwinder state to be the same on
27044 all paths to any point. So we need to emit the
27045 cfa_restores before the return. For -m64 we really
27046 don't need epilogue cfa_restores at all, except for
27047 this irritating dwarf2cfi with shrink-wrap
27048 requirement; The stack red-zone means eh_frame info
27049 from the prologue telling the unwinder to restore
27050 from the stack is perfectly good right to the end of
27052 emit_insn (gen_blockage ());
27053 emit_cfa_restores (cfa_restores
);
27054 cfa_restores
= NULL_RTX
;
27056 p
= rtvec_alloc (2);
27057 RTVEC_ELT (p
, 0) = simple_return_rtx
;
27060 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
27061 ? gen_rtx_USE (VOIDmode
,
27062 gen_rtx_REG (Pmode
, LR_REGNO
))
27063 : gen_rtx_CLOBBER (VOIDmode
,
27064 gen_rtx_REG (Pmode
, LR_REGNO
)));
27066 /* If we have to restore more than two FP registers, branch to the
27067 restore function. It will return to our caller. */
27068 if (! restoring_FPRs_inline
)
27074 if (flag_shrink_wrap
)
27075 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
27077 sym
= rs6000_savres_routine_sym (info
,
27078 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
27079 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
27080 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
27081 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
27083 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
27085 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
27087 RTVEC_ELT (p
, i
+ 4)
27088 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
27089 if (flag_shrink_wrap
)
27090 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
27095 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27101 /* Ensure the cfa_restores are hung off an insn that won't
27102 be reordered above other restores. */
27103 emit_insn (gen_blockage ());
27105 emit_cfa_restores (cfa_restores
);
27109 /* Write function epilogue. */
27112 rs6000_output_function_epilogue (FILE *file
,
27113 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
27116 macho_branch_islands ();
27117 /* Mach-O doesn't support labels at the end of objects, so if
27118 it looks like we might want one, insert a NOP. */
27120 rtx_insn
*insn
= get_last_insn ();
27121 rtx_insn
*deleted_debug_label
= NULL
;
27124 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
27126 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
27127 notes only, instead set their CODE_LABEL_NUMBER to -1,
27128 otherwise there would be code generation differences
27129 in between -g and -g0. */
27130 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
27131 deleted_debug_label
= insn
;
27132 insn
= PREV_INSN (insn
);
27137 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
27138 fputs ("\tnop\n", file
);
27139 else if (deleted_debug_label
)
27140 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
27141 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
27142 CODE_LABEL_NUMBER (insn
) = -1;
27146 /* Output a traceback table here. See /usr/include/sys/debug.h for info
27149 We don't output a traceback table if -finhibit-size-directive was
27150 used. The documentation for -finhibit-size-directive reads
27151 ``don't output a @code{.size} assembler directive, or anything
27152 else that would cause trouble if the function is split in the
27153 middle, and the two halves are placed at locations far apart in
27154 memory.'' The traceback table has this property, since it
27155 includes the offset from the start of the function to the
27156 traceback table itself.
27158 System V.4 Powerpc's (and the embedded ABI derived from it) use a
27159 different traceback table. */
27160 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27161 && ! flag_inhibit_size_directive
27162 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
27164 const char *fname
= NULL
;
27165 const char *language_string
= lang_hooks
.name
;
27166 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
27168 int optional_tbtab
;
27169 rs6000_stack_t
*info
= rs6000_stack_info ();
27171 if (rs6000_traceback
== traceback_full
)
27172 optional_tbtab
= 1;
27173 else if (rs6000_traceback
== traceback_part
)
27174 optional_tbtab
= 0;
27176 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
27178 if (optional_tbtab
)
27180 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
27181 while (*fname
== '.') /* V.4 encodes . in the name */
27184 /* Need label immediately before tbtab, so we can compute
27185 its offset from the function start. */
27186 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
27187 ASM_OUTPUT_LABEL (file
, fname
);
27190 /* The .tbtab pseudo-op can only be used for the first eight
27191 expressions, since it can't handle the possibly variable
27192 length fields that follow. However, if you omit the optional
27193 fields, the assembler outputs zeros for all optional fields
27194 anyways, giving each variable length field is minimum length
27195 (as defined in sys/debug.h). Thus we can not use the .tbtab
27196 pseudo-op at all. */
27198 /* An all-zero word flags the start of the tbtab, for debuggers
27199 that have to find it by searching forward from the entry
27200 point or from the current pc. */
27201 fputs ("\t.long 0\n", file
);
27203 /* Tbtab format type. Use format type 0. */
27204 fputs ("\t.byte 0,", file
);
27206 /* Language type. Unfortunately, there does not seem to be any
27207 official way to discover the language being compiled, so we
27208 use language_string.
27209 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
27210 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
27211 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
27212 either, so for now use 0. */
27214 || ! strcmp (language_string
, "GNU GIMPLE")
27215 || ! strcmp (language_string
, "GNU Go")
27216 || ! strcmp (language_string
, "libgccjit"))
27218 else if (! strcmp (language_string
, "GNU F77")
27219 || lang_GNU_Fortran ())
27221 else if (! strcmp (language_string
, "GNU Pascal"))
27223 else if (! strcmp (language_string
, "GNU Ada"))
27225 else if (lang_GNU_CXX ()
27226 || ! strcmp (language_string
, "GNU Objective-C++"))
27228 else if (! strcmp (language_string
, "GNU Java"))
27230 else if (! strcmp (language_string
, "GNU Objective-C"))
27233 gcc_unreachable ();
27234 fprintf (file
, "%d,", i
);
27236 /* 8 single bit fields: global linkage (not set for C extern linkage,
27237 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
27238 from start of procedure stored in tbtab, internal function, function
27239 has controlled storage, function has no toc, function uses fp,
27240 function logs/aborts fp operations. */
27241 /* Assume that fp operations are used if any fp reg must be saved. */
27242 fprintf (file
, "%d,",
27243 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
27245 /* 6 bitfields: function is interrupt handler, name present in
27246 proc table, function calls alloca, on condition directives
27247 (controls stack walks, 3 bits), saves condition reg, saves
27249 /* The `function calls alloca' bit seems to be set whenever reg 31 is
27250 set up as a frame pointer, even when there is no alloca call. */
27251 fprintf (file
, "%d,",
27252 ((optional_tbtab
<< 6)
27253 | ((optional_tbtab
& frame_pointer_needed
) << 5)
27254 | (info
->cr_save_p
<< 1)
27255 | (info
->lr_save_p
)));
27257 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
27259 fprintf (file
, "%d,",
27260 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
27262 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
27263 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
27265 if (optional_tbtab
)
27267 /* Compute the parameter info from the function decl argument
27270 int next_parm_info_bit
= 31;
27272 for (decl
= DECL_ARGUMENTS (current_function_decl
);
27273 decl
; decl
= DECL_CHAIN (decl
))
27275 rtx parameter
= DECL_INCOMING_RTL (decl
);
27276 machine_mode mode
= GET_MODE (parameter
);
27278 if (GET_CODE (parameter
) == REG
)
27280 if (SCALAR_FLOAT_MODE_P (mode
))
27303 gcc_unreachable ();
27306 /* If only one bit will fit, don't or in this entry. */
27307 if (next_parm_info_bit
> 0)
27308 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
27309 next_parm_info_bit
-= 2;
27313 fixed_parms
+= ((GET_MODE_SIZE (mode
)
27314 + (UNITS_PER_WORD
- 1))
27316 next_parm_info_bit
-= 1;
27322 /* Number of fixed point parameters. */
27323 /* This is actually the number of words of fixed point parameters; thus
27324 an 8 byte struct counts as 2; and thus the maximum value is 8. */
27325 fprintf (file
, "%d,", fixed_parms
);
27327 /* 2 bitfields: number of floating point parameters (7 bits), parameters
27329 /* This is actually the number of fp registers that hold parameters;
27330 and thus the maximum value is 13. */
27331 /* Set parameters on stack bit if parameters are not in their original
27332 registers, regardless of whether they are on the stack? Xlc
27333 seems to set the bit when not optimizing. */
27334 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
27336 if (! optional_tbtab
)
27339 /* Optional fields follow. Some are variable length. */
27341 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
27342 11 double float. */
27343 /* There is an entry for each parameter in a register, in the order that
27344 they occur in the parameter list. Any intervening arguments on the
27345 stack are ignored. If the list overflows a long (max possible length
27346 34 bits) then completely leave off all elements that don't fit. */
27347 /* Only emit this long if there was at least one parameter. */
27348 if (fixed_parms
|| float_parms
)
27349 fprintf (file
, "\t.long %d\n", parm_info
);
27351 /* Offset from start of code to tb table. */
27352 fputs ("\t.long ", file
);
27353 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
27354 RS6000_OUTPUT_BASENAME (file
, fname
);
27356 rs6000_output_function_entry (file
, fname
);
27359 /* Interrupt handler mask. */
27360 /* Omit this long, since we never set the interrupt handler bit
27363 /* Number of CTL (controlled storage) anchors. */
27364 /* Omit this long, since the has_ctl bit is never set above. */
27366 /* Displacement into stack of each CTL anchor. */
27367 /* Omit this list of longs, because there are no CTL anchors. */
27369 /* Length of function name. */
27372 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
27374 /* Function name. */
27375 assemble_string (fname
, strlen (fname
));
27377 /* Register for alloca automatic storage; this is always reg 31.
27378 Only emit this if the alloca bit was set above. */
27379 if (frame_pointer_needed
)
27380 fputs ("\t.byte 31\n", file
);
27382 fputs ("\t.align 2\n", file
);
27386 /* -fsplit-stack support. */
27388 /* A SYMBOL_REF for __morestack. */
27389 static GTY(()) rtx morestack_ref
;
27392 gen_add3_const (rtx rt
, rtx ra
, long c
)
27395 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
27397 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
27400 /* Emit -fsplit-stack prologue, which goes before the regular function
27401 prologue (at local entry point in the case of ELFv2). */
27404 rs6000_expand_split_stack_prologue (void)
27406 rs6000_stack_t
*info
= rs6000_stack_info ();
27407 unsigned HOST_WIDE_INT allocate
;
27408 long alloc_hi
, alloc_lo
;
27409 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
27412 gcc_assert (flag_split_stack
&& reload_completed
);
27417 if (global_regs
[29])
27419 error ("-fsplit-stack uses register r29");
27420 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
27421 "conflicts with %qD", global_regs_decl
[29]);
27424 allocate
= info
->total_size
;
27425 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
27427 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
27430 if (morestack_ref
== NULL_RTX
)
27432 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
27433 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
27434 | SYMBOL_FLAG_FUNCTION
);
27437 r0
= gen_rtx_REG (Pmode
, 0);
27438 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
27439 r12
= gen_rtx_REG (Pmode
, 12);
27440 emit_insn (gen_load_split_stack_limit (r0
));
27441 /* Always emit two insns here to calculate the requested stack,
27442 so that the linker can edit them when adjusting size for calling
27443 non-split-stack code. */
27444 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
27445 alloc_lo
= -allocate
- alloc_hi
;
27448 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
27450 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
27452 emit_insn (gen_nop ());
27456 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
27457 emit_insn (gen_nop ());
27460 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
27461 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
27462 ok_label
= gen_label_rtx ();
27463 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
27464 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
27465 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
27467 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
27468 JUMP_LABEL (jump
) = ok_label
;
27469 /* Mark the jump as very likely to be taken. */
27470 add_int_reg_note (jump
, REG_BR_PROB
,
27471 REG_BR_PROB_BASE
- REG_BR_PROB_BASE
/ 100);
27473 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27474 insn
= emit_move_insn (r0
, lr
);
27475 RTX_FRAME_RELATED_P (insn
) = 1;
27476 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
27477 RTX_FRAME_RELATED_P (insn
) = 1;
27479 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
27480 const0_rtx
, const0_rtx
));
27481 call_fusage
= NULL_RTX
;
27482 use_reg (&call_fusage
, r12
);
27483 add_function_usage_to (insn
, call_fusage
);
27484 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
27485 insn
= emit_move_insn (lr
, r0
);
27486 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27487 RTX_FRAME_RELATED_P (insn
) = 1;
27488 emit_insn (gen_split_stack_return ());
27490 emit_label (ok_label
);
27491 LABEL_NUSES (ok_label
) = 1;
27494 /* Return the internal arg pointer used for function incoming
27495 arguments. When -fsplit-stack, the arg pointer is r12 so we need
27496 to copy it to a pseudo in order for it to be preserved over calls
27497 and suchlike. We'd really like to use a pseudo here for the
27498 internal arg pointer but data-flow analysis is not prepared to
27499 accept pseudos as live at the beginning of a function. */
27502 rs6000_internal_arg_pointer (void)
27504 if (flag_split_stack
27505 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
27509 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
27513 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
27514 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
27516 /* Put the pseudo initialization right after the note at the
27517 beginning of the function. */
27518 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
27519 gen_rtx_REG (Pmode
, 12));
27520 push_topmost_sequence ();
27521 emit_insn_after (pat
, get_insns ());
27522 pop_topmost_sequence ();
27524 return plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
27525 FIRST_PARM_OFFSET (current_function_decl
));
27527 return virtual_incoming_args_rtx
;
27530 /* We may have to tell the dataflow pass that the split stack prologue
27531 is initializing a register. */
27534 rs6000_live_on_entry (bitmap regs
)
27536 if (flag_split_stack
)
27537 bitmap_set_bit (regs
, 12);
27540 /* Emit -fsplit-stack dynamic stack allocation space check. */
27543 rs6000_split_stack_space_check (rtx size
, rtx label
)
27545 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
27546 rtx limit
= gen_reg_rtx (Pmode
);
27547 rtx requested
= gen_reg_rtx (Pmode
);
27548 rtx cmp
= gen_reg_rtx (CCUNSmode
);
27551 emit_insn (gen_load_split_stack_limit (limit
));
27552 if (CONST_INT_P (size
))
27553 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
27556 size
= force_reg (Pmode
, size
);
27557 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
27559 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
27560 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
27561 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
27562 gen_rtx_LABEL_REF (VOIDmode
, label
),
27564 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
27565 JUMP_LABEL (jump
) = label
;
27568 /* A C compound statement that outputs the assembler code for a thunk
27569 function, used to implement C++ virtual function calls with
27570 multiple inheritance. The thunk acts as a wrapper around a virtual
27571 function, adjusting the implicit object parameter before handing
27572 control off to the real function.
27574 First, emit code to add the integer DELTA to the location that
27575 contains the incoming first argument. Assume that this argument
27576 contains a pointer, and is the one used to pass the `this' pointer
27577 in C++. This is the incoming argument *before* the function
27578 prologue, e.g. `%o0' on a sparc. The addition must preserve the
27579 values of all other incoming arguments.
27581 After the addition, emit code to jump to FUNCTION, which is a
27582 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
27583 not touch the return address. Hence returning from FUNCTION will
27584 return to whoever called the current `thunk'.
27586 The effect must be as if FUNCTION had been called directly with the
27587 adjusted first argument. This macro is responsible for emitting
27588 all of the code for a thunk function; output_function_prologue()
27589 and output_function_epilogue() are not invoked.
27591 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
27592 been extracted from it.) It might possibly be useful on some
27593 targets, but probably not.
27595 If you do not define this macro, the target-independent code in the
27596 C++ frontend will generate a less efficient heavyweight thunk that
27597 calls FUNCTION instead of jumping to it. The generic approach does
27598 not support varargs. */
27601 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
27602 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
27605 rtx this_rtx
, funexp
;
27608 reload_completed
= 1;
27609 epilogue_completed
= 1;
27611 /* Mark the end of the (empty) prologue. */
27612 emit_note (NOTE_INSN_PROLOGUE_END
);
27614 /* Find the "this" pointer. If the function returns a structure,
27615 the structure return pointer is in r3. */
27616 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
27617 this_rtx
= gen_rtx_REG (Pmode
, 4);
27619 this_rtx
= gen_rtx_REG (Pmode
, 3);
27621 /* Apply the constant offset, if required. */
27623 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
27625 /* Apply the offset from the vtable, if required. */
27628 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
27629 rtx tmp
= gen_rtx_REG (Pmode
, 12);
27631 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
27632 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
27634 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
27635 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
27639 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
27641 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
27643 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
27646 /* Generate a tail call to the target function. */
27647 if (!TREE_USED (function
))
27649 assemble_external (function
);
27650 TREE_USED (function
) = 1;
27652 funexp
= XEXP (DECL_RTL (function
), 0);
27653 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
27656 if (MACHOPIC_INDIRECT
)
27657 funexp
= machopic_indirect_call_target (funexp
);
27660 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
27661 generate sibcall RTL explicitly. */
27662 insn
= emit_call_insn (
27663 gen_rtx_PARALLEL (VOIDmode
,
27665 gen_rtx_CALL (VOIDmode
,
27666 funexp
, const0_rtx
),
27667 gen_rtx_USE (VOIDmode
, const0_rtx
),
27668 gen_rtx_USE (VOIDmode
,
27669 gen_rtx_REG (SImode
,
27671 simple_return_rtx
)));
27672 SIBLING_CALL_P (insn
) = 1;
27675 /* Run just enough of rest_of_compilation to get the insns emitted.
27676 There's not really enough bulk here to make other passes such as
27677 instruction scheduling worth while. Note that use_thunk calls
27678 assemble_start_function and assemble_end_function. */
27679 insn
= get_insns ();
27680 shorten_branches (insn
);
27681 final_start_function (insn
, file
, 1);
27682 final (insn
, file
, 1);
27683 final_end_function ();
27685 reload_completed
= 0;
27686 epilogue_completed
= 0;
27689 /* A quick summary of the various types of 'constant-pool tables'
27692 Target Flags Name One table per
27693 AIX (none) AIX TOC object file
27694 AIX -mfull-toc AIX TOC object file
27695 AIX -mminimal-toc AIX minimal TOC translation unit
27696 SVR4/EABI (none) SVR4 SDATA object file
27697 SVR4/EABI -fpic SVR4 pic object file
27698 SVR4/EABI -fPIC SVR4 PIC translation unit
27699 SVR4/EABI -mrelocatable EABI TOC function
27700 SVR4/EABI -maix AIX TOC object file
27701 SVR4/EABI -maix -mminimal-toc
27702 AIX minimal TOC translation unit
27704 Name Reg. Set by entries contains:
27705 made by addrs? fp? sum?
27707 AIX TOC 2 crt0 as Y option option
27708 AIX minimal TOC 30 prolog gcc Y Y option
27709 SVR4 SDATA 13 crt0 gcc N Y N
27710 SVR4 pic 30 prolog ld Y not yet N
27711 SVR4 PIC 30 prolog gcc Y option option
27712 EABI TOC 30 prolog gcc Y option option
27716 /* Hash functions for the hash table. */
27719 rs6000_hash_constant (rtx k
)
27721 enum rtx_code code
= GET_CODE (k
);
27722 machine_mode mode
= GET_MODE (k
);
27723 unsigned result
= (code
<< 3) ^ mode
;
27724 const char *format
;
27727 format
= GET_RTX_FORMAT (code
);
27728 flen
= strlen (format
);
27734 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
27736 case CONST_WIDE_INT
:
27739 flen
= CONST_WIDE_INT_NUNITS (k
);
27740 for (i
= 0; i
< flen
; i
++)
27741 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
27746 if (mode
!= VOIDmode
)
27747 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
27759 for (; fidx
< flen
; fidx
++)
27760 switch (format
[fidx
])
27765 const char *str
= XSTR (k
, fidx
);
27766 len
= strlen (str
);
27767 result
= result
* 613 + len
;
27768 for (i
= 0; i
< len
; i
++)
27769 result
= result
* 613 + (unsigned) str
[i
];
27774 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
27778 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
27781 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
27782 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
27786 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
27787 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
27794 gcc_unreachable ();
27801 toc_hasher::hash (toc_hash_struct
*thc
)
27803 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
27806 /* Compare H1 and H2 for equivalence. */
27809 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
27814 if (h1
->key_mode
!= h2
->key_mode
)
27817 return rtx_equal_p (r1
, r2
);
27820 /* These are the names given by the C++ front-end to vtables, and
27821 vtable-like objects. Ideally, this logic should not be here;
27822 instead, there should be some programmatic way of inquiring as
27823 to whether or not an object is a vtable. */
27825 #define VTABLE_NAME_P(NAME) \
27826 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
27827 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
27828 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
27829 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
27830 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
27832 #ifdef NO_DOLLAR_IN_LABEL
27833 /* Return a GGC-allocated character string translating dollar signs in
27834 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
27837 rs6000_xcoff_strip_dollar (const char *name
)
27843 q
= (const char *) strchr (name
, '$');
27845 if (q
== 0 || q
== name
)
27848 len
= strlen (name
);
27849 strip
= XALLOCAVEC (char, len
+ 1);
27850 strcpy (strip
, name
);
27851 p
= strip
+ (q
- name
);
27855 p
= strchr (p
+ 1, '$');
27858 return ggc_alloc_string (strip
, len
);
27863 rs6000_output_symbol_ref (FILE *file
, rtx x
)
27865 /* Currently C++ toc references to vtables can be emitted before it
27866 is decided whether the vtable is public or private. If this is
27867 the case, then the linker will eventually complain that there is
27868 a reference to an unknown section. Thus, for vtables only,
27869 we emit the TOC reference to reference the symbol and not the
27871 const char *name
= XSTR (x
, 0);
27873 tree decl
= SYMBOL_REF_DECL (x
);
27874 if (decl
/* sync condition with assemble_external () */
27875 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
27876 && (TREE_CODE (decl
) == VAR_DECL
27877 || TREE_CODE (decl
) == FUNCTION_DECL
)
27878 && name
[strlen (name
) - 1] != ']')
27880 name
= concat (name
,
27881 (TREE_CODE (decl
) == FUNCTION_DECL
27882 ? "[DS]" : "[UA]"),
27884 XSTR (x
, 0) = name
;
27887 if (VTABLE_NAME_P (name
))
27889 RS6000_OUTPUT_BASENAME (file
, name
);
27892 assemble_name (file
, name
);
27895 /* Output a TOC entry. We derive the entry name from what is being
27899 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
27902 const char *name
= buf
;
27904 HOST_WIDE_INT offset
= 0;
27906 gcc_assert (!TARGET_NO_TOC
);
27908 /* When the linker won't eliminate them, don't output duplicate
27909 TOC entries (this happens on AIX if there is any kind of TOC,
27910 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
27912 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
27914 struct toc_hash_struct
*h
;
27916 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
27917 time because GGC is not initialized at that point. */
27918 if (toc_hash_table
== NULL
)
27919 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
27921 h
= ggc_alloc
<toc_hash_struct
> ();
27923 h
->key_mode
= mode
;
27924 h
->labelno
= labelno
;
27926 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
27927 if (*found
== NULL
)
27929 else /* This is indeed a duplicate.
27930 Set this label equal to that label. */
27932 fputs ("\t.set ", file
);
27933 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
27934 fprintf (file
, "%d,", labelno
);
27935 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
27936 fprintf (file
, "%d\n", ((*found
)->labelno
));
27939 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
27940 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
27941 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
27943 fputs ("\t.set ", file
);
27944 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
27945 fprintf (file
, "%d,", labelno
);
27946 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
27947 fprintf (file
, "%d\n", ((*found
)->labelno
));
27954 /* If we're going to put a double constant in the TOC, make sure it's
27955 aligned properly when strict alignment is on. */
27956 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
27957 && STRICT_ALIGNMENT
27958 && GET_MODE_BITSIZE (mode
) >= 64
27959 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
27960 ASM_OUTPUT_ALIGN (file
, 3);
27963 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
27965 /* Handle FP constants specially. Note that if we have a minimal
27966 TOC, things we put here aren't actually in the TOC, so we can allow
27968 if (GET_CODE (x
) == CONST_DOUBLE
&&
27969 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
27970 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
27974 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
27975 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
27977 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
27981 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27982 fputs (DOUBLE_INT_ASM_OP
, file
);
27984 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
27985 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
27986 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
27987 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
27988 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
27989 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
27990 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
27991 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
27996 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27997 fputs ("\t.long ", file
);
27999 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
28000 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
28001 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
28002 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
28003 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
28004 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
28008 else if (GET_CODE (x
) == CONST_DOUBLE
&&
28009 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
28013 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
28014 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
28016 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
28020 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28021 fputs (DOUBLE_INT_ASM_OP
, file
);
28023 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
28024 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
28025 fprintf (file
, "0x%lx%08lx\n",
28026 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
28027 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
28032 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28033 fputs ("\t.long ", file
);
28035 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
28036 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
28037 fprintf (file
, "0x%lx,0x%lx\n",
28038 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
28042 else if (GET_CODE (x
) == CONST_DOUBLE
&&
28043 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
28047 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
28048 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x
), l
);
28050 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
28054 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28055 fputs (DOUBLE_INT_ASM_OP
, file
);
28057 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
28058 if (WORDS_BIG_ENDIAN
)
28059 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
28061 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
28066 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28067 fputs ("\t.long ", file
);
28069 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
28070 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
28074 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
28076 unsigned HOST_WIDE_INT low
;
28077 HOST_WIDE_INT high
;
28079 low
= INTVAL (x
) & 0xffffffff;
28080 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
28082 /* TOC entries are always Pmode-sized, so when big-endian
28083 smaller integer constants in the TOC need to be padded.
28084 (This is still a win over putting the constants in
28085 a separate constant pool, because then we'd have
28086 to have both a TOC entry _and_ the actual constant.)
28088 For a 32-bit target, CONST_INT values are loaded and shifted
28089 entirely within `low' and can be stored in one TOC entry. */
28091 /* It would be easy to make this work, but it doesn't now. */
28092 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
28094 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
28097 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
28098 high
= (HOST_WIDE_INT
) low
>> 32;
28104 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28105 fputs (DOUBLE_INT_ASM_OP
, file
);
28107 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
28108 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
28109 fprintf (file
, "0x%lx%08lx\n",
28110 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
28115 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
28117 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28118 fputs ("\t.long ", file
);
28120 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
28121 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
28122 fprintf (file
, "0x%lx,0x%lx\n",
28123 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
28127 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28128 fputs ("\t.long ", file
);
28130 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
28131 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
28137 if (GET_CODE (x
) == CONST
)
28139 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
28140 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
28142 base
= XEXP (XEXP (x
, 0), 0);
28143 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
28146 switch (GET_CODE (base
))
28149 name
= XSTR (base
, 0);
28153 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
28154 CODE_LABEL_NUMBER (XEXP (base
, 0)));
28158 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
28162 gcc_unreachable ();
28165 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
28166 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
28169 fputs ("\t.tc ", file
);
28170 RS6000_OUTPUT_BASENAME (file
, name
);
28173 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
28175 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
28177 /* Mark large TOC symbols on AIX with [TE] so they are mapped
28178 after other TOC symbols, reducing overflow of small TOC access
28179 to [TC] symbols. */
28180 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
28181 ? "[TE]," : "[TC],", file
);
28184 /* Currently C++ toc references to vtables can be emitted before it
28185 is decided whether the vtable is public or private. If this is
28186 the case, then the linker will eventually complain that there is
28187 a TOC reference to an unknown section. Thus, for vtables only,
28188 we emit the TOC reference to reference the symbol and not the
28190 if (VTABLE_NAME_P (name
))
28192 RS6000_OUTPUT_BASENAME (file
, name
);
28194 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
28195 else if (offset
> 0)
28196 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
28199 output_addr_const (file
, x
);
28202 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
)
28204 switch (SYMBOL_REF_TLS_MODEL (base
))
28208 case TLS_MODEL_LOCAL_EXEC
:
28209 fputs ("@le", file
);
28211 case TLS_MODEL_INITIAL_EXEC
:
28212 fputs ("@ie", file
);
28214 /* Use global-dynamic for local-dynamic. */
28215 case TLS_MODEL_GLOBAL_DYNAMIC
:
28216 case TLS_MODEL_LOCAL_DYNAMIC
:
28218 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
28219 fputs ("\t.tc .", file
);
28220 RS6000_OUTPUT_BASENAME (file
, name
);
28221 fputs ("[TC],", file
);
28222 output_addr_const (file
, x
);
28223 fputs ("@m", file
);
28226 gcc_unreachable ();
28234 /* Output an assembler pseudo-op to write an ASCII string of N characters
28235 starting at P to FILE.
28237 On the RS/6000, we have to do this using the .byte operation and
28238 write out special characters outside the quoted string.
28239 Also, the assembler is broken; very long strings are truncated,
28240 so we must artificially break them up early. */
28243 output_ascii (FILE *file
, const char *p
, int n
)
28246 int i
, count_string
;
28247 const char *for_string
= "\t.byte \"";
28248 const char *for_decimal
= "\t.byte ";
28249 const char *to_close
= NULL
;
28252 for (i
= 0; i
< n
; i
++)
28255 if (c
>= ' ' && c
< 0177)
28258 fputs (for_string
, file
);
28261 /* Write two quotes to get one. */
28269 for_decimal
= "\"\n\t.byte ";
28273 if (count_string
>= 512)
28275 fputs (to_close
, file
);
28277 for_string
= "\t.byte \"";
28278 for_decimal
= "\t.byte ";
28286 fputs (for_decimal
, file
);
28287 fprintf (file
, "%d", c
);
28289 for_string
= "\n\t.byte \"";
28290 for_decimal
= ", ";
28296 /* Now close the string if we have written one. Then end the line. */
28298 fputs (to_close
, file
);
28301 /* Generate a unique section name for FILENAME for a section type
28302 represented by SECTION_DESC. Output goes into BUF.
28304 SECTION_DESC can be any string, as long as it is different for each
28305 possible section type.
28307 We name the section in the same manner as xlc. The name begins with an
28308 underscore followed by the filename (after stripping any leading directory
28309 names) with the last period replaced by the string SECTION_DESC. If
28310 FILENAME does not contain a period, SECTION_DESC is appended to the end of
28314 rs6000_gen_section_name (char **buf
, const char *filename
,
28315 const char *section_desc
)
28317 const char *q
, *after_last_slash
, *last_period
= 0;
28321 after_last_slash
= filename
;
28322 for (q
= filename
; *q
; q
++)
28325 after_last_slash
= q
+ 1;
28326 else if (*q
== '.')
28330 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
28331 *buf
= (char *) xmalloc (len
);
28336 for (q
= after_last_slash
; *q
; q
++)
28338 if (q
== last_period
)
28340 strcpy (p
, section_desc
);
28341 p
+= strlen (section_desc
);
28345 else if (ISALNUM (*q
))
28349 if (last_period
== 0)
28350 strcpy (p
, section_desc
);
28355 /* Emit profile function. */
28358 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
28360 /* Non-standard profiling for kernels, which just saves LR then calls
28361 _mcount without worrying about arg saves. The idea is to change
28362 the function prologue as little as possible as it isn't easy to
28363 account for arg save/restore code added just for _mcount. */
28364 if (TARGET_PROFILE_KERNEL
)
28367 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28369 #ifndef NO_PROFILE_COUNTERS
28370 # define NO_PROFILE_COUNTERS 0
28372 if (NO_PROFILE_COUNTERS
)
28373 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
28374 LCT_NORMAL
, VOIDmode
, 0);
28378 const char *label_name
;
28381 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
28382 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
28383 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
28385 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
28386 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
28389 else if (DEFAULT_ABI
== ABI_DARWIN
)
28391 const char *mcount_name
= RS6000_MCOUNT
;
28392 int caller_addr_regno
= LR_REGNO
;
28394 /* Be conservative and always set this, at least for now. */
28395 crtl
->uses_pic_offset_table
= 1;
28398 /* For PIC code, set up a stub and collect the caller's address
28399 from r0, which is where the prologue puts it. */
28400 if (MACHOPIC_INDIRECT
28401 && crtl
->uses_pic_offset_table
)
28402 caller_addr_regno
= 0;
28404 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
28405 LCT_NORMAL
, VOIDmode
, 1,
28406 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
28410 /* Write function profiler code. */
28413 output_function_profiler (FILE *file
, int labelno
)
28417 switch (DEFAULT_ABI
)
28420 gcc_unreachable ();
28425 warning (0, "no profiling of 64-bit code for this ABI");
28428 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
28429 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
28430 if (NO_PROFILE_COUNTERS
)
28432 asm_fprintf (file
, "\tstw %s,4(%s)\n",
28433 reg_names
[0], reg_names
[1]);
28435 else if (TARGET_SECURE_PLT
&& flag_pic
)
28437 if (TARGET_LINK_STACK
)
28440 get_ppc476_thunk_name (name
);
28441 asm_fprintf (file
, "\tbl %s\n", name
);
28444 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
28445 asm_fprintf (file
, "\tstw %s,4(%s)\n",
28446 reg_names
[0], reg_names
[1]);
28447 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
28448 asm_fprintf (file
, "\taddis %s,%s,",
28449 reg_names
[12], reg_names
[12]);
28450 assemble_name (file
, buf
);
28451 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
28452 assemble_name (file
, buf
);
28453 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
28455 else if (flag_pic
== 1)
28457 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
28458 asm_fprintf (file
, "\tstw %s,4(%s)\n",
28459 reg_names
[0], reg_names
[1]);
28460 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
28461 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
28462 assemble_name (file
, buf
);
28463 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
28465 else if (flag_pic
> 1)
28467 asm_fprintf (file
, "\tstw %s,4(%s)\n",
28468 reg_names
[0], reg_names
[1]);
28469 /* Now, we need to get the address of the label. */
28470 if (TARGET_LINK_STACK
)
28473 get_ppc476_thunk_name (name
);
28474 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
28475 assemble_name (file
, buf
);
28476 fputs ("-.\n1:", file
);
28477 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
28478 asm_fprintf (file
, "\taddi %s,%s,4\n",
28479 reg_names
[11], reg_names
[11]);
28483 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
28484 assemble_name (file
, buf
);
28485 fputs ("-.\n1:", file
);
28486 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
28488 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
28489 reg_names
[0], reg_names
[11]);
28490 asm_fprintf (file
, "\tadd %s,%s,%s\n",
28491 reg_names
[0], reg_names
[0], reg_names
[11]);
28495 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
28496 assemble_name (file
, buf
);
28497 fputs ("@ha\n", file
);
28498 asm_fprintf (file
, "\tstw %s,4(%s)\n",
28499 reg_names
[0], reg_names
[1]);
28500 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
28501 assemble_name (file
, buf
);
28502 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
28505 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
28506 fprintf (file
, "\tbl %s%s\n",
28507 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
28513 /* Don't do anything, done in output_profile_hook (). */
28520 /* The following variable value is the last issued insn. */
28522 static rtx last_scheduled_insn
;
28524 /* The following variable helps to balance issuing of load and
28525 store instructions */
28527 static int load_store_pendulum
;
28529 /* Power4 load update and store update instructions are cracked into a
28530 load or store and an integer insn which are executed in the same cycle.
28531 Branches have their own dispatch slot which does not count against the
28532 GCC issue rate, but it changes the program flow so there are no other
28533 instructions to issue in this cycle. */
28536 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
28538 last_scheduled_insn
= insn
;
28539 if (GET_CODE (PATTERN (insn
)) == USE
28540 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28542 cached_can_issue_more
= more
;
28543 return cached_can_issue_more
;
28546 if (insn_terminates_group_p (insn
, current_group
))
28548 cached_can_issue_more
= 0;
28549 return cached_can_issue_more
;
28552 /* If no reservation, but reach here */
28553 if (recog_memoized (insn
) < 0)
28556 if (rs6000_sched_groups
)
28558 if (is_microcoded_insn (insn
))
28559 cached_can_issue_more
= 0;
28560 else if (is_cracked_insn (insn
))
28561 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
28563 cached_can_issue_more
= more
- 1;
28565 return cached_can_issue_more
;
28568 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
28571 cached_can_issue_more
= more
- 1;
28572 return cached_can_issue_more
;
28576 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
28578 int r
= rs6000_variable_issue_1 (insn
, more
);
28580 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
28584 /* Adjust the cost of a scheduling dependency. Return the new cost of
28585 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
28588 rs6000_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
28590 enum attr_type attr_type
;
28592 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
28595 switch (REG_NOTE_KIND (link
))
28599 /* Data dependency; DEP_INSN writes a register that INSN reads
28600 some cycles later. */
28602 /* Separate a load from a narrower, dependent store. */
28603 if (rs6000_sched_groups
28604 && GET_CODE (PATTERN (insn
)) == SET
28605 && GET_CODE (PATTERN (dep_insn
)) == SET
28606 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
28607 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
28608 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
28609 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
28612 attr_type
= get_attr_type (insn
);
28617 /* Tell the first scheduling pass about the latency between
28618 a mtctr and bctr (and mtlr and br/blr). The first
28619 scheduling pass will not know about this latency since
28620 the mtctr instruction, which has the latency associated
28621 to it, will be generated by reload. */
28624 /* Leave some extra cycles between a compare and its
28625 dependent branch, to inhibit expensive mispredicts. */
28626 if ((rs6000_cpu_attr
== CPU_PPC603
28627 || rs6000_cpu_attr
== CPU_PPC604
28628 || rs6000_cpu_attr
== CPU_PPC604E
28629 || rs6000_cpu_attr
== CPU_PPC620
28630 || rs6000_cpu_attr
== CPU_PPC630
28631 || rs6000_cpu_attr
== CPU_PPC750
28632 || rs6000_cpu_attr
== CPU_PPC7400
28633 || rs6000_cpu_attr
== CPU_PPC7450
28634 || rs6000_cpu_attr
== CPU_PPCE5500
28635 || rs6000_cpu_attr
== CPU_PPCE6500
28636 || rs6000_cpu_attr
== CPU_POWER4
28637 || rs6000_cpu_attr
== CPU_POWER5
28638 || rs6000_cpu_attr
== CPU_POWER7
28639 || rs6000_cpu_attr
== CPU_POWER8
28640 || rs6000_cpu_attr
== CPU_POWER9
28641 || rs6000_cpu_attr
== CPU_CELL
)
28642 && recog_memoized (dep_insn
)
28643 && (INSN_CODE (dep_insn
) >= 0))
28645 switch (get_attr_type (dep_insn
))
28648 case TYPE_FPCOMPARE
:
28649 case TYPE_CR_LOGICAL
:
28650 case TYPE_DELAYED_CR
:
28654 if (get_attr_dot (dep_insn
) == DOT_YES
)
28659 if (get_attr_dot (dep_insn
) == DOT_YES
28660 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
28671 if ((rs6000_cpu
== PROCESSOR_POWER6
)
28672 && recog_memoized (dep_insn
)
28673 && (INSN_CODE (dep_insn
) >= 0))
28676 if (GET_CODE (PATTERN (insn
)) != SET
)
28677 /* If this happens, we have to extend this to schedule
28678 optimally. Return default for now. */
28681 /* Adjust the cost for the case where the value written
28682 by a fixed point operation is used as the address
28683 gen value on a store. */
28684 switch (get_attr_type (dep_insn
))
28689 if (! store_data_bypass_p (dep_insn
, insn
))
28690 return get_attr_sign_extend (dep_insn
)
28691 == SIGN_EXTEND_YES
? 6 : 4;
28696 if (! store_data_bypass_p (dep_insn
, insn
))
28697 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
28707 if (! store_data_bypass_p (dep_insn
, insn
))
28715 if (get_attr_update (dep_insn
) == UPDATE_YES
28716 && ! store_data_bypass_p (dep_insn
, insn
))
28722 if (! store_data_bypass_p (dep_insn
, insn
))
28728 if (! store_data_bypass_p (dep_insn
, insn
))
28729 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
28739 if ((rs6000_cpu
== PROCESSOR_POWER6
)
28740 && recog_memoized (dep_insn
)
28741 && (INSN_CODE (dep_insn
) >= 0))
28744 /* Adjust the cost for the case where the value written
28745 by a fixed point instruction is used within the address
28746 gen portion of a subsequent load(u)(x) */
28747 switch (get_attr_type (dep_insn
))
28752 if (set_to_load_agen (dep_insn
, insn
))
28753 return get_attr_sign_extend (dep_insn
)
28754 == SIGN_EXTEND_YES
? 6 : 4;
28759 if (set_to_load_agen (dep_insn
, insn
))
28760 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
28770 if (set_to_load_agen (dep_insn
, insn
))
28778 if (get_attr_update (dep_insn
) == UPDATE_YES
28779 && set_to_load_agen (dep_insn
, insn
))
28785 if (set_to_load_agen (dep_insn
, insn
))
28791 if (set_to_load_agen (dep_insn
, insn
))
28792 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
28802 if ((rs6000_cpu
== PROCESSOR_POWER6
)
28803 && get_attr_update (insn
) == UPDATE_NO
28804 && recog_memoized (dep_insn
)
28805 && (INSN_CODE (dep_insn
) >= 0)
28806 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
28813 /* Fall out to return default cost. */
28817 case REG_DEP_OUTPUT
:
28818 /* Output dependency; DEP_INSN writes a register that INSN writes some
28820 if ((rs6000_cpu
== PROCESSOR_POWER6
)
28821 && recog_memoized (dep_insn
)
28822 && (INSN_CODE (dep_insn
) >= 0))
28824 attr_type
= get_attr_type (insn
);
28829 if (get_attr_type (dep_insn
) == TYPE_FP
)
28833 if (get_attr_update (insn
) == UPDATE_NO
28834 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
28842 /* Anti dependency; DEP_INSN reads a register that INSN writes some
28847 gcc_unreachable ();
28853 /* Debug version of rs6000_adjust_cost. */
28856 rs6000_debug_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
,
28859 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
28865 switch (REG_NOTE_KIND (link
))
28867 default: dep
= "unknown depencency"; break;
28868 case REG_DEP_TRUE
: dep
= "data dependency"; break;
28869 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
28870 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
28874 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
28875 "%s, insn:\n", ret
, cost
, dep
);
28883 /* The function returns a true if INSN is microcoded.
28884 Return false otherwise. */
28887 is_microcoded_insn (rtx_insn
*insn
)
28889 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28890 || GET_CODE (PATTERN (insn
)) == USE
28891 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28894 if (rs6000_cpu_attr
== CPU_CELL
)
28895 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
28897 if (rs6000_sched_groups
28898 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
28900 enum attr_type type
= get_attr_type (insn
);
28901 if ((type
== TYPE_LOAD
28902 && get_attr_update (insn
) == UPDATE_YES
28903 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
28904 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
28905 && get_attr_update (insn
) == UPDATE_YES
28906 && get_attr_indexed (insn
) == INDEXED_YES
)
28907 || type
== TYPE_MFCR
)
28914 /* The function returns true if INSN is cracked into 2 instructions
28915 by the processor (and therefore occupies 2 issue slots). */
28918 is_cracked_insn (rtx_insn
*insn
)
28920 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28921 || GET_CODE (PATTERN (insn
)) == USE
28922 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28925 if (rs6000_sched_groups
28926 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
28928 enum attr_type type
= get_attr_type (insn
);
28929 if ((type
== TYPE_LOAD
28930 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28931 && get_attr_update (insn
) == UPDATE_NO
)
28932 || (type
== TYPE_LOAD
28933 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
28934 && get_attr_update (insn
) == UPDATE_YES
28935 && get_attr_indexed (insn
) == INDEXED_NO
)
28936 || (type
== TYPE_STORE
28937 && get_attr_update (insn
) == UPDATE_YES
28938 && get_attr_indexed (insn
) == INDEXED_NO
)
28939 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
28940 && get_attr_update (insn
) == UPDATE_YES
)
28941 || type
== TYPE_DELAYED_CR
28942 || (type
== TYPE_EXTS
28943 && get_attr_dot (insn
) == DOT_YES
)
28944 || (type
== TYPE_SHIFT
28945 && get_attr_dot (insn
) == DOT_YES
28946 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
28947 || (type
== TYPE_MUL
28948 && get_attr_dot (insn
) == DOT_YES
)
28949 || type
== TYPE_DIV
28950 || (type
== TYPE_INSERT
28951 && get_attr_size (insn
) == SIZE_32
))
28958 /* The function returns true if INSN can be issued only from
28959 the branch slot. */
28962 is_branch_slot_insn (rtx_insn
*insn
)
28964 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28965 || GET_CODE (PATTERN (insn
)) == USE
28966 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28969 if (rs6000_sched_groups
)
28971 enum attr_type type
= get_attr_type (insn
);
28972 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
28980 /* The function returns true if out_inst sets a value that is
28981 used in the address generation computation of in_insn */
28983 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
28985 rtx out_set
, in_set
;
28987 /* For performance reasons, only handle the simple case where
28988 both loads are a single_set. */
28989 out_set
= single_set (out_insn
);
28992 in_set
= single_set (in_insn
);
28994 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
29000 /* Try to determine base/offset/size parts of the given MEM.
29001 Return true if successful, false if all the values couldn't
29004 This function only looks for REG or REG+CONST address forms.
29005 REG+REG address form will return false. */
29008 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
29009 HOST_WIDE_INT
*size
)
29012 if MEM_SIZE_KNOWN_P (mem
)
29013 *size
= MEM_SIZE (mem
);
29017 addr_rtx
= (XEXP (mem
, 0));
29018 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
29019 addr_rtx
= XEXP (addr_rtx
, 1);
29022 while (GET_CODE (addr_rtx
) == PLUS
29023 && CONST_INT_P (XEXP (addr_rtx
, 1)))
29025 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
29026 addr_rtx
= XEXP (addr_rtx
, 0);
29028 if (!REG_P (addr_rtx
))
29035 /* The function returns true if the target storage location of
29036 mem1 is adjacent to the target storage location of mem2 */
29037 /* Return 1 if memory locations are adjacent. */
29040 adjacent_mem_locations (rtx mem1
, rtx mem2
)
29043 HOST_WIDE_INT off1
, size1
, off2
, size2
;
29045 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
29046 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
29047 return ((REGNO (reg1
) == REGNO (reg2
))
29048 && ((off1
+ size1
== off2
)
29049 || (off2
+ size2
== off1
)));
29054 /* This function returns true if it can be determined that the two MEM
29055 locations overlap by at least 1 byte based on base reg/offset/size. */
29058 mem_locations_overlap (rtx mem1
, rtx mem2
)
29061 HOST_WIDE_INT off1
, size1
, off2
, size2
;
29063 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
29064 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
29065 return ((REGNO (reg1
) == REGNO (reg2
))
29066 && (((off1
<= off2
) && (off1
+ size1
> off2
))
29067 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
29072 /* A C statement (sans semicolon) to update the integer scheduling
29073 priority INSN_PRIORITY (INSN). Increase the priority to execute the
29074 INSN earlier, reduce the priority to execute INSN later. Do not
29075 define this macro if you do not need to adjust the scheduling
29076 priorities of insns. */
29079 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
29081 rtx load_mem
, str_mem
;
29082 /* On machines (like the 750) which have asymmetric integer units,
29083 where one integer unit can do multiply and divides and the other
29084 can't, reduce the priority of multiply/divide so it is scheduled
29085 before other integer operations. */
29088 if (! INSN_P (insn
))
29091 if (GET_CODE (PATTERN (insn
)) == USE
)
29094 switch (rs6000_cpu_attr
) {
29096 switch (get_attr_type (insn
))
29103 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
29104 priority
, priority
);
29105 if (priority
>= 0 && priority
< 0x01000000)
29112 if (insn_must_be_first_in_group (insn
)
29113 && reload_completed
29114 && current_sched_info
->sched_max_insns_priority
29115 && rs6000_sched_restricted_insns_priority
)
29118 /* Prioritize insns that can be dispatched only in the first
29120 if (rs6000_sched_restricted_insns_priority
== 1)
29121 /* Attach highest priority to insn. This means that in
29122 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
29123 precede 'priority' (critical path) considerations. */
29124 return current_sched_info
->sched_max_insns_priority
;
29125 else if (rs6000_sched_restricted_insns_priority
== 2)
29126 /* Increase priority of insn by a minimal amount. This means that in
29127 haifa-sched.c:ready_sort(), only 'priority' (critical path)
29128 considerations precede dispatch-slot restriction considerations. */
29129 return (priority
+ 1);
29132 if (rs6000_cpu
== PROCESSOR_POWER6
29133 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
29134 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
29135 /* Attach highest priority to insn if the scheduler has just issued two
29136 stores and this instruction is a load, or two loads and this instruction
29137 is a store. Power6 wants loads and stores scheduled alternately
29139 return current_sched_info
->sched_max_insns_priority
;
29144 /* Return true if the instruction is nonpipelined on the Cell. */
29146 is_nonpipeline_insn (rtx_insn
*insn
)
29148 enum attr_type type
;
29149 if (!insn
|| !NONDEBUG_INSN_P (insn
)
29150 || GET_CODE (PATTERN (insn
)) == USE
29151 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
29154 type
= get_attr_type (insn
);
29155 if (type
== TYPE_MUL
29156 || type
== TYPE_DIV
29157 || type
== TYPE_SDIV
29158 || type
== TYPE_DDIV
29159 || type
== TYPE_SSQRT
29160 || type
== TYPE_DSQRT
29161 || type
== TYPE_MFCR
29162 || type
== TYPE_MFCRF
29163 || type
== TYPE_MFJMPR
)
29171 /* Return how many instructions the machine can issue per cycle. */
29174 rs6000_issue_rate (void)
29176 /* Unless scheduling for register pressure, use issue rate of 1 for
29177 first scheduling pass to decrease degradation. */
29178 if (!reload_completed
&& !flag_sched_pressure
)
29181 switch (rs6000_cpu_attr
) {
29183 case CPU_PPC601
: /* ? */
29193 case CPU_PPCE300C2
:
29194 case CPU_PPCE300C3
:
29195 case CPU_PPCE500MC
:
29196 case CPU_PPCE500MC64
:
29220 /* Return how many instructions to look ahead for better insn
29224 rs6000_use_sched_lookahead (void)
29226 switch (rs6000_cpu_attr
)
29233 return (reload_completed
? 8 : 0);
29240 /* We are choosing insn from the ready queue. Return zero if INSN can be
29243 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
29245 if (ready_index
== 0)
29248 if (rs6000_cpu_attr
!= CPU_CELL
)
29251 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
29253 if (!reload_completed
29254 || is_nonpipeline_insn (insn
)
29255 || is_microcoded_insn (insn
))
29261 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
29262 and return true. */
29265 find_mem_ref (rtx pat
, rtx
*mem_ref
)
29270 /* stack_tie does not produce any real memory traffic. */
29271 if (tie_operand (pat
, VOIDmode
))
29274 if (GET_CODE (pat
) == MEM
)
29280 /* Recursively process the pattern. */
29281 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
29283 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
29287 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
29290 else if (fmt
[i
] == 'E')
29291 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
29293 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
29301 /* Determine if PAT is a PATTERN of a load insn. */
29304 is_load_insn1 (rtx pat
, rtx
*load_mem
)
29306 if (!pat
|| pat
== NULL_RTX
)
29309 if (GET_CODE (pat
) == SET
)
29310 return find_mem_ref (SET_SRC (pat
), load_mem
);
29312 if (GET_CODE (pat
) == PARALLEL
)
29316 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
29317 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
29324 /* Determine if INSN loads from memory. */
29327 is_load_insn (rtx insn
, rtx
*load_mem
)
29329 if (!insn
|| !INSN_P (insn
))
29335 return is_load_insn1 (PATTERN (insn
), load_mem
);
29338 /* Determine if PAT is a PATTERN of a store insn. */
29341 is_store_insn1 (rtx pat
, rtx
*str_mem
)
29343 if (!pat
|| pat
== NULL_RTX
)
29346 if (GET_CODE (pat
) == SET
)
29347 return find_mem_ref (SET_DEST (pat
), str_mem
);
29349 if (GET_CODE (pat
) == PARALLEL
)
29353 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
29354 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
29361 /* Determine if INSN stores to memory. */
29364 is_store_insn (rtx insn
, rtx
*str_mem
)
29366 if (!insn
|| !INSN_P (insn
))
29369 return is_store_insn1 (PATTERN (insn
), str_mem
);
29372 /* Returns whether the dependence between INSN and NEXT is considered
29373 costly by the given target. */
29376 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
29380 rtx load_mem
, str_mem
;
29382 /* If the flag is not enabled - no dependence is considered costly;
29383 allow all dependent insns in the same group.
29384 This is the most aggressive option. */
29385 if (rs6000_sched_costly_dep
== no_dep_costly
)
29388 /* If the flag is set to 1 - a dependence is always considered costly;
29389 do not allow dependent instructions in the same group.
29390 This is the most conservative option. */
29391 if (rs6000_sched_costly_dep
== all_deps_costly
)
29394 insn
= DEP_PRO (dep
);
29395 next
= DEP_CON (dep
);
29397 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
29398 && is_load_insn (next
, &load_mem
)
29399 && is_store_insn (insn
, &str_mem
))
29400 /* Prevent load after store in the same group. */
29403 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
29404 && is_load_insn (next
, &load_mem
)
29405 && is_store_insn (insn
, &str_mem
)
29406 && DEP_TYPE (dep
) == REG_DEP_TRUE
29407 && mem_locations_overlap(str_mem
, load_mem
))
29408 /* Prevent load after store in the same group if it is a true
29412 /* The flag is set to X; dependences with latency >= X are considered costly,
29413 and will not be scheduled in the same group. */
29414 if (rs6000_sched_costly_dep
<= max_dep_latency
29415 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
29421 /* Return the next insn after INSN that is found before TAIL is reached,
29422 skipping any "non-active" insns - insns that will not actually occupy
29423 an issue slot. Return NULL_RTX if such an insn is not found. */
29426 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
29428 if (insn
== NULL_RTX
|| insn
== tail
)
29433 insn
= NEXT_INSN (insn
);
29434 if (insn
== NULL_RTX
|| insn
== tail
)
29438 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
29439 || (NONJUMP_INSN_P (insn
)
29440 && GET_CODE (PATTERN (insn
)) != USE
29441 && GET_CODE (PATTERN (insn
)) != CLOBBER
29442 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
29448 /* We are about to begin issuing insns for this clock cycle. */
29451 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
29452 rtx_insn
**ready ATTRIBUTE_UNUSED
,
29453 int *pn_ready ATTRIBUTE_UNUSED
,
29454 int clock_var ATTRIBUTE_UNUSED
)
29456 int n_ready
= *pn_ready
;
29459 fprintf (dump
, "// rs6000_sched_reorder :\n");
29461 /* Reorder the ready list, if the second to last ready insn
29462 is a nonepipeline insn. */
29463 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
29465 if (is_nonpipeline_insn (ready
[n_ready
- 1])
29466 && (recog_memoized (ready
[n_ready
- 2]) > 0))
29467 /* Simply swap first two insns. */
29468 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
29471 if (rs6000_cpu
== PROCESSOR_POWER6
)
29472 load_store_pendulum
= 0;
29474 return rs6000_issue_rate ();
29477 /* Like rs6000_sched_reorder, but called after issuing each insn. */
29480 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
29481 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
29484 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
29486 /* For Power6, we need to handle some special cases to try and keep the
29487 store queue from overflowing and triggering expensive flushes.
29489 This code monitors how load and store instructions are being issued
29490 and skews the ready list one way or the other to increase the likelihood
29491 that a desired instruction is issued at the proper time.
29493 A couple of things are done. First, we maintain a "load_store_pendulum"
29494 to track the current state of load/store issue.
29496 - If the pendulum is at zero, then no loads or stores have been
29497 issued in the current cycle so we do nothing.
29499 - If the pendulum is 1, then a single load has been issued in this
29500 cycle and we attempt to locate another load in the ready list to
29503 - If the pendulum is -2, then two stores have already been
29504 issued in this cycle, so we increase the priority of the first load
29505 in the ready list to increase it's likelihood of being chosen first
29508 - If the pendulum is -1, then a single store has been issued in this
29509 cycle and we attempt to locate another store in the ready list to
29510 issue with it, preferring a store to an adjacent memory location to
29511 facilitate store pairing in the store queue.
29513 - If the pendulum is 2, then two loads have already been
29514 issued in this cycle, so we increase the priority of the first store
29515 in the ready list to increase it's likelihood of being chosen first
29518 - If the pendulum < -2 or > 2, then do nothing.
29520 Note: This code covers the most common scenarios. There exist non
29521 load/store instructions which make use of the LSU and which
29522 would need to be accounted for to strictly model the behavior
29523 of the machine. Those instructions are currently unaccounted
29524 for to help minimize compile time overhead of this code.
29526 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
29531 rtx load_mem
, str_mem
;
29533 if (is_store_insn (last_scheduled_insn
, &str_mem
))
29534 /* Issuing a store, swing the load_store_pendulum to the left */
29535 load_store_pendulum
--;
29536 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
29537 /* Issuing a load, swing the load_store_pendulum to the right */
29538 load_store_pendulum
++;
29540 return cached_can_issue_more
;
29542 /* If the pendulum is balanced, or there is only one instruction on
29543 the ready list, then all is well, so return. */
29544 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
29545 return cached_can_issue_more
;
29547 if (load_store_pendulum
== 1)
29549 /* A load has been issued in this cycle. Scan the ready list
29550 for another load to issue with it */
29555 if (is_load_insn (ready
[pos
], &load_mem
))
29557 /* Found a load. Move it to the head of the ready list,
29558 and adjust it's priority so that it is more likely to
29561 for (i
=pos
; i
<*pn_ready
-1; i
++)
29562 ready
[i
] = ready
[i
+ 1];
29563 ready
[*pn_ready
-1] = tmp
;
29565 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
29566 INSN_PRIORITY (tmp
)++;
29572 else if (load_store_pendulum
== -2)
29574 /* Two stores have been issued in this cycle. Increase the
29575 priority of the first load in the ready list to favor it for
29576 issuing in the next cycle. */
29581 if (is_load_insn (ready
[pos
], &load_mem
)
29583 && INSN_PRIORITY_KNOWN (ready
[pos
]))
29585 INSN_PRIORITY (ready
[pos
])++;
29587 /* Adjust the pendulum to account for the fact that a load
29588 was found and increased in priority. This is to prevent
29589 increasing the priority of multiple loads */
29590 load_store_pendulum
--;
29597 else if (load_store_pendulum
== -1)
29599 /* A store has been issued in this cycle. Scan the ready list for
29600 another store to issue with it, preferring a store to an adjacent
29602 int first_store_pos
= -1;
29608 if (is_store_insn (ready
[pos
], &str_mem
))
29611 /* Maintain the index of the first store found on the
29613 if (first_store_pos
== -1)
29614 first_store_pos
= pos
;
29616 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
29617 && adjacent_mem_locations (str_mem
, str_mem2
))
29619 /* Found an adjacent store. Move it to the head of the
29620 ready list, and adjust it's priority so that it is
29621 more likely to stay there */
29623 for (i
=pos
; i
<*pn_ready
-1; i
++)
29624 ready
[i
] = ready
[i
+ 1];
29625 ready
[*pn_ready
-1] = tmp
;
29627 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
29628 INSN_PRIORITY (tmp
)++;
29630 first_store_pos
= -1;
29638 if (first_store_pos
>= 0)
29640 /* An adjacent store wasn't found, but a non-adjacent store was,
29641 so move the non-adjacent store to the front of the ready
29642 list, and adjust its priority so that it is more likely to
29644 tmp
= ready
[first_store_pos
];
29645 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
29646 ready
[i
] = ready
[i
+ 1];
29647 ready
[*pn_ready
-1] = tmp
;
29648 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
29649 INSN_PRIORITY (tmp
)++;
29652 else if (load_store_pendulum
== 2)
29654 /* Two loads have been issued in this cycle. Increase the priority
29655 of the first store in the ready list to favor it for issuing in
29661 if (is_store_insn (ready
[pos
], &str_mem
)
29663 && INSN_PRIORITY_KNOWN (ready
[pos
]))
29665 INSN_PRIORITY (ready
[pos
])++;
29667 /* Adjust the pendulum to account for the fact that a store
29668 was found and increased in priority. This is to prevent
29669 increasing the priority of multiple stores */
29670 load_store_pendulum
++;
29679 return cached_can_issue_more
;
29682 /* Return whether the presence of INSN causes a dispatch group termination
29683 of group WHICH_GROUP.
29685 If WHICH_GROUP == current_group, this function will return true if INSN
29686 causes the termination of the current group (i.e, the dispatch group to
29687 which INSN belongs). This means that INSN will be the last insn in the
29688 group it belongs to.
29690 If WHICH_GROUP == previous_group, this function will return true if INSN
29691 causes the termination of the previous group (i.e, the dispatch group that
29692 precedes the group to which INSN belongs). This means that INSN will be
29693 the first insn in the group it belongs to). */
29696 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
29703 first
= insn_must_be_first_in_group (insn
);
29704 last
= insn_must_be_last_in_group (insn
);
29709 if (which_group
== current_group
)
29711 else if (which_group
== previous_group
)
29719 insn_must_be_first_in_group (rtx_insn
*insn
)
29721 enum attr_type type
;
29725 || DEBUG_INSN_P (insn
)
29726 || GET_CODE (PATTERN (insn
)) == USE
29727 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
29730 switch (rs6000_cpu
)
29732 case PROCESSOR_POWER5
:
29733 if (is_cracked_insn (insn
))
29735 case PROCESSOR_POWER4
:
29736 if (is_microcoded_insn (insn
))
29739 if (!rs6000_sched_groups
)
29742 type
= get_attr_type (insn
);
29749 case TYPE_DELAYED_CR
:
29750 case TYPE_CR_LOGICAL
:
29763 case PROCESSOR_POWER6
:
29764 type
= get_attr_type (insn
);
29773 case TYPE_FPCOMPARE
:
29784 if (get_attr_dot (insn
) == DOT_NO
29785 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
29790 if (get_attr_size (insn
) == SIZE_32
)
29798 if (get_attr_update (insn
) == UPDATE_YES
)
29806 case PROCESSOR_POWER7
:
29807 type
= get_attr_type (insn
);
29811 case TYPE_CR_LOGICAL
:
29825 if (get_attr_dot (insn
) == DOT_YES
)
29830 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29831 || get_attr_update (insn
) == UPDATE_YES
)
29838 if (get_attr_update (insn
) == UPDATE_YES
)
29846 case PROCESSOR_POWER8
:
29847 case PROCESSOR_POWER9
:
29848 type
= get_attr_type (insn
);
29852 case TYPE_CR_LOGICAL
:
29853 case TYPE_DELAYED_CR
:
29861 case TYPE_VECSTORE
:
29868 if (get_attr_dot (insn
) == DOT_YES
)
29873 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29874 || get_attr_update (insn
) == UPDATE_YES
)
29879 if (get_attr_update (insn
) == UPDATE_YES
29880 && get_attr_indexed (insn
) == INDEXED_YES
)
29896 insn_must_be_last_in_group (rtx_insn
*insn
)
29898 enum attr_type type
;
29902 || DEBUG_INSN_P (insn
)
29903 || GET_CODE (PATTERN (insn
)) == USE
29904 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
29907 switch (rs6000_cpu
) {
29908 case PROCESSOR_POWER4
:
29909 case PROCESSOR_POWER5
:
29910 if (is_microcoded_insn (insn
))
29913 if (is_branch_slot_insn (insn
))
29917 case PROCESSOR_POWER6
:
29918 type
= get_attr_type (insn
);
29926 case TYPE_FPCOMPARE
:
29937 if (get_attr_dot (insn
) == DOT_NO
29938 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
29943 if (get_attr_size (insn
) == SIZE_32
)
29951 case PROCESSOR_POWER7
:
29952 type
= get_attr_type (insn
);
29962 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29963 && get_attr_update (insn
) == UPDATE_YES
)
29968 if (get_attr_update (insn
) == UPDATE_YES
29969 && get_attr_indexed (insn
) == INDEXED_YES
)
29977 case PROCESSOR_POWER8
:
29978 case PROCESSOR_POWER9
:
29979 type
= get_attr_type (insn
);
29991 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29992 && get_attr_update (insn
) == UPDATE_YES
)
29997 if (get_attr_update (insn
) == UPDATE_YES
29998 && get_attr_indexed (insn
) == INDEXED_YES
)
30013 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
30014 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
30017 is_costly_group (rtx
*group_insns
, rtx next_insn
)
30020 int issue_rate
= rs6000_issue_rate ();
30022 for (i
= 0; i
< issue_rate
; i
++)
30024 sd_iterator_def sd_it
;
30026 rtx insn
= group_insns
[i
];
30031 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
30033 rtx next
= DEP_CON (dep
);
30035 if (next
== next_insn
30036 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
30044 /* Utility of the function redefine_groups.
30045 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
30046 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
30047 to keep it "far" (in a separate group) from GROUP_INSNS, following
30048 one of the following schemes, depending on the value of the flag
30049 -minsert_sched_nops = X:
30050 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
30051 in order to force NEXT_INSN into a separate group.
30052 (2) X < sched_finish_regroup_exact: insert exactly X nops.
30053 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
30054 insertion (has a group just ended, how many vacant issue slots remain in the
30055 last group, and how many dispatch groups were encountered so far). */
30058 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
30059 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
30064 int issue_rate
= rs6000_issue_rate ();
30065 bool end
= *group_end
;
30068 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
30069 return can_issue_more
;
30071 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
30072 return can_issue_more
;
30074 force
= is_costly_group (group_insns
, next_insn
);
30076 return can_issue_more
;
30078 if (sched_verbose
> 6)
30079 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
30080 *group_count
,can_issue_more
);
30082 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
30085 can_issue_more
= 0;
30087 /* Since only a branch can be issued in the last issue_slot, it is
30088 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
30089 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
30090 in this case the last nop will start a new group and the branch
30091 will be forced to the new group. */
30092 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
30095 /* Do we have a special group ending nop? */
30096 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
30097 || rs6000_cpu_attr
== CPU_POWER8
|| rs6000_cpu_attr
== CPU_POWER9
)
30099 nop
= gen_group_ending_nop ();
30100 emit_insn_before (nop
, next_insn
);
30101 can_issue_more
= 0;
30104 while (can_issue_more
> 0)
30107 emit_insn_before (nop
, next_insn
);
30115 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
30117 int n_nops
= rs6000_sched_insert_nops
;
30119 /* Nops can't be issued from the branch slot, so the effective
30120 issue_rate for nops is 'issue_rate - 1'. */
30121 if (can_issue_more
== 0)
30122 can_issue_more
= issue_rate
;
30124 if (can_issue_more
== 0)
30126 can_issue_more
= issue_rate
- 1;
30129 for (i
= 0; i
< issue_rate
; i
++)
30131 group_insns
[i
] = 0;
30138 emit_insn_before (nop
, next_insn
);
30139 if (can_issue_more
== issue_rate
- 1) /* new group begins */
30142 if (can_issue_more
== 0)
30144 can_issue_more
= issue_rate
- 1;
30147 for (i
= 0; i
< issue_rate
; i
++)
30149 group_insns
[i
] = 0;
30155 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
30158 /* Is next_insn going to start a new group? */
30161 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
30162 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
30163 || (can_issue_more
< issue_rate
&&
30164 insn_terminates_group_p (next_insn
, previous_group
)));
30165 if (*group_end
&& end
)
30168 if (sched_verbose
> 6)
30169 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
30170 *group_count
, can_issue_more
);
30171 return can_issue_more
;
30174 return can_issue_more
;
30177 /* This function tries to synch the dispatch groups that the compiler "sees"
30178 with the dispatch groups that the processor dispatcher is expected to
30179 form in practice. It tries to achieve this synchronization by forcing the
30180 estimated processor grouping on the compiler (as opposed to the function
30181 'pad_goups' which tries to force the scheduler's grouping on the processor).
30183 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
30184 examines the (estimated) dispatch groups that will be formed by the processor
30185 dispatcher. It marks these group boundaries to reflect the estimated
30186 processor grouping, overriding the grouping that the scheduler had marked.
30187 Depending on the value of the flag '-minsert-sched-nops' this function can
30188 force certain insns into separate groups or force a certain distance between
30189 them by inserting nops, for example, if there exists a "costly dependence"
30192 The function estimates the group boundaries that the processor will form as
30193 follows: It keeps track of how many vacant issue slots are available after
30194 each insn. A subsequent insn will start a new group if one of the following
30196 - no more vacant issue slots remain in the current dispatch group.
30197 - only the last issue slot, which is the branch slot, is vacant, but the next
30198 insn is not a branch.
30199 - only the last 2 or less issue slots, including the branch slot, are vacant,
30200 which means that a cracked insn (which occupies two issue slots) can't be
30201 issued in this group.
30202 - less than 'issue_rate' slots are vacant, and the next insn always needs to
30203 start a new group. */
30206 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
30209 rtx_insn
*insn
, *next_insn
;
30211 int can_issue_more
;
30214 int group_count
= 0;
30218 issue_rate
= rs6000_issue_rate ();
30219 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
30220 for (i
= 0; i
< issue_rate
; i
++)
30222 group_insns
[i
] = 0;
30224 can_issue_more
= issue_rate
;
30226 insn
= get_next_active_insn (prev_head_insn
, tail
);
30229 while (insn
!= NULL_RTX
)
30231 slot
= (issue_rate
- can_issue_more
);
30232 group_insns
[slot
] = insn
;
30234 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
30235 if (insn_terminates_group_p (insn
, current_group
))
30236 can_issue_more
= 0;
30238 next_insn
= get_next_active_insn (insn
, tail
);
30239 if (next_insn
== NULL_RTX
)
30240 return group_count
+ 1;
30242 /* Is next_insn going to start a new group? */
30244 = (can_issue_more
== 0
30245 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
30246 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
30247 || (can_issue_more
< issue_rate
&&
30248 insn_terminates_group_p (next_insn
, previous_group
)));
30250 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
30251 next_insn
, &group_end
, can_issue_more
,
30257 can_issue_more
= 0;
30258 for (i
= 0; i
< issue_rate
; i
++)
30260 group_insns
[i
] = 0;
30264 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
30265 PUT_MODE (next_insn
, VOIDmode
);
30266 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
30267 PUT_MODE (next_insn
, TImode
);
30270 if (can_issue_more
== 0)
30271 can_issue_more
= issue_rate
;
30274 return group_count
;
30277 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
30278 dispatch group boundaries that the scheduler had marked. Pad with nops
30279 any dispatch groups which have vacant issue slots, in order to force the
30280 scheduler's grouping on the processor dispatcher. The function
30281 returns the number of dispatch groups found. */
30284 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
30287 rtx_insn
*insn
, *next_insn
;
30290 int can_issue_more
;
30292 int group_count
= 0;
30294 /* Initialize issue_rate. */
30295 issue_rate
= rs6000_issue_rate ();
30296 can_issue_more
= issue_rate
;
30298 insn
= get_next_active_insn (prev_head_insn
, tail
);
30299 next_insn
= get_next_active_insn (insn
, tail
);
30301 while (insn
!= NULL_RTX
)
30304 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
30306 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
30308 if (next_insn
== NULL_RTX
)
30313 /* If the scheduler had marked group termination at this location
30314 (between insn and next_insn), and neither insn nor next_insn will
30315 force group termination, pad the group with nops to force group
30318 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
30319 && !insn_terminates_group_p (insn
, current_group
)
30320 && !insn_terminates_group_p (next_insn
, previous_group
))
30322 if (!is_branch_slot_insn (next_insn
))
30325 while (can_issue_more
)
30328 emit_insn_before (nop
, next_insn
);
30333 can_issue_more
= issue_rate
;
30338 next_insn
= get_next_active_insn (insn
, tail
);
30341 return group_count
;
30344 /* We're beginning a new block. Initialize data structures as necessary. */
30347 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
30348 int sched_verbose ATTRIBUTE_UNUSED
,
30349 int max_ready ATTRIBUTE_UNUSED
)
30351 last_scheduled_insn
= NULL_RTX
;
30352 load_store_pendulum
= 0;
30355 /* The following function is called at the end of scheduling BB.
30356 After reload, it inserts nops at insn group bundling. */
30359 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
30364 fprintf (dump
, "=== Finishing schedule.\n");
30366 if (reload_completed
&& rs6000_sched_groups
)
30368 /* Do not run sched_finish hook when selective scheduling enabled. */
30369 if (sel_sched_p ())
30372 if (rs6000_sched_insert_nops
== sched_finish_none
)
30375 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
30376 n_groups
= pad_groups (dump
, sched_verbose
,
30377 current_sched_info
->prev_head
,
30378 current_sched_info
->next_tail
);
30380 n_groups
= redefine_groups (dump
, sched_verbose
,
30381 current_sched_info
->prev_head
,
30382 current_sched_info
->next_tail
);
30384 if (sched_verbose
>= 6)
30386 fprintf (dump
, "ngroups = %d\n", n_groups
);
30387 print_rtl (dump
, current_sched_info
->prev_head
);
30388 fprintf (dump
, "Done finish_sched\n");
30393 struct _rs6000_sched_context
30395 short cached_can_issue_more
;
30396 rtx last_scheduled_insn
;
30397 int load_store_pendulum
;
30400 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
30401 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
30403 /* Allocate store for new scheduling context. */
30405 rs6000_alloc_sched_context (void)
30407 return xmalloc (sizeof (rs6000_sched_context_def
));
30410 /* If CLEAN_P is true then initializes _SC with clean data,
30411 and from the global context otherwise. */
30413 rs6000_init_sched_context (void *_sc
, bool clean_p
)
30415 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
30419 sc
->cached_can_issue_more
= 0;
30420 sc
->last_scheduled_insn
= NULL_RTX
;
30421 sc
->load_store_pendulum
= 0;
30425 sc
->cached_can_issue_more
= cached_can_issue_more
;
30426 sc
->last_scheduled_insn
= last_scheduled_insn
;
30427 sc
->load_store_pendulum
= load_store_pendulum
;
30431 /* Sets the global scheduling context to the one pointed to by _SC. */
30433 rs6000_set_sched_context (void *_sc
)
30435 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
30437 gcc_assert (sc
!= NULL
);
30439 cached_can_issue_more
= sc
->cached_can_issue_more
;
30440 last_scheduled_insn
= sc
->last_scheduled_insn
;
30441 load_store_pendulum
= sc
->load_store_pendulum
;
30446 rs6000_free_sched_context (void *_sc
)
30448 gcc_assert (_sc
!= NULL
);
30454 /* Length in units of the trampoline for entering a nested function. */
30457 rs6000_trampoline_size (void)
30461 switch (DEFAULT_ABI
)
30464 gcc_unreachable ();
30467 ret
= (TARGET_32BIT
) ? 12 : 24;
30471 gcc_assert (!TARGET_32BIT
);
30477 ret
= (TARGET_32BIT
) ? 40 : 48;
30484 /* Emit RTL insns to initialize the variable parts of a trampoline.
30485 FNADDR is an RTX for the address of the function's pure code.
30486 CXT is an RTX for the static chain value for the function. */
30489 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
30491 int regsize
= (TARGET_32BIT
) ? 4 : 8;
30492 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
30493 rtx ctx_reg
= force_reg (Pmode
, cxt
);
30494 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
30496 switch (DEFAULT_ABI
)
30499 gcc_unreachable ();
30501 /* Under AIX, just build the 3 word function descriptor */
30504 rtx fnmem
, fn_reg
, toc_reg
;
30506 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
30507 error ("You cannot take the address of a nested function if you use "
30508 "the -mno-pointers-to-nested-functions option.");
30510 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
30511 fn_reg
= gen_reg_rtx (Pmode
);
30512 toc_reg
= gen_reg_rtx (Pmode
);
30514 /* Macro to shorten the code expansions below. */
30515 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
30517 m_tramp
= replace_equiv_address (m_tramp
, addr
);
30519 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
30520 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
30521 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
30522 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
30523 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
30529 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
30533 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
30534 LCT_NORMAL
, VOIDmode
, 4,
30536 GEN_INT (rs6000_trampoline_size ()), SImode
,
30544 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
30545 identifier as an argument, so the front end shouldn't look it up. */
30548 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
30550 return is_attribute_p ("altivec", attr_id
);
30553 /* Handle the "altivec" attribute. The attribute may have
30554 arguments as follows:
30556 __attribute__((altivec(vector__)))
30557 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
30558 __attribute__((altivec(bool__))) (always followed by 'unsigned')
30560 and may appear more than once (e.g., 'vector bool char') in a
30561 given declaration. */
30564 rs6000_handle_altivec_attribute (tree
*node
,
30565 tree name ATTRIBUTE_UNUSED
,
30567 int flags ATTRIBUTE_UNUSED
,
30568 bool *no_add_attrs
)
30570 tree type
= *node
, result
= NULL_TREE
;
30574 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
30575 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
30576 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
30579 while (POINTER_TYPE_P (type
)
30580 || TREE_CODE (type
) == FUNCTION_TYPE
30581 || TREE_CODE (type
) == METHOD_TYPE
30582 || TREE_CODE (type
) == ARRAY_TYPE
)
30583 type
= TREE_TYPE (type
);
30585 mode
= TYPE_MODE (type
);
30587 /* Check for invalid AltiVec type qualifiers. */
30588 if (type
== long_double_type_node
)
30589 error ("use of %<long double%> in AltiVec types is invalid");
30590 else if (type
== boolean_type_node
)
30591 error ("use of boolean types in AltiVec types is invalid");
30592 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
30593 error ("use of %<complex%> in AltiVec types is invalid");
30594 else if (DECIMAL_FLOAT_MODE_P (mode
))
30595 error ("use of decimal floating point types in AltiVec types is invalid");
30596 else if (!TARGET_VSX
)
30598 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
30601 error ("use of %<long%> in AltiVec types is invalid for "
30602 "64-bit code without -mvsx");
30603 else if (rs6000_warn_altivec_long
)
30604 warning (0, "use of %<long%> in AltiVec types is deprecated; "
30607 else if (type
== long_long_unsigned_type_node
30608 || type
== long_long_integer_type_node
)
30609 error ("use of %<long long%> in AltiVec types is invalid without "
30611 else if (type
== double_type_node
)
30612 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
30615 switch (altivec_type
)
30618 unsigned_p
= TYPE_UNSIGNED (type
);
30622 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
30625 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
30628 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
30631 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
30634 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
30636 case SFmode
: result
= V4SF_type_node
; break;
30637 case DFmode
: result
= V2DF_type_node
; break;
30638 /* If the user says 'vector int bool', we may be handed the 'bool'
30639 attribute _before_ the 'vector' attribute, and so select the
30640 proper type in the 'b' case below. */
30641 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
30642 case V2DImode
: case V2DFmode
:
30650 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
30651 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
30652 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
30653 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
30660 case V8HImode
: result
= pixel_V8HI_type_node
;
30666 /* Propagate qualifiers attached to the element type
30667 onto the vector type. */
30668 if (result
&& result
!= type
&& TYPE_QUALS (type
))
30669 result
= build_qualified_type (result
, TYPE_QUALS (type
));
30671 *no_add_attrs
= true; /* No need to hang on to the attribute. */
30674 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
30679 /* AltiVec defines four built-in scalar types that serve as vector
30680 elements; we must teach the compiler how to mangle them. */
30682 static const char *
30683 rs6000_mangle_type (const_tree type
)
30685 type
= TYPE_MAIN_VARIANT (type
);
30687 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
30688 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
30691 if (type
== bool_char_type_node
) return "U6__boolc";
30692 if (type
== bool_short_type_node
) return "U6__bools";
30693 if (type
== pixel_type_node
) return "u7__pixel";
30694 if (type
== bool_int_type_node
) return "U6__booli";
30695 if (type
== bool_long_type_node
) return "U6__booll";
30697 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
30698 "g" for IBM extended double, no matter whether it is long double (using
30699 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
30700 if (TARGET_FLOAT128
)
30702 if (type
== ieee128_float_type_node
)
30703 return "U10__float128";
30705 if (type
== ibm128_float_type_node
)
30708 if (type
== long_double_type_node
&& TARGET_LONG_DOUBLE_128
)
30709 return (TARGET_IEEEQUAD
) ? "U10__float128" : "g";
30712 /* Mangle IBM extended float long double as `g' (__float128) on
30713 powerpc*-linux where long-double-64 previously was the default. */
30714 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
30716 && TARGET_LONG_DOUBLE_128
30717 && !TARGET_IEEEQUAD
)
30720 /* For all other types, use normal C++ mangling. */
30724 /* Handle a "longcall" or "shortcall" attribute; arguments as in
30725 struct attribute_spec.handler. */
30728 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
30729 tree args ATTRIBUTE_UNUSED
,
30730 int flags ATTRIBUTE_UNUSED
,
30731 bool *no_add_attrs
)
30733 if (TREE_CODE (*node
) != FUNCTION_TYPE
30734 && TREE_CODE (*node
) != FIELD_DECL
30735 && TREE_CODE (*node
) != TYPE_DECL
)
30737 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
30739 *no_add_attrs
= true;
30745 /* Set longcall attributes on all functions declared when
30746 rs6000_default_long_calls is true. */
30748 rs6000_set_default_type_attributes (tree type
)
30750 if (rs6000_default_long_calls
30751 && (TREE_CODE (type
) == FUNCTION_TYPE
30752 || TREE_CODE (type
) == METHOD_TYPE
))
30753 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
30755 TYPE_ATTRIBUTES (type
));
30758 darwin_set_default_type_attributes (type
);
30762 /* Return a reference suitable for calling a function with the
30763 longcall attribute. */
30766 rs6000_longcall_ref (rtx call_ref
)
30768 const char *call_name
;
30771 if (GET_CODE (call_ref
) != SYMBOL_REF
)
30774 /* System V adds '.' to the internal name, so skip them. */
30775 call_name
= XSTR (call_ref
, 0);
30776 if (*call_name
== '.')
30778 while (*call_name
== '.')
30781 node
= get_identifier (call_name
);
30782 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
30785 return force_reg (Pmode
, call_ref
);
30788 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
30789 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
30792 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
30793 struct attribute_spec.handler. */
30795 rs6000_handle_struct_attribute (tree
*node
, tree name
,
30796 tree args ATTRIBUTE_UNUSED
,
30797 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
30800 if (DECL_P (*node
))
30802 if (TREE_CODE (*node
) == TYPE_DECL
)
30803 type
= &TREE_TYPE (*node
);
30808 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
30809 || TREE_CODE (*type
) == UNION_TYPE
)))
30811 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
30812 *no_add_attrs
= true;
30815 else if ((is_attribute_p ("ms_struct", name
)
30816 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
30817 || ((is_attribute_p ("gcc_struct", name
)
30818 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
30820 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
30822 *no_add_attrs
= true;
30829 rs6000_ms_bitfield_layout_p (const_tree record_type
)
30831 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
30832 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
30833 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
30836 #ifdef USING_ELFOS_H
30838 /* A get_unnamed_section callback, used for switching to toc_section. */
30841 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
30843 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
30844 && TARGET_MINIMAL_TOC
30845 && !TARGET_RELOCATABLE
)
30847 if (!toc_initialized
)
30849 toc_initialized
= 1;
30850 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
30851 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
30852 fprintf (asm_out_file
, "\t.tc ");
30853 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
30854 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
30855 fprintf (asm_out_file
, "\n");
30857 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
30858 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
30859 fprintf (asm_out_file
, " = .+32768\n");
30862 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
30864 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
30865 && !TARGET_RELOCATABLE
)
30866 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
30869 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
30870 if (!toc_initialized
)
30872 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
30873 fprintf (asm_out_file
, " = .+32768\n");
30874 toc_initialized
= 1;
30879 /* Implement TARGET_ASM_INIT_SECTIONS. */
30882 rs6000_elf_asm_init_sections (void)
30885 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
30888 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
30889 SDATA2_SECTION_ASM_OP
);
30892 /* Implement TARGET_SELECT_RTX_SECTION. */
30895 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
30896 unsigned HOST_WIDE_INT align
)
30898 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
30899 return toc_section
;
30901 return default_elf_select_rtx_section (mode
, x
, align
);
30904 /* For a SYMBOL_REF, set generic flags and then perform some
30905 target-specific processing.
30907 When the AIX ABI is requested on a non-AIX system, replace the
30908 function name with the real name (with a leading .) rather than the
30909 function descriptor name. This saves a lot of overriding code to
30910 read the prefixes. */
30912 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
30914 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
30916 default_encode_section_info (decl
, rtl
, first
);
30919 && TREE_CODE (decl
) == FUNCTION_DECL
30921 && DEFAULT_ABI
== ABI_AIX
)
30923 rtx sym_ref
= XEXP (rtl
, 0);
30924 size_t len
= strlen (XSTR (sym_ref
, 0));
30925 char *str
= XALLOCAVEC (char, len
+ 2);
30927 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
30928 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
30933 compare_section_name (const char *section
, const char *templ
)
30937 len
= strlen (templ
);
30938 return (strncmp (section
, templ
, len
) == 0
30939 && (section
[len
] == 0 || section
[len
] == '.'));
30943 rs6000_elf_in_small_data_p (const_tree decl
)
30945 if (rs6000_sdata
== SDATA_NONE
)
30948 /* We want to merge strings, so we never consider them small data. */
30949 if (TREE_CODE (decl
) == STRING_CST
)
30952 /* Functions are never in the small data area. */
30953 if (TREE_CODE (decl
) == FUNCTION_DECL
)
30956 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
30958 const char *section
= DECL_SECTION_NAME (decl
);
30959 if (compare_section_name (section
, ".sdata")
30960 || compare_section_name (section
, ".sdata2")
30961 || compare_section_name (section
, ".gnu.linkonce.s")
30962 || compare_section_name (section
, ".sbss")
30963 || compare_section_name (section
, ".sbss2")
30964 || compare_section_name (section
, ".gnu.linkonce.sb")
30965 || strcmp (section
, ".PPC.EMB.sdata0") == 0
30966 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
30971 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
30974 && size
<= g_switch_value
30975 /* If it's not public, and we're not going to reference it there,
30976 there's no need to put it in the small data section. */
30977 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
30984 #endif /* USING_ELFOS_H */
30986 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
30989 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
30991 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
30994 /* Do not place thread-local symbols refs in the object blocks. */
30997 rs6000_use_blocks_for_decl_p (const_tree decl
)
30999 return !DECL_THREAD_LOCAL_P (decl
);
31002 /* Return a REG that occurs in ADDR with coefficient 1.
31003 ADDR can be effectively incremented by incrementing REG.
31005 r0 is special and we must not select it as an address
31006 register by this routine since our caller will try to
31007 increment the returned register via an "la" instruction. */
31010 find_addr_reg (rtx addr
)
31012 while (GET_CODE (addr
) == PLUS
)
31014 if (GET_CODE (XEXP (addr
, 0)) == REG
31015 && REGNO (XEXP (addr
, 0)) != 0)
31016 addr
= XEXP (addr
, 0);
31017 else if (GET_CODE (XEXP (addr
, 1)) == REG
31018 && REGNO (XEXP (addr
, 1)) != 0)
31019 addr
= XEXP (addr
, 1);
31020 else if (CONSTANT_P (XEXP (addr
, 0)))
31021 addr
= XEXP (addr
, 1);
31022 else if (CONSTANT_P (XEXP (addr
, 1)))
31023 addr
= XEXP (addr
, 0);
31025 gcc_unreachable ();
31027 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
31032 rs6000_fatal_bad_address (rtx op
)
31034 fatal_insn ("bad address", op
);
31039 typedef struct branch_island_d
{
31040 tree function_name
;
31046 static vec
<branch_island
, va_gc
> *branch_islands
;
31048 /* Remember to generate a branch island for far calls to the given
31052 add_compiler_branch_island (tree label_name
, tree function_name
,
31055 branch_island bi
= {function_name
, label_name
, line_number
};
31056 vec_safe_push (branch_islands
, bi
);
31059 /* Generate far-jump branch islands for everything recorded in
31060 branch_islands. Invoked immediately after the last instruction of
31061 the epilogue has been emitted; the branch islands must be appended
31062 to, and contiguous with, the function body. Mach-O stubs are
31063 generated in machopic_output_stub(). */
31066 macho_branch_islands (void)
31070 while (!vec_safe_is_empty (branch_islands
))
31072 branch_island
*bi
= &branch_islands
->last ();
31073 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
31074 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
31075 char name_buf
[512];
31076 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
31077 if (name
[0] == '*' || name
[0] == '&')
31078 strcpy (name_buf
, name
+1);
31082 strcpy (name_buf
+1, name
);
31084 strcpy (tmp_buf
, "\n");
31085 strcat (tmp_buf
, label
);
31086 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
31087 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
31088 dbxout_stabd (N_SLINE
, bi
->line_number
);
31089 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
31092 if (TARGET_LINK_STACK
)
31095 get_ppc476_thunk_name (name
);
31096 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
31097 strcat (tmp_buf
, name
);
31098 strcat (tmp_buf
, "\n");
31099 strcat (tmp_buf
, label
);
31100 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
31104 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
31105 strcat (tmp_buf
, label
);
31106 strcat (tmp_buf
, "_pic\n");
31107 strcat (tmp_buf
, label
);
31108 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
31111 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
31112 strcat (tmp_buf
, name_buf
);
31113 strcat (tmp_buf
, " - ");
31114 strcat (tmp_buf
, label
);
31115 strcat (tmp_buf
, "_pic)\n");
31117 strcat (tmp_buf
, "\tmtlr r0\n");
31119 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
31120 strcat (tmp_buf
, name_buf
);
31121 strcat (tmp_buf
, " - ");
31122 strcat (tmp_buf
, label
);
31123 strcat (tmp_buf
, "_pic)\n");
31125 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
31129 strcat (tmp_buf
, ":\nlis r12,hi16(");
31130 strcat (tmp_buf
, name_buf
);
31131 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
31132 strcat (tmp_buf
, name_buf
);
31133 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
31135 output_asm_insn (tmp_buf
, 0);
31136 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
31137 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
31138 dbxout_stabd (N_SLINE
, bi
->line_number
);
31139 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
31140 branch_islands
->pop ();
31144 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
31145 already there or not. */
31148 no_previous_def (tree function_name
)
31153 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
31154 if (function_name
== bi
->function_name
)
31159 /* GET_PREV_LABEL gets the label name from the previous definition of
31163 get_prev_label (tree function_name
)
31168 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
31169 if (function_name
== bi
->function_name
)
31170 return bi
->label_name
;
31174 /* INSN is either a function call or a millicode call. It may have an
31175 unconditional jump in its delay slot.
31177 CALL_DEST is the routine we are calling. */
31180 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
31181 int cookie_operand_number
)
31183 static char buf
[256];
31184 if (darwin_emit_branch_islands
31185 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
31186 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
31189 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
31191 if (no_previous_def (funname
))
31193 rtx label_rtx
= gen_label_rtx ();
31194 char *label_buf
, temp_buf
[256];
31195 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
31196 CODE_LABEL_NUMBER (label_rtx
));
31197 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
31198 labelname
= get_identifier (label_buf
);
31199 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
31202 labelname
= get_prev_label (funname
);
31204 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
31205 instruction will reach 'foo', otherwise link as 'bl L42'".
31206 "L42" should be a 'branch island', that will do a far jump to
31207 'foo'. Branch islands are generated in
31208 macho_branch_islands(). */
31209 sprintf (buf
, "jbsr %%z%d,%.246s",
31210 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
31213 sprintf (buf
, "bl %%z%d", dest_operand_number
);
31217 /* Generate PIC and indirect symbol stubs. */
31220 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
31222 unsigned int length
;
31223 char *symbol_name
, *lazy_ptr_name
;
31224 char *local_label_0
;
31225 static int label
= 0;
31227 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
31228 symb
= (*targetm
.strip_name_encoding
) (symb
);
31231 length
= strlen (symb
);
31232 symbol_name
= XALLOCAVEC (char, length
+ 32);
31233 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
31235 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
31236 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
31239 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
31241 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
31245 fprintf (file
, "\t.align 5\n");
31247 fprintf (file
, "%s:\n", stub
);
31248 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
31251 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
31252 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
31254 fprintf (file
, "\tmflr r0\n");
31255 if (TARGET_LINK_STACK
)
31258 get_ppc476_thunk_name (name
);
31259 fprintf (file
, "\tbl %s\n", name
);
31260 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
31264 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
31265 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
31267 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
31268 lazy_ptr_name
, local_label_0
);
31269 fprintf (file
, "\tmtlr r0\n");
31270 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
31271 (TARGET_64BIT
? "ldu" : "lwzu"),
31272 lazy_ptr_name
, local_label_0
);
31273 fprintf (file
, "\tmtctr r12\n");
31274 fprintf (file
, "\tbctr\n");
31278 fprintf (file
, "\t.align 4\n");
31280 fprintf (file
, "%s:\n", stub
);
31281 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
31283 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
31284 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
31285 (TARGET_64BIT
? "ldu" : "lwzu"),
31287 fprintf (file
, "\tmtctr r12\n");
31288 fprintf (file
, "\tbctr\n");
31291 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
31292 fprintf (file
, "%s:\n", lazy_ptr_name
);
31293 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
31294 fprintf (file
, "%sdyld_stub_binding_helper\n",
31295 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
31298 /* Legitimize PIC addresses. If the address is already
31299 position-independent, we return ORIG. Newly generated
31300 position-independent addresses go into a reg. This is REG if non
31301 zero, otherwise we allocate register(s) as necessary. */
31303 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
31306 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
31311 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
31312 reg
= gen_reg_rtx (Pmode
);
31314 if (GET_CODE (orig
) == CONST
)
31318 if (GET_CODE (XEXP (orig
, 0)) == PLUS
31319 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
31322 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
31324 /* Use a different reg for the intermediate value, as
31325 it will be marked UNCHANGING. */
31326 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
31327 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
31330 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
31333 if (GET_CODE (offset
) == CONST_INT
)
31335 if (SMALL_INT (offset
))
31336 return plus_constant (Pmode
, base
, INTVAL (offset
));
31337 else if (! reload_in_progress
&& ! reload_completed
)
31338 offset
= force_reg (Pmode
, offset
);
31341 rtx mem
= force_const_mem (Pmode
, orig
);
31342 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
31345 return gen_rtx_PLUS (Pmode
, base
, offset
);
31348 /* Fall back on generic machopic code. */
31349 return machopic_legitimize_pic_address (orig
, mode
, reg
);
31352 /* Output a .machine directive for the Darwin assembler, and call
31353 the generic start_file routine. */
31356 rs6000_darwin_file_start (void)
31358 static const struct
31362 HOST_WIDE_INT if_set
;
31364 { "ppc64", "ppc64", MASK_64BIT
},
31365 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
31366 { "power4", "ppc970", 0 },
31367 { "G5", "ppc970", 0 },
31368 { "7450", "ppc7450", 0 },
31369 { "7400", "ppc7400", MASK_ALTIVEC
},
31370 { "G4", "ppc7400", 0 },
31371 { "750", "ppc750", 0 },
31372 { "740", "ppc750", 0 },
31373 { "G3", "ppc750", 0 },
31374 { "604e", "ppc604e", 0 },
31375 { "604", "ppc604", 0 },
31376 { "603e", "ppc603", 0 },
31377 { "603", "ppc603", 0 },
31378 { "601", "ppc601", 0 },
31379 { NULL
, "ppc", 0 } };
31380 const char *cpu_id
= "";
31383 rs6000_file_start ();
31384 darwin_file_start ();
31386 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
31388 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
31389 cpu_id
= rs6000_default_cpu
;
31391 if (global_options_set
.x_rs6000_cpu_index
)
31392 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
31394 /* Look through the mapping array. Pick the first name that either
31395 matches the argument, has a bit set in IF_SET that is also set
31396 in the target flags, or has a NULL name. */
31399 while (mapping
[i
].arg
!= NULL
31400 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
31401 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
31404 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
31407 #endif /* TARGET_MACHO */
31411 rs6000_elf_reloc_rw_mask (void)
31415 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
31421 /* Record an element in the table of global constructors. SYMBOL is
31422 a SYMBOL_REF of the function to be called; PRIORITY is a number
31423 between 0 and MAX_INIT_PRIORITY.
31425 This differs from default_named_section_asm_out_constructor in
31426 that we have special handling for -mrelocatable. */
31428 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
31430 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
31432 const char *section
= ".ctors";
31435 if (priority
!= DEFAULT_INIT_PRIORITY
)
31437 sprintf (buf
, ".ctors.%.5u",
31438 /* Invert the numbering so the linker puts us in the proper
31439 order; constructors are run from right to left, and the
31440 linker sorts in increasing order. */
31441 MAX_INIT_PRIORITY
- priority
);
31445 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
31446 assemble_align (POINTER_SIZE
);
31448 if (TARGET_RELOCATABLE
)
31450 fputs ("\t.long (", asm_out_file
);
31451 output_addr_const (asm_out_file
, symbol
);
31452 fputs (")@fixup\n", asm_out_file
);
31455 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
31458 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
31460 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
31462 const char *section
= ".dtors";
31465 if (priority
!= DEFAULT_INIT_PRIORITY
)
31467 sprintf (buf
, ".dtors.%.5u",
31468 /* Invert the numbering so the linker puts us in the proper
31469 order; constructors are run from right to left, and the
31470 linker sorts in increasing order. */
31471 MAX_INIT_PRIORITY
- priority
);
31475 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
31476 assemble_align (POINTER_SIZE
);
31478 if (TARGET_RELOCATABLE
)
31480 fputs ("\t.long (", asm_out_file
);
31481 output_addr_const (asm_out_file
, symbol
);
31482 fputs (")@fixup\n", asm_out_file
);
31485 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
31489 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
31491 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
31493 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
31494 ASM_OUTPUT_LABEL (file
, name
);
31495 fputs (DOUBLE_INT_ASM_OP
, file
);
31496 rs6000_output_function_entry (file
, name
);
31497 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
31500 fputs ("\t.size\t", file
);
31501 assemble_name (file
, name
);
31502 fputs (",24\n\t.type\t.", file
);
31503 assemble_name (file
, name
);
31504 fputs (",@function\n", file
);
31505 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
31507 fputs ("\t.globl\t.", file
);
31508 assemble_name (file
, name
);
31513 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
31514 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
31515 rs6000_output_function_entry (file
, name
);
31516 fputs (":\n", file
);
31520 if (TARGET_RELOCATABLE
31521 && !TARGET_SECURE_PLT
31522 && (get_pool_size () != 0 || crtl
->profile
)
31527 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
31529 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
31530 fprintf (file
, "\t.long ");
31531 assemble_name (file
, buf
);
31533 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
31534 assemble_name (file
, buf
);
31538 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
31539 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
31541 if (TARGET_CMODEL
== CMODEL_LARGE
&& rs6000_global_entry_point_needed_p ())
31545 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
31547 fprintf (file
, "\t.quad .TOC.-");
31548 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
31549 assemble_name (file
, buf
);
31553 if (DEFAULT_ABI
== ABI_AIX
)
31555 const char *desc_name
, *orig_name
;
31557 orig_name
= (*targetm
.strip_name_encoding
) (name
);
31558 desc_name
= orig_name
;
31559 while (*desc_name
== '.')
31562 if (TREE_PUBLIC (decl
))
31563 fprintf (file
, "\t.globl %s\n", desc_name
);
31565 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
31566 fprintf (file
, "%s:\n", desc_name
);
31567 fprintf (file
, "\t.long %s\n", orig_name
);
31568 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
31569 fputs ("\t.long 0\n", file
);
31570 fprintf (file
, "\t.previous\n");
31572 ASM_OUTPUT_LABEL (file
, name
);
31575 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
31577 rs6000_elf_file_end (void)
31579 #ifdef HAVE_AS_GNU_ATTRIBUTE
31580 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
31582 if (rs6000_passes_float
)
31583 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
31584 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
31585 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
31587 if (rs6000_passes_vector
)
31588 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
31589 (TARGET_ALTIVEC_ABI
? 2
31590 : TARGET_SPE_ABI
? 3
31592 if (rs6000_returns_struct
)
31593 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
31594 aix_struct_return
? 2 : 1);
31597 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
31598 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
31599 file_end_indicate_exec_stack ();
31602 if (flag_split_stack
)
31603 file_end_indicate_split_stack ();
31609 #ifndef HAVE_XCOFF_DWARF_EXTRAS
31610 #define HAVE_XCOFF_DWARF_EXTRAS 0
31613 static enum unwind_info_type
31614 rs6000_xcoff_debug_unwind_info (void)
31620 rs6000_xcoff_asm_output_anchor (rtx symbol
)
31624 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
31625 SYMBOL_REF_BLOCK_OFFSET (symbol
));
31626 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
31627 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
31628 fprintf (asm_out_file
, ",");
31629 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
31630 fprintf (asm_out_file
, "\n");
31634 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
31636 fputs (GLOBAL_ASM_OP
, stream
);
31637 RS6000_OUTPUT_BASENAME (stream
, name
);
31638 putc ('\n', stream
);
31641 /* A get_unnamed_decl callback, used for read-only sections. PTR
31642 points to the section string variable. */
31645 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
31647 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
31648 *(const char *const *) directive
,
31649 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
31652 /* Likewise for read-write sections. */
31655 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
31657 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
31658 *(const char *const *) directive
,
31659 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
31663 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
31665 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
31666 *(const char *const *) directive
,
31667 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
31670 /* A get_unnamed_section callback, used for switching to toc_section. */
31673 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
31675 if (TARGET_MINIMAL_TOC
)
31677 /* toc_section is always selected at least once from
31678 rs6000_xcoff_file_start, so this is guaranteed to
31679 always be defined once and only once in each file. */
31680 if (!toc_initialized
)
31682 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
31683 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
31684 toc_initialized
= 1;
31686 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
31687 (TARGET_32BIT
? "" : ",3"));
31690 fputs ("\t.toc\n", asm_out_file
);
31693 /* Implement TARGET_ASM_INIT_SECTIONS. */
31696 rs6000_xcoff_asm_init_sections (void)
31698 read_only_data_section
31699 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
31700 &xcoff_read_only_section_name
);
31702 private_data_section
31703 = get_unnamed_section (SECTION_WRITE
,
31704 rs6000_xcoff_output_readwrite_section_asm_op
,
31705 &xcoff_private_data_section_name
);
31708 = get_unnamed_section (SECTION_TLS
,
31709 rs6000_xcoff_output_tls_section_asm_op
,
31710 &xcoff_tls_data_section_name
);
31712 tls_private_data_section
31713 = get_unnamed_section (SECTION_TLS
,
31714 rs6000_xcoff_output_tls_section_asm_op
,
31715 &xcoff_private_data_section_name
);
31717 read_only_private_data_section
31718 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
31719 &xcoff_private_data_section_name
);
31722 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
31724 readonly_data_section
= read_only_data_section
;
31728 rs6000_xcoff_reloc_rw_mask (void)
31734 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
31735 tree decl ATTRIBUTE_UNUSED
)
31738 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
31740 if (flags
& SECTION_EXCLUDE
)
31742 else if (flags
& SECTION_DEBUG
)
31744 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
31747 else if (flags
& SECTION_CODE
)
31749 else if (flags
& SECTION_TLS
)
31751 else if (flags
& SECTION_WRITE
)
31756 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
31757 (flags
& SECTION_CODE
) ? "." : "",
31758 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
31761 #define IN_NAMED_SECTION(DECL) \
31762 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
31763 && DECL_SECTION_NAME (DECL) != NULL)
31766 rs6000_xcoff_select_section (tree decl
, int reloc
,
31767 unsigned HOST_WIDE_INT align
)
31769 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
31771 if (align
> BIGGEST_ALIGNMENT
)
31773 resolve_unique_section (decl
, reloc
, true);
31774 if (IN_NAMED_SECTION (decl
))
31775 return get_named_section (decl
, NULL
, reloc
);
31778 if (decl_readonly_section (decl
, reloc
))
31780 if (TREE_PUBLIC (decl
))
31781 return read_only_data_section
;
31783 return read_only_private_data_section
;
31788 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
31790 if (TREE_PUBLIC (decl
))
31791 return tls_data_section
;
31792 else if (bss_initializer_p (decl
))
31794 /* Convert to COMMON to emit in BSS. */
31795 DECL_COMMON (decl
) = 1;
31796 return tls_comm_section
;
31799 return tls_private_data_section
;
31803 if (TREE_PUBLIC (decl
))
31804 return data_section
;
31806 return private_data_section
;
31811 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
31815 /* Use select_section for private data and uninitialized data with
31816 alignment <= BIGGEST_ALIGNMENT. */
31817 if (!TREE_PUBLIC (decl
)
31818 || DECL_COMMON (decl
)
31819 || (DECL_INITIAL (decl
) == NULL_TREE
31820 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
31821 || DECL_INITIAL (decl
) == error_mark_node
31822 || (flag_zero_initialized_in_bss
31823 && initializer_zerop (DECL_INITIAL (decl
))))
31826 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
31827 name
= (*targetm
.strip_name_encoding
) (name
);
31828 set_decl_section_name (decl
, name
);
31831 /* Select section for constant in constant pool.
31833 On RS/6000, all constants are in the private read-only data area.
31834 However, if this is being placed in the TOC it must be output as a
31838 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
31839 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
31841 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
31842 return toc_section
;
31844 return read_only_private_data_section
;
31847 /* Remove any trailing [DS] or the like from the symbol name. */
31849 static const char *
31850 rs6000_xcoff_strip_name_encoding (const char *name
)
31855 len
= strlen (name
);
31856 if (name
[len
- 1] == ']')
31857 return ggc_alloc_string (name
, len
- 4);
31862 /* Section attributes. AIX is always PIC. */
31864 static unsigned int
31865 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
31867 unsigned int align
;
31868 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
31870 /* Align to at least UNIT size. */
31871 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
31872 align
= MIN_UNITS_PER_WORD
;
31874 /* Increase alignment of large objects if not already stricter. */
31875 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
31876 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
31877 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
31879 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
31882 /* Output at beginning of assembler file.
31884 Initialize the section names for the RS/6000 at this point.
31886 Specify filename, including full path, to assembler.
31888 We want to go into the TOC section so at least one .toc will be emitted.
31889 Also, in order to output proper .bs/.es pairs, we need at least one static
31890 [RW] section emitted.
31892 Finally, declare mcount when profiling to make the assembler happy. */
31895 rs6000_xcoff_file_start (void)
31897 rs6000_gen_section_name (&xcoff_bss_section_name
,
31898 main_input_filename
, ".bss_");
31899 rs6000_gen_section_name (&xcoff_private_data_section_name
,
31900 main_input_filename
, ".rw_");
31901 rs6000_gen_section_name (&xcoff_read_only_section_name
,
31902 main_input_filename
, ".ro_");
31903 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
31904 main_input_filename
, ".tls_");
31905 rs6000_gen_section_name (&xcoff_tbss_section_name
,
31906 main_input_filename
, ".tbss_[UL]");
31908 fputs ("\t.file\t", asm_out_file
);
31909 output_quoted_string (asm_out_file
, main_input_filename
);
31910 fputc ('\n', asm_out_file
);
31911 if (write_symbols
!= NO_DEBUG
)
31912 switch_to_section (private_data_section
);
31913 switch_to_section (text_section
);
31915 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
31916 rs6000_file_start ();
31919 /* Output at end of assembler file.
31920 On the RS/6000, referencing data should automatically pull in text. */
31923 rs6000_xcoff_file_end (void)
31925 switch_to_section (text_section
);
31926 fputs ("_section_.text:\n", asm_out_file
);
31927 switch_to_section (data_section
);
31928 fputs (TARGET_32BIT
31929 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
31933 struct declare_alias_data
31936 bool function_descriptor
;
31939 /* Declare alias N. A helper function for for_node_and_aliases. */
31942 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
31944 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
31945 /* Main symbol is output specially, because varasm machinery does part of
31946 the job for us - we do not need to declare .globl/lglobs and such. */
31947 if (!n
->alias
|| n
->weakref
)
31950 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
31953 /* Prevent assemble_alias from trying to use .set pseudo operation
31954 that does not behave as expected by the middle-end. */
31955 TREE_ASM_WRITTEN (n
->decl
) = true;
31957 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
31958 char *buffer
= (char *) alloca (strlen (name
) + 2);
31960 int dollar_inside
= 0;
31962 strcpy (buffer
, name
);
31963 p
= strchr (buffer
, '$');
31967 p
= strchr (p
+ 1, '$');
31969 if (TREE_PUBLIC (n
->decl
))
31971 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
31973 if (dollar_inside
) {
31974 if (data
->function_descriptor
)
31975 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
31976 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
31978 if (data
->function_descriptor
)
31980 fputs ("\t.globl .", data
->file
);
31981 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
31982 putc ('\n', data
->file
);
31984 fputs ("\t.globl ", data
->file
);
31985 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
31986 putc ('\n', data
->file
);
31988 #ifdef ASM_WEAKEN_DECL
31989 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
31990 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
31997 if (data
->function_descriptor
)
31998 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
31999 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
32001 if (data
->function_descriptor
)
32003 fputs ("\t.lglobl .", data
->file
);
32004 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
32005 putc ('\n', data
->file
);
32007 fputs ("\t.lglobl ", data
->file
);
32008 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
32009 putc ('\n', data
->file
);
32011 if (data
->function_descriptor
)
32012 fputs (".", data
->file
);
32013 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
32014 fputs (":\n", data
->file
);
32018 /* This macro produces the initial definition of a function name.
32019 On the RS/6000, we need to place an extra '.' in the function name and
32020 output the function descriptor.
32021 Dollar signs are converted to underscores.
32023 The csect for the function will have already been created when
32024 text_section was selected. We do have to go back to that csect, however.
32026 The third and fourth parameters to the .function pseudo-op (16 and 044)
32027 are placeholders which no longer have any use.
32029 Because AIX assembler's .set command has unexpected semantics, we output
32030 all aliases as alternative labels in front of the definition. */
32033 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
32035 char *buffer
= (char *) alloca (strlen (name
) + 1);
32037 int dollar_inside
= 0;
32038 struct declare_alias_data data
= {file
, false};
32040 strcpy (buffer
, name
);
32041 p
= strchr (buffer
, '$');
32045 p
= strchr (p
+ 1, '$');
32047 if (TREE_PUBLIC (decl
))
32049 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
32051 if (dollar_inside
) {
32052 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
32053 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
32055 fputs ("\t.globl .", file
);
32056 RS6000_OUTPUT_BASENAME (file
, buffer
);
32062 if (dollar_inside
) {
32063 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
32064 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
32066 fputs ("\t.lglobl .", file
);
32067 RS6000_OUTPUT_BASENAME (file
, buffer
);
32070 fputs ("\t.csect ", file
);
32071 RS6000_OUTPUT_BASENAME (file
, buffer
);
32072 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
32073 RS6000_OUTPUT_BASENAME (file
, buffer
);
32074 fputs (":\n", file
);
32075 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
32076 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
32077 RS6000_OUTPUT_BASENAME (file
, buffer
);
32078 fputs (", TOC[tc0], 0\n", file
);
32080 switch_to_section (function_section (decl
));
32082 RS6000_OUTPUT_BASENAME (file
, buffer
);
32083 fputs (":\n", file
);
32084 data
.function_descriptor
= true;
32085 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
32086 if (!DECL_IGNORED_P (decl
))
32088 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
32089 xcoffout_declare_function (file
, decl
, buffer
);
32090 else if (write_symbols
== DWARF2_DEBUG
)
32092 name
= (*targetm
.strip_name_encoding
) (name
);
32093 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
32099 /* This macro produces the initial definition of a object (variable) name.
32100 Because AIX assembler's .set command has unexpected semantics, we output
32101 all aliases as alternative labels in front of the definition. */
32104 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
32106 struct declare_alias_data data
= {file
, false};
32107 RS6000_OUTPUT_BASENAME (file
, name
);
32108 fputs (":\n", file
);
32109 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
32112 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
32115 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
32117 fputs (integer_asm_op (size
, FALSE
), file
);
32118 assemble_name (file
, label
);
32119 fputs ("-$", file
);
32122 /* Output a symbol offset relative to the dbase for the current object.
32123 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
32126 __gcc_unwind_dbase is embedded in all executables/libraries through
32127 libgcc/config/rs6000/crtdbase.S. */
32130 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
32132 fputs (integer_asm_op (size
, FALSE
), file
);
32133 assemble_name (file
, label
);
32134 fputs("-__gcc_unwind_dbase", file
);
32139 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
32144 default_encode_section_info (decl
, rtl
, first
);
32146 /* Careful not to prod global register variables. */
32149 symbol
= XEXP (rtl
, 0);
32150 if (GET_CODE (symbol
) != SYMBOL_REF
)
32153 flags
= SYMBOL_REF_FLAGS (symbol
);
32155 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
32156 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
32158 SYMBOL_REF_FLAGS (symbol
) = flags
;
32160 #endif /* HAVE_AS_TLS */
32161 #endif /* TARGET_XCOFF */
32163 /* Return true if INSN should not be copied. */
32166 rs6000_cannot_copy_insn_p (rtx_insn
*insn
)
32168 return recog_memoized (insn
) >= 0
32169 && get_attr_cannot_copy (insn
);
32172 /* Compute a (partial) cost for rtx X. Return true if the complete
32173 cost has been computed, and false if subexpressions should be
32174 scanned. In either case, *TOTAL contains the cost result. */
32177 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
32178 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
32180 int code
= GET_CODE (x
);
32184 /* On the RS/6000, if it is valid in the insn, it is free. */
32186 if (((outer_code
== SET
32187 || outer_code
== PLUS
32188 || outer_code
== MINUS
)
32189 && (satisfies_constraint_I (x
)
32190 || satisfies_constraint_L (x
)))
32191 || (outer_code
== AND
32192 && (satisfies_constraint_K (x
)
32194 ? satisfies_constraint_L (x
)
32195 : satisfies_constraint_J (x
))))
32196 || ((outer_code
== IOR
|| outer_code
== XOR
)
32197 && (satisfies_constraint_K (x
)
32199 ? satisfies_constraint_L (x
)
32200 : satisfies_constraint_J (x
))))
32201 || outer_code
== ASHIFT
32202 || outer_code
== ASHIFTRT
32203 || outer_code
== LSHIFTRT
32204 || outer_code
== ROTATE
32205 || outer_code
== ROTATERT
32206 || outer_code
== ZERO_EXTRACT
32207 || (outer_code
== MULT
32208 && satisfies_constraint_I (x
))
32209 || ((outer_code
== DIV
|| outer_code
== UDIV
32210 || outer_code
== MOD
|| outer_code
== UMOD
)
32211 && exact_log2 (INTVAL (x
)) >= 0)
32212 || (outer_code
== COMPARE
32213 && (satisfies_constraint_I (x
)
32214 || satisfies_constraint_K (x
)))
32215 || ((outer_code
== EQ
|| outer_code
== NE
)
32216 && (satisfies_constraint_I (x
)
32217 || satisfies_constraint_K (x
)
32219 ? satisfies_constraint_L (x
)
32220 : satisfies_constraint_J (x
))))
32221 || (outer_code
== GTU
32222 && satisfies_constraint_I (x
))
32223 || (outer_code
== LTU
32224 && satisfies_constraint_P (x
)))
32229 else if ((outer_code
== PLUS
32230 && reg_or_add_cint_operand (x
, VOIDmode
))
32231 || (outer_code
== MINUS
32232 && reg_or_sub_cint_operand (x
, VOIDmode
))
32233 || ((outer_code
== SET
32234 || outer_code
== IOR
32235 || outer_code
== XOR
)
32237 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
32239 *total
= COSTS_N_INSNS (1);
32245 case CONST_WIDE_INT
:
32250 /* When optimizing for size, MEM should be slightly more expensive
32251 than generating address, e.g., (plus (reg) (const)).
32252 L1 cache latency is about two instructions. */
32253 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
32262 if (FLOAT_MODE_P (mode
))
32263 *total
= rs6000_cost
->fp
;
32265 *total
= COSTS_N_INSNS (1);
32269 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
32270 && satisfies_constraint_I (XEXP (x
, 1)))
32272 if (INTVAL (XEXP (x
, 1)) >= -256
32273 && INTVAL (XEXP (x
, 1)) <= 255)
32274 *total
= rs6000_cost
->mulsi_const9
;
32276 *total
= rs6000_cost
->mulsi_const
;
32278 else if (mode
== SFmode
)
32279 *total
= rs6000_cost
->fp
;
32280 else if (FLOAT_MODE_P (mode
))
32281 *total
= rs6000_cost
->dmul
;
32282 else if (mode
== DImode
)
32283 *total
= rs6000_cost
->muldi
;
32285 *total
= rs6000_cost
->mulsi
;
32289 if (mode
== SFmode
)
32290 *total
= rs6000_cost
->fp
;
32292 *total
= rs6000_cost
->dmul
;
32297 if (FLOAT_MODE_P (mode
))
32299 *total
= mode
== DFmode
? rs6000_cost
->ddiv
32300 : rs6000_cost
->sdiv
;
32307 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
32308 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
32310 if (code
== DIV
|| code
== MOD
)
32312 *total
= COSTS_N_INSNS (2);
32315 *total
= COSTS_N_INSNS (1);
32319 if (GET_MODE (XEXP (x
, 1)) == DImode
)
32320 *total
= rs6000_cost
->divdi
;
32322 *total
= rs6000_cost
->divsi
;
32324 /* Add in shift and subtract for MOD unless we have a mod instruction. */
32325 if (!TARGET_MODULO
&& (code
== MOD
|| code
== UMOD
))
32326 *total
+= COSTS_N_INSNS (2);
32330 *total
= COSTS_N_INSNS (TARGET_CTZ
? 1 : 4);
32334 *total
= COSTS_N_INSNS (4);
32338 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
32342 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
32346 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
32349 *total
= COSTS_N_INSNS (1);
32353 if (CONST_INT_P (XEXP (x
, 1)))
32355 rtx left
= XEXP (x
, 0);
32356 rtx_code left_code
= GET_CODE (left
);
32358 /* rotate-and-mask: 1 insn. */
32359 if ((left_code
== ROTATE
32360 || left_code
== ASHIFT
32361 || left_code
== LSHIFTRT
)
32362 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
32364 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
32365 if (!CONST_INT_P (XEXP (left
, 1)))
32366 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
32367 *total
+= COSTS_N_INSNS (1);
32371 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
32372 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
32373 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
32374 || (val
& 0xffff) == val
32375 || (val
& 0xffff0000) == val
32376 || ((val
& 0xffff) == 0 && mode
== SImode
))
32378 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
32379 *total
+= COSTS_N_INSNS (1);
32384 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
32386 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
32387 *total
+= COSTS_N_INSNS (2);
32392 *total
= COSTS_N_INSNS (1);
32397 *total
= COSTS_N_INSNS (1);
32403 *total
= COSTS_N_INSNS (1);
32407 /* The EXTSWSLI instruction is a combined instruction. Don't count both
32408 the sign extend and shift separately within the insn. */
32409 if (TARGET_EXTSWSLI
&& mode
== DImode
32410 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
32411 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
32422 /* Handle mul_highpart. */
32423 if (outer_code
== TRUNCATE
32424 && GET_CODE (XEXP (x
, 0)) == MULT
)
32426 if (mode
== DImode
)
32427 *total
= rs6000_cost
->muldi
;
32429 *total
= rs6000_cost
->mulsi
;
32432 else if (outer_code
== AND
)
32435 *total
= COSTS_N_INSNS (1);
32440 if (GET_CODE (XEXP (x
, 0)) == MEM
)
32443 *total
= COSTS_N_INSNS (1);
32449 if (!FLOAT_MODE_P (mode
))
32451 *total
= COSTS_N_INSNS (1);
32457 case UNSIGNED_FLOAT
:
32460 case FLOAT_TRUNCATE
:
32461 *total
= rs6000_cost
->fp
;
32465 if (mode
== DFmode
)
32466 *total
= rs6000_cost
->sfdf_convert
;
32468 *total
= rs6000_cost
->fp
;
32472 switch (XINT (x
, 1))
32475 *total
= rs6000_cost
->fp
;
32487 *total
= COSTS_N_INSNS (1);
32490 else if (FLOAT_MODE_P (mode
)
32491 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
32493 *total
= rs6000_cost
->fp
;
32502 /* Carry bit requires mode == Pmode.
32503 NEG or PLUS already counted so only add one. */
32505 && (outer_code
== NEG
|| outer_code
== PLUS
))
32507 *total
= COSTS_N_INSNS (1);
32510 if (outer_code
== SET
)
32512 if (XEXP (x
, 1) == const0_rtx
)
32514 if (TARGET_ISEL
&& !TARGET_MFCRF
)
32515 *total
= COSTS_N_INSNS (8);
32517 *total
= COSTS_N_INSNS (2);
32522 *total
= COSTS_N_INSNS (3);
32531 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
32533 if (TARGET_ISEL
&& !TARGET_MFCRF
)
32534 *total
= COSTS_N_INSNS (8);
32536 *total
= COSTS_N_INSNS (2);
32540 if (outer_code
== COMPARE
)
32554 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
32557 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
32558 int opno
, int *total
, bool speed
)
32560 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
32563 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
32564 "opno = %d, total = %d, speed = %s, x:\n",
32565 ret
? "complete" : "scan inner",
32566 GET_MODE_NAME (mode
),
32567 GET_RTX_NAME (outer_code
),
32570 speed
? "true" : "false");
32577 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
32580 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
32581 addr_space_t as
, bool speed
)
32583 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
32585 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
32586 ret
, speed
? "true" : "false");
32593 /* A C expression returning the cost of moving data from a register of class
32594 CLASS1 to one of CLASS2. */
32597 rs6000_register_move_cost (machine_mode mode
,
32598 reg_class_t from
, reg_class_t to
)
32602 if (TARGET_DEBUG_COST
)
32605 /* Moves from/to GENERAL_REGS. */
32606 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
32607 || reg_classes_intersect_p (from
, GENERAL_REGS
))
32609 reg_class_t rclass
= from
;
32611 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
32614 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
32615 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
32616 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
32618 /* It's more expensive to move CR_REGS than CR0_REGS because of the
32620 else if (rclass
== CR_REGS
)
32623 /* For those processors that have slow LR/CTR moves, make them more
32624 expensive than memory in order to bias spills to memory .*/
32625 else if ((rs6000_cpu
== PROCESSOR_POWER6
32626 || rs6000_cpu
== PROCESSOR_POWER7
32627 || rs6000_cpu
== PROCESSOR_POWER8
32628 || rs6000_cpu
== PROCESSOR_POWER9
)
32629 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
32630 ret
= 6 * hard_regno_nregs
[0][mode
];
32633 /* A move will cost one instruction per GPR moved. */
32634 ret
= 2 * hard_regno_nregs
[0][mode
];
32637 /* If we have VSX, we can easily move between FPR or Altivec registers. */
32638 else if (VECTOR_MEM_VSX_P (mode
)
32639 && reg_classes_intersect_p (to
, VSX_REGS
)
32640 && reg_classes_intersect_p (from
, VSX_REGS
))
32641 ret
= 2 * hard_regno_nregs
[32][mode
];
32643 /* Moving between two similar registers is just one instruction. */
32644 else if (reg_classes_intersect_p (to
, from
))
32645 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
32647 /* Everything else has to go through GENERAL_REGS. */
32649 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
32650 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
32652 if (TARGET_DEBUG_COST
)
32654 if (dbg_cost_ctrl
== 1)
32656 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
32657 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
32658 reg_class_names
[to
]);
32665 /* A C expressions returning the cost of moving data of MODE from a register to
32669 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
32670 bool in ATTRIBUTE_UNUSED
)
32674 if (TARGET_DEBUG_COST
)
32677 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
32678 ret
= 4 * hard_regno_nregs
[0][mode
];
32679 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
32680 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
32681 ret
= 4 * hard_regno_nregs
[32][mode
];
32682 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
32683 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
32685 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
32687 if (TARGET_DEBUG_COST
)
32689 if (dbg_cost_ctrl
== 1)
32691 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
32692 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
32699 /* Returns a code for a target-specific builtin that implements
32700 reciprocal of the function, or NULL_TREE if not available. */
32703 rs6000_builtin_reciprocal (tree fndecl
)
32705 switch (DECL_FUNCTION_CODE (fndecl
))
32707 case VSX_BUILTIN_XVSQRTDP
:
32708 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
32711 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
32713 case VSX_BUILTIN_XVSQRTSP
:
32714 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
32717 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
32724 /* Load up a constant. If the mode is a vector mode, splat the value across
32725 all of the vector elements. */
32728 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
32732 if (mode
== SFmode
|| mode
== DFmode
)
32734 rtx d
= const_double_from_real_value (dconst
, mode
);
32735 reg
= force_reg (mode
, d
);
32737 else if (mode
== V4SFmode
)
32739 rtx d
= const_double_from_real_value (dconst
, SFmode
);
32740 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
32741 reg
= gen_reg_rtx (mode
);
32742 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
32744 else if (mode
== V2DFmode
)
32746 rtx d
= const_double_from_real_value (dconst
, DFmode
);
32747 rtvec v
= gen_rtvec (2, d
, d
);
32748 reg
= gen_reg_rtx (mode
);
32749 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
32752 gcc_unreachable ();
32757 /* Generate an FMA instruction. */
32760 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
32762 machine_mode mode
= GET_MODE (target
);
32765 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
32766 gcc_assert (dst
!= NULL
);
32769 emit_move_insn (target
, dst
);
32772 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
32775 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
32777 machine_mode mode
= GET_MODE (dst
);
32780 /* This is a tad more complicated, since the fnma_optab is for
32781 a different expression: fma(-m1, m2, a), which is the same
32782 thing except in the case of signed zeros.
32784 Fortunately we know that if FMA is supported that FNMSUB is
32785 also supported in the ISA. Just expand it directly. */
32787 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
32789 r
= gen_rtx_NEG (mode
, a
);
32790 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
32791 r
= gen_rtx_NEG (mode
, r
);
32792 emit_insn (gen_rtx_SET (dst
, r
));
32795 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
32796 add a reg_note saying that this was a division. Support both scalar and
32797 vector divide. Assumes no trapping math and finite arguments. */
32800 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
32802 machine_mode mode
= GET_MODE (dst
);
32803 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
32806 /* Low precision estimates guarantee 5 bits of accuracy. High
32807 precision estimates guarantee 14 bits of accuracy. SFmode
32808 requires 23 bits of accuracy. DFmode requires 52 bits of
32809 accuracy. Each pass at least doubles the accuracy, leading
32810 to the following. */
32811 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
32812 if (mode
== DFmode
|| mode
== V2DFmode
)
32815 enum insn_code code
= optab_handler (smul_optab
, mode
);
32816 insn_gen_fn gen_mul
= GEN_FCN (code
);
32818 gcc_assert (code
!= CODE_FOR_nothing
);
32820 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
32822 /* x0 = 1./d estimate */
32823 x0
= gen_reg_rtx (mode
);
32824 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
32827 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
32830 /* e0 = 1. - d * x0 */
32831 e0
= gen_reg_rtx (mode
);
32832 rs6000_emit_nmsub (e0
, d
, x0
, one
);
32834 /* x1 = x0 + e0 * x0 */
32835 x1
= gen_reg_rtx (mode
);
32836 rs6000_emit_madd (x1
, e0
, x0
, x0
);
32838 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
32839 ++i
, xprev
= xnext
, eprev
= enext
) {
32841 /* enext = eprev * eprev */
32842 enext
= gen_reg_rtx (mode
);
32843 emit_insn (gen_mul (enext
, eprev
, eprev
));
32845 /* xnext = xprev + enext * xprev */
32846 xnext
= gen_reg_rtx (mode
);
32847 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
32853 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
32855 /* u = n * xprev */
32856 u
= gen_reg_rtx (mode
);
32857 emit_insn (gen_mul (u
, n
, xprev
));
32859 /* v = n - (d * u) */
32860 v
= gen_reg_rtx (mode
);
32861 rs6000_emit_nmsub (v
, d
, u
, n
);
32863 /* dst = (v * xprev) + u */
32864 rs6000_emit_madd (dst
, v
, xprev
, u
);
32867 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
32870 /* Goldschmidt's Algorithm for single/double-precision floating point
32871 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
32874 rs6000_emit_swsqrt (rtx dst
, rtx src
, bool recip
)
32876 machine_mode mode
= GET_MODE (src
);
32877 rtx e
= gen_reg_rtx (mode
);
32878 rtx g
= gen_reg_rtx (mode
);
32879 rtx h
= gen_reg_rtx (mode
);
32881 /* Low precision estimates guarantee 5 bits of accuracy. High
32882 precision estimates guarantee 14 bits of accuracy. SFmode
32883 requires 23 bits of accuracy. DFmode requires 52 bits of
32884 accuracy. Each pass at least doubles the accuracy, leading
32885 to the following. */
32886 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
32887 if (mode
== DFmode
|| mode
== V2DFmode
)
32892 enum insn_code code
= optab_handler (smul_optab
, mode
);
32893 insn_gen_fn gen_mul
= GEN_FCN (code
);
32895 gcc_assert (code
!= CODE_FOR_nothing
);
32897 mhalf
= rs6000_load_constant_and_splat (mode
, dconsthalf
);
32899 /* e = rsqrt estimate */
32900 emit_insn (gen_rtx_SET (e
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
32903 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
32906 rtx zero
= force_reg (mode
, CONST0_RTX (mode
));
32908 if (mode
== SFmode
)
32910 rtx target
= emit_conditional_move (e
, GT
, src
, zero
, mode
,
32913 emit_move_insn (e
, target
);
32917 rtx cond
= gen_rtx_GT (VOIDmode
, e
, zero
);
32918 rs6000_emit_vector_cond_expr (e
, e
, zero
, cond
, src
, zero
);
32922 /* g = sqrt estimate. */
32923 emit_insn (gen_mul (g
, e
, src
));
32924 /* h = 1/(2*sqrt) estimate. */
32925 emit_insn (gen_mul (h
, e
, mhalf
));
32931 rtx t
= gen_reg_rtx (mode
);
32932 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
32933 /* Apply correction directly to 1/rsqrt estimate. */
32934 rs6000_emit_madd (dst
, e
, t
, e
);
32938 for (i
= 0; i
< passes
; i
++)
32940 rtx t1
= gen_reg_rtx (mode
);
32941 rtx g1
= gen_reg_rtx (mode
);
32942 rtx h1
= gen_reg_rtx (mode
);
32944 rs6000_emit_nmsub (t1
, g
, h
, mhalf
);
32945 rs6000_emit_madd (g1
, g
, t1
, g
);
32946 rs6000_emit_madd (h1
, h
, t1
, h
);
32951 /* Multiply by 2 for 1/rsqrt. */
32952 emit_insn (gen_add3_insn (dst
, h
, h
));
32957 rtx t
= gen_reg_rtx (mode
);
32958 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
32959 rs6000_emit_madd (dst
, g
, t
, g
);
32965 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
32966 (Power7) targets. DST is the target, and SRC is the argument operand. */
32969 rs6000_emit_popcount (rtx dst
, rtx src
)
32971 machine_mode mode
= GET_MODE (dst
);
32974 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
32975 if (TARGET_POPCNTD
)
32977 if (mode
== SImode
)
32978 emit_insn (gen_popcntdsi2 (dst
, src
));
32980 emit_insn (gen_popcntddi2 (dst
, src
));
32984 tmp1
= gen_reg_rtx (mode
);
32986 if (mode
== SImode
)
32988 emit_insn (gen_popcntbsi2 (tmp1
, src
));
32989 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
32991 tmp2
= force_reg (SImode
, tmp2
);
32992 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
32996 emit_insn (gen_popcntbdi2 (tmp1
, src
));
32997 tmp2
= expand_mult (DImode
, tmp1
,
32998 GEN_INT ((HOST_WIDE_INT
)
32999 0x01010101 << 32 | 0x01010101),
33001 tmp2
= force_reg (DImode
, tmp2
);
33002 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
33007 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
33008 target, and SRC is the argument operand. */
33011 rs6000_emit_parity (rtx dst
, rtx src
)
33013 machine_mode mode
= GET_MODE (dst
);
33016 tmp
= gen_reg_rtx (mode
);
33018 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
33021 if (mode
== SImode
)
33023 emit_insn (gen_popcntbsi2 (tmp
, src
));
33024 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
33028 emit_insn (gen_popcntbdi2 (tmp
, src
));
33029 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
33034 if (mode
== SImode
)
33036 /* Is mult+shift >= shift+xor+shift+xor? */
33037 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
33039 rtx tmp1
, tmp2
, tmp3
, tmp4
;
33041 tmp1
= gen_reg_rtx (SImode
);
33042 emit_insn (gen_popcntbsi2 (tmp1
, src
));
33044 tmp2
= gen_reg_rtx (SImode
);
33045 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
33046 tmp3
= gen_reg_rtx (SImode
);
33047 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
33049 tmp4
= gen_reg_rtx (SImode
);
33050 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
33051 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
33054 rs6000_emit_popcount (tmp
, src
);
33055 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
33059 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
33060 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
33062 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
33064 tmp1
= gen_reg_rtx (DImode
);
33065 emit_insn (gen_popcntbdi2 (tmp1
, src
));
33067 tmp2
= gen_reg_rtx (DImode
);
33068 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
33069 tmp3
= gen_reg_rtx (DImode
);
33070 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
33072 tmp4
= gen_reg_rtx (DImode
);
33073 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
33074 tmp5
= gen_reg_rtx (DImode
);
33075 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
33077 tmp6
= gen_reg_rtx (DImode
);
33078 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
33079 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
33082 rs6000_emit_popcount (tmp
, src
);
33083 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
33087 /* Expand an Altivec constant permutation for little endian mode.
33088 There are two issues: First, the two input operands must be
33089 swapped so that together they form a double-wide array in LE
33090 order. Second, the vperm instruction has surprising behavior
33091 in LE mode: it interprets the elements of the source vectors
33092 in BE mode ("left to right") and interprets the elements of
33093 the destination vector in LE mode ("right to left"). To
33094 correct for this, we must subtract each element of the permute
33095 control vector from 31.
33097 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
33098 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
33099 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
33100 serve as the permute control vector. Then, in BE mode,
33104 places the desired result in vr9. However, in LE mode the
33105 vector contents will be
33107 vr10 = 00000003 00000002 00000001 00000000
33108 vr11 = 00000007 00000006 00000005 00000004
33110 The result of the vperm using the same permute control vector is
33112 vr9 = 05000000 07000000 01000000 03000000
33114 That is, the leftmost 4 bytes of vr10 are interpreted as the
33115 source for the rightmost 4 bytes of vr9, and so on.
33117 If we change the permute control vector to
33119 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
33127 vr9 = 00000006 00000004 00000002 00000000. */
33130 altivec_expand_vec_perm_const_le (rtx operands
[4])
33134 rtx constv
, unspec
;
33135 rtx target
= operands
[0];
33136 rtx op0
= operands
[1];
33137 rtx op1
= operands
[2];
33138 rtx sel
= operands
[3];
33140 /* Unpack and adjust the constant selector. */
33141 for (i
= 0; i
< 16; ++i
)
33143 rtx e
= XVECEXP (sel
, 0, i
);
33144 unsigned int elt
= 31 - (INTVAL (e
) & 31);
33145 perm
[i
] = GEN_INT (elt
);
33148 /* Expand to a permute, swapping the inputs and using the
33149 adjusted selector. */
33151 op0
= force_reg (V16QImode
, op0
);
33153 op1
= force_reg (V16QImode
, op1
);
33155 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
33156 constv
= force_reg (V16QImode
, constv
);
33157 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
33159 if (!REG_P (target
))
33161 rtx tmp
= gen_reg_rtx (V16QImode
);
33162 emit_move_insn (tmp
, unspec
);
33166 emit_move_insn (target
, unspec
);
33169 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
33170 permute control vector. But here it's not a constant, so we must
33171 generate a vector NAND or NOR to do the adjustment. */
33174 altivec_expand_vec_perm_le (rtx operands
[4])
33176 rtx notx
, iorx
, unspec
;
33177 rtx target
= operands
[0];
33178 rtx op0
= operands
[1];
33179 rtx op1
= operands
[2];
33180 rtx sel
= operands
[3];
33182 rtx norreg
= gen_reg_rtx (V16QImode
);
33183 machine_mode mode
= GET_MODE (target
);
33185 /* Get everything in regs so the pattern matches. */
33187 op0
= force_reg (mode
, op0
);
33189 op1
= force_reg (mode
, op1
);
33191 sel
= force_reg (V16QImode
, sel
);
33192 if (!REG_P (target
))
33193 tmp
= gen_reg_rtx (mode
);
33195 /* Invert the selector with a VNAND if available, else a VNOR.
33196 The VNAND is preferred for future fusion opportunities. */
33197 notx
= gen_rtx_NOT (V16QImode
, sel
);
33198 iorx
= (TARGET_P8_VECTOR
33199 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
33200 : gen_rtx_AND (V16QImode
, notx
, notx
));
33201 emit_insn (gen_rtx_SET (norreg
, iorx
));
33203 /* Permute with operands reversed and adjusted selector. */
33204 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
33207 /* Copy into target, possibly by way of a register. */
33208 if (!REG_P (target
))
33210 emit_move_insn (tmp
, unspec
);
33214 emit_move_insn (target
, unspec
);
33217 /* Expand an Altivec constant permutation. Return true if we match
33218 an efficient implementation; false to fall back to VPERM. */
33221 altivec_expand_vec_perm_const (rtx operands
[4])
33223 struct altivec_perm_insn
{
33224 HOST_WIDE_INT mask
;
33225 enum insn_code impl
;
33226 unsigned char perm
[16];
33228 static const struct altivec_perm_insn patterns
[] = {
33229 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
33230 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
33231 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
33232 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
33233 { OPTION_MASK_ALTIVEC
,
33234 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
33235 : CODE_FOR_altivec_vmrglb_direct
),
33236 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
33237 { OPTION_MASK_ALTIVEC
,
33238 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
33239 : CODE_FOR_altivec_vmrglh_direct
),
33240 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
33241 { OPTION_MASK_ALTIVEC
,
33242 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
33243 : CODE_FOR_altivec_vmrglw_direct
),
33244 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
33245 { OPTION_MASK_ALTIVEC
,
33246 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
33247 : CODE_FOR_altivec_vmrghb_direct
),
33248 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
33249 { OPTION_MASK_ALTIVEC
,
33250 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
33251 : CODE_FOR_altivec_vmrghh_direct
),
33252 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
33253 { OPTION_MASK_ALTIVEC
,
33254 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
33255 : CODE_FOR_altivec_vmrghw_direct
),
33256 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
33257 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
33258 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
33259 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
33260 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
33263 unsigned int i
, j
, elt
, which
;
33264 unsigned char perm
[16];
33265 rtx target
, op0
, op1
, sel
, x
;
33268 target
= operands
[0];
33273 /* Unpack the constant selector. */
33274 for (i
= which
= 0; i
< 16; ++i
)
33276 rtx e
= XVECEXP (sel
, 0, i
);
33277 elt
= INTVAL (e
) & 31;
33278 which
|= (elt
< 16 ? 1 : 2);
33282 /* Simplify the constant selector based on operands. */
33286 gcc_unreachable ();
33290 if (!rtx_equal_p (op0
, op1
))
33295 for (i
= 0; i
< 16; ++i
)
33307 /* Look for splat patterns. */
33312 for (i
= 0; i
< 16; ++i
)
33313 if (perm
[i
] != elt
)
33317 if (!BYTES_BIG_ENDIAN
)
33319 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
33325 for (i
= 0; i
< 16; i
+= 2)
33326 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
33330 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
33331 x
= gen_reg_rtx (V8HImode
);
33332 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
33334 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
33341 for (i
= 0; i
< 16; i
+= 4)
33343 || perm
[i
+ 1] != elt
+ 1
33344 || perm
[i
+ 2] != elt
+ 2
33345 || perm
[i
+ 3] != elt
+ 3)
33349 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
33350 x
= gen_reg_rtx (V4SImode
);
33351 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
33353 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
33359 /* Look for merge and pack patterns. */
33360 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
33364 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
33367 elt
= patterns
[j
].perm
[0];
33368 if (perm
[0] == elt
)
33370 else if (perm
[0] == elt
+ 16)
33374 for (i
= 1; i
< 16; ++i
)
33376 elt
= patterns
[j
].perm
[i
];
33378 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
33379 else if (one_vec
&& elt
>= 16)
33381 if (perm
[i
] != elt
)
33386 enum insn_code icode
= patterns
[j
].impl
;
33387 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
33388 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
33390 /* For little-endian, don't use vpkuwum and vpkuhum if the
33391 underlying vector type is not V4SI and V8HI, respectively.
33392 For example, using vpkuwum with a V8HI picks up the even
33393 halfwords (BE numbering) when the even halfwords (LE
33394 numbering) are what we need. */
33395 if (!BYTES_BIG_ENDIAN
33396 && icode
== CODE_FOR_altivec_vpkuwum_direct
33397 && ((GET_CODE (op0
) == REG
33398 && GET_MODE (op0
) != V4SImode
)
33399 || (GET_CODE (op0
) == SUBREG
33400 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
33402 if (!BYTES_BIG_ENDIAN
33403 && icode
== CODE_FOR_altivec_vpkuhum_direct
33404 && ((GET_CODE (op0
) == REG
33405 && GET_MODE (op0
) != V8HImode
)
33406 || (GET_CODE (op0
) == SUBREG
33407 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
33410 /* For little-endian, the two input operands must be swapped
33411 (or swapped back) to ensure proper right-to-left numbering
33413 if (swapped
^ !BYTES_BIG_ENDIAN
)
33414 std::swap (op0
, op1
);
33415 if (imode
!= V16QImode
)
33417 op0
= gen_lowpart (imode
, op0
);
33418 op1
= gen_lowpart (imode
, op1
);
33420 if (omode
== V16QImode
)
33423 x
= gen_reg_rtx (omode
);
33424 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
33425 if (omode
!= V16QImode
)
33426 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
33431 if (!BYTES_BIG_ENDIAN
)
33433 altivec_expand_vec_perm_const_le (operands
);
33440 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
33441 Return true if we match an efficient implementation. */
33444 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
33445 unsigned char perm0
, unsigned char perm1
)
33449 /* If both selectors come from the same operand, fold to single op. */
33450 if ((perm0
& 2) == (perm1
& 2))
33457 /* If both operands are equal, fold to simpler permutation. */
33458 if (rtx_equal_p (op0
, op1
))
33461 perm1
= (perm1
& 1) + 2;
33463 /* If the first selector comes from the second operand, swap. */
33464 else if (perm0
& 2)
33470 std::swap (op0
, op1
);
33472 /* If the second selector does not come from the second operand, fail. */
33473 else if ((perm1
& 2) == 0)
33477 if (target
!= NULL
)
33479 machine_mode vmode
, dmode
;
33482 vmode
= GET_MODE (target
);
33483 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
33484 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
33485 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
33486 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
33487 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
33488 emit_insn (gen_rtx_SET (target
, x
));
33494 rs6000_expand_vec_perm_const (rtx operands
[4])
33496 rtx target
, op0
, op1
, sel
;
33497 unsigned char perm0
, perm1
;
33499 target
= operands
[0];
33504 /* Unpack the constant selector. */
33505 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
33506 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
33508 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
33511 /* Test whether a constant permutation is supported. */
33514 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode
,
33515 const unsigned char *sel
)
33517 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
33518 if (TARGET_ALTIVEC
)
33521 /* Check for ps_merge* or evmerge* insns. */
33522 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
33523 || (TARGET_SPE
&& vmode
== V2SImode
))
33525 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
33526 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
33527 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
33533 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
33536 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
33537 machine_mode vmode
, unsigned nelt
, rtx perm
[])
33539 machine_mode imode
;
33543 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
33545 imode
= mode_for_size (GET_MODE_UNIT_BITSIZE (vmode
), MODE_INT
, 0);
33546 imode
= mode_for_vector (imode
, nelt
);
33549 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
33550 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
33552 emit_move_insn (target
, x
);
33555 /* Expand an extract even operation. */
33558 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
33560 machine_mode vmode
= GET_MODE (target
);
33561 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
33564 for (i
= 0; i
< nelt
; i
++)
33565 perm
[i
] = GEN_INT (i
* 2);
33567 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
33570 /* Expand a vector interleave operation. */
33573 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
33575 machine_mode vmode
= GET_MODE (target
);
33576 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
33579 high
= (highp
? 0 : nelt
/ 2);
33580 for (i
= 0; i
< nelt
/ 2; i
++)
33582 perm
[i
* 2] = GEN_INT (i
+ high
);
33583 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
33586 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
33589 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
33591 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
33593 HOST_WIDE_INT
hwi_scale (scale
);
33594 REAL_VALUE_TYPE r_pow
;
33595 rtvec v
= rtvec_alloc (2);
33597 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
33598 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
33599 elt
= const_double_from_real_value (r_pow
, DFmode
);
33600 RTVEC_ELT (v
, 0) = elt
;
33601 RTVEC_ELT (v
, 1) = elt
;
33602 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
33603 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
33606 /* Return an RTX representing where to find the function value of a
33607 function returning MODE. */
33609 rs6000_complex_function_value (machine_mode mode
)
33611 unsigned int regno
;
33613 machine_mode inner
= GET_MODE_INNER (mode
);
33614 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
33616 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
33617 regno
= FP_ARG_RETURN
;
33620 regno
= GP_ARG_RETURN
;
33622 /* 32-bit is OK since it'll go in r3/r4. */
33623 if (TARGET_32BIT
&& inner_bytes
>= 4)
33624 return gen_rtx_REG (mode
, regno
);
33627 if (inner_bytes
>= 8)
33628 return gen_rtx_REG (mode
, regno
);
33630 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
33632 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
33633 GEN_INT (inner_bytes
));
33634 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
33637 /* Return an rtx describing a return value of MODE as a PARALLEL
33638 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
33639 stride REG_STRIDE. */
33642 rs6000_parallel_return (machine_mode mode
,
33643 int n_elts
, machine_mode elt_mode
,
33644 unsigned int regno
, unsigned int reg_stride
)
33646 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
33649 for (i
= 0; i
< n_elts
; i
++)
33651 rtx r
= gen_rtx_REG (elt_mode
, regno
);
33652 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
33653 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
33654 regno
+= reg_stride
;
33660 /* Target hook for TARGET_FUNCTION_VALUE.
33662 On the SPE, both FPs and vectors are returned in r3.
33664 On RS/6000 an integer value is in r3 and a floating-point value is in
33665 fp1, unless -msoft-float. */
33668 rs6000_function_value (const_tree valtype
,
33669 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
33670 bool outgoing ATTRIBUTE_UNUSED
)
33673 unsigned int regno
;
33674 machine_mode elt_mode
;
33677 /* Special handling for structs in darwin64. */
33679 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
33681 CUMULATIVE_ARGS valcum
;
33685 valcum
.fregno
= FP_ARG_MIN_REG
;
33686 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
33687 /* Do a trial code generation as if this were going to be passed as
33688 an argument; if any part goes in memory, we return NULL. */
33689 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
33692 /* Otherwise fall through to standard ABI rules. */
33695 mode
= TYPE_MODE (valtype
);
33697 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
33698 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
33700 int first_reg
, n_regs
;
33702 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
33704 /* _Decimal128 must use even/odd register pairs. */
33705 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
33706 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
33710 first_reg
= ALTIVEC_ARG_RETURN
;
33714 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
33717 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
33718 if (TARGET_32BIT
&& TARGET_POWERPC64
)
33727 int count
= GET_MODE_SIZE (mode
) / 4;
33728 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
33731 if ((INTEGRAL_TYPE_P (valtype
)
33732 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
33733 || POINTER_TYPE_P (valtype
))
33734 mode
= TARGET_32BIT
? SImode
: DImode
;
33736 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
33737 /* _Decimal128 must use an even/odd register pair. */
33738 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
33739 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
33740 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
33741 regno
= FP_ARG_RETURN
;
33742 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
33743 && targetm
.calls
.split_complex_arg
)
33744 return rs6000_complex_function_value (mode
);
33745 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
33746 return register is used in both cases, and we won't see V2DImode/V2DFmode
33747 for pure altivec, combine the two cases. */
33748 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
33749 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
33750 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
33751 regno
= ALTIVEC_ARG_RETURN
;
33752 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
33753 && (mode
== DFmode
|| mode
== DCmode
33754 || FLOAT128_IBM_P (mode
) || mode
== TCmode
))
33755 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
33757 regno
= GP_ARG_RETURN
;
33759 return gen_rtx_REG (mode
, regno
);
33762 /* Define how to find the value returned by a library function
33763 assuming the value has mode MODE. */
33765 rs6000_libcall_value (machine_mode mode
)
33767 unsigned int regno
;
33769 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
33770 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
33771 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
33773 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
33774 /* _Decimal128 must use an even/odd register pair. */
33775 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
33776 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
)
33777 && TARGET_HARD_FLOAT
&& TARGET_FPRS
33778 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
33779 regno
= FP_ARG_RETURN
;
33780 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
33781 return register is used in both cases, and we won't see V2DImode/V2DFmode
33782 for pure altivec, combine the two cases. */
33783 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
33784 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
33785 regno
= ALTIVEC_ARG_RETURN
;
33786 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
33787 return rs6000_complex_function_value (mode
);
33788 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
33789 && (mode
== DFmode
|| mode
== DCmode
33790 || FLOAT128_IBM_P (mode
) || mode
== TCmode
))
33791 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
33793 regno
= GP_ARG_RETURN
;
33795 return gen_rtx_REG (mode
, regno
);
33799 /* Return true if we use LRA instead of reload pass. */
33801 rs6000_lra_p (void)
33803 return rs6000_lra_flag
;
33806 /* Given FROM and TO register numbers, say whether this elimination is allowed.
33807 Frame pointer elimination is automatically handled.
33809 For the RS/6000, if frame pointer elimination is being done, we would like
33810 to convert ap into fp, not sp.
33812 We need r30 if -mminimal-toc was specified, and there are constant pool
33816 rs6000_can_eliminate (const int from
, const int to
)
33818 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
33819 ? ! frame_pointer_needed
33820 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
33821 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
33825 /* Define the offset between two registers, FROM to be eliminated and its
33826 replacement TO, at the start of a routine. */
33828 rs6000_initial_elimination_offset (int from
, int to
)
33830 rs6000_stack_t
*info
= rs6000_stack_info ();
33831 HOST_WIDE_INT offset
;
33833 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
33834 offset
= info
->push_p
? 0 : -info
->total_size
;
33835 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
33837 offset
= info
->push_p
? 0 : -info
->total_size
;
33838 if (FRAME_GROWS_DOWNWARD
)
33839 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
33841 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
33842 offset
= FRAME_GROWS_DOWNWARD
33843 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
33845 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
33846 offset
= info
->total_size
;
33847 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
33848 offset
= info
->push_p
? info
->total_size
: 0;
33849 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
33852 gcc_unreachable ();
33858 rs6000_dwarf_register_span (rtx reg
)
33862 unsigned regno
= REGNO (reg
);
33863 machine_mode mode
= GET_MODE (reg
);
33867 && (SPE_VECTOR_MODE (GET_MODE (reg
))
33868 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
33869 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
33874 regno
= REGNO (reg
);
33876 /* The duality of the SPE register size wreaks all kinds of havoc.
33877 This is a way of distinguishing r0 in 32-bits from r0 in
33879 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
33880 gcc_assert (words
<= 4);
33881 for (i
= 0; i
< words
; i
++, regno
++)
33883 if (BYTES_BIG_ENDIAN
)
33885 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
33886 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
33890 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
33891 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
33895 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
33898 /* Fill in sizes for SPE register high parts in table used by unwinder. */
33901 rs6000_init_dwarf_reg_sizes_extra (tree address
)
33906 machine_mode mode
= TYPE_MODE (char_type_node
);
33907 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
33908 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
33909 rtx value
= gen_int_mode (4, mode
);
33911 for (i
= FIRST_SPE_HIGH_REGNO
; i
< LAST_SPE_HIGH_REGNO
+1; i
++)
33913 int column
= DWARF_REG_TO_UNWIND_COLUMN
33914 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
33915 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
33917 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
33921 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
33924 machine_mode mode
= TYPE_MODE (char_type_node
);
33925 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
33926 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
33927 rtx value
= gen_int_mode (16, mode
);
33929 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
33930 The unwinder still needs to know the size of Altivec registers. */
33932 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
33934 int column
= DWARF_REG_TO_UNWIND_COLUMN
33935 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
33936 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
33938 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
33943 /* Map internal gcc register numbers to debug format register numbers.
33944 FORMAT specifies the type of debug register number to use:
33945 0 -- debug information, except for frame-related sections
33946 1 -- DWARF .debug_frame section
33947 2 -- DWARF .eh_frame section */
33950 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
33952 /* We never use the GCC internal number for SPE high registers.
33953 Those are mapped to the 1200..1231 range for all debug formats. */
33954 if (SPE_HIGH_REGNO_P (regno
))
33955 return regno
- FIRST_SPE_HIGH_REGNO
+ 1200;
33957 /* Except for the above, we use the internal number for non-DWARF
33958 debug information, and also for .eh_frame. */
33959 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
33962 /* On some platforms, we use the standard DWARF register
33963 numbering for .debug_info and .debug_frame. */
33964 #ifdef RS6000_USE_DWARF_NUMBERING
33967 if (regno
== LR_REGNO
)
33969 if (regno
== CTR_REGNO
)
33971 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
33972 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
33973 The actual code emitted saves the whole of CR, so we map CR2_REGNO
33974 to the DWARF reg for CR. */
33975 if (format
== 1 && regno
== CR2_REGNO
)
33977 if (CR_REGNO_P (regno
))
33978 return regno
- CR0_REGNO
+ 86;
33979 if (regno
== CA_REGNO
)
33980 return 101; /* XER */
33981 if (ALTIVEC_REGNO_P (regno
))
33982 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
33983 if (regno
== VRSAVE_REGNO
)
33985 if (regno
== VSCR_REGNO
)
33987 if (regno
== SPE_ACC_REGNO
)
33989 if (regno
== SPEFSCR_REGNO
)
33995 /* target hook eh_return_filter_mode */
33996 static machine_mode
33997 rs6000_eh_return_filter_mode (void)
33999 return TARGET_32BIT
? SImode
: word_mode
;
34002 /* Target hook for scalar_mode_supported_p. */
34004 rs6000_scalar_mode_supported_p (machine_mode mode
)
34006 /* -m32 does not support TImode. This is the default, from
34007 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
34008 same ABI as for -m32. But default_scalar_mode_supported_p allows
34009 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
34010 for -mpowerpc64. */
34011 if (TARGET_32BIT
&& mode
== TImode
)
34014 if (DECIMAL_FLOAT_MODE_P (mode
))
34015 return default_decimal_float_supported_p ();
34016 else if (TARGET_FLOAT128
&& (mode
== KFmode
|| mode
== IFmode
))
34019 return default_scalar_mode_supported_p (mode
);
34022 /* Target hook for vector_mode_supported_p. */
34024 rs6000_vector_mode_supported_p (machine_mode mode
)
34027 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
34030 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
34033 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
34034 128-bit, the compiler might try to widen IEEE 128-bit to IBM
34036 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
34043 /* Target hook for c_mode_for_suffix. */
34044 static machine_mode
34045 rs6000_c_mode_for_suffix (char suffix
)
34047 if (TARGET_FLOAT128
)
34049 if (suffix
== 'q' || suffix
== 'Q')
34050 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
34052 /* At the moment, we are not defining a suffix for IBM extended double.
34053 If/when the default for -mabi=ieeelongdouble is changed, and we want
34054 to support __ibm128 constants in legacy library code, we may need to
34055 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
34056 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
34057 __float80 constants. */
34063 /* Target hook for invalid_arg_for_unprototyped_fn. */
34064 static const char *
34065 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
34067 return (!rs6000_darwin64_abi
34069 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
34070 && (funcdecl
== NULL_TREE
34071 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
34072 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
34073 ? N_("AltiVec argument passed to unprototyped function")
34077 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
34078 setup by using __stack_chk_fail_local hidden function instead of
34079 calling __stack_chk_fail directly. Otherwise it is better to call
34080 __stack_chk_fail directly. */
34082 static tree ATTRIBUTE_UNUSED
34083 rs6000_stack_protect_fail (void)
34085 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
34086 ? default_hidden_stack_protect_fail ()
34087 : default_external_stack_protect_fail ();
34091 rs6000_final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
34092 int num_operands ATTRIBUTE_UNUSED
)
34094 if (rs6000_warn_cell_microcode
)
34097 int insn_code_number
= recog_memoized (insn
);
34098 location_t location
= INSN_LOCATION (insn
);
34100 /* Punt on insns we cannot recognize. */
34101 if (insn_code_number
< 0)
34104 temp
= get_insn_template (insn_code_number
, insn
);
34106 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
34107 warning_at (location
, OPT_mwarn_cell_microcode
,
34108 "emitting microcode insn %s\t[%s] #%d",
34109 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
34110 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
34111 warning_at (location
, OPT_mwarn_cell_microcode
,
34112 "emitting conditional microcode insn %s\t[%s] #%d",
34113 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
34117 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
34120 static unsigned HOST_WIDE_INT
34121 rs6000_asan_shadow_offset (void)
34123 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
34127 /* Mask options that we want to support inside of attribute((target)) and
34128 #pragma GCC target operations. Note, we do not include things like
34129 64/32-bit, endianess, hard/soft floating point, etc. that would have
34130 different calling sequences. */
34132 struct rs6000_opt_mask
{
34133 const char *name
; /* option name */
34134 HOST_WIDE_INT mask
; /* mask to set */
34135 bool invert
; /* invert sense of mask */
34136 bool valid_target
; /* option is a target option */
34139 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
34141 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
34142 { "cmpb", OPTION_MASK_CMPB
, false, true },
34143 { "crypto", OPTION_MASK_CRYPTO
, false, true },
34144 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
34145 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
34146 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
34148 { "float128", OPTION_MASK_FLOAT128
, false, true },
34149 { "float128-hardware", OPTION_MASK_FLOAT128_HW
, false, true },
34150 { "fprnd", OPTION_MASK_FPRND
, false, true },
34151 { "hard-dfp", OPTION_MASK_DFP
, false, true },
34152 { "htm", OPTION_MASK_HTM
, false, true },
34153 { "isel", OPTION_MASK_ISEL
, false, true },
34154 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
34155 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
34156 { "modulo", OPTION_MASK_MODULO
, false, true },
34157 { "mulhw", OPTION_MASK_MULHW
, false, true },
34158 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
34159 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
34160 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
34161 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
34162 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
34163 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
34164 { "power9-dform", OPTION_MASK_P9_DFORM
, false, true },
34165 { "power9-fusion", OPTION_MASK_P9_FUSION
, false, true },
34166 { "power9-minmax", OPTION_MASK_P9_MINMAX
, false, true },
34167 { "power9-vector", OPTION_MASK_P9_VECTOR
, false, true },
34168 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
34169 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
34170 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
34171 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
34172 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
34173 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
34174 { "string", OPTION_MASK_STRING
, false, true },
34175 { "toc-fusion", OPTION_MASK_TOC_FUSION
, false, true },
34176 { "update", OPTION_MASK_NO_UPDATE
, true , true },
34177 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, true },
34178 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, true },
34179 { "vsx", OPTION_MASK_VSX
, false, true },
34180 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
34181 #ifdef OPTION_MASK_64BIT
34183 { "aix64", OPTION_MASK_64BIT
, false, false },
34184 { "aix32", OPTION_MASK_64BIT
, true, false },
34186 { "64", OPTION_MASK_64BIT
, false, false },
34187 { "32", OPTION_MASK_64BIT
, true, false },
34190 #ifdef OPTION_MASK_EABI
34191 { "eabi", OPTION_MASK_EABI
, false, false },
34193 #ifdef OPTION_MASK_LITTLE_ENDIAN
34194 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
34195 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
34197 #ifdef OPTION_MASK_RELOCATABLE
34198 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
34200 #ifdef OPTION_MASK_STRICT_ALIGN
34201 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
34203 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
34204 { "string", OPTION_MASK_STRING
, false, false },
34207 /* Builtin mask mapping for printing the flags. */
34208 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
34210 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
34211 { "vsx", RS6000_BTM_VSX
, false, false },
34212 { "spe", RS6000_BTM_SPE
, false, false },
34213 { "paired", RS6000_BTM_PAIRED
, false, false },
34214 { "fre", RS6000_BTM_FRE
, false, false },
34215 { "fres", RS6000_BTM_FRES
, false, false },
34216 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
34217 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
34218 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
34219 { "cell", RS6000_BTM_CELL
, false, false },
34220 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
34221 { "crypto", RS6000_BTM_CRYPTO
, false, false },
34222 { "htm", RS6000_BTM_HTM
, false, false },
34223 { "hard-dfp", RS6000_BTM_DFP
, false, false },
34224 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
34225 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
34228 /* Option variables that we want to support inside attribute((target)) and
34229 #pragma GCC target operations. */
34231 struct rs6000_opt_var
{
34232 const char *name
; /* option name */
34233 size_t global_offset
; /* offset of the option in global_options. */
34234 size_t target_offset
; /* offset of the option in target options. */
34237 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
34240 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
34241 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
34242 { "avoid-indexed-addresses",
34243 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
34244 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
34246 offsetof (struct gcc_options
, x_rs6000_paired_float
),
34247 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
34249 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
34250 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
34251 { "optimize-swaps",
34252 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
34253 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
34254 { "allow-movmisalign",
34255 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
34256 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
34257 { "allow-df-permute",
34258 offsetof (struct gcc_options
, x_TARGET_ALLOW_DF_PERMUTE
),
34259 offsetof (struct cl_target_option
, x_TARGET_ALLOW_DF_PERMUTE
), },
34261 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
34262 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
34264 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
34265 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
34266 { "align-branch-targets",
34267 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
34268 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
34269 { "vectorize-builtins",
34270 offsetof (struct gcc_options
, x_TARGET_VECTORIZE_BUILTINS
),
34271 offsetof (struct cl_target_option
, x_TARGET_VECTORIZE_BUILTINS
), },
34273 offsetof (struct gcc_options
, x_tls_markers
),
34274 offsetof (struct cl_target_option
, x_tls_markers
), },
34276 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
34277 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
34279 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
34280 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
34281 { "gen-cell-microcode",
34282 offsetof (struct gcc_options
, x_rs6000_gen_cell_microcode
),
34283 offsetof (struct cl_target_option
, x_rs6000_gen_cell_microcode
), },
34284 { "warn-cell-microcode",
34285 offsetof (struct gcc_options
, x_rs6000_warn_cell_microcode
),
34286 offsetof (struct cl_target_option
, x_rs6000_warn_cell_microcode
), },
34289 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
34290 parsing. Return true if there were no errors. */
34293 rs6000_inner_target_options (tree args
, bool attr_p
)
34297 if (args
== NULL_TREE
)
34300 else if (TREE_CODE (args
) == STRING_CST
)
34302 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
34305 while ((q
= strtok (p
, ",")) != NULL
)
34307 bool error_p
= false;
34308 bool not_valid_p
= false;
34309 const char *cpu_opt
= NULL
;
34312 if (strncmp (q
, "cpu=", 4) == 0)
34314 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
34315 if (cpu_index
>= 0)
34316 rs6000_cpu_index
= cpu_index
;
34323 else if (strncmp (q
, "tune=", 5) == 0)
34325 int tune_index
= rs6000_cpu_name_lookup (q
+5);
34326 if (tune_index
>= 0)
34327 rs6000_tune_index
= tune_index
;
34337 bool invert
= false;
34341 if (strncmp (r
, "no-", 3) == 0)
34347 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
34348 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
34350 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
34352 if (!rs6000_opt_masks
[i
].valid_target
)
34353 not_valid_p
= true;
34357 rs6000_isa_flags_explicit
|= mask
;
34359 /* VSX needs altivec, so -mvsx automagically sets
34360 altivec and disables -mavoid-indexed-addresses. */
34363 if (mask
== OPTION_MASK_VSX
)
34365 mask
|= OPTION_MASK_ALTIVEC
;
34366 TARGET_AVOID_XFORM
= 0;
34370 if (rs6000_opt_masks
[i
].invert
)
34374 rs6000_isa_flags
&= ~mask
;
34376 rs6000_isa_flags
|= mask
;
34381 if (error_p
&& !not_valid_p
)
34383 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
34384 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
34386 size_t j
= rs6000_opt_vars
[i
].global_offset
;
34387 *((int *) ((char *)&global_options
+ j
)) = !invert
;
34389 not_valid_p
= false;
34397 const char *eprefix
, *esuffix
;
34402 eprefix
= "__attribute__((__target__(";
34407 eprefix
= "#pragma GCC target ";
34412 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
34414 else if (not_valid_p
)
34415 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
34417 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
34422 else if (TREE_CODE (args
) == TREE_LIST
)
34426 tree value
= TREE_VALUE (args
);
34429 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
34433 args
= TREE_CHAIN (args
);
34435 while (args
!= NULL_TREE
);
34439 gcc_unreachable ();
34444 /* Print out the target options as a list for -mdebug=target. */
34447 rs6000_debug_target_options (tree args
, const char *prefix
)
34449 if (args
== NULL_TREE
)
34450 fprintf (stderr
, "%s<NULL>", prefix
);
34452 else if (TREE_CODE (args
) == STRING_CST
)
34454 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
34457 while ((q
= strtok (p
, ",")) != NULL
)
34460 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
34465 else if (TREE_CODE (args
) == TREE_LIST
)
34469 tree value
= TREE_VALUE (args
);
34472 rs6000_debug_target_options (value
, prefix
);
34475 args
= TREE_CHAIN (args
);
34477 while (args
!= NULL_TREE
);
34481 gcc_unreachable ();
34487 /* Hook to validate attribute((target("..."))). */
34490 rs6000_valid_attribute_p (tree fndecl
,
34491 tree
ARG_UNUSED (name
),
34495 struct cl_target_option cur_target
;
34497 tree old_optimize
= build_optimization_node (&global_options
);
34498 tree new_target
, new_optimize
;
34499 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
34501 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
34503 if (TARGET_DEBUG_TARGET
)
34505 tree tname
= DECL_NAME (fndecl
);
34506 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
34508 fprintf (stderr
, "function: %.*s\n",
34509 (int) IDENTIFIER_LENGTH (tname
),
34510 IDENTIFIER_POINTER (tname
));
34512 fprintf (stderr
, "function: unknown\n");
34514 fprintf (stderr
, "args:");
34515 rs6000_debug_target_options (args
, " ");
34516 fprintf (stderr
, "\n");
34519 fprintf (stderr
, "flags: 0x%x\n", flags
);
34521 fprintf (stderr
, "--------------------\n");
34524 old_optimize
= build_optimization_node (&global_options
);
34525 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
34527 /* If the function changed the optimization levels as well as setting target
34528 options, start with the optimizations specified. */
34529 if (func_optimize
&& func_optimize
!= old_optimize
)
34530 cl_optimization_restore (&global_options
,
34531 TREE_OPTIMIZATION (func_optimize
));
34533 /* The target attributes may also change some optimization flags, so update
34534 the optimization options if necessary. */
34535 cl_target_option_save (&cur_target
, &global_options
);
34536 rs6000_cpu_index
= rs6000_tune_index
= -1;
34537 ret
= rs6000_inner_target_options (args
, true);
34539 /* Set up any additional state. */
34542 ret
= rs6000_option_override_internal (false);
34543 new_target
= build_target_option_node (&global_options
);
34548 new_optimize
= build_optimization_node (&global_options
);
34555 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
34557 if (old_optimize
!= new_optimize
)
34558 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
34561 cl_target_option_restore (&global_options
, &cur_target
);
34563 if (old_optimize
!= new_optimize
)
34564 cl_optimization_restore (&global_options
,
34565 TREE_OPTIMIZATION (old_optimize
));
34571 /* Hook to validate the current #pragma GCC target and set the state, and
34572 update the macros based on what was changed. If ARGS is NULL, then
34573 POP_TARGET is used to reset the options. */
34576 rs6000_pragma_target_parse (tree args
, tree pop_target
)
34578 tree prev_tree
= build_target_option_node (&global_options
);
34580 struct cl_target_option
*prev_opt
, *cur_opt
;
34581 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
34582 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
34584 if (TARGET_DEBUG_TARGET
)
34586 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
34587 fprintf (stderr
, "args:");
34588 rs6000_debug_target_options (args
, " ");
34589 fprintf (stderr
, "\n");
34593 fprintf (stderr
, "pop_target:\n");
34594 debug_tree (pop_target
);
34597 fprintf (stderr
, "pop_target: <NULL>\n");
34599 fprintf (stderr
, "--------------------\n");
34604 cur_tree
= ((pop_target
)
34606 : target_option_default_node
);
34607 cl_target_option_restore (&global_options
,
34608 TREE_TARGET_OPTION (cur_tree
));
34612 rs6000_cpu_index
= rs6000_tune_index
= -1;
34613 if (!rs6000_inner_target_options (args
, false)
34614 || !rs6000_option_override_internal (false)
34615 || (cur_tree
= build_target_option_node (&global_options
))
34618 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
34619 fprintf (stderr
, "invalid pragma\n");
34625 target_option_current_node
= cur_tree
;
34627 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
34628 change the macros that are defined. */
34629 if (rs6000_target_modify_macros_ptr
)
34631 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
34632 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
34633 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
34635 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
34636 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
34637 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
34639 diff_bumask
= (prev_bumask
^ cur_bumask
);
34640 diff_flags
= (prev_flags
^ cur_flags
);
34642 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
34644 /* Delete old macros. */
34645 rs6000_target_modify_macros_ptr (false,
34646 prev_flags
& diff_flags
,
34647 prev_bumask
& diff_bumask
);
34649 /* Define new macros. */
34650 rs6000_target_modify_macros_ptr (true,
34651 cur_flags
& diff_flags
,
34652 cur_bumask
& diff_bumask
);
34660 /* Remember the last target of rs6000_set_current_function. */
34661 static GTY(()) tree rs6000_previous_fndecl
;
34663 /* Establish appropriate back-end context for processing the function
34664 FNDECL. The argument might be NULL to indicate processing at top
34665 level, outside of any function scope. */
34667 rs6000_set_current_function (tree fndecl
)
34669 tree old_tree
= (rs6000_previous_fndecl
34670 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
34673 tree new_tree
= (fndecl
34674 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
34677 if (TARGET_DEBUG_TARGET
)
34679 bool print_final
= false;
34680 fprintf (stderr
, "\n==================== rs6000_set_current_function");
34683 fprintf (stderr
, ", fndecl %s (%p)",
34684 (DECL_NAME (fndecl
)
34685 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
34686 : "<unknown>"), (void *)fndecl
);
34688 if (rs6000_previous_fndecl
)
34689 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
34691 fprintf (stderr
, "\n");
34694 fprintf (stderr
, "\nnew fndecl target specific options:\n");
34695 debug_tree (new_tree
);
34696 print_final
= true;
34701 fprintf (stderr
, "\nold fndecl target specific options:\n");
34702 debug_tree (old_tree
);
34703 print_final
= true;
34707 fprintf (stderr
, "--------------------\n");
34710 /* Only change the context if the function changes. This hook is called
34711 several times in the course of compiling a function, and we don't want to
34712 slow things down too much or call target_reinit when it isn't safe. */
34713 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
34715 rs6000_previous_fndecl
= fndecl
;
34716 if (old_tree
== new_tree
)
34719 else if (new_tree
&& new_tree
!= target_option_default_node
)
34721 cl_target_option_restore (&global_options
,
34722 TREE_TARGET_OPTION (new_tree
));
34723 if (TREE_TARGET_GLOBALS (new_tree
))
34724 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
34726 TREE_TARGET_GLOBALS (new_tree
)
34727 = save_target_globals_default_opts ();
34730 else if (old_tree
&& old_tree
!= target_option_default_node
)
34732 new_tree
= target_option_current_node
;
34733 cl_target_option_restore (&global_options
,
34734 TREE_TARGET_OPTION (new_tree
));
34735 if (TREE_TARGET_GLOBALS (new_tree
))
34736 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
34737 else if (new_tree
== target_option_default_node
)
34738 restore_target_globals (&default_target_globals
);
34740 TREE_TARGET_GLOBALS (new_tree
)
34741 = save_target_globals_default_opts ();
34747 /* Save the current options */
34750 rs6000_function_specific_save (struct cl_target_option
*ptr
,
34751 struct gcc_options
*opts
)
34753 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
34754 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
34757 /* Restore the current options */
34760 rs6000_function_specific_restore (struct gcc_options
*opts
,
34761 struct cl_target_option
*ptr
)
34764 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
34765 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
34766 (void) rs6000_option_override_internal (false);
34769 /* Print the current options */
34772 rs6000_function_specific_print (FILE *file
, int indent
,
34773 struct cl_target_option
*ptr
)
34775 rs6000_print_isa_options (file
, indent
, "Isa options set",
34776 ptr
->x_rs6000_isa_flags
);
34778 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
34779 ptr
->x_rs6000_isa_flags_explicit
);
34782 /* Helper function to print the current isa or misc options on a line. */
34785 rs6000_print_options_internal (FILE *file
,
34787 const char *string
,
34788 HOST_WIDE_INT flags
,
34789 const char *prefix
,
34790 const struct rs6000_opt_mask
*opts
,
34791 size_t num_elements
)
34794 size_t start_column
= 0;
34796 size_t max_column
= 76;
34797 const char *comma
= "";
34800 start_column
+= fprintf (file
, "%*s", indent
, "");
34804 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
34808 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
34810 /* Print the various mask options. */
34811 cur_column
= start_column
;
34812 for (i
= 0; i
< num_elements
; i
++)
34814 if ((flags
& opts
[i
].mask
) != 0)
34816 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
34817 size_t len
= (strlen (comma
)
34820 + strlen (rs6000_opt_masks
[i
].name
));
34823 if (cur_column
> max_column
)
34825 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
34826 cur_column
= start_column
+ len
;
34830 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
34831 rs6000_opt_masks
[i
].name
);
34832 flags
&= ~ opts
[i
].mask
;
34837 fputs ("\n", file
);
34840 /* Helper function to print the current isa options on a line. */
34843 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
34844 HOST_WIDE_INT flags
)
34846 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
34847 &rs6000_opt_masks
[0],
34848 ARRAY_SIZE (rs6000_opt_masks
));
34852 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
34853 HOST_WIDE_INT flags
)
34855 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
34856 &rs6000_builtin_mask_names
[0],
34857 ARRAY_SIZE (rs6000_builtin_mask_names
));
34861 /* Hook to determine if one function can safely inline another. */
34864 rs6000_can_inline_p (tree caller
, tree callee
)
34867 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
34868 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
34870 /* If callee has no option attributes, then it is ok to inline. */
34874 /* If caller has no option attributes, but callee does then it is not ok to
34876 else if (!caller_tree
)
34881 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
34882 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
34884 /* Callee's options should a subset of the caller's, i.e. a vsx function
34885 can inline an altivec function but a non-vsx function can't inline a
34887 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
34888 == callee_opts
->x_rs6000_isa_flags
)
34892 if (TARGET_DEBUG_TARGET
)
34893 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
34894 (DECL_NAME (caller
)
34895 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
34897 (DECL_NAME (callee
)
34898 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
34900 (ret
? "can" : "cannot"));
34905 /* Allocate a stack temp and fixup the address so it meets the particular
34906 memory requirements (either offetable or REG+REG addressing). */
34909 rs6000_allocate_stack_temp (machine_mode mode
,
34910 bool offsettable_p
,
34913 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
34914 rtx addr
= XEXP (stack
, 0);
34915 int strict_p
= (reload_in_progress
|| reload_completed
);
34917 if (!legitimate_indirect_address_p (addr
, strict_p
))
34920 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
34921 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
34923 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
34924 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
34930 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
34931 to such a form to deal with memory reference instructions like STFIWX that
34932 only take reg+reg addressing. */
34935 rs6000_address_for_fpconvert (rtx x
)
34937 int strict_p
= (reload_in_progress
|| reload_completed
);
34940 gcc_assert (MEM_P (x
));
34941 addr
= XEXP (x
, 0);
34942 if (! legitimate_indirect_address_p (addr
, strict_p
)
34943 && ! legitimate_indexed_address_p (addr
, strict_p
))
34945 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
34947 rtx reg
= XEXP (addr
, 0);
34948 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
34949 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
34950 gcc_assert (REG_P (reg
));
34951 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
34954 else if (GET_CODE (addr
) == PRE_MODIFY
)
34956 rtx reg
= XEXP (addr
, 0);
34957 rtx expr
= XEXP (addr
, 1);
34958 gcc_assert (REG_P (reg
));
34959 gcc_assert (GET_CODE (expr
) == PLUS
);
34960 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
34964 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
34970 /* Given a memory reference, if it is not in the form for altivec memory
34971 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
34972 convert to the altivec format. */
34975 rs6000_address_for_altivec (rtx x
)
34977 gcc_assert (MEM_P (x
));
34978 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
34980 rtx addr
= XEXP (x
, 0);
34981 int strict_p
= (reload_in_progress
|| reload_completed
);
34983 if (!legitimate_indexed_address_p (addr
, strict_p
)
34984 && !legitimate_indirect_address_p (addr
, strict_p
))
34985 addr
= copy_to_mode_reg (Pmode
, addr
);
34987 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
34988 x
= change_address (x
, GET_MODE (x
), addr
);
34994 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
34996 On the RS/6000, all integer constants are acceptable, most won't be valid
34997 for particular insns, though. Only easy FP constants are acceptable. */
35000 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
35002 if (TARGET_ELF
&& tls_referenced_p (x
))
35005 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
35006 || GET_MODE (x
) == VOIDmode
35007 || (TARGET_POWERPC64
&& mode
== DImode
)
35008 || easy_fp_constant (x
, mode
)
35009 || easy_vector_constant (x
, mode
));
35013 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
35016 chain_already_loaded (rtx_insn
*last
)
35018 for (; last
!= NULL
; last
= PREV_INSN (last
))
35020 if (NONJUMP_INSN_P (last
))
35022 rtx patt
= PATTERN (last
);
35024 if (GET_CODE (patt
) == SET
)
35026 rtx lhs
= XEXP (patt
, 0);
35028 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
35036 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
35039 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
35041 const bool direct_call_p
35042 = GET_CODE (func_desc
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (func_desc
);
35043 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
35044 rtx toc_load
= NULL_RTX
;
35045 rtx toc_restore
= NULL_RTX
;
35047 rtx abi_reg
= NULL_RTX
;
35052 /* Handle longcall attributes. */
35053 if (INTVAL (cookie
) & CALL_LONG
)
35054 func_desc
= rs6000_longcall_ref (func_desc
);
35056 /* Handle indirect calls. */
35057 if (GET_CODE (func_desc
) != SYMBOL_REF
35058 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
35060 /* Save the TOC into its reserved slot before the call,
35061 and prepare to restore it after the call. */
35062 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
35063 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
35064 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
35065 gen_rtx_PLUS (Pmode
, stack_ptr
,
35066 stack_toc_offset
));
35067 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
35068 gen_rtvec (1, stack_toc_offset
),
35070 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
35072 /* Can we optimize saving the TOC in the prologue or
35073 do we need to do it at every call? */
35074 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
35075 cfun
->machine
->save_toc_in_prologue
= true;
35078 MEM_VOLATILE_P (stack_toc_mem
) = 1;
35079 emit_move_insn (stack_toc_mem
, toc_reg
);
35082 if (DEFAULT_ABI
== ABI_ELFv2
)
35084 /* A function pointer in the ELFv2 ABI is just a plain address, but
35085 the ABI requires it to be loaded into r12 before the call. */
35086 func_addr
= gen_rtx_REG (Pmode
, 12);
35087 emit_move_insn (func_addr
, func_desc
);
35088 abi_reg
= func_addr
;
35092 /* A function pointer under AIX is a pointer to a data area whose
35093 first word contains the actual address of the function, whose
35094 second word contains a pointer to its TOC, and whose third word
35095 contains a value to place in the static chain register (r11).
35096 Note that if we load the static chain, our "trampoline" need
35097 not have any executable code. */
35099 /* Load up address of the actual function. */
35100 func_desc
= force_reg (Pmode
, func_desc
);
35101 func_addr
= gen_reg_rtx (Pmode
);
35102 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
35104 /* Prepare to load the TOC of the called function. Note that the
35105 TOC load must happen immediately before the actual call so
35106 that unwinding the TOC registers works correctly. See the
35107 comment in frob_update_context. */
35108 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
35109 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
35110 gen_rtx_PLUS (Pmode
, func_desc
,
35112 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
35114 /* If we have a static chain, load it up. But, if the call was
35115 originally direct, the 3rd word has not been written since no
35116 trampoline has been built, so we ought not to load it, lest we
35117 override a static chain value. */
35119 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
35120 && !chain_already_loaded (get_current_sequence ()->next
->last
))
35122 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
35123 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
35124 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
35125 gen_rtx_PLUS (Pmode
, func_desc
,
35127 emit_move_insn (sc_reg
, func_sc_mem
);
35134 /* Direct calls use the TOC: for local calls, the callee will
35135 assume the TOC register is set; for non-local calls, the
35136 PLT stub needs the TOC register. */
35138 func_addr
= func_desc
;
35141 /* Create the call. */
35142 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
35143 if (value
!= NULL_RTX
)
35144 call
[0] = gen_rtx_SET (value
, call
[0]);
35148 call
[n_call
++] = toc_load
;
35150 call
[n_call
++] = toc_restore
;
35152 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
35154 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
35155 insn
= emit_call_insn (insn
);
35157 /* Mention all registers defined by the ABI to hold information
35158 as uses in CALL_INSN_FUNCTION_USAGE. */
35160 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
35163 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
35166 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
35171 gcc_assert (INTVAL (cookie
) == 0);
35173 /* Create the call. */
35174 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
35175 if (value
!= NULL_RTX
)
35176 call
[0] = gen_rtx_SET (value
, call
[0]);
35178 call
[1] = simple_return_rtx
;
35180 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
35181 insn
= emit_call_insn (insn
);
35183 /* Note use of the TOC register. */
35184 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
35185 /* We need to also mark a use of the link register since the function we
35186 sibling-call to will use it to return to our caller. */
35187 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
35190 /* Return whether we need to always update the saved TOC pointer when we update
35191 the stack pointer. */
35194 rs6000_save_toc_in_prologue_p (void)
35196 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
35199 #ifdef HAVE_GAS_HIDDEN
35200 # define USE_HIDDEN_LINKONCE 1
35202 # define USE_HIDDEN_LINKONCE 0
35205 /* Fills in the label name that should be used for a 476 link stack thunk. */
35208 get_ppc476_thunk_name (char name
[32])
35210 gcc_assert (TARGET_LINK_STACK
);
35212 if (USE_HIDDEN_LINKONCE
)
35213 sprintf (name
, "__ppc476.get_thunk");
35215 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
35218 /* This function emits the simple thunk routine that is used to preserve
35219 the link stack on the 476 cpu. */
35221 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
35223 rs6000_code_end (void)
35228 if (!TARGET_LINK_STACK
)
35231 get_ppc476_thunk_name (name
);
35233 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
35234 build_function_type_list (void_type_node
, NULL_TREE
));
35235 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
35236 NULL_TREE
, void_type_node
);
35237 TREE_PUBLIC (decl
) = 1;
35238 TREE_STATIC (decl
) = 1;
35241 if (USE_HIDDEN_LINKONCE
)
35243 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
35244 targetm
.asm_out
.unique_section (decl
, 0);
35245 switch_to_section (get_named_section (decl
, NULL
, 0));
35246 DECL_WEAK (decl
) = 1;
35247 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
35248 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
35249 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
35250 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
35255 switch_to_section (text_section
);
35256 ASM_OUTPUT_LABEL (asm_out_file
, name
);
35259 DECL_INITIAL (decl
) = make_node (BLOCK
);
35260 current_function_decl
= decl
;
35261 allocate_struct_function (decl
, false);
35262 init_function_start (decl
);
35263 first_function_block_is_cold
= false;
35264 /* Make sure unwind info is emitted for the thunk if needed. */
35265 final_start_function (emit_barrier (), asm_out_file
, 1);
35267 fputs ("\tblr\n", asm_out_file
);
35269 final_end_function ();
35270 init_insn_lengths ();
35271 free_after_compilation (cfun
);
35273 current_function_decl
= NULL
;
35276 /* Add r30 to hard reg set if the prologue sets it up and it is not
35277 pic_offset_table_rtx. */
35280 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
35282 if (!TARGET_SINGLE_PIC_BASE
35284 && TARGET_MINIMAL_TOC
35285 && get_pool_size () != 0)
35286 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
35287 if (cfun
->machine
->split_stack_argp_used
)
35288 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
35292 /* Helper function for rs6000_split_logical to emit a logical instruction after
35293 spliting the operation to single GPR registers.
35295 DEST is the destination register.
35296 OP1 and OP2 are the input source registers.
35297 CODE is the base operation (AND, IOR, XOR, NOT).
35298 MODE is the machine mode.
35299 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
35300 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
35301 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
35304 rs6000_split_logical_inner (rtx dest
,
35307 enum rtx_code code
,
35309 bool complement_final_p
,
35310 bool complement_op1_p
,
35311 bool complement_op2_p
)
35315 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
35316 if (op2
&& GET_CODE (op2
) == CONST_INT
35317 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
35318 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
35320 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
35321 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
35323 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
35328 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
35332 else if (value
== mask
)
35334 if (!rtx_equal_p (dest
, op1
))
35335 emit_insn (gen_rtx_SET (dest
, op1
));
35340 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
35341 into separate ORI/ORIS or XORI/XORIS instrucitons. */
35342 else if (code
== IOR
|| code
== XOR
)
35346 if (!rtx_equal_p (dest
, op1
))
35347 emit_insn (gen_rtx_SET (dest
, op1
));
35353 if (code
== AND
&& mode
== SImode
35354 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
35356 emit_insn (gen_andsi3 (dest
, op1
, op2
));
35360 if (complement_op1_p
)
35361 op1
= gen_rtx_NOT (mode
, op1
);
35363 if (complement_op2_p
)
35364 op2
= gen_rtx_NOT (mode
, op2
);
35366 /* For canonical RTL, if only one arm is inverted it is the first. */
35367 if (!complement_op1_p
&& complement_op2_p
)
35368 std::swap (op1
, op2
);
35370 bool_rtx
= ((code
== NOT
)
35371 ? gen_rtx_NOT (mode
, op1
)
35372 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
35374 if (complement_final_p
)
35375 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
35377 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
35380 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
35381 operations are split immediately during RTL generation to allow for more
35382 optimizations of the AND/IOR/XOR.
35384 OPERANDS is an array containing the destination and two input operands.
35385 CODE is the base operation (AND, IOR, XOR, NOT).
35386 MODE is the machine mode.
35387 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
35388 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
35389 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
35390 CLOBBER_REG is either NULL or a scratch register of type CC to allow
35391 formation of the AND instructions. */
35394 rs6000_split_logical_di (rtx operands
[3],
35395 enum rtx_code code
,
35396 bool complement_final_p
,
35397 bool complement_op1_p
,
35398 bool complement_op2_p
)
35400 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
35401 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
35402 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
35403 enum hi_lo
{ hi
= 0, lo
= 1 };
35404 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
35407 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
35408 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
35409 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
35410 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
35413 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
35416 if (GET_CODE (operands
[2]) != CONST_INT
)
35418 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
35419 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
35423 HOST_WIDE_INT value
= INTVAL (operands
[2]);
35424 HOST_WIDE_INT value_hi_lo
[2];
35426 gcc_assert (!complement_final_p
);
35427 gcc_assert (!complement_op1_p
);
35428 gcc_assert (!complement_op2_p
);
35430 value_hi_lo
[hi
] = value
>> 32;
35431 value_hi_lo
[lo
] = value
& lower_32bits
;
35433 for (i
= 0; i
< 2; i
++)
35435 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
35437 if (sub_value
& sign_bit
)
35438 sub_value
|= upper_32bits
;
35440 op2_hi_lo
[i
] = GEN_INT (sub_value
);
35442 /* If this is an AND instruction, check to see if we need to load
35443 the value in a register. */
35444 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
35445 && !and_operand (op2_hi_lo
[i
], SImode
))
35446 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
35451 for (i
= 0; i
< 2; i
++)
35453 /* Split large IOR/XOR operations. */
35454 if ((code
== IOR
|| code
== XOR
)
35455 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
35456 && !complement_final_p
35457 && !complement_op1_p
35458 && !complement_op2_p
35459 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
35461 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
35462 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
35463 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
35464 rtx tmp
= gen_reg_rtx (SImode
);
35466 /* Make sure the constant is sign extended. */
35467 if ((hi_16bits
& sign_bit
) != 0)
35468 hi_16bits
|= upper_32bits
;
35470 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
35471 code
, SImode
, false, false, false);
35473 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
35474 code
, SImode
, false, false, false);
35477 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
35478 code
, SImode
, complement_final_p
,
35479 complement_op1_p
, complement_op2_p
);
35485 /* Split the insns that make up boolean operations operating on multiple GPR
35486 registers. The boolean MD patterns ensure that the inputs either are
35487 exactly the same as the output registers, or there is no overlap.
35489 OPERANDS is an array containing the destination and two input operands.
35490 CODE is the base operation (AND, IOR, XOR, NOT).
35491 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
35492 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
35493 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
35496 rs6000_split_logical (rtx operands
[3],
35497 enum rtx_code code
,
35498 bool complement_final_p
,
35499 bool complement_op1_p
,
35500 bool complement_op2_p
)
35502 machine_mode mode
= GET_MODE (operands
[0]);
35503 machine_mode sub_mode
;
35505 int sub_size
, regno0
, regno1
, nregs
, i
;
35507 /* If this is DImode, use the specialized version that can run before
35508 register allocation. */
35509 if (mode
== DImode
&& !TARGET_POWERPC64
)
35511 rs6000_split_logical_di (operands
, code
, complement_final_p
,
35512 complement_op1_p
, complement_op2_p
);
35518 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
35519 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
35520 sub_size
= GET_MODE_SIZE (sub_mode
);
35521 regno0
= REGNO (op0
);
35522 regno1
= REGNO (op1
);
35524 gcc_assert (reload_completed
);
35525 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
35526 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
35528 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
35529 gcc_assert (nregs
> 1);
35531 if (op2
&& REG_P (op2
))
35532 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
35534 for (i
= 0; i
< nregs
; i
++)
35536 int offset
= i
* sub_size
;
35537 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
35538 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
35539 rtx sub_op2
= ((code
== NOT
)
35541 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
35543 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
35544 complement_final_p
, complement_op1_p
,
35552 /* Return true if the peephole2 can combine a load involving a combination of
35553 an addis instruction and a load with an offset that can be fused together on
35557 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
35558 rtx addis_value
, /* addis value. */
35559 rtx target
, /* target register that is loaded. */
35560 rtx mem
) /* bottom part of the memory addr. */
35565 /* Validate arguments. */
35566 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
35569 if (!base_reg_operand (target
, GET_MODE (target
)))
35572 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
35575 /* Allow sign/zero extension. */
35576 if (GET_CODE (mem
) == ZERO_EXTEND
35577 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
35578 mem
= XEXP (mem
, 0);
35583 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
35586 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
35587 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
35590 /* Validate that the register used to load the high value is either the
35591 register being loaded, or we can safely replace its use.
35593 This function is only called from the peephole2 pass and we assume that
35594 there are 2 instructions in the peephole (addis and load), so we want to
35595 check if the target register was not used in the memory address and the
35596 register to hold the addis result is dead after the peephole. */
35597 if (REGNO (addis_reg
) != REGNO (target
))
35599 if (reg_mentioned_p (target
, mem
))
35602 if (!peep2_reg_dead_p (2, addis_reg
))
35605 /* If the target register being loaded is the stack pointer, we must
35606 avoid loading any other value into it, even temporarily. */
35607 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
35611 base_reg
= XEXP (addr
, 0);
35612 return REGNO (addis_reg
) == REGNO (base_reg
);
35615 /* During the peephole2 pass, adjust and expand the insns for a load fusion
35616 sequence. We adjust the addis register to use the target register. If the
35617 load sign extends, we adjust the code to do the zero extending load, and an
35618 explicit sign extension later since the fusion only covers zero extending
35622 operands[0] register set with addis (to be replaced with target)
35623 operands[1] value set via addis
35624 operands[2] target register being loaded
35625 operands[3] D-form memory reference using operands[0]. */
35628 expand_fusion_gpr_load (rtx
*operands
)
35630 rtx addis_value
= operands
[1];
35631 rtx target
= operands
[2];
35632 rtx orig_mem
= operands
[3];
35633 rtx new_addr
, new_mem
, orig_addr
, offset
;
35634 enum rtx_code plus_or_lo_sum
;
35635 machine_mode target_mode
= GET_MODE (target
);
35636 machine_mode extend_mode
= target_mode
;
35637 machine_mode ptr_mode
= Pmode
;
35638 enum rtx_code extend
= UNKNOWN
;
35640 if (GET_CODE (orig_mem
) == ZERO_EXTEND
35641 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
35643 extend
= GET_CODE (orig_mem
);
35644 orig_mem
= XEXP (orig_mem
, 0);
35645 target_mode
= GET_MODE (orig_mem
);
35648 gcc_assert (MEM_P (orig_mem
));
35650 orig_addr
= XEXP (orig_mem
, 0);
35651 plus_or_lo_sum
= GET_CODE (orig_addr
);
35652 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
35654 offset
= XEXP (orig_addr
, 1);
35655 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
35656 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
35658 if (extend
!= UNKNOWN
)
35659 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
35661 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
35662 UNSPEC_FUSION_GPR
);
35663 emit_insn (gen_rtx_SET (target
, new_mem
));
35665 if (extend
== SIGN_EXTEND
)
35667 int sub_off
= ((BYTES_BIG_ENDIAN
)
35668 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
35671 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
35673 emit_insn (gen_rtx_SET (target
,
35674 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
35680 /* Emit the addis instruction that will be part of a fused instruction
35684 emit_fusion_addis (rtx target
, rtx addis_value
, const char *comment
,
35685 const char *mode_name
)
35688 char insn_template
[80];
35689 const char *addis_str
= NULL
;
35690 const char *comment_str
= ASM_COMMENT_START
;
35692 if (*comment_str
== ' ')
35695 /* Emit the addis instruction. */
35696 fuse_ops
[0] = target
;
35697 if (satisfies_constraint_L (addis_value
))
35699 fuse_ops
[1] = addis_value
;
35700 addis_str
= "lis %0,%v1";
35703 else if (GET_CODE (addis_value
) == PLUS
)
35705 rtx op0
= XEXP (addis_value
, 0);
35706 rtx op1
= XEXP (addis_value
, 1);
35708 if (REG_P (op0
) && CONST_INT_P (op1
)
35709 && satisfies_constraint_L (op1
))
35713 addis_str
= "addis %0,%1,%v2";
35717 else if (GET_CODE (addis_value
) == HIGH
)
35719 rtx value
= XEXP (addis_value
, 0);
35720 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
35722 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
35723 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
35725 addis_str
= "addis %0,%2,%1@toc@ha";
35727 else if (TARGET_XCOFF
)
35728 addis_str
= "addis %0,%1@u(%2)";
35731 gcc_unreachable ();
35734 else if (GET_CODE (value
) == PLUS
)
35736 rtx op0
= XEXP (value
, 0);
35737 rtx op1
= XEXP (value
, 1);
35739 if (GET_CODE (op0
) == UNSPEC
35740 && XINT (op0
, 1) == UNSPEC_TOCREL
35741 && CONST_INT_P (op1
))
35743 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
35744 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
35747 addis_str
= "addis %0,%2,%1+%3@toc@ha";
35749 else if (TARGET_XCOFF
)
35750 addis_str
= "addis %0,%1+%3@u(%2)";
35753 gcc_unreachable ();
35757 else if (satisfies_constraint_L (value
))
35759 fuse_ops
[1] = value
;
35760 addis_str
= "lis %0,%v1";
35763 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
35765 fuse_ops
[1] = value
;
35766 addis_str
= "lis %0,%1@ha";
35771 fatal_insn ("Could not generate addis value for fusion", addis_value
);
35773 sprintf (insn_template
, "%s\t\t%s %s, type %s", addis_str
, comment_str
,
35774 comment
, mode_name
);
35775 output_asm_insn (insn_template
, fuse_ops
);
35778 /* Emit a D-form load or store instruction that is the second instruction
35779 of a fusion sequence. */
35782 emit_fusion_load_store (rtx load_store_reg
, rtx addis_reg
, rtx offset
,
35783 const char *insn_str
)
35786 char insn_template
[80];
35788 fuse_ops
[0] = load_store_reg
;
35789 fuse_ops
[1] = addis_reg
;
35791 if (CONST_INT_P (offset
) && satisfies_constraint_I (offset
))
35793 sprintf (insn_template
, "%s %%0,%%2(%%1)", insn_str
);
35794 fuse_ops
[2] = offset
;
35795 output_asm_insn (insn_template
, fuse_ops
);
35798 else if (GET_CODE (offset
) == UNSPEC
35799 && XINT (offset
, 1) == UNSPEC_TOCREL
)
35802 sprintf (insn_template
, "%s %%0,%%2@toc@l(%%1)", insn_str
);
35804 else if (TARGET_XCOFF
)
35805 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
35808 gcc_unreachable ();
35810 fuse_ops
[2] = XVECEXP (offset
, 0, 0);
35811 output_asm_insn (insn_template
, fuse_ops
);
35814 else if (GET_CODE (offset
) == PLUS
35815 && GET_CODE (XEXP (offset
, 0)) == UNSPEC
35816 && XINT (XEXP (offset
, 0), 1) == UNSPEC_TOCREL
35817 && CONST_INT_P (XEXP (offset
, 1)))
35819 rtx tocrel_unspec
= XEXP (offset
, 0);
35821 sprintf (insn_template
, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str
);
35823 else if (TARGET_XCOFF
)
35824 sprintf (insn_template
, "%s %%0,%%2+%%3@l(%%1)", insn_str
);
35827 gcc_unreachable ();
35829 fuse_ops
[2] = XVECEXP (tocrel_unspec
, 0, 0);
35830 fuse_ops
[3] = XEXP (offset
, 1);
35831 output_asm_insn (insn_template
, fuse_ops
);
35834 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (offset
))
35836 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
35838 fuse_ops
[2] = offset
;
35839 output_asm_insn (insn_template
, fuse_ops
);
35843 fatal_insn ("Unable to generate load/store offset for fusion", offset
);
35848 /* Wrap a TOC address that can be fused to indicate that special fusion
35849 processing is needed. */
35852 fusion_wrap_memory_address (rtx old_mem
)
35854 rtx old_addr
= XEXP (old_mem
, 0);
35855 rtvec v
= gen_rtvec (1, old_addr
);
35856 rtx new_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_FUSION_ADDIS
);
35857 return replace_equiv_address_nv (old_mem
, new_addr
, false);
35860 /* Given an address, convert it into the addis and load offset parts. Addresses
35861 created during the peephole2 process look like:
35862 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
35863 (unspec [(...)] UNSPEC_TOCREL))
35865 Addresses created via toc fusion look like:
35866 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
35869 fusion_split_address (rtx addr
, rtx
*p_hi
, rtx
*p_lo
)
35873 if (GET_CODE (addr
) == UNSPEC
&& XINT (addr
, 1) == UNSPEC_FUSION_ADDIS
)
35875 lo
= XVECEXP (addr
, 0, 0);
35876 hi
= gen_rtx_HIGH (Pmode
, lo
);
35878 else if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
35880 hi
= XEXP (addr
, 0);
35881 lo
= XEXP (addr
, 1);
35884 gcc_unreachable ();
35890 /* Return a string to fuse an addis instruction with a gpr load to the same
35891 register that we loaded up the addis instruction. The address that is used
35892 is the logical address that was formed during peephole2:
35893 (lo_sum (high) (low-part))
35895 Or the address is the TOC address that is wrapped before register allocation:
35896 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
35898 The code is complicated, so we call output_asm_insn directly, and just
35902 emit_fusion_gpr_load (rtx target
, rtx mem
)
35907 const char *load_str
= NULL
;
35908 const char *mode_name
= NULL
;
35911 if (GET_CODE (mem
) == ZERO_EXTEND
)
35912 mem
= XEXP (mem
, 0);
35914 gcc_assert (REG_P (target
) && MEM_P (mem
));
35916 addr
= XEXP (mem
, 0);
35917 fusion_split_address (addr
, &addis_value
, &load_offset
);
35919 /* Now emit the load instruction to the same register. */
35920 mode
= GET_MODE (mem
);
35924 mode_name
= "char";
35929 mode_name
= "short";
35935 mode_name
= (mode
== SFmode
) ? "float" : "int";
35941 gcc_assert (TARGET_POWERPC64
);
35942 mode_name
= (mode
== DFmode
) ? "double" : "long";
35947 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target
, mem
));
35950 /* Emit the addis instruction. */
35951 emit_fusion_addis (target
, addis_value
, "gpr load fusion", mode_name
);
35953 /* Emit the D-form load instruction. */
35954 emit_fusion_load_store (target
, target
, load_offset
, load_str
);
35960 /* Return true if the peephole2 can combine a load/store involving a
35961 combination of an addis instruction and the memory operation. This was
35962 added to the ISA 3.0 (power9) hardware. */
35965 fusion_p9_p (rtx addis_reg
, /* register set via addis. */
35966 rtx addis_value
, /* addis value. */
35967 rtx dest
, /* destination (memory or register). */
35968 rtx src
) /* source (register or memory). */
35970 rtx addr
, mem
, offset
;
35971 enum machine_mode mode
= GET_MODE (src
);
35973 /* Validate arguments. */
35974 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
35977 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
35980 /* Ignore extend operations that are part of the load. */
35981 if (GET_CODE (src
) == FLOAT_EXTEND
|| GET_CODE (src
) == ZERO_EXTEND
)
35982 src
= XEXP (src
, 0);
35984 /* Test for memory<-register or register<-memory. */
35985 if (fpr_reg_operand (src
, mode
) || int_reg_operand (src
, mode
))
35993 else if (MEM_P (src
))
35995 if (!fpr_reg_operand (dest
, mode
) && !int_reg_operand (dest
, mode
))
36004 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
36005 if (GET_CODE (addr
) == PLUS
)
36007 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
36010 return satisfies_constraint_I (XEXP (addr
, 1));
36013 else if (GET_CODE (addr
) == LO_SUM
)
36015 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
36018 offset
= XEXP (addr
, 1);
36019 if (TARGET_XCOFF
|| (TARGET_ELF
&& TARGET_POWERPC64
))
36020 return small_toc_ref (offset
, GET_MODE (offset
));
36022 else if (TARGET_ELF
&& !TARGET_POWERPC64
)
36023 return CONSTANT_P (offset
);
36029 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
36033 operands[0] register set with addis
36034 operands[1] value set via addis
36035 operands[2] target register being loaded
36036 operands[3] D-form memory reference using operands[0].
36038 This is similar to the fusion introduced with power8, except it scales to
36039 both loads/stores and does not require the result register to be the same as
36040 the base register. At the moment, we only do this if register set with addis
36044 expand_fusion_p9_load (rtx
*operands
)
36046 rtx tmp_reg
= operands
[0];
36047 rtx addis_value
= operands
[1];
36048 rtx target
= operands
[2];
36049 rtx orig_mem
= operands
[3];
36050 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
;
36051 enum rtx_code plus_or_lo_sum
;
36052 machine_mode target_mode
= GET_MODE (target
);
36053 machine_mode extend_mode
= target_mode
;
36054 machine_mode ptr_mode
= Pmode
;
36055 enum rtx_code extend
= UNKNOWN
;
36057 if (GET_CODE (orig_mem
) == FLOAT_EXTEND
|| GET_CODE (orig_mem
) == ZERO_EXTEND
)
36059 extend
= GET_CODE (orig_mem
);
36060 orig_mem
= XEXP (orig_mem
, 0);
36061 target_mode
= GET_MODE (orig_mem
);
36064 gcc_assert (MEM_P (orig_mem
));
36066 orig_addr
= XEXP (orig_mem
, 0);
36067 plus_or_lo_sum
= GET_CODE (orig_addr
);
36068 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
36070 offset
= XEXP (orig_addr
, 1);
36071 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
36072 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
36074 if (extend
!= UNKNOWN
)
36075 new_mem
= gen_rtx_fmt_e (extend
, extend_mode
, new_mem
);
36077 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
36080 set
= gen_rtx_SET (target
, new_mem
);
36081 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
36082 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
36088 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
36092 operands[0] register set with addis
36093 operands[1] value set via addis
36094 operands[2] target D-form memory being stored to
36095 operands[3] register being stored
36097 This is similar to the fusion introduced with power8, except it scales to
36098 both loads/stores and does not require the result register to be the same as
36099 the base register. At the moment, we only do this if register set with addis
36103 expand_fusion_p9_store (rtx
*operands
)
36105 rtx tmp_reg
= operands
[0];
36106 rtx addis_value
= operands
[1];
36107 rtx orig_mem
= operands
[2];
36108 rtx src
= operands
[3];
36109 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
, new_src
;
36110 enum rtx_code plus_or_lo_sum
;
36111 machine_mode target_mode
= GET_MODE (orig_mem
);
36112 machine_mode ptr_mode
= Pmode
;
36114 gcc_assert (MEM_P (orig_mem
));
36116 orig_addr
= XEXP (orig_mem
, 0);
36117 plus_or_lo_sum
= GET_CODE (orig_addr
);
36118 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
36120 offset
= XEXP (orig_addr
, 1);
36121 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
36122 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
36124 new_src
= gen_rtx_UNSPEC (target_mode
, gen_rtvec (1, src
),
36127 set
= gen_rtx_SET (new_mem
, new_src
);
36128 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
36129 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
36135 /* Return a string to fuse an addis instruction with a load using extended
36136 fusion. The address that is used is the logical address that was formed
36137 during peephole2: (lo_sum (high) (low-part))
36139 The code is complicated, so we call output_asm_insn directly, and just
36143 emit_fusion_p9_load (rtx reg
, rtx mem
, rtx tmp_reg
)
36145 enum machine_mode mode
= GET_MODE (reg
);
36149 const char *load_string
;
36152 if (GET_CODE (mem
) == FLOAT_EXTEND
|| GET_CODE (mem
) == ZERO_EXTEND
)
36154 mem
= XEXP (mem
, 0);
36155 mode
= GET_MODE (mem
);
36158 if (GET_CODE (reg
) == SUBREG
)
36160 gcc_assert (SUBREG_BYTE (reg
) == 0);
36161 reg
= SUBREG_REG (reg
);
36165 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg
);
36168 if (FP_REGNO_P (r
))
36170 if (mode
== SFmode
)
36171 load_string
= "lfs";
36172 else if (mode
== DFmode
|| mode
== DImode
)
36173 load_string
= "lfd";
36175 gcc_unreachable ();
36177 else if (INT_REGNO_P (r
))
36182 load_string
= "lbz";
36185 load_string
= "lhz";
36189 load_string
= "lwz";
36193 if (!TARGET_POWERPC64
)
36194 gcc_unreachable ();
36195 load_string
= "ld";
36198 gcc_unreachable ();
36202 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg
);
36205 fatal_insn ("emit_fusion_p9_load not MEM", mem
);
36207 addr
= XEXP (mem
, 0);
36208 fusion_split_address (addr
, &hi
, &lo
);
36210 /* Emit the addis instruction. */
36211 emit_fusion_addis (tmp_reg
, hi
, "power9 load fusion", GET_MODE_NAME (mode
));
36213 /* Emit the D-form load instruction. */
36214 emit_fusion_load_store (reg
, tmp_reg
, lo
, load_string
);
36219 /* Return a string to fuse an addis instruction with a store using extended
36220 fusion. The address that is used is the logical address that was formed
36221 during peephole2: (lo_sum (high) (low-part))
36223 The code is complicated, so we call output_asm_insn directly, and just
36227 emit_fusion_p9_store (rtx mem
, rtx reg
, rtx tmp_reg
)
36229 enum machine_mode mode
= GET_MODE (reg
);
36233 const char *store_string
;
36236 if (GET_CODE (reg
) == SUBREG
)
36238 gcc_assert (SUBREG_BYTE (reg
) == 0);
36239 reg
= SUBREG_REG (reg
);
36243 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg
);
36246 if (FP_REGNO_P (r
))
36248 if (mode
== SFmode
)
36249 store_string
= "stfs";
36250 else if (mode
== DFmode
)
36251 store_string
= "stfd";
36253 gcc_unreachable ();
36255 else if (INT_REGNO_P (r
))
36260 store_string
= "stb";
36263 store_string
= "sth";
36267 store_string
= "stw";
36271 if (!TARGET_POWERPC64
)
36272 gcc_unreachable ();
36273 store_string
= "std";
36276 gcc_unreachable ();
36280 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg
);
36283 fatal_insn ("emit_fusion_p9_store not MEM", mem
);
36285 addr
= XEXP (mem
, 0);
36286 fusion_split_address (addr
, &hi
, &lo
);
36288 /* Emit the addis instruction. */
36289 emit_fusion_addis (tmp_reg
, hi
, "power9 store fusion", GET_MODE_NAME (mode
));
36291 /* Emit the D-form load instruction. */
36292 emit_fusion_load_store (reg
, tmp_reg
, lo
, store_string
);
36298 /* Analyze vector computations and remove unnecessary doubleword
36299 swaps (xxswapdi instructions). This pass is performed only
36300 for little-endian VSX code generation.
36302 For this specific case, loads and stores of 4x32 and 2x64 vectors
36303 are inefficient. These are implemented using the lvx2dx and
36304 stvx2dx instructions, which invert the order of doublewords in
36305 a vector register. Thus the code generation inserts an xxswapdi
36306 after each such load, and prior to each such store. (For spill
36307 code after register assignment, an additional xxswapdi is inserted
36308 following each store in order to return a hard register to its
36311 The extra xxswapdi instructions reduce performance. This can be
36312 particularly bad for vectorized code. The purpose of this pass
36313 is to reduce the number of xxswapdi instructions required for
36316 The primary insight is that much code that operates on vectors
36317 does not care about the relative order of elements in a register,
36318 so long as the correct memory order is preserved. If we have
36319 a computation where all input values are provided by lvxd2x/xxswapdi
36320 sequences, all outputs are stored using xxswapdi/stvxd2x sequences,
36321 and all intermediate computations are pure SIMD (independent of
36322 element order), then all the xxswapdi's associated with the loads
36323 and stores may be removed.
36325 This pass uses some of the infrastructure and logical ideas from
36326 the "web" pass in web.c. We create maximal webs of computations
36327 fitting the description above using union-find. Each such web is
36328 then optimized by removing its unnecessary xxswapdi instructions.
36330 The pass is placed prior to global optimization so that we can
36331 perform the optimization in the safest and simplest way possible;
36332 that is, by replacing each xxswapdi insn with a register copy insn.
36333 Subsequent forward propagation will remove copies where possible.
36335 There are some operations sensitive to element order for which we
36336 can still allow the operation, provided we modify those operations.
36337 These include CONST_VECTORs, for which we must swap the first and
36338 second halves of the constant vector; and SUBREGs, for which we
36339 must adjust the byte offset to account for the swapped doublewords.
36340 A remaining opportunity would be non-immediate-form splats, for
36341 which we should adjust the selected lane of the input. We should
36342 also make code generation adjustments for sum-across operations,
36343 since this is a common vectorizer reduction.
36345 Because we run prior to the first split, we can see loads and stores
36346 here that match *vsx_le_perm_{load,store}_<mode>. These are vanilla
36347 vector loads and stores that have not yet been split into a permuting
36348 load/store and a swap. (One way this can happen is with a builtin
36349 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
36350 than deleting a swap, we convert the load/store into a permuting
36351 load/store (which effectively removes the swap). */
36353 /* Notes on Permutes
36355 We do not currently handle computations that contain permutes. There
36356 is a general transformation that can be performed correctly, but it
36357 may introduce more expensive code than it replaces. To handle these
36358 would require a cost model to determine when to perform the optimization.
36359 This commentary records how this could be done if desired.
36361 The most general permute is something like this (example for V16QI):
36363 (vec_select:V16QI (vec_concat:V32QI (op1:V16QI) (op2:V16QI))
36364 (parallel [(const_int a0) (const_int a1)
36366 (const_int a14) (const_int a15)]))
36368 where a0,...,a15 are in [0,31] and select elements from op1 and op2
36369 to produce in the result.
36371 Regardless of mode, we can convert the PARALLEL to a mask of 16
36372 byte-element selectors. Let's call this M, with M[i] representing
36373 the ith byte-element selector value. Then if we swap doublewords
36374 throughout the computation, we can get correct behavior by replacing
36375 M with M' as follows:
36377 M'[i] = { (M[i]+8)%16 : M[i] in [0,15]
36378 { ((M[i]+8)%16)+16 : M[i] in [16,31]
36380 This seems promising at first, since we are just replacing one mask
36381 with another. But certain masks are preferable to others. If M
36382 is a mask that matches a vmrghh pattern, for example, M' certainly
36383 will not. Instead of a single vmrghh, we would generate a load of
36384 M' and a vperm. So we would need to know how many xxswapd's we can
36385 remove as a result of this transformation to determine if it's
36386 profitable; and preferably the logic would need to be aware of all
36387 the special preferable masks.
36389 Another form of permute is an UNSPEC_VPERM, in which the mask is
36390 already in a register. In some cases, this mask may be a constant
36391 that we can discover with ud-chains, in which case the above
36392 transformation is ok. However, the common usage here is for the
36393 mask to be produced by an UNSPEC_LVSL, in which case the mask
36394 cannot be known at compile time. In such a case we would have to
36395 generate several instructions to compute M' as above at run time,
36396 and a cost model is needed again.
36398 However, when the mask M for an UNSPEC_VPERM is loaded from the
36399 constant pool, we can replace M with M' as above at no cost
36400 beyond adding a constant pool entry. */
36402 /* This is based on the union-find logic in web.c. web_entry_base is
36403 defined in df.h. */
36404 class swap_web_entry
: public web_entry_base
36407 /* Pointer to the insn. */
36409 /* Set if insn contains a mention of a vector register. All other
36410 fields are undefined if this field is unset. */
36411 unsigned int is_relevant
: 1;
36412 /* Set if insn is a load. */
36413 unsigned int is_load
: 1;
36414 /* Set if insn is a store. */
36415 unsigned int is_store
: 1;
36416 /* Set if insn is a doubleword swap. This can either be a register swap
36417 or a permuting load or store (test is_load and is_store for this). */
36418 unsigned int is_swap
: 1;
36419 /* Set if the insn has a live-in use of a parameter register. */
36420 unsigned int is_live_in
: 1;
36421 /* Set if the insn has a live-out def of a return register. */
36422 unsigned int is_live_out
: 1;
36423 /* Set if the insn contains a subreg reference of a vector register. */
36424 unsigned int contains_subreg
: 1;
36425 /* Set if the insn contains a 128-bit integer operand. */
36426 unsigned int is_128_int
: 1;
36427 /* Set if this is a call-insn. */
36428 unsigned int is_call
: 1;
36429 /* Set if this insn does not perform a vector operation for which
36430 element order matters, or if we know how to fix it up if it does.
36431 Undefined if is_swap is set. */
36432 unsigned int is_swappable
: 1;
36433 /* A nonzero value indicates what kind of special handling for this
36434 insn is required if doublewords are swapped. Undefined if
36435 is_swappable is not set. */
36436 unsigned int special_handling
: 4;
36437 /* Set if the web represented by this entry cannot be optimized. */
36438 unsigned int web_not_optimizable
: 1;
36439 /* Set if this insn should be deleted. */
36440 unsigned int will_delete
: 1;
36443 enum special_handling_values
{
36456 /* Union INSN with all insns containing definitions that reach USE.
36457 Detect whether USE is live-in to the current function. */
36459 union_defs (swap_web_entry
*insn_entry
, rtx insn
, df_ref use
)
36461 struct df_link
*link
= DF_REF_CHAIN (use
);
36464 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
36468 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
36469 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
36471 if (DF_REF_INSN_INFO (link
->ref
))
36473 rtx def_insn
= DF_REF_INSN (link
->ref
);
36474 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
36475 insn_entry
+ INSN_UID (def_insn
));
36482 /* Union INSN with all insns containing uses reached from DEF.
36483 Detect whether DEF is live-out from the current function. */
36485 union_uses (swap_web_entry
*insn_entry
, rtx insn
, df_ref def
)
36487 struct df_link
*link
= DF_REF_CHAIN (def
);
36490 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
36494 /* This could be an eh use or some other artificial use;
36495 we treat these all the same (killing the optimization). */
36496 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
36497 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
36499 if (DF_REF_INSN_INFO (link
->ref
))
36501 rtx use_insn
= DF_REF_INSN (link
->ref
);
36502 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
36503 insn_entry
+ INSN_UID (use_insn
));
36510 /* Return 1 iff INSN is a load insn, including permuting loads that
36511 represent an lvxd2x instruction; else return 0. */
36512 static unsigned int
36513 insn_is_load_p (rtx insn
)
36515 rtx body
= PATTERN (insn
);
36517 if (GET_CODE (body
) == SET
)
36519 if (GET_CODE (SET_SRC (body
)) == MEM
)
36522 if (GET_CODE (SET_SRC (body
)) == VEC_SELECT
36523 && GET_CODE (XEXP (SET_SRC (body
), 0)) == MEM
)
36529 if (GET_CODE (body
) != PARALLEL
)
36532 rtx set
= XVECEXP (body
, 0, 0);
36534 if (GET_CODE (set
) == SET
&& GET_CODE (SET_SRC (set
)) == MEM
)
36540 /* Return 1 iff INSN is a store insn, including permuting stores that
36541 represent an stvxd2x instruction; else return 0. */
36542 static unsigned int
36543 insn_is_store_p (rtx insn
)
36545 rtx body
= PATTERN (insn
);
36546 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == MEM
)
36548 if (GET_CODE (body
) != PARALLEL
)
36550 rtx set
= XVECEXP (body
, 0, 0);
36551 if (GET_CODE (set
) == SET
&& GET_CODE (SET_DEST (set
)) == MEM
)
36556 /* Return 1 iff INSN swaps doublewords. This may be a reg-reg swap,
36557 a permuting load, or a permuting store. */
36558 static unsigned int
36559 insn_is_swap_p (rtx insn
)
36561 rtx body
= PATTERN (insn
);
36562 if (GET_CODE (body
) != SET
)
36564 rtx rhs
= SET_SRC (body
);
36565 if (GET_CODE (rhs
) != VEC_SELECT
)
36567 rtx parallel
= XEXP (rhs
, 1);
36568 if (GET_CODE (parallel
) != PARALLEL
)
36570 unsigned int len
= XVECLEN (parallel
, 0);
36571 if (len
!= 2 && len
!= 4 && len
!= 8 && len
!= 16)
36573 for (unsigned int i
= 0; i
< len
/ 2; ++i
)
36575 rtx op
= XVECEXP (parallel
, 0, i
);
36576 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != len
/ 2 + i
)
36579 for (unsigned int i
= len
/ 2; i
< len
; ++i
)
36581 rtx op
= XVECEXP (parallel
, 0, i
);
36582 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != i
- len
/ 2)
36588 /* Return TRUE if insn is a swap fed by a load from the constant pool. */
36590 const_load_sequence_p (swap_web_entry
*insn_entry
, rtx insn
)
36592 unsigned uid
= INSN_UID (insn
);
36593 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
)
36596 /* Find the unique use in the swap and locate its def. If the def
36597 isn't unique, punt. */
36598 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
36600 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
36602 struct df_link
*def_link
= DF_REF_CHAIN (use
);
36603 if (!def_link
|| def_link
->next
)
36606 rtx def_insn
= DF_REF_INSN (def_link
->ref
);
36607 unsigned uid2
= INSN_UID (def_insn
);
36608 if (!insn_entry
[uid2
].is_load
|| !insn_entry
[uid2
].is_swap
)
36611 rtx body
= PATTERN (def_insn
);
36612 if (GET_CODE (body
) != SET
36613 || GET_CODE (SET_SRC (body
)) != VEC_SELECT
36614 || GET_CODE (XEXP (SET_SRC (body
), 0)) != MEM
)
36617 rtx mem
= XEXP (SET_SRC (body
), 0);
36618 rtx base_reg
= XEXP (mem
, 0);
36621 insn_info
= DF_INSN_INFO_GET (def_insn
);
36622 FOR_EACH_INSN_INFO_USE (base_use
, insn_info
)
36624 if (!rtx_equal_p (DF_REF_REG (base_use
), base_reg
))
36627 struct df_link
*base_def_link
= DF_REF_CHAIN (base_use
);
36628 if (!base_def_link
|| base_def_link
->next
)
36631 rtx tocrel_insn
= DF_REF_INSN (base_def_link
->ref
);
36632 rtx tocrel_body
= PATTERN (tocrel_insn
);
36634 if (GET_CODE (tocrel_body
) != SET
)
36636 /* There is an extra level of indirection for small/large
36638 rtx tocrel_expr
= SET_SRC (tocrel_body
);
36639 if (GET_CODE (tocrel_expr
) == MEM
)
36640 tocrel_expr
= XEXP (tocrel_expr
, 0);
36641 if (!toc_relative_expr_p (tocrel_expr
, false))
36643 split_const (XVECEXP (tocrel_base
, 0, 0), &base
, &offset
);
36644 if (GET_CODE (base
) != SYMBOL_REF
|| !CONSTANT_POOL_ADDRESS_P (base
))
36651 /* Return TRUE iff OP matches a V2DF reduction pattern. See the
36652 definition of vsx_reduc_<VEC_reduc_name>_v2df in vsx.md. */
36654 v2df_reduction_p (rtx op
)
36656 if (GET_MODE (op
) != V2DFmode
)
36659 enum rtx_code code
= GET_CODE (op
);
36660 if (code
!= PLUS
&& code
!= SMIN
&& code
!= SMAX
)
36663 rtx concat
= XEXP (op
, 0);
36664 if (GET_CODE (concat
) != VEC_CONCAT
)
36667 rtx select0
= XEXP (concat
, 0);
36668 rtx select1
= XEXP (concat
, 1);
36669 if (GET_CODE (select0
) != VEC_SELECT
|| GET_CODE (select1
) != VEC_SELECT
)
36672 rtx reg0
= XEXP (select0
, 0);
36673 rtx reg1
= XEXP (select1
, 0);
36674 if (!rtx_equal_p (reg0
, reg1
) || !REG_P (reg0
))
36677 rtx parallel0
= XEXP (select0
, 1);
36678 rtx parallel1
= XEXP (select1
, 1);
36679 if (GET_CODE (parallel0
) != PARALLEL
|| GET_CODE (parallel1
) != PARALLEL
)
36682 if (!rtx_equal_p (XVECEXP (parallel0
, 0, 0), const1_rtx
)
36683 || !rtx_equal_p (XVECEXP (parallel1
, 0, 0), const0_rtx
))
36689 /* Return 1 iff OP is an operand that will not be affected by having
36690 vector doublewords swapped in memory. */
36691 static unsigned int
36692 rtx_is_swappable_p (rtx op
, unsigned int *special
)
36694 enum rtx_code code
= GET_CODE (op
);
36713 *special
= SH_CONST_VECTOR
;
36717 case VEC_DUPLICATE
:
36718 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
36719 and XEXP (op, 1) is a PARALLEL with a single QImode const int,
36720 it represents a vector splat for which we can do special
36722 if (GET_CODE (XEXP (op
, 0)) == CONST_INT
)
36724 else if (GET_CODE (XEXP (op
, 0)) == REG
36725 && GET_MODE_INNER (GET_MODE (op
)) == GET_MODE (XEXP (op
, 0)))
36726 /* This catches V2DF and V2DI splat, at a minimum. */
36728 else if (GET_CODE (XEXP (op
, 0)) == VEC_SELECT
)
36729 /* If the duplicated item is from a select, defer to the select
36730 processing to see if we can change the lane for the splat. */
36731 return rtx_is_swappable_p (XEXP (op
, 0), special
);
36736 /* A vec_extract operation is ok if we change the lane. */
36737 if (GET_CODE (XEXP (op
, 0)) == REG
36738 && GET_MODE_INNER (GET_MODE (XEXP (op
, 0))) == GET_MODE (op
)
36739 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
36740 && XVECLEN (parallel
, 0) == 1
36741 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
)
36743 *special
= SH_EXTRACT
;
36746 /* An XXPERMDI is ok if we adjust the lanes. Note that if the
36747 XXPERMDI is a swap operation, it will be identified by
36748 insn_is_swap_p and therefore we won't get here. */
36749 else if (GET_CODE (XEXP (op
, 0)) == VEC_CONCAT
36750 && (GET_MODE (XEXP (op
, 0)) == V4DFmode
36751 || GET_MODE (XEXP (op
, 0)) == V4DImode
)
36752 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
36753 && XVECLEN (parallel
, 0) == 2
36754 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
36755 && GET_CODE (XVECEXP (parallel
, 0, 1)) == CONST_INT
)
36757 *special
= SH_XXPERMDI
;
36760 else if (v2df_reduction_p (op
))
36767 /* Various operations are unsafe for this optimization, at least
36768 without significant additional work. Permutes are obviously
36769 problematic, as both the permute control vector and the ordering
36770 of the target values are invalidated by doubleword swapping.
36771 Vector pack and unpack modify the number of vector lanes.
36772 Merge-high/low will not operate correctly on swapped operands.
36773 Vector shifts across element boundaries are clearly uncool,
36774 as are vector select and concatenate operations. Vector
36775 sum-across instructions define one operand with a specific
36776 order-dependent element, so additional fixup code would be
36777 needed to make those work. Vector set and non-immediate-form
36778 vector splat are element-order sensitive. A few of these
36779 cases might be workable with special handling if required.
36780 Adding cost modeling would be appropriate in some cases. */
36781 int val
= XINT (op
, 1);
36786 case UNSPEC_VMRGH_DIRECT
:
36787 case UNSPEC_VMRGL_DIRECT
:
36788 case UNSPEC_VPACK_SIGN_SIGN_SAT
:
36789 case UNSPEC_VPACK_SIGN_UNS_SAT
:
36790 case UNSPEC_VPACK_UNS_UNS_MOD
:
36791 case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
:
36792 case UNSPEC_VPACK_UNS_UNS_SAT
:
36794 case UNSPEC_VPERM_UNS
:
36795 case UNSPEC_VPERMHI
:
36796 case UNSPEC_VPERMSI
:
36798 case UNSPEC_VSLDOI
:
36801 case UNSPEC_VSUM2SWS
:
36802 case UNSPEC_VSUM4S
:
36803 case UNSPEC_VSUM4UBS
:
36804 case UNSPEC_VSUMSWS
:
36805 case UNSPEC_VSUMSWS_DIRECT
:
36806 case UNSPEC_VSX_CONCAT
:
36807 case UNSPEC_VSX_SET
:
36808 case UNSPEC_VSX_SLDWI
:
36809 case UNSPEC_VUNPACK_HI_SIGN
:
36810 case UNSPEC_VUNPACK_HI_SIGN_DIRECT
:
36811 case UNSPEC_VUNPACK_LO_SIGN
:
36812 case UNSPEC_VUNPACK_LO_SIGN_DIRECT
:
36813 case UNSPEC_VUPKHPX
:
36814 case UNSPEC_VUPKHS_V4SF
:
36815 case UNSPEC_VUPKHU_V4SF
:
36816 case UNSPEC_VUPKLPX
:
36817 case UNSPEC_VUPKLS_V4SF
:
36818 case UNSPEC_VUPKLU_V4SF
:
36819 case UNSPEC_VSX_CVDPSPN
:
36820 case UNSPEC_VSX_CVSPDP
:
36821 case UNSPEC_VSX_CVSPDPN
:
36823 case UNSPEC_VSPLT_DIRECT
:
36824 *special
= SH_SPLAT
;
36826 case UNSPEC_REDUC_PLUS
:
36836 const char *fmt
= GET_RTX_FORMAT (code
);
36839 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
36840 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
36842 unsigned int special_op
= SH_NONE
;
36843 ok
&= rtx_is_swappable_p (XEXP (op
, i
), &special_op
);
36844 if (special_op
== SH_NONE
)
36846 /* Ensure we never have two kinds of special handling
36847 for the same insn. */
36848 if (*special
!= SH_NONE
&& *special
!= special_op
)
36850 *special
= special_op
;
36852 else if (fmt
[i
] == 'E')
36853 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
36855 unsigned int special_op
= SH_NONE
;
36856 ok
&= rtx_is_swappable_p (XVECEXP (op
, i
, j
), &special_op
);
36857 if (special_op
== SH_NONE
)
36859 /* Ensure we never have two kinds of special handling
36860 for the same insn. */
36861 if (*special
!= SH_NONE
&& *special
!= special_op
)
36863 *special
= special_op
;
36869 /* Return 1 iff INSN is an operand that will not be affected by
36870 having vector doublewords swapped in memory (in which case
36871 *SPECIAL is unchanged), or that can be modified to be correct
36872 if vector doublewords are swapped in memory (in which case
36873 *SPECIAL is changed to a value indicating how). */
36874 static unsigned int
36875 insn_is_swappable_p (swap_web_entry
*insn_entry
, rtx insn
,
36876 unsigned int *special
)
36878 /* Calls are always bad. */
36879 if (GET_CODE (insn
) == CALL_INSN
)
36882 /* Loads and stores seen here are not permuting, but we can still
36883 fix them up by converting them to permuting ones. Exceptions:
36884 UNSPEC_LVE, UNSPEC_LVX, and UNSPEC_STVX, which have a PARALLEL
36885 body instead of a SET; and UNSPEC_STVE, which has an UNSPEC
36886 for the SET source. */
36887 rtx body
= PATTERN (insn
);
36888 int i
= INSN_UID (insn
);
36890 if (insn_entry
[i
].is_load
)
36892 if (GET_CODE (body
) == SET
)
36894 *special
= SH_NOSWAP_LD
;
36901 if (insn_entry
[i
].is_store
)
36903 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) != UNSPEC
)
36905 *special
= SH_NOSWAP_ST
;
36912 /* A convert to single precision can be left as is provided that
36913 all of its uses are in xxspltw instructions that splat BE element
36915 if (GET_CODE (body
) == SET
36916 && GET_CODE (SET_SRC (body
)) == UNSPEC
36917 && XINT (SET_SRC (body
), 1) == UNSPEC_VSX_CVDPSPN
)
36920 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
36922 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
36924 struct df_link
*link
= DF_REF_CHAIN (def
);
36928 for (; link
; link
= link
->next
) {
36929 rtx use_insn
= DF_REF_INSN (link
->ref
);
36930 rtx use_body
= PATTERN (use_insn
);
36931 if (GET_CODE (use_body
) != SET
36932 || GET_CODE (SET_SRC (use_body
)) != UNSPEC
36933 || XINT (SET_SRC (use_body
), 1) != UNSPEC_VSX_XXSPLTW
36934 || XEXP (XEXP (SET_SRC (use_body
), 0), 1) != const0_rtx
)
36942 /* A concatenation of two doublewords is ok if we reverse the
36943 order of the inputs. */
36944 if (GET_CODE (body
) == SET
36945 && GET_CODE (SET_SRC (body
)) == VEC_CONCAT
36946 && (GET_MODE (SET_SRC (body
)) == V2DFmode
36947 || GET_MODE (SET_SRC (body
)) == V2DImode
))
36949 *special
= SH_CONCAT
;
36953 /* V2DF reductions are always swappable. */
36954 if (GET_CODE (body
) == PARALLEL
)
36956 rtx expr
= XVECEXP (body
, 0, 0);
36957 if (GET_CODE (expr
) == SET
36958 && v2df_reduction_p (SET_SRC (expr
)))
36962 /* An UNSPEC_VPERM is ok if the mask operand is loaded from the
36964 if (GET_CODE (body
) == SET
36965 && GET_CODE (SET_SRC (body
)) == UNSPEC
36966 && XINT (SET_SRC (body
), 1) == UNSPEC_VPERM
36967 && XVECLEN (SET_SRC (body
), 0) == 3
36968 && GET_CODE (XVECEXP (SET_SRC (body
), 0, 2)) == REG
)
36970 rtx mask_reg
= XVECEXP (SET_SRC (body
), 0, 2);
36971 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
36973 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
36974 if (rtx_equal_p (DF_REF_REG (use
), mask_reg
))
36976 struct df_link
*def_link
= DF_REF_CHAIN (use
);
36977 /* Punt if multiple definitions for this reg. */
36978 if (def_link
&& !def_link
->next
&&
36979 const_load_sequence_p (insn_entry
,
36980 DF_REF_INSN (def_link
->ref
)))
36982 *special
= SH_VPERM
;
36988 /* Otherwise check the operands for vector lane violations. */
36989 return rtx_is_swappable_p (body
, special
);
36992 enum chain_purpose
{ FOR_LOADS
, FOR_STORES
};
36994 /* Return true if the UD or DU chain headed by LINK is non-empty,
36995 and every entry on the chain references an insn that is a
36996 register swap. Furthermore, if PURPOSE is FOR_LOADS, each such
36997 register swap must have only permuting loads as reaching defs.
36998 If PURPOSE is FOR_STORES, each such register swap must have only
36999 register swaps or permuting stores as reached uses. */
37001 chain_contains_only_swaps (swap_web_entry
*insn_entry
, struct df_link
*link
,
37002 enum chain_purpose purpose
)
37007 for (; link
; link
= link
->next
)
37009 if (!ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (DF_REF_REG (link
->ref
))))
37012 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
37015 rtx reached_insn
= DF_REF_INSN (link
->ref
);
37016 unsigned uid
= INSN_UID (reached_insn
);
37017 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (reached_insn
);
37019 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
37020 || insn_entry
[uid
].is_store
)
37023 if (purpose
== FOR_LOADS
)
37026 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
37028 struct df_link
*swap_link
= DF_REF_CHAIN (use
);
37032 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
37035 rtx swap_def_insn
= DF_REF_INSN (swap_link
->ref
);
37036 unsigned uid2
= INSN_UID (swap_def_insn
);
37038 /* Only permuting loads are allowed. */
37039 if (!insn_entry
[uid2
].is_swap
|| !insn_entry
[uid2
].is_load
)
37042 swap_link
= swap_link
->next
;
37046 else if (purpose
== FOR_STORES
)
37049 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
37051 struct df_link
*swap_link
= DF_REF_CHAIN (def
);
37055 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
37058 rtx swap_use_insn
= DF_REF_INSN (swap_link
->ref
);
37059 unsigned uid2
= INSN_UID (swap_use_insn
);
37061 /* Permuting stores or register swaps are allowed. */
37062 if (!insn_entry
[uid2
].is_swap
|| insn_entry
[uid2
].is_load
)
37065 swap_link
= swap_link
->next
;
37074 /* Mark the xxswapdi instructions associated with permuting loads and
37075 stores for removal. Note that we only flag them for deletion here,
37076 as there is a possibility of a swap being reached from multiple
37079 mark_swaps_for_removal (swap_web_entry
*insn_entry
, unsigned int i
)
37081 rtx insn
= insn_entry
[i
].insn
;
37082 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
37084 if (insn_entry
[i
].is_load
)
37087 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
37089 struct df_link
*link
= DF_REF_CHAIN (def
);
37091 /* We know by now that these are swaps, so we can delete
37092 them confidently. */
37095 rtx use_insn
= DF_REF_INSN (link
->ref
);
37096 insn_entry
[INSN_UID (use_insn
)].will_delete
= 1;
37101 else if (insn_entry
[i
].is_store
)
37104 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
37106 /* Ignore uses for addressability. */
37107 machine_mode mode
= GET_MODE (DF_REF_REG (use
));
37108 if (!ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
37111 struct df_link
*link
= DF_REF_CHAIN (use
);
37113 /* We know by now that these are swaps, so we can delete
37114 them confidently. */
37117 rtx def_insn
= DF_REF_INSN (link
->ref
);
37118 insn_entry
[INSN_UID (def_insn
)].will_delete
= 1;
37125 /* OP is either a CONST_VECTOR or an expression containing one.
37126 Swap the first half of the vector with the second in the first
37127 case. Recurse to find it in the second. */
37129 swap_const_vector_halves (rtx op
)
37132 enum rtx_code code
= GET_CODE (op
);
37133 if (GET_CODE (op
) == CONST_VECTOR
)
37135 int half_units
= GET_MODE_NUNITS (GET_MODE (op
)) / 2;
37136 for (i
= 0; i
< half_units
; ++i
)
37138 rtx temp
= CONST_VECTOR_ELT (op
, i
);
37139 CONST_VECTOR_ELT (op
, i
) = CONST_VECTOR_ELT (op
, i
+ half_units
);
37140 CONST_VECTOR_ELT (op
, i
+ half_units
) = temp
;
37146 const char *fmt
= GET_RTX_FORMAT (code
);
37147 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
37148 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
37149 swap_const_vector_halves (XEXP (op
, i
));
37150 else if (fmt
[i
] == 'E')
37151 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
37152 swap_const_vector_halves (XVECEXP (op
, i
, j
));
37156 /* Find all subregs of a vector expression that perform a narrowing,
37157 and adjust the subreg index to account for doubleword swapping. */
37159 adjust_subreg_index (rtx op
)
37161 enum rtx_code code
= GET_CODE (op
);
37163 && (GET_MODE_SIZE (GET_MODE (op
))
37164 < GET_MODE_SIZE (GET_MODE (XEXP (op
, 0)))))
37166 unsigned int index
= SUBREG_BYTE (op
);
37171 SUBREG_BYTE (op
) = index
;
37174 const char *fmt
= GET_RTX_FORMAT (code
);
37176 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
37177 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
37178 adjust_subreg_index (XEXP (op
, i
));
37179 else if (fmt
[i
] == 'E')
37180 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
37181 adjust_subreg_index (XVECEXP (op
, i
, j
));
37184 /* Convert the non-permuting load INSN to a permuting one. */
37186 permute_load (rtx_insn
*insn
)
37188 rtx body
= PATTERN (insn
);
37189 rtx mem_op
= SET_SRC (body
);
37190 rtx tgt_reg
= SET_DEST (body
);
37191 machine_mode mode
= GET_MODE (tgt_reg
);
37192 int n_elts
= GET_MODE_NUNITS (mode
);
37193 int half_elts
= n_elts
/ 2;
37194 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
37196 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
37197 XVECEXP (par
, 0, i
) = GEN_INT (j
);
37198 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
37199 XVECEXP (par
, 0, i
) = GEN_INT (j
);
37200 rtx sel
= gen_rtx_VEC_SELECT (mode
, mem_op
, par
);
37201 SET_SRC (body
) = sel
;
37202 INSN_CODE (insn
) = -1; /* Force re-recognition. */
37203 df_insn_rescan (insn
);
37206 fprintf (dump_file
, "Replacing load %d with permuted load\n",
37210 /* Convert the non-permuting store INSN to a permuting one. */
37212 permute_store (rtx_insn
*insn
)
37214 rtx body
= PATTERN (insn
);
37215 rtx src_reg
= SET_SRC (body
);
37216 machine_mode mode
= GET_MODE (src_reg
);
37217 int n_elts
= GET_MODE_NUNITS (mode
);
37218 int half_elts
= n_elts
/ 2;
37219 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
37221 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
37222 XVECEXP (par
, 0, i
) = GEN_INT (j
);
37223 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
37224 XVECEXP (par
, 0, i
) = GEN_INT (j
);
37225 rtx sel
= gen_rtx_VEC_SELECT (mode
, src_reg
, par
);
37226 SET_SRC (body
) = sel
;
37227 INSN_CODE (insn
) = -1; /* Force re-recognition. */
37228 df_insn_rescan (insn
);
37231 fprintf (dump_file
, "Replacing store %d with permuted store\n",
37235 /* Given OP that contains a vector extract operation, adjust the index
37236 of the extracted lane to account for the doubleword swap. */
37238 adjust_extract (rtx_insn
*insn
)
37240 rtx pattern
= PATTERN (insn
);
37241 if (GET_CODE (pattern
) == PARALLEL
)
37242 pattern
= XVECEXP (pattern
, 0, 0);
37243 rtx src
= SET_SRC (pattern
);
37244 /* The vec_select may be wrapped in a vec_duplicate for a splat, so
37245 account for that. */
37246 rtx sel
= GET_CODE (src
) == VEC_DUPLICATE
? XEXP (src
, 0) : src
;
37247 rtx par
= XEXP (sel
, 1);
37248 int half_elts
= GET_MODE_NUNITS (GET_MODE (XEXP (sel
, 0))) >> 1;
37249 int lane
= INTVAL (XVECEXP (par
, 0, 0));
37250 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
37251 XVECEXP (par
, 0, 0) = GEN_INT (lane
);
37252 INSN_CODE (insn
) = -1; /* Force re-recognition. */
37253 df_insn_rescan (insn
);
37256 fprintf (dump_file
, "Changing lane for extract %d\n", INSN_UID (insn
));
37259 /* Given OP that contains a vector direct-splat operation, adjust the index
37260 of the source lane to account for the doubleword swap. */
37262 adjust_splat (rtx_insn
*insn
)
37264 rtx body
= PATTERN (insn
);
37265 rtx unspec
= XEXP (body
, 1);
37266 int half_elts
= GET_MODE_NUNITS (GET_MODE (unspec
)) >> 1;
37267 int lane
= INTVAL (XVECEXP (unspec
, 0, 1));
37268 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
37269 XVECEXP (unspec
, 0, 1) = GEN_INT (lane
);
37270 INSN_CODE (insn
) = -1; /* Force re-recognition. */
37271 df_insn_rescan (insn
);
37274 fprintf (dump_file
, "Changing lane for splat %d\n", INSN_UID (insn
));
37277 /* Given OP that contains an XXPERMDI operation (that is not a doubleword
37278 swap), reverse the order of the source operands and adjust the indices
37279 of the source lanes to account for doubleword reversal. */
37281 adjust_xxpermdi (rtx_insn
*insn
)
37283 rtx set
= PATTERN (insn
);
37284 rtx select
= XEXP (set
, 1);
37285 rtx concat
= XEXP (select
, 0);
37286 rtx src0
= XEXP (concat
, 0);
37287 XEXP (concat
, 0) = XEXP (concat
, 1);
37288 XEXP (concat
, 1) = src0
;
37289 rtx parallel
= XEXP (select
, 1);
37290 int lane0
= INTVAL (XVECEXP (parallel
, 0, 0));
37291 int lane1
= INTVAL (XVECEXP (parallel
, 0, 1));
37292 int new_lane0
= 3 - lane1
;
37293 int new_lane1
= 3 - lane0
;
37294 XVECEXP (parallel
, 0, 0) = GEN_INT (new_lane0
);
37295 XVECEXP (parallel
, 0, 1) = GEN_INT (new_lane1
);
37296 INSN_CODE (insn
) = -1; /* Force re-recognition. */
37297 df_insn_rescan (insn
);
37300 fprintf (dump_file
, "Changing lanes for xxpermdi %d\n", INSN_UID (insn
));
37303 /* Given OP that contains a VEC_CONCAT operation of two doublewords,
37304 reverse the order of those inputs. */
37306 adjust_concat (rtx_insn
*insn
)
37308 rtx set
= PATTERN (insn
);
37309 rtx concat
= XEXP (set
, 1);
37310 rtx src0
= XEXP (concat
, 0);
37311 XEXP (concat
, 0) = XEXP (concat
, 1);
37312 XEXP (concat
, 1) = src0
;
37313 INSN_CODE (insn
) = -1; /* Force re-recognition. */
37314 df_insn_rescan (insn
);
37317 fprintf (dump_file
, "Reversing inputs for concat %d\n", INSN_UID (insn
));
37320 /* Given an UNSPEC_VPERM insn, modify the mask loaded from the
37321 constant pool to reflect swapped doublewords. */
37323 adjust_vperm (rtx_insn
*insn
)
37325 /* We previously determined that the UNSPEC_VPERM was fed by a
37326 swap of a swapping load of a TOC-relative constant pool symbol.
37327 Find the MEM in the swapping load and replace it with a MEM for
37328 the adjusted mask constant. */
37329 rtx set
= PATTERN (insn
);
37330 rtx mask_reg
= XVECEXP (SET_SRC (set
), 0, 2);
37332 /* Find the swap. */
37333 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
37335 rtx_insn
*swap_insn
= 0;
37336 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
37337 if (rtx_equal_p (DF_REF_REG (use
), mask_reg
))
37339 struct df_link
*def_link
= DF_REF_CHAIN (use
);
37340 gcc_assert (def_link
&& !def_link
->next
);
37341 swap_insn
= DF_REF_INSN (def_link
->ref
);
37344 gcc_assert (swap_insn
);
37346 /* Find the load. */
37347 insn_info
= DF_INSN_INFO_GET (swap_insn
);
37348 rtx_insn
*load_insn
= 0;
37349 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
37351 struct df_link
*def_link
= DF_REF_CHAIN (use
);
37352 gcc_assert (def_link
&& !def_link
->next
);
37353 load_insn
= DF_REF_INSN (def_link
->ref
);
37356 gcc_assert (load_insn
);
37358 /* Find the TOC-relative symbol access. */
37359 insn_info
= DF_INSN_INFO_GET (load_insn
);
37360 rtx_insn
*tocrel_insn
= 0;
37361 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
37363 struct df_link
*def_link
= DF_REF_CHAIN (use
);
37364 gcc_assert (def_link
&& !def_link
->next
);
37365 tocrel_insn
= DF_REF_INSN (def_link
->ref
);
37368 gcc_assert (tocrel_insn
);
37370 /* Find the embedded CONST_VECTOR. We have to call toc_relative_expr_p
37371 to set tocrel_base; otherwise it would be unnecessary as we've
37372 already established it will return true. */
37374 rtx tocrel_expr
= SET_SRC (PATTERN (tocrel_insn
));
37375 /* There is an extra level of indirection for small/large code models. */
37376 if (GET_CODE (tocrel_expr
) == MEM
)
37377 tocrel_expr
= XEXP (tocrel_expr
, 0);
37378 if (!toc_relative_expr_p (tocrel_expr
, false))
37379 gcc_unreachable ();
37380 split_const (XVECEXP (tocrel_base
, 0, 0), &base
, &offset
);
37381 rtx const_vector
= get_pool_constant (base
);
37382 /* With the extra indirection, get_pool_constant will produce the
37383 real constant from the reg_equal expression, so get the real
37385 if (GET_CODE (const_vector
) == SYMBOL_REF
)
37386 const_vector
= get_pool_constant (const_vector
);
37387 gcc_assert (GET_CODE (const_vector
) == CONST_VECTOR
);
37389 /* Create an adjusted mask from the initial mask. */
37390 unsigned int new_mask
[16], i
, val
;
37391 for (i
= 0; i
< 16; ++i
) {
37392 val
= INTVAL (XVECEXP (const_vector
, 0, i
));
37394 new_mask
[i
] = (val
+ 8) % 16;
37396 new_mask
[i
] = ((val
+ 8) % 16) + 16;
37399 /* Create a new CONST_VECTOR and a MEM that references it. */
37400 rtx vals
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
37401 for (i
= 0; i
< 16; ++i
)
37402 XVECEXP (vals
, 0, i
) = GEN_INT (new_mask
[i
]);
37403 rtx new_const_vector
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (vals
, 0));
37404 rtx new_mem
= force_const_mem (V16QImode
, new_const_vector
);
37405 /* This gives us a MEM whose base operand is a SYMBOL_REF, which we
37406 can't recognize. Force the SYMBOL_REF into a register. */
37407 if (!REG_P (XEXP (new_mem
, 0))) {
37408 rtx base_reg
= force_reg (Pmode
, XEXP (new_mem
, 0));
37409 XEXP (new_mem
, 0) = base_reg
;
37410 /* Move the newly created insn ahead of the load insn. */
37411 rtx_insn
*force_insn
= get_last_insn ();
37412 remove_insn (force_insn
);
37413 rtx_insn
*before_load_insn
= PREV_INSN (load_insn
);
37414 add_insn_after (force_insn
, before_load_insn
, BLOCK_FOR_INSN (load_insn
));
37415 df_insn_rescan (before_load_insn
);
37416 df_insn_rescan (force_insn
);
37419 /* Replace the MEM in the load instruction and rescan it. */
37420 XEXP (SET_SRC (PATTERN (load_insn
)), 0) = new_mem
;
37421 INSN_CODE (load_insn
) = -1; /* Force re-recognition. */
37422 df_insn_rescan (load_insn
);
37425 fprintf (dump_file
, "Adjusting mask for vperm %d\n", INSN_UID (insn
));
37428 /* The insn described by INSN_ENTRY[I] can be swapped, but only
37429 with special handling. Take care of that here. */
37431 handle_special_swappables (swap_web_entry
*insn_entry
, unsigned i
)
37433 rtx_insn
*insn
= insn_entry
[i
].insn
;
37434 rtx body
= PATTERN (insn
);
37436 switch (insn_entry
[i
].special_handling
)
37439 gcc_unreachable ();
37440 case SH_CONST_VECTOR
:
37442 /* A CONST_VECTOR will only show up somewhere in the RHS of a SET. */
37443 gcc_assert (GET_CODE (body
) == SET
);
37444 rtx rhs
= SET_SRC (body
);
37445 swap_const_vector_halves (rhs
);
37447 fprintf (dump_file
, "Swapping constant halves in insn %d\n", i
);
37451 /* A subreg of the same size is already safe. For subregs that
37452 select a smaller portion of a reg, adjust the index for
37453 swapped doublewords. */
37454 adjust_subreg_index (body
);
37456 fprintf (dump_file
, "Adjusting subreg in insn %d\n", i
);
37459 /* Convert a non-permuting load to a permuting one. */
37460 permute_load (insn
);
37463 /* Convert a non-permuting store to a permuting one. */
37464 permute_store (insn
);
37467 /* Change the lane on an extract operation. */
37468 adjust_extract (insn
);
37471 /* Change the lane on a direct-splat operation. */
37472 adjust_splat (insn
);
37475 /* Change the lanes on an XXPERMDI operation. */
37476 adjust_xxpermdi (insn
);
37479 /* Reverse the order of a concatenation operation. */
37480 adjust_concat (insn
);
37483 /* Change the mask loaded from the constant pool for a VPERM. */
37484 adjust_vperm (insn
);
37489 /* Find the insn from the Ith table entry, which is known to be a
37490 register swap Y = SWAP(X). Replace it with a copy Y = X. */
37492 replace_swap_with_copy (swap_web_entry
*insn_entry
, unsigned i
)
37494 rtx_insn
*insn
= insn_entry
[i
].insn
;
37495 rtx body
= PATTERN (insn
);
37496 rtx src_reg
= XEXP (SET_SRC (body
), 0);
37497 rtx copy
= gen_rtx_SET (SET_DEST (body
), src_reg
);
37498 rtx_insn
*new_insn
= emit_insn_before (copy
, insn
);
37499 set_block_for_insn (new_insn
, BLOCK_FOR_INSN (insn
));
37500 df_insn_rescan (new_insn
);
37504 unsigned int new_uid
= INSN_UID (new_insn
);
37505 fprintf (dump_file
, "Replacing swap %d with copy %d\n", i
, new_uid
);
37508 df_insn_delete (insn
);
37509 remove_insn (insn
);
37510 insn
->set_deleted ();
37513 /* Dump the swap table to DUMP_FILE. */
37515 dump_swap_insn_table (swap_web_entry
*insn_entry
)
37517 int e
= get_max_uid ();
37518 fprintf (dump_file
, "\nRelevant insns with their flag settings\n\n");
37520 for (int i
= 0; i
< e
; ++i
)
37521 if (insn_entry
[i
].is_relevant
)
37523 swap_web_entry
*pred_entry
= (swap_web_entry
*)insn_entry
[i
].pred ();
37524 fprintf (dump_file
, "%6d %6d ", i
,
37525 pred_entry
&& pred_entry
->insn
37526 ? INSN_UID (pred_entry
->insn
) : 0);
37527 if (insn_entry
[i
].is_load
)
37528 fputs ("load ", dump_file
);
37529 if (insn_entry
[i
].is_store
)
37530 fputs ("store ", dump_file
);
37531 if (insn_entry
[i
].is_swap
)
37532 fputs ("swap ", dump_file
);
37533 if (insn_entry
[i
].is_live_in
)
37534 fputs ("live-in ", dump_file
);
37535 if (insn_entry
[i
].is_live_out
)
37536 fputs ("live-out ", dump_file
);
37537 if (insn_entry
[i
].contains_subreg
)
37538 fputs ("subreg ", dump_file
);
37539 if (insn_entry
[i
].is_128_int
)
37540 fputs ("int128 ", dump_file
);
37541 if (insn_entry
[i
].is_call
)
37542 fputs ("call ", dump_file
);
37543 if (insn_entry
[i
].is_swappable
)
37545 fputs ("swappable ", dump_file
);
37546 if (insn_entry
[i
].special_handling
== SH_CONST_VECTOR
)
37547 fputs ("special:constvec ", dump_file
);
37548 else if (insn_entry
[i
].special_handling
== SH_SUBREG
)
37549 fputs ("special:subreg ", dump_file
);
37550 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_LD
)
37551 fputs ("special:load ", dump_file
);
37552 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_ST
)
37553 fputs ("special:store ", dump_file
);
37554 else if (insn_entry
[i
].special_handling
== SH_EXTRACT
)
37555 fputs ("special:extract ", dump_file
);
37556 else if (insn_entry
[i
].special_handling
== SH_SPLAT
)
37557 fputs ("special:splat ", dump_file
);
37558 else if (insn_entry
[i
].special_handling
== SH_XXPERMDI
)
37559 fputs ("special:xxpermdi ", dump_file
);
37560 else if (insn_entry
[i
].special_handling
== SH_CONCAT
)
37561 fputs ("special:concat ", dump_file
);
37562 else if (insn_entry
[i
].special_handling
== SH_VPERM
)
37563 fputs ("special:vperm ", dump_file
);
37565 if (insn_entry
[i
].web_not_optimizable
)
37566 fputs ("unoptimizable ", dump_file
);
37567 if (insn_entry
[i
].will_delete
)
37568 fputs ("delete ", dump_file
);
37569 fputs ("\n", dump_file
);
37571 fputs ("\n", dump_file
);
37574 /* Main entry point for this pass. */
37576 rs6000_analyze_swaps (function
*fun
)
37578 swap_web_entry
*insn_entry
;
37582 /* Dataflow analysis for use-def chains. */
37583 df_set_flags (DF_RD_PRUNE_DEAD_DEFS
);
37584 df_chain_add_problem (DF_DU_CHAIN
| DF_UD_CHAIN
);
37586 df_set_flags (DF_DEFER_INSN_RESCAN
);
37588 /* Allocate structure to represent webs of insns. */
37589 insn_entry
= XCNEWVEC (swap_web_entry
, get_max_uid ());
37591 /* Walk the insns to gather basic data. */
37592 FOR_ALL_BB_FN (bb
, fun
)
37593 FOR_BB_INSNS (bb
, insn
)
37595 unsigned int uid
= INSN_UID (insn
);
37596 if (NONDEBUG_INSN_P (insn
))
37598 insn_entry
[uid
].insn
= insn
;
37600 if (GET_CODE (insn
) == CALL_INSN
)
37601 insn_entry
[uid
].is_call
= 1;
37603 /* Walk the uses and defs to see if we mention vector regs.
37604 Record any constraints on optimization of such mentions. */
37605 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
37607 FOR_EACH_INSN_INFO_USE (mention
, insn_info
)
37609 /* We use DF_REF_REAL_REG here to get inside any subregs. */
37610 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
37612 /* If a use gets its value from a call insn, it will be
37613 a hard register and will look like (reg:V4SI 3 3).
37614 The df analysis creates two mentions for GPR3 and GPR4,
37615 both DImode. We must recognize this and treat it as a
37616 vector mention to ensure the call is unioned with this
37618 if (mode
== DImode
&& DF_REF_INSN_INFO (mention
))
37620 rtx feeder
= DF_REF_INSN (mention
);
37621 /* FIXME: It is pretty hard to get from the df mention
37622 to the mode of the use in the insn. We arbitrarily
37623 pick a vector mode here, even though the use might
37624 be a real DImode. We can be too conservative
37625 (create a web larger than necessary) because of
37626 this, so consider eventually fixing this. */
37627 if (GET_CODE (feeder
) == CALL_INSN
)
37631 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
) || mode
== TImode
)
37633 insn_entry
[uid
].is_relevant
= 1;
37634 if (mode
== TImode
|| mode
== V1TImode
37635 || FLOAT128_VECTOR_P (mode
))
37636 insn_entry
[uid
].is_128_int
= 1;
37637 if (DF_REF_INSN_INFO (mention
))
37638 insn_entry
[uid
].contains_subreg
37639 = !rtx_equal_p (DF_REF_REG (mention
),
37640 DF_REF_REAL_REG (mention
));
37641 union_defs (insn_entry
, insn
, mention
);
37644 FOR_EACH_INSN_INFO_DEF (mention
, insn_info
)
37646 /* We use DF_REF_REAL_REG here to get inside any subregs. */
37647 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
37649 /* If we're loading up a hard vector register for a call,
37650 it looks like (set (reg:V4SI 9 9) (...)). The df
37651 analysis creates two mentions for GPR9 and GPR10, both
37652 DImode. So relying on the mode from the mentions
37653 isn't sufficient to ensure we union the call into the
37654 web with the parameter setup code. */
37655 if (mode
== DImode
&& GET_CODE (insn
) == SET
37656 && ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (SET_DEST (insn
))))
37657 mode
= GET_MODE (SET_DEST (insn
));
37659 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
) || mode
== TImode
)
37661 insn_entry
[uid
].is_relevant
= 1;
37662 if (mode
== TImode
|| mode
== V1TImode
37663 || FLOAT128_VECTOR_P (mode
))
37664 insn_entry
[uid
].is_128_int
= 1;
37665 if (DF_REF_INSN_INFO (mention
))
37666 insn_entry
[uid
].contains_subreg
37667 = !rtx_equal_p (DF_REF_REG (mention
),
37668 DF_REF_REAL_REG (mention
));
37669 /* REG_FUNCTION_VALUE_P is not valid for subregs. */
37670 else if (REG_FUNCTION_VALUE_P (DF_REF_REG (mention
)))
37671 insn_entry
[uid
].is_live_out
= 1;
37672 union_uses (insn_entry
, insn
, mention
);
37676 if (insn_entry
[uid
].is_relevant
)
37678 /* Determine if this is a load or store. */
37679 insn_entry
[uid
].is_load
= insn_is_load_p (insn
);
37680 insn_entry
[uid
].is_store
= insn_is_store_p (insn
);
37682 /* Determine if this is a doubleword swap. If not,
37683 determine whether it can legally be swapped. */
37684 if (insn_is_swap_p (insn
))
37685 insn_entry
[uid
].is_swap
= 1;
37688 unsigned int special
= SH_NONE
;
37689 insn_entry
[uid
].is_swappable
37690 = insn_is_swappable_p (insn_entry
, insn
, &special
);
37691 if (special
!= SH_NONE
&& insn_entry
[uid
].contains_subreg
)
37692 insn_entry
[uid
].is_swappable
= 0;
37693 else if (special
!= SH_NONE
)
37694 insn_entry
[uid
].special_handling
= special
;
37695 else if (insn_entry
[uid
].contains_subreg
)
37696 insn_entry
[uid
].special_handling
= SH_SUBREG
;
37704 fprintf (dump_file
, "\nSwap insn entry table when first built\n");
37705 dump_swap_insn_table (insn_entry
);
37708 /* Record unoptimizable webs. */
37709 unsigned e
= get_max_uid (), i
;
37710 for (i
= 0; i
< e
; ++i
)
37712 if (!insn_entry
[i
].is_relevant
)
37715 swap_web_entry
*root
37716 = (swap_web_entry
*)(&insn_entry
[i
])->unionfind_root ();
37718 if (insn_entry
[i
].is_live_in
|| insn_entry
[i
].is_live_out
37719 || (insn_entry
[i
].contains_subreg
37720 && insn_entry
[i
].special_handling
!= SH_SUBREG
)
37721 || insn_entry
[i
].is_128_int
|| insn_entry
[i
].is_call
37722 || !(insn_entry
[i
].is_swappable
|| insn_entry
[i
].is_swap
))
37723 root
->web_not_optimizable
= 1;
37725 /* If we have loads or stores that aren't permuting then the
37726 optimization isn't appropriate. */
37727 else if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
37728 && !insn_entry
[i
].is_swap
&& !insn_entry
[i
].is_swappable
)
37729 root
->web_not_optimizable
= 1;
37731 /* If we have permuting loads or stores that are not accompanied
37732 by a register swap, the optimization isn't appropriate. */
37733 else if (insn_entry
[i
].is_load
&& insn_entry
[i
].is_swap
)
37735 rtx insn
= insn_entry
[i
].insn
;
37736 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
37739 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
37741 struct df_link
*link
= DF_REF_CHAIN (def
);
37743 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_LOADS
))
37745 root
->web_not_optimizable
= 1;
37750 else if (insn_entry
[i
].is_store
&& insn_entry
[i
].is_swap
)
37752 rtx insn
= insn_entry
[i
].insn
;
37753 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
37756 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
37758 struct df_link
*link
= DF_REF_CHAIN (use
);
37760 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_STORES
))
37762 root
->web_not_optimizable
= 1;
37771 fprintf (dump_file
, "\nSwap insn entry table after web analysis\n");
37772 dump_swap_insn_table (insn_entry
);
37775 /* For each load and store in an optimizable web (which implies
37776 the loads and stores are permuting), find the associated
37777 register swaps and mark them for removal. Due to various
37778 optimizations we may mark the same swap more than once. Also
37779 perform special handling for swappable insns that require it. */
37780 for (i
= 0; i
< e
; ++i
)
37781 if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
37782 && insn_entry
[i
].is_swap
)
37784 swap_web_entry
* root_entry
37785 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
37786 if (!root_entry
->web_not_optimizable
)
37787 mark_swaps_for_removal (insn_entry
, i
);
37789 else if (insn_entry
[i
].is_swappable
&& insn_entry
[i
].special_handling
)
37791 swap_web_entry
* root_entry
37792 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
37793 if (!root_entry
->web_not_optimizable
)
37794 handle_special_swappables (insn_entry
, i
);
37797 /* Now delete the swaps marked for removal. */
37798 for (i
= 0; i
< e
; ++i
)
37799 if (insn_entry
[i
].will_delete
)
37800 replace_swap_with_copy (insn_entry
, i
);
37807 const pass_data pass_data_analyze_swaps
=
37809 RTL_PASS
, /* type */
37810 "swaps", /* name */
37811 OPTGROUP_NONE
, /* optinfo_flags */
37812 TV_NONE
, /* tv_id */
37813 0, /* properties_required */
37814 0, /* properties_provided */
37815 0, /* properties_destroyed */
37816 0, /* todo_flags_start */
37817 TODO_df_finish
, /* todo_flags_finish */
37820 class pass_analyze_swaps
: public rtl_opt_pass
37823 pass_analyze_swaps(gcc::context
*ctxt
)
37824 : rtl_opt_pass(pass_data_analyze_swaps
, ctxt
)
37827 /* opt_pass methods: */
37828 virtual bool gate (function
*)
37830 return (optimize
> 0 && !BYTES_BIG_ENDIAN
&& TARGET_VSX
37831 && !TARGET_P9_VECTOR
&& rs6000_optimize_swaps
);
37834 virtual unsigned int execute (function
*fun
)
37836 return rs6000_analyze_swaps (fun
);
37839 }; // class pass_analyze_swaps
37842 make_pass_analyze_swaps (gcc::context
*ctxt
)
37844 return new pass_analyze_swaps (ctxt
);
37847 #ifdef RS6000_GLIBC_ATOMIC_FENV
37848 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
37849 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
37852 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
37855 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
37857 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
)
37859 #ifdef RS6000_GLIBC_ATOMIC_FENV
37860 if (atomic_hold_decl
== NULL_TREE
)
37863 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
37864 get_identifier ("__atomic_feholdexcept"),
37865 build_function_type_list (void_type_node
,
37866 double_ptr_type_node
,
37868 TREE_PUBLIC (atomic_hold_decl
) = 1;
37869 DECL_EXTERNAL (atomic_hold_decl
) = 1;
37872 if (atomic_clear_decl
== NULL_TREE
)
37875 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
37876 get_identifier ("__atomic_feclearexcept"),
37877 build_function_type_list (void_type_node
,
37879 TREE_PUBLIC (atomic_clear_decl
) = 1;
37880 DECL_EXTERNAL (atomic_clear_decl
) = 1;
37883 tree const_double
= build_qualified_type (double_type_node
,
37885 tree const_double_ptr
= build_pointer_type (const_double
);
37886 if (atomic_update_decl
== NULL_TREE
)
37889 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
37890 get_identifier ("__atomic_feupdateenv"),
37891 build_function_type_list (void_type_node
,
37894 TREE_PUBLIC (atomic_update_decl
) = 1;
37895 DECL_EXTERNAL (atomic_update_decl
) = 1;
37898 tree fenv_var
= create_tmp_var_raw (double_type_node
);
37899 TREE_ADDRESSABLE (fenv_var
) = 1;
37900 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
37902 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
37903 *clear
= build_call_expr (atomic_clear_decl
, 0);
37904 *update
= build_call_expr (atomic_update_decl
, 1,
37905 fold_convert (const_double_ptr
, fenv_addr
));
37910 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
37911 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
37912 tree call_mffs
= build_call_expr (mffs
, 0);
37914 /* Generates the equivalent of feholdexcept (&fenv_var)
37916 *fenv_var = __builtin_mffs ();
37918 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
37919 __builtin_mtfsf (0xff, fenv_hold); */
37921 /* Mask to clear everything except for the rounding modes and non-IEEE
37922 arithmetic flag. */
37923 const unsigned HOST_WIDE_INT hold_exception_mask
=
37924 HOST_WIDE_INT_C (0xffffffff00000007);
37926 tree fenv_var
= create_tmp_var_raw (double_type_node
);
37928 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
37930 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
37931 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
37932 build_int_cst (uint64_type_node
,
37933 hold_exception_mask
));
37935 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
37938 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
37939 build_int_cst (unsigned_type_node
, 0xff),
37942 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
37944 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
37946 double fenv_clear = __builtin_mffs ();
37947 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
37948 __builtin_mtfsf (0xff, fenv_clear); */
37950 /* Mask to clear everything except for the rounding modes and non-IEEE
37951 arithmetic flag. */
37952 const unsigned HOST_WIDE_INT clear_exception_mask
=
37953 HOST_WIDE_INT_C (0xffffffff00000000);
37955 tree fenv_clear
= create_tmp_var_raw (double_type_node
);
37957 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
37959 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
37960 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
37962 build_int_cst (uint64_type_node
,
37963 clear_exception_mask
));
37965 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
37966 fenv_clear_llu_and
);
37968 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
37969 build_int_cst (unsigned_type_node
, 0xff),
37972 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
37974 /* Generates the equivalent of feupdateenv (&fenv_var)
37976 double old_fenv = __builtin_mffs ();
37977 double fenv_update;
37978 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
37979 (*(uint64_t*)fenv_var 0x1ff80fff);
37980 __builtin_mtfsf (0xff, fenv_update); */
37982 const unsigned HOST_WIDE_INT update_exception_mask
=
37983 HOST_WIDE_INT_C (0xffffffff1fffff00);
37984 const unsigned HOST_WIDE_INT new_exception_mask
=
37985 HOST_WIDE_INT_C (0x1ff80fff);
37987 tree old_fenv
= create_tmp_var_raw (double_type_node
);
37988 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
37990 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
37991 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
37992 build_int_cst (uint64_type_node
,
37993 update_exception_mask
));
37995 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
37996 build_int_cst (uint64_type_node
,
37997 new_exception_mask
));
37999 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
38000 old_llu_and
, new_llu_and
);
38002 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
38005 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
38006 build_int_cst (unsigned_type_node
, 0xff),
38007 fenv_update_mtfsf
);
38009 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
38012 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
38015 rs6000_optab_supported_p (int op
, machine_mode mode1
, machine_mode
,
38016 optimization_type opt_type
)
38021 return (opt_type
== OPTIMIZE_FOR_SPEED
38022 && RS6000_RECIP_AUTO_RSQRTE_P (mode1
));
38029 struct gcc_target targetm
= TARGET_INITIALIZER
;
38031 #include "gt-rs6000.h"