2014-04-15 Richard Biener <rguenther@suse.de>
[official-gcc.git] / gcc / ree.c
blobfcde9a0f3993d5a16281ed9a058cd3a040bd3db5
1 /* Redundant Extension Elimination pass for the GNU compiler.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Ilya Enkovich (ilya.enkovich@intel.com)
5 Based on the Redundant Zero-extension elimination pass contributed by
6 Sriraman Tallam (tmsriram@google.com) and Silvius Rus (rus@google.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
13 version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Problem Description :
26 --------------------
27 This pass is intended to remove redundant extension instructions.
28 Such instructions appear for different reasons. We expect some of
29 them due to implicit zero-extension in 64-bit registers after writing
30 to their lower 32-bit half (e.g. for the x86-64 architecture).
31 Another possible reason is a type cast which follows a load (for
32 instance a register restore) and which can be combined into a single
33 instruction, and for which earlier local passes, e.g. the combiner,
34 weren't able to optimize.
36 How does this pass work ?
37 --------------------------
39 This pass is run after register allocation. Hence, all registers that
40 this pass deals with are hard registers. This pass first looks for an
41 extension instruction that could possibly be redundant. Such extension
42 instructions show up in RTL with the pattern :
43 (set (reg:<SWI248> x) (any_extend:<SWI248> (reg:<SWI124> x))),
44 where x can be any hard register.
45 Now, this pass tries to eliminate this instruction by merging the
46 extension with the definitions of register x. For instance, if
47 one of the definitions of register x was :
48 (set (reg:SI x) (plus:SI (reg:SI z1) (reg:SI z2))),
49 followed by extension :
50 (set (reg:DI x) (zero_extend:DI (reg:SI x)))
51 then the combination converts this into :
52 (set (reg:DI x) (zero_extend:DI (plus:SI (reg:SI z1) (reg:SI z2)))).
53 If all the merged definitions are recognizable assembly instructions,
54 the extension is effectively eliminated.
56 For example, for the x86-64 architecture, implicit zero-extensions
57 are captured with appropriate patterns in the i386.md file. Hence,
58 these merged definition can be matched to a single assembly instruction.
59 The original extension instruction is then deleted if all the
60 definitions can be merged.
62 However, there are cases where the definition instruction cannot be
63 merged with an extension. Examples are CALL instructions. In such
64 cases, the original extension is not redundant and this pass does
65 not delete it.
67 Handling conditional moves :
68 ----------------------------
70 Architectures like x86-64 support conditional moves whose semantics for
71 extension differ from the other instructions. For instance, the
72 instruction *cmov ebx, eax*
73 zero-extends eax onto rax only when the move from ebx to eax happens.
74 Otherwise, eax may not be zero-extended. Consider conditional moves as
75 RTL instructions of the form
76 (set (reg:SI x) (if_then_else (cond) (reg:SI y) (reg:SI z))).
77 This pass tries to merge an extension with a conditional move by
78 actually merging the definitions of y and z with an extension and then
79 converting the conditional move into :
80 (set (reg:DI x) (if_then_else (cond) (reg:DI y) (reg:DI z))).
81 Since registers y and z are extended, register x will also be extended
82 after the conditional move. Note that this step has to be done
83 transitively since the definition of a conditional copy can be
84 another conditional copy.
86 Motivating Example I :
87 ---------------------
88 For this program :
89 **********************************************
90 bad_code.c
92 int mask[1000];
94 int foo(unsigned x)
96 if (x < 10)
97 x = x * 45;
98 else
99 x = x * 78;
100 return mask[x];
102 **********************************************
104 $ gcc -O2 bad_code.c
105 ........
106 400315: b8 4e 00 00 00 mov $0x4e,%eax
107 40031a: 0f af f8 imul %eax,%edi
108 40031d: 89 ff mov %edi,%edi - useless extension
109 40031f: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax
110 400326: c3 retq
111 ......
112 400330: ba 2d 00 00 00 mov $0x2d,%edx
113 400335: 0f af fa imul %edx,%edi
114 400338: 89 ff mov %edi,%edi - useless extension
115 40033a: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax
116 400341: c3 retq
118 $ gcc -O2 -free bad_code.c
119 ......
120 400315: 6b ff 4e imul $0x4e,%edi,%edi
121 400318: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax
122 40031f: c3 retq
123 400320: 6b ff 2d imul $0x2d,%edi,%edi
124 400323: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax
125 40032a: c3 retq
127 Motivating Example II :
128 ---------------------
130 Here is an example with a conditional move.
132 For this program :
133 **********************************************
135 unsigned long long foo(unsigned x , unsigned y)
137 unsigned z;
138 if (x > 100)
139 z = x + y;
140 else
141 z = x - y;
142 return (unsigned long long)(z);
145 $ gcc -O2 bad_code.c
146 ............
147 400360: 8d 14 3e lea (%rsi,%rdi,1),%edx
148 400363: 89 f8 mov %edi,%eax
149 400365: 29 f0 sub %esi,%eax
150 400367: 83 ff 65 cmp $0x65,%edi
151 40036a: 0f 43 c2 cmovae %edx,%eax
152 40036d: 89 c0 mov %eax,%eax - useless extension
153 40036f: c3 retq
155 $ gcc -O2 -free bad_code.c
156 .............
157 400360: 89 fa mov %edi,%edx
158 400362: 8d 04 3e lea (%rsi,%rdi,1),%eax
159 400365: 29 f2 sub %esi,%edx
160 400367: 83 ff 65 cmp $0x65,%edi
161 40036a: 89 d6 mov %edx,%esi
162 40036c: 48 0f 42 c6 cmovb %rsi,%rax
163 400370: c3 retq
165 Motivating Example III :
166 ---------------------
168 Here is an example with a type cast.
170 For this program :
171 **********************************************
173 void test(int size, unsigned char *in, unsigned char *out)
175 int i;
176 unsigned char xr, xg, xy=0;
178 for (i = 0; i < size; i++) {
179 xr = *in++;
180 xg = *in++;
181 xy = (unsigned char) ((19595*xr + 38470*xg) >> 16);
182 *out++ = xy;
186 $ gcc -O2 bad_code.c
187 ............
188 10: 0f b6 0e movzbl (%rsi),%ecx
189 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax
190 17: 48 83 c6 02 add $0x2,%rsi
191 1b: 0f b6 c9 movzbl %cl,%ecx - useless extension
192 1e: 0f b6 c0 movzbl %al,%eax - useless extension
193 21: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx
194 27: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax
196 $ gcc -O2 -free bad_code.c
197 .............
198 10: 0f b6 0e movzbl (%rsi),%ecx
199 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax
200 17: 48 83 c6 02 add $0x2,%rsi
201 1b: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx
202 21: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax
204 Usefulness :
205 ----------
207 The original redundant zero-extension elimination pass reported reduction
208 of the dynamic instruction count of a compression benchmark by 2.8% and
209 improvement of its run time by about 1%.
211 The additional performance gain with the enhanced pass is mostly expected
212 on in-order architectures where redundancy cannot be compensated by out of
213 order execution. Measurements showed up to 10% performance gain (reduced
214 run time) on EEMBC 2.0 benchmarks on Atom processor with geomean performance
215 gain 1%. */
218 #include "config.h"
219 #include "system.h"
220 #include "coretypes.h"
221 #include "tm.h"
222 #include "rtl.h"
223 #include "tree.h"
224 #include "tm_p.h"
225 #include "flags.h"
226 #include "regs.h"
227 #include "hard-reg-set.h"
228 #include "basic-block.h"
229 #include "insn-config.h"
230 #include "function.h"
231 #include "expr.h"
232 #include "insn-attr.h"
233 #include "recog.h"
234 #include "diagnostic-core.h"
235 #include "target.h"
236 #include "optabs.h"
237 #include "insn-codes.h"
238 #include "rtlhooks-def.h"
239 #include "params.h"
240 #include "tree-pass.h"
241 #include "df.h"
242 #include "cgraph.h"
244 /* This structure represents a candidate for elimination. */
246 typedef struct ext_cand
248 /* The expression. */
249 const_rtx expr;
251 /* The kind of extension. */
252 enum rtx_code code;
254 /* The destination mode. */
255 enum machine_mode mode;
257 /* The instruction where it lives. */
258 rtx insn;
259 } ext_cand;
262 static int max_insn_uid;
264 /* Given a insn (CURR_INSN), an extension candidate for removal (CAND)
265 and a pointer to the SET rtx (ORIG_SET) that needs to be modified,
266 this code modifies the SET rtx to a new SET rtx that extends the
267 right hand expression into a register on the left hand side. Note
268 that multiple assumptions are made about the nature of the set that
269 needs to be true for this to work and is called from merge_def_and_ext.
271 Original :
272 (set (reg a) (expression))
274 Transform :
275 (set (reg a) (any_extend (expression)))
277 Special Cases :
278 If the expression is a constant or another extension, then directly
279 assign it to the register. */
281 static bool
282 combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set)
284 rtx orig_src = SET_SRC (*orig_set);
285 rtx new_set;
286 rtx cand_pat = PATTERN (cand->insn);
288 /* If the extension's source/destination registers are not the same
289 then we need to change the original load to reference the destination
290 of the extension. Then we need to emit a copy from that destination
291 to the original destination of the load. */
292 rtx new_reg;
293 bool copy_needed
294 = (REGNO (SET_DEST (cand_pat)) != REGNO (XEXP (SET_SRC (cand_pat), 0)));
295 if (copy_needed)
296 new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (cand_pat)));
297 else
298 new_reg = gen_rtx_REG (cand->mode, REGNO (SET_DEST (*orig_set)));
300 #if 0
301 /* Rethinking test. Temporarily disabled. */
302 /* We're going to be widening the result of DEF_INSN, ensure that doing so
303 doesn't change the number of hard registers needed for the result. */
304 if (HARD_REGNO_NREGS (REGNO (new_reg), cand->mode)
305 != HARD_REGNO_NREGS (REGNO (SET_DEST (*orig_set)),
306 GET_MODE (SET_DEST (*orig_set))))
307 return false;
308 #endif
310 /* Merge constants by directly moving the constant into the register under
311 some conditions. Recall that RTL constants are sign-extended. */
312 if (GET_CODE (orig_src) == CONST_INT
313 && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (cand->mode))
315 if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
316 new_set = gen_rtx_SET (VOIDmode, new_reg, orig_src);
317 else
319 /* Zero-extend the negative constant by masking out the bits outside
320 the source mode. */
321 enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set));
322 rtx new_const_int
323 = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (src_mode),
324 GET_MODE (new_reg));
325 new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int);
328 else if (GET_MODE (orig_src) == VOIDmode)
330 /* This is mostly due to a call insn that should not be optimized. */
331 return false;
333 else if (GET_CODE (orig_src) == cand->code)
335 /* Here is a sequence of two extensions. Try to merge them. */
336 rtx temp_extension
337 = gen_rtx_fmt_e (cand->code, cand->mode, XEXP (orig_src, 0));
338 rtx simplified_temp_extension = simplify_rtx (temp_extension);
339 if (simplified_temp_extension)
340 temp_extension = simplified_temp_extension;
341 new_set = gen_rtx_SET (VOIDmode, new_reg, temp_extension);
343 else if (GET_CODE (orig_src) == IF_THEN_ELSE)
345 /* Only IF_THEN_ELSE of phi-type copies are combined. Otherwise,
346 in general, IF_THEN_ELSE should not be combined. */
347 return false;
349 else
351 /* This is the normal case. */
352 rtx temp_extension
353 = gen_rtx_fmt_e (cand->code, cand->mode, orig_src);
354 rtx simplified_temp_extension = simplify_rtx (temp_extension);
355 if (simplified_temp_extension)
356 temp_extension = simplified_temp_extension;
357 new_set = gen_rtx_SET (VOIDmode, new_reg, temp_extension);
360 /* This change is a part of a group of changes. Hence,
361 validate_change will not try to commit the change. */
362 if (validate_change (curr_insn, orig_set, new_set, true))
364 if (dump_file)
366 fprintf (dump_file,
367 "Tentatively merged extension with definition %s:\n",
368 (copy_needed) ? "(copy needed)" : "");
369 print_rtl_single (dump_file, curr_insn);
371 return true;
374 return false;
377 /* Treat if_then_else insns, where the operands of both branches
378 are registers, as copies. For instance,
379 Original :
380 (set (reg:SI a) (if_then_else (cond) (reg:SI b) (reg:SI c)))
381 Transformed :
382 (set (reg:DI a) (if_then_else (cond) (reg:DI b) (reg:DI c)))
383 DEF_INSN is the if_then_else insn. */
385 static bool
386 transform_ifelse (ext_cand *cand, rtx def_insn)
388 rtx set_insn = PATTERN (def_insn);
389 rtx srcreg, dstreg, srcreg2;
390 rtx map_srcreg, map_dstreg, map_srcreg2;
391 rtx ifexpr;
392 rtx cond;
393 rtx new_set;
395 gcc_assert (GET_CODE (set_insn) == SET);
397 cond = XEXP (SET_SRC (set_insn), 0);
398 dstreg = SET_DEST (set_insn);
399 srcreg = XEXP (SET_SRC (set_insn), 1);
400 srcreg2 = XEXP (SET_SRC (set_insn), 2);
401 /* If the conditional move already has the right or wider mode,
402 there is nothing to do. */
403 if (GET_MODE_SIZE (GET_MODE (dstreg)) >= GET_MODE_SIZE (cand->mode))
404 return true;
406 map_srcreg = gen_rtx_REG (cand->mode, REGNO (srcreg));
407 map_srcreg2 = gen_rtx_REG (cand->mode, REGNO (srcreg2));
408 map_dstreg = gen_rtx_REG (cand->mode, REGNO (dstreg));
409 ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2);
410 new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr);
412 if (validate_change (def_insn, &PATTERN (def_insn), new_set, true))
414 if (dump_file)
416 fprintf (dump_file,
417 "Mode of conditional move instruction extended:\n");
418 print_rtl_single (dump_file, def_insn);
420 return true;
423 return false;
426 /* Get all the reaching definitions of an instruction. The definitions are
427 desired for REG used in INSN. Return the definition list or NULL if a
428 definition is missing. If DEST is non-NULL, additionally push the INSN
429 of the definitions onto DEST. */
431 static struct df_link *
432 get_defs (rtx insn, rtx reg, vec<rtx> *dest)
434 df_ref reg_info, *uses;
435 struct df_link *ref_chain, *ref_link;
437 reg_info = NULL;
439 for (uses = DF_INSN_USES (insn); *uses; uses++)
441 reg_info = *uses;
442 if (GET_CODE (DF_REF_REG (reg_info)) == SUBREG)
443 return NULL;
444 if (REGNO (DF_REF_REG (reg_info)) == REGNO (reg))
445 break;
448 gcc_assert (reg_info != NULL && uses != NULL);
450 ref_chain = DF_REF_CHAIN (reg_info);
452 for (ref_link = ref_chain; ref_link; ref_link = ref_link->next)
454 /* Problem getting some definition for this instruction. */
455 if (ref_link->ref == NULL)
456 return NULL;
457 if (DF_REF_INSN_INFO (ref_link->ref) == NULL)
458 return NULL;
461 if (dest)
462 for (ref_link = ref_chain; ref_link; ref_link = ref_link->next)
463 dest->safe_push (DF_REF_INSN (ref_link->ref));
465 return ref_chain;
468 /* Return true if INSN is
469 (SET (reg REGNO (def_reg)) (if_then_else (cond) (REG x1) (REG x2)))
470 and store x1 and x2 in REG_1 and REG_2. */
472 static bool
473 is_cond_copy_insn (rtx insn, rtx *reg1, rtx *reg2)
475 rtx expr = single_set (insn);
477 if (expr != NULL_RTX
478 && GET_CODE (expr) == SET
479 && GET_CODE (SET_DEST (expr)) == REG
480 && GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE
481 && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG
482 && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG)
484 *reg1 = XEXP (SET_SRC (expr), 1);
485 *reg2 = XEXP (SET_SRC (expr), 2);
486 return true;
489 return false;
492 enum ext_modified_kind
494 /* The insn hasn't been modified by ree pass yet. */
495 EXT_MODIFIED_NONE,
496 /* Changed into zero extension. */
497 EXT_MODIFIED_ZEXT,
498 /* Changed into sign extension. */
499 EXT_MODIFIED_SEXT
502 struct ATTRIBUTE_PACKED ext_modified
504 /* Mode from which ree has zero or sign extended the destination. */
505 ENUM_BITFIELD(machine_mode) mode : 8;
507 /* Kind of modification of the insn. */
508 ENUM_BITFIELD(ext_modified_kind) kind : 2;
510 /* True if the insn is scheduled to be deleted. */
511 unsigned int deleted : 1;
514 /* Vectors used by combine_reaching_defs and its helpers. */
515 typedef struct ext_state
517 /* In order to avoid constant alloc/free, we keep these
518 4 vectors live through the entire find_and_remove_re and just
519 truncate them each time. */
520 vec<rtx> defs_list;
521 vec<rtx> copies_list;
522 vec<rtx> modified_list;
523 vec<rtx> work_list;
525 /* For instructions that have been successfully modified, this is
526 the original mode from which the insn is extending and
527 kind of extension. */
528 struct ext_modified *modified;
529 } ext_state;
531 /* Reaching Definitions of the extended register could be conditional copies
532 or regular definitions. This function separates the two types into two
533 lists, STATE->DEFS_LIST and STATE->COPIES_LIST. This is necessary because,
534 if a reaching definition is a conditional copy, merging the extension with
535 this definition is wrong. Conditional copies are merged by transitively
536 merging their definitions. The defs_list is populated with all the reaching
537 definitions of the extension instruction (EXTEND_INSN) which must be merged
538 with an extension. The copies_list contains all the conditional moves that
539 will later be extended into a wider mode conditional move if all the merges
540 are successful. The function returns false upon failure, true upon
541 success. */
543 static bool
544 make_defs_and_copies_lists (rtx extend_insn, const_rtx set_pat,
545 ext_state *state)
547 rtx src_reg = XEXP (SET_SRC (set_pat), 0);
548 bool *is_insn_visited;
549 bool ret = true;
551 state->work_list.truncate (0);
553 /* Initialize the work list. */
554 if (!get_defs (extend_insn, src_reg, &state->work_list))
555 gcc_unreachable ();
557 is_insn_visited = XCNEWVEC (bool, max_insn_uid);
559 /* Perform transitive closure for conditional copies. */
560 while (!state->work_list.is_empty ())
562 rtx def_insn = state->work_list.pop ();
563 rtx reg1, reg2;
565 gcc_assert (INSN_UID (def_insn) < max_insn_uid);
567 if (is_insn_visited[INSN_UID (def_insn)])
568 continue;
569 is_insn_visited[INSN_UID (def_insn)] = true;
571 if (is_cond_copy_insn (def_insn, &reg1, &reg2))
573 /* Push it onto the copy list first. */
574 state->copies_list.safe_push (def_insn);
576 /* Now perform the transitive closure. */
577 if (!get_defs (def_insn, reg1, &state->work_list)
578 || !get_defs (def_insn, reg2, &state->work_list))
580 ret = false;
581 break;
584 else
585 state->defs_list.safe_push (def_insn);
588 XDELETEVEC (is_insn_visited);
590 return ret;
593 /* If DEF_INSN has single SET expression, possibly buried inside
594 a PARALLEL, return the address of the SET expression, else
595 return NULL. This is similar to single_set, except that
596 single_set allows multiple SETs when all but one is dead. */
597 static rtx *
598 get_sub_rtx (rtx def_insn)
600 enum rtx_code code = GET_CODE (PATTERN (def_insn));
601 rtx *sub_rtx = NULL;
603 if (code == PARALLEL)
605 for (int i = 0; i < XVECLEN (PATTERN (def_insn), 0); i++)
607 rtx s_expr = XVECEXP (PATTERN (def_insn), 0, i);
608 if (GET_CODE (s_expr) != SET)
609 continue;
611 if (sub_rtx == NULL)
612 sub_rtx = &XVECEXP (PATTERN (def_insn), 0, i);
613 else
615 /* PARALLEL with multiple SETs. */
616 return NULL;
620 else if (code == SET)
621 sub_rtx = &PATTERN (def_insn);
622 else
624 /* It is not a PARALLEL or a SET, what could it be ? */
625 return NULL;
628 gcc_assert (sub_rtx != NULL);
629 return sub_rtx;
632 /* Merge the DEF_INSN with an extension. Calls combine_set_extension
633 on the SET pattern. */
635 static bool
636 merge_def_and_ext (ext_cand *cand, rtx def_insn, ext_state *state)
638 enum machine_mode ext_src_mode;
639 rtx *sub_rtx;
641 ext_src_mode = GET_MODE (XEXP (SET_SRC (cand->expr), 0));
642 sub_rtx = get_sub_rtx (def_insn);
644 if (sub_rtx == NULL)
645 return false;
647 if (REG_P (SET_DEST (*sub_rtx))
648 && (GET_MODE (SET_DEST (*sub_rtx)) == ext_src_mode
649 || ((state->modified[INSN_UID (def_insn)].kind
650 == (cand->code == ZERO_EXTEND
651 ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT))
652 && state->modified[INSN_UID (def_insn)].mode
653 == ext_src_mode)))
655 if (GET_MODE_SIZE (GET_MODE (SET_DEST (*sub_rtx)))
656 >= GET_MODE_SIZE (cand->mode))
657 return true;
658 /* If def_insn is already scheduled to be deleted, don't attempt
659 to modify it. */
660 if (state->modified[INSN_UID (def_insn)].deleted)
661 return false;
662 if (combine_set_extension (cand, def_insn, sub_rtx))
664 if (state->modified[INSN_UID (def_insn)].kind == EXT_MODIFIED_NONE)
665 state->modified[INSN_UID (def_insn)].mode = ext_src_mode;
666 return true;
670 return false;
673 /* Given SRC, which should be one or more extensions of a REG, strip
674 away the extensions and return the REG. */
676 static inline rtx
677 get_extended_src_reg (rtx src)
679 while (GET_CODE (src) == SIGN_EXTEND || GET_CODE (src) == ZERO_EXTEND)
680 src = XEXP (src, 0);
681 gcc_assert (REG_P (src));
682 return src;
685 /* This function goes through all reaching defs of the source
686 of the candidate for elimination (CAND) and tries to combine
687 the extension with the definition instruction. The changes
688 are made as a group so that even if one definition cannot be
689 merged, all reaching definitions end up not being merged.
690 When a conditional copy is encountered, merging is attempted
691 transitively on its definitions. It returns true upon success
692 and false upon failure. */
694 static bool
695 combine_reaching_defs (ext_cand *cand, const_rtx set_pat, ext_state *state)
697 rtx def_insn;
698 bool merge_successful = true;
699 int i;
700 int defs_ix;
701 bool outcome;
703 state->defs_list.truncate (0);
704 state->copies_list.truncate (0);
706 outcome = make_defs_and_copies_lists (cand->insn, set_pat, state);
708 if (!outcome)
709 return false;
711 /* If the destination operand of the extension is a different
712 register than the source operand, then additional restrictions
713 are needed. Note we have to handle cases where we have nested
714 extensions in the source operand. */
715 if (REGNO (SET_DEST (PATTERN (cand->insn)))
716 != REGNO (get_extended_src_reg (SET_SRC (PATTERN (cand->insn)))))
718 /* In theory we could handle more than one reaching def, it
719 just makes the code to update the insn stream more complex. */
720 if (state->defs_list.length () != 1)
721 return false;
723 /* We require the candidate not already be modified. It may,
724 for example have been changed from a (sign_extend (reg))
725 into (zero_extend (sign_extend (reg)).
727 Handling that case shouldn't be terribly difficult, but the code
728 here and the code to emit copies would need auditing. Until
729 we see a need, this is the safe thing to do. */
730 if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE)
731 return false;
733 /* Transformation of
734 (set (reg1) (expression))
735 (set (reg2) (any_extend (reg1)))
736 into
737 (set (reg2) (any_extend (expression)))
738 (set (reg1) (reg2))
739 is only valid for scalar integral modes, as it relies on the low
740 subreg of reg1 to have the value of (expression), which is not true
741 e.g. for vector modes. */
742 if (!SCALAR_INT_MODE_P (GET_MODE (SET_DEST (PATTERN (cand->insn)))))
743 return false;
745 /* There's only one reaching def. */
746 rtx def_insn = state->defs_list[0];
748 /* The defining statement must not have been modified either. */
749 if (state->modified[INSN_UID (def_insn)].kind != EXT_MODIFIED_NONE)
750 return false;
752 /* The defining statement and candidate insn must be in the same block.
753 This is merely to keep the test for safety and updating the insn
754 stream simple. Also ensure that within the block the candidate
755 follows the defining insn. */
756 if (BLOCK_FOR_INSN (cand->insn) != BLOCK_FOR_INSN (def_insn)
757 || DF_INSN_LUID (def_insn) > DF_INSN_LUID (cand->insn))
758 return false;
760 /* If there is an overlap between the destination of DEF_INSN and
761 CAND->insn, then this transformation is not safe. Note we have
762 to test in the widened mode. */
763 rtx *dest_sub_rtx = get_sub_rtx (def_insn);
764 if (dest_sub_rtx == NULL
765 || !REG_P (SET_DEST (*dest_sub_rtx)))
766 return false;
768 rtx tmp_reg = gen_rtx_REG (GET_MODE (SET_DEST (PATTERN (cand->insn))),
769 REGNO (SET_DEST (*dest_sub_rtx)));
770 if (reg_overlap_mentioned_p (tmp_reg, SET_DEST (PATTERN (cand->insn))))
771 return false;
773 /* The destination register of the extension insn must not be
774 used or set between the def_insn and cand->insn exclusive. */
775 if (reg_used_between_p (SET_DEST (PATTERN (cand->insn)),
776 def_insn, cand->insn)
777 || reg_set_between_p (SET_DEST (PATTERN (cand->insn)),
778 def_insn, cand->insn))
779 return false;
783 /* If cand->insn has been already modified, update cand->mode to a wider
784 mode if possible, or punt. */
785 if (state->modified[INSN_UID (cand->insn)].kind != EXT_MODIFIED_NONE)
787 enum machine_mode mode;
788 rtx set;
790 if (state->modified[INSN_UID (cand->insn)].kind
791 != (cand->code == ZERO_EXTEND
792 ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT)
793 || state->modified[INSN_UID (cand->insn)].mode != cand->mode
794 || (set = single_set (cand->insn)) == NULL_RTX)
795 return false;
796 mode = GET_MODE (SET_DEST (set));
797 gcc_assert (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (cand->mode));
798 cand->mode = mode;
801 merge_successful = true;
803 /* Go through the defs vector and try to merge all the definitions
804 in this vector. */
805 state->modified_list.truncate (0);
806 FOR_EACH_VEC_ELT (state->defs_list, defs_ix, def_insn)
808 if (merge_def_and_ext (cand, def_insn, state))
809 state->modified_list.safe_push (def_insn);
810 else
812 merge_successful = false;
813 break;
817 /* Now go through the conditional copies vector and try to merge all
818 the copies in this vector. */
819 if (merge_successful)
821 FOR_EACH_VEC_ELT (state->copies_list, i, def_insn)
823 if (transform_ifelse (cand, def_insn))
824 state->modified_list.safe_push (def_insn);
825 else
827 merge_successful = false;
828 break;
833 if (merge_successful)
835 /* Commit the changes here if possible
836 FIXME: It's an all-or-nothing scenario. Even if only one definition
837 cannot be merged, we entirely give up. In the future, we should allow
838 extensions to be partially eliminated along those paths where the
839 definitions could be merged. */
840 if (apply_change_group ())
842 if (dump_file)
843 fprintf (dump_file, "All merges were successful.\n");
845 FOR_EACH_VEC_ELT (state->modified_list, i, def_insn)
846 if (state->modified[INSN_UID (def_insn)].kind == EXT_MODIFIED_NONE)
847 state->modified[INSN_UID (def_insn)].kind
848 = (cand->code == ZERO_EXTEND
849 ? EXT_MODIFIED_ZEXT : EXT_MODIFIED_SEXT);
851 return true;
853 else
855 /* Changes need not be cancelled explicitly as apply_change_group
856 does it. Print list of definitions in the dump_file for debug
857 purposes. This extension cannot be deleted. */
858 if (dump_file)
860 fprintf (dump_file,
861 "Merge cancelled, non-mergeable definitions:\n");
862 FOR_EACH_VEC_ELT (state->modified_list, i, def_insn)
863 print_rtl_single (dump_file, def_insn);
867 else
869 /* Cancel any changes that have been made so far. */
870 cancel_changes (0);
873 return false;
876 /* Add an extension pattern that could be eliminated. */
878 static void
879 add_removable_extension (const_rtx expr, rtx insn,
880 vec<ext_cand> *insn_list,
881 unsigned *def_map)
883 enum rtx_code code;
884 enum machine_mode mode;
885 unsigned int idx;
886 rtx src, dest;
888 /* We are looking for SET (REG N) (ANY_EXTEND (REG N)). */
889 if (GET_CODE (expr) != SET)
890 return;
892 src = SET_SRC (expr);
893 code = GET_CODE (src);
894 dest = SET_DEST (expr);
895 mode = GET_MODE (dest);
897 if (REG_P (dest)
898 && (code == SIGN_EXTEND || code == ZERO_EXTEND)
899 && REG_P (XEXP (src, 0)))
901 struct df_link *defs, *def;
902 ext_cand *cand;
904 /* First, make sure we can get all the reaching definitions. */
905 defs = get_defs (insn, XEXP (src, 0), NULL);
906 if (!defs)
908 if (dump_file)
910 fprintf (dump_file, "Cannot eliminate extension:\n");
911 print_rtl_single (dump_file, insn);
912 fprintf (dump_file, " because of missing definition(s)\n");
914 return;
917 /* Second, make sure the reaching definitions don't feed another and
918 different extension. FIXME: this obviously can be improved. */
919 for (def = defs; def; def = def->next)
920 if ((idx = def_map[INSN_UID (DF_REF_INSN (def->ref))])
921 && (cand = &(*insn_list)[idx - 1])
922 && cand->code != code)
924 if (dump_file)
926 fprintf (dump_file, "Cannot eliminate extension:\n");
927 print_rtl_single (dump_file, insn);
928 fprintf (dump_file, " because of other extension\n");
930 return;
933 /* Then add the candidate to the list and insert the reaching definitions
934 into the definition map. */
935 ext_cand e = {expr, code, mode, insn};
936 insn_list->safe_push (e);
937 idx = insn_list->length ();
939 for (def = defs; def; def = def->next)
940 def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx;
944 /* Traverse the instruction stream looking for extensions and return the
945 list of candidates. */
947 static vec<ext_cand>
948 find_removable_extensions (void)
950 vec<ext_cand> insn_list = vNULL;
951 basic_block bb;
952 rtx insn, set;
953 unsigned *def_map = XCNEWVEC (unsigned, max_insn_uid);
955 FOR_EACH_BB_FN (bb, cfun)
956 FOR_BB_INSNS (bb, insn)
958 if (!NONDEBUG_INSN_P (insn))
959 continue;
961 set = single_set (insn);
962 if (set == NULL_RTX)
963 continue;
964 add_removable_extension (set, insn, &insn_list, def_map);
967 XDELETEVEC (def_map);
969 return insn_list;
972 /* This is the main function that checks the insn stream for redundant
973 extensions and tries to remove them if possible. */
975 static void
976 find_and_remove_re (void)
978 ext_cand *curr_cand;
979 rtx curr_insn = NULL_RTX;
980 int num_re_opportunities = 0, num_realized = 0, i;
981 vec<ext_cand> reinsn_list;
982 auto_vec<rtx> reinsn_del_list;
983 auto_vec<rtx> reinsn_copy_list;
984 ext_state state;
986 /* Construct DU chain to get all reaching definitions of each
987 extension instruction. */
988 df_set_flags (DF_RD_PRUNE_DEAD_DEFS);
989 df_chain_add_problem (DF_UD_CHAIN + DF_DU_CHAIN);
990 df_analyze ();
991 df_set_flags (DF_DEFER_INSN_RESCAN);
993 max_insn_uid = get_max_uid ();
994 reinsn_list = find_removable_extensions ();
995 state.defs_list.create (0);
996 state.copies_list.create (0);
997 state.modified_list.create (0);
998 state.work_list.create (0);
999 if (reinsn_list.is_empty ())
1000 state.modified = NULL;
1001 else
1002 state.modified = XCNEWVEC (struct ext_modified, max_insn_uid);
1004 FOR_EACH_VEC_ELT (reinsn_list, i, curr_cand)
1006 num_re_opportunities++;
1008 /* Try to combine the extension with the definition. */
1009 if (dump_file)
1011 fprintf (dump_file, "Trying to eliminate extension:\n");
1012 print_rtl_single (dump_file, curr_cand->insn);
1015 if (combine_reaching_defs (curr_cand, curr_cand->expr, &state))
1017 if (dump_file)
1018 fprintf (dump_file, "Eliminated the extension.\n");
1019 num_realized++;
1020 /* If the RHS of the current candidate is not (extend (reg)), then
1021 we do not allow the optimization of extensions where
1022 the source and destination registers do not match. Thus
1023 checking REG_P here is correct. */
1024 if (REG_P (XEXP (SET_SRC (PATTERN (curr_cand->insn)), 0))
1025 && (REGNO (SET_DEST (PATTERN (curr_cand->insn)))
1026 != REGNO (XEXP (SET_SRC (PATTERN (curr_cand->insn)), 0))))
1028 reinsn_copy_list.safe_push (curr_cand->insn);
1029 reinsn_copy_list.safe_push (state.defs_list[0]);
1031 reinsn_del_list.safe_push (curr_cand->insn);
1032 state.modified[INSN_UID (curr_cand->insn)].deleted = 1;
1036 /* The copy list contains pairs of insns which describe copies we
1037 need to insert into the INSN stream.
1039 The first insn in each pair is the extension insn, from which
1040 we derive the source and destination of the copy.
1042 The second insn in each pair is the memory reference where the
1043 extension will ultimately happen. We emit the new copy
1044 immediately after this insn.
1046 It may first appear that the arguments for the copy are reversed.
1047 Remember that the memory reference will be changed to refer to the
1048 destination of the extention. So we're actually emitting a copy
1049 from the new destination to the old destination. */
1050 for (unsigned int i = 0; i < reinsn_copy_list.length (); i += 2)
1052 rtx curr_insn = reinsn_copy_list[i];
1053 rtx def_insn = reinsn_copy_list[i + 1];
1055 /* Use the mode of the destination of the defining insn
1056 for the mode of the copy. This is necessary if the
1057 defining insn was used to eliminate a second extension
1058 that was wider than the first. */
1059 rtx sub_rtx = *get_sub_rtx (def_insn);
1060 rtx pat = PATTERN (curr_insn);
1061 rtx new_dst = gen_rtx_REG (GET_MODE (SET_DEST (sub_rtx)),
1062 REGNO (XEXP (SET_SRC (pat), 0)));
1063 rtx new_src = gen_rtx_REG (GET_MODE (SET_DEST (sub_rtx)),
1064 REGNO (SET_DEST (pat)));
1065 rtx set = gen_rtx_SET (VOIDmode, new_dst, new_src);
1066 emit_insn_after (set, def_insn);
1069 /* Delete all useless extensions here in one sweep. */
1070 FOR_EACH_VEC_ELT (reinsn_del_list, i, curr_insn)
1071 delete_insn (curr_insn);
1073 reinsn_list.release ();
1074 state.defs_list.release ();
1075 state.copies_list.release ();
1076 state.modified_list.release ();
1077 state.work_list.release ();
1078 XDELETEVEC (state.modified);
1080 if (dump_file && num_re_opportunities > 0)
1081 fprintf (dump_file, "Elimination opportunities = %d realized = %d\n",
1082 num_re_opportunities, num_realized);
1085 /* Find and remove redundant extensions. */
1087 static unsigned int
1088 rest_of_handle_ree (void)
1090 timevar_push (TV_REE);
1091 find_and_remove_re ();
1092 timevar_pop (TV_REE);
1093 return 0;
1096 /* Run REE pass when flag_ree is set at optimization level > 0. */
1098 static bool
1099 gate_handle_ree (void)
1101 return (optimize > 0 && flag_ree);
1104 namespace {
1106 const pass_data pass_data_ree =
1108 RTL_PASS, /* type */
1109 "ree", /* name */
1110 OPTGROUP_NONE, /* optinfo_flags */
1111 true, /* has_gate */
1112 true, /* has_execute */
1113 TV_REE, /* tv_id */
1114 0, /* properties_required */
1115 0, /* properties_provided */
1116 0, /* properties_destroyed */
1117 0, /* todo_flags_start */
1118 ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
1121 class pass_ree : public rtl_opt_pass
1123 public:
1124 pass_ree (gcc::context *ctxt)
1125 : rtl_opt_pass (pass_data_ree, ctxt)
1128 /* opt_pass methods: */
1129 bool gate () { return gate_handle_ree (); }
1130 unsigned int execute () { return rest_of_handle_ree (); }
1132 }; // class pass_ree
1134 } // anon namespace
1136 rtl_opt_pass *
1137 make_pass_ree (gcc::context *ctxt)
1139 return new pass_ree (ctxt);