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Add support for interrupt function attribute
[official-gcc.git] / gcc / config / arm / arm.h
blob40287c8d99ecc0753975a58674156a6cb0c887ce
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef __ARM_H__
27 #define __ARM_H__
28
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
55
56 typedef enum arm_cond_code
57 {
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 }
61 arm_cc;
62
63 extern arm_cc arm_current_cc;
64 extern const char * arm_condition_codes[];
65
66 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
67
68 extern int arm_target_label;
69 extern int arm_ccfsm_state;
70 extern struct rtx_def * arm_target_insn;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75 /* Define the information needed to generate branch insns. This is
76 stored from the compare operation. Note that we can't use "rtx" here
77 since it hasn't been defined! */
78 extern struct rtx_def * arm_compare_op0;
79 extern struct rtx_def * arm_compare_op1;
80 /* The label of the current constant pool. */
81 extern struct rtx_def * pool_vector_label;
82 /* Set to 1 when a return insn is output, this means that the epilogue
83 is not needed. */
84 extern int return_used_this_function;
85 /* Nonzero if the prologue must setup `fp'. */
86 extern int current_function_anonymous_args;
87 \f
88 /* Just in case configure has failed to define anything. */
89 #ifndef TARGET_CPU_DEFAULT
90 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
91 #endif
92
93 /* If the configuration file doesn't specify the cpu, the subtarget may
94 override it. If it doesn't, then default to an ARM6. */
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
96 #undef TARGET_CPU_DEFAULT
97
98 #ifdef SUBTARGET_CPU_DEFAULT
99 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
100 #else
101 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
102 #endif
103 #endif
104
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
107 #else
108 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
109 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
110 #else
111 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
112 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
113 #else
114 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
115 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
116 #else
117 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
118 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
119 #else
120 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
121 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
122 #else
123 Unrecognized value in TARGET_CPU_DEFAULT.
124 #endif
125 #endif
126 #endif
127 #endif
128 #endif
129 #endif
130
131 #ifndef CPP_PREDEFINES
132 #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
133 #endif
134
135 #define CPP_SPEC "\
136 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
137 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
138
139 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
140
141 /* Set the architecture define -- if -march= is set, then it overrides
142 the -mcpu= setting. */
143 #define CPP_CPU_ARCH_SPEC "\
144 %{march=arm2:-D__ARM_ARCH_2__} \
145 %{march=arm250:-D__ARM_ARCH_2__} \
146 %{march=arm3:-D__ARM_ARCH_2__} \
147 %{march=arm6:-D__ARM_ARCH_3__} \
148 %{march=arm600:-D__ARM_ARCH_3__} \
149 %{march=arm610:-D__ARM_ARCH_3__} \
150 %{march=arm7:-D__ARM_ARCH_3__} \
151 %{march=arm700:-D__ARM_ARCH_3__} \
152 %{march=arm710:-D__ARM_ARCH_3__} \
153 %{march=arm720:-D__ARM_ARCH_3__} \
154 %{march=arm7100:-D__ARM_ARCH_3__} \
155 %{march=arm7500:-D__ARM_ARCH_3__} \
156 %{march=arm7500fe:-D__ARM_ARCH_3__} \
157 %{march=arm7m:-D__ARM_ARCH_3M__} \
158 %{march=arm7dm:-D__ARM_ARCH_3M__} \
159 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
160 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
161 %{march=arm8:-D__ARM_ARCH_4__} \
162 %{march=arm810:-D__ARM_ARCH_4__} \
163 %{march=arm9:-D__ARM_ARCH_4T__} \
164 %{march=arm920:-D__ARM_ARCH_4__} \
165 %{march=arm920t:-D__ARM_ARCH_4T__} \
166 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
167 %{march=strongarm:-D__ARM_ARCH_4__} \
168 %{march=strongarm110:-D__ARM_ARCH_4__} \
169 %{march=strongarm1100:-D__ARM_ARCH_4__} \
170 %{march=xscale:-D__ARM_ARCH_5TE__} \
171 %{march=xscale:-D__XSCALE__} \
172 %{march=armv2:-D__ARM_ARCH_2__} \
173 %{march=armv2a:-D__ARM_ARCH_2__} \
174 %{march=armv3:-D__ARM_ARCH_3__} \
175 %{march=armv3m:-D__ARM_ARCH_3M__} \
176 %{march=armv4:-D__ARM_ARCH_4__} \
177 %{march=armv4t:-D__ARM_ARCH_4T__} \
178 %{march=armv5:-D__ARM_ARCH_5__} \
179 %{march=armv5t:-D__ARM_ARCH_5T__} \
180 %{march=armv5e:-D__ARM_ARCH_5E__} \
181 %{march=armv5te:-D__ARM_ARCH_5TE__} \
182 %{!march=*: \
183 %{mcpu=arm2:-D__ARM_ARCH_2__} \
184 %{mcpu=arm250:-D__ARM_ARCH_2__} \
185 %{mcpu=arm3:-D__ARM_ARCH_2__} \
186 %{mcpu=arm6:-D__ARM_ARCH_3__} \
187 %{mcpu=arm600:-D__ARM_ARCH_3__} \
188 %{mcpu=arm610:-D__ARM_ARCH_3__} \
189 %{mcpu=arm7:-D__ARM_ARCH_3__} \
190 %{mcpu=arm700:-D__ARM_ARCH_3__} \
191 %{mcpu=arm710:-D__ARM_ARCH_3__} \
192 %{mcpu=arm720:-D__ARM_ARCH_3__} \
193 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
194 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
195 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
196 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
197 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
198 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
199 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm8:-D__ARM_ARCH_4__} \
201 %{mcpu=arm810:-D__ARM_ARCH_4__} \
202 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
203 %{mcpu=arm920:-D__ARM_ARCH_4__} \
204 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
205 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
206 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
207 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
208 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
209 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
210 %{mcpu=xscale:-D__XSCALE__} \
211 %{!mcpu*:%(cpp_cpu_arch_default)}} \
212 "
213
214 /* Define __APCS_26__ if the PC also contains the PSR */
215 #define CPP_APCS_PC_SPEC "\
216 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
217 -D__APCS_32__} \
218 %{mapcs-26:-D__APCS_26__} \
219 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
220 "
221
222 #ifndef CPP_APCS_PC_DEFAULT_SPEC
223 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
224 #endif
225
226 #define CPP_FLOAT_SPEC "\
227 %{msoft-float:\
228 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
229 -D__SOFTFP__} \
230 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
231 "
232
233 /* Default is hard float, which doesn't define anything */
234 #define CPP_FLOAT_DEFAULT_SPEC ""
235
236 #define CPP_ENDIAN_SPEC "\
237 %{mbig-endian: \
238 %{mlittle-endian: \
239 %e-mbig-endian and -mlittle-endian may not be used together} \
240 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
241 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
242 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
243 "
244
245 /* Default is little endian. */
246 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
247
248 /* Add a define for interworking. Needed when building libgcc.a.
249 This must define __THUMB_INTERWORK__ to the pre-processor if
250 interworking is enabled by default. */
251 #ifndef CPP_INTERWORK_DEFAULT_SPEC
252 #define CPP_INTERWORK_DEFAULT_SPEC ""
253 #endif
254
255 #define CPP_INTERWORK_SPEC " \
256 %{mthumb-interwork: \
257 %{mno-thumb-interwork: %eIncompatible interworking options} \
258 -D__THUMB_INTERWORK__} \
259 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
260 "
261
262 #define CC1_SPEC ""
263
264 /* This macro defines names of additional specifications to put in the specs
265 that can be used in various specifications like CC1_SPEC. Its definition
266 is an initializer with a subgrouping for each command option.
267
268 Each subgrouping contains a string constant, that defines the
269 specification name, and a string constant that used by the GNU CC driver
270 program.
271
272 Do not define this macro if it does not need to do anything. */
273 #define EXTRA_SPECS \
274 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
275 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
276 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
277 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
278 { "cpp_float", CPP_FLOAT_SPEC }, \
279 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
280 { "cpp_endian", CPP_ENDIAN_SPEC }, \
281 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
282 { "cpp_isa", CPP_ISA_SPEC }, \
283 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
284 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
285 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
286 SUBTARGET_EXTRA_SPECS
287
288 #ifndef SUBTARGET_EXTRA_SPECS
289 #define SUBTARGET_EXTRA_SPECS
290 #endif
291
292 #ifndef SUBTARGET_CPP_SPEC
293 #define SUBTARGET_CPP_SPEC ""
294 #endif
295 \f
296 /* Run-time Target Specification. */
297 #ifndef TARGET_VERSION
298 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
299 #endif
300
301 /* Nonzero if the function prologue (and epilogue) should obey
302 the ARM Procedure Call Standard. */
303 #define ARM_FLAG_APCS_FRAME (1 << 0)
304
305 /* Nonzero if the function prologue should output the function name to enable
306 the post mortem debugger to print a backtrace (very useful on RISCOS,
307 unused on RISCiX). Specifying this flag also enables
308 -fno-omit-frame-pointer.
309 XXX Must still be implemented in the prologue. */
310 #define ARM_FLAG_POKE (1 << 1)
311
312 /* Nonzero if floating point instructions are emulated by the FPE, in which
313 case instruction scheduling becomes very uninteresting. */
314 #define ARM_FLAG_FPE (1 << 2)
315
316 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
317 that assume restoration of the condition flags when returning from a
318 branch and link (ie a function). */
319 #define ARM_FLAG_APCS_32 (1 << 3)
320
321 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
322
323 /* Nonzero if stack checking should be performed on entry to each function
324 which allocates temporary variables on the stack. */
325 #define ARM_FLAG_APCS_STACK (1 << 4)
326
327 /* Nonzero if floating point parameters should be passed to functions in
328 floating point registers. */
329 #define ARM_FLAG_APCS_FLOAT (1 << 5)
330
331 /* Nonzero if re-entrant, position independent code should be generated.
332 This is equivalent to -fpic. */
333 #define ARM_FLAG_APCS_REENT (1 << 6)
334
335 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
336 be loaded using either LDRH or LDRB instructions. */
337 #define ARM_FLAG_MMU_TRAPS (1 << 7)
338
339 /* Nonzero if all floating point instructions are missing (and there is no
340 emulator either). Generate function calls for all ops in this case. */
341 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
342
343 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
344 #define ARM_FLAG_BIG_END (1 << 9)
345
346 /* Nonzero if we should compile for Thumb interworking. */
347 #define ARM_FLAG_INTERWORK (1 << 10)
348
349 /* Nonzero if we should have little-endian words even when compiling for
350 big-endian (for backwards compatibility with older versions of GCC). */
351 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
352
353 /* Nonzero if we need to protect the prolog from scheduling */
354 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
355
356 /* Nonzero if a call to abort should be generated if a noreturn
357 function tries to return. */
358 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
359
360 /* Nonzero if function prologues should not load the PIC register. */
361 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
362
363 /* Nonzero if all call instructions should be indirect. */
364 #define ARM_FLAG_LONG_CALLS (1 << 15)
365
366 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
367 #define ARM_FLAG_THUMB (1 << 16)
368
369 /* Set if a TPCS style stack frame should be generated, for non-leaf
370 functions, even if they do not need one. */
371 #define THUMB_FLAG_BACKTRACE (1 << 17)
372
373 /* Set if a TPCS style stack frame should be generated, for leaf
374 functions, even if they do not need one. */
375 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
376
377 /* Set if externally visible functions should assume that they
378 might be called in ARM mode, from a non-thumb aware code. */
379 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
380
381 /* Set if calls via function pointers should assume that their
382 destination is non-Thumb aware. */
383 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
384
385 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
386 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
387 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
388 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
389 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
390 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
391 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
392 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
393 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
394 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
395 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
396 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
397 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
398 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
399 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
400 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
401 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
402 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
403 #define TARGET_ARM (! TARGET_THUMB)
404 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
405 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
406 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
407 #define TARGET_BACKTRACE (leaf_function_p () \
408 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
409 : (target_flags & THUMB_FLAG_BACKTRACE))
410
411 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
412 Bit 31 is reserved. See riscix.h. */
413 #ifndef SUBTARGET_SWITCHES
414 #define SUBTARGET_SWITCHES
415 #endif
416
417 #define TARGET_SWITCHES \
418 { \
419 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
420 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
421 N_("Generate APCS conformant stack frames") }, \
422 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
423 {"poke-function-name", ARM_FLAG_POKE, \
424 N_("Store function names in object code") }, \
425 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
426 {"fpe", ARM_FLAG_FPE, "" }, \
427 {"apcs-32", ARM_FLAG_APCS_32, \
428 N_("Use the 32bit version of the APCS") }, \
429 {"apcs-26", -ARM_FLAG_APCS_32, \
430 N_("Use the 26bit version of the APCS") }, \
431 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
432 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
433 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
434 N_("Pass FP arguments in FP registers") }, \
435 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
436 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
437 N_("Generate re-entrant, PIC code") }, \
438 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
439 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
440 N_("The MMU will trap on unaligned accesses") }, \
441 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
442 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
443 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
444 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
446 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
447 N_("Use library calls to perform FP operations") }, \
448 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
449 N_("Use hardware floating point instructions") }, \
450 {"big-endian", ARM_FLAG_BIG_END, \
451 N_("Assume target CPU is configured as big endian") }, \
452 {"little-endian", -ARM_FLAG_BIG_END, \
453 N_("Assume target CPU is configured as little endian") }, \
454 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
455 N_("Assume big endian bytes, little endian words") }, \
456 {"thumb-interwork", ARM_FLAG_INTERWORK, \
457 N_("Support calls between THUMB and ARM instructions sets") }, \
458 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
459 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
460 N_("Generate a call to abort if a noreturn function returns")}, \
461 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
462 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
463 N_("Do not move instructions into a function's prologue") }, \
464 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
465 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
466 N_("Do not load the PIC register in function prologues") }, \
467 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
468 {"long-calls", ARM_FLAG_LONG_CALLS, \
469 N_("Generate call insns as indirect calls, if necessary") }, \
470 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
471 {"thumb", ARM_FLAG_THUMB, \
472 N_("Compile for the Thumb not the ARM") }, \
473 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
474 {"arm", -ARM_FLAG_THUMB, "" }, \
475 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
476 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
477 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
478 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
479 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
480 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
481 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
482 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
483 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
484 "" }, \
485 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
486 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
487 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
488 "" }, \
489 SUBTARGET_SWITCHES \
490 {"", TARGET_DEFAULT, "" } \
491 }
492
493 #define TARGET_OPTIONS \
494 { \
495 {"cpu=", & arm_select[0].string, \
496 N_("Specify the name of the target CPU") }, \
497 {"arch=", & arm_select[1].string, \
498 N_("Specify the name of the target architecture") }, \
499 {"tune=", & arm_select[2].string, "" }, \
500 {"fpe=", & target_fp_name, "" }, \
501 {"fp=", & target_fp_name, \
502 N_("Specify the version of the floating point emulator") }, \
503 {"structure-size-boundary=", & structure_size_string, \
504 N_("Specify the minimum bit alignment of structures") }, \
505 {"pic-register=", & arm_pic_register_string, \
506 N_("Specify the register to be used for PIC addressing") } \
507 }
508
509 struct arm_cpu_select
510 {
511 const char * string;
512 const char * name;
513 const struct processors * processors;
514 };
515
516 /* This is a magic array. If the user specifies a command line switch
517 which matches one of the entries in TARGET_OPTIONS then the corresponding
518 string pointer will be set to the value specified by the user. */
519 extern struct arm_cpu_select arm_select[];
520
521 enum prog_mode_type
522 {
523 prog_mode26,
524 prog_mode32
525 };
526
527 /* Recast the program mode class to be the prog_mode attribute */
528 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
529
530 extern enum prog_mode_type arm_prgmode;
531
532 /* What sort of floating point unit do we have? Hardware or software.
533 If software, is it issue 2 or issue 3? */
534 enum floating_point_type
535 {
536 FP_HARD,
537 FP_SOFT2,
538 FP_SOFT3
539 };
540
541 /* Recast the floating point class to be the floating point attribute. */
542 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
543
544 /* What type of floating point to tune for */
545 extern enum floating_point_type arm_fpu;
546
547 /* What type of floating point instructions are available */
548 extern enum floating_point_type arm_fpu_arch;
549
550 /* Default floating point architecture. Override in sub-target if
551 necessary. */
552 #define FP_DEFAULT FP_SOFT2
553
554 /* Nonzero if the processor has a fast multiply insn, and one that does
555 a 64-bit multiply of two 32-bit values. */
556 extern int arm_fast_multiply;
557
558 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
559 extern int arm_arch4;
560
561 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
562 extern int arm_arch5;
563
564 /* Nonzero if this chip can benefit from load scheduling. */
565 extern int arm_ld_sched;
566
567 /* Nonzero if generating thumb code. */
568 extern int thumb_code;
569
570 /* Nonzero if this chip is a StrongARM. */
571 extern int arm_is_strong;
572
573 /* Nonzero if this chip is an XScale. */
574 extern int arm_is_xscale;
575
576 /* Nonzero if this chip is a an ARM6 or an ARM7. */
577 extern int arm_is_6_or_7;
578
579 #ifndef TARGET_DEFAULT
580 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
581 #endif
582
583 /* The frame pointer register used in gcc has nothing to do with debugging;
584 that is controlled by the APCS-FRAME option. */
585 #define CAN_DEBUG_WITHOUT_FP
586
587 #define TARGET_MEM_FUNCTIONS 1
588
589 #define OVERRIDE_OPTIONS arm_override_options ()
590
591 /* Nonzero if PIC code requires explicit qualifiers to generate
592 PLT and GOT relocs rather than the assembler doing so implicitly.
593 Subtargets can override these if required. */
594 #ifndef NEED_GOT_RELOC
595 #define NEED_GOT_RELOC 0
596 #endif
597 #ifndef NEED_PLT_RELOC
598 #define NEED_PLT_RELOC 0
599 #endif
600
601 /* Nonzero if we need to refer to the GOT with a PC-relative
602 offset. In other words, generate
603
604 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
605
606 rather than
607
608 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
609
610 The default is true, which matches NetBSD. Subtargets can
611 override this if required. */
612 #ifndef GOT_PCREL
613 #define GOT_PCREL 1
614 #endif
615 \f
616 /* Target machine storage Layout. */
617
618
619 /* Define this macro if it is advisable to hold scalars in registers
620 in a wider mode than that declared by the program. In such cases,
621 the value is constrained to be within the bounds of the declared
622 type, but kept valid in the wider mode. The signedness of the
623 extension may differ from that of the type. */
624
625 /* It is far faster to zero extend chars than to sign extend them */
626
627 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
628 if (GET_MODE_CLASS (MODE) == MODE_INT \
629 && GET_MODE_SIZE (MODE) < 4) \
630 { \
631 if (MODE == QImode) \
632 UNSIGNEDP = 1; \
633 else if (MODE == HImode) \
634 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
635 (MODE) = SImode; \
636 }
637
638 /* Define this macro if the promotion described by `PROMOTE_MODE'
639 should also be done for outgoing function arguments. */
640 /* This is required to ensure that push insns always push a word. */
641 #define PROMOTE_FUNCTION_ARGS
642
643 /* Define for XFmode extended real floating point support.
644 This will automatically cause REAL_ARITHMETIC to be defined. */
645 /* For the ARM:
646 I think I have added all the code to make this work. Unfortunately,
647 early releases of the floating point emulation code on RISCiX used a
648 different format for extended precision numbers. On my RISCiX box there
649 is a bug somewhere which causes the machine to lock up when running enquire
650 with long doubles. There is the additional aspect that Norcroft C
651 treats long doubles as doubles and we ought to remain compatible.
652 Perhaps someone with an FPA coprocessor and not running RISCiX would like
653 to try this someday. */
654 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
655
656 /* Disable XFmode patterns in md file */
657 #define ENABLE_XF_PATTERNS 0
658
659 /* Define if you don't want extended real, but do want to use the
660 software floating point emulator for REAL_ARITHMETIC and
661 decimal <-> binary conversion. */
662 /* See comment above */
663 #define REAL_ARITHMETIC
664
665 /* Define this if most significant bit is lowest numbered
666 in instructions that operate on numbered bit-fields. */
667 #define BITS_BIG_ENDIAN 0
668
669 /* Define this if most significant byte of a word is the lowest numbered.
670 Most ARM processors are run in little endian mode, so that is the default.
671 If you want to have it run-time selectable, change the definition in a
672 cover file to be TARGET_BIG_ENDIAN. */
673 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
674
675 /* Define this if most significant word of a multiword number is the lowest
676 numbered.
677 This is always false, even when in big-endian mode. */
678 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
679
680 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
681 on processor pre-defineds when compiling libgcc2.c. */
682 #if defined(__ARMEB__) && !defined(__ARMWEL__)
683 #define LIBGCC2_WORDS_BIG_ENDIAN 1
684 #else
685 #define LIBGCC2_WORDS_BIG_ENDIAN 0
686 #endif
687
688 /* Define this if most significant word of doubles is the lowest numbered.
689 This is always true, even when in little-endian mode. */
690 #define FLOAT_WORDS_BIG_ENDIAN 1
691
692 /* Number of bits in an addressable storage unit */
693 #define BITS_PER_UNIT 8
694
695 #define BITS_PER_WORD 32
696
697 #define UNITS_PER_WORD 4
698
699 #define POINTER_SIZE 32
700
701 #define PARM_BOUNDARY 32
702
703 #define STACK_BOUNDARY 32
704
705 #define FUNCTION_BOUNDARY 32
706
707 #define EMPTY_FIELD_BOUNDARY 32
708
709 #define BIGGEST_ALIGNMENT 32
710
711 /* Make strings word-aligned so strcpy from constants will be faster. */
712 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
713
714 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
715 ((TREE_CODE (EXP) == STRING_CST \
716 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
717 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
718
719 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
720 value set in previous versions of this toolchain was 8, which produces more
721 compact structures. The command line option -mstructure_size_boundary=<n>
722 can be used to change this value. For compatability with the ARM SDK
723 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
724 0020D) page 2-20 says "Structures are aligned on word boundaries". */
725 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
726 extern int arm_structure_size_boundary;
727
728 /* This is the value used to initialise arm_structure_size_boundary. If a
729 particular arm target wants to change the default value it should change
730 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
731 for an example of this. */
732 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
733 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
734 #endif
735
736 /* Used when parsing command line option -mstructure_size_boundary. */
737 extern const char * structure_size_string;
738
739 /* Non-zero if move instructions will actually fail to work
740 when given unaligned data. */
741 #define STRICT_ALIGNMENT 1
742
743 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
744
745 \f
746 /* Standard register usage. */
747
748 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
749 (S - saved over call).
750
751 r0 * argument word/integer result
752 r1-r3 argument word
753
754 r4-r8 S register variable
755 r9 S (rfp) register variable (real frame pointer)
756
757 r10 F S (sl) stack limit (used by -mapcs-stack-check)
758 r11 F S (fp) argument pointer
759 r12 (ip) temp workspace
760 r13 F S (sp) lower end of current stack frame
761 r14 (lr) link address/workspace
762 r15 F (pc) program counter
763
764 f0 floating point result
765 f1-f3 floating point scratch
766
767 f4-f7 S floating point variable
768
769 cc This is NOT a real register, but is used internally
770 to represent things that use or set the condition
771 codes.
772 sfp This isn't either. It is used during rtl generation
773 since the offset between the frame pointer and the
774 auto's isn't known until after register allocation.
775 afp Nor this, we only need this because of non-local
776 goto. Without it fp appears to be used and the
777 elimination code won't get rid of sfp. It tracks
778 fp exactly at all times.
779
780 *: See CONDITIONAL_REGISTER_USAGE */
781
782 /* The stack backtrace structure is as follows:
783 fp points to here: | save code pointer | [fp]
784 | return link value | [fp, #-4]
785 | return sp value | [fp, #-8]
786 | return fp value | [fp, #-12]
787 [| saved r10 value |]
788 [| saved r9 value |]
789 [| saved r8 value |]
790 [| saved r7 value |]
791 [| saved r6 value |]
792 [| saved r5 value |]
793 [| saved r4 value |]
794 [| saved r3 value |]
795 [| saved r2 value |]
796 [| saved r1 value |]
797 [| saved r0 value |]
798 [| saved f7 value |] three words
799 [| saved f6 value |] three words
800 [| saved f5 value |] three words
801 [| saved f4 value |] three words
802 r0-r3 are not normally saved in a C function. */
803
804 /* 1 for registers that have pervasive standard uses
805 and are not available for the register allocator. */
806 #define FIXED_REGISTERS \
807 { \
808 0,0,0,0,0,0,0,0, \
809 0,0,0,0,0,1,0,1, \
810 0,0,0,0,0,0,0,0, \
811 1,1,1 \
812 }
813
814 /* 1 for registers not available across function calls.
815 These must include the FIXED_REGISTERS and also any
816 registers that can be used without being saved.
817 The latter must include the registers where values are returned
818 and the register where structure-value addresses are passed.
819 Aside from that, you can include as many other registers as you like.
820 The CC is not preserved over function calls on the ARM 6, so it is
821 easier to assume this for all. SFP is preserved, since FP is. */
822 #define CALL_USED_REGISTERS \
823 { \
824 1,1,1,1,0,0,0,0, \
825 0,0,0,0,1,1,1,1, \
826 1,1,1,1,0,0,0,0, \
827 1,1,1 \
828 }
829
830 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
831 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
832 #endif
833
834 #define CONDITIONAL_REGISTER_USAGE \
835 { \
836 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
837 { \
838 int regno; \
839 for (regno = FIRST_ARM_FP_REGNUM; \
840 regno <= LAST_ARM_FP_REGNUM; ++regno) \
841 fixed_regs[regno] = call_used_regs[regno] = 1; \
842 } \
843 if (flag_pic) \
844 { \
845 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
846 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
847 } \
848 else if (TARGET_APCS_STACK) \
849 { \
850 fixed_regs[10] = 1; \
851 call_used_regs[10] = 1; \
852 } \
853 if (TARGET_APCS_FRAME) \
854 { \
855 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
856 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
857 } \
858 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
859 }
860
861 /* These are a couple of extensions to the formats accecpted
862 by asm_fprintf:
863 %@ prints out ASM_COMMENT_START
864 %r prints out REGISTER_PREFIX reg_names[arg] */
865 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
866 case '@': \
867 fputs (ASM_COMMENT_START, FILE); \
868 break; \
869 \
870 case 'r': \
871 fputs (REGISTER_PREFIX, FILE); \
872 fputs (reg_names [va_arg (ARGS, int)], FILE); \
873 break;
874
875 /* Round X up to the nearest word. */
876 #define ROUND_UP(X) (((X) + 3) & ~3)
877
878 /* Convert fron bytes to ints. */
879 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
880
881 /* The number of (integer) registers required to hold a quantity of type MODE. */
882 #define NUM_REGS(MODE) \
883 NUM_INTS (GET_MODE_SIZE (MODE))
884
885 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
886 #define NUM_REGS2(MODE, TYPE) \
887 NUM_INTS ((MODE) == BLKmode ? \
888 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
889
890 /* The number of (integer) argument register available. */
891 #define NUM_ARG_REGS 4
892
893 /* Return the regiser number of the N'th (integer) argument. */
894 #define ARG_REGISTER(N) (N - 1)
895
896 /* RTX for structure returns. NULL means use a hidden first argument. */
897 #define STRUCT_VALUE 0
898
899 /* Specify the registers used for certain standard purposes.
900 The values of these macros are register numbers. */
901
902 /* The number of the last argument register. */
903 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
904
905 /* The number of the last "lo" register (thumb). */
906 #define LAST_LO_REGNUM 7
907
908 /* The register that holds the return address in exception handlers. */
909 #define EXCEPTION_LR_REGNUM 2
910
911 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
912 as an invisible last argument (possible since varargs don't exist in
913 Pascal), so the following is not true. */
914 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
915
916 /* Define this to be where the real frame pointer is if it is not possible to
917 work out the offset between the frame pointer and the automatic variables
918 until after register allocation has taken place. FRAME_POINTER_REGNUM
919 should point to a special register that we will make sure is eliminated.
920
921 For the Thumb we have another problem. The TPCS defines the frame pointer
922 as r11, and GCC belives that it is always possible to use the frame pointer
923 as base register for addressing purposes. (See comments in
924 find_reloads_address()). But - the Thumb does not allow high registers,
925 including r11, to be used as base address registers. Hence our problem.
926
927 The solution used here, and in the old thumb port is to use r7 instead of
928 r11 as the hard frame pointer and to have special code to generate
929 backtrace structures on the stack (if required to do so via a command line
930 option) using r11. This is the only 'user visable' use of r11 as a frame
931 pointer. */
932 #define ARM_HARD_FRAME_POINTER_REGNUM 11
933 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
934 #define HARD_FRAME_POINTER_REGNUM (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM)
935 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
936
937 /* Scratch register - used in all kinds of places, eg trampolines. */
938 #define IP_REGNUM 12
939
940 /* Register to use for pushing function arguments. */
941 #define STACK_POINTER_REGNUM 13
942 #define SP_REGNUM STACK_POINTER_REGNUM
943
944 /* Register which holds return address from a subroutine call. */
945 #define LR_REGNUM 14
946
947 /* Define this if the program counter is overloaded on a register. */
948 #define PC_REGNUM 15
949
950 /* The number of the last ARM (integer) register. */
951 #define LAST_ARM_REGNUM 15
952
953 /* ARM floating pointer registers. */
954 #define FIRST_ARM_FP_REGNUM 16
955 #define LAST_ARM_FP_REGNUM 23
956
957 /* Internal, so that we don't need to refer to a raw number */
958 #define CC_REGNUM 24
959
960 /* Base register for access to local variables of the function. */
961 #define FRAME_POINTER_REGNUM 25
962
963 /* Base register for access to arguments of the function. */
964 #define ARG_POINTER_REGNUM 26
965
966 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
967 #define FIRST_PSEUDO_REGISTER 27
968
969 /* Value should be nonzero if functions must have frame pointers.
970 Zero means the frame pointer need not be set up (and parms may be accessed
971 via the stack pointer) in functions that seem suitable.
972 If we have to have a frame pointer we might as well make use of it.
973 APCS says that the frame pointer does not need to be pushed in leaf
974 functions, or simple tail call functions. */
975 #define FRAME_POINTER_REQUIRED \
976 (current_function_has_nonlocal_label \
977 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
978
979 /* Return number of consecutive hard regs needed starting at reg REGNO
980 to hold something of mode MODE.
981 This is ordinarily the length in words of a value of mode MODE
982 but can be less for certain modes in special long registers.
983
984 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
985 mode. */
986 #define HARD_REGNO_NREGS(REGNO, MODE) \
987 ((TARGET_ARM \
988 && REGNO >= FIRST_ARM_FP_REGNUM \
989 && REGNO != FRAME_POINTER_REGNUM \
990 && REGNO != ARG_POINTER_REGNUM) \
991 ? 1 : NUM_REGS (MODE))
992
993 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
994 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
995 regs holding FP.
996 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
997 so that there is always a second lo register available to hold the upper
998 part of the value. Probably we ought to ensure that the register is the
999 start of an even numbered register pair. */
1000 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1001 (TARGET_ARM ? \
1002 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1003 ( REGNO <= LAST_ARM_REGNUM \
1004 || REGNO == FRAME_POINTER_REGNUM \
1005 || REGNO == ARG_POINTER_REGNUM \
1006 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1007 : \
1008 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1009 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
1010
1011 /* Value is 1 if it is a good idea to tie two pseudo registers
1012 when one has mode MODE1 and one has mode MODE2.
1013 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1014 for any hard reg, then this must be 0 for correct output. */
1015 #define MODES_TIEABLE_P(MODE1, MODE2) \
1016 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1017
1018 /* The order in which register should be allocated. It is good to use ip
1019 since no saving is required (though calls clobber it) and it never contains
1020 function parameters. It is quite good to use lr since other calls may
1021 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1022 least likely to contain a function parameter; in addition results are
1023 returned in r0. */
1024 #define REG_ALLOC_ORDER \
1025 { \
1026 3, 2, 1, 0, 12, 14, 4, 5, \
1027 6, 7, 8, 10, 9, 11, 13, 15, \
1028 16, 17, 18, 19, 20, 21, 22, 23, \
1029 24, 25, 26 \
1030 }
1031 \f
1032 /* Register and constant classes. */
1033
1034 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1035 Now that the Thumb is involved it has become more compilcated. */
1036 enum reg_class
1037 {
1038 NO_REGS,
1039 FPU_REGS,
1040 LO_REGS,
1041 STACK_REG,
1042 BASE_REGS,
1043 HI_REGS,
1044 CC_REG,
1045 GENERAL_REGS,
1046 ALL_REGS,
1047 LIM_REG_CLASSES
1048 };
1049
1050 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1051
1052 /* Give names of register classes as strings for dump file. */
1053 #define REG_CLASS_NAMES \
1054 { \
1055 "NO_REGS", \
1056 "FPU_REGS", \
1057 "LO_REGS", \
1058 "STACK_REG", \
1059 "BASE_REGS", \
1060 "HI_REGS", \
1061 "CC_REG", \
1062 "GENERAL_REGS", \
1063 "ALL_REGS", \
1064 }
1065
1066 /* Define which registers fit in which classes.
1067 This is an initializer for a vector of HARD_REG_SET
1068 of length N_REG_CLASSES. */
1069 #define REG_CLASS_CONTENTS \
1070 { \
1071 { 0x0000000 }, /* NO_REGS */ \
1072 { 0x0FF0000 }, /* FPU_REGS */ \
1073 { 0x00000FF }, /* LO_REGS */ \
1074 { 0x0002000 }, /* STACK_REG */ \
1075 { 0x00020FF }, /* BASE_REGS */ \
1076 { 0x000FF00 }, /* HI_REGS */ \
1077 { 0x1000000 }, /* CC_REG */ \
1078 { 0x200FFFF }, /* GENERAL_REGS */ \
1079 { 0x2FFFFFF } /* ALL_REGS */ \
1080 }
1081
1082 /* The same information, inverted:
1083 Return the class number of the smallest class containing
1084 reg number REGNO. This could be a conditional expression
1085 or could index an array. */
1086 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1087
1088 /* The class value for index registers, and the one for base regs. */
1089 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1090 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1091
1092 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1093 registers explicitly used in the rtl to be used as spill registers
1094 but prevents the compiler from extending the lifetime of these
1095 registers. */
1096 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1097
1098 /* Get reg_class from a letter such as appears in the machine description.
1099 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1100 ARM, but several more letters for the Thumb. */
1101 #define REG_CLASS_FROM_LETTER(C) \
1102 ( (C) == 'f' ? FPU_REGS \
1103 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1104 : TARGET_ARM ? NO_REGS \
1105 : (C) == 'h' ? HI_REGS \
1106 : (C) == 'b' ? BASE_REGS \
1107 : (C) == 'k' ? STACK_REG \
1108 : (C) == 'c' ? CC_REG \
1109 : NO_REGS)
1110
1111 /* The letters I, J, K, L and M in a register constraint string
1112 can be used to stand for particular ranges of immediate operands.
1113 This macro defines what the ranges are.
1114 C is the letter, and VALUE is a constant value.
1115 Return 1 if VALUE is in the range specified by C.
1116 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1117 J: valid indexing constants.
1118 K: ~value ok in rhs argument of data operand.
1119 L: -value ok in rhs argument of data operand.
1120 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1121 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1122 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1123 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1124 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1125 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1126 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1127 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1128 : 0)
1129
1130 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1131 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1132 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1133 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1134 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1135 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1136 && ((VAL) & 3) == 0) : \
1137 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1138 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1139 : 0)
1140
1141 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1142 (TARGET_ARM ? \
1143 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1144
1145 /* Constant letter 'G' for the FPU immediate constants.
1146 'H' means the same constant negated. */
1147 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1148 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1149 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1150
1151 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1152 (TARGET_ARM ? \
1153 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1154
1155 /* For the ARM, `Q' means that this is a memory operand that is just
1156 an offset from a register.
1157 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1158 address. This means that the symbol is in the text segment and can be
1159 accessed without using a load. */
1160
1161 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1162 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1163 (C) == 'R' ? (GET_CODE (OP) == MEM \
1164 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1165 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1166 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1167 : 0)
1168
1169 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1170 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1171 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1172
1173 #define EXTRA_CONSTRAINT(X, C) \
1174 (TARGET_ARM ? \
1175 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1176
1177 /* Given an rtx X being reloaded into a reg required to be
1178 in class CLASS, return the class of reg to actually use.
1179 In general this is just CLASS, but for the Thumb we prefer
1180 a LO_REGS class or a subset. */
1181 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1182 (TARGET_ARM ? (CLASS) : \
1183 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1184
1185 /* Must leave BASE_REGS reloads alone */
1186 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1187 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1188 ? ((true_regnum (X) == -1 ? LO_REGS \
1189 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1190 : NO_REGS)) \
1191 : NO_REGS)
1192
1193 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1194 ((CLASS) != LO_REGS \
1195 ? ((true_regnum (X) == -1 ? LO_REGS \
1196 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1197 : NO_REGS)) \
1198 : NO_REGS)
1199
1200 /* Return the register class of a scratch register needed to copy IN into
1201 or out of a register in CLASS in MODE. If it can be done directly,
1202 NO_REGS is returned. */
1203 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1204 (TARGET_ARM ? \
1205 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1206 ? GENERAL_REGS : NO_REGS) \
1207 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1208
1209 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1210 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1211 (TARGET_ARM ? \
1212 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1213 && (GET_CODE (X) == MEM \
1214 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1215 && true_regnum (X) == -1))) \
1216 ? GENERAL_REGS : NO_REGS) \
1217 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1218
1219 /* Try a machine-dependent way of reloading an illegitimate address
1220 operand. If we find one, push the reload and jump to WIN. This
1221 macro is used in only one place: `find_reloads_address' in reload.c.
1222
1223 For the ARM, we wish to handle large displacements off a base
1224 register by splitting the addend across a MOV and the mem insn.
1225 This can cut the number of reloads needed. */
1226 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1227 do \
1228 { \
1229 if (GET_CODE (X) == PLUS \
1230 && GET_CODE (XEXP (X, 0)) == REG \
1231 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1232 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1233 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1234 { \
1235 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1236 HOST_WIDE_INT low, high; \
1237 \
1238 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1239 low = ((val & 0xf) ^ 0x8) - 0x8; \
1240 else if (MODE == SImode \
1241 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1242 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1243 /* Need to be careful, -4096 is not a valid offset. */ \
1244 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1245 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1246 /* Need to be careful, -256 is not a valid offset. */ \
1247 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1248 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1249 && TARGET_HARD_FLOAT) \
1250 /* Need to be careful, -1024 is not a valid offset. */ \
1251 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1252 else \
1253 break; \
1254 \
1255 high = ((((val - low) & HOST_UINT (0xffffffff)) \
1256 ^ HOST_UINT (0x80000000)) \
1257 - HOST_UINT (0x80000000)); \
1258 /* Check for overflow or zero */ \
1259 if (low == 0 || high == 0 || (high + low != val)) \
1260 break; \
1261 \
1262 /* Reload the high part into a base reg; leave the low part \
1263 in the mem. */ \
1264 X = gen_rtx_PLUS (GET_MODE (X), \
1265 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1266 GEN_INT (high)), \
1267 GEN_INT (low)); \
1268 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1269 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1270 OPNUM, TYPE); \
1271 goto WIN; \
1272 } \
1273 } \
1274 while (0)
1275
1276 /* ??? If an HImode FP+large_offset address is converted to an HImode
1277 SP+large_offset address, then reload won't know how to fix it. It sees
1278 only that SP isn't valid for HImode, and so reloads the SP into an index
1279 register, but the resulting address is still invalid because the offset
1280 is too big. We fix it here instead by reloading the entire address. */
1281 /* We could probably achieve better results by defining PROMOTE_MODE to help
1282 cope with the variances between the Thumb's signed and unsigned byte and
1283 halfword load instructions. */
1284 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1285 { \
1286 if (GET_CODE (X) == PLUS \
1287 && GET_MODE_SIZE (MODE) < 4 \
1288 && GET_CODE (XEXP (X, 0)) == REG \
1289 && XEXP (X, 0) == stack_pointer_rtx \
1290 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1291 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1292 { \
1293 rtx orig_X = X; \
1294 X = copy_rtx (X); \
1295 push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \
1296 BASE_REG_CLASS, \
1297 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1298 goto WIN; \
1299 } \
1300 }
1301
1302 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1303 if (TARGET_ARM) \
1304 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1305 else \
1306 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1307
1308 /* Return the maximum number of consecutive registers
1309 needed to represent mode MODE in a register of class CLASS.
1310 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1311 #define CLASS_MAX_NREGS(CLASS, MODE) \
1312 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1313
1314 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1315 #define REGISTER_MOVE_COST(FROM, TO) \
1316 (TARGET_ARM ? \
1317 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1318 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1319 : \
1320 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1321 \f
1322 /* Stack layout; function entry, exit and calling. */
1323
1324 /* Define this if pushing a word on the stack
1325 makes the stack pointer a smaller address. */
1326 #define STACK_GROWS_DOWNWARD 1
1327
1328 /* Define this if the nominal address of the stack frame
1329 is at the high-address end of the local variables;
1330 that is, each additional local variable allocated
1331 goes at a more negative offset in the frame. */
1332 #define FRAME_GROWS_DOWNWARD 1
1333
1334 /* Offset within stack frame to start allocating local variables at.
1335 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1336 first local allocated. Otherwise, it is the offset to the BEGINNING
1337 of the first local allocated. */
1338 #define STARTING_FRAME_OFFSET 0
1339
1340 /* If we generate an insn to push BYTES bytes,
1341 this says how many the stack pointer really advances by. */
1342 /* The push insns do not do this rounding implicitly.
1343 So don't define this. */
1344 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1345
1346 /* Define this if the maximum size of all the outgoing args is to be
1347 accumulated and pushed during the prologue. The amount can be
1348 found in the variable current_function_outgoing_args_size. */
1349 #define ACCUMULATE_OUTGOING_ARGS 1
1350
1351 /* Offset of first parameter from the argument pointer register value. */
1352 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1353
1354 /* Value is the number of byte of arguments automatically
1355 popped when returning from a subroutine call.
1356 FUNDECL is the declaration node of the function (as a tree),
1357 FUNTYPE is the data type of the function (as a tree),
1358 or for a library call it is an identifier node for the subroutine name.
1359 SIZE is the number of bytes of arguments passed on the stack.
1360
1361 On the ARM, the caller does not pop any of its arguments that were passed
1362 on the stack. */
1363 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1364
1365 /* Define how to find the value returned by a library function
1366 assuming the value has mode MODE. */
1367 #define LIBCALL_VALUE(MODE) \
1368 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1369 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1370 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1371
1372 /* Define how to find the value returned by a function.
1373 VALTYPE is the data type of the value (as a tree).
1374 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1375 otherwise, FUNC is 0. */
1376 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1377 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1378
1379 /* 1 if N is a possible register number for a function value.
1380 On the ARM, only r0 and f0 can return results. */
1381 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1382 ((REGNO) == ARG_REGISTER (1) \
1383 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1384
1385 /* How large values are returned */
1386 /* A C expression which can inhibit the returning of certain function values
1387 in registers, based on the type of value. */
1388 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1389
1390 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1391 values must be in memory. On the ARM, they need only do so if larger
1392 than a word, or if they contain elements offset from zero in the struct. */
1393 #define DEFAULT_PCC_STRUCT_RETURN 0
1394
1395 /* Flags for the call/call_value rtl operations set up by function_arg. */
1396 #define CALL_NORMAL 0x00000000 /* No special processing. */
1397 #define CALL_LONG 0x00000001 /* Always call indirect. */
1398 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1399
1400 /* These bits describe the different types of function supported
1401 by the ARM backend. They are exclusive. ie a function cannot be both a
1402 normal function and an interworked function, for example. Knowing the
1403 type of a function is important for determining its prologue and
1404 epilogue sequences.
1405 Note value 7 is currently unassigned. Also note that the interrupt
1406 function types all have bit 2 set, so that they can be tested for easily.
1407 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1408 machine_function structure is initialised (to zero) func_type will
1409 default to unknown. This will force the first use of arm_current_func_type
1410 to call arm_compute_func_type. */
1411 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1412 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1413 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1414 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1415 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1416 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1417 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1418
1419 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1420
1421 /* In addition functions can have several type modifiers,
1422 outlined by these bit masks: */
1423 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1424 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1425 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1426 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1427
1428 /* Some macros to test these flags. */
1429 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1430 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1431 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1432 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1433 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1434
1435 /* A C structure for machine-specific, per-function data.
1436 This is added to the cfun structure. */
1437 typedef struct machine_function
1438 {
1439 /* Records __builtin_return address. */
1440 struct rtx_def *ra_rtx;
1441 /* Additionsl stack adjustment in __builtin_eh_throw. */
1442 struct rtx_def *eh_epilogue_sp_ofs;
1443 /* Records if LR has to be saved for far jumps. */
1444 int far_jump_used;
1445 /* Records if ARG_POINTER was ever live. */
1446 int arg_pointer_live;
1447 /* Records the type of the current function. */
1448 unsigned long func_type;
1449 }
1450 machine_function;
1451
1452 /* A C type for declaring a variable that is used as the first argument of
1453 `FUNCTION_ARG' and other related values. For some target machines, the
1454 type `int' suffices and can hold the number of bytes of argument so far. */
1455 typedef struct
1456 {
1457 /* This is the number of registers of arguments scanned so far. */
1458 int nregs;
1459 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1460 int call_cookie;
1461 } CUMULATIVE_ARGS;
1462
1463 /* Define where to put the arguments to a function.
1464 Value is zero to push the argument on the stack,
1465 or a hard register in which to store the argument.
1466
1467 MODE is the argument's machine mode.
1468 TYPE is the data type of the argument (as a tree).
1469 This is null for libcalls where that information may
1470 not be available.
1471 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1472 the preceding args and about the function being called.
1473 NAMED is nonzero if this argument is a named parameter
1474 (otherwise it is an extra parameter matching an ellipsis).
1475
1476 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1477 other arguments are passed on the stack. If (NAMED == 0) (which happens
1478 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1479 passed in the stack (function_prologue will indeed make it pass in the
1480 stack if necessary). */
1481 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1482 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1483
1484 /* For an arg passed partly in registers and partly in memory,
1485 this is the number of registers used.
1486 For args passed entirely in registers or entirely in memory, zero. */
1487 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1488 ( NUM_ARG_REGS > (CUM).nregs \
1489 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1490 ? NUM_ARG_REGS - (CUM).nregs : 0)
1491
1492 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1493 for a call to a function whose data type is FNTYPE.
1494 For a library call, FNTYPE is 0.
1495 On the ARM, the offset starts at 0. */
1496 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1497 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1498
1499 /* Update the data in CUM to advance over an argument
1500 of mode MODE and data type TYPE.
1501 (TYPE is null for libcalls where that information may not be available.) */
1502 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1503 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1504
1505 /* 1 if N is a possible register number for function argument passing.
1506 On the ARM, r0-r3 are used to pass args. */
1507 #define FUNCTION_ARG_REGNO_P(REGNO) \
1508 ((REGNO) >= 0 && (REGNO) <= 3)
1509
1510 \f
1511 /* Tail calling. */
1512
1513 /* A C expression that evaluates to true if it is ok to perform a sibling
1514 call to DECL. */
1515 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1516
1517 /* Perform any actions needed for a function that is receiving a variable
1518 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1519 of the current parameter. PRETEND_SIZE is a variable that should be set to
1520 the amount of stack that must be pushed by the prolog to pretend that our
1521 caller pushed it.
1522
1523 Normally, this macro will push all remaining incoming registers on the
1524 stack and set PRETEND_SIZE to the length of the registers pushed.
1525
1526 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1527 named arg and all anonymous args onto the stack.
1528 XXX I know the prologue shouldn't be pushing registers, but it is faster
1529 that way. */
1530 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1531 { \
1532 extern int current_function_anonymous_args; \
1533 current_function_anonymous_args = 1; \
1534 if ((CUM).nregs < NUM_ARG_REGS) \
1535 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1536 }
1537
1538 /* Generate assembly output for the start of a function. */
1539 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1540 do \
1541 { \
1542 if (TARGET_ARM) \
1543 output_arm_prologue (STREAM, SIZE); \
1544 else \
1545 output_thumb_prologue (STREAM); \
1546 } \
1547 while (0)
1548
1549 /* If your target environment doesn't prefix user functions with an
1550 underscore, you may wish to re-define this to prevent any conflicts.
1551 e.g. AOF may prefix mcount with an underscore. */
1552 #ifndef ARM_MCOUNT_NAME
1553 #define ARM_MCOUNT_NAME "*mcount"
1554 #endif
1555
1556 /* Call the function profiler with a given profile label. The Acorn
1557 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1558 On the ARM the full profile code will look like:
1559 .data
1560 LP1
1561 .word 0
1562 .text
1563 mov ip, lr
1564 bl mcount
1565 .word LP1
1566
1567 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1568 will output the .text section.
1569
1570 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1571 ``prof'' doesn't seem to mind about this! */
1572 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1573 { \
1574 char temp[20]; \
1575 rtx sym; \
1576 \
1577 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1578 IP_REGNUM, LR_REGNUM); \
1579 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1580 fputc ('\n', STREAM); \
1581 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1582 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1583 ASM_OUTPUT_INT (STREAM, sym); \
1584 }
1585
1586 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1587 { \
1588 fprintf (STREAM, "\tmov\\tip, lr\n"); \
1589 fprintf (STREAM, "\tbl\tmcount\n"); \
1590 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1591 }
1592
1593 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1594 if (TARGET_ARM) \
1595 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1596 else \
1597 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1598
1599 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1600 the stack pointer does not matter. The value is tested only in
1601 functions that have frame pointers.
1602 No definition is equivalent to always zero.
1603
1604 On the ARM, the function epilogue recovers the stack pointer from the
1605 frame. */
1606 #define EXIT_IGNORE_STACK 1
1607
1608 /* Generate the assembly code for function exit. */
1609 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1610 output_func_epilogue (SIZE)
1611
1612 /* Determine if the epilogue should be output as RTL.
1613 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1614 #define USE_RETURN_INSN(ISCOND) \
1615 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1616
1617 /* Definitions for register eliminations.
1618
1619 This is an array of structures. Each structure initializes one pair
1620 of eliminable registers. The "from" register number is given first,
1621 followed by "to". Eliminations of the same "from" register are listed
1622 in order of preference.
1623
1624 We have two registers that can be eliminated on the ARM. First, the
1625 arg pointer register can often be eliminated in favor of the stack
1626 pointer register. Secondly, the pseudo frame pointer register can always
1627 be eliminated; it is replaced with either the stack or the real frame
1628 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1629 because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */
1630
1631 #define ELIMINABLE_REGS \
1632 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1633 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1634 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1635 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1636 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1637 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1638 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1639
1640 /* Given FROM and TO register numbers, say whether this elimination is
1641 allowed. Frame pointer elimination is automatically handled.
1642
1643 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1644 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1645 pointer, we must eliminate FRAME_POINTER_REGNUM into
1646 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1647 ARG_POINTER_REGNUM. */
1648 #define CAN_ELIMINATE(FROM, TO) \
1649 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1650 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1651 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1652 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1653 1)
1654
1655 /* Define the offset between two registers, one to be eliminated, and the
1656 other its replacement, at the start of a routine. */
1657 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1658 { \
1659 int volatile_func = IS_VOLATILE (arm_current_func_type ()); \
1660 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1661 { \
1662 if (! current_function_needs_context || ! frame_pointer_needed) \
1663 (OFFSET) = 0; \
1664 else \
1665 (OFFSET) = 4; \
1666 } \
1667 else if ((FROM) == FRAME_POINTER_REGNUM \
1668 && (TO) == STACK_POINTER_REGNUM) \
1669 (OFFSET) = current_function_outgoing_args_size \
1670 + ROUND_UP (get_frame_size ()); \
1671 else \
1672 { \
1673 int regno; \
1674 int offset = 12; \
1675 int saved_hard_reg = 0; \
1676 \
1677 if (! volatile_func) \
1678 { \
1679 for (regno = 0; regno <= 10; regno++) \
1680 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1681 saved_hard_reg = 1, offset += 4; \
1682 if (! TARGET_APCS_FRAME \
1683 && ! frame_pointer_needed \
1684 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \
1685 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \
1686 saved_hard_reg = 1, offset += 4; \
1687 /* PIC register is a fixed reg, so call_used_regs set. */ \
1688 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1689 saved_hard_reg = 1, offset += 4; \
1690 for (regno = FIRST_ARM_FP_REGNUM; \
1691 regno <= LAST_ARM_FP_REGNUM; regno++) \
1692 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1693 offset += 12; \
1694 } \
1695 if ((FROM) == FRAME_POINTER_REGNUM) \
1696 (OFFSET) = - offset; \
1697 else \
1698 { \
1699 if (! frame_pointer_needed) \
1700 offset -= 16; \
1701 if (! volatile_func \
1702 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1703 offset += 4; \
1704 offset += current_function_outgoing_args_size; \
1705 (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \
1706 } \
1707 } \
1708 }
1709
1710 /* Note: This macro must match the code in thumb_function_prologue(). */
1711 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1712 { \
1713 (OFFSET) = 0; \
1714 if ((FROM) == ARG_POINTER_REGNUM) \
1715 { \
1716 int count_regs = 0; \
1717 int regno; \
1718 for (regno = 8; regno < 13; regno ++) \
1719 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1720 count_regs ++; \
1721 if (count_regs) \
1722 (OFFSET) += 4 * count_regs; \
1723 count_regs = 0; \
1724 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1725 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1726 count_regs ++; \
1727 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1728 (OFFSET) += 4 * (count_regs + 1); \
1729 if (TARGET_BACKTRACE) \
1730 { \
1731 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1732 (OFFSET) += 20; \
1733 else \
1734 (OFFSET) += 16; \
1735 } \
1736 } \
1737 if ((TO) == STACK_POINTER_REGNUM) \
1738 { \
1739 (OFFSET) += current_function_outgoing_args_size; \
1740 (OFFSET) += ROUND_UP (get_frame_size ()); \
1741 } \
1742 }
1743
1744 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1745 if (TARGET_ARM) \
1746 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \
1747 else \
1748 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1749
1750 /* Special case handling of the location of arguments passed on the stack. */
1751 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1752
1753 /* Initialize data used by insn expanders. This is called from insn_emit,
1754 once for every function before code is generated. */
1755 #define INIT_EXPANDERS arm_init_expanders ()
1756
1757 /* Output assembler code for a block containing the constant parts
1758 of a trampoline, leaving space for the variable parts.
1759
1760 On the ARM, (if r8 is the static chain regnum, and remembering that
1761 referencing pc adds an offset of 8) the trampoline looks like:
1762 ldr r8, [pc, #0]
1763 ldr pc, [pc]
1764 .word static chain value
1765 .word function's address
1766 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1767 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1768 { \
1769 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1770 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1771 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1772 PC_REGNUM, PC_REGNUM); \
1773 ASM_OUTPUT_INT (FILE, const0_rtx); \
1774 ASM_OUTPUT_INT (FILE, const0_rtx); \
1775 }
1776
1777 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1778 Why - because it is easier. This code will always be branched to via
1779 a BX instruction and since the compiler magically generates the address
1780 of the function the linker has no opportunity to ensure that the
1781 bottom bit is set. Thus the processor will be in ARM mode when it
1782 reaches this code. So we duplicate the ARM trampoline code and add
1783 a switch into Thumb mode as well. */
1784 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1785 { \
1786 fprintf (FILE, "\t.code 32\n"); \
1787 fprintf (FILE, ".Ltrampoline_start:\n"); \
1788 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1789 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1790 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1791 IP_REGNUM, PC_REGNUM); \
1792 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1793 IP_REGNUM, IP_REGNUM); \
1794 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1795 fprintf (FILE, "\t.word\t0\n"); \
1796 fprintf (FILE, "\t.word\t0\n"); \
1797 fprintf (FILE, "\t.code 16\n"); \
1798 }
1799
1800 #define TRAMPOLINE_TEMPLATE(FILE) \
1801 if (TARGET_ARM) \
1802 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1803 else \
1804 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1805
1806 /* Length in units of the trampoline for entering a nested function. */
1807 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1808
1809 /* Alignment required for a trampoline in units. */
1810 #define TRAMPOLINE_ALIGN 4
1811
1812 /* Emit RTL insns to initialize the variable parts of a trampoline.
1813 FNADDR is an RTX for the address of the function's pure code.
1814 CXT is an RTX for the static chain value for the function. */
1815 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1816 { \
1817 emit_move_insn \
1818 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1819 emit_move_insn \
1820 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1821 }
1822
1823 \f
1824 /* Addressing modes, and classification of registers for them. */
1825 #define HAVE_POST_INCREMENT 1
1826 #define HAVE_PRE_INCREMENT TARGET_ARM
1827 #define HAVE_POST_DECREMENT TARGET_ARM
1828 #define HAVE_PRE_DECREMENT TARGET_ARM
1829
1830 /* Macros to check register numbers against specific register classes. */
1831
1832 /* These assume that REGNO is a hard or pseudo reg number.
1833 They give nonzero only if REGNO is a hard reg of the suitable class
1834 or a pseudo reg currently allocated to a suitable hard reg.
1835 Since they use reg_renumber, they are safe only once reg_renumber
1836 has been allocated, which happens in local-alloc.c. */
1837 #define TEST_REGNO(R, TEST, VALUE) \
1838 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1839
1840 /* On the ARM, don't allow the pc to be used. */
1841 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1842 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1843 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1844 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1845
1846 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1847 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1848 || (GET_MODE_SIZE (MODE) >= 4 \
1849 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1850
1851 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1852 (TARGET_THUMB \
1853 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1854 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1855
1856 /* For ARM code, we don't care about the mode, but for Thumb, the index
1857 must be suitable for use in a QImode load. */
1858 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1859 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1860
1861 /* Maximum number of registers that can appear in a valid memory address.
1862 Shifts in addresses can't be by a register. */
1863 #define MAX_REGS_PER_ADDRESS 2
1864
1865 /* Recognize any constant value that is a valid address. */
1866 /* XXX We can address any constant, eventually... */
1867
1868 #ifdef AOF_ASSEMBLER
1869
1870 #define CONSTANT_ADDRESS_P(X) \
1871 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1872
1873 #else
1874
1875 #define CONSTANT_ADDRESS_P(X) \
1876 (GET_CODE (X) == SYMBOL_REF \
1877 && (CONSTANT_POOL_ADDRESS_P (X) \
1878 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1879
1880 #endif /* AOF_ASSEMBLER */
1881
1882 /* Nonzero if the constant value X is a legitimate general operand.
1883 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1884
1885 On the ARM, allow any integer (invalid ones are removed later by insn
1886 patterns), nice doubles and symbol_refs which refer to the function's
1887 constant pool XXX.
1888
1889 When generating pic allow anything. */
1890 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1891
1892 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1893 ( GET_CODE (X) == CONST_INT \
1894 || GET_CODE (X) == CONST_DOUBLE \
1895 || CONSTANT_ADDRESS_P (X))
1896
1897 #define LEGITIMATE_CONSTANT_P(X) \
1898 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1899
1900 /* Special characters prefixed to function names
1901 in order to encode attribute like information.
1902 Note, '@' and '*' have already been taken. */
1903 #define SHORT_CALL_FLAG_CHAR '^'
1904 #define LONG_CALL_FLAG_CHAR '#'
1905
1906 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1907 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1908
1909 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1910 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1911
1912 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1913 #define SUBTARGET_NAME_ENCODING_LENGTHS
1914 #endif
1915
1916 /* This is a C fragement for the inside of a switch statement.
1917 Each case label should return the number of characters to
1918 be stripped from the start of a function's name, if that
1919 name starts with the indicated character. */
1920 #define ARM_NAME_ENCODING_LENGTHS \
1921 case SHORT_CALL_FLAG_CHAR: return 1; \
1922 case LONG_CALL_FLAG_CHAR: return 1; \
1923 case '*': return 1; \
1924 SUBTARGET_NAME_ENCODING_LENGTHS
1925
1926 /* This has to be handled by a function because more than part of the
1927 ARM backend uses function name prefixes to encode attributes. */
1928 #undef STRIP_NAME_ENCODING
1929 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1930 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1931
1932 /* This is how to output a reference to a user-level label named NAME.
1933 `assemble_name' uses this. */
1934 #undef ASM_OUTPUT_LABELREF
1935 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1936 fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME))
1937
1938 /* If we are referencing a function that is weak then encode a long call
1939 flag in the function name, otherwise if the function is static or
1940 or known to be defined in this file then encode a short call flag.
1941 This macro is used inside the ENCODE_SECTION macro. */
1942 #define ARM_ENCODE_CALL_TYPE(decl) \
1943 if (TREE_CODE (decl) == FUNCTION_DECL) \
1944 { \
1945 if (DECL_WEAK (decl)) \
1946 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1947 else if (! TREE_PUBLIC (decl)) \
1948 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1949 } \
1950
1951 /* Symbols in the text segment can be accessed without indirecting via the
1952 constant pool; it may take an extra binary operation, but this is still
1953 faster than indirecting via memory. Don't do this when not optimizing,
1954 since we won't be calculating al of the offsets necessary to do this
1955 simplification. */
1956 /* This doesn't work with AOF syntax, since the string table may be in
1957 a different AREA. */
1958 #ifndef AOF_ASSEMBLER
1959 #define ENCODE_SECTION_INFO(decl) \
1960 { \
1961 if (optimize > 0 && TREE_CONSTANT (decl) \
1962 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1963 { \
1964 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1965 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1966 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1967 } \
1968 ARM_ENCODE_CALL_TYPE (decl) \
1969 }
1970 #else
1971 #define ENCODE_SECTION_INFO(decl) \
1972 { \
1973 ARM_ENCODE_CALL_TYPE (decl) \
1974 }
1975 #endif
1976
1977 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1978 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1979
1980 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1981 and check its validity for a certain class.
1982 We have two alternate definitions for each of them.
1983 The usual definition accepts all pseudo regs; the other rejects
1984 them unless they have been allocated suitable hard regs.
1985 The symbol REG_OK_STRICT causes the latter definition to be used. */
1986 #ifndef REG_OK_STRICT
1987
1988 #define ARM_REG_OK_FOR_BASE_P(X) \
1989 (REGNO (X) <= LAST_ARM_REGNUM \
1990 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1991 || REGNO (X) == FRAME_POINTER_REGNUM \
1992 || REGNO (X) == ARG_POINTER_REGNUM)
1993
1994 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1995 (REGNO (X) <= LAST_LO_REGNUM \
1996 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1997 || (GET_MODE_SIZE (MODE) >= 4 \
1998 && (REGNO (X) == STACK_POINTER_REGNUM \
1999 || (X) == hard_frame_pointer_rtx \
2000 || (X) == arg_pointer_rtx)))
2001
2002 #else /* REG_OK_STRICT */
2003
2004 #define ARM_REG_OK_FOR_BASE_P(X) \
2005 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2006
2007 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2008 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2009
2010 #endif /* REG_OK_STRICT */
2011
2012 /* Now define some helpers in terms of the above. */
2013
2014 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2015 (TARGET_THUMB \
2016 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2017 : ARM_REG_OK_FOR_BASE_P (X))
2018
2019 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2020
2021 /* For Thumb, a valid index register is anything that can be used in
2022 a byte load instruction. */
2023 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2024
2025 /* Nonzero if X is a hard reg that can be used as an index
2026 or if it is a pseudo reg. On the Thumb, the stack pointer
2027 is not suitable. */
2028 #define REG_OK_FOR_INDEX_P(X) \
2029 (TARGET_THUMB \
2030 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2031 : ARM_REG_OK_FOR_INDEX_P (X))
2032
2033 \f
2034 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2035 that is a valid memory address for an instruction.
2036 The MODE argument is the machine mode for the MEM expression
2037 that wants to use this address.
2038
2039 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
2040
2041 /* --------------------------------arm version----------------------------- */
2042 #define ARM_BASE_REGISTER_RTX_P(X) \
2043 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2044
2045 #define ARM_INDEX_REGISTER_RTX_P(X) \
2046 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2047
2048 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2049 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2050 only be small constants. */
2051 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2052 do \
2053 { \
2054 HOST_WIDE_INT range; \
2055 enum rtx_code code = GET_CODE (INDEX); \
2056 \
2057 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2058 { \
2059 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2060 && INTVAL (INDEX) > -1024 \
2061 && (INTVAL (INDEX) & 3) == 0) \
2062 goto LABEL; \
2063 } \
2064 else \
2065 { \
2066 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2067 && GET_MODE_SIZE (MODE) <= 4) \
2068 goto LABEL; \
2069 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2070 && (! arm_arch4 || (MODE) != HImode)) \
2071 { \
2072 rtx xiop0 = XEXP (INDEX, 0); \
2073 rtx xiop1 = XEXP (INDEX, 1); \
2074 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2075 && power_of_two_operand (xiop1, SImode)) \
2076 goto LABEL; \
2077 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2078 && power_of_two_operand (xiop0, SImode)) \
2079 goto LABEL; \
2080 } \
2081 if (GET_MODE_SIZE (MODE) <= 4 \
2082 && (code == LSHIFTRT || code == ASHIFTRT \
2083 || code == ASHIFT || code == ROTATERT) \
2084 && (! arm_arch4 || (MODE) != HImode)) \
2085 { \
2086 rtx op = XEXP (INDEX, 1); \
2087 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2088 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2089 && INTVAL (op) <= 31) \
2090 goto LABEL; \
2091 } \
2092 /* NASTY: Since this limits the addressing of unsigned \
2093 byte loads. */ \
2094 range = ((MODE) == HImode || (MODE) == QImode) \
2095 ? (arm_arch4 ? 256 : 4095) : 4096; \
2096 if (code == CONST_INT && INTVAL (INDEX) < range \
2097 && INTVAL (INDEX) > -range) \
2098 goto LABEL; \
2099 } \
2100 } \
2101 while (0)
2102
2103 /* Jump to LABEL if X is a valid address RTX. This must take
2104 REG_OK_STRICT into account when deciding about valid registers.
2105
2106 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2107 floating SYMBOL_REF to the constant pool. Allow REG-only and
2108 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2109 forced though a static cell to ensure addressability. */
2110 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2111 { \
2112 if (ARM_BASE_REGISTER_RTX_P (X)) \
2113 goto LABEL; \
2114 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2115 && GET_CODE (XEXP (X, 0)) == REG \
2116 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2117 goto LABEL; \
2118 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2119 && (GET_CODE (X) == LABEL_REF \
2120 || (GET_CODE (X) == CONST \
2121 && GET_CODE (XEXP ((X), 0)) == PLUS \
2122 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2123 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2124 goto LABEL; \
2125 else if ((MODE) == TImode) \
2126 ; \
2127 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2128 { \
2129 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2130 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2131 { \
2132 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2133 if (val == 4 || val == -4 || val == -8) \
2134 goto LABEL; \
2135 } \
2136 } \
2137 else if (GET_CODE (X) == PLUS) \
2138 { \
2139 rtx xop0 = XEXP (X, 0); \
2140 rtx xop1 = XEXP (X, 1); \
2141 \
2142 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2143 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2144 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2145 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2146 } \
2147 /* Reload currently can't handle MINUS, so disable this for now */ \
2148 /* else if (GET_CODE (X) == MINUS) \
2149 { \
2150 rtx xop0 = XEXP (X,0); \
2151 rtx xop1 = XEXP (X,1); \
2152 \
2153 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2154 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2155 } */ \
2156 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2157 && GET_CODE (X) == SYMBOL_REF \
2158 && CONSTANT_POOL_ADDRESS_P (X) \
2159 && ! (flag_pic \
2160 && symbol_mentioned_p (get_pool_constant (X)))) \
2161 goto LABEL; \
2162 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2163 && (GET_MODE_SIZE (MODE) <= 4) \
2164 && GET_CODE (XEXP (X, 0)) == REG \
2165 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2166 goto LABEL; \
2167 }
2168
2169 /* ---------------------thumb version----------------------------------*/
2170 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2171 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2172 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2173 && ((VAL) & 1) == 0) \
2174 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2175 && ((VAL) & 3) == 0))
2176
2177 /* The AP may be eliminated to either the SP or the FP, so we use the
2178 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2179
2180 /* ??? Verify whether the above is the right approach. */
2181
2182 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2183 needs special handling also. */
2184
2185 /* ??? Look at how the mips16 port solves this problem. It probably uses
2186 better ways to solve some of these problems. */
2187
2188 /* Although it is not incorrect, we don't accept QImode and HImode
2189 addresses based on the frame pointer or arg pointer until the
2190 reload pass starts. This is so that eliminating such addresses
2191 into stack based ones won't produce impossible code. */
2192 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2193 { \
2194 /* ??? Not clear if this is right. Experiment. */ \
2195 if (GET_MODE_SIZE (MODE) < 4 \
2196 && ! (reload_in_progress || reload_completed) \
2197 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2198 || reg_mentioned_p (arg_pointer_rtx, X) \
2199 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2200 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2201 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2202 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2203 ; \
2204 /* Accept any base register. SP only in SImode or larger. */ \
2205 else if (GET_CODE (X) == REG \
2206 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2207 goto WIN; \
2208 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2209 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2210 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2211 goto WIN; \
2212 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2213 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2214 && (GET_CODE (X) == LABEL_REF \
2215 || (GET_CODE (X) == CONST \
2216 && GET_CODE (XEXP (X, 0)) == PLUS \
2217 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2218 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2219 goto WIN; \
2220 /* Post-inc indexing only supported for SImode and larger. */ \
2221 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2222 && GET_CODE (XEXP (X, 0)) == REG \
2223 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2224 goto WIN; \
2225 else if (GET_CODE (X) == PLUS) \
2226 { \
2227 /* REG+REG address can be any two index registers. */ \
2228 /* We disallow FRAME+REG addressing since we know that FRAME \
2229 will be replaced with STACK, and SP relative addressing only \
2230 permits SP+OFFSET. */ \
2231 if (GET_MODE_SIZE (MODE) <= 4 \
2232 && GET_CODE (XEXP (X, 0)) == REG \
2233 && GET_CODE (XEXP (X, 1)) == REG \
2234 && XEXP (X, 0) != frame_pointer_rtx \
2235 && XEXP (X, 1) != frame_pointer_rtx \
2236 && XEXP (X, 0) != virtual_stack_vars_rtx \
2237 && XEXP (X, 1) != virtual_stack_vars_rtx \
2238 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2239 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2240 goto WIN; \
2241 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2242 else if (GET_CODE (XEXP (X, 0)) == REG \
2243 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2244 || XEXP (X, 0) == arg_pointer_rtx) \
2245 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2246 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2247 goto WIN; \
2248 /* REG+const has 10 bit offset for SP, but only SImode and \
2249 larger is supported. */ \
2250 /* ??? Should probably check for DI/DFmode overflow here \
2251 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2252 else if (GET_CODE (XEXP (X, 0)) == REG \
2253 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2254 && GET_MODE_SIZE (MODE) >= 4 \
2255 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2256 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2257 + GET_MODE_SIZE (MODE)) <= 1024 \
2258 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2259 goto WIN; \
2260 else if (GET_CODE (XEXP (X, 0)) == REG \
2261 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2262 && GET_MODE_SIZE (MODE) >= 4 \
2263 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2264 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2265 goto WIN; \
2266 } \
2267 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2268 && GET_CODE (X) == SYMBOL_REF \
2269 && CONSTANT_POOL_ADDRESS_P (X) \
2270 && ! (flag_pic \
2271 && symbol_mentioned_p (get_pool_constant (X)))) \
2272 goto WIN; \
2273 }
2274
2275 /* ------------------------------------------------------------------- */
2276 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2277 if (TARGET_ARM) \
2278 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2279 else /* if (TARGET_THUMB) */ \
2280 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2281 /* ------------------------------------------------------------------- */
2282 \f
2283 /* Try machine-dependent ways of modifying an illegitimate address
2284 to be legitimate. If we find one, return the new, valid address.
2285 This macro is used in only one place: `memory_address' in explow.c.
2286
2287 OLDX is the address as it was before break_out_memory_refs was called.
2288 In some cases it is useful to look at this to decide what needs to be done.
2289
2290 MODE and WIN are passed so that this macro can use
2291 GO_IF_LEGITIMATE_ADDRESS.
2292
2293 It is always safe for this macro to do nothing. It exists to recognize
2294 opportunities to optimize the output.
2295
2296 On the ARM, try to convert [REG, #BIGCONST]
2297 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2298 where VALIDCONST == 0 in case of TImode. */
2299 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2300 { \
2301 if (GET_CODE (X) == PLUS) \
2302 { \
2303 rtx xop0 = XEXP (X, 0); \
2304 rtx xop1 = XEXP (X, 1); \
2305 \
2306 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2307 xop0 = force_reg (SImode, xop0); \
2308 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2309 xop1 = force_reg (SImode, xop1); \
2310 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2311 && GET_CODE (xop1) == CONST_INT) \
2312 { \
2313 HOST_WIDE_INT n, low_n; \
2314 rtx base_reg, val; \
2315 n = INTVAL (xop1); \
2316 \
2317 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2318 { \
2319 low_n = n & 0x0f; \
2320 n &= ~0x0f; \
2321 if (low_n > 4) \
2322 { \
2323 n += 16; \
2324 low_n -= 16; \
2325 } \
2326 } \
2327 else \
2328 { \
2329 low_n = ((MODE) == TImode ? 0 \
2330 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2331 n -= low_n; \
2332 } \
2333 base_reg = gen_reg_rtx (SImode); \
2334 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2335 GEN_INT (n)), NULL_RTX); \
2336 emit_move_insn (base_reg, val); \
2337 (X) = (low_n == 0 ? base_reg \
2338 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2339 } \
2340 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2341 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2342 } \
2343 else if (GET_CODE (X) == MINUS) \
2344 { \
2345 rtx xop0 = XEXP (X, 0); \
2346 rtx xop1 = XEXP (X, 1); \
2347 \
2348 if (CONSTANT_P (xop0)) \
2349 xop0 = force_reg (SImode, xop0); \
2350 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2351 xop1 = force_reg (SImode, xop1); \
2352 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2353 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2354 } \
2355 if (flag_pic) \
2356 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2357 if (memory_address_p (MODE, X)) \
2358 goto WIN; \
2359 }
2360
2361 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2362 if (flag_pic) \
2363 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2364
2365 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2366 if (TARGET_ARM) \
2367 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2368 else \
2369 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2370
2371 /* Go to LABEL if ADDR (a legitimate address expression)
2372 has an effect that depends on the machine mode it is used for. */
2373 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2374 { \
2375 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2376 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2377 goto LABEL; \
2378 }
2379
2380 /* Nothing helpful to do for the Thumb */
2381 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2382 if (TARGET_ARM) \
2383 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2384 \f
2385
2386 /* Specify the machine mode that this machine uses
2387 for the index in the tablejump instruction. */
2388 #define CASE_VECTOR_MODE Pmode
2389
2390 /* Define as C expression which evaluates to nonzero if the tablejump
2391 instruction expects the table to contain offsets from the address of the
2392 table.
2393 Do not define this if the table should contain absolute addresses. */
2394 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2395
2396 /* Specify the tree operation to be used to convert reals to integers. */
2397 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2398
2399 /* This is the kind of divide that is easiest to do in the general case. */
2400 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2401
2402 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2403 unsigned is probably best, but may break some code. */
2404 #ifndef DEFAULT_SIGNED_CHAR
2405 #define DEFAULT_SIGNED_CHAR 0
2406 #endif
2407
2408 /* Don't cse the address of the function being compiled. */
2409 #define NO_RECURSIVE_FUNCTION_CSE 1
2410
2411 /* Max number of bytes we can move from memory to memory
2412 in one reasonably fast instruction. */
2413 #define MOVE_MAX 4
2414
2415 #undef MOVE_RATIO
2416 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2417
2418 /* Define if operations between registers always perform the operation
2419 on the full register even if a narrower mode is specified. */
2420 #define WORD_REGISTER_OPERATIONS
2421
2422 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2423 will either zero-extend or sign-extend. The value of this macro should
2424 be the code that says which one of the two operations is implicitly
2425 done, NIL if none. */
2426 #define LOAD_EXTEND_OP(MODE) \
2427 (TARGET_THUMB ? ZERO_EXTEND : \
2428 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2429 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2430
2431 /* Define this if zero-extension is slow (more than one real instruction).
2432 On the ARM, it is more than one instruction only if not fetching from
2433 memory. */
2434 /* #define SLOW_ZERO_EXTEND */
2435
2436 /* Nonzero if access to memory by bytes is slow and undesirable. */
2437 #define SLOW_BYTE_ACCESS 0
2438
2439 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2440
2441 /* Immediate shift counts are truncated by the output routines (or was it
2442 the assembler?). Shift counts in a register are truncated by ARM. Note
2443 that the native compiler puts too large (> 32) immediate shift counts
2444 into a register and shifts by the register, letting the ARM decide what
2445 to do instead of doing that itself. */
2446 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2447 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2448 On the arm, Y in a register is used modulo 256 for the shift. Only for
2449 rotates is modulo 32 used. */
2450 /* #define SHIFT_COUNT_TRUNCATED 1 */
2451
2452 /* All integers have the same format so truncation is easy. */
2453 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2454
2455 /* Calling from registers is a massive pain. */
2456 #define NO_FUNCTION_CSE 1
2457
2458 /* Chars and shorts should be passed as ints. */
2459 #define PROMOTE_PROTOTYPES 1
2460
2461 /* The machine modes of pointers and functions */
2462 #define Pmode SImode
2463 #define FUNCTION_MODE Pmode
2464
2465 #define ARM_FRAME_RTX(X) \
2466 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2467 || (X) == arg_pointer_rtx)
2468
2469 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2470 return arm_rtx_costs (X, CODE, OUTER_CODE);
2471
2472 /* Moves to and from memory are quite expensive */
2473 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2474 (TARGET_ARM ? 10 : \
2475 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2476 * (CLASS == LO_REGS ? 1 : 2)))
2477
2478 /* All address computations that can be done are free, but rtx cost returns
2479 the same for practically all of them. So we weight the different types
2480 of address here in the order (most pref first):
2481 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2482 #define ARM_ADDRESS_COST(X) \
2483 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2484 || GET_CODE (X) == SYMBOL_REF) \
2485 ? 0 \
2486 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2487 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2488 ? 10 \
2489 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2490 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2491 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2492 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2493 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2494 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2495 ? 1 : 0)) \
2496 : 4)))))
2497
2498 #define THUMB_ADDRESS_COST(X) \
2499 ((GET_CODE (X) == REG \
2500 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2501 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2502 ? 1 : 2)
2503
2504 #define ADDRESS_COST(X) \
2505 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2506
2507 /* Try to generate sequences that don't involve branches, we can then use
2508 conditional instructions */
2509 #define BRANCH_COST \
2510 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2511
2512 /* A C statement to update the variable COST based on the relationship
2513 between INSN that is dependent on DEP through dependence LINK. */
2514 #define ADJUST_COST(INSN, LINK, DEP, COST) \
2515 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
2516 \f
2517 /* Position Independent Code. */
2518 /* We decide which register to use based on the compilation options and
2519 the assembler in use; this is more general than the APCS restriction of
2520 using sb (r9) all the time. */
2521 extern int arm_pic_register;
2522
2523 /* Used when parsing command line option -mpic-register=. */
2524 extern const char * arm_pic_register_string;
2525
2526 /* The register number of the register used to address a table of static
2527 data addresses in memory. */
2528 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2529
2530 #define FINALIZE_PIC arm_finalize_pic ()
2531
2532 /* We can't directly access anything that contains a symbol,
2533 nor can we indirect via the constant pool. */
2534 #define LEGITIMATE_PIC_OPERAND_P(X) \
2535 ( ! symbol_mentioned_p (X) \
2536 && ! label_mentioned_p (X) \
2537 && (! CONSTANT_POOL_ADDRESS_P (X) \
2538 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2539 && ! label_mentioned_p (get_pool_constant (X)))))
2540
2541 /* We need to know when we are making a constant pool; this determines
2542 whether data needs to be in the GOT or can be referenced via a GOT
2543 offset. */
2544 extern int making_const_table;
2545 \f
2546 /* If defined, a C expression whose value is nonzero if IDENTIFIER
2547 with arguments ARGS is a valid machine specific attribute for TYPE.
2548 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
2549 #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \
2550 (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS))
2551
2552 /* If defined, a C expression whose value is zero if the attributes on
2553 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
2554 two if they are nearly compatible (which causes a warning to be
2555 generated). */
2556 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
2557 (arm_comp_type_attributes (TYPE1, TYPE2))
2558
2559 /* If defined, a C statement that assigns default attributes to newly
2560 defined TYPE. */
2561 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
2562 arm_set_default_type_attributes (TYPE)
2563
2564 /* Handle pragmas for compatibility with Intel's compilers. */
2565 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2566 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2567 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2568 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2569 } while (0)
2570
2571 /* Condition code information. */
2572 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2573 return the mode to be used for the comparison.
2574 CCFPEmode should be used with floating inequalities,
2575 CCFPmode should be used with floating equalities.
2576 CC_NOOVmode should be used with SImode integer equalities.
2577 CC_Zmode should be used if only the Z flag is set correctly
2578 CCmode should be used otherwise. */
2579
2580 #define EXTRA_CC_MODES \
2581 CC(CC_NOOVmode, "CC_NOOV") \
2582 CC(CC_Zmode, "CC_Z") \
2583 CC(CC_SWPmode, "CC_SWP") \
2584 CC(CCFPmode, "CCFP") \
2585 CC(CCFPEmode, "CCFPE") \
2586 CC(CC_DNEmode, "CC_DNE") \
2587 CC(CC_DEQmode, "CC_DEQ") \
2588 CC(CC_DLEmode, "CC_DLE") \
2589 CC(CC_DLTmode, "CC_DLT") \
2590 CC(CC_DGEmode, "CC_DGE") \
2591 CC(CC_DGTmode, "CC_DGT") \
2592 CC(CC_DLEUmode, "CC_DLEU") \
2593 CC(CC_DLTUmode, "CC_DLTU") \
2594 CC(CC_DGEUmode, "CC_DGEU") \
2595 CC(CC_DGTUmode, "CC_DGTU") \
2596 CC(CC_Cmode, "CC_C")
2597
2598 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2599
2600 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2601
2602 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2603 do \
2604 { \
2605 if (GET_CODE (OP1) == CONST_INT \
2606 && ! (const_ok_for_arm (INTVAL (OP1)) \
2607 || (const_ok_for_arm (- INTVAL (OP1))))) \
2608 { \
2609 rtx const_op = OP1; \
2610 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2611 OP1 = const_op; \
2612 } \
2613 } \
2614 while (0)
2615
2616 #define STORE_FLAG_VALUE 1
2617
2618 \f
2619
2620 /* Gcc puts the pool in the wrong place for ARM, since we can only
2621 load addresses a limited distance around the pc. We do some
2622 special munging to move the constant pool values to the correct
2623 point in the code. */
2624 #define MACHINE_DEPENDENT_REORG(INSN) \
2625 arm_reorg (INSN); \
2626
2627 #undef ASM_APP_OFF
2628 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2629
2630 /* Output an internal label definition. */
2631 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2632 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2633 do \
2634 { \
2635 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2636 \
2637 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2638 && !strcmp (PREFIX, "L")) \
2639 { \
2640 arm_ccfsm_state = 0; \
2641 arm_target_insn = NULL; \
2642 } \
2643 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2644 ASM_OUTPUT_LABEL (STREAM, s); \
2645 } \
2646 while (0)
2647 #endif
2648
2649 /* Output a push or a pop instruction (only used when profiling). */
2650 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2651 if (TARGET_ARM) \
2652 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2653 STACK_POINTER_REGNUM, REGNO); \
2654 else \
2655 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2656
2657
2658 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2659 if (TARGET_ARM) \
2660 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2661 STACK_POINTER_REGNUM, REGNO); \
2662 else \
2663 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2664
2665 /* This is how to output a label which precedes a jumptable. Since
2666 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2667 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2668 do \
2669 { \
2670 if (TARGET_THUMB) \
2671 ASM_OUTPUT_ALIGN (FILE, 2); \
2672 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2673 } \
2674 while (0)
2675
2676 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2677 do \
2678 { \
2679 if (TARGET_THUMB) \
2680 { \
2681 if (is_called_in_ARM_mode (DECL)) \
2682 fprintf (STREAM, "\t.code 32\n") ; \
2683 else \
2684 fprintf (STREAM, "\t.thumb_func\n") ; \
2685 } \
2686 if (TARGET_POKE_FUNCTION_NAME) \
2687 arm_poke_function_name (STREAM, (char *) NAME); \
2688 } \
2689 while (0)
2690
2691 /* For aliases of functions we use .thumb_set instead. */
2692 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2693 do \
2694 { \
2695 char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2696 char * LABEL2 = IDENTIFIER_POINTER (DECL2); \
2697 \
2698 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2699 { \
2700 fprintf (FILE, "\t.thumb_set "); \
2701 assemble_name (FILE, LABEL1); \
2702 fprintf (FILE, ","); \
2703 assemble_name (FILE, LABEL2); \
2704 fprintf (FILE, "\n"); \
2705 } \
2706 else \
2707 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2708 } \
2709 while (0)
2710
2711 /* Target characters. */
2712 #define TARGET_BELL 007
2713 #define TARGET_BS 010
2714 #define TARGET_TAB 011
2715 #define TARGET_NEWLINE 012
2716 #define TARGET_VT 013
2717 #define TARGET_FF 014
2718 #define TARGET_CR 015
2719 \f
2720 /* Only perform branch elimination (by making instructions conditional) if
2721 we're optimising. Otherwise it's of no use anyway. */
2722 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2723 if (TARGET_ARM && optimize) \
2724 arm_final_prescan_insn (INSN); \
2725 else if (TARGET_THUMB) \
2726 thumb_final_prescan_insn (INSN)
2727
2728 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2729 (CODE == '@' || CODE == '|' \
2730 || (TARGET_ARM && (CODE == '?')) \
2731 || (TARGET_THUMB && (CODE == '_')))
2732
2733 /* Output an operand of an instruction. */
2734 #define PRINT_OPERAND(STREAM, X, CODE) \
2735 arm_print_operand (STREAM, X, CODE)
2736
2737 /* Create an [unsigned] host sized integer declaration that
2738 avoids compiler warnings. */
2739 #ifdef __STDC__
2740 #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL)
2741 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL)
2742 #else
2743 #define HOST_INT(x) ((HOST_WIDE_INT) x)
2744 #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x)
2745 #endif
2746
2747 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2748 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2749 : (((x) & HOST_UINT (0xffffffff)) | \
2750 (((x) & HOST_UINT (0x80000000)) \
2751 ? ((~ HOST_INT (0)) \
2752 & ~ HOST_UINT(0xffffffff)) \
2753 : 0))))
2754
2755 /* Output the address of an operand. */
2756 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2757 { \
2758 int is_minus = GET_CODE (X) == MINUS; \
2759 \
2760 if (GET_CODE (X) == REG) \
2761 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2762 else if (GET_CODE (X) == PLUS || is_minus) \
2763 { \
2764 rtx base = XEXP (X, 0); \
2765 rtx index = XEXP (X, 1); \
2766 HOST_WIDE_INT offset = 0; \
2767 if (GET_CODE (base) != REG) \
2768 { \
2769 /* Ensure that BASE is a register */ \
2770 /* (one of them must be). */ \
2771 rtx temp = base; \
2772 base = index; \
2773 index = temp; \
2774 } \
2775 switch (GET_CODE (index)) \
2776 { \
2777 case CONST_INT: \
2778 offset = INTVAL (index); \
2779 if (is_minus) \
2780 offset = -offset; \
2781 asm_fprintf (STREAM, "[%r, #%d]", \
2782 REGNO (base), offset); \
2783 break; \
2784 \
2785 case REG: \
2786 asm_fprintf (STREAM, "[%r, %s%r]", \
2787 REGNO (base), is_minus ? "-" : "", \
2788 REGNO (index)); \
2789 break; \
2790 \
2791 case MULT: \
2792 case ASHIFTRT: \
2793 case LSHIFTRT: \
2794 case ASHIFT: \
2795 case ROTATERT: \
2796 { \
2797 asm_fprintf (STREAM, "[%r, %s%r", \
2798 REGNO (base), is_minus ? "-" : "", \
2799 REGNO (XEXP (index, 0))); \
2800 arm_print_operand (STREAM, index, 'S'); \
2801 fputs ("]", STREAM); \
2802 break; \
2803 } \
2804 \
2805 default: \
2806 abort(); \
2807 } \
2808 } \
2809 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2810 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2811 { \
2812 extern int output_memory_reference_mode; \
2813 \
2814 if (GET_CODE (XEXP (X, 0)) != REG) \
2815 abort (); \
2816 \
2817 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2818 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2819 REGNO (XEXP (X, 0)), \
2820 GET_CODE (X) == PRE_DEC ? "-" : "", \
2821 GET_MODE_SIZE (output_memory_reference_mode));\
2822 else \
2823 asm_fprintf (STREAM, "[%r], #%s%d", \
2824 REGNO (XEXP (X, 0)), \
2825 GET_CODE (X) == POST_DEC ? "-" : "", \
2826 GET_MODE_SIZE (output_memory_reference_mode));\
2827 } \
2828 else output_addr_const (STREAM, X); \
2829 }
2830
2831 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2832 { \
2833 if (GET_CODE (X) == REG) \
2834 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2835 else if (GET_CODE (X) == POST_INC) \
2836 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2837 else if (GET_CODE (X) == PLUS) \
2838 { \
2839 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2840 asm_fprintf (STREAM, "[%r, #%d]", \
2841 REGNO (XEXP (X, 0)), \
2842 (int) INTVAL (XEXP (X, 1))); \
2843 else \
2844 asm_fprintf (STREAM, "[%r, %r]", \
2845 REGNO (XEXP (X, 0)), \
2846 REGNO (XEXP (X, 1))); \
2847 } \
2848 else \
2849 output_addr_const (STREAM, X); \
2850 }
2851
2852 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2853 if (TARGET_ARM) \
2854 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2855 else \
2856 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2857
2858 /* Handles PIC addr specially */
2859 #define OUTPUT_INT_ADDR_CONST(STREAM, X) \
2860 { \
2861 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2862 { \
2863 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2864 fputs (" - (", STREAM); \
2865 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2866 fputs (")", STREAM); \
2867 } \
2868 else \
2869 output_addr_const (STREAM, X); \
2870 \
2871 /* Mark symbols as position independent. We only do this in the \
2872 .text segment, not in the .data segment. */ \
2873 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2874 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2875 { \
2876 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2877 fprintf (STREAM, "(GOTOFF)"); \
2878 else if (GET_CODE (X) == LABEL_REF) \
2879 fprintf (STREAM, "(GOTOFF)"); \
2880 else \
2881 fprintf (STREAM, "(GOT)"); \
2882 } \
2883 }
2884
2885 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2886 Used for C++ multiple inheritance. */
2887 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2888 do \
2889 { \
2890 int mi_delta = (DELTA); \
2891 const char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2892 int shift = 0; \
2893 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2894 ? 1 : 0); \
2895 if (mi_delta < 0) \
2896 mi_delta = - mi_delta; \
2897 while (mi_delta != 0) \
2898 { \
2899 if ((mi_delta & (3 << shift)) == 0) \
2900 shift += 2; \
2901 else \
2902 { \
2903 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2904 mi_op, this_regno, this_regno, \
2905 mi_delta & (0xff << shift)); \
2906 mi_delta &= ~(0xff << shift); \
2907 shift += 8; \
2908 } \
2909 } \
2910 fputs ("\tb\t", FILE); \
2911 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2912 if (NEED_PLT_RELOC) \
2913 fputs ("(PLT)", FILE); \
2914 fputc ('\n', FILE); \
2915 } \
2916 while (0)
2917
2918 /* A C expression whose value is RTL representing the value of the return
2919 address for the frame COUNT steps up from the current frame. */
2920
2921 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2922 arm_return_addr (COUNT, FRAME)
2923
2924 /* Mask of the bits in the PC that contain the real return address
2925 when running in 26-bit mode. */
2926 #define RETURN_ADDR_MASK26 (0x03fffffc)
2927
2928 /* Pick up the return address upon entry to a procedure. Used for
2929 dwarf2 unwind information. This also enables the table driven
2930 mechanism. */
2931 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2932 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2933
2934 /* Used to mask out junk bits from the return address, such as
2935 processor state, interrupt status, condition codes and the like. */
2936 #define MASK_RETURN_ADDR \
2937 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2938 in 26 bit mode, the condition codes must be masked out of the \
2939 return address. This does not apply to ARM6 and later processors \
2940 when running in 32 bit mode. */ \
2941 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2942 : (GEN_INT ((unsigned long)0xffffffff)))
2943
2944 \f
2945 /* Define the codes that are matched by predicates in arm.c */
2946 #define PREDICATE_CODES \
2947 {"s_register_operand", {SUBREG, REG}}, \
2948 {"f_register_operand", {SUBREG, REG}}, \
2949 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2950 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2951 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2952 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2953 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2954 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2955 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2956 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2957 {"offsettable_memory_operand", {MEM}}, \
2958 {"bad_signed_byte_operand", {MEM}}, \
2959 {"alignable_memory_operand", {MEM}}, \
2960 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2961 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2962 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2963 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2964 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2965 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2966 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2967 {"load_multiple_operation", {PARALLEL}}, \
2968 {"store_multiple_operation", {PARALLEL}}, \
2969 {"equality_operator", {EQ, NE}}, \
2970 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2971 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2972 UNGE, UNGT}}, \
2973 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2974 {"const_shift_operand", {CONST_INT}}, \
2975 {"multi_register_push", {PARALLEL}}, \
2976 {"cc_register", {REG}}, \
2977 {"logical_binary_operator", {AND, IOR, XOR}}, \
2978 {"dominant_cc_register", {REG}},
2979
2980 /* Define this if you have special predicates that know special things
2981 about modes. Genrecog will warn about certain forms of
2982 match_operand without a mode; if the operand predicate is listed in
2983 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2984 #define SPECIAL_MODE_PREDICATES \
2985 "cc_register", "dominant_cc_register",
2986
2987 enum arm_builtins
2988 {
2989 ARM_BUILTIN_CLZ,
2990 ARM_BUILTIN_PREFETCH,
2991 ARM_BUILTIN_MAX
2992 };
2993
2994 #define MD_INIT_BUILTINS \
2995 do \
2996 { \
2997 arm_init_builtins (); \
2998 } \
2999 while (0)
3000
3001 #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
3002 arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
3003 #endif /* __ARM_H__ */
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