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* Makefile.in (CRTSTUFF_CFLAGS): New.
[official-gcc.git] / gcc / config / i386 / i386.h
blob25705e6420ce4c483815dff5196999ef7ea5861b
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
38
39 #ifndef HALF_PIC_P
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
49 #endif
50
51 /* Define the specific costs for a given cpu */
52
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
91 operations. */
92 };
93
94 extern const struct processor_costs *ix86_cost;
95
96 /* Run-time compilation parameters selecting different hardware subsets. */
97
98 extern int target_flags;
99
100 /* Macros used in the machine description to test the flags. */
101
102 /* configure can arrange to make this 2, to force a 486. */
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
140
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
145
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 #else
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
197 #else
198 #define TARGET_64BIT 0
199 #endif
200 #endif
201
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
209
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern int x86_prefetch_sse;
226
227 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
228 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
229 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
230 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
231 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
232 /* For sane SSE instruction set generation we need fcomi instruction. It is
233 safe to enable all CMOVE instructions. */
234 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
235 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
236 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
237 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
238 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
239 #define TARGET_MOVX (x86_movx & CPUMASK)
240 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
241 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
242 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
243 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
244 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
245 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
246 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
247 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
248 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
249 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
250 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
251 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
252 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
253 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
254 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
255 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
256 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
257 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
258 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
259 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
260 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
261 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
262 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
263 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
264 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
265
266 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
267
268 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
269 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
270
271 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
272
273 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
274 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
275 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
276 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
277 && (ix86_fpmath & FPMATH_387))
278 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
279 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
280 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
281
282 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
283
284 #define TARGET_SWITCHES \
285 { { "80387", MASK_80387, N_("Use hardware fp") }, \
286 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
287 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
288 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
289 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
290 { "386", 0, N_("") /*Deprecated.*/}, \
291 { "486", 0, N_("") /*Deprecated.*/}, \
292 { "pentium", 0, N_("") /*Deprecated.*/}, \
293 { "pentiumpro", 0, N_("") /*Deprecated.*/}, \
294 { "intel-syntax", 0, N_("") /*Deprecated.*/}, \
295 { "no-intel-syntax", 0, N_("") /*Deprecated.*/}, \
296 { "rtd", MASK_RTD, \
297 N_("Alternate calling convention") }, \
298 { "no-rtd", -MASK_RTD, \
299 N_("Use normal calling convention") }, \
300 { "align-double", MASK_ALIGN_DOUBLE, \
301 N_("Align some doubles on dword boundary") }, \
302 { "no-align-double", -MASK_ALIGN_DOUBLE, \
303 N_("Align doubles on word boundary") }, \
304 { "svr3-shlib", MASK_SVR3_SHLIB, \
305 N_("Uninitialized locals in .bss") }, \
306 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
307 N_("Uninitialized locals in .data") }, \
308 { "ieee-fp", MASK_IEEE_FP, \
309 N_("Use IEEE math for fp comparisons") }, \
310 { "no-ieee-fp", -MASK_IEEE_FP, \
311 N_("Do not use IEEE math for fp comparisons") }, \
312 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
313 N_("Return values of functions in FPU registers") }, \
314 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
315 N_("Do not return values of functions in FPU registers")}, \
316 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
317 N_("Do not generate sin, cos, sqrt for FPU") }, \
318 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
319 N_("Generate sin, cos, sqrt for FPU")}, \
320 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
321 N_("Omit the frame pointer in leaf functions") }, \
322 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
323 { "stack-arg-probe", MASK_STACK_PROBE, \
324 N_("Enable stack probing") }, \
325 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
326 { "windows", 0, 0 /* undocumented */ }, \
327 { "dll", 0, 0 /* undocumented */ }, \
328 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
329 N_("Align destination of the string operations") }, \
330 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
331 N_("Do not align destination of the string operations") }, \
332 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
333 N_("Inline all known string operations") }, \
334 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
335 N_("Do not inline all known string operations") }, \
336 { "push-args", -MASK_NO_PUSH_ARGS, \
337 N_("Use push instructions to save outgoing arguments") }, \
338 { "no-push-args", MASK_NO_PUSH_ARGS, \
339 N_("Do not use push instructions to save outgoing arguments") }, \
340 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
341 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
342 N_("Use push instructions to save outgoing arguments") }, \
343 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
344 N_("Do not use push instructions to save outgoing arguments") }, \
345 { "mmx", MASK_MMX | MASK_MMX_SET, \
346 N_("Support MMX built-in functions") }, \
347 { "no-mmx", -MASK_MMX, \
348 N_("Do not support MMX built-in functions") }, \
349 { "no-mmx", MASK_MMX_SET, N_("") }, \
350 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
351 N_("Support 3DNow! built-in functions") }, \
352 { "no-3dnow", -MASK_3DNOW, N_("") }, \
353 { "no-3dnow", MASK_3DNOW_SET, \
354 N_("Do not support 3DNow! built-in functions") }, \
355 { "sse", MASK_SSE | MASK_SSE_SET, \
356 N_("Support MMX and SSE built-in functions and code generation") }, \
357 { "no-sse", -MASK_SSE, N_("") }, \
358 { "no-sse", MASK_SSE_SET, \
359 N_("Do not support MMX and SSE built-in functions and code generation") },\
360 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
361 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
362 { "no-sse2", -MASK_SSE2, N_("") }, \
363 { "no-sse2", MASK_SSE2_SET, \
364 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
365 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
366 N_("sizeof(long double) is 16") }, \
367 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
368 N_("sizeof(long double) is 12") }, \
369 { "64", MASK_64BIT, \
370 N_("Generate 64bit x86-64 code") }, \
371 { "32", -MASK_64BIT, \
372 N_("Generate 32bit i386 code") }, \
373 { "red-zone", -MASK_NO_RED_ZONE, \
374 N_("Use red-zone in the x86-64 code") }, \
375 { "no-red-zone", MASK_NO_RED_ZONE, \
376 N_("Do not use red-zone in the x86-64 code") }, \
377 SUBTARGET_SWITCHES \
378 { "", TARGET_DEFAULT, 0 }}
379
380 #ifdef TARGET_64BIT_DEFAULT
381 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
382 #else
383 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
384 #endif
385
386 /* Which processor to schedule for. The cpu attribute defines a list that
387 mirrors this list, so changes to i386.md must be made at the same time. */
388
389 enum processor_type
390 {
391 PROCESSOR_I386, /* 80386 */
392 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
393 PROCESSOR_PENTIUM,
394 PROCESSOR_PENTIUMPRO,
395 PROCESSOR_K6,
396 PROCESSOR_ATHLON,
397 PROCESSOR_PENTIUM4,
398 PROCESSOR_max
399 };
400 enum fpmath_unit
401 {
402 FPMATH_387 = 1,
403 FPMATH_SSE = 2
404 };
405
406 extern enum processor_type ix86_cpu;
407 extern enum fpmath_unit ix86_fpmath;
408
409 extern int ix86_arch;
410
411 /* This macro is similar to `TARGET_SWITCHES' but defines names of
412 command options that have values. Its definition is an
413 initializer with a subgrouping for each command option.
414
415 Each subgrouping contains a string constant, that defines the
416 fixed part of the option name, and the address of a variable. The
417 variable, type `char *', is set to the variable part of the given
418 option if the fixed part matches. The actual option name is made
419 by appending `-m' to the specified name. */
420 #define TARGET_OPTIONS \
421 { { "cpu=", &ix86_cpu_string, \
422 N_("Schedule code for given CPU")}, \
423 { "fpmath=", &ix86_fpmath_string, \
424 N_("Generate floating point mathematics using given instruction set")},\
425 { "arch=", &ix86_arch_string, \
426 N_("Generate code for given CPU")}, \
427 { "regparm=", &ix86_regparm_string, \
428 N_("Number of registers used to pass integer arguments") }, \
429 { "align-loops=", &ix86_align_loops_string, \
430 N_("Loop code aligned to this power of 2") }, \
431 { "align-jumps=", &ix86_align_jumps_string, \
432 N_("Jump targets are aligned to this power of 2") }, \
433 { "align-functions=", &ix86_align_funcs_string, \
434 N_("Function starts are aligned to this power of 2") }, \
435 { "preferred-stack-boundary=", \
436 &ix86_preferred_stack_boundary_string, \
437 N_("Attempt to keep stack aligned to this power of 2") }, \
438 { "branch-cost=", &ix86_branch_cost_string, \
439 N_("Branches are this expensive (1-5, arbitrary units)") }, \
440 { "cmodel=", &ix86_cmodel_string, \
441 N_("Use given x86-64 code model") }, \
442 { "debug-arg", &ix86_debug_arg_string, \
443 N_("" /* Undocumented. */) }, \
444 { "debug-addr", &ix86_debug_addr_string, \
445 N_("" /* Undocumented. */) }, \
446 { "asm=", &ix86_asm_string, \
447 N_("Use given assembler dialect") }, \
448 SUBTARGET_OPTIONS \
449 }
450
451 /* Sometimes certain combinations of command options do not make
452 sense on a particular target machine. You can define a macro
453 `OVERRIDE_OPTIONS' to take account of this. This macro, if
454 defined, is executed once just after all the command options have
455 been parsed.
456
457 Don't use this macro to turn on various extra optimizations for
458 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
459
460 #define OVERRIDE_OPTIONS override_options ()
461
462 /* These are meant to be redefined in the host dependent files */
463 #define SUBTARGET_SWITCHES
464 #define SUBTARGET_OPTIONS
465
466 /* Define this to change the optimizations performed by default. */
467 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
468 optimization_options ((LEVEL), (SIZE))
469
470 /* Specs for the compiler proper */
471
472 #ifndef CC1_CPU_SPEC
473 #define CC1_CPU_SPEC "\
474 %{!mcpu*: \
475 %{m386:-mcpu=i386 \
476 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
477 %{m486:-mcpu=i486 \
478 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
479 %{mpentium:-mcpu=pentium \
480 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
481 %{mpentiumpro:-mcpu=pentiumpro \
482 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
483 %{mintel-syntax:-masm=intel \
484 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
485 %{mno-intel-syntax:-masm=att \
486 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
487 #endif
488 \f
489 #define TARGET_CPU_DEFAULT_i386 0
490 #define TARGET_CPU_DEFAULT_i486 1
491 #define TARGET_CPU_DEFAULT_pentium 2
492 #define TARGET_CPU_DEFAULT_pentium_mmx 3
493 #define TARGET_CPU_DEFAULT_pentiumpro 4
494 #define TARGET_CPU_DEFAULT_pentium2 5
495 #define TARGET_CPU_DEFAULT_pentium3 6
496 #define TARGET_CPU_DEFAULT_pentium4 7
497 #define TARGET_CPU_DEFAULT_k6 8
498 #define TARGET_CPU_DEFAULT_k6_2 9
499 #define TARGET_CPU_DEFAULT_k6_3 10
500 #define TARGET_CPU_DEFAULT_athlon 11
501 #define TARGET_CPU_DEFAULT_athlon_sse 12
502
503 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
504 "pentiumpro", "pentium2", "pentium3", \
505 "pentium4", "k6", "k6-2", "k6-3",\
506 "athlon", "athlon-4"}
507 #ifndef CPP_CPU_DEFAULT_SPEC
508 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
509 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
510 #endif
511 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
512 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
513 #endif
514 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
515 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
516 #endif
517 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
518 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
519 #endif
520 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
521 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
522 -D__tune_pentium2__"
523 #endif
524 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
525 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
526 -D__tune_pentium2__ -D__tune_pentium3__"
527 #endif
528 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
529 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
530 #endif
531 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
532 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
533 #endif
534 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
535 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
536 #endif
537 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
538 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
539 #endif
540 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
541 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
542 #endif
543 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
544 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
545 #endif
546 #ifndef CPP_CPU_DEFAULT_SPEC
547 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
548 #endif
549 #endif /* CPP_CPU_DEFAULT_SPEC */
550
551 #ifdef TARGET_BI_ARCH
552 #define NO_BUILTIN_SIZE_TYPE
553 #define NO_BUILTIN_PTRDIFF_TYPE
554 #endif
555
556 #ifdef NO_BUILTIN_SIZE_TYPE
557 #define CPP_CPU32_SIZE_TYPE_SPEC \
558 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
559 #define CPP_CPU64_SIZE_TYPE_SPEC \
560 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
561 #else
562 #define CPP_CPU32_SIZE_TYPE_SPEC ""
563 #define CPP_CPU64_SIZE_TYPE_SPEC ""
564 #endif
565
566 #define CPP_CPU32_SPEC \
567 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
568 -D__i386__ %(cpp_cpu32sizet)"
569
570 #define CPP_CPU64_SPEC \
571 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
572
573 #define CPP_CPUCOMMON_SPEC "\
574 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
575 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
576 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
577 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
578 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
579 -D__pentium__mmx__ \
580 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
581 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
582 -D__pentiumpro -D__pentiumpro__ \
583 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
584 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
585 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
586 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
587 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
588 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
589 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
590 %{!mcpu*:-D__tune_athlon__ }}\
591 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
592 -D__athlon_sse__ \
593 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
594 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
595 %{m386|mcpu=i386:-D__tune_i386__ }\
596 %{m486|mcpu=i486:-D__tune_i486__ }\
597 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
598 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
599 -D__tune_pentiumpro__ }\
600 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
601 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
602 -D__tune_athlon__ }\
603 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
604 -D__tune_athlon_sse__ }\
605 %{mcpu=pentium4:-D__tune_pentium4__ }\
606 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
607 -D__SSE__ }\
608 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
609 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
610 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
611 %{march=k6-2|march=k6-3\
612 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
613 |march=athlon-mp: -D__3dNOW__ }\
614 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
615 |march=athlon-mp: -D__3dNOW_A__ }\
616 %{march=pentium4: -D__SSE2__ }\
617 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
618
619 #ifndef CPP_CPU_SPEC
620 #ifdef TARGET_BI_ARCH
621 #ifdef TARGET_64BIT_DEFAULT
622 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
623 #else
624 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
625 #endif
626 #else
627 #ifdef TARGET_64BIT_DEFAULT
628 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
629 #else
630 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
631 #endif
632 #endif
633 #endif
634
635 #ifndef CC1_SPEC
636 #define CC1_SPEC "%(cc1_cpu) "
637 #endif
638
639 /* This macro defines names of additional specifications to put in the
640 specs that can be used in various specifications like CC1_SPEC. Its
641 definition is an initializer with a subgrouping for each command option.
642
643 Each subgrouping contains a string constant, that defines the
644 specification name, and a string constant that used by the GNU CC driver
645 program.
646
647 Do not define this macro if it does not need to do anything. */
648
649 #ifndef SUBTARGET_EXTRA_SPECS
650 #define SUBTARGET_EXTRA_SPECS
651 #endif
652
653 #define EXTRA_SPECS \
654 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
655 { "cpp_cpu", CPP_CPU_SPEC }, \
656 { "cpp_cpu32", CPP_CPU32_SPEC }, \
657 { "cpp_cpu64", CPP_CPU64_SPEC }, \
658 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
659 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
660 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
661 { "cc1_cpu", CC1_CPU_SPEC }, \
662 SUBTARGET_EXTRA_SPECS
663 \f
664 /* target machine storage layout */
665
666 /* Define for XFmode or TFmode extended real floating point support.
667 This will automatically cause REAL_ARITHMETIC to be defined.
668
669 The XFmode is specified by i386 ABI, while TFmode may be faster
670 due to alignment and simplifications in the address calculations.
671 */
672 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
673 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
674 #ifdef __x86_64__
675 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
676 #else
677 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
678 #endif
679 /* Tell real.c that this is the 80-bit Intel extended float format
680 packaged in a 128-bit or 96bit entity. */
681 #define INTEL_EXTENDED_IEEE_FORMAT 1
682
683
684 #define SHORT_TYPE_SIZE 16
685 #define INT_TYPE_SIZE 32
686 #define FLOAT_TYPE_SIZE 32
687 #define LONG_TYPE_SIZE BITS_PER_WORD
688 #define MAX_WCHAR_TYPE_SIZE 32
689 #define DOUBLE_TYPE_SIZE 64
690 #define LONG_LONG_TYPE_SIZE 64
691
692 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
693 #define MAX_BITS_PER_WORD 64
694 #define MAX_LONG_TYPE_SIZE 64
695 #else
696 #define MAX_BITS_PER_WORD 32
697 #define MAX_LONG_TYPE_SIZE 32
698 #endif
699
700 /* Define if you don't want extended real, but do want to use the
701 software floating point emulator for REAL_ARITHMETIC and
702 decimal <-> binary conversion. */
703 /* #define REAL_ARITHMETIC */
704
705 /* Define this if most significant byte of a word is the lowest numbered. */
706 /* That is true on the 80386. */
707
708 #define BITS_BIG_ENDIAN 0
709
710 /* Define this if most significant byte of a word is the lowest numbered. */
711 /* That is not true on the 80386. */
712 #define BYTES_BIG_ENDIAN 0
713
714 /* Define this if most significant word of a multiword number is the lowest
715 numbered. */
716 /* Not true for 80386 */
717 #define WORDS_BIG_ENDIAN 0
718
719 /* number of bits in an addressable storage unit */
720 #define BITS_PER_UNIT 8
721
722 /* Width in bits of a "word", which is the contents of a machine register.
723 Note that this is not necessarily the width of data type `int';
724 if using 16-bit ints on a 80386, this would still be 32.
725 But on a machine with 16-bit registers, this would be 16. */
726 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
727
728 /* Width of a word, in units (bytes). */
729 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
730 #define MIN_UNITS_PER_WORD 4
731
732 /* Width in bits of a pointer.
733 See also the macro `Pmode' defined below. */
734 #define POINTER_SIZE BITS_PER_WORD
735
736 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
737 #define PARM_BOUNDARY BITS_PER_WORD
738
739 /* Boundary (in *bits*) on which stack pointer should be aligned. */
740 #define STACK_BOUNDARY BITS_PER_WORD
741
742 /* Boundary (in *bits*) on which the stack pointer preferrs to be
743 aligned; the compiler cannot rely on having this alignment. */
744 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
745
746 /* As of July 2001, many runtimes to not align the stack properly when
747 entering main. This causes expand_main_function to forcably align
748 the stack, which results in aligned frames for functions called from
749 main, though it does nothing for the alignment of main itself. */
750 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
751 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
752
753 /* Allocation boundary for the code of a function. */
754 #define FUNCTION_BOUNDARY 16
755
756 /* Alignment of field after `int : 0' in a structure. */
757
758 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
759
760 /* Minimum size in bits of the largest boundary to which any
761 and all fundamental data types supported by the hardware
762 might need to be aligned. No data type wants to be aligned
763 rounder than this.
764
765 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
766 and Pentium Pro XFmode values at 128 bit boundaries. */
767
768 #define BIGGEST_ALIGNMENT 128
769
770 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
771 #define ALIGN_MODE_128(MODE) \
772 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
773 || (MODE) == V4SFmode || (MODE) == V4SImode)
774
775 /* The published ABIs say that doubles should be aligned on word
776 boundaries, so lower the aligment for structure fields unless
777 -malign-double is set. */
778 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
779 constant. Use the smaller value in that context. */
780 #ifndef IN_TARGET_LIBS
781 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
782 #else
783 #define BIGGEST_FIELD_ALIGNMENT 32
784 #endif
785
786 /* If defined, a C expression to compute the alignment given to a
787 constant that is being placed in memory. EXP is the constant
788 and ALIGN is the alignment that the object would ordinarily have.
789 The value of this macro is used instead of that alignment to align
790 the object.
791
792 If this macro is not defined, then ALIGN is used.
793
794 The typical use of this macro is to increase alignment for string
795 constants to be word aligned so that `strcpy' calls that copy
796 constants can be done inline. */
797
798 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
799
800 /* If defined, a C expression to compute the alignment for a static
801 variable. TYPE is the data type, and ALIGN is the alignment that
802 the object would ordinarily have. The value of this macro is used
803 instead of that alignment to align the object.
804
805 If this macro is not defined, then ALIGN is used.
806
807 One use of this macro is to increase alignment of medium-size
808 data to make it all fit in fewer cache lines. Another is to
809 cause character arrays to be word-aligned so that `strcpy' calls
810 that copy constants to character arrays can be done inline. */
811
812 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
813
814 /* If defined, a C expression to compute the alignment for a local
815 variable. TYPE is the data type, and ALIGN is the alignment that
816 the object would ordinarily have. The value of this macro is used
817 instead of that alignment to align the object.
818
819 If this macro is not defined, then ALIGN is used.
820
821 One use of this macro is to increase alignment of medium-size
822 data to make it all fit in fewer cache lines. */
823
824 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
825
826 /* If defined, a C expression that gives the alignment boundary, in
827 bits, of an argument with the specified mode and type. If it is
828 not defined, `PARM_BOUNDARY' is used for all arguments. */
829
830 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
831 ix86_function_arg_boundary ((MODE), (TYPE))
832
833 /* Set this non-zero if move instructions will actually fail to work
834 when given unaligned data. */
835 #define STRICT_ALIGNMENT 0
836
837 /* If bit field type is int, don't let it cross an int,
838 and give entire struct the alignment of an int. */
839 /* Required on the 386 since it doesn't have bitfield insns. */
840 #define PCC_BITFIELD_TYPE_MATTERS 1
841 \f
842 /* Standard register usage. */
843
844 /* This processor has special stack-like registers. See reg-stack.c
845 for details. */
846
847 #define STACK_REGS
848 #define IS_STACK_MODE(MODE) \
849 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
850 || (MODE) == TFmode)
851
852 /* Number of actual hardware registers.
853 The hardware registers are assigned numbers for the compiler
854 from 0 to just below FIRST_PSEUDO_REGISTER.
855 All registers that the compiler knows about must be given numbers,
856 even those that are not normally considered general registers.
857
858 In the 80386 we give the 8 general purpose registers the numbers 0-7.
859 We number the floating point registers 8-15.
860 Note that registers 0-7 can be accessed as a short or int,
861 while only 0-3 may be used with byte `mov' instructions.
862
863 Reg 16 does not correspond to any hardware register, but instead
864 appears in the RTL as an argument pointer prior to reload, and is
865 eliminated during reloading in favor of either the stack or frame
866 pointer. */
867
868 #define FIRST_PSEUDO_REGISTER 53
869
870 /* Number of hardware registers that go into the DWARF-2 unwind info.
871 If not defined, equals FIRST_PSEUDO_REGISTER. */
872
873 #define DWARF_FRAME_REGISTERS 17
874
875 /* 1 for registers that have pervasive standard uses
876 and are not available for the register allocator.
877 On the 80386, the stack pointer is such, as is the arg pointer.
878
879 The value is an mask - bit 1 is set for fixed registers
880 for 32bit target, while 2 is set for fixed registers for 64bit.
881 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
882 */
883 #define FIXED_REGISTERS \
884 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
885 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
886 /*arg,flags,fpsr,dir,frame*/ \
887 3, 3, 3, 3, 3, \
888 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
889 0, 0, 0, 0, 0, 0, 0, 0, \
890 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
891 0, 0, 0, 0, 0, 0, 0, 0, \
892 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
893 1, 1, 1, 1, 1, 1, 1, 1, \
894 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
895 1, 1, 1, 1, 1, 1, 1, 1}
896
897
898 /* 1 for registers not available across function calls.
899 These must include the FIXED_REGISTERS and also any
900 registers that can be used without being saved.
901 The latter must include the registers where values are returned
902 and the register where structure-value addresses are passed.
903 Aside from that, you can include as many other registers as you like.
904
905 The value is an mask - bit 1 is set for call used
906 for 32bit target, while 2 is set for call used for 64bit.
907 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
908 */
909 #define CALL_USED_REGISTERS \
910 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
911 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
912 /*arg,flags,fpsr,dir,frame*/ \
913 3, 3, 3, 3, 3, \
914 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
915 3, 3, 3, 3, 3, 3, 3, 3, \
916 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
917 3, 3, 3, 3, 3, 3, 3, 3, \
918 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
919 3, 3, 3, 3, 1, 1, 1, 1, \
920 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
921 3, 3, 3, 3, 3, 3, 3, 3} \
922
923 /* Order in which to allocate registers. Each register must be
924 listed once, even those in FIXED_REGISTERS. List frame pointer
925 late and fixed registers last. Note that, in general, we prefer
926 registers listed in CALL_USED_REGISTERS, keeping the others
927 available for storage of persistent values.
928
929 Three different versions of REG_ALLOC_ORDER have been tried:
930
931 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
932 but slower code on simple functions returning values in eax.
933
934 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
935 perl 4.036 due to not being able to create a DImode register (to hold a 2
936 word union).
937
938 If the order is eax, edx, ecx, ... it produces better code for simple
939 functions, and a slightly slower compiler. Users complained about the code
940 generated by allocating edx first, so restore the 'natural' order of things. */
941
942 #define REG_ALLOC_ORDER \
943 /*ax,dx,cx,*/ \
944 { 0, 1, 2, \
945 /* bx,si,di,bp,sp,*/ \
946 3, 4, 5, 6, 7, \
947 /*r8,r9,r10,r11,*/ \
948 37,38, 39, 40, \
949 /*r12,r15,r14,r13*/ \
950 41, 44, 43, 42, \
951 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
952 21, 22, 23, 24, 25, 26, 27, 28, \
953 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
954 45, 46, 47, 48, 49, 50, 51, 52, \
955 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
956 8, 9, 10, 11, 12, 13, 14, 15, \
957 /*,arg,cc,fpsr,dir,frame*/ \
958 16,17, 18, 19, 20, \
959 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
960 29, 30, 31, 32, 33, 34, 35, 36 }
961
962 /* Macro to conditionally modify fixed_regs/call_used_regs. */
963 #define CONDITIONAL_REGISTER_USAGE \
964 do { \
965 int i; \
966 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
967 { \
968 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
969 call_used_regs[i] = (call_used_regs[i] \
970 & (TARGET_64BIT ? 2 : 1)) != 0; \
971 } \
972 if (flag_pic) \
973 { \
974 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
975 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
976 } \
977 if (! TARGET_MMX) \
978 { \
979 int i; \
980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
981 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
982 fixed_regs[i] = call_used_regs[i] = 1; \
983 } \
984 if (! TARGET_SSE) \
985 { \
986 int i; \
987 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
988 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
989 fixed_regs[i] = call_used_regs[i] = 1; \
990 } \
991 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
992 { \
993 int i; \
994 HARD_REG_SET x; \
995 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
996 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
997 if (TEST_HARD_REG_BIT (x, i)) \
998 fixed_regs[i] = call_used_regs[i] = 1; \
999 } \
1000 } while (0)
1001
1002 /* Return number of consecutive hard regs needed starting at reg REGNO
1003 to hold something of mode MODE.
1004 This is ordinarily the length in words of a value of mode MODE
1005 but can be less for certain modes in special long registers.
1006
1007 Actually there are no two word move instructions for consecutive
1008 registers. And only registers 0-3 may have mov byte instructions
1009 applied to them.
1010 */
1011
1012 #define HARD_REGNO_NREGS(REGNO, MODE) \
1013 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1014 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1015 : ((MODE) == TFmode \
1016 ? (TARGET_64BIT ? 2 : 3) \
1017 : (MODE) == TCmode \
1018 ? (TARGET_64BIT ? 4 : 6) \
1019 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1020
1021 #define VALID_SSE_REG_MODE(MODE) \
1022 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1023 || (MODE) == SFmode \
1024 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1025
1026 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1027 ((MODE) == V2SFmode || (MODE) == SFmode)
1028
1029 #define VALID_MMX_REG_MODE(MODE) \
1030 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1031 || (MODE) == V2SImode || (MODE) == SImode)
1032
1033 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1034 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1035 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1036 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1037
1038 #define VALID_FP_MODE_P(MODE) \
1039 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1040 || (!TARGET_64BIT && (MODE) == XFmode) \
1041 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1042 || (!TARGET_64BIT && (MODE) == XCmode))
1043
1044 #define VALID_INT_MODE_P(MODE) \
1045 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1046 || (MODE) == DImode \
1047 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1048 || (MODE) == CDImode \
1049 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1050
1051 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1052
1053 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1054 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1055
1056 /* Value is 1 if it is a good idea to tie two pseudo registers
1057 when one has mode MODE1 and one has mode MODE2.
1058 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1059 for any hard reg, then this must be 0 for correct output. */
1060
1061 #define MODES_TIEABLE_P(MODE1, MODE2) \
1062 ((MODE1) == (MODE2) \
1063 || (((MODE1) == HImode || (MODE1) == SImode \
1064 || ((MODE1) == QImode \
1065 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1066 || ((MODE1) == DImode && TARGET_64BIT)) \
1067 && ((MODE2) == HImode || (MODE2) == SImode \
1068 || ((MODE1) == QImode \
1069 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1070 || ((MODE2) == DImode && TARGET_64BIT))))
1071
1072
1073 /* Specify the modes required to caller save a given hard regno.
1074 We do this on i386 to prevent flags from being saved at all.
1075
1076 Kill any attempts to combine saving of modes. */
1077
1078 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1079 (CC_REGNO_P (REGNO) ? VOIDmode \
1080 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1081 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1082 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1083 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1084 : (MODE))
1085 /* Specify the registers used for certain standard purposes.
1086 The values of these macros are register numbers. */
1087
1088 /* on the 386 the pc register is %eip, and is not usable as a general
1089 register. The ordinary mov instructions won't work */
1090 /* #define PC_REGNUM */
1091
1092 /* Register to use for pushing function arguments. */
1093 #define STACK_POINTER_REGNUM 7
1094
1095 /* Base register for access to local variables of the function. */
1096 #define HARD_FRAME_POINTER_REGNUM 6
1097
1098 /* Base register for access to local variables of the function. */
1099 #define FRAME_POINTER_REGNUM 20
1100
1101 /* First floating point reg */
1102 #define FIRST_FLOAT_REG 8
1103
1104 /* First & last stack-like regs */
1105 #define FIRST_STACK_REG FIRST_FLOAT_REG
1106 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1107
1108 #define FLAGS_REG 17
1109 #define FPSR_REG 18
1110 #define DIRFLAG_REG 19
1111
1112 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1113 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1114
1115 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1116 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1117
1118 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1119 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1120
1121 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1122 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1123
1124 /* Value should be nonzero if functions must have frame pointers.
1125 Zero means the frame pointer need not be set up (and parms
1126 may be accessed via the stack pointer) in functions that seem suitable.
1127 This is computed in `reload', in reload1.c. */
1128 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1129
1130 /* Override this in other tm.h files to cope with various OS losage
1131 requiring a frame pointer. */
1132 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1133 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1134 #endif
1135
1136 /* Make sure we can access arbitrary call frames. */
1137 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1138
1139 /* Base register for access to arguments of the function. */
1140 #define ARG_POINTER_REGNUM 16
1141
1142 /* Register in which static-chain is passed to a function.
1143 We do use ECX as static chain register for 32 bit ABI. On the
1144 64bit ABI, ECX is an argument register, so we use R10 instead. */
1145 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1146
1147 /* Register to hold the addressing base for position independent
1148 code access to data items.
1149 We don't use PIC pointer for 64bit mode. Define the regnum to
1150 dummy value to prevent gcc from pessimizing code dealing with EBX.
1151 */
1152 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1153
1154 /* Register in which address to store a structure value
1155 arrives in the function. On the 386, the prologue
1156 copies this from the stack to register %eax. */
1157 #define STRUCT_VALUE_INCOMING 0
1158
1159 /* Place in which caller passes the structure value address.
1160 0 means push the value on the stack like an argument. */
1161 #define STRUCT_VALUE 0
1162
1163 /* A C expression which can inhibit the returning of certain function
1164 values in registers, based on the type of value. A nonzero value
1165 says to return the function value in memory, just as large
1166 structures are always returned. Here TYPE will be a C expression
1167 of type `tree', representing the data type of the value.
1168
1169 Note that values of mode `BLKmode' must be explicitly handled by
1170 this macro. Also, the option `-fpcc-struct-return' takes effect
1171 regardless of this macro. On most systems, it is possible to
1172 leave the macro undefined; this causes a default definition to be
1173 used, whose value is the constant 1 for `BLKmode' values, and 0
1174 otherwise.
1175
1176 Do not use this macro to indicate that structures and unions
1177 should always be returned in memory. You should instead use
1178 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1179
1180 #define RETURN_IN_MEMORY(TYPE) \
1181 ix86_return_in_memory (TYPE)
1182
1183 \f
1184 /* Define the classes of registers for register constraints in the
1185 machine description. Also define ranges of constants.
1186
1187 One of the classes must always be named ALL_REGS and include all hard regs.
1188 If there is more than one class, another class must be named NO_REGS
1189 and contain no registers.
1190
1191 The name GENERAL_REGS must be the name of a class (or an alias for
1192 another name such as ALL_REGS). This is the class of registers
1193 that is allowed by "g" or "r" in a register constraint.
1194 Also, registers outside this class are allocated only when
1195 instructions express preferences for them.
1196
1197 The classes must be numbered in nondecreasing order; that is,
1198 a larger-numbered class must never be contained completely
1199 in a smaller-numbered class.
1200
1201 For any two classes, it is very desirable that there be another
1202 class that represents their union.
1203
1204 It might seem that class BREG is unnecessary, since no useful 386
1205 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1206 and the "b" register constraint is useful in asms for syscalls.
1207
1208 The flags and fpsr registers are in no class. */
1209
1210 enum reg_class
1211 {
1212 NO_REGS,
1213 AREG, DREG, CREG, BREG, SIREG, DIREG,
1214 AD_REGS, /* %eax/%edx for DImode */
1215 Q_REGS, /* %eax %ebx %ecx %edx */
1216 NON_Q_REGS, /* %esi %edi %ebp %esp */
1217 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1218 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1219 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1220 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1221 FLOAT_REGS,
1222 SSE_REGS,
1223 MMX_REGS,
1224 FP_TOP_SSE_REGS,
1225 FP_SECOND_SSE_REGS,
1226 FLOAT_SSE_REGS,
1227 FLOAT_INT_REGS,
1228 INT_SSE_REGS,
1229 FLOAT_INT_SSE_REGS,
1230 ALL_REGS, LIM_REG_CLASSES
1231 };
1232
1233 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1234
1235 #define INTEGER_CLASS_P(CLASS) \
1236 reg_class_subset_p ((CLASS), GENERAL_REGS)
1237 #define FLOAT_CLASS_P(CLASS) \
1238 reg_class_subset_p ((CLASS), FLOAT_REGS)
1239 #define SSE_CLASS_P(CLASS) \
1240 reg_class_subset_p ((CLASS), SSE_REGS)
1241 #define MMX_CLASS_P(CLASS) \
1242 reg_class_subset_p ((CLASS), MMX_REGS)
1243 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1244 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1245 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1246 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1247 #define MAYBE_SSE_CLASS_P(CLASS) \
1248 reg_classes_intersect_p (SSE_REGS, (CLASS))
1249 #define MAYBE_MMX_CLASS_P(CLASS) \
1250 reg_classes_intersect_p (MMX_REGS, (CLASS))
1251
1252 #define Q_CLASS_P(CLASS) \
1253 reg_class_subset_p ((CLASS), Q_REGS)
1254
1255 /* Give names of register classes as strings for dump file. */
1256
1257 #define REG_CLASS_NAMES \
1258 { "NO_REGS", \
1259 "AREG", "DREG", "CREG", "BREG", \
1260 "SIREG", "DIREG", \
1261 "AD_REGS", \
1262 "Q_REGS", "NON_Q_REGS", \
1263 "INDEX_REGS", \
1264 "LEGACY_REGS", \
1265 "GENERAL_REGS", \
1266 "FP_TOP_REG", "FP_SECOND_REG", \
1267 "FLOAT_REGS", \
1268 "SSE_REGS", \
1269 "MMX_REGS", \
1270 "FP_TOP_SSE_REGS", \
1271 "FP_SECOND_SSE_REGS", \
1272 "FLOAT_SSE_REGS", \
1273 "FLOAT_INT_REGS", \
1274 "INT_SSE_REGS", \
1275 "FLOAT_INT_SSE_REGS", \
1276 "ALL_REGS" }
1277
1278 /* Define which registers fit in which classes.
1279 This is an initializer for a vector of HARD_REG_SET
1280 of length N_REG_CLASSES. */
1281
1282 #define REG_CLASS_CONTENTS \
1283 { { 0x00, 0x0 }, \
1284 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1285 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1286 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1287 { 0x03, 0x0 }, /* AD_REGS */ \
1288 { 0x0f, 0x0 }, /* Q_REGS */ \
1289 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1290 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1291 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1292 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1293 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1294 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1295 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1296 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1297 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1298 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1299 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1300 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1301 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1302 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1303 { 0xffffffff,0x1fffff } \
1304 }
1305
1306 /* The same information, inverted:
1307 Return the class number of the smallest class containing
1308 reg number REGNO. This could be a conditional expression
1309 or could index an array. */
1310
1311 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1312
1313 /* When defined, the compiler allows registers explicitly used in the
1314 rtl to be used as spill registers but prevents the compiler from
1315 extending the lifetime of these registers. */
1316
1317 #define SMALL_REGISTER_CLASSES 1
1318
1319 #define QI_REG_P(X) \
1320 (REG_P (X) && REGNO (X) < 4)
1321
1322 #define GENERAL_REGNO_P(N) \
1323 ((N) < 8 || REX_INT_REGNO_P (N))
1324
1325 #define GENERAL_REG_P(X) \
1326 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1327
1328 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1329
1330 #define NON_QI_REG_P(X) \
1331 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1332
1333 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1334 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1335
1336 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1337 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1338 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1339 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1340
1341 #define SSE_REGNO_P(N) \
1342 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1343 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1344
1345 #define SSE_REGNO(N) \
1346 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1347 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1348
1349 #define SSE_FLOAT_MODE_P(MODE) \
1350 ((TARGET_SSE_MATH && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1351
1352 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1353 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1354
1355 #define STACK_REG_P(XOP) \
1356 (REG_P (XOP) && \
1357 REGNO (XOP) >= FIRST_STACK_REG && \
1358 REGNO (XOP) <= LAST_STACK_REG)
1359
1360 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1361
1362 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1363
1364 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1365 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1366
1367 /* Indicate whether hard register numbered REG_NO should be converted
1368 to SSA form. */
1369 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1370 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1371
1372 /* The class value for index registers, and the one for base regs. */
1373
1374 #define INDEX_REG_CLASS INDEX_REGS
1375 #define BASE_REG_CLASS GENERAL_REGS
1376
1377 /* Get reg_class from a letter such as appears in the machine description. */
1378
1379 #define REG_CLASS_FROM_LETTER(C) \
1380 ((C) == 'r' ? GENERAL_REGS : \
1381 (C) == 'R' ? LEGACY_REGS : \
1382 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1383 (C) == 'Q' ? Q_REGS : \
1384 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1385 ? FLOAT_REGS \
1386 : NO_REGS) : \
1387 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1388 ? FP_TOP_REG \
1389 : NO_REGS) : \
1390 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1391 ? FP_SECOND_REG \
1392 : NO_REGS) : \
1393 (C) == 'a' ? AREG : \
1394 (C) == 'b' ? BREG : \
1395 (C) == 'c' ? CREG : \
1396 (C) == 'd' ? DREG : \
1397 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1398 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1399 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1400 (C) == 'A' ? AD_REGS : \
1401 (C) == 'D' ? DIREG : \
1402 (C) == 'S' ? SIREG : NO_REGS)
1403
1404 /* The letters I, J, K, L and M in a register constraint string
1405 can be used to stand for particular ranges of immediate operands.
1406 This macro defines what the ranges are.
1407 C is the letter, and VALUE is a constant value.
1408 Return 1 if VALUE is in the range specified by C.
1409
1410 I is for non-DImode shifts.
1411 J is for DImode shifts.
1412 K is for signed imm8 operands.
1413 L is for andsi as zero-extending move.
1414 M is for shifts that can be executed by the "lea" opcode.
1415 N is for immedaite operands for out/in instructions (0-255)
1416 */
1417
1418 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1419 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1420 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1421 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1422 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1423 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1424 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1425 : 0)
1426
1427 /* Similar, but for floating constants, and defining letters G and H.
1428 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1429 TARGET_387 isn't set, because the stack register converter may need to
1430 load 0.0 into the function value register. */
1431
1432 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1433 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1434 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1435
1436 /* A C expression that defines the optional machine-dependent
1437 constraint letters that can be used to segregate specific types of
1438 operands, usually memory references, for the target machine. Any
1439 letter that is not elsewhere defined and not matched by
1440 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1441 be defined.
1442
1443 If it is required for a particular target machine, it should
1444 return 1 if VALUE corresponds to the operand type represented by
1445 the constraint letter C. If C is not defined as an extra
1446 constraint, the value returned should be 0 regardless of VALUE. */
1447
1448 #define EXTRA_CONSTRAINT(VALUE, C) \
1449 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1450 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1451 : 0)
1452
1453 /* Place additional restrictions on the register class to use when it
1454 is necessary to be able to hold a value of mode MODE in a reload
1455 register for which class CLASS would ordinarily be used. */
1456
1457 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1458 ((MODE) == QImode && !TARGET_64BIT \
1459 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1460 ? Q_REGS : (CLASS))
1461
1462 /* Given an rtx X being reloaded into a reg required to be
1463 in class CLASS, return the class of reg to actually use.
1464 In general this is just CLASS; but on some machines
1465 in some cases it is preferable to use a more restrictive class.
1466 On the 80386 series, we prevent floating constants from being
1467 reloaded into floating registers (since no move-insn can do that)
1468 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1469
1470 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1471 QImode must go into class Q_REGS.
1472 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1473 movdf to do mem-to-mem moves through integer regs. */
1474
1475 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1476 ix86_preferred_reload_class ((X), (CLASS))
1477
1478 /* If we are copying between general and FP registers, we need a memory
1479 location. The same is true for SSE and MMX registers. */
1480 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1481 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1482
1483 /* QImode spills from non-QI registers need a scratch. This does not
1484 happen often -- the only example so far requires an uninitialized
1485 pseudo. */
1486
1487 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1488 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1489 ? Q_REGS : NO_REGS)
1490
1491 /* Return the maximum number of consecutive registers
1492 needed to represent mode MODE in a register of class CLASS. */
1493 /* On the 80386, this is the size of MODE in words,
1494 except in the FP regs, where a single reg is always enough.
1495 The TFmodes are really just 80bit values, so we use only 3 registers
1496 to hold them, instead of 4, as the size would suggest.
1497 */
1498 #define CLASS_MAX_NREGS(CLASS, MODE) \
1499 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1500 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1501 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1502 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1503
1504 /* A C expression whose value is nonzero if pseudos that have been
1505 assigned to registers of class CLASS would likely be spilled
1506 because registers of CLASS are needed for spill registers.
1507
1508 The default value of this macro returns 1 if CLASS has exactly one
1509 register and zero otherwise. On most machines, this default
1510 should be used. Only define this macro to some other expression
1511 if pseudo allocated by `local-alloc.c' end up in memory because
1512 their hard registers were needed for spill registers. If this
1513 macro returns nonzero for those classes, those pseudos will only
1514 be allocated by `global.c', which knows how to reallocate the
1515 pseudo to another register. If there would not be another
1516 register available for reallocation, you should not change the
1517 definition of this macro since the only effect of such a
1518 definition would be to slow down register allocation. */
1519
1520 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1521 (((CLASS) == AREG) \
1522 || ((CLASS) == DREG) \
1523 || ((CLASS) == CREG) \
1524 || ((CLASS) == BREG) \
1525 || ((CLASS) == AD_REGS) \
1526 || ((CLASS) == SIREG) \
1527 || ((CLASS) == DIREG))
1528
1529 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1530 to automatically clobber for all asms.
1531
1532 We do this in the new i386 backend to maintain source compatibility
1533 with the old cc0-based compiler. */
1534
1535 #define MD_ASM_CLOBBERS(CLOBBERS) \
1536 do { \
1537 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1538 (CLOBBERS)); \
1539 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1540 (CLOBBERS)); \
1541 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1542 (CLOBBERS)); \
1543 } while (0)
1544 \f
1545 /* Stack layout; function entry, exit and calling. */
1546
1547 /* Define this if pushing a word on the stack
1548 makes the stack pointer a smaller address. */
1549 #define STACK_GROWS_DOWNWARD
1550
1551 /* Define this if the nominal address of the stack frame
1552 is at the high-address end of the local variables;
1553 that is, each additional local variable allocated
1554 goes at a more negative offset in the frame. */
1555 #define FRAME_GROWS_DOWNWARD
1556
1557 /* Offset within stack frame to start allocating local variables at.
1558 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1559 first local allocated. Otherwise, it is the offset to the BEGINNING
1560 of the first local allocated. */
1561 #define STARTING_FRAME_OFFSET 0
1562
1563 /* If we generate an insn to push BYTES bytes,
1564 this says how many the stack pointer really advances by.
1565 On 386 pushw decrements by exactly 2 no matter what the position was.
1566 On the 386 there is no pushb; we use pushw instead, and this
1567 has the effect of rounding up to 2.
1568
1569 For 64bit ABI we round up to 8 bytes.
1570 */
1571
1572 #define PUSH_ROUNDING(BYTES) \
1573 (TARGET_64BIT \
1574 ? (((BYTES) + 7) & (-8)) \
1575 : (((BYTES) + 1) & (-2)))
1576
1577 /* If defined, the maximum amount of space required for outgoing arguments will
1578 be computed and placed into the variable
1579 `current_function_outgoing_args_size'. No space will be pushed onto the
1580 stack for each call; instead, the function prologue should increase the stack
1581 frame size by this amount. */
1582
1583 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1584
1585 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1586 instructions to pass outgoing arguments. */
1587
1588 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1589
1590 /* Offset of first parameter from the argument pointer register value. */
1591 #define FIRST_PARM_OFFSET(FNDECL) 0
1592
1593 /* Define this macro if functions should assume that stack space has been
1594 allocated for arguments even when their values are passed in registers.
1595
1596 The value of this macro is the size, in bytes, of the area reserved for
1597 arguments passed in registers for the function represented by FNDECL.
1598
1599 This space can be allocated by the caller, or be a part of the
1600 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1601 which. */
1602 #define REG_PARM_STACK_SPACE(FNDECL) 0
1603
1604 /* Define as a C expression that evaluates to nonzero if we do not know how
1605 to pass TYPE solely in registers. The file expr.h defines a
1606 definition that is usually appropriate, refer to expr.h for additional
1607 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1608 computed in the stack and then loaded into a register. */
1609 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1610 ((TYPE) != 0 \
1611 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1612 || TREE_ADDRESSABLE (TYPE) \
1613 || ((MODE) == TImode) \
1614 || ((MODE) == BLKmode \
1615 && ! ((TYPE) != 0 \
1616 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1617 && 0 == (int_size_in_bytes (TYPE) \
1618 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1619 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1620 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1621
1622 /* Value is the number of bytes of arguments automatically
1623 popped when returning from a subroutine call.
1624 FUNDECL is the declaration node of the function (as a tree),
1625 FUNTYPE is the data type of the function (as a tree),
1626 or for a library call it is an identifier node for the subroutine name.
1627 SIZE is the number of bytes of arguments passed on the stack.
1628
1629 On the 80386, the RTD insn may be used to pop them if the number
1630 of args is fixed, but if the number is variable then the caller
1631 must pop them all. RTD can't be used for library calls now
1632 because the library is compiled with the Unix compiler.
1633 Use of RTD is a selectable option, since it is incompatible with
1634 standard Unix calling sequences. If the option is not selected,
1635 the caller must always pop the args.
1636
1637 The attribute stdcall is equivalent to RTD on a per module basis. */
1638
1639 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1640 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1641
1642 /* Define how to find the value returned by a function.
1643 VALTYPE is the data type of the value (as a tree).
1644 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1645 otherwise, FUNC is 0. */
1646 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1647 ix86_function_value (VALTYPE)
1648
1649 #define FUNCTION_VALUE_REGNO_P(N) \
1650 ix86_function_value_regno_p (N)
1651
1652 /* Define how to find the value returned by a library function
1653 assuming the value has mode MODE. */
1654
1655 #define LIBCALL_VALUE(MODE) \
1656 ix86_libcall_value (MODE)
1657
1658 /* Define the size of the result block used for communication between
1659 untyped_call and untyped_return. The block contains a DImode value
1660 followed by the block used by fnsave and frstor. */
1661
1662 #define APPLY_RESULT_SIZE (8+108)
1663
1664 /* 1 if N is a possible register number for function argument passing. */
1665 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1666
1667 /* Define a data type for recording info about an argument list
1668 during the scan of that argument list. This data type should
1669 hold all necessary information about the function itself
1670 and about the args processed so far, enough to enable macros
1671 such as FUNCTION_ARG to determine where the next arg should go. */
1672
1673 typedef struct ix86_args {
1674 int words; /* # words passed so far */
1675 int nregs; /* # registers available for passing */
1676 int regno; /* next available register number */
1677 int sse_words; /* # sse words passed so far */
1678 int sse_nregs; /* # sse registers available for passing */
1679 int sse_regno; /* next available sse register number */
1680 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1681 } CUMULATIVE_ARGS;
1682
1683 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1684 for a call to a function whose data type is FNTYPE.
1685 For a library call, FNTYPE is 0. */
1686
1687 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1688 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1689
1690 /* Update the data in CUM to advance over an argument
1691 of mode MODE and data type TYPE.
1692 (TYPE is null for libcalls where that information may not be available.) */
1693
1694 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1695 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1696
1697 /* Define where to put the arguments to a function.
1698 Value is zero to push the argument on the stack,
1699 or a hard register in which to store the argument.
1700
1701 MODE is the argument's machine mode.
1702 TYPE is the data type of the argument (as a tree).
1703 This is null for libcalls where that information may
1704 not be available.
1705 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1706 the preceding args and about the function being called.
1707 NAMED is nonzero if this argument is a named parameter
1708 (otherwise it is an extra parameter matching an ellipsis). */
1709
1710 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1711 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1712
1713 /* For an arg passed partly in registers and partly in memory,
1714 this is the number of registers used.
1715 For args passed entirely in registers or entirely in memory, zero. */
1716
1717 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1718
1719 /* If PIC, we cannot make sibling calls to global functions
1720 because the PLT requires %ebx live.
1721 If we are returning floats on the register stack, we cannot make
1722 sibling calls to functions that return floats. (The stack adjust
1723 instruction will wind up after the sibcall jump, and not be executed.) */
1724 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1725 ((DECL) \
1726 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1727 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1728 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1729 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1730
1731 /* Perform any needed actions needed for a function that is receiving a
1732 variable number of arguments.
1733
1734 CUM is as above.
1735
1736 MODE and TYPE are the mode and type of the current parameter.
1737
1738 PRETEND_SIZE is a variable that should be set to the amount of stack
1739 that must be pushed by the prolog to pretend that our caller pushed
1740 it.
1741
1742 Normally, this macro will push all remaining incoming registers on the
1743 stack and set PRETEND_SIZE to the length of the registers pushed. */
1744
1745 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1746 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1747 (NO_RTL))
1748
1749 /* Define the `__builtin_va_list' type for the ABI. */
1750 #define BUILD_VA_LIST_TYPE(VALIST) \
1751 ((VALIST) = ix86_build_va_list ())
1752
1753 /* Implement `va_start' for varargs and stdarg. */
1754 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1755 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1756
1757 /* Implement `va_arg'. */
1758 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1759 ix86_va_arg ((VALIST), (TYPE))
1760
1761 /* This macro is invoked at the end of compilation. It is used here to
1762 output code for -fpic that will load the return address into %ebx. */
1763
1764 #undef ASM_FILE_END
1765 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1766
1767 /* Output assembler code to FILE to increment profiler label # LABELNO
1768 for profiling a function entry. */
1769
1770 #define FUNCTION_PROFILER(FILE, LABELNO) \
1771 do { \
1772 if (flag_pic) \
1773 { \
1774 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1775 LPREFIX, (LABELNO)); \
1776 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1777 } \
1778 else \
1779 { \
1780 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1781 fprintf ((FILE), "\tcall\t_mcount\n"); \
1782 } \
1783 } while (0)
1784
1785 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1786 the stack pointer does not matter. The value is tested only in
1787 functions that have frame pointers.
1788 No definition is equivalent to always zero. */
1789 /* Note on the 386 it might be more efficient not to define this since
1790 we have to restore it ourselves from the frame pointer, in order to
1791 use pop */
1792
1793 #define EXIT_IGNORE_STACK 1
1794
1795 /* Output assembler code for a block containing the constant parts
1796 of a trampoline, leaving space for the variable parts. */
1797
1798 /* On the 386, the trampoline contains two instructions:
1799 mov #STATIC,ecx
1800 jmp FUNCTION
1801 The trampoline is generated entirely at runtime. The operand of JMP
1802 is the address of FUNCTION relative to the instruction following the
1803 JMP (which is 5 bytes long). */
1804
1805 /* Length in units of the trampoline for entering a nested function. */
1806
1807 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1808
1809 /* Emit RTL insns to initialize the variable parts of a trampoline.
1810 FNADDR is an RTX for the address of the function's pure code.
1811 CXT is an RTX for the static chain value for the function. */
1812
1813 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1814 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1815 \f
1816 /* Definitions for register eliminations.
1817
1818 This is an array of structures. Each structure initializes one pair
1819 of eliminable registers. The "from" register number is given first,
1820 followed by "to". Eliminations of the same "from" register are listed
1821 in order of preference.
1822
1823 There are two registers that can always be eliminated on the i386.
1824 The frame pointer and the arg pointer can be replaced by either the
1825 hard frame pointer or to the stack pointer, depending upon the
1826 circumstances. The hard frame pointer is not used before reload and
1827 so it is not eligible for elimination. */
1828
1829 #define ELIMINABLE_REGS \
1830 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1831 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1832 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1833 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1834
1835 /* Given FROM and TO register numbers, say whether this elimination is
1836 allowed. Frame pointer elimination is automatically handled.
1837
1838 All other eliminations are valid. */
1839
1840 #define CAN_ELIMINATE(FROM, TO) \
1841 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1842
1843 /* Define the offset between two registers, one to be eliminated, and the other
1844 its replacement, at the start of a routine. */
1845
1846 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1847 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1848 \f
1849 /* Addressing modes, and classification of registers for them. */
1850
1851 /* #define HAVE_POST_INCREMENT 0 */
1852 /* #define HAVE_POST_DECREMENT 0 */
1853
1854 /* #define HAVE_PRE_DECREMENT 0 */
1855 /* #define HAVE_PRE_INCREMENT 0 */
1856
1857 /* Macros to check register numbers against specific register classes. */
1858
1859 /* These assume that REGNO is a hard or pseudo reg number.
1860 They give nonzero only if REGNO is a hard reg of the suitable class
1861 or a pseudo reg currently allocated to a suitable hard reg.
1862 Since they use reg_renumber, they are safe only once reg_renumber
1863 has been allocated, which happens in local-alloc.c. */
1864
1865 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1866 ((REGNO) < STACK_POINTER_REGNUM \
1867 || (REGNO >= FIRST_REX_INT_REG \
1868 && (REGNO) <= LAST_REX_INT_REG) \
1869 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1870 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1871 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1872
1873 #define REGNO_OK_FOR_BASE_P(REGNO) \
1874 ((REGNO) <= STACK_POINTER_REGNUM \
1875 || (REGNO) == ARG_POINTER_REGNUM \
1876 || (REGNO) == FRAME_POINTER_REGNUM \
1877 || (REGNO >= FIRST_REX_INT_REG \
1878 && (REGNO) <= LAST_REX_INT_REG) \
1879 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1880 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1881 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1882
1883 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1884 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1885 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1886 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1887
1888 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1889 and check its validity for a certain class.
1890 We have two alternate definitions for each of them.
1891 The usual definition accepts all pseudo regs; the other rejects
1892 them unless they have been allocated suitable hard regs.
1893 The symbol REG_OK_STRICT causes the latter definition to be used.
1894
1895 Most source files want to accept pseudo regs in the hope that
1896 they will get allocated to the class that the insn wants them to be in.
1897 Source files for reload pass need to be strict.
1898 After reload, it makes no difference, since pseudo regs have
1899 been eliminated by then. */
1900
1901
1902 /* Non strict versions, pseudos are ok */
1903 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1904 (REGNO (X) < STACK_POINTER_REGNUM \
1905 || (REGNO (X) >= FIRST_REX_INT_REG \
1906 && REGNO (X) <= LAST_REX_INT_REG) \
1907 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1908
1909 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1910 (REGNO (X) <= STACK_POINTER_REGNUM \
1911 || REGNO (X) == ARG_POINTER_REGNUM \
1912 || REGNO (X) == FRAME_POINTER_REGNUM \
1913 || (REGNO (X) >= FIRST_REX_INT_REG \
1914 && REGNO (X) <= LAST_REX_INT_REG) \
1915 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1916
1917 /* Strict versions, hard registers only */
1918 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1919 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1920
1921 #ifndef REG_OK_STRICT
1922 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1923 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1924
1925 #else
1926 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1927 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1928 #endif
1929
1930 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1931 that is a valid memory address for an instruction.
1932 The MODE argument is the machine mode for the MEM expression
1933 that wants to use this address.
1934
1935 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1936 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1937
1938 See legitimize_pic_address in i386.c for details as to what
1939 constitutes a legitimate address when -fpic is used. */
1940
1941 #define MAX_REGS_PER_ADDRESS 2
1942
1943 #define CONSTANT_ADDRESS_P(X) \
1944 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1945 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1946 || GET_CODE (X) == CONST_DOUBLE)
1947
1948 /* Nonzero if the constant value X is a legitimate general operand.
1949 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1950
1951 #define LEGITIMATE_CONSTANT_P(X) 1
1952
1953 #ifdef REG_OK_STRICT
1954 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1955 do { \
1956 if (legitimate_address_p ((MODE), (X), 1)) \
1957 goto ADDR; \
1958 } while (0)
1959
1960 #else
1961 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1962 do { \
1963 if (legitimate_address_p ((MODE), (X), 0)) \
1964 goto ADDR; \
1965 } while (0)
1966
1967 #endif
1968
1969 /* If defined, a C expression to determine the base term of address X.
1970 This macro is used in only one place: `find_base_term' in alias.c.
1971
1972 It is always safe for this macro to not be defined. It exists so
1973 that alias analysis can understand machine-dependent addresses.
1974
1975 The typical use of this macro is to handle addresses containing
1976 a label_ref or symbol_ref within an UNSPEC. */
1977
1978 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1979
1980 /* Try machine-dependent ways of modifying an illegitimate address
1981 to be legitimate. If we find one, return the new, valid address.
1982 This macro is used in only one place: `memory_address' in explow.c.
1983
1984 OLDX is the address as it was before break_out_memory_refs was called.
1985 In some cases it is useful to look at this to decide what needs to be done.
1986
1987 MODE and WIN are passed so that this macro can use
1988 GO_IF_LEGITIMATE_ADDRESS.
1989
1990 It is always safe for this macro to do nothing. It exists to recognize
1991 opportunities to optimize the output.
1992
1993 For the 80386, we handle X+REG by loading X into a register R and
1994 using R+REG. R will go in a general reg and indexing will be used.
1995 However, if REG is a broken-out memory address or multiplication,
1996 nothing needs to be done because REG can certainly go in a general reg.
1997
1998 When -fpic is used, special handling is needed for symbolic references.
1999 See comments by legitimize_pic_address in i386.c for details. */
2000
2001 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2002 do { \
2003 (X) = legitimize_address ((X), (OLDX), (MODE)); \
2004 if (memory_address_p ((MODE), (X))) \
2005 goto WIN; \
2006 } while (0)
2007
2008 #define REWRITE_ADDRESS(X) rewrite_address (X)
2009
2010 /* Nonzero if the constant value X is a legitimate general operand
2011 when generating PIC code. It is given that flag_pic is on and
2012 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2013
2014 #define LEGITIMATE_PIC_OPERAND_P(X) \
2015 (! SYMBOLIC_CONST (X) \
2016 || legitimate_pic_address_disp_p (X))
2017
2018 #define SYMBOLIC_CONST(X) \
2019 (GET_CODE (X) == SYMBOL_REF \
2020 || GET_CODE (X) == LABEL_REF \
2021 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2022
2023 /* Go to LABEL if ADDR (a legitimate address expression)
2024 has an effect that depends on the machine mode it is used for.
2025 On the 80386, only postdecrement and postincrement address depend thus
2026 (the amount of decrement or increment being the length of the operand). */
2027 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2028 do { \
2029 if (GET_CODE (ADDR) == POST_INC \
2030 || GET_CODE (ADDR) == POST_DEC) \
2031 goto LABEL; \
2032 } while (0)
2033 \f
2034 /* Codes for all the SSE/MMX builtins. */
2035 enum ix86_builtins
2036 {
2037 IX86_BUILTIN_ADDPS,
2038 IX86_BUILTIN_ADDSS,
2039 IX86_BUILTIN_DIVPS,
2040 IX86_BUILTIN_DIVSS,
2041 IX86_BUILTIN_MULPS,
2042 IX86_BUILTIN_MULSS,
2043 IX86_BUILTIN_SUBPS,
2044 IX86_BUILTIN_SUBSS,
2045
2046 IX86_BUILTIN_CMPEQPS,
2047 IX86_BUILTIN_CMPLTPS,
2048 IX86_BUILTIN_CMPLEPS,
2049 IX86_BUILTIN_CMPGTPS,
2050 IX86_BUILTIN_CMPGEPS,
2051 IX86_BUILTIN_CMPNEQPS,
2052 IX86_BUILTIN_CMPNLTPS,
2053 IX86_BUILTIN_CMPNLEPS,
2054 IX86_BUILTIN_CMPNGTPS,
2055 IX86_BUILTIN_CMPNGEPS,
2056 IX86_BUILTIN_CMPORDPS,
2057 IX86_BUILTIN_CMPUNORDPS,
2058 IX86_BUILTIN_CMPNEPS,
2059 IX86_BUILTIN_CMPEQSS,
2060 IX86_BUILTIN_CMPLTSS,
2061 IX86_BUILTIN_CMPLESS,
2062 IX86_BUILTIN_CMPGTSS,
2063 IX86_BUILTIN_CMPGESS,
2064 IX86_BUILTIN_CMPNEQSS,
2065 IX86_BUILTIN_CMPNLTSS,
2066 IX86_BUILTIN_CMPNLESS,
2067 IX86_BUILTIN_CMPNGTSS,
2068 IX86_BUILTIN_CMPNGESS,
2069 IX86_BUILTIN_CMPORDSS,
2070 IX86_BUILTIN_CMPUNORDSS,
2071 IX86_BUILTIN_CMPNESS,
2072
2073 IX86_BUILTIN_COMIEQSS,
2074 IX86_BUILTIN_COMILTSS,
2075 IX86_BUILTIN_COMILESS,
2076 IX86_BUILTIN_COMIGTSS,
2077 IX86_BUILTIN_COMIGESS,
2078 IX86_BUILTIN_COMINEQSS,
2079 IX86_BUILTIN_UCOMIEQSS,
2080 IX86_BUILTIN_UCOMILTSS,
2081 IX86_BUILTIN_UCOMILESS,
2082 IX86_BUILTIN_UCOMIGTSS,
2083 IX86_BUILTIN_UCOMIGESS,
2084 IX86_BUILTIN_UCOMINEQSS,
2085
2086 IX86_BUILTIN_CVTPI2PS,
2087 IX86_BUILTIN_CVTPS2PI,
2088 IX86_BUILTIN_CVTSI2SS,
2089 IX86_BUILTIN_CVTSS2SI,
2090 IX86_BUILTIN_CVTTPS2PI,
2091 IX86_BUILTIN_CVTTSS2SI,
2092
2093 IX86_BUILTIN_MAXPS,
2094 IX86_BUILTIN_MAXSS,
2095 IX86_BUILTIN_MINPS,
2096 IX86_BUILTIN_MINSS,
2097
2098 IX86_BUILTIN_LOADAPS,
2099 IX86_BUILTIN_LOADUPS,
2100 IX86_BUILTIN_STOREAPS,
2101 IX86_BUILTIN_STOREUPS,
2102 IX86_BUILTIN_LOADSS,
2103 IX86_BUILTIN_STORESS,
2104 IX86_BUILTIN_MOVSS,
2105
2106 IX86_BUILTIN_MOVHLPS,
2107 IX86_BUILTIN_MOVLHPS,
2108 IX86_BUILTIN_LOADHPS,
2109 IX86_BUILTIN_LOADLPS,
2110 IX86_BUILTIN_STOREHPS,
2111 IX86_BUILTIN_STORELPS,
2112
2113 IX86_BUILTIN_MASKMOVQ,
2114 IX86_BUILTIN_MOVMSKPS,
2115 IX86_BUILTIN_PMOVMSKB,
2116
2117 IX86_BUILTIN_MOVNTPS,
2118 IX86_BUILTIN_MOVNTQ,
2119
2120 IX86_BUILTIN_PACKSSWB,
2121 IX86_BUILTIN_PACKSSDW,
2122 IX86_BUILTIN_PACKUSWB,
2123
2124 IX86_BUILTIN_PADDB,
2125 IX86_BUILTIN_PADDW,
2126 IX86_BUILTIN_PADDD,
2127 IX86_BUILTIN_PADDSB,
2128 IX86_BUILTIN_PADDSW,
2129 IX86_BUILTIN_PADDUSB,
2130 IX86_BUILTIN_PADDUSW,
2131 IX86_BUILTIN_PSUBB,
2132 IX86_BUILTIN_PSUBW,
2133 IX86_BUILTIN_PSUBD,
2134 IX86_BUILTIN_PSUBSB,
2135 IX86_BUILTIN_PSUBSW,
2136 IX86_BUILTIN_PSUBUSB,
2137 IX86_BUILTIN_PSUBUSW,
2138
2139 IX86_BUILTIN_PAND,
2140 IX86_BUILTIN_PANDN,
2141 IX86_BUILTIN_POR,
2142 IX86_BUILTIN_PXOR,
2143
2144 IX86_BUILTIN_PAVGB,
2145 IX86_BUILTIN_PAVGW,
2146
2147 IX86_BUILTIN_PCMPEQB,
2148 IX86_BUILTIN_PCMPEQW,
2149 IX86_BUILTIN_PCMPEQD,
2150 IX86_BUILTIN_PCMPGTB,
2151 IX86_BUILTIN_PCMPGTW,
2152 IX86_BUILTIN_PCMPGTD,
2153
2154 IX86_BUILTIN_PEXTRW,
2155 IX86_BUILTIN_PINSRW,
2156
2157 IX86_BUILTIN_PMADDWD,
2158
2159 IX86_BUILTIN_PMAXSW,
2160 IX86_BUILTIN_PMAXUB,
2161 IX86_BUILTIN_PMINSW,
2162 IX86_BUILTIN_PMINUB,
2163
2164 IX86_BUILTIN_PMULHUW,
2165 IX86_BUILTIN_PMULHW,
2166 IX86_BUILTIN_PMULLW,
2167
2168 IX86_BUILTIN_PSADBW,
2169 IX86_BUILTIN_PSHUFW,
2170
2171 IX86_BUILTIN_PSLLW,
2172 IX86_BUILTIN_PSLLD,
2173 IX86_BUILTIN_PSLLQ,
2174 IX86_BUILTIN_PSRAW,
2175 IX86_BUILTIN_PSRAD,
2176 IX86_BUILTIN_PSRLW,
2177 IX86_BUILTIN_PSRLD,
2178 IX86_BUILTIN_PSRLQ,
2179 IX86_BUILTIN_PSLLWI,
2180 IX86_BUILTIN_PSLLDI,
2181 IX86_BUILTIN_PSLLQI,
2182 IX86_BUILTIN_PSRAWI,
2183 IX86_BUILTIN_PSRADI,
2184 IX86_BUILTIN_PSRLWI,
2185 IX86_BUILTIN_PSRLDI,
2186 IX86_BUILTIN_PSRLQI,
2187
2188 IX86_BUILTIN_PUNPCKHBW,
2189 IX86_BUILTIN_PUNPCKHWD,
2190 IX86_BUILTIN_PUNPCKHDQ,
2191 IX86_BUILTIN_PUNPCKLBW,
2192 IX86_BUILTIN_PUNPCKLWD,
2193 IX86_BUILTIN_PUNPCKLDQ,
2194
2195 IX86_BUILTIN_SHUFPS,
2196
2197 IX86_BUILTIN_RCPPS,
2198 IX86_BUILTIN_RCPSS,
2199 IX86_BUILTIN_RSQRTPS,
2200 IX86_BUILTIN_RSQRTSS,
2201 IX86_BUILTIN_SQRTPS,
2202 IX86_BUILTIN_SQRTSS,
2203
2204 IX86_BUILTIN_UNPCKHPS,
2205 IX86_BUILTIN_UNPCKLPS,
2206
2207 IX86_BUILTIN_ANDPS,
2208 IX86_BUILTIN_ANDNPS,
2209 IX86_BUILTIN_ORPS,
2210 IX86_BUILTIN_XORPS,
2211
2212 IX86_BUILTIN_EMMS,
2213 IX86_BUILTIN_LDMXCSR,
2214 IX86_BUILTIN_STMXCSR,
2215 IX86_BUILTIN_SFENCE,
2216
2217 /* 3DNow! Original */
2218 IX86_BUILTIN_FEMMS,
2219 IX86_BUILTIN_PAVGUSB,
2220 IX86_BUILTIN_PF2ID,
2221 IX86_BUILTIN_PFACC,
2222 IX86_BUILTIN_PFADD,
2223 IX86_BUILTIN_PFCMPEQ,
2224 IX86_BUILTIN_PFCMPGE,
2225 IX86_BUILTIN_PFCMPGT,
2226 IX86_BUILTIN_PFMAX,
2227 IX86_BUILTIN_PFMIN,
2228 IX86_BUILTIN_PFMUL,
2229 IX86_BUILTIN_PFRCP,
2230 IX86_BUILTIN_PFRCPIT1,
2231 IX86_BUILTIN_PFRCPIT2,
2232 IX86_BUILTIN_PFRSQIT1,
2233 IX86_BUILTIN_PFRSQRT,
2234 IX86_BUILTIN_PFSUB,
2235 IX86_BUILTIN_PFSUBR,
2236 IX86_BUILTIN_PI2FD,
2237 IX86_BUILTIN_PMULHRW,
2238
2239 /* 3DNow! Athlon Extensions */
2240 IX86_BUILTIN_PF2IW,
2241 IX86_BUILTIN_PFNACC,
2242 IX86_BUILTIN_PFPNACC,
2243 IX86_BUILTIN_PI2FW,
2244 IX86_BUILTIN_PSWAPDSI,
2245 IX86_BUILTIN_PSWAPDSF,
2246
2247 IX86_BUILTIN_SSE_ZERO,
2248 IX86_BUILTIN_MMX_ZERO,
2249
2250 IX86_BUILTIN_MAX
2251 };
2252 \f
2253 /* Define this macro if references to a symbol must be treated
2254 differently depending on something about the variable or
2255 function named by the symbol (such as what section it is in).
2256
2257 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2258 so that we may access it directly in the GOT. */
2259
2260 #define ENCODE_SECTION_INFO(DECL) \
2261 do { \
2262 if (flag_pic) \
2263 { \
2264 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2265 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2266 \
2267 if (GET_CODE (rtl) == MEM) \
2268 { \
2269 if (TARGET_DEBUG_ADDR \
2270 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2271 { \
2272 fprintf (stderr, "Encode %s, public = %d\n", \
2273 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2274 TREE_PUBLIC (DECL)); \
2275 } \
2276 \
2277 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2278 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2279 || ! TREE_PUBLIC (DECL)); \
2280 } \
2281 } \
2282 } while (0)
2283
2284 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2285 codes once the function is being compiled into assembly code, but
2286 not before. (It is not done before, because in the case of
2287 compiling an inline function, it would lead to multiple PIC
2288 prologues being included in functions which used inline functions
2289 and were compiled to assembly language.) */
2290
2291 #define FINALIZE_PIC \
2292 (current_function_uses_pic_offset_table |= current_function_profile)
2293
2294 \f
2295 /* Max number of args passed in registers. If this is more than 3, we will
2296 have problems with ebx (register #4), since it is a caller save register and
2297 is also used as the pic register in ELF. So for now, don't allow more than
2298 3 registers to be passed in registers. */
2299
2300 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2301
2302 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2303
2304 \f
2305 /* Specify the machine mode that this machine uses
2306 for the index in the tablejump instruction. */
2307 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2308
2309 /* Define as C expression which evaluates to nonzero if the tablejump
2310 instruction expects the table to contain offsets from the address of the
2311 table.
2312 Do not define this if the table should contain absolute addresses. */
2313 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2314
2315 /* Define this as 1 if `char' should by default be signed; else as 0. */
2316 #define DEFAULT_SIGNED_CHAR 1
2317
2318 /* Number of bytes moved into a data cache for a single prefetch operation. */
2319 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2320
2321 /* Number of prefetch operations that can be done in parallel. */
2322 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2323
2324 /* Max number of bytes we can move from memory to memory
2325 in one reasonably fast instruction. */
2326 #define MOVE_MAX 16
2327
2328 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2329 move efficiently, as opposed to MOVE_MAX which is the maximum
2330 number of bytes we can move with a single instruction. */
2331 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2332
2333 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2334 move-instruction pairs, we will do a movstr or libcall instead.
2335 Increasing the value will always make code faster, but eventually
2336 incurs high cost in increased code size.
2337
2338 If you don't define this, a reasonable default is used. */
2339
2340 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2341
2342 /* Define if shifts truncate the shift count
2343 which implies one can omit a sign-extension or zero-extension
2344 of a shift count. */
2345 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2346
2347 /* #define SHIFT_COUNT_TRUNCATED */
2348
2349 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2350 is done just by pretending it is already truncated. */
2351 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2352
2353 /* We assume that the store-condition-codes instructions store 0 for false
2354 and some other value for true. This is the value stored for true. */
2355
2356 #define STORE_FLAG_VALUE 1
2357
2358 /* When a prototype says `char' or `short', really pass an `int'.
2359 (The 386 can't easily push less than an int.) */
2360
2361 #define PROMOTE_PROTOTYPES 1
2362
2363 /* A macro to update M and UNSIGNEDP when an object whose type is
2364 TYPE and which has the specified mode and signedness is to be
2365 stored in a register. This macro is only called when TYPE is a
2366 scalar type.
2367
2368 On i386 it is sometimes useful to promote HImode and QImode
2369 quantities to SImode. The choice depends on target type. */
2370
2371 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2372 do { \
2373 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2374 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2375 (MODE) = SImode; \
2376 } while (0)
2377
2378 /* Specify the machine mode that pointers have.
2379 After generation of rtl, the compiler makes no further distinction
2380 between pointers and any other objects of this machine mode. */
2381 #define Pmode (TARGET_64BIT ? DImode : SImode)
2382
2383 /* A function address in a call instruction
2384 is a byte address (for indexing purposes)
2385 so give the MEM rtx a byte's mode. */
2386 #define FUNCTION_MODE QImode
2387 \f
2388 /* A part of a C `switch' statement that describes the relative costs
2389 of constant RTL expressions. It must contain `case' labels for
2390 expression codes `const_int', `const', `symbol_ref', `label_ref'
2391 and `const_double'. Each case must ultimately reach a `return'
2392 statement to return the relative cost of the use of that kind of
2393 constant value in an expression. The cost may depend on the
2394 precise value of the constant, which is available for examination
2395 in X, and the rtx code of the expression in which it is contained,
2396 found in OUTER_CODE.
2397
2398 CODE is the expression code--redundant, since it can be obtained
2399 with `GET_CODE (X)'. */
2400
2401 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2402 case CONST_INT: \
2403 case CONST: \
2404 case LABEL_REF: \
2405 case SYMBOL_REF: \
2406 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2407 return 3; \
2408 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2409 return 2; \
2410 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2411 \
2412 case CONST_DOUBLE: \
2413 { \
2414 int code; \
2415 if (GET_MODE (RTX) == VOIDmode) \
2416 return 0; \
2417 \
2418 code = standard_80387_constant_p (RTX); \
2419 return code == 1 ? 1 : \
2420 code == 2 ? 2 : \
2421 3; \
2422 }
2423
2424 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2425 #define TOPLEVEL_COSTS_N_INSNS(N) \
2426 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2427
2428 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2429 This can be used, for example, to indicate how costly a multiply
2430 instruction is. In writing this macro, you can use the construct
2431 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2432 instructions. OUTER_CODE is the code of the expression in which X
2433 is contained.
2434
2435 This macro is optional; do not define it if the default cost
2436 assumptions are adequate for the target machine. */
2437
2438 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2439 case ZERO_EXTEND: \
2440 /* The zero extensions is often completely free on x86_64, so make \
2441 it as cheap as possible. */ \
2442 if (TARGET_64BIT && GET_MODE (X) == DImode \
2443 && GET_MODE (XEXP (X, 0)) == SImode) \
2444 { \
2445 total = 1; goto egress_rtx_costs; \
2446 } \
2447 else \
2448 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2449 ix86_cost->add : ix86_cost->movzx); \
2450 break; \
2451 case SIGN_EXTEND: \
2452 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2453 break; \
2454 case ASHIFT: \
2455 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2456 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2457 { \
2458 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2459 if (value == 1) \
2460 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2461 if ((value == 2 || value == 3) \
2462 && !TARGET_DECOMPOSE_LEA \
2463 && ix86_cost->lea <= ix86_cost->shift_const) \
2464 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2465 } \
2466 /* fall through */ \
2467 \
2468 case ROTATE: \
2469 case ASHIFTRT: \
2470 case LSHIFTRT: \
2471 case ROTATERT: \
2472 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2473 { \
2474 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2475 { \
2476 if (INTVAL (XEXP (X, 1)) > 32) \
2477 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2478 else \
2479 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2480 } \
2481 else \
2482 { \
2483 if (GET_CODE (XEXP (X, 1)) == AND) \
2484 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2485 else \
2486 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2487 } \
2488 } \
2489 else \
2490 { \
2491 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2492 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2493 else \
2494 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2495 } \
2496 break; \
2497 \
2498 case MULT: \
2499 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2500 { \
2501 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2502 int nbits = 0; \
2503 \
2504 while (value != 0) \
2505 { \
2506 nbits++; \
2507 value >>= 1; \
2508 } \
2509 \
2510 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2511 + nbits * ix86_cost->mult_bit); \
2512 } \
2513 else /* This is arbitrary */ \
2514 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2515 + 7 * ix86_cost->mult_bit); \
2516 \
2517 case DIV: \
2518 case UDIV: \
2519 case MOD: \
2520 case UMOD: \
2521 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2522 \
2523 case PLUS: \
2524 if (!TARGET_DECOMPOSE_LEA \
2525 && INTEGRAL_MODE_P (GET_MODE (X)) \
2526 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2527 { \
2528 if (GET_CODE (XEXP (X, 0)) == PLUS \
2529 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2530 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2531 && CONSTANT_P (XEXP (X, 1))) \
2532 { \
2533 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2534 if (val == 2 || val == 4 || val == 8) \
2535 { \
2536 return (COSTS_N_INSNS (ix86_cost->lea) \
2537 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2538 (OUTER_CODE)) \
2539 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2540 (OUTER_CODE)) \
2541 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2542 } \
2543 } \
2544 else if (GET_CODE (XEXP (X, 0)) == MULT \
2545 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2546 { \
2547 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2548 if (val == 2 || val == 4 || val == 8) \
2549 { \
2550 return (COSTS_N_INSNS (ix86_cost->lea) \
2551 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2552 (OUTER_CODE)) \
2553 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2554 } \
2555 } \
2556 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2557 { \
2558 return (COSTS_N_INSNS (ix86_cost->lea) \
2559 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2560 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2561 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2562 } \
2563 } \
2564 \
2565 /* fall through */ \
2566 case AND: \
2567 case IOR: \
2568 case XOR: \
2569 case MINUS: \
2570 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2571 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2572 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2573 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2574 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2575 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2576 \
2577 /* fall through */ \
2578 case NEG: \
2579 case NOT: \
2580 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2581 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2582 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2583 \
2584 egress_rtx_costs: \
2585 break;
2586
2587
2588 /* An expression giving the cost of an addressing mode that contains
2589 ADDRESS. If not defined, the cost is computed from the ADDRESS
2590 expression and the `CONST_COSTS' values.
2591
2592 For most CISC machines, the default cost is a good approximation
2593 of the true cost of the addressing mode. However, on RISC
2594 machines, all instructions normally have the same length and
2595 execution time. Hence all addresses will have equal costs.
2596
2597 In cases where more than one form of an address is known, the form
2598 with the lowest cost will be used. If multiple forms have the
2599 same, lowest, cost, the one that is the most complex will be used.
2600
2601 For example, suppose an address that is equal to the sum of a
2602 register and a constant is used twice in the same basic block.
2603 When this macro is not defined, the address will be computed in a
2604 register and memory references will be indirect through that
2605 register. On machines where the cost of the addressing mode
2606 containing the sum is no higher than that of a simple indirect
2607 reference, this will produce an additional instruction and
2608 possibly require an additional register. Proper specification of
2609 this macro eliminates this overhead for such machines.
2610
2611 Similar use of this macro is made in strength reduction of loops.
2612
2613 ADDRESS need not be valid as an address. In such a case, the cost
2614 is not relevant and can be any value; invalid addresses need not be
2615 assigned a different cost.
2616
2617 On machines where an address involving more than one register is as
2618 cheap as an address computation involving only one register,
2619 defining `ADDRESS_COST' to reflect this can cause two registers to
2620 be live over a region of code where only one would have been if
2621 `ADDRESS_COST' were not defined in that manner. This effect should
2622 be considered in the definition of this macro. Equivalent costs
2623 should probably only be given to addresses with different numbers
2624 of registers on machines with lots of registers.
2625
2626 This macro will normally either not be defined or be defined as a
2627 constant.
2628
2629 For i386, it is better to use a complex address than let gcc copy
2630 the address into a reg and make a new pseudo. But not if the address
2631 requires to two regs - that would mean more pseudos with longer
2632 lifetimes. */
2633
2634 #define ADDRESS_COST(RTX) \
2635 ix86_address_cost (RTX)
2636
2637 /* A C expression for the cost of moving data from a register in class FROM to
2638 one in class TO. The classes are expressed using the enumeration values
2639 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2640 interpreted relative to that.
2641
2642 It is not required that the cost always equal 2 when FROM is the same as TO;
2643 on some machines it is expensive to move between registers if they are not
2644 general registers. */
2645
2646 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2647 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2648
2649 /* A C expression for the cost of moving data of mode M between a
2650 register and memory. A value of 2 is the default; this cost is
2651 relative to those in `REGISTER_MOVE_COST'.
2652
2653 If moving between registers and memory is more expensive than
2654 between two registers, you should define this macro to express the
2655 relative cost. */
2656
2657 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2658 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2659
2660 /* A C expression for the cost of a branch instruction. A value of 1
2661 is the default; other values are interpreted relative to that. */
2662
2663 #define BRANCH_COST ix86_branch_cost
2664
2665 /* Define this macro as a C expression which is nonzero if accessing
2666 less than a word of memory (i.e. a `char' or a `short') is no
2667 faster than accessing a word of memory, i.e., if such access
2668 require more than one instruction or if there is no difference in
2669 cost between byte and (aligned) word loads.
2670
2671 When this macro is not defined, the compiler will access a field by
2672 finding the smallest containing object; when it is defined, a
2673 fullword load will be used if alignment permits. Unless bytes
2674 accesses are faster than word accesses, using word accesses is
2675 preferable since it may eliminate subsequent memory access if
2676 subsequent accesses occur to other fields in the same word of the
2677 structure, but to different bytes. */
2678
2679 #define SLOW_BYTE_ACCESS 0
2680
2681 /* Nonzero if access to memory by shorts is slow and undesirable. */
2682 #define SLOW_SHORT_ACCESS 0
2683
2684 /* Define this macro to be the value 1 if unaligned accesses have a
2685 cost many times greater than aligned accesses, for example if they
2686 are emulated in a trap handler.
2687
2688 When this macro is non-zero, the compiler will act as if
2689 `STRICT_ALIGNMENT' were non-zero when generating code for block
2690 moves. This can cause significantly more instructions to be
2691 produced. Therefore, do not set this macro non-zero if unaligned
2692 accesses only add a cycle or two to the time for a memory access.
2693
2694 If the value of this macro is always zero, it need not be defined. */
2695
2696 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2697
2698 /* Define this macro to inhibit strength reduction of memory
2699 addresses. (On some machines, such strength reduction seems to do
2700 harm rather than good.) */
2701
2702 /* #define DONT_REDUCE_ADDR */
2703
2704 /* Define this macro if it is as good or better to call a constant
2705 function address than to call an address kept in a register.
2706
2707 Desirable on the 386 because a CALL with a constant address is
2708 faster than one with a register address. */
2709
2710 #define NO_FUNCTION_CSE
2711
2712 /* Define this macro if it is as good or better for a function to call
2713 itself with an explicit address than to call an address kept in a
2714 register. */
2715
2716 #define NO_RECURSIVE_FUNCTION_CSE
2717 \f
2718 /* Add any extra modes needed to represent the condition code.
2719
2720 For the i386, we need separate modes when floating-point
2721 equality comparisons are being done.
2722
2723 Add CCNO to indicate comparisons against zero that requires
2724 Overflow flag to be unset. Sign bit test is used instead and
2725 thus can be used to form "a&b>0" type of tests.
2726
2727 Add CCGC to indicate comparisons agains zero that allows
2728 unspecified garbage in the Carry flag. This mode is used
2729 by inc/dec instructions.
2730
2731 Add CCGOC to indicate comparisons agains zero that allows
2732 unspecified garbage in the Carry and Overflow flag. This
2733 mode is used to simulate comparisons of (a-b) and (a+b)
2734 against zero using sub/cmp/add operations.
2735
2736 Add CCZ to indicate that only the Zero flag is valid. */
2737
2738 #define EXTRA_CC_MODES \
2739 CC (CCGCmode, "CCGC") \
2740 CC (CCGOCmode, "CCGOC") \
2741 CC (CCNOmode, "CCNO") \
2742 CC (CCZmode, "CCZ") \
2743 CC (CCFPmode, "CCFP") \
2744 CC (CCFPUmode, "CCFPU")
2745
2746 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2747 return the mode to be used for the comparison.
2748
2749 For floating-point equality comparisons, CCFPEQmode should be used.
2750 VOIDmode should be used in all other cases.
2751
2752 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2753 possible, to allow for more combinations. */
2754
2755 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2756
2757 /* Return non-zero if MODE implies a floating point inequality can be
2758 reversed. */
2759
2760 #define REVERSIBLE_CC_MODE(MODE) 1
2761
2762 /* A C expression whose value is reversed condition code of the CODE for
2763 comparison done in CC_MODE mode. */
2764 #define REVERSE_CONDITION(CODE, MODE) \
2765 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2766 : reverse_condition_maybe_unordered (CODE))
2767
2768 \f
2769 /* Control the assembler format that we output, to the extent
2770 this does not vary between assemblers. */
2771
2772 /* How to refer to registers in assembler output.
2773 This sequence is indexed by compiler's hard-register-number (see above). */
2774
2775 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2776 For non floating point regs, the following are the HImode names.
2777
2778 For float regs, the stack top is sometimes referred to as "%st(0)"
2779 instead of just "%st". PRINT_REG handles this with the "y" code. */
2780
2781 #undef HI_REGISTER_NAMES
2782 #define HI_REGISTER_NAMES \
2783 {"ax","dx","cx","bx","si","di","bp","sp", \
2784 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2785 "flags","fpsr", "dirflag", "frame", \
2786 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2787 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2788 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2789 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2790
2791 #define REGISTER_NAMES HI_REGISTER_NAMES
2792
2793 /* Table of additional register names to use in user input. */
2794
2795 #define ADDITIONAL_REGISTER_NAMES \
2796 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2797 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2798 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2799 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2800 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2801 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2802 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2803 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2804
2805 /* Note we are omitting these since currently I don't know how
2806 to get gcc to use these, since they want the same but different
2807 number as al, and ax.
2808 */
2809
2810 #define QI_REGISTER_NAMES \
2811 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2812
2813 /* These parallel the array above, and can be used to access bits 8:15
2814 of regs 0 through 3. */
2815
2816 #define QI_HIGH_REGISTER_NAMES \
2817 {"ah", "dh", "ch", "bh", }
2818
2819 /* How to renumber registers for dbx and gdb. */
2820
2821 #define DBX_REGISTER_NUMBER(N) \
2822 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2823
2824 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2825 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2826 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2827
2828 /* Before the prologue, RA is at 0(%esp). */
2829 #define INCOMING_RETURN_ADDR_RTX \
2830 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2831
2832 /* After the prologue, RA is at -4(AP) in the current frame. */
2833 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2834 ((COUNT) == 0 \
2835 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2836 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2837
2838 /* PC is dbx register 8; let's use that column for RA. */
2839 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2840
2841 /* Before the prologue, the top of the frame is at 4(%esp). */
2842 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2843
2844 /* Describe how we implement __builtin_eh_return. */
2845 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2846 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2847
2848
2849 /* Select a format to encode pointers in exception handling data. CODE
2850 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2851 true if the symbol may be affected by dynamic relocations.
2852
2853 ??? All x86 object file formats are capable of representing this.
2854 After all, the relocation needed is the same as for the call insn.
2855 Whether or not a particular assembler allows us to enter such, I
2856 guess we'll have to see. */
2857 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2858 (flag_pic \
2859 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2860 : DW_EH_PE_absptr)
2861
2862 /* This is how to output the definition of a user-level label named NAME,
2863 such as the label on a static function or variable NAME. */
2864
2865 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2866 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2867
2868 /* Store in OUTPUT a string (made with alloca) containing
2869 an assembler-name for a local static variable named NAME.
2870 LABELNO is an integer which is different for each call. */
2871
2872 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2873 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2874 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2875
2876 /* This is how to output an insn to push a register on the stack.
2877 It need not be very fast code. */
2878
2879 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2880 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
2881
2882 /* This is how to output an insn to pop a register from the stack.
2883 It need not be very fast code. */
2884
2885 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2886 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
2887
2888 /* This is how to output an element of a case-vector that is absolute. */
2889
2890 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2891 ix86_output_addr_vec_elt ((FILE), (VALUE))
2892
2893 /* This is how to output an element of a case-vector that is relative. */
2894
2895 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2896 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2897
2898 /* Under some conditions we need jump tables in the text section, because
2899 the assembler cannot handle label differences between sections. */
2900
2901 #define JUMP_TABLES_IN_TEXT_SECTION \
2902 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2903
2904 /* A C statement that outputs an address constant appropriate to
2905 for DWARF debugging. */
2906
2907 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2908 i386_dwarf_output_addr_const ((FILE), (X))
2909
2910 /* Either simplify a location expression, or return the original. */
2911
2912 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2913 i386_simplify_dwarf_addr (X)
2914
2915 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2916 and switch back. For x86 we do this only to save a few bytes that
2917 would otherwise be unused in the text section. */
2918 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2919 asm (SECTION_OP "\n\t" \
2920 "call " USER_LABEL_PREFIX #FUNC "\n" \
2921 TEXT_SECTION_ASM_OP);
2922 \f
2923 /* Print operand X (an rtx) in assembler syntax to file FILE.
2924 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2925 Effect of various CODE letters is described in i386.c near
2926 print_operand function. */
2927
2928 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2929 ((CODE) == '*' || (CODE) == '+')
2930
2931 /* Print the name of a register based on its machine mode and number.
2932 If CODE is 'w', pretend the mode is HImode.
2933 If CODE is 'b', pretend the mode is QImode.
2934 If CODE is 'k', pretend the mode is SImode.
2935 If CODE is 'q', pretend the mode is DImode.
2936 If CODE is 'h', pretend the reg is the `high' byte register.
2937 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2938
2939 #define PRINT_REG(X, CODE, FILE) \
2940 print_reg ((X), (CODE), (FILE))
2941
2942 #define PRINT_OPERAND(FILE, X, CODE) \
2943 print_operand ((FILE), (X), (CODE))
2944
2945 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2946 print_operand_address ((FILE), (ADDR))
2947
2948 /* Print the name of a register for based on its machine mode and number.
2949 This macro is used to print debugging output.
2950 This macro is different from PRINT_REG in that it may be used in
2951 programs that are not linked with aux-output.o. */
2952
2953 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2954 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2955 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2956 fprintf ((FILE), "%d ", REGNO (X)); \
2957 if (REGNO (X) == FLAGS_REG) \
2958 { fputs ("flags", (FILE)); break; } \
2959 if (REGNO (X) == DIRFLAG_REG) \
2960 { fputs ("dirflag", (FILE)); break; } \
2961 if (REGNO (X) == FPSR_REG) \
2962 { fputs ("fpsr", (FILE)); break; } \
2963 if (REGNO (X) == ARG_POINTER_REGNUM) \
2964 { fputs ("argp", (FILE)); break; } \
2965 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2966 { fputs ("frame", (FILE)); break; } \
2967 if (STACK_TOP_P (X)) \
2968 { fputs ("st(0)", (FILE)); break; } \
2969 if (FP_REG_P (X)) \
2970 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2971 if (REX_INT_REG_P (X)) \
2972 { \
2973 switch (GET_MODE_SIZE (GET_MODE (X))) \
2974 { \
2975 default: \
2976 case 8: \
2977 fprintf ((FILE), "r%i", REGNO (X) \
2978 - FIRST_REX_INT_REG + 8); \
2979 break; \
2980 case 4: \
2981 fprintf ((FILE), "r%id", REGNO (X) \
2982 - FIRST_REX_INT_REG + 8); \
2983 break; \
2984 case 2: \
2985 fprintf ((FILE), "r%iw", REGNO (X) \
2986 - FIRST_REX_INT_REG + 8); \
2987 break; \
2988 case 1: \
2989 fprintf ((FILE), "r%ib", REGNO (X) \
2990 - FIRST_REX_INT_REG + 8); \
2991 break; \
2992 } \
2993 break; \
2994 } \
2995 switch (GET_MODE_SIZE (GET_MODE (X))) \
2996 { \
2997 case 8: \
2998 fputs ("r", (FILE)); \
2999 fputs (hi_name[REGNO (X)], (FILE)); \
3000 break; \
3001 default: \
3002 fputs ("e", (FILE)); \
3003 case 2: \
3004 fputs (hi_name[REGNO (X)], (FILE)); \
3005 break; \
3006 case 1: \
3007 fputs (qi_name[REGNO (X)], (FILE)); \
3008 break; \
3009 } \
3010 } while (0)
3011
3012 /* a letter which is not needed by the normal asm syntax, which
3013 we can use for operand syntax in the extended asm */
3014
3015 #define ASM_OPERAND_LETTER '#'
3016 #define RET return ""
3017 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3018 \f
3019 /* Define the codes that are matched by predicates in i386.c. */
3020
3021 #define PREDICATE_CODES \
3022 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3023 SYMBOL_REF, LABEL_REF, CONST}}, \
3024 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3025 SYMBOL_REF, LABEL_REF, CONST}}, \
3026 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3027 SYMBOL_REF, LABEL_REF, CONST}}, \
3028 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3029 SYMBOL_REF, LABEL_REF, CONST}}, \
3030 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3031 SYMBOL_REF, LABEL_REF, CONST}}, \
3032 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3033 SYMBOL_REF, LABEL_REF, CONST}}, \
3034 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3035 SYMBOL_REF, LABEL_REF}}, \
3036 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3037 {"const_int_1_operand", {CONST_INT}}, \
3038 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3039 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3040 LABEL_REF, SUBREG, REG, MEM}}, \
3041 {"pic_symbolic_operand", {CONST}}, \
3042 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3043 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3044 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3045 {"const1_operand", {CONST_INT}}, \
3046 {"const248_operand", {CONST_INT}}, \
3047 {"incdec_operand", {CONST_INT}}, \
3048 {"mmx_reg_operand", {REG}}, \
3049 {"reg_no_sp_operand", {SUBREG, REG}}, \
3050 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3051 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3052 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3053 {"q_regs_operand", {SUBREG, REG}}, \
3054 {"non_q_regs_operand", {SUBREG, REG}}, \
3055 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3056 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3057 GE, UNGE, LTGT, UNEQ}}, \
3058 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3059 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3060 }}, \
3061 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3062 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3063 UNGE, UNGT, LTGT, UNEQ }}, \
3064 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3065 {"ext_register_operand", {SUBREG, REG}}, \
3066 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3067 {"mult_operator", {MULT}}, \
3068 {"div_operator", {DIV}}, \
3069 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3070 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3071 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3072 LSHIFTRT, ROTATERT}}, \
3073 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3074 {"memory_displacement_operand", {MEM}}, \
3075 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3076 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3077 {"long_memory_operand", {MEM}},
3078
3079 /* A list of predicates that do special things with modes, and so
3080 should not elicit warnings for VOIDmode match_operand. */
3081
3082 #define SPECIAL_MODE_PREDICATES \
3083 "ext_register_operand",
3084 \f
3085 /* CM_32 is used by 32bit ABI
3086 CM_SMALL is small model assuming that all code and data fits in the first
3087 31bits of address space.
3088 CM_KERNEL is model assuming that all code and data fits in the negative
3089 31bits of address space.
3090 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3091 space. Size of data is unlimited.
3092 CM_LARGE is model making no assumptions about size of particular sections.
3093
3094 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3095 tables first in 31bits of address space.
3096 */
3097 enum cmodel {
3098 CM_32,
3099 CM_SMALL,
3100 CM_KERNEL,
3101 CM_MEDIUM,
3102 CM_LARGE,
3103 CM_SMALL_PIC
3104 };
3105
3106 /* Size of the RED_ZONE area. */
3107 #define RED_ZONE_SIZE 128
3108 /* Reserved area of the red zone for temporaries. */
3109 #define RED_ZONE_RESERVE 8
3110 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3111
3112 enum asm_dialect {
3113 ASM_ATT,
3114 ASM_INTEL
3115 };
3116 extern const char *ix86_asm_string;
3117 extern enum asm_dialect ix86_asm_dialect;
3118 /* Value of -mcmodel specified by user. */
3119 extern const char *ix86_cmodel_string;
3120 extern enum cmodel ix86_cmodel;
3121 \f
3122 /* Variables in i386.c */
3123 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3124 extern const char *ix86_arch_string; /* for -march=<xxx> */
3125 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3126 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3127 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3128 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3129 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3130 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3131 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3132 extern int ix86_regparm; /* ix86_regparm_string as a number */
3133 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3134 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3135 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
3136 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3137 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3138 \f
3139 /* To properly truncate FP values into integers, we need to set i387 control
3140 word. We can't emit proper mode switching code before reload, as spills
3141 generated by reload may truncate values incorrectly, but we still can avoid
3142 redundant computation of new control word by the mode switching pass.
3143 The fldcw instructions are still emitted redundantly, but this is probably
3144 not going to be noticeable problem, as most CPUs do have fast path for
3145 the sequence.
3146
3147 The machinery is to emit simple truncation instructions and split them
3148 before reload to instructions having USEs of two memory locations that
3149 are filled by this code to old and new control word.
3150
3151 Post-reload pass may be later used to eliminate the redundant fildcw if
3152 needed. */
3153
3154 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3155
3156 /* Define this macro if the port needs extra instructions inserted
3157 for mode switching in an optimizing compilation. */
3158
3159 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3160
3161 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3162 initializer for an array of integers. Each initializer element N
3163 refers to an entity that needs mode switching, and specifies the
3164 number of different modes that might need to be set for this
3165 entity. The position of the initializer in the initializer -
3166 starting counting at zero - determines the integer that is used to
3167 refer to the mode-switched entity in question. */
3168
3169 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3170
3171 /* ENTITY is an integer specifying a mode-switched entity. If
3172 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3173 return an integer value not larger than the corresponding element
3174 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3175 must be switched into prior to the execution of INSN. */
3176
3177 #define MODE_NEEDED(ENTITY, I) \
3178 (GET_CODE (I) == CALL_INSN \
3179 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3180 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3181 ? FP_CW_UNINITIALIZED \
3182 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3183 ? FP_CW_ANY \
3184 : FP_CW_STORED)
3185
3186 /* This macro specifies the order in which modes for ENTITY are
3187 processed. 0 is the highest priority. */
3188
3189 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3190
3191 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3192 is the set of hard registers live at the point where the insn(s)
3193 are to be inserted. */
3194
3195 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3196 ((MODE) == FP_CW_STORED \
3197 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3198 assign_386_stack_local (HImode, 2)), 0\
3199 : 0)
3200 \f
3201 /* Avoid renaming of stack registers, as doing so in combination with
3202 scheduling just increases amount of live registers at time and in
3203 the turn amount of fxch instructions needed.
3204
3205 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3206
3207 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3208 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3209
3210 \f
3211 /*
3212 Local variables:
3213 version-control: t
3214 End:
3215 */
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