| blob | b385bd00179bad61c304dae5d7f641200cd56ed6 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
93 #ifndef CHECK_STACK_LIMIT
94 #define CHECK_STACK_LIMIT (-1)
95 #endif
97 /* Return index of given mode in mult and division cost tables. */
98 #define MODE_INDEX(mode) \
99 ((mode) == QImode ? 0 \
100 : (mode) == HImode ? 1 \
101 : (mode) == SImode ? 2 \
102 : (mode) == DImode ? 3 \
103 : 4)
105 /* Processor costs (relative to an add) */
106 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
107 #define COSTS_N_BYTES(N) ((N) * 2)
109 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
118 const
141 in QImode, HImode and SImode.
142 Relative to reg-reg move (2). */
146 in SFmode, DFmode and XFmode */
148 in SFmode, DFmode and XFmode */
151 in SImode and DImode */
153 in SImode and DImode */
156 in SImode, DImode and TImode */
158 in SImode, DImode and TImode */
171 ix86_size_memcpy,
172 ix86_size_memset,
184 };
186 /* Processor costs (relative to an add) */
189 DUMMY_STRINGOP_ALGS};
192 DUMMY_STRINGOP_ALGS};
194 static const
217 in QImode, HImode and SImode.
218 Relative to reg-reg move (2). */
222 in SFmode, DFmode and XFmode */
224 in SFmode, DFmode and XFmode */
227 in SImode and DImode */
229 in SImode and DImode */
232 in SImode, DImode and TImode */
234 in SImode, DImode and TImode */
247 i386_memcpy,
248 i386_memset,
260 };
264 DUMMY_STRINGOP_ALGS};
267 DUMMY_STRINGOP_ALGS};
269 static const
292 in QImode, HImode and SImode.
293 Relative to reg-reg move (2). */
297 in SFmode, DFmode and XFmode */
299 in SFmode, DFmode and XFmode */
302 in SImode and DImode */
304 in SImode and DImode */
307 in SImode, DImode and TImode */
309 in SImode, DImode and TImode */
312 shared for code and data, so 4kB is
313 not really precise. */
324 i486_memcpy,
325 i486_memset,
337 };
341 DUMMY_STRINGOP_ALGS};
344 DUMMY_STRINGOP_ALGS};
346 static const
369 in QImode, HImode and SImode.
370 Relative to reg-reg move (2). */
374 in SFmode, DFmode and XFmode */
376 in SFmode, DFmode and XFmode */
379 in SImode and DImode */
381 in SImode and DImode */
384 in SImode, DImode and TImode */
386 in SImode, DImode and TImode */
399 pentium_memcpy,
400 pentium_memset,
412 };
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
415 (we ensure the alignment). For small blocks inline loop is still a
416 noticeable win, for bigger blocks either rep movsl or rep movsb is
417 way to go. Rep movsb has apparently more expensive startup time in CPU,
418 but after 4K the difference is down in the noise. */
423 DUMMY_STRINGOP_ALGS};
428 DUMMY_STRINGOP_ALGS};
429 static const
452 in QImode, HImode and SImode.
453 Relative to reg-reg move (2). */
457 in SFmode, DFmode and XFmode */
459 in SFmode, DFmode and XFmode */
462 in SImode and DImode */
464 in SImode and DImode */
467 in SImode, DImode and TImode */
469 in SImode, DImode and TImode */
482 pentiumpro_memcpy,
483 pentiumpro_memset,
495 };
499 DUMMY_STRINGOP_ALGS};
502 DUMMY_STRINGOP_ALGS};
503 static const
526 in QImode, HImode and SImode.
527 Relative to reg-reg move (2). */
531 in SFmode, DFmode and XFmode */
533 in SFmode, DFmode and XFmode */
537 in SImode and DImode */
539 in SImode and DImode */
542 in SImode, DImode and TImode */
544 in SImode, DImode and TImode */
557 geode_memcpy,
558 geode_memset,
570 };
574 DUMMY_STRINGOP_ALGS};
577 DUMMY_STRINGOP_ALGS};
578 static const
601 in QImode, HImode and SImode.
602 Relative to reg-reg move (2). */
606 in SFmode, DFmode and XFmode */
608 in SFmode, DFmode and XFmode */
611 in SImode and DImode */
613 in SImode and DImode */
616 in SImode, DImode and TImode */
618 in SImode, DImode and TImode */
622 have integrated l2 cache, but
623 optimizing for k6 is not important
624 enough to worry about that. */
634 k6_memcpy,
635 k6_memset,
647 };
649 /* For some reason, Athlon deals better with REP prefix (relative to loops)
650 compared to K8. Alignment becomes important after 8 bytes for memcpy and
651 128 bytes for memset. */
654 DUMMY_STRINGOP_ALGS};
657 DUMMY_STRINGOP_ALGS};
658 static const
681 in QImode, HImode and SImode.
682 Relative to reg-reg move (2). */
686 in SFmode, DFmode and XFmode */
688 in SFmode, DFmode and XFmode */
691 in SImode and DImode */
693 in SImode and DImode */
696 in SImode, DImode and TImode */
698 in SImode, DImode and TImode */
711 athlon_memcpy,
712 athlon_memset,
724 };
726 /* K8 has optimized REP instruction for medium sized blocks, but for very
727 small blocks it is better to use loop. For large blocks, libcall can
728 do nontemporary accesses and beat inline considerably. */
739 static const
762 in QImode, HImode and SImode.
763 Relative to reg-reg move (2). */
767 in SFmode, DFmode and XFmode */
769 in SFmode, DFmode and XFmode */
772 in SImode and DImode */
774 in SImode and DImode */
777 in SImode, DImode and TImode */
779 in SImode, DImode and TImode */
784 /* New AMD processors never drop prefetches; if they cannot be performed
785 immediately, they are queued. We set number of simultaneous prefetches
786 to a large constant to reflect this (it probably is not a good idea not
787 to limit number of prefetches at all, as their execution also takes some
788 time). */
798 k8_memcpy,
799 k8_memset,
811 };
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
848 in QImode, HImode and SImode.
849 Relative to reg-reg move (2). */
853 in SFmode, DFmode and XFmode */
855 in SFmode, DFmode and XFmode */
858 in SImode and DImode */
860 in SImode and DImode */
863 in SImode, DImode and TImode */
865 in SImode, DImode and TImode */
867 /* On K8:
868 MOVD reg64, xmmreg Double FSTORE 4
869 MOVD reg32, xmmreg Double FSTORE 4
870 On AMDFAM10:
871 MOVD reg64, xmmreg Double FADD 3
872 1/1 1/1
873 MOVD reg32, xmmreg Double FADD 3
874 1/1 1/1 */
878 /* New AMD processors never drop prefetches; if they cannot be performed
879 immediately, they are queued. We set number of simultaneous prefetches
880 to a large constant to reflect this (it probably is not a good idea not
881 to limit number of prefetches at all, as their execution also takes some
882 time). */
892 amdfam10_memcpy,
893 amdfam10_memset,
905 };
907 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
908 very small blocks it is better to use loop. For large blocks, libcall
909 can do nontemporary accesses and beat inline considerably. */
943 in QImode, HImode and SImode.
944 Relative to reg-reg move (2). */
948 in SFmode, DFmode and XFmode */
950 in SFmode, DFmode and XFmode */
953 in SImode and DImode */
955 in SImode and DImode */
958 in SImode, DImode and TImode */
960 in SImode, DImode and TImode */
962 /* On K8:
963 MOVD reg64, xmmreg Double FSTORE 4
964 MOVD reg32, xmmreg Double FSTORE 4
965 On AMDFAM10:
966 MOVD reg64, xmmreg Double FADD 3
967 1/1 1/1
968 MOVD reg32, xmmreg Double FADD 3
969 1/1 1/1 */
973 /* New AMD processors never drop prefetches; if they cannot be performed
974 immediately, they are queued. We set number of simultaneous prefetches
975 to a large constant to reflect this (it probably is not a good idea not
976 to limit number of prefetches at all, as their execution also takes some
977 time). */
987 bdver1_memcpy,
988 bdver1_memset,
1000 };
1002 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1003 very small blocks it is better to use loop. For large blocks, libcall
1004 can do nontemporary accesses and beat inline considerably. */
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1058 /* On K8:
1059 MOVD reg64, xmmreg Double FSTORE 4
1060 MOVD reg32, xmmreg Double FSTORE 4
1061 On AMDFAM10:
1062 MOVD reg64, xmmreg Double FADD 3
1063 1/1 1/1
1064 MOVD reg32, xmmreg Double FADD 3
1065 1/1 1/1 */
1069 /* New AMD processors never drop prefetches; if they cannot be performed
1070 immediately, they are queued. We set number of simultaneous prefetches
1071 to a large constant to reflect this (it probably is not a good idea not
1072 to limit number of prefetches at all, as their execution also takes some
1073 time). */
1083 bdver2_memcpy,
1084 bdver2_memset,
1096 };
1099 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1100 very small blocks it is better to use loop. For large blocks, libcall
1101 can do nontemporary accesses and beat inline considerably. */
1134 in QImode, HImode and SImode.
1135 Relative to reg-reg move (2). */
1139 in SFmode, DFmode and XFmode */
1141 in SFmode, DFmode and XFmode */
1144 in SImode and DImode */
1146 in SImode and DImode */
1149 in SImode, DImode and TImode */
1151 in SImode, DImode and TImode */
1156 /* New AMD processors never drop prefetches; if they cannot be performed
1157 immediately, they are queued. We set number of simultaneous prefetches
1158 to a large constant to reflect this (it probably is not a good idea not
1159 to limit number of prefetches at all, as their execution also takes some
1160 time). */
1170 bdver3_memcpy,
1171 bdver3_memset,
1183 };
1185 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1186 very small blocks it is better to use loop. For large blocks, libcall
1187 can do nontemporary accesses and beat inline considerably. */
1220 in QImode, HImode and SImode.
1221 Relative to reg-reg move (2). */
1225 in SFmode, DFmode and XFmode */
1227 in SFmode, DFmode and XFmode */
1230 in SImode and DImode */
1232 in SImode and DImode */
1235 in SImode, DImode and TImode */
1237 in SImode, DImode and TImode */
1242 /* New AMD processors never drop prefetches; if they cannot be performed
1243 immediately, they are queued. We set number of simultaneous prefetches
1244 to a large constant to reflect this (it probably is not a good idea not
1245 to limit number of prefetches at all, as their execution also takes some
1246 time). */
1256 bdver4_memcpy,
1257 bdver4_memset,
1269 };
1271 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1272 very small blocks it is better to use loop. For large blocks, libcall can
1273 do nontemporary accesses and beat inline considerably. */
1306 in QImode, HImode and SImode.
1307 Relative to reg-reg move (2). */
1311 in SFmode, DFmode and XFmode */
1313 in SFmode, DFmode and XFmode */
1316 in SImode and DImode */
1318 in SImode and DImode */
1321 in SImode, DImode and TImode */
1323 in SImode, DImode and TImode */
1325 /* On K8:
1326 MOVD reg64, xmmreg Double FSTORE 4
1327 MOVD reg32, xmmreg Double FSTORE 4
1328 On AMDFAM10:
1329 MOVD reg64, xmmreg Double FADD 3
1330 1/1 1/1
1331 MOVD reg32, xmmreg Double FADD 3
1332 1/1 1/1 */
1345 btver1_memcpy,
1346 btver1_memset,
1358 };
1392 in QImode, HImode and SImode.
1393 Relative to reg-reg move (2). */
1397 in SFmode, DFmode and XFmode */
1399 in SFmode, DFmode and XFmode */
1402 in SImode and DImode */
1404 in SImode and DImode */
1407 in SImode, DImode and TImode */
1409 in SImode, DImode and TImode */
1411 /* On K8:
1412 MOVD reg64, xmmreg Double FSTORE 4
1413 MOVD reg32, xmmreg Double FSTORE 4
1414 On AMDFAM10:
1415 MOVD reg64, xmmreg Double FADD 3
1416 1/1 1/1
1417 MOVD reg32, xmmreg Double FADD 3
1418 1/1 1/1 */
1430 btver2_memcpy,
1431 btver2_memset,
1443 };
1447 DUMMY_STRINGOP_ALGS};
1451 DUMMY_STRINGOP_ALGS};
1453 static const
1476 in QImode, HImode and SImode.
1477 Relative to reg-reg move (2). */
1481 in SFmode, DFmode and XFmode */
1483 in SFmode, DFmode and XFmode */
1486 in SImode and DImode */
1488 in SImode and DImode */
1491 in SImode, DImode and TImode */
1493 in SImode, DImode and TImode */
1506 pentium4_memcpy,
1507 pentium4_memset,
1519 };
1532 static const
1555 in QImode, HImode and SImode.
1556 Relative to reg-reg move (2). */
1560 in SFmode, DFmode and XFmode */
1562 in SFmode, DFmode and XFmode */
1565 in SImode and DImode */
1567 in SImode and DImode */
1570 in SImode, DImode and TImode */
1572 in SImode, DImode and TImode */
1585 nocona_memcpy,
1586 nocona_memset,
1598 };
1609 static const
1632 in QImode, HImode and SImode.
1633 Relative to reg-reg move (2). */
1637 in SFmode, DFmode and XFmode */
1639 in SFmode, DFmode and XFmode */
1642 in SImode and DImode */
1644 in SImode and DImode */
1647 in SImode, DImode and TImode */
1649 in SImode, DImode and TImode */
1662 atom_memcpy,
1663 atom_memset,
1675 };
1686 static const
1709 in QImode, HImode and SImode.
1710 Relative to reg-reg move (2). */
1714 in SFmode, DFmode and XFmode */
1716 in SFmode, DFmode and XFmode */
1719 in SImode and DImode */
1721 in SImode and DImode */
1724 in SImode, DImode and TImode */
1726 in SImode, DImode and TImode */
1739 slm_memcpy,
1740 slm_memset,
1752 };
1763 static const
1786 in QImode, HImode and SImode.
1787 Relative to reg-reg move (2). */
1791 in SFmode, DFmode and XFmode */
1793 in SFmode, DFmode and XFmode */
1796 in SImode and DImode */
1798 in SImode and DImode */
1801 in SImode, DImode and TImode */
1803 in SImode, DImode and TImode */
1816 intel_memcpy,
1817 intel_memset,
1829 };
1831 /* Generic should produce code tuned for Core-i7 (and newer chips)
1832 and btver1 (and newer chips). */
1844 static const
1847 /* On all chips taken into consideration lea is 2 cycles and more. With
1848 this cost however our current implementation of synth_mult results in
1849 use of unnecessary temporary registers causing regression on several
1850 SPECfp benchmarks. */
1871 in QImode, HImode and SImode.
1872 Relative to reg-reg move (2). */
1876 in SFmode, DFmode and XFmode */
1878 in SFmode, DFmode and XFmode */
1881 in SImode and DImode */
1883 in SImode and DImode */
1886 in SImode, DImode and TImode */
1888 in SImode, DImode and TImode */
1894 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1895 value is increased to perhaps more appropriate value of 5. */
1903 generic_memcpy,
1904 generic_memset,
1916 };
1918 /* core_cost should produce code tuned for Core familly of CPUs. */
1931 static const
1934 /* On all chips taken into consideration lea is 2 cycles and more. With
1935 this cost however our current implementation of synth_mult results in
1936 use of unnecessary temporary registers causing regression on several
1937 SPECfp benchmarks. */
1958 in QImode, HImode and SImode.
1959 Relative to reg-reg move (2). */
1963 in SFmode, DFmode and XFmode */
1965 in SFmode, DFmode and XFmode */
1968 in SImode and DImode */
1970 in SImode and DImode */
1973 in SImode, DImode and TImode */
1975 in SImode, DImode and TImode */
1981 /* FIXME perhaps more appropriate value is 5. */
1989 core_memcpy,
1990 core_memset,
2002 };
2005 /* Set by -mtune. */
2008 /* Set by -mtune or -Os. */
2011 /* Processor feature/optimization bitmasks. */
2012 #define m_386 (1<<PROCESSOR_I386)
2013 #define m_486 (1<<PROCESSOR_I486)
2014 #define m_PENT (1<<PROCESSOR_PENTIUM)
2015 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2016 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2017 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2018 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2019 #define m_CORE2 (1<<PROCESSOR_CORE2)
2020 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2021 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2022 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2023 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2024 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2025 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2026 #define m_INTEL (1<<PROCESSOR_INTEL)
2028 #define m_GEODE (1<<PROCESSOR_GEODE)
2029 #define m_K6 (1<<PROCESSOR_K6)
2030 #define m_K6_GEODE (m_K6 | m_GEODE)
2031 #define m_K8 (1<<PROCESSOR_K8)
2032 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2033 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2034 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2035 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2036 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2037 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2038 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2039 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2040 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2041 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2042 #define m_BTVER (m_BTVER1 | m_BTVER2)
2043 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2045 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2048 #undef DEF_TUNE
2049 #define DEF_TUNE(tune, name, selector) name,
2051 #undef DEF_TUNE
2052 };
2054 /* Feature tests against the various tunings. */
2057 /* Feature tests against the various tunings used to create ix86_tune_features
2058 based on the processor mask. */
2060 #undef DEF_TUNE
2061 #define DEF_TUNE(tune, name, selector) selector,
2063 #undef DEF_TUNE
2064 };
2066 /* Feature tests against the various architecture variations. */
2069 /* Feature tests against the various architecture variations, used to create
2070 ix86_arch_features based on the processor mask. */
2072 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2075 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2078 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2081 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2084 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2086 };
2088 /* In case the average insn count for single function invocation is
2089 lower than this constant, emit fast (but longer) prologue and
2090 epilogue code. */
2091 #define FAST_PROLOGUE_INSN_COUNT 20
2093 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2098 /* Array of the smallest class containing reg number REGNO, indexed by
2099 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2102 {
2103 /* ax, dx, cx, bx */
2105 /* si, di, bp, sp */
2107 /* FP registers */
2110 /* arg pointer */
2111 NON_Q_REGS,
2112 /* flags, fpsr, fpcr, frame */
2114 /* SSE registers */
2117 /* MMX registers */
2120 /* REX registers */
2123 /* SSE REX registers */
2126 /* AVX-512 SSE registers */
2131 /* Mask registers. */
2134 };
2136 /* The "default" register map used in 32bit mode. */
2139 {
2150 };
2152 /* The "default" register map used in 64bit mode. */
2155 {
2166 };
2168 /* Define the register numbers to be used in Dwarf debugging information.
2169 The SVR4 reference port C compiler uses the following register numbers
2170 in its Dwarf output code:
2171 0 for %eax (gcc regno = 0)
2172 1 for %ecx (gcc regno = 2)
2173 2 for %edx (gcc regno = 1)
2174 3 for %ebx (gcc regno = 3)
2175 4 for %esp (gcc regno = 7)
2176 5 for %ebp (gcc regno = 6)
2177 6 for %esi (gcc regno = 4)
2178 7 for %edi (gcc regno = 5)
2179 The following three DWARF register numbers are never generated by
2180 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2181 believes these numbers have these meanings.
2182 8 for %eip (no gcc equivalent)
2183 9 for %eflags (gcc regno = 17)
2184 10 for %trapno (no gcc equivalent)
2185 It is not at all clear how we should number the FP stack registers
2186 for the x86 architecture. If the version of SDB on x86/svr4 were
2187 a bit less brain dead with respect to floating-point then we would
2188 have a precedent to follow with respect to DWARF register numbers
2189 for x86 FP registers, but the SDB on x86/svr4 is so completely
2190 broken with respect to FP registers that it is hardly worth thinking
2191 of it as something to strive for compatibility with.
2192 The version of x86/svr4 SDB I have at the moment does (partially)
2193 seem to believe that DWARF register number 11 is associated with
2194 the x86 register %st(0), but that's about all. Higher DWARF
2195 register numbers don't seem to be associated with anything in
2196 particular, and even for DWARF regno 11, SDB only seems to under-
2197 stand that it should say that a variable lives in %st(0) (when
2198 asked via an `=' command) if we said it was in DWARF regno 11,
2199 but SDB still prints garbage when asked for the value of the
2200 variable in question (via a `/' command).
2201 (Also note that the labels SDB prints for various FP stack regs
2202 when doing an `x' command are all wrong.)
2203 Note that these problems generally don't affect the native SVR4
2204 C compiler because it doesn't allow the use of -O with -g and
2205 because when it is *not* optimizing, it allocates a memory
2206 location for each floating-point variable, and the memory
2207 location is what gets described in the DWARF AT_location
2208 attribute for the variable in question.
2209 Regardless of the severe mental illness of the x86/svr4 SDB, we
2210 do something sensible here and we use the following DWARF
2211 register numbers. Note that these are all stack-top-relative
2212 numbers.
2213 11 for %st(0) (gcc regno = 8)
2214 12 for %st(1) (gcc regno = 9)
2215 13 for %st(2) (gcc regno = 10)
2216 14 for %st(3) (gcc regno = 11)
2217 15 for %st(4) (gcc regno = 12)
2218 16 for %st(5) (gcc regno = 13)
2219 17 for %st(6) (gcc regno = 14)
2220 18 for %st(7) (gcc regno = 15)
2221 */
2223 {
2234 };
2236 /* Define parameter passing and return registers. */
2239 {
2241 };
2244 {
2246 };
2249 {
2251 };
2253 /* Additional registers that are clobbered by SYSV calls. */
2256 {
2261 };
2263 /* Define the structure for the machine field in struct function. */
2268 rtx rtl;
2270 };
2272 /* Structure describing stack frame layout.
2273 Stack grows downward:
2275 [arguments]
2276 <- ARG_POINTER
2277 saved pc
2279 saved static chain if ix86_static_chain_on_stack
2281 saved frame pointer if frame_pointer_needed
2282 <- HARD_FRAME_POINTER
2283 [saved regs]
2284 <- regs_save_offset
2285 [padding0]
2287 [saved SSE regs]
2288 <- sse_regs_save_offset
2289 [padding1] |
2290 | <- FRAME_POINTER
2291 [va_arg registers] |
2292 |
2293 [frame] |
2294 |
2295 [padding2] | = to_allocate
2296 <- STACK_POINTER
2297 */
2298 struct ix86_frame
2299 {
2306 /* The offsets relative to ARG_POINTER. */
2307 HOST_WIDE_INT frame_pointer_offset;
2308 HOST_WIDE_INT hard_frame_pointer_offset;
2309 HOST_WIDE_INT stack_pointer_offset;
2310 HOST_WIDE_INT hfp_save_offset;
2311 HOST_WIDE_INT reg_save_offset;
2312 HOST_WIDE_INT sse_reg_save_offset;
2314 /* When save_regs_using_mov is set, emit prologue using
2315 move instead of push instructions. */
2317 };
2319 /* Which cpu are we scheduling for. */
2322 /* Which cpu are we optimizing for. */
2325 /* Which instruction set architecture to use. */
2328 /* True if processor has SSE prefetch instruction. */
2331 /* -mstackrealign option */
2348 /* Preferred alignment for stack boundary in bits. */
2351 /* Alignment for incoming stack boundary in bits specified at
2352 command line. */
2355 /* Default alignment for incoming stack boundary in bits. */
2358 /* Alignment for incoming stack boundary in bits. */
2361 /* Calling abi specific va_list type nodes. */
2365 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2369 /* Fence to use after loop using movnt. */
2370 tree x86_mfence;
2372 /* Register class used for passing given 64bit part of the argument.
2373 These represent classes as documented by the PS ABI, with the exception
2374 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2375 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2377 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2378 whenever possible (upper half does contain padding). */
2379 enum x86_64_reg_class
2380 {
2381 X86_64_NO_CLASS,
2382 X86_64_INTEGER_CLASS,
2383 X86_64_INTEGERSI_CLASS,
2384 X86_64_SSE_CLASS,
2385 X86_64_SSESF_CLASS,
2386 X86_64_SSEDF_CLASS,
2387 X86_64_SSEUP_CLASS,
2388 X86_64_X87_CLASS,
2389 X86_64_X87UP_CLASS,
2390 X86_64_COMPLEX_X87_CLASS,
2391 X86_64_MEMORY_CLASS
2392 };
2394 #define MAX_CLASSES 8
2396 /* Table of constants used by fldpi, fldln2, etc.... */
2400 \f
2405 const_tree);
2417 enum ix86_function_specific_strings
2418 {
2419 IX86_FUNCTION_SPECIFIC_ARCH,
2420 IX86_FUNCTION_SPECIFIC_TUNE,
2421 IX86_FUNCTION_SPECIFIC_MAX
2422 };
2443 \f
2444 #ifndef SUBTARGET32_DEFAULT_CPU
2446 #endif
2448 /* Whether -mtune= or -march= were specified */
2452 /* Vectorization library interface and handlers. */
2458 /* Processor target table, indexed by processor number */
2459 struct ptt
2460 {
2468 };
2470 /* This table must be in sync with enum processor_type in i386.h. */
2472 {
2498 };
2499 \f
2500 static unsigned int
2502 {
2505 /* vzeroupper instructions are inserted immediately after reload to
2506 account for possible spills from 256bit registers. The pass
2507 reuses mode switching infrastructure by re-running mode insertion
2508 pass, so disable entities that have already been processed. */
2514 /* Call optimize_mode_switching. */
2517 }
2522 {
2532 };
2535 {
2539 {}
2541 /* opt_pass methods: */
2543 {
2545 }
2548 {
2550 }
2556 rtl_opt_pass *
2558 {
2560 }
2562 /* Return true if a red-zone is in use. */
2566 {
2568 }
2569 \f
2570 /* Return a string that documents the current -m options. The caller is
2571 responsible for freeing the string. */
2577 {
2578 struct ix86_target_opts
2579 {
2582 };
2584 /* This table is ordered so that options like -msse4.2 that imply
2585 preceding options while match those first. */
2587 {
2635 };
2637 /* Flag options. */
2639 {
2668 };
2685 /* Add -march= option. */
2687 {
2690 }
2692 /* Add -mtune= option. */
2694 {
2697 }
2699 /* Add -m32/-m64/-mx32. */
2701 {
2704 else
2706 isa &= ~ (OPTION_MASK_ISA_64BIT
2707 | OPTION_MASK_ABI_64
2709 }
2710 else
2714 /* Pick out the options in isa options. */
2716 {
2718 {
2721 }
2722 }
2725 {
2728 isa);
2729 }
2731 /* Add flag options. */
2733 {
2735 {
2738 }
2739 }
2742 {
2745 }
2747 /* Add -fpmath= option. */
2749 {
2752 {
2767 }
2768 }
2770 /* Any options? */
2776 /* Size the string. */
2780 {
2785 }
2787 /* Build the string. */
2792 {
2799 {
2801 line_len++;
2804 {
2808 }
2809 }
2813 {
2817 }
2818 }
2824 }
2826 /* Return true, if profiling code should be emitted before
2827 prologue. Otherwise it returns false.
2828 Note: For x86 with "hotfix" it is sorried. */
2829 static bool
2831 {
2833 }
2835 /* Function that is callable from the debugger to print the current
2836 options. */
2837 void ATTRIBUTE_UNUSED
2839 {
2845 {
2848 }
2849 else
2853 }
2856 #define DEF_ENUM
2857 #define DEF_ALG(alg, name) #name,
2859 #undef DEF_ENUM
2860 #undef DEF_ALG
2861 };
2863 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2864 The string is of the following form (or comma separated list of it):
2866 strategy_alg:max_size:[align|noalign]
2868 where the full size range for the strategy is either [0, max_size] or
2869 [min_size, max_size], in which min_size is the max_size + 1 of the
2870 preceding range. The last size range must have max_size == -1.
2872 Examples:
2874 1.
2875 -mmemcpy-strategy=libcall:-1:noalign
2877 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2880 2.
2881 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2883 This is to tell the compiler to use the following strategy for memset
2884 1) when the expected size is between [1, 16], use rep_8byte strategy;
2885 2) when the size is between [17, 2048], use vector_loop;
2886 3) when the size is > 2048, use libcall. */
2888 struct stringop_size_range
2889 {
2891 stringop_alg alg;
2893 };
2895 static void
2897 {
2905 else
2910 do
2911 {
2921 {
2925 }
2928 {
2932 }
2939 {
2941 alg_name,
2944 }
2952 else
2953 {
2957 }
2958 n++;
2960 }
2964 {
2969 }
2972 {
2976 }
2978 /* Now override the default algs array. */
2980 {
2986 }
2987 }
2989 \f
2990 /* parse -mtune-ctrl= option. When DUMP is true,
2991 print the features that are explicitly set. */
2993 static void
2995 {
3003 do
3004 {
3011 {
3012 curr_feature_string++;
3014 }
3016 {
3018 {
3024 }
3025 }
3030 }
3033 }
3035 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3036 processor type. */
3038 static void
3040 {
3045 {
3048 else
3050 }
3053 {
3058 }
3061 }
3064 /* Override various settings based on options. If MAIN_ARGS_P, the
3065 options are from the command line, otherwise they are from
3066 attributes. */
3068 static void
3072 {
3080 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3081 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3082 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3083 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3084 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3085 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3086 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3087 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3088 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3089 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3090 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3091 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3092 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3093 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3094 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3095 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3096 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3097 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3098 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3099 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3100 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3101 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3102 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3103 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3104 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3105 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3106 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3107 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3108 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3109 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3110 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3111 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3112 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3113 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3114 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3115 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3116 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3117 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3118 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3119 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3120 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3121 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3122 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3123 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3124 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3125 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3126 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3127 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3128 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3129 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3130 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3131 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3133 #define PTA_CORE2 \
3134 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3135 | PTA_CX16 | PTA_FXSR)
3136 #define PTA_NEHALEM \
3137 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3138 #define PTA_WESTMERE \
3139 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3140 #define PTA_SANDYBRIDGE \
3141 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3142 #define PTA_IVYBRIDGE \
3143 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3144 #define PTA_HASWELL \
3145 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3146 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3147 #define PTA_BROADWELL \
3148 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3149 #define PTA_BONNELL \
3150 (PTA_CORE2 | PTA_MOVBE)
3151 #define PTA_SILVERMONT \
3152 (PTA_WESTMERE | PTA_MOVBE)
3154 /* if this reaches 64, need to widen struct pta flags below */
3156 static struct pta
3157 {
3162 }
3164 {
3198 PTA_SANDYBRIDGE},
3200 PTA_SANDYBRIDGE},
3202 PTA_IVYBRIDGE},
3204 PTA_IVYBRIDGE},
3294 PTA_64BIT
3296 };
3298 /* -mrecip options. */
3299 static struct
3300 {
3303 }
3305 {
3312 };
3316 /* Set up prefix/suffix so the error messages refer to either the command
3317 line argument, or the attribute(target). */
3319 {
3323 }
3324 else
3325 {
3329 }
3331 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3332 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3335 #ifdef TARGET_BI_ARCH
3336 else
3337 {
3338 #if TARGET_BI_ARCH == 1
3339 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3340 is on and OPTION_MASK_ABI_X32 is off. We turn off
3341 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3342 -mx32. */
3345 #else
3346 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3347 on and OPTION_MASK_ABI_64 is off. We turn off
3348 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3349 -m64. */
3352 #endif
3353 }
3354 #endif
3357 {
3358 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3359 OPTION_MASK_ABI_64 for TARGET_X32. */
3362 }
3365 | OPTION_MASK_ABI_X32
3368 {
3369 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3370 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3373 }
3375 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3376 SUBTARGET_OVERRIDE_OPTIONS;
3377 #endif
3379 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3380 SUBSUBTARGET_OVERRIDE_OPTIONS;
3381 #endif
3383 /* -fPIC is the default for x86_64. */
3387 /* Need to check -mtune=generic first. */
3389 {
3390 /* As special support for cross compilers we read -mtune=native
3391 as -mtune=generic. With native compilers we won't see the
3392 -mtune=native, as it was changed by the driver. */
3394 {
3396 }
3401 }
3402 else
3403 {
3407 {
3408 opts->x_ix86_tune_string
3411 }
3413 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3414 or defaulted. We need to use a sensible tune option. */
3416 {
3418 }
3419 }
3423 {
3424 /* rep; movq isn't available in 32-bit code. */
3427 }
3430 opts->x_ix86_arch_string
3433 else
3437 {
3445 }
3446 else
3453 /* For targets using ms ABI enable ms-extensions, if not
3454 explicit turned off. For non-ms ABI we turn off this
3455 option. */
3460 {
3462 {
3506 {
3509 }
3517 }
3518 }
3519 else
3520 {
3521 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3522 use of rip-relative addressing. This eliminates fixups that
3523 would otherwise be needed if this object is to be placed in a
3524 DLL, and is essentially just as efficient as direct addressing. */
3530 else
3532 }
3534 {
3537 }
3545 {
3548 /* Default cpu tuning to the architecture. */
3711 }
3729 {
3733 {
3735 {
3737 {
3745 }
3746 else
3749 }
3750 }
3751 /* Intel CPUs have always interpreted SSE prefetch instructions as
3752 NOPs; so, we can enable SSE prefetch instructions even when
3753 -mtune (rather than -march) points us to a processor that has them.
3754 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3755 higher processors. */
3760 }
3768 #ifndef USE_IX86_FRAME_POINTER
3769 #define USE_IX86_FRAME_POINTER 0
3770 #endif
3772 #ifndef USE_X86_64_FRAME_POINTER
3773 #define USE_X86_64_FRAME_POINTER 0
3774 #endif
3776 /* Set the default values for switches whose default depends on TARGET_64BIT
3777 in case they weren't overwritten by command line options. */
3779 {
3787 opts->x_flag_unwind_tables
3791 }
3792 else
3793 {
3795 opts->x_flag_omit_frame_pointer
3801 }
3806 else
3809 /* Arrange to set up i386_stack_locals for all functions. */
3812 /* Validate -mregparm= value. */
3814 {
3818 {
3822 }
3823 }
3827 /* Default align_* from the processor table. */
3829 {
3832 }
3834 {
3837 }
3839 {
3841 }
3843 /* Provide default for -mbranch-cost= value. */
3848 {
3849 opts->x_target_flags
3852 /* Enable by default the SSE and MMX builtins. Do allow the user to
3853 explicitly disable any of these. In particular, disabling SSE and
3854 MMX for kernel code is extremely useful. */
3856 opts->x_ix86_isa_flags
3863 }
3864 else
3865 {
3866 opts->x_target_flags
3870 opts->x_ix86_isa_flags
3873 /* i386 ABI does not specify red zone. It still makes sense to use it
3874 when programmer takes care to stack from being destroyed. */
3877 }
3879 /* Keep nonleaf frame pointers. */
3885 /* If we're doing fast math, we don't care about comparison order
3886 wrt NaNs. This lets us use a shorter comparison sequence. */
3890 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3891 since the insns won't need emulation. */
3895 /* Likewise, if the target doesn't have a 387, or we've specified
3896 software floating point, don't use 387 inline intrinsics. */
3900 /* Turn on MMX builtins for -msse. */
3902 opts->x_ix86_isa_flags
3905 /* Enable SSE prefetch. */
3910 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3913 opts->x_ix86_isa_flags
3916 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3919 opts->x_ix86_isa_flags
3922 /* Enable lzcnt instruction for -mabm. */
3924 opts->x_ix86_isa_flags
3927 /* Validate -mpreferred-stack-boundary= value or default it to
3928 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3931 {
3938 {
3942 else
3945 }
3946 else
3947 ix86_preferred_stack_boundary
3949 }
3951 /* Set the default value for -mstackrealign. */
3957 /* Validate -mincoming-stack-boundary= value or default it to
3958 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3961 {
3968 else
3969 {
3970 ix86_user_incoming_stack_boundary
3972 ix86_incoming_stack_boundary
3974 }
3975 }
3977 /* Accept -msseregparm only if at least SSE support is enabled. */
3983 {
3985 {
3987 {
3990 }
3993 {
3996 }
3997 }
3998 }
3999 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4000 fpmath=387. The second is however default at many targets since the
4001 extra 80bit precision of temporaries is considered to be part of ABI.
4002 Overwrite the default at least for -ffast-math.
4003 TODO: -mfpmath=both seems to produce same performing code with bit
4004 smaller binaries. It is however not clear if register allocation is
4005 ready for this setting.
4006 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4007 codegen. We may switch to 387 with -ffast-math for size optimized
4008 functions. */
4012 else
4015 /* If the i387 is disabled, then do not return values in it. */
4019 /* Use external vectorized library in vectorizing intrinsics. */
4022 {
4033 }
4040 /* If stack probes are required, the space used for large function
4041 arguments on the stack must also be probed, so enable
4042 -maccumulate-outgoing-args so this happens in the prologue. */
4045 {
4050 }
4052 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4053 {
4059 }
4061 /* When scheduling description is not available, disable scheduler pass
4062 so it won't slow down the compilation and make x87 code slower. */
4083 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4085 && HAVE_prefetch
4090 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4091 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4096 {
4099 {
4101 ix86_gen_tls_local_dynamic_base_64
4103 }
4104 else
4105 {
4107 ix86_gen_tls_local_dynamic_base_64
4109 }
4110 }
4111 else
4115 {
4125 }
4126 else
4127 {
4137 }
4139 #ifdef USE_IX86_CLD
4140 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4143 #endif
4146 {
4151 }
4153 {
4157 }
4159 {
4160 #if defined(PROFILE_BEFORE_PROLOGUE)
4162 #else
4164 #endif
4165 }
4167 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4168 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4169 AVX unaligned load/store. */
4171 {
4181 /* Enable 128-bit AVX instruction generation
4182 for the auto-vectorizer. */
4186 }
4189 {
4196 {
4199 {
4201 q++;
4202 }
4203 else
4208 else
4209 {
4212 {
4215 }
4218 {
4222 }
4223 }
4228 else
4230 }
4231 }
4238 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4239 for 64-bit Bionic. */
4244 ? MASK_LONG_DOUBLE_128
4247 /* Only one of them can be active. */
4251 /* Save the initial options in case the user does function specific
4252 options. */
4254 target_option_default_node = target_option_current_node
4257 /* Handle stack protector */
4259 opts->x_ix86_stack_protector_guard
4262 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4264 {
4268 }
4271 {
4275 }
4276 }
4278 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4280 static void
4282 {
4284 static struct register_pass_info insert_vzeroupper_info
4287 };
4292 /* This needs to be done at start up. It's convenient to do it here. */
4294 }
4296 /* Update register usage after having seen the compiler flags. */
4298 static void
4300 {
4304 /* The PIC register, if it exists, is fixed. */
4309 /* For 32-bit targets, squash the REX registers. */
4311 {
4318 }
4320 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4328 {
4329 /* Set/reset conditionally defined registers from
4330 CALL_USED_REGISTERS initializer. */
4334 /* Calculate registers of CLOBBERED_REGS register set
4335 as call used registers from GENERAL_REGS register set. */
4339 }
4341 /* If MMX is disabled, squash the registers. */
4347 /* If SSE is disabled, squash the registers. */
4353 /* If the FPU is disabled, squash the registers. */
4359 /* If AVX512F is disabled, squash the registers. */
4361 {
4367 }
4368 }
4370 \f
4371 /* Save the current options */
4373 static void
4376 {
4411 /* The fields are char but the variables are not; make sure the
4412 values fit in the fields. */
4417 }
4419 /* Restore the current options */
4421 static void
4424 {
4430 /* We don't change -fPIC. */
4467 /* Recreate the arch feature tests if the arch changed */
4469 {
4474 }
4476 /* Recreate the tune optimization tests */
4479 }
4481 /* Print the current options */
4483 static void
4486 {
4504 {
4507 }
4508 }
4510 \f
4511 /* Inner function to process the attribute((target(...))), take an argument and
4512 set the current options from the argument. If we have a list, recursively go
4513 over the list. */
4515 static bool
4520 {
4524 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4525 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4526 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4527 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4528 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4530 enum ix86_opt_type
4531 {
4532 ix86_opt_unknown,
4533 ix86_opt_yes,
4534 ix86_opt_no,
4535 ix86_opt_str,
4536 ix86_opt_enum,
4537 ix86_opt_isa
4538 };
4540 static const struct
4541 {
4548 /* isa options */
4597 /* enum options */
4600 /* string options */
4604 /* flag options */
4606 OPT_mcld,
4607 MASK_CLD),
4610 OPT_mfancy_math_387,
4611 MASK_NO_FANCY_MATH_387),
4614 OPT_mieee_fp,
4615 MASK_IEEE_FP),
4618 OPT_minline_all_stringops,
4619 MASK_INLINE_ALL_STRINGOPS),
4622 OPT_minline_stringops_dynamically,
4623 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4626 OPT_mno_align_stringops,
4627 MASK_NO_ALIGN_STRINGOPS),
4630 OPT_mrecip,
4631 MASK_RECIP),
4633 };
4635 /* If this is a list, recurse to get the options. */
4637 {
4644 enum_opts_set))
4648 }
4651 {
4654 }
4656 /* Handle multiple arguments separated by commas. */
4660 {
4674 {
4678 }
4679 else
4680 {
4683 }
4685 /* Recognize no-xxx. */
4687 {
4691 }
4692 else
4695 /* Find the option. */
4699 {
4707 {
4712 }
4713 }
4715 /* Process the option. */
4717 {
4720 }
4723 {
4729 }
4732 {
4738 else
4740 }
4743 {
4745 {
4748 }
4749 else
4751 }
4754 {
4762 global_dc);
4763 else
4764 {
4767 }
4768 }
4770 else
4772 }
4775 }
4777 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4779 tree
4783 {
4798 /* Process each of the options on the chain. */
4803 /* If the changed options are different from the default, rerun
4804 ix86_option_override_internal, and then save the options away.
4805 The string options are are attribute options, and will be undone
4806 when we copy the save structure. */
4812 {
4813 /* If we are using the default tune= or arch=, undo the string assigned,
4814 and use the default. */
4825 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4830 {
4833 }
4835 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4838 /* Add any builtin functions with the new isa if any. */
4841 /* Save the current options unless we are validating options for
4842 #pragma. */
4849 /* Free up memory allocated to hold the strings */
4852 }
4855 }
4857 /* Hook to validate attribute((target("string"))). */
4859 static bool
4862 tree args,
4864 {
4869 /* attribute((target("default"))) does nothing, beyond
4870 affecting multi-versioning. */
4879 /* Get the optimization options of the current function. */
4885 /* Init func_options. */
4893 /* Initialize func_options to the default before its target options can
4894 be set. */
4907 {
4912 }
4915 }
4917 \f
4918 /* Hook to determine if one function can safely inline another. */
4920 static bool
4922 {
4927 /* If callee has no option attributes, then it is ok to inline. */
4931 /* If caller has no option attributes, but callee does then it is not ok to
4932 inline. */
4936 else
4937 {
4941 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4942 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4943 function. */
4948 /* See if we have the same non-isa options. */
4952 /* See if arch, tune, etc. are the same. */
4965 else
4967 }
4970 }
4972 \f
4973 /* Remember the last target of ix86_set_current_function. */
4976 /* Invalidate ix86_previous_fndecl cache. */
4977 void
4979 {
4981 }
4983 /* Establish appropriate back-end context for processing the function
4984 FNDECL. The argument might be NULL to indicate processing at top
4985 level, outside of any function scope. */
4986 static void
4988 {
4989 /* Only change the context if the function changes. This hook is called
4990 several times in the course of compiling a function, and we don't want to
4991 slow things down too much or call target_reinit when it isn't safe. */
4993 {
4994 tree old_tree = (ix86_previous_fndecl
4998 tree new_tree = (fndecl
5004 ;
5007 {
5012 else
5015 }
5018 {
5026 else
5029 }
5030 }
5031 }
5033 \f
5034 /* Return true if this goes in large data/bss. */
5036 static bool
5038 {
5042 /* Functions are never large data. */
5047 {
5053 }
5054 else
5055 {
5058 /* If this is an incomplete type with size 0, then we can't put it
5059 in data because it might be too big when completed. Also,
5060 int_size_in_bytes returns -1 if size can vary or is larger than
5061 an integer in which case also it is safer to assume that it goes in
5062 large data. */
5065 }
5068 }
5070 /* Switch to the appropriate section for output of DECL.
5071 DECL is either a `VAR_DECL' node or a constant of some sort.
5072 RELOC indicates whether forming the initial value of DECL requires
5073 link-time relocations. */
5078 {
5081 {
5085 {
5119 /* We don't split these for medium model. Place them into
5120 default sections and hope for best. */
5122 }
5124 {
5125 /* We might get called with string constants, but get_named_section
5126 doesn't like them as they are not DECLs. Also, we need to set
5127 flags in that case. */
5131 }
5132 }
5134 }
5136 /* Select a set of attributes for section NAME based on the properties
5137 of DECL and whether or not RELOC indicates that DECL's initializer
5138 might contain runtime relocations. */
5140 static unsigned int ATTRIBUTE_UNUSED
5142 {
5156 }
5158 /* Build up a unique section name, expressed as a
5159 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5160 RELOC indicates whether the initial value of EXP requires
5161 link-time relocations. */
5163 static void ATTRIBUTE_UNUSED
5165 {
5168 {
5170 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5174 {
5198 /* We don't split these for medium model. Place them into
5199 default sections and hope for best. */
5201 }
5203 {
5210 /* If we're using one_only, then there needs to be a .gnu.linkonce
5211 prefix to the section name. */
5218 }
5219 }
5221 }
5223 #ifdef COMMON_ASM_OP
5224 /* This says how to output assembler code to declare an
5225 uninitialized external linkage data object.
5227 For medium model x86-64 we need to use .largecomm opcode for
5228 large objects. */
5229 void
5233 {
5237 else
5242 }
5243 #endif
5245 /* Utility function for targets to use in implementing
5246 ASM_OUTPUT_ALIGNED_BSS. */
5248 void
5252 {
5256 else
5259 #ifdef ASM_DECLARE_OBJECT_NAME
5262 #else
5263 /* Standard thing is just output label for the object. */
5267 }
5268 \f
5269 /* Decide whether we must probe the stack before any space allocation
5270 on this target. It's essentially TARGET_STACK_PROBE except when
5271 -fstack-check causes the stack to be already probed differently. */
5273 bool
5275 {
5276 /* Do not probe the stack twice if static stack checking is enabled. */
5281 }
5282 \f
5283 /* Decide whether we can make a sibling call to a function. DECL is the
5284 declaration of the function being targeted by the call and EXP is the
5285 CALL_EXPR representing the call. */
5287 static bool
5289 {
5293 /* If we are generating position-independent code, we cannot sibcall
5294 optimize any indirect call, or a direct call to a global function,
5295 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5297 && !TARGET_64BIT
5298 && flag_pic
5302 /* If we need to align the outgoing stack, then sibcalling would
5303 unalign the stack, which may break the called function. */
5309 {
5312 }
5313 else
5314 {
5315 /* We're looking at the CALL_EXPR, we need the type of the function. */
5320 }
5322 /* Check that the return value locations are the same. Like
5323 if we are returning floats on the 80387 register stack, we cannot
5324 make a sibcall from a function that doesn't return a float to a
5325 function that does or, conversely, from a function that does return
5326 a float to a function that doesn't; the necessary stack adjustment
5327 would not be executed. This is also the place we notice
5328 differences in the return value ABI. Note that it is ok for one
5329 of the functions to have void return type as long as the return
5330 value of the other is passed in a register. */
5335 {
5338 }
5340 ;
5345 {
5346 /* The SYSV ABI has more call-clobbered registers;
5347 disallow sibcalls from MS to SYSV. */
5351 }
5352 else
5353 {
5354 /* If this call is indirect, we'll need to be able to use a
5355 call-clobbered register for the address of the target function.
5356 Make sure that all such registers are not used for passing
5357 parameters. Note that DLLIMPORT functions are indirect. */
5360 {
5362 {
5363 /* ??? Need to count the actual number of registers to be used,
5364 not the possible number of registers. Fix later. */
5366 }
5367 }
5368 }
5370 /* Otherwise okay. That also includes certain types of indirect calls. */
5372 }
5374 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5375 and "sseregparm" calling convention attributes;
5376 arguments as in struct attribute_spec.handler. */
5378 static tree
5380 tree args,
5383 {
5388 {
5390 name);
5393 }
5395 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5397 {
5398 tree cst;
5401 {
5403 }
5406 {
5408 }
5412 {
5415 name);
5417 }
5419 {
5423 }
5426 }
5429 {
5430 /* Do not warn when emulating the MS ABI. */
5435 name);
5438 }
5440 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5442 {
5444 {
5446 }
5448 {
5450 }
5452 {
5454 }
5456 {
5458 }
5459 }
5461 /* Can combine stdcall with fastcall (redundant), regparm and
5462 sseregparm. */
5464 {
5466 {
5468 }
5470 {
5472 }
5474 {
5476 }
5477 }
5479 /* Can combine cdecl with regparm and sseregparm. */
5481 {
5483 {
5485 }
5487 {
5489 }
5491 {
5493 }
5494 }
5496 {
5499 name);
5501 {
5503 }
5505 {
5507 }
5509 {
5511 }
5512 }
5514 /* Can combine sseregparm with all attributes. */
5517 }
5519 /* The transactional memory builtins are implicitly regparm or fastcall
5520 depending on the ABI. Override the generic do-nothing attribute that
5521 these builtins were declared with, and replace it with one of the two
5522 attributes that we expect elsewhere. */
5524 static tree
5526 tree args ATTRIBUTE_UNUSED,
5528 {
5529 tree alt;
5531 /* In no case do we want to add the placeholder attribute. */
5534 /* The 64-bit ABI is unchanged for transactional memory. */
5538 /* ??? Is there a better way to validate 32-bit windows? We have
5539 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5542 else
5543 {
5546 }
5550 }
5552 /* This function determines from TYPE the calling-convention. */
5554 unsigned int
5556 {
5559 tree attrs;
5566 {
5576 /* Regparam isn't allowed for thiscall and fastcall. */
5578 {
5583 }
5587 }
5594 || is_stdarg
5600 }
5602 /* Return 0 if the attributes for two types are incompatible, 1 if they
5603 are compatible, and 2 if they are nearly compatible (which causes a
5604 warning to be generated). */
5606 static int
5608 {
5624 }
5625 \f
5626 /* Return the regparm value for a function with the indicated TYPE and DECL.
5627 DECL may be NULL when calling function indirectly
5628 or considering a libcall. */
5630 static int
5632 {
5633 tree attr;
5644 {
5647 {
5650 }
5651 }
5657 /* Use register calling convention for local functions when possible. */
5660 /* Caller and callee must agree on the calling convention, so
5661 checking here just optimize means that with
5662 __attribute__((optimize (...))) caller could use regparm convention
5663 and callee not, or vice versa. Instead look at whether the callee
5664 is optimized or not. */
5667 {
5668 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5671 {
5674 /* Make sure no regparm register is taken by a
5675 fixed register variable. */
5680 /* We don't want to use regparm(3) for nested functions as
5681 these use a static chain pointer in the third argument. */
5685 /* In 32-bit mode save a register for the split stack. */
5689 /* Each fixed register usage increases register pressure,
5690 so less registers should be used for argument passing.
5691 This functionality can be overriden by an explicit
5692 regparm value. */
5695 globals++;
5697 local_regparm
5702 }
5703 }
5706 }
5708 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5709 DFmode (2) arguments in SSE registers for a function with the
5710 indicated TYPE and DECL. DECL may be NULL when calling function
5711 indirectly or considering a libcall. Otherwise return 0. */
5713 static int
5715 {
5718 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5719 by the sseregparm attribute. */
5722 {
5724 {
5726 {
5730 else
5733 }
5735 }
5738 }
5740 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5741 (and DFmode for SSE2) arguments in SSE registers. */
5744 {
5745 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5749 }
5752 }
5754 /* Return true if EAX is live at the start of the function. Used by
5755 ix86_expand_prologue to determine if we need special help before
5756 calling allocate_stack_worker. */
5758 static bool
5760 {
5761 /* Cheat. Don't bother working forward from ix86_function_regparm
5762 to the function type to whether an actual argument is located in
5763 eax. Instead just look at cfg info, which is still close enough
5764 to correct at this point. This gives false positives for broken
5765 functions that might use uninitialized data that happens to be
5766 allocated in eax, but who cares? */
5768 }
5770 static bool
5772 {
5773 tree attr;
5776 {
5782 /* For 32-bit MS-ABI the default is to keep aggregate
5783 return pointer. */
5786 }
5788 }
5790 /* Value is the number of bytes of arguments automatically
5791 popped when returning from a subroutine call.
5792 FUNDECL is the declaration node of the function (as a tree),
5793 FUNTYPE is the data type of the function (as a tree),
5794 or for a library call it is an identifier node for the subroutine name.
5795 SIZE is the number of bytes of arguments passed on the stack.
5797 On the 80386, the RTD insn may be used to pop them if the number
5798 of args is fixed, but if the number is variable then the caller
5799 must pop them all. RTD can't be used for library calls now
5800 because the library is compiled with the Unix compiler.
5801 Use of RTD is a selectable option, since it is incompatible with
5802 standard Unix calling sequences. If the option is not selected,
5803 the caller must always pop the args.
5805 The attribute stdcall is equivalent to RTD on a per module basis. */
5807 static int
5809 {
5812 /* None of the 64-bit ABIs pop arguments. */
5823 /* Lose any fake structure return argument if it is passed on the stack. */
5826 {
5830 }
5833 }
5835 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5837 static bool
5839 {
5840 /* Check operand constraints in case hard registers were propagated
5841 into insn pattern. This check prevents combine pass from
5842 generating insn patterns with invalid hard register operands.
5843 These invalid insns can eventually confuse reload to error out
5844 with a spill failure. See also PRs 46829 and 46843. */
5846 {
5855 {
5863 /* For pre-AVX disallow unaligned loads/stores where the
5864 instructions don't support it. */
5868 {
5872 }
5874 /* A unary operator may be accepted by the predicate, but it
5875 is irrelevant for matching constraints. */
5880 {
5888 }
5895 /* Operand has no constraints, anything is OK. */
5900 {
5905 && operands_match_p
5909 {
5912 }
5913 }
5917 }
5918 }
5921 }
5922 \f
5923 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5925 static unsigned HOST_WIDE_INT
5927 {
5931 }
5932 \f
5933 /* Argument support functions. */
5935 /* Return true when register may be used to pass function parameters. */
5936 bool
5938 {
5943 {
5947 else
5953 }
5959 /* TODO: The function should depend on current function ABI but
5960 builtins.c would need updating then. Therefore we use the
5961 default ABI. */
5963 /* RAX is used as hidden argument to va_arg functions. */
5969 else
5976 }
5978 /* Return if we do not know how to pass TYPE solely in registers. */
5980 static bool
5982 {
5986 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5987 The layout_type routine is crafty and tries to trick us into passing
5988 currently unsupported vector types on the stack by using TImode. */
5991 }
5993 /* It returns the size, in bytes, of the area reserved for arguments passed
5994 in registers for the function represented by fndecl dependent to the used
5995 abi format. */
5996 int
5998 {
6002 else
6007 }
6009 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6010 call abi used. */
6011 enum calling_abi
6013 {
6015 {
6018 {
6021 }
6025 }
6027 }
6029 /* We add this as a workaround in order to use libc_has_function
6030 hook in i386.md. */
6031 bool
6033 {
6035 }
6037 static bool
6039 {
6041 {
6045 else
6047 }
6049 }
6051 static enum calling_abi
6053 {
6057 }
6059 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6060 call abi used. */
6061 enum calling_abi
6063 {
6067 }
6069 /* Write the extra assembler code needed to declare a function properly. */
6071 void
6073 tree decl)
6074 {
6078 {
6084 }
6086 #ifdef SUBTARGET_ASM_UNWIND_INIT
6088 #endif
6092 /* Output magic byte marker, if hot-patch attribute is set. */
6094 {
6096 {
6097 /* leaq [%rsp + 0], %rsp */
6100 }
6101 else
6102 {
6103 /* movl.s %edi, %edi
6104 push %ebp
6105 movl.s %esp, %ebp */
6108 }
6109 }
6110 }
6112 /* regclass.c */
6115 /* Implementation of call abi switching target hook. Specific to FNDECL
6116 the specific call register sets are set. See also
6117 ix86_conditional_register_usage for more details. */
6118 void
6120 {
6123 else
6125 }
6127 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6128 expensive re-initialization of init_regs each time we switch function context
6129 since this is needed only during RTL expansion. */
6130 static void
6132 {
6136 }
6138 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6139 for a call to a function whose data type is FNTYPE.
6140 For a library call, FNTYPE is 0. */
6142 void
6146 tree fndecl,
6148 {
6154 {
6157 }
6158 else
6159 {
6162 }
6166 /* Set up the number of registers to use for passing arguments. */
6169 {
6171 ? X86_64_REGPARM_MAX
6173 }
6175 {
6178 {
6180 ? X86_64_SSE_REGPARM_MAX
6182 }
6183 }
6191 /* Because type might mismatch in between caller and callee, we need to
6192 use actual type of function for local calls.
6193 FIXME: cgraph_analyze can be told to actually record if function uses
6194 va_start so for local functions maybe_vaarg can be made aggressive
6195 helping K&R code.
6196 FIXME: once typesytem is fixed, we won't need this code anymore. */
6204 {
6205 /* If there are variable arguments, then we won't pass anything
6206 in registers in 32-bit mode. */
6208 {
6217 }
6219 /* Use ecx and edx registers if function has fastcall attribute,
6220 else look for regparm information. */
6222 {
6225 {
6228 }
6230 {
6233 }
6234 else
6236 }
6238 /* Set up the number of SSE registers used for passing SFmode
6239 and DFmode arguments. Warn for mismatching ABI. */
6241 }
6242 }
6244 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6245 But in the case of vector types, it is some vector mode.
6247 When we have only some of our vector isa extensions enabled, then there
6248 are some modes for which vector_mode_supported_p is false. For these
6249 modes, the generic vector support in gcc will choose some non-vector mode
6250 in order to implement the type. By computing the natural mode, we'll
6251 select the proper ABI location for the operand and not depend on whatever
6252 the middle-end decides to do with these vector types.
6254 The midde-end can't deal with the vector types > 16 bytes. In this
6255 case, we return the original mode and warn ABI change if CUM isn't
6256 NULL.
6258 If INT_RETURN is true, warn ABI change if the vector mode isn't
6259 available for function return value. */
6261 static enum machine_mode
6264 {
6268 {
6271 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6273 {
6278 else
6281 /* Get the mode which has this inner mode and number of units. */
6285 {
6287 {
6292 {
6296 }
6298 {
6302 }
6305 }
6307 {
6312 {
6316 }
6318 {
6322 }
6325 }
6328 {
6333 {
6337 }
6339 {
6343 }
6344 }
6346 {
6351 {
6355 }
6357 {
6361 }
6362 }
6364 }
6367 }
6368 }
6371 }
6373 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6374 this may not agree with the mode that the type system has chosen for the
6375 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6376 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6378 static rtx
6381 {
6382 rtx tmp;
6386 else
6387 {
6391 }
6394 }
6396 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6397 of this code is to classify each 8bytes of incoming argument by the register
6398 class and assign registers accordingly. */
6400 /* Return the union class of CLASS1 and CLASS2.
6401 See the x86-64 PS ABI for details. */
6403 static enum x86_64_reg_class
6405 {
6406 /* Rule #1: If both classes are equal, this is the resulting class. */
6410 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6411 the other class. */
6417 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6421 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6429 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6430 MEMORY is used. */
6439 /* Rule #6: Otherwise class SSE is used. */
6441 }
6443 /* Classify the argument of type TYPE and mode MODE.
6444 CLASSES will be filled by the register class used to pass each word
6445 of the operand. The number of words is returned. In case the parameter
6446 should be passed in memory, 0 is returned. As a special case for zero
6447 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6449 BIT_OFFSET is used internally for handling records and specifies offset
6450 of the offset in bits modulo 512 to avoid overflow cases.
6452 See the x86-64 PS ABI for details.
6453 */
6455 static int
6458 {
6459 HOST_WIDE_INT bytes =
6461 int words
6464 /* Variable sized entities are always passed/returned in memory. */
6473 {
6475 tree field;
6478 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6485 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6486 signalize memory class, so handle it as special case. */
6488 {
6491 }
6493 /* Classify each field of record and merge classes. */
6495 {
6497 /* And now merge the fields of structure. */
6499 {
6501 {
6507 /* Bitfields are always classified as integer. Handle them
6508 early, since later code would consider them to be
6509 misaligned integers. */
6511 {
6520 }
6521 else
6522 {
6527 /* Flexible array member is ignored. */
6534 {
6538 {
6541 "the ABI of passing struct with"
6542 " a flexible array member has"
6544 }
6546 }
6548 subclasses,
6558 }
6559 }
6560 }
6564 /* Arrays are handled as small records. */
6565 {
6572 /* The partial classes are now full classes. */
6583 }
6586 /* Unions are similar to RECORD_TYPE but offset is always 0.
6587 */
6589 {
6591 {
6599 bit_offset);
6604 }
6605 }
6610 }
6613 {
6614 /* When size > 16 bytes, if the first one isn't
6615 X86_64_SSE_CLASS or any other ones aren't
6616 X86_64_SSEUP_CLASS, everything should be passed in
6617 memory. */
6624 }
6626 /* Final merger cleanup. */
6628 {
6629 /* If one class is MEMORY, everything should be passed in
6630 memory. */
6634 /* The X86_64_SSEUP_CLASS should be always preceded by
6635 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6639 {
6640 /* The first one should never be X86_64_SSEUP_CLASS. */
6643 }
6645 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6646 everything should be passed in memory. */
6649 {
6652 /* The first one should never be X86_64_X87UP_CLASS. */
6655 {
6658 "the ABI of passing union with long double"
6660 }
6662 }
6663 }
6665 }
6667 /* Compute alignment needed. We align all types to natural boundaries with
6668 exception of XFmode that is aligned to 64bits. */
6670 {
6679 /* Misaligned fields are always returned in memory. */
6682 }
6684 /* for V1xx modes, just use the base mode */
6689 /* Classification of atomic types. */
6691 {
6707 {
6710 /* Analyze last 128 bits only. */
6714 {
6717 }
6719 {
6722 }
6724 {
6728 }
6730 {
6733 }
6734 else
6736 }
6743 /* OImode shouldn't be used directly. */
6750 else
6768 else
6769 {
6773 {
6776 "the ABI of passing structure with complex float"
6778 }
6781 }
6790 /* This modes is larger than 16 bytes. */
6848 else
6852 }
6853 }
6855 /* Examine the argument and return set number of register required in each
6856 class. Return true iff parameter should be passed in memory. */
6858 static bool
6861 {
6872 {
6893 }
6896 }
6898 /* Construct container for the argument used by GCC interface. See
6899 FUNCTION_ARG for the detailed description. */
6901 static rtx
6905 {
6906 /* The following variables hold the static issued_error state. */
6920 rtx ret;
6931 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6932 some less clueful developer tries to use floating-point anyway. */
6934 {
6936 {
6938 {
6941 }
6942 }
6944 {
6947 }
6949 }
6951 /* Likewise, error if the ABI requires us to return values in the
6952 x87 registers and the user specified -mno-80387. */
6958 {
6960 {
6963 }
6965 }
6967 /* First construct simple cases. Avoid SCmode, since we want to use
6968 single register to pass this type. */
6971 {
6986 /* Zero sized array, struct or class. */
6990 }
7029 /* Otherwise figure out the entries of the PARALLEL. */
7031 {
7035 {
7040 /* Merge TImodes on aligned occasions here too. */
7042 tmpmode
7046 else
7048 /* We've requested 24 bytes we
7049 don't have mode for. Use DImode. */
7056 intreg++;
7064 sse_regno++;
7072 sse_regno++;
7077 {
7083 {
7085 i++;
7086 }
7087 else
7112 }
7118 sse_regno++;
7122 }
7123 }
7125 /* Empty aligned struct, union or class. */
7133 }
7135 /* Update the data in CUM to advance over an argument of mode MODE
7136 and data type TYPE. (TYPE is null for libcalls where that information
7137 may not be available.) */
7139 static void
7142 HOST_WIDE_INT words)
7143 {
7145 {
7152 /* FALLTHRU */
7163 {
7166 }
7170 /* OImode shouldn't be used directly. */
7179 /* FALLTHRU */
7201 {
7206 {
7209 }
7210 }
7220 {
7225 {
7228 }
7229 }
7231 }
7232 }
7234 static void
7237 {
7240 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7247 {
7252 }
7253 else
7254 {
7258 }
7259 }
7261 static void
7263 HOST_WIDE_INT words)
7264 {
7265 /* Otherwise, this should be passed indirect. */
7270 {
7273 }
7274 }
7276 /* Update the data in CUM to advance over an argument of mode MODE and
7277 data type TYPE. (TYPE is null for libcalls where that information
7278 may not be available.) */
7280 static void
7283 {
7289 else
7300 else
7302 }
7304 /* Define where to put the arguments to a function.
7305 Value is zero to push the argument on the stack,
7306 or a hard register in which to store the argument.
7308 MODE is the argument's machine mode.
7309 TYPE is the data type of the argument (as a tree).
7310 This is null for libcalls where that information may
7311 not be available.
7312 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7313 the preceding args and about the function being called.
7314 NAMED is nonzero if this argument is a named parameter
7315 (otherwise it is an extra parameter matching an ellipsis). */
7317 static rtx
7321 {
7322 /* Avoid the AL settings for the Unix64 ABI. */
7327 {
7334 /* FALLTHRU */
7340 {
7343 /* Fastcall allocates the first two DWORD (SImode) or
7344 smaller arguments to ECX and EDX if it isn't an
7345 aggregate type . */
7347 {
7353 /* ECX not EAX is the first allocated register. */
7356 }
7358 }
7367 /* FALLTHRU */
7369 /* In 32bit, we pass TImode in xmm registers. */
7377 {
7381 }
7386 /* OImode and XImode shouldn't be used directly. */
7402 {
7406 }
7416 {
7420 }
7422 }
7425 }
7427 static rtx
7430 {
7431 /* Handle a hidden AL argument containing number of registers
7432 for varargs x86-64 functions. */
7436 ? X86_64_SSE_REGPARM_MAX
7441 {
7457 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7461 }
7467 }
7469 static rtx
7472 HOST_WIDE_INT bytes)
7473 {
7476 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7477 We use value of -2 to specify that current function call is MSABI. */
7481 /* If we've run out of registers, it goes on the stack. */
7487 /* Only floating point modes are passed in anything but integer regs. */
7489 {
7492 else
7493 {
7496 /* Unnamed floating parameters are passed in both the
7497 SSE and integer registers. */
7503 }
7504 }
7505 /* Handle aggregated types passed in register. */
7507 {
7512 }
7515 }
7517 /* Return where to put the arguments to a function.
7518 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7520 MODE is the argument's machine mode. TYPE is the data type of the
7521 argument. It is null for libcalls where that information may not be
7522 available. CUM gives information about the preceding args and about
7523 the function being called. NAMED is nonzero if this argument is a
7524 named parameter (otherwise it is an extra parameter matching an
7525 ellipsis). */
7527 static rtx
7530 {
7534 rtx arg;
7538 else
7542 /* To simplify the code below, represent vector types with a vector mode
7543 even if MMX/SSE are not active. */
7551 else
7555 }
7557 /* A C expression that indicates when an argument must be passed by
7558 reference. If nonzero for an argument, a copy of that argument is
7559 made in memory and a pointer to the argument is passed instead of
7560 the argument itself. The pointer is passed in whatever way is
7561 appropriate for passing a pointer to that type. */
7563 static bool
7566 {
7569 /* See Windows x64 Software Convention. */
7571 {
7574 {
7575 /* Arrays are passed by reference. */
7580 {
7581 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7582 are passed by reference. */
7584 }
7585 }
7587 /* __m128 is passed by reference. */
7593 }
7594 }
7599 }
7601 /* Return true when TYPE should be 128bit aligned for 32bit argument
7602 passing ABI. XXX: This function is obsolete and is only used for
7603 checking psABI compatibility with previous versions of GCC. */
7605 static bool
7607 {
7619 {
7620 /* Walk the aggregates recursively. */
7622 {
7626 {
7627 tree field;
7629 /* Walk all the structure fields. */
7631 {
7635 }
7637 }
7640 /* Just for use if some languages passes arrays by value. */
7647 }
7648 }
7650 }
7652 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7653 XXX: This function is obsolete and is only used for checking psABI
7654 compatibility with previous versions of GCC. */
7656 static unsigned int
7659 {
7660 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7661 natural boundaries. */
7663 {
7664 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7665 make an exception for SSE modes since these require 128bit
7666 alignment.
7668 The handling here differs from field_alignment. ICC aligns MMX
7669 arguments to 4 byte boundaries, while structure fields are aligned
7670 to 8 byte boundaries. */
7672 {
7675 }
7676 else
7677 {
7680 }
7681 }
7685 }
7687 /* Return true when TYPE should be 128bit aligned for 32bit argument
7688 passing ABI. */
7690 static bool
7692 {
7702 {
7703 /* Walk the aggregates recursively. */
7705 {
7709 {
7710 tree field;
7712 /* Walk all the structure fields. */
7714 field;
7716 {
7720 }
7722 }
7725 /* Just for use if some languages passes arrays by value. */
7732 }
7733 }
7734 else
7738 }
7740 /* Gives the alignment boundary, in bits, of an argument with the
7741 specified mode and type. */
7743 static unsigned int
7745 {
7748 {
7749 /* Since the main variant type is used for call, we convert it to
7750 the main variant type. */
7753 }
7754 else
7758 else
7759 {
7764 {
7765 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7767 {
7770 }
7776 }
7779 && !warned
7781 saved_align))
7782 {
7785 "The ABI for passing parameters with %d-byte"
7788 }
7789 }
7792 }
7794 /* Return true if N is a possible register number of function value. */
7796 static bool
7798 {
7800 {
7809 /* Complex values are returned in %st(0)/%st(1) pair. */
7812 /* TODO: The function should depend on current function ABI but
7813 builtins.c would need updating then. Therefore we use the
7814 default ABI. */
7819 /* Complex values are returned in %xmm0/%xmm1 pair. */
7828 }
7831 }
7833 /* Define how to find the value returned by a function.
7834 VALTYPE is the data type of the value (as a tree).
7835 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7836 otherwise, FUNC is 0. */
7838 static rtx
7841 {
7844 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7845 we normally prevent this case when mmx is not available. However
7846 some ABIs may require the result to be returned like DImode. */
7850 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7851 we prevent this case when sse is not available. However some ABIs
7852 may require the result to be returned like integer TImode. */
7857 /* 32-byte vector modes in %ymm0. */
7861 /* 64-byte vector modes in %zmm0. */
7865 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7868 else
7869 /* Most things go in %eax. */
7872 /* Override FP return register with %xmm0 for local functions when
7873 SSE math is enabled or for functions with sseregparm attribute. */
7875 {
7880 }
7882 /* OImode shouldn't be used directly. */
7886 }
7888 static rtx
7890 const_tree valtype)
7891 {
7892 rtx ret;
7894 /* Handle libcalls, which don't provide a type node. */
7896 {
7900 {
7919 }
7922 }
7924 {
7925 /* Pointers are always returned in word_mode. */
7927 }
7933 /* For zero sized structures, construct_container returns NULL, but we
7934 need to keep rest of compiler happy by returning meaningful value. */
7939 }
7941 static rtx
7943 const_tree valtype)
7944 {
7948 {
7950 {
7969 }
7970 }
7972 }
7974 static rtx
7977 {
7989 else
7991 }
7993 static rtx
7996 {
8002 }
8004 /* Pointer function arguments and return values are promoted to
8005 word_mode. */
8007 static enum machine_mode
8011 {
8013 {
8016 }
8018 for_return);
8019 }
8021 /* Return true if a structure, union or array with MODE containing FIELD
8022 should be accessed using BLKmode. */
8024 static bool
8026 {
8027 /* Union with XFmode must be in BLKmode. */
8031 }
8033 rtx
8035 {
8037 }
8039 /* Return true iff type is returned in memory. */
8041 static bool
8043 {
8044 #ifdef SUBTARGET_RETURN_IN_MEMORY
8046 #else
8048 HOST_WIDE_INT size;
8051 {
8053 {
8056 /* __m128 is returned in xmm0. */
8065 /* Otherwise, the size must be exactly in [1248]. */
8067 }
8068 else
8069 {
8074 }
8075 }
8076 else
8077 {
8087 {
8088 /* User-created vectors small enough to fit in EAX. */
8092 /* Unless ABI prescibes otherwise,
8093 MMX/3dNow values are returned in MM0 if available. */
8098 /* SSE values are returned in XMM0 if available. */
8102 /* AVX values are returned in YMM0 if available. */
8106 /* AVX512F values are returned in ZMM0 if available. */
8109 }
8117 /* OImode shouldn't be used directly. */
8121 }
8122 #endif
8123 }
8125 \f
8126 /* Create the va_list data type. */
8128 /* Returns the calling convention specific va_list date type.
8129 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8131 static tree
8133 {
8136 /* For i386 we use plain pointer to argument area. */
8146 unsigned_type_node);
8149 unsigned_type_node);
8152 ptr_type_node);
8155 ptr_type_node);
8174 /* The correct type is an array type of one element. */
8176 }
8178 /* Setup the builtin va_list data type and for 64-bit the additional
8179 calling convention specific va_list data types. */
8181 static tree
8183 {
8186 /* Initialize abi specific va_list builtin types. */
8188 {
8189 tree t;
8191 {
8196 }
8197 else
8198 {
8203 }
8205 {
8210 }
8211 else
8212 {
8217 }
8218 }
8221 }
8223 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8225 static void
8227 {
8229 alias_set_type set;
8232 /* GPR size of varargs save area. */
8235 else
8238 /* FPR size of varargs save area. We don't need it if we don't pass
8239 anything in SSE registers. */
8242 else
8256 {
8264 }
8267 {
8271 /* Now emit code to save SSE registers. The AX parameter contains number
8272 of SSE parameter registers used to call this function, though all we
8273 actually check here is the zero/non-zero status. */
8278 label));
8280 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8281 we used movdqa (i.e. TImode) instead? Perhaps even better would
8282 be if we could determine the real mode of the data, via a hook
8283 into pass_stdarg. Ignore all that for now. */
8293 {
8302 }
8305 }
8306 }
8308 static void
8310 {
8314 /* Reset to zero, as there might be a sysv vaarg used
8315 before. */
8320 {
8331 }
8332 }
8334 static void
8338 {
8340 CUMULATIVE_ARGS next_cum;
8341 tree fntype;
8343 /* This argument doesn't appear to be used anymore. Which is good,
8344 because the old code here didn't suppress rtl generation. */
8352 /* For varargs, we do not want to skip the dummy va_dcl argument.
8353 For stdargs, we do want to skip the last named argument. */
8361 else
8363 }
8365 /* Checks if TYPE is of kind va_list char *. */
8367 static bool
8369 {
8370 tree canonic;
8372 /* For 32-bit it is always true. */
8378 }
8380 /* Implement va_start. */
8382 static void
8384 {
8388 tree type;
8389 rtx ovf_rtx;
8393 {
8396 /* When we are splitting the stack, we can't refer to the stack
8397 arguments using internal_arg_pointer, because they may be on
8398 the old stack. The split stack prologue will arrange to
8399 leave a pointer to the old stack arguments in a scratch
8400 register, which we here copy to a pseudo-register. The split
8401 stack prologue can't set the pseudo-register directly because
8402 it (the prologue) runs before any registers have been saved. */
8406 {
8420 }
8421 }
8423 /* Only 64bit target needs something special. */
8425 {
8428 else
8429 {
8438 }
8440 }
8449 /* The following should be folded into the MEM_REF offset. */
8459 /* Count number of gp and fp argument registers used. */
8465 {
8471 }
8474 {
8480 }
8482 /* Find the overflow area. */
8486 else
8496 {
8497 /* Find the register save area.
8498 Prologue of the function save it right above stack frame. */
8506 }
8507 }
8509 /* Implement va_arg. */
8511 static tree
8514 {
8521 rtx container;
8523 tree ptrtype;
8527 /* Only 64bit target needs something special. */
8551 {
8564 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8566 {
8569 }
8577 }
8579 /* Pull the value out of the saved registers. */
8584 {
8598 /* In case we are passing structure, verify that it is consecutive block
8599 on the register save area. If not we need to do moves. */
8601 {
8602 /* Verify that all registers are strictly consecutive */
8604 {
8608 {
8613 }
8614 }
8615 else
8616 {
8620 {
8625 }
8626 }
8627 }
8629 {
8632 }
8633 else
8634 {
8637 }
8639 /* First ensure that we fit completely in registers. */
8641 {
8648 }
8650 {
8658 }
8660 /* Compute index to start of area used for integer regs. */
8662 {
8663 /* int_addr = gpr + sav; */
8666 }
8668 {
8669 /* sse_addr = fpr + sav; */
8672 }
8674 {
8678 /* addr = &temp; */
8683 {
8687 tree piece_type;
8688 tree addr_type;
8689 tree daddr_type;
8698 {
8703 }
8707 else
8714 {
8717 }
8718 else
8719 {
8722 }
8729 {
8734 }
8735 else
8736 {
8737 tree copy
8742 }
8744 }
8745 }
8748 {
8752 }
8755 {
8759 }
8764 }
8766 /* ... otherwise out of the overflow area. */
8768 /* When we align parameter on stack for caller, if the parameter
8769 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8770 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8771 here with caller. */
8776 /* Care for on-stack alignment if needed. */
8779 else
8780 {
8785 }
8802 }
8803 \f
8804 /* Return true if OPNUM's MEM should be matched
8805 in movabs* patterns. */
8807 bool
8809 {
8821 }
8822 \f
8823 /* Initialize the table of extra 80387 mathematical constants. */
8825 static void
8827 {
8829 {
8835 };
8839 {
8841 /* Ensure each constant is rounded to XFmode precision. */
8844 }
8847 }
8849 /* Return non-zero if the constant is something that
8850 can be loaded with a special instruction. */
8852 int
8854 {
8857 REAL_VALUE_TYPE r;
8869 /* For XFmode constants, try to find a special 80387 instruction when
8870 optimizing for size or on those CPUs that benefit from them. */
8873 {
8882 }
8884 /* Load of the constant -0.0 or -1.0 will be split as
8885 fldz;fchs or fld1;fchs sequence. */
8892 }
8894 /* Return the opcode of the special instruction to be used to load
8895 the constant X. */
8899 {
8901 {
8921 }
8922 }
8924 /* Return the CONST_DOUBLE representing the 80387 constant that is
8925 loaded by the specified special instruction. The argument IDX
8926 matches the return value from standard_80387_constant_p. */
8928 rtx
8930 {
8937 {
8948 }
8951 XFmode);
8952 }
8954 /* Return 1 if X is all 0s and 2 if x is all 1s
8955 in supported SSE/AVX vector mode. */
8957 int
8959 {
8966 {
8987 }
8990 }
8992 /* Return the opcode of the special instruction to be used to load
8993 the constant X. */
8997 {
8999 {
9002 {
9029 }
9039 else
9044 }
9046 }
9048 /* Returns true if OP contains a symbol reference */
9050 bool
9052 {
9061 {
9063 {
9069 }
9073 }
9076 }
9078 /* Return true if it is appropriate to emit `ret' instructions in the
9079 body of a function. Do this only if the epilogue is simple, needing a
9080 couple of insns. Prior to reloading, we can't tell how many registers
9081 must be saved, so return false then. Return false if there is no frame
9082 marker to de-allocate. */
9084 bool
9086 {
9092 /* Don't allow more than 32k pop, since that's all we can do
9093 with one instruction. */
9100 }
9101 \f
9102 /* Value should be nonzero if functions must have frame pointers.
9103 Zero means the frame pointer need not be set up (and parms may
9104 be accessed via the stack pointer) in functions that seem suitable. */
9106 static bool
9108 {
9109 /* If we accessed previous frames, then the generated code expects
9110 to be able to access the saved ebp value in our frame. */
9114 /* Several x86 os'es need a frame pointer for other reasons,
9115 usually pertaining to setjmp. */
9119 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9123 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9124 allocation is 4GB. */
9128 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9129 turns off the frame pointer by default. Turn it back on now if
9130 we've not got a leaf function. */
9140 }
9142 /* Record that the current function accesses previous call frames. */
9144 void
9146 {
9148 }
9149 \f
9150 #ifndef USE_HIDDEN_LINKONCE
9151 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9152 # define USE_HIDDEN_LINKONCE 1
9153 # else
9154 # define USE_HIDDEN_LINKONCE 0
9155 # endif
9156 #endif
9160 /* Fills in the label name that should be used for a pc thunk for
9161 the given register. */
9163 static void
9165 {
9170 else
9172 }
9175 /* This function generates code for -fpic that loads %ebx with
9176 the return address of the caller and then returns. */
9178 static void
9180 {
9185 {
9187 tree decl;
9203 #if TARGET_MACHO
9205 {
9214 }
9215 else
9216 #endif
9218 {
9229 }
9230 else
9231 {
9234 }
9240 /* Make sure unwind info is emitted for the thunk if needed. */
9243 /* Pad stack IP move with 4 instructions (two NOPs count
9244 as one instruction). */
9246 {
9251 }
9262 }
9266 }
9268 /* Emit code for the SET_GOT patterns. */
9272 {
9278 {
9279 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9284 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9285 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9286 an unadorned address. */
9291 }
9296 {
9298 /* We don't need a pic base, we're not producing pic. */
9305 }
9306 else
9307 {
9316 #if TARGET_MACHO
9317 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9318 This is what will be referenced by the Mach-O PIC subsystem. */
9322 /* When we are restoring the pic base at the site of a nonlocal label,
9323 and we decided to emit the pic base above, we will still output a
9324 local label used for calculating the correction offset (even though
9325 the offset will be 0 in that case). */
9329 #endif
9330 }
9336 }
9338 /* Generate an "push" pattern for input ARG. */
9340 static rtx
9342 {
9355 stack_pointer_rtx)),
9356 arg);
9357 }
9359 /* Generate an "pop" pattern for input ARG. */
9361 static rtx
9363 {
9368 arg,
9371 stack_pointer_rtx)));
9372 }
9374 /* Return >= 0 if there is an unused call-clobbered register available
9375 for the entire function. */
9377 static unsigned int
9379 {
9383 {
9385 /* Can't use the same register for both PIC and DRAP. */
9388 else
9393 }
9396 }
9398 /* Return TRUE if we need to save REGNO. */
9400 static bool
9402 {
9413 {
9416 {
9422 }
9423 }
9434 }
9436 /* Return number of saved general prupose registers. */
9438 static int
9440 {
9446 nregs ++;
9448 }
9450 /* Return number of saved SSE registrers. */
9452 static int
9454 {
9462 nregs ++;
9464 }
9466 /* Given FROM and TO register numbers, say whether this elimination is
9467 allowed. If stack alignment is needed, we can only replace argument
9468 pointer with hard frame pointer, or replace frame pointer with stack
9469 pointer. Otherwise, frame pointer elimination is automatically
9470 handled and all other eliminations are valid. */
9472 static bool
9474 {
9480 else
9482 }
9484 /* Return the offset between two registers, one to be eliminated, and the other
9485 its replacement, at the start of a routine. */
9487 HOST_WIDE_INT
9489 {
9498 else
9499 {
9507 }
9508 }
9510 /* In a dynamically-aligned function, we can't know the offset from
9511 stack pointer to frame pointer, so we must ensure that setjmp
9512 eliminates fp against the hard fp (%ebp) rather than trying to
9513 index from %esp up to the top of the frame across a gap that is
9514 of unknown (at compile-time) size. */
9515 static rtx
9517 {
9519 }
9521 /* When using -fsplit-stack, the allocation routines set a field in
9522 the TCB to the bottom of the stack plus this much space, measured
9523 in bytes. */
9525 #define SPLIT_STACK_AVAILABLE 256
9527 /* Fill structure ix86_frame about frame of currently computed function. */
9529 static void
9531 {
9533 HOST_WIDE_INT offset;
9536 HOST_WIDE_INT to_allocate;
9541 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9542 function prologues and leaf. */
9546 {
9549 }
9550 /* preferred_stack_boundary is never updated for call
9551 expanded from tls descriptor. Update it here. We don't update it in
9552 expand stage because according to the comments before
9553 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
9554 away. */
9557 {
9561 }
9570 /* For SEH we have to limit the amount of code movement into the prologue.
9571 At present we do this via a BLOCKAGE, at which point there's very little
9572 scheduling that can be done, which means that there's very little point
9573 in doing anything except PUSHs. */
9577 /* During reload iteration the amount of registers saved can change.
9578 Recompute the value as needed. Do not recompute when amount of registers
9579 didn't change as reload does multiple calls to the function and does not
9580 expect the decision to change within single iteration. */
9583 {
9589 /* The fast prologue uses move instead of push to save registers. This
9590 is significantly longer, but also executes faster as modern hardware
9591 can execute the moves in parallel, but can't do that for push/pop.
9593 Be careful about choosing what prologue to emit: When function takes
9594 many instructions to execute we may use slow version as well as in
9595 case function is known to be outside hot spot (this is known with
9596 feedback only). Weight the size of function by number of registers
9597 to save as it is cheap to use one or two push instructions but very
9598 slow to use many of them. */
9602 || (flag_branch_probabilities
9605 else
9608 }
9610 frame->save_regs_using_mov
9612 /* If static stack checking is enabled and done with probes,
9613 the registers need to be saved before allocating the frame. */
9616 /* Skip return address. */
9619 /* Skip pushed static chain. */
9623 /* Skip saved base pointer. */
9628 /* The traditional frame pointer location is at the top of the frame. */
9631 /* Register save area */
9635 /* On SEH target, registers are pushed just before the frame pointer
9636 location. */
9640 /* Align and set SSE register save area. */
9642 {
9643 /* The only ABI that has saved SSE registers (Win64) also has a
9644 16-byte aligned default stack, and thus we don't need to be
9645 within the re-aligned local stack frame to save them. */
9649 }
9652 /* The re-aligned stack starts here. Values before this point are not
9653 directly comparable with values below this point. In order to make
9654 sure that no value happens to be the same before and after, force
9655 the alignment computation below to add a non-zero value. */
9659 /* Va-arg area */
9663 /* Align start of frame for local function. */
9672 /* Frame pointer points here. */
9677 /* Add outgoing arguments area. Can be skipped if we eliminated
9678 all the function calls as dead code.
9679 Skipping is however impossible when function calls alloca. Alloca
9680 expander assumes that last crtl->outgoing_args_size
9681 of stack frame are unused. */
9685 {
9688 }
9689 else
9692 /* Align stack boundary. Only needed if we're calling another function
9693 or using alloca. */
9698 /* We've reached end of stack frame. */
9701 /* Size prologue needs to allocate. */
9712 {
9718 }
9719 else
9723 /* The SEH frame pointer location is near the bottom of the frame.
9724 This is enforced by the fact that the difference between the
9725 stack pointer and the frame pointer is limited to 240 bytes in
9726 the unwind data structure. */
9728 {
9729 HOST_WIDE_INT diff;
9731 /* If we can leave the frame pointer where it is, do so. Also, returns
9732 the establisher frame for __builtin_frame_address (0). */
9737 {
9738 /* Ideally we'd determine what portion of the local stack frame
9739 (within the constraint of the lowest 240) is most heavily used.
9740 But without that complication, simply bias the frame pointer
9741 by 128 bytes so as to maximize the amount of the local stack
9742 frame that is addressable with 8-bit offsets. */
9744 }
9745 }
9746 }
9748 /* This is semi-inlined memory_address_length, but simplified
9749 since we know that we're always dealing with reg+offset, and
9750 to avoid having to create and discard all that rtl. */
9754 {
9758 {
9759 /* EBP and R13 cannot be encoded without an offset. */
9761 }
9765 /* ESP and R12 must be encoded with a SIB byte. */
9767 len++;
9770 }
9772 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9773 The valid base registers are taken from CFUN->MACHINE->FS. */
9775 static rtx
9777 {
9783 {
9784 /* Choose the base register most likely to allow the most scheduling
9785 opportunities. Generally FP is valid throughout the function,
9786 while DRAP must be reloaded within the epilogue. But choose either
9787 over the SP due to increased encoding size. */
9790 {
9793 }
9795 {
9798 }
9800 {
9803 }
9804 }
9805 else
9806 {
9807 HOST_WIDE_INT toffset;
9810 /* Choose the base register with the smallest address encoding.
9811 With a tie, choose FP > DRAP > SP. */
9813 {
9817 }
9819 {
9823 {
9827 }
9828 }
9830 {
9834 {
9838 }
9839 }
9840 }
9844 }
9846 /* Emit code to save registers in the prologue. */
9848 static void
9850 {
9852 rtx insn;
9856 {
9859 }
9860 }
9862 /* Emit a single register save at CFA - CFA_OFFSET. */
9864 static void
9866 HOST_WIDE_INT cfa_offset)
9867 {
9875 /* For SSE saves, we need to indicate the 128-bit alignment. */
9886 /* When saving registers into a re-aligned local stack frame, avoid
9887 any tricky guessing by dwarf2out. */
9889 {
9893 {
9894 /* A bit of a hack. We force the DRAP register to be saved in
9895 the re-aligned stack frame, which provides us with a copy
9896 of the CFA that will last past the prologue. Install it. */
9902 }
9903 else
9904 {
9905 /* The frame pointer is a stable reference within the
9906 aligned frame. Use it. */
9913 }
9914 }
9916 /* The memory may not be relative to the current CFA register,
9917 which means that we may need to generate a new pattern for
9918 use by the unwind info. */
9920 {
9925 }
9926 }
9928 /* Emit code to save registers using MOV insns.
9929 First register is stored at CFA - CFA_OFFSET. */
9930 static void
9932 {
9937 {
9940 }
9941 }
9943 /* Emit code to save SSE registers using MOV insns.
9944 First register is stored at CFA - CFA_OFFSET. */
9945 static void
9947 {
9952 {
9955 }
9956 }
9960 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9961 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9962 Don't add the note if the previously saved value will be left untouched
9963 within stack red-zone till return, as unwinders can find the same value
9964 in the register and on the stack. */
9966 static void
9968 {
9974 {
9977 }
9978 else
9979 queued_cfa_restores
9981 }
9983 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9985 static void
9987 {
9988 rtx last;
9992 ;
9997 }
9999 /* Expand prologue or epilogue stack adjustment.
10000 The pattern exist to put a dependency on all ebp-based memory accesses.
10001 STYLE should be negative if instructions should be marked as frame related,
10002 zero if %r11 register is live and cannot be freely used and positive
10003 otherwise. */
10005 static void
10008 {
10010 rtx insn;
10017 else
10018 {
10019 rtx tmp;
10020 /* r11 is used by indirect sibcall return as well, set before the
10021 epilogue and used after the epilogue. */
10024 else
10025 {
10029 }
10035 }
10042 {
10043 rtx r;
10053 }
10055 {
10058 {
10062 }
10063 }
10066 {
10071 {
10074 }
10076 {
10079 }
10080 else
10081 {
10082 /* Else there are two possibilities: SP itself, which we set
10083 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10084 taken care of this by hand along the eh_return path. */
10087 }
10091 }
10092 }
10094 /* Find an available register to be used as dynamic realign argument
10095 pointer regsiter. Such a register will be written in prologue and
10096 used in begin of body, so it must not be
10097 1. parameter passing register.
10098 2. GOT pointer.
10099 We reuse static-chain register if it is available. Otherwise, we
10100 use DI for i386 and R13 for x86-64. We chose R13 since it has
10101 shorter encoding.
10103 Return: the regno of chosen register. */
10105 static unsigned int
10107 {
10111 {
10112 /* Use R13 for nested function or function need static chain.
10113 Since function with tail call may use any caller-saved
10114 registers in epilogue, DRAP must not use caller-saved
10115 register in such case. */
10120 }
10121 else
10122 {
10123 /* Use DI for nested function or function need static chain.
10124 Since function with tail call may use any caller-saved
10125 registers in epilogue, DRAP must not use caller-saved
10126 register in such case. */
10130 /* Reuse static chain register if it isn't used for parameter
10131 passing. */
10133 {
10137 }
10139 }
10140 }
10142 /* Return minimum incoming stack alignment. */
10144 static unsigned int
10146 {
10149 /* Prefer the one specified at command line. */
10152 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10153 if -mstackrealign is used, it isn't used for sibcall check and
10154 estimated stack alignment is 128bit. */
10156 && !TARGET_64BIT
10157 && ix86_force_align_arg_pointer
10160 else
10163 /* Incoming stack alignment can be changed on individual functions
10164 via force_align_arg_pointer attribute. We use the smallest
10165 incoming stack boundary. */
10171 /* The incoming stack frame has to be aligned at least at
10172 parm_stack_boundary. */
10176 /* Stack at entrance of main is aligned by runtime. We use the
10177 smallest incoming stack boundary. */
10185 }
10187 /* Update incoming stack boundary and estimated stack alignment. */
10189 static void
10191 {
10192 ix86_incoming_stack_boundary
10195 /* x86_64 vararg needs 16byte stack alignment for register save
10196 area. */
10201 }
10203 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10204 needed or an rtx for DRAP otherwise. */
10206 static rtx
10208 {
10213 {
10214 /* Assign DRAP to vDRAP and returns vDRAP */
10216 rtx drap_vreg;
10217 rtx arg_ptr;
10230 {
10233 }
10235 }
10236 else
10238 }
10240 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10242 static rtx
10244 {
10246 }
10249 rtx reg;
10251 };
10253 /* Return a short-lived scratch register for use on function entry.
10254 In 32-bit mode, it is valid only after the registers are saved
10255 in the prologue. This register must be released by means of
10256 release_scratch_register_on_entry once it is dead. */
10258 static void
10260 {
10266 {
10267 /* We always use R11 in 64-bit mode. */
10269 }
10270 else
10271 {
10273 bool fastcall_p
10275 bool thiscall_p
10279 int drap_regno
10282 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10283 for the static chain register. */
10287 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10288 for the static chain register. */
10293 /* ecx is the static chain register. */
10295 && !static_chain_p
10300 /* esi is the static chain register. */
10306 else
10307 {
10310 }
10311 }
10315 {
10318 }
10319 }
10321 /* Release a scratch register obtained from the preceding function. */
10323 static void
10325 {
10327 {
10331 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10337 }
10338 }
10340 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10342 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10344 static void
10346 {
10347 /* We skip the probe for the first interval + a small dope of 4 words and
10348 probe that many bytes past the specified size to maintain a protection
10349 area at the botton of the stack. */
10353 /* See if we have a constant small number of probes to generate. If so,
10354 that's the easy case. The run-time loop is made up of 11 insns in the
10355 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10356 for n # of intervals. */
10358 {
10362 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10363 values of N from 1 until it exceeds SIZE. If only one probe is
10364 needed, this will not generate any code. Then adjust and probe
10365 to PROBE_INTERVAL + SIZE. */
10367 {
10369 {
10372 }
10373 else
10380 }
10384 else
10392 /* Adjust back to account for the additional first interval. */
10396 }
10398 /* Otherwise, do the same as above, but in a loop. Note that we must be
10399 extra careful with variables wrapping around because we might be at
10400 the very top (or the very bottom) of the address space and we have
10401 to be able to handle this case properly; in particular, we use an
10402 equality test for the loop condition. */
10403 else
10404 {
10405 HOST_WIDE_INT rounded_size;
10411 /* Step 1: round SIZE to the previous multiple of the interval. */
10416 /* Step 2: compute initial and final value of the loop counter. */
10418 /* SP = SP_0 + PROBE_INTERVAL. */
10423 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10427 stack_pointer_rtx)));
10430 /* Step 3: the loop
10432 while (SP != LAST_ADDR)
10433 {
10434 SP = SP + PROBE_INTERVAL
10435 probe at SP
10436 }
10438 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10439 values of N from 1 until it is equal to ROUNDED_SIZE. */
10444 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10445 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10448 {
10453 }
10455 /* Adjust back to account for the additional first interval. */
10461 }
10465 /* Even if the stack pointer isn't the CFA register, we need to correctly
10466 describe the adjustments made to it, in particular differentiate the
10467 frame-related ones from the frame-unrelated ones. */
10469 {
10482 }
10484 /* Make sure nothing is scheduled before we are done. */
10486 }
10488 /* Adjust the stack pointer up to REG while probing it. */
10492 {
10502 /* Jump to END_LAB if SP == LAST_ADDR. */
10510 /* SP = SP + PROBE_INTERVAL. */
10514 /* Probe at SP. */
10525 }
10527 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10528 inclusive. These are offsets from the current stack pointer. */
10530 static void
10532 {
10533 /* See if we have a constant small number of probes to generate. If so,
10534 that's the easy case. The run-time loop is made up of 7 insns in the
10535 generic case while the compile-time loop is made up of n insns for n #
10536 of intervals. */
10538 {
10539 HOST_WIDE_INT i;
10541 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10542 it exceeds SIZE. If only one probe is needed, this will not
10543 generate any code. Then probe at FIRST + SIZE. */
10550 }
10552 /* Otherwise, do the same as above, but in a loop. Note that we must be
10553 extra careful with variables wrapping around because we might be at
10554 the very top (or the very bottom) of the address space and we have
10555 to be able to handle this case properly; in particular, we use an
10556 equality test for the loop condition. */
10557 else
10558 {
10565 /* Step 1: round SIZE to the previous multiple of the interval. */
10570 /* Step 2: compute initial and final value of the loop counter. */
10572 /* TEST_OFFSET = FIRST. */
10575 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10579 /* Step 3: the loop
10581 while (TEST_ADDR != LAST_ADDR)
10582 {
10583 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10584 probe at TEST_ADDR
10585 }
10587 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10588 until it is equal to ROUNDED_SIZE. */
10593 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10594 that SIZE is equal to ROUNDED_SIZE. */
10599 stack_pointer_rtx,
10604 }
10606 /* Make sure nothing is scheduled before we are done. */
10608 }
10610 /* Probe a range of stack addresses from REG to END, inclusive. These are
10611 offsets from the current stack pointer. */
10615 {
10625 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10633 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10637 /* Probe at TEST_ADDR. */
10650 }
10652 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10653 to be generated in correct form. */
10654 static void
10656 {
10657 /* Check if stack realign is really needed after reload, and
10658 stores result in cfun */
10659 unsigned int incoming_stack_boundary
10668 {
10669 /* After stack_realign_needed is finalized, we can't no longer
10670 change it. */
10673 }
10675 /* If the only reason for frame_pointer_needed is that we conservatively
10676 assumed stack realignment might be needed, but in the end nothing that
10677 needed the stack alignment had been spilled, clear frame_pointer_needed
10678 and say we don't need stack realignment. */
10680 && frame_pointer_needed
10682 && flag_omit_frame_pointer
10684 && !ix86_current_function_calls_tls_descriptor
10693 {
10695 basic_block bb;
10702 HARD_FRAME_POINTER_REGNUM);
10704 {
10705 rtx insn;
10709 set_up_by_prologue))
10710 {
10714 }
10715 }
10717 /* If drap has been set, but it actually isn't live at the start
10718 of the function, there is no reason to set it up. */
10720 {
10723 {
10726 }
10727 }
10728 else
10743 }
10747 }
10749 /* Expand the prologue into a bunch of separate insns. */
10751 void
10753 {
10758 HOST_WIDE_INT allocate;
10764 /* DRAP should not coexist with stack_realign_fp */
10769 /* Initialize CFA state for before the prologue. */
10773 /* Track SP offset to the CFA. We continue tracking this after we've
10774 swapped the CFA register away from SP. In the case of re-alignment
10775 this is fudged; we're interested to offsets within the local frame. */
10782 {
10783 /* We should have already generated an error for any use of
10784 ms_hook on a nested function. */
10787 /* Check if profiling is active and we shall use profiling before
10788 prologue variant. If so sorry. */
10793 /* In ix86_asm_output_function_label we emitted:
10794 8b ff movl.s %edi,%edi
10795 55 push %ebp
10796 8b ec movl.s %esp,%ebp
10798 This matches the hookable function prologue in Win32 API
10799 functions in Microsoft Windows XP Service Pack 2 and newer.
10800 Wine uses this to enable Windows apps to hook the Win32 API
10801 functions provided by Wine.
10803 What that means is that we've already set up the frame pointer. */
10807 {
10810 /* We've decided to use the frame pointer already set up.
10811 Describe this to the unwinder by pretending that both
10812 push and mov insns happen right here.
10814 Putting the unwind info here at the end of the ms_hook
10815 is done so that we can make absolutely certain we get
10816 the required byte sequence at the start of the function,
10817 rather than relying on an assembler that can produce
10818 the exact encoding required.
10820 However it does mean (in the unpatched case) that we have
10821 a 1 insn window where the asynchronous unwind info is
10822 incorrect. However, if we placed the unwind info at
10823 its correct location we would have incorrect unwind info
10824 in the patched case. Which is probably all moot since
10825 I don't expect Wine generates dwarf2 unwind info for the
10826 system libraries that use this feature. */
10832 stack_pointer_rtx);
10840 /* Note that gen_push incremented m->fs.cfa_offset, even
10841 though we didn't emit the push insn here. */
10845 }
10846 else
10847 {
10848 /* The frame pointer is not needed so pop %ebp again.
10849 This leaves us with a pristine state. */
10851 }
10852 }
10854 /* The first insn of a function that accepts its static chain on the
10855 stack is to push the register that would be filled in by a direct
10856 call. This insn will be skipped by the trampoline. */
10858 {
10862 /* We don't want to interpret this push insn as a register save,
10863 only as a stack adjustment. The real copy of the register as
10864 a save will be done later, if needed. */
10869 }
10871 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10872 of DRAP is needed and stack realignment is really needed after reload */
10874 {
10877 /* Only need to push parameter pointer reg if it is caller saved. */
10879 {
10880 /* Push arg pointer reg */
10883 }
10885 /* Grab the argument pointer. */
10892 /* Align the stack. */
10894 stack_pointer_rtx,
10898 /* Replicate the return address on the stack so that return
10899 address can be reached via (argp - 1) slot. This is needed
10900 to implement macro RETURN_ADDR_RTX and intrinsic function
10901 expand_builtin_return_addr etc. */
10907 /* For the purposes of frame and register save area addressing,
10908 we've started over with a new frame. */
10911 }
10917 {
10918 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10919 slower on all targets. Also sdb doesn't like it. */
10923 /* Push registers now, before setting the frame pointer
10924 on SEH target. */
10926 && TARGET_SEH
10928 {
10932 }
10935 {
10943 }
10944 }
10947 {
10948 /* If saving registers via PUSH, do so now. */
10950 {
10954 }
10956 /* When using red zone we may start register saving before allocating
10957 the stack frame saving one cycle of the prologue. However, avoid
10958 doing this if we have to probe the stack; at least on x86_64 the
10959 stack probe can turn into a call that clobbers a red zone location. */
10961 && (! TARGET_STACK_PROBE
10963 {
10966 }
10967 }
10970 {
10974 /* The computation of the size of the re-aligned stack frame means
10975 that we must allocate the size of the register save area before
10976 performing the actual alignment. Otherwise we cannot guarantee
10977 that there's enough storage above the realignment point. */
10984 /* Align the stack. */
10986 stack_pointer_rtx,
10989 /* For the purposes of register save area addressing, the stack
10990 pointer is no longer valid. As for the value of sp_offset,
10991 see ix86_compute_frame_layout, which we need to match in order
10992 to pass verification of stack_pointer_offset at the end. */
10995 }
11000 {
11001 /* We start to count from ARG_POINTER. */
11004 /* If it was realigned, take into account the fake frame. */
11006 {
11013 /* This over-estimates by 1 minimal-stack-alignment-unit but
11014 mitigates that by counting in the new return address slot. */
11015 current_function_dynamic_stack_size
11017 }
11020 }
11022 /* On SEH target with very large frame size, allocate an area to save
11023 SSE registers (as the very large allocation won't be described). */
11027 {
11028 HOST_WIDE_INT sse_size =
11033 /* No need to do stack checking as the area will be immediately
11034 written. */
11041 }
11043 /* The stack has already been decremented by the instruction calling us
11044 so probe if the size is non-negative to preserve the protection area. */
11046 {
11047 /* We expect the registers to be saved when probes are used. */
11051 {
11054 {
11057 }
11058 }
11059 else
11060 {
11067 {
11069 {
11072 }
11073 else
11075 }
11076 else
11077 {
11079 {
11083 }
11084 else
11086 }
11087 }
11088 }
11091 ;
11094 {
11098 }
11099 else
11100 {
11112 {
11115 /* Note that SEH directives need to continue tracking the stack
11116 pointer even after the frame pointer has been set up. */
11118 {
11122 }
11123 }
11126 {
11131 {
11135 }
11136 }
11141 /* Use the fact that AX still contains ALLOCATE. */
11143 ? gen_pro_epilogue_adjust_stack_di_sub
11150 {
11158 }
11161 /* Use stack_pointer_rtx for relative addressing so that code
11162 works for realigned stack, too. */
11164 {
11171 }
11173 {
11178 }
11179 }
11182 /* If we havn't already set up the frame pointer, do so now. */
11184 {
11196 }
11204 /* We don't use pic-register for pe-coff target. */
11206 && !TARGET_PECOFF
11209 {
11216 }
11219 {
11221 {
11223 {
11233 label));
11237 }
11238 else
11240 }
11241 else
11242 {
11246 }
11247 }
11249 /* In the pic_reg_used case, make sure that the got load isn't deleted
11250 when mcount needs it. Blockage to avoid call movement across mcount
11251 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11252 note. */
11257 {
11258 /* vDRAP is setup but after reload it turns out stack realign
11259 isn't necessary, here we will emit prologue to setup DRAP
11260 without stack realign adjustment */
11263 }
11265 /* Prevent instructions from being scheduled into register save push
11266 sequence when access to the redzone area is done through frame pointer.
11267 The offset between the frame pointer and the stack pointer is calculated
11268 relative to the value of the stack pointer at the end of the function
11269 prologue, and moving instructions that access redzone area via frame
11270 pointer inside push sequence violates this assumption. */
11274 /* Emit cld instruction if stringops are used in the function. */
11278 /* SEH requires that the prologue end within 256 bytes of the start of
11279 the function. Prevent instruction schedules that would extend that.
11280 Further, prevent alloca modifications to the stack pointer from being
11281 combined with prologue modifications. */
11284 }
11286 /* Emit code to restore REG using a POP insn. */
11288 static void
11290 {
11299 {
11300 /* Previously we'd represented the CFA as an expression
11301 like *(%ebp - 8). We've just popped that value from
11302 the stack, which means we need to reset the CFA to
11303 the drap register. This will remain until we restore
11304 the stack pointer. */
11308 /* This means that the DRAP register is valid for addressing too. */
11311 }
11314 {
11321 }
11323 /* When the frame pointer is the CFA, and we pop it, we are
11324 swapping back to the stack pointer as the CFA. This happens
11325 for stack frames that don't allocate other data, so we assume
11326 the stack pointer is now pointing at the return address, i.e.
11327 the function entry state, which makes the offset be 1 word. */
11329 {
11332 {
11340 }
11341 }
11342 }
11344 /* Emit code to restore saved registers using POP insns. */
11346 static void
11348 {
11354 }
11356 /* Emit code and notes for the LEAVE instruction. */
11358 static void
11360 {
11372 {
11380 }
11383 }
11385 /* Emit code to restore saved registers using MOV insns.
11386 First register is restored from CFA - CFA_OFFSET. */
11387 static void
11390 {
11396 {
11405 {
11406 /* Previously we'd represented the CFA as an expression
11407 like *(%ebp - 8). We've just popped that value from
11408 the stack, which means we need to reset the CFA to
11409 the drap register. This will remain until we restore
11410 the stack pointer. */
11414 /* This means that the DRAP register is valid for addressing. */
11416 }
11417 else
11421 }
11422 }
11424 /* Emit code to restore saved registers using MOV insns.
11425 First register is restored from CFA - CFA_OFFSET. */
11426 static void
11429 {
11434 {
11436 rtx mem;
11446 }
11447 }
11449 /* Restore function stack, frame, and registers. */
11451 void
11453 {
11469 /* The FP must be valid if the frame pointer is present. */
11474 /* We must have *some* valid pointer to the stack frame. */
11477 /* The DRAP is never valid at this point. */
11480 /* See the comment about red zone and frame
11481 pointer usage in ix86_expand_prologue. */
11488 /* Determine the CFA offset of the end of the red-zone. */
11491 {
11492 /* The red-zone begins below the return address. */
11495 /* When the register save area is in the aligned portion of
11496 the stack, determine the maximum runtime displacement that
11497 matches up with the aligned frame. */
11501 }
11503 /* Special care must be taken for the normal return case of a function
11504 using eh_return: the eax and edx registers are marked as saved, but
11505 not restored along this path. Adjust the save location to match. */
11509 /* EH_RETURN requires the use of moves to function properly. */
11512 /* SEH requires the use of pops to identify the epilogue. */
11515 /* If we're only restoring one register and sp is not valid then
11516 using a move instruction to restore the register since it's
11517 less work than reloading sp and popping the register. */
11530 && TARGET_USE_LEAVE
11534 else
11538 {
11539 /* Ensure that the entire register save area is addressable via
11540 the stack pointer, if we will restore via sp. */
11545 {
11549 style,
11551 }
11552 }
11554 /* If there are any SSE registers to restore, then we have to do it
11555 via moves, since there's obviously no pop for SSE regs. */
11561 {
11562 rtx t;
11567 /* eh_return epilogues need %ecx added to the stack pointer. */
11569 {
11572 /* Stack align doesn't work with eh_return. */
11574 /* Neither does regparm nested functions. */
11578 {
11586 /* Note that we use SA as a temporary CFA, as the return
11587 address is at the proper place relative to it. We
11588 pretend this happens at the FP restore insn because
11589 prior to this insn the FP would be stored at the wrong
11590 offset relative to SA, and after this insn we have no
11591 other reasonable register to use for the CFA. We don't
11592 bother resetting the CFA to the SP for the duration of
11593 the return insn. */
11606 }
11607 else
11608 {
11616 {
11620 UNITS_PER_WORD));
11622 }
11623 }
11626 }
11627 }
11628 else
11629 {
11630 /* SEH requires that the function end with (1) a stack adjustment
11631 if necessary, (2) a sequence of pops, and (3) a return or
11632 jump instruction. Prevent insns from the function body from
11633 being scheduled into this sequence. */
11635 {
11636 /* Prevent a catch region from being adjacent to the standard
11637 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11638 several other flags that would be interesting to test are
11639 not yet set up. */
11642 else
11644 }
11646 /* First step is to deallocate the stack frame so that we can
11647 pop the registers. Also do it on SEH target for very large
11648 frame as the emitted instructions aren't allowed by the ABI in
11649 epilogues. */
11651 || (TARGET_SEH
11654 {
11659 }
11661 {
11665 style,
11667 }
11670 }
11672 /* If we used a stack pointer and haven't already got rid of it,
11673 then do so now. */
11675 {
11676 /* If the stack pointer is valid and pointing at the frame
11677 pointer store address, then we only need a pop. */
11680 /* Leave results in shorter dependency chains on CPUs that are
11681 able to grok it fast. */
11686 else
11687 {
11689 hard_frame_pointer_rtx,
11692 }
11693 }
11696 {
11698 rtx insn;
11724 }
11726 /* At this point the stack pointer must be valid, and we must have
11727 restored all of the registers. We may not have deallocated the
11728 entire stack frame. We've delayed this until now because it may
11729 be possible to merge the local stack deallocation with the
11730 deallocation forced by ix86_static_chain_on_stack. */
11735 {
11739 }
11740 else
11743 /* Sibcall epilogues don't want a return instruction. */
11745 {
11748 }
11751 {
11754 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11755 address, do explicit add, and jump indirectly to the caller. */
11758 {
11760 rtx insn;
11762 /* There is no "pascal" calling convention in any 64bit ABI. */
11779 }
11780 else
11782 }
11783 else
11786 /* Restore the state back to the state from the prologue,
11787 so that it's correct for the next epilogue. */
11789 }
11791 /* Reset from the function's potential modifications. */
11793 static void
11795 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11796 {
11799 #if TARGET_MACHO
11800 /* Mach-O doesn't support labels at the end of objects, so if
11801 it looks like we might want one, insert a NOP. */
11802 {
11808 {
11809 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11810 notes only, instead set their CODE_LABEL_NUMBER to -1,
11811 otherwise there would be code generation differences
11812 in between -g and -g0. */
11816 }
11826 }
11827 #endif
11829 }
11831 /* Return a scratch register to use in the split stack prologue. The
11832 split stack prologue is used for -fsplit-stack. It is the first
11833 instructions in the function, even before the regular prologue.
11834 The scratch register can be any caller-saved register which is not
11835 used for parameters or for the static chain. */
11837 static unsigned int
11839 {
11842 else
11843 {
11856 {
11858 {
11862 }
11864 }
11866 {
11870 }
11872 {
11875 else
11876 {
11878 {
11882 }
11884 }
11885 }
11886 else
11887 {
11888 /* FIXME: We could make this work by pushing a register
11889 around the addition and comparison. */
11892 }
11893 }
11894 }
11896 /* A SYMBOL_REF for the function which allocates new stackspace for
11897 -fsplit-stack. */
11901 /* A SYMBOL_REF for the more stack function when using the large
11902 model. */
11906 /* Handle -fsplit-stack. These are the first instructions in the
11907 function, even before the regular prologue. */
11909 void
11911 {
11913 HOST_WIDE_INT allocate;
11918 rtx fn;
11926 /* This is the label we will branch to if we have enough stack
11927 space. We expect the basic block reordering pass to reverse this
11928 branch if optimizing, so that we branch in the unlikely case. */
11931 /* We need to compare the stack pointer minus the frame size with
11932 the stack boundary in the TCB. The stack boundary always gives
11933 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11934 can compare directly. Otherwise we need to do an addition. */
11937 UNSPEC_STACK_CHECK);
11942 else
11943 {
11945 rtx offset;
11947 /* We need a scratch register to hold the stack pointer minus
11948 the required frame size. Since this is the very start of the
11949 function, the scratch register can be any caller-saved
11950 register which is not used for parameters. */
11957 {
11958 /* We don't use ix86_gen_add3 in this case because it will
11959 want to split to lea, but when not optimizing the insn
11960 will not be split after this point. */
11963 offset)));
11964 }
11965 else
11966 {
11969 stack_pointer_rtx));
11970 }
11972 }
11978 /* Mark the jump as very likely to be taken. */
11986 /* Get more stack space. We pass in the desired stack space and the
11987 size of the arguments to copy to the new stack. In 32-bit mode
11988 we push the parameters; __morestack will return on a new stack
11989 anyhow. In 64-bit mode we pass the parameters in r10 and
11990 r11. */
11995 {
12001 /* If this function uses a static chain, it will be in %r10.
12002 Preserve it across the call to __morestack. */
12004 {
12005 rtx rax;
12010 }
12014 {
12015 HOST_WIDE_INT argval;
12018 /* When using the large model we need to load the address
12019 into a register, and we've run out of registers. So we
12020 switch to a different calling convention, and we call a
12021 different function: __morestack_large. We pass the
12022 argument size in the upper 32 bits of r10 and pass the
12023 frame size in the lower 32 bits. */
12028 split_stack_fn_large =
12032 {
12042 UNSPEC_GOT);
12048 }
12049 else
12056 }
12057 else
12058 {
12062 }
12065 }
12066 else
12067 {
12070 }
12076 /* In order to make call/return prediction work right, we now need
12077 to execute a return instruction. See
12078 libgcc/config/i386/morestack.S for the details on how this works.
12080 For flow purposes gcc must not see this as a return
12081 instruction--we need control flow to continue at the subsequent
12082 label. Therefore, we use an unspec. */
12086 /* If we are in 64-bit mode and this function uses a static chain,
12087 we saved %r10 in %rax before calling _morestack. */
12092 /* If this function calls va_start, we need to store a pointer to
12093 the arguments on the old stack, because they may not have been
12094 all copied to the new stack. At this point the old stack can be
12095 found at the frame pointer value used by __morestack, because
12096 __morestack has set that up before calling back to us. Here we
12097 store that pointer in a scratch register, and in
12098 ix86_expand_prologue we store the scratch register in a stack
12099 slot. */
12101 {
12103 rtx frame_reg;
12110 /* 64-bit:
12111 fp -> old fp value
12112 return address within this function
12113 return address of caller of this function
12114 stack arguments
12115 So we add three words to get to the stack arguments.
12117 32-bit:
12118 fp -> old fp value
12119 return address within this function
12120 first argument to __morestack
12121 second argument to __morestack
12122 return address of caller of this function
12123 stack arguments
12124 So we add five words to get to the stack arguments.
12125 */
12136 }
12141 /* If this function calls va_start, we now have to set the scratch
12142 register for the case where we do not call __morestack. In this
12143 case we need to set it based on the stack pointer. */
12145 {
12152 }
12153 }
12155 /* We may have to tell the dataflow pass that the split stack prologue
12156 is initializing a scratch register. */
12158 static void
12160 {
12162 {
12165 }
12166 }
12167 \f
12168 /* Extract the parts of an RTL expression that is a valid memory address
12169 for an instruction. Return 0 if the structure of the address is
12170 grossly off. Return -1 if the address contains ASHIFT, so it is not
12171 strictly valid, but still used for computing length of lea instruction. */
12173 int
12175 {
12180 rtx tmp;
12184 /* Allow zero-extended SImode addresses,
12185 they will be emitted with addr32 prefix. */
12187 {
12190 {
12194 }
12197 {
12204 }
12205 }
12207 /* Allow SImode subregs of DImode addresses,
12208 they will be emitted with addr32 prefix. */
12210 {
12213 {
12217 }
12218 }
12223 {
12226 else
12228 }
12230 {
12235 do
12236 {
12241 }
12248 {
12251 {
12276 /* FALLTHRU */
12280 && TARGET_TLS_DIRECT_SEG_REFS
12283 else
12290 /* FALLTHRU */
12297 else
12312 }
12313 }
12314 }
12316 {
12319 }
12321 {
12322 /* We're called for lea too, which implements ashift on occasion. */
12332 }
12333 else
12337 {
12339 ;
12342 ;
12343 else
12345 }
12347 /* Extract the integral value of scale. */
12349 {
12353 }
12358 /* Avoid useless 0 displacement. */
12362 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12367 {
12368 rtx tmp;
12371 }
12373 /* Special case: %ebp cannot be encoded as a base without a displacement.
12374 Similarly %r13. */
12376 && base_reg
12385 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12386 Avoid this by transforming to [%esi+0].
12387 Reload calls address legitimization without cfun defined, so we need
12388 to test cfun for being non-NULL. */
12394 /* Special case: encode reg+reg instead of reg*2. */
12398 /* Special case: scaling cannot be encoded without base or displacement. */
12409 }
12410 \f
12411 /* Return cost of the memory address x.
12412 For i386, it is better to use a complex address than let gcc copy
12413 the address into a reg and make a new pseudo. But not if the address
12414 requires to two regs - that would mean more pseudos with longer
12415 lifetimes. */
12416 static int
12418 addr_space_t as ATTRIBUTE_UNUSED,
12420 {
12432 /* Attempt to minimize number of registers in the address. */
12438 cost++;
12445 cost++;
12447 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12448 since it's predecode logic can't detect the length of instructions
12449 and it degenerates to vector decoded. Increase cost of such
12450 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12451 to split such addresses or even refuse such addresses at all.
12453 Following addressing modes are affected:
12454 [base+scale*index]
12455 [scale*index+disp]
12456 [base+index]
12458 The first and last case may be avoidable by explicitly coding the zero in
12459 memory address, but I don't have AMD-K6 machine handy to check this
12460 theory. */
12469 }
12470 \f
12471 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12472 this is used for to form addresses to local data when -fPIC is in
12473 use. */
12475 static bool
12477 {
12480 }
12482 /* Determine if a given RTX is a valid constant. We already know this
12483 satisfies CONSTANT_P. */
12485 static bool
12487 {
12489 {
12494 {
12498 }
12503 /* Only some unspecs are valid as "constants". */
12506 {
12522 }
12524 /* We must have drilled down to a symbol. */
12529 /* FALLTHRU */
12532 /* TLS symbols are never valid. */
12536 /* DLLIMPORT symbols are never valid. */
12541 #if TARGET_MACHO
12542 /* mdynamic-no-pic */
12545 #endif
12561 }
12563 /* Otherwise we handle everything else in the move patterns. */
12565 }
12567 /* Determine if it's legal to put X into the constant pool. This
12568 is not possible for the address of thread-local symbols, which
12569 is checked above. */
12571 static bool
12573 {
12574 /* We can always put integral constants and vectors in memory. */
12576 {
12584 }
12586 }
12588 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12589 otherwise zero. */
12591 static bool
12593 {
12599 }
12602 /* Nonzero if the constant value X is a legitimate general operand
12603 when generating PIC code. It is given that flag_pic is on and
12604 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12606 bool
12608 {
12609 rtx inner;
12612 {
12619 /* Only some unspecs are valid as "constants". */
12622 {
12635 }
12636 /* FALLTHRU */
12644 }
12645 }
12647 /* Determine if a given CONST RTX is a valid memory displacement
12648 in PIC mode. */
12650 bool
12652 {
12655 /* In 64bit mode we can allow direct addresses of symbols and labels
12656 when they are not dynamic symbols. */
12658 {
12662 {
12686 /* FALLTHRU */
12689 /* TLS references should always be enclosed in UNSPEC.
12690 The dllimported symbol needs always to be resolved. */
12696 {
12704 /* Function-symbols need to be resolved only for
12705 large-model.
12706 For the small-model we don't need to resolve anything
12707 here. */
12712 /* Non-external symbols don't need to be resolved for
12713 large, and medium-model. */
12718 }
12727 }
12728 }
12734 {
12735 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12736 of GOT tables. We should not need these anyway. */
12748 }
12752 {
12757 }
12766 {
12770 /* We need to check for both symbols and labels because VxWorks loads
12771 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12772 details. */
12776 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12777 While ABI specify also 32bit relocation but we don't produce it in
12778 small PIC model at all. */
12800 }
12803 }
12805 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12806 replace the input X, or the original X if no replacement is called for.
12807 The output parameter *WIN is 1 if the calling macro should goto WIN,
12808 0 if it should not. */
12810 bool
12815 {
12816 /* Reload can generate:
12818 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12819 (reg:DI 97))
12820 (reg:DI 2 cx))
12822 This RTX is rejected from ix86_legitimate_address_p due to
12823 non-strictness of base register 97. Following this rejection,
12824 reload pushes all three components into separate registers,
12825 creating invalid memory address RTX.
12827 Following code reloads only the invalid part of the
12828 memory address RTX. */
12834 {
12840 {
12845 }
12849 {
12854 }
12858 }
12861 }
12863 /* Determine if op is suitable RTX for an address register.
12864 Return naked register if a register or a register subreg is
12865 found, otherwise return NULL_RTX. */
12867 static rtx
12869 {
12872 /* Only SImode or DImode registers can form the address. */
12879 {
12887 /* Don't allow SUBREGs that span more than a word. It can
12888 lead to spill failures when the register is one word out
12889 of a two word structure. */
12893 /* Allow only SUBREGs of non-eliminable hard registers. */
12896 }
12898 /* Op is not a register. */
12900 }
12902 /* Recognizes RTL expressions that are valid memory addresses for an
12903 instruction. The MODE argument is the machine mode for the MEM
12904 expression that wants to use this address.
12906 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12907 convert common non-canonical forms to canonical form so that they will
12908 be recognized. */
12910 static bool
12913 {
12916 HOST_WIDE_INT scale;
12920 /* Decomposition failed. */
12929 /* Validate base register. */
12931 {
12939 /* Base is not valid. */
12941 }
12943 /* Validate index register. */
12945 {
12953 /* Index is not valid. */
12955 }
12957 /* Index and base should have the same mode. */
12962 /* Address override works only on the (%reg) part of %fs:(%reg). */
12968 /* Validate scale factor. */
12970 {
12972 /* Scale without index. */
12976 /* Scale is not a valid multiplier. */
12978 }
12980 /* Validate displacement. */
12982 {
12987 {
12988 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12989 used. While ABI specify also 32bit relocations, we don't produce
12990 them at all and use IP relative instead. */
12997 /* 64bit address unspec. */
13017 /* Invalid address unspec. */
13019 }
13022 && (flag_pic
13023 || (TARGET_MACHO
13024 #if TARGET_MACHO
13025 && MACHOPIC_INDIRECT
13027 #endif
13028 )))
13029 {
13031 is_legitimate_pic:
13033 {
13034 /* foo@dtpoff(%rX) is ok. */
13041 /* Non-constant pic memory reference. */
13043 }
13046 /* Displacement is an invalid pic construct. */
13048 #if TARGET_MACHO
13051 /* displacment must be referenced via non_lazy_pointer */
13053 #endif
13055 /* This code used to verify that a symbolic pic displacement
13056 includes the pic_offset_table_rtx register.
13058 While this is good idea, unfortunately these constructs may
13059 be created by "adds using lea" optimization for incorrect
13060 code like:
13062 int a;
13063 int foo(int i)
13064 {
13065 return *(&a+i);
13066 }
13068 This code is nonsensical, but results in addressing
13069 GOT table with pic_offset_table_rtx base. We can't
13070 just refuse it easily, since it gets matched by
13071 "addsi3" pattern, that later gets split to lea in the
13072 case output register differs from input. While this
13073 can be handled by separate addsi pattern for this case
13074 that never results in lea, this seems to be easier and
13075 correct fix for crash to disable this test. */
13076 }
13083 /* Displacement is not constant. */
13087 /* Displacement is out of range. */
13089 /* In x32 mode, constant addresses are sign extended to 64bit, so
13090 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13095 }
13097 /* Everything looks valid. */
13099 }
13101 /* Determine if a given RTX is a valid constant address. */
13103 bool
13105 {
13107 }
13108 \f
13109 /* Return a unique alias set for the GOT. */
13111 static alias_set_type
13113 {
13118 }
13120 /* Return a legitimate reference for ORIG (an address) using the
13121 register REG. If REG is 0, a new pseudo is generated.
13123 There are two types of references that must be handled:
13125 1. Global data references must load the address from the GOT, via
13126 the PIC reg. An insn is emitted to do this load, and the reg is
13127 returned.
13129 2. Static data references, constant pool addresses, and code labels
13130 compute the address as an offset from the GOT, whose base is in
13131 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13132 differentiate them from global data objects. The returned
13133 address is the PIC reg + an unspec constant.
13135 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13136 reg also appears in the address. */
13138 static rtx
13140 {
13144 #if TARGET_MACHO
13146 {
13149 /* Use the generic Mach-O PIC machinery. */
13151 }
13152 #endif
13155 {
13159 }
13165 {
13166 rtx tmpreg;
13167 /* This symbol may be referenced via a displacement from the PIC
13168 base address (@GOTOFF). */
13175 {
13177 UNSPEC_GOTOFF);
13179 }
13180 else
13185 else
13190 {
13194 }
13195 else
13197 }
13199 {
13200 /* This symbol may be referenced via a displacement from the PIC
13201 base address (@GOTOFF). */
13208 {
13210 UNSPEC_GOTOFF);
13212 }
13213 else
13219 {
13222 }
13223 }
13225 /* We can't use @GOTOFF for text labels on VxWorks;
13226 see gotoff_operand. */
13228 {
13233 /* For x64 PE-COFF there is no GOT table. So we use address
13234 directly. */
13236 {
13244 }
13246 {
13254 /* Use directly gen_movsi, otherwise the address is loaded
13255 into register for CSE. We don't want to CSE this addresses,
13256 instead we CSE addresses from the GOT table, so skip this. */
13259 }
13260 else
13261 {
13262 /* This symbol must be referenced via a load from the
13263 Global Offset Table (@GOT). */
13279 }
13280 }
13281 else
13282 {
13285 {
13287 {
13290 }
13291 else
13293 }
13295 {
13298 /* We must match stuff we generate before. Assume the only
13299 unspecs that can get here are ours. Not that we could do
13300 anything with them anyway.... */
13306 }
13308 {
13311 /* Check first to see if this is a constant offset from a @GOTOFF
13312 symbol reference. */
13315 {
13317 {
13321 UNSPEC_GOTOFF);
13327 {
13330 }
13331 }
13332 else
13333 {
13336 {
13340 }
13341 }
13342 }
13343 else
13344 {
13347 new_rtx
13351 {
13354 {
13357 new_rtx
13359 }
13360 else
13362 }
13363 else
13364 {
13367 {
13370 }
13372 }
13373 }
13374 }
13375 }
13377 }
13378 \f
13379 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13381 static rtx
13383 {
13387 {
13392 }
13398 }
13400 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13404 static rtx
13406 {
13408 {
13414 }
13417 {
13419 UNSPEC_PLTOFF);
13422 }
13425 }
13427 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13431 rtx
13433 {
13435 {
13436 ix86_tls_module_base_symbol
13441 }
13444 }
13446 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13447 false if we expect this to be used for a memory address and true if
13448 we expect to load the address into a register. */
13450 static rtx
13452 {
13458 /* Fall back to global dynamic model if tool chain cannot support local
13459 dynamic. */
13466 {
13471 {
13474 else
13475 {
13478 }
13479 }
13482 {
13485 else
13495 }
13496 else
13497 {
13501 {
13503 rtx insns;
13506 emit_call_insn
13516 }
13517 else
13519 }
13526 {
13529 else
13530 {
13533 }
13534 }
13537 {
13542 else
13548 }
13549 else
13550 {
13554 {
13559 emit_call_insn
13564 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13565 share the LD_BASE result with other LD model accesses. */
13567 UNSPEC_TLS_LD_BASE);
13571 }
13572 else
13574 }
13582 {
13589 }
13594 {
13596 {
13597 /* The Sun linker took the AMD64 TLS spec literally
13598 and can only handle %rax as destination of the
13599 initial executable code sequence. */
13604 }
13606 /* Generate DImode references to avoid %fs:(%reg32)
13607 problems and linker IE->LE relaxation bug. */
13611 }
13613 {
13618 }
13620 {
13624 }
13625 else
13626 {
13629 }
13639 {
13644 }
13645 else
13646 {
13650 }
13660 {
13664 }
13665 else
13666 {
13670 }
13675 }
13678 }
13680 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13681 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13682 unique refptr-DECL symbol corresponding to symbol DECL. */
13685 htab_t dllimport_map;
13687 static tree
13689 {
13696 tree to;
13697 rtx rtl;
13724 else
13737 {
13739 #ifdef SUB_TARGET_RECORD_STUB
13741 #endif
13742 }
13751 }
13753 /* Expand SYMBOL into its corresponding far-addresse symbol.
13754 WANT_REG is true if we require the result be a register. */
13756 static rtx
13758 {
13759 tree imp_decl;
13760 rtx x;
13769 }
13771 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13772 true if we require the result be a register. */
13774 static rtx
13776 {
13777 tree imp_decl;
13778 rtx x;
13787 }
13789 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13790 is true if we require the result be a register. */
13792 static rtx
13794 {
13799 {
13806 {
13809 }
13810 }
13826 {
13829 }
13831 }
13833 /* Try machine-dependent ways of modifying an illegitimate address
13834 to be legitimate. If we find one, return the new, valid address.
13835 This macro is used in only one place: `memory_address' in explow.c.
13837 OLDX is the address as it was before break_out_memory_refs was called.
13838 In some cases it is useful to look at this to decide what needs to be done.
13840 It is always safe for this macro to do nothing. It exists to recognize
13841 opportunities to optimize the output.
13843 For the 80386, we handle X+REG by loading X into a register R and
13844 using R+REG. R will go in a general reg and indexing will be used.
13845 However, if REG is a broken-out memory address or multiplication,
13846 nothing needs to be done because REG can certainly go in a general reg.
13848 When -fpic is used, special handling is needed for symbolic references.
13849 See comments by legitimize_pic_address in i386.c for details. */
13851 static rtx
13854 {
13865 {
13869 }
13872 {
13876 }
13881 #if TARGET_MACHO
13884 #endif
13886 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13890 {
13895 }
13898 {
13899 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13904 {
13910 }
13915 {
13921 }
13923 /* Put multiply first if it isn't already. */
13925 {
13930 }
13932 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13933 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13934 created by virtual register instantiation, register elimination, and
13935 similar optimizations. */
13937 {
13943 }
13945 /* Canonicalize
13946 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13947 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13952 {
13953 rtx constant;
13957 {
13960 }
13962 {
13965 }
13966 else
13970 {
13977 }
13978 }
13984 {
13987 }
13990 {
13993 }
14001 {
14004 }
14010 {
14014 {
14017 }
14021 }
14024 {
14028 {
14031 }
14035 }
14036 }
14039 }
14040 \f
14041 /* Print an integer constant expression in assembler syntax. Addition
14042 and subtraction are the only arithmetic that may appear in these
14043 expressions. FILE is the stdio stream to write to, X is the rtx, and
14044 CODE is the operand print code from the output string. */
14046 static void
14048 {
14052 {
14061 else
14062 {
14065 /* Mark the decl as referenced so that cgraph will
14066 output the function. */
14070 #if TARGET_MACHO
14074 #endif
14076 }
14084 /* FALLTHRU */
14095 /* This used to output parentheses around the expression,
14096 but that does not work on the 386 (either ATT or BSD assembler). */
14102 {
14103 /* We can use %d if the number is <32 bits and positive. */
14108 else
14110 }
14111 else
14112 /* We can't handle floating point constants;
14113 TARGET_PRINT_OPERAND must handle them. */
14118 /* Some assemblers need integer constants to appear first. */
14120 {
14124 }
14125 else
14126 {
14131 }
14146 {
14150 }
14155 {
14174 /* FIXME: This might be @TPOFF in Sun ld too. */
14183 else
14193 else
14199 #if TARGET_MACHO
14204 #endif
14208 }
14213 }
14214 }
14216 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14217 We need to emit DTP-relative relocations. */
14219 static void ATTRIBUTE_UNUSED
14221 {
14226 {
14234 }
14235 }
14237 /* Return true if X is a representation of the PIC register. This copes
14238 with calls from ix86_find_base_term, where the register might have
14239 been replaced by a cselib value. */
14241 static bool
14243 {
14247 else
14249 }
14251 /* Helper function for ix86_delegitimize_address.
14252 Attempt to delegitimize TLS local-exec accesses. */
14254 static rtx
14256 {
14281 {
14286 }
14292 }
14294 /* In the name of slightly smaller debug output, and to cater to
14295 general assembler lossage, recognize PIC+GOTOFF and turn it back
14296 into a direct symbol reference.
14298 On Darwin, this is necessary to avoid a crash, because Darwin
14299 has a different PIC label for each routine but the DWARF debugging
14300 information is not associated with any particular routine, so it's
14301 necessary to remove references to the PIC label from RTL stored by
14302 the DWARF output code. */
14304 static rtx
14306 {
14308 /* addend is NULL or some rtx if x is something+GOTOFF where
14309 something doesn't include the PIC register. */
14311 /* reg_addend is NULL or a multiple of some register. */
14313 /* const_addend is NULL or a const_int. */
14315 /* This is the result, or NULL. */
14324 {
14331 {
14337 }
14344 {
14347 {
14352 }
14354 }
14359 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14360 and -mcmodel=medium -fpic. */
14361 }
14368 /* %ebx + GOT/GOTOFF */
14369 ;
14371 {
14372 /* %ebx + %reg * scale + GOT/GOTOFF */
14378 else
14379 {
14382 }
14383 }
14384 else
14390 {
14393 }
14414 {
14415 /* If the rest of original X doesn't involve the PIC register, add
14416 addend and subtract pic_offset_table_rtx. This can happen e.g.
14417 for code like:
14418 leal (%ebx, %ecx, 4), %ecx
14419 ...
14420 movl foo@GOTOFF(%ecx), %edx
14421 in which case we return (%ecx - %ebx) + foo. */
14424 pic_offset_table_rtx),
14425 result);
14426 else
14428 }
14430 {
14434 }
14436 }
14438 /* If X is a machine specific address (i.e. a symbol or label being
14439 referenced as a displacement from the GOT implemented using an
14440 UNSPEC), then return the base term. Otherwise return X. */
14442 rtx
14444 {
14445 rtx term;
14448 {
14462 }
14465 }
14466 \f
14467 static void
14470 {
14474 {
14477 }
14482 {
14485 {
14504 }
14508 {
14527 }
14534 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14535 Those same assemblers have the same but opposite lossage on cmov. */
14538 else
14543 {
14556 }
14563 else
14568 {
14581 }
14588 else
14598 else
14609 }
14611 }
14613 /* Print the name of register X to FILE based on its machine mode and number.
14614 If CODE is 'w', pretend the mode is HImode.
14615 If CODE is 'b', pretend the mode is QImode.
14616 If CODE is 'k', pretend the mode is SImode.
14617 If CODE is 'q', pretend the mode is DImode.
14618 If CODE is 'x', pretend the mode is V4SFmode.
14619 If CODE is 't', pretend the mode is V8SFmode.
14620 If CODE is 'g', pretend the mode is V16SFmode.
14621 If CODE is 'h', pretend the reg is the 'high' byte register.
14622 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14623 If CODE is 'd', duplicate the operand for AVX instruction.
14624 */
14626 void
14628 {
14637 {
14641 }
14668 else
14671 /* Irritatingly, AMD extended registers use different naming convention
14672 from the normal registers: "r%d[bwd]" */
14674 {
14679 {
14693 /* no suffix */
14698 }
14700 }
14704 {
14707 {
14710 }
14711 /* FALLTHRU */
14717 /* FALLTHRU */
14720 normal:
14735 {
14740 }
14743 {
14748 }
14752 }
14756 {
14759 else
14761 }
14762 }
14764 /* Locate some local-dynamic symbol still in use by this function
14765 so that we can print its name in some tls_local_dynamic_base
14766 pattern. */
14768 static int
14770 {
14775 {
14778 }
14781 }
14785 {
14786 rtx insn;
14797 }
14799 /* Meaning of CODE:
14800 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14801 C -- print opcode suffix for set/cmov insn.
14802 c -- like C, but print reversed condition
14803 F,f -- likewise, but for floating-point.
14804 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14805 otherwise nothing
14806 R -- print embeded rounding and sae.
14807 r -- print only sae.
14808 z -- print the opcode suffix for the size of the current operand.
14809 Z -- likewise, with special suffixes for x87 instructions.
14810 * -- print a star (in certain assembler syntax)
14811 A -- print an absolute memory reference.
14812 E -- print address with DImode register names if TARGET_64BIT.
14813 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14814 s -- print a shift double count, followed by the assemblers argument
14815 delimiter.
14816 b -- print the QImode name of the register for the indicated operand.
14817 %b0 would print %al if operands[0] is reg 0.
14818 w -- likewise, print the HImode name of the register.
14819 k -- likewise, print the SImode name of the register.
14820 q -- likewise, print the DImode name of the register.
14821 x -- likewise, print the V4SFmode name of the register.
14822 t -- likewise, print the V8SFmode name of the register.
14823 g -- likewise, print the V16SFmode name of the register.
14824 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14825 y -- print "st(0)" instead of "st" as a register.
14826 d -- print duplicated register operand for AVX instruction.
14827 D -- print condition for SSE cmp instruction.
14828 P -- if PIC, print an @PLT suffix.
14829 p -- print raw symbol name.
14830 X -- don't print any sort of PIC '@' suffix for a symbol.
14831 & -- print some in-use local-dynamic symbol name.
14832 H -- print a memory address offset by 8; used for sse high-parts
14833 Y -- print condition for XOP pcom* instruction.
14834 + -- print a branch hint as 'cs' or 'ds' prefix
14835 ; -- print a semicolon (after prefixes due to bug in older gas).
14836 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14837 @ -- print a segment register of thread base pointer load
14838 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14839 */
14841 void
14843 {
14845 {
14847 {
14850 {
14856 /* Intel syntax. For absolute addresses, registers should not
14857 be surrounded by braces. */
14859 {
14864 }
14869 }
14875 /* Wrap address in an UNSPEC to declare special handling. */
14913 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14918 {
14932 output_operand_lossage
14935 }
14938 #endif
14943 {
14944 /* Opcodes don't get size suffixes if using Intel opcodes. */
14949 {
14967 output_operand_lossage
14970 }
14971 }
14974 warning
14976 /* FALLTHRU */
14979 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14984 {
14986 {
14988 #ifdef HAVE_AS_IX86_FILDS
14990 #endif
14998 #ifdef HAVE_AS_IX86_FILDQ
15000 #else
15002 #endif
15007 }
15008 }
15010 {
15011 /* 387 opcodes don't get size suffixes
15012 if the operands are registers. */
15017 {
15033 }
15034 }
15035 else
15036 {
15037 output_operand_lossage
15040 }
15042 output_operand_lossage
15063 {
15066 }
15071 {
15122 }
15126 /* Little bit of braindamage here. The SSE compare instructions
15127 does use completely different names for the comparisons that the
15128 fp conditional moves. */
15130 {
15133 {
15136 }
15142 {
15145 }
15151 {
15154 }
15163 {
15166 }
15172 {
15175 }
15181 {
15184 }
15195 }
15200 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15203 #endif
15208 {
15212 }
15216 file);
15221 {
15225 }
15226 /* It doesn't actually matter what mode we use here, as we're
15227 only going to use this for printing. */
15229 /* Output 'qword ptr' for intel assembler dialect. */
15238 #ifdef HAVE_AS_IX86_HLE
15240 #else
15242 #endif
15244 #ifdef HAVE_AS_IX86_HLE
15246 #else
15248 #endif
15249 /* We do not want to print value of the operand. */
15278 {
15293 }
15306 {
15311 else
15314 }
15317 {
15318 rtx x;
15327 {
15332 {
15334 bool cputaken
15337 /* Emit hints only in the case default branch prediction
15338 heuristics would fail. */
15340 {
15341 /* We use 3e (DS) prefix for taken branches and
15342 2e (CS) prefix for not taken branches. */
15345 else
15347 }
15348 }
15349 }
15351 }
15354 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15356 #endif
15363 /* The kernel uses a different segment register for performance
15364 reasons; a system call would not have to trash the userspace
15365 segment register, which would be expensive. */
15368 else
15383 }
15384 }
15390 {
15391 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15394 {
15397 {
15406 else
15413 }
15415 /* Check for explicit size override (codes 'b', 'w', 'k',
15416 'q' and 'x') */
15430 }
15433 /* Avoid (%rip) for call operands. */
15439 else
15441 }
15444 {
15445 REAL_VALUE_TYPE r;
15453 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15457 else
15459 }
15462 {
15463 REAL_VALUE_TYPE r;
15472 }
15474 /* These float cases don't actually occur as immediate operands. */
15476 {
15481 }
15483 else
15484 {
15485 /* We have patterns that allow zero sets of memory, for instance.
15486 In 64-bit mode, we should probably support all 8-byte vectors,
15487 since we can in fact encode that into an immediate. */
15489 {
15492 }
15495 {
15497 {
15500 }
15503 {
15506 else
15508 }
15509 }
15514 else
15516 }
15517 }
15519 static bool
15521 {
15524 }
15525 \f
15526 /* Print a memory operand whose address is ADDR. */
15528 static void
15530 {
15539 {
15546 }
15548 {
15552 }
15553 else
15564 {
15575 }
15577 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15579 {
15591 }
15593 {
15594 /* Displacement only requires special attention. */
15597 {
15601 }
15604 else
15606 }
15607 else
15608 {
15609 /* Print SImode register names to force addr32 prefix. */
15611 {
15612 #ifdef ENABLE_CHECKING
15615 {
15626 }
15627 #endif
15630 }
15632 && TARGET_X32
15633 && disp
15636 {
15637 /* X32 runs in 64-bit mode, where displacement, DISP, in
15638 address DISP(%r64), is encoded as 32-bit immediate sign-
15639 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15640 address is %r64 + 0xffffffffbffffd00. When %r64 <
15641 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15642 which is invalid for x32. The correct address is %r64
15643 - 0x40000300 == 0xf7ffdd64. To properly encode
15644 -0x40000300(%r64) for x32, we zero-extend negative
15645 displacement by forcing addr32 prefix which truncates
15646 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15647 zero-extend all negative displacements, including -1(%rsp).
15648 However, for small negative displacements, sign-extension
15649 won't cause overflow. We only zero-extend negative
15650 displacements if they < -16*1024*1024, which is also used
15651 to check legitimate address displacements for PIC. */
15653 }
15656 {
15658 {
15663 else
15665 }
15671 {
15676 }
15678 }
15679 else
15680 {
15684 {
15685 /* Pull out the offset of a symbol; print any symbol itself. */
15689 {
15693 }
15701 else
15703 }
15707 {
15710 {
15714 }
15715 }
15718 else
15722 {
15727 }
15729 }
15730 }
15731 }
15733 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15735 static bool
15737 {
15738 rtx op;
15745 {
15748 /* FIXME: This might be @TPOFF in Sun ld. */
15759 else
15771 else
15778 #if TARGET_MACHO
15784 #endif
15787 {
15792 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15794 #else
15796 #endif
15799 }
15804 }
15807 }
15808 \f
15809 /* Split one or more double-mode RTL references into pairs of half-mode
15810 references. The RTL can be REG, offsettable MEM, integer constant, or
15811 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15812 split and "num" is its length. lo_half and hi_half are output arrays
15813 that parallel "operands". */
15815 void
15818 {
15823 {
15832 }
15837 {
15840 /* simplify_subreg refuse to split volatile memory addresses,
15841 but we still have to handle it. */
15843 {
15846 }
15847 else
15848 {
15855 }
15856 }
15857 }
15858 \f
15859 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15860 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15861 is the expression of the binary operation. The output may either be
15862 emitted here, or returned to the caller, like all output_* functions.
15864 There is no guarantee that the operands are the same mode, as they
15865 might be within FLOAT or FLOAT_EXTEND expressions. */
15867 #ifndef SYSV386_COMPAT
15868 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15869 wants to fix the assemblers because that causes incompatibility
15870 with gcc. No-one wants to fix gcc because that causes
15871 incompatibility with assemblers... You can use the option of
15872 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15873 #define SYSV386_COMPAT 1
15874 #endif
15878 {
15884 #ifdef ENABLE_CHECKING
15885 /* Even if we do not want to check the inputs, this documents input
15886 constraints. Which helps in understanding the following code. */
15896 else
15898 #endif
15901 {
15906 else
15915 else
15924 else
15933 else
15940 }
15943 {
15945 {
15949 else
15951 }
15952 else
15953 {
15957 else
15959 }
15961 }
15965 {
15969 {
15973 }
15975 /* know operands[0] == operands[1]. */
15978 {
15981 }
15984 {
15986 /* How is it that we are storing to a dead operand[2]?
15987 Well, presumably operands[1] is dead too. We can't
15988 store the result to st(0) as st(0) gets popped on this
15989 instruction. Instead store to operands[2] (which I
15990 think has to be st(1)). st(1) will be popped later.
15991 gcc <= 2.8.1 didn't have this check and generated
15992 assembly code that the Unixware assembler rejected. */
15994 else
15997 }
16001 else
16008 {
16011 }
16014 {
16017 }
16020 {
16021 #if SYSV386_COMPAT
16022 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16023 derived assemblers, confusingly reverse the direction of
16024 the operation for fsub{r} and fdiv{r} when the
16025 destination register is not st(0). The Intel assembler
16026 doesn't have this brain damage. Read !SYSV386_COMPAT to
16027 figure out what the hardware really does. */
16030 else
16032 #else
16034 /* As above for fmul/fadd, we can't store to st(0). */
16036 else
16038 #endif
16040 }
16043 {
16044 #if SYSV386_COMPAT
16047 else
16049 #else
16052 else
16054 #endif
16056 }
16059 {
16062 else
16065 }
16067 {
16068 #if SYSV386_COMPAT
16070 #else
16072 #endif
16073 }
16074 else
16075 {
16076 #if SYSV386_COMPAT
16078 #else
16080 #endif
16081 }
16086 }
16090 }
16092 /* Check if a 256bit AVX register is referenced inside of EXP. */
16094 static int
16096 {
16107 }
16109 /* Return needed mode for entity in optimize_mode_switching pass. */
16111 static int
16113 {
16115 {
16116 rtx link;
16118 /* Needed mode is set to AVX_U128_CLEAN if there are
16119 no 256bit modes used in function arguments. */
16121 link;
16123 {
16125 {
16130 }
16131 }
16134 }
16136 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16137 changes state only when a 256bit register is written to, but we need
16138 to prevent the compiler from moving optimal insertion point above
16139 eventual read from 256bit register. */
16144 }
16146 /* Return mode that i387 must be switched into
16147 prior to the execution of insn. */
16149 static int
16151 {
16154 /* The mode UNINITIALIZED is used to store control word after a
16155 function call or ASM pattern. The mode ANY specify that function
16156 has no requirements on the control word and make no changes in the
16157 bits we are interested in. */
16171 {
16194 }
16197 }
16199 /* Return mode that entity must be switched into
16200 prior to the execution of insn. */
16202 static int
16204 {
16206 {
16216 }
16218 }
16220 /* Check if a 256bit AVX register is referenced in stores. */
16222 static void
16224 {
16226 {
16229 }
16230 }
16232 /* Calculate mode of upper 128bit AVX registers after the insn. */
16234 static int
16236 {
16243 /* We know that state is clean after CALL insn if there are no
16244 256bit registers used in the function return register. */
16246 {
16251 }
16253 /* Otherwise, return current mode. Remember that if insn
16254 references AVX 256bit registers, the mode was already changed
16255 to DIRTY from MODE_NEEDED. */
16257 }
16259 /* Return the mode that an insn results in. */
16261 int
16263 {
16265 {
16275 }
16276 }
16278 static int
16280 {
16281 tree arg;
16283 /* Entry mode is set to AVX_U128_DIRTY if there are
16284 256bit modes used in function arguments. */
16287 {
16292 }
16295 }
16297 /* Return a mode that ENTITY is assumed to be
16298 switched to at function entry. */
16300 static int
16302 {
16304 {
16314 }
16315 }
16317 static int
16319 {
16322 /* Exit mode is set to AVX_U128_DIRTY if there are
16323 256bit modes used in the function return register. */
16328 }
16330 /* Return a mode that ENTITY is assumed to be
16331 switched to at function exit. */
16333 static int
16335 {
16337 {
16347 }
16348 }
16350 static int
16352 {
16354 }
16356 /* Output code to initialize control word copies used by trunc?f?i and
16357 rounding patterns. CURRENT_MODE is set to current control word,
16358 while NEW_MODE is set to new control word. */
16360 static void
16362 {
16364 rtx new_mode;
16375 {
16377 {
16379 /* round toward zero (truncate) */
16385 /* round down toward -oo */
16392 /* round up toward +oo */
16399 /* mask precision exception for nearbyint() */
16406 }
16407 }
16408 else
16409 {
16411 {
16413 /* round toward zero (truncate) */
16419 /* round down toward -oo */
16425 /* round up toward +oo */
16431 /* mask precision exception for nearbyint() */
16438 }
16439 }
16445 }
16447 /* Emit vzeroupper. */
16449 void
16451 {
16454 /* Cancel automatic vzeroupper insertion if there are
16455 live call-saved SSE registers at the insertion point. */
16467 }
16469 /* Generate one or more insns to set ENTITY to MODE. */
16471 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16472 is the set of hard registers live at the point where the insn(s)
16473 are to be inserted. */
16475 static void
16477 HARD_REG_SET regs_live)
16478 {
16480 {
16495 }
16496 }
16498 /* Output code for INSN to convert a float to a signed int. OPERANDS
16499 are the insn operands. The output may be [HSD]Imode and the input
16500 operand may be [SDX]Fmode. */
16504 {
16509 /* Jump through a hoop or two for DImode, since the hardware has no
16510 non-popping instruction. We used to do this a different way, but
16511 that was somewhat fragile and broke with post-reload splitters. */
16521 else
16522 {
16527 else
16531 }
16534 }
16536 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16537 have the values zero or one, indicates the ffreep insn's operand
16538 from the OPERANDS array. */
16542 {
16544 #ifdef HAVE_AS_IX86_FFREEP
16546 #else
16547 {
16557 }
16558 #endif
16561 }
16564 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16565 should be used. UNORDERED_P is true when fucom should be used. */
16569 {
16575 {
16578 }
16579 else
16580 {
16583 }
16586 {
16590 else
16592 else
16595 else
16597 }
16604 {
16606 {
16609 }
16610 else
16612 }
16615 && stack_top_dies
16618 {
16619 /* If both the top of the 387 stack dies, and the other operand
16620 is also a stack register that dies, then this must be a
16621 `fcompp' float compare */
16624 {
16625 /* There is no double popping fcomi variant. Fortunately,
16626 eflags is immune from the fstp's cc clobbering. */
16629 else
16632 }
16633 else
16634 {
16637 else
16639 }
16640 }
16641 else
16642 {
16643 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16646 {
16654 NULL,
16655 NULL,
16662 NULL,
16663 NULL,
16664 NULL,
16665 NULL
16666 };
16681 }
16682 }
16684 void
16686 {
16689 #ifdef ASM_QUAD
16692 #else
16694 #endif
16697 }
16699 void
16701 {
16704 #ifdef ASM_QUAD
16707 #else
16709 #endif
16710 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16716 #if TARGET_MACHO
16718 {
16722 }
16723 #endif
16724 else
16727 }
16728 \f
16729 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16730 for the target. */
16732 void
16734 {
16735 rtx tmp;
16737 /* We play register width games, which are only valid after reload. */
16740 /* Avoid HImode and its attendant prefix byte. */
16746 {
16749 }
16752 }
16754 /* X is an unchanging MEM. If it is a constant pool reference, return
16755 the constant pool rtx, else NULL. */
16757 rtx
16759 {
16766 }
16768 void
16770 {
16778 {
16779 rtx tmp;
16783 {
16789 }
16792 }
16796 {
16799 rtx tmp;
16804 else
16808 {
16815 }
16816 }
16820 {
16822 {
16823 #if TARGET_MACHO
16824 /* dynamic-no-pic */
16826 {
16827 rtx temp = ((reload_in_progress
16835 }
16837 {
16841 }
16844 else
16845 {
16853 }
16854 /* dynamic-no-pic */
16855 #endif
16856 }
16857 else
16858 {
16862 {
16868 }
16869 }
16870 }
16871 else
16872 {
16883 /* Force large constants in 64bit compilation into register
16884 to get them CSEed. */
16896 {
16897 /* If we are loading a floating point constant to a register,
16898 force the value to memory now, since we'll get better code
16899 out the back end. */
16903 {
16908 }
16909 }
16910 }
16913 }
16915 void
16917 {
16924 /* Force constants other than zero into memory. We do not know how
16925 the instructions used to build constants modify the upper 64 bits
16926 of the register, once we have that information we may be able
16927 to handle some of them more efficiently. */
16936 /* We need to check memory alignment for SSE mode since attribute
16937 can make operands unaligned. */
16942 {
16945 /* ix86_expand_vector_move_misalign() does not like constants ... */
16951 /* ... nor both arguments in memory. */
16959 }
16961 /* Make operand1 a register if it isn't already. */
16965 {
16968 }
16971 }
16973 /* Split 32-byte AVX unaligned load and store if needed. */
16975 static void
16977 {
16978 rtx m;
16985 {
17006 }
17009 {
17011 {
17018 }
17019 /* Normal *mov<mode>_internal pattern will handle
17020 unaligned loads just fine if misaligned_operand
17021 is true, and without the UNSPEC it can be combined
17022 with arithmetic instructions. */
17025 else
17027 }
17029 {
17031 {
17036 }
17037 else
17039 }
17040 else
17042 }
17044 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17045 straight to ix86_expand_vector_move. */
17046 /* Code generation for scalar reg-reg moves of single and double precision data:
17047 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17048 movaps reg, reg
17049 else
17050 movss reg, reg
17051 if (x86_sse_partial_reg_dependency == true)
17052 movapd reg, reg
17053 else
17054 movsd reg, reg
17056 Code generation for scalar loads of double precision data:
17057 if (x86_sse_split_regs == true)
17058 movlpd mem, reg (gas syntax)
17059 else
17060 movsd mem, reg
17062 Code generation for unaligned packed loads of single precision data
17063 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17064 if (x86_sse_unaligned_move_optimal)
17065 movups mem, reg
17067 if (x86_sse_partial_reg_dependency == true)
17068 {
17069 xorps reg, reg
17070 movlps mem, reg
17071 movhps mem+8, reg
17072 }
17073 else
17074 {
17075 movlps mem, reg
17076 movhps mem+8, reg
17077 }
17079 Code generation for unaligned packed loads of double precision data
17080 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17081 if (x86_sse_unaligned_move_optimal)
17082 movupd mem, reg
17084 if (x86_sse_split_regs == true)
17085 {
17086 movlpd mem, reg
17087 movhpd mem+8, reg
17088 }
17089 else
17090 {
17091 movsd mem, reg
17092 movhpd mem+8, reg
17093 }
17094 */
17096 void
17098 {
17107 {
17109 {
17113 {
17115 {
17118 }
17119 else
17121 }
17123 /* FALLTHRU */
17127 {
17142 }
17148 else
17156 }
17159 }
17163 {
17165 {
17169 {
17171 {
17174 }
17175 else
17177 }
17179 /* FALLTHRU */
17189 }
17192 }
17195 {
17196 /* Normal *mov<mode>_internal pattern will handle
17197 unaligned loads just fine if misaligned_operand
17198 is true, and without the UNSPEC it can be combined
17199 with arithmetic instructions. */
17205 /* ??? If we have typed data, then it would appear that using
17206 movdqu is the only way to get unaligned data loaded with
17207 integer type. */
17209 {
17211 {
17214 }
17216 /* We will eventually emit movups based on insn attributes. */
17220 }
17222 {
17223 rtx zero;
17226 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17227 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17229 {
17230 /* We will eventually emit movups based on insn attributes. */
17233 }
17235 /* When SSE registers are split into halves, we can avoid
17236 writing to the top half twice. */
17238 {
17241 }
17242 else
17243 {
17244 /* ??? Not sure about the best option for the Intel chips.
17245 The following would seem to satisfy; the register is
17246 entirely cleared, breaking the dependency chain. We
17247 then store to the upper half, with a dependency depth
17248 of one. A rumor has it that Intel recommends two movsd
17249 followed by an unpacklpd, but this is unconfirmed. And
17250 given that the dependency depth of the unpacklpd would
17251 still be one, I'm not sure why this would be better. */
17253 }
17259 }
17260 else
17261 {
17262 rtx t;
17265 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17266 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17268 {
17270 {
17273 }
17280 }
17284 else
17289 else
17298 }
17299 }
17301 {
17303 {
17306 /* We will eventually emit movups based on insn attributes. */
17308 }
17310 {
17312 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17313 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17315 /* We will eventually emit movups based on insn attributes. */
17317 else
17318 {
17323 }
17324 }
17325 else
17326 {
17331 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17332 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17334 {
17337 }
17338 else
17339 {
17344 }
17345 }
17346 }
17347 else
17349 }
17351 /* Helper function of ix86_fixup_binary_operands to canonicalize
17352 operand order. Returns true if the operands should be swapped. */
17354 static bool
17356 rtx operands[])
17357 {
17362 /* If the operation is not commutative, we can't do anything. */
17366 /* Highest priority is that src1 should match dst. */
17372 /* Next highest priority is that immediate constants come second. */
17378 /* Lowest priority is that memory references should come second. */
17385 }
17388 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17389 destination to use for the operation. If different from the true
17390 destination in operands[0], a copy operation will be required. */
17392 rtx
17394 rtx operands[])
17395 {
17400 /* Canonicalize operand order. */
17402 {
17403 rtx temp;
17405 /* It is invalid to swap operands of different modes. */
17411 }
17413 /* Both source operands cannot be in memory. */
17415 {
17416 /* Optimization: Only read from memory once. */
17418 {
17421 }
17424 else
17426 }
17428 /* If the destination is memory, and we do not have matching source
17429 operands, do things in registers. */
17433 /* Source 1 cannot be a constant. */
17437 /* Source 1 cannot be a non-matching memory. */
17441 /* Improve address combine. */
17450 }
17452 /* Similarly, but assume that the destination has already been
17453 set up properly. */
17455 void
17458 {
17461 }
17463 /* Attempt to expand a binary operator. Make the expansion closer to the
17464 actual machine, then just general_operand, which will allow 3 separate
17465 memory references (one output, two input) in a single insn. */
17467 void
17469 rtx operands[])
17470 {
17477 /* Emit the instruction. */
17481 {
17482 /* Reload doesn't know about the flags register, and doesn't know that
17483 it doesn't want to clobber it. We can only do this with PLUS. */
17486 }
17490 {
17491 /* This is going to be an LEA; avoid splitting it later. */
17493 }
17494 else
17495 {
17498 }
17500 /* Fix up the destination if needed. */
17503 }
17505 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17506 the given OPERANDS. */
17508 void
17510 rtx operands[])
17511 {
17514 {
17517 }
17519 {
17522 }
17523 /* Optimize (__m128i) d | (__m128i) e and similar code
17524 when d and e are float vectors into float vector logical
17525 insn. In C/C++ without using intrinsics there is no other way
17526 to express vector logical operation on float vectors than
17527 to cast them temporarily to integer vectors. */
17529 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17538 {
17539 rtx dst;
17541 {
17550 {
17553 }
17554 else
17555 {
17560 }
17571 }
17572 }
17581 }
17583 /* Return TRUE or FALSE depending on whether the binary operator meets the
17584 appropriate constraints. */
17586 bool
17589 {
17594 /* Both source operands cannot be in memory. */
17598 /* Canonicalize operand order for commutative operators. */
17600 {
17604 }
17606 /* If the destination is memory, we must have a matching source operand. */
17610 /* Source 1 cannot be a constant. */
17614 /* Source 1 cannot be a non-matching memory. */
17616 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17624 }
17626 /* Attempt to expand a unary operator. Make the expansion closer to the
17627 actual machine, then just general_operand, which will allow 2 separate
17628 memory references (one output, one input) in a single insn. */
17630 void
17632 rtx operands[])
17633 {
17640 /* If the destination is memory, and we do not have matching source
17641 operands, do things in registers. */
17644 {
17647 else
17649 }
17651 /* When source operand is memory, destination must match. */
17655 /* Emit the instruction. */
17659 {
17660 /* Reload doesn't know about the flags register, and doesn't know that
17661 it doesn't want to clobber it. */
17664 }
17665 else
17666 {
17669 }
17671 /* Fix up the destination if needed. */
17674 }
17676 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17677 divisor are within the range [0-255]. */
17679 void
17682 {
17691 {
17704 }
17711 /* Use 8bit unsigned divimod if dividend and divisor are within
17712 the range [0-255]. */
17721 pc_rtx);
17726 /* Generate original signed/unsigned divimod. */
17731 /* Branch to the end. */
17735 /* Generate 8bit unsigned divide. */
17737 /* Don't use operands[0] for result of 8bit divide since not all
17738 registers support QImode ZERO_EXTRACT. */
17745 {
17748 }
17749 else
17750 {
17753 }
17755 /* Extract remainder from AH. */
17759 else
17760 {
17761 /* Need a new scratch register since the old one has result
17762 of 8bit divide. */
17766 }
17769 /* Zero extend quotient from AL. */
17775 }
17777 /* Whether it is OK to emit CFI directives when emitting asm code. */
17779 bool
17781 {
17783 }
17785 #define LEA_MAX_STALL (3)
17786 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17788 /* Increase given DISTANCE in half-cycles according to
17789 dependencies between PREV and NEXT instructions.
17790 Add 1 half-cycle if there is no dependency and
17791 go to next cycle if there is some dependecy. */
17793 static unsigned int
17795 {
17811 }
17813 /* Function checks if instruction INSN defines register number
17814 REGNO1 or REGNO2. */
17816 static bool
17818 rtx insn)
17819 {
17820 df_ref def;
17830 }
17832 /* Function checks if instruction INSN uses register number
17833 REGNO as a part of address expression. */
17835 static bool
17837 {
17838 df_ref use;
17845 }
17847 /* Search backward for non-agu definition of register number REGNO1
17848 or register number REGNO2 in basic block starting from instruction
17849 START up to head of basic block or instruction INSN.
17851 Function puts true value into *FOUND var if definition was found
17852 and false otherwise.
17854 Distance in half-cycles between START and found instruction or head
17855 of BB is added to DISTANCE and returned. */
17857 static int
17861 {
17871 {
17873 {
17876 {
17879 {
17882 }
17883 }
17886 }
17891 }
17894 }
17896 /* Search backward for non-agu definition of register number REGNO1
17897 or register number REGNO2 in INSN's basic block until
17898 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17899 2. Reach neighbour BBs boundary, or
17900 3. Reach agu definition.
17901 Returns the distance between the non-agu definition point and INSN.
17902 If no definition point, returns -1. */
17904 static int
17906 rtx insn)
17907 {
17918 {
17919 edge e;
17920 edge_iterator ei;
17925 {
17928 }
17934 else
17935 {
17940 {
17941 int bb_dist
17947 {
17954 }
17955 }
17958 }
17959 }
17961 /* get_attr_type may modify recog data. We want to make sure
17962 that recog data is valid for instruction INSN, on which
17963 distance_non_agu_define is called. INSN is unchanged here. */
17970 }
17972 /* Return the distance in half-cycles between INSN and the next
17973 insn that uses register number REGNO in memory address added
17974 to DISTANCE. Return -1 if REGNO0 is set.
17976 Put true value into *FOUND if register usage was found and
17977 false otherwise.
17978 Put true value into *REDEFINED if register redefinition was
17979 found and false otherwise. */
17981 static int
17985 {
17994 {
17997 /* If insn and start belong to the same bb, set prev to insn,
17998 so the call to increase_distance will increase the distance
17999 between insns by 1. */
18001 }
18006 {
18008 {
18011 {
18012 /* Return DISTANCE if OP0 is used in memory
18013 address in NEXT. */
18016 }
18019 {
18020 /* Return -1 if OP0 is set in NEXT. */
18023 }
18026 }
18032 }
18035 }
18037 /* Return the distance between INSN and the next insn that uses
18038 register number REGNO0 in memory address. Return -1 if no such
18039 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18041 static int
18043 {
18055 {
18056 edge e;
18057 edge_iterator ei;
18062 {
18065 }
18071 else
18072 {
18078 {
18079 int bb_dist
18084 {
18091 }
18092 }
18095 }
18096 }
18102 }
18104 /* Define this macro to tune LEA priority vs ADD, it take effect when
18105 there is a dilemma of choicing LEA or ADD
18106 Negative value: ADD is more preferred than LEA
18107 Zero: Netrual
18108 Positive value: LEA is more preferred than ADD*/
18109 #define IX86_LEA_PRIORITY 0
18111 /* Return true if usage of lea INSN has performance advantage
18112 over a sequence of instructions. Instructions sequence has
18113 SPLIT_COST cycles higher latency than lea latency. */
18115 static bool
18118 {
18121 /* For Silvermont if using a 2-source or 3-source LEA for
18122 non-destructive destination purposes, or due to wanting
18123 ability to use SCALE, the use of LEA is justified. */
18125 {
18133 }
18139 {
18140 /* If there is no non AGU operand definition, no AGU
18141 operand usage and split cost is 0 then both lea
18142 and non lea variants have same priority. Currently
18143 we prefer lea for 64 bit code and non lea on 32 bit
18144 code. */
18147 else
18149 }
18151 /* With longer definitions distance lea is more preferable.
18152 Here we change it to take into account splitting cost and
18153 lea priority. */
18156 /* If there is no use in memory addess then we just check
18157 that split cost exceeds AGU stall. */
18161 /* If this insn has both backward non-agu dependence and forward
18162 agu dependence, the one with short distance takes effect. */
18164 }
18166 /* Return true if it is legal to clobber flags by INSN and
18167 false otherwise. */
18169 static bool
18171 {
18173 df_ref use;
18174 bitmap live;
18177 {
18179 {
18186 }
18192 }
18196 }
18198 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18199 move and add to avoid AGU stalls. */
18201 bool
18203 {
18206 /* Check if we need to optimize. */
18210 /* Check it is correct to split here. */
18218 /* We need to split only adds with non destructive
18219 destination operand. */
18222 else
18224 }
18226 /* Return true if we should emit lea instruction instead of mov
18227 instruction. */
18229 bool
18231 {
18234 /* Check if we need to optimize. */
18238 /* Use lea for reg to reg moves only. */
18246 }
18248 /* Return true if we need to split lea into a sequence of
18249 instructions to avoid AGU stalls. */
18251 bool
18253 {
18259 /* Check we need to optimize. */
18263 /* The "at least two components" test below might not catch simple
18264 move or zero extension insns if parts.base is non-NULL and parts.disp
18265 is const0_rtx as the only components in the address, e.g. if the
18266 register is %rbp or %r13. As this test is much cheaper and moves or
18267 zero extensions are the common case, do this check first. */
18273 /* Check if it is OK to split here. */
18280 /* There should be at least two components in the address. */
18285 /* We should not split into add if non legitimate pic
18286 operand is used as displacement. */
18301 /* Compute how many cycles we will add to execution time
18302 if split lea into a sequence of instructions. */
18304 {
18305 /* Have to use mov instruction if non desctructive
18306 destination form is used. */
18310 /* Have to add index to base if both exist. */
18314 /* Have to use shift and adds if scale is 2 or greater. */
18316 {
18321 else
18323 }
18325 /* Have to use add instruction with immediate if
18326 disp is non zero. */
18330 /* Subtract the price of lea. */
18332 }
18336 }
18338 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18339 matches destination. RTX includes clobber of FLAGS_REG. */
18341 static void
18344 {
18351 }
18353 /* Return true if regno1 def is nearest to the insn. */
18355 static bool
18357 {
18364 {
18366 {
18369 }
18375 }
18377 /* None of the regs is defined in the bb. */
18379 }
18381 /* Split lea instructions into a sequence of instructions
18382 which are executed on ALU to avoid AGU stalls.
18383 It is assumed that it is allowed to clobber flags register
18384 at lea position. */
18386 void
18388 {
18404 {
18407 }
18410 {
18413 }
18419 {
18420 /* Case r1 = r1 + ... */
18422 {
18423 /* If we have a case r1 = r1 + C * r2 then we
18424 should use multiplication which is very
18425 expensive. Assume cost model is wrong if we
18426 have such case here. */
18431 }
18432 else
18433 {
18434 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18438 /* Use shift for scaling. */
18447 }
18448 }
18450 {
18453 }
18454 else
18455 {
18457 {
18460 }
18462 {
18465 }
18466 else
18467 {
18472 else
18473 {
18474 rtx tmp1;
18476 /* Find better operand for SET instruction, depending
18477 on which definition is farther from the insn. */
18480 else
18490 }
18493 }
18497 }
18498 }
18500 /* Return true if it is ok to optimize an ADD operation to LEA
18501 operation to avoid flag register consumation. For most processors,
18502 ADD is faster than LEA. For the processors like BONNELL, if the
18503 destination register of LEA holds an actual address which will be
18504 used soon, LEA is better and otherwise ADD is better. */
18506 bool
18508 {
18513 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18521 }
18523 /* Return true if destination reg of SET_BODY is shift count of
18524 USE_BODY. */
18526 static bool
18528 {
18529 rtx set_dest;
18530 rtx shift_rtx;
18533 /* Retrieve destination of SET_BODY. */
18535 {
18544 use_body))
18549 }
18551 /* Retrieve shift count of USE_BODY. */
18553 {
18565 }
18573 {
18576 /* Return true if shift count is dest of SET_BODY. */
18578 {
18579 /* Add check since it can be invoked before register
18580 allocation in pre-reload schedule. */
18586 }
18587 }
18590 }
18592 /* Return true if destination reg of SET_INSN is shift count of
18593 USE_INSN. */
18595 bool
18597 {
18600 }
18602 /* Return TRUE or FALSE depending on whether the unary operator meets the
18603 appropriate constraints. */
18605 bool
18609 {
18610 /* If one of operands is memory, source and destination must match. */
18616 }
18618 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18619 are ok, keeping in mind the possible movddup alternative. */
18621 bool
18623 {
18629 }
18631 /* Post-reload splitter for converting an SF or DFmode value in an
18632 SSE register into an unsigned SImode. */
18634 void
18636 {
18647 /* Load up the value into the low element. We must ensure that the other
18648 elements are valid floats -- zero is the easiest such value. */
18650 {
18653 else
18655 }
18656 else
18657 {
18662 else
18664 }
18684 else
18689 }
18691 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18692 Expects the 64-bit DImode to be supplied in a pair of integral
18693 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18694 -mfpmath=sse, !optimize_size only. */
18696 void
18698 {
18702 rtx x;
18708 {
18711 }
18712 else
18713 {
18717 }
18725 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18728 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18729 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18730 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18731 (0x1.0p84 + double(fp_value_hi_xmm)).
18732 Note these exponents differ by 32. */
18736 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18737 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18746 /* Add the upper and lower DFmode values together. */
18749 else
18750 {
18754 }
18757 }
18759 /* Not used, but eases macroization of patterns. */
18760 void
18762 rtx input ATTRIBUTE_UNUSED)
18763 {
18765 }
18767 /* Convert an unsigned SImode value into a DFmode. Only currently used
18768 for SSE, but applicable anywhere. */
18770 void
18772 {
18773 REAL_VALUE_TYPE TWO31r;
18788 }
18790 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18791 32-bit mode; otherwise we have a direct convert instruction. */
18793 void
18795 {
18796 REAL_VALUE_TYPE TWO32r;
18814 }
18816 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18817 For x86_32, -mfpmath=sse, !optimize_size only. */
18818 void
18820 {
18821 REAL_VALUE_TYPE ONE16r;
18840 }
18842 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18843 a vector of unsigned ints VAL to vector of floats TARGET. */
18845 void
18847 {
18849 REAL_VALUE_TYPE TWO16r;
18855 {
18858 }
18860 {
18863 else
18866 }
18869 else
18874 OPTAB_DIRECT);
18885 OPTAB_DIRECT);
18887 OPTAB_DIRECT);
18890 }
18892 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18893 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18894 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18895 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18897 rtx
18899 {
18900 REAL_VALUE_TYPE TWO31r;
18915 {
18921 }
18930 OPTAB_DIRECT);
18931 else
18932 {
18938 OPTAB_DIRECT);
18939 }
18942 }
18944 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18945 then replicate the value for all elements of the vector
18946 register. */
18948 rtx
18950 {
18952 rtvec v;
18956 {
18989 }
18990 }
18992 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18993 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18994 for an SSE register. If VECT is true, then replicate the mask for
18995 all elements of the vector register. If INVERT is true, then create
18996 a mask excluding the sign bit. */
18998 rtx
19000 {
19004 rtx v;
19005 rtx mask;
19007 /* Find the sign bit, sign extended to 2*HWI. */
19009 {
19033 else
19041 {
19044 }
19045 else
19046 {
19047 rtvec vec;
19053 {
19056 }
19057 else
19067 }
19072 }
19077 /* Force this value into the low part of a fp vector constant. */
19086 }
19088 /* Generate code for floating point ABS or NEG. */
19090 void
19092 rtx operands[])
19093 {
19104 {
19110 }
19112 /* NEG and ABS performed with SSE use bitwise mask operations.
19113 Create the appropriate mask now. */
19116 else
19126 {
19128 rtvec par;
19133 else
19134 {
19137 }
19139 }
19140 else
19142 }
19144 /* Expand a copysign operation. Special case operand 0 being a constant. */
19146 void
19148 {
19162 else
19166 {
19173 {
19176 else
19177 {
19181 }
19182 }
19192 else
19196 }
19197 else
19198 {
19208 else
19212 }
19213 }
19215 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19216 be a constant, and so has already been expanded into a vector constant. */
19218 void
19220 {
19236 {
19239 }
19240 }
19242 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19243 so we have to do two masks. */
19245 void
19247 {
19262 {
19263 /* Shouldn't happen often (it's useless, obviously), but when it does
19264 we'd generate incorrect code if we continue below. */
19267 }
19270 {
19281 }
19282 else
19283 {
19285 {
19287 }
19289 {
19293 }
19297 {
19300 }
19302 {
19307 }
19309 }
19313 }
19315 /* Return TRUE or FALSE depending on whether the first SET in INSN
19316 has source and destination with matching CC modes, and that the
19317 CC mode is at least as constrained as REQ_MODE. */
19319 bool
19321 {
19322 rtx set;
19333 {
19343 /* FALLTHRU */
19347 /* FALLTHRU */
19351 /* FALLTHRU */
19365 }
19368 }
19370 /* Generate insn patterns to do an integer compare of OPERANDS. */
19372 static rtx
19374 {
19381 /* This is very simple, but making the interface the same as in the
19382 FP case makes the rest of the code easier. */
19386 /* Return the test that should be put into the flags user, i.e.
19387 the bcc, scc, or cmov instruction. */
19389 }
19391 /* Figure out whether to use ordered or unordered fp comparisons.
19392 Return the appropriate mode to use. */
19394 enum machine_mode
19396 {
19397 /* ??? In order to make all comparisons reversible, we do all comparisons
19398 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19399 all forms trapping and nontrapping comparisons, we can make inequality
19400 comparisons trapping again, since it results in better code when using
19401 FCOM based compares. */
19403 }
19405 enum machine_mode
19407 {
19411 {
19414 }
19417 {
19418 /* Only zero flag is needed. */
19422 /* Codes needing carry flag. */
19425 /* Detect overflow checks. They need just the carry flag. */
19429 else
19434 /* Codes possibly doable only with sign flag when
19435 comparing against zero. */
19440 else
19441 /* For other cases Carry flag is not required. */
19443 /* Codes doable only with sign flag when comparing
19444 against zero, but we miss jump instruction for it
19445 so we need to use relational tests against overflow
19446 that thus needs to be zero. */
19451 else
19453 /* strcmp pattern do (use flags) and combine may ask us for proper
19454 mode. */
19459 }
19460 }
19462 /* Return the fixed registers used for condition codes. */
19464 static bool
19466 {
19470 }
19472 /* If two condition code modes are compatible, return a condition code
19473 mode which is compatible with both. Otherwise, return
19474 VOIDmode. */
19476 static enum machine_mode
19478 {
19495 {
19509 {
19523 }
19527 /* These are only compatible with themselves, which we already
19528 checked above. */
19530 }
19531 }
19534 /* Return a comparison we can do and that it is equivalent to
19535 swap_condition (code) apart possibly from orderedness.
19536 But, never change orderedness if TARGET_IEEE_FP, returning
19537 UNKNOWN in that case if necessary. */
19539 static enum rtx_code
19541 {
19543 {
19554 }
19555 }
19557 /* Return cost of comparison CODE using the best strategy for performance.
19558 All following functions do use number of instructions as a cost metrics.
19559 In future this should be tweaked to compute bytes for optimize_size and
19560 take into account performance of various instructions on various CPUs. */
19562 static int
19564 {
19567 /* The cost of code using bit-twiddling on %ah. */
19569 {
19592 }
19595 {
19602 }
19603 }
19605 /* Return strategy to use for floating-point. We assume that fcomi is always
19606 preferrable where available, since that is also true when looking at size
19607 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19609 enum ix86_fpcmp_strategy
19611 {
19612 /* Do fcomi/sahf based test when profitable. */
19621 }
19623 /* Swap, force into registers, or otherwise massage the two operands
19624 to a fp comparison. The operands are updated in place; the new
19625 comparison code is returned. */
19627 static enum rtx_code
19629 {
19635 /* All of the unordered compare instructions only work on registers.
19636 The same is true of the fcomi compare instructions. The XFmode
19637 compare instructions require registers except when comparing
19638 against zero or when converting operand 1 from fixed point to
19639 floating point. */
19648 {
19651 }
19652 else
19653 {
19654 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19655 things around if they appear profitable, otherwise force op0
19656 into a register. */
19662 {
19665 {
19666 rtx tmp;
19669 }
19670 }
19676 {
19681 {
19684 }
19685 else
19687 }
19688 }
19690 /* Try to rearrange the comparison to make it cheaper. */
19694 {
19695 rtx tmp;
19700 }
19705 }
19707 /* Convert comparison codes we use to represent FP comparison to integer
19708 code that will result in proper branch. Return UNKNOWN if no such code
19709 is available. */
19711 enum rtx_code
19713 {
19715 {
19738 }
19739 }
19741 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19743 static rtx
19745 {
19752 /* Do fcomi/sahf based test when profitable. */
19754 {
19759 tmp);
19767 tmp);
19776 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19783 /* In the unordered case, we have to check C2 for NaN's, which
19784 doesn't happen to work out to anything nice combination-wise.
19785 So do some bit twiddling on the value we've got in AH to come
19786 up with an appropriate set of condition codes. */
19790 {
19794 {
19797 }
19798 else
19799 {
19805 }
19810 {
19815 }
19816 else
19817 {
19820 }
19825 {
19828 }
19829 else
19830 {
19834 }
19839 {
19845 }
19846 else
19847 {
19850 }
19855 {
19860 }
19861 else
19862 {
19865 }
19870 {
19875 }
19876 else
19877 {
19880 }
19894 }
19899 }
19901 /* Return the test that should be put into the flags user, i.e.
19902 the bcc, scc, or cmov instruction. */
19905 const0_rtx);
19906 }
19908 static rtx
19910 {
19911 rtx ret;
19917 {
19920 }
19921 else
19925 }
19927 void
19929 {
19931 rtx tmp;
19934 {
19941 simple:
19945 pc_rtx);
19953 /* Expand DImode branch into multiple compare+branch. */
19954 {
19960 {
19963 }
19970 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19971 avoid two branches. This costs one extra insn, so disable when
19972 optimizing for size. */
19977 {
19995 }
19997 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19998 op1 is a constant and the low word is zero, then we can just
19999 examine the high word. Similarly for low word -1 and
20000 less-or-equal-than or greater-than. */
20004 {
20007 {
20010 }
20014 {
20017 }
20021 }
20023 /* Otherwise, we need two or three jumps. */
20032 {
20046 }
20048 /*
20049 * a < b =>
20050 * if (hi(a) < hi(b)) goto true;
20051 * if (hi(a) > hi(b)) goto false;
20052 * if (lo(a) < lo(b)) goto true;
20053 * false:
20054 */
20066 }
20071 }
20072 }
20074 /* Split branch based on floating point condition. */
20075 void
20078 {
20079 rtx condition;
20080 rtx i;
20083 {
20088 }
20091 tmp);
20099 }
20101 void
20103 {
20104 rtx ret;
20111 }
20113 /* Expand comparison setting or clearing carry flag. Return true when
20114 successful and set pop for the operation. */
20115 static bool
20117 {
20121 /* Do not handle double-mode compares that go through special path. */
20126 {
20131 /* Shortcut: following common codes never translate
20132 into carry flag compares. */
20137 /* These comparisons require zero flag; swap operands so they won't. */
20140 {
20145 }
20147 /* Try to expand the comparison and verify that we end up with
20148 carry flag based comparison. This fails to be true only when
20149 we decide to expand comparison using arithmetic that is not
20150 too common scenario. */
20159 else
20168 }
20174 {
20179 /* Convert a==0 into (unsigned)a<1. */
20188 /* Convert a>b into b<a or a>=b-1. */
20192 {
20194 /* Bail out on overflow. We still can swap operands but that
20195 would force loading of the constant into register. */
20200 }
20201 else
20202 {
20207 }
20210 /* Convert a>=0 into (unsigned)a<0x80000000. */
20228 }
20229 /* Swapping operands may cause constant to appear as first operand. */
20231 {
20235 }
20239 }
20241 bool
20243 {
20267 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20268 HImode insns, we'd be swallowed in word prefix ops. */
20274 {
20278 HOST_WIDE_INT diff;
20281 /* Sign bit compares are better done using shifts than we do by using
20282 sbb. */
20285 {
20286 /* Detect overlap between destination and compare sources. */
20290 {
20291 rtx flags;
20300 {
20302 compare_code
20304 }
20306 /* To simplify rest of code, restrict to the GEU case. */
20308 {
20314 }
20315 else
20316 {
20319 reverse_condition_maybe_unordered
20321 else
20324 }
20333 else
20336 }
20337 else
20338 {
20341 else
20342 {
20347 }
20349 }
20352 {
20353 /*
20354 * cmpl op0,op1
20355 * sbbl dest,dest
20356 * [addl dest, ct]
20357 *
20358 * Size 5 - 8.
20359 */
20364 }
20366 {
20367 /*
20368 * cmpl op0,op1
20369 * sbbl dest,dest
20370 * orl $ct, dest
20371 *
20372 * Size 8.
20373 */
20377 }
20379 {
20380 /*
20381 * cmpl op0,op1
20382 * sbbl dest,dest
20383 * notl dest
20384 * [addl dest, cf]
20385 *
20386 * Size 8 - 11.
20387 */
20393 }
20394 else
20395 {
20396 /*
20397 * cmpl op0,op1
20398 * sbbl dest,dest
20399 * [notl dest]
20400 * andl cf - ct, dest
20401 * [addl dest, ct]
20402 *
20403 * Size 8 - 11.
20404 */
20407 {
20411 }
20421 }
20427 }
20430 {
20433 HOST_WIDE_INT tmp;
20438 {
20441 /* We may be reversing unordered compare to normal compare, that
20442 is not valid in general (we may convert non-trapping condition
20443 to trapping one), however on i386 we currently emit all
20444 comparisons unordered. */
20447 }
20448 else
20449 {
20452 }
20453 }
20458 {
20463 {
20468 }
20469 }
20471 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20475 {
20476 /* If lea code below could be used, only optimize
20477 if it results in a 2 insn sequence. */
20483 {
20484 /*
20485 * notl op1 (if necessary)
20486 * sarl $31, op1
20487 * orl cf, op1
20488 */
20490 {
20494 }
20505 }
20506 }
20514 {
20515 /*
20516 * xorl dest,dest
20517 * cmpl op1,op2
20518 * setcc dest
20519 * lea cf(dest*(ct-cf)),dest
20520 *
20521 * Size 14.
20522 *
20523 * This also catches the degenerate setcc-only case.
20524 */
20526 rtx tmp;
20532 /* On x86_64 the lea instruction operates on Pmode, so we need
20533 to get arithmetics done in proper mode to match. */
20536 else
20537 {
20538 rtx out1;
20541 nops++;
20543 {
20545 nops++;
20546 }
20547 }
20549 {
20551 nops++;
20552 }
20554 {
20557 else
20559 }
20564 }
20566 /*
20567 * General case: Jumpful:
20568 * xorl dest,dest cmpl op1, op2
20569 * cmpl op1, op2 movl ct, dest
20570 * setcc dest jcc 1f
20571 * decl dest movl cf, dest
20572 * andl (cf-ct),dest 1:
20573 * addl ct,dest
20574 *
20575 * Size 20. Size 14.
20576 *
20577 * This is reasonably steep, but branch mispredict costs are
20578 * high on modern cpus, so consider failing only if optimizing
20579 * for space.
20580 */
20585 {
20587 {
20594 {
20597 /* We may be reversing unordered compare to normal compare,
20598 that is not valid in general (we may convert non-trapping
20599 condition to trapping one), however on i386 we currently
20600 emit all comparisons unordered. */
20602 }
20603 else
20604 {
20608 }
20609 }
20612 {
20613 /* notl op1 (if needed)
20614 sarl $31, op1
20615 andl (cf-ct), op1
20616 addl ct, op1
20618 For x < 0 (resp. x <= -1) there will be no notl,
20619 so if possible swap the constants to get rid of the
20620 complement.
20621 True/false will be -1/0 while code below (store flag
20622 followed by decrement) is 0/-1, so the constants need
20623 to be exchanged once more. */
20626 {
20629 }
20630 else
20631 {
20635 }
20638 }
20639 else
20640 {
20644 constm1_rtx,
20646 }
20658 }
20659 }
20662 {
20663 /* Try a few things more with specific constants and a variable. */
20665 optab op;
20671 /* If one of the two operands is an interesting constant, load a
20672 constant with the above and mask it in with a logical operation. */
20675 {
20681 else
20683 }
20685 {
20691 else
20693 }
20694 else
20701 /* Recurse to get the constant loaded. */
20705 /* Mask in the interesting variable. */
20707 OPTAB_WIDEN);
20712 }
20714 /*
20715 * For comparison with above,
20716 *
20717 * movl cf,dest
20718 * movl ct,tmp
20719 * cmpl op1,op2
20720 * cmovcc tmp,dest
20721 *
20722 * Size 15.
20723 */
20745 }
20747 /* Swap, force into registers, or otherwise massage the two operands
20748 to an sse comparison with a mask result. Thus we differ a bit from
20749 ix86_prepare_fp_compare_args which expects to produce a flags result.
20751 The DEST operand exists to help determine whether to commute commutative
20752 operators. The POP0/POP1 operands are updated in place. The new
20753 comparison code is returned, or UNKNOWN if not implementable. */
20755 static enum rtx_code
20758 {
20759 rtx tmp;
20762 {
20765 /* AVX supports all the needed comparisons. */
20768 /* We have no LTGT as an operator. We could implement it with
20769 NE & ORDERED, but this requires an extra temporary. It's
20770 not clear that it's worth it. */
20777 /* These are supported directly. */
20784 /* AVX has 3 operand comparisons, no need to swap anything. */
20787 /* For commutative operators, try to canonicalize the destination
20788 operand to be first in the comparison - this helps reload to
20789 avoid extra moves. */
20792 /* FALLTHRU */
20798 /* These are not supported directly before AVX, and furthermore
20799 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20800 comparison operands to transform into something that is
20801 supported. */
20810 }
20813 }
20815 /* Detect conditional moves that exactly match min/max operational
20816 semantics. Note that this is IEEE safe, as long as we don't
20817 interchange the operands.
20819 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20820 and TRUE if the operation is successful and instructions are emitted. */
20822 static bool
20825 {
20828 rtx tmp;
20831 ;
20833 {
20837 }
20838 else
20845 else
20850 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20851 but MODE may be a vector mode and thus not appropriate. */
20853 {
20855 rtvec v;
20860 }
20861 else
20862 {
20865 }
20869 }
20871 /* Expand an sse vector comparison. Return the register with the result. */
20873 static rtx
20876 {
20880 /* In general case result of comparison can differ from operands' type. */
20883 /* In AVX512F the result of comparison is an integer mask. */
20885 rtx x;
20888 {
20893 }
20894 else
20907 /* Compare patterns for int modes are unspec in AVX512F only. */
20909 {
20913 {
20922 }
20925 {
20928 }
20929 }
20933 {
20936 }
20937 else
20941 }
20943 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20944 operations. This is used for both scalar and vector conditional moves. */
20946 static void
20948 {
20952 /* In AVX512F the result of comparison is an integer mask. */
20960 {
20962 }
20965 {
20969 }
20972 {
20977 }
20980 {
20984 }
20987 {
20995 op_true,
20996 op_false)));
20997 }
20998 else
20999 {
21009 {
21023 {
21030 }
21045 {
21052 }
21076 }
21079 {
21083 }
21084 else
21085 {
21091 else
21103 }
21104 }
21105 }
21107 /* Expand a floating-point conditional move. Return true if successful. */
21109 bool
21111 {
21119 {
21122 /* Since we've no cmove for sse registers, don't force bad register
21123 allocation just to gain access to it. Deny movcc when the
21124 comparison mode doesn't match the move mode. */
21143 }
21150 /* The floating point conditional move instructions don't directly
21151 support conditions resulting from a signed integer comparison. */
21155 {
21160 }
21167 }
21169 /* Expand a floating-point vector conditional move; a vcond operation
21170 rather than a movcc operation. */
21172 bool
21174 {
21176 rtx cmp;
21181 {
21182 rtx temp;
21184 {
21201 }
21203 OPTAB_DIRECT);
21206 }
21216 }
21218 /* Expand a signed/unsigned integral vector conditional move. */
21220 bool
21222 {
21232 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21233 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21242 {
21246 {
21252 }
21255 {
21261 }
21262 }
21271 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21275 ;
21276 else
21277 {
21278 /* Canonicalize the comparison to EQ, GT, GTU. */
21280 {
21297 /* FALLTHRU */
21307 }
21309 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21311 {
21313 {
21315 /* SSE4.1 supports EQ. */
21322 /* SSE4.2 supports GT/GTU. */
21329 }
21330 }
21332 /* Unsigned parallel compare is not supported by the hardware.
21333 Play some tricks to turn this into a signed comparison
21334 against 0. */
21336 {
21340 {
21347 {
21352 {
21361 }
21362 /* Subtract (-(INT MAX) - 1) from both operands to make
21363 them signed. */
21374 }
21383 /* Perform a parallel unsigned saturating subtraction. */
21396 }
21397 }
21398 }
21400 /* Allow the comparison to be done in one mode, but the movcc to
21401 happen in another mode. */
21403 {
21406 }
21407 else
21408 {
21414 }
21419 }
21421 static bool
21423 {
21426 {
21427 /* There is no byte version of vpermi2. So we use vpermi2w. */
21487 op1));
21504 op1));
21540 }
21541 }
21543 /* Expand a variable vector permutation. */
21545 void
21547 {
21558 /* Number of elements in the vector. */
21567 {
21569 {
21570 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21571 an constant shuffle operand. With a tiny bit of effort we can
21572 use VPERMD instead. A re-interpretation stall for V4DFmode is
21573 unfortunate but there's no avoiding it.
21574 Similarly for V16HImode we don't have instructions for variable
21575 shuffling, while for V32QImode we can use after preparing suitable
21576 masks vpshufb; vpshufb; vpermq; vpor. */
21579 {
21583 }
21584 else
21585 {
21589 }
21592 /* Replicate the low bits of the V4DImode mask into V8SImode:
21593 mask = { A B C D }
21594 t1 = { A A B B C C D D }. */
21602 else
21605 /* Multiply the shuffle indicies by two. */
21607 OPTAB_DIRECT);
21609 /* Add one to the odd shuffle indicies:
21610 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21612 {
21615 }
21619 OPTAB_DIRECT);
21621 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21626 }
21629 {
21631 /* The VPERMD and VPERMPS instructions already properly ignore
21632 the high bits of the shuffle elements. No need for us to
21633 perform an AND ourselves. */
21635 {
21640 }
21641 else
21642 {
21648 }
21655 else
21656 {
21662 }
21666 /* By combining the two 128-bit input vectors into one 256-bit
21667 input vector, we can use VPERMD and VPERMPS for the full
21668 two-operand shuffle. */
21700 /* From mask create two adjusted masks, which contain the same
21701 bits as mask in the low 7 bits of each vector element.
21702 The first mask will have the most significant bit clear
21703 if it requests element from the same 128-bit lane
21704 and MSB set if it requests element from the other 128-bit lane.
21705 The second mask will have the opposite values of the MSB,
21706 and additionally will have its 128-bit lanes swapped.
21707 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21708 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21709 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21710 stands for other 12 bytes. */
21711 /* The bit whether element is from the same lane or the other
21712 lane is bit 4, so shift it up by 3 to the MSB position. */
21716 /* Clear MSB bits from the mask just in case it had them set. */
21718 /* After this t1 will have MSB set for elements from other lane. */
21720 /* Clear bits other than MSB. */
21722 /* Or in the lower bits from mask into t3. */
21724 /* And invert MSB bits in t1, so MSB is set for elements from the same
21725 lane. */
21727 /* Swap 128-bit lanes in t3. */
21732 /* And or in the lower bits from mask into t1. */
21735 {
21736 /* Each of these shuffles will put 0s in places where
21737 element from the other 128-bit lane is needed, otherwise
21738 will shuffle in the requested value. */
21742 /* For t3 the 128-bit lanes are swapped again. */
21747 /* And oring both together leads to the result. */
21754 }
21757 /* Similarly to the above one_operand_shuffle code,
21758 just for repeated twice for each operand. merge_two:
21759 code will merge the two results together. */
21783 }
21784 }
21787 {
21788 /* The XOP VPPERM insn supports three inputs. By ignoring the
21789 one_operand_shuffle special case, we avoid creating another
21790 set of constant vectors in memory. */
21793 /* mask = mask & {2*w-1, ...} */
21795 }
21796 else
21797 {
21798 /* mask = mask & {w-1, ...} */
21800 }
21808 /* For non-QImode operations, convert the word permutation control
21809 into a byte permutation control. */
21811 {
21816 /* Convert mask to vector of chars. */
21819 /* Replicate each of the input bytes into byte positions:
21820 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21821 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21822 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21829 else
21832 /* Convert it into the byte positions by doing
21833 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21839 }
21841 /* The actual shuffle operations all operate on V16QImode. */
21846 {
21853 }
21855 {
21862 }
21863 else
21864 {
21868 /* Shuffle the two input vectors independently. */
21874 merge_two:
21875 /* Then merge them together. The key is whether any given control
21876 element contained a bit set that indicates the second word. */
21880 {
21881 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21882 more shuffle to convert the V2DI input mask into a V4SI
21883 input mask. At which point the masking that expand_int_vcond
21884 will work as desired. */
21892 }
21914 }
21915 }
21917 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21918 true if we should do zero extension, else sign extension. HIGH_P is
21919 true if we want the N/2 high elements, else the low elements. */
21921 void
21923 {
21925 rtx tmp;
21928 {
21934 {
21938 else
21941 extract
21947 else
21950 extract
21956 else
21959 extract
21965 else
21968 extract
21974 else
21977 extract
21983 else
21986 extract
21992 else
21998 else
22004 else
22009 }
22012 {
22015 }
22017 {
22018 /* Shift higher 8 bytes to lower 8 bytes. */
22023 }
22024 else
22028 }
22029 else
22030 {
22034 {
22038 else
22044 else
22050 else
22055 }
22059 else
22066 }
22067 }
22069 /* Expand conditional increment or decrement using adb/sbb instructions.
22070 The default case using setcc followed by the conditional move can be
22071 done by generic code. */
22072 bool
22074 {
22076 rtx flags;
22078 rtx compare_op;
22096 {
22099 }
22102 {
22106 reverse_condition_maybe_unordered
22108 else
22110 }
22114 /* Construct either adc or sbb insn. */
22116 {
22118 {
22133 }
22134 }
22135 else
22136 {
22138 {
22153 }
22154 }
22158 }
22161 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22162 but works for floating pointer parameters and nonoffsetable memories.
22163 For pushes, it returns just stack offsets; the values will be saved
22164 in the right order. Maximally three parts are generated. */
22166 static int
22168 {
22173 else
22179 /* Optimize constant pool reference to immediates. This is used by fp
22180 moves, that force all constants to memory to allow combining. */
22182 {
22186 }
22189 {
22190 /* The only non-offsetable memories we handle are pushes. */
22199 }
22202 {
22204 /* Caution: if we looked through a constant pool memory above,
22205 the operand may actually have a different mode now. That's
22206 ok, since we want to pun this all the way back to an integer. */
22210 }
22213 {
22216 else
22217 {
22221 {
22225 }
22227 {
22232 }
22234 {
22235 REAL_VALUE_TYPE r;
22240 {
22247 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22248 long double may not be 80-bit. */
22257 }
22260 }
22261 else
22263 }
22264 }
22265 else
22266 {
22270 {
22273 {
22277 }
22279 {
22283 }
22285 {
22286 REAL_VALUE_TYPE r;
22292 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22295 = gen_int_mode
22298 DImode);
22299 else
22306 = gen_int_mode
22309 DImode);
22310 else
22312 }
22313 else
22315 }
22316 }
22319 }
22321 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22322 Return false when normal moves are needed; true when all required
22323 insns have been emitted. Operands 2-4 contain the input values
22324 int the correct order; operands 5-7 contain the output values. */
22326 void
22328 {
22336 /* The DFmode expanders may ask us to move double.
22337 For 64bit target this is single move. By hiding the fact
22338 here we simplify i386.md splitters. */
22340 {
22341 /* Optimize constant pool reference to immediates. This is used by
22342 fp moves, that force all constants to memory to allow combining. */
22349 {
22352 }
22353 else
22358 }
22360 /* The only non-offsettable memory we handle is push. */
22363 else
22370 /* When emitting push, take care for source operands on the stack. */
22373 {
22376 /* Compensate for the stack decrement by 4. */
22381 /* src_base refers to the stack pointer and is
22382 automatically decreased by emitted push. */
22386 }
22388 /* We need to do copy in the right order in case an address register
22389 of the source overlaps the destination. */
22391 {
22392 rtx tmp;
22395 {
22399 collisions++;
22400 }
22402 /* Collision in the middle part can be handled by reordering. */
22404 {
22407 }
22411 {
22413 {
22416 }
22417 else
22418 {
22421 }
22422 }
22424 /* If there are more collisions, we can't handle it by reordering.
22425 Do an lea to the last part and use only one colliding move. */
22427 {
22428 rtx base;
22434 /* Handle the case when the last part isn't valid for lea.
22435 Happens in 64-bit mode storing the 12-byte XFmode. */
22442 {
22445 }
22446 }
22447 }
22450 {
22452 {
22454 {
22459 }
22461 {
22464 }
22465 }
22466 else
22467 {
22468 /* In 64bit mode we don't have 32bit push available. In case this is
22469 register, it is OK - we will just use larger counterpart. We also
22470 retype memory - these comes from attempt to avoid REX prefix on
22471 moving of second half of TFmode value. */
22473 {
22475 {
22486 }
22490 }
22491 }
22495 }
22497 /* Choose correct order to not overwrite the source before it is copied. */
22507 {
22509 {
22512 }
22513 }
22514 else
22515 {
22517 {
22520 }
22521 }
22523 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22525 {
22534 }
22540 }
22542 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22543 left shift by a constant, either using a single shift or
22544 a sequence of add instructions. */
22546 static void
22548 {
22554 {
22558 }
22559 else
22560 {
22563 }
22564 }
22566 void
22568 {
22577 {
22582 {
22588 }
22589 else
22590 {
22598 }
22600 }
22607 {
22608 /* Assuming we've chosen a QImode capable registers, then 1 << N
22609 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22611 {
22627 }
22629 /* Otherwise, we can get the same results by manually performing
22630 a bit extract operation on bit 5/6, and then performing the two
22631 shifts. The two methods of getting 0/1 into low/high are exactly
22632 the same size. Avoiding the shift in the bit extract case helps
22633 pentium4 a bit; no one else seems to care much either way. */
22634 else
22635 {
22640 HOST_WIDE_INT bits;
22641 rtx x;
22644 {
22650 }
22651 else
22652 {
22658 }
22662 else
22670 }
22675 }
22678 {
22679 /* For -1 << N, we can avoid the shld instruction, because we
22680 know that we're shifting 0...31/63 ones into a -1. */
22684 else
22686 }
22687 else
22688 {
22696 }
22701 {
22707 }
22708 else
22709 {
22714 }
22715 }
22717 void
22719 {
22729 {
22734 {
22740 }
22742 {
22751 }
22752 else
22753 {
22761 }
22762 }
22763 else
22764 {
22776 {
22784 scratch));
22785 }
22786 else
22787 {
22792 }
22793 }
22794 }
22796 void
22798 {
22808 {
22813 {
22820 }
22821 else
22822 {
22830 }
22831 }
22832 else
22833 {
22845 {
22851 scratch));
22852 }
22853 else
22854 {
22859 }
22860 }
22861 }
22863 /* Predict just emitted jump instruction to be taken with probability PROB. */
22864 static void
22866 {
22870 }
22872 /* Helper function for the string operations below. Dest VARIABLE whether
22873 it is aligned to VALUE bytes. If true, jump to the label. */
22874 static rtx
22876 {
22881 else
22887 else
22890 }
22892 /* Adjust COUNTER by the VALUE. */
22893 static void
22895 {
22900 }
22902 /* Zero extend possibly SImode EXP to Pmode register. */
22903 rtx
22905 {
22907 }
22909 /* Divide COUNTREG by SCALE. */
22910 static rtx
22912 {
22913 rtx sc;
22925 }
22927 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22928 DImode for constant loop counts. */
22930 static enum machine_mode
22932 {
22940 }
22942 /* Copy the address to a Pmode register. This is used for x32 to
22943 truncate DImode TLS address to a SImode register. */
22945 static rtx
22947 {
22950 else
22951 {
22954 }
22955 }
22957 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
22958 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
22959 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
22960 memory by VALUE (supposed to be in MODE).
22962 The size is rounded down to whole number of chunk size moved at once.
22963 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22966 static void
22971 {
22977 rtx size;
22986 /* Those two should combine. */
22988 {
22992 }
22999 /* This assert could be relaxed - in this case we'll need to compute
23000 smallest power of two, containing in PIECE_SIZE_N and pass it to
23001 offset_address. */
23007 {
23011 /* When unrolling for chips that reorder memory reads and writes,
23012 we can save registers by using single temporary.
23013 Also using 4 temporaries is overkill in 32bit mode. */
23015 {
23017 {
23019 {
23020 destmem =
23022 srcmem =
23024 }
23026 }
23027 }
23028 else
23029 {
23033 {
23036 {
23037 srcmem =
23039 }
23041 }
23043 {
23045 {
23046 destmem =
23048 }
23050 }
23051 }
23052 }
23053 else
23055 {
23057 destmem =
23060 }
23070 {
23076 else
23078 }
23079 else
23087 {
23092 }
23094 }
23096 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23097 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23098 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23099 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23100 ORIG_VALUE is the original value passed to memset to fill the memory with.
23101 Other arguments have same meaning as for previous function. */
23103 static void
23106 rtx count,
23108 {
23109 rtx destexp;
23110 rtx srcexp;
23111 rtx countreg;
23112 HOST_WIDE_INT rounded_count;
23114 /* If possible, it is shorter to use rep movs.
23115 TODO: Maybe it is better to move this logic to decide_alg. */
23126 {
23130 }
23131 else
23134 {
23139 }
23144 {
23147 }
23148 else
23149 {
23153 {
23157 }
23158 else
23161 {
23166 }
23167 else
23168 {
23171 }
23174 }
23175 }
23177 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23178 DESTMEM.
23179 SRC is passed by pointer to be updated on return.
23180 Return value is updated DST. */
23181 static rtx
23183 HOST_WIDE_INT size_to_move)
23184 {
23190 /* Find the widest mode in which we could perform moves.
23191 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23192 it until move of such size is supported. */
23197 {
23201 }
23203 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23204 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23206 {
23211 {
23215 }
23216 }
23222 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23226 {
23227 /* We move from memory to memory, so we'll need to do it via
23228 a temporary register. */
23239 piece_size);
23241 piece_size);
23242 }
23244 /* Update DST and SRC rtx. */
23247 }
23249 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23250 static void
23253 {
23256 {
23261 /* For now MAX_SIZE should be a power of 2. This assert could be
23262 relaxed, but it'll require a bit more complicated epilogue
23263 expanding. */
23266 {
23269 }
23271 }
23273 {
23279 }
23281 /* When there are stringops, we can cheaply increase dest and src pointers.
23282 Otherwise we save code size by maintaining offset (zero is readily
23283 available from preceding rep operation) and using x86 addressing modes.
23284 */
23286 {
23288 {
23295 }
23297 {
23304 }
23306 {
23313 }
23314 }
23315 else
23316 {
23318 rtx tmp;
23321 {
23332 }
23334 {
23347 }
23349 {
23358 }
23359 }
23360 }
23362 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23363 with value PROMOTED_VAL.
23364 SRC is passed by pointer to be updated on return.
23365 Return value is updated DST. */
23366 static rtx
23368 HOST_WIDE_INT size_to_move)
23369 {
23375 /* Find the widest mode in which we could perform moves.
23376 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23377 it until move of such size is supported. */
23382 {
23385 }
23392 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23396 {
23398 {
23401 piece_size);
23403 }
23411 piece_size);
23412 }
23414 /* Update DST rtx. */
23416 }
23417 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23418 static void
23421 {
23422 count =
23428 }
23430 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23431 static void
23434 {
23435 rtx dest;
23438 {
23443 /* For now MAX_SIZE should be a power of 2. This assert could be
23444 relaxed, but it'll require a bit more complicated epilogue
23445 expanding. */
23448 {
23450 {
23453 else
23455 }
23456 }
23458 }
23460 {
23463 }
23465 {
23468 {
23473 }
23474 else
23475 {
23484 }
23487 }
23489 {
23492 {
23495 }
23496 else
23497 {
23502 }
23505 }
23507 {
23513 }
23515 {
23521 }
23523 {
23529 }
23530 }
23532 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23533 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23534 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23535 ignored.
23536 Return value is updated DESTMEM. */
23537 static rtx
23542 {
23545 {
23547 {
23550 {
23553 else
23555 }
23556 else
23562 }
23563 }
23565 }
23567 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23568 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23569 and jump to DONE_LABEL. */
23570 static void
23576 {
23579 rtx modesize;
23582 /* If we do not have vector value to copy, we must reduce size. */
23584 {
23586 {
23591 }
23592 else
23594 }
23595 else
23596 {
23597 /* Choose appropriate vector mode. */
23603 }
23608 {
23611 else
23612 {
23615 }
23617 }
23623 {
23627 }
23629 {
23632 else
23633 {
23636 }
23638 }
23644 }
23646 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23647 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23648 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23649 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23650 DONE_LABEL is a label after the whole copying sequence. The label is created
23651 on demand if *DONE_LABEL is NULL.
23652 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23653 bounds after the initial copies.
23655 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23656 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23657 we will dispatch to a library call for large blocks.
23659 In pseudocode we do:
23661 if (COUNT < SIZE)
23662 {
23663 Assume that SIZE is 4. Bigger sizes are handled analogously
23664 if (COUNT & 4)
23665 {
23666 copy 4 bytes from SRCPTR to DESTPTR
23667 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23668 goto done_label
23669 }
23670 if (!COUNT)
23671 goto done_label;
23672 copy 1 byte from SRCPTR to DESTPTR
23673 if (COUNT & 2)
23674 {
23675 copy 2 bytes from SRCPTR to DESTPTR
23676 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23677 }
23678 }
23679 else
23680 {
23681 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23682 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23684 OLD_DESPTR = DESTPTR;
23685 Align DESTPTR up to DESIRED_ALIGN
23686 SRCPTR += DESTPTR - OLD_DESTPTR
23687 COUNT -= DEST_PTR - OLD_DESTPTR
23688 if (DYNAMIC_CHECK)
23689 Round COUNT down to multiple of SIZE
23690 << optional caller supplied zero size guard is here >>
23691 << optional caller suppplied dynamic check is here >>
23692 << caller supplied main copy loop is here >>
23693 }
23694 done_label:
23695 */
23696 static void
23709 {
23712 rtx modesize;
23714 rtx mode_value;
23716 /* Chose proper value to copy. */
23719 else
23723 /* See if block is big or small, handle small blocks. */
23725 {
23736 /* Handle sizes > 3. */
23743 /* Nothing to copy? Jump to DONE_LABEL if so */
23747 /* Do a byte copy. */
23751 else
23752 {
23755 }
23757 /* Handle sizes 2 and 3. */
23764 else
23765 {
23770 }
23776 }
23777 else
23781 /* Start memcpy for COUNT >= SIZE. */
23783 {
23786 }
23788 /* Copy first desired_align bytes. */
23794 {
23797 else
23798 {
23801 }
23804 }
23807 /* Copy last SIZE bytes. */
23814 else
23815 {
23821 }
23823 {
23827 else
23828 {
23831 }
23832 }
23834 /* Align destination. */
23836 {
23840 /* Align destptr up, place it to new register. */
23847 /* See how many bytes we skipped. */
23851 /* Adjust srcptr and count. */
23857 /* We copied at most size + prolog_size. */
23860 else
23863 /* Our loops always round down the bock size, but for dispatch to library
23864 we need precise value. */
23868 }
23869 else
23870 {
23872 /* Decrease count, so we won't end up copying last word twice. */
23876 else
23880 }
23881 }
23884 /* This function is like the previous one, except here we know how many bytes
23885 need to be copied. That allows us to update alignment not only of DST, which
23886 is returned, but also of SRC, which is passed as a pointer for that
23887 reason. */
23888 static rtx
23893 {
23901 {
23905 }
23910 {
23912 {
23914 {
23917 else
23919 }
23920 else
23923 }
23924 }
23931 {
23937 {
23940 {
23944 }
23949 }
23953 }
23956 }
23958 /* Return true if ALG can be used in current context.
23959 Assume we expand memset if MEMSET is true. */
23960 static bool
23962 {
23967 /* Algorithms using the rep prefix want at least edi and ecx;
23968 additionally, memset wants eax and memcpy wants esi. Don't
23969 consider such algorithms if the user has appropriated those
23970 registers for their own purposes. */
23977 }
23979 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
23980 static enum stringop_alg
23984 {
23995 /* Even if the string operation call is cold, we still might spend a lot
23996 of time processing large blocks. */
24002 else
24008 else
24011 /* See maximal size for user defined algorithm. */
24013 {
24020 }
24022 /* If expected size is not known but max size is small enough
24023 so inline version is a win, set expected size into
24024 the range. */
24029 /* If user specified the algorithm, honnor it if possible. */
24033 /* rep; movq or rep; movl is the smallest variant. */
24035 {
24040 else
24043 }
24044 /* Very tiny blocks are best handled via the loop, REP is expensive to
24045 setup. */
24049 {
24053 {
24054 /* We get here if the algorithms that were not libcall-based
24055 were rep-prefix based and we are unable to use rep prefixes
24056 based on global register usage. Break out of the loop and
24057 use the heuristic below. */
24061 {
24065 {
24068 }
24069 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24070 last non-libcall inline algorithm. */
24072 {
24073 /* When the current size is best to be copied by a libcall,
24074 but we are still forced to inline, run the heuristic below
24075 that will pick code for medium sized blocks. */
24077 {
24080 }
24082 }
24084 {
24087 }
24088 }
24089 }
24090 }
24091 /* When asked to inline the call anyway, try to pick meaningful choice.
24092 We look for maximal size of block that is faster to copy by hand and
24093 take blocks of at most of that size guessing that average size will
24094 be roughly half of the block.
24096 If this turns out to be bad, we might simply specify the preferred
24097 choice in ix86_costs. */
24101 {
24104 /* If there aren't any usable algorithms, then recursing on
24105 smaller sizes isn't going to find anything. Just return the
24106 simple byte-at-a-time copy loop. */
24108 {
24109 /* Pick something reasonable. */
24113 }
24123 }
24126 }
24128 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24129 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24130 static int
24135 {
24146 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24147 copying whole cacheline at once. */
24160 }
24163 /* Helper function for memcpy. For QImode value 0xXY produce
24164 0xXYXYXYXY of wide specified by MODE. This is essentially
24165 a * 0x10101010, but we can do slightly better than
24166 synth_mult by unwinding the sequence by hand on CPUs with
24167 slow multiply. */
24168 static rtx
24170 {
24172 rtx tmp;
24179 {
24187 }
24196 nops--;
24201 {
24205 OPTAB_DIRECT);
24206 }
24207 else
24208 {
24214 else
24216 else
24217 {
24220 reg =
24222 }
24232 }
24233 }
24235 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24236 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24237 alignment from ALIGN to DESIRED_ALIGN. */
24238 static rtx
24241 {
24242 rtx promoted_val;
24251 else
24255 }
24257 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24258 operations when profitable. The code depends upon architecture, block size
24259 and alignment, but always has one of the following overall structures:
24261 Aligned move sequence:
24263 1) Prologue guard: Conditional that jumps up to epilogues for small
24264 blocks that can be handled by epilogue alone. This is faster
24265 but also needed for correctness, since prologue assume the block
24266 is larger than the desired alignment.
24268 Optional dynamic check for size and libcall for large
24269 blocks is emitted here too, with -minline-stringops-dynamically.
24271 2) Prologue: copy first few bytes in order to get destination
24272 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24273 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24274 copied. We emit either a jump tree on power of two sized
24275 blocks, or a byte loop.
24277 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24278 with specified algorithm.
24280 4) Epilogue: code copying tail of the block that is too small to be
24281 handled by main body (or up to size guarded by prologue guard).
24283 Misaligned move sequence
24285 1) missaligned move prologue/epilogue containing:
24286 a) Prologue handling small memory blocks and jumping to done_label
24287 (skipped if blocks are known to be large enough)
24288 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24289 needed by single possibly misaligned move
24290 (skipped if alignment is not needed)
24291 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24293 2) Zero size guard dispatching to done_label, if needed
24295 3) dispatch to library call, if needed,
24297 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24298 with specified algorithm. */
24299 bool
24305 {
24306 rtx destreg;
24309 rtx tmp;
24325 /* TODO: Once value ranges are available, fill in proper data. */
24333 /* i386 can do misaligned access on reasonably increased cost. */
24337 /* ALIGN is the minimum of destination and source alignment, but we care here
24338 just about destination alignment. */
24344 {
24347 /* When COUNT is 0, there is nothing to do. */
24350 }
24351 else
24352 {
24361 }
24363 /* Make sure we don't need to care about overflow later on. */
24367 /* Step 0: Decide on preferred algorithm, desired alignment and
24368 size of chunks to be copied by main loop. */
24370 issetmem,
24377 /* For now vector-version of memset is generated only for memory zeroing, as
24378 creating of promoted vector value is very cheap in this case. */
24391 {
24410 /* Find the widest supported mode. */
24416 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24417 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24419 {
24424 }
24436 }
24444 /* Step 1: Prologue guard. */
24446 /* Alignment code needs count to be in register. */
24448 {
24451 {
24452 align_bytes
24456 else
24458 }
24461 }
24464 /* Misaligned move sequences handle both prologue and epilogue at once.
24465 Default code generation results in a smaller code for large alignments
24466 and also avoids redundant job when sizes are known precisely. */
24467 misaligned_prologue_used
24468 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24474 /* Do the cheap promotion to allow better CSE across the
24475 main loop and epilogue (ie one load of the big constant in the
24476 front of all code.
24477 For now the misaligned move sequences do not have fast path
24478 without broadcasting. */
24480 {
24482 {
24488 }
24489 else
24490 {
24493 }
24494 }
24495 /* Misaligned move sequences handles both prologues and epilogues at once.
24496 Default code generation results in smaller code for large alignments and
24497 also avoids redundant job when sizes are known precisely. */
24499 {
24500 /* Misaligned move prologue handled small blocks by itself. */
24501 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24506 desired_align < align
24515 {
24516 /* It is possible that we copied enough so the main loop will not
24517 execute. */
24527 else
24529 }
24530 }
24531 /* Ensure that alignment prologue won't copy past end of block. */
24533 {
24535 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24536 Make sure it is power of 2. */
24539 /* To improve performance of small blocks, we jump around the VAL
24540 promoting mode. This mean that if the promoted VAL is not constant,
24541 we might not use it in the epilogue and have to use byte
24542 loop variant. */
24547 {
24548 /* If main algorithm works on QImode, no epilogue is needed.
24549 For small sizes just don't align anything. */
24552 else
24554 }
24557 {
24564 else
24566 }
24567 }
24569 /* Emit code to decide on runtime whether library call or inline should be
24570 used. */
24572 {
24574 {
24576 {
24580 }
24581 }
24582 else
24583 {
24593 else
24597 }
24598 }
24600 /* Step 2: Alignment prologue. */
24601 /* Do the expensive promotion once we branched off the small blocks. */
24607 {
24609 {
24610 /* Except for the first move in prologue, we no longer know
24611 constant offset in aliasing info. It don't seems to worth
24612 the pain to maintain it for the first move, so throw away
24613 the info early. */
24620 issetmem);
24621 /* At most desired_align - align bytes are copied. */
24624 else
24626 }
24627 else
24628 {
24629 /* If we know how many bytes need to be stored before dst is
24630 sufficiently aligned, maintain aliasing info accurately. */
24632 srcreg,
24633 promoted_val,
24634 vec_promoted_val,
24635 desired_align,
24636 align_bytes,
24637 issetmem);
24644 }
24646 && !min_size
24651 {
24652 /* It is possible that we copied enough so the main loop will not
24653 execute. */
24663 else
24665 }
24666 }
24668 {
24675 }
24679 /* Step 3: Main loop. */
24682 {
24705 }
24706 /* Adjust properly the offset of src and dest memory for aliasing. */
24708 {
24714 }
24715 else
24716 {
24720 }
24722 /* Step 4: Epilogue to copy the remaining bytes. */
24723 epilogue:
24725 {
24726 /* When the main loop is done, COUNT_EXP might hold original count,
24727 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24728 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24729 bytes. Compensate if needed. */
24732 {
24733 tmp =
24736 OPTAB_DIRECT);
24739 }
24742 }
24745 {
24748 epilogue_size_needed);
24749 else
24750 {
24754 epilogue_size_needed);
24755 else
24757 epilogue_size_needed);
24758 }
24759 }
24763 }
24766 /* Expand the appropriate insns for doing strlen if not just doing
24767 repnz; scasb
24769 out = result, initialized with the start address
24770 align_rtx = alignment of the address.
24771 scratch = scratch register, initialized with the startaddress when
24772 not aligned, otherwise undefined
24774 This is just the body. It needs the initializations mentioned above and
24775 some address computing at the end. These things are done in i386.md. */
24777 static void
24779 {
24781 rtx tmp;
24786 rtx mem;
24789 rtx cmp;
24795 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24797 /* Is there a known alignment and is it less than 4? */
24799 {
24802 /* Is there a known alignment and is it not 2? */
24804 {
24808 /* Leave just the 3 lower bits. */
24818 }
24819 else
24820 {
24821 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24822 check if is aligned to 4 - byte. */
24829 }
24833 /* Now compare the bytes. */
24835 /* Compare the first n unaligned byte on a byte per byte basis. */
24839 /* Increment the address. */
24842 /* Not needed with an alignment of 2 */
24844 {
24848 end_0_label);
24853 }
24856 end_0_label);
24859 }
24861 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24862 align this loop. It gives only huge programs, but does not help to
24863 speed up. */
24870 /* This formula yields a nonzero result iff one of the bytes is zero.
24871 This saves three branches inside loop and many cycles. */
24879 align_4_label);
24882 {
24888 /* If zero is not in the first two bytes, move two bytes forward. */
24894 reg,
24895 tmpreg)));
24896 /* Emit lea manually to avoid clobbering of flags. */
24904 reg2,
24905 out)));
24906 }
24907 else
24908 {
24910 /* Is zero in the first two bytes? */
24917 pc_rtx);
24921 /* Not in the first two. Move two bytes forward. */
24927 }
24929 /* Avoid branch in fixing the byte. */
24937 }
24939 /* Expand strlen. */
24941 bool
24943 {
24946 /* The generic case of strlen expander is long. Avoid it's
24947 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
24950 && !TARGET_INLINE_ALL_STRINGOPS
24960 {
24961 /* Well it seems that some optimizer does not combine a call like
24962 foo(strlen(bar), strlen(bar));
24963 when the move and the subtraction is done here. It does calculate
24964 the length just once when these instructions are done inside of
24965 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
24966 often used and I use one fewer register for the lifetime of
24967 output_strlen_unroll() this is better. */
24973 /* strlensi_unroll_1 returns the address of the zero at the end of
24974 the string, like memchr(), so compute the length by subtracting
24975 the start address. */
24977 }
24978 else
24979 {
24980 rtx unspec;
24982 /* Can't use this if the user has appropriated eax, ecx, or edi. */
24995 /* If .md starts supporting :P, this can be done in .md. */
25001 }
25003 }
25005 /* For given symbol (function) construct code to compute address of it's PLT
25006 entry in large x86-64 PIC model. */
25007 static rtx
25009 {
25022 }
25024 rtx
25026 rtx callarg2,
25028 {
25029 unsigned int const cregs_size
25040 {
25041 #if TARGET_MACHO
25044 #endif
25045 }
25046 else
25047 {
25048 /* Static functions and indirect calls don't need the pic register. */
25050 && (!TARGET_64BIT
25056 }
25059 {
25063 }
25066 && !TARGET_PECOFF
25074 {
25077 }
25085 {
25089 }
25093 {
25097 UNSPEC_MS_TO_SYSV_CALL);
25100 {
25106 }
25107 }
25116 }
25118 /* Output the assembly for a call instruction. */
25122 {
25128 {
25131 /* SEH epilogue detection requires the indirect branch case
25132 to include REX.W. */
25135 else
25140 }
25142 /* SEH unwinding can require an extra nop to be emitted in several
25143 circumstances. Determine if we have one of those. */
25145 {
25146 rtx i;
25149 {
25150 /* If we get to another real insn, we don't need the nop. */
25154 /* If we get to the epilogue note, prevent a catch region from
25155 being adjacent to the standard epilogue sequence. If non-
25156 call-exceptions, we'll have done this during epilogue emission. */
25158 && !flag_non_call_exceptions
25160 {
25163 }
25164 }
25166 /* If we didn't find a real insn following the call, prevent the
25167 unwinder from looking into the next function. */
25170 }
25174 else
25183 }
25184 \f
25185 /* Clear stack slot assignments remembered from previous functions.
25186 This is called from INIT_EXPANDERS once before RTL is emitted for each
25187 function. */
25191 {
25199 }
25201 /* Return a MEM corresponding to a stack slot with mode MODE.
25202 Allocate a new slot if necessary.
25204 The RTL for a function can have several slots available: N is
25205 which slot to use. */
25207 rtx
25209 {
25226 }
25228 static void
25230 {
25236 }
25237 \f
25238 /* Check whether x86 address PARTS is a pc-relative address. */
25240 static bool
25242 {
25250 {
25252 {
25269 }
25270 }
25272 }
25274 /* Calculate the length of the memory address in the instruction encoding.
25275 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25276 or other prefixes. We never generate addr32 prefix for LEA insn. */
25278 int
25280 {
25297 /* If this is not LEA instruction, add the length of addr32 prefix. */
25302 len++;
25316 /* Rule of thumb:
25317 - esp as the base always wants an index,
25318 - ebp as the base always wants a displacement,
25319 - r12 as the base always wants an index,
25320 - r13 as the base always wants a displacement. */
25322 /* Register Indirect. */
25324 {
25325 /* esp (for its index) and ebp (for its displacement) need
25326 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25327 code. */
25334 len++;
25335 }
25337 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25338 is not disp32, but disp32(%rip), so for disp32
25339 SIB byte is needed, unless print_operand_address
25340 optimizes it into disp32(%rip) or (%rip) is implied
25341 by UNSPEC. */
25343 {
25346 len++;
25347 }
25348 else
25349 {
25350 /* Find the length of the displacement constant. */
25352 {
25355 else
25357 }
25358 /* ebp always wants a displacement. Similarly r13. */
25360 len++;
25362 /* An index requires the two-byte modrm form.... */
25364 /* ...like esp (or r12), which always wants an index. */
25368 len++;
25369 }
25372 }
25374 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25375 is set, expect that insn have 8bit immediate alternative. */
25376 int
25378 {
25384 {
25389 {
25392 {
25404 }
25406 {
25409 }
25410 }
25412 {
25422 /* Immediates for DImode instructions are encoded
25423 as 32bit sign extended values. */
25429 }
25430 }
25432 }
25434 /* Compute default value for "length_address" attribute. */
25435 int
25437 {
25441 {
25452 }
25457 {
25460 {
25465 constraints++;
25468 ;
25469 /* Skip ignored operands. */
25472 }
25474 }
25476 }
25478 /* Compute default value for "length_vex" attribute. It includes
25479 2 or 3 byte VEX prefix and 1 opcode byte. */
25481 int
25483 {
25486 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25487 byte VEX prefix. */
25491 /* We can always use 2 byte VEX prefix in 32bit. */
25499 {
25500 /* REX.W bit uses 3 byte VEX prefix. */
25504 }
25505 else
25506 {
25507 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25511 }
25514 }
25515 \f
25516 /* Return the maximum number of instructions a cpu can issue. */
25518 static int
25520 {
25522 {
25553 }
25554 }
25556 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25557 by DEP_INSN and nothing set by DEP_INSN. */
25559 static bool
25561 {
25564 /* Simplify the test for uninteresting insns. */
25572 {
25575 }
25580 {
25583 }
25584 else
25590 /* This test is true if the dependent insn reads the flags but
25591 not any other potentially set register. */
25599 }
25601 /* Return true iff USE_INSN has a memory address with operands set by
25602 SET_INSN. */
25604 bool
25606 {
25611 {
25614 }
25616 }
25618 /* Helper function for exact_store_load_dependency.
25619 Return true if addr is found in insn. */
25620 static bool
25622 {
25629 {
25635 CASE_CONST_ANY:
25644 }
25648 {
25650 {
25660 }
25661 }
25663 }
25665 /* Return true if there exists exact dependency for store & load, i.e.
25666 the same memory address is used in them. */
25667 static bool
25669 {
25683 }
25685 static int
25687 {
25693 /* Anti and output dependencies have zero cost on all CPUs. */
25699 /* If we can't recognize the insns, we can't really do anything. */
25707 {
25709 /* Address Generation Interlock adds a cycle of latency. */
25711 {
25722 }
25726 /* ??? Compares pair with jump/setcc. */
25730 /* Floating point stores require value to be ready one cycle earlier. */
25738 /* INT->FP conversion is expensive. */
25742 /* There is one cycle extra latency between an FP op and a store. */
25752 /* Show ability of reorder buffer to hide latency of load by executing
25753 in parallel with previous instruction in case
25754 previous instruction is not needed to compute the address. */
25757 {
25758 /* Claim moves to take one cycle, as core can issue one load
25759 at time and the next load can start cycle later. */
25764 cost--;
25765 }
25769 /* The esp dependency is resolved before
25770 the instruction is really finished. */
25775 /* INT->FP conversion is expensive. */
25781 /* Show ability of reorder buffer to hide latency of load by executing
25782 in parallel with previous instruction in case
25783 previous instruction is not needed to compute the address. */
25786 {
25787 /* Claim moves to take one cycle, as core can issue one load
25788 at time and the next load can start cycle later. */
25794 else
25796 }
25807 /* Stack engine allows to execute push&pop instructions in parall. */
25811 /* FALLTHRU */
25817 /* Show ability of reorder buffer to hide latency of load by executing
25818 in parallel with previous instruction in case
25819 previous instruction is not needed to compute the address. */
25822 {
25826 /* Because of the difference between the length of integer and
25827 floating unit pipeline preparation stages, the memory operands
25828 for floating point are cheaper.
25830 ??? For Athlon it the difference is most probably 2. */
25833 else
25838 else
25840 }
25847 /* Stack engine allows to execute push&pop instructions in parall. */
25854 /* Show ability of reorder buffer to hide latency of load by executing
25855 in parallel with previous instruction in case
25856 previous instruction is not needed to compute the address. */
25859 {
25862 else
25864 }
25872 /* Increase cost of integer loads. */
25875 {
25878 {
25881 else
25882 {
25883 /* Increase cost of ld/st for short int types only
25884 because of store forwarding issue. */
25888 {
25889 /* Increase cost of store/load insn if exact
25890 dependence exists and it is load insn. */
25895 }
25896 }
25897 }
25898 }
25902 }
25905 }
25907 /* How many alternative schedules to try. This should be as wide as the
25908 scheduling freedom in the DFA, but no wider. Making this value too
25909 large results extra work for the scheduler. */
25911 static int
25913 {
25915 {
25927 /* We use lookahead value 4 for BD both before and after reload
25928 schedules. Plan is to have value 8 included for O3. */
25938 /* Generally, we want haifa-sched:max_issue() to look ahead as far
25939 as many instructions can be executed on a cycle, i.e.,
25940 issue_rate. I wonder why tuning for many CPUs does not do this. */
25943 /* Don't use lookahead for pre-reload schedule to save compile time. */
25948 }
25949 }
25951 /* Return true if target platform supports macro-fusion. */
25953 static bool
25955 {
25957 }
25959 /* Check whether current microarchitecture support macro fusion
25960 for insn pair "CONDGEN + CONDJMP". Refer to
25961 "Intel Architectures Optimization Reference Manual". */
25963 static bool
25965 {
25984 else
25985 {
25990 {
25994 else
25996 }
25997 }
26004 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26005 supported. */
26012 /* No fusion for RIP-relative address. */
26019 ix86_address parts;
26025 }
26030 /* Check whether conditional jump use Sign or Overflow Flags. */
26038 /* Return true for TYPE_TEST and TYPE_ICMP. */
26043 /* The following is the case that macro-fusion for alu + jmp. */
26047 /* No fusion for alu op with memory destination operand. */
26052 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26053 supported. */
26062 }
26064 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26065 execution. It is applied if
26066 (1) IMUL instruction is on the top of list;
26067 (2) There exists the only producer of independent IMUL instruction in
26068 ready list.
26069 Return index of IMUL producer if it was found and -1 otherwise. */
26070 static int
26072 {
26074 sd_iterator_def sd_it;
26075 dep_t dep;
26082 /* Check that IMUL instruction is on the top of ready list. */
26091 /* Search for producer of independent IMUL instruction. */
26093 {
26097 /* Skip IMUL instruction. */
26107 {
26108 rtx con;
26119 {
26120 sd_iterator_def sd_it1;
26121 dep_t dep1;
26122 /* Check if there is no other dependee for IMUL. */
26125 {
26126 rtx pro;
26132 }
26135 }
26136 }
26139 }
26141 }
26143 /* Try to find the best candidate on the top of ready list if two insns
26144 have the same priority - candidate is best if its dependees were
26145 scheduled earlier. Applied for Silvermont only.
26146 Return true if top 2 insns must be interchanged. */
26147 static bool
26149 {
26152 rtx set;
26153 sd_iterator_def sd_it;
26154 dep_t dep;
26157 #define INSN_TICK(INSN) (HID (INSN)->tick)
26178 {
26181 /* Determine winner more precise. */
26183 {
26184 rtx pro;
26190 }
26192 {
26193 rtx pro;
26199 }
26202 {
26203 /* Determine winner - load must win. */
26209 }
26211 }
26213 #undef INSN_TICK
26214 }
26216 /* Perform possible reodering of ready list for Atom/Silvermont only.
26217 Return issue rate. */
26218 static int
26221 {
26225 rtx insn;
26228 /* Set up issue rate. */
26231 /* Do reodering for BONNELL/SILVERMONT only. */
26235 /* Nothing to do if ready list contains only 1 instruction. */
26239 /* Do reodering for post-reload scheduler only. */
26244 {
26249 /* Put IMUL producer (ready[index]) at the top of ready list. */
26255 }
26257 {
26261 /* Swap 2 top elements of ready list. */
26265 }
26267 }
26269 static bool
26272 /* Returns true if lhs of insn is HW function argument register and set up
26273 is_spilled to true if it is likely spilled HW register. */
26274 static bool
26276 {
26277 rtx dst;
26281 /* Call instructions are not movable, ignore it. */
26292 {
26293 /* Is it likely spilled HW register? */
26298 }
26300 }
26302 /* Add output dependencies for chain of function adjacent arguments if only
26303 there is a move to likely spilled HW register. Return first argument
26304 if at least one dependence was added or NULL otherwise. */
26305 static rtx
26307 {
26308 rtx insn;
26315 /* Find nearest to call argument passing instruction. */
26317 {
26326 }
26330 {
26337 {
26340 }
26342 {
26343 /* Add output depdendence between two function arguments if chain
26344 of output arguments contains likely spilled HW registers. */
26348 }
26349 else
26351 }
26355 }
26357 /* Add output or anti dependency from insn to first_arg to restrict its code
26358 motion. */
26359 static void
26361 {
26362 rtx set;
26363 rtx tmp;
26370 {
26371 /* Add output dependency to the first function argument. */
26374 }
26375 /* Add anti dependency. */
26377 }
26379 /* Avoid cross block motion of function argument through adding dependency
26380 from the first non-jump instruction in bb. */
26381 static void
26383 {
26387 {
26389 {
26392 {
26395 }
26396 }
26400 }
26401 }
26403 /* Hook for pre-reload schedule - avoid motion of function arguments
26404 passed in likely spilled HW registers. */
26405 static void
26407 {
26408 rtx insn;
26416 {
26419 {
26420 /* Add dependee for first argument to predecessors if only
26421 region contains more than one block. */
26425 /* Skip trivial regions and region head blocks that can have
26426 predecessors outside of region. */
26428 {
26429 edge e;
26430 edge_iterator ei;
26432 /* Regions are SCCs with the exception of selective
26433 scheduling with pipelining of outer blocks enabled.
26434 So also check that immediate predecessors of a non-head
26435 block are in the same region. */
26437 {
26438 /* Avoid creating of loop-carried dependencies through
26439 using topological ordering in the region. */
26443 }
26444 }
26448 }
26449 }
26452 }
26454 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26455 HW registers to maximum, to schedule them at soon as possible. These are
26456 moves from function argument registers at the top of the function entry
26457 and moves from function return value registers after call. */
26458 static int
26460 {
26461 rtx set;
26471 {
26478 }
26481 }
26483 /* Model decoder of Core 2/i7.
26484 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26485 track the instruction fetch block boundaries and make sure that long
26486 (9+ bytes) instructions are assigned to D0. */
26488 /* Maximum length of an insn that can be handled by
26489 a secondary decoder unit. '8' for Core 2/i7. */
26492 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26493 '16' for Core 2/i7. */
26496 /* Maximum number of instructions decoder can handle per cycle.
26497 '6' for Core 2/i7. */
26501 ix86_first_cycle_multipass_data_t;
26503 const_ix86_first_cycle_multipass_data_t;
26505 /* A variable to store target state across calls to max_issue within
26506 one cycle. */
26510 /* Initialize DATA. */
26511 static void
26513 {
26514 ix86_first_cycle_multipass_data_t data
26521 }
26523 /* Advancing the cycle; reset ifetch block counts. */
26524 static void
26526 {
26533 }
26537 /* Filter out insns from ready_try that the core will not be able to issue
26538 on current cycle due to decoder. */
26539 static void
26540 core2i7_first_cycle_multipass_filter_ready_try
26543 {
26545 {
26546 rtx insn;
26556 (!first_cycle_insn_p
26558 /* ... or it would not fit into the ifetch block ... */
26560 /* ... or the decoder is full already ... */
26562 /* ... mask the insn out. */
26563 {
26568 }
26569 }
26570 }
26572 /* Prepare for a new round of multipass lookahead scheduling. */
26573 static void
26577 {
26578 ix86_first_cycle_multipass_data_t data
26580 const_ix86_first_cycle_multipass_data_t prev_data
26583 /* Restore the state from the end of the previous round. */
26587 /* Filter instructions that cannot be issued on current cycle due to
26588 decoder restrictions. */
26590 first_cycle_insn_p);
26591 }
26593 /* INSN is being issued in current solution. Account for its impact on
26594 the decoder model. */
26595 static void
26599 {
26600 ix86_first_cycle_multipass_data_t data
26602 const_ix86_first_cycle_multipass_data_t prev_data
26612 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26614 {
26617 }
26619 {
26623 }
26626 /* Filter out insns from ready_try that the core will not be able to issue
26627 on current cycle due to decoder. */
26630 }
26632 /* Revert the effect on ready_try. */
26633 static void
26637 {
26638 const_ix86_first_cycle_multipass_data_t data
26641 sbitmap_iterator sbi;
26645 {
26647 }
26648 }
26650 /* Save the result of multipass lookahead scheduling for the next round. */
26651 static void
26653 {
26654 const_ix86_first_cycle_multipass_data_t data
26656 ix86_first_cycle_multipass_data_t next_data
26660 {
26663 }
26664 }
26666 /* Deallocate target data. */
26667 static void
26669 {
26670 ix86_first_cycle_multipass_data_t data
26674 {
26678 }
26679 }
26681 /* Prepare for scheduling pass. */
26682 static void
26686 {
26687 /* Install scheduling hooks for current CPU. Some of these hooks are used
26688 in time-critical parts of the scheduler, so we only set them up when
26689 they are actually used. */
26691 {
26696 /* Do not perform multipass scheduling for pre-reload schedule
26697 to save compile time. */
26699 {
26715 /* Set decoder parameters. */
26720 }
26721 /* ... Fall through ... */
26731 }
26732 }
26734 \f
26735 /* Compute the alignment given to a constant that is being placed in memory.
26736 EXP is the constant and ALIGN is the alignment that the object would
26737 ordinarily have.
26738 The value of this function is used instead of that alignment to align
26739 the object. */
26741 int
26743 {
26746 {
26751 }
26757 }
26759 /* Compute the alignment for a static variable.
26760 TYPE is the data type, and ALIGN is the alignment that
26761 the object would ordinarily have. The value of this function is used
26762 instead of that alignment to align the object. */
26764 int
26766 {
26767 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26768 for symbols from other compilation units or symbols that don't need
26769 to bind locally. In order to preserve some ABI compatibility with
26770 those compilers, ensure we don't decrease alignment from what we
26771 used to assume. */
26773 int max_align_compat
26776 /* A data structure, equal or greater than the size of a cache line
26777 (64 bytes in the Pentium 4 and other recent Intel processors, including
26778 processors based on Intel Core microarchitecture) should be aligned
26779 so that its base address is a multiple of a cache line size. */
26781 int max_align
26791 {
26798 }
26800 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26801 to 16byte boundary. */
26803 {
26810 }
26816 {
26821 }
26823 {
26830 }
26835 {
26840 }
26843 {
26848 }
26851 }
26853 /* Compute the alignment for a local variable or a stack slot. EXP is
26854 the data type or decl itself, MODE is the widest mode available and
26855 ALIGN is the alignment that the object would ordinarily have. The
26856 value of this macro is used instead of that alignment to align the
26857 object. */
26859 unsigned int
26862 {
26866 {
26869 }
26870 else
26871 {
26874 }
26876 /* Don't do dynamic stack realignment for long long objects with
26877 -mpreferred-stack-boundary=2. */
26886 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26887 register in MODE. We will return the largest alignment of XF
26888 and DF. */
26890 {
26894 }
26896 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26897 to 16byte boundary. Exact wording is:
26899 An array uses the same alignment as its elements, except that a local or
26900 global array variable of length at least 16 bytes or
26901 a C99 variable-length array variable always has alignment of at least 16 bytes.
26903 This was added to allow use of aligned SSE instructions at arrays. This
26904 rule is meant for static storage (where compiler can not do the analysis
26905 by itself). We follow it for automatic variables only when convenient.
26906 We fully control everything in the function compiled and functions from
26907 other unit can not rely on the alignment.
26909 Exclude va_list type. It is the common case of local array where
26910 we can not benefit from the alignment.
26912 TODO: Probably one should optimize for size only when var is not escaping. */
26915 {
26925 }
26927 {
26932 }
26934 {
26940 }
26945 {
26950 }
26953 {
26959 }
26961 }
26963 /* Compute the minimum required alignment for dynamic stack realignment
26964 purposes for a local variable, parameter or a stack slot. EXP is
26965 the data type or decl itself, MODE is its mode and ALIGN is the
26966 alignment that the object would ordinarily have. */
26968 unsigned int
26971 {
26975 {
26978 }
26979 else
26980 {
26983 }
26988 /* Don't do dynamic stack realignment for long long objects with
26989 -mpreferred-stack-boundary=2. */
26996 }
26997 \f
26998 /* Find a location for the static chain incoming to a nested function.
26999 This is a register, unless all free registers are used by arguments. */
27001 static rtx
27003 {
27010 {
27011 /* We always use R10 in 64-bit mode. */
27013 }
27014 else
27015 {
27016 tree fntype;
27019 /* By default in 32-bit mode we use ECX to pass the static chain. */
27025 {
27026 /* Fastcall functions use ecx/edx for arguments, which leaves
27027 us with EAX for the static chain.
27028 Thiscall functions use ecx for arguments, which also
27029 leaves us with EAX for the static chain. */
27031 }
27033 {
27034 /* Thiscall functions use ecx for arguments, which leaves
27035 us with EAX and EDX for the static chain.
27036 We are using for abi-compatibility EAX. */
27038 }
27040 {
27041 /* For regparm 3, we have no free call-clobbered registers in
27042 which to store the static chain. In order to implement this,
27043 we have the trampoline push the static chain to the stack.
27044 However, we can't push a value below the return address when
27045 we call the nested function directly, so we have to use an
27046 alternate entry point. For this we use ESI, and have the
27047 alternate entry point push ESI, so that things appear the
27048 same once we're executing the nested function. */
27050 {
27056 }
27058 }
27059 }
27062 }
27064 /* Emit RTL insns to initialize the variable parts of a trampoline.
27065 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27066 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27067 to be passed to the target function. */
27069 static void
27071 {
27079 {
27082 /* Load the function address to r11. Try to load address using
27083 the shorter movl instead of movabs. We may want to support
27084 movq for kernel mode, but kernel does not use trampolines at
27085 the moment. FNADDR is a 32bit address and may not be in
27086 DImode when ptr_mode == SImode. Always use movl in this
27087 case. */
27090 {
27099 }
27100 else
27101 {
27108 }
27110 /* Load static chain using movabs to r10. Use the shorter movl
27111 instead of movabs when ptr_mode == SImode. */
27113 {
27116 }
27117 else
27118 {
27121 }
27130 /* Jump to r11; the last (unused) byte is a nop, only there to
27131 pad the write out to a single 32-bit store. */
27135 }
27136 else
27137 {
27140 /* Depending on the static chain location, either load a register
27141 with a constant, or push the constant to the stack. All of the
27142 instructions are the same size. */
27145 {
27147 {
27154 }
27155 }
27156 else
27171 /* Compute offset from the end of the jmp to the target function.
27172 In the case in which the trampoline stores the static chain on
27173 the stack, we need to skip the first insn which pushes the
27174 (call-saved) register static chain; this push is 1 byte. */
27181 }
27185 #ifdef HAVE_ENABLE_EXECUTE_STACK
27186 #ifdef CHECK_EXECUTE_STACK_ENABLED
27188 #endif
27191 #endif
27192 }
27193 \f
27194 /* The following file contains several enumerations and data structures
27195 built from the definitions in i386-builtin-types.def. */
27199 /* Table for the ix86 builtin non-function types. */
27202 /* Retrieve an element from the above table, building some of
27203 the types lazily. */
27205 static tree
27207 {
27219 {
27227 }
27228 else
27229 {
27235 else
27243 }
27247 }
27249 /* Table for the ix86 builtin function types. */
27252 /* Retrieve an element from the above table, building some of
27253 the types lazily. */
27255 static tree
27257 {
27258 tree type;
27267 {
27275 {
27278 }
27281 }
27282 else
27283 {
27289 }
27293 }
27296 /* Codes for all the SSE/MMX builtins. */
27297 enum ix86_builtins
27298 {
27299 IX86_BUILTIN_ADDPS,
27300 IX86_BUILTIN_ADDSS,
27301 IX86_BUILTIN_DIVPS,
27302 IX86_BUILTIN_DIVSS,
27303 IX86_BUILTIN_MULPS,
27304 IX86_BUILTIN_MULSS,
27305 IX86_BUILTIN_SUBPS,
27306 IX86_BUILTIN_SUBSS,
27308 IX86_BUILTIN_CMPEQPS,
27309 IX86_BUILTIN_CMPLTPS,
27310 IX86_BUILTIN_CMPLEPS,
27311 IX86_BUILTIN_CMPGTPS,
27312 IX86_BUILTIN_CMPGEPS,
27313 IX86_BUILTIN_CMPNEQPS,
27314 IX86_BUILTIN_CMPNLTPS,
27315 IX86_BUILTIN_CMPNLEPS,
27316 IX86_BUILTIN_CMPNGTPS,
27317 IX86_BUILTIN_CMPNGEPS,
27318 IX86_BUILTIN_CMPORDPS,
27319 IX86_BUILTIN_CMPUNORDPS,
27320 IX86_BUILTIN_CMPEQSS,
27321 IX86_BUILTIN_CMPLTSS,
27322 IX86_BUILTIN_CMPLESS,
27323 IX86_BUILTIN_CMPNEQSS,
27324 IX86_BUILTIN_CMPNLTSS,
27325 IX86_BUILTIN_CMPNLESS,
27326 IX86_BUILTIN_CMPORDSS,
27327 IX86_BUILTIN_CMPUNORDSS,
27329 IX86_BUILTIN_COMIEQSS,
27330 IX86_BUILTIN_COMILTSS,
27331 IX86_BUILTIN_COMILESS,
27332 IX86_BUILTIN_COMIGTSS,
27333 IX86_BUILTIN_COMIGESS,
27334 IX86_BUILTIN_COMINEQSS,
27335 IX86_BUILTIN_UCOMIEQSS,
27336 IX86_BUILTIN_UCOMILTSS,
27337 IX86_BUILTIN_UCOMILESS,
27338 IX86_BUILTIN_UCOMIGTSS,
27339 IX86_BUILTIN_UCOMIGESS,
27340 IX86_BUILTIN_UCOMINEQSS,
27342 IX86_BUILTIN_CVTPI2PS,
27343 IX86_BUILTIN_CVTPS2PI,
27344 IX86_BUILTIN_CVTSI2SS,
27345 IX86_BUILTIN_CVTSI642SS,
27346 IX86_BUILTIN_CVTSS2SI,
27347 IX86_BUILTIN_CVTSS2SI64,
27348 IX86_BUILTIN_CVTTPS2PI,
27349 IX86_BUILTIN_CVTTSS2SI,
27350 IX86_BUILTIN_CVTTSS2SI64,
27352 IX86_BUILTIN_MAXPS,
27353 IX86_BUILTIN_MAXSS,
27354 IX86_BUILTIN_MINPS,
27355 IX86_BUILTIN_MINSS,
27357 IX86_BUILTIN_LOADUPS,
27358 IX86_BUILTIN_STOREUPS,
27359 IX86_BUILTIN_MOVSS,
27361 IX86_BUILTIN_MOVHLPS,
27362 IX86_BUILTIN_MOVLHPS,
27363 IX86_BUILTIN_LOADHPS,
27364 IX86_BUILTIN_LOADLPS,
27365 IX86_BUILTIN_STOREHPS,
27366 IX86_BUILTIN_STORELPS,
27368 IX86_BUILTIN_MASKMOVQ,
27369 IX86_BUILTIN_MOVMSKPS,
27370 IX86_BUILTIN_PMOVMSKB,
27372 IX86_BUILTIN_MOVNTPS,
27373 IX86_BUILTIN_MOVNTQ,
27375 IX86_BUILTIN_LOADDQU,
27376 IX86_BUILTIN_STOREDQU,
27378 IX86_BUILTIN_PACKSSWB,
27379 IX86_BUILTIN_PACKSSDW,
27380 IX86_BUILTIN_PACKUSWB,
27382 IX86_BUILTIN_PADDB,
27383 IX86_BUILTIN_PADDW,
27384 IX86_BUILTIN_PADDD,
27385 IX86_BUILTIN_PADDQ,
27386 IX86_BUILTIN_PADDSB,
27387 IX86_BUILTIN_PADDSW,
27388 IX86_BUILTIN_PADDUSB,
27389 IX86_BUILTIN_PADDUSW,
27390 IX86_BUILTIN_PSUBB,
27391 IX86_BUILTIN_PSUBW,
27392 IX86_BUILTIN_PSUBD,
27393 IX86_BUILTIN_PSUBQ,
27394 IX86_BUILTIN_PSUBSB,
27395 IX86_BUILTIN_PSUBSW,
27396 IX86_BUILTIN_PSUBUSB,
27397 IX86_BUILTIN_PSUBUSW,
27399 IX86_BUILTIN_PAND,
27400 IX86_BUILTIN_PANDN,
27401 IX86_BUILTIN_POR,
27402 IX86_BUILTIN_PXOR,
27404 IX86_BUILTIN_PAVGB,
27405 IX86_BUILTIN_PAVGW,
27407 IX86_BUILTIN_PCMPEQB,
27408 IX86_BUILTIN_PCMPEQW,
27409 IX86_BUILTIN_PCMPEQD,
27410 IX86_BUILTIN_PCMPGTB,
27411 IX86_BUILTIN_PCMPGTW,
27412 IX86_BUILTIN_PCMPGTD,
27414 IX86_BUILTIN_PMADDWD,
27416 IX86_BUILTIN_PMAXSW,
27417 IX86_BUILTIN_PMAXUB,
27418 IX86_BUILTIN_PMINSW,
27419 IX86_BUILTIN_PMINUB,
27421 IX86_BUILTIN_PMULHUW,
27422 IX86_BUILTIN_PMULHW,
27423 IX86_BUILTIN_PMULLW,
27425 IX86_BUILTIN_PSADBW,
27426 IX86_BUILTIN_PSHUFW,
27428 IX86_BUILTIN_PSLLW,
27429 IX86_BUILTIN_PSLLD,
27430 IX86_BUILTIN_PSLLQ,
27431 IX86_BUILTIN_PSRAW,
27432 IX86_BUILTIN_PSRAD,
27433 IX86_BUILTIN_PSRLW,
27434 IX86_BUILTIN_PSRLD,
27435 IX86_BUILTIN_PSRLQ,
27436 IX86_BUILTIN_PSLLWI,
27437 IX86_BUILTIN_PSLLDI,
27438 IX86_BUILTIN_PSLLQI,
27439 IX86_BUILTIN_PSRAWI,
27440 IX86_BUILTIN_PSRADI,
27441 IX86_BUILTIN_PSRLWI,
27442 IX86_BUILTIN_PSRLDI,
27443 IX86_BUILTIN_PSRLQI,
27445 IX86_BUILTIN_PUNPCKHBW,
27446 IX86_BUILTIN_PUNPCKHWD,
27447 IX86_BUILTIN_PUNPCKHDQ,
27448 IX86_BUILTIN_PUNPCKLBW,
27449 IX86_BUILTIN_PUNPCKLWD,
27450 IX86_BUILTIN_PUNPCKLDQ,
27452 IX86_BUILTIN_SHUFPS,
27454 IX86_BUILTIN_RCPPS,
27455 IX86_BUILTIN_RCPSS,
27456 IX86_BUILTIN_RSQRTPS,
27457 IX86_BUILTIN_RSQRTPS_NR,
27458 IX86_BUILTIN_RSQRTSS,
27459 IX86_BUILTIN_RSQRTF,
27460 IX86_BUILTIN_SQRTPS,
27461 IX86_BUILTIN_SQRTPS_NR,
27462 IX86_BUILTIN_SQRTSS,
27464 IX86_BUILTIN_UNPCKHPS,
27465 IX86_BUILTIN_UNPCKLPS,
27467 IX86_BUILTIN_ANDPS,
27468 IX86_BUILTIN_ANDNPS,
27469 IX86_BUILTIN_ORPS,
27470 IX86_BUILTIN_XORPS,
27472 IX86_BUILTIN_EMMS,
27473 IX86_BUILTIN_LDMXCSR,
27474 IX86_BUILTIN_STMXCSR,
27475 IX86_BUILTIN_SFENCE,
27477 IX86_BUILTIN_FXSAVE,
27478 IX86_BUILTIN_FXRSTOR,
27479 IX86_BUILTIN_FXSAVE64,
27480 IX86_BUILTIN_FXRSTOR64,
27482 IX86_BUILTIN_XSAVE,
27483 IX86_BUILTIN_XRSTOR,
27484 IX86_BUILTIN_XSAVE64,
27485 IX86_BUILTIN_XRSTOR64,
27487 IX86_BUILTIN_XSAVEOPT,
27488 IX86_BUILTIN_XSAVEOPT64,
27490 IX86_BUILTIN_XSAVEC,
27491 IX86_BUILTIN_XSAVEC64,
27493 IX86_BUILTIN_XSAVES,
27494 IX86_BUILTIN_XRSTORS,
27495 IX86_BUILTIN_XSAVES64,
27496 IX86_BUILTIN_XRSTORS64,
27498 /* 3DNow! Original */
27499 IX86_BUILTIN_FEMMS,
27500 IX86_BUILTIN_PAVGUSB,
27501 IX86_BUILTIN_PF2ID,
27502 IX86_BUILTIN_PFACC,
27503 IX86_BUILTIN_PFADD,
27504 IX86_BUILTIN_PFCMPEQ,
27505 IX86_BUILTIN_PFCMPGE,
27506 IX86_BUILTIN_PFCMPGT,
27507 IX86_BUILTIN_PFMAX,
27508 IX86_BUILTIN_PFMIN,
27509 IX86_BUILTIN_PFMUL,
27510 IX86_BUILTIN_PFRCP,
27511 IX86_BUILTIN_PFRCPIT1,
27512 IX86_BUILTIN_PFRCPIT2,
27513 IX86_BUILTIN_PFRSQIT1,
27514 IX86_BUILTIN_PFRSQRT,
27515 IX86_BUILTIN_PFSUB,
27516 IX86_BUILTIN_PFSUBR,
27517 IX86_BUILTIN_PI2FD,
27518 IX86_BUILTIN_PMULHRW,
27520 /* 3DNow! Athlon Extensions */
27521 IX86_BUILTIN_PF2IW,
27522 IX86_BUILTIN_PFNACC,
27523 IX86_BUILTIN_PFPNACC,
27524 IX86_BUILTIN_PI2FW,
27525 IX86_BUILTIN_PSWAPDSI,
27526 IX86_BUILTIN_PSWAPDSF,
27528 /* SSE2 */
27529 IX86_BUILTIN_ADDPD,
27530 IX86_BUILTIN_ADDSD,
27531 IX86_BUILTIN_DIVPD,
27532 IX86_BUILTIN_DIVSD,
27533 IX86_BUILTIN_MULPD,
27534 IX86_BUILTIN_MULSD,
27535 IX86_BUILTIN_SUBPD,
27536 IX86_BUILTIN_SUBSD,
27538 IX86_BUILTIN_CMPEQPD,
27539 IX86_BUILTIN_CMPLTPD,
27540 IX86_BUILTIN_CMPLEPD,
27541 IX86_BUILTIN_CMPGTPD,
27542 IX86_BUILTIN_CMPGEPD,
27543 IX86_BUILTIN_CMPNEQPD,
27544 IX86_BUILTIN_CMPNLTPD,
27545 IX86_BUILTIN_CMPNLEPD,
27546 IX86_BUILTIN_CMPNGTPD,
27547 IX86_BUILTIN_CMPNGEPD,
27548 IX86_BUILTIN_CMPORDPD,
27549 IX86_BUILTIN_CMPUNORDPD,
27550 IX86_BUILTIN_CMPEQSD,
27551 IX86_BUILTIN_CMPLTSD,
27552 IX86_BUILTIN_CMPLESD,
27553 IX86_BUILTIN_CMPNEQSD,
27554 IX86_BUILTIN_CMPNLTSD,
27555 IX86_BUILTIN_CMPNLESD,
27556 IX86_BUILTIN_CMPORDSD,
27557 IX86_BUILTIN_CMPUNORDSD,
27559 IX86_BUILTIN_COMIEQSD,
27560 IX86_BUILTIN_COMILTSD,
27561 IX86_BUILTIN_COMILESD,
27562 IX86_BUILTIN_COMIGTSD,
27563 IX86_BUILTIN_COMIGESD,
27564 IX86_BUILTIN_COMINEQSD,
27565 IX86_BUILTIN_UCOMIEQSD,
27566 IX86_BUILTIN_UCOMILTSD,
27567 IX86_BUILTIN_UCOMILESD,
27568 IX86_BUILTIN_UCOMIGTSD,
27569 IX86_BUILTIN_UCOMIGESD,
27570 IX86_BUILTIN_UCOMINEQSD,
27572 IX86_BUILTIN_MAXPD,
27573 IX86_BUILTIN_MAXSD,
27574 IX86_BUILTIN_MINPD,
27575 IX86_BUILTIN_MINSD,
27577 IX86_BUILTIN_ANDPD,
27578 IX86_BUILTIN_ANDNPD,
27579 IX86_BUILTIN_ORPD,
27580 IX86_BUILTIN_XORPD,
27582 IX86_BUILTIN_SQRTPD,
27583 IX86_BUILTIN_SQRTSD,
27585 IX86_BUILTIN_UNPCKHPD,
27586 IX86_BUILTIN_UNPCKLPD,
27588 IX86_BUILTIN_SHUFPD,
27590 IX86_BUILTIN_LOADUPD,
27591 IX86_BUILTIN_STOREUPD,
27592 IX86_BUILTIN_MOVSD,
27594 IX86_BUILTIN_LOADHPD,
27595 IX86_BUILTIN_LOADLPD,
27597 IX86_BUILTIN_CVTDQ2PD,
27598 IX86_BUILTIN_CVTDQ2PS,
27600 IX86_BUILTIN_CVTPD2DQ,
27601 IX86_BUILTIN_CVTPD2PI,
27602 IX86_BUILTIN_CVTPD2PS,
27603 IX86_BUILTIN_CVTTPD2DQ,
27604 IX86_BUILTIN_CVTTPD2PI,
27606 IX86_BUILTIN_CVTPI2PD,
27607 IX86_BUILTIN_CVTSI2SD,
27608 IX86_BUILTIN_CVTSI642SD,
27610 IX86_BUILTIN_CVTSD2SI,
27611 IX86_BUILTIN_CVTSD2SI64,
27612 IX86_BUILTIN_CVTSD2SS,
27613 IX86_BUILTIN_CVTSS2SD,
27614 IX86_BUILTIN_CVTTSD2SI,
27615 IX86_BUILTIN_CVTTSD2SI64,
27617 IX86_BUILTIN_CVTPS2DQ,
27618 IX86_BUILTIN_CVTPS2PD,
27619 IX86_BUILTIN_CVTTPS2DQ,
27621 IX86_BUILTIN_MOVNTI,
27622 IX86_BUILTIN_MOVNTI64,
27623 IX86_BUILTIN_MOVNTPD,
27624 IX86_BUILTIN_MOVNTDQ,
27626 IX86_BUILTIN_MOVQ128,
27628 /* SSE2 MMX */
27629 IX86_BUILTIN_MASKMOVDQU,
27630 IX86_BUILTIN_MOVMSKPD,
27631 IX86_BUILTIN_PMOVMSKB128,
27633 IX86_BUILTIN_PACKSSWB128,
27634 IX86_BUILTIN_PACKSSDW128,
27635 IX86_BUILTIN_PACKUSWB128,
27637 IX86_BUILTIN_PADDB128,
27638 IX86_BUILTIN_PADDW128,
27639 IX86_BUILTIN_PADDD128,
27640 IX86_BUILTIN_PADDQ128,
27641 IX86_BUILTIN_PADDSB128,
27642 IX86_BUILTIN_PADDSW128,
27643 IX86_BUILTIN_PADDUSB128,
27644 IX86_BUILTIN_PADDUSW128,
27645 IX86_BUILTIN_PSUBB128,
27646 IX86_BUILTIN_PSUBW128,
27647 IX86_BUILTIN_PSUBD128,
27648 IX86_BUILTIN_PSUBQ128,
27649 IX86_BUILTIN_PSUBSB128,
27650 IX86_BUILTIN_PSUBSW128,
27651 IX86_BUILTIN_PSUBUSB128,
27652 IX86_BUILTIN_PSUBUSW128,
27654 IX86_BUILTIN_PAND128,
27655 IX86_BUILTIN_PANDN128,
27656 IX86_BUILTIN_POR128,
27657 IX86_BUILTIN_PXOR128,
27659 IX86_BUILTIN_PAVGB128,
27660 IX86_BUILTIN_PAVGW128,
27662 IX86_BUILTIN_PCMPEQB128,
27663 IX86_BUILTIN_PCMPEQW128,
27664 IX86_BUILTIN_PCMPEQD128,
27665 IX86_BUILTIN_PCMPGTB128,
27666 IX86_BUILTIN_PCMPGTW128,
27667 IX86_BUILTIN_PCMPGTD128,
27669 IX86_BUILTIN_PMADDWD128,
27671 IX86_BUILTIN_PMAXSW128,
27672 IX86_BUILTIN_PMAXUB128,
27673 IX86_BUILTIN_PMINSW128,
27674 IX86_BUILTIN_PMINUB128,
27676 IX86_BUILTIN_PMULUDQ,
27677 IX86_BUILTIN_PMULUDQ128,
27678 IX86_BUILTIN_PMULHUW128,
27679 IX86_BUILTIN_PMULHW128,
27680 IX86_BUILTIN_PMULLW128,
27682 IX86_BUILTIN_PSADBW128,
27683 IX86_BUILTIN_PSHUFHW,
27684 IX86_BUILTIN_PSHUFLW,
27685 IX86_BUILTIN_PSHUFD,
27687 IX86_BUILTIN_PSLLDQI128,
27688 IX86_BUILTIN_PSLLWI128,
27689 IX86_BUILTIN_PSLLDI128,
27690 IX86_BUILTIN_PSLLQI128,
27691 IX86_BUILTIN_PSRAWI128,
27692 IX86_BUILTIN_PSRADI128,
27693 IX86_BUILTIN_PSRLDQI128,
27694 IX86_BUILTIN_PSRLWI128,
27695 IX86_BUILTIN_PSRLDI128,
27696 IX86_BUILTIN_PSRLQI128,
27698 IX86_BUILTIN_PSLLDQ128,
27699 IX86_BUILTIN_PSLLW128,
27700 IX86_BUILTIN_PSLLD128,
27701 IX86_BUILTIN_PSLLQ128,
27702 IX86_BUILTIN_PSRAW128,
27703 IX86_BUILTIN_PSRAD128,
27704 IX86_BUILTIN_PSRLW128,
27705 IX86_BUILTIN_PSRLD128,
27706 IX86_BUILTIN_PSRLQ128,
27708 IX86_BUILTIN_PUNPCKHBW128,
27709 IX86_BUILTIN_PUNPCKHWD128,
27710 IX86_BUILTIN_PUNPCKHDQ128,
27711 IX86_BUILTIN_PUNPCKHQDQ128,
27712 IX86_BUILTIN_PUNPCKLBW128,
27713 IX86_BUILTIN_PUNPCKLWD128,
27714 IX86_BUILTIN_PUNPCKLDQ128,
27715 IX86_BUILTIN_PUNPCKLQDQ128,
27717 IX86_BUILTIN_CLFLUSH,
27718 IX86_BUILTIN_MFENCE,
27719 IX86_BUILTIN_LFENCE,
27720 IX86_BUILTIN_PAUSE,
27722 IX86_BUILTIN_FNSTENV,
27723 IX86_BUILTIN_FLDENV,
27724 IX86_BUILTIN_FNSTSW,
27725 IX86_BUILTIN_FNCLEX,
27727 IX86_BUILTIN_BSRSI,
27728 IX86_BUILTIN_BSRDI,
27729 IX86_BUILTIN_RDPMC,
27730 IX86_BUILTIN_RDTSC,
27731 IX86_BUILTIN_RDTSCP,
27732 IX86_BUILTIN_ROLQI,
27733 IX86_BUILTIN_ROLHI,
27734 IX86_BUILTIN_RORQI,
27735 IX86_BUILTIN_RORHI,
27737 /* SSE3. */
27738 IX86_BUILTIN_ADDSUBPS,
27739 IX86_BUILTIN_HADDPS,
27740 IX86_BUILTIN_HSUBPS,
27741 IX86_BUILTIN_MOVSHDUP,
27742 IX86_BUILTIN_MOVSLDUP,
27743 IX86_BUILTIN_ADDSUBPD,
27744 IX86_BUILTIN_HADDPD,
27745 IX86_BUILTIN_HSUBPD,
27746 IX86_BUILTIN_LDDQU,
27748 IX86_BUILTIN_MONITOR,
27749 IX86_BUILTIN_MWAIT,
27751 /* SSSE3. */
27752 IX86_BUILTIN_PHADDW,
27753 IX86_BUILTIN_PHADDD,
27754 IX86_BUILTIN_PHADDSW,
27755 IX86_BUILTIN_PHSUBW,
27756 IX86_BUILTIN_PHSUBD,
27757 IX86_BUILTIN_PHSUBSW,
27758 IX86_BUILTIN_PMADDUBSW,
27759 IX86_BUILTIN_PMULHRSW,
27760 IX86_BUILTIN_PSHUFB,
27761 IX86_BUILTIN_PSIGNB,
27762 IX86_BUILTIN_PSIGNW,
27763 IX86_BUILTIN_PSIGND,
27764 IX86_BUILTIN_PALIGNR,
27765 IX86_BUILTIN_PABSB,
27766 IX86_BUILTIN_PABSW,
27767 IX86_BUILTIN_PABSD,
27769 IX86_BUILTIN_PHADDW128,
27770 IX86_BUILTIN_PHADDD128,
27771 IX86_BUILTIN_PHADDSW128,
27772 IX86_BUILTIN_PHSUBW128,
27773 IX86_BUILTIN_PHSUBD128,
27774 IX86_BUILTIN_PHSUBSW128,
27775 IX86_BUILTIN_PMADDUBSW128,
27776 IX86_BUILTIN_PMULHRSW128,
27777 IX86_BUILTIN_PSHUFB128,
27778 IX86_BUILTIN_PSIGNB128,
27779 IX86_BUILTIN_PSIGNW128,
27780 IX86_BUILTIN_PSIGND128,
27781 IX86_BUILTIN_PALIGNR128,
27782 IX86_BUILTIN_PABSB128,
27783 IX86_BUILTIN_PABSW128,
27784 IX86_BUILTIN_PABSD128,
27786 /* AMDFAM10 - SSE4A New Instructions. */
27787 IX86_BUILTIN_MOVNTSD,
27788 IX86_BUILTIN_MOVNTSS,
27789 IX86_BUILTIN_EXTRQI,
27790 IX86_BUILTIN_EXTRQ,
27791 IX86_BUILTIN_INSERTQI,
27792 IX86_BUILTIN_INSERTQ,
27794 /* SSE4.1. */
27795 IX86_BUILTIN_BLENDPD,
27796 IX86_BUILTIN_BLENDPS,
27797 IX86_BUILTIN_BLENDVPD,
27798 IX86_BUILTIN_BLENDVPS,
27799 IX86_BUILTIN_PBLENDVB128,
27800 IX86_BUILTIN_PBLENDW128,
27802 IX86_BUILTIN_DPPD,
27803 IX86_BUILTIN_DPPS,
27805 IX86_BUILTIN_INSERTPS128,
27807 IX86_BUILTIN_MOVNTDQA,
27808 IX86_BUILTIN_MPSADBW128,
27809 IX86_BUILTIN_PACKUSDW128,
27810 IX86_BUILTIN_PCMPEQQ,
27811 IX86_BUILTIN_PHMINPOSUW128,
27813 IX86_BUILTIN_PMAXSB128,
27814 IX86_BUILTIN_PMAXSD128,
27815 IX86_BUILTIN_PMAXUD128,
27816 IX86_BUILTIN_PMAXUW128,
27818 IX86_BUILTIN_PMINSB128,
27819 IX86_BUILTIN_PMINSD128,
27820 IX86_BUILTIN_PMINUD128,
27821 IX86_BUILTIN_PMINUW128,
27823 IX86_BUILTIN_PMOVSXBW128,
27824 IX86_BUILTIN_PMOVSXBD128,
27825 IX86_BUILTIN_PMOVSXBQ128,
27826 IX86_BUILTIN_PMOVSXWD128,
27827 IX86_BUILTIN_PMOVSXWQ128,
27828 IX86_BUILTIN_PMOVSXDQ128,
27830 IX86_BUILTIN_PMOVZXBW128,
27831 IX86_BUILTIN_PMOVZXBD128,
27832 IX86_BUILTIN_PMOVZXBQ128,
27833 IX86_BUILTIN_PMOVZXWD128,
27834 IX86_BUILTIN_PMOVZXWQ128,
27835 IX86_BUILTIN_PMOVZXDQ128,
27837 IX86_BUILTIN_PMULDQ128,
27838 IX86_BUILTIN_PMULLD128,
27840 IX86_BUILTIN_ROUNDSD,
27841 IX86_BUILTIN_ROUNDSS,
27843 IX86_BUILTIN_ROUNDPD,
27844 IX86_BUILTIN_ROUNDPS,
27846 IX86_BUILTIN_FLOORPD,
27847 IX86_BUILTIN_CEILPD,
27848 IX86_BUILTIN_TRUNCPD,
27849 IX86_BUILTIN_RINTPD,
27850 IX86_BUILTIN_ROUNDPD_AZ,
27852 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27853 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27854 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27856 IX86_BUILTIN_FLOORPS,
27857 IX86_BUILTIN_CEILPS,
27858 IX86_BUILTIN_TRUNCPS,
27859 IX86_BUILTIN_RINTPS,
27860 IX86_BUILTIN_ROUNDPS_AZ,
27862 IX86_BUILTIN_FLOORPS_SFIX,
27863 IX86_BUILTIN_CEILPS_SFIX,
27864 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27866 IX86_BUILTIN_PTESTZ,
27867 IX86_BUILTIN_PTESTC,
27868 IX86_BUILTIN_PTESTNZC,
27870 IX86_BUILTIN_VEC_INIT_V2SI,
27871 IX86_BUILTIN_VEC_INIT_V4HI,
27872 IX86_BUILTIN_VEC_INIT_V8QI,
27873 IX86_BUILTIN_VEC_EXT_V2DF,
27874 IX86_BUILTIN_VEC_EXT_V2DI,
27875 IX86_BUILTIN_VEC_EXT_V4SF,
27876 IX86_BUILTIN_VEC_EXT_V4SI,
27877 IX86_BUILTIN_VEC_EXT_V8HI,
27878 IX86_BUILTIN_VEC_EXT_V2SI,
27879 IX86_BUILTIN_VEC_EXT_V4HI,
27880 IX86_BUILTIN_VEC_EXT_V16QI,
27881 IX86_BUILTIN_VEC_SET_V2DI,
27882 IX86_BUILTIN_VEC_SET_V4SF,
27883 IX86_BUILTIN_VEC_SET_V4SI,
27884 IX86_BUILTIN_VEC_SET_V8HI,
27885 IX86_BUILTIN_VEC_SET_V4HI,
27886 IX86_BUILTIN_VEC_SET_V16QI,
27888 IX86_BUILTIN_VEC_PACK_SFIX,
27889 IX86_BUILTIN_VEC_PACK_SFIX256,
27891 /* SSE4.2. */
27892 IX86_BUILTIN_CRC32QI,
27893 IX86_BUILTIN_CRC32HI,
27894 IX86_BUILTIN_CRC32SI,
27895 IX86_BUILTIN_CRC32DI,
27897 IX86_BUILTIN_PCMPESTRI128,
27898 IX86_BUILTIN_PCMPESTRM128,
27899 IX86_BUILTIN_PCMPESTRA128,
27900 IX86_BUILTIN_PCMPESTRC128,
27901 IX86_BUILTIN_PCMPESTRO128,
27902 IX86_BUILTIN_PCMPESTRS128,
27903 IX86_BUILTIN_PCMPESTRZ128,
27904 IX86_BUILTIN_PCMPISTRI128,
27905 IX86_BUILTIN_PCMPISTRM128,
27906 IX86_BUILTIN_PCMPISTRA128,
27907 IX86_BUILTIN_PCMPISTRC128,
27908 IX86_BUILTIN_PCMPISTRO128,
27909 IX86_BUILTIN_PCMPISTRS128,
27910 IX86_BUILTIN_PCMPISTRZ128,
27912 IX86_BUILTIN_PCMPGTQ,
27914 /* AES instructions */
27915 IX86_BUILTIN_AESENC128,
27916 IX86_BUILTIN_AESENCLAST128,
27917 IX86_BUILTIN_AESDEC128,
27918 IX86_BUILTIN_AESDECLAST128,
27919 IX86_BUILTIN_AESIMC128,
27920 IX86_BUILTIN_AESKEYGENASSIST128,
27922 /* PCLMUL instruction */
27923 IX86_BUILTIN_PCLMULQDQ128,
27925 /* AVX */
27926 IX86_BUILTIN_ADDPD256,
27927 IX86_BUILTIN_ADDPS256,
27928 IX86_BUILTIN_ADDSUBPD256,
27929 IX86_BUILTIN_ADDSUBPS256,
27930 IX86_BUILTIN_ANDPD256,
27931 IX86_BUILTIN_ANDPS256,
27932 IX86_BUILTIN_ANDNPD256,
27933 IX86_BUILTIN_ANDNPS256,
27934 IX86_BUILTIN_BLENDPD256,
27935 IX86_BUILTIN_BLENDPS256,
27936 IX86_BUILTIN_BLENDVPD256,
27937 IX86_BUILTIN_BLENDVPS256,
27938 IX86_BUILTIN_DIVPD256,
27939 IX86_BUILTIN_DIVPS256,
27940 IX86_BUILTIN_DPPS256,
27941 IX86_BUILTIN_HADDPD256,
27942 IX86_BUILTIN_HADDPS256,
27943 IX86_BUILTIN_HSUBPD256,
27944 IX86_BUILTIN_HSUBPS256,
27945 IX86_BUILTIN_MAXPD256,
27946 IX86_BUILTIN_MAXPS256,
27947 IX86_BUILTIN_MINPD256,
27948 IX86_BUILTIN_MINPS256,
27949 IX86_BUILTIN_MULPD256,
27950 IX86_BUILTIN_MULPS256,
27951 IX86_BUILTIN_ORPD256,
27952 IX86_BUILTIN_ORPS256,
27953 IX86_BUILTIN_SHUFPD256,
27954 IX86_BUILTIN_SHUFPS256,
27955 IX86_BUILTIN_SUBPD256,
27956 IX86_BUILTIN_SUBPS256,
27957 IX86_BUILTIN_XORPD256,
27958 IX86_BUILTIN_XORPS256,
27959 IX86_BUILTIN_CMPSD,
27960 IX86_BUILTIN_CMPSS,
27961 IX86_BUILTIN_CMPPD,
27962 IX86_BUILTIN_CMPPS,
27963 IX86_BUILTIN_CMPPD256,
27964 IX86_BUILTIN_CMPPS256,
27965 IX86_BUILTIN_CVTDQ2PD256,
27966 IX86_BUILTIN_CVTDQ2PS256,
27967 IX86_BUILTIN_CVTPD2PS256,
27968 IX86_BUILTIN_CVTPS2DQ256,
27969 IX86_BUILTIN_CVTPS2PD256,
27970 IX86_BUILTIN_CVTTPD2DQ256,
27971 IX86_BUILTIN_CVTPD2DQ256,
27972 IX86_BUILTIN_CVTTPS2DQ256,
27973 IX86_BUILTIN_EXTRACTF128PD256,
27974 IX86_BUILTIN_EXTRACTF128PS256,
27975 IX86_BUILTIN_EXTRACTF128SI256,
27976 IX86_BUILTIN_VZEROALL,
27977 IX86_BUILTIN_VZEROUPPER,
27978 IX86_BUILTIN_VPERMILVARPD,
27979 IX86_BUILTIN_VPERMILVARPS,
27980 IX86_BUILTIN_VPERMILVARPD256,
27981 IX86_BUILTIN_VPERMILVARPS256,
27982 IX86_BUILTIN_VPERMILPD,
27983 IX86_BUILTIN_VPERMILPS,
27984 IX86_BUILTIN_VPERMILPD256,
27985 IX86_BUILTIN_VPERMILPS256,
27986 IX86_BUILTIN_VPERMIL2PD,
27987 IX86_BUILTIN_VPERMIL2PS,
27988 IX86_BUILTIN_VPERMIL2PD256,
27989 IX86_BUILTIN_VPERMIL2PS256,
27990 IX86_BUILTIN_VPERM2F128PD256,
27991 IX86_BUILTIN_VPERM2F128PS256,
27992 IX86_BUILTIN_VPERM2F128SI256,
27993 IX86_BUILTIN_VBROADCASTSS,
27994 IX86_BUILTIN_VBROADCASTSD256,
27995 IX86_BUILTIN_VBROADCASTSS256,
27996 IX86_BUILTIN_VBROADCASTPD256,
27997 IX86_BUILTIN_VBROADCASTPS256,
27998 IX86_BUILTIN_VINSERTF128PD256,
27999 IX86_BUILTIN_VINSERTF128PS256,
28000 IX86_BUILTIN_VINSERTF128SI256,
28001 IX86_BUILTIN_LOADUPD256,
28002 IX86_BUILTIN_LOADUPS256,
28003 IX86_BUILTIN_STOREUPD256,
28004 IX86_BUILTIN_STOREUPS256,
28005 IX86_BUILTIN_LDDQU256,
28006 IX86_BUILTIN_MOVNTDQ256,
28007 IX86_BUILTIN_MOVNTPD256,
28008 IX86_BUILTIN_MOVNTPS256,
28009 IX86_BUILTIN_LOADDQU256,
28010 IX86_BUILTIN_STOREDQU256,
28011 IX86_BUILTIN_MASKLOADPD,
28012 IX86_BUILTIN_MASKLOADPS,
28013 IX86_BUILTIN_MASKSTOREPD,
28014 IX86_BUILTIN_MASKSTOREPS,
28015 IX86_BUILTIN_MASKLOADPD256,
28016 IX86_BUILTIN_MASKLOADPS256,
28017 IX86_BUILTIN_MASKSTOREPD256,
28018 IX86_BUILTIN_MASKSTOREPS256,
28019 IX86_BUILTIN_MOVSHDUP256,
28020 IX86_BUILTIN_MOVSLDUP256,
28021 IX86_BUILTIN_MOVDDUP256,
28023 IX86_BUILTIN_SQRTPD256,
28024 IX86_BUILTIN_SQRTPS256,
28025 IX86_BUILTIN_SQRTPS_NR256,
28026 IX86_BUILTIN_RSQRTPS256,
28027 IX86_BUILTIN_RSQRTPS_NR256,
28029 IX86_BUILTIN_RCPPS256,
28031 IX86_BUILTIN_ROUNDPD256,
28032 IX86_BUILTIN_ROUNDPS256,
28034 IX86_BUILTIN_FLOORPD256,
28035 IX86_BUILTIN_CEILPD256,
28036 IX86_BUILTIN_TRUNCPD256,
28037 IX86_BUILTIN_RINTPD256,
28038 IX86_BUILTIN_ROUNDPD_AZ256,
28040 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28041 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28042 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28044 IX86_BUILTIN_FLOORPS256,
28045 IX86_BUILTIN_CEILPS256,
28046 IX86_BUILTIN_TRUNCPS256,
28047 IX86_BUILTIN_RINTPS256,
28048 IX86_BUILTIN_ROUNDPS_AZ256,
28050 IX86_BUILTIN_FLOORPS_SFIX256,
28051 IX86_BUILTIN_CEILPS_SFIX256,
28052 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28054 IX86_BUILTIN_UNPCKHPD256,
28055 IX86_BUILTIN_UNPCKLPD256,
28056 IX86_BUILTIN_UNPCKHPS256,
28057 IX86_BUILTIN_UNPCKLPS256,
28059 IX86_BUILTIN_SI256_SI,
28060 IX86_BUILTIN_PS256_PS,
28061 IX86_BUILTIN_PD256_PD,
28062 IX86_BUILTIN_SI_SI256,
28063 IX86_BUILTIN_PS_PS256,
28064 IX86_BUILTIN_PD_PD256,
28066 IX86_BUILTIN_VTESTZPD,
28067 IX86_BUILTIN_VTESTCPD,
28068 IX86_BUILTIN_VTESTNZCPD,
28069 IX86_BUILTIN_VTESTZPS,
28070 IX86_BUILTIN_VTESTCPS,
28071 IX86_BUILTIN_VTESTNZCPS,
28072 IX86_BUILTIN_VTESTZPD256,
28073 IX86_BUILTIN_VTESTCPD256,
28074 IX86_BUILTIN_VTESTNZCPD256,
28075 IX86_BUILTIN_VTESTZPS256,
28076 IX86_BUILTIN_VTESTCPS256,
28077 IX86_BUILTIN_VTESTNZCPS256,
28078 IX86_BUILTIN_PTESTZ256,
28079 IX86_BUILTIN_PTESTC256,
28080 IX86_BUILTIN_PTESTNZC256,
28082 IX86_BUILTIN_MOVMSKPD256,
28083 IX86_BUILTIN_MOVMSKPS256,
28085 /* AVX2 */
28086 IX86_BUILTIN_MPSADBW256,
28087 IX86_BUILTIN_PABSB256,
28088 IX86_BUILTIN_PABSW256,
28089 IX86_BUILTIN_PABSD256,
28090 IX86_BUILTIN_PACKSSDW256,
28091 IX86_BUILTIN_PACKSSWB256,
28092 IX86_BUILTIN_PACKUSDW256,
28093 IX86_BUILTIN_PACKUSWB256,
28094 IX86_BUILTIN_PADDB256,
28095 IX86_BUILTIN_PADDW256,
28096 IX86_BUILTIN_PADDD256,
28097 IX86_BUILTIN_PADDQ256,
28098 IX86_BUILTIN_PADDSB256,
28099 IX86_BUILTIN_PADDSW256,
28100 IX86_BUILTIN_PADDUSB256,
28101 IX86_BUILTIN_PADDUSW256,
28102 IX86_BUILTIN_PALIGNR256,
28103 IX86_BUILTIN_AND256I,
28104 IX86_BUILTIN_ANDNOT256I,
28105 IX86_BUILTIN_PAVGB256,
28106 IX86_BUILTIN_PAVGW256,
28107 IX86_BUILTIN_PBLENDVB256,
28108 IX86_BUILTIN_PBLENDVW256,
28109 IX86_BUILTIN_PCMPEQB256,
28110 IX86_BUILTIN_PCMPEQW256,
28111 IX86_BUILTIN_PCMPEQD256,
28112 IX86_BUILTIN_PCMPEQQ256,
28113 IX86_BUILTIN_PCMPGTB256,
28114 IX86_BUILTIN_PCMPGTW256,
28115 IX86_BUILTIN_PCMPGTD256,
28116 IX86_BUILTIN_PCMPGTQ256,
28117 IX86_BUILTIN_PHADDW256,
28118 IX86_BUILTIN_PHADDD256,
28119 IX86_BUILTIN_PHADDSW256,
28120 IX86_BUILTIN_PHSUBW256,
28121 IX86_BUILTIN_PHSUBD256,
28122 IX86_BUILTIN_PHSUBSW256,
28123 IX86_BUILTIN_PMADDUBSW256,
28124 IX86_BUILTIN_PMADDWD256,
28125 IX86_BUILTIN_PMAXSB256,
28126 IX86_BUILTIN_PMAXSW256,
28127 IX86_BUILTIN_PMAXSD256,
28128 IX86_BUILTIN_PMAXUB256,
28129 IX86_BUILTIN_PMAXUW256,
28130 IX86_BUILTIN_PMAXUD256,
28131 IX86_BUILTIN_PMINSB256,
28132 IX86_BUILTIN_PMINSW256,
28133 IX86_BUILTIN_PMINSD256,
28134 IX86_BUILTIN_PMINUB256,
28135 IX86_BUILTIN_PMINUW256,
28136 IX86_BUILTIN_PMINUD256,
28137 IX86_BUILTIN_PMOVMSKB256,
28138 IX86_BUILTIN_PMOVSXBW256,
28139 IX86_BUILTIN_PMOVSXBD256,
28140 IX86_BUILTIN_PMOVSXBQ256,
28141 IX86_BUILTIN_PMOVSXWD256,
28142 IX86_BUILTIN_PMOVSXWQ256,
28143 IX86_BUILTIN_PMOVSXDQ256,
28144 IX86_BUILTIN_PMOVZXBW256,
28145 IX86_BUILTIN_PMOVZXBD256,
28146 IX86_BUILTIN_PMOVZXBQ256,
28147 IX86_BUILTIN_PMOVZXWD256,
28148 IX86_BUILTIN_PMOVZXWQ256,
28149 IX86_BUILTIN_PMOVZXDQ256,
28150 IX86_BUILTIN_PMULDQ256,
28151 IX86_BUILTIN_PMULHRSW256,
28152 IX86_BUILTIN_PMULHUW256,
28153 IX86_BUILTIN_PMULHW256,
28154 IX86_BUILTIN_PMULLW256,
28155 IX86_BUILTIN_PMULLD256,
28156 IX86_BUILTIN_PMULUDQ256,
28157 IX86_BUILTIN_POR256,
28158 IX86_BUILTIN_PSADBW256,
28159 IX86_BUILTIN_PSHUFB256,
28160 IX86_BUILTIN_PSHUFD256,
28161 IX86_BUILTIN_PSHUFHW256,
28162 IX86_BUILTIN_PSHUFLW256,
28163 IX86_BUILTIN_PSIGNB256,
28164 IX86_BUILTIN_PSIGNW256,
28165 IX86_BUILTIN_PSIGND256,
28166 IX86_BUILTIN_PSLLDQI256,
28167 IX86_BUILTIN_PSLLWI256,
28168 IX86_BUILTIN_PSLLW256,
28169 IX86_BUILTIN_PSLLDI256,
28170 IX86_BUILTIN_PSLLD256,
28171 IX86_BUILTIN_PSLLQI256,
28172 IX86_BUILTIN_PSLLQ256,
28173 IX86_BUILTIN_PSRAWI256,
28174 IX86_BUILTIN_PSRAW256,
28175 IX86_BUILTIN_PSRADI256,
28176 IX86_BUILTIN_PSRAD256,
28177 IX86_BUILTIN_PSRLDQI256,
28178 IX86_BUILTIN_PSRLWI256,
28179 IX86_BUILTIN_PSRLW256,
28180 IX86_BUILTIN_PSRLDI256,
28181 IX86_BUILTIN_PSRLD256,
28182 IX86_BUILTIN_PSRLQI256,
28183 IX86_BUILTIN_PSRLQ256,
28184 IX86_BUILTIN_PSUBB256,
28185 IX86_BUILTIN_PSUBW256,
28186 IX86_BUILTIN_PSUBD256,
28187 IX86_BUILTIN_PSUBQ256,
28188 IX86_BUILTIN_PSUBSB256,
28189 IX86_BUILTIN_PSUBSW256,
28190 IX86_BUILTIN_PSUBUSB256,
28191 IX86_BUILTIN_PSUBUSW256,
28192 IX86_BUILTIN_PUNPCKHBW256,
28193 IX86_BUILTIN_PUNPCKHWD256,
28194 IX86_BUILTIN_PUNPCKHDQ256,
28195 IX86_BUILTIN_PUNPCKHQDQ256,
28196 IX86_BUILTIN_PUNPCKLBW256,
28197 IX86_BUILTIN_PUNPCKLWD256,
28198 IX86_BUILTIN_PUNPCKLDQ256,
28199 IX86_BUILTIN_PUNPCKLQDQ256,
28200 IX86_BUILTIN_PXOR256,
28201 IX86_BUILTIN_MOVNTDQA256,
28202 IX86_BUILTIN_VBROADCASTSS_PS,
28203 IX86_BUILTIN_VBROADCASTSS_PS256,
28204 IX86_BUILTIN_VBROADCASTSD_PD256,
28205 IX86_BUILTIN_VBROADCASTSI256,
28206 IX86_BUILTIN_PBLENDD256,
28207 IX86_BUILTIN_PBLENDD128,
28208 IX86_BUILTIN_PBROADCASTB256,
28209 IX86_BUILTIN_PBROADCASTW256,
28210 IX86_BUILTIN_PBROADCASTD256,
28211 IX86_BUILTIN_PBROADCASTQ256,
28212 IX86_BUILTIN_PBROADCASTB128,
28213 IX86_BUILTIN_PBROADCASTW128,
28214 IX86_BUILTIN_PBROADCASTD128,
28215 IX86_BUILTIN_PBROADCASTQ128,
28216 IX86_BUILTIN_VPERMVARSI256,
28217 IX86_BUILTIN_VPERMDF256,
28218 IX86_BUILTIN_VPERMVARSF256,
28219 IX86_BUILTIN_VPERMDI256,
28220 IX86_BUILTIN_VPERMTI256,
28221 IX86_BUILTIN_VEXTRACT128I256,
28222 IX86_BUILTIN_VINSERT128I256,
28223 IX86_BUILTIN_MASKLOADD,
28224 IX86_BUILTIN_MASKLOADQ,
28225 IX86_BUILTIN_MASKLOADD256,
28226 IX86_BUILTIN_MASKLOADQ256,
28227 IX86_BUILTIN_MASKSTORED,
28228 IX86_BUILTIN_MASKSTOREQ,
28229 IX86_BUILTIN_MASKSTORED256,
28230 IX86_BUILTIN_MASKSTOREQ256,
28231 IX86_BUILTIN_PSLLVV4DI,
28232 IX86_BUILTIN_PSLLVV2DI,
28233 IX86_BUILTIN_PSLLVV8SI,
28234 IX86_BUILTIN_PSLLVV4SI,
28235 IX86_BUILTIN_PSRAVV8SI,
28236 IX86_BUILTIN_PSRAVV4SI,
28237 IX86_BUILTIN_PSRLVV4DI,
28238 IX86_BUILTIN_PSRLVV2DI,
28239 IX86_BUILTIN_PSRLVV8SI,
28240 IX86_BUILTIN_PSRLVV4SI,
28242 IX86_BUILTIN_GATHERSIV2DF,
28243 IX86_BUILTIN_GATHERSIV4DF,
28244 IX86_BUILTIN_GATHERDIV2DF,
28245 IX86_BUILTIN_GATHERDIV4DF,
28246 IX86_BUILTIN_GATHERSIV4SF,
28247 IX86_BUILTIN_GATHERSIV8SF,
28248 IX86_BUILTIN_GATHERDIV4SF,
28249 IX86_BUILTIN_GATHERDIV8SF,
28250 IX86_BUILTIN_GATHERSIV2DI,
28251 IX86_BUILTIN_GATHERSIV4DI,
28252 IX86_BUILTIN_GATHERDIV2DI,
28253 IX86_BUILTIN_GATHERDIV4DI,
28254 IX86_BUILTIN_GATHERSIV4SI,
28255 IX86_BUILTIN_GATHERSIV8SI,
28256 IX86_BUILTIN_GATHERDIV4SI,
28257 IX86_BUILTIN_GATHERDIV8SI,
28259 /* AVX512F */
28260 IX86_BUILTIN_ADDPD512,
28261 IX86_BUILTIN_ADDPS512,
28262 IX86_BUILTIN_ADDSD_ROUND,
28263 IX86_BUILTIN_ADDSS_ROUND,
28264 IX86_BUILTIN_ALIGND512,
28265 IX86_BUILTIN_ALIGNQ512,
28266 IX86_BUILTIN_BLENDMD512,
28267 IX86_BUILTIN_BLENDMPD512,
28268 IX86_BUILTIN_BLENDMPS512,
28269 IX86_BUILTIN_BLENDMQ512,
28270 IX86_BUILTIN_BROADCASTF32X4_512,
28271 IX86_BUILTIN_BROADCASTF64X4_512,
28272 IX86_BUILTIN_BROADCASTI32X4_512,
28273 IX86_BUILTIN_BROADCASTI64X4_512,
28274 IX86_BUILTIN_BROADCASTSD512,
28275 IX86_BUILTIN_BROADCASTSS512,
28276 IX86_BUILTIN_CMPD512,
28277 IX86_BUILTIN_CMPPD512,
28278 IX86_BUILTIN_CMPPS512,
28279 IX86_BUILTIN_CMPQ512,
28280 IX86_BUILTIN_CMPSD_MASK,
28281 IX86_BUILTIN_CMPSS_MASK,
28282 IX86_BUILTIN_COMIDF,
28283 IX86_BUILTIN_COMISF,
28284 IX86_BUILTIN_COMPRESSPD512,
28285 IX86_BUILTIN_COMPRESSPDSTORE512,
28286 IX86_BUILTIN_COMPRESSPS512,
28287 IX86_BUILTIN_COMPRESSPSSTORE512,
28288 IX86_BUILTIN_CVTDQ2PD512,
28289 IX86_BUILTIN_CVTDQ2PS512,
28290 IX86_BUILTIN_CVTPD2DQ512,
28291 IX86_BUILTIN_CVTPD2PS512,
28292 IX86_BUILTIN_CVTPD2UDQ512,
28293 IX86_BUILTIN_CVTPH2PS512,
28294 IX86_BUILTIN_CVTPS2DQ512,
28295 IX86_BUILTIN_CVTPS2PD512,
28296 IX86_BUILTIN_CVTPS2PH512,
28297 IX86_BUILTIN_CVTPS2UDQ512,
28298 IX86_BUILTIN_CVTSD2SS_ROUND,
28299 IX86_BUILTIN_CVTSI2SD64,
28300 IX86_BUILTIN_CVTSI2SS32,
28301 IX86_BUILTIN_CVTSI2SS64,
28302 IX86_BUILTIN_CVTSS2SD_ROUND,
28303 IX86_BUILTIN_CVTTPD2DQ512,
28304 IX86_BUILTIN_CVTTPD2UDQ512,
28305 IX86_BUILTIN_CVTTPS2DQ512,
28306 IX86_BUILTIN_CVTTPS2UDQ512,
28307 IX86_BUILTIN_CVTUDQ2PD512,
28308 IX86_BUILTIN_CVTUDQ2PS512,
28309 IX86_BUILTIN_CVTUSI2SD32,
28310 IX86_BUILTIN_CVTUSI2SD64,
28311 IX86_BUILTIN_CVTUSI2SS32,
28312 IX86_BUILTIN_CVTUSI2SS64,
28313 IX86_BUILTIN_DIVPD512,
28314 IX86_BUILTIN_DIVPS512,
28315 IX86_BUILTIN_DIVSD_ROUND,
28316 IX86_BUILTIN_DIVSS_ROUND,
28317 IX86_BUILTIN_EXPANDPD512,
28318 IX86_BUILTIN_EXPANDPD512Z,
28319 IX86_BUILTIN_EXPANDPDLOAD512,
28320 IX86_BUILTIN_EXPANDPDLOAD512Z,
28321 IX86_BUILTIN_EXPANDPS512,
28322 IX86_BUILTIN_EXPANDPS512Z,
28323 IX86_BUILTIN_EXPANDPSLOAD512,
28324 IX86_BUILTIN_EXPANDPSLOAD512Z,
28325 IX86_BUILTIN_EXTRACTF32X4,
28326 IX86_BUILTIN_EXTRACTF64X4,
28327 IX86_BUILTIN_EXTRACTI32X4,
28328 IX86_BUILTIN_EXTRACTI64X4,
28329 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28330 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28331 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28332 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28333 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28334 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28335 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28336 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28337 IX86_BUILTIN_GETEXPPD512,
28338 IX86_BUILTIN_GETEXPPS512,
28339 IX86_BUILTIN_GETEXPSD128,
28340 IX86_BUILTIN_GETEXPSS128,
28341 IX86_BUILTIN_GETMANTPD512,
28342 IX86_BUILTIN_GETMANTPS512,
28343 IX86_BUILTIN_GETMANTSD128,
28344 IX86_BUILTIN_GETMANTSS128,
28345 IX86_BUILTIN_INSERTF32X4,
28346 IX86_BUILTIN_INSERTF64X4,
28347 IX86_BUILTIN_INSERTI32X4,
28348 IX86_BUILTIN_INSERTI64X4,
28349 IX86_BUILTIN_LOADAPD512,
28350 IX86_BUILTIN_LOADAPS512,
28351 IX86_BUILTIN_LOADDQUDI512,
28352 IX86_BUILTIN_LOADDQUSI512,
28353 IX86_BUILTIN_LOADUPD512,
28354 IX86_BUILTIN_LOADUPS512,
28355 IX86_BUILTIN_MAXPD512,
28356 IX86_BUILTIN_MAXPS512,
28357 IX86_BUILTIN_MAXSD_ROUND,
28358 IX86_BUILTIN_MAXSS_ROUND,
28359 IX86_BUILTIN_MINPD512,
28360 IX86_BUILTIN_MINPS512,
28361 IX86_BUILTIN_MINSD_ROUND,
28362 IX86_BUILTIN_MINSS_ROUND,
28363 IX86_BUILTIN_MOVAPD512,
28364 IX86_BUILTIN_MOVAPS512,
28365 IX86_BUILTIN_MOVDDUP512,
28366 IX86_BUILTIN_MOVDQA32LOAD512,
28367 IX86_BUILTIN_MOVDQA32STORE512,
28368 IX86_BUILTIN_MOVDQA32_512,
28369 IX86_BUILTIN_MOVDQA64LOAD512,
28370 IX86_BUILTIN_MOVDQA64STORE512,
28371 IX86_BUILTIN_MOVDQA64_512,
28372 IX86_BUILTIN_MOVNTDQ512,
28373 IX86_BUILTIN_MOVNTDQA512,
28374 IX86_BUILTIN_MOVNTPD512,
28375 IX86_BUILTIN_MOVNTPS512,
28376 IX86_BUILTIN_MOVSHDUP512,
28377 IX86_BUILTIN_MOVSLDUP512,
28378 IX86_BUILTIN_MULPD512,
28379 IX86_BUILTIN_MULPS512,
28380 IX86_BUILTIN_MULSD_ROUND,
28381 IX86_BUILTIN_MULSS_ROUND,
28382 IX86_BUILTIN_PABSD512,
28383 IX86_BUILTIN_PABSQ512,
28384 IX86_BUILTIN_PADDD512,
28385 IX86_BUILTIN_PADDQ512,
28386 IX86_BUILTIN_PANDD512,
28387 IX86_BUILTIN_PANDND512,
28388 IX86_BUILTIN_PANDNQ512,
28389 IX86_BUILTIN_PANDQ512,
28390 IX86_BUILTIN_PBROADCASTD512,
28391 IX86_BUILTIN_PBROADCASTD512_GPR,
28392 IX86_BUILTIN_PBROADCASTMB512,
28393 IX86_BUILTIN_PBROADCASTMW512,
28394 IX86_BUILTIN_PBROADCASTQ512,
28395 IX86_BUILTIN_PBROADCASTQ512_GPR,
28396 IX86_BUILTIN_PBROADCASTQ512_MEM,
28397 IX86_BUILTIN_PCMPEQD512_MASK,
28398 IX86_BUILTIN_PCMPEQQ512_MASK,
28399 IX86_BUILTIN_PCMPGTD512_MASK,
28400 IX86_BUILTIN_PCMPGTQ512_MASK,
28401 IX86_BUILTIN_PCOMPRESSD512,
28402 IX86_BUILTIN_PCOMPRESSDSTORE512,
28403 IX86_BUILTIN_PCOMPRESSQ512,
28404 IX86_BUILTIN_PCOMPRESSQSTORE512,
28405 IX86_BUILTIN_PEXPANDD512,
28406 IX86_BUILTIN_PEXPANDD512Z,
28407 IX86_BUILTIN_PEXPANDDLOAD512,
28408 IX86_BUILTIN_PEXPANDDLOAD512Z,
28409 IX86_BUILTIN_PEXPANDQ512,
28410 IX86_BUILTIN_PEXPANDQ512Z,
28411 IX86_BUILTIN_PEXPANDQLOAD512,
28412 IX86_BUILTIN_PEXPANDQLOAD512Z,
28413 IX86_BUILTIN_PMAXSD512,
28414 IX86_BUILTIN_PMAXSQ512,
28415 IX86_BUILTIN_PMAXUD512,
28416 IX86_BUILTIN_PMAXUQ512,
28417 IX86_BUILTIN_PMINSD512,
28418 IX86_BUILTIN_PMINSQ512,
28419 IX86_BUILTIN_PMINUD512,
28420 IX86_BUILTIN_PMINUQ512,
28421 IX86_BUILTIN_PMOVDB512,
28422 IX86_BUILTIN_PMOVDB512_MEM,
28423 IX86_BUILTIN_PMOVDW512,
28424 IX86_BUILTIN_PMOVDW512_MEM,
28425 IX86_BUILTIN_PMOVQB512,
28426 IX86_BUILTIN_PMOVQB512_MEM,
28427 IX86_BUILTIN_PMOVQD512,
28428 IX86_BUILTIN_PMOVQD512_MEM,
28429 IX86_BUILTIN_PMOVQW512,
28430 IX86_BUILTIN_PMOVQW512_MEM,
28431 IX86_BUILTIN_PMOVSDB512,
28432 IX86_BUILTIN_PMOVSDB512_MEM,
28433 IX86_BUILTIN_PMOVSDW512,
28434 IX86_BUILTIN_PMOVSDW512_MEM,
28435 IX86_BUILTIN_PMOVSQB512,
28436 IX86_BUILTIN_PMOVSQB512_MEM,
28437 IX86_BUILTIN_PMOVSQD512,
28438 IX86_BUILTIN_PMOVSQD512_MEM,
28439 IX86_BUILTIN_PMOVSQW512,
28440 IX86_BUILTIN_PMOVSQW512_MEM,
28441 IX86_BUILTIN_PMOVSXBD512,
28442 IX86_BUILTIN_PMOVSXBQ512,
28443 IX86_BUILTIN_PMOVSXDQ512,
28444 IX86_BUILTIN_PMOVSXWD512,
28445 IX86_BUILTIN_PMOVSXWQ512,
28446 IX86_BUILTIN_PMOVUSDB512,
28447 IX86_BUILTIN_PMOVUSDB512_MEM,
28448 IX86_BUILTIN_PMOVUSDW512,
28449 IX86_BUILTIN_PMOVUSDW512_MEM,
28450 IX86_BUILTIN_PMOVUSQB512,
28451 IX86_BUILTIN_PMOVUSQB512_MEM,
28452 IX86_BUILTIN_PMOVUSQD512,
28453 IX86_BUILTIN_PMOVUSQD512_MEM,
28454 IX86_BUILTIN_PMOVUSQW512,
28455 IX86_BUILTIN_PMOVUSQW512_MEM,
28456 IX86_BUILTIN_PMOVZXBD512,
28457 IX86_BUILTIN_PMOVZXBQ512,
28458 IX86_BUILTIN_PMOVZXDQ512,
28459 IX86_BUILTIN_PMOVZXWD512,
28460 IX86_BUILTIN_PMOVZXWQ512,
28461 IX86_BUILTIN_PMULDQ512,
28462 IX86_BUILTIN_PMULLD512,
28463 IX86_BUILTIN_PMULUDQ512,
28464 IX86_BUILTIN_PORD512,
28465 IX86_BUILTIN_PORQ512,
28466 IX86_BUILTIN_PROLD512,
28467 IX86_BUILTIN_PROLQ512,
28468 IX86_BUILTIN_PROLVD512,
28469 IX86_BUILTIN_PROLVQ512,
28470 IX86_BUILTIN_PRORD512,
28471 IX86_BUILTIN_PRORQ512,
28472 IX86_BUILTIN_PRORVD512,
28473 IX86_BUILTIN_PRORVQ512,
28474 IX86_BUILTIN_PSHUFD512,
28475 IX86_BUILTIN_PSLLD512,
28476 IX86_BUILTIN_PSLLDI512,
28477 IX86_BUILTIN_PSLLQ512,
28478 IX86_BUILTIN_PSLLQI512,
28479 IX86_BUILTIN_PSLLVV16SI,
28480 IX86_BUILTIN_PSLLVV8DI,
28481 IX86_BUILTIN_PSRAD512,
28482 IX86_BUILTIN_PSRADI512,
28483 IX86_BUILTIN_PSRAQ512,
28484 IX86_BUILTIN_PSRAQI512,
28485 IX86_BUILTIN_PSRAVV16SI,
28486 IX86_BUILTIN_PSRAVV8DI,
28487 IX86_BUILTIN_PSRLD512,
28488 IX86_BUILTIN_PSRLDI512,
28489 IX86_BUILTIN_PSRLQ512,
28490 IX86_BUILTIN_PSRLQI512,
28491 IX86_BUILTIN_PSRLVV16SI,
28492 IX86_BUILTIN_PSRLVV8DI,
28493 IX86_BUILTIN_PSUBD512,
28494 IX86_BUILTIN_PSUBQ512,
28495 IX86_BUILTIN_PTESTMD512,
28496 IX86_BUILTIN_PTESTMQ512,
28497 IX86_BUILTIN_PTESTNMD512,
28498 IX86_BUILTIN_PTESTNMQ512,
28499 IX86_BUILTIN_PUNPCKHDQ512,
28500 IX86_BUILTIN_PUNPCKHQDQ512,
28501 IX86_BUILTIN_PUNPCKLDQ512,
28502 IX86_BUILTIN_PUNPCKLQDQ512,
28503 IX86_BUILTIN_PXORD512,
28504 IX86_BUILTIN_PXORQ512,
28505 IX86_BUILTIN_RCP14PD512,
28506 IX86_BUILTIN_RCP14PS512,
28507 IX86_BUILTIN_RCP14SD,
28508 IX86_BUILTIN_RCP14SS,
28509 IX86_BUILTIN_RNDSCALEPD,
28510 IX86_BUILTIN_RNDSCALEPS,
28511 IX86_BUILTIN_RNDSCALESD,
28512 IX86_BUILTIN_RNDSCALESS,
28513 IX86_BUILTIN_RSQRT14PD512,
28514 IX86_BUILTIN_RSQRT14PS512,
28515 IX86_BUILTIN_RSQRT14SD,
28516 IX86_BUILTIN_RSQRT14SS,
28517 IX86_BUILTIN_SCALEFPD512,
28518 IX86_BUILTIN_SCALEFPS512,
28519 IX86_BUILTIN_SCALEFSD,
28520 IX86_BUILTIN_SCALEFSS,
28521 IX86_BUILTIN_SHUFPD512,
28522 IX86_BUILTIN_SHUFPS512,
28523 IX86_BUILTIN_SHUF_F32x4,
28524 IX86_BUILTIN_SHUF_F64x2,
28525 IX86_BUILTIN_SHUF_I32x4,
28526 IX86_BUILTIN_SHUF_I64x2,
28527 IX86_BUILTIN_SQRTPD512,
28528 IX86_BUILTIN_SQRTPD512_MASK,
28529 IX86_BUILTIN_SQRTPS512_MASK,
28530 IX86_BUILTIN_SQRTPS_NR512,
28531 IX86_BUILTIN_SQRTSD_ROUND,
28532 IX86_BUILTIN_SQRTSS_ROUND,
28533 IX86_BUILTIN_STOREAPD512,
28534 IX86_BUILTIN_STOREAPS512,
28535 IX86_BUILTIN_STOREDQUDI512,
28536 IX86_BUILTIN_STOREDQUSI512,
28537 IX86_BUILTIN_STOREUPD512,
28538 IX86_BUILTIN_STOREUPS512,
28539 IX86_BUILTIN_SUBPD512,
28540 IX86_BUILTIN_SUBPS512,
28541 IX86_BUILTIN_SUBSD_ROUND,
28542 IX86_BUILTIN_SUBSS_ROUND,
28543 IX86_BUILTIN_UCMPD512,
28544 IX86_BUILTIN_UCMPQ512,
28545 IX86_BUILTIN_UNPCKHPD512,
28546 IX86_BUILTIN_UNPCKHPS512,
28547 IX86_BUILTIN_UNPCKLPD512,
28548 IX86_BUILTIN_UNPCKLPS512,
28549 IX86_BUILTIN_VCVTSD2SI32,
28550 IX86_BUILTIN_VCVTSD2SI64,
28551 IX86_BUILTIN_VCVTSD2USI32,
28552 IX86_BUILTIN_VCVTSD2USI64,
28553 IX86_BUILTIN_VCVTSS2SI32,
28554 IX86_BUILTIN_VCVTSS2SI64,
28555 IX86_BUILTIN_VCVTSS2USI32,
28556 IX86_BUILTIN_VCVTSS2USI64,
28557 IX86_BUILTIN_VCVTTSD2SI32,
28558 IX86_BUILTIN_VCVTTSD2SI64,
28559 IX86_BUILTIN_VCVTTSD2USI32,
28560 IX86_BUILTIN_VCVTTSD2USI64,
28561 IX86_BUILTIN_VCVTTSS2SI32,
28562 IX86_BUILTIN_VCVTTSS2SI64,
28563 IX86_BUILTIN_VCVTTSS2USI32,
28564 IX86_BUILTIN_VCVTTSS2USI64,
28565 IX86_BUILTIN_VFMADDPD512_MASK,
28566 IX86_BUILTIN_VFMADDPD512_MASK3,
28567 IX86_BUILTIN_VFMADDPD512_MASKZ,
28568 IX86_BUILTIN_VFMADDPS512_MASK,
28569 IX86_BUILTIN_VFMADDPS512_MASK3,
28570 IX86_BUILTIN_VFMADDPS512_MASKZ,
28571 IX86_BUILTIN_VFMADDSD3_ROUND,
28572 IX86_BUILTIN_VFMADDSS3_ROUND,
28573 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28574 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28575 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28576 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28577 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28578 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28579 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28580 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28581 IX86_BUILTIN_VFMSUBPD512_MASK3,
28582 IX86_BUILTIN_VFMSUBPS512_MASK3,
28583 IX86_BUILTIN_VFMSUBSD3_MASK3,
28584 IX86_BUILTIN_VFMSUBSS3_MASK3,
28585 IX86_BUILTIN_VFNMADDPD512_MASK,
28586 IX86_BUILTIN_VFNMADDPS512_MASK,
28587 IX86_BUILTIN_VFNMSUBPD512_MASK,
28588 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28589 IX86_BUILTIN_VFNMSUBPS512_MASK,
28590 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28591 IX86_BUILTIN_VPCLZCNTD512,
28592 IX86_BUILTIN_VPCLZCNTQ512,
28593 IX86_BUILTIN_VPCONFLICTD512,
28594 IX86_BUILTIN_VPCONFLICTQ512,
28595 IX86_BUILTIN_VPERMDF512,
28596 IX86_BUILTIN_VPERMDI512,
28597 IX86_BUILTIN_VPERMI2VARD512,
28598 IX86_BUILTIN_VPERMI2VARPD512,
28599 IX86_BUILTIN_VPERMI2VARPS512,
28600 IX86_BUILTIN_VPERMI2VARQ512,
28601 IX86_BUILTIN_VPERMILPD512,
28602 IX86_BUILTIN_VPERMILPS512,
28603 IX86_BUILTIN_VPERMILVARPD512,
28604 IX86_BUILTIN_VPERMILVARPS512,
28605 IX86_BUILTIN_VPERMT2VARD512,
28606 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28607 IX86_BUILTIN_VPERMT2VARPD512,
28608 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28609 IX86_BUILTIN_VPERMT2VARPS512,
28610 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28611 IX86_BUILTIN_VPERMT2VARQ512,
28612 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28613 IX86_BUILTIN_VPERMVARDF512,
28614 IX86_BUILTIN_VPERMVARDI512,
28615 IX86_BUILTIN_VPERMVARSF512,
28616 IX86_BUILTIN_VPERMVARSI512,
28617 IX86_BUILTIN_VTERNLOGD512_MASK,
28618 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28619 IX86_BUILTIN_VTERNLOGQ512_MASK,
28620 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28622 /* Mask arithmetic operations */
28623 IX86_BUILTIN_KAND16,
28624 IX86_BUILTIN_KANDN16,
28625 IX86_BUILTIN_KNOT16,
28626 IX86_BUILTIN_KOR16,
28627 IX86_BUILTIN_KORTESTC16,
28628 IX86_BUILTIN_KORTESTZ16,
28629 IX86_BUILTIN_KUNPCKBW,
28630 IX86_BUILTIN_KXNOR16,
28631 IX86_BUILTIN_KXOR16,
28632 IX86_BUILTIN_KMOV16,
28634 /* AVX512VL. */
28635 IX86_BUILTIN_PMOVUSQD256_MEM,
28636 IX86_BUILTIN_PMOVUSQD128_MEM,
28637 IX86_BUILTIN_PMOVSQD256_MEM,
28638 IX86_BUILTIN_PMOVSQD128_MEM,
28639 IX86_BUILTIN_PMOVQD256_MEM,
28640 IX86_BUILTIN_PMOVQD128_MEM,
28641 IX86_BUILTIN_PMOVUSQW256_MEM,
28642 IX86_BUILTIN_PMOVUSQW128_MEM,
28643 IX86_BUILTIN_PMOVSQW256_MEM,
28644 IX86_BUILTIN_PMOVSQW128_MEM,
28645 IX86_BUILTIN_PMOVQW256_MEM,
28646 IX86_BUILTIN_PMOVQW128_MEM,
28647 IX86_BUILTIN_PMOVUSQB256_MEM,
28648 IX86_BUILTIN_PMOVUSQB128_MEM,
28649 IX86_BUILTIN_PMOVSQB256_MEM,
28650 IX86_BUILTIN_PMOVSQB128_MEM,
28651 IX86_BUILTIN_PMOVQB256_MEM,
28652 IX86_BUILTIN_PMOVQB128_MEM,
28653 IX86_BUILTIN_PMOVUSDW256_MEM,
28654 IX86_BUILTIN_PMOVUSDW128_MEM,
28655 IX86_BUILTIN_PMOVSDW256_MEM,
28656 IX86_BUILTIN_PMOVSDW128_MEM,
28657 IX86_BUILTIN_PMOVDW256_MEM,
28658 IX86_BUILTIN_PMOVDW128_MEM,
28659 IX86_BUILTIN_PMOVUSDB256_MEM,
28660 IX86_BUILTIN_PMOVUSDB128_MEM,
28661 IX86_BUILTIN_PMOVSDB256_MEM,
28662 IX86_BUILTIN_PMOVSDB128_MEM,
28663 IX86_BUILTIN_PMOVDB256_MEM,
28664 IX86_BUILTIN_PMOVDB128_MEM,
28665 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
28666 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
28667 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
28668 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
28669 IX86_BUILTIN_MOVDQA64STORE256_MASK,
28670 IX86_BUILTIN_MOVDQA64STORE128_MASK,
28671 IX86_BUILTIN_MOVDQA32STORE256_MASK,
28672 IX86_BUILTIN_MOVDQA32STORE128_MASK,
28673 IX86_BUILTIN_LOADAPD256_MASK,
28674 IX86_BUILTIN_LOADAPD128_MASK,
28675 IX86_BUILTIN_LOADAPS256_MASK,
28676 IX86_BUILTIN_LOADAPS128_MASK,
28677 IX86_BUILTIN_STOREAPD256_MASK,
28678 IX86_BUILTIN_STOREAPD128_MASK,
28679 IX86_BUILTIN_STOREAPS256_MASK,
28680 IX86_BUILTIN_STOREAPS128_MASK,
28681 IX86_BUILTIN_LOADUPD256_MASK,
28682 IX86_BUILTIN_LOADUPD128_MASK,
28683 IX86_BUILTIN_LOADUPS256_MASK,
28684 IX86_BUILTIN_LOADUPS128_MASK,
28685 IX86_BUILTIN_STOREUPD256_MASK,
28686 IX86_BUILTIN_STOREUPD128_MASK,
28687 IX86_BUILTIN_STOREUPS256_MASK,
28688 IX86_BUILTIN_STOREUPS128_MASK,
28689 IX86_BUILTIN_LOADDQUDI256_MASK,
28690 IX86_BUILTIN_LOADDQUDI128_MASK,
28691 IX86_BUILTIN_LOADDQUSI256_MASK,
28692 IX86_BUILTIN_LOADDQUSI128_MASK,
28693 IX86_BUILTIN_LOADDQUHI256_MASK,
28694 IX86_BUILTIN_LOADDQUHI128_MASK,
28695 IX86_BUILTIN_LOADDQUQI256_MASK,
28696 IX86_BUILTIN_LOADDQUQI128_MASK,
28697 IX86_BUILTIN_STOREDQUDI256_MASK,
28698 IX86_BUILTIN_STOREDQUDI128_MASK,
28699 IX86_BUILTIN_STOREDQUSI256_MASK,
28700 IX86_BUILTIN_STOREDQUSI128_MASK,
28701 IX86_BUILTIN_STOREDQUHI256_MASK,
28702 IX86_BUILTIN_STOREDQUHI128_MASK,
28703 IX86_BUILTIN_STOREDQUQI256_MASK,
28704 IX86_BUILTIN_STOREDQUQI128_MASK,
28705 IX86_BUILTIN_COMPRESSPDSTORE256,
28706 IX86_BUILTIN_COMPRESSPDSTORE128,
28707 IX86_BUILTIN_COMPRESSPSSTORE256,
28708 IX86_BUILTIN_COMPRESSPSSTORE128,
28709 IX86_BUILTIN_PCOMPRESSQSTORE256,
28710 IX86_BUILTIN_PCOMPRESSQSTORE128,
28711 IX86_BUILTIN_PCOMPRESSDSTORE256,
28712 IX86_BUILTIN_PCOMPRESSDSTORE128,
28713 IX86_BUILTIN_EXPANDPDLOAD256,
28714 IX86_BUILTIN_EXPANDPDLOAD128,
28715 IX86_BUILTIN_EXPANDPSLOAD256,
28716 IX86_BUILTIN_EXPANDPSLOAD128,
28717 IX86_BUILTIN_PEXPANDQLOAD256,
28718 IX86_BUILTIN_PEXPANDQLOAD128,
28719 IX86_BUILTIN_PEXPANDDLOAD256,
28720 IX86_BUILTIN_PEXPANDDLOAD128,
28721 IX86_BUILTIN_EXPANDPDLOAD256Z,
28722 IX86_BUILTIN_EXPANDPDLOAD128Z,
28723 IX86_BUILTIN_EXPANDPSLOAD256Z,
28724 IX86_BUILTIN_EXPANDPSLOAD128Z,
28725 IX86_BUILTIN_PEXPANDQLOAD256Z,
28726 IX86_BUILTIN_PEXPANDQLOAD128Z,
28727 IX86_BUILTIN_PEXPANDDLOAD256Z,
28728 IX86_BUILTIN_PEXPANDDLOAD128Z,
28729 IX86_BUILTIN_PALIGNR256_MASK,
28730 IX86_BUILTIN_PALIGNR128_MASK,
28731 IX86_BUILTIN_MOVDQA64_256_MASK,
28732 IX86_BUILTIN_MOVDQA64_128_MASK,
28733 IX86_BUILTIN_MOVDQA32_256_MASK,
28734 IX86_BUILTIN_MOVDQA32_128_MASK,
28735 IX86_BUILTIN_MOVAPD256_MASK,
28736 IX86_BUILTIN_MOVAPD128_MASK,
28737 IX86_BUILTIN_MOVAPS256_MASK,
28738 IX86_BUILTIN_MOVAPS128_MASK,
28739 IX86_BUILTIN_MOVDQUHI256_MASK,
28740 IX86_BUILTIN_MOVDQUHI128_MASK,
28741 IX86_BUILTIN_MOVDQUQI256_MASK,
28742 IX86_BUILTIN_MOVDQUQI128_MASK,
28743 IX86_BUILTIN_MINPS128_MASK,
28744 IX86_BUILTIN_MAXPS128_MASK,
28745 IX86_BUILTIN_MINPD128_MASK,
28746 IX86_BUILTIN_MAXPD128_MASK,
28747 IX86_BUILTIN_MAXPD256_MASK,
28748 IX86_BUILTIN_MAXPS256_MASK,
28749 IX86_BUILTIN_MINPD256_MASK,
28750 IX86_BUILTIN_MINPS256_MASK,
28751 IX86_BUILTIN_MULPS128_MASK,
28752 IX86_BUILTIN_DIVPS128_MASK,
28753 IX86_BUILTIN_MULPD128_MASK,
28754 IX86_BUILTIN_DIVPD128_MASK,
28755 IX86_BUILTIN_DIVPD256_MASK,
28756 IX86_BUILTIN_DIVPS256_MASK,
28757 IX86_BUILTIN_MULPD256_MASK,
28758 IX86_BUILTIN_MULPS256_MASK,
28759 IX86_BUILTIN_ADDPD128_MASK,
28760 IX86_BUILTIN_ADDPD256_MASK,
28761 IX86_BUILTIN_ADDPS128_MASK,
28762 IX86_BUILTIN_ADDPS256_MASK,
28763 IX86_BUILTIN_SUBPD128_MASK,
28764 IX86_BUILTIN_SUBPD256_MASK,
28765 IX86_BUILTIN_SUBPS128_MASK,
28766 IX86_BUILTIN_SUBPS256_MASK,
28767 IX86_BUILTIN_XORPD256_MASK,
28768 IX86_BUILTIN_XORPD128_MASK,
28769 IX86_BUILTIN_XORPS256_MASK,
28770 IX86_BUILTIN_XORPS128_MASK,
28771 IX86_BUILTIN_ORPD256_MASK,
28772 IX86_BUILTIN_ORPD128_MASK,
28773 IX86_BUILTIN_ORPS256_MASK,
28774 IX86_BUILTIN_ORPS128_MASK,
28775 IX86_BUILTIN_BROADCASTF32x2_256,
28776 IX86_BUILTIN_BROADCASTI32x2_256,
28777 IX86_BUILTIN_BROADCASTI32x2_128,
28778 IX86_BUILTIN_BROADCASTF64X2_256,
28779 IX86_BUILTIN_BROADCASTI64X2_256,
28780 IX86_BUILTIN_BROADCASTF32X4_256,
28781 IX86_BUILTIN_BROADCASTI32X4_256,
28782 IX86_BUILTIN_EXTRACTF32X4_256,
28783 IX86_BUILTIN_EXTRACTI32X4_256,
28784 IX86_BUILTIN_DBPSADBW256,
28785 IX86_BUILTIN_DBPSADBW128,
28786 IX86_BUILTIN_CVTTPD2QQ256,
28787 IX86_BUILTIN_CVTTPD2QQ128,
28788 IX86_BUILTIN_CVTTPD2UQQ256,
28789 IX86_BUILTIN_CVTTPD2UQQ128,
28790 IX86_BUILTIN_CVTPD2QQ256,
28791 IX86_BUILTIN_CVTPD2QQ128,
28792 IX86_BUILTIN_CVTPD2UQQ256,
28793 IX86_BUILTIN_CVTPD2UQQ128,
28794 IX86_BUILTIN_CVTPD2UDQ256_MASK,
28795 IX86_BUILTIN_CVTPD2UDQ128_MASK,
28796 IX86_BUILTIN_CVTTPS2QQ256,
28797 IX86_BUILTIN_CVTTPS2QQ128,
28798 IX86_BUILTIN_CVTTPS2UQQ256,
28799 IX86_BUILTIN_CVTTPS2UQQ128,
28800 IX86_BUILTIN_CVTTPS2DQ256_MASK,
28801 IX86_BUILTIN_CVTTPS2DQ128_MASK,
28802 IX86_BUILTIN_CVTTPS2UDQ256,
28803 IX86_BUILTIN_CVTTPS2UDQ128,
28804 IX86_BUILTIN_CVTTPD2DQ256_MASK,
28805 IX86_BUILTIN_CVTTPD2DQ128_MASK,
28806 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
28807 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
28808 IX86_BUILTIN_CVTPD2DQ256_MASK,
28809 IX86_BUILTIN_CVTPD2DQ128_MASK,
28810 IX86_BUILTIN_CVTDQ2PD256_MASK,
28811 IX86_BUILTIN_CVTDQ2PD128_MASK,
28812 IX86_BUILTIN_CVTUDQ2PD256_MASK,
28813 IX86_BUILTIN_CVTUDQ2PD128_MASK,
28814 IX86_BUILTIN_CVTDQ2PS256_MASK,
28815 IX86_BUILTIN_CVTDQ2PS128_MASK,
28816 IX86_BUILTIN_CVTUDQ2PS256_MASK,
28817 IX86_BUILTIN_CVTUDQ2PS128_MASK,
28818 IX86_BUILTIN_CVTPS2PD256_MASK,
28819 IX86_BUILTIN_CVTPS2PD128_MASK,
28820 IX86_BUILTIN_PBROADCASTB256_MASK,
28821 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
28822 IX86_BUILTIN_PBROADCASTB128_MASK,
28823 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
28824 IX86_BUILTIN_PBROADCASTW256_MASK,
28825 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
28826 IX86_BUILTIN_PBROADCASTW128_MASK,
28827 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
28828 IX86_BUILTIN_PBROADCASTD256_MASK,
28829 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
28830 IX86_BUILTIN_PBROADCASTD128_MASK,
28831 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
28832 IX86_BUILTIN_PBROADCASTQ256_MASK,
28833 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
28834 IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
28835 IX86_BUILTIN_PBROADCASTQ128_MASK,
28836 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
28837 IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
28838 IX86_BUILTIN_BROADCASTSS256,
28839 IX86_BUILTIN_BROADCASTSS128,
28840 IX86_BUILTIN_BROADCASTSD256,
28841 IX86_BUILTIN_EXTRACTF64X2_256,
28842 IX86_BUILTIN_EXTRACTI64X2_256,
28843 IX86_BUILTIN_INSERTF32X4_256,
28844 IX86_BUILTIN_INSERTI32X4_256,
28845 IX86_BUILTIN_PMOVSXBW256_MASK,
28846 IX86_BUILTIN_PMOVSXBW128_MASK,
28847 IX86_BUILTIN_PMOVSXBD256_MASK,
28848 IX86_BUILTIN_PMOVSXBD128_MASK,
28849 IX86_BUILTIN_PMOVSXBQ256_MASK,
28850 IX86_BUILTIN_PMOVSXBQ128_MASK,
28851 IX86_BUILTIN_PMOVSXWD256_MASK,
28852 IX86_BUILTIN_PMOVSXWD128_MASK,
28853 IX86_BUILTIN_PMOVSXWQ256_MASK,
28854 IX86_BUILTIN_PMOVSXWQ128_MASK,
28855 IX86_BUILTIN_PMOVSXDQ256_MASK,
28856 IX86_BUILTIN_PMOVSXDQ128_MASK,
28857 IX86_BUILTIN_PMOVZXBW256_MASK,
28858 IX86_BUILTIN_PMOVZXBW128_MASK,
28859 IX86_BUILTIN_PMOVZXBD256_MASK,
28860 IX86_BUILTIN_PMOVZXBD128_MASK,
28861 IX86_BUILTIN_PMOVZXBQ256_MASK,
28862 IX86_BUILTIN_PMOVZXBQ128_MASK,
28863 IX86_BUILTIN_PMOVZXWD256_MASK,
28864 IX86_BUILTIN_PMOVZXWD128_MASK,
28865 IX86_BUILTIN_PMOVZXWQ256_MASK,
28866 IX86_BUILTIN_PMOVZXWQ128_MASK,
28867 IX86_BUILTIN_PMOVZXDQ256_MASK,
28868 IX86_BUILTIN_PMOVZXDQ128_MASK,
28869 IX86_BUILTIN_REDUCEPD256_MASK,
28870 IX86_BUILTIN_REDUCEPD128_MASK,
28871 IX86_BUILTIN_REDUCEPS256_MASK,
28872 IX86_BUILTIN_REDUCEPS128_MASK,
28873 IX86_BUILTIN_REDUCESD_MASK,
28874 IX86_BUILTIN_REDUCESS_MASK,
28875 IX86_BUILTIN_VPERMVARHI256_MASK,
28876 IX86_BUILTIN_VPERMVARHI128_MASK,
28877 IX86_BUILTIN_VPERMT2VARHI256,
28878 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
28879 IX86_BUILTIN_VPERMT2VARHI128,
28880 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
28881 IX86_BUILTIN_VPERMI2VARHI256,
28882 IX86_BUILTIN_VPERMI2VARHI128,
28883 IX86_BUILTIN_RCP14PD256,
28884 IX86_BUILTIN_RCP14PD128,
28885 IX86_BUILTIN_RCP14PS256,
28886 IX86_BUILTIN_RCP14PS128,
28887 IX86_BUILTIN_RSQRT14PD256_MASK,
28888 IX86_BUILTIN_RSQRT14PD128_MASK,
28889 IX86_BUILTIN_RSQRT14PS256_MASK,
28890 IX86_BUILTIN_RSQRT14PS128_MASK,
28891 IX86_BUILTIN_SQRTPD256_MASK,
28892 IX86_BUILTIN_SQRTPD128_MASK,
28893 IX86_BUILTIN_SQRTPS256_MASK,
28894 IX86_BUILTIN_SQRTPS128_MASK,
28895 IX86_BUILTIN_PADDB128_MASK,
28896 IX86_BUILTIN_PADDW128_MASK,
28897 IX86_BUILTIN_PADDD128_MASK,
28898 IX86_BUILTIN_PADDQ128_MASK,
28899 IX86_BUILTIN_PSUBB128_MASK,
28900 IX86_BUILTIN_PSUBW128_MASK,
28901 IX86_BUILTIN_PSUBD128_MASK,
28902 IX86_BUILTIN_PSUBQ128_MASK,
28903 IX86_BUILTIN_PADDSB128_MASK,
28904 IX86_BUILTIN_PADDSW128_MASK,
28905 IX86_BUILTIN_PSUBSB128_MASK,
28906 IX86_BUILTIN_PSUBSW128_MASK,
28907 IX86_BUILTIN_PADDUSB128_MASK,
28908 IX86_BUILTIN_PADDUSW128_MASK,
28909 IX86_BUILTIN_PSUBUSB128_MASK,
28910 IX86_BUILTIN_PSUBUSW128_MASK,
28911 IX86_BUILTIN_PADDB256_MASK,
28912 IX86_BUILTIN_PADDW256_MASK,
28913 IX86_BUILTIN_PADDD256_MASK,
28914 IX86_BUILTIN_PADDQ256_MASK,
28915 IX86_BUILTIN_PADDSB256_MASK,
28916 IX86_BUILTIN_PADDSW256_MASK,
28917 IX86_BUILTIN_PADDUSB256_MASK,
28918 IX86_BUILTIN_PADDUSW256_MASK,
28919 IX86_BUILTIN_PSUBB256_MASK,
28920 IX86_BUILTIN_PSUBW256_MASK,
28921 IX86_BUILTIN_PSUBD256_MASK,
28922 IX86_BUILTIN_PSUBQ256_MASK,
28923 IX86_BUILTIN_PSUBSB256_MASK,
28924 IX86_BUILTIN_PSUBSW256_MASK,
28925 IX86_BUILTIN_PSUBUSB256_MASK,
28926 IX86_BUILTIN_PSUBUSW256_MASK,
28927 IX86_BUILTIN_SHUF_F64x2_256,
28928 IX86_BUILTIN_SHUF_I64x2_256,
28929 IX86_BUILTIN_SHUF_I32x4_256,
28930 IX86_BUILTIN_SHUF_F32x4_256,
28931 IX86_BUILTIN_PMOVWB128,
28932 IX86_BUILTIN_PMOVWB256,
28933 IX86_BUILTIN_PMOVSWB128,
28934 IX86_BUILTIN_PMOVSWB256,
28935 IX86_BUILTIN_PMOVUSWB128,
28936 IX86_BUILTIN_PMOVUSWB256,
28937 IX86_BUILTIN_PMOVDB128,
28938 IX86_BUILTIN_PMOVDB256,
28939 IX86_BUILTIN_PMOVSDB128,
28940 IX86_BUILTIN_PMOVSDB256,
28941 IX86_BUILTIN_PMOVUSDB128,
28942 IX86_BUILTIN_PMOVUSDB256,
28943 IX86_BUILTIN_PMOVDW128,
28944 IX86_BUILTIN_PMOVDW256,
28945 IX86_BUILTIN_PMOVSDW128,
28946 IX86_BUILTIN_PMOVSDW256,
28947 IX86_BUILTIN_PMOVUSDW128,
28948 IX86_BUILTIN_PMOVUSDW256,
28949 IX86_BUILTIN_PMOVQB128,
28950 IX86_BUILTIN_PMOVQB256,
28951 IX86_BUILTIN_PMOVSQB128,
28952 IX86_BUILTIN_PMOVSQB256,
28953 IX86_BUILTIN_PMOVUSQB128,
28954 IX86_BUILTIN_PMOVUSQB256,
28955 IX86_BUILTIN_PMOVQW128,
28956 IX86_BUILTIN_PMOVQW256,
28957 IX86_BUILTIN_PMOVSQW128,
28958 IX86_BUILTIN_PMOVSQW256,
28959 IX86_BUILTIN_PMOVUSQW128,
28960 IX86_BUILTIN_PMOVUSQW256,
28961 IX86_BUILTIN_PMOVQD128,
28962 IX86_BUILTIN_PMOVQD256,
28963 IX86_BUILTIN_PMOVSQD128,
28964 IX86_BUILTIN_PMOVSQD256,
28965 IX86_BUILTIN_PMOVUSQD128,
28966 IX86_BUILTIN_PMOVUSQD256,
28967 IX86_BUILTIN_RANGEPD256,
28968 IX86_BUILTIN_RANGEPD128,
28969 IX86_BUILTIN_RANGEPS256,
28970 IX86_BUILTIN_RANGEPS128,
28971 IX86_BUILTIN_GETEXPPS256,
28972 IX86_BUILTIN_GETEXPPD256,
28973 IX86_BUILTIN_GETEXPPS128,
28974 IX86_BUILTIN_GETEXPPD128,
28975 IX86_BUILTIN_FIXUPIMMPD256,
28976 IX86_BUILTIN_FIXUPIMMPD256_MASK,
28977 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
28978 IX86_BUILTIN_FIXUPIMMPS256,
28979 IX86_BUILTIN_FIXUPIMMPS256_MASK,
28980 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
28981 IX86_BUILTIN_FIXUPIMMPD128,
28982 IX86_BUILTIN_FIXUPIMMPD128_MASK,
28983 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
28984 IX86_BUILTIN_FIXUPIMMPS128,
28985 IX86_BUILTIN_FIXUPIMMPS128_MASK,
28986 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
28987 IX86_BUILTIN_PABSQ256,
28988 IX86_BUILTIN_PABSQ128,
28989 IX86_BUILTIN_PABSD256_MASK,
28990 IX86_BUILTIN_PABSD128_MASK,
28991 IX86_BUILTIN_PMULHRSW256_MASK,
28992 IX86_BUILTIN_PMULHRSW128_MASK,
28993 IX86_BUILTIN_PMULHUW128_MASK,
28994 IX86_BUILTIN_PMULHUW256_MASK,
28995 IX86_BUILTIN_PMULHW256_MASK,
28996 IX86_BUILTIN_PMULHW128_MASK,
28997 IX86_BUILTIN_PMULLW256_MASK,
28998 IX86_BUILTIN_PMULLW128_MASK,
28999 IX86_BUILTIN_PMULLQ256,
29000 IX86_BUILTIN_PMULLQ128,
29001 IX86_BUILTIN_ANDPD256_MASK,
29002 IX86_BUILTIN_ANDPD128_MASK,
29003 IX86_BUILTIN_ANDPS256_MASK,
29004 IX86_BUILTIN_ANDPS128_MASK,
29005 IX86_BUILTIN_ANDNPD256_MASK,
29006 IX86_BUILTIN_ANDNPD128_MASK,
29007 IX86_BUILTIN_ANDNPS256_MASK,
29008 IX86_BUILTIN_ANDNPS128_MASK,
29009 IX86_BUILTIN_PSLLWI128_MASK,
29010 IX86_BUILTIN_PSLLDI128_MASK,
29011 IX86_BUILTIN_PSLLQI128_MASK,
29012 IX86_BUILTIN_PSLLW128_MASK,
29013 IX86_BUILTIN_PSLLD128_MASK,
29014 IX86_BUILTIN_PSLLQ128_MASK,
29015 IX86_BUILTIN_PSLLWI256_MASK ,
29016 IX86_BUILTIN_PSLLW256_MASK,
29017 IX86_BUILTIN_PSLLDI256_MASK,
29018 IX86_BUILTIN_PSLLD256_MASK,
29019 IX86_BUILTIN_PSLLQI256_MASK,
29020 IX86_BUILTIN_PSLLQ256_MASK,
29021 IX86_BUILTIN_PSRADI128_MASK,
29022 IX86_BUILTIN_PSRAD128_MASK,
29023 IX86_BUILTIN_PSRADI256_MASK,
29024 IX86_BUILTIN_PSRAD256_MASK,
29025 IX86_BUILTIN_PSRAQI128_MASK,
29026 IX86_BUILTIN_PSRAQ128_MASK,
29027 IX86_BUILTIN_PSRAQI256_MASK,
29028 IX86_BUILTIN_PSRAQ256_MASK,
29029 IX86_BUILTIN_PANDD256,
29030 IX86_BUILTIN_PANDD128,
29031 IX86_BUILTIN_PSRLDI128_MASK,
29032 IX86_BUILTIN_PSRLD128_MASK,
29033 IX86_BUILTIN_PSRLDI256_MASK,
29034 IX86_BUILTIN_PSRLD256_MASK,
29035 IX86_BUILTIN_PSRLQI128_MASK,
29036 IX86_BUILTIN_PSRLQ128_MASK,
29037 IX86_BUILTIN_PSRLQI256_MASK,
29038 IX86_BUILTIN_PSRLQ256_MASK,
29039 IX86_BUILTIN_PANDQ256,
29040 IX86_BUILTIN_PANDQ128,
29041 IX86_BUILTIN_PANDND256,
29042 IX86_BUILTIN_PANDND128,
29043 IX86_BUILTIN_PANDNQ256,
29044 IX86_BUILTIN_PANDNQ128,
29045 IX86_BUILTIN_PORD256,
29046 IX86_BUILTIN_PORD128,
29047 IX86_BUILTIN_PORQ256,
29048 IX86_BUILTIN_PORQ128,
29049 IX86_BUILTIN_PXORD256,
29050 IX86_BUILTIN_PXORD128,
29051 IX86_BUILTIN_PXORQ256,
29052 IX86_BUILTIN_PXORQ128,
29053 IX86_BUILTIN_PACKSSWB256_MASK,
29054 IX86_BUILTIN_PACKSSWB128_MASK,
29055 IX86_BUILTIN_PACKUSWB256_MASK,
29056 IX86_BUILTIN_PACKUSWB128_MASK,
29057 IX86_BUILTIN_RNDSCALEPS256,
29058 IX86_BUILTIN_RNDSCALEPD256,
29059 IX86_BUILTIN_RNDSCALEPS128,
29060 IX86_BUILTIN_RNDSCALEPD128,
29061 IX86_BUILTIN_VTERNLOGQ256_MASK,
29062 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29063 IX86_BUILTIN_VTERNLOGD256_MASK,
29064 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29065 IX86_BUILTIN_VTERNLOGQ128_MASK,
29066 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29067 IX86_BUILTIN_VTERNLOGD128_MASK,
29068 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29069 IX86_BUILTIN_SCALEFPD256,
29070 IX86_BUILTIN_SCALEFPS256,
29071 IX86_BUILTIN_SCALEFPD128,
29072 IX86_BUILTIN_SCALEFPS128,
29073 IX86_BUILTIN_VFMADDPD256_MASK,
29074 IX86_BUILTIN_VFMADDPD256_MASK3,
29075 IX86_BUILTIN_VFMADDPD256_MASKZ,
29076 IX86_BUILTIN_VFMADDPD128_MASK,
29077 IX86_BUILTIN_VFMADDPD128_MASK3,
29078 IX86_BUILTIN_VFMADDPD128_MASKZ,
29079 IX86_BUILTIN_VFMADDPS256_MASK,
29080 IX86_BUILTIN_VFMADDPS256_MASK3,
29081 IX86_BUILTIN_VFMADDPS256_MASKZ,
29082 IX86_BUILTIN_VFMADDPS128_MASK,
29083 IX86_BUILTIN_VFMADDPS128_MASK3,
29084 IX86_BUILTIN_VFMADDPS128_MASKZ,
29085 IX86_BUILTIN_VFMSUBPD256_MASK3,
29086 IX86_BUILTIN_VFMSUBPD128_MASK3,
29087 IX86_BUILTIN_VFMSUBPS256_MASK3,
29088 IX86_BUILTIN_VFMSUBPS128_MASK3,
29089 IX86_BUILTIN_VFNMADDPD256_MASK,
29090 IX86_BUILTIN_VFNMADDPD128_MASK,
29091 IX86_BUILTIN_VFNMADDPS256_MASK,
29092 IX86_BUILTIN_VFNMADDPS128_MASK,
29093 IX86_BUILTIN_VFNMSUBPD256_MASK,
29094 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29095 IX86_BUILTIN_VFNMSUBPD128_MASK,
29096 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29097 IX86_BUILTIN_VFNMSUBPS256_MASK,
29098 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29099 IX86_BUILTIN_VFNMSUBPS128_MASK,
29100 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29101 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29102 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29103 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29104 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29105 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29106 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29107 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29108 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29109 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29110 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29111 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29112 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29113 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29114 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29115 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29116 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29117 IX86_BUILTIN_INSERTF64X2_256,
29118 IX86_BUILTIN_INSERTI64X2_256,
29119 IX86_BUILTIN_PSRAVV16HI,
29120 IX86_BUILTIN_PSRAVV8HI,
29121 IX86_BUILTIN_PMADDUBSW256_MASK,
29122 IX86_BUILTIN_PMADDUBSW128_MASK,
29123 IX86_BUILTIN_PMADDWD256_MASK,
29124 IX86_BUILTIN_PMADDWD128_MASK,
29125 IX86_BUILTIN_PSRLVV16HI,
29126 IX86_BUILTIN_PSRLVV8HI,
29127 IX86_BUILTIN_CVTPS2DQ256_MASK,
29128 IX86_BUILTIN_CVTPS2DQ128_MASK,
29129 IX86_BUILTIN_CVTPS2UDQ256,
29130 IX86_BUILTIN_CVTPS2UDQ128,
29131 IX86_BUILTIN_CVTPS2QQ256,
29132 IX86_BUILTIN_CVTPS2QQ128,
29133 IX86_BUILTIN_CVTPS2UQQ256,
29134 IX86_BUILTIN_CVTPS2UQQ128,
29135 IX86_BUILTIN_GETMANTPS256,
29136 IX86_BUILTIN_GETMANTPS128,
29137 IX86_BUILTIN_GETMANTPD256,
29138 IX86_BUILTIN_GETMANTPD128,
29139 IX86_BUILTIN_MOVDDUP256_MASK,
29140 IX86_BUILTIN_MOVDDUP128_MASK,
29141 IX86_BUILTIN_MOVSHDUP256_MASK,
29142 IX86_BUILTIN_MOVSHDUP128_MASK,
29143 IX86_BUILTIN_MOVSLDUP256_MASK,
29144 IX86_BUILTIN_MOVSLDUP128_MASK,
29145 IX86_BUILTIN_CVTQQ2PS256,
29146 IX86_BUILTIN_CVTQQ2PS128,
29147 IX86_BUILTIN_CVTUQQ2PS256,
29148 IX86_BUILTIN_CVTUQQ2PS128,
29149 IX86_BUILTIN_CVTQQ2PD256,
29150 IX86_BUILTIN_CVTQQ2PD128,
29151 IX86_BUILTIN_CVTUQQ2PD256,
29152 IX86_BUILTIN_CVTUQQ2PD128,
29153 IX86_BUILTIN_VPERMT2VARQ256,
29154 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29155 IX86_BUILTIN_VPERMT2VARD256,
29156 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29157 IX86_BUILTIN_VPERMI2VARQ256,
29158 IX86_BUILTIN_VPERMI2VARD256,
29159 IX86_BUILTIN_VPERMT2VARPD256,
29160 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29161 IX86_BUILTIN_VPERMT2VARPS256,
29162 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29163 IX86_BUILTIN_VPERMI2VARPD256,
29164 IX86_BUILTIN_VPERMI2VARPS256,
29165 IX86_BUILTIN_VPERMT2VARQ128,
29166 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29167 IX86_BUILTIN_VPERMT2VARD128,
29168 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29169 IX86_BUILTIN_VPERMI2VARQ128,
29170 IX86_BUILTIN_VPERMI2VARD128,
29171 IX86_BUILTIN_VPERMT2VARPD128,
29172 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29173 IX86_BUILTIN_VPERMT2VARPS128,
29174 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29175 IX86_BUILTIN_VPERMI2VARPD128,
29176 IX86_BUILTIN_VPERMI2VARPS128,
29177 IX86_BUILTIN_PSHUFB256_MASK,
29178 IX86_BUILTIN_PSHUFB128_MASK,
29179 IX86_BUILTIN_PSHUFHW256_MASK,
29180 IX86_BUILTIN_PSHUFHW128_MASK,
29181 IX86_BUILTIN_PSHUFLW256_MASK,
29182 IX86_BUILTIN_PSHUFLW128_MASK,
29183 IX86_BUILTIN_PSHUFD256_MASK,
29184 IX86_BUILTIN_PSHUFD128_MASK,
29185 IX86_BUILTIN_SHUFPD256_MASK,
29186 IX86_BUILTIN_SHUFPD128_MASK,
29187 IX86_BUILTIN_SHUFPS256_MASK,
29188 IX86_BUILTIN_SHUFPS128_MASK,
29189 IX86_BUILTIN_PROLVQ256,
29190 IX86_BUILTIN_PROLVQ128,
29191 IX86_BUILTIN_PROLQ256,
29192 IX86_BUILTIN_PROLQ128,
29193 IX86_BUILTIN_PRORVQ256,
29194 IX86_BUILTIN_PRORVQ128,
29195 IX86_BUILTIN_PRORQ256,
29196 IX86_BUILTIN_PRORQ128,
29197 IX86_BUILTIN_PSRAVQ128,
29198 IX86_BUILTIN_PSRAVQ256,
29199 IX86_BUILTIN_PSLLVV4DI_MASK,
29200 IX86_BUILTIN_PSLLVV2DI_MASK,
29201 IX86_BUILTIN_PSLLVV8SI_MASK,
29202 IX86_BUILTIN_PSLLVV4SI_MASK,
29203 IX86_BUILTIN_PSRAVV8SI_MASK,
29204 IX86_BUILTIN_PSRAVV4SI_MASK,
29205 IX86_BUILTIN_PSRLVV4DI_MASK,
29206 IX86_BUILTIN_PSRLVV2DI_MASK,
29207 IX86_BUILTIN_PSRLVV8SI_MASK,
29208 IX86_BUILTIN_PSRLVV4SI_MASK,
29209 IX86_BUILTIN_PSRAWI256_MASK,
29210 IX86_BUILTIN_PSRAW256_MASK,
29211 IX86_BUILTIN_PSRAWI128_MASK,
29212 IX86_BUILTIN_PSRAW128_MASK,
29213 IX86_BUILTIN_PSRLWI256_MASK,
29214 IX86_BUILTIN_PSRLW256_MASK,
29215 IX86_BUILTIN_PSRLWI128_MASK,
29216 IX86_BUILTIN_PSRLW128_MASK,
29217 IX86_BUILTIN_PRORVD256,
29218 IX86_BUILTIN_PROLVD256,
29219 IX86_BUILTIN_PRORD256,
29220 IX86_BUILTIN_PROLD256,
29221 IX86_BUILTIN_PRORVD128,
29222 IX86_BUILTIN_PROLVD128,
29223 IX86_BUILTIN_PRORD128,
29224 IX86_BUILTIN_PROLD128,
29225 IX86_BUILTIN_FPCLASSPD256,
29226 IX86_BUILTIN_FPCLASSPD128,
29227 IX86_BUILTIN_FPCLASSSD,
29228 IX86_BUILTIN_FPCLASSPS256,
29229 IX86_BUILTIN_FPCLASSPS128,
29230 IX86_BUILTIN_FPCLASSSS,
29231 IX86_BUILTIN_CVTB2MASK128,
29232 IX86_BUILTIN_CVTB2MASK256,
29233 IX86_BUILTIN_CVTW2MASK128,
29234 IX86_BUILTIN_CVTW2MASK256,
29235 IX86_BUILTIN_CVTD2MASK128,
29236 IX86_BUILTIN_CVTD2MASK256,
29237 IX86_BUILTIN_CVTQ2MASK128,
29238 IX86_BUILTIN_CVTQ2MASK256,
29239 IX86_BUILTIN_CVTMASK2B128,
29240 IX86_BUILTIN_CVTMASK2B256,
29241 IX86_BUILTIN_CVTMASK2W128,
29242 IX86_BUILTIN_CVTMASK2W256,
29243 IX86_BUILTIN_CVTMASK2D128,
29244 IX86_BUILTIN_CVTMASK2D256,
29245 IX86_BUILTIN_CVTMASK2Q128,
29246 IX86_BUILTIN_CVTMASK2Q256,
29247 IX86_BUILTIN_PCMPEQB128_MASK,
29248 IX86_BUILTIN_PCMPEQB256_MASK,
29249 IX86_BUILTIN_PCMPEQW128_MASK,
29250 IX86_BUILTIN_PCMPEQW256_MASK,
29251 IX86_BUILTIN_PCMPEQD128_MASK,
29252 IX86_BUILTIN_PCMPEQD256_MASK,
29253 IX86_BUILTIN_PCMPEQQ128_MASK,
29254 IX86_BUILTIN_PCMPEQQ256_MASK,
29255 IX86_BUILTIN_PCMPGTB128_MASK,
29256 IX86_BUILTIN_PCMPGTB256_MASK,
29257 IX86_BUILTIN_PCMPGTW128_MASK,
29258 IX86_BUILTIN_PCMPGTW256_MASK,
29259 IX86_BUILTIN_PCMPGTD128_MASK,
29260 IX86_BUILTIN_PCMPGTD256_MASK,
29261 IX86_BUILTIN_PCMPGTQ128_MASK,
29262 IX86_BUILTIN_PCMPGTQ256_MASK,
29263 IX86_BUILTIN_PTESTMB128,
29264 IX86_BUILTIN_PTESTMB256,
29265 IX86_BUILTIN_PTESTMW128,
29266 IX86_BUILTIN_PTESTMW256,
29267 IX86_BUILTIN_PTESTMD128,
29268 IX86_BUILTIN_PTESTMD256,
29269 IX86_BUILTIN_PTESTMQ128,
29270 IX86_BUILTIN_PTESTMQ256,
29271 IX86_BUILTIN_PTESTNMB128,
29272 IX86_BUILTIN_PTESTNMB256,
29273 IX86_BUILTIN_PTESTNMW128,
29274 IX86_BUILTIN_PTESTNMW256,
29275 IX86_BUILTIN_PTESTNMD128,
29276 IX86_BUILTIN_PTESTNMD256,
29277 IX86_BUILTIN_PTESTNMQ128,
29278 IX86_BUILTIN_PTESTNMQ256,
29279 IX86_BUILTIN_PBROADCASTMB128,
29280 IX86_BUILTIN_PBROADCASTMB256,
29281 IX86_BUILTIN_PBROADCASTMW128,
29282 IX86_BUILTIN_PBROADCASTMW256,
29283 IX86_BUILTIN_COMPRESSPD256,
29284 IX86_BUILTIN_COMPRESSPD128,
29285 IX86_BUILTIN_COMPRESSPS256,
29286 IX86_BUILTIN_COMPRESSPS128,
29287 IX86_BUILTIN_PCOMPRESSQ256,
29288 IX86_BUILTIN_PCOMPRESSQ128,
29289 IX86_BUILTIN_PCOMPRESSD256,
29290 IX86_BUILTIN_PCOMPRESSD128,
29291 IX86_BUILTIN_EXPANDPD256,
29292 IX86_BUILTIN_EXPANDPD128,
29293 IX86_BUILTIN_EXPANDPS256,
29294 IX86_BUILTIN_EXPANDPS128,
29295 IX86_BUILTIN_PEXPANDQ256,
29296 IX86_BUILTIN_PEXPANDQ128,
29297 IX86_BUILTIN_PEXPANDD256,
29298 IX86_BUILTIN_PEXPANDD128,
29299 IX86_BUILTIN_EXPANDPD256Z,
29300 IX86_BUILTIN_EXPANDPD128Z,
29301 IX86_BUILTIN_EXPANDPS256Z,
29302 IX86_BUILTIN_EXPANDPS128Z,
29303 IX86_BUILTIN_PEXPANDQ256Z,
29304 IX86_BUILTIN_PEXPANDQ128Z,
29305 IX86_BUILTIN_PEXPANDD256Z,
29306 IX86_BUILTIN_PEXPANDD128Z,
29307 IX86_BUILTIN_PMAXSD256_MASK,
29308 IX86_BUILTIN_PMINSD256_MASK,
29309 IX86_BUILTIN_PMAXUD256_MASK,
29310 IX86_BUILTIN_PMINUD256_MASK,
29311 IX86_BUILTIN_PMAXSD128_MASK,
29312 IX86_BUILTIN_PMINSD128_MASK,
29313 IX86_BUILTIN_PMAXUD128_MASK,
29314 IX86_BUILTIN_PMINUD128_MASK,
29315 IX86_BUILTIN_PMAXSQ256_MASK,
29316 IX86_BUILTIN_PMINSQ256_MASK,
29317 IX86_BUILTIN_PMAXUQ256_MASK,
29318 IX86_BUILTIN_PMINUQ256_MASK,
29319 IX86_BUILTIN_PMAXSQ128_MASK,
29320 IX86_BUILTIN_PMINSQ128_MASK,
29321 IX86_BUILTIN_PMAXUQ128_MASK,
29322 IX86_BUILTIN_PMINUQ128_MASK,
29323 IX86_BUILTIN_PMINSB256_MASK,
29324 IX86_BUILTIN_PMINUB256_MASK,
29325 IX86_BUILTIN_PMAXSB256_MASK,
29326 IX86_BUILTIN_PMAXUB256_MASK,
29327 IX86_BUILTIN_PMINSB128_MASK,
29328 IX86_BUILTIN_PMINUB128_MASK,
29329 IX86_BUILTIN_PMAXSB128_MASK,
29330 IX86_BUILTIN_PMAXUB128_MASK,
29331 IX86_BUILTIN_PMINSW256_MASK,
29332 IX86_BUILTIN_PMINUW256_MASK,
29333 IX86_BUILTIN_PMAXSW256_MASK,
29334 IX86_BUILTIN_PMAXUW256_MASK,
29335 IX86_BUILTIN_PMINSW128_MASK,
29336 IX86_BUILTIN_PMINUW128_MASK,
29337 IX86_BUILTIN_PMAXSW128_MASK,
29338 IX86_BUILTIN_PMAXUW128_MASK,
29339 IX86_BUILTIN_VPCONFLICTQ256,
29340 IX86_BUILTIN_VPCONFLICTD256,
29341 IX86_BUILTIN_VPCLZCNTQ256,
29342 IX86_BUILTIN_VPCLZCNTD256,
29343 IX86_BUILTIN_UNPCKHPD256_MASK,
29344 IX86_BUILTIN_UNPCKHPD128_MASK,
29345 IX86_BUILTIN_UNPCKHPS256_MASK,
29346 IX86_BUILTIN_UNPCKHPS128_MASK,
29347 IX86_BUILTIN_UNPCKLPD256_MASK,
29348 IX86_BUILTIN_UNPCKLPD128_MASK,
29349 IX86_BUILTIN_UNPCKLPS256_MASK,
29350 IX86_BUILTIN_VPCONFLICTQ128,
29351 IX86_BUILTIN_VPCONFLICTD128,
29352 IX86_BUILTIN_VPCLZCNTQ128,
29353 IX86_BUILTIN_VPCLZCNTD128,
29354 IX86_BUILTIN_UNPCKLPS128_MASK,
29355 IX86_BUILTIN_ALIGND256,
29356 IX86_BUILTIN_ALIGNQ256,
29357 IX86_BUILTIN_ALIGND128,
29358 IX86_BUILTIN_ALIGNQ128,
29359 IX86_BUILTIN_CVTPS2PH256_MASK,
29360 IX86_BUILTIN_CVTPS2PH_MASK,
29361 IX86_BUILTIN_CVTPH2PS_MASK,
29362 IX86_BUILTIN_CVTPH2PS256_MASK,
29363 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29364 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29365 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29366 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29367 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29368 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29369 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29370 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29371 IX86_BUILTIN_PUNPCKHBW128_MASK,
29372 IX86_BUILTIN_PUNPCKHBW256_MASK,
29373 IX86_BUILTIN_PUNPCKHWD128_MASK,
29374 IX86_BUILTIN_PUNPCKHWD256_MASK,
29375 IX86_BUILTIN_PUNPCKLBW128_MASK,
29376 IX86_BUILTIN_PUNPCKLBW256_MASK,
29377 IX86_BUILTIN_PUNPCKLWD128_MASK,
29378 IX86_BUILTIN_PUNPCKLWD256_MASK,
29379 IX86_BUILTIN_PSLLVV16HI,
29380 IX86_BUILTIN_PSLLVV8HI,
29381 IX86_BUILTIN_PACKSSDW256_MASK,
29382 IX86_BUILTIN_PACKSSDW128_MASK,
29383 IX86_BUILTIN_PACKUSDW256_MASK,
29384 IX86_BUILTIN_PACKUSDW128_MASK,
29385 IX86_BUILTIN_PAVGB256_MASK,
29386 IX86_BUILTIN_PAVGW256_MASK,
29387 IX86_BUILTIN_PAVGB128_MASK,
29388 IX86_BUILTIN_PAVGW128_MASK,
29389 IX86_BUILTIN_VPERMVARSF256_MASK,
29390 IX86_BUILTIN_VPERMVARDF256_MASK,
29391 IX86_BUILTIN_VPERMDF256_MASK,
29392 IX86_BUILTIN_PABSB256_MASK,
29393 IX86_BUILTIN_PABSB128_MASK,
29394 IX86_BUILTIN_PABSW256_MASK,
29395 IX86_BUILTIN_PABSW128_MASK,
29396 IX86_BUILTIN_VPERMILVARPD_MASK,
29397 IX86_BUILTIN_VPERMILVARPS_MASK,
29398 IX86_BUILTIN_VPERMILVARPD256_MASK,
29399 IX86_BUILTIN_VPERMILVARPS256_MASK,
29400 IX86_BUILTIN_VPERMILPD_MASK,
29401 IX86_BUILTIN_VPERMILPS_MASK,
29402 IX86_BUILTIN_VPERMILPD256_MASK,
29403 IX86_BUILTIN_VPERMILPS256_MASK,
29404 IX86_BUILTIN_BLENDMQ256,
29405 IX86_BUILTIN_BLENDMD256,
29406 IX86_BUILTIN_BLENDMPD256,
29407 IX86_BUILTIN_BLENDMPS256,
29408 IX86_BUILTIN_BLENDMQ128,
29409 IX86_BUILTIN_BLENDMD128,
29410 IX86_BUILTIN_BLENDMPD128,
29411 IX86_BUILTIN_BLENDMPS128,
29412 IX86_BUILTIN_BLENDMW256,
29413 IX86_BUILTIN_BLENDMB256,
29414 IX86_BUILTIN_BLENDMW128,
29415 IX86_BUILTIN_BLENDMB128,
29416 IX86_BUILTIN_PMULLD256_MASK,
29417 IX86_BUILTIN_PMULLD128_MASK,
29418 IX86_BUILTIN_PMULUDQ256_MASK,
29419 IX86_BUILTIN_PMULDQ256_MASK,
29420 IX86_BUILTIN_PMULDQ128_MASK,
29421 IX86_BUILTIN_PMULUDQ128_MASK,
29422 IX86_BUILTIN_CVTPD2PS256_MASK,
29423 IX86_BUILTIN_CVTPD2PS_MASK,
29424 IX86_BUILTIN_VPERMVARSI256_MASK,
29425 IX86_BUILTIN_VPERMVARDI256_MASK,
29426 IX86_BUILTIN_VPERMDI256_MASK,
29427 IX86_BUILTIN_CMPQ256,
29428 IX86_BUILTIN_CMPD256,
29429 IX86_BUILTIN_UCMPQ256,
29430 IX86_BUILTIN_UCMPD256,
29431 IX86_BUILTIN_CMPB256,
29432 IX86_BUILTIN_CMPW256,
29433 IX86_BUILTIN_UCMPB256,
29434 IX86_BUILTIN_UCMPW256,
29435 IX86_BUILTIN_CMPPD256_MASK,
29436 IX86_BUILTIN_CMPPS256_MASK,
29437 IX86_BUILTIN_CMPQ128,
29438 IX86_BUILTIN_CMPD128,
29439 IX86_BUILTIN_UCMPQ128,
29440 IX86_BUILTIN_UCMPD128,
29441 IX86_BUILTIN_CMPB128,
29442 IX86_BUILTIN_CMPW128,
29443 IX86_BUILTIN_UCMPB128,
29444 IX86_BUILTIN_UCMPW128,
29445 IX86_BUILTIN_CMPPD128_MASK,
29446 IX86_BUILTIN_CMPPS128_MASK,
29448 IX86_BUILTIN_GATHER3SIV8SF,
29449 IX86_BUILTIN_GATHER3SIV4SF,
29450 IX86_BUILTIN_GATHER3SIV4DF,
29451 IX86_BUILTIN_GATHER3SIV2DF,
29452 IX86_BUILTIN_GATHER3DIV8SF,
29453 IX86_BUILTIN_GATHER3DIV4SF,
29454 IX86_BUILTIN_GATHER3DIV4DF,
29455 IX86_BUILTIN_GATHER3DIV2DF,
29456 IX86_BUILTIN_GATHER3SIV8SI,
29457 IX86_BUILTIN_GATHER3SIV4SI,
29458 IX86_BUILTIN_GATHER3SIV4DI,
29459 IX86_BUILTIN_GATHER3SIV2DI,
29460 IX86_BUILTIN_GATHER3DIV8SI,
29461 IX86_BUILTIN_GATHER3DIV4SI,
29462 IX86_BUILTIN_GATHER3DIV4DI,
29463 IX86_BUILTIN_GATHER3DIV2DI,
29464 IX86_BUILTIN_SCATTERSIV8SF,
29465 IX86_BUILTIN_SCATTERSIV4SF,
29466 IX86_BUILTIN_SCATTERSIV4DF,
29467 IX86_BUILTIN_SCATTERSIV2DF,
29468 IX86_BUILTIN_SCATTERDIV8SF,
29469 IX86_BUILTIN_SCATTERDIV4SF,
29470 IX86_BUILTIN_SCATTERDIV4DF,
29471 IX86_BUILTIN_SCATTERDIV2DF,
29472 IX86_BUILTIN_SCATTERSIV8SI,
29473 IX86_BUILTIN_SCATTERSIV4SI,
29474 IX86_BUILTIN_SCATTERSIV4DI,
29475 IX86_BUILTIN_SCATTERSIV2DI,
29476 IX86_BUILTIN_SCATTERDIV8SI,
29477 IX86_BUILTIN_SCATTERDIV4SI,
29478 IX86_BUILTIN_SCATTERDIV4DI,
29479 IX86_BUILTIN_SCATTERDIV2DI,
29481 /* AVX512DQ. */
29482 IX86_BUILTIN_RANGESD128,
29483 IX86_BUILTIN_RANGESS128,
29484 IX86_BUILTIN_KUNPCKWD,
29485 IX86_BUILTIN_KUNPCKDQ,
29486 IX86_BUILTIN_BROADCASTF32x2_512,
29487 IX86_BUILTIN_BROADCASTI32x2_512,
29488 IX86_BUILTIN_BROADCASTF64X2_512,
29489 IX86_BUILTIN_BROADCASTI64X2_512,
29490 IX86_BUILTIN_BROADCASTF32X8_512,
29491 IX86_BUILTIN_BROADCASTI32X8_512,
29492 IX86_BUILTIN_EXTRACTF64X2_512,
29493 IX86_BUILTIN_EXTRACTF32X8,
29494 IX86_BUILTIN_EXTRACTI64X2_512,
29495 IX86_BUILTIN_EXTRACTI32X8,
29496 IX86_BUILTIN_REDUCEPD512_MASK,
29497 IX86_BUILTIN_REDUCEPS512_MASK,
29498 IX86_BUILTIN_PMULLQ512,
29499 IX86_BUILTIN_XORPD512,
29500 IX86_BUILTIN_XORPS512,
29501 IX86_BUILTIN_ORPD512,
29502 IX86_BUILTIN_ORPS512,
29503 IX86_BUILTIN_ANDPD512,
29504 IX86_BUILTIN_ANDPS512,
29505 IX86_BUILTIN_ANDNPD512,
29506 IX86_BUILTIN_ANDNPS512,
29507 IX86_BUILTIN_INSERTF32X8,
29508 IX86_BUILTIN_INSERTI32X8,
29509 IX86_BUILTIN_INSERTF64X2_512,
29510 IX86_BUILTIN_INSERTI64X2_512,
29511 IX86_BUILTIN_FPCLASSPD512,
29512 IX86_BUILTIN_FPCLASSPS512,
29513 IX86_BUILTIN_CVTD2MASK512,
29514 IX86_BUILTIN_CVTQ2MASK512,
29515 IX86_BUILTIN_CVTMASK2D512,
29516 IX86_BUILTIN_CVTMASK2Q512,
29517 IX86_BUILTIN_CVTPD2QQ512,
29518 IX86_BUILTIN_CVTPS2QQ512,
29519 IX86_BUILTIN_CVTPD2UQQ512,
29520 IX86_BUILTIN_CVTPS2UQQ512,
29521 IX86_BUILTIN_CVTQQ2PS512,
29522 IX86_BUILTIN_CVTUQQ2PS512,
29523 IX86_BUILTIN_CVTQQ2PD512,
29524 IX86_BUILTIN_CVTUQQ2PD512,
29525 IX86_BUILTIN_CVTTPS2QQ512,
29526 IX86_BUILTIN_CVTTPS2UQQ512,
29527 IX86_BUILTIN_CVTTPD2QQ512,
29528 IX86_BUILTIN_CVTTPD2UQQ512,
29529 IX86_BUILTIN_RANGEPS512,
29530 IX86_BUILTIN_RANGEPD512,
29532 /* AVX512BW. */
29533 IX86_BUILTIN_PACKUSDW512,
29534 IX86_BUILTIN_PACKSSDW512,
29535 IX86_BUILTIN_LOADDQUHI512_MASK,
29536 IX86_BUILTIN_LOADDQUQI512_MASK,
29537 IX86_BUILTIN_PSLLDQ512,
29538 IX86_BUILTIN_PSRLDQ512,
29539 IX86_BUILTIN_STOREDQUHI512_MASK,
29540 IX86_BUILTIN_STOREDQUQI512_MASK,
29541 IX86_BUILTIN_PALIGNR512,
29542 IX86_BUILTIN_PALIGNR512_MASK,
29543 IX86_BUILTIN_MOVDQUHI512_MASK,
29544 IX86_BUILTIN_MOVDQUQI512_MASK,
29545 IX86_BUILTIN_PSADBW512,
29546 IX86_BUILTIN_DBPSADBW512,
29547 IX86_BUILTIN_PBROADCASTB512,
29548 IX86_BUILTIN_PBROADCASTB512_GPR,
29549 IX86_BUILTIN_PBROADCASTW512,
29550 IX86_BUILTIN_PBROADCASTW512_GPR,
29551 IX86_BUILTIN_PMOVSXBW512_MASK,
29552 IX86_BUILTIN_PMOVZXBW512_MASK,
29553 IX86_BUILTIN_VPERMVARHI512_MASK,
29554 IX86_BUILTIN_VPERMT2VARHI512,
29555 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
29556 IX86_BUILTIN_VPERMI2VARHI512,
29557 IX86_BUILTIN_PAVGB512,
29558 IX86_BUILTIN_PAVGW512,
29559 IX86_BUILTIN_PADDB512,
29560 IX86_BUILTIN_PSUBB512,
29561 IX86_BUILTIN_PSUBSB512,
29562 IX86_BUILTIN_PADDSB512,
29563 IX86_BUILTIN_PSUBUSB512,
29564 IX86_BUILTIN_PADDUSB512,
29565 IX86_BUILTIN_PSUBW512,
29566 IX86_BUILTIN_PADDW512,
29567 IX86_BUILTIN_PSUBSW512,
29568 IX86_BUILTIN_PADDSW512,
29569 IX86_BUILTIN_PSUBUSW512,
29570 IX86_BUILTIN_PADDUSW512,
29571 IX86_BUILTIN_PMAXUW512,
29572 IX86_BUILTIN_PMAXSW512,
29573 IX86_BUILTIN_PMINUW512,
29574 IX86_BUILTIN_PMINSW512,
29575 IX86_BUILTIN_PMAXUB512,
29576 IX86_BUILTIN_PMAXSB512,
29577 IX86_BUILTIN_PMINUB512,
29578 IX86_BUILTIN_PMINSB512,
29579 IX86_BUILTIN_PMOVWB512,
29580 IX86_BUILTIN_PMOVSWB512,
29581 IX86_BUILTIN_PMOVUSWB512,
29582 IX86_BUILTIN_PMULHRSW512_MASK,
29583 IX86_BUILTIN_PMULHUW512_MASK,
29584 IX86_BUILTIN_PMULHW512_MASK,
29585 IX86_BUILTIN_PMULLW512_MASK,
29586 IX86_BUILTIN_PSLLWI512_MASK,
29587 IX86_BUILTIN_PSLLW512_MASK,
29588 IX86_BUILTIN_PACKSSWB512,
29589 IX86_BUILTIN_PACKUSWB512,
29590 IX86_BUILTIN_PSRAVV32HI,
29591 IX86_BUILTIN_PMADDUBSW512_MASK,
29592 IX86_BUILTIN_PMADDWD512_MASK,
29593 IX86_BUILTIN_PSRLVV32HI,
29594 IX86_BUILTIN_PUNPCKHBW512,
29595 IX86_BUILTIN_PUNPCKHWD512,
29596 IX86_BUILTIN_PUNPCKLBW512,
29597 IX86_BUILTIN_PUNPCKLWD512,
29598 IX86_BUILTIN_PSHUFB512,
29599 IX86_BUILTIN_PSHUFHW512,
29600 IX86_BUILTIN_PSHUFLW512,
29601 IX86_BUILTIN_PSRAWI512,
29602 IX86_BUILTIN_PSRAW512,
29603 IX86_BUILTIN_PSRLWI512,
29604 IX86_BUILTIN_PSRLW512,
29605 IX86_BUILTIN_CVTB2MASK512,
29606 IX86_BUILTIN_CVTW2MASK512,
29607 IX86_BUILTIN_CVTMASK2B512,
29608 IX86_BUILTIN_CVTMASK2W512,
29609 IX86_BUILTIN_PCMPEQB512_MASK,
29610 IX86_BUILTIN_PCMPEQW512_MASK,
29611 IX86_BUILTIN_PCMPGTB512_MASK,
29612 IX86_BUILTIN_PCMPGTW512_MASK,
29613 IX86_BUILTIN_PTESTMB512,
29614 IX86_BUILTIN_PTESTMW512,
29615 IX86_BUILTIN_PTESTNMB512,
29616 IX86_BUILTIN_PTESTNMW512,
29617 IX86_BUILTIN_PSLLVV32HI,
29618 IX86_BUILTIN_PABSB512,
29619 IX86_BUILTIN_PABSW512,
29620 IX86_BUILTIN_BLENDMW512,
29621 IX86_BUILTIN_BLENDMB512,
29622 IX86_BUILTIN_CMPB512,
29623 IX86_BUILTIN_CMPW512,
29624 IX86_BUILTIN_UCMPB512,
29625 IX86_BUILTIN_UCMPW512,
29627 /* Alternate 4 and 8 element gather/scatter for the vectorizer
29628 where all operands are 32-byte or 64-byte wide respectively. */
29629 IX86_BUILTIN_GATHERALTSIV4DF,
29630 IX86_BUILTIN_GATHERALTDIV8SF,
29631 IX86_BUILTIN_GATHERALTSIV4DI,
29632 IX86_BUILTIN_GATHERALTDIV8SI,
29633 IX86_BUILTIN_GATHER3ALTDIV16SF,
29634 IX86_BUILTIN_GATHER3ALTDIV16SI,
29635 IX86_BUILTIN_GATHER3ALTSIV4DF,
29636 IX86_BUILTIN_GATHER3ALTDIV8SF,
29637 IX86_BUILTIN_GATHER3ALTSIV4DI,
29638 IX86_BUILTIN_GATHER3ALTDIV8SI,
29639 IX86_BUILTIN_GATHER3ALTSIV8DF,
29640 IX86_BUILTIN_GATHER3ALTSIV8DI,
29641 IX86_BUILTIN_GATHER3DIV16SF,
29642 IX86_BUILTIN_GATHER3DIV16SI,
29643 IX86_BUILTIN_GATHER3DIV8DF,
29644 IX86_BUILTIN_GATHER3DIV8DI,
29645 IX86_BUILTIN_GATHER3SIV16SF,
29646 IX86_BUILTIN_GATHER3SIV16SI,
29647 IX86_BUILTIN_GATHER3SIV8DF,
29648 IX86_BUILTIN_GATHER3SIV8DI,
29649 IX86_BUILTIN_SCATTERDIV16SF,
29650 IX86_BUILTIN_SCATTERDIV16SI,
29651 IX86_BUILTIN_SCATTERDIV8DF,
29652 IX86_BUILTIN_SCATTERDIV8DI,
29653 IX86_BUILTIN_SCATTERSIV16SF,
29654 IX86_BUILTIN_SCATTERSIV16SI,
29655 IX86_BUILTIN_SCATTERSIV8DF,
29656 IX86_BUILTIN_SCATTERSIV8DI,
29658 /* AVX512PF */
29659 IX86_BUILTIN_GATHERPFQPD,
29660 IX86_BUILTIN_GATHERPFDPS,
29661 IX86_BUILTIN_GATHERPFDPD,
29662 IX86_BUILTIN_GATHERPFQPS,
29663 IX86_BUILTIN_SCATTERPFDPD,
29664 IX86_BUILTIN_SCATTERPFDPS,
29665 IX86_BUILTIN_SCATTERPFQPD,
29666 IX86_BUILTIN_SCATTERPFQPS,
29668 /* AVX-512ER */
29669 IX86_BUILTIN_EXP2PD_MASK,
29670 IX86_BUILTIN_EXP2PS_MASK,
29671 IX86_BUILTIN_EXP2PS,
29672 IX86_BUILTIN_RCP28PD,
29673 IX86_BUILTIN_RCP28PS,
29674 IX86_BUILTIN_RCP28SD,
29675 IX86_BUILTIN_RCP28SS,
29676 IX86_BUILTIN_RSQRT28PD,
29677 IX86_BUILTIN_RSQRT28PS,
29678 IX86_BUILTIN_RSQRT28SD,
29679 IX86_BUILTIN_RSQRT28SS,
29681 /* SHA builtins. */
29682 IX86_BUILTIN_SHA1MSG1,
29683 IX86_BUILTIN_SHA1MSG2,
29684 IX86_BUILTIN_SHA1NEXTE,
29685 IX86_BUILTIN_SHA1RNDS4,
29686 IX86_BUILTIN_SHA256MSG1,
29687 IX86_BUILTIN_SHA256MSG2,
29688 IX86_BUILTIN_SHA256RNDS2,
29690 /* CLFLUSHOPT instructions. */
29691 IX86_BUILTIN_CLFLUSHOPT,
29693 /* TFmode support builtins. */
29694 IX86_BUILTIN_INFQ,
29695 IX86_BUILTIN_HUGE_VALQ,
29696 IX86_BUILTIN_FABSQ,
29697 IX86_BUILTIN_COPYSIGNQ,
29699 /* Vectorizer support builtins. */
29700 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
29701 IX86_BUILTIN_CPYSGNPS,
29702 IX86_BUILTIN_CPYSGNPD,
29703 IX86_BUILTIN_CPYSGNPS256,
29704 IX86_BUILTIN_CPYSGNPS512,
29705 IX86_BUILTIN_CPYSGNPD256,
29706 IX86_BUILTIN_CPYSGNPD512,
29707 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
29708 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
29711 /* FMA4 instructions. */
29712 IX86_BUILTIN_VFMADDSS,
29713 IX86_BUILTIN_VFMADDSD,
29714 IX86_BUILTIN_VFMADDPS,
29715 IX86_BUILTIN_VFMADDPD,
29716 IX86_BUILTIN_VFMADDPS256,
29717 IX86_BUILTIN_VFMADDPD256,
29718 IX86_BUILTIN_VFMADDSUBPS,
29719 IX86_BUILTIN_VFMADDSUBPD,
29720 IX86_BUILTIN_VFMADDSUBPS256,
29721 IX86_BUILTIN_VFMADDSUBPD256,
29723 /* FMA3 instructions. */
29724 IX86_BUILTIN_VFMADDSS3,
29725 IX86_BUILTIN_VFMADDSD3,
29727 /* XOP instructions. */
29728 IX86_BUILTIN_VPCMOV,
29729 IX86_BUILTIN_VPCMOV_V2DI,
29730 IX86_BUILTIN_VPCMOV_V4SI,
29731 IX86_BUILTIN_VPCMOV_V8HI,
29732 IX86_BUILTIN_VPCMOV_V16QI,
29733 IX86_BUILTIN_VPCMOV_V4SF,
29734 IX86_BUILTIN_VPCMOV_V2DF,
29735 IX86_BUILTIN_VPCMOV256,
29736 IX86_BUILTIN_VPCMOV_V4DI256,
29737 IX86_BUILTIN_VPCMOV_V8SI256,
29738 IX86_BUILTIN_VPCMOV_V16HI256,
29739 IX86_BUILTIN_VPCMOV_V32QI256,
29740 IX86_BUILTIN_VPCMOV_V8SF256,
29741 IX86_BUILTIN_VPCMOV_V4DF256,
29743 IX86_BUILTIN_VPPERM,
29745 IX86_BUILTIN_VPMACSSWW,
29746 IX86_BUILTIN_VPMACSWW,
29747 IX86_BUILTIN_VPMACSSWD,
29748 IX86_BUILTIN_VPMACSWD,
29749 IX86_BUILTIN_VPMACSSDD,
29750 IX86_BUILTIN_VPMACSDD,
29751 IX86_BUILTIN_VPMACSSDQL,
29752 IX86_BUILTIN_VPMACSSDQH,
29753 IX86_BUILTIN_VPMACSDQL,
29754 IX86_BUILTIN_VPMACSDQH,
29755 IX86_BUILTIN_VPMADCSSWD,
29756 IX86_BUILTIN_VPMADCSWD,
29758 IX86_BUILTIN_VPHADDBW,
29759 IX86_BUILTIN_VPHADDBD,
29760 IX86_BUILTIN_VPHADDBQ,
29761 IX86_BUILTIN_VPHADDWD,
29762 IX86_BUILTIN_VPHADDWQ,
29763 IX86_BUILTIN_VPHADDDQ,
29764 IX86_BUILTIN_VPHADDUBW,
29765 IX86_BUILTIN_VPHADDUBD,
29766 IX86_BUILTIN_VPHADDUBQ,
29767 IX86_BUILTIN_VPHADDUWD,
29768 IX86_BUILTIN_VPHADDUWQ,
29769 IX86_BUILTIN_VPHADDUDQ,
29770 IX86_BUILTIN_VPHSUBBW,
29771 IX86_BUILTIN_VPHSUBWD,
29772 IX86_BUILTIN_VPHSUBDQ,
29774 IX86_BUILTIN_VPROTB,
29775 IX86_BUILTIN_VPROTW,
29776 IX86_BUILTIN_VPROTD,
29777 IX86_BUILTIN_VPROTQ,
29778 IX86_BUILTIN_VPROTB_IMM,
29779 IX86_BUILTIN_VPROTW_IMM,
29780 IX86_BUILTIN_VPROTD_IMM,
29781 IX86_BUILTIN_VPROTQ_IMM,
29783 IX86_BUILTIN_VPSHLB,
29784 IX86_BUILTIN_VPSHLW,
29785 IX86_BUILTIN_VPSHLD,
29786 IX86_BUILTIN_VPSHLQ,
29787 IX86_BUILTIN_VPSHAB,
29788 IX86_BUILTIN_VPSHAW,
29789 IX86_BUILTIN_VPSHAD,
29790 IX86_BUILTIN_VPSHAQ,
29792 IX86_BUILTIN_VFRCZSS,
29793 IX86_BUILTIN_VFRCZSD,
29794 IX86_BUILTIN_VFRCZPS,
29795 IX86_BUILTIN_VFRCZPD,
29796 IX86_BUILTIN_VFRCZPS256,
29797 IX86_BUILTIN_VFRCZPD256,
29799 IX86_BUILTIN_VPCOMEQUB,
29800 IX86_BUILTIN_VPCOMNEUB,
29801 IX86_BUILTIN_VPCOMLTUB,
29802 IX86_BUILTIN_VPCOMLEUB,
29803 IX86_BUILTIN_VPCOMGTUB,
29804 IX86_BUILTIN_VPCOMGEUB,
29805 IX86_BUILTIN_VPCOMFALSEUB,
29806 IX86_BUILTIN_VPCOMTRUEUB,
29808 IX86_BUILTIN_VPCOMEQUW,
29809 IX86_BUILTIN_VPCOMNEUW,
29810 IX86_BUILTIN_VPCOMLTUW,
29811 IX86_BUILTIN_VPCOMLEUW,
29812 IX86_BUILTIN_VPCOMGTUW,
29813 IX86_BUILTIN_VPCOMGEUW,
29814 IX86_BUILTIN_VPCOMFALSEUW,
29815 IX86_BUILTIN_VPCOMTRUEUW,
29817 IX86_BUILTIN_VPCOMEQUD,
29818 IX86_BUILTIN_VPCOMNEUD,
29819 IX86_BUILTIN_VPCOMLTUD,
29820 IX86_BUILTIN_VPCOMLEUD,
29821 IX86_BUILTIN_VPCOMGTUD,
29822 IX86_BUILTIN_VPCOMGEUD,
29823 IX86_BUILTIN_VPCOMFALSEUD,
29824 IX86_BUILTIN_VPCOMTRUEUD,
29826 IX86_BUILTIN_VPCOMEQUQ,
29827 IX86_BUILTIN_VPCOMNEUQ,
29828 IX86_BUILTIN_VPCOMLTUQ,
29829 IX86_BUILTIN_VPCOMLEUQ,
29830 IX86_BUILTIN_VPCOMGTUQ,
29831 IX86_BUILTIN_VPCOMGEUQ,
29832 IX86_BUILTIN_VPCOMFALSEUQ,
29833 IX86_BUILTIN_VPCOMTRUEUQ,
29835 IX86_BUILTIN_VPCOMEQB,
29836 IX86_BUILTIN_VPCOMNEB,
29837 IX86_BUILTIN_VPCOMLTB,
29838 IX86_BUILTIN_VPCOMLEB,
29839 IX86_BUILTIN_VPCOMGTB,
29840 IX86_BUILTIN_VPCOMGEB,
29841 IX86_BUILTIN_VPCOMFALSEB,
29842 IX86_BUILTIN_VPCOMTRUEB,
29844 IX86_BUILTIN_VPCOMEQW,
29845 IX86_BUILTIN_VPCOMNEW,
29846 IX86_BUILTIN_VPCOMLTW,
29847 IX86_BUILTIN_VPCOMLEW,
29848 IX86_BUILTIN_VPCOMGTW,
29849 IX86_BUILTIN_VPCOMGEW,
29850 IX86_BUILTIN_VPCOMFALSEW,
29851 IX86_BUILTIN_VPCOMTRUEW,
29853 IX86_BUILTIN_VPCOMEQD,
29854 IX86_BUILTIN_VPCOMNED,
29855 IX86_BUILTIN_VPCOMLTD,
29856 IX86_BUILTIN_VPCOMLED,
29857 IX86_BUILTIN_VPCOMGTD,
29858 IX86_BUILTIN_VPCOMGED,
29859 IX86_BUILTIN_VPCOMFALSED,
29860 IX86_BUILTIN_VPCOMTRUED,
29862 IX86_BUILTIN_VPCOMEQQ,
29863 IX86_BUILTIN_VPCOMNEQ,
29864 IX86_BUILTIN_VPCOMLTQ,
29865 IX86_BUILTIN_VPCOMLEQ,
29866 IX86_BUILTIN_VPCOMGTQ,
29867 IX86_BUILTIN_VPCOMGEQ,
29868 IX86_BUILTIN_VPCOMFALSEQ,
29869 IX86_BUILTIN_VPCOMTRUEQ,
29871 /* LWP instructions. */
29872 IX86_BUILTIN_LLWPCB,
29873 IX86_BUILTIN_SLWPCB,
29874 IX86_BUILTIN_LWPVAL32,
29875 IX86_BUILTIN_LWPVAL64,
29876 IX86_BUILTIN_LWPINS32,
29877 IX86_BUILTIN_LWPINS64,
29879 IX86_BUILTIN_CLZS,
29881 /* RTM */
29882 IX86_BUILTIN_XBEGIN,
29883 IX86_BUILTIN_XEND,
29884 IX86_BUILTIN_XABORT,
29885 IX86_BUILTIN_XTEST,
29887 /* BMI instructions. */
29888 IX86_BUILTIN_BEXTR32,
29889 IX86_BUILTIN_BEXTR64,
29890 IX86_BUILTIN_CTZS,
29892 /* TBM instructions. */
29893 IX86_BUILTIN_BEXTRI32,
29894 IX86_BUILTIN_BEXTRI64,
29896 /* BMI2 instructions. */
29897 IX86_BUILTIN_BZHI32,
29898 IX86_BUILTIN_BZHI64,
29899 IX86_BUILTIN_PDEP32,
29900 IX86_BUILTIN_PDEP64,
29901 IX86_BUILTIN_PEXT32,
29902 IX86_BUILTIN_PEXT64,
29904 /* ADX instructions. */
29905 IX86_BUILTIN_ADDCARRYX32,
29906 IX86_BUILTIN_ADDCARRYX64,
29908 /* FSGSBASE instructions. */
29909 IX86_BUILTIN_RDFSBASE32,
29910 IX86_BUILTIN_RDFSBASE64,
29911 IX86_BUILTIN_RDGSBASE32,
29912 IX86_BUILTIN_RDGSBASE64,
29913 IX86_BUILTIN_WRFSBASE32,
29914 IX86_BUILTIN_WRFSBASE64,
29915 IX86_BUILTIN_WRGSBASE32,
29916 IX86_BUILTIN_WRGSBASE64,
29918 /* RDRND instructions. */
29919 IX86_BUILTIN_RDRAND16_STEP,
29920 IX86_BUILTIN_RDRAND32_STEP,
29921 IX86_BUILTIN_RDRAND64_STEP,
29923 /* RDSEED instructions. */
29924 IX86_BUILTIN_RDSEED16_STEP,
29925 IX86_BUILTIN_RDSEED32_STEP,
29926 IX86_BUILTIN_RDSEED64_STEP,
29928 /* F16C instructions. */
29929 IX86_BUILTIN_CVTPH2PS,
29930 IX86_BUILTIN_CVTPH2PS256,
29931 IX86_BUILTIN_CVTPS2PH,
29932 IX86_BUILTIN_CVTPS2PH256,
29934 /* CFString built-in for darwin */
29935 IX86_BUILTIN_CFSTRING,
29937 /* Builtins to get CPU type and supported features. */
29938 IX86_BUILTIN_CPU_INIT,
29939 IX86_BUILTIN_CPU_IS,
29940 IX86_BUILTIN_CPU_SUPPORTS,
29942 /* Read/write FLAGS register built-ins. */
29943 IX86_BUILTIN_READ_FLAGS,
29944 IX86_BUILTIN_WRITE_FLAGS,
29946 IX86_BUILTIN_MAX
29947 };
29949 /* Table for the ix86 builtin decls. */
29952 /* Table of all of the builtin functions that are possible with different ISA's
29953 but are waiting to be built until a function is declared to use that
29954 ISA. */
29961 };
29966 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
29967 of which isa_flags to use in the ix86_builtins_isa array. Stores the
29968 function decl in the ix86_builtins array. Returns the function decl or
29969 NULL_TREE, if the builtin was not added.
29971 If the front end has a special hook for builtin functions, delay adding
29972 builtin functions that aren't in the current ISA until the ISA is changed
29973 with function specific optimization. Doing so, can save about 300K for the
29974 default compiler. When the builtin is expanded, check at that time whether
29975 it is valid.
29977 If the front end doesn't have a special hook, record all builtins, even if
29978 it isn't an instruction set in the current ISA in case the user uses
29979 function specific options for a different ISA, so that we don't get scope
29980 errors if a builtin is added in the middle of a function scope. */
29986 {
29990 {
29999 {
30005 }
30006 else
30007 {
30013 }
30014 }
30017 }
30019 /* Like def_builtin, but also marks the function decl "const". */
30024 {
30028 else
30032 }
30034 /* Add any new builtin functions for a given ISA that may not have been
30035 declared. This saves a bit of space compared to adding all of the
30036 declarations to the tree, even if we didn't use them. */
30038 static void
30040 {
30044 {
30047 {
30050 /* Don't define the builtin again. */
30056 NULL_TREE);
30061 }
30062 }
30063 }
30065 /* Bits for builtin_description.flag. */
30067 /* Set when we don't support the comparison natively, and should
30068 swap_comparison in order to support it. */
30069 #define BUILTIN_DESC_SWAP_OPERANDS 1
30071 struct builtin_description
30072 {
30079 };
30082 {
30083 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30086 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30107 };
30110 {
30111 /* SSE4.2 */
30112 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30113 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30114 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30115 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30116 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30117 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30118 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30119 };
30122 {
30123 /* SSE4.2 */
30124 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30125 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30126 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30127 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30128 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30129 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30130 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30131 };
30133 /* Special builtins with variable number of arguments. */
30135 {
30136 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30137 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30138 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30140 /* 80387 (for use internally for atomic compound assignment). */
30141 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30142 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30143 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30144 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30146 /* MMX */
30147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30149 /* 3DNow! */
30150 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30152 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30153 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30154 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30155 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30156 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30157 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30158 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30159 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30160 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30162 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30163 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30164 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30165 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30166 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30167 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30168 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30169 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30171 /* SSE */
30172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30173 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30174 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30176 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30177 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30178 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30179 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30181 /* SSE or 3DNow!A */
30182 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30183 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30185 /* SSE2 */
30186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30191 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30193 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30198 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30200 /* SSE3 */
30201 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30203 /* SSE4.1 */
30204 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30206 /* SSE4A */
30207 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30208 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30210 /* AVX */
30211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30212 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30214 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30215 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30216 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30217 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30218 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30220 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30221 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30222 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30223 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30224 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30225 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30226 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30228 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30229 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30230 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30232 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30233 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30234 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30235 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30236 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30237 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30238 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30239 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30241 /* AVX2 */
30242 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30243 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30244 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30245 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30246 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30247 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30248 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30249 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30250 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30252 /* AVX512F */
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512dq_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30301 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30302 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30303 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30304 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30305 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30306 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30308 /* FSGSBASE */
30309 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30310 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30311 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30312 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30313 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30314 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30315 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30316 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30318 /* RTM */
30319 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30320 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30321 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30323 /* AVX512BW */
30324 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30325 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30326 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30327 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30329 /* AVX512VL */
30330 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30331 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30332 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30333 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30366 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
30367 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
30368 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
30369 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
30370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
30372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
30373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
30374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_store_mask, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_store_mask, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_store_mask, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_store_mask, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_store_mask, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
30399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_store_mask, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
30400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_store_mask, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_store_mask, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_store_mask, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_store_mask, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_store_mask, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
30405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_store_mask, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
30406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_store_mask, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_store_mask, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_store_mask, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_store_mask, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_store_mask, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
30411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_store_mask, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
30412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_store_mask, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_store_mask, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_store_mask, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_store_mask, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_store_mask, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
30417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_store_mask, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
30418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_store_mask, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_store_mask, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_store_mask, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_store_mask, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_store_mask, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
30423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_store_mask, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
30424 };
30426 /* Builtins with variable number of arguments. */
30428 {
30429 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
30430 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
30431 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
30432 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30433 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30434 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
30435 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
30437 /* MMX */
30438 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30439 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30440 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30441 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30442 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30443 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30445 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30446 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30447 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30448 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30449 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30450 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30451 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30452 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30454 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30455 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30457 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30458 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30459 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30460 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30462 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30463 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30464 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30465 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30466 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30467 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30469 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30470 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30471 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30472 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30473 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
30474 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
30476 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30477 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
30478 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
30480 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
30482 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30483 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30484 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30485 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30486 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30487 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30489 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30490 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30491 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
30492 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30493 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30494 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
30496 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
30497 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
30498 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
30499 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
30501 /* 3DNow! */
30502 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30503 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30504 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30505 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30507 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30508 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30509 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30510 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30511 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30512 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
30513 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30514 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30515 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30516 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30517 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30518 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30519 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30520 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30521 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30523 /* 3DNow!A */
30524 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
30525 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
30526 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
30527 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
30528 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30529 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
30531 /* SSE */
30532 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
30533 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30534 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30535 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30536 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30537 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30538 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
30539 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
30540 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
30541 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
30542 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
30543 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
30545 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30547 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30548 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30549 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30550 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30551 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30552 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30553 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30554 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30556 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
30557 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
30558 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
30559 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30560 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30561 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30562 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
30563 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
30564 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
30565 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
30566 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
30567 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30568 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
30569 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
30570 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
30571 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30572 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
30573 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
30574 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
30575 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
30577 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30578 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30579 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30580 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30582 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30583 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30584 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30585 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30587 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30589 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30590 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30591 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30592 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30593 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30595 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
30596 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
30597 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
30599 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
30601 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
30602 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
30603 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
30605 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
30606 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
30608 /* SSE MMX or 3Dnow!A */
30609 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30610 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30611 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30613 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30614 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30615 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30616 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30618 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
30619 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
30621 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
30623 /* SSE2 */
30624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30626 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
30627 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
30628 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
30629 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
30630 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
30632 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
30633 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
30634 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
30635 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
30636 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
30638 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
30640 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
30641 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
30642 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
30643 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
30645 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
30646 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
30647 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
30649 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30650 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30651 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30652 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30653 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30654 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30655 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30656 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
30659 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
30660 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
30661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
30662 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
30663 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
30664 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
30665 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
30666 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
30667 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
30668 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
30669 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
30670 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
30671 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
30672 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
30673 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
30674 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
30675 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
30676 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
30677 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
30679 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30680 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30681 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30682 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30684 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30685 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30686 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30687 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30689 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30691 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30692 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30693 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30695 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
30697 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30698 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30699 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30700 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30701 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30702 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30703 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30704 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30708 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30709 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30711 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30712 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30713 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30715 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30716 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
30718 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30719 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30720 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30721 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30726 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30727 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30728 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30731 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30733 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30734 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30735 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30736 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30738 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30739 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30740 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30741 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30742 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30743 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30744 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30745 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30747 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
30748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
30749 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
30751 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
30754 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
30755 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
30757 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
30759 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
30760 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
30761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
30762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
30764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
30765 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
30766 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
30767 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
30768 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
30769 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
30770 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
30772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
30773 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
30774 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
30775 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
30776 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
30777 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
30778 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
30780 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
30781 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
30782 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
30783 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
30785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
30786 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
30787 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
30789 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
30791 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
30793 /* SSE2 MMX */
30794 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
30795 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
30797 /* SSE3 */
30798 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
30799 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30801 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30802 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30803 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30804 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30805 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30806 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30808 /* SSSE3 */
30809 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
30810 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
30811 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
30812 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
30813 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
30814 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
30816 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30817 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30818 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30819 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30820 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30821 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30822 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30823 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30824 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30825 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30826 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30827 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30828 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
30829 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
30830 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30831 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30832 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30833 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30834 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30835 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
30836 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30837 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
30838 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30839 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
30841 /* SSSE3. */
30842 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
30843 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
30845 /* SSE4.1 */
30846 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30847 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30848 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
30849 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
30850 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30851 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30852 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30853 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
30854 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
30855 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
30857 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
30858 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
30859 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
30860 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
30861 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
30862 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
30863 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
30864 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
30865 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
30866 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
30867 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
30868 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
30869 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
30871 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
30872 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30873 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30874 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30875 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30876 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30877 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
30878 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30879 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30880 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
30881 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
30882 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30884 /* SSE4.1 */
30885 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
30886 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
30887 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30888 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30890 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
30891 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
30892 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
30893 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
30895 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
30896 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
30898 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
30899 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
30901 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
30902 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
30903 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
30904 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
30906 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
30907 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
30909 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30910 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
30912 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
30913 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
30914 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
30916 /* SSE4.2 */
30917 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30918 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
30919 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
30920 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30921 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30923 /* SSE4A */
30924 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
30925 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
30926 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
30927 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30929 /* AES */
30930 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
30931 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
30933 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30934 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30935 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30936 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30938 /* PCLMUL */
30939 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
30941 /* AVX */
30942 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30943 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30944 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30945 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30946 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30947 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30948 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30949 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30950 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30951 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30952 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30953 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30954 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30955 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30956 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30957 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30958 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30959 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30960 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30961 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30962 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30963 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30964 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30965 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30966 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30967 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30969 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
30970 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
30971 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
30972 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
30974 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30975 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30976 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
30977 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
30978 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30979 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30980 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30981 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30982 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30983 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30984 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30985 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30986 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
30987 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
30988 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
30989 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
30990 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
30991 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
30992 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
30993 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
30994 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
30995 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
30996 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
30997 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
30998 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
30999 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31007 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31013 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31015 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31017 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31019 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31021 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31022 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31024 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31025 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31026 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31027 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31029 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31030 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31032 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31033 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31037 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31043 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31044 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31054 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31055 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31056 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31077 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31078 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31080 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31082 /* AVX2 */
31083 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31084 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31085 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31086 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31087 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31088 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31089 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31090 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31091 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31092 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31093 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31094 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31095 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31096 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31097 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31098 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31099 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31100 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31101 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31102 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31103 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31104 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31105 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31106 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31107 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31108 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31109 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31110 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31111 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31112 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31113 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31114 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31115 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31116 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31117 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31118 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31119 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31120 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31121 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31122 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31123 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31124 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31125 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31126 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31127 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31128 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31129 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31130 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31131 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31132 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31133 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31134 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31135 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31136 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31137 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31138 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31139 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31140 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31141 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31142 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31143 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31144 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31145 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31146 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31147 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31148 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31149 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31150 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31151 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31152 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31153 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31154 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31155 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31156 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31157 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31158 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31159 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31160 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31161 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31162 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31163 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31164 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31165 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31166 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31167 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31168 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31169 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31170 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31171 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31172 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31173 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31174 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31175 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31176 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31177 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31178 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31179 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31180 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31181 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31182 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31183 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31184 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31185 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31186 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31187 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31188 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31189 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31190 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31191 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31192 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31193 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31194 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31195 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31196 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31197 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31198 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31199 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31200 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31201 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31202 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31203 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31204 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31205 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31206 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31207 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31208 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31209 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31210 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31211 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31212 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31213 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31214 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31215 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31216 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31217 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31218 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31219 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31220 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31221 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31222 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31223 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31224 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31225 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31226 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31227 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31228 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31230 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31232 /* BMI */
31233 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31234 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31235 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31237 /* TBM */
31238 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31239 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31241 /* F16C */
31242 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31243 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31244 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31245 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31247 /* BMI2 */
31248 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31249 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31250 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31251 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31252 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31253 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31255 /* AVX512F */
31256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31305 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31306 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31308 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31309 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31316 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31320 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31322 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31324 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31325 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31326 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31327 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31328 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31348 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
31350 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
31351 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
31352 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
31353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31354 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
31356 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31357 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31358 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31359 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31360 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31362 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31364 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31366 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31368 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31370 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31372 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31374 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31376 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31378 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31379 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
31380 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
31381 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
31382 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31383 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31384 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31385 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31386 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31387 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31388 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31389 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31390 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31391 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31392 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31393 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31394 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31395 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31396 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31397 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31398 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31399 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31400 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31401 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31402 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31403 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31404 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31405 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31406 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31407 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
31408 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
31409 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31410 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31411 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31412 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31413 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31414 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31415 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
31416 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
31417 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31418 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31419 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31420 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31421 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31422 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
31423 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31424 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31425 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31426 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31427 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
31428 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
31429 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31430 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31431 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31432 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31433 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31434 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
31435 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31436 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
31437 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31438 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31439 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
31440 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31441 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
31442 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31443 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31444 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
31445 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31446 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
31448 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
31449 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
31450 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
31451 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31452 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
31453 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
31454 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31455 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
31457 /* Mask arithmetic operations */
31458 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31459 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31460 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
31461 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31462 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31463 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31464 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
31465 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31466 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
31467 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
31469 /* SHA */
31470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
31478 /* AVX512VL. */
31479 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
31480 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
31481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
31482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
31484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31489 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
31490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
31491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
31492 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31517 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31518 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31519 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31520 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31521 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31522 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31523 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31524 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31525 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31526 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31527 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31528 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
31529 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
31530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
31533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
31534 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
31535 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
31536 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31537 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31538 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31539 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31540 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31541 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31542 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
31543 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
31544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31546 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31547 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31548 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31549 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
31559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
31560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
31561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
31562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
31563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
31564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
31565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
31566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
31567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
31568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
31569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
31570 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
31571 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
31572 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
31573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
31574 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
31575 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
31576 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
31577 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
31578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
31579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
31580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
31582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
31583 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
31584 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
31585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31586 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
31587 { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
31588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
31589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
31591 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
31592 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
31593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
31594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
31595 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
31596 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
31597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
31598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
31599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
31600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
31601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
31602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
31603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
31604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
31605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
31606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
31607 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
31608 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
31609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
31610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
31611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
31612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
31613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
31614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
31615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
31616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
31617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
31618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
31619 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
31620 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
31621 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
31622 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
31623 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31624 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31625 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31626 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31627 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31628 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31629 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31630 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31631 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31632 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31641 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31642 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31643 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31644 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31647 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31649 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31650 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31653 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31654 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31655 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31656 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31657 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31658 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31659 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31660 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31661 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31662 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31665 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31666 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31667 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31668 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31669 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31670 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31673 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31674 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31675 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31676 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
31678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
31679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
31680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
31681 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
31682 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
31683 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
31684 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
31685 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
31686 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
31687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
31688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
31689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
31690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
31691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
31692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
31693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
31694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
31695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
31696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
31697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
31698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
31699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
31700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
31701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
31702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
31703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
31704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
31705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
31706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
31707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
31708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
31709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
31710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
31711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
31712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
31713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
31714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
31715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
31716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
31717 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
31718 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
31719 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
31720 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
31721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df, "__builtin_ia32_fixupimmpd256", IX86_BUILTIN_FIXUPIMMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT },
31726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
31727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
31728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf, "__builtin_ia32_fixupimmps256", IX86_BUILTIN_FIXUPIMMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT },
31729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
31730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
31731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df, "__builtin_ia32_fixupimmpd128", IX86_BUILTIN_FIXUPIMMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT },
31732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
31733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
31734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf, "__builtin_ia32_fixupimmps128", IX86_BUILTIN_FIXUPIMMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT },
31735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
31736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
31737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
31738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
31739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
31740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
31741 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31742 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31743 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31744 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31745 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31746 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31747 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31748 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31749 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31750 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31751 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31752 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31753 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31754 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31755 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31756 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31757 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31758 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31759 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
31760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
31761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
31762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31765 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
31766 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
31767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
31768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
31769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
31770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
31771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
31772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
31774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
31775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask_1, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
31776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask_1, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
31778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
31779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
31782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
31784 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
31785 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
31786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
31788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
31789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31802 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31803 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
31804 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
31805 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
31806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
31807 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
31808 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
31809 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
31810 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
31811 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
31812 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
31813 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
31814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
31815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
31816 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
31817 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
31818 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
31819 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31824 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31825 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31846 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
31864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
31865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
31866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
31867 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
31868 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
31869 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31870 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31871 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
31872 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
31873 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
31874 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
31875 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
31876 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
31880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
31881 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31882 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31883 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
31884 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
31885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
31886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
31887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
31888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
31889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
31890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
31891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
31894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
31895 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
31896 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
31897 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
31898 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
31899 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
31900 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
31901 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
31902 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
31903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
31910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
31911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
31912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
31913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
31914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
31915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
31922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
31923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
31924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
31925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
31926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
31927 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
31928 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
31929 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
31930 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
31931 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
31932 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
31933 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
31934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
31935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
31936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
31937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
31938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
31939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
31942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
31943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
31946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
31947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31953 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
31956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
31957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31959 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
31960 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
31961 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
31962 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31963 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
31964 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
31965 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
31966 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
31967 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31968 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
31969 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
31970 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
31971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
31973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
31974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
31975 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
31976 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
31977 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
31978 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
31979 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
31980 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
31981 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
31982 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
31983 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
31984 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
31985 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
31986 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
31987 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
31988 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
31989 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
31990 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
31991 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
31992 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
31993 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
31994 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
31995 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
31996 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
31997 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
31998 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
31999 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32000 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32005 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32006 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32007 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32008 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32013 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32014 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32015 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32016 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32021 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32022 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32023 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32024 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32029 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32030 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32031 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32032 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32043 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32044 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32045 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32073 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32074 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32075 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32076 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32077 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32078 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32079 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32080 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32081 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32082 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32083 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32084 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32085 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32086 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32087 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32088 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32099 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32100 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32101 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32102 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32103 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32104 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32105 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32106 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32107 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32108 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32109 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32110 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32111 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32112 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32113 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32114 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32115 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32116 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32117 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32118 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32119 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32120 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32121 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32122 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32123 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32124 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32125 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32126 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32127 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32128 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32129 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32130 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32131 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32132 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32133 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32134 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32135 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32136 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32137 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32138 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32139 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32140 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32142 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32143 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32144 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32145 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32149 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32150 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32151 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32152 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32162 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32163 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32164 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32165 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32181 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32182 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32183 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32184 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32191 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32192 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32193 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32194 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32198 /* AVX512DQ. */
32199 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32200 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32201 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32202 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32203 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32204 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32205 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32206 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32207 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32208 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32209 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32210 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32211 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32212 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32213 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32214 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32215 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32216 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32217 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32218 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32219 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32220 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32221 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32222 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32223 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32224 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32225 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32226 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32227 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32228 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32229 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32231 /* AVX512BW. */
32232 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32233 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32234 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32235 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32236 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32237 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32238 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32239 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32240 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32241 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32242 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32243 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32244 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32245 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32246 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32247 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32248 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32249 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32250 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32251 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32252 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32253 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32254 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32255 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32256 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32257 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32258 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32259 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32260 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32261 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32262 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32263 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32264 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32265 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32266 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32267 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32268 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32269 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32270 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32271 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32272 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32273 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32274 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32275 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32276 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32277 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32278 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512vl_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32279 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32280 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32281 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32282 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32283 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32284 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32285 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32286 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32287 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32288 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32289 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32290 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32291 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32292 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32293 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32294 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32295 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32296 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32297 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32298 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32299 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32300 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32301 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32302 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32303 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32304 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32305 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32306 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32307 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32308 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32309 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32310 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32311 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32312 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32313 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32314 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32315 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32316 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32317 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32318 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32319 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32320 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32321 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32322 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32323 };
32325 /* Builtins with rounding support. */
32327 {
32328 /* AVX512F */
32329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
32334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
32335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
32336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
32337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
32338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
32339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
32342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
32344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
32346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
32348 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
32349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
32350 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
32351 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
32352 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
32354 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
32356 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
32357 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
32358 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
32359 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
32360 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32362 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32364 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
32366 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
32368 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
32370 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
32372 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32374 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32376 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32378 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32379 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32380 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32381 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32382 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32383 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32384 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32385 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32386 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32387 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32388 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32389 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32390 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32391 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32392 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
32393 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
32394 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32395 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32396 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32397 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32398 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32399 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32400 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32401 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32402 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32403 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32404 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32405 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32406 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32407 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32408 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32409 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32410 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32411 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32412 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32413 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32414 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32415 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32416 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
32417 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
32418 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
32419 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
32420 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
32421 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
32422 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
32423 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
32424 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32425 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32426 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32427 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32428 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32429 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32430 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
32431 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
32432 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32433 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32434 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32435 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32436 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32437 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32438 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32439 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32440 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32441 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32442 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32443 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32444 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32445 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
32446 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32447 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
32449 /* AVX512ER */
32450 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32451 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32452 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32453 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32454 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32455 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32456 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
32457 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
32458 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32459 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32461 /* AVX512DQ. */
32462 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
32463 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
32464 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32465 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32466 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32467 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32468 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32469 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
32470 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32471 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
32472 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32473 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
32474 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32475 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
32476 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
32477 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
32478 };
32480 /* FMA4 and XOP. */
32481 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
32482 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
32483 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
32484 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
32485 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
32486 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
32487 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
32488 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
32489 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
32490 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
32491 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
32492 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
32493 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
32494 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
32495 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
32496 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
32497 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
32498 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
32499 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
32500 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
32501 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
32502 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
32503 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
32504 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
32505 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
32506 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
32507 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
32508 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
32509 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
32510 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
32511 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
32512 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
32513 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
32514 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
32515 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
32516 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
32517 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
32518 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
32519 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
32520 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
32521 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
32522 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
32523 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
32524 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
32525 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
32526 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
32527 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
32528 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
32529 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
32530 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
32531 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
32532 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
32535 {
32576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
32577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
32578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
32579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
32580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
32581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
32582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
32584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
32585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
32586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
32587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
32588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
32589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
32590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
32592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
32594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
32595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
32596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
32599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
32600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
32604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
32607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
32608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
32609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
32610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
32611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
32612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
32613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
32614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
32615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
32616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
32617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
32618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
32619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
32620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
32621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
32622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
32624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
32625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
32626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
32627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
32628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
32629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
32631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
32632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
32633 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
32634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
32635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
32636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
32637 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
32638 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
32639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
32640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
32641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
32642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
32643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
32644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
32645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
32647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
32648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
32649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
32650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
32651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
32652 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
32653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
32655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
32656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
32657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
32658 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
32659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
32660 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
32661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
32663 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
32664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
32665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
32666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
32667 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
32668 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
32669 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
32671 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
32672 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
32673 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
32674 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
32675 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
32676 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
32677 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
32679 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
32680 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
32681 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
32682 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
32683 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
32684 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
32685 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
32687 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
32688 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
32689 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
32690 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
32691 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
32692 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
32693 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
32695 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
32696 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
32697 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
32698 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
32699 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
32700 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
32701 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
32703 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
32704 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
32705 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
32706 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
32707 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
32708 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
32709 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
32711 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
32712 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
32713 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
32714 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
32715 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
32716 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
32717 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
32718 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
32720 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
32721 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
32722 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
32723 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
32724 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
32725 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
32726 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
32727 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
32729 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
32730 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
32731 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
32732 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
32734 };
32735 \f
32736 /* TM vector builtins. */
32738 /* Reuse the existing x86-specific `struct builtin_description' cause
32739 we're lazy. Add casts to make them fit. */
32741 {
32742 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
32743 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
32744 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
32745 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
32746 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
32747 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
32748 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
32750 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
32751 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
32752 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
32753 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
32754 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
32755 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
32756 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
32758 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
32759 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
32760 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
32761 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
32762 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
32763 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
32764 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
32766 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
32767 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
32768 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
32769 };
32771 /* TM callbacks. */
32773 /* Return the builtin decl needed to load a vector of TYPE. */
32775 static tree
32777 {
32779 {
32781 {
32788 }
32789 }
32791 }
32793 /* Return the builtin decl needed to store a vector of TYPE. */
32795 static tree
32797 {
32799 {
32801 {
32808 }
32809 }
32811 }
32812 \f
32813 /* Initialize the transactional memory vector load/store builtins. */
32815 static void
32817 {
32821 tree decl;
32828 /* If there are no builtins defined, we must be compiling in a
32829 language without trans-mem support. */
32833 /* Use whatever attributes a normal TM load has. */
32837 /* Use whatever attributes a normal TM store has. */
32841 /* Use whatever attributes a normal TM log has. */
32849 {
32853 {
32861 {
32864 }
32866 {
32869 }
32870 else
32871 {
32874 }
32876 /* The builtin without the prefix for
32877 calling it directly. */
32879 attrs);
32880 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
32881 set the TYPE_ATTRIBUTES. */
32885 }
32886 }
32887 }
32889 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
32890 in the current target ISA to allow the user to compile particular modules
32891 with different target specific options that differ from the command line
32892 options. */
32893 static void
32895 {
32900 /* Add all special builtins with variable number of operands. */
32904 {
32910 }
32912 /* Add all builtins with variable number of operands. */
32916 {
32922 }
32924 /* Add all builtins with rounding. */
32928 {
32934 }
32936 /* pcmpestr[im] insns. */
32940 {
32943 else
32946 }
32948 /* pcmpistr[im] insns. */
32952 {
32955 else
32958 }
32960 /* comi/ucomi insns. */
32962 {
32965 else
32968 }
32970 /* SSE */
32976 /* SSE or 3DNow!A */
32979 IX86_BUILTIN_MASKMOVQ);
32981 /* SSE2 */
32990 /* SSE3. */
32996 /* AES */
33010 /* PCLMUL */
33014 /* RDRND */
33021 IX86_BUILTIN_RDRAND64_STEP);
33023 /* AVX2 */
33025 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33026 IX86_BUILTIN_GATHERSIV2DF);
33029 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33030 IX86_BUILTIN_GATHERSIV4DF);
33033 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33034 IX86_BUILTIN_GATHERDIV2DF);
33037 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33038 IX86_BUILTIN_GATHERDIV4DF);
33041 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33042 IX86_BUILTIN_GATHERSIV4SF);
33045 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33046 IX86_BUILTIN_GATHERSIV8SF);
33049 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33050 IX86_BUILTIN_GATHERDIV4SF);
33053 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33054 IX86_BUILTIN_GATHERDIV8SF);
33057 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33058 IX86_BUILTIN_GATHERSIV2DI);
33061 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33062 IX86_BUILTIN_GATHERSIV4DI);
33065 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33066 IX86_BUILTIN_GATHERDIV2DI);
33069 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33070 IX86_BUILTIN_GATHERDIV4DI);
33073 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33074 IX86_BUILTIN_GATHERSIV4SI);
33077 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33078 IX86_BUILTIN_GATHERSIV8SI);
33081 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33082 IX86_BUILTIN_GATHERDIV4SI);
33085 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33086 IX86_BUILTIN_GATHERDIV8SI);
33089 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33090 IX86_BUILTIN_GATHERALTSIV4DF);
33093 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33094 IX86_BUILTIN_GATHERALTDIV8SF);
33097 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33098 IX86_BUILTIN_GATHERALTSIV4DI);
33101 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33102 IX86_BUILTIN_GATHERALTDIV8SI);
33104 /* AVX512F */
33106 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33107 IX86_BUILTIN_GATHER3SIV16SF);
33110 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33111 IX86_BUILTIN_GATHER3SIV8DF);
33114 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33115 IX86_BUILTIN_GATHER3DIV16SF);
33118 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33119 IX86_BUILTIN_GATHER3DIV8DF);
33122 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33123 IX86_BUILTIN_GATHER3SIV16SI);
33126 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33127 IX86_BUILTIN_GATHER3SIV8DI);
33130 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33131 IX86_BUILTIN_GATHER3DIV16SI);
33134 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33135 IX86_BUILTIN_GATHER3DIV8DI);
33138 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33139 IX86_BUILTIN_GATHER3ALTSIV8DF);
33142 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33143 IX86_BUILTIN_GATHER3ALTDIV16SF);
33146 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33147 IX86_BUILTIN_GATHER3ALTSIV8DI);
33150 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33151 IX86_BUILTIN_GATHER3ALTDIV16SI);
33154 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33155 IX86_BUILTIN_SCATTERSIV16SF);
33158 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33159 IX86_BUILTIN_SCATTERSIV8DF);
33162 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33163 IX86_BUILTIN_SCATTERDIV16SF);
33166 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33167 IX86_BUILTIN_SCATTERDIV8DF);
33170 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33171 IX86_BUILTIN_SCATTERSIV16SI);
33174 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33175 IX86_BUILTIN_SCATTERSIV8DI);
33178 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33179 IX86_BUILTIN_SCATTERDIV16SI);
33182 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33183 IX86_BUILTIN_SCATTERDIV8DI);
33185 /* AVX512VL */
33187 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33188 IX86_BUILTIN_GATHER3SIV2DF);
33191 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33192 IX86_BUILTIN_GATHER3SIV4DF);
33195 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33196 IX86_BUILTIN_GATHER3DIV2DF);
33199 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33200 IX86_BUILTIN_GATHER3DIV4DF);
33203 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33204 IX86_BUILTIN_GATHER3SIV4SF);
33207 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33208 IX86_BUILTIN_GATHER3SIV8SF);
33211 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33212 IX86_BUILTIN_GATHER3DIV4SF);
33215 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33216 IX86_BUILTIN_GATHER3DIV8SF);
33219 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33220 IX86_BUILTIN_GATHER3SIV2DI);
33223 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33224 IX86_BUILTIN_GATHER3SIV4DI);
33227 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33228 IX86_BUILTIN_GATHER3DIV2DI);
33231 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33232 IX86_BUILTIN_GATHER3DIV4DI);
33235 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33236 IX86_BUILTIN_GATHER3SIV4SI);
33239 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33240 IX86_BUILTIN_GATHER3SIV8SI);
33243 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33244 IX86_BUILTIN_GATHER3DIV4SI);
33247 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33248 IX86_BUILTIN_GATHER3DIV8SI);
33251 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33252 IX86_BUILTIN_GATHER3ALTSIV4DF);
33255 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33256 IX86_BUILTIN_GATHER3ALTDIV8SF);
33259 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33260 IX86_BUILTIN_GATHER3ALTSIV4DI);
33263 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33264 IX86_BUILTIN_GATHER3ALTDIV8SI);
33267 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33268 IX86_BUILTIN_SCATTERSIV8SF);
33271 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33272 IX86_BUILTIN_SCATTERSIV4SF);
33275 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33276 IX86_BUILTIN_SCATTERSIV4DF);
33279 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33280 IX86_BUILTIN_SCATTERSIV2DF);
33283 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33284 IX86_BUILTIN_SCATTERDIV8SF);
33287 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33288 IX86_BUILTIN_SCATTERDIV4SF);
33291 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33292 IX86_BUILTIN_SCATTERDIV4DF);
33295 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
33296 IX86_BUILTIN_SCATTERDIV2DF);
33299 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
33300 IX86_BUILTIN_SCATTERSIV8SI);
33303 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
33304 IX86_BUILTIN_SCATTERSIV4SI);
33307 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
33308 IX86_BUILTIN_SCATTERSIV4DI);
33311 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
33312 IX86_BUILTIN_SCATTERSIV2DI);
33315 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
33316 IX86_BUILTIN_SCATTERDIV8SI);
33319 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
33320 IX86_BUILTIN_SCATTERDIV4SI);
33323 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
33324 IX86_BUILTIN_SCATTERDIV4DI);
33327 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
33328 IX86_BUILTIN_SCATTERDIV2DI);
33330 /* AVX512PF */
33332 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33333 IX86_BUILTIN_GATHERPFDPD);
33335 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33336 IX86_BUILTIN_GATHERPFDPS);
33338 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33339 IX86_BUILTIN_GATHERPFQPD);
33341 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33342 IX86_BUILTIN_GATHERPFQPS);
33344 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
33345 IX86_BUILTIN_SCATTERPFDPD);
33347 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
33348 IX86_BUILTIN_SCATTERPFDPS);
33350 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
33351 IX86_BUILTIN_SCATTERPFQPD);
33353 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
33354 IX86_BUILTIN_SCATTERPFQPS);
33356 /* SHA */
33372 /* RTM. */
33376 /* MMX access to the vec_init patterns. */
33381 V4HI_FTYPE_HI_HI_HI_HI,
33382 IX86_BUILTIN_VEC_INIT_V4HI);
33385 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
33386 IX86_BUILTIN_VEC_INIT_V8QI);
33388 /* Access to the vec_extract patterns. */
33410 /* Access to the vec_set patterns. */
33431 /* RDSEED */
33440 /* ADCX */
33445 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
33446 IX86_BUILTIN_ADDCARRYX64);
33448 /* Read/write FLAGS. */
33458 /* CLFLUSHOPT. */
33462 /* Add FMA4 multi-arg argument instructions */
33464 {
33470 }
33471 }
33473 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
33474 to return a pointer to VERSION_DECL if the outcome of the expression
33475 formed by PREDICATE_CHAIN is true. This function will be called during
33476 version dispatch to decide which function version to execute. It returns
33477 the basic block at the end, to which more conditions can be added. */
33479 static basic_block
33482 {
33483 gimple return_stmt;
33485 gimple convert_stmt;
33486 gimple call_cond_stmt;
33487 gimple if_else_stmt;
33493 gimple_seq gseq;
33510 {
33518 }
33521 {
33536 else
33537 {
33538 gimple assign_stmt;
33539 /* Use MIN_EXPR to check if any integer is zero?.
33540 and_expr_var = min_expr <cond_var, and_expr_var> */
33548 }
33549 }
33552 integer_zero_node,
33582 }
33584 /* This parses the attribute arguments to target in DECL and determines
33585 the right builtin to use to match the platform specification.
33586 It returns the priority value for this version decl. If PREDICATE_LIST
33587 is not NULL, it stores the list of cpu features that need to be checked
33588 before dispatching this function. */
33590 static unsigned int
33592 {
33593 tree attrs;
33595 tree target_node;
33602 /* Priority of i386 features, greater value is higher priority. This is
33603 used to decide the order in which function dispatch must happen. For
33604 instance, a version specialized for SSE4.2 should be checked for dispatch
33605 before a version for SSE3, as SSE4.2 implies SSE3. */
33606 enum feature_priority
33607 {
33609 P_MMX,
33610 P_SSE,
33611 P_SSE2,
33612 P_SSE3,
33613 P_SSSE3,
33614 P_PROC_SSSE3,
33615 P_SSE4_A,
33616 P_PROC_SSE4_A,
33617 P_SSE4_1,
33618 P_SSE4_2,
33619 P_PROC_SSE4_2,
33620 P_POPCNT,
33621 P_AVX,
33622 P_PROC_AVX,
33623 P_FMA4,
33624 P_XOP,
33625 P_PROC_XOP,
33626 P_FMA,
33627 P_PROC_FMA,
33628 P_AVX2,
33629 P_PROC_AVX2
33630 };
33634 /* These are the target attribute strings for which a dispatcher is
33635 available, from fold_builtin_cpu. */
33637 static struct _feature_list
33638 {
33641 }
33643 {
33658 };
33661 static unsigned int NUM_FEATURES
33677 /* Return priority zero for default function. */
33681 /* Handle arch= if specified. For priority, set it to be 1 more than
33682 the best instruction set the processor can handle. For instance, if
33683 there is a version for atom and a version for ssse3 (the highest ISA
33684 priority for atom), the atom version must be checked for dispatch
33685 before the ssse3 version. */
33687 {
33697 {
33699 {
33707 else
33708 /* We translate "arch=corei7" and "arch=nehalem" to
33709 "corei7" so that it will be mapped to M_INTEL_COREI7
33710 as cpu type to cover all M_INTEL_COREI7_XXXs. */
33717 else
33724 else
33764 }
33765 }
33770 {
33774 }
33777 {
33779 /* For a C string literal the length includes the trailing NULL. */
33782 predicate_chain);
33783 }
33784 }
33786 /* Process feature name. */
33793 {
33794 /* Do not process "arch=" */
33796 {
33799 }
33801 {
33803 {
33805 {
33810 predicate_chain);
33811 }
33812 /* Find the maximum priority feature. */
33817 }
33818 }
33820 {
33824 }
33826 }
33830 {
33833 attrs_str);
33835 }
33837 {
33840 }
33843 }
33845 /* This compares the priority of target features in function DECL1
33846 and DECL2. It returns positive value if DECL1 is higher priority,
33847 negative value if DECL2 is higher priority and 0 if they are the
33848 same. */
33850 static int
33852 {
33857 }
33859 /* V1 and V2 point to function versions with different priorities
33860 based on the target ISA. This function compares their priorities. */
33862 static int
33864 {
33866 {
33867 tree version_decl;
33868 tree predicate_chain;
33875 }
33877 /* This function generates the dispatch function for
33878 multi-versioned functions. DISPATCH_DECL is the function which will
33879 contain the dispatch logic. FNDECLS are the function choices for
33880 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
33881 in DISPATCH_DECL in which the dispatch code is generated. */
33883 static int
33887 {
33888 tree default_decl;
33889 gimple ifunc_cpu_init_stmt;
33890 gimple_seq gseq;
33892 tree ele;
33898 struct _function_version_info
33899 {
33900 tree version_decl;
33901 tree predicate_chain;
33909 /*fndecls_p is actually a vector. */
33912 /* At least one more version other than the default. */
33919 /* The first version in the vector is the default decl. */
33925 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
33926 constructors, so explicity call __builtin_cpu_init here. */
33937 {
33941 /* Get attribute string, parse it and find the right predicate decl.
33942 The predicate function could be a lengthy combination of many
33943 features, like arch-type and various isa-variants. */
33954 actual_versions++;
33955 }
33957 /* Sort the versions according to descending order of dispatch priority. The
33958 priority is based on the ISA. This is not a perfect solution. There
33959 could still be ambiguity. If more than one function version is suitable
33960 to execute, which one should be dispatched? In future, allow the user
33961 to specify a dispatch priority next to the version. */
33971 /* dispatch default version at the end. */
33977 }
33979 /* Comparator function to be used in qsort routine to sort attribute
33980 specification strings to "target". */
33982 static int
33984 {
33988 }
33990 /* ARGLIST is the argument to target attribute. This function tokenizes
33991 the comma separated arguments, sorts them and returns a string which
33992 is a unique identifier for the comma separated arguments. It also
33993 replaces non-identifier characters "=,-" with "_". */
33997 {
33998 tree arg;
34007 {
34012 argnum++;
34015 argnum++;
34016 }
34021 {
34027 }
34029 /* Replace "=,-" with "_". */
34042 {
34044 i++;
34046 }
34053 {
34058 }
34063 }
34065 /* This function changes the assembler name for functions that are
34066 versions. If DECL is a function version and has a "target"
34067 attribute, it appends the attribute string to its assembler name. */
34069 static tree
34071 {
34072 tree version_attr;
34080 "Function versions cannot be marked as gnu_inline,"
34089 /* target attribute string cannot be NULL. */
34093 version_string
34104 /* Allow assembler name to be modified if already set. */
34112 }
34114 /* This function returns true if FN1 and FN2 are versions of the same function,
34115 that is, the target strings of the function decls are different. This assumes
34116 that FN1 and FN2 have the same signature. */
34118 static bool
34120 {
34132 /* At least one function decl should have the target attribute specified. */
34136 /* Diagnose missing target attribute if one of the decls is already
34137 multi-versioned. */
34139 {
34141 {
34143 {
34148 }
34151 fn2);
34154 /* Prevent diagnosing of the same error multiple times. */
34159 }
34161 }
34166 /* The sorted target strings must be different for fn1 and fn2
34167 to be versions. */
34170 else
34177 }
34179 static tree
34181 {
34182 /* For function version, add the target suffix to the assembler name. */
34186 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34188 #endif
34191 }
34193 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34194 is true, append the full path name of the source file. */
34198 {
34206 /* Get a unique name that can be used globally without any chances
34207 of collision at link time. */
34217 /* Use '.' to concatenate names as it is demangler friendly. */
34220 suffix);
34221 else
34225 }
34227 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34229 /* Make a dispatcher declaration for the multi-versioned function DECL.
34230 Calls to DECL function will be replaced with calls to the dispatcher
34231 by the front-end. Return the decl created. */
34233 static tree
34235 {
34236 tree func_decl;
34256 /* Mark this func as external, the resolver will flip it again if
34257 it gets generated. */
34259 /* This will be of type IFUNCs have to be externally visible. */
34263 }
34265 #endif
34267 /* Returns true if decl is multi-versioned and DECL is the default function,
34268 that is it is not tagged with target specific optimization. */
34270 static bool
34272 {
34281 }
34283 /* Make a dispatcher declaration for the multi-versioned function DECL.
34284 Calls to DECL function will be replaced with calls to the dispatcher
34285 by the front-end. Returns the decl of the dispatcher function. */
34287 static tree
34289 {
34311 /* Find the default version and make it the first node. */
34313 /* Go to the beginning of the chain. */
34318 {
34323 }
34325 /* If there is no default node, just return NULL. */
34329 /* Make default info the first node. */
34331 {
34338 }
34342 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
34344 {
34349 /* Right now, the dispatching is done via ifunc. */
34355 dispatcher_version_info
34360 /* Set the dispatcher for all the versions. */
34363 {
34366 }
34367 }
34368 else
34369 #endif
34370 {
34372 "multiversioning needs ifunc which is not supported "
34374 }
34377 }
34379 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
34380 it to CHAIN. */
34382 static tree
34384 {
34385 tree attr_name;
34386 tree attr_arg_name;
34387 tree attr_args;
34388 tree attr;
34395 }
34397 /* Make the resolver function decl to dispatch the versions of
34398 a multi-versioned function, DEFAULT_DECL. Create an
34399 empty basic block in the resolver and store the pointer in
34400 EMPTY_BB. Return the decl of the resolver function. */
34402 static tree
34406 {
34411 /* IFUNC's have to be globally visible. So, if the default_decl is
34412 not, then the name of the IFUNC should be made unique. */
34416 /* Append the filename to the resolver function if the versions are
34417 not externally visible. This is because the resolver function has
34418 to be externally visible for the loader to find it. So, appending
34419 the filename will prevent conflicts with a resolver function from
34420 another module which is based on the same version name. */
34423 /* The resolver function should return a (void *). */
34434 /* IFUNC resolvers have to be externally visible. */
34438 /* Resolver is not external, body is generated. */
34448 {
34449 /* In this case, each translation unit with a call to this
34450 versioned function will put out a resolver. Ensure it
34451 is comdat to keep just one copy. */
34454 }
34455 /* Build result decl and add to function_decl. */
34471 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
34475 /* Create the alias for dispatch to resolver here. */
34476 /*cgraph_create_function_alias (dispatch_decl, decl);*/
34480 }
34482 /* Generate the dispatching code body to dispatch multi-versioned function
34483 DECL. The target hook is called to process the "target" attributes and
34484 provide the code to dispatch the right function at run-time. NODE points
34485 to the dispatcher decl whose body will be created. */
34487 static tree
34489 {
34490 tree resolver_decl;
34491 basic_block empty_bb;
34492 tree default_ver_decl;
34508 /* The first version in the chain corresponds to the default version. */
34511 /* node is going to be an alias, so remove the finalized bit. */
34525 {
34527 /* Check for virtual functions here again, as by this time it should
34528 have been determined if this function needs a vtable index or
34529 not. This happens for methods in derived classes that override
34530 virtual methods in base classes but are not explicitly marked as
34531 virtual. */
34536 }
34542 }
34543 /* This builds the processor_model struct type defined in
34544 libgcc/config/i386/cpuinfo.c */
34546 static tree
34548 {
34555 /* The first 3 fields are unsigned int. */
34557 {
34563 }
34565 /* The last field is an array of unsigned integers of size one. */
34576 }
34578 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
34580 static tree
34582 {
34583 tree new_decl;
34586 VAR_DECL,
34588 type);
34601 }
34603 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
34604 into an integer defined in libgcc/config/i386/cpuinfo.c */
34606 static tree
34608 {
34614 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
34615 enum processor_features
34616 {
34618 F_MMX,
34619 F_POPCNT,
34620 F_SSE,
34621 F_SSE2,
34622 F_SSE3,
34623 F_SSSE3,
34624 F_SSE4_1,
34625 F_SSE4_2,
34626 F_AVX,
34627 F_AVX2,
34628 F_SSE4_A,
34629 F_FMA4,
34630 F_XOP,
34631 F_FMA,
34632 F_MAX
34633 };
34635 /* These are the values for vendor types and cpu types and subtypes
34636 in cpuinfo.c. Cpu types and subtypes should be subtracted by
34637 the corresponding start value. */
34638 enum processor_model
34639 {
34641 M_AMD,
34642 M_CPU_TYPE_START,
34643 M_INTEL_BONNELL,
34644 M_INTEL_CORE2,
34645 M_INTEL_COREI7,
34646 M_AMDFAM10H,
34647 M_AMDFAM15H,
34648 M_INTEL_SILVERMONT,
34649 M_AMD_BTVER1,
34650 M_AMD_BTVER2,
34651 M_CPU_SUBTYPE_START,
34652 M_INTEL_COREI7_NEHALEM,
34653 M_INTEL_COREI7_WESTMERE,
34654 M_INTEL_COREI7_SANDYBRIDGE,
34655 M_AMDFAM10H_BARCELONA,
34656 M_AMDFAM10H_SHANGHAI,
34657 M_AMDFAM10H_ISTANBUL,
34658 M_AMDFAM15H_BDVER1,
34659 M_AMDFAM15H_BDVER2,
34660 M_AMDFAM15H_BDVER3,
34661 M_AMDFAM15H_BDVER4,
34662 M_INTEL_COREI7_IVYBRIDGE,
34663 M_INTEL_COREI7_HASWELL
34664 };
34666 static struct _arch_names_table
34667 {
34670 }
34672 {
34697 };
34699 static struct _isa_names_table
34700 {
34703 }
34705 {
34721 };
34735 {
34736 /* *args must be a expr that can contain other EXPRS leading to a
34737 STRING_CST. */
34739 {
34742 }
34744 }
34749 {
34750 tree ref;
34751 tree field;
34752 tree final;
34755 unsigned int NUM_ARCH_NAMES
34764 {
34768 }
34773 /* CPU types are stored in the next field. */
34776 {
34779 }
34781 /* CPU subtypes are stored in the next field. */
34783 {
34786 }
34788 /* Get the appropriate field in __cpu_model. */
34792 /* Check the value. */
34796 }
34798 {
34799 tree ref;
34800 tree array_elt;
34801 tree field;
34802 tree final;
34805 unsigned int NUM_ISA_NAMES
34814 {
34818 }
34821 /* Get the last field, which is __cpu_features. */
34825 /* Get the appropriate field: __cpu_model.__cpu_features */
34829 /* Access the 0th element of __cpu_features array. */
34834 /* Return __cpu_model.__cpu_features[0] & field_val */
34838 }
34840 }
34842 static tree
34845 {
34847 {
34852 {
34855 }
34856 }
34858 #ifdef SUBTARGET_FOLD_BUILTIN
34860 #endif
34863 }
34865 /* Make builtins to detect cpu type and features supported. NAME is
34866 the builtin name, CODE is the builtin code, and FTYPE is the function
34867 type of the builtin. */
34869 static void
34872 {
34873 tree decl;
34874 tree type;
34882 }
34884 /* Make builtins to get CPU type and features supported. The created
34885 builtins are :
34887 __builtin_cpu_init (), to detect cpu type and features,
34888 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
34889 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
34890 */
34892 static void
34894 {
34901 }
34903 /* Internal method for ix86_init_builtins. */
34905 static void
34907 {
34919 sysv_va_ref =
34922 fnvoid_va_end_ms =
34924 fnvoid_va_start_ms =
34926 fnvoid_va_end_sysv =
34928 fnvoid_va_start_sysv =
34930 NULL_TREE);
34931 fnvoid_va_copy_ms =
34933 NULL_TREE);
34934 fnvoid_va_copy_sysv =
34950 }
34952 static void
34954 {
34957 /* The __float80 type. */
34960 {
34961 /* The __float80 type. */
34966 }
34969 /* The __float128 type. */
34975 /* This macro is built by i386-builtin-types.awk. */
34976 DEFINE_BUILTIN_PRIMITIVE_TYPES;
34977 }
34979 static void
34981 {
34982 tree t;
34986 /* Builtins to get CPU type and features. */
34989 /* TFmode support builtins. */
34995 /* We will expand them to normal call if SSE isn't available since
34996 they are used by libgcc. */
35015 #ifdef SUBTARGET_INIT_BUILTINS
35016 SUBTARGET_INIT_BUILTINS;
35017 #endif
35018 }
35020 /* Return the ix86 builtin for CODE. */
35022 static tree
35024 {
35029 }
35031 /* Errors in the source file can cause expand_expr to return const0_rtx
35032 where we expect a vector. To avoid crashing, use one of the vector
35033 clear instructions. */
35034 static rtx
35036 {
35040 }
35042 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35044 static rtx
35046 {
35047 rtx pat;
35067 {
35071 }
35085 }
35087 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35089 static rtx
35093 {
35094 rtx pat;
35102 rtx op;
35109 {
35189 }
35199 {
35206 {
35208 {
35211 {
35229 xop_rotl:
35231 {
35234 gcc_checking_assert
35236 }
35237 else
35238 {
35239 gcc_checking_assert
35250 }
35254 }
35255 }
35256 }
35257 else
35258 {
35259 non_constant:
35263 /* If we aren't optimizing, only allow one memory operand to be
35264 generated. */
35266 num_memory++;
35274 }
35278 }
35281 {
35292 else
35293 {
35299 }
35312 }
35319 }
35321 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
35322 insns with vec_merge. */
35324 static rtx
35326 rtx target)
35327 {
35328 rtx pat;
35355 }
35357 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
35359 static rtx
35362 {
35363 rtx pat;
35368 rtx op2;
35379 /* Swap operands if we have a comparison that isn't available in
35380 hardware. */
35382 {
35387 }
35407 }
35409 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
35411 static rtx
35413 rtx target)
35414 {
35415 rtx pat;
35429 /* Swap operands if we have a comparison that isn't available in
35430 hardware. */
35432 {
35436 }
35457 const0_rtx)));
35460 }
35462 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
35464 static rtx
35466 rtx target)
35467 {
35468 rtx pat;
35493 }
35495 static rtx
35498 {
35499 rtx pat;
35504 rtx op2;
35531 }
35533 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
35535 static rtx
35537 rtx target)
35538 {
35539 rtx pat;
35572 const0_rtx)));
35575 }
35577 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
35579 static rtx
35582 {
35583 rtx pat;
35621 {
35624 }
35627 {
35636 }
35638 {
35647 }
35648 else
35649 {
35656 }
35664 {
35669 emit_insn
35673 FLAGS_REG),
35674 const0_rtx)));
35676 }
35677 else
35679 }
35682 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
35684 static rtx
35687 {
35688 rtx pat;
35716 {
35719 }
35722 {
35731 }
35733 {
35742 }
35743 else
35744 {
35751 }
35759 {
35764 emit_insn
35768 FLAGS_REG),
35769 const0_rtx)));
35771 }
35772 else
35774 }
35776 /* Subroutine of ix86_expand_builtin to take care of insns with
35777 variable number of operands. */
35779 static rtx
35782 {
35788 struct
35789 {
35790 rtx op;
35802 {
36509 }
36514 {
36517 }
36520 {
36527 }
36528 else
36529 {
36532 }
36535 {
36542 {
36543 /* SIMD shift insns take either an 8-bit immediate or
36544 register as count. But builtin functions take int as
36545 count. If count doesn't match, we put it in register. */
36547 {
36551 }
36552 }
36555 {
36558 {
36667 {
36671 {
36674 }
36680 }
36682 }
36683 }
36684 else
36685 {
36689 /* If we aren't optimizing, only allow one memory operand to
36690 be generated. */
36692 num_memory++;
36695 {
36698 }
36699 else
36700 {
36703 }
36704 }
36708 }
36711 {
36736 }
36743 }
36745 /* Transform pattern of following layout:
36746 (parallel [
36747 set (A B)
36748 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
36749 ])
36750 into:
36751 (set (A B))
36753 Or:
36754 (parallel [ A B
36755 ...
36756 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
36757 ...
36758 ])
36759 into:
36760 (parallel [ A B ... ]) */
36762 static rtx
36764 {
36771 {
36780 }
36781 else
36782 {
36788 {
36793 }
36795 /* No more than 1 occurence was removed. */
36799 }
36800 }
36802 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
36803 with rounding. */
36804 static rtx
36807 {
36824 /* See avxintrin.h for values. */
36826 {
36830 };
36832 {
36837 };
36840 {
36843 }
36845 {
36848 }
36851 {
36854 }
36877 ? CODE_FOR_sse_ucomi_round
36884 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
36886 {
36892 }
36893 else
36894 {
36897 }
36903 set_dst,
36904 const0_rtx)));
36907 }
36909 static rtx
36912 {
36913 rtx pat;
36915 struct
36916 {
36917 rtx op;
36927 {
37010 }
37020 {
37027 {
37029 {
37031 {
37047 }
37048 }
37049 }
37051 {
37053 {
37056 }
37058 /* If there is no rounding use normal version of the pattern. */
37061 }
37062 else
37063 {
37068 {
37071 }
37072 else
37073 {
37076 }
37077 }
37081 }
37084 {
37109 }
37119 }
37121 /* Subroutine of ix86_expand_builtin to take care of special insns
37122 with variable number of operands. */
37124 static rtx
37127 {
37128 tree arg;
37132 struct
37133 {
37134 rtx op;
37144 {
37184 {
37192 }
37211 /* Reserve memory operand for target. */
37214 {
37215 /* These builtins and instructions require the memory
37216 to be properly aligned. */
37235 }
37264 {
37265 /* These builtins and instructions require the memory
37266 to be properly aligned. */
37283 }
37284 /* FALLTHRU */
37322 /* Reserve memory operand for target. */
37349 {
37350 /* These builtins and instructions require the memory
37351 to be properly aligned. */
37374 }
37387 }
37392 {
37397 {
37400 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
37401 on it. Try to improve it using get_pointer_alignment,
37402 and if the special builtin is one that requires strict
37403 mode alignment, also from it's GET_MODE_ALIGNMENT.
37404 Failure to do so could lead to ix86_legitimate_combined_insn
37405 rejecting all changes to such insns. */
37411 }
37412 else
37415 }
37416 else
37417 {
37424 }
37427 {
37436 {
37438 {
37444 else
37447 }
37448 }
37449 else
37450 {
37452 {
37453 /* This must be the memory operand. */
37456 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
37457 on it. Try to improve it using get_pointer_alignment,
37458 and if the special builtin is one that requires strict
37459 mode alignment, also from it's GET_MODE_ALIGNMENT.
37460 Failure to do so could lead to ix86_legitimate_combined_insn
37461 rejecting all changes to such insns. */
37467 }
37468 else
37469 {
37470 /* This must be register. */
37476 else
37477 {
37480 }
37481 }
37482 }
37486 }
37489 {
37504 }
37510 }
37512 /* Return the integer constant in ARG. Constrain it to be in the range
37513 of the subparts of VEC_TYPE; issue an error if not. */
37515 static int
37517 {
37522 {
37525 }
37528 }
37530 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
37531 ix86_expand_vector_init. We DO have language-level syntax for this, in
37532 the form of (type){ init-list }. Except that since we can't place emms
37533 instructions from inside the compiler, we can't allow the use of MMX
37534 registers unless the user explicitly asks for it. So we do *not* define
37535 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
37536 we have builtins invoked by mmintrin.h that gives us license to emit
37537 these sorts of instructions. */
37539 static rtx
37541 {
37551 {
37554 }
37561 }
37563 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
37564 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
37565 had a language-level syntax for referencing vector elements. */
37567 static rtx
37569 {
37573 rtx op0;
37593 }
37595 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
37596 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
37597 a language-level syntax for referencing vector elements. */
37599 static rtx
37601 {
37625 /* OP0 is the source of these builtin functions and shouldn't be
37626 modified. Create a copy, use it and return it as target. */
37632 }
37634 /* Expand an expression EXP that calls a built-in function,
37635 with result going to TARGET if that's convenient
37636 (and in mode MODE if that's convenient).
37637 SUBTARGET may be used as the target for computing one of EXP's operands.
37638 IGNORE is nonzero if the value is to be ignored. */
37640 static rtx
37643 {
37653 /* For CPU builtins that can be folded, fold first and expand the fold. */
37655 {
37657 {
37658 /* Make it call __cpu_indicator_init in libgcc. */
37664 }
37667 {
37672 }
37673 }
37675 /* Determine whether the builtin function is available under the current ISA.
37676 Originally the builtin was not created if it wasn't applicable to the
37677 current ISA based on the command line switches. With function specific
37678 options, we need to check in the context of the function making the call
37679 whether it is supported. */
37682 {
37688 else
37689 {
37693 }
37695 }
37698 {
37702 ? CODE_FOR_mmx_maskmovq
37704 /* Note the arg order is different from the operand order. */
37815 {
37816 REAL_VALUE_TYPE inf;
37817 rtx tmp;
37829 }
37839 {
37845 insn = (TARGET_64BIT
37849 }
37851 {
37852 insn = (TARGET_64BIT
37856 }
37857 else
37858 {
37861 insn = (TARGET_64BIT
37869 {
37872 }
37874 }
37877 {
37878 /* mode is VOIDmode if __builtin_rd* has been called
37879 without lhs. */
37883 }
37886 {
37891 }
37904 {
37925 }
37931 {
37934 }
37960 {
37963 }
37969 {
37973 {
38012 }
38017 }
38018 else
38019 {
38021 {
38042 }
38044 }
38074 ? CODE_FOR_tbm_bextri_si
38077 {
38080 }
38081 else
38082 {
38091 }
38107 rdrand_step:
38114 {
38117 }
38123 /* Emit SImode conditional move. */
38125 {
38128 }
38131 else
38139 const0_rtx);
38158 rdseed_step:
38165 {
38168 }
38174 const0_rtx);
38193 addcarryx:
38201 /* Generate CF from input operand. */
38206 /* Gen ADCX instruction to compute X+Y+CF. */
38221 /* Store the result. */
38224 {
38227 }
38230 /* Return current CF value. */
38272 kortest:
38286 /* Emit kortest. */
38288 /* And use setcc to return result from flags. */
38546 gather_gen:
38547 rtx half;
38560 /* Note the arg order is different from the operand order. */
38571 else
38575 {
38599 else
38606 {
38611 }
38620 else
38627 {
38632 }
38636 }
38638 /* Force memory operand only with base register here. But we
38639 don't want to do it on memory operand for other builtin
38640 functions. */
38650 {
38653 }
38654 else
38655 {
38658 }
38660 {
38663 }
38665 /* Optimize. If mask is known to have all high bits set,
38666 replace op0 with pc_rtx to signal that the instruction
38667 overwrites the whole destination and doesn't use its
38668 previous contents. */
38670 {
38672 {
38675 }
38677 {
38680 {
38684 negative++;
38687 negative++;
38688 }
38691 }
38694 {
38695 /* Recognize also when mask is like:
38696 __v2df src = _mm_setzero_pd ();
38697 __v2df mask = _mm_cmpeq_pd (src, src);
38698 or
38699 __v8sf src = _mm256_setzero_ps ();
38700 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
38701 as that is a cheaper way to load all ones into
38702 a register than having to load a constant from
38703 memory. */
38706 {
38711 {
38718 /* FALLTHRU */
38728 }
38729 }
38730 }
38731 }
38739 {
38765 }
38768 scatter_gen:
38784 /* Force memory operand only with base register here. But we
38785 don't want to do it on memory operand for other builtin
38786 functions. */
38793 {
38796 }
38797 else
38798 {
38801 }
38810 {
38813 }
38822 vec_prefetch_gen:
38840 {
38843 }
38845 {
38848 }
38853 /* Force memory operand only with base register here. But we
38854 don't want to do it on memory operand for other builtin
38855 functions. */
38862 {
38865 }
38868 {
38871 }
38887 {
38890 }
38896 }
38909 {
38913 /* Emit a normal call if SSE isn't available. */
38917 }
38946 }
38948 /* This returns the target-specific builtin with code CODE if
38949 current_function_decl has visibility on this builtin, which is checked
38950 using isa flags. Returns NULL_TREE otherwise. */
38953 {
38957 /* Determine the isa flags of current_function_decl. */
38969 else
38971 }
38973 /* Returns a function decl for a vectorized version of the builtin function
38974 with builtin function code FN and the result vector type TYPE, or NULL_TREE
38975 if it is not available. */
38977 static tree
38979 tree type_in)
38980 {
38996 {
38999 {
39006 }
39011 {
39014 }
39019 {
39026 }
39032 /* The round insn does not trap on denormals. */
39037 {
39044 }
39050 /* The round insn does not trap on denormals. */
39055 {
39060 }
39066 /* The round insn does not trap on denormals. */
39071 {
39078 }
39084 /* The round insn does not trap on denormals. */
39089 {
39094 }
39101 {
39106 }
39113 {
39118 }
39124 /* The round insn does not trap on denormals. */
39129 {
39136 }
39142 /* The round insn does not trap on denormals. */
39147 {
39152 }
39157 {
39164 }
39169 {
39176 }
39180 /* The round insn does not trap on denormals. */
39185 {
39190 }
39194 /* The round insn does not trap on denormals. */
39199 {
39204 }
39208 /* The round insn does not trap on denormals. */
39213 {
39218 }
39222 /* The round insn does not trap on denormals. */
39227 {
39232 }
39236 /* The round insn does not trap on denormals. */
39241 {
39246 }
39250 /* The round insn does not trap on denormals. */
39255 {
39260 }
39264 /* The round insn does not trap on denormals. */
39269 {
39274 }
39278 /* The round insn does not trap on denormals. */
39283 {
39288 }
39292 /* The round insn does not trap on denormals. */
39297 {
39302 }
39306 /* The round insn does not trap on denormals. */
39311 {
39316 }
39321 {
39326 }
39331 {
39336 }
39341 }
39343 /* Dispatch to a handler for a vectorization library. */
39346 type_in);
39349 }
39351 /* Handler for an SVML-style interface to
39352 a library with vectorized intrinsics. */
39354 static tree
39356 {
39364 /* The SVML is suitable for unsafe math only. */
39377 {
39424 }
39433 {
39436 }
39437 else
39440 /* Convert to uppercase. */
39445 args;
39447 arity++;
39451 else
39454 /* Build a function declaration for the vectorized function. */
39463 }
39465 /* Handler for an ACML-style interface to
39466 a library with vectorized intrinsics. */
39468 static tree
39470 {
39478 /* The ACML is 64bits only and suitable for unsafe math only as
39479 it does not correctly support parts of IEEE with the required
39480 precision such as denormals. */
39494 {
39524 }
39531 args;
39533 arity++;
39537 else
39540 /* Build a function declaration for the vectorized function. */
39549 }
39551 /* Returns a decl of a function that implements gather load with
39552 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
39553 Return NULL_TREE if it is not available. */
39555 static tree
39558 {
39574 /* v*gather* insn sign extends index to pointer mode. */
39586 {
39590 else
39596 else
39602 else
39608 else
39614 else
39620 else
39626 else
39632 else
39638 else
39644 else
39650 else
39656 else
39661 }
39664 }
39666 /* Returns a code for a target-specific builtin that implements
39667 reciprocal of the function, or NULL_TREE if not available. */
39669 static tree
39672 {
39679 /* Machine dependent builtins. */
39681 {
39682 /* Vectorized version of sqrt to rsqrt conversion. */
39691 }
39692 else
39693 /* Normal builtins. */
39695 {
39696 /* Sqrt to rsqrt conversion. */
39702 }
39703 }
39704 \f
39705 /* Helper for avx_vpermilps256_operand et al. This is also used by
39706 the expansion functions to turn the parallel back into a mask.
39707 The return value is 0 for no match and the imm8+1 for a match. */
39709 int
39711 {
39719 /* Validate that all of the elements are constants, and not totally
39720 out of range. Copy the data into an integral array to make the
39721 subsequent checks easier. */
39723 {
39733 }
39736 {
39738 /* In the 512-bit DFmode case, we can only move elements within
39739 a 128-bit lane. First fill the second part of the mask,
39740 then fallthru. */
39742 {
39746 }
39748 {
39752 }
39753 /* FALLTHRU */
39756 /* In the 256-bit DFmode case, we can only move elements within
39757 a 128-bit lane. */
39759 {
39763 }
39765 {
39769 }
39773 /* In 512 bit SFmode case, permutation in the upper 256 bits
39774 must mirror the permutation in the lower 256-bits. */
39778 /* FALLTHRU */
39781 /* In 256 bit SFmode case, we have full freedom of
39782 movement within the low 128-bit lane, but the high 128-bit
39783 lane must mirror the exact same pattern. */
39788 /* FALLTHRU */
39792 /* In the 128-bit case, we've full freedom in the placement of
39793 the elements from the source operand. */
39800 }
39802 /* Make sure success has a non-zero value by adding one. */
39804 }
39806 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
39807 the expansion functions to turn the parallel back into a mask.
39808 The return value is 0 for no match and the imm8+1 for a match. */
39810 int
39812 {
39820 /* Validate that all of the elements are constants, and not totally
39821 out of range. Copy the data into an integral array to make the
39822 subsequent checks easier. */
39824 {
39834 }
39836 /* Validate that the halves of the permute are halves. */
39844 /* Reconstruct the mask. */
39846 {
39852 }
39854 /* Make sure success has a non-zero value by adding one. */
39856 }
39857 \f
39858 /* Return a register priority for hard reg REGNO. */
39859 static int
39861 {
39862 /* ebp and r13 as the base always wants a displacement, r12 as the
39863 base always wants an index. So discourage their usage in an
39864 address. */
39869 /* New x86-64 int registers result in bigger code size. Discourage
39870 them. */
39873 /* New x86-64 SSE registers result in bigger code size. Discourage
39874 them. */
39877 /* Usage of AX register results in smaller code. Prefer it. */
39881 }
39883 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
39885 Put float CONST_DOUBLE in the constant pool instead of fp regs.
39886 QImode must go into class Q_REGS.
39887 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
39888 movdf to do mem-to-mem moves through integer regs. */
39890 static reg_class_t
39892 {
39895 /* We're only allowed to return a subclass of CLASS. Many of the
39896 following checks fail for NO_REGS, so eliminate that early. */
39900 /* All classes can load zeros. */
39904 /* Force constants into memory if we are loading a (nonzero) constant into
39905 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
39906 instructions to load from a constant. */
39913 /* Prefer SSE regs only, if we can use them for math. */
39917 /* Floating-point constants need more complex checks. */
39919 {
39920 /* General regs can load everything. */
39924 /* Floats can load 0 and 1 plus some others. Note that we eliminated
39925 zero above. We only want to wind up preferring 80387 registers if
39926 we plan on doing computation with them. */
39929 {
39930 /* Limit class to non-sse. */
39939 }
39942 }
39944 /* Generally when we see PLUS here, it's the function invariant
39945 (plus soft-fp const_int). Which can only be computed into general
39946 regs. */
39950 /* QImode constants are easy to load, but non-constant QImode data
39951 must go into Q_REGS. */
39953 {
39959 }
39962 }
39964 /* Discourage putting floating-point values in SSE registers unless
39965 SSE math is being used, and likewise for the 387 registers. */
39966 static reg_class_t
39968 {
39971 /* Restrict the output reload class to the register bank that we are doing
39972 math on. If we would like not to return a subset of CLASS, reject this
39973 alternative: if reload cannot do this, it will still use its choice. */
39979 {
39984 else
39986 }
39989 }
39991 static reg_class_t
39994 {
39995 /* Double-word spills from general registers to non-offsettable memory
39996 references (zero-extended addresses) require special handling. */
40002 {
40004 ? CODE_FOR_reload_noff_load
40006 /* Add the cost of moving address to a temporary. */
40010 }
40012 /* QImode spills from non-QI registers require
40013 intermediate register on 32bit targets. */
40019 {
40024 else
40030 /* Return Q_REGS if the operand is in memory. */
40033 }
40035 /* This condition handles corner case where an expression involving
40036 pointers gets vectorized. We're trying to use the address of a
40037 stack slot as a vector initializer.
40039 (set (reg:V2DI 74 [ vect_cst_.2 ])
40040 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
40042 Eventually frame gets turned into sp+offset like this:
40044 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
40045 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
40046 (const_int 392 [0x188]))))
40048 That later gets turned into:
40050 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
40051 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
40052 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
40054 We'll have the following reload recorded:
40056 Reload 0: reload_in (DI) =
40057 (plus:DI (reg/f:DI 7 sp)
40058 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
40059 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
40060 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
40061 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
40062 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
40063 reload_reg_rtx: (reg:V2DI 22 xmm1)
40065 Which isn't going to work since SSE instructions can't handle scalar
40066 additions. Returning GENERAL_REGS forces the addition into integer
40067 register and reload can handle subsequent reloads without problems. */
40075 }
40077 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
40079 static bool
40081 {
40083 {
40098 }
40101 }
40103 /* If we are copying between general and FP registers, we need a memory
40104 location. The same is true for SSE and MMX registers.
40106 To optimize register_move_cost performance, allow inline variant.
40108 The macro can't work reliably when one of the CLASSES is class containing
40109 registers from multiple units (SSE, MMX, integer). We avoid this by never
40110 combining those units in single alternative in the machine description.
40111 Ensure that this constraint holds to avoid unexpected surprises.
40113 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
40114 enforce these sanity checks. */
40119 {
40128 {
40131 }
40136 /* Between mask and general, we have moves no larger than word size. */
40141 /* ??? This is a lie. We do have moves between mmx/general, and for
40142 mmx/sse2. But by saying we need secondary memory we discourage the
40143 register allocator from using the mmx registers unless needed. */
40148 {
40149 /* SSE1 doesn't have any direct moves from other classes. */
40153 /* If the target says that inter-unit moves are more expensive
40154 than moving through memory, then don't generate them. */
40159 /* Between SSE and general, we have moves no larger than word size. */
40162 }
40165 }
40167 bool
40170 {
40172 }
40174 /* Implement the TARGET_CLASS_MAX_NREGS hook.
40176 On the 80386, this is the size of MODE in words,
40177 except in the FP regs, where a single reg is always enough. */
40179 static unsigned char
40181 {
40183 {
40188 else
40190 }
40191 else
40192 {
40195 else
40197 }
40198 }
40200 /* Return true if the registers in CLASS cannot represent the change from
40201 modes FROM to TO. */
40203 bool
40206 {
40210 /* x87 registers can't do subreg at all, as all values are reformatted
40211 to extended precision. */
40216 {
40217 /* Vector registers do not support QI or HImode loads. If we don't
40218 disallow a change to these modes, reload will assume it's ok to
40219 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
40220 the vec_dupv4hi pattern. */
40224 /* Vector registers do not support subreg with nonzero offsets, which
40225 are otherwise valid for integer registers. Since we can't see
40226 whether we have a nonzero offset from here, prohibit all
40227 nonparadoxical subregs changing size. */
40230 }
40233 }
40235 /* Return the cost of moving data of mode M between a
40236 register and memory. A value of 2 is the default; this cost is
40237 relative to those in `REGISTER_MOVE_COST'.
40239 This function is used extensively by register_move_cost that is used to
40240 build tables at startup. Make it inline in this case.
40241 When IN is 2, return maximum of in and out move cost.
40243 If moving between registers and memory is more expensive than
40244 between two registers, you should define this macro to express the
40245 relative cost.
40247 Model also increased moving costs of QImode registers in non
40248 Q_REGS classes.
40249 */
40253 {
40256 {
40259 {
40271 }
40275 }
40277 {
40280 {
40292 }
40296 }
40298 {
40301 {
40310 }
40314 }
40316 {
40319 {
40325 else
40330 }
40331 else
40332 {
40337 else
40339 }
40346 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
40353 else
40357 }
40358 }
40360 static int
40363 {
40365 }
40368 /* Return the cost of moving data from a register in class CLASS1 to
40369 one in class CLASS2.
40371 It is not required that the cost always equal 2 when FROM is the same as TO;
40372 on some machines it is expensive to move between registers if they are not
40373 general registers. */
40375 static int
40377 reg_class_t class2_i)
40378 {
40382 /* In case we require secondary memory, compute cost of the store followed
40383 by load. In order to avoid bad register allocation choices, we need
40384 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
40387 {
40393 /* In case of copying from general_purpose_register we may emit multiple
40394 stores followed by single load causing memory size mismatch stall.
40395 Count this as arbitrarily high cost of 20. */
40400 /* In the case of FP/MMX moves, the registers actually overlap, and we
40401 have to switch modes in order to treat them differently. */
40407 }
40409 /* Moves between SSE/MMX and integer unit are expensive. */
40413 /* ??? By keeping returned value relatively high, we limit the number
40414 of moves between integer and MMX/SSE registers for all targets.
40415 Additionally, high value prevents problem with x86_modes_tieable_p(),
40416 where integer modes in MMX/SSE registers are not tieable
40417 because of missing QImode and HImode moves to, from or between
40418 MMX/SSE registers. */
40428 }
40430 /* Return TRUE if hard register REGNO can hold a value of machine-mode
40431 MODE. */
40433 bool
40435 {
40436 /* Flags and only flags can only hold CCmode values. */
40449 {
40450 /* We implement the move patterns for all vector modes into and
40451 out of SSE registers, even when no operation instructions
40452 are available. */
40454 /* For AVX-512 we allow, regardless of regno:
40455 - XI mode
40456 - any of 512-bit wide vector mode
40457 - any scalar mode. */
40464 /* TODO check for QI/HI scalars. */
40465 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
40473 /* xmm16-xmm31 are only available for AVX-512. */
40477 /* OImode and AVX modes are available only when AVX is enabled. */
40484 }
40486 {
40487 /* We implement the move patterns for 3DNOW modes even in MMX mode,
40488 so if the register is available at all, then we can move data of
40489 the given mode into or out of it. */
40492 }
40495 {
40496 /* Take care for QImode values - they can be in non-QI regs,
40497 but then they do cause partial register stalls. */
40502 /* LRA checks if the hard register is OK for the given mode.
40503 QImode values can live in non-QI regs, so we allow all
40504 registers here. */
40508 }
40509 /* We handle both integer and floats in the general purpose registers. */
40516 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
40517 on to use that value in smaller contexts, this can easily force a
40518 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
40519 supporting DImode, allow it. */
40524 }
40526 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
40527 tieable integer mode. */
40529 static bool
40531 {
40533 {
40546 }
40547 }
40549 /* Return true if MODE1 is accessible in a register that can hold MODE2
40550 without copying. That is, all register classes that can hold MODE2
40551 can also hold MODE1. */
40553 bool
40555 {
40563 /* MODE2 being XFmode implies fp stack or general regs, which means we
40564 can tie any smaller floating point modes to it. Note that we do not
40565 tie this with TFmode. */
40569 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
40570 that we can tie it with SFmode. */
40574 /* If MODE2 is only appropriate for an SSE register, then tie with
40575 any other mode acceptable to SSE registers. */
40585 /* If MODE2 is appropriate for an MMX register, then tie
40586 with any other mode acceptable to MMX registers. */
40593 }
40595 /* Return the cost of moving between two registers of mode MODE. */
40597 static int
40599 {
40603 {
40635 }
40637 /* Return the cost of moving between two registers of mode MODE,
40638 assuming that the move will be in pieces of at most UNITS bytes. */
40640 }
40642 /* Compute a (partial) cost for rtx X. Return true if the complete
40643 cost has been computed, and false if subexpressions should be
40644 scanned. In either case, *TOTAL contains the cost result. */
40646 static bool
40649 {
40650 rtx mask;
40657 {
40661 {
40664 }
40676 && !(TARGET_64BIT
40681 else
40687 {
40690 }
40692 {
40702 }
40704 {
40707 {
40716 }
40717 }
40718 /* Fall back to (MEM (SYMBOL_REF)), since that's where
40719 it'll probably end up. Add a penalty for size. */
40726 /* The zero extensions is often completely free on x86_64, so make
40727 it as cheap as possible. */
40733 else
40745 {
40748 {
40751 }
40754 {
40757 }
40758 }
40759 /* FALLTHRU */
40766 {
40767 /* ??? Should be SSE vector operation cost. */
40768 /* At least for published AMD latencies, this really is the same
40769 as the latency for a simple fpu operation like fabs. */
40770 /* V*QImode is emulated with 1-11 insns. */
40772 {
40775 {
40776 /* For XOP we use vpshab, which requires a broadcast of the
40777 value to the variable shift insn. For constants this
40778 means a V16Q const in mem; even when we can perform the
40779 shift with one insn set the cost to prefer paddb. */
40781 {
40786 }
40788 }
40792 }
40793 else
40795 }
40797 {
40799 {
40802 else
40804 }
40805 else
40806 {
40809 else
40811 }
40812 }
40813 else
40814 {
40819 {
40820 /* Return the cost after shift-and truncation. */
40823 }
40824 else
40826 }
40830 {
40831 rtx sub;
40836 /* ??? SSE scalar/vector cost should be used here. */
40837 /* ??? Bald assumption that fma has the same cost as fmul. */
40841 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
40852 }
40856 {
40857 /* ??? SSE scalar cost should be used here. */
40860 }
40862 {
40865 }
40867 {
40868 /* ??? SSE vector cost should be used here. */
40871 }
40873 {
40874 /* V*QImode is emulated with 7-13 insns. */
40876 {
40883 }
40884 /* V*DImode is emulated with 5-8 insns. */
40886 {
40889 else
40891 }
40892 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
40893 insns, including two PMULUDQ. */
40896 else
40899 }
40900 else
40901 {
40906 {
40909 nbits++;
40910 }
40911 else
40912 /* This is arbitrary. */
40915 /* Compute costs correctly for widening multiplication. */
40919 {
40926 {
40930 else
40932 }
40936 }
40944 }
40951 /* ??? SSE cost should be used here. */
40956 /* ??? SSE vector cost should be used here. */
40958 else
40965 {
40970 {
40973 {
40981 }
40982 }
40985 {
40988 {
40994 }
40995 }
40997 {
41005 }
41006 }
41007 /* FALLTHRU */
41011 {
41012 /* ??? SSE cost should be used here. */
41015 }
41017 {
41020 }
41022 {
41023 /* ??? SSE vector cost should be used here. */
41026 }
41027 /* FALLTHRU */
41034 {
41041 }
41042 /* FALLTHRU */
41046 {
41047 /* ??? SSE cost should be used here. */
41050 }
41052 {
41055 }
41057 {
41058 /* ??? SSE vector cost should be used here. */
41061 }
41062 /* FALLTHRU */
41066 {
41067 /* ??? Should be SSE vector operation cost. */
41068 /* At least for published AMD latencies, this really is the same
41069 as the latency for a simple fpu operation like fabs. */
41071 }
41074 else
41083 {
41084 /* This kind of construct is implemented using test[bwl].
41085 Treat it as if we had an AND. */
41090 }
41100 /* ??? SSE cost should be used here. */
41105 /* ??? SSE vector cost should be used here. */
41111 /* ??? SSE cost should be used here. */
41116 /* ??? SSE vector cost should be used here. */
41128 /* ??? Assume all of these vector manipulation patterns are
41129 recognizable. In which case they all pretty much have the
41130 same cost. */
41135 /* This is masked instruction, assume the same cost,
41136 as nonmasked variant. */
41139 else
41145 }
41146 }
41148 #if TARGET_MACHO
41152 /* Given a symbol name and its associated stub, write out the
41153 definition of the stub. */
41155 void
41157 {
41162 /* For 64-bit we shouldn't get here. */
41165 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
41182 else
41189 {
41191 }
41193 {
41194 /* PIC stub. */
41195 /* 25-byte PIC stub using "CALL get_pc_thunk". */
41201 }
41202 else
41205 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
41206 it needs no stub-binding-helper. */
41213 {
41216 }
41217 else
41222 /* N.B. Keep the correspondence of these
41223 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
41224 old-pic/new-pic/non-pic stubs; altering this will break
41225 compatibility with existing dylibs. */
41227 {
41228 /* 25-byte PIC stub using "CALL get_pc_thunk". */
41230 }
41231 else
41232 /* 16-byte -mdynamic-no-pic stub. */
41238 }
41241 /* Order the registers for register allocator. */
41243 void
41245 {
41249 /* First allocate the local general purpose registers. */
41254 /* Global general purpose registers. */
41259 /* x87 registers come first in case we are doing FP math
41260 using them. */
41265 /* SSE registers. */
41271 /* Extended REX SSE registers. */
41275 /* Mask register. */
41279 /* x87 registers. */
41287 /* Initialize the rest of array as we do not allocate some registers
41288 at all. */
41291 }
41293 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
41294 in struct attribute_spec handler. */
41295 static tree
41297 tree args,
41300 {
41305 {
41307 name);
41310 }
41312 {
41314 name);
41317 }
41319 {
41320 tree cst;
41324 {
41327 name);
41329 }
41332 {
41335 name);
41337 }
41340 }
41343 }
41345 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
41346 struct attribute_spec.handler. */
41347 static tree
41349 tree args ATTRIBUTE_UNUSED,
41351 {
41356 {
41358 name);
41361 }
41363 /* Can combine regparm with all attributes but fastcall. */
41365 {
41367 {
41369 }
41372 }
41374 {
41376 {
41378 }
41381 }
41384 }
41386 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
41387 struct attribute_spec.handler. */
41388 static tree
41390 tree args ATTRIBUTE_UNUSED,
41392 {
41395 {
41398 }
41399 else
41403 {
41405 name);
41407 }
41413 {
41415 name);
41417 }
41420 }
41422 static tree
41424 tree args ATTRIBUTE_UNUSED,
41426 {
41428 {
41430 name);
41432 }
41434 }
41436 static bool
41438 {
41442 }
41444 /* Returns an expression indicating where the this parameter is
41445 located on entry to the FUNCTION. */
41447 static rtx
41449 {
41455 {
41460 else
41463 }
41468 {
41475 {
41480 }
41481 else
41482 {
41485 {
41491 }
41492 }
41494 }
41498 }
41500 /* Determine whether x86_output_mi_thunk can succeed. */
41502 static bool
41504 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
41506 {
41507 /* 64-bit can handle anything. */
41511 /* For 32-bit, everything's fine if we have one free register. */
41515 /* Need a free register for vcall_offset. */
41519 /* Need a free register for GOT references. */
41523 /* Otherwise ok. */
41525 }
41527 /* Output the assembler code for a thunk function. THUNK_DECL is the
41528 declaration for the thunk function itself, FUNCTION is the decl for
41529 the target function. DELTA is an immediate constant offset to be
41530 added to THIS. If VCALL_OFFSET is nonzero, the word at
41531 *(*this + vcall_offset) should be added to THIS. */
41533 static void
41537 {
41544 else
41545 {
41551 else
41553 }
41557 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
41558 pull it in now and let DELTA benefit. */
41562 {
41563 /* Put the this parameter into %eax. */
41566 }
41567 else
41570 /* Adjust the this parameter by a fixed constant. */
41572 {
41577 {
41579 {
41583 }
41584 }
41587 }
41589 /* Adjust the this parameter by a value stored in the vtable. */
41591 {
41601 /* Adjust the this parameter. */
41605 {
41609 }
41616 vcall_mem));
41617 else
41619 }
41621 /* If necessary, drop THIS back to its stack slot. */
41627 {
41630 ;
41631 else
41632 {
41636 }
41637 }
41638 else
41639 {
41641 ;
41642 #if TARGET_MACHO
41644 {
41647 }
41649 else
41650 {
41658 }
41659 }
41661 /* Our sibling call patterns do not allow memories, because we have no
41662 predicate that can distinguish between frame and non-frame memory.
41663 For our purposes here, we can get away with (ab)using a jump pattern,
41664 because we're going to do no optimization. */
41666 {
41668 {
41672 }
41673 else
41675 }
41676 else
41677 {
41683 {
41689 }
41695 }
41698 /* Emit just enough of rest_of_compilation to get the insns emitted.
41699 Note that use_thunk calls assemble_start_function et al. */
41705 }
41707 static void
41709 {
41713 #if TARGET_MACHO
41715 #endif
41722 }
41724 int
41726 {
41738 }
41740 /* Output assembler code to FILE to increment profiler label # LABELNO
41741 for profiling a function entry. */
41742 void
41744 {
41749 {
41750 #ifndef NO_PROFILE_COUNTERS
41752 #endif
41756 else
41758 }
41760 {
41761 #ifndef NO_PROFILE_COUNTERS
41764 #endif
41766 }
41767 else
41768 {
41769 #ifndef NO_PROFILE_COUNTERS
41772 #endif
41774 }
41775 }
41777 /* We don't have exact information about the insn sizes, but we may assume
41778 quite safely that we are informed about all 1 byte insns and memory
41779 address sizes. This is enough to eliminate unnecessary padding in
41780 99% of cases. */
41782 static int
41784 {
41790 /* Discard alignments we've emit and jump instructions. */
41795 /* Important case - calls are always 5 bytes.
41796 It is common to have many calls in the row. */
41805 /* For normal instructions we rely on get_attr_length being exact,
41806 with a few exceptions. */
41808 {
41812 {
41822 /* Otherwise trust get_attr_length. */
41824 }
41829 }
41832 else
41834 }
41836 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
41838 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
41839 window. */
41841 static void
41843 {
41848 /* Look for all minimal intervals of instructions containing 4 jumps.
41849 The intervals are bounded by START and INSN. NBYTES is the total
41850 size of instructions in the interval including INSN and not including
41851 START. When the NBYTES is smaller than 16 bytes, it is possible
41852 that the end of START and INSN ends up in the same 16byte page.
41854 The smallest offset in the page INSN can start is the case where START
41855 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
41856 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
41858 Don't consider asm goto as jump, while it can contain a jump, it doesn't
41859 have to, control transfer to label(s) can be performed through other
41860 means, and also we estimate minimum length of all asm stmts as 0. */
41862 {
41866 {
41872 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
41873 already in the current 16 byte page, because otherwise
41874 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
41875 bytes to reach 16 byte boundary. */
41883 {
41885 {
41890 else
41893 }
41894 }
41896 }
41905 njumps++;
41906 else
41910 {
41915 else
41918 }
41925 {
41932 }
41933 }
41934 }
41935 #endif
41937 /* AMD Athlon works faster
41938 when RET is not destination of conditional jump or directly preceded
41939 by other jump instruction. We avoid the penalty by inserting NOP just
41940 before the RET instructions in such cases. */
41941 static void
41943 {
41944 edge e;
41945 edge_iterator ei;
41948 {
41951 rtx prev;
41961 {
41962 edge e;
41963 edge_iterator ei;
41968 {
41971 }
41972 }
41974 {
41980 /* Empty functions get branch mispredict even when
41981 the jump destination is not visible to us. */
41984 }
41986 {
41989 }
41990 }
41991 }
41993 /* Count the minimum number of instructions in BB. Return 4 if the
41994 number of instructions >= 4. */
41996 static int
41998 {
41999 rtx insn;
42002 /* Count number of instructions in this block. Return 4 if the number
42003 of instructions >= 4. */
42005 {
42006 /* Only happen in exit blocks. */
42014 {
42015 insn_count++;
42018 }
42019 }
42022 }
42025 /* Count the minimum number of instructions in code path in BB.
42026 Return 4 if the number of instructions >= 4. */
42028 static int
42030 {
42031 edge e;
42032 edge_iterator ei;
42035 /* Only bother counting instructions along paths with no
42036 more than 2 basic blocks between entry and exit. Given
42037 that BB has an edge to exit, determine if a predecessor
42038 of BB has an edge from entry. If so, compute the number
42039 of instructions in the predecessor block. If there
42040 happen to be multiple such blocks, compute the minimum. */
42043 {
42044 edge prev_e;
42045 edge_iterator prev_ei;
42048 {
42051 }
42053 {
42055 {
42060 }
42061 }
42062 }
42068 }
42070 /* Pad short function to 4 instructions. */
42072 static void
42074 {
42075 edge e;
42076 edge_iterator ei;
42079 {
42082 {
42085 /* Pad short function. */
42087 {
42090 /* Find epilogue. */
42099 /* Two NOPs count as one instruction. */
42102 }
42103 }
42104 }
42105 }
42107 /* Fix up a Windows system unwinder issue. If an EH region falls through into
42108 the epilogue, the Windows system unwinder will apply epilogue logic and
42109 produce incorrect offsets. This can be avoided by adding a nop between
42110 the last insn that can throw and the first insn of the epilogue. */
42112 static void
42114 {
42115 edge e;
42116 edge_iterator ei;
42119 {
42122 /* Find the beginning of the epilogue. */
42129 /* We only care about preceding insns that can throw. */
42134 /* Do not separate calls from their debug information. */
42140 else
42144 }
42145 }
42147 /* Implement machine specific optimizations. We implement padding of returns
42148 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
42149 static void
42151 {
42152 /* We are freeing block_for_insn in the toplev to keep compatibility
42153 with old MDEP_REORGS that are not CFG based. Recompute it now. */
42160 {
42165 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
42168 #endif
42169 }
42170 }
42172 /* Return nonzero when QImode register that must be represented via REX prefix
42173 is used. */
42174 bool
42176 {
42184 }
42186 /* Return nonzero when P points to register encoded via REX prefix.
42187 Called via for_each_rtx. */
42188 static int
42190 {
42196 }
42198 /* Return true when INSN mentions register that must be encoded using REX
42199 prefix. */
42200 bool
42202 {
42205 }
42207 /* If profitable, negate (without causing overflow) integer constant
42208 of mode MODE at location LOC. Return true in this case. */
42209 bool
42211 {
42212 HOST_WIDE_INT val;
42218 {
42220 /* DImode x86_64 constants must fit in 32 bits. */
42233 }
42235 /* Avoid overflows. */
42241 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
42242 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
42245 {
42248 }
42251 }
42253 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
42254 optabs would emit if we didn't have TFmode patterns. */
42256 void
42258 {
42292 }
42293 \f
42294 /* AVX512F does support 64-byte integer vector operations,
42295 thus the longest vector we are faced with is V64QImode. */
42296 #define MAX_VECT_LEN 64
42298 struct expand_vec_perm_d
42299 {
42306 };
42312 /* Get a vector mode of the same size as the original but with elements
42313 twice as wide. This is only guaranteed to apply to integral vectors. */
42317 {
42318 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
42323 }
42325 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
42326 fill target with val via vec_duplicate. */
42328 static bool
42330 {
42334 /* First attempt to recognize VAL as-is. */
42338 {
42339 rtx seq;
42340 /* If that fails, force VAL into a register. */
42351 }
42353 }
42355 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
42356 with all elements equal to VAR. Return true if successful. */
42358 static bool
42361 {
42365 {
42370 /* FALLTHRU */
42392 {
42393 rtx x;
42400 }
42413 {
42417 permute:
42425 /* Extend to SImode using a paradoxical SUBREG. */
42429 /* Insert the SImode value as low element of a V4SImode vector. */
42438 }
42449 widen:
42450 /* Replicate the value once into the next wider mode and recurse. */
42451 {
42453 rtx x;
42470 }
42476 else
42477 {
42486 }
42491 }
42492 }
42494 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
42495 whose ONE_VAR element is VAR, and other elements are zero. Return true
42496 if successful. */
42498 static bool
42501 {
42503 rtx new_target;
42508 {
42510 /* For SSE4.1, we normally use vector set. But if the second
42511 element is zero and inter-unit moves are OK, we use movq
42512 instead. */
42514 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
42536 /* Use ix86_expand_vector_set in 64bit mode only. */
42541 }
42544 {
42549 }
42552 {
42557 /* FALLTHRU */
42572 else
42579 {
42580 /* We need to shuffle the value to the correct position, so
42581 create a new pseudo to store the intermediate result. */
42583 /* With SSE2, we can use the integer shuffle insns. */
42585 {
42587 const1_rtx,
42594 }
42596 /* Otherwise convert the intermediate result to V4SFmode and
42597 use the SSE1 shuffle instructions. */
42599 {
42602 }
42603 else
42607 const1_rtx,
42616 }
42631 widen:
42635 /* Zero extend the variable element to SImode and recurse. */
42648 }
42649 }
42651 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
42652 consisting of the values in VALS. It is known that all elements
42653 except ONE_VAR are constants. Return true if successful. */
42655 static bool
42658 {
42668 {
42673 /* For the two element vectors, it's just as easy to use
42674 the general case. */
42678 /* Use ix86_expand_vector_set in 64bit mode only. */
42700 widen:
42701 /* There's no way to set one QImode entry easily. Combine
42702 the variable value with its adjacent constant value, and
42703 promote to an HImode set. */
42706 {
42711 }
42712 else
42713 {
42716 }
42730 }
42735 }
42737 /* A subroutine of ix86_expand_vector_init_general. Use vector
42738 concatenate to handle the most general case: all values variable,
42739 and none identical. */
42741 static void
42744 {
42747 rtvec v;
42751 {
42754 {
42799 }
42812 {
42827 }
42832 {
42851 }
42856 {
42869 }
42872 half:
42873 /* FIXME: We process inputs backward to help RA. PR 36222. */
42877 {
42882 }
42886 {
42890 {
42894 }
42897 {
42901 }
42904 }
42906 {
42909 {
42913 }
42916 }
42917 else
42923 }
42924 }
42926 /* A subroutine of ix86_expand_vector_init_general. Use vector
42927 interleave to handle the most general case: all values variable,
42928 and none identical. */
42930 static void
42933 {
42942 {
42963 }
42966 {
42967 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
42971 /* Insert the SImode value as low element of V4SImode vector. */
42975 op0),
42977 const1_rtx);
42980 /* Cast the V4SImode vector back to a vector in orignal mode. */
42984 /* Load even elements into the second position. */
42988 const1_rtx));
42990 /* Cast vector to FIRST_IMODE vector. */
42993 }
42995 /* Interleave low FIRST_IMODE vectors. */
42997 {
43001 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
43004 }
43006 /* Interleave low SECOND_IMODE vectors. */
43008 {
43011 {
43016 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
43017 vector. */
43020 }
43023 /* FALLTHRU */
43030 /* Cast the SECOND_IMODE vector back to a vector on original
43031 mode. */
43038 }
43039 }
43041 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
43042 all values variable, and none identical. */
43044 static void
43047 {
43054 {
43059 /* FALLTHRU */
43087 half:
43111 quarter:
43140 /* FALLTHRU */
43146 /* Don't use ix86_expand_vector_init_interleave if we can't
43147 move from GPR to SSE register directly. */
43163 }
43165 {
43177 {
43181 {
43187 else
43188 {
43193 }
43194 }
43197 }
43202 {
43208 }
43210 {
43216 }
43217 else
43219 }
43220 }
43222 /* Initialize vector TARGET via VALS. Suppress the use of MMX
43223 instructions unless MMX_OK is true. */
43225 void
43227 {
43234 rtx x;
43237 {
43247 }
43249 /* Constants are best loaded from the constant pool. */
43251 {
43254 }
43256 /* If all values are identical, broadcast the value. */
43262 /* Values where only one field is non-constant are best loaded from
43263 the pool and overwritten via move later. */
43265 {
43269 one_var))
43274 }
43277 }
43279 void
43281 {
43286 rtx tmp;
43288 = {
43295 };
43297 = {
43304 };
43308 {
43312 {
43317 else
43321 }
43333 else
43339 {
43342 /* For the two element vectors, we implement a VEC_CONCAT with
43343 the extraction of the other element. */
43350 else
43355 }
43364 {
43370 /* tmp = target = A B C D */
43372 /* target = A A B B */
43374 /* target = X A B B */
43376 /* target = A X C D */
43383 /* tmp = target = A B C D */
43385 /* tmp = X B C D */
43387 /* target = A B X D */
43394 /* tmp = target = A B C D */
43396 /* tmp = X B C D */
43398 /* target = A B X D */
43406 }
43414 /* Element 0 handled by vec_merge below. */
43416 {
43419 }
43422 {
43423 /* With SSE2, use integer shuffles to swap element 0 and ELT,
43424 store into element 0, then shuffle them back. */
43441 }
43442 else
43443 {
43444 /* For SSE1, we have to reuse the V4SF code. */
43448 }
43501 half:
43502 /* Compute offset. */
43508 /* Extract the half. */
43512 /* Put val in tmp at elt. */
43515 /* Put it back. */
43564 }
43567 {
43571 }
43572 else
43573 {
43582 }
43583 }
43585 void
43587 {
43591 rtx tmp;
43594 {
43599 /* FALLTHRU */
43612 {
43632 }
43644 {
43646 {
43666 }
43670 }
43671 else
43672 {
43673 /* For SSE1, we have to reuse the V4SF code. */
43677 }
43693 {
43697 else
43701 }
43706 {
43710 else
43714 }
43719 {
43723 else
43727 }
43732 {
43736 else
43740 }
43745 {
43749 else
43753 }
43758 {
43762 else
43766 }
43771 {
43775 else
43779 }
43784 {
43788 else
43792 }
43799 else
43808 else
43817 else
43826 else
43832 /* ??? Could extract the appropriate HImode element and shift. */
43835 }
43838 {
43842 /* Let the rtl optimizers know about the zero extension performed. */
43844 {
43847 }
43850 }
43851 else
43852 {
43859 }
43860 }
43862 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
43863 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
43864 The upper bits of DEST are undefined, though they shouldn't cause
43865 exceptions (some bits from src or all zeros are ok). */
43867 static void
43869 {
43872 {
43876 else
43894 else
43901 else
43909 {
43914 const1_rtx);
43915 }
43916 else
43917 {
43921 }
43943 else
43965 }
43969 }
43971 /* Expand a vector reduction. FN is the binary pattern to reduce;
43972 DEST is the destination; IN is the input vector. */
43974 void
43976 {
43981 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
43985 {
43988 }
43993 {
43998 else
44002 }
44003 }
44004 \f
44005 /* Target hook for scalar_mode_supported_p. */
44006 static bool
44008 {
44013 else
44015 }
44017 /* Implements target hook vector_mode_supported_p. */
44018 static bool
44020 {
44034 }
44036 /* Target hook for c_mode_for_suffix. */
44037 static enum machine_mode
44039 {
44046 }
44048 /* Worker function for TARGET_MD_ASM_CLOBBERS.
44050 We do this in the new i386 backend to maintain source compatibility
44051 with the old cc0-based compiler. */
44053 static tree
44055 tree inputs ATTRIBUTE_UNUSED,
44056 tree clobbers)
44057 {
44059 clobbers);
44061 clobbers);
44063 }
44065 /* Implements target vector targetm.asm.encode_section_info. */
44067 static void ATTRIBUTE_UNUSED
44069 {
44076 }
44078 /* Worker function for REVERSE_CONDITION. */
44080 enum rtx_code
44082 {
44086 }
44088 /* Output code to perform an x87 FP register move, from OPERANDS[1]
44089 to OPERANDS[0]. */
44093 {
44095 {
44098 {
44102 }
44106 }
44108 {
44112 else
44113 {
44114 /* There is no non-popping store to memory for XFmode.
44115 So if we need one, follow the store with a load. */
44118 else
44120 }
44121 }
44122 else
44124 }
44126 /* Output code to perform a conditional jump to LABEL, if C2 flag in
44127 FP status register is set. */
44129 void
44131 {
44133 rtx temp;
44138 {
44143 }
44144 else
44145 {
44150 }
44154 pc_rtx);
44159 }
44161 /* Output code to perform a log1p XFmode calculation. */
44164 {
44170 rtx test;
44176 XFmode));
44190 }
44192 /* Emit code for round calculation. */
44194 {
44201 rtx insn;
44206 {
44218 }
44221 {
44242 }
44250 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
44252 /* scratch = fxam(op1) */
44255 UNSPEC_FXAM)));
44256 /* e1 = fabs(op1) */
44259 /* e2 = e1 + 0.5 */
44264 /* res = floor(e2) */
44266 {
44271 }
44272 else
44276 {
44279 {
44286 UNSPEC_TRUNC_NOOP)));
44287 }
44303 }
44305 /* flags = signbit(a) */
44308 /* if (flags) then res = -res */
44312 pc_rtx);
44323 }
44325 /* Output code to perform a Newton-Rhapson approximation of a single precision
44326 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
44329 {
44337 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
44341 /* x0 = rcp(b) estimate */
44345 UNSPEC_RCP14)));
44346 else
44349 UNSPEC_RCP)));
44351 /* e0 = x0 * b */
44355 /* e0 = x0 * e0 */
44359 /* e1 = x0 + x0 */
44363 /* x1 = e1 - e0 */
44367 /* res = a * x1 */
44370 }
44372 /* Output code to perform a Newton-Rhapson approximation of a
44373 single precision floating point [reciprocal] square root. */
44377 {
44379 REAL_VALUE_TYPE r;
44396 {
44399 /* There is no 512-bit rsqrt. There is however rsqrt14. */
44402 }
44404 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
44405 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
44409 /* x0 = rsqrt(a) estimate */
44412 unspec)));
44414 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
44416 {
44424 /* Handle masked compare. */
44426 {
44428 /* Imm value 0x4 corresponds to not-equal comparison. */
44431 }
44432 else
44433 {
44439 }
44440 }
44442 /* e0 = x0 * a */
44445 /* e1 = e0 * x0 */
44449 /* e2 = e1 - 3. */
44456 /* e3 = -.5 * x0 */
44459 else
44460 /* e3 = -.5 * e0 */
44463 /* ret = e2 * e3 */
44466 }
44468 #ifdef TARGET_SOLARIS
44469 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
44471 static void
44473 tree decl)
44474 {
44475 /* With Binutils 2.15, the "@unwind" marker must be specified on
44476 every occurrence of the ".eh_frame" section, not just the first
44477 one. */
44480 {
44484 }
44486 #ifndef USE_GAS
44488 {
44491 }
44492 #endif
44495 }
44498 /* Return the mangling of TYPE if it is an extended fundamental type. */
44502 {
44510 {
44512 /* __float128 is "g". */
44515 /* "long double" or __float80 is "e". */
44519 }
44520 }
44522 /* For 32-bit code we can save PIC register setup by using
44523 __stack_chk_fail_local hidden function instead of calling
44524 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
44525 register, so it is better to call __stack_chk_fail directly. */
44527 static tree ATTRIBUTE_UNUSED
44529 {
44530 return TARGET_64BIT
44533 }
44535 /* Select a format to encode pointers in exception handling data. CODE
44536 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
44537 true if the symbol may be affected by dynamic relocations.
44539 ??? All x86 object file formats are capable of representing this.
44540 After all, the relocation needed is the same as for the call insn.
44541 Whether or not a particular assembler allows us to enter such, I
44542 guess we'll have to see. */
44543 int
44545 {
44547 {
44554 }
44559 }
44560 \f
44561 /* Expand copysign from SIGN to the positive value ABS_VALUE
44562 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
44563 the sign-bit. */
44564 static void
44566 {
44570 {
44577 else
44582 {
44583 /* We need to generate a scalar mode mask in this case. */
44588 }
44589 }
44590 else
44596 }
44598 /* Expand fabs (OP0) and return a new rtx that holds the result. The
44599 mask for masking out the sign-bit is stored in *SMASK, if that is
44600 non-null. */
44601 static rtx
44603 {
44612 else
44616 {
44617 /* We need to generate a scalar mode mask in this case. */
44622 }
44630 }
44632 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
44633 swapping the operands if SWAP_OPERANDS is true. The expanded
44634 code is a forward jump to a newly created label in case the
44635 comparison is true. The generated label rtx is returned. */
44636 static rtx
44639 {
44644 {
44648 }
44661 }
44663 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
44664 using comparison code CODE. Operands are swapped for the comparison if
44665 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
44666 static rtx
44669 {
44675 {
44679 }
44686 }
44688 /* Generate and return a rtx of mode MODE for 2**n where n is the number
44689 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
44690 static rtx
44692 {
44693 REAL_VALUE_TYPE TWO52r;
44694 rtx TWO52;
44701 }
44703 /* Expand SSE sequence for computing lround from OP1 storing
44704 into OP0. */
44705 void
44707 {
44708 /* C code for the stuff we're doing below:
44709 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
44710 return (long)tmp;
44711 */
44715 rtx adj;
44717 /* load nextafter (0.5, 0.0) */
44722 /* adj = copysign (0.5, op1) */
44726 /* adj = op1 + adj */
44729 /* op0 = (imode)adj */
44731 }
44733 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
44734 into OPERAND0. */
44735 void
44737 {
44738 /* C code for the stuff we're doing below (for do_floor):
44739 xi = (long)op1;
44740 xi -= (double)xi > op1 ? 1 : 0;
44741 return xi;
44742 */
44747 /* reg = (long)op1 */
44751 /* freg = (double)reg */
44755 /* ireg = (freg > op1) ? ireg - 1 : ireg */
44766 }
44768 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
44769 result in OPERAND0. */
44770 void
44772 {
44773 /* C code for the stuff we're doing below:
44774 xa = fabs (operand1);
44775 if (!isless (xa, 2**52))
44776 return operand1;
44777 xa = xa + 2**52 - 2**52;
44778 return copysign (xa, operand1);
44779 */
44786 /* xa = abs (operand1) */
44789 /* if (!isless (xa, TWO52)) goto label; */
44802 }
44804 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
44805 into OPERAND0. */
44806 void
44808 {
44809 /* C code for the stuff we expand below.
44810 double xa = fabs (x), x2;
44811 if (!isless (xa, TWO52))
44812 return x;
44813 xa = xa + TWO52 - TWO52;
44814 x2 = copysign (xa, x);
44815 Compensate. Floor:
44816 if (x2 > x)
44817 x2 -= 1;
44818 Compensate. Ceil:
44819 if (x2 < x)
44820 x2 -= -1;
44821 return x2;
44822 */
44828 /* Temporary for holding the result, initialized to the input
44829 operand to ease control flow. */
44833 /* xa = abs (operand1) */
44836 /* if (!isless (xa, TWO52)) goto label; */
44839 /* xa = xa + TWO52 - TWO52; */
44843 /* xa = copysign (xa, operand1) */
44846 /* generate 1.0 or -1.0 */
44851 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
44855 /* We always need to subtract here to preserve signed zero. */
44864 }
44866 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
44867 into OPERAND0. */
44868 void
44870 {
44871 /* C code for the stuff we expand below.
44872 double xa = fabs (x), x2;
44873 if (!isless (xa, TWO52))
44874 return x;
44875 x2 = (double)(long)x;
44876 Compensate. Floor:
44877 if (x2 > x)
44878 x2 -= 1;
44879 Compensate. Ceil:
44880 if (x2 < x)
44881 x2 += 1;
44882 if (HONOR_SIGNED_ZEROS (mode))
44883 return copysign (x2, x);
44884 return x2;
44885 */
44891 /* Temporary for holding the result, initialized to the input
44892 operand to ease control flow. */
44896 /* xa = abs (operand1) */
44899 /* if (!isless (xa, TWO52)) goto label; */
44902 /* xa = (double)(long)x */
44907 /* generate 1.0 */
44910 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
44925 }
44927 /* Expand SSE sequence for computing round from OPERAND1 storing
44928 into OPERAND0. Sequence that works without relying on DImode truncation
44929 via cvttsd2siq that is only available on 64bit targets. */
44930 void
44932 {
44933 /* C code for the stuff we expand below.
44934 double xa = fabs (x), xa2, x2;
44935 if (!isless (xa, TWO52))
44936 return x;
44937 Using the absolute value and copying back sign makes
44938 -0.0 -> -0.0 correct.
44939 xa2 = xa + TWO52 - TWO52;
44940 Compensate.
44941 dxa = xa2 - xa;
44942 if (dxa <= -0.5)
44943 xa2 += 1;
44944 else if (dxa > 0.5)
44945 xa2 -= 1;
44946 x2 = copysign (xa2, x);
44947 return x2;
44948 */
44954 /* Temporary for holding the result, initialized to the input
44955 operand to ease control flow. */
44959 /* xa = abs (operand1) */
44962 /* if (!isless (xa, TWO52)) goto label; */
44965 /* xa2 = xa + TWO52 - TWO52; */
44969 /* dxa = xa2 - xa; */
44972 /* generate 0.5, 1.0 and -0.5 */
44978 /* Compensate. */
44980 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
44985 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
44991 /* res = copysign (xa2, operand1) */
44998 }
45000 /* Expand SSE sequence for computing trunc from OPERAND1 storing
45001 into OPERAND0. */
45002 void
45004 {
45005 /* C code for SSE variant we expand below.
45006 double xa = fabs (x), x2;
45007 if (!isless (xa, TWO52))
45008 return x;
45009 x2 = (double)(long)x;
45010 if (HONOR_SIGNED_ZEROS (mode))
45011 return copysign (x2, x);
45012 return x2;
45013 */
45019 /* Temporary for holding the result, initialized to the input
45020 operand to ease control flow. */
45024 /* xa = abs (operand1) */
45027 /* if (!isless (xa, TWO52)) goto label; */
45030 /* x = (double)(long)x */
45042 }
45044 /* Expand SSE sequence for computing trunc from OPERAND1 storing
45045 into OPERAND0. */
45046 void
45048 {
45052 /* C code for SSE variant we expand below.
45053 double xa = fabs (x), x2;
45054 if (!isless (xa, TWO52))
45055 return x;
45056 xa2 = xa + TWO52 - TWO52;
45057 Compensate:
45058 if (xa2 > xa)
45059 xa2 -= 1.0;
45060 x2 = copysign (xa2, x);
45061 return x2;
45062 */
45066 /* Temporary for holding the result, initialized to the input
45067 operand to ease control flow. */
45071 /* xa = abs (operand1) */
45074 /* if (!isless (xa, TWO52)) goto label; */
45077 /* res = xa + TWO52 - TWO52; */
45082 /* generate 1.0 */
45085 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
45093 /* res = copysign (res, operand1) */
45100 }
45102 /* Expand SSE sequence for computing round from OPERAND1 storing
45103 into OPERAND0. */
45104 void
45106 {
45107 /* C code for the stuff we're doing below:
45108 double xa = fabs (x);
45109 if (!isless (xa, TWO52))
45110 return x;
45111 xa = (double)(long)(xa + nextafter (0.5, 0.0));
45112 return copysign (xa, x);
45113 */
45119 /* Temporary for holding the result, initialized to the input
45120 operand to ease control flow. */
45128 /* load nextafter (0.5, 0.0) */
45133 /* xa = xa + 0.5 */
45137 /* xa = (double)(int64_t)xa */
45142 /* res = copysign (xa, operand1) */
45149 }
45151 /* Expand SSE sequence for computing round
45152 from OP1 storing into OP0 using sse4 round insn. */
45153 void
45155 {
45164 {
45175 }
45177 /* round (a) = trunc (a + copysign (0.5, a)) */
45179 /* load nextafter (0.5, 0.0) */
45185 /* e1 = copysign (0.5, op1) */
45189 /* e2 = op1 + e1 */
45192 /* res = trunc (e2) */
45197 }
45198 \f
45200 /* Table of valid machine attributes. */
45202 {
45203 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
45204 affects_type_identity } */
45205 /* Stdcall attribute says callee is responsible for popping arguments
45206 if they are not variable. */
45209 /* Fastcall attribute says callee is responsible for popping arguments
45210 if they are not variable. */
45213 /* Thiscall attribute says callee is responsible for popping arguments
45214 if they are not variable. */
45217 /* Cdecl attribute says the callee is a normal C declaration */
45220 /* Regparm attribute specifies how many integer arguments are to be
45221 passed in registers. */
45224 /* Sseregparm attribute says we are using x86_64 calling conventions
45225 for FP arguments. */
45228 /* The transactional memory builtins are implicitly regparm or fastcall
45229 depending on the ABI. Override the generic do-nothing attribute that
45230 these builtins were declared with. */
45233 /* force_align_arg_pointer says this function realigns the stack at entry. */
45236 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
45241 #endif
45246 #ifdef SUBTARGET_ATTRIBUTE_TABLE
45247 SUBTARGET_ATTRIBUTE_TABLE,
45248 #endif
45249 /* ms_abi and sysv_abi calling convention function attributes. */
45256 /* End element. */
45258 };
45260 /* Implement targetm.vectorize.builtin_vectorization_cost. */
45261 static int
45263 tree vectype,
45265 {
45269 {
45314 }
45315 }
45317 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
45318 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
45319 insn every time. */
45323 /* Initialize vselect_insn. */
45325 static void
45327 {
45329 rtx x;
45340 }
45342 /* Construct (set target (vec_select op0 (parallel perm))) and
45343 return true if that's a valid instruction in the active ISA. */
45345 static bool
45348 {
45374 }
45376 /* Similar, but generate a vec_concat from op0 and op1 as well. */
45378 static bool
45382 {
45384 rtx x;
45399 }
45401 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
45402 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
45404 static bool
45406 {
45416 ;
45418 ;
45420 ;
45422 ;
45424 ;
45425 else
45428 /* This is a blend, not a permute. Elements must stay in their
45429 respective lanes. */
45431 {
45435 }
45440 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
45441 decision should be extracted elsewhere, so that we only try that
45442 sequence once all budget==3 options have been tried. */
45449 {
45479 /* See if bytes move in pairs so we can use pblendw with
45480 an immediate argument, rather than pblendvb with a vector
45481 argument. */
45484 {
45485 use_pblendvb:
45489 finish_pblendvb:
45495 else
45500 }
45505 /* FALLTHRU */
45507 do_subreg:
45514 /* See if bytes move in pairs. If not, vpblendvb must be used. */
45518 /* See if bytes move in quadruplets. If yes, vpblendd
45519 with immediate can be used. */
45524 {
45525 /* See if bytes move the same in both lanes. If yes,
45526 vpblendw with immediate can be used. */
45531 /* Use vpblendw. */
45536 }
45538 /* Use vpblendd. */
45545 /* See if words move in pairs. If yes, vpblendd can be used. */
45550 {
45551 /* See if words move the same in both lanes. If not,
45552 vpblendvb must be used. */
45555 {
45556 /* Use vpblendvb. */
45566 }
45568 /* Use vpblendw. */
45572 }
45574 /* Use vpblendd. */
45581 /* Use vpblendd. */
45589 }
45591 /* This matches five different patterns with the different modes. */
45599 }
45601 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
45602 in terms of the variable form of vpermilps.
45604 Note that we will have already failed the immediate input vpermilps,
45605 which requires that the high and low part shuffle be identical; the
45606 variable form doesn't require that. */
45608 static bool
45610 {
45617 /* We can only permute within the 128-bit lane. */
45619 {
45623 }
45629 {
45632 /* Within each 128-bit lane, the elements of op0 are numbered
45633 from 0 and the elements of op1 are numbered from 4. */
45640 }
45647 }
45649 /* Return true if permutation D can be performed as VMODE permutation
45650 instead. */
45652 static bool
45654 {
45669 else
45675 }
45677 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
45678 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
45680 static bool
45682 {
45691 {
45693 {
45696 {
45700 /* Use vperm2i128 insn. The pattern uses
45701 V4DImode instead of V2TImode. */
45714 }
45716 }
45717 }
45718 else
45719 {
45721 {
45724 }
45726 {
45730 /* V4DImode should be already handled through
45731 expand_vselect by vpermq instruction. */
45738 {
45739 /* First see if vpermq can be used for
45740 V8SImode/V16HImode/V32QImode. */
45742 {
45750 {
45754 }
45756 }
45758 /* Next see if vpermd can be used. */
45761 }
45762 /* Or if vpermps can be used. */
45767 {
45768 /* vpshufb only works intra lanes, it is not
45769 possible to shuffle bytes in between the lanes. */
45773 }
45774 }
45776 {
45780 {
45784 }
45785 }
45786 else
45788 }
45796 else
45797 {
45805 else
45809 {
45813 }
45814 }
45825 {
45834 else
45836 }
45837 else
45838 {
45841 }
45846 }
45848 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
45849 in a single instruction. */
45851 static bool
45853 {
45857 /* Check plain VEC_SELECT first, because AVX has instructions that could
45858 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
45859 input where SEL+CONCAT may not. */
45861 {
45867 {
45873 }
45876 {
45880 }
45882 {
45883 /* Use vpbroadcast{b,w,d}. */
45886 {
45929 /* For other modes prefer other shuffles this function creates. */
45931 }
45933 {
45937 }
45938 }
45943 /* There are plenty of patterns in sse.md that are written for
45944 SEL+CONCAT and are not replicated for a single op. Perhaps
45945 that should be changed, to avoid the nastiness here. */
45947 /* Recognize interleave style patterns, which means incrementing
45948 every other permutation operand. */
45950 {
45953 }
45958 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
45960 {
45962 {
45967 }
45972 }
45973 }
45975 /* Finally, try the fully general two operand permute. */
45980 /* Recognize interleave style patterns with reversed operands. */
45982 {
45984 {
45988 else
45991 }
45996 }
45998 /* Try the SSE4.1 blend variable merge instructions. */
46002 /* Try one of the AVX vpermil variable permutations. */
46006 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
46007 vpshufb, vpermd, vpermps or vpermq variable permutation. */
46011 /* Try the AVX512F vpermi2 instructions. */
46033 }
46035 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46036 in terms of a pair of pshuflw + pshufhw instructions. */
46038 static bool
46040 {
46048 /* The two permutations only operate in 64-bit lanes. */
46059 /* Emit the pshuflw. */
46066 /* Emit the pshufhw. */
46074 }
46076 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
46077 the permutation using the SSSE3 palignr instruction. This succeeds
46078 when all of the elements in PERM fit within one vector and we merely
46079 need to shift them down so that a single vector permutation has a
46080 chance to succeed. */
46082 static bool
46084 {
46091 /* Even with AVX, palignr only operates on 128-bit vectors. */
46097 {
46103 }
46107 /* Given that we have SSSE3, we know we'll be able to implement the
46108 single operand permutation after the palignr with pshufb. */
46123 {
46128 }
46130 /* Test for the degenerate case where the alignment by itself
46131 produces the desired permutation. */
46133 {
46136 }
46142 }
46144 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
46145 the permutation using the SSE4_1 pblendv instruction. Potentially
46146 reduces permutaion from 2 pshufb and or to 1 pshufb and pblendv. */
46148 static bool
46150 {
46156 /* Use the same checks as in expand_vec_perm_blend, but skipping
46157 AVX and AVX2 as they require more than 2 instructions. */
46161 ;
46162 else
46165 /* Figure out where permutation elements stay not in their
46166 respective lanes. */
46168 {
46172 }
46173 /* We can pblend the part where elements stay not in their
46174 respective lanes only when these elements are all in one
46175 half of a permutation.
46176 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
46177 lanes, but both 8 and 9 >= 8
46178 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
46179 respective lanes and 8 >= 8, but 2 not. */
46185 /* First we apply one operand permutation to the part where
46186 elements stay not in their respective lanes. */
46190 else
46200 /* Next we put permuted elements into their positions. */
46204 else
46214 }
46218 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
46219 a two vector permutation into a single vector permutation by using
46220 an interleave operation to merge the vectors. */
46222 static bool
46224 {
46229 rtx seq;
46233 {
46236 }
46238 {
46241 /* For 32-byte modes allow even d->one_operand_p.
46242 The lack of cross-lane shuffling in some instructions
46243 might prevent a single insn shuffle. */
46246 /* If expand_vec_perm_interleave3 can expand this into
46247 a 3 insn sequence, give up and let it be expanded as
46248 3 insn sequence. While that is one insn longer,
46249 it doesn't need a memory operand and in the common
46250 case that both interleave low and high permutations
46251 with the same operands are adjacent needs 4 insns
46252 for both after CSE. */
46255 }
46256 else
46259 /* Examine from whence the elements come. */
46268 {
46271 /* Split the two input vectors into 4 halves. */
46277 /* If the elements from the low halves use interleave low, and similarly
46278 for interleave high. If the elements are from mis-matched halves, we
46279 can use shufps for V4SF/V4SI or do a DImode shuffle. */
46281 {
46282 /* punpckl* */
46284 {
46289 }
46292 }
46294 {
46295 /* punpckh* */
46297 {
46302 }
46305 }
46307 {
46308 /* shufps */
46310 {
46315 }
46317 {
46318 /* shufpd */
46323 }
46324 }
46326 {
46327 /* shufps */
46329 {
46334 }
46336 {
46337 /* shufpd */
46342 }
46343 }
46344 else
46346 }
46347 else
46348 {
46353 /* Split the two input vectors into 8 quarters. */
46359 {
46362 }
46365 {
46369 }
46371 {
46374 }
46377 {
46379 {
46380 /* Attempt to increase the likelihood that dfinal
46381 shuffle will be intra-lane. */
46385 }
46387 /* vperm2f128 or vperm2i128. */
46389 {
46394 }
46399 {
46403 {
46406 }
46407 }
46408 }
46413 {
46414 /* vpunpckl* */
46416 {
46425 }
46426 }
46429 {
46430 /* vpunpckh* */
46432 {
46441 }
46442 }
46443 else
46445 }
46447 /* Use the remapping array set up above to move the elements from their
46448 swizzled locations into their final destinations. */
46451 {
46454 /* If same_halves is true, both halves of the remapped vector are the
46455 same. Avoid cross-lane accesses if possible. */
46457 {
46460 }
46461 else
46463 }
46465 {
46468 }
46472 /* Test if the final remap can be done with a single insn. For V4SFmode or
46473 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
46486 {
46489 }
46496 }
46498 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
46499 a single vector cross-lane permutation into vpermq followed
46500 by any of the single insn permutations. */
46502 static bool
46504 {
46518 {
46521 }
46524 {
46529 }
46542 {
46549 }
46556 {
46561 ;
46564 else
46566 }
46575 }
46577 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
46578 a vector permutation using two instructions, vperm2f128 resp.
46579 vperm2i128 followed by any single in-lane permutation. */
46581 static bool
46583 {
46597 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
46598 immediate. For perm < 16 the second permutation uses
46599 d->op0 as first operand, for perm >= 16 it uses d->op1
46600 as first operand. The second operand is the result of
46601 vperm2[fi]128. */
46603 {
46604 /* Ignore permutations which do not move anything cross-lane. */
46606 {
46607 /* The second shuffle for e.g. V4DFmode has
46608 0123 and ABCD operands.
46609 Ignore AB23, as 23 is already in the second lane
46610 of the first operand. */
46612 /* And 01CD, as 01 is in the first lane of the first
46613 operand. */
46615 /* And 4567, as then the vperm2[fi]128 doesn't change
46616 anything on the original 4567 second operand. */
46618 }
46619 else
46620 {
46621 /* The second shuffle for e.g. V4DFmode has
46622 4567 and ABCD operands.
46623 Ignore AB67, as 67 is already in the second lane
46624 of the first operand. */
46626 /* And 45CD, as 45 is in the first lane of the first
46627 operand. */
46629 /* And 0123, as then the vperm2[fi]128 doesn't change
46630 anything on the original 0123 first operand. */
46632 }
46635 {
46641 else
46643 }
46646 {
46650 }
46651 else
46655 {
46659 /* Found a usable second shuffle. dfirst will be
46660 vperm2f128 on d->op0 and d->op1. */
46671 /* And dsecond is some single insn shuffle, taking
46672 d->op0 and result of vperm2f128 (if perm < 16) or
46673 d->op1 and result of vperm2f128 (otherwise). */
46682 }
46684 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
46687 }
46690 }
46692 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
46693 a two vector permutation using 2 intra-lane interleave insns
46694 and cross-lane shuffle for 32-byte vectors. */
46696 static bool
46698 {
46705 ;
46707 ;
46708 else
46723 {
46727 else
46733 else
46739 else
46745 else
46751 else
46757 else
46762 }
46766 }
46768 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
46769 a single vector permutation using a single intra-lane vector
46770 permutation, vperm2f128 swapping the lanes and vblend* insn blending
46771 the non-swapped and swapped vectors together. */
46773 static bool
46775 {
46778 rtx seq;
46783 || TARGET_AVX2
46792 {
46799 }
46834 }
46836 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
46837 permutation using two vperm2f128, followed by a vshufpd insn blending
46838 the two vectors together. */
46840 static bool
46842 {
46885 }
46887 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
46888 permutation with two pshufb insns and an ior. We should have already
46889 failed all two instruction sequences. */
46891 static bool
46893 {
46907 /* Generate two permutation masks. If the required element is within
46908 the given vector it is shuffled into the proper lane. If the required
46909 element is in the other vector, force a zero into the lane by setting
46910 bit 7 in the permutation mask. */
46913 {
46920 {
46923 }
46924 }
46948 }
46950 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
46951 with two vpshufb insns, vpermq and vpor. We should have already failed
46952 all two or three instruction sequences. */
46954 static bool
46956 {
46971 /* Generate two permutation masks. If the required element is within
46972 the same lane, it is shuffled in. If the required element from the
46973 other lane, force a zero by setting bit 7 in the permutation mask.
46974 In the other mask the mask has non-negative elements if element
46975 is requested from the other lane, but also moved to the other lane,
46976 so that the result of vpshufb can have the two V2TImode halves
46977 swapped. */
46980 {
46985 {
46988 }
46989 }
46998 /* Swap the 128-byte lanes of h into hp. */
47002 const1_rtx));
47019 }
47021 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
47022 and extract-odd permutations of two V32QImode and V16QImode operand
47023 with two vpshufb insns, vpor and vpermq. We should have already
47024 failed all two or three instruction sequences. */
47026 static bool
47028 {
47047 /* Generate two permutation masks. In the first permutation mask
47048 the first quarter will contain indexes for the first half
47049 of the op0, the second quarter will contain bit 7 set, third quarter
47050 will contain indexes for the second half of the op0 and the
47051 last quarter bit 7 set. In the second permutation mask
47052 the first quarter will contain bit 7 set, the second quarter
47053 indexes for the first half of the op1, the third quarter bit 7 set
47054 and last quarter indexes for the second half of the op1.
47055 I.e. the first mask e.g. for V32QImode extract even will be:
47056 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
47057 (all values masked with 0xf except for -128) and second mask
47058 for extract even will be
47059 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
47062 {
47068 {
47071 }
47072 }
47091 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
47099 }
47101 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
47102 and extract-odd permutations. */
47104 static bool
47106 {
47110 {
47117 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
47121 /* Now an unpck[lh]pd will produce the result required. */
47124 else
47130 {
47139 /* Shuffle within the 128-bit lanes to produce:
47140 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
47144 /* Shuffle the lanes around to produce:
47145 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
47149 /* Shuffle within the 128-bit lanes to produce:
47150 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
47153 /* Shuffle within the 128-bit lanes to produce:
47154 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
47157 /* Shuffle the lanes around to produce:
47158 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
47161 }
47168 /* These are always directly implementable by expand_vec_perm_1. */
47174 else
47175 {
47178 /* We need 2*log2(N)-1 operations to achieve odd/even
47179 with interleave. */
47188 else
47191 }
47197 else
47198 {
47212 else
47215 }
47224 {
47229 else
47234 {
47239 }
47241 }
47249 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
47253 /* Now an vpunpck[lh]qdq will produce the result required. */
47256 else
47263 {
47268 else
47273 {
47278 }
47280 }
47291 /* Shuffle the lanes around into
47292 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
47300 /* Swap the 2nd and 3rd position in each lane into
47301 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
47307 /* Now an vpunpck[lh]qdq will produce
47308 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
47312 else
47321 }
47324 }
47326 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
47327 extract-even and extract-odd permutations. */
47329 static bool
47331 {
47343 }
47345 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
47346 permutations. We assume that expand_vec_perm_1 has already failed. */
47348 static bool
47350 {
47358 {
47361 /* These are special-cased in sse.md so that we can optionally
47362 use the vbroadcast instruction. They expand to two insns
47363 if the input happens to be in a register. */
47370 /* These are always implementable using standard shuffle patterns. */
47375 /* These can be implemented via interleave. We save one insn by
47376 stopping once we have promoted to V4SImode and then use pshufd. */
47379 do
47380 {
47381 rtx dest;
47387 {
47391 }
47398 }
47413 /* For AVX2 broadcasts of the first element vpbroadcast* or
47414 vpermq should be used by expand_vec_perm_1. */
47420 }
47421 }
47423 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
47424 broadcast permutations. */
47426 static bool
47428 {
47440 }
47442 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
47443 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
47444 all the shorter instruction sequences. */
47446 static bool
47448 {
47464 /* Generate 4 permutation masks. If the required element is within
47465 the same lane, it is shuffled in. If the required element from the
47466 other lane, force a zero by setting bit 7 in the permutation mask.
47467 In the other mask the mask has non-negative elements if element
47468 is requested from the other lane, but also moved to the other lane,
47469 so that the result of vpshufb can have the two V2TImode halves
47470 swapped. */
47473 {
47478 }
47484 {
47492 }
47495 {
47497 {
47500 }
47507 }
47509 /* Swap the 128-byte lanes of h[X]. */
47511 {
47517 const1_rtx));
47519 }
47522 {
47524 {
47527 }
47533 }
47536 {
47538 {
47542 }
47545 }
47555 }
47557 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
47558 With all of the interface bits taken care of, perform the expansion
47559 in D and return true on success. */
47561 static bool
47563 {
47564 /* Try a single instruction expansion. */
47568 /* Try sequences of two instructions. */
47569 /* ix86_expand_vec_perm_vpermi2 is also called from
47570 * ix86_expand_vec_perm. So it doesn't take d as parameter.
47571 * Construct needed params. */
47601 /* Try sequences of three instructions. */
47615 /* Try sequences of four instructions. */
47623 /* ??? Look for narrow permutations whose element orderings would
47624 allow the promotion to a wider mode. */
47626 /* ??? Look for sequences of interleave or a wider permute that place
47627 the data into the correct lanes for a half-vector shuffle like
47628 pshuf[lh]w or vpermilps. */
47630 /* ??? Look for sequences of interleave that produce the desired results.
47631 The combinatorics of punpck[lh] get pretty ugly... */
47636 /* Even longer sequences. */
47641 }
47643 /* If a permutation only uses one operand, make it clear. Returns true
47644 if the permutation references both operands. */
47646 static bool
47648 {
47656 {
47662 {
47665 }
47666 /* The elements of PERM do not suggest that only the first operand
47667 is used, but both operands are identical. Allow easier matching
47668 of the permutation by folding the permutation into the single
47669 input vector. */
47670 /* FALLTHRU */
47681 }
47684 }
47686 bool
47688 {
47693 rtx sel;
47710 {
47715 }
47722 /* If the selector says both arguments are needed, but the operands are the
47723 same, the above tried to expand with one_operand_p and flattened selector.
47724 If that didn't work, retry without one_operand_p; we succeeded with that
47725 during testing. */
47727 {
47731 }
47734 }
47736 /* Implement targetm.vectorize.vec_perm_const_ok. */
47738 static bool
47741 {
47750 /* Given sufficient ISA support we can just return true here
47751 for selected vector modes. */
47755 /* All implementable with a single vpermi2 insn. */
47758 {
47759 /* All implementable with a single vpperm insn. */
47762 /* All implementable with 2 pshufb + 1 ior. */
47765 /* All implementable with shufpd or unpck[lh]pd. */
47768 }
47770 /* Extract the values from the vector CST into the permutation
47771 array in D. */
47774 {
47778 }
47780 /* For all elements from second vector, fold the elements to first. */
47785 /* Check whether the mask can be applied to the vector type. */
47788 /* Implementable with shufps or pshufd. */
47792 /* Otherwise we have to go through the motions and see if we can
47793 figure out how to generate the requested permutation. */
47804 }
47806 void
47808 {
47823 /* We'll either be able to implement the permutation directly... */
47827 /* ... or we use the special-case patterns. */
47829 }
47831 static void
47833 {
47848 {
47851 }
47853 /* Note that for AVX this isn't one instruction. */
47856 }
47859 /* Expand a vector operation CODE for a V*QImode in terms of the
47860 same operation on V*HImode. */
47862 void
47864 {
47876 {
47894 }
47898 {
47900 /* Unpack data such that we've got a source byte in each low byte of
47901 each word. We don't care what goes into the high byte of each word.
47902 Rather than trying to get zero in there, most convenient is to let
47903 it be a copy of the low byte. */
47908 /* FALLTHRU */
47920 /* FALLTHRU */
47930 }
47932 /* Perform the operation. */
47939 /* Merge the data back into the right place. */
47949 {
47950 /* For SSE2, we used an full interleave, so the desired
47951 results are in the even elements. */
47954 }
47955 else
47956 {
47957 /* For AVX, the interleave used above was not cross-lane. So the
47958 extraction is evens but with the second and third quarter swapped.
47959 Happily, that is even one insn shorter than even extraction. */
47962 }
47969 }
47971 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
47972 if op is CONST_VECTOR with all odd elements equal to their
47973 preceding element. */
47975 static bool
47977 {
47987 }
47989 void
47992 {
47995 rtx x;
48003 /* We only play even/odd games with vectors of SImode. */
48006 /* If we're looking for the odd results, shift those members down to
48007 the even slots. For some cpus this is faster than a PSHUFD. */
48009 {
48010 /* For XOP use vpmacsdqh, but only for smult, as it is only
48011 signed. */
48013 {
48017 }
48028 }
48031 {
48034 else
48036 }
48038 {
48041 else
48043 }
48048 else
48049 {
48052 /* The easiest way to implement this without PMULDQ is to go through
48053 the motions as if we are performing a full 64-bit multiply. With
48054 the exception that we need to do less shuffling of the elements. */
48056 /* Compute the sign-extension, aka highparts, of the two operands. */
48062 /* Multiply LO(A) * HI(B), and vice-versa. */
48068 /* Multiply LO(A) * LO(B). */
48072 /* Combine and shift the highparts into place. */
48077 /* Combine high and low parts. */
48080 }
48082 }
48084 void
48087 {
48093 {
48098 {
48099 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
48100 shuffle the elements once so that all elements are in the right
48101 place for immediate use: { A C B D }. */
48106 }
48107 else
48108 {
48109 /* Put the elements into place for the multiply. */
48113 }
48118 /* Shuffle the elements between the lanes. After this we
48119 have { A B E F | C D G H } for each operand. */
48129 /* Shuffle the elements within the lanes. After this we
48130 have { A A B B | C C D D } or { E E F F | G G H H }. */
48158 /* TODO why handle hi here and not in hi case*/
48172 }
48173 }
48175 void
48177 {
48187 /* Move the results in element 2 down to element 1; we don't care
48188 what goes in elements 2 and 3. Then we can merge the parts
48189 back together with an interleave.
48191 Note that two other sequences were tried:
48192 (1) Use interleaves at the start instead of psrldq, which allows
48193 us to use a single shufps to merge things back at the end.
48194 (2) Use shufps here to combine the two vectors, then pshufd to
48195 put the elements in the correct order.
48196 In both cases the cost of the reformatting stall was too high
48197 and the overall sequence slower. */
48208 }
48210 void
48212 {
48223 {
48224 /* op1: A,B,C,D, op2: E,F,G,H */
48233 /* t1: B,A,D,C */
48240 /* t2: (B*E),(A*F),(D*G),(C*H) */
48243 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
48246 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
48249 /* Multiply lower parts and add all */
48256 }
48257 else
48258 {
48263 {
48266 }
48268 {
48271 }
48273 {
48276 }
48277 else
48281 /* Multiply low parts. */
48285 /* Shift input vectors right 32 bits so we can multiply high parts. */
48290 /* Multiply high parts by low parts. */
48296 /* Combine and shift the highparts back. */
48300 /* Combine high and low parts. */
48302 }
48306 }
48308 /* Calculate integer abs() using only SSE2 instructions. */
48310 void
48312 {
48317 {
48318 /* For 32-bit signed integer X, the best way to calculate the absolute
48319 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
48331 /* For 16-bit signed integer X, the best way to calculate the absolute
48332 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
48340 /* For 8-bit signed integer X, the best way to calculate the absolute
48341 value of X is min ((unsigned char) X, (unsigned char) (-X)),
48342 as SSE2 provides the PMINUB insn. */
48352 }
48356 }
48358 /* Expand an insert into a vector register through pinsr insn.
48359 Return true if successful. */
48361 bool
48363 {
48371 {
48374 }
48380 {
48385 {
48392 {
48424 }
48438 }
48442 }
48443 }
48444 \f
48445 /* This function returns the calling abi specific va_list type node.
48446 It returns the FNDECL specific va_list type. */
48448 static tree
48450 {
48457 else
48459 }
48461 /* Returns the canonical va_list type specified by TYPE. If there
48462 is no valid TYPE provided, it return NULL_TREE. */
48464 static tree
48466 {
48469 /* Resolve references and pointers to va_list type. */
48478 {
48483 {
48484 /* If va_list is an array type, the argument may have decayed
48485 to a pointer type, e.g. by being passed to another function.
48486 In that case, unwrap both types so that we can compare the
48487 underlying records. */
48490 {
48493 }
48494 }
48501 {
48502 /* If va_list is an array type, the argument may have decayed
48503 to a pointer type, e.g. by being passed to another function.
48504 In that case, unwrap both types so that we can compare the
48505 underlying records. */
48508 {
48511 }
48512 }
48519 {
48520 /* If va_list is an array type, the argument may have decayed
48521 to a pointer type, e.g. by being passed to another function.
48522 In that case, unwrap both types so that we can compare the
48523 underlying records. */
48526 {
48529 }
48530 }
48534 }
48536 }
48538 /* Iterate through the target-specific builtin types for va_list.
48539 IDX denotes the iterator, *PTREE is set to the result type of
48540 the va_list builtin, and *PNAME to its internal type.
48541 Returns zero if there is no element for this index, otherwise
48542 IDX should be increased upon the next call.
48543 Note, do not iterate a base builtin's name like __builtin_va_list.
48544 Used from c_common_nodes_and_builtins. */
48546 static int
48548 {
48550 {
48552 {
48565 }
48566 }
48569 }
48571 #undef TARGET_SCHED_DISPATCH
48572 #define TARGET_SCHED_DISPATCH has_dispatch
48573 #undef TARGET_SCHED_DISPATCH_DO
48574 #define TARGET_SCHED_DISPATCH_DO do_dispatch
48575 #undef TARGET_SCHED_REASSOCIATION_WIDTH
48576 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
48577 #undef TARGET_SCHED_REORDER
48578 #define TARGET_SCHED_REORDER ix86_sched_reorder
48579 #undef TARGET_SCHED_ADJUST_PRIORITY
48580 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
48581 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
48582 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
48583 ix86_dependencies_evaluation_hook
48585 /* The size of the dispatch window is the total number of bytes of
48586 object code allowed in a window. */
48587 #define DISPATCH_WINDOW_SIZE 16
48589 /* Number of dispatch windows considered for scheduling. */
48590 #define MAX_DISPATCH_WINDOWS 3
48592 /* Maximum number of instructions in a window. */
48593 #define MAX_INSN 4
48595 /* Maximum number of immediate operands in a window. */
48596 #define MAX_IMM 4
48598 /* Maximum number of immediate bits allowed in a window. */
48599 #define MAX_IMM_SIZE 128
48601 /* Maximum number of 32 bit immediates allowed in a window. */
48602 #define MAX_IMM_32 4
48604 /* Maximum number of 64 bit immediates allowed in a window. */
48605 #define MAX_IMM_64 2
48607 /* Maximum total of loads or prefetches allowed in a window. */
48608 #define MAX_LOAD 2
48610 /* Maximum total of stores allowed in a window. */
48611 #define MAX_STORE 1
48613 #undef BIG
48614 #define BIG 100
48617 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
48620 disp_load,
48621 disp_store,
48622 disp_load_store,
48623 disp_prefetch,
48624 disp_imm,
48625 disp_imm_32,
48626 disp_imm_64,
48627 disp_branch,
48628 disp_cmp,
48629 disp_jcc,
48630 disp_last
48631 };
48633 /* Number of allowable groups in a dispatch window. It is an array
48634 indexed by dispatch_group enum. 100 is used as a big number,
48635 because the number of these kind of operations does not have any
48636 effect in dispatch window, but we need them for other reasons in
48637 the table. */
48640 };
48646 };
48648 /* Instruction path. */
48654 last_path
48655 };
48657 /* sched_insn_info defines a window to the instructions scheduled in
48658 the basic block. It contains a pointer to the insn_info table and
48659 the instruction scheduled.
48661 Windows are allocated for each basic block and are linked
48662 together. */
48664 rtx insn;
48671 /* Linked list of dispatch windows. This is a two way list of
48672 dispatch windows of a basic block. It contains information about
48673 the number of uops in the window and the total number of
48674 instructions and of bytes in the object code for this dispatch
48675 window. */
48693 /* Immediate valuse used in an insn. */
48695 {
48704 /* Get dispatch group of insn. */
48706 static enum dispatch_group
48708 {
48724 }
48726 /* Return true if insn is a compare instruction. */
48728 static bool
48730 {
48738 }
48740 /* Return true if a dispatch violation encountered. */
48742 static bool
48744 {
48748 }
48750 /* Return true if insn is a branch instruction. */
48752 static bool
48754 {
48756 }
48758 /* Return true if insn is a prefetch instruction. */
48760 static bool
48762 {
48764 }
48766 /* This function initializes a dispatch window and the list container holding a
48767 pointer to the window. */
48769 static void
48771 {
48777 else
48795 {
48801 }
48803 }
48805 /* This function allocates and initializes a dispatch window and the
48806 list container holding a pointer to the window. */
48810 {
48815 }
48817 /* This routine initializes the dispatch scheduling information. It
48818 initiates building dispatch scheduler tables and constructs the
48819 first dispatch window. */
48821 static void
48823 {
48824 /* Allocate a dispatch list and a window. */
48829 }
48831 /* This function returns true if a branch is detected. End of a basic block
48832 does not have to be a branch, but here we assume only branches end a
48833 window. */
48835 static bool
48837 {
48839 }
48841 /* This function is called when the end of a window processing is reached. */
48843 static void
48845 {
48848 {
48853 }
48855 }
48857 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
48858 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
48859 for 48 bytes of instructions. Note that these windows are not dispatch
48860 windows that their sizes are DISPATCH_WINDOW_SIZE. */
48864 {
48866 {
48871 }
48877 }
48879 /* Increment the number of immediate operands of an instruction. */
48881 static int
48883 {
48888 {
48895 else
48906 {
48909 }
48914 }
48917 }
48919 /* Compute number of immediate operands of an instruction. */
48921 static void
48923 {
48926 }
48928 /* Return total size of immediate operands of an instruction along with number
48929 of corresponding immediate-operands. It initializes its parameters to zero
48930 befor calling FIND_CONSTANT.
48931 INSN is the input instruction. IMM is the total of immediates.
48932 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
48933 bit immediates. */
48935 static int
48937 {
48945 }
48947 /* This function indicates if an operand of an instruction is an
48948 immediate. */
48950 static bool
48952 {
48961 }
48963 /* Return single or double path for instructions. */
48965 static enum insn_path
48967 {
48977 }
48979 /* Return insn dispatch group. */
48981 static enum dispatch_group
48983 {
49001 }
49003 /* Count number of GROUP restricted instructions in a dispatch
49004 window WINDOW_LIST. */
49006 static int
49008 {
49019 {
49038 }
49051 }
49053 /* This function returns true if insn satisfies dispatch rules on the
49054 last window scheduled. */
49056 static bool
49058 {
49066 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
49067 instructions should be given the lowest priority in the
49068 scheduling process in Haifa scheduler to make sure they will be
49069 scheduled in the same dispatch window as the reference to them. */
49073 /* Check nonrestricted. */
49077 /* Get last dispatch window. */
49082 {
49087 /* Window 1 is full. Go for next window. */
49089 }
49096 /* See if it fits in the first window. */
49098 {
49099 /* The first widow should have only single and double path
49100 uops. */
49106 }
49108 }
49110 /* Add an instruction INSN with NUM_UOPS micro-operations to the
49111 dispatch window WINDOW_LIST. */
49113 static void
49115 {
49133 /* Initialize window with new instruction. */
49154 {
49157 }
49158 }
49160 /* Adds a scheduled instruction, INSN, to the current dispatch window.
49161 If the total bytes of instructions or the number of instructions in
49162 the window exceed allowable, it allocates a new window. */
49164 static void
49166 {
49189 /* Get the last dispatch window. */
49197 else
49200 /* If current window is full, get a new window.
49201 Window number zero is full, if MAX_INSN uops are scheduled in it.
49202 Window number one is full, if window zero's bytes plus window
49203 one's bytes is 32, or if the bytes of the new instruction added
49204 to the total makes it greater than 48, or it has already MAX_INSN
49205 instructions in it. */
49214 {
49217 }
49220 {
49224 {
49227 }
49228 }
49230 {
49235 {
49238 }
49241 }
49242 else
49246 {
49247 /* End of basic block is reached do end-basic-block process. */
49250 }
49251 }
49253 /* Print the dispatch window, WINDOW_NUM, to FILE. */
49255 DEBUG_FUNCTION static void
49257 {
49263 else
49277 {
49280 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
49286 }
49287 }
49289 /* Print to stdout a dispatch window. */
49291 DEBUG_FUNCTION void
49293 {
49295 }
49297 /* Print INSN dispatch information to FILE. */
49299 DEBUG_FUNCTION static void
49301 {
49324 }
49326 /* Print to STDERR the status of the ready list with respect to
49327 dispatch windows. */
49329 DEBUG_FUNCTION void
49331 {
49339 }
49341 /* This routine is the driver of the dispatch scheduler. */
49343 static void
49345 {
49350 }
49352 /* Return TRUE if Dispatch Scheduling is supported. */
49354 static bool
49356 {
49360 {
49376 }
49379 }
49381 /* Implementation of reassociation_width target hook used by
49382 reassoc phase to identify parallelism level in reassociated
49383 tree. Statements tree_code is passed in OPC. Arguments type
49384 is passed in MODE.
49386 Currently parallel reassociation is enabled for Atom
49387 processors only and we set reassociation width to be 2
49388 because Atom may issue up to 2 instructions per cycle.
49390 Return value should be fixed if parallel reassociation is
49391 enabled for other processors. */
49393 static int
49396 {
49399 /* Vector part. */
49401 {
49404 else
49406 }
49408 /* Scalar part. */
49415 }
49417 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
49418 place emms and femms instructions. */
49420 static enum machine_mode
49422 {
49427 {
49446 else
49458 /* FALLTHRU */
49462 }
49463 }
49465 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
49466 vectors. If AVX512F is enabled then try vectorizing with 512bit,
49467 256bit and 128bit vectors. */
49469 static unsigned int
49471 {
49474 }
49476 \f
49478 /* Return class of registers which could be used for pseudo of MODE
49479 and of class RCLASS for spilling instead of memory. Return NO_REGS
49480 if it is not possible or non-profitable. */
49481 static reg_class_t
49483 {
49489 }
49491 /* Implement targetm.vectorize.init_cost. */
49495 {
49499 }
49501 /* Implement targetm.vectorize.add_stmt_cost. */
49503 static unsigned
49507 {
49514 /* Statements in an inner loop relative to the loop being
49515 vectorized are weighted more heavily. The value here is
49516 arbitrary and could potentially be improved with analysis. */
49522 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
49523 for Silvermont as it has out of order integer pipeline and can execute
49524 2 scalar instruction per tick, but has in order SIMD pipeline. */
49527 {
49531 }
49536 }
49538 /* Implement targetm.vectorize.finish_cost. */
49540 static void
49543 {
49548 }
49550 /* Implement targetm.vectorize.destroy_cost_data. */
49552 static void
49554 {
49556 }
49558 /* Validate target specific memory model bits in VAL. */
49560 static unsigned HOST_WIDE_INT
49562 {
49569 {
49573 }
49576 {
49580 }
49582 {
49586 }
49588 }
49590 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
49591 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
49592 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
49593 or number of vecsize_mangle variants that should be emitted. */
49595 static int
49599 {
49606 {
49610 }
49615 {
49622 /* case SCmode: */
49623 /* case DCmode: */
49629 }
49631 tree t;
49635 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
49637 {
49644 /* case SCmode: */
49645 /* case DCmode: */
49651 }
49654 {
49655 /* Parse here processor clause. If not present, default to 'b'. */
49657 }
49659 {
49660 /* If the function isn't exported, we can pick up just one ISA
49661 for the clones. */
49666 else
49669 }
49670 else
49671 {
49674 }
49676 {
49689 }
49691 {
49694 else
49699 }
49701 }
49703 /* Add target attribute to SIMD clone NODE if needed. */
49705 static void
49707 {
49711 {
49726 }
49736 }
49738 /* If SIMD clone NODE can't be used in a vectorized loop
49739 in current function, return -1, otherwise return a badness of using it
49740 (0 if it is most desirable from vecsize_mangle point of view, 1
49741 slightly less desirable, etc.). */
49743 static int
49745 {
49747 {
49765 }
49766 }
49768 /* This function gives out the number of memory references.
49769 This value determines the unrolling factor for
49770 bdver3 and bdver4 architectures. */
49772 static int
49774 {
49776 {
49785 else
49787 }
49789 }
49791 /* This function adjusts the unroll factor based on
49792 the hardware capabilities. For ex, bdver3 has
49793 a loop buffer which makes unrolling of smaller
49794 loops less important. This function decides the
49795 unroll factor using number of memory references
49796 (value 32 is used) as a heuristic. */
49798 static unsigned
49800 {
49802 rtx insn;
49809 /* Count the number of memory references within the loop body. */
49812 {
49816 }
49823 }
49826 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
49828 static bool
49830 {
49831 /* For x87 floating point with standard excess precision handling,
49832 there is no adddf3 pattern (since x87 floating point only has
49833 XFmode operations) so the default hook implementation gets this
49834 wrong. */
49836 }
49838 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
49840 static void
49842 {
49847 {
49862 hold_fnclex);
49875 }
49877 {
49886 mxcsr_orig_var,
49896 ldmxcsr_hold_call);
49899 else
49904 ldmxcsr_clear_call);
49905 else
49909 stxmcsr_update_call);
49911 {
49917 exceptions_assign);
49918 }
49919 else
49924 ldmxcsr_update_call);
49925 }
49926 tree atomic_feraiseexcept
49931 atomic_feraiseexcept_call);
49932 }
49934 /* Initialize the GCC target structure. */
49935 #undef TARGET_RETURN_IN_MEMORY
49936 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
49938 #undef TARGET_LEGITIMIZE_ADDRESS
49939 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
49941 #undef TARGET_ATTRIBUTE_TABLE
49942 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
49943 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
49944 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
49945 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
49946 # undef TARGET_MERGE_DECL_ATTRIBUTES
49947 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
49948 #endif
49950 #undef TARGET_COMP_TYPE_ATTRIBUTES
49951 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
49953 #undef TARGET_INIT_BUILTINS
49954 #define TARGET_INIT_BUILTINS ix86_init_builtins
49955 #undef TARGET_BUILTIN_DECL
49956 #define TARGET_BUILTIN_DECL ix86_builtin_decl
49957 #undef TARGET_EXPAND_BUILTIN
49958 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
49960 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
49961 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
49962 ix86_builtin_vectorized_function
49964 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
49965 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
49967 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
49968 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
49970 #undef TARGET_VECTORIZE_BUILTIN_GATHER
49971 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
49973 #undef TARGET_BUILTIN_RECIPROCAL
49974 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
49976 #undef TARGET_ASM_FUNCTION_EPILOGUE
49977 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
49979 #undef TARGET_ENCODE_SECTION_INFO
49980 #ifndef SUBTARGET_ENCODE_SECTION_INFO
49981 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
49982 #else
49983 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
49984 #endif
49986 #undef TARGET_ASM_OPEN_PAREN
49988 #undef TARGET_ASM_CLOSE_PAREN
49991 #undef TARGET_ASM_BYTE_OP
49992 #define TARGET_ASM_BYTE_OP ASM_BYTE
49994 #undef TARGET_ASM_ALIGNED_HI_OP
49995 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
49996 #undef TARGET_ASM_ALIGNED_SI_OP
49997 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
49998 #ifdef ASM_QUAD
49999 #undef TARGET_ASM_ALIGNED_DI_OP
50000 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
50001 #endif
50003 #undef TARGET_PROFILE_BEFORE_PROLOGUE
50004 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
50006 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
50007 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
50009 #undef TARGET_ASM_UNALIGNED_HI_OP
50010 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
50011 #undef TARGET_ASM_UNALIGNED_SI_OP
50012 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
50013 #undef TARGET_ASM_UNALIGNED_DI_OP
50014 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
50016 #undef TARGET_PRINT_OPERAND
50017 #define TARGET_PRINT_OPERAND ix86_print_operand
50018 #undef TARGET_PRINT_OPERAND_ADDRESS
50019 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
50020 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
50021 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
50022 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
50023 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
50025 #undef TARGET_SCHED_INIT_GLOBAL
50026 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
50027 #undef TARGET_SCHED_ADJUST_COST
50028 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
50029 #undef TARGET_SCHED_ISSUE_RATE
50030 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
50031 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
50032 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
50033 ia32_multipass_dfa_lookahead
50034 #undef TARGET_SCHED_MACRO_FUSION_P
50035 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
50036 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
50037 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
50039 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
50040 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
50042 #undef TARGET_MEMMODEL_CHECK
50043 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
50045 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
50046 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
50048 #ifdef HAVE_AS_TLS
50049 #undef TARGET_HAVE_TLS
50050 #define TARGET_HAVE_TLS true
50051 #endif
50052 #undef TARGET_CANNOT_FORCE_CONST_MEM
50053 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
50054 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
50055 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
50057 #undef TARGET_DELEGITIMIZE_ADDRESS
50058 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
50060 #undef TARGET_MS_BITFIELD_LAYOUT_P
50061 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
50063 #if TARGET_MACHO
50064 #undef TARGET_BINDS_LOCAL_P
50065 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
50066 #endif
50067 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
50068 #undef TARGET_BINDS_LOCAL_P
50069 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
50070 #endif
50072 #undef TARGET_ASM_OUTPUT_MI_THUNK
50073 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
50074 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
50075 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
50077 #undef TARGET_ASM_FILE_START
50078 #define TARGET_ASM_FILE_START x86_file_start
50080 #undef TARGET_OPTION_OVERRIDE
50081 #define TARGET_OPTION_OVERRIDE ix86_option_override
50083 #undef TARGET_REGISTER_MOVE_COST
50084 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
50085 #undef TARGET_MEMORY_MOVE_COST
50086 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
50087 #undef TARGET_RTX_COSTS
50088 #define TARGET_RTX_COSTS ix86_rtx_costs
50089 #undef TARGET_ADDRESS_COST
50090 #define TARGET_ADDRESS_COST ix86_address_cost
50092 #undef TARGET_FIXED_CONDITION_CODE_REGS
50093 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
50094 #undef TARGET_CC_MODES_COMPATIBLE
50095 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
50097 #undef TARGET_MACHINE_DEPENDENT_REORG
50098 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
50100 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
50101 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
50103 #undef TARGET_BUILD_BUILTIN_VA_LIST
50104 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
50106 #undef TARGET_FOLD_BUILTIN
50107 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
50109 #undef TARGET_COMPARE_VERSION_PRIORITY
50110 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
50112 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
50113 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
50114 ix86_generate_version_dispatcher_body
50116 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
50117 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
50118 ix86_get_function_versions_dispatcher
50120 #undef TARGET_ENUM_VA_LIST_P
50121 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
50123 #undef TARGET_FN_ABI_VA_LIST
50124 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
50126 #undef TARGET_CANONICAL_VA_LIST_TYPE
50127 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
50129 #undef TARGET_EXPAND_BUILTIN_VA_START
50130 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
50132 #undef TARGET_MD_ASM_CLOBBERS
50133 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
50135 #undef TARGET_PROMOTE_PROTOTYPES
50136 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
50137 #undef TARGET_SETUP_INCOMING_VARARGS
50138 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
50139 #undef TARGET_MUST_PASS_IN_STACK
50140 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
50141 #undef TARGET_FUNCTION_ARG_ADVANCE
50142 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
50143 #undef TARGET_FUNCTION_ARG
50144 #define TARGET_FUNCTION_ARG ix86_function_arg
50145 #undef TARGET_FUNCTION_ARG_BOUNDARY
50146 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
50147 #undef TARGET_PASS_BY_REFERENCE
50148 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
50149 #undef TARGET_INTERNAL_ARG_POINTER
50150 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
50151 #undef TARGET_UPDATE_STACK_BOUNDARY
50152 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
50153 #undef TARGET_GET_DRAP_RTX
50154 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
50155 #undef TARGET_STRICT_ARGUMENT_NAMING
50156 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
50157 #undef TARGET_STATIC_CHAIN
50158 #define TARGET_STATIC_CHAIN ix86_static_chain
50159 #undef TARGET_TRAMPOLINE_INIT
50160 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
50161 #undef TARGET_RETURN_POPS_ARGS
50162 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
50164 #undef TARGET_LEGITIMATE_COMBINED_INSN
50165 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
50167 #undef TARGET_ASAN_SHADOW_OFFSET
50168 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
50170 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
50171 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
50173 #undef TARGET_SCALAR_MODE_SUPPORTED_P
50174 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
50176 #undef TARGET_VECTOR_MODE_SUPPORTED_P
50177 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
50179 #undef TARGET_C_MODE_FOR_SUFFIX
50180 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
50182 #ifdef HAVE_AS_TLS
50183 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
50184 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
50185 #endif
50187 #ifdef SUBTARGET_INSERT_ATTRIBUTES
50188 #undef TARGET_INSERT_ATTRIBUTES
50189 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
50190 #endif
50192 #undef TARGET_MANGLE_TYPE
50193 #define TARGET_MANGLE_TYPE ix86_mangle_type
50195 #if !TARGET_MACHO
50196 #undef TARGET_STACK_PROTECT_FAIL
50197 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
50198 #endif
50200 #undef TARGET_FUNCTION_VALUE
50201 #define TARGET_FUNCTION_VALUE ix86_function_value
50203 #undef TARGET_FUNCTION_VALUE_REGNO_P
50204 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
50206 #undef TARGET_PROMOTE_FUNCTION_MODE
50207 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
50209 #undef TARGET_MEMBER_TYPE_FORCES_BLK
50210 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
50212 #undef TARGET_INSTANTIATE_DECLS
50213 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
50215 #undef TARGET_SECONDARY_RELOAD
50216 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
50218 #undef TARGET_CLASS_MAX_NREGS
50219 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
50221 #undef TARGET_PREFERRED_RELOAD_CLASS
50222 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
50223 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
50224 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
50225 #undef TARGET_CLASS_LIKELY_SPILLED_P
50226 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
50228 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
50229 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
50230 ix86_builtin_vectorization_cost
50231 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
50232 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
50233 ix86_vectorize_vec_perm_const_ok
50234 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
50235 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
50236 ix86_preferred_simd_mode
50237 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
50238 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
50239 ix86_autovectorize_vector_sizes
50240 #undef TARGET_VECTORIZE_INIT_COST
50241 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
50242 #undef TARGET_VECTORIZE_ADD_STMT_COST
50243 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
50244 #undef TARGET_VECTORIZE_FINISH_COST
50245 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
50246 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
50247 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
50249 #undef TARGET_SET_CURRENT_FUNCTION
50250 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
50252 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
50253 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
50255 #undef TARGET_OPTION_SAVE
50256 #define TARGET_OPTION_SAVE ix86_function_specific_save
50258 #undef TARGET_OPTION_RESTORE
50259 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
50261 #undef TARGET_OPTION_PRINT
50262 #define TARGET_OPTION_PRINT ix86_function_specific_print
50264 #undef TARGET_OPTION_FUNCTION_VERSIONS
50265 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
50267 #undef TARGET_CAN_INLINE_P
50268 #define TARGET_CAN_INLINE_P ix86_can_inline_p
50270 #undef TARGET_EXPAND_TO_RTL_HOOK
50271 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
50273 #undef TARGET_LEGITIMATE_ADDRESS_P
50274 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
50276 #undef TARGET_LRA_P
50277 #define TARGET_LRA_P hook_bool_void_true
50279 #undef TARGET_REGISTER_PRIORITY
50280 #define TARGET_REGISTER_PRIORITY ix86_register_priority
50282 #undef TARGET_REGISTER_USAGE_LEVELING_P
50283 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
50285 #undef TARGET_LEGITIMATE_CONSTANT_P
50286 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
50288 #undef TARGET_FRAME_POINTER_REQUIRED
50289 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
50291 #undef TARGET_CAN_ELIMINATE
50292 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
50294 #undef TARGET_EXTRA_LIVE_ON_ENTRY
50295 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
50297 #undef TARGET_ASM_CODE_END
50298 #define TARGET_ASM_CODE_END ix86_code_end
50300 #undef TARGET_CONDITIONAL_REGISTER_USAGE
50301 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
50303 #if TARGET_MACHO
50304 #undef TARGET_INIT_LIBFUNCS
50305 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
50306 #endif
50308 #undef TARGET_LOOP_UNROLL_ADJUST
50309 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
50311 #undef TARGET_SPILL_CLASS
50312 #define TARGET_SPILL_CLASS ix86_spill_class
50314 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
50315 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
50316 ix86_simd_clone_compute_vecsize_and_simdlen
50318 #undef TARGET_SIMD_CLONE_ADJUST
50319 #define TARGET_SIMD_CLONE_ADJUST \
50320 ix86_simd_clone_adjust
50322 #undef TARGET_SIMD_CLONE_USABLE
50323 #define TARGET_SIMD_CLONE_USABLE \
50324 ix86_simd_clone_usable
50326 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
50327 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
50328 ix86_float_exceptions_rounding_supported_p
50330 #undef TARGET_MODE_EMIT
50331 #define TARGET_MODE_EMIT ix86_emit_mode_set
50333 #undef TARGET_MODE_NEEDED
50334 #define TARGET_MODE_NEEDED ix86_mode_needed
50336 #undef TARGET_MODE_AFTER
50337 #define TARGET_MODE_AFTER ix86_mode_after
50339 #undef TARGET_MODE_ENTRY
50340 #define TARGET_MODE_ENTRY ix86_mode_entry
50342 #undef TARGET_MODE_EXIT
50343 #define TARGET_MODE_EXIT ix86_mode_exit
50345 #undef TARGET_MODE_PRIORITY
50346 #define TARGET_MODE_PRIORITY ix86_mode_priority
50348 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
50349 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
50352 \f