| blob | 83d86071312a25789dc40f4f236fec5260d04c87 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
71 /* This file should be included last. */
74 /* Defined for convenience. */
75 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
77 /* Classifies an address.
79 ADDRESS_REG_IMM
80 A simple base register plus immediate offset.
82 ADDRESS_REG_WB
83 A base register indexed by immediate offset with writeback.
85 ADDRESS_REG_REG
86 A base register indexed by (optionally scaled) register.
88 ADDRESS_REG_UXTW
89 A base register indexed by (optionally scaled) zero-extended register.
91 ADDRESS_REG_SXTW
92 A base register indexed by (optionally scaled) sign-extended register.
94 ADDRESS_LO_SUM
95 A LO_SUM rtx with a base register and "LO12" symbol relocation.
97 ADDRESS_SYMBOLIC:
98 A constant symbolic address, in pc-relative literal pool. */
101 ADDRESS_REG_IMM,
102 ADDRESS_REG_WB,
103 ADDRESS_REG_REG,
104 ADDRESS_REG_UXTW,
105 ADDRESS_REG_SXTW,
106 ADDRESS_LO_SUM,
107 ADDRESS_SYMBOLIC
108 };
112 rtx base;
113 rtx offset;
116 };
118 struct simd_immediate_info
119 {
120 rtx value;
125 };
127 /* The current code model. */
130 #ifdef HAVE_AS_TLS
131 #undef TARGET_HAVE_TLS
132 #define TARGET_HAVE_TLS 1
133 #endif
137 const_tree,
145 vec_perm_indices);
148 const_tree type,
151 static machine_mode
155 /* Major revision number of the ARM Architecture implemented by the target. */
158 /* The processor for which instructions should be scheduled. */
161 /* Mask to specify which instruction scheduling options should be used. */
164 /* Global flag for PC relative loads. */
167 /* Support for command line parsing of boolean flags in the tuning
168 structures. */
169 struct aarch64_flag_desc
170 {
173 };
175 #define AARCH64_FUSION_PAIR(name, internal_name) \
176 { name, AARCH64_FUSE_##internal_name },
178 {
183 };
185 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
186 { name, AARCH64_EXTRA_TUNE_##internal_name },
188 {
193 };
195 /* Tuning parameters. */
198 {
199 {
204 },
211 };
214 {
215 {
220 },
227 };
230 {
231 {
236 },
243 };
246 {
247 {
252 },
259 };
262 {
264 /* Avoid the use of slow int<->fp moves for spilling by setting
265 their cost higher than memmov_cost. */
269 };
272 {
274 /* Avoid the use of slow int<->fp moves for spilling by setting
275 their cost higher than memmov_cost. */
279 };
282 {
284 /* Avoid the use of slow int<->fp moves for spilling by setting
285 their cost higher than memmov_cost. */
289 };
292 {
294 /* Avoid the use of slow int<->fp moves for spilling by setting
295 their cost higher than memmov_cost (actual, 4 and 9). */
299 };
302 {
307 };
310 {
312 /* Avoid the use of slow int<->fp moves for spilling by setting
313 their cost higher than memmov_cost. */
317 };
320 {
322 /* Avoid the use of int<->fp moves for spilling. */
326 };
329 {
331 /* Avoid the use of int<->fp moves for spilling. */
335 };
337 /* Generic costs for vector insn classes. */
339 {
355 };
357 /* ThunderX costs for vector insn classes. */
359 {
375 };
377 /* Generic costs for vector insn classes. */
379 {
395 };
398 {
414 };
416 /* Generic costs for vector insn classes. */
418 {
434 };
436 /* Costs for vector insn classes for Vulcan. */
438 {
454 };
456 /* Generic costs for branch instructions. */
458 {
461 };
463 /* Generic approximation modes. */
465 {
468 AARCH64_APPROX_NONE /* recip_sqrt */
469 };
471 /* Approximation modes for Exynos M1. */
473 {
476 AARCH64_APPROX_ALL /* recip_sqrt */
477 };
479 /* Approximation modes for X-Gene 1. */
481 {
484 AARCH64_APPROX_ALL /* recip_sqrt */
485 };
487 /* Generic prefetch settings (which disable prefetch). */
489 {
495 };
498 {
504 };
507 {
513 };
516 {
522 };
525 {
531 };
534 {
540 };
543 {
564 &generic_prefetch_tune
565 };
568 {
590 &generic_prefetch_tune
591 };
594 {
616 &generic_prefetch_tune
617 };
620 {
642 &generic_prefetch_tune
643 };
646 {
668 &generic_prefetch_tune
669 };
672 {
694 &generic_prefetch_tune
695 };
700 {
721 &exynosm1_prefetch_tune
722 };
725 {
746 &thunderxt88_prefetch_tune
747 };
750 {
770 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
772 &thunderx_prefetch_tune
773 };
776 {
797 &generic_prefetch_tune
798 };
801 {
823 &qdf24xx_prefetch_tune
824 };
826 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
827 for now. */
829 {
851 &generic_prefetch_tune
852 };
855 {
877 &thunderx2t99_prefetch_tune
878 };
880 /* Support for fine-grained override of the tuning structures. */
881 struct aarch64_tuning_override_function
882 {
885 };
890 static const struct aarch64_tuning_override_function
891 aarch64_tuning_override_functions[] =
892 {
896 };
898 /* A processor implementing AArch64. */
899 struct processor
900 {
908 };
910 /* Architectures implementing AArch64. */
912 {
913 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
914 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
917 };
919 /* Processor cores implementing AArch64. */
921 {
922 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
923 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
924 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
925 FLAGS, &COSTS##_tunings},
930 };
933 /* Target specification. These are populated by the -march, -mtune, -mcpu
934 handling code or by target attributes. */
939 /* The current tuning set. */
942 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
944 /* An ISA extension in the co-processor and main instruction set space. */
945 struct aarch64_option_extension
946 {
950 };
953 {
957 }
958 aarch64_cc;
960 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
962 /* The condition codes of the processor, and the inverse function. */
964 {
967 };
969 /* Generate code to enable conditional branches in functions over 1 MiB. */
973 {
990 }
992 void
994 {
998 else
1000 }
1002 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
1003 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
1004 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
1005 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
1006 cost (in this case the best class is the lowest cost one). Using ALL_REGS
1007 irrespectively of its cost results in bad allocations with many redundant
1008 int<->FP moves which are expensive on various cores.
1009 To avoid this we don't allow ALL_REGS as the allocno class, but force a
1010 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
1011 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
1012 Otherwise set the allocno class depending on the mode.
1013 The result of this is that it is no longer inefficient to have a higher
1014 memory move cost than the register move cost.
1015 */
1017 static reg_class_t
1019 reg_class_t best_class)
1020 {
1021 machine_mode mode;
1031 }
1033 static unsigned int
1035 {
1039 }
1041 static int
1043 machine_mode mode)
1044 {
1052 }
1054 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
1055 unsigned
1057 {
1065 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
1066 equivalent DWARF register. */
1068 }
1070 /* Return TRUE if MODE is any of the large INT modes. */
1071 static bool
1073 {
1075 }
1077 /* Return TRUE if MODE is any of the vector modes. */
1078 static bool
1080 {
1083 }
1085 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1086 static bool
1089 {
1097 }
1099 /* Implement TARGET_HARD_REGNO_NREGS. */
1101 static unsigned int
1103 {
1105 {
1111 }
1113 }
1115 /* Implement TARGET_HARD_REGNO_MODE_OK. */
1117 static bool
1119 {
1124 /* The purpose of comparing with ptr_mode is to support the
1125 global register variable associated with the stack pointer
1126 register via the syntax of asm ("wsp") in ILP32. */
1136 {
1139 else
1141 }
1144 }
1146 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
1147 the lower 64 bits of a 128-bit register. Tell the compiler the callee
1148 clobbers the top 64 bits when restoring the bottom 64 bits. */
1150 static bool
1152 {
1154 }
1156 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1157 machine_mode
1159 machine_mode mode)
1160 {
1161 /* Handle modes that fit within single registers. */
1163 {
1166 else
1168 }
1169 /* Fall back to generic for multi-reg and very large modes. */
1170 else
1172 }
1174 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
1175 that strcpy from constants will be faster. */
1177 static HOST_WIDE_INT
1179 {
1183 }
1185 /* Return true if calls to DECL should be treated as
1186 long-calls (ie called via a register). */
1187 static bool
1189 {
1191 }
1193 /* Return true if calls to symbol-ref SYM should be treated as
1194 long-calls (ie called via a register). */
1195 bool
1197 {
1199 }
1201 /* Return true if calls to symbol-ref SYM should not go through
1202 plt stubs. */
1204 bool
1206 {
1210 && decl
1211 && (!flag_plt
1217 }
1219 /* Return true if the offsets to a zero/sign-extract operation
1220 represent an expression that matches an extend operation. The
1221 operands represent the paramters from
1223 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1224 bool
1226 rtx extract_imm)
1227 {
1244 }
1246 /* Emit an insn that's a simple single-set. Both the operands must be
1247 known to be valid. */
1250 {
1252 }
1254 /* X and Y are two things to compare using CODE. Emit the compare insn and
1255 return the rtx for register 0 in the proper mode. */
1256 rtx
1258 {
1264 }
1266 /* Build the SYMBOL_REF for __tls_get_addr. */
1270 rtx
1272 {
1276 }
1278 /* Return the TLS model to use for ADDR. */
1280 static enum tls_model
1282 {
1287 {
1291 }
1296 }
1298 /* We'll allow lo_sum's in addresses in our legitimate addresses
1299 so that combine would take care of combining addresses where
1300 necessary, but for generation purposes, we'll generate the address
1301 as :
1302 RTL Absolute
1303 tmp = hi (symbol_ref); adrp x1, foo
1304 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1305 nop
1307 PIC TLS
1308 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1309 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1310 bl __tls_get_addr
1311 nop
1313 Load TLS symbol, depending on TLS mechanism and TLS access model.
1315 Global Dynamic - Traditional TLS:
1316 adrp tmp, :tlsgd:imm
1317 add dest, tmp, #:tlsgd_lo12:imm
1318 bl __tls_get_addr
1320 Global Dynamic - TLS Descriptors:
1321 adrp dest, :tlsdesc:imm
1322 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1323 add dest, dest, #:tlsdesc_lo12:imm
1324 blr tmp
1325 mrs tp, tpidr_el0
1326 add dest, dest, tp
1328 Initial Exec:
1329 mrs tp, tpidr_el0
1330 adrp tmp, :gottprel:imm
1331 ldr dest, [tmp, #:gottprel_lo12:imm]
1332 add dest, dest, tp
1334 Local Exec:
1335 mrs tp, tpidr_el0
1336 add t0, tp, #:tprel_hi12:imm, lsl #12
1337 add t0, t0, #:tprel_lo12_nc:imm
1338 */
1340 static void
1343 {
1345 {
1347 {
1348 /* In ILP32, the mode of dest can be either SImode or DImode. */
1360 }
1367 {
1370 rtx insn;
1371 rtx mem;
1373 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1374 here before rtl expand. Tree IVOPT will generate rtl pattern to
1375 decide rtx costs, in which case pic_offset_table_rtx is not
1376 initialized. For that case no need to generate the first adrp
1377 instruction as the final cost for global variable access is
1378 one instruction. */
1380 {
1381 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1382 using the page base as GOT base, the first page may be wasted,
1383 in the worst scenario, there is only 28K space for GOT).
1385 The generate instruction sequence for accessing global variable
1386 is:
1388 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1390 Only one instruction needed. But we must initialize
1391 pic_offset_table_rtx properly. We generate initialize insn for
1392 every global access, and allow CSE to remove all redundant.
1394 The final instruction sequences will look like the following
1395 for multiply global variables access.
1397 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1399 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1400 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1401 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1402 ... */
1411 }
1414 {
1417 else
1421 }
1422 else
1423 {
1428 }
1430 /* The operand is expected to be MEM. Whenever the related insn
1431 pattern changed, above code which calculate mem should be
1432 updated. */
1438 }
1441 {
1442 /* In ILP32, the mode of dest can be either SImode or DImode,
1443 while the got entry is always of SImode size. The mode of
1444 dest depends on how dest is used: if dest is assigned to a
1445 pointer (e.g. in the memory), it has SImode; it may have
1446 DImode if dest is dereferenced to access the memeory.
1447 This is why we have to handle three different ldr_got_small
1448 patterns here (two patterns for ILP32). */
1450 rtx insn;
1451 rtx mem;
1460 {
1463 else
1467 }
1468 else
1469 {
1474 }
1481 }
1484 {
1492 else
1500 }
1503 {
1506 rtx tp;
1510 /* In ILP32, the got entry is always of SImode size. Unlike
1511 small GOT, the dest is fixed at reg 0. */
1514 else
1525 }
1528 {
1529 /* In ILP32, the mode of dest can be either SImode or DImode,
1530 while the got entry is always of SImode size. The mode of
1531 dest depends on how dest is used: if dest is assigned to a
1532 pointer (e.g. in the memory), it has SImode; it may have
1533 DImode if dest is dereferenced to access the memeory.
1534 This is why we have to handle three different tlsie_small
1535 patterns here (two patterns for ILP32). */
1541 {
1544 else
1545 {
1548 }
1549 }
1550 else
1551 {
1554 }
1560 }
1566 {
1574 {
1597 }
1602 }
1609 {
1614 {
1617 else
1618 {
1621 }
1622 }
1623 else
1624 {
1627 }
1632 }
1636 }
1637 }
1639 /* Emit a move from SRC to DEST. Assume that the move expanders can
1640 handle all moves if !can_create_pseudo_p (). The distinction is
1641 important because, unlike emit_move_insn, the move expanders know
1642 how to force Pmode objects into the constant pool even when the
1643 constant pool address is not itself legitimate. */
1644 static rtx
1646 {
1650 }
1652 /* Split a 128-bit move operation into two 64-bit move operations,
1653 taking care to handle partial overlap of register to register
1654 copies. Special cases are needed when moving between GP regs and
1655 FP regs. SRC can be a register, constant or memory; DST a register
1656 or memory. If either operand is memory it must not have any side
1657 effects. */
1658 void
1660 {
1671 {
1675 /* Handle FP <-> GP regs. */
1677 {
1682 {
1685 }
1686 else
1687 {
1690 }
1692 }
1694 {
1699 {
1702 }
1703 else
1704 {
1707 }
1709 }
1710 }
1717 /* At most one pairing may overlap. */
1719 {
1722 }
1723 else
1724 {
1727 }
1728 }
1730 bool
1732 {
1735 }
1737 /* Split a complex SIMD combine. */
1739 void
1741 {
1753 {
1777 }
1781 }
1783 /* Split a complex SIMD move. */
1785 void
1787 {
1794 {
1800 {
1824 }
1828 }
1829 }
1831 bool
1834 {
1838 }
1841 static rtx
1843 {
1846 else
1847 {
1850 }
1851 }
1854 static rtx
1856 HOST_WIDE_INT offset)
1857 {
1859 {
1860 rtx high;
1861 /* Load the full offset into a register. This
1862 might be improvable in the future. */
1868 }
1870 }
1872 static int
1874 scalar_int_mode mode)
1875 {
1884 {
1888 }
1890 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
1891 (with XXXX non-zero). In that case check to see if the move can be done in
1892 a smaller mode. */
1897 {
1901 /* Check if we have to emit a second instruction by checking to see
1902 if any of the upper 32 bits of the original DI mode value is set. */
1913 }
1916 {
1918 {
1923 else
1926 }
1928 }
1930 /* Remaining cases are all for DImode. */
1939 {
1940 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1941 For a 64-bit bitmask try whether changing 16 bits to all ones or
1942 zeroes creates a valid bitmask. To check any repeated bitmask,
1943 try using 16 bits from the other 32-bit half of val. */
1946 {
1957 }
1959 {
1961 {
1965 }
1967 }
1968 }
1970 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1971 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1972 otherwise skip zero bits. */
1984 {
1990 num_insns ++;
1991 }
1994 }
1996 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1997 temporary value if necessary. FRAME_RELATED_P should be true if
1998 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1999 to the generated instructions. If SCRATCHREG is known to hold
2000 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
2001 immediate again.
2003 Since this function may be used to adjust the stack pointer, we must
2004 ensure that it cannot cause transient stack deallocation (for example
2005 by first incrementing SP and then decrementing when adjusting by a
2006 large immediate). */
2008 static void
2012 {
2020 /* Single instruction adjustment. */
2022 {
2026 }
2028 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2029 Only do this if mdelta is not a 16-bit move as adjusting using a move
2030 is better. */
2032 {
2041 }
2043 /* Emit a move immediate if required and an addition/subtraction. */
2050 {
2054 }
2055 }
2059 HOST_WIDE_INT delta)
2060 {
2062 }
2066 {
2069 }
2073 {
2076 }
2078 void
2080 {
2085 /* Check on what type of symbol it is. */
2086 scalar_int_mode int_mode;
2091 {
2095 /* If we have (const (plus symbol offset)), separate out the offset
2096 before we start classifying the symbol. */
2101 {
2105 {
2112 }
2117 /* If we aren't generating PC relative literals, then
2118 we need to expand the literal pool access carefully.
2119 This is something that needs to be done in a number
2120 of places, so could well live as a separate function. */
2122 {
2129 }
2146 {
2153 }
2154 /* FALLTHRU */
2167 }
2168 }
2171 {
2174 else
2175 {
2179 }
2182 }
2186 }
2188 static bool
2190 tree exp ATTRIBUTE_UNUSED)
2191 {
2192 /* Currently, always true. */
2194 }
2196 /* Implement TARGET_PASS_BY_REFERENCE. */
2198 static bool
2200 machine_mode mode,
2201 const_tree type,
2203 {
2204 HOST_WIDE_INT size;
2205 machine_mode dummymode;
2208 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2212 /* Aggregates are passed by reference based on their size. */
2214 {
2216 }
2218 /* Variable sized arguments are always returned by reference. */
2222 /* Can this be a candidate to be passed in fp/simd register(s)? */
2225 NULL))
2228 /* Arguments which are variable sized or larger than 2 registers are
2229 passed by reference unless they are a homogenous floating point
2230 aggregate. */
2232 }
2234 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2235 static bool
2237 {
2238 machine_mode dummy_mode;
2241 /* Never happens in little-endian mode. */
2245 /* Only composite types smaller than or equal to 16 bytes can
2246 be potentially returned in registers. */
2252 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2253 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2254 is always passed/returned in the least significant bits of fp/simd
2255 register(s). */
2261 }
2263 /* Implement TARGET_FUNCTION_VALUE.
2264 Define how to find the value returned by a function. */
2266 static rtx
2269 {
2270 machine_mode mode;
2273 machine_mode ag_mode;
2280 {
2284 {
2287 }
2288 }
2292 {
2294 {
2297 }
2298 else
2299 {
2301 rtx par;
2305 {
2310 }
2312 }
2313 }
2314 else
2316 }
2318 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2319 Return true if REGNO is the number of a hard register in which the values
2320 of called function may come back. */
2322 static bool
2324 {
2325 /* Maximum of 16 bytes can be returned in the general registers. Examples
2326 of 16-byte return values are: 128-bit integers and 16-byte small
2327 structures (excluding homogeneous floating-point aggregates). */
2331 /* Up to four fp/simd registers can return a function value, e.g. a
2332 homogeneous floating-point aggregate having four members. */
2337 }
2339 /* Implement TARGET_RETURN_IN_MEMORY.
2341 If the type T of the result of a function is such that
2342 void func (T arg)
2343 would require that arg be passed as a value in a register (or set of
2344 registers) according to the parameter passing rules, then the result
2345 is returned in the same registers as would be used for such an
2346 argument. */
2348 static bool
2350 {
2351 HOST_WIDE_INT size;
2352 machine_mode ag_mode;
2358 /* Simple scalar types always returned in registers. */
2362 type,
2365 NULL))
2368 /* Types larger than 2 registers returned in memory. */
2371 }
2373 static bool
2376 {
2379 type,
2381 nregs,
2382 NULL);
2383 }
2385 /* Given MODE and TYPE of a function argument, return the alignment in
2386 bits. The idea is to suppress any stronger alignment requested by
2387 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2388 This is a helper function for local use only. */
2390 static unsigned int
2392 {
2413 }
2415 /* Layout a function argument according to the AAPCS64 rules. The rule
2416 numbers refer to the rule numbers in the AAPCS64. */
2418 static void
2420 const_tree type,
2422 {
2426 HOST_WIDE_INT size;
2428 /* We need to do this once per argument. */
2434 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2435 size
2437 UNITS_PER_WORD);
2441 mode,
2442 type,
2445 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2446 The following code thus handles passing by SIMD/FP registers first. */
2450 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2451 and homogenous short-vector aggregates (HVA). */
2453 {
2458 {
2461 {
2464 }
2465 else
2466 {
2467 rtx par;
2471 {
2474 tmp = gen_rtx_EXPR_LIST
2478 }
2480 }
2482 }
2483 else
2484 {
2485 /* C.3 NSRN is set to 8. */
2488 }
2489 }
2494 /* C6 - C9. though the sign and zero extension semantics are
2495 handled elsewhere. This is the case where the argument fits
2496 entirely general registers. */
2498 {
2502 /* C.8 if the argument has an alignment of 16 then the NGRN is
2503 rounded up to the next even number. */
2506 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
2507 comparison is there because for > 16 * BITS_PER_UNIT
2508 alignment nregs should be > 2 and therefore it should be
2509 passed by reference rather than value. */
2511 {
2514 }
2516 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2517 A reg is still generated for it, but the caller should be smart
2518 enough not to use it. */
2521 else
2522 {
2523 rtx par;
2528 {
2533 }
2535 }
2539 }
2541 /* C.11 */
2544 /* The argument is passed on stack; record the needed number of words for
2545 this argument and align the total size if necessary. */
2546 on_stack:
2553 }
2555 /* Implement TARGET_FUNCTION_ARG. */
2557 static rtx
2560 {
2569 }
2571 void
2573 const_tree fntype ATTRIBUTE_UNUSED,
2574 rtx libname ATTRIBUTE_UNUSED,
2575 const_tree fndecl ATTRIBUTE_UNUSED,
2577 {
2591 {
2598 }
2600 }
2602 static void
2604 machine_mode mode,
2605 const_tree type,
2607 {
2610 {
2620 }
2621 }
2623 bool
2625 {
2628 }
2630 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2631 PARM_BOUNDARY bits of alignment, but will be given anything up
2632 to STACK_BOUNDARY bits if the type requires it. This makes sure
2633 that both before and after the layout of each argument, the Next
2634 Stacked Argument Address (NSAA) will have a minimum alignment of
2635 8 bytes. */
2637 static unsigned int
2639 {
2642 }
2644 /* Implement TARGET_FUNCTION_ARG_PADDING.
2646 Small aggregate types are placed in the lowest memory address.
2648 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2650 static pad_direction
2652 {
2653 /* On little-endian targets, the least significant byte of every stack
2654 argument is passed at the lowest byte address of the stack slot. */
2658 /* Otherwise, integral, floating-point and pointer types are padded downward:
2659 the least significant byte of a stack argument is passed at the highest
2660 byte address of the stack slot. */
2667 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2669 }
2671 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2673 It specifies padding for the last (may also be the only)
2674 element of a block move between registers and memory. If
2675 assuming the block is in the memory, padding upward means that
2676 the last element is padded after its highest significant byte,
2677 while in downward padding, the last element is padded at the
2678 its least significant byte side.
2680 Small aggregates and small complex types are always padded
2681 upwards.
2683 We don't need to worry about homogeneous floating-point or
2684 short-vector aggregates; their move is not affected by the
2685 padding direction determined here. Regardless of endianness,
2686 each element of such an aggregate is put in the least
2687 significant bits of a fp/simd register.
2689 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2690 register has useful data, and return the opposite if the most
2691 significant byte does. */
2693 bool
2696 {
2698 /* Small composite types are always padded upward. */
2700 {
2705 }
2707 /* Otherwise, use the default padding. */
2709 }
2711 static scalar_int_mode
2713 {
2715 }
2717 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2719 /* We use the 12-bit shifted immediate arithmetic instructions so values
2720 must be multiple of (1 << 12), i.e. 4096. */
2721 #define ARITH_FACTOR 4096
2723 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2724 #error Cannot use simple address calculation for stack probing
2725 #endif
2727 /* The pair of scratch registers used for stack probing. */
2728 #define PROBE_STACK_FIRST_REG 9
2729 #define PROBE_STACK_SECOND_REG 10
2731 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2732 inclusive. These are offsets from the current stack pointer. */
2734 static void
2736 {
2739 /* See the same assertion on PROBE_INTERVAL above. */
2742 /* See if we have a constant small number of probes to generate. If so,
2743 that's the easy case. */
2745 {
2752 }
2754 /* The run-time loop is made up of 8 insns in the generic case while the
2755 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2757 {
2762 stack_pointer_rtx,
2766 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2767 it exceeds SIZE. If only two probes are needed, this will not
2768 generate any code. Then probe at FIRST + SIZE. */
2770 {
2774 }
2778 {
2783 }
2784 else
2786 }
2788 /* Otherwise, do the same as above, but in a loop. Note that we must be
2789 extra careful with variables wrapping around because we might be at
2790 the very top (or the very bottom) of the address space and we have
2791 to be able to handle this case properly; in particular, we use an
2792 equality test for the loop condition. */
2793 else
2794 {
2797 /* Step 1: round SIZE to the previous multiple of the interval. */
2802 /* Step 2: compute initial and final value of the loop counter. */
2804 /* TEST_ADDR = SP + FIRST. */
2808 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2811 {
2815 }
2816 else
2817 {
2820 }
2822 /* Step 3: the loop
2824 do
2825 {
2826 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2827 probe at TEST_ADDR
2828 }
2829 while (TEST_ADDR != LAST_ADDR)
2831 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2832 until it is equal to ROUNDED_SIZE. */
2837 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2838 that SIZE is equal to ROUNDED_SIZE. */
2841 {
2845 {
2850 }
2851 else
2853 }
2854 }
2856 /* Make sure nothing is scheduled before we are done. */
2858 }
2860 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2861 absolute addresses. */
2865 {
2872 /* Loop. */
2875 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2880 /* Probe at TEST_ADDR. */
2883 /* Test if TEST_ADDR == LAST_ADDR. */
2887 /* Branch. */
2893 }
2895 /* Mark the registers that need to be saved by the callee and calculate
2896 the size of the callee-saved registers area and frame record (both FP
2897 and LR may be omitted). */
2898 static void
2900 {
2907 /* Force a frame chain for EH returns so the return address is at FP+8. */
2911 /* Emit a frame chain if the frame pointer is enabled.
2912 If -momit-leaf-frame-pointer is used, do not use a frame chain
2913 in leaf functions which do not use LR. */
2919 #define SLOT_NOT_REQUIRED (-2)
2920 #define SLOT_REQUIRED (-1)
2925 /* First mark all the registers that really need to be saved... */
2932 /* ... that includes the eh data registers (if needed)... */
2938 /* ... and any callee saved register that dataflow says is live. */
2948 {
2951 }
2954 {
2955 /* FP and LR are placed in the linkage record. */
2961 }
2963 /* Now assign stack slots for them. */
2966 {
2973 }
2981 {
2982 /* If there is an alignment gap between integer and fp callee-saves,
2983 allocate the last fp register to it if possible. */
2985 {
2988 }
2997 }
3003 HOST_WIDE_INT varargs_and_saved_regs_size
3030 {
3031 /* Simple, small frame with no outgoing arguments:
3032 stp reg1, reg2, [sp, -frame_size]!
3033 stp reg3, reg4, [sp, 16] */
3035 }
3040 {
3041 /* Frame with small outgoing arguments:
3042 sub sp, sp, frame_size
3043 stp reg1, reg2, [sp, outgoing_args_size]
3044 stp reg3, reg4, [sp, outgoing_args_size + 16] */
3048 }
3050 {
3051 /* Frame with large outgoing arguments but a small local area:
3052 stp reg1, reg2, [sp, -hard_fp_offset]!
3053 stp reg3, reg4, [sp, 16]
3054 sub sp, sp, outgoing_args_size */
3058 }
3059 else
3060 {
3061 /* Frame with large local area and outgoing arguments using frame pointer:
3062 sub sp, sp, hard_fp_offset
3063 stp x29, x30, [sp, 0]
3064 add x29, sp, 0
3065 stp reg3, reg4, [sp, 16]
3066 sub sp, sp, outgoing_args_size */
3070 }
3073 }
3075 /* Return true if the register REGNO is saved on entry to
3076 the current function. */
3078 static bool
3080 {
3082 }
3084 /* Return the next register up from REGNO up to LIMIT for the callee
3085 to save. */
3087 static unsigned
3089 {
3091 regno ++;
3093 }
3095 /* Push the register number REGNO of mode MODE to the stack with write-back
3096 adjusting the stack by ADJUSTMENT. */
3098 static void
3100 HOST_WIDE_INT adjustment)
3101 {
3112 }
3114 /* Generate and return an instruction to store the pair of registers
3115 REG and REG2 of mode MODE to location BASE with write-back adjusting
3116 the stack location BASE by ADJUSTMENT. */
3118 static rtx
3120 HOST_WIDE_INT adjustment)
3121 {
3123 {
3134 }
3135 }
3137 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3138 stack pointer by ADJUSTMENT. */
3140 static void
3142 {
3157 }
3159 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3160 adjusting it by ADJUSTMENT afterwards. */
3162 static rtx
3164 HOST_WIDE_INT adjustment)
3165 {
3167 {
3176 }
3177 }
3179 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3180 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3181 into CFI_OPS. */
3183 static void
3186 {
3193 {
3197 }
3198 else
3199 {
3204 }
3205 }
3207 /* Generate and return a store pair instruction of mode MODE to store
3208 register REG1 to MEM1 and register REG2 to MEM2. */
3210 static rtx
3212 rtx reg2)
3213 {
3215 {
3224 }
3225 }
3227 /* Generate and regurn a load pair isntruction of mode MODE to load register
3228 REG1 from MEM1 and register REG2 from MEM2. */
3230 static rtx
3232 rtx mem2)
3233 {
3235 {
3244 }
3245 }
3247 /* Return TRUE if return address signing should be enabled for the current
3248 function, otherwise return FALSE. */
3250 bool
3252 {
3253 /* This function should only be called after frame laid out. */
3256 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3257 if it's LR is pushed onto stack. */
3261 }
3263 /* Emit code to save the callee-saved registers from register number START
3264 to LIMIT to the stack at the location starting at offset START_OFFSET,
3265 skipping any write-back candidates if SKIP_WB is true. */
3267 static void
3270 {
3278 {
3280 HOST_WIDE_INT offset;
3293 offset));
3302 {
3304 rtx mem2;
3308 offset));
3310 reg2));
3312 /* The first part of a frame-related parallel insn is
3313 always assumed to be relevant to the frame
3314 calculations; subsequent parts, are only
3315 frame-related if explicitly marked. */
3318 }
3319 else
3323 }
3324 }
3326 /* Emit code to restore the callee registers of mode MODE from register
3327 number START up to and including LIMIT. Restore from the stack offset
3328 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3329 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3331 static void
3335 {
3339 HOST_WIDE_INT offset;
3344 {
3365 {
3367 rtx mem2;
3375 }
3376 else
3379 }
3380 }
3384 HOST_WIDE_INT offset)
3385 {
3387 }
3391 {
3395 }
3397 bool
3399 {
3403 }
3405 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3407 static sbitmap
3409 {
3415 /* The registers we need saved to the frame. */
3418 {
3423 /* Check that we can access the stack slot of the register with one
3424 direct load with no adjustments needed. */
3427 }
3429 /* Don't mess with the hard frame pointer. */
3435 /* If aarch64_layout_frame has chosen registers to store/restore with
3436 writeback don't interfere with them to avoid having to output explicit
3437 stack adjustment instructions. */
3447 }
3449 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3451 static sbitmap
3453 {
3461 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3470 }
3472 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3473 Nothing to do for aarch64. */
3475 static void
3477 {
3478 }
3480 /* Return the next set bit in BMP from START onwards. Return the total number
3481 of bits in BMP if no set bit is found at or after START. */
3483 static unsigned int
3485 {
3496 }
3498 /* Do the work for aarch64_emit_prologue_components and
3499 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3500 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3501 for these components or the epilogue sequence. That is, it determines
3502 whether we should emit stores or loads and what kind of CFA notes to attach
3503 to the insns. Otherwise the logic for the two sequences is very
3504 similar. */
3506 static void
3508 {
3510 ? HARD_FRAME_POINTER_REGNUM
3518 {
3519 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3520 so DFmode for the vector registers is enough. */
3532 /* No more registers to handle after REGNO.
3533 Emit a single save/restore and exit. */
3535 {
3540 else
3543 }
3546 /* The next register is not of the same class or its offset is not
3547 mergeable with the current one into a pair. */
3552 {
3557 else
3562 }
3564 /* REGNO2 can be saved/restored in a pair with REGNO. */
3576 else
3581 {
3584 }
3585 else
3586 {
3589 }
3592 }
3593 }
3595 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3597 static void
3599 {
3601 }
3603 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3605 static void
3607 {
3609 }
3611 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3613 static void
3615 {
3619 }
3621 /* AArch64 stack frames generated by this compiler look like:
3623 +-------------------------------+
3624 | |
3625 | incoming stack arguments |
3626 | |
3627 +-------------------------------+
3628 | | <-- incoming stack pointer (aligned)
3629 | callee-allocated save area |
3630 | for register varargs |
3631 | |
3632 +-------------------------------+
3633 | local variables | <-- frame_pointer_rtx
3634 | |
3635 +-------------------------------+
3636 | padding0 | \
3637 +-------------------------------+ |
3638 | callee-saved registers | | frame.saved_regs_size
3639 +-------------------------------+ |
3640 | LR' | |
3641 +-------------------------------+ |
3642 | FP' | / <- hard_frame_pointer_rtx (aligned)
3643 +-------------------------------+
3644 | dynamic allocation |
3645 +-------------------------------+
3646 | padding |
3647 +-------------------------------+
3648 | outgoing stack arguments | <-- arg_pointer
3649 | |
3650 +-------------------------------+
3651 | | <-- stack_pointer_rtx (aligned)
3653 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3654 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3655 unchanged. */
3657 /* Generate the prologue instructions for entry into a function.
3658 Establish the stack frame by decreasing the stack pointer with a
3659 properly calculated size and, if necessary, create a frame record
3660 filled with the values of LR and previous frame pointer. The
3661 current FP is also set up if it is in use. */
3663 void
3665 {
3678 /* Sign return address for functions. */
3680 {
3684 }
3690 {
3692 {
3696 (frame_size
3698 }
3701 }
3709 {
3714 stack_pointer_rtx,
3718 }
3725 }
3727 /* Return TRUE if we can use a simple_return insn.
3729 This function checks whether the callee saved stack is empty, which
3730 means no restore actions are need. The pro_and_epilogue will use
3731 this to check whether shrink-wrapping opt is feasible. */
3733 bool
3735 {
3745 }
3747 /* Generate the epilogue instructions for returning from a function.
3748 This is almost exactly the reverse of the prolog sequence, except
3749 that we need to insert barriers to avoid scheduling loads that read
3750 from a deallocated stack, and we optimize the unwind records by
3751 emitting them all together if possible. */
3752 void
3754 {
3766 /* We need to add memory barrier to prevent read from deallocated stack. */
3770 /* Emit a barrier to prevent loads from a deallocated stack. */
3773 {
3776 }
3778 /* Restore the stack pointer from the frame pointer if it may not
3779 be the same as the stack pointer. */
3781 {
3783 hard_frame_pointer_rtx,
3785 /* If writeback is used when restoring callee-saves, the CFA
3786 is restored on the instruction doing the writeback. */
3788 }
3789 else
3804 {
3805 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3811 }
3816 {
3817 /* Emit delayed restores and reset the CFA to be SP. */
3822 }
3824 /* We prefer to emit the combined return/authenticate instruction RETAA,
3825 however there are three cases in which we must instead emit an explicit
3826 authentication instruction.
3828 1) Sibcalls don't return in a normal way, so if we're about to call one
3829 we must authenticate.
3831 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3832 generating code for !TARGET_ARMV8_3 we can't use it and must
3833 explicitly authenticate.
3835 3) On an eh_return path we make extra stack adjustments to update the
3836 canonical frame address to be the exception handler's CFA. We want
3837 to authenticate using the CFA of the function which calls eh_return.
3838 */
3841 {
3845 }
3847 /* Stack adjustment for exception handler. */
3849 {
3850 /* We need to unwind the stack by the offset computed by
3851 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3852 to be SP; letting the CFA move during this adjustment
3853 is just as correct as retaining the CFA from the body
3854 of the function. Therefore, do nothing special. */
3856 }
3861 }
3863 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3864 normally or return to a previous frame after unwinding.
3866 An EH return uses a single shared return sequence. The epilogue is
3867 exactly like a normal epilogue except that it has an extra input
3868 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3869 that must be applied after the frame has been destroyed. An extra label
3870 is inserted before the epilogue which initializes this register to zero,
3871 and this is the entry point for a normal return.
3873 An actual EH return updates the return address, initializes the stack
3874 adjustment and jumps directly into the epilogue (bypassing the zeroing
3875 of the adjustment). Since the return address is typically saved on the
3876 stack when a function makes a call, the saved LR must be updated outside
3877 the epilogue.
3879 This poses problems as the store is generated well before the epilogue,
3880 so the offset of LR is not known yet. Also optimizations will remove the
3881 store as it appears dead, even after the epilogue is generated (as the
3882 base or offset for loading LR is different in many cases).
3884 To avoid these problems this implementation forces the frame pointer
3885 in eh_return functions so that the location of LR is fixed and known early.
3886 It also marks the store volatile, so no optimization is permitted to
3887 remove the store. */
3888 rtx
3890 {
3894 /* Mark the store volatile, so no optimization is permitted to remove it. */
3897 }
3899 /* Output code to add DELTA to the first argument, and then jump
3900 to FUNCTION. Used for C++ multiple inheritance. */
3901 static void
3903 HOST_WIDE_INT delta,
3904 HOST_WIDE_INT vcall_offset,
3905 tree function)
3906 {
3907 /* The this pointer is always in x0. Note that this differs from
3908 Arm where the this pointer maybe bumped to r1 if r0 is required
3909 to return a pointer to an aggregate. On AArch64 a result value
3910 pointer will be in x8. */
3920 else
3921 {
3930 {
3934 else
3936 }
3940 else
3947 else
3948 {
3950 Pmode);
3952 }
3956 else
3962 }
3964 /* Generate a tail call to the target function. */
3966 {
3969 }
3981 /* Stop pretending to be a post-reload pass. */
3983 }
3985 static bool
3987 {
3992 {
3996 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3997 TLS offsets, not real symbol references. */
4000 }
4002 }
4005 /* Return true if val can be encoded as a 12-bit unsigned immediate with
4006 a left shift of 0 or 12 bits. */
4007 bool
4009 {
4012 );
4013 }
4016 /* Return true if val is an immediate that can be loaded into a
4017 register by a MOVZ instruction. */
4018 static bool
4020 {
4022 {
4026 }
4027 else
4028 {
4029 /* Ignore sign extension. */
4031 }
4034 }
4036 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
4039 {
4045 };
4048 /* Return true if val is a valid bitmask immediate. */
4050 bool
4052 {
4056 /* Check for a single sequence of one bits and return quickly if so.
4057 The special cases of all ones and all zeroes returns false. */
4064 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
4068 /* Invert if the immediate doesn't start with a zero bit - this means we
4069 only need to search for sequences of one bits. */
4073 /* Find the first set bit and set tmp to val with the first sequence of one
4074 bits removed. Return success if there is a single sequence of ones. */
4081 /* Find the next set bit and compute the difference in bit position. */
4086 /* Check the bit position difference is a power of 2, and that the first
4087 sequence of one bits fits within 'bits' bits. */
4091 /* Check the sequence of one bits is repeated 64/bits times. */
4093 }
4095 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
4096 Assumed precondition: VAL_IN Is not zero. */
4098 unsigned HOST_WIDE_INT
4100 {
4107 }
4109 /* Create constant where bits outside of lowest bit set to highest bit set
4110 are set to 1. */
4112 unsigned HOST_WIDE_INT
4114 {
4116 }
4118 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4120 bool
4122 {
4123 scalar_int_mode int_mode;
4136 }
4138 /* Return true if val is an immediate that can be loaded into a
4139 register in a single instruction. */
4140 bool
4142 {
4143 scalar_int_mode int_mode;
4150 }
4152 static bool
4154 {
4162 {
4166 else
4167 /* Avoid generating a 64-bit relocation in ILP32; leave
4168 to aarch64_expand_mov_immediate to handle it properly. */
4170 }
4173 }
4175 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4176 The expansion for a table switch is quite expensive due to the number
4177 of instructions, the table lookup and hard to predict indirect jump.
4178 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4179 set, otherwise use tables for > 16 cases as a tradeoff between size and
4180 performance. When optimizing for size, use the default setting. */
4182 static unsigned int
4184 {
4185 /* Use the specified limit for the number of cases before using jump
4186 tables at higher optimization levels. */
4190 else
4192 }
4194 /* Return true if register REGNO is a valid index register.
4195 STRICT_P is true if REG_OK_STRICT is in effect. */
4197 bool
4199 {
4201 {
4209 }
4211 }
4213 /* Return true if register REGNO is a valid base register for mode MODE.
4214 STRICT_P is true if REG_OK_STRICT is in effect. */
4216 bool
4218 {
4220 {
4228 }
4230 /* The fake registers will be eliminated to either the stack or
4231 hard frame pointer, both of which are usually valid base registers.
4232 Reload deals with the cases where the eliminated form isn't valid. */
4237 }
4239 /* Return true if X is a valid base register for mode MODE.
4240 STRICT_P is true if REG_OK_STRICT is in effect. */
4242 static bool
4244 {
4251 }
4253 /* Return true if address offset is a valid index. If it is, fill in INFO
4254 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4256 static bool
4259 {
4261 rtx index;
4264 /* (reg:P) */
4267 {
4271 }
4272 /* (sign_extend:DI (reg:SI)) */
4277 {
4282 }
4283 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4290 {
4295 }
4296 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4303 {
4308 }
4309 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4316 {
4324 }
4325 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4326 (const_int 0xffffffff<<shift)) */
4333 {
4339 }
4340 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4347 {
4355 }
4356 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4357 (const_int 0xffffffff<<shift)) */
4364 {
4370 }
4371 /* (mult:P (reg:P) (const_int scale)) */
4376 {
4380 }
4381 /* (ashift:P (reg:P) (const_int shift)) */
4386 {
4390 }
4391 else
4404 {
4409 }
4412 }
4414 /* Return true if MODE is one of the modes for which we
4415 support LDP/STP operations. */
4417 static bool
4419 {
4424 }
4426 /* Return true if REGNO is a virtual pointer register, or an eliminable
4427 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4428 include stack_pointer or hard_frame_pointer. */
4429 static bool
4431 {
4436 }
4438 /* Return true if X is a valid address for machine mode MODE. If it is,
4439 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4440 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4442 static bool
4446 {
4450 /* On BE, we use load/store pair for all large int mode load/stores.
4451 TI/TFmode may also use a load/store pair. */
4455 || (BYTES_BIG_ENDIAN
4459 !load_store_pair_p
4463 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4464 REG addressing. */
4470 {
4486 {
4492 }
4497 {
4504 /* TImode and TFmode values are allowed in both pairs of X
4505 registers and individual Q registers. The available
4506 address modes are:
4507 X,X: 7-bit signed scaled offset
4508 Q: 9-bit signed offset
4509 We conservatively require an offset representable in either mode.
4510 When performing the check for pairs of X registers i.e. LDP/STP
4511 pass down DImode since that is the natural size of the LDP/STP
4512 instruction memory accesses. */
4518 /* A 7bit offset check because OImode will emit a ldp/stp
4519 instruction (only big endian will get here).
4520 For ldp/stp instructions, the offset is scaled for the size of a
4521 single element of the pair. */
4525 /* Three 9/12 bit offsets checks because CImode will emit three
4526 ldr/str instructions (only big endian will get here). */
4533 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4534 instructions (only big endian will get here). */
4543 else
4546 }
4549 {
4550 /* Look for base + (scaled/extended) index register. */
4553 {
4556 }
4559 {
4562 }
4563 }
4584 {
4585 HOST_WIDE_INT offset;
4589 /* TImode and TFmode values are allowed in both pairs of X
4590 registers and individual Q registers. The available
4591 address modes are:
4592 X,X: 7-bit signed scaled offset
4593 Q: 9-bit signed offset
4594 We conservatively require an offset representable in either mode.
4595 */
4603 else
4605 }
4611 /* load literal: pc-relative constant pool entry. Only supported
4612 for SI mode or larger. */
4616 {
4624 }
4633 {
4638 {
4639 /* The symbol and offset must be aligned to the access size. */
4646 {
4650 }
4656 else
4665 }
4666 }
4671 }
4672 }
4674 /* Return true if the address X is valid for a PRFM instruction.
4675 STRICT_P is true if we should do strict checking with
4676 aarch64_classify_address. */
4678 bool
4680 {
4683 /* PRFM accepts the same addresses as DImode... */
4688 /* ... except writeback forms. */
4690 }
4692 bool
4694 {
4695 rtx offset;
4699 }
4701 /* Classify the base of symbolic expression X. */
4703 enum aarch64_symbol_type
4705 {
4706 rtx offset;
4710 }
4713 /* Return TRUE if X is a legitimate address for accessing memory in
4714 mode MODE. */
4715 static bool
4717 {
4721 }
4723 /* Return TRUE if X is a legitimate address for accessing memory in
4724 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4725 pair operation. */
4726 bool
4729 {
4733 }
4735 /* Split an out-of-range address displacement into a base and offset.
4736 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4737 to increase opportunities for sharing the base address of different sizes.
4738 Unaligned accesses use the signed 9-bit range, TImode/TFmode use
4739 the intersection of signed scaled 7-bit and signed 9-bit offset. */
4740 static bool
4742 {
4744 HOST_WIDE_INT base;
4750 else
4756 }
4758 /* Return the binary representation of floating point constant VALUE in INTVAL.
4759 If the value cannot be converted, return false without setting INTVAL.
4760 The conversion is done in the given MODE. */
4761 bool
4763 {
4765 /* We make a general exception for 0. */
4767 {
4770 }
4776 /* Only support up to DF mode. */
4788 {
4792 }
4793 else
4798 }
4800 /* Return TRUE if rtx X is an immediate constant that can be moved using a
4801 single MOV(+MOVK) followed by an FMOV. */
4802 bool
4804 {
4809 /* Determine whether it's cheaper to write float constants as
4810 mov/movk pairs over ldr/adrp pairs. */
4816 {
4818 ? SImode
4823 }
4826 }
4828 /* Return TRUE if rtx X is immediate constant 0.0 */
4829 bool
4831 {
4838 }
4840 /* Return TRUE if rtx X is immediate constant that fits in a single
4841 MOVI immediate operation. */
4842 bool
4844 {
4848 machine_mode vmode;
4849 scalar_int_mode imode;
4854 {
4858 /* We make a general exception for 0. */
4863 }
4867 else
4870 /* use a 64 bit mode for everything except for DI/DF mode, where we use
4871 a 128 bit vector mode. */
4878 }
4881 /* Return the fixed registers used for condition codes. */
4883 static bool
4885 {
4889 }
4891 /* This function is used by the call expanders of the machine description.
4892 RESULT is the register in which the result is returned. It's NULL for
4893 "call" and "sibcall".
4894 MEM is the location of the function call.
4895 SIBCALL indicates whether this function call is normal call or sibling call.
4896 It will generate different pattern accordingly. */
4898 void
4900 {
4902 rtvec vec;
4903 machine_mode mode;
4910 /* Decide if we should generate indirect calls by loading the
4911 address of the callee into a register before performing
4912 the branch-and-link. */
4926 else
4933 }
4935 /* Emit call insn with PAT and do aarch64-specific handling. */
4937 void
4939 {
4945 }
4947 machine_mode
4949 {
4950 /* All floating point compares return CCFP if it is an equality
4951 comparison, and CCFPE otherwise. */
4953 {
4955 {
4976 }
4977 }
4979 /* Equality comparisons of short modes against zero can be performed
4980 using the TST instruction with the appropriate bitmask. */
4986 /* Similarly, comparisons of zero_extends from shorter modes can
4987 be performed using an ANDS with an immediate mask. */
5003 /* A compare with a shifted operand. Because of canonicalization,
5004 the comparison will have to be swapped when we emit the assembly
5005 code. */
5013 /* Similarly for a negated operand, but we can only do this for
5014 equalities. */
5021 /* A test for unsigned overflow. */
5028 /* For everything else, return CCmode. */
5030 }
5032 static int
5035 int
5037 {
5044 }
5046 static int
5048 {
5050 {
5054 {
5068 }
5073 {
5085 }
5090 {
5102 }
5107 {
5113 }
5118 {
5122 }
5127 {
5131 }
5136 }
5139 }
5141 bool
5143 HOST_WIDE_INT minval,
5144 HOST_WIDE_INT maxval)
5145 {
5146 HOST_WIDE_INT firstval;
5163 }
5165 bool
5167 {
5169 }
5172 /* N Z C V. */
5173 #define AARCH64_CC_V 1
5174 #define AARCH64_CC_C (1 << 1)
5175 #define AARCH64_CC_Z (1 << 2)
5176 #define AARCH64_CC_N (1 << 3)
5178 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
5180 {
5197 };
5199 /* Print operand X to file F in a target specific manner according to CODE.
5200 The acceptable formatting commands given by CODE are:
5201 'c': An integer or symbol address without a preceding #
5202 sign.
5203 'e': Print the sign/zero-extend size as a character 8->b,
5204 16->h, 32->w.
5205 'p': Prints N such that 2^N == X (X must be power of 2 and
5206 const int).
5207 'P': Print the number of non-zero bits in X (a const_int).
5208 'H': Print the higher numbered register of a pair (TImode)
5209 of regs.
5210 'm': Print a condition (eq, ne, etc).
5211 'M': Same as 'm', but invert condition.
5212 'b/h/s/d/q': Print a scalar FP/SIMD register name.
5213 'S/T/U/V': Print a FP/SIMD register name for a register list.
5214 The register printed is the FP/SIMD register name
5215 of X + 0/1/2/3 for S/T/U/V.
5216 'R': Print a scalar FP/SIMD register name + 1.
5217 'X': Print bottom 16 bits of integer constant in hex.
5218 'w/x': Print a general register name or the zero register
5219 (32-bit or 64-bit).
5220 '0': Print a normal operand, if it's a general register,
5221 then we assume DImode.
5222 'k': Print NZCV for conditional compare instructions.
5223 'A': Output address constant representing the first
5224 argument of X, specifying a relocation offset
5225 if appropriate.
5226 'L': Output constant address specified by X
5227 with a relocation offset if appropriate.
5228 'G': Prints address of X, specifying a PC relative
5229 relocation mode if appropriate.
5230 'y': Output address of LDP or STP - this is used for
5231 some LDP/STPs which don't use a PARALLEL in their
5232 pattern (so the mode needs to be adjusted).
5233 'z': Output address of a typical LDP or STP. */
5235 static void
5237 {
5239 {
5242 {
5254 {
5257 }
5258 /* Fall through. */
5262 }
5266 {
5271 {
5274 }
5277 {
5290 }
5291 }
5295 {
5299 {
5302 }
5305 }
5310 {
5313 }
5320 {
5323 }
5330 {
5332 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
5334 {
5338 }
5341 {
5344 }
5351 }
5360 {
5361 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5363 }
5372 {
5373 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5375 }
5381 {
5382 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5384 }
5390 {
5393 }
5401 {
5404 }
5407 {
5410 }
5413 {
5416 }
5418 /* Fall through */
5422 {
5425 }
5428 {
5449 {
5452 HOST_WIDE_INT_MIN,
5453 HOST_WIDE_INT_MAX));
5455 }
5457 {
5459 }
5460 else
5465 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5466 be getting CONST_DOUBLEs holding integers. */
5469 {
5472 }
5474 {
5475 #define buf_size 20
5483 #undef buf_size
5484 }
5490 }
5498 {
5525 }
5531 {
5566 }
5572 {
5578 }
5583 {
5584 HOST_WIDE_INT cond_code;
5587 {
5590 }
5595 }
5600 {
5605 {
5608 }
5611 /* LDP/STP which uses a single double-width memory operand.
5612 Adjust the mode to appear like a typical LDP/STP.
5613 Currently this is supported for 16-byte accesses only. */
5618 }
5624 }
5625 }
5627 /* Print address 'x' of a memory access with mode 'mode'.
5628 'op' is the context required by aarch64_classify_address. It can either be
5629 MEM for a normal memory access or PARALLEL for LDP/STP. */
5630 static bool
5632 {
5635 /* Check all addresses are Pmode - including ILP32. */
5640 {
5644 else
5653 else
5662 else
5671 else
5678 {
5705 }
5717 }
5720 }
5722 /* Print address 'x' of a LDP/STP with mode 'mode'. */
5723 static bool
5725 {
5727 }
5729 /* Print address 'x' of a memory access with mode 'mode'. */
5730 static void
5732 {
5735 }
5737 bool
5739 {
5746 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5747 referencing instruction, but they are constant offsets, not
5748 symbols. */
5754 {
5756 {
5762 }
5765 }
5768 }
5770 /* Implement REGNO_REG_CLASS. */
5772 enum reg_class
5774 {
5789 }
5791 static rtx
5793 {
5794 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5795 where mask is selected by alignment and size of the offset.
5796 We try to pick as large a range for the offset as possible to
5797 maximize the chance of a CSE. However, for aligned addresses
5798 we limit the range to 4k so that structures with different sized
5799 elements are likely to use the same base. We need to be careful
5800 not to split a CONST for some forms of address expression, otherwise
5801 it will generate sub-optimal code. */
5804 {
5810 {
5814 /* Force any scaling into a temp for CSE. */
5818 /* Let the pointer register be in op0. */
5822 /* If the pointer is virtual or frame related, then we know that
5823 virtual register instantiation or register elimination is going
5824 to apply a second constant. We want the two constants folded
5825 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5827 {
5831 }
5833 /* Otherwise, in order to encourage CSE (and thence loop strength
5834 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5838 }
5840 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5841 HOST_WIDE_INT base_offset;
5844 /* For offsets aren't a multiple of the access size, the limit is
5845 -256...255. */
5847 {
5850 /* BLKmode typically uses LDP of X-registers. */
5853 }
5854 /* Small negative offsets are supported. */
5859 /* Use 12-bit offset by access size. */
5860 else
5864 {
5868 }
5869 }
5872 }
5874 /* Return the reload icode required for a constant pool in mode. */
5875 static enum insn_code
5877 {
5879 {
5915 }
5918 }
5919 static reg_class_t
5921 reg_class_t rclass,
5922 machine_mode mode,
5924 {
5926 /* If we have to disable direct literal pool loads and stores because the
5927 function is too big, then we need a scratch register. */
5932 {
5935 }
5937 /* Without the TARGET_SIMD instructions we cannot move a Q register
5938 to a Q register directly. We need a scratch. */
5942 {
5948 }
5950 /* A TFmode or TImode memory access should be handled via an FP_REGS
5951 because AArch64 has richer addressing modes for LDR/STR instructions
5952 than LDP/STP instructions. */
5961 }
5963 static bool
5965 {
5968 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
5969 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
5973 }
5975 HOST_WIDE_INT
5977 {
5981 {
5988 }
5991 {
5995 }
5998 }
6000 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
6001 previous frame. */
6003 rtx
6005 {
6009 }
6012 static void
6014 {
6016 {
6019 }
6020 else
6021 {
6024 }
6029 }
6031 static void
6033 {
6037 /* Don't need to copy the trailing D-words, we fill those in below. */
6049 /* XXX We should really define a "clear_cache" pattern and use
6050 gen_clear_cache(). */
6055 ptr_mode);
6056 }
6058 static unsigned char
6060 {
6062 {
6070 return
6082 }
6084 }
6086 static reg_class_t
6088 {
6093 {
6099 }
6101 /* Register eliminiation can result in a request for
6102 SP+constant->FP_REGS. We cannot support such operations which
6103 use SP as source and an FP_REG as destination, so reject out
6104 right now. */
6106 {
6109 /* Look through a possible SUBREG introduced by ILP32. */
6115 POINTER_REGS));
6117 }
6120 }
6122 void
6124 {
6126 }
6128 static void
6130 {
6133 else
6134 {
6136 /* While priority is known to be in range [0, 65535], so 18 bytes
6137 would be enough, the compiler might not know that. To avoid
6138 -Wformat-truncation false positive, use a larger size. */
6145 }
6146 }
6148 static void
6150 {
6153 else
6154 {
6156 /* While priority is known to be in range [0, 65535], so 18 bytes
6157 would be enough, the compiler might not know that. To avoid
6158 -Wformat-truncation false positive, use a larger size. */
6165 }
6166 }
6170 {
6176 {
6177 {
6180 },
6181 {
6184 },
6185 {
6188 },
6189 /* We assume that DImode is only generated when not optimizing and
6190 that we don't really need 64-bit address offsets. That would
6191 imply an object file with 8GB of code in a single function! */
6192 {
6195 }
6196 };
6205 /* Need to implement table size reduction, by chaning the code below. */
6215 }
6218 /* Return size in bits of an arithmetic operand which is shifted/scaled and
6219 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
6220 operator. */
6222 int
6224 {
6226 {
6229 {
6233 }
6234 }
6236 }
6238 /* Constant pools are per function only when PC relative
6239 literal loads are true or we are in the large memory
6240 model. */
6244 {
6247 }
6249 static bool
6251 {
6252 /* Fixme:: In an ideal world this would work similar
6253 to the logic in aarch64_select_rtx_section but this
6254 breaks bootstrap in gcc go. For now we workaround
6255 this by returning false here. */
6257 }
6259 /* Select appropriate section for constants depending
6260 on where we place literal pools. */
6264 rtx x,
6266 {
6271 }
6273 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
6274 void
6276 HOST_WIDE_INT offset)
6277 {
6278 /* When using per-function literal pools, we must ensure that any code
6279 section is aligned to the minimal instruction length, lest we get
6280 errors from the assembler re "unaligned instructions". */
6283 }
6285 /* Costs. */
6287 /* Helper function for rtx cost calculation. Strip a shift expression
6288 from X. Returns the inner operand if successful, or the original
6289 expression on failure. */
6290 static rtx
6292 {
6295 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
6296 we can convert both to ROR during final output. */
6311 }
6313 /* Helper function for rtx cost calculation. Strip an extend
6314 expression from X. Returns the inner operand if successful, or the
6315 original expression on failure. We deal with a number of possible
6316 canonicalization variations here. If STRIP_SHIFT is true, then
6317 we can strip off a shift also. */
6318 static rtx
6320 {
6321 scalar_int_mode mode;
6327 /* Zero and sign extraction of a widened value. */
6335 /* It can also be represented (for zero-extend) as an AND with an
6336 immediate. */
6345 /* Now handle extended register, as this may also have an optional
6346 left shift by 1..4. */
6361 }
6363 /* Return true iff CODE is a shift supported in combination
6364 with arithmetic instructions. */
6366 static bool
6368 {
6370 }
6373 /* Return true iff X is a cheap shift without a sign extend. */
6375 static bool
6377 {
6403 }
6405 /* Helper function for rtx cost calculation. Calculate the cost of
6406 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6407 Return the calculated cost of the expression, recursing manually in to
6408 operands where needed. */
6410 static int
6412 {
6428 /* Integer multiply/fma. */
6430 {
6431 /* The multiply will be canonicalized as a shift, cost it as such. */
6435 {
6439 {
6441 {
6442 /* If the shift is considered cheap,
6443 then don't add any cost. */
6445 ;
6447 /* ARITH + shift-by-register. */
6450 /* ARITH + extended register. We don't have a cost field
6451 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6453 else
6454 /* ARITH + shift-by-immediate. */
6456 }
6457 else
6458 /* LSL (immediate). */
6461 }
6462 /* Strip extends as we will have costed them in the case above. */
6469 }
6471 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6472 compound and let the below cases handle it. After all, MNEG is a
6473 special-case alias of MSUB. */
6475 {
6478 }
6480 /* Integer multiplies or FMAs have zero/sign extending variants. */
6485 {
6490 {
6492 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6494 else
6495 /* MUL/SMULL/UMULL. */
6497 }
6500 }
6502 /* This is either an integer multiply or a MADD. In both cases
6503 we want to recurse and cost the operands. */
6508 {
6510 /* MADD/MSUB. */
6512 else
6513 /* MUL. */
6515 }
6518 }
6519 else
6520 {
6522 {
6523 /* Floating-point FMA/FMUL can also support negations of the
6524 operands, unless the rounding mode is upward or downward in
6525 which case FNMUL is different than FMUL with operand negation. */
6529 {
6534 }
6537 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6539 else
6540 /* FMUL/FNMUL. */
6542 }
6547 }
6548 }
6550 static int
6552 machine_mode mode,
6553 addr_space_t as ATTRIBUTE_UNUSED,
6555 {
6563 {
6565 {
6566 /* This is a CONST or SYMBOL ref which will be split
6567 in a different way depending on the code model in use.
6568 Cost it through the generic infrastructure. */
6570 /* Divide through by the cost of one instruction to
6571 bring it to the same units as the address costs. */
6573 /* The cost is then the cost of preparing the address,
6574 followed by an immediate (possibly 0) offset. */
6576 }
6577 else
6578 {
6579 /* This is most likely a jump table from a case
6580 statement. */
6582 }
6583 }
6586 {
6598 else
6617 }
6621 {
6622 /* For the sake of calculating the cost of the shifted register
6623 component, we can treat same sized modes in the same way. */
6625 {
6638 /* We can't tell, or this is a 128-bit vector. */
6642 }
6643 }
6646 }
6648 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6649 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6650 to be taken. */
6652 int
6654 {
6655 /* When optimizing for speed, use the cost of unpredictable branches. */
6661 else
6663 }
6665 /* Return true if the RTX X in mode MODE is a zero or sign extract
6666 usable in an ADD or SUB (extended register) instruction. */
6667 static bool
6669 {
6670 /* Catch add with a sign extract.
6671 This is add_<optab><mode>_multp2. */
6674 {
6685 op1))
6686 {
6688 }
6689 }
6690 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6691 No shift. */
6697 }
6699 static bool
6701 {
6703 {
6715 }
6716 }
6718 /* Return true iff X is an rtx that will match an extr instruction
6719 i.e. as described in the *extr<mode>5_insn family of patterns.
6720 OP0 and OP1 will be set to the operands of the shifts involved
6721 on success and will be NULL_RTX otherwise. */
6723 static bool
6725 {
6727 scalar_int_mode mode;
6742 {
6743 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6755 {
6759 }
6760 }
6763 }
6765 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6766 storing it in *COST. Result is true if the total cost of the operation
6767 has now been calculated. */
6768 static bool
6770 {
6771 rtx inner;
6772 rtx comparator;
6776 {
6780 }
6781 else
6782 {
6786 }
6789 {
6790 /* Conditional branch. */
6793 else
6794 {
6796 {
6798 {
6799 /* TBZ/TBNZ/CBZ/CBNZ. */
6801 /* TBZ/TBNZ. */
6804 else
6805 /* CBZ/CBNZ. */
6809 }
6810 }
6812 {
6813 /* TBZ/TBNZ. */
6816 }
6817 }
6818 }
6820 {
6821 /* CCMP. */
6823 {
6824 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6828 {
6835 else
6837 }
6839 }
6841 /* It's a conditional operation based on the status flags,
6842 so it must be some flavor of CSEL. */
6844 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6850 {
6851 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6854 }
6859 }
6861 /* We don't know what this is, cost all operands. */
6863 }
6865 /* Check whether X is a bitfield operation of the form shift + extend that
6866 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6867 operand to which the bitfield operation is applied. Otherwise return
6868 NULL_RTX. */
6870 static rtx
6872 {
6886 {
6904 }
6907 }
6909 /* Return true if the mask and a shift amount from an RTX of the form
6910 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6911 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6913 bool
6915 rtx shft_amnt)
6916 {
6921 }
6923 /* Calculate the cost of calculating X, storing it in *COST. Result
6924 is true if the total cost of the operation has now been calculated. */
6925 static bool
6928 {
6933 scalar_int_mode int_mode;
6935 /* By default, assume that everything has equivalent cost to the
6936 cheapest instruction. Any additional costs are applied as a delta
6937 above this default. */
6941 {
6943 /* The cost depends entirely on the operands to SET. */
6949 {
6952 {
6966 }
6975 /* Fall through. */
6977 /* The cost is one per vector-register copied. */
6979 {
6982 }
6983 /* const0_rtx is in general free, but we will use an
6984 instruction to set a register to 0. */
6986 {
6987 /* The cost is 1 per register copied. */
6990 }
6991 else
6992 /* Cost is just the cost of the RHS of the set. */
6998 /* Bit-field insertion. Strip any redundant widening of
6999 the RHS to meet the width of the target. */
7010 {
7011 /* MOV immediate is assumed to always be cheap. */
7013 }
7014 else
7015 {
7016 /* BFM. */
7020 }
7025 /* We can't make sense of this, assume default cost. */
7028 }
7032 /* If an instruction can incorporate a constant within the
7033 instruction, the instruction's expression avoids calling
7034 rtx_cost() on the constant. If rtx_cost() is called on a
7035 constant, then it is usually because the constant must be
7036 moved into a register by one or more instructions.
7038 The exception is constant 0, which can be expressed
7039 as XZR/WZR and is therefore free. The exception to this is
7040 if we have (set (reg) (const0_rtx)) in which case we must cost
7041 the move. However, we can catch that when we cost the SET, so
7042 we don't need to consider that here. */
7045 else
7046 {
7047 /* To an approximation, building any other constant is
7048 proportionally expensive to the number of instructions
7049 required to build that constant. This is true whether we
7050 are compiling for SPEED or otherwise. */
7055 }
7060 /* First determine number of instructions to do the move
7061 as an integer constant. */
7065 {
7071 ? SImode
7077 }
7080 {
7081 /* mov[df,sf]_aarch64. */
7083 /* FMOV (scalar immediate). */
7086 {
7087 /* This will be a load from memory. */
7090 else
7092 }
7093 else
7094 /* Otherwise this is +0.0. We get this using MOVI d0, #0
7095 or MOV v0.s[0], wzr - neither of which are modeled by the
7096 cost tables. Just use the default cost. */
7097 {
7098 }
7099 }
7105 {
7106 /* For loads we want the base cost of a load, plus an
7107 approximation for the additional cost of the addressing
7108 mode. */
7122 }
7130 {
7132 {
7133 /* FNEG. */
7135 }
7137 }
7140 {
7143 {
7144 /* CSETM. */
7147 }
7149 /* Cost this as SUB wzr, X. */
7153 }
7156 {
7157 /* Support (neg(fma...)) as a single instruction only if
7158 sign of zeros is unimportant. This matches the decision
7159 making in aarch64.md. */
7161 {
7162 /* FNMADD. */
7165 }
7167 {
7168 /* FNMUL. */
7171 }
7173 /* FNEG. */
7176 }
7183 {
7186 else
7188 }
7198 {
7202 }
7205 {
7206 /* TODO: A write to the CC flags possibly costs extra, this
7207 needs encoding in the cost tables. */
7210 /* ANDS. */
7212 {
7215 }
7218 {
7219 /* ADDS (and CMN alias). */
7222 }
7225 {
7226 /* SUBS. */
7229 }
7234 {
7235 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
7236 Handle it here directly rather than going to cost_logic
7237 since we know the immediate generated for the TST is valid
7238 so we can avoid creating an intermediate rtx for it only
7239 for costing purposes. */
7246 }
7249 {
7250 /* CMN. */
7257 }
7259 /* CMP.
7261 Compare can freely swap the order of operands, and
7262 canonicalization puts the more complex operation first.
7263 But the integer MINUS logic expects the shift/extend
7264 operation in op1. */
7267 {
7270 }
7272 }
7275 {
7276 /* FCMP. */
7281 {
7283 /* FCMP supports constant 0.0 for no extra cost. */
7285 }
7287 }
7290 {
7291 /* Vector compare. */
7296 {
7297 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
7298 cost. */
7300 }
7302 }
7306 {
7310 cost_minus:
7313 /* Detect valid immediates. */
7319 {
7321 /* SUB(S) (immediate). */
7324 }
7326 /* Look for SUB (extended register). */
7329 {
7337 }
7341 /* Cost this as an FMA-alike operation. */
7345 {
7348 speed);
7350 }
7355 {
7357 {
7358 /* Vector SUB. */
7360 }
7362 {
7363 /* SUB(S). */
7365 }
7367 {
7368 /* FSUB. */
7370 }
7371 }
7373 }
7376 {
7377 rtx new_op0;
7382 cost_plus:
7385 {
7386 /* CSINC. */
7390 }
7395 {
7399 /* ADD (immediate). */
7402 }
7406 /* Look for ADD (extended register). */
7409 {
7417 }
7419 /* Strip any extend, leave shifts behind as we will
7420 cost them through mult_cost. */
7425 {
7427 speed);
7429 }
7434 {
7436 {
7437 /* Vector ADD. */
7439 }
7441 {
7442 /* ADD. */
7444 }
7446 {
7447 /* FADD. */
7449 }
7450 }
7452 }
7458 {
7461 else
7463 }
7468 {
7472 {
7475 else
7477 }
7479 }
7482 {
7489 }
7490 /* Fall through. */
7493 cost_logic:
7498 {
7502 }
7510 {
7511 /* This is a UBFM/SBFM. */
7516 }
7519 {
7521 {
7522 /* We have a mask + shift version of a UBFIZ
7523 i.e. the *andim_ashift<mode>_bfiz pattern. */
7527 {
7534 }
7536 {
7537 /* We possibly get the immediate for free, this is not
7538 modelled. */
7545 }
7546 }
7547 else
7548 {
7551 /* Handle ORN, EON, or BIC. */
7557 /* If we had a shift on op0 then this is a logical-shift-
7558 by-register/immediate operation. Otherwise, this is just
7559 a logical operation. */
7561 {
7563 {
7564 /* Shift by immediate. */
7567 else
7569 }
7570 else
7572 }
7574 /* In both cases we want to cost both operands. */
7581 }
7582 }
7590 {
7591 /* Vector NOT. */
7594 }
7596 /* MVN-shifted-reg. */
7598 {
7605 }
7606 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7607 Handle the second form here taking care that 'a' in the above can
7608 be a shift. */
7610 {
7619 {
7622 else
7624 }
7627 }
7628 /* MVN. */
7637 /* If a value is written in SI mode, then zero extended to DI
7638 mode, the operation will in general be free as a write to
7639 a 'w' register implicitly zeroes the upper bits of an 'x'
7640 register. However, if this is
7642 (set (reg) (zero_extend (reg)))
7644 we must cost the explicit register move. */
7648 {
7651 /* If OP_COST is non-zero, then the cost of the zero extend
7652 is effectively the cost of the inner operation. Otherwise
7653 we have a MOV instruction and we take the cost from the MOV
7654 itself. This is true independently of whether we are
7655 optimizing for space or time. */
7660 }
7662 {
7663 /* All loads can zero extend to any size for free. */
7666 }
7670 {
7675 }
7678 {
7680 {
7681 /* UMOV. */
7683 }
7684 else
7685 {
7686 /* We generate an AND instead of UXTB/UXTH. */
7688 }
7689 }
7694 {
7695 /* LDRSH. */
7697 {
7704 }
7706 }
7710 {
7715 }
7718 {
7721 else
7723 }
7731 {
7733 {
7735 {
7736 /* Vector shift (immediate). */
7738 }
7739 else
7740 {
7741 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7742 aliases. */
7744 }
7745 }
7747 /* We can incorporate zero/sign extend for free. */
7754 }
7755 else
7756 {
7758 {
7760 /* Vector shift (register). */
7762 }
7763 else
7764 {
7766 /* LSLV. */
7772 {
7774 /* We already demanded XEXP (op1, 0) to be REG_P, so
7775 don't recurse into it. */
7777 }
7778 }
7780 }
7790 {
7791 /* ASR (immediate) and friends. */
7793 {
7796 else
7798 }
7802 }
7803 else
7804 {
7806 {
7808 /* Vector shift (register). */
7810 }
7811 else
7812 {
7814 /* ASR (register) and friends. */
7820 {
7822 /* We already demanded XEXP (op1, 0) to be REG_P, so
7823 don't recurse into it. */
7825 }
7826 }
7828 }
7834 {
7835 /* LDR. */
7838 }
7841 {
7842 /* ADRP, followed by ADD. */
7846 }
7849 {
7850 /* ADR. */
7853 }
7856 {
7857 /* One extra load instruction, after accessing the GOT. */
7861 }
7866 /* ADRP/ADD (immediate). */
7873 /* UBFX/SBFX. */
7875 {
7878 else
7880 }
7882 /* We can trust that the immediates used will be correct (there
7883 are no by-register forms), so we need only cost op0. */
7889 /* aarch64_rtx_mult_cost always handles recursion to its
7890 operands. */
7894 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7895 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7896 an unconditional negate. This case should only ever be reached through
7897 the set_smod_pow2_cheap check in expmed.c. */
7901 {
7902 /* We expand to 4 instructions. Reset the baseline. */
7910 }
7912 /* Fall-through. */
7915 {
7916 /* Slighly prefer UMOD over SMOD. */
7923 }
7930 {
7934 /* There is no integer SQRT, so only DIV and UDIV can get
7935 here. */
7937 /* Slighly prefer UDIV over SDIV. */
7939 else
7941 }
7967 {
7970 else
7972 }
7974 /* FMSUB, FNMADD, and FNMSUB are free. */
7981 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7982 and the by-element operand as operand 0. */
7986 /* Catch vector-by-element operations. The by-element operand can
7987 either be (vec_duplicate (vec_select (x))) or just
7988 (vec_select (x)), depending on whether we are multiplying by
7989 a vector or a scalar.
7991 Canonicalization is not very good in these cases, FMA4 will put the
7992 by-element operand as operand 0, FNMA4 will have it as operand 1. */
8003 /* If the remaining parameters are not registers,
8004 get the cost to put them into registers. */
8018 {
8020 {
8021 /*Vector truncate. */
8023 }
8024 else
8026 }
8031 {
8033 {
8034 /*Vector conversion. */
8036 }
8037 else
8039 }
8045 /* Strip the rounding part. They will all be implemented
8046 by the fcvt* family of instructions anyway. */
8048 {
8057 }
8060 {
8063 else
8065 }
8067 /* We can combine fmul by a power of 2 followed by a fcvt into a single
8068 fixed-point fcvt. */
8073 {
8077 }
8084 {
8085 /* ABS (vector). */
8088 }
8090 {
8093 /* FABD, which is analogous to FADD. */
8095 {
8102 }
8103 /* Simple FABS is analogous to FNEG. */
8106 }
8107 else
8108 {
8109 /* Integer ABS will either be split to
8110 two arithmetic instructions, or will be an ABS
8111 (scalar), which we don't model. */
8115 }
8121 {
8124 else
8125 {
8126 /* FMAXNM/FMINNM/FMAX/FMIN.
8127 TODO: This may not be accurate for all implementations, but
8128 we do not model this in the cost tables. */
8130 }
8131 }
8135 /* The floating point round to integer frint* instructions. */
8137 {
8142 }
8145 {
8150 }
8155 /* Decompose <su>muldi3_highpart. */
8157 mode == DImode
8158 /* (lshiftrt:TI */
8161 /* (mult:TI */
8163 /* (ANY_EXTEND:TI (reg:DI))
8164 (ANY_EXTEND:TI (reg:DI))) */
8171 /* (const_int 64) */
8174 {
8175 /* UMULH/SMULH. */
8183 }
8185 /* Fall through. */
8188 }
8196 }
8198 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
8199 calculated for X. This cost is stored in *COST. Returns true
8200 if the total cost of X was calculated. */
8201 static bool
8204 {
8209 {
8214 }
8217 }
8219 static int
8222 {
8228 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
8235 /* Moving between GPR and stack cost is the same as GP2GP. */
8240 /* To/From the stack register, we move via the gprs. */
8246 {
8247 /* 128-bit operations on general registers require 2 instructions. */
8255 /* When AdvSIMD instructions are disabled it is not possible to move
8256 a 128-bit value directly between Q registers. This is handled in
8257 secondary reload. A general register is used as a scratch to move
8258 the upper DI value and the lower DI value is moved directly,
8259 hence the cost is the sum of three moves. */
8264 }
8274 }
8276 static int
8278 reg_class_t rclass ATTRIBUTE_UNUSED,
8280 {
8282 }
8284 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
8285 to optimize 1.0/sqrt. */
8287 static bool
8289 {
8291 && flag_unsafe_math_optimizations
8295 }
8297 /* Function to decide when to use the approximate reciprocal square root
8298 builtin. */
8300 static tree
8302 {
8308 }
8312 /* Select reciprocal square root initial estimate insn depending on machine
8313 mode. */
8315 static rsqrte_type
8317 {
8319 {
8326 }
8327 }
8331 /* Select reciprocal square root series step insn depending on machine mode. */
8333 static rsqrts_type
8335 {
8337 {
8344 }
8345 }
8347 /* Emit instruction sequence to compute either the approximate square root
8348 or its approximate reciprocal, depending on the flag RECP, and return
8349 whether the sequence was emitted or not. */
8351 bool
8353 {
8357 {
8360 }
8363 {
8370 || flag_trapping_math
8371 || !flag_unsafe_math_optimizations
8374 }
8375 else
8376 /* Caller assumes we cannot fail. */
8382 /* When calculating the approximate square root, compare the
8383 argument with 0.0 and create a mask. */
8389 /* Estimate the approximate reciprocal square root. */
8393 /* Iterate over the series twice for SF and thrice for DF. */
8396 /* Optionally iterate over the series once less for faster performance
8397 while sacrificing the accuracy. */
8400 iterations--;
8402 /* Iterate over the series to calculate the approximate reciprocal square
8403 root. */
8406 {
8414 }
8417 {
8418 /* Qualify the approximate reciprocal square root when the argument is
8419 0.0 by squashing the intermediary result to 0.0. */
8425 /* Calculate the approximate square root. */
8427 }
8429 /* Finalize the approximation. */
8433 }
8437 /* Select reciprocal initial estimate insn depending on machine mode. */
8439 static recpe_type
8441 {
8443 {
8450 }
8451 }
8455 /* Select reciprocal series step insn depending on machine mode. */
8457 static recps_type
8459 {
8461 {
8468 }
8469 }
8471 /* Emit the instruction sequence to compute the approximation for the division
8472 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8474 bool
8476 {
8487 || flag_trapping_math
8488 || !flag_unsafe_math_optimizations
8496 /* Estimate the approximate reciprocal. */
8500 /* Iterate over the series twice for SF and thrice for DF. */
8503 /* Optionally iterate over the series once less for faster performance,
8504 while sacrificing the accuracy. */
8506 iterations--;
8508 /* Iterate over the series to calculate the approximate reciprocal. */
8511 {
8516 }
8519 {
8520 /* As the approximate reciprocal of DEN is already calculated, only
8521 calculate the approximate division when NUM is not 1.0. */
8524 }
8526 /* Finalize the approximation. */
8529 }
8531 /* Return the number of instructions that can be issued per cycle. */
8532 static int
8534 {
8536 }
8538 static int
8540 {
8544 }
8547 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8548 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8549 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8551 static int
8554 {
8556 }
8559 /* Vectorizer cost model target hooks. */
8561 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8562 static int
8564 tree vectype,
8566 {
8575 {
8626 }
8627 }
8629 /* Implement targetm.vectorize.add_stmt_cost. */
8630 static unsigned
8634 {
8639 {
8644 /* Statements in an inner loop relative to the loop being
8645 vectorized are weighted more heavily. The value here is
8646 arbitrary and could potentially be improved with analysis. */
8652 }
8655 }
8659 /* Parse the TO_PARSE string and put the architecture struct that it
8660 selects into RES and the architectural features into ISA_FLAGS.
8661 Return an aarch64_parse_opt_result describing the parse result.
8662 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8664 static enum aarch64_parse_opt_result
8667 {
8679 else
8686 /* Loop through the list of supported ARCHes to find a match. */
8688 {
8690 {
8694 {
8695 /* TO_PARSE string contains at least one extension. */
8696 enum aarch64_parse_opt_result ext_res
8701 }
8702 /* Extension parsing was successful. Confirm the result
8703 arch and ISA flags. */
8707 }
8708 }
8710 /* ARCH name not found in list. */
8712 }
8714 /* Parse the TO_PARSE string and put the result tuning in RES and the
8715 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8716 describing the parse result. If there is an error parsing, RES and
8717 ISA_FLAGS are left unchanged. */
8719 static enum aarch64_parse_opt_result
8722 {
8734 else
8741 /* Loop through the list of supported CPUs to find a match. */
8743 {
8745 {
8750 {
8751 /* TO_PARSE string contains at least one extension. */
8752 enum aarch64_parse_opt_result ext_res
8757 }
8758 /* Extension parsing was successfull. Confirm the result
8759 cpu and ISA flags. */
8763 }
8764 }
8766 /* CPU name not found in list. */
8768 }
8770 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8771 Return an aarch64_parse_opt_result describing the parse result.
8772 If the parsing fails the RES does not change. */
8774 static enum aarch64_parse_opt_result
8776 {
8782 /* Loop through the list of supported CPUs to find a match. */
8784 {
8786 {
8789 }
8790 }
8792 /* CPU name not found in list. */
8794 }
8796 /* Parse TOKEN, which has length LENGTH to see if it is an option
8797 described in FLAG. If it is, return the index bit for that fusion type.
8798 If not, error (printing OPTION_NAME) and return zero. */
8800 static unsigned int
8805 {
8807 {
8811 }
8815 }
8817 /* Parse OPTION which is a comma-separated list of flags to enable.
8818 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8819 default state we inherit from the CPU tuning structures. OPTION_NAME
8820 gives the top-level option we are parsing in the -moverride string,
8821 for use in error messages. */
8823 static unsigned int
8828 {
8835 {
8838 token_length,
8839 flags,
8840 option_name);
8841 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8842 in the token stream, reset the supported operations. So:
8844 adrp+add.cmp+branch.none.adrp+add
8846 would have the result of turning on only adrp+add fusion. */
8852 }
8854 /* We ended with a comma, print something. */
8856 {
8859 }
8861 /* We still have one more token to parse. */
8864 token_length,
8865 flags,
8866 option_name);
8872 }
8874 /* Support for overriding instruction fusion. */
8876 static void
8879 {
8881 aarch64_fusible_pairs,
8884 }
8886 /* Support for overriding other tuning flags. */
8888 static void
8891 {
8892 tune->extra_tuning_flags
8894 aarch64_tuning_flags,
8897 }
8899 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8900 we understand. If it is, extract the option string and handoff to
8901 the appropriate function. */
8903 void
8907 {
8913 {
8916 }
8918 /* Get the length of the option name. */
8920 /* Skip the '=' to get to the option string. */
8921 option_part++;
8924 {
8926 {
8929 }
8930 }
8934 }
8936 /* A checking mechanism for the implementation of the tls size. */
8938 static void
8940 {
8945 {
8947 /* Both the default and maximum TLS size allowed under tiny is 1M which
8948 needs two instructions to address, so we clamp the size to 24. */
8953 /* The maximum TLS size allowed under small is 4G. */
8958 /* The maximum TLS size allowed under large is 16E.
8959 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8965 }
8968 }
8970 /* Parse STRING looking for options in the format:
8971 string :: option:string
8972 option :: name=substring
8973 name :: {a-z}
8974 substring :: defined by option. */
8976 static void
8979 {
8990 {
8992 /* Make this substring look like a string. */
8996 }
8998 /* One last option to parse. */
9001 }
9004 static void
9006 {
9007 /* PR 70044: We have to be careful about being called multiple times for the
9008 same function. This means all changes should be repeatable. */
9010 /* If the frame pointer is enabled, set it to a special value that behaves
9011 similar to frame pointer omission. If we don't do this all leaf functions
9012 will get a frame pointer even if flag_omit_leaf_frame_pointer is set.
9013 If flag_omit_frame_pointer has this special value, we must force the
9014 frame pointer if not in a leaf function. We also need to force it in a
9015 leaf function if flag_omit_frame_pointer is not set or if LR is used. */
9019 /* If not optimizing for size, set the default
9020 alignment to what the target wants. */
9022 {
9029 }
9031 /* We default to no pc-relative literal loads. */
9035 /* If -mpc-relative-literal-loads is set on the command line, this
9036 implies that the user asked for PC relative literal loads. */
9040 /* In the tiny memory model it makes no sense to disallow PC relative
9041 literal pool loads. */
9046 /* When enabling the lower precision Newton series for the square root, also
9047 enable it for the reciprocal square root, since the latter is an
9048 intermediary step for the former. */
9051 }
9053 /* 'Unpack' up the internal tuning structs and update the options
9054 in OPTS. The caller must have set up selected_tune and selected_arch
9055 as all the other target-specific codegen decisions are
9056 derived from them. */
9058 void
9060 {
9063 /* Make a copy of the tuning parameters attached to the core, which
9064 we may later overwrite. */
9072 /* This target defaults to strict volatile bitfields. */
9081 {
9093 }
9095 /* We don't mind passing in global_options_set here as we don't use
9096 the *options_set structs anyway. */
9098 queue_depth,
9102 /* Set up parameters to be used in prefetching algorithm. Do not
9103 override the defaults unless we are tuning for a core we have
9104 researched values for. */
9126 /* Use the alternative scheduling-pressure algorithm by default. */
9131 /* Enable sw prefetching at specified optimization level for
9132 CPUS that have prefetch. Lower optimization level threshold by 1
9133 when profiling is enabled. */
9141 }
9143 /* Print a hint with a suggestion for a core or architecture name that
9144 most closely resembles what the user passed in STR. ARCH is true if
9145 the user is asking for an architecture name. ARCH is false if the user
9146 is asking for a core name. */
9148 static void
9150 {
9161 }
9163 /* Print a hint with a suggestion for a core name that most closely resembles
9164 what the user passed in STR. */
9168 {
9170 }
9172 /* Print a hint with a suggestion for an architecture name that most closely
9173 resembles what the user passed in STR. */
9177 {
9179 }
9181 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
9182 specified in STR and throw errors if appropriate. Put the results if
9183 they are valid in RES and ISA_FLAGS. Return whether the option is
9184 valid. */
9186 static bool
9189 {
9190 enum aarch64_parse_opt_result parse_res
9197 {
9210 }
9213 }
9215 /* Validate a command-line -march option. Parse the arch and extensions
9216 (if any) specified in STR and throw errors if appropriate. Put the
9217 results, if they are valid, in RES and ISA_FLAGS. Return whether the
9218 option is valid. */
9220 static bool
9223 {
9224 enum aarch64_parse_opt_result parse_res
9231 {
9244 }
9247 }
9249 /* Validate a command-line -mtune option. Parse the cpu
9250 specified in STR and throw errors if appropriate. Put the
9251 result, if it is valid, in RES. Return whether the option is
9252 valid. */
9254 static bool
9256 {
9257 enum aarch64_parse_opt_result parse_res
9264 {
9274 }
9276 }
9278 /* Return the CPU corresponding to the enum CPU.
9279 If it doesn't specify a cpu, return the default. */
9283 {
9287 /* The & 0x3f is to extract the bottom 6 bits that encode the
9288 default cpu as selected by the --with-cpu GCC configure option
9289 in config.gcc.
9290 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
9291 flags mechanism should be reworked to make it more sane. */
9293 }
9295 /* Return the architecture corresponding to the enum ARCH.
9296 If it doesn't specify a valid architecture, return the default. */
9300 {
9307 }
9309 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
9310 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
9311 tuning structs. In particular it must set selected_tune and
9312 aarch64_isa_flags that define the available ISA features and tuning
9313 decisions. It must also set selected_arch as this will be used to
9314 output the .arch asm tags for each function. */
9316 static void
9318 {
9331 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
9332 If either of -march or -mtune is given, they override their
9333 respective component of -mcpu. */
9345 /* If the user did not specify a processor, choose the default
9346 one for them. This will be the CPU set during configuration using
9347 --with-cpu, otherwise it is "generic". */
9349 {
9351 {
9355 }
9356 else
9357 {
9358 /* Get default configure-time CPU. */
9361 }
9365 }
9366 /* If both -mcpu and -march are specified check that they are architecturally
9367 compatible, warn if they're not and prefer the -march ISA flags. */
9369 {
9371 {
9375 }
9380 }
9381 else
9382 {
9383 /* -mcpu but no -march. */
9390 }
9392 /* Set the arch as well as we will need it when outputing
9393 the .arch directive in assembly. */
9395 {
9398 }
9403 #ifndef HAVE_AS_MABI_OPTION
9404 /* The compiler may have been configured with 2.23.* binutils, which does
9405 not have support for ILP32. */
9408 #endif
9413 /* Make sure we properly set up the explicit options. */
9424 /* Save these options as the default ones in case we push and pop them later
9425 while processing functions with potential target attributes. */
9426 target_option_default_node = target_option_current_node
9428 }
9430 /* Implement targetm.override_options_after_change. */
9432 static void
9434 {
9436 }
9440 {
9444 }
9446 void
9448 {
9450 }
9452 /* A checking mechanism for the implementation of the various code models. */
9453 static void
9455 {
9457 {
9459 {
9464 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9466 ? AARCH64_CMODEL_SMALL_PIC
9468 #else
9470 #endif
9478 }
9479 }
9480 else
9482 }
9484 /* Implement TARGET_OPTION_SAVE. */
9486 static void
9488 {
9490 }
9492 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9493 using the information saved in PTR. */
9495 static void
9497 {
9505 }
9507 /* Implement TARGET_OPTION_PRINT. */
9509 static void
9511 {
9522 }
9526 void
9528 {
9530 }
9532 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9533 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9534 make sure optab availability predicates are recomputed when necessary. */
9536 void
9538 {
9543 else
9545 }
9547 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9548 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9549 of the function, if such exists. This function may be called multiple
9550 times on a single function so use aarch64_previous_fndecl to avoid
9551 setting up identical state. */
9553 static void
9555 {
9559 tree old_tree = (aarch64_previous_fndecl
9565 /* If current function has no attributes but the previous one did,
9566 use the default node. */
9570 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9571 the default have been handled by aarch64_save_restore_target_globals from
9572 aarch64_pragma_target_parse. */
9578 /* First set the target options. */
9582 }
9584 /* Enum describing the various ways we can handle attributes.
9585 In many cases we can reuse the generic option handling machinery. */
9587 enum aarch64_attr_opt_type
9588 {
9592 aarch64_attr_custom /* Attribute requires a custom handling function. */
9593 };
9595 /* All the information needed to handle a target attribute.
9596 NAME is the name of the attribute.
9597 ATTR_TYPE specifies the type of behavior of the attribute as described
9598 in the definition of enum aarch64_attr_opt_type.
9599 ALLOW_NEG is true if the attribute supports a "no-" form.
9600 HANDLER is the function that takes the attribute string as an argument
9601 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
9602 OPT_NUM is the enum specifying the option that the attribute modifies.
9603 This is needed for attributes that mirror the behavior of a command-line
9604 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9605 aarch64_attr_enum. */
9607 struct aarch64_attribute_info
9608 {
9614 };
9616 /* Handle the ARCH_STR argument to the arch= target attribute. */
9618 static bool
9620 {
9622 enum aarch64_parse_opt_result parse_res
9626 {
9631 }
9634 {
9647 }
9650 }
9652 /* Handle the argument CPU_STR to the cpu= target attribute. */
9654 static bool
9656 {
9658 enum aarch64_parse_opt_result parse_res
9662 {
9670 }
9673 {
9686 }
9689 }
9691 /* Handle the argument STR to the tune= target attribute. */
9693 static bool
9695 {
9697 enum aarch64_parse_opt_result parse_res
9701 {
9706 }
9709 {
9716 }
9719 }
9721 /* Parse an architecture extensions target attribute string specified in STR.
9722 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9723 if successful. Update aarch64_isa_flags to reflect the ISA features
9724 modified. */
9726 static bool
9728 {
9732 /* We allow "+nothing" in the beginning to clear out all architectural
9733 features if the user wants to handpick specific features. */
9735 {
9738 }
9743 {
9746 }
9749 {
9760 }
9763 }
9765 /* The target attributes that we support. On top of these we also support just
9766 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9767 handled explicitly in aarch64_process_one_target_attr. */
9770 {
9772 OPT_mgeneral_regs_only },
9774 OPT_mfix_cortex_a53_835769 },
9776 OPT_mfix_cortex_a53_843419 },
9780 OPT_momit_leaf_frame_pointer },
9783 OPT_march_ },
9786 OPT_mtune_ },
9788 OPT_msign_return_address_ },
9790 };
9792 /* Parse ARG_STR which contains the definition of one target attribute.
9793 Show appropriate errors if any or return true if the attribute is valid. */
9795 static bool
9797 {
9803 {
9806 }
9811 /* Skip leading whitespace. */
9813 str_to_check++;
9815 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9816 It is easier to detect and handle it explicitly here rather than going
9817 through the machinery for the rest of the target attributes in this
9818 function. */
9823 {
9826 }
9829 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9830 and point ARG to "foo". */
9832 {
9834 arg++;
9835 }
9839 {
9840 /* If the names don't match up, or the user has given an argument
9841 to an attribute that doesn't accept one, or didn't give an argument
9842 to an attribute that expects one, fail to match. */
9851 {
9854 }
9856 /* If the name matches but the attribute does not allow "no-" versions
9857 then we can't match. */
9859 {
9862 }
9865 {
9866 /* Has a custom handler registered.
9867 For example, cpu=, arch=, tune=. */
9874 /* Either set or unset a boolean option. */
9876 {
9884 }
9885 /* Set or unset a bit in the target_flags. aarch64_handle_option
9886 should know what mask to apply given the option number. */
9888 {
9890 /* We only need to specify the option number.
9891 aarch64_handle_option will know which mask to apply. */
9897 }
9898 /* Use the option setting machinery to set an option to an enum. */
9900 {
9907 {
9910 global_dc);
9911 }
9912 else
9913 {
9915 }
9917 }
9920 }
9921 }
9923 /* If we reached here we either have found an attribute and validated
9924 it or didn't match any. If we matched an attribute but its arguments
9925 were malformed we will have returned false already. */
9927 }
9929 /* Count how many times the character C appears in
9930 NULL-terminated string STR. */
9932 static unsigned int
9934 {
9937 {
9939 res++;
9941 str++;
9942 }
9945 }
9947 /* Parse the tree in ARGS that contains the target attribute information
9948 and update the global target options space. */
9950 bool
9952 {
9954 {
9955 do
9956 {
9959 {
9962 }
9967 }
9970 {
9973 }
9980 {
9983 }
9985 /* Used to catch empty spaces between commas i.e.
9986 attribute ((target ("attr1,,attr2"))). */
9989 /* Handle multiple target attributes separated by ','. */
9994 {
9995 num_attrs++;
9997 {
10000 }
10003 }
10006 {
10009 }
10012 }
10014 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
10015 process attribute ((target ("..."))). */
10017 static bool
10019 {
10022 tree old_optimize;
10026 /* If what we're processing is the current pragma string then the
10027 target option node is already stored in target_option_current_node
10028 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
10029 having to re-parse the string. This is especially useful to keep
10030 arm_neon.h compile times down since that header contains a lot
10031 of intrinsics enclosed in pragmas. */
10033 {
10036 }
10042 /* If the function changed the optimization levels as well as setting
10043 target options, start with the optimizations specified. */
10048 /* Save the current target options to restore at the end. */
10051 /* If fndecl already has some target attributes applied to it, unpack
10052 them so that we add this attribute on top of them, rather than
10053 overwriting them. */
10055 {
10061 }
10062 else
10068 /* Set up any additional state. */
10070 {
10072 /* Initialize SIMD builtins if we haven't already.
10073 Set current_target_pragma to NULL for the duration so that
10074 the builtin initialization code doesn't try to tag the functions
10075 being built with the attributes specified by any current pragma, thus
10076 going into an infinite recursion. */
10078 {
10083 }
10085 }
10086 else
10092 {
10097 }
10105 }
10107 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
10108 tri-bool options (yes, no, don't care) and the default value is
10109 DEF, determine whether to reject inlining. */
10111 static bool
10114 {
10115 /* If the callee doesn't care, always allow inlining. */
10119 /* If the caller doesn't care, always allow inlining. */
10123 /* Otherwise, allow inlining if either the callee and caller values
10124 agree, or if the callee is using the default value. */
10126 }
10128 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
10129 to inline CALLEE into CALLER based on target-specific info.
10130 Make sure that the caller and callee have compatible architectural
10131 features. Then go through the other possible target attributes
10132 and see if they can block inlining. Try not to reject always_inline
10133 callees unless they are incompatible architecturally. */
10135 static bool
10137 {
10141 /* If callee has no option attributes, then it is ok to inline. */
10152 /* Callee's ISA flags should be a subset of the caller's. */
10157 /* Allow non-strict aligned functions inlining into strict
10158 aligned ones. */
10168 /* If the architectural features match up and the callee is always_inline
10169 then the other attributes don't matter. */
10181 /* Honour explicit requests to workaround errata. */
10194 /* If the user explicitly specified -momit-leaf-frame-pointer for the
10195 caller and calle and they don't match up, reject inlining. */
10202 /* If the callee has specific tuning overrides, respect them. */
10207 /* If the user specified tuning override strings for the
10208 caller and callee and they don't match up, reject inlining.
10209 We just do a string compare here, we don't analyze the meaning
10210 of the string, as it would be too costly for little gain. */
10218 }
10220 /* Return true if SYMBOL_REF X binds locally. */
10222 static bool
10224 {
10228 }
10230 /* Return true if SYMBOL_REF X is thread local */
10231 static bool
10233 {
10241 }
10243 /* Classify a TLS symbol into one of the TLS kinds. */
10244 enum aarch64_symbol_type
10246 {
10250 {
10257 {
10263 }
10274 else
10283 }
10284 }
10286 /* Return the method that should be used to access SYMBOL_REF or
10287 LABEL_REF X. */
10289 enum aarch64_symbol_type
10291 {
10293 {
10295 {
10310 }
10311 }
10314 {
10319 {
10321 /* When we retrieve symbol + offset address, we have to make sure
10322 the offset does not cause overflow of the final address. But
10323 we have no way of knowing the address of symbol at compile time
10324 so we can't accurately say if the distance between the PC and
10325 symbol + offset is outside the addressible range of +/-1M in the
10326 TINY code model. So we rely on images not being greater than
10327 1M and cap the offset at 1M and anything beyond 1M will have to
10328 be loaded using an alternative mechanism. Furthermore if the
10329 symbol is a weak reference to something that isn't known to
10330 resolve to a symbol in this module, then force to memory. */
10338 /* Same reasoning as the tiny code model, but the offset cap here is
10339 4G. */
10360 /* This is alright even in PIC code as the constant
10361 pool reference is always PC relative and within
10362 the same translation unit. */
10365 else
10370 }
10371 }
10373 /* By default push everything into the constant pool. */
10375 }
10377 bool
10379 {
10381 }
10383 bool
10385 {
10393 }
10395 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
10396 that should be rematerialized rather than spilled. */
10398 static bool
10400 {
10401 /* Support CSE and rematerialization of common constants. */
10405 /* Do not allow vector struct mode constants. We could support
10406 0 and -1 easily, but they need support in aarch64-simd.md. */
10410 /* Do not allow wide int constants - this requires support in movti. */
10414 /* Do not allow const (plus (anchor_symbol, const_int)). */
10416 {
10417 rtx offset;
10423 }
10428 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
10429 so spilling them is better than rematerialization. */
10433 /* Label references are always constant. */
10438 }
10440 rtx
10442 {
10448 /* Can return in any reg. */
10451 }
10453 /* On AAPCS systems, this is the "struct __va_list". */
10456 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10457 Return the type to use as __builtin_va_list.
10459 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10461 struct __va_list
10462 {
10463 void *__stack;
10464 void *__gr_top;
10465 void *__vr_top;
10466 int __gr_offs;
10467 int __vr_offs;
10468 }; */
10470 static tree
10472 {
10473 tree va_list_name;
10476 /* Create the type. */
10478 /* Give it the required name. */
10480 TYPE_DECL,
10482 va_list_type);
10487 /* Create the fields. */
10490 ptr_type_node);
10493 ptr_type_node);
10496 ptr_type_node);
10499 integer_type_node);
10502 integer_type_node);
10504 /* Tell tree-stdarg pass about our internal offset fields.
10505 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10506 purpose to identify whether the code is updating va_list internal
10507 offset fields through irregular way. */
10529 /* Compute its layout. */
10533 }
10535 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10536 static void
10538 {
10542 tree t;
10556 {
10559 }
10568 NULL_TREE);
10570 NULL_TREE);
10572 NULL_TREE);
10574 NULL_TREE);
10576 NULL_TREE);
10578 /* Emit code to initialize STACK, which points to the next varargs stack
10579 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10580 by named arguments. STACK is 8-byte aligned. */
10587 /* Emit code to initialize GRTOP, the top of the GR save area.
10588 virtual_incoming_args_rtx should have been 16 byte aligned. */
10593 /* Emit code to initialize VRTOP, the top of the VR save area.
10594 This address is gr_save_area_bytes below GRTOP, rounded
10595 down to the next 16-byte boundary. */
10605 /* Emit code to initialize GROFF, the offset from GRTOP of the
10606 next GPR argument. */
10611 /* Likewise emit code to initialize VROFF, the offset from FTOP
10612 of the next VR argument. */
10616 }
10618 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10620 static tree
10623 {
10624 tree addr;
10630 machine_mode mode;
10657 type,
10661 {
10662 /* TYPE passed in fp/simd registers. */
10674 {
10677 }
10680 {
10682 }
10683 }
10684 else
10685 {
10686 /* TYPE passed in general registers. */
10699 {
10701 }
10702 }
10704 /* Get a local temporary for the field value. */
10707 /* Emit code to branch if off >= 0. */
10713 {
10714 /* Emit: offs = (offs + 15) & -16. */
10720 }
10721 else
10724 /* Update ap.__[g|v]r_offs */
10729 /* String up. */
10733 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10738 /* String up: make sure the assignment happens before the use. */
10742 /* Prepare the trees handling the argument that is passed on the stack;
10743 the top level node will store in ON_STACK. */
10746 {
10747 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10755 }
10756 else
10758 /* Advance ap.__stack */
10766 /* String up roundup and advance. */
10769 /* String up with arg */
10771 /* Big-endianness related address adjustment. */
10774 {
10778 }
10783 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10793 {
10794 /* type ha; // treat as "struct {ftype field[n];}"
10795 ... [computing offs]
10796 for (i = 0; i <nregs; ++i, offs += 16)
10797 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10798 return ha; */
10802 /* Declare a local variable. */
10806 /* Establish the base type. */
10808 {
10827 {
10831 }
10835 }
10837 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10845 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10847 {
10857 }
10861 }
10871 }
10873 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10875 static void
10879 {
10881 CUMULATIVE_ARGS local_cum;
10885 /* The caller has advanced CUM up to, but not beyond, the last named
10886 argument. Advance a local copy of CUM past the last "real" named
10887 argument, to find out how many registers are left over. */
10891 /* Found out how many registers we need to save.
10892 Honor tree-stdvar analysis results. */
10901 {
10904 }
10907 {
10909 {
10912 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10920 }
10922 {
10923 /* We can't use move_block_from_reg, because it will use
10924 the wrong mode, storing D regs only. */
10928 /* Set OFF to the offset from virtual_incoming_args_rtx of
10929 the first vector register. The VR save area lies below
10930 the GR one, and is aligned to 16 bytes. */
10937 {
10945 }
10946 }
10947 }
10949 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10950 any complication of having crtl->args.pretend_args_size changed. */
10955 }
10957 static void
10959 {
10962 {
10964 {
10967 }
10968 }
10969 }
10971 /* Walk down the type tree of TYPE counting consecutive base elements.
10972 If *MODEP is VOIDmode, then set it to the first valid floating point
10973 type. If a non-floating point type is found, or if a floating point
10974 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10975 otherwise return the count in the sub-tree. */
10976 static int
10978 {
10979 machine_mode mode;
10980 HOST_WIDE_INT size;
10983 {
11013 /* Use V2SImode and V4SImode as representatives of all 64-bit
11014 and 128-bit vector types. */
11017 {
11026 }
11031 /* Vector modes are considered to be opaque: two vectors are
11032 equivalent for the purposes of being homogeneous aggregates
11033 if they are the same size. */
11040 {
11044 /* Can't handle incomplete types nor sizes that are not
11045 fixed. */
11052 || !index
11063 /* There must be no padding. */
11069 }
11072 {
11075 tree field;
11077 /* Can't handle incomplete types nor sizes that are not
11078 fixed. */
11084 {
11092 }
11094 /* There must be no padding. */
11100 }
11104 {
11105 /* These aren't very interesting except in a degenerate case. */
11108 tree field;
11110 /* Can't handle incomplete types nor sizes that are not
11111 fixed. */
11117 {
11125 }
11127 /* There must be no padding. */
11133 }
11137 }
11140 }
11142 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
11143 type as described in AAPCS64 \S 4.1.2.
11145 See the comment above aarch64_composite_type_p for the notes on MODE. */
11147 static bool
11149 machine_mode mode)
11150 {
11160 }
11162 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
11163 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
11164 array types. The C99 floating-point complex types are also considered
11165 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
11166 types, which are GCC extensions and out of the scope of AAPCS64, are
11167 treated as composite types here as well.
11169 Note that MODE itself is not sufficient in determining whether a type
11170 is such a composite type or not. This is because
11171 stor-layout.c:compute_record_mode may have already changed the MODE
11172 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
11173 structure with only one field may have its MODE set to the mode of the
11174 field. Also an integer mode whose size matches the size of the
11175 RECORD_TYPE type may be used to substitute the original mode
11176 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
11177 solely relied on. */
11179 static bool
11181 machine_mode mode)
11182 {
11195 }
11197 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
11198 shall be passed or returned in simd/fp register(s) (providing these
11199 parameter passing registers are available).
11201 Upon successful return, *COUNT returns the number of needed registers,
11202 *BASE_MODE returns the mode of the individual register and when IS_HAF
11203 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
11204 floating-point aggregate or a homogeneous short-vector aggregate. */
11206 static bool
11208 const_tree type,
11212 {
11220 {
11223 }
11225 {
11229 }
11231 {
11235 {
11238 }
11239 else
11241 }
11242 else
11247 }
11249 /* Implement TARGET_STRUCT_VALUE_RTX. */
11251 static rtx
11254 {
11256 }
11258 /* Implements target hook vector_mode_supported_p. */
11259 static bool
11261 {
11273 }
11275 /* Return appropriate SIMD container
11276 for MODE within a vector of WIDTH bits. */
11277 static machine_mode
11279 {
11282 {
11285 {
11302 }
11303 else
11305 {
11318 }
11319 }
11321 }
11323 /* Return 128-bit container as the preferred SIMD mode for MODE. */
11324 static machine_mode
11326 {
11328 }
11330 /* Return the bitmask of possible vector sizes for the vectorizer
11331 to iterate over. */
11332 static unsigned int
11334 {
11336 }
11338 /* Implement TARGET_MANGLE_TYPE. */
11342 {
11343 /* The AArch64 ABI documents say that "__va_list" has to be
11344 managled as if it is in the "std" namespace. */
11348 /* Half-precision float. */
11352 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
11353 builtin types. */
11357 /* Use the default mangling. */
11359 }
11361 /* Find the first rtx_insn before insn that will generate an assembly
11362 instruction. */
11366 {
11370 do
11371 {
11373 }
11377 }
11379 static bool
11381 {
11383 /* A number of these may be AArch32 only. */
11388 };
11391 {
11394 }
11397 }
11399 /* Check if there is a register dependency between a load and the insn
11400 for which we hold recog_data. */
11402 static bool
11404 {
11405 rtx load_reg;
11415 {
11421 }
11423 }
11426 /* When working around the Cortex-A53 erratum 835769,
11427 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
11428 instruction and has a preceding memory instruction such that a NOP
11429 should be inserted between them. */
11431 bool
11433 {
11436 rtx body;
11449 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11450 Restore recog state to INSN to avoid state corruption. */
11458 /* If the previous insn is a memory op and there is no dependency between
11459 it and the DImode madd, emit a NOP between them. If body is NULL then we
11460 have a complex memory operation, probably a load/store pair.
11461 Be conservative for now and emit a NOP. */
11468 }
11471 /* Implement FINAL_PRESCAN_INSN. */
11473 void
11475 {
11478 }
11481 /* Return the equivalent letter for size. */
11482 static char
11484 {
11486 {
11492 }
11493 }
11495 /* Return true iff x is a uniform vector of floating-point
11496 constants, and the constant can be represented in
11497 quarter-precision form. Note, as aarch64_float_const_representable
11498 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11499 static bool
11501 {
11502 rtx elt;
11506 }
11508 /* Return true for valid and false for invalid. */
11509 bool
11513 {
11514 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11515 matches = 1; \
11516 for (i = 0; i < idx; i += (STRIDE)) \
11517 if (!(TEST)) \
11518 matches = 0; \
11519 if (matches) \
11520 { \
11521 immtype = (CLASS); \
11522 elsize = (ELSIZE); \
11523 eshift = (SHIFT); \
11524 emvn = (NEG); \
11525 break; \
11526 }
11536 {
11542 {
11544 scalar_float_mode elt_mode
11551 }
11554 }
11556 /* Splat vector constant out into a byte vector. */
11558 {
11559 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11560 it must be laid out in the vector register in reverse order. */
11568 {
11571 }
11573 }
11575 /* Sanity check. */
11578 do
11579 {
11581 {
11597 }
11600 {
11616 }
11618 /* Shifting ones / 8-bit / 64-bit variants only checked
11619 for 'ALL' (MOVI/MVNI). */
11621 {
11638 }
11639 }
11646 {
11656 /* Un-invert bytes of recognized vector, if necessary. */
11662 {
11663 /* FIXME: Broken on 32-bit H_W_I hosts. */
11672 }
11673 else
11674 {
11678 /* Construct 'abcdefgh' because the assembler cannot handle
11679 generic constants. */
11684 }
11685 }
11688 #undef CHECK
11689 }
11691 /* Check of immediate shift constants are within range. */
11692 bool
11694 {
11698 else
11700 }
11702 /* Return true if X is a uniform vector where all elements
11703 are either the floating-point constant 0.0 or the
11704 integer constant 0. */
11705 bool
11707 {
11709 }
11712 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11713 operation of width WIDTH at bit position POS. */
11715 rtx
11717 {
11721 unsigned HOST_WIDE_INT mask
11724 }
11726 bool
11728 {
11741 }
11743 /* Return a const_int vector of VAL. */
11744 rtx
11746 {
11749 }
11751 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11753 bool
11755 {
11756 machine_mode vmode;
11761 }
11763 /* Construct and return a PARALLEL RTX vector with elements numbering the
11764 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11765 the vector - from the perspective of the architecture. This does not
11766 line up with GCC's perspective on lane numbers, so we end up with
11767 different masks depending on our target endian-ness. The diagram
11768 below may help. We must draw the distinction when building masks
11769 which select one half of the vector. An instruction selecting
11770 architectural low-lanes for a big-endian target, must be described using
11771 a mask selecting GCC high-lanes.
11773 Big-Endian Little-Endian
11775 GCC 0 1 2 3 3 2 1 0
11776 | x | x | x | x | | x | x | x | x |
11777 Architecture 3 2 1 0 3 2 1 0
11779 Low Mask: { 2, 3 } { 0, 1 }
11780 High Mask: { 0, 1 } { 2, 3 }
11782 MODE Is the mode of the vector and NUNITS is the number of units in it. */
11784 rtx
11786 {
11791 rtx t1;
11796 else
11804 }
11806 /* Check OP for validity as a PARALLEL RTX vector with elements
11807 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11808 from the perspective of the architecture. See the diagram above
11809 aarch64_simd_vect_par_cnst_half for more details. */
11811 bool
11814 {
11819 high);
11828 {
11835 }
11837 }
11839 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11840 HIGH (exclusive). */
11841 void
11843 const_tree exp)
11844 {
11845 HOST_WIDE_INT lane;
11850 {
11853 else
11855 }
11856 }
11858 /* Peform endian correction on lane number N, which indexes a vector
11859 of mode MODE, and return the result as an SImode rtx. */
11861 rtx
11863 {
11865 }
11867 /* Return TRUE if OP is a valid vector addressing mode. */
11868 bool
11870 {
11873 }
11875 /* Emit a register copy from operand to operand, taking care not to
11876 early-clobber source registers in the process.
11878 COUNT is the number of components into which the copy needs to be
11879 decomposed. */
11880 void
11883 {
11893 else
11897 }
11899 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11900 one of VSTRUCT modes: OI, CI, or XI. */
11901 int
11903 {
11905 }
11907 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11908 alignment of a vector to 128 bits. */
11909 static HOST_WIDE_INT
11911 {
11914 }
11916 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11917 static bool
11919 {
11923 /* We guarantee alignment for vectors up to 128-bits. */
11928 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11930 }
11932 /* Return true if the vector misalignment factor is supported by the
11933 target. */
11934 static bool
11938 {
11940 {
11941 /* Return if movmisalign pattern is not supported for this mode. */
11945 /* Misalignment factor is unknown at compile time. */
11948 }
11950 is_packed);
11951 }
11953 /* If VALS is a vector constant that can be loaded into a register
11954 using DUP, generate instructions to do so and return an RTX to
11955 assign to the register. Otherwise return NULL_RTX. */
11956 static rtx
11958 {
11961 rtx x;
11966 /* We can load this constant by using DUP and a constant in a
11967 single ARM register. This will be cheaper than a vector
11968 load. */
11971 }
11974 /* Generate code to load VALS, which is a PARALLEL containing only
11975 constants (for vec_init) or CONST_VECTOR, efficiently into a
11976 register. Returns an RTX to copy into the register, or NULL_RTX
11977 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11978 static rtx
11980 {
11982 rtx const_dup;
11991 {
11992 /* A CONST_VECTOR must contain only CONST_INTs and
11993 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11994 Only store valid constants in a CONST_VECTOR. */
11996 {
11999 n_const++;
12000 }
12003 }
12004 else
12009 /* Load using MOVI/MVNI. */
12012 /* Loaded using DUP. */
12015 /* Load from constant pool. We can not take advantage of single-cycle
12016 LD1 because we need a PC-relative addressing mode. */
12018 else
12019 /* A PARALLEL containing something not valid inside CONST_VECTOR.
12020 We can not construct an initializer. */
12022 }
12024 /* Expand a vector initialisation sequence, such that TARGET is
12025 initialised to contain VALS. */
12027 void
12029 {
12032 /* The number of vector elements. */
12034 /* The number of vector elements which are not constant. */
12037 /* The first element of vals. */
12041 /* Count the number of variable elements to initialise. */
12043 {
12047 else
12051 }
12053 /* No variable elements, hand off to aarch64_simd_make_constant which knows
12054 how best to handle this. */
12056 {
12059 {
12062 }
12063 }
12065 /* Splat a single non-constant element if we can. */
12067 {
12071 }
12076 /* If there are only variable elements, try to optimize
12077 the insertion using dup for the most common element
12078 followed by insertions. */
12080 /* The algorithm will fill matches[*][0] with the earliest matching element,
12081 and matches[X][1] with the count of duplicate elements (if X is the
12082 earliest element which has duplicates). */
12085 {
12088 {
12090 {
12092 {
12096 }
12097 }
12098 }
12103 {
12106 }
12108 /* Create a duplicate of the most common element. */
12112 /* Insert the rest. */
12114 {
12120 }
12122 }
12124 /* Initialise a vector which is part-variable. We want to first try
12125 to build those lanes which are constant in the most efficient way we
12126 can. */
12128 {
12131 /* Load constant part of vector. We really don't care what goes into the
12132 parts we will overwrite, but we're more likely to be able to load the
12133 constant efficiently if it has fewer, larger, repeating parts
12134 (see aarch64_simd_valid_immediate). */
12136 {
12142 {
12143 /* Look in the copied vector, as more elements are const. */
12146 {
12149 }
12150 }
12152 }
12154 }
12156 /* Insert the variable lanes directly. */
12158 {
12164 }
12165 }
12167 static unsigned HOST_WIDE_INT
12169 {
12170 return
12171 (!SHIFT_COUNT_TRUNCATED
12174 }
12176 /* Select a format to encode pointers in exception handling data. */
12177 int
12179 {
12182 {
12188 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
12189 for everything. */
12193 /* No assumptions here. 8-byte relocs required. */
12196 }
12198 }
12200 /* The last .arch and .tune assembly strings that we printed. */
12204 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
12205 by the function fndecl. */
12207 void
12209 tree fndecl)
12210 {
12216 else
12227 /* Only update the assembler .arch string if it is distinct from the last
12228 such string we printed. */
12231 {
12234 }
12236 /* Print the cpu name we're tuning for in the comments, might be
12237 useful to readers of the generated asm. Do it only when it changes
12238 from function to function and verbose assembly is requested. */
12243 {
12247 }
12249 /* Don't forget the type directive for ELF. */
12252 }
12254 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
12256 static void
12258 {
12275 }
12277 /* Emit load exclusive. */
12279 static void
12282 {
12286 {
12293 }
12296 }
12298 /* Emit store exclusive. */
12300 static void
12303 {
12307 {
12314 }
12317 }
12319 /* Mark the previous jump instruction as unlikely. */
12321 static void
12323 {
12326 }
12328 /* Expand a compare and swap pattern. */
12330 void
12332 {
12337 gen_cas_fn gen;
12339 {
12340 gen_aarch64_compare_and_swapqi,
12341 gen_aarch64_compare_and_swaphi,
12342 gen_aarch64_compare_and_swapsi,
12343 gen_aarch64_compare_and_swapdi
12344 };
12346 {
12347 gen_aarch64_compare_and_swapqi_lse,
12348 gen_aarch64_compare_and_swaphi_lse,
12349 gen_aarch64_compare_and_swapsi_lse,
12350 gen_aarch64_compare_and_swapdi_lse
12351 };
12364 /* Normally the succ memory model must be stronger than fail, but in the
12365 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
12366 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
12373 {
12376 /* For short modes, we're going to perform the comparison in SImode,
12377 so do the zero-extension now. */
12381 /* Fall through. */
12385 /* Force the value into a register if needed. */
12392 }
12395 {
12402 }
12405 else
12416 }
12418 /* Test whether the target supports using a atomic load-operate instruction.
12419 CODE is the operation and AFTER is TRUE if the data in memory after the
12420 operation should be returned and FALSE if the data before the operation
12421 should be returned. Returns FALSE if the operation isn't supported by the
12422 architecture. */
12424 bool
12426 {
12431 {
12441 }
12442 }
12444 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
12445 sequence implementing an atomic operation. */
12447 static void
12449 {
12456 {
12458 }
12459 }
12461 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
12462 for the data in memory. EXPECTED is the value expected to be in memory.
12463 DESIRED is the value to store to memory. MEM is the memory location. MODEL
12464 is the memory ordering to use. */
12466 void
12469 rtx model)
12470 {
12472 machine_mode mode;
12477 {
12484 }
12486 /* Move the expected value into the CAS destination register. */
12489 /* Emit the CAS. */
12492 /* Compare the expected value with the value loaded by the CAS, to establish
12493 whether the swap was made. */
12495 }
12497 /* Split a compare and swap pattern. */
12499 void
12501 {
12503 machine_mode mode;
12508 rtx model_rtx;
12520 /* When OLDVAL is zero and we want the strong version we can emit a tighter
12521 loop:
12522 .label1:
12523 LD[A]XR rval, [mem]
12524 CBNZ rval, .label2
12525 ST[L]XR scratch, newval, [mem]
12526 CBNZ scratch, .label1
12527 .label2:
12528 CMP rval, 0. */
12533 {
12536 }
12539 /* The initial load can be relaxed for a __sync operation since a final
12540 barrier will be emitted to stop code hoisting. */
12544 else
12548 {
12553 }
12554 else
12555 {
12561 }
12566 {
12571 }
12572 else
12573 {
12577 }
12580 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
12581 to set the condition flags. If this is not used it will be removed by
12582 later passes. */
12584 {
12588 }
12589 /* Emit any final barrier needed for a __sync operation. */
12592 }
12594 /* Emit a BIC instruction. */
12596 static void
12598 {
12603 {
12608 }
12611 }
12613 /* Emit an atomic swap. */
12615 static void
12618 {
12622 {
12629 }
12632 }
12634 /* Operations supported by aarch64_emit_atomic_load_op. */
12636 enum aarch64_atomic_load_op_code
12637 {
12641 AARCH64_LDOP_BIC /* A & ~B */
12642 };
12644 /* Emit an atomic load-operate. */
12646 static void
12650 {
12653 {
12654 gen_aarch64_atomic_loadaddqi,
12655 gen_aarch64_atomic_loadaddhi,
12656 gen_aarch64_atomic_loadaddsi,
12657 gen_aarch64_atomic_loadadddi
12658 };
12660 {
12661 gen_aarch64_atomic_loadeorqi,
12662 gen_aarch64_atomic_loadeorhi,
12663 gen_aarch64_atomic_loadeorsi,
12664 gen_aarch64_atomic_loadeordi
12665 };
12667 {
12668 gen_aarch64_atomic_loadsetqi,
12669 gen_aarch64_atomic_loadsethi,
12670 gen_aarch64_atomic_loadsetsi,
12671 gen_aarch64_atomic_loadsetdi
12672 };
12674 {
12675 gen_aarch64_atomic_loadclrqi,
12676 gen_aarch64_atomic_loadclrhi,
12677 gen_aarch64_atomic_loadclrsi,
12678 gen_aarch64_atomic_loadclrdi
12679 };
12680 aarch64_atomic_load_op_fn gen;
12684 {
12691 }
12694 {
12701 }
12704 }
12706 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12707 location to store the data read from memory. OUT_RESULT is the location to
12708 store the result of the operation. MEM is the memory location to read and
12709 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12710 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12711 be NULL. */
12713 void
12716 {
12720 aarch64_atomic_load_op_code ldop_code;
12721 rtx src;
12722 rtx x;
12730 /* Make sure the value is in a register, putting it into a destination
12731 register if it needs to be manipulated. */
12734 {
12737 }
12738 else
12742 /* Preprocess the data for the operation as necessary. If the operation is
12743 a SET then emit a swap instruction and finish. */
12745 {
12751 /* Negate the value and treat it as a PLUS. */
12752 {
12753 rtx neg_src;
12755 /* Resize the value if necessary. */
12764 }
12765 /* Fall-through. */
12779 {
12780 rtx not_src;
12782 /* Resize the value if necessary. */
12791 }
12796 /* The operation can't be done with atomic instructions. */
12798 }
12802 /* If necessary, calculate the data in memory after the update by redoing the
12803 operation from values in registers. */
12808 {
12812 }
12817 {
12833 }
12838 }
12840 /* Split an atomic operation. */
12842 void
12845 {
12851 rtx x;
12853 /* Split the atomic operation into a sequence. */
12861 else
12865 /* The initial load can be relaxed for a __sync operation since a final
12866 barrier will be emitted to stop code hoisting. */
12870 else
12874 {
12888 {
12891 }
12892 /* Fall through. */
12898 }
12908 /* Emit any final barrier needed for a __sync operation. */
12911 }
12913 static void
12915 {
12916 /* Half-precision float operations. The compiler handles all operations
12917 with NULL libfuncs by converting to SFmode. */
12919 /* Conversions. */
12923 /* Arithmetic. */
12930 /* Comparisons. */
12938 }
12940 /* Target hook for c_mode_for_suffix. */
12941 static machine_mode
12943 {
12948 }
12950 /* We can only represent floating point constants which will fit in
12951 "quarter-precision" values. These values are characterised by
12952 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12953 by:
12955 (-1)^s * (n/16) * 2^r
12957 Where:
12958 's' is the sign bit.
12959 'n' is an integer in the range 16 <= n <= 31.
12960 'r' is an integer in the range -3 <= r <= 4. */
12962 /* Return true iff X can be represented by a quarter-precision
12963 floating point immediate operand X. Note, we cannot represent 0.0. */
12964 bool
12966 {
12967 /* This represents our current view of how many bits
12968 make up the mantissa. */
12978 /* We don't support HFmode constants yet. */
12984 /* We cannot represent infinities, NaNs or +/-zero. We won't
12985 know if we have +zero until we analyse the mantissa, but we
12986 can reject the other invalid values. */
12991 /* Extract exponent. */
12995 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12996 highest (sign) bit, with a fixed binary point at bit point_pos.
12997 m1 holds the low part of the mantissa, m2 the high part.
12998 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12999 bits for the mantissa, this can fail (low bits will be lost). */
13003 /* If the low part of the mantissa has bits set we cannot represent
13004 the value. */
13007 /* We have rejected the lower HOST_WIDE_INT, so update our
13008 understanding of how many bits lie in the mantissa and
13009 look only at the high HOST_WIDE_INT. */
13013 /* We can only represent values with a mantissa of the form 1.xxxx. */
13018 /* Having filtered unrepresentable values, we may now remove all
13019 but the highest 5 bits. */
13022 /* We cannot represent the value 0.0, so reject it. This is handled
13023 elsewhere. */
13027 /* Then, as bit 4 is always set, we can mask it off, leaving
13028 the mantissa in the range [0, 15]. */
13032 /* GCC internally does not use IEEE754-like encoding (where normalized
13033 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
13034 Our mantissa values are shifted 4 places to the left relative to
13035 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
13036 by 5 places to correct for GCC's representation. */
13040 }
13042 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
13043 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
13044 output MOVI/MVNI, ORR or BIC immediate. */
13047 machine_mode mode,
13050 {
13060 /* This will return true to show const_vector is legal for use as either
13061 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
13062 It will also update INFO to show how the immediate should be generated.
13063 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
13073 {
13075 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
13076 move immediate path. */
13079 else
13080 {
13089 else
13093 }
13094 }
13099 {
13109 else
13113 }
13114 else
13115 {
13116 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
13122 else
13126 }
13128 }
13132 {
13134 /* If a floating point number was passed and we desire to use it in an
13135 integer mode do the conversion to integer. */
13137 {
13142 }
13144 machine_mode vmode;
13145 /* use a 64 bit mode for everything except for DI/DF mode, where we use
13146 a 128 bit vector mode. */
13152 }
13154 /* Split operands into moves from op[1] + op[2] into op[0]. */
13156 void
13158 {
13169 {
13170 /* No-op move. Can't split to nothing; emit something. */
13173 }
13175 /* Preserve register attributes for variable tracking. */
13180 /* Special case of reversed high/low parts. */
13183 {
13187 }
13189 {
13190 /* Try to avoid unnecessary moves if part of the result
13191 is in the right place already. */
13196 }
13197 else
13198 {
13203 }
13204 }
13206 /* vec_perm support. */
13208 #define MAX_VECT_LEN 16
13210 struct expand_vec_perm_d
13211 {
13213 auto_vec_perm_indices perm;
13214 machine_mode vmode;
13217 };
13219 /* Generate a variable permutation. */
13221 static void
13223 {
13234 {
13236 {
13237 /* Expand the argument to a V16QI mode by duplicating it. */
13241 }
13242 else
13243 {
13245 }
13246 }
13247 else
13248 {
13249 rtx pair;
13252 {
13256 }
13257 else
13258 {
13262 }
13263 }
13264 }
13266 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
13267 NELT is the number of elements in the vector. */
13269 void
13272 {
13275 rtx mask;
13277 /* The TBL instruction does not use a modulo index, so we must take care
13278 of that ourselves. */
13283 /* For big-endian, we also need to reverse the index within the vector
13284 (but not which vector). */
13286 {
13287 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
13292 }
13294 }
13296 /* Recognize patterns suitable for the TRN instructions. */
13297 static bool
13299 {
13307 /* Note that these are little-endian tests.
13308 We correct for big-endian later. */
13313 else
13318 {
13323 }
13325 /* Success! */
13332 {
13335 }
13341 }
13343 /* Recognize patterns suitable for the UZP instructions. */
13344 static bool
13346 {
13354 /* Note that these are little-endian tests.
13355 We correct for big-endian later. */
13360 else
13365 {
13369 }
13371 /* Success! */
13378 {
13381 }
13387 }
13389 /* Recognize patterns suitable for the ZIP instructions. */
13390 static bool
13392 {
13400 /* Note that these are little-endian tests.
13401 We correct for big-endian later. */
13404 /* Do Nothing. */
13405 ;
13408 else
13413 {
13420 }
13422 /* Success! */
13429 {
13432 }
13438 }
13440 /* Recognize patterns for the EXT insn. */
13442 static bool
13444 {
13446 rtx offset;
13450 /* Check if the extracted indices are increasing by one. */
13452 {
13455 {
13456 /* We'll pass the same vector in twice, so allow indices to wrap. */
13458 }
13461 }
13463 /* Success! */
13467 /* The case where (location == 0) is a no-op for both big- and little-endian,
13468 and is removed by the mid-end at optimization levels -O1 and higher. */
13471 {
13472 /* After setup, we want the high elements of the first vector (stored
13473 at the LSB end of the register), and the low elements of the second
13474 vector (stored at the MSB end of the register). So swap. */
13476 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13478 }
13484 UNSPEC_EXT));
13486 }
13488 /* Recognize patterns for the REV insns. */
13490 static bool
13492 {
13506 else
13511 {
13512 /* This is guaranteed to be true as the value of diff
13513 is 7, 3, 1 and we should have enough elements in the
13514 queue to generate this. Getting a vector mask with a
13515 value of diff other than these values implies that
13516 something is wrong by the time we get here. */
13520 }
13522 /* Success! */
13527 unspec));
13529 }
13531 static bool
13533 {
13535 rtx in0;
13538 rtx lane;
13542 {
13545 }
13547 /* The generic preparation in aarch64_expand_vec_perm_const_1
13548 swaps the operand order and the permute indices if it finds
13549 d->perm[0] to be in the second operand. Thus, we can always
13550 use d->op0 and need not do any extra arithmetic to get the
13551 correct lane number. */
13559 }
13561 static bool
13563 {
13571 /* Generic code will try constant permutation twice. Once with the
13572 original mode and again with the elements lowered to QImode.
13573 So wait and don't do the selector expansion ourselves. */
13578 {
13581 /* If big-endian and two vectors we end up with a weird mixed-endian
13582 mode on NEON. Reverse the index within each word but not the word
13583 itself. */
13586 }
13592 }
13594 static bool
13596 {
13597 /* The pattern matching functions above are written to look for a small
13598 number to begin the sequence (0, 1, N/2). If we begin with an index
13599 from the second operand, we can swap the operands. */
13602 {
13608 }
13611 {
13625 }
13627 }
13629 /* Expand a vec_perm_const pattern with the operands given by TARGET,
13630 OP0, OP1 and SEL. NELT is the number of elements in the vector. */
13632 bool
13635 {
13649 {
13654 }
13657 {
13666 /* The elements of PERM do not suggest that only the first operand
13667 is used, but both operands are identical. Allow easier matching
13668 of the permutation by folding the permutation into the single
13669 input vector. */
13670 /* Fall Through. */
13682 }
13685 }
13687 static bool
13689 {
13698 /* Calculate whether all elements are in one vector. */
13701 {
13705 }
13707 /* If all elements are from the second vector, reindex as if from the
13708 first vector. */
13713 /* Check whether the mask can be applied to a single vector. */
13726 }
13728 /* Generate a byte permute mask for a register of mode MODE,
13729 which has NUNITS units. */
13731 rtx
13733 {
13734 /* We have to reverse each vector because we dont have
13735 a permuted load that can reverse-load according to ABI rules. */
13736 rtx mask;
13749 }
13751 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
13752 true. However due to issues with register allocation it is preferable
13753 to avoid tieing integer scalar and FP scalar modes. Executing integer
13754 operations in general registers is better than treating them as scalar
13755 vector operations. This reduces latency and avoids redundant int<->FP
13756 moves. So tie modes if they are either the same class, or vector modes
13757 with other vector modes, vector structs or any scalar mode. */
13759 static bool
13761 {
13765 /* We specifically want to allow elements of "structure" modes to
13766 be tieable to the structure. This more general condition allows
13767 other rarer situations too. */
13771 /* Also allow any scalar modes with vectors. */
13777 }
13779 /* Return a new RTX holding the result of moving POINTER forward by
13780 AMOUNT bytes. */
13782 static rtx
13784 {
13789 }
13791 /* Return a new RTX holding the result of moving POINTER forward by the
13792 size of the mode it points to. */
13794 static rtx
13796 {
13800 }
13802 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13803 MODE bytes. */
13805 static void
13807 machine_mode mode)
13808 {
13811 /* "Cast" the pointers to the correct mode. */
13814 /* Emit the memcpy. */
13817 /* Move the pointers forward. */
13820 }
13822 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13823 we succeed, otherwise return false. */
13825 bool
13827 {
13831 rtx base;
13834 /* When optimizing for size, give a better estimate of the length of a
13835 memcpy call, but use the default otherwise. */
13838 /* We can't do anything smart if the amount to copy is not constant. */
13844 /* Try to keep the number of instructions low. For cases below 16 bytes we
13845 need to make at most two moves. For cases above 16 bytes it will be one
13846 move for each 16 byte chunk, then at most two additional moves. */
13856 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13857 1-byte chunk. */
13859 {
13861 {
13864 }
13870 }
13872 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13873 4-byte chunk, partially overlapping with the previously copied chunk. */
13875 {
13879 {
13885 }
13887 }
13889 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13890 them, then (if applicable) an 8-byte chunk. */
13892 {
13894 {
13897 }
13898 else
13899 {
13902 }
13903 }
13905 /* Finish the final bytes of the copy. We can always do this in one
13906 instruction. We either copy the exact amount we need, or partially
13907 overlap with the previous chunk we copied and copy 8-bytes. */
13916 else
13917 {
13919 {
13923 }
13924 else
13925 {
13931 }
13932 }
13935 }
13937 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13938 SImode stores. Handle the case when the constant has identical
13939 bottom and top halves. This is beneficial when the two stores can be
13940 merged into an STP and we avoid synthesising potentially expensive
13941 immediates twice. Return true if such a split is possible. */
13943 bool
13945 {
13954 unsigned int orig_cost
13956 unsigned int lo_cost
13959 /* We want to transform:
13960 MOV x1, 49370
13961 MOVK x1, 0x140, lsl 16
13962 MOVK x1, 0xc0da, lsl 32
13963 MOVK x1, 0x140, lsl 48
13964 STR x1, [x0]
13965 into:
13966 MOV w1, 49370
13967 MOVK w1, 0x140, lsl 16
13968 STP w1, w1, [x0]
13969 So we want to perform this only when we save two instructions
13970 or more. When optimizing for size, however, accept any code size
13971 savings we can. */
13986 /* Don't emit an explicit store pair as this may not be always profitable.
13987 Let the sched-fusion logic decide whether to merge them. */
13992 }
13994 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13996 static unsigned HOST_WIDE_INT
13998 {
14000 }
14002 static rtx
14005 {
14009 insn_code icode;
14020 {
14048 }
14053 {
14056 }
14065 {
14068 }
14074 }
14076 static rtx
14079 {
14083 insn_code icode;
14095 {
14123 }
14128 {
14131 }
14139 {
14144 }
14155 {
14158 }
14164 }
14166 #undef TARGET_GEN_CCMP_FIRST
14167 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
14169 #undef TARGET_GEN_CCMP_NEXT
14170 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
14172 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
14173 instruction fusion of some sort. */
14175 static bool
14177 {
14179 }
14182 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
14183 should be kept together during scheduling. */
14185 static bool
14187 {
14188 rtx set_dest;
14191 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
14198 {
14199 /* We are trying to match:
14200 prev (mov) == (set (reg r0) (const_int imm16))
14201 curr (movk) == (set (zero_extract (reg r0)
14202 (const_int 16)
14203 (const_int 16))
14204 (const_int imm16_1)) */
14216 {
14218 }
14219 }
14222 {
14224 /* We're trying to match:
14225 prev (adrp) == (set (reg r1)
14226 (high (symbol_ref ("SYM"))))
14227 curr (add) == (set (reg r0)
14228 (lo_sum (reg r1)
14229 (symbol_ref ("SYM"))))
14230 Note that r0 need not necessarily be the same as r1, especially
14231 during pre-regalloc scheduling. */
14235 {
14243 }
14244 }
14247 {
14249 /* We're trying to match:
14250 prev (movk) == (set (zero_extract (reg r0)
14251 (const_int 16)
14252 (const_int 32))
14253 (const_int imm16_1))
14254 curr (movk) == (set (zero_extract (reg r0)
14255 (const_int 16)
14256 (const_int 48))
14257 (const_int imm16_2)) */
14273 }
14275 {
14276 /* We're trying to match:
14277 prev (adrp) == (set (reg r0)
14278 (high (symbol_ref ("SYM"))))
14279 curr (ldr) == (set (reg r1)
14280 (mem (lo_sum (reg r0)
14281 (symbol_ref ("SYM")))))
14282 or
14283 curr (ldr) == (set (reg r1)
14284 (zero_extend (mem
14285 (lo_sum (reg r0)
14286 (symbol_ref ("SYM")))))) */
14289 {
14302 }
14303 }
14311 {
14315 rtx cc_reg_1;
14320 && prev
14322 {
14323 /* FIXME: this misses some which is considered simple arthematic
14324 instructions for ThunderX. Simple shifts are missed here. */
14330 }
14331 }
14334 && curr_set
14337 {
14338 /* We're trying to match:
14339 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
14340 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
14341 (const_int 0))
14342 (label_ref ("SYM"))
14343 (pc)) */
14350 {
14351 /* Fuse ALU operations followed by conditional branch instruction. */
14353 {
14374 }
14375 }
14376 }
14379 }
14381 /* Return true iff the instruction fusion described by OP is enabled. */
14383 bool
14385 {
14387 }
14389 /* If MEM is in the form of [base+offset], extract the two parts
14390 of address and set to BASE and OFFSET, otherwise return false
14391 after clearing BASE and OFFSET. */
14393 bool
14395 {
14396 rtx addr;
14403 {
14407 }
14411 {
14415 }
14421 }
14423 /* Types for scheduling fusion. */
14424 enum sched_fusion_type
14425 {
14427 SCHED_FUSION_LD_SIGN_EXTEND,
14428 SCHED_FUSION_LD_ZERO_EXTEND,
14429 SCHED_FUSION_LD,
14430 SCHED_FUSION_ST,
14431 SCHED_FUSION_NUM
14432 };
14434 /* If INSN is a load or store of address in the form of [base+offset],
14435 extract the two parts and set to BASE and OFFSET. Return scheduling
14436 fusion type this INSN is. */
14438 static enum sched_fusion_type
14440 {
14458 {
14463 }
14465 {
14470 }
14475 {
14478 }
14479 else
14486 }
14488 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14490 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14491 and PRI are only calculated for these instructions. For other instruction,
14492 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14493 type instruction fusion can be added by returning different priorities.
14495 It's important that irrelevant instructions get the largest FUSION_PRI. */
14497 static void
14500 {
14510 {
14514 }
14516 /* Set FUSION_PRI according to fusion type and base register. */
14519 /* Calculate PRI. */
14522 /* INSN with smaller offset goes first. */
14526 else
14531 }
14533 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14534 Adjust priority of sha1h instructions so they are scheduled before
14535 other SHA1 instructions. */
14537 static int
14539 {
14543 {
14548 }
14551 }
14553 /* Given OPERANDS of consecutive load/store, check if we can merge
14554 them into ldp/stp. LOAD is true if they are load instructions.
14555 MODE is the mode of memory operands. */
14557 bool
14559 machine_mode mode)
14560 {
14566 {
14574 }
14575 else
14576 {
14581 }
14583 /* The mems cannot be volatile. */
14587 /* If we have SImode and slow unaligned ldp,
14588 check the alignment to be at least 8 byte. */
14592 && !optimize_size
14596 /* Check if the addresses are in the form of [base+offset]. */
14604 /* Check if the bases are same. */
14611 /* Check if the offsets are consecutive. */
14615 /* Check if the addresses are clobbered by load. */
14617 {
14621 /* In increasing order, the last load can clobber the address. */
14624 }
14628 else
14633 else
14636 /* Check if the registers are of same class. */
14641 }
14643 /* Given OPERANDS of consecutive load/store, check if we can merge
14644 them into ldp/stp by adjusting the offset. LOAD is true if they
14645 are load instructions. MODE is the mode of memory operands.
14647 Given below consecutive stores:
14649 str w1, [xb, 0x100]
14650 str w1, [xb, 0x104]
14651 str w1, [xb, 0x108]
14652 str w1, [xb, 0x10c]
14654 Though the offsets are out of the range supported by stp, we can
14655 still pair them after adjusting the offset, like:
14657 add scratch, xb, 0x100
14658 stp w1, w1, [scratch]
14659 stp w1, w1, [scratch, 0x8]
14661 The peephole patterns detecting this opportunity should guarantee
14662 the scratch register is avaliable. */
14664 bool
14666 scalar_mode mode)
14667 {
14674 {
14687 }
14688 else
14689 {
14698 }
14699 /* Skip if memory operand is by itslef valid for ldp/stp. */
14703 /* The mems cannot be volatile. */
14708 /* Check if the addresses are in the form of [base+offset]. */
14722 /* Check if the bases are same. */
14733 /* Check if the offsets are consecutive. */
14742 /* Check if the addresses are clobbered by load. */
14744 {
14750 /* In increasing order, the last load can clobber the address. */
14753 }
14755 /* If we have SImode and slow unaligned ldp,
14756 check the alignment to be at least 8 byte. */
14760 && !optimize_size
14766 else
14771 else
14776 else
14781 else
14784 /* Check if the registers are of same class. */
14789 }
14791 /* Given OPERANDS of consecutive load/store, this function pairs them
14792 into ldp/stp after adjusting the offset. It depends on the fact
14793 that addresses of load/store instructions are in increasing order.
14794 MODE is the mode of memory operands. CODE is the rtl operator
14795 which should be applied to all memory operands, it's SIGN_EXTEND,
14796 ZERO_EXTEND or UNKNOWN. */
14798 bool
14801 {
14807 {
14812 }
14813 else
14814 {
14820 }
14825 /* Adjust offset thus it can fit in ldp/stp instruction. */
14833 /* Further adjust to make sure all offsets are OK. */
14835 {
14838 }
14840 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14845 {
14848 }
14850 /* Create new memory references. */
14854 /* Check if the adjusted address is OK for ldp/stp. */
14873 {
14878 }
14880 {
14885 }
14888 {
14893 }
14894 else
14895 {
14900 }
14902 /* Emit adjusting instruction. */
14904 /* Emit ldp/stp instructions. */
14912 }
14914 /* Return 1 if pseudo register should be created and used to hold
14915 GOT address for PIC code. */
14917 bool
14919 {
14921 }
14923 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14925 static int
14927 {
14929 {
14936 }
14939 }
14942 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14943 return the log2 of that value. Otherwise return -1. */
14945 int
14947 {
14962 }
14964 /* If X is a vector of equal CONST_DOUBLE values and that value is
14965 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14967 int
14969 {
14985 }
14987 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14988 to float.
14990 __fp16 always promotes through this hook.
14991 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14992 through the generic excess precision logic rather than here. */
14994 static tree
14996 {
15002 }
15004 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
15006 static bool
15008 optimization_type opt_type)
15009 {
15011 {
15017 }
15018 }
15020 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
15021 if MODE is HFmode, and punt to the generic implementation otherwise. */
15023 static bool
15025 {
15029 }
15031 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
15032 if MODE is HFmode, and punt to the generic implementation otherwise. */
15034 static bool
15036 {
15040 }
15042 /* Set the value of FLT_EVAL_METHOD.
15043 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
15045 0: evaluate all operations and constants, whose semantic type has at
15046 most the range and precision of type float, to the range and
15047 precision of float; evaluate all other operations and constants to
15048 the range and precision of the semantic type;
15050 N, where _FloatN is a supported interchange floating type
15051 evaluate all operations and constants, whose semantic type has at
15052 most the range and precision of _FloatN type, to the range and
15053 precision of the _FloatN type; evaluate all other operations and
15054 constants to the range and precision of the semantic type;
15056 If we have the ARMv8.2-A extensions then we support _Float16 in native
15057 precision, so we should set this to 16. Otherwise, we support the type,
15058 but want to evaluate expressions in float precision, so set this to
15059 0. */
15061 static enum flt_eval_method
15063 {
15065 {
15068 /* We can calculate either in 16-bit range and precision or
15069 32-bit range and precision. Make that decision based on whether
15070 we have native support for the ARMv8.2-A 16-bit floating-point
15071 instructions or not. */
15073 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
15079 }
15081 }
15083 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
15084 scheduled for speculative execution. Reject the long-running division
15085 and square-root instructions. */
15087 static bool
15089 {
15091 {
15109 }
15110 }
15112 /* Target-specific selftests. */
15114 #if CHECKING_P
15118 /* Selftest for the RTL loader.
15119 Verify that the RTL loader copes with a dump from
15120 print_rtx_function. This is essentially just a test that class
15121 function_reader can handle a real dump, but it also verifies
15122 that lookup_reg_by_dump_name correctly handles hard regs.
15123 The presence of hard reg names in the dump means that the test is
15124 target-specific, hence it is in this file. */
15126 static void
15128 {
15140 /* Verify crtl->return_rtx. */
15144 }
15146 /* Run all target-specific selftests. */
15148 static void
15150 {
15152 }
15158 #undef TARGET_ADDRESS_COST
15159 #define TARGET_ADDRESS_COST aarch64_address_cost
15161 /* This hook will determines whether unnamed bitfields affect the alignment
15162 of the containing structure. The hook returns true if the structure
15163 should inherit the alignment requirements of an unnamed bitfield's
15164 type. */
15165 #undef TARGET_ALIGN_ANON_BITFIELD
15166 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
15168 #undef TARGET_ASM_ALIGNED_DI_OP
15171 #undef TARGET_ASM_ALIGNED_HI_OP
15174 #undef TARGET_ASM_ALIGNED_SI_OP
15177 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15178 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
15179 hook_bool_const_tree_hwi_hwi_const_tree_true
15181 #undef TARGET_ASM_FILE_START
15182 #define TARGET_ASM_FILE_START aarch64_start_file
15184 #undef TARGET_ASM_OUTPUT_MI_THUNK
15185 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
15187 #undef TARGET_ASM_SELECT_RTX_SECTION
15188 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
15190 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
15191 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
15193 #undef TARGET_BUILD_BUILTIN_VA_LIST
15194 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
15196 #undef TARGET_CALLEE_COPIES
15197 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
15199 #undef TARGET_CAN_ELIMINATE
15200 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
15202 #undef TARGET_CAN_INLINE_P
15203 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
15205 #undef TARGET_CANNOT_FORCE_CONST_MEM
15206 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
15208 #undef TARGET_CASE_VALUES_THRESHOLD
15209 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
15211 #undef TARGET_CONDITIONAL_REGISTER_USAGE
15212 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
15214 /* Only the least significant bit is used for initialization guard
15215 variables. */
15216 #undef TARGET_CXX_GUARD_MASK_BIT
15217 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
15219 #undef TARGET_C_MODE_FOR_SUFFIX
15220 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
15222 #ifdef TARGET_BIG_ENDIAN_DEFAULT
15223 #undef TARGET_DEFAULT_TARGET_FLAGS
15224 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
15225 #endif
15227 #undef TARGET_CLASS_MAX_NREGS
15228 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
15230 #undef TARGET_BUILTIN_DECL
15231 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
15233 #undef TARGET_BUILTIN_RECIPROCAL
15234 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
15236 #undef TARGET_C_EXCESS_PRECISION
15237 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
15239 #undef TARGET_EXPAND_BUILTIN
15240 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
15242 #undef TARGET_EXPAND_BUILTIN_VA_START
15243 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
15245 #undef TARGET_FOLD_BUILTIN
15246 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
15248 #undef TARGET_FUNCTION_ARG
15249 #define TARGET_FUNCTION_ARG aarch64_function_arg
15251 #undef TARGET_FUNCTION_ARG_ADVANCE
15252 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
15254 #undef TARGET_FUNCTION_ARG_BOUNDARY
15255 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
15257 #undef TARGET_FUNCTION_ARG_PADDING
15258 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
15260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15261 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
15263 #undef TARGET_FUNCTION_VALUE
15264 #define TARGET_FUNCTION_VALUE aarch64_function_value
15266 #undef TARGET_FUNCTION_VALUE_REGNO_P
15267 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
15269 #undef TARGET_GIMPLE_FOLD_BUILTIN
15270 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
15272 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15273 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
15275 #undef TARGET_INIT_BUILTINS
15276 #define TARGET_INIT_BUILTINS aarch64_init_builtins
15278 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
15279 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
15280 aarch64_ira_change_pseudo_allocno_class
15282 #undef TARGET_LEGITIMATE_ADDRESS_P
15283 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
15285 #undef TARGET_LEGITIMATE_CONSTANT_P
15286 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
15288 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
15289 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
15290 aarch64_legitimize_address_displacement
15292 #undef TARGET_LIBGCC_CMP_RETURN_MODE
15293 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
15295 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
15296 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
15297 aarch64_libgcc_floating_mode_supported_p
15299 #undef TARGET_MANGLE_TYPE
15300 #define TARGET_MANGLE_TYPE aarch64_mangle_type
15302 #undef TARGET_MEMORY_MOVE_COST
15303 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
15305 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
15306 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
15308 #undef TARGET_MUST_PASS_IN_STACK
15309 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15311 /* This target hook should return true if accesses to volatile bitfields
15312 should use the narrowest mode possible. It should return false if these
15313 accesses should use the bitfield container type. */
15314 #undef TARGET_NARROW_VOLATILE_BITFIELD
15315 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
15317 #undef TARGET_OPTION_OVERRIDE
15318 #define TARGET_OPTION_OVERRIDE aarch64_override_options
15320 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
15321 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
15322 aarch64_override_options_after_change
15324 #undef TARGET_OPTION_SAVE
15325 #define TARGET_OPTION_SAVE aarch64_option_save
15327 #undef TARGET_OPTION_RESTORE
15328 #define TARGET_OPTION_RESTORE aarch64_option_restore
15330 #undef TARGET_OPTION_PRINT
15331 #define TARGET_OPTION_PRINT aarch64_option_print
15333 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
15334 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
15336 #undef TARGET_SET_CURRENT_FUNCTION
15337 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
15339 #undef TARGET_PASS_BY_REFERENCE
15340 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
15342 #undef TARGET_PREFERRED_RELOAD_CLASS
15343 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
15345 #undef TARGET_SCHED_REASSOCIATION_WIDTH
15346 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
15348 #undef TARGET_PROMOTED_TYPE
15349 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
15351 #undef TARGET_SECONDARY_RELOAD
15352 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
15354 #undef TARGET_SHIFT_TRUNCATION_MASK
15355 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
15357 #undef TARGET_SETUP_INCOMING_VARARGS
15358 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
15360 #undef TARGET_STRUCT_VALUE_RTX
15361 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
15363 #undef TARGET_REGISTER_MOVE_COST
15364 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
15366 #undef TARGET_RETURN_IN_MEMORY
15367 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
15369 #undef TARGET_RETURN_IN_MSB
15370 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
15372 #undef TARGET_RTX_COSTS
15373 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
15375 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15376 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
15378 #undef TARGET_SCHED_ISSUE_RATE
15379 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
15381 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15382 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15383 aarch64_sched_first_cycle_multipass_dfa_lookahead
15385 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
15386 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
15387 aarch64_first_cycle_multipass_dfa_lookahead_guard
15389 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
15390 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
15391 aarch64_get_separate_components
15393 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
15394 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
15395 aarch64_components_for_bb
15397 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
15398 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
15399 aarch64_disqualify_components
15401 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
15402 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
15403 aarch64_emit_prologue_components
15405 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
15406 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
15407 aarch64_emit_epilogue_components
15409 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
15410 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
15411 aarch64_set_handled_components
15413 #undef TARGET_TRAMPOLINE_INIT
15414 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
15416 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15417 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
15419 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15420 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
15422 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
15423 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
15424 aarch64_builtin_support_vector_misalignment
15426 #undef TARGET_ARRAY_MODE_SUPPORTED_P
15427 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15429 #undef TARGET_VECTORIZE_ADD_STMT_COST
15430 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15432 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15433 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15434 aarch64_builtin_vectorization_cost
15436 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15437 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15439 #undef TARGET_VECTORIZE_BUILTINS
15440 #define TARGET_VECTORIZE_BUILTINS
15442 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15443 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15444 aarch64_builtin_vectorized_function
15446 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15447 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15448 aarch64_autovectorize_vector_sizes
15450 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15451 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15452 aarch64_atomic_assign_expand_fenv
15454 /* Section anchor support. */
15456 #undef TARGET_MIN_ANCHOR_OFFSET
15457 #define TARGET_MIN_ANCHOR_OFFSET -256
15459 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15460 byte offset; we can do much more for larger data types, but have no way
15461 to determine the size of the access. We assume accesses are aligned. */
15462 #undef TARGET_MAX_ANCHOR_OFFSET
15463 #define TARGET_MAX_ANCHOR_OFFSET 4095
15465 #undef TARGET_VECTOR_ALIGNMENT
15466 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15468 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15469 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15470 aarch64_simd_vector_alignment_reachable
15472 /* vec_perm support. */
15474 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15475 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15476 aarch64_vectorize_vec_perm_const_ok
15478 #undef TARGET_INIT_LIBFUNCS
15479 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15481 #undef TARGET_FIXED_CONDITION_CODE_REGS
15482 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15484 #undef TARGET_FLAGS_REGNUM
15485 #define TARGET_FLAGS_REGNUM CC_REGNUM
15487 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15488 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15490 #undef TARGET_ASAN_SHADOW_OFFSET
15491 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15493 #undef TARGET_LEGITIMIZE_ADDRESS
15494 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15496 #undef TARGET_SCHED_CAN_SPECULATE_INSN
15497 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
15499 #undef TARGET_CAN_USE_DOLOOP_P
15500 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15502 #undef TARGET_SCHED_ADJUST_PRIORITY
15503 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15505 #undef TARGET_SCHED_MACRO_FUSION_P
15506 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15508 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15509 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15511 #undef TARGET_SCHED_FUSION_PRIORITY
15512 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15514 #undef TARGET_UNSPEC_MAY_TRAP_P
15515 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15517 #undef TARGET_USE_PSEUDO_PIC_REG
15518 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15520 #undef TARGET_PRINT_OPERAND
15521 #define TARGET_PRINT_OPERAND aarch64_print_operand
15523 #undef TARGET_PRINT_OPERAND_ADDRESS
15524 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15526 #undef TARGET_OPTAB_SUPPORTED_P
15527 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15529 #undef TARGET_OMIT_STRUCT_RETURN_REG
15530 #define TARGET_OMIT_STRUCT_RETURN_REG true
15532 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15533 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15534 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15536 #undef TARGET_HARD_REGNO_NREGS
15537 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
15538 #undef TARGET_HARD_REGNO_MODE_OK
15539 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
15541 #undef TARGET_MODES_TIEABLE_P
15542 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
15544 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
15545 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
15546 aarch64_hard_regno_call_part_clobbered
15548 #undef TARGET_CONSTANT_ALIGNMENT
15549 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
15551 #if CHECKING_P
15552 #undef TARGET_RUN_TARGET_SELFTESTS
15553 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests