1 /* Definitions of x86 tunable features.
2 Copyright (C
) 2013-2017 Free Software Foundation
, Inc.
4 This file is part of GCC.
6 GCC is free software
; you can redistribute it and
/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation
; either version
3, or (at your option
)
11 GCC is distributed in the hope that it will be useful
,
12 but WITHOUT ANY WARRANTY
; without even the implied warranty of
13 MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License and
17 a copy of the GCC Runtime Library Exception along with this program
;
18 see the files COPYING3 and COPYING.RUNTIME respectively. If not
, see
19 <http
://www.gnu.org
/licenses
/>.
*/
21 /* Tuning for a given CPU XXXX consists of
:
22 - adding new CPU into
:
23 - adding PROCESSOR_XXX to
processor_type (in i386.h
)
24 - possibly adding XXX into CPU attribute in i386.md
25 - adding XXX to
processor_alias_table (in i386.c
)
26 - introducing ix86_XXX_cost in i386.c
27 - Stringop generation table can be build based on test_stringop
28 - script (once rest of tuning is complete
)
29 - designing a scheduler model in
31 - Updating ix86_issue_rate and ix86_adjust_cost in i386.md
32 - possibly updating ia32_multipass_dfa_lookahead
, ix86_sched_reorder
33 and ix86_sched_init_global if those tricks are needed.
34 - Tunning the flags bellow. Those are split into sections and each
35 section is very roughly ordered by importance.
*/
37 /*****************************************************************************/
38 /* Scheduling flags.
*/
39 /*****************************************************************************/
41 /* X86_TUNE_SCHEDULE
: Enable scheduling.
*/
42 DEF_TUNE (X86_TUNE_SCHEDULE
, "schedule",
43 m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
44 | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC
)
46 /* X86_TUNE_PARTIAL_REG_DEPENDENCY
: Enable more register renaming
47 on modern chips. Preffer stores affecting whole integer register
48 over partial stores. For example preffer MOVZBL or MOVQ to load
8bit
50 DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY
, "partial_reg_dependency",
51 m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
52 | m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC
)
54 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY
: This knob promotes all store
55 destinations to be
128bit to allow register renaming on
128bit SSE units
,
56 but usually results in one extra microop on
64bit SSE units.
57 Experimental results shows that disabling this option on P4 brings over
20%
58 SPECfp regression
, while enabling it on K8 brings roughly
2.4% regression
59 that can be partly masked by careful scheduling of moves.
*/
60 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY
, "sse_partial_reg_dependency",
61 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
62 | m_BDVER | m_ZNVER1 | m_GENERIC
)
64 /* X86_TUNE_SSE_SPLIT_REGS
: Set for machines where the type and dependencies
65 are resolved on SSE register parts instead of whole registers
, so we may
66 maintain just lower part of scalar values in proper format leaving the
67 upper part undefined.
*/
68 DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS
, "sse_split_regs", m_ATHLON_K8
)
70 /* X86_TUNE_PARTIAL_FLAG_REG_STALL
: this flag disables use of of flags
71 set by instructions affecting just some
flags (in particular shifts
).
72 This is because Core2 resolves dependencies on whole flags register
73 and such sequences introduce false dependency on previous instruction
76 The flags does not affect generation of
INC and
DEC that is controlled
77 by X86_TUNE_USE_INCDEC.
79 This flag may be dropped from generic once core2
-corei5 machines are
81 DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL
, "partial_flag_reg_stall",
84 /* X86_TUNE_MOVX
: Enable to zero extend integer registers to avoid
85 partial dependencies.
*/
86 DEF_TUNE (X86_TUNE_MOVX
, "movx",
87 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
88 | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC
)
90 /* X86_TUNE_MEMORY_MISMATCH_STALL
: Avoid partial stores that are followed by
92 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL
, "memory_mismatch_stall",
93 m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
94 | m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC
)
96 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32
: Fuse compare with a subsequent
97 conditional jump instruction for
32 bit TARGET.
98 FIXME
: revisit for generic.
*/
99 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32
, "fuse_cmp_and_branch_32",
100 m_CORE_ALL | m_BDVER | m_ZNVER1
)
102 /* X86_TUNE_FUSE_CMP_AND_BRANCH_64
: Fuse compare with a subsequent
103 conditional jump instruction for TARGET_64BIT.
104 FIXME
: revisit for generic.
*/
105 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64
, "fuse_cmp_and_branch_64",
106 m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1
)
108 /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS
: Fuse compare with a
109 subsequent conditional jump instruction when the condition jump
110 check sign
flag (SF
) or overflow
flag (OF).
*/
111 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS
, "fuse_cmp_and_branch_soflags",
112 m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1
)
114 /* X86_TUNE_FUSE_ALU_AND_BRANCH
: Fuse alu with a subsequent conditional
115 jump instruction when the alu instruction produces the CCFLAG consumed by
116 the conditional jump instruction.
*/
117 DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH
, "fuse_alu_and_branch",
118 m_SANDYBRIDGE | m_HASWELL
)
121 /*****************************************************************************/
122 /* Function prologue
, epilogue and function calling sequences.
*/
123 /*****************************************************************************/
125 /* X86_TUNE_ACCUMULATE_OUTGOING_ARGS
: Allocate stack space for outgoing
126 arguments in prologue
/epilogue instead of separately for each call
127 by push
/pop instructions.
128 This increase code size by about
5% in
32bit mode
, less so in
64bit mode
129 because parameters are passed in registers. It is considerable
130 win for targets without stack engine that prevents multple push operations
131 to happen in parallel.
133 FIXME
: the flags is incorrectly enabled for amdfam10
, Bulldozer
,
134 Bobcat and Generic. This is because disabling it causes large
135 regression on mgrid due to IRA limitation leading to unecessary
136 use of the frame pointer in
32bit mode.
*/
137 DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS
, "accumulate_outgoing_args",
138 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
141 /* X86_TUNE_PROLOGUE_USING_MOVE
: Do not use push
/pop in prologues that are
142 considered on critical path.
*/
143 DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE
, "prologue_using_move",
144 m_PPRO | m_ATHLON_K8
)
146 /* X86_TUNE_PROLOGUE_USING_MOVE
: Do not use push
/pop in epilogues that are
147 considered on critical path.
*/
148 DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE
, "epilogue_using_move",
149 m_PPRO | m_ATHLON_K8
)
151 /* X86_TUNE_USE_LEAVE
: Use
"leave" instruction in epilogues where it fits.
*/
152 DEF_TUNE (X86_TUNE_USE_LEAVE
, "use_leave",
153 m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC
)
155 /* X86_TUNE_PUSH_MEMORY
: Enable generation of
"push mem" instructions.
156 Some chips
, like
486 and Pentium works faster with separate load
157 and push instructions.
*/
158 DEF_TUNE (X86_TUNE_PUSH_MEMORY
, "push_memory",
159 m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
162 /* X86_TUNE_SINGLE_PUSH
: Enable if single push insn is preferred
163 over esp subtraction.
*/
164 DEF_TUNE (X86_TUNE_SINGLE_PUSH
, "single_push", m_386 | m_486 | m_PENT
165 | m_LAKEMONT | m_K6_GEODE
)
167 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
168 over esp subtraction.
*/
169 DEF_TUNE (X86_TUNE_DOUBLE_PUSH
, "double_push", m_PENT | m_LAKEMONT
172 /* X86_TUNE_SINGLE_POP
: Enable if single pop insn is preferred
173 over esp addition.
*/
174 DEF_TUNE (X86_TUNE_SINGLE_POP
, "single_pop", m_386 | m_486 | m_PENT
175 | m_LAKEMONT | m_PPRO
)
177 /* X86_TUNE_DOUBLE_POP
: Enable if double pop insn is preferred
178 over esp addition.
*/
179 DEF_TUNE (X86_TUNE_DOUBLE_POP
, "double_pop", m_PENT | m_LAKEMONT
)
181 /*****************************************************************************/
182 /* Branch predictor tuning
*/
183 /*****************************************************************************/
185 /* X86_TUNE_PAD_SHORT_FUNCTION
: Make every function to be at least
4
186 instructions long.
*/
187 DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION
, "pad_short_function", m_BONNELL
)
189 /* X86_TUNE_PAD_RETURNS
: Place NOP before every RET that is a destination
190 of conditional jump or directly preceded by other jump instruction.
191 This is important for
AND K8
-AMDFAM10 because the branch prediction
192 architecture expect at most one jump per
2 byte window. Failing to
193 pad returns leads to misaligned return stack.
*/
194 DEF_TUNE (X86_TUNE_PAD_RETURNS
, "pad_returns",
195 m_ATHLON_K8 | m_AMDFAM10 | m_GENERIC
)
197 /* X86_TUNE_FOUR_JUMP_LIMIT
: Some CPU cores are not able to predict more
198 than
4 branch instructions in the
16 byte window.
*/
199 DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT
, "four_jump_limit",
200 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
201 |m_INTEL | m_ATHLON_K8 | m_AMDFAM10
)
203 /*****************************************************************************/
204 /* Integer instruction selection tuning
*/
205 /*****************************************************************************/
207 /* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL
: Enable software prefetching
208 at
-O3. For the moment
, the prefetching seems badly tuned for Intel
210 DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL
, "software_prefetching_beneficial",
211 m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
)
213 /* X86_TUNE_LCP_STALL
: Avoid an expensive length
-changing prefix stall
214 on
16-bit immediate moves into memory on Core2 and Corei7.
*/
215 DEF_TUNE (X86_TUNE_LCP_STALL
, "lcp_stall", m_CORE_ALL | m_GENERIC
)
217 /* X86_TUNE_READ_MODIFY
: Enable use of read
-modify instructions such
218 as
"add mem, reg".
*/
219 DEF_TUNE (X86_TUNE_READ_MODIFY
, "read_modify", ~
(m_PENT | m_LAKEMONT | m_PPRO
))
221 /* X86_TUNE_USE_INCDEC
: Enable use of inc
/dec instructions.
*/
222 DEF_TUNE (X86_TUNE_USE_INCDEC
, "use_incdec",
223 ~
(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
224 | m_KNL | m_KNM | m_GENERIC
))
226 /* X86_TUNE_INTEGER_DFMODE_MOVES
: Enable if integer moves are preferred
228 DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES
, "integer_dfmode_moves",
229 ~
(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
230 | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC
))
232 /* X86_TUNE_OPT_AGU
: Optimize for Address Generation Unit. This flag
233 will impact LEA instruction selection.
*/
234 DEF_TUNE (X86_TUNE_OPT_AGU
, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
237 /* X86_TUNE_AVOID_LEA_FOR_ADDR
: Avoid lea for address computation.
*/
238 DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR
, "avoid_lea_for_addr",
239 m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
)
241 /* X86_TUNE_SLOW_IMUL_IMM32_MEM
: Imul of
32-bit constant and memory is
242 vector path on AMD machines.
243 FIXME
: Do we need to enable this for core?
*/
244 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM
, "slow_imul_imm32_mem",
247 /* X86_TUNE_SLOW_IMUL_IMM8
: Imul of
8-bit constant is vector path on AMD
249 FIXME
: Do we need to enable this for core?
*/
250 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8
, "slow_imul_imm8",
253 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE
: Try to avoid memory operands for
254 a conditional move.
*/
255 DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE
, "avoid_mem_opnd_for_cmove",
256 m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
)
258 /* X86_TUNE_SINGLE_STRINGOP
: Enable use of single string operations
, such
259 as MOVS and
STOS (without a REP prefix
) to move
/set sequences of bytes.
*/
260 DEF_TUNE (X86_TUNE_SINGLE_STRINGOP
, "single_stringop", m_386 | m_P4_NOCONA
)
262 /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
: Enable generation of
263 compact prologues and epilogues by issuing a misaligned moves. This
264 requires target to handle misaligned moves and partial memory stalls
266 FIXME
: This may actualy be a win on more targets than listed here.
*/
267 DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
,
268 "misaligned_move_string_pro_epilogues",
269 m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC
)
271 /* X86_TUNE_USE_SAHF
: Controls use of SAHF.
*/
272 DEF_TUNE (X86_TUNE_USE_SAHF
, "use_sahf",
273 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
274 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
275 | m_BTVER | m_ZNVER1 | m_GENERIC
)
277 /* X86_TUNE_USE_CLTD
: Controls use of CLTD and CTQO instructions.
*/
278 DEF_TUNE (X86_TUNE_USE_CLTD
, "use_cltd",
279 ~
(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
282 /* X86_TUNE_USE_BT
: Enable use of
BT (bit test
) instructions.
*/
283 DEF_TUNE (X86_TUNE_USE_BT
, "use_bt",
284 m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
285 | m_LAKEMONT | m_AMD_MULTIPLE | m_GENERIC
)
287 /*****************************************************************************/
288 /* 387 instruction selection tuning
*/
289 /*****************************************************************************/
291 /* X86_TUNE_USE_HIMODE_FIOP
: Enables use of x87 instructions with
16bit
293 FIXME
: Why this is disabled for modern chips?
*/
294 DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP
, "use_himode_fiop",
295 m_386 | m_486 | m_K6_GEODE
)
297 /* X86_TUNE_USE_SIMODE_FIOP
: Enables use of x87 instructions with
32bit
299 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP
, "use_simode_fiop",
300 ~
(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
301 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE | m_GENERIC
))
303 /* X86_TUNE_USE_FFREEP
: Use freep instruction instead of fstp.
*/
304 DEF_TUNE (X86_TUNE_USE_FFREEP
, "use_ffreep", m_AMD_MULTIPLE
)
306 /* X86_TUNE_EXT_80387_CONSTANTS
: Use fancy
80387 constants
, such as PI.
*/
307 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS
, "ext_80387_constants",
308 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
309 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC
)
311 /*****************************************************************************/
312 /* SSE instruction selection tuning
*/
313 /*****************************************************************************/
315 /* X86_TUNE_GENERAL_REGS_SSE_SPILL
: Try to spill general regs to SSE
316 regs instead of memory.
*/
317 DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL
, "general_regs_sse_spill",
320 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL
: Use movups for misaligned loads instead
321 of a sequence loading registers by parts.
*/
322 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL
, "sse_unaligned_load_optimal",
323 m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
324 | m_INTEL | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC
)
326 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL
: Use movups for misaligned stores instead
327 of a sequence loading registers by parts.
*/
328 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL
, "sse_unaligned_store_optimal",
329 m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
330 | m_INTEL | m_BDVER | m_ZNVER1 | m_GENERIC
)
332 /* Use packed single precision instructions where posisble. I.e. movups instead
334 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL
, "sse_packed_single_insn_optimal",
337 /* X86_TUNE_SSE_TYPELESS_STORES
: Always movaps
/movups for
128bit stores.
*/
338 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES
, "sse_typeless_stores",
339 m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC
)
341 /* X86_TUNE_SSE_LOAD0_BY_PXOR
: Always use pxor to load0 as opposed to
342 xorps
/xorpd and other variants.
*/
343 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR
, "sse_load0_by_pxor",
344 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER1
347 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC
: Enable moves in from integer
348 to SSE registers. If disabled
, the moves will be done by storing
349 the value to memory and reloading.
*/
350 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC
, "inter_unit_moves_to_vec",
351 ~
(m_AMD_MULTIPLE | m_GENERIC
))
353 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC
: Enable moves in from SSE
354 to integer registers. If disabled
, the moves will be done by storing
355 the value to memory and reloading.
*/
356 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC
, "inter_unit_moves_from_vec",
359 /* X86_TUNE_INTER_UNIT_CONVERSIONS
: Enable float
<->integer conversions
360 to use both SSE and integer registers at a same time.
361 FIXME
: revisit importance of this for generic.
*/
362 DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS
, "inter_unit_conversions",
363 ~
(m_AMDFAM10 | m_BDVER
))
365 /* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS
: Try to split memory operand for
366 fp converts to destination register.
*/
367 DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS
, "split_mem_opnd_for_fp_converts",
368 m_SILVERMONT | m_KNL | m_KNM | m_INTEL
)
370 /* X86_TUNE_USE_VECTOR_FP_CONVERTS
: Prefer vector packed SSE conversion
371 from FP to FP. This form of instructions avoids partial write to the
373 DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS
, "use_vector_fp_converts",
376 /* X86_TUNE_USE_VECTOR_CONVERTS
: Prefer vector packed SSE conversion
377 from integer to FP.
*/
378 DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS
, "use_vector_converts", m_AMDFAM10
)
380 /* X86_TUNE_SLOW_SHUFB
: Indicates tunings with slow pshufb instruction.
*/
381 DEF_TUNE (X86_TUNE_SLOW_PSHUFB
, "slow_pshufb",
382 m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
)
384 /* X86_TUNE_AVOID_4BYTE_PREFIXES
: Avoid instructions requiring
4+ bytes of prefixes.
*/
385 DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES
, "avoid_4byte_prefixes",
386 m_SILVERMONT | m_INTEL
)
388 /*****************************************************************************/
389 /* AVX instruction selection
tuning (some of SSE flags affects AVX
, too
) */
390 /*****************************************************************************/
392 /* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL
: if false
, unaligned loads are
394 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL
, "256_unaligned_load_optimal",
395 ~
(m_NEHALEM | m_SANDYBRIDGE | m_GENERIC
))
397 /* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL
: if false
, unaligned stores are
399 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL
, "256_unaligned_store_optimal",
400 ~
(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1 | m_GENERIC
))
402 /* X86_TUNE_AVX128_OPTIMAL
: Enable
128-bit AVX instruction generation for
403 the auto
-vectorizer.
*/
404 DEF_TUNE (X86_TUNE_AVX128_OPTIMAL
, "avx128_optimal", m_BDVER | m_BTVER2
407 /*****************************************************************************/
408 /* Historical relics
: tuning flags that helps a specific old CPU designs
*/
409 /*****************************************************************************/
411 /* X86_TUNE_DOUBLE_WITH_ADD
: Use add instead of sal to double value in
412 an integer register.
*/
413 DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD
, "double_with_add", ~m_386
)
415 /* X86_TUNE_ALWAYS_FANCY_MATH_387
: controls use of fancy
387 operations
,
416 such as fsqrt
, fprem
, fsin
, fcos
, fsincos etc.
417 Should be enabled for all targets that always has coprocesor.
*/
418 DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387
, "always_fancy_math_387",
419 ~
(m_386 | m_486 | m_LAKEMONT
))
421 /* X86_TUNE_UNROLL_STRLEN
: Produce (quite lame
) unrolled sequence for
422 inline strlen. This affects only
-minline
-all
-stringops mode. By
423 default we always dispatch to a library since our internal strlen
425 DEF_TUNE (X86_TUNE_UNROLL_STRLEN
, "unroll_strlen", ~m_386
)
427 /* X86_TUNE_SHIFT1
: Enables use of short encoding of
"sal reg" instead of
428 longer
"sal $1, reg".
*/
429 DEF_TUNE (X86_TUNE_SHIFT1
, "shift1", ~m_486
)
431 /* X86_TUNE_ZERO_EXTEND_WITH_AND
: Use
AND instruction instead
433 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND
, "zero_extend_with_and",
436 /* X86_TUNE_PROMOTE_HIMODE_IMUL
: Modern CPUs have same latency for HImode
437 and SImode multiply
, but
386 and
486 do HImode multiply faster.
*/
438 DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL
, "promote_himode_imul",
441 /* X86_TUNE_FAST_PREFIX
: Enable demoting some
32bit or
64bit arithmetic
442 into
16bit
/8bit when resulting sequence is shorter. For example
443 for
"and $-65536, reg" to
16bit store of
0.
*/
444 DEF_TUNE (X86_TUNE_FAST_PREFIX
, "fast_prefix",
445 ~
(m_386 | m_486 | m_PENT | m_LAKEMONT
))
447 /* X86_TUNE_READ_MODIFY_WRITE
: Enable use of read modify write instructions
448 such as
"add $1, mem".
*/
449 DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE
, "read_modify_write",
450 ~
(m_PENT | m_LAKEMONT
))
452 /* X86_TUNE_MOVE_M1_VIA_OR
: On pentiums
, it is faster to load
-1 via
OR
454 DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR
, "move_m1_via_or", m_PENT | m_LAKEMONT
)
456 /* X86_TUNE_NOT_UNPAIRABLE
: NOT is not pairable on Pentium
, while XOR is
,
457 but one byte longer.
*/
458 DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE
, "not_unpairable", m_PENT | m_LAKEMONT
)
460 /* X86_TUNE_PARTIAL_REG_STALL
: Pentium pro
, unlike later chips
, handled
461 use of partial registers by renaming. This improved performance of
16bit
462 code where upper halves of registers are not used. It also leads to
463 an penalty whenever a
16bit store is followed by
32bit use. This flag
464 disables production of such sequences in common cases.
465 See also X86_TUNE_HIMODE_MATH.
467 In current implementation the partial register stalls are not eliminated
468 very well
- they can be introduced via subregs synthesized by combine
469 and can happen in caller
/callee saving sequences.
*/
470 DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL
, "partial_reg_stall", m_PPRO
)
472 /* X86_TUNE_PROMOTE_QIMODE
: When it is cheap
, turn
8bit arithmetic to
473 corresponding
32bit arithmetic.
*/
474 DEF_TUNE (X86_TUNE_PROMOTE_QIMODE
, "promote_qimode",
477 /* X86_TUNE_PROMOTE_HI_REGS
: Same
, but for
16bit artihmetic. Again we avoid
478 partial register stalls on PentiumPro targets.
*/
479 DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS
, "promote_hi_regs", m_PPRO
)
481 /* X86_TUNE_HIMODE_MATH
: Enable use of
16bit arithmetic.
482 On PPro this flag is meant to avoid partial register stalls.
*/
483 DEF_TUNE (X86_TUNE_HIMODE_MATH
, "himode_math", ~m_PPRO
)
485 /* X86_TUNE_SPLIT_LONG_MOVES
: Avoid instructions moving immediates
486 directly to memory.
*/
487 DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES
, "split_long_moves", m_PPRO
)
489 /* X86_TUNE_USE_XCHGB
: Use xchgb
%rh
,%rl instead of rolw
/rorw $
8,rx.
*/
490 DEF_TUNE (X86_TUNE_USE_XCHGB
, "use_xchgb", m_PENT4
)
492 /* X86_TUNE_USE_MOV0
: Use
"mov $0, reg" instead of
"xor reg, reg" to clear
494 DEF_TUNE (X86_TUNE_USE_MOV0
, "use_mov0", m_K6
)
496 /* X86_TUNE_NOT_VECTORMODE
: On AMD K6
, NOT is vector decoded with memory
497 operand that cannot be represented using a modRM byte. The XOR
498 replacement is long decoded
, so this split helps here as well.
*/
499 DEF_TUNE (X86_TUNE_NOT_VECTORMODE
, "not_vectormode", m_K6
)
501 /* X86_TUNE_AVOID_VECTOR_DECODE
: Enable splitters that avoid vector decoded
502 forms of instructions on K8 targets.
*/
503 DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE
, "avoid_vector_decode",
506 /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI
: Avoid false dependency
507 for bit
-manipulation instructions.
*/
508 DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI
, "avoid_false_dep_for_bmi",
509 m_SANDYBRIDGE | m_HASWELL | m_GENERIC
)
511 /*****************************************************************************/
512 /* This never worked well before.
*/
513 /*****************************************************************************/
515 /* X86_TUNE_BRANCH_PREDICTION_HINTS
: Branch hints were put in P4 based
516 on simulation result. But after P4 was made
, no performance benefit
517 was observed with branch hints. It also increases the code size.
518 As a result
, icc never generates branch hints.
*/
519 DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS
, "branch_prediction_hints", 0U)
521 /* X86_TUNE_QIMODE_MATH
: Enable use of
8bit arithmetic.
*/
522 DEF_TUNE (X86_TUNE_QIMODE_MATH
, "qimode_math", ~
0U)
524 /* X86_TUNE_PROMOTE_QI_REGS
: This enables generic code that promotes all
8bit
525 arithmetic to
32bit via PROMOTE_MODE macro. This code generation scheme
526 is usually used for RISC targets.
*/
527 DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS
, "promote_qi_regs", 0U)
529 /* X86_TUNE_ADJUST_UNROLL
: This enables adjusting the unroll factor based
530 on hardware capabilities. Bdver3 hardware has a loop buffer which makes
531 unrolling small loop less important. For
, such architectures we adjust
532 the unroll factor so that the unrolled loop fits the loop buffer.
*/
533 DEF_TUNE (X86_TUNE_ADJUST_UNROLL
, "adjust_unroll_factor", m_BDVER3 | m_BDVER4
)
535 /* X86_TUNE_ONE_IF_CONV_INSNS
: Restrict a number of cmov insns in
536 if
-converted sequence to one.
*/
537 DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN
, "one_if_conv_insn",
538 m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GENERIC
)