gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "diagnostic-core.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 #include "params.h"
 101 #include "tree-pass.h"
 102 #include "df.h"
 103 #include "valtrack.h"
 104 #include "cgraph.h"
 105 #include "obstack.h"
 106
 107 /* Number of attempts to combine instructions in this function.  */
 108
 109 static int combine_attempts;
 110
 111 /* Number of attempts that got as far as substitution in this function.  */
 112
 113 static int combine_merges;
 114
 115 /* Number of instructions combined with added SETs in this function.  */
 116
 117 static int combine_extras;
 118
 119 /* Number of instructions combined in this function.  */
 120
 121 static int combine_successes;
 122
 123 /* Totals over entire compilation.  */
 124
 125 static int total_attempts, total_merges, total_extras, total_successes;
 126
 127 /* combine_instructions may try to replace the right hand side of the
 128    second instruction with the value of an associated REG_EQUAL note
 129    before throwing it at try_combine.  That is problematic when there
 130    is a REG_DEAD note for a register used in the old right hand side
 131    and can cause distribute_notes to do wrong things.  This is the
 132    second instruction if it has been so modified, null otherwise.  */
 133
 134 static rtx i2mod;
 135
 136 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 137
 138 static rtx i2mod_old_rhs;
 139
 140 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 141
 142 static rtx i2mod_new_rhs;
 143 \f
 144 typedef struct reg_stat_struct {
 145   /* Record last point of death of (hard or pseudo) register n.  */
 146   rtx                           last_death;
 147
 148   /* Record last point of modification of (hard or pseudo) register n.  */
 149   rtx                           last_set;
 150
 151   /* The next group of fields allows the recording of the last value assigned
 152      to (hard or pseudo) register n.  We use this information to see if an
 153      operation being processed is redundant given a prior operation performed
 154      on the register.  For example, an `and' with a constant is redundant if
 155      all the zero bits are already known to be turned off.
 156
 157      We use an approach similar to that used by cse, but change it in the
 158      following ways:
 159
 160      (1) We do not want to reinitialize at each label.
 161      (2) It is useful, but not critical, to know the actual value assigned
 162          to a register.  Often just its form is helpful.
 163
 164      Therefore, we maintain the following fields:
 165
 166      last_set_value             the last value assigned
 167      last_set_label             records the value of label_tick when the
 168                                 register was assigned
 169      last_set_table_tick        records the value of label_tick when a
 170                                 value using the register is assigned
 171      last_set_invalid           set to nonzero when it is not valid
 172                                 to use the value of this register in some
 173                                 register's value
 174
 175      To understand the usage of these tables, it is important to understand
 176      the distinction between the value in last_set_value being valid and
 177      the register being validly contained in some other expression in the
 178      table.
 179
 180      (The next two parameters are out of date).
 181
 182      reg_stat[i].last_set_value is valid if it is nonzero, and either
 183      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 184
 185      Register I may validly appear in any expression returned for the value
 186      of another register if reg_n_sets[i] is 1.  It may also appear in the
 187      value for register J if reg_stat[j].last_set_invalid is zero, or
 188      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 189
 190      If an expression is found in the table containing a register which may
 191      not validly appear in an expression, the register is replaced by
 192      something that won't match, (clobber (const_int 0)).  */
 193
 194   /* Record last value assigned to (hard or pseudo) register n.  */
 195
 196   rtx                           last_set_value;
 197
 198   /* Record the value of label_tick when an expression involving register n
 199      is placed in last_set_value.  */
 200
 201   int                           last_set_table_tick;
 202
 203   /* Record the value of label_tick when the value for register n is placed in
 204      last_set_value.  */
 205
 206   int                           last_set_label;
 207
 208   /* These fields are maintained in parallel with last_set_value and are
 209      used to store the mode in which the register was last set, the bits
 210      that were known to be zero when it was last set, and the number of
 211      sign bits copies it was known to have when it was last set.  */
 212
 213   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 214   char                          last_set_sign_bit_copies;
 215   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 216
 217   /* Set nonzero if references to register n in expressions should not be
 218      used.  last_set_invalid is set nonzero when this register is being
 219      assigned to and last_set_table_tick == label_tick.  */
 220
 221   char                          last_set_invalid;
 222
 223   /* Some registers that are set more than once and used in more than one
 224      basic block are nevertheless always set in similar ways.  For example,
 225      a QImode register may be loaded from memory in two places on a machine
 226      where byte loads zero extend.
 227
 228      We record in the following fields if a register has some leading bits
 229      that are always equal to the sign bit, and what we know about the
 230      nonzero bits of a register, specifically which bits are known to be
 231      zero.
 232
 233      If an entry is zero, it means that we don't know anything special.  */
 234
 235   unsigned char                 sign_bit_copies;
 236
 237   unsigned HOST_WIDE_INT        nonzero_bits;
 238
 239   /* Record the value of the label_tick when the last truncation
 240      happened.  The field truncated_to_mode is only valid if
 241      truncation_label == label_tick.  */
 242
 243   int                           truncation_label;
 244
 245   /* Record the last truncation seen for this register.  If truncation
 246      is not a nop to this mode we might be able to save an explicit
 247      truncation if we know that value already contains a truncated
 248      value.  */
 249
 250   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 251 } reg_stat_type;
 252
 253
 254 static vec<reg_stat_type> reg_stat;
 255
 256 /* Record the luid of the last insn that invalidated memory
 257    (anything that writes memory, and subroutine calls, but not pushes).  */
 258
 259 static int mem_last_set;
 260
 261 /* Record the luid of the last CALL_INSN
 262    so we can tell whether a potential combination crosses any calls.  */
 263
 264 static int last_call_luid;
 265
 266 /* When `subst' is called, this is the insn that is being modified
 267    (by combining in a previous insn).  The PATTERN of this insn
 268    is still the old pattern partially modified and it should not be
 269    looked at, but this may be used to examine the successors of the insn
 270    to judge whether a simplification is valid.  */
 271
 272 static rtx subst_insn;
 273
 274 /* This is the lowest LUID that `subst' is currently dealing with.
 275    get_last_value will not return a value if the register was set at or
 276    after this LUID.  If not for this mechanism, we could get confused if
 277    I2 or I1 in try_combine were an insn that used the old value of a register
 278    to obtain a new value.  In that case, we might erroneously get the
 279    new value of the register when we wanted the old one.  */
 280
 281 static int subst_low_luid;
 282
 283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 284    must consider all these registers to be always live.  */
 285
 286 static HARD_REG_SET newpat_used_regs;
 287
 288 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 289    insn is the earlier than I2 or I3, combine should rescan starting at
 290    that location.  */
 291
 292 static rtx added_links_insn;
 293
 294 /* Basic block in which we are performing combines.  */
 295 static basic_block this_basic_block;
 296 static bool optimize_this_for_speed_p;
 297
 298 \f
 299 /* Length of the currently allocated uid_insn_cost array.  */
 300
 301 static int max_uid_known;
 302
 303 /* The following array records the insn_rtx_cost for every insn
 304    in the instruction stream.  */
 305
 306 static int *uid_insn_cost;
 307
 308 /* The following array records the LOG_LINKS for every insn in the
 309    instruction stream as struct insn_link pointers.  */
 310
 311 struct insn_link {
 312   rtx insn;
 313   struct insn_link *next;
 314 };
 315
 316 static struct insn_link **uid_log_links;
 317
 318 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 319 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 320
 321 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 322   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 323
 324 /* Links for LOG_LINKS are allocated from this obstack.  */
 325
 326 static struct obstack insn_link_obstack;
 327
 328 /* Allocate a link.  */
 329
 330 static inline struct insn_link *
 331 alloc_insn_link (rtx insn, struct insn_link *next)
 332 {
 333   struct insn_link *l
 334     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 335                                           sizeof (struct insn_link));
 336   l->insn = insn;
 337   l->next = next;
 338   return l;
 339 }
 340
 341 /* Incremented for each basic block.  */
 342
 343 static int label_tick;
 344
 345 /* Reset to label_tick for each extended basic block in scanning order.  */
 346
 347 static int label_tick_ebb_start;
 348
 349 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 350    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 351
 352 static enum machine_mode nonzero_bits_mode;
 353
 354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 355    be safely used.  It is zero while computing them and after combine has
 356    completed.  This former test prevents propagating values based on
 357    previously set values, which can be incorrect if a variable is modified
 358    in a loop.  */
 359
 360 static int nonzero_sign_valid;
 361
 362 \f
 363 /* Record one modification to rtl structure
 364    to be undone by storing old_contents into *where.  */
 365
 366 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 367
 368 struct undo
 369 {
 370   struct undo *next;
 371   enum undo_kind kind;
 372   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 373   union { rtx *r; int *i; struct insn_link **l; } where;
 374 };
 375
 376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 377    num_undo says how many are currently recorded.
 378
 379    other_insn is nonzero if we have modified some other insn in the process
 380    of working on subst_insn.  It must be verified too.  */
 381
 382 struct undobuf
 383 {
 384   struct undo *undos;
 385   struct undo *frees;
 386   rtx other_insn;
 387 };
 388
 389 static struct undobuf undobuf;
 390
 391 /* Number of times the pseudo being substituted for
 392    was found and replaced.  */
 393
 394 static int n_occurrences;
 395
 396 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 397                                          enum machine_mode,
 398                                          unsigned HOST_WIDE_INT,
 399                                          unsigned HOST_WIDE_INT *);
 400 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                                 enum machine_mode,
 402                                                 unsigned int, unsigned int *);
 403 static void do_SUBST (rtx *, rtx);
 404 static void do_SUBST_INT (int *, int);
 405 static void init_reg_last (void);
 406 static void setup_incoming_promotions (rtx);
 407 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 408 static int cant_combine_insn_p (rtx);
 409 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 410 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 411 static int contains_muldiv (rtx);
 412 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 413 static void undo_all (void);
 414 static void undo_commit (void);
 415 static rtx *find_split_point (rtx *, rtx, bool);
 416 static rtx subst (rtx, rtx, rtx, int, int, int);
 417 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 418 static rtx simplify_if_then_else (rtx);
 419 static rtx simplify_set (rtx);
 420 static rtx simplify_logical (rtx);
 421 static rtx expand_compound_operation (rtx);
 422 static const_rtx expand_field_assignment (const_rtx);
 423 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 424                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 425 static rtx extract_left_shift (rtx, int);
 426 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 427                               unsigned HOST_WIDE_INT *);
 428 static rtx canon_reg_for_combine (rtx, rtx);
 429 static rtx force_to_mode (rtx, enum machine_mode,
 430                           unsigned HOST_WIDE_INT, int);
 431 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 432 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 433 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 434 static rtx make_field_assignment (rtx);
 435 static rtx apply_distributive_law (rtx);
 436 static rtx distribute_and_simplify_rtx (rtx, int);
 437 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 438                                      unsigned HOST_WIDE_INT);
 439 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 440                                    unsigned HOST_WIDE_INT);
 441 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 442                             HOST_WIDE_INT, enum machine_mode, int *);
 443 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 444 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 445                                  int);
 446 static int recog_for_combine (rtx *, rtx, rtx *);
 447 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 448 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 449 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 450 static void update_table_tick (rtx);
 451 static void record_value_for_reg (rtx, rtx, rtx);
 452 static void check_promoted_subreg (rtx, rtx);
 453 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 454 static void record_dead_and_set_regs (rtx);
 455 static int get_last_value_validate (rtx *, rtx, int, int);
 456 static rtx get_last_value (const_rtx);
 457 static int use_crosses_set_p (const_rtx, int);
 458 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 459 static int reg_dead_at_p (rtx, rtx);
 460 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 461 static int reg_bitfield_target_p (rtx, rtx);
 462 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 463 static void distribute_links (struct insn_link *);
 464 static void mark_used_regs_combine (rtx);
 465 static void record_promoted_value (rtx, rtx);
 466 static int unmentioned_reg_p_1 (rtx *, void *);
 467 static bool unmentioned_reg_p (rtx, rtx);
 468 static int record_truncated_value (rtx *, void *);
 469 static void record_truncated_values (rtx *, void *);
 470 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 471 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 472 \f
 473
 474 /* It is not safe to use ordinary gen_lowpart in combine.
 475    See comments in gen_lowpart_for_combine.  */
 476 #undef RTL_HOOKS_GEN_LOWPART
 477 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 478
 479 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 482
 483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 484 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 485
 486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 488
 489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 491
 492 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 493
 494 \f
 495 /* Convenience wrapper for the canonicalize_comparison target hook.
 496    Target hooks cannot use enum rtx_code.  */
 497 static inline void
 498 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 499                                 bool op0_preserve_value)
 500 {
 501   int code_int = (int)*code;
 502   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 503   *code = (enum rtx_code)code_int;
 504 }
 505
 506 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 507    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 508    This is a wrapper around split_insns which ensures that the
 509    reg_stat vector is made larger if the splitter creates a new
 510    register.  */
 511
 512 static rtx
 513 combine_split_insns (rtx pattern, rtx insn)
 514 {
 515   rtx ret;
 516   unsigned int nregs;
 517
 518   ret = split_insns (pattern, insn);
 519   nregs = max_reg_num ();
 520   if (nregs > reg_stat.length ())
 521     reg_stat.safe_grow_cleared (nregs);
 522   return ret;
 523 }
 524
 525 /* This is used by find_single_use to locate an rtx in LOC that
 526    contains exactly one use of DEST, which is typically either a REG
 527    or CC0.  It returns a pointer to the innermost rtx expression
 528    containing DEST.  Appearances of DEST that are being used to
 529    totally replace it are not counted.  */
 530
 531 static rtx *
 532 find_single_use_1 (rtx dest, rtx *loc)
 533 {
 534   rtx x = *loc;
 535   enum rtx_code code = GET_CODE (x);
 536   rtx *result = NULL;
 537   rtx *this_result;
 538   int i;
 539   const char *fmt;
 540
 541   switch (code)
 542     {
 543     case CONST:
 544     case LABEL_REF:
 545     case SYMBOL_REF:
 546     CASE_CONST_ANY:
 547     case CLOBBER:
 548       return 0;
 549
 550     case SET:
 551       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 552          of a REG that occupies all of the REG, the insn uses DEST if
 553          it is mentioned in the destination or the source.  Otherwise, we
 554          need just check the source.  */
 555       if (GET_CODE (SET_DEST (x)) != CC0
 556           && GET_CODE (SET_DEST (x)) != PC
 557           && !REG_P (SET_DEST (x))
 558           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 559                 && REG_P (SUBREG_REG (SET_DEST (x)))
 560                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 561                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 562                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 563                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 564         break;
 565
 566       return find_single_use_1 (dest, &SET_SRC (x));
 567
 568     case MEM:
 569     case SUBREG:
 570       return find_single_use_1 (dest, &XEXP (x, 0));
 571
 572     default:
 573       break;
 574     }
 575
 576   /* If it wasn't one of the common cases above, check each expression and
 577      vector of this code.  Look for a unique usage of DEST.  */
 578
 579   fmt = GET_RTX_FORMAT (code);
 580   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 581     {
 582       if (fmt[i] == 'e')
 583         {
 584           if (dest == XEXP (x, i)
 585               || (REG_P (dest) && REG_P (XEXP (x, i))
 586                   && REGNO (dest) == REGNO (XEXP (x, i))))
 587             this_result = loc;
 588           else
 589             this_result = find_single_use_1 (dest, &XEXP (x, i));
 590
 591           if (result == NULL)
 592             result = this_result;
 593           else if (this_result)
 594             /* Duplicate usage.  */
 595             return NULL;
 596         }
 597       else if (fmt[i] == 'E')
 598         {
 599           int j;
 600
 601           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 602             {
 603               if (XVECEXP (x, i, j) == dest
 604                   || (REG_P (dest)
 605                       && REG_P (XVECEXP (x, i, j))
 606                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 607                 this_result = loc;
 608               else
 609                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 610
 611               if (result == NULL)
 612                 result = this_result;
 613               else if (this_result)
 614                 return NULL;
 615             }
 616         }
 617     }
 618
 619   return result;
 620 }
 621
 622
 623 /* See if DEST, produced in INSN, is used only a single time in the
 624    sequel.  If so, return a pointer to the innermost rtx expression in which
 625    it is used.
 626
 627    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 628
 629    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 630    care about REG_DEAD notes or LOG_LINKS.
 631
 632    Otherwise, we find the single use by finding an insn that has a
 633    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 634    only referenced once in that insn, we know that it must be the first
 635    and last insn referencing DEST.  */
 636
 637 static rtx *
 638 find_single_use (rtx dest, rtx insn, rtx *ploc)
 639 {
 640   basic_block bb;
 641   rtx next;
 642   rtx *result;
 643   struct insn_link *link;
 644
 645 #ifdef HAVE_cc0
 646   if (dest == cc0_rtx)
 647     {
 648       next = NEXT_INSN (insn);
 649       if (next == 0
 650           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 651         return 0;
 652
 653       result = find_single_use_1 (dest, &PATTERN (next));
 654       if (result && ploc)
 655         *ploc = next;
 656       return result;
 657     }
 658 #endif
 659
 660   if (!REG_P (dest))
 661     return 0;
 662
 663   bb = BLOCK_FOR_INSN (insn);
 664   for (next = NEXT_INSN (insn);
 665        next && BLOCK_FOR_INSN (next) == bb;
 666        next = NEXT_INSN (next))
 667     if (INSN_P (next) && dead_or_set_p (next, dest))
 668       {
 669         FOR_EACH_LOG_LINK (link, next)
 670           if (link->insn == insn)
 671             break;
 672
 673         if (link)
 674           {
 675             result = find_single_use_1 (dest, &PATTERN (next));
 676             if (ploc)
 677               *ploc = next;
 678             return result;
 679           }
 680       }
 681
 682   return 0;
 683 }
 684 \f
 685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 686    insn.  The substitution can be undone by undo_all.  If INTO is already
 687    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 688    also call SUBST, we have to compute it before we put anything into
 689    the undo table.  */
 690
 691 static void
 692 do_SUBST (rtx *into, rtx newval)
 693 {
 694   struct undo *buf;
 695   rtx oldval = *into;
 696
 697   if (oldval == newval)
 698     return;
 699
 700   /* We'd like to catch as many invalid transformations here as
 701      possible.  Unfortunately, there are way too many mode changes
 702      that are perfectly valid, so we'd waste too much effort for
 703      little gain doing the checks here.  Focus on catching invalid
 704      transformations involving integer constants.  */
 705   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 706       && CONST_INT_P (newval))
 707     {
 708       /* Sanity check that we're replacing oldval with a CONST_INT
 709          that is a valid sign-extension for the original mode.  */
 710       gcc_assert (INTVAL (newval)
 711                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 712
 713       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 714          CONST_INT is not valid, because after the replacement, the
 715          original mode would be gone.  Unfortunately, we can't tell
 716          when do_SUBST is called to replace the operand thereof, so we
 717          perform this test on oldval instead, checking whether an
 718          invalid replacement took place before we got here.  */
 719       gcc_assert (!(GET_CODE (oldval) == SUBREG
 720                     && CONST_INT_P (SUBREG_REG (oldval))));
 721       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 722                     && CONST_INT_P (XEXP (oldval, 0))));
 723     }
 724
 725   if (undobuf.frees)
 726     buf = undobuf.frees, undobuf.frees = buf->next;
 727   else
 728     buf = XNEW (struct undo);
 729
 730   buf->kind = UNDO_RTX;
 731   buf->where.r = into;
 732   buf->old_contents.r = oldval;
 733   *into = newval;
 734
 735   buf->next = undobuf.undos, undobuf.undos = buf;
 736 }
 737
 738 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 739
 740 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 741    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 742    not safe.  */
 743
 744 static void
 745 do_SUBST_INT (int *into, int newval)
 746 {
 747   struct undo *buf;
 748   int oldval = *into;
 749
 750   if (oldval == newval)
 751     return;
 752
 753   if (undobuf.frees)
 754     buf = undobuf.frees, undobuf.frees = buf->next;
 755   else
 756     buf = XNEW (struct undo);
 757
 758   buf->kind = UNDO_INT;
 759   buf->where.i = into;
 760   buf->old_contents.i = oldval;
 761   *into = newval;
 762
 763   buf->next = undobuf.undos, undobuf.undos = buf;
 764 }
 765
 766 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 767
 768 /* Similar to SUBST, but just substitute the mode.  This is used when
 769    changing the mode of a pseudo-register, so that any other
 770    references to the entry in the regno_reg_rtx array will change as
 771    well.  */
 772
 773 static void
 774 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 775 {
 776   struct undo *buf;
 777   enum machine_mode oldval = GET_MODE (*into);
 778
 779   if (oldval == newval)
 780     return;
 781
 782   if (undobuf.frees)
 783     buf = undobuf.frees, undobuf.frees = buf->next;
 784   else
 785     buf = XNEW (struct undo);
 786
 787   buf->kind = UNDO_MODE;
 788   buf->where.r = into;
 789   buf->old_contents.m = oldval;
 790   adjust_reg_mode (*into, newval);
 791
 792   buf->next = undobuf.undos, undobuf.undos = buf;
 793 }
 794
 795 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE (&(INTO), (NEWVAL))
 796
 797 #ifndef HAVE_cc0
 798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 799
 800 static void
 801 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 802 {
 803   struct undo *buf;
 804   struct insn_link * oldval = *into;
 805
 806   if (oldval == newval)
 807     return;
 808
 809   if (undobuf.frees)
 810     buf = undobuf.frees, undobuf.frees = buf->next;
 811   else
 812     buf = XNEW (struct undo);
 813
 814   buf->kind = UNDO_LINKS;
 815   buf->where.l = into;
 816   buf->old_contents.l = oldval;
 817   *into = newval;
 818
 819   buf->next = undobuf.undos, undobuf.undos = buf;
 820 }
 821
 822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 823 #endif
 824 \f
 825 /* Subroutine of try_combine.  Determine whether the replacement patterns
 826    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 827    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 828    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 829    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 830    of all the instructions can be estimated and the replacements are more
 831    expensive than the original sequence.  */
 832
 833 static bool
 834 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 835                        rtx newi2pat, rtx newotherpat)
 836 {
 837   int i0_cost, i1_cost, i2_cost, i3_cost;
 838   int new_i2_cost, new_i3_cost;
 839   int old_cost, new_cost;
 840
 841   /* Lookup the original insn_rtx_costs.  */
 842   i2_cost = INSN_COST (i2);
 843   i3_cost = INSN_COST (i3);
 844
 845   if (i1)
 846     {
 847       i1_cost = INSN_COST (i1);
 848       if (i0)
 849         {
 850           i0_cost = INSN_COST (i0);
 851           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 852                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 853         }
 854       else
 855         {
 856           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 857                       ? i1_cost + i2_cost + i3_cost : 0);
 858           i0_cost = 0;
 859         }
 860     }
 861   else
 862     {
 863       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 864       i1_cost = i0_cost = 0;
 865     }
 866
 867   /* Calculate the replacement insn_rtx_costs.  */
 868   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 869   if (newi2pat)
 870     {
 871       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 872       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 873                  ? new_i2_cost + new_i3_cost : 0;
 874     }
 875   else
 876     {
 877       new_cost = new_i3_cost;
 878       new_i2_cost = 0;
 879     }
 880
 881   if (undobuf.other_insn)
 882     {
 883       int old_other_cost, new_other_cost;
 884
 885       old_other_cost = INSN_COST (undobuf.other_insn);
 886       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 887       if (old_other_cost > 0 && new_other_cost > 0)
 888         {
 889           old_cost += old_other_cost;
 890           new_cost += new_other_cost;
 891         }
 892       else
 893         old_cost = 0;
 894     }
 895
 896   /* Disallow this combination if both new_cost and old_cost are greater than
 897      zero, and new_cost is greater than old cost.  */
 898   if (old_cost > 0 && new_cost > old_cost)
 899     {
 900       if (dump_file)
 901         {
 902           if (i0)
 903             {
 904               fprintf (dump_file,
 905                        "rejecting combination of insns %d, %d, %d and %d\n",
 906                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 907                        INSN_UID (i3));
 908               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 909                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 910             }
 911           else if (i1)
 912             {
 913               fprintf (dump_file,
 914                        "rejecting combination of insns %d, %d and %d\n",
 915                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 916               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 917                        i1_cost, i2_cost, i3_cost, old_cost);
 918             }
 919           else
 920             {
 921               fprintf (dump_file,
 922                        "rejecting combination of insns %d and %d\n",
 923                        INSN_UID (i2), INSN_UID (i3));
 924               fprintf (dump_file, "original costs %d + %d = %d\n",
 925                        i2_cost, i3_cost, old_cost);
 926             }
 927
 928           if (newi2pat)
 929             {
 930               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 931                        new_i2_cost, new_i3_cost, new_cost);
 932             }
 933           else
 934             fprintf (dump_file, "replacement cost %d\n", new_cost);
 935         }
 936
 937       return false;
 938     }
 939
 940   /* Update the uid_insn_cost array with the replacement costs.  */
 941   INSN_COST (i2) = new_i2_cost;
 942   INSN_COST (i3) = new_i3_cost;
 943   if (i1)
 944     {
 945       INSN_COST (i1) = 0;
 946       if (i0)
 947         INSN_COST (i0) = 0;
 948     }
 949
 950   return true;
 951 }
 952
 953
 954 /* Delete any insns that copy a register to itself.  */
 955
 956 static void
 957 delete_noop_moves (void)
 958 {
 959   rtx insn, next;
 960   basic_block bb;
 961
 962   FOR_EACH_BB (bb)
 963     {
 964       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 965         {
 966           next = NEXT_INSN (insn);
 967           if (INSN_P (insn) && noop_move_p (insn))
 968             {
 969               if (dump_file)
 970                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 971
 972               delete_insn_and_edges (insn);
 973             }
 974         }
 975     }
 976 }
 977
 978 \f
 979 /* Fill in log links field for all insns.  */
 980
 981 static void
 982 create_log_links (void)
 983 {
 984   basic_block bb;
 985   rtx *next_use, insn;
 986   df_ref *def_vec, *use_vec;
 987
 988   next_use = XCNEWVEC (rtx, max_reg_num ());
 989
 990   /* Pass through each block from the end, recording the uses of each
 991      register and establishing log links when def is encountered.
 992      Note that we do not clear next_use array in order to save time,
 993      so we have to test whether the use is in the same basic block as def.
 994
 995      There are a few cases below when we do not consider the definition or
 996      usage -- these are taken from original flow.c did. Don't ask me why it is
 997      done this way; I don't know and if it works, I don't want to know.  */
 998
 999   FOR_EACH_BB (bb)
1000     {
1001       FOR_BB_INSNS_REVERSE (bb, insn)
1002         {
1003           if (!NONDEBUG_INSN_P (insn))
1004             continue;
1005
1006           /* Log links are created only once.  */
1007           gcc_assert (!LOG_LINKS (insn));
1008
1009           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1010             {
1011               df_ref def = *def_vec;
1012               int regno = DF_REF_REGNO (def);
1013               rtx use_insn;
1014
1015               if (!next_use[regno])
1016                 continue;
1017
1018               /* Do not consider if it is pre/post modification in MEM.  */
1019               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1020                 continue;
1021
1022               /* Do not make the log link for frame pointer.  */
1023               if ((regno == FRAME_POINTER_REGNUM
1024                    && (! reload_completed || frame_pointer_needed))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026                   || (regno == HARD_FRAME_POINTER_REGNUM
1027                       && (! reload_completed || frame_pointer_needed))
1028 #endif
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1031 #endif
1032                   )
1033                 continue;
1034
1035               use_insn = next_use[regno];
1036               if (BLOCK_FOR_INSN (use_insn) == bb)
1037                 {
1038                   /* flow.c claimed:
1039
1040                      We don't build a LOG_LINK for hard registers contained
1041                      in ASM_OPERANDs.  If these registers get replaced,
1042                      we might wind up changing the semantics of the insn,
1043                      even if reload can make what appear to be valid
1044                      assignments later.  */
1045                   if (regno >= FIRST_PSEUDO_REGISTER
1046                       || asm_noperands (PATTERN (use_insn)) < 0)
1047                     {
1048                       /* Don't add duplicate links between instructions.  */
1049                       struct insn_link *links;
1050                       FOR_EACH_LOG_LINK (links, use_insn)
1051                         if (insn == links->insn)
1052                           break;
1053
1054                       if (!links)
1055                         LOG_LINKS (use_insn)
1056                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1057                     }
1058                 }
1059               next_use[regno] = NULL_RTX;
1060             }
1061
1062           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1063             {
1064               df_ref use = *use_vec;
1065               int regno = DF_REF_REGNO (use);
1066
1067               /* Do not consider the usage of the stack pointer
1068                  by function call.  */
1069               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1070                 continue;
1071
1072               next_use[regno] = insn;
1073             }
1074         }
1075     }
1076
1077   free (next_use);
1078 }
1079
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1081    true if we found a LOG_LINK that proves that A feeds B.  This only works
1082    if there are no instructions between A and B which could have a link
1083    depending on A, since in that case we would not record a link for B.
1084    We also check the implicit dependency created by a cc0 setter/user
1085    pair.  */
1086
1087 static bool
1088 insn_a_feeds_b (rtx a, rtx b)
1089 {
1090   struct insn_link *links;
1091   FOR_EACH_LOG_LINK (links, b)
1092     if (links->insn == a)
1093       return true;
1094 #ifdef HAVE_cc0
1095   if (sets_cc0_p (a))
1096     return true;
1097 #endif
1098   return false;
1099 }
1100 \f
1101 /* Main entry point for combiner.  F is the first insn of the function.
1102    NREGS is the first unused pseudo-reg number.
1103
1104    Return nonzero if the combiner has turned an indirect jump
1105    instruction into a direct jump.  */
1106 static int
1107 combine_instructions (rtx f, unsigned int nregs)
1108 {
1109   rtx insn, next;
1110 #ifdef HAVE_cc0
1111   rtx prev;
1112 #endif
1113   struct insn_link *links, *nextlinks;
1114   rtx first;
1115   basic_block last_bb;
1116
1117   int new_direct_jump_p = 0;
1118
1119   for (first = f; first && !INSN_P (first); )
1120     first = NEXT_INSN (first);
1121   if (!first)
1122     return 0;
1123
1124   combine_attempts = 0;
1125   combine_merges = 0;
1126   combine_extras = 0;
1127   combine_successes = 0;
1128
1129   rtl_hooks = combine_rtl_hooks;
1130
1131   reg_stat.safe_grow_cleared (nregs);
1132
1133   init_recog_no_volatile ();
1134
1135   /* Allocate array for insn info.  */
1136   max_uid_known = get_max_uid ();
1137   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1138   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1139   gcc_obstack_init (&insn_link_obstack);
1140
1141   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1142
1143   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1144      problems when, for example, we have j <<= 1 in a loop.  */
1145
1146   nonzero_sign_valid = 0;
1147   label_tick = label_tick_ebb_start = 1;
1148
1149   /* Scan all SETs and see if we can deduce anything about what
1150      bits are known to be zero for some registers and how many copies
1151      of the sign bit are known to exist for those registers.
1152
1153      Also set any known values so that we can use it while searching
1154      for what bits are known to be set.  */
1155
1156   setup_incoming_promotions (first);
1157   /* Allow the entry block and the first block to fall into the same EBB.
1158      Conceptually the incoming promotions are assigned to the entry block.  */
1159   last_bb = ENTRY_BLOCK_PTR;
1160
1161   create_log_links ();
1162   FOR_EACH_BB (this_basic_block)
1163     {
1164       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165       last_call_luid = 0;
1166       mem_last_set = -1;
1167
1168       label_tick++;
1169       if (!single_pred_p (this_basic_block)
1170           || single_pred (this_basic_block) != last_bb)
1171         label_tick_ebb_start = label_tick;
1172       last_bb = this_basic_block;
1173
1174       FOR_BB_INSNS (this_basic_block, insn)
1175         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1176           {
1177 #ifdef AUTO_INC_DEC
1178             rtx links;
1179 #endif
1180
1181             subst_low_luid = DF_INSN_LUID (insn);
1182             subst_insn = insn;
1183
1184             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1185                          insn);
1186             record_dead_and_set_regs (insn);
1187
1188 #ifdef AUTO_INC_DEC
1189             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1190               if (REG_NOTE_KIND (links) == REG_INC)
1191                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1192                                                   insn);
1193 #endif
1194
1195             /* Record the current insn_rtx_cost of this instruction.  */
1196             if (NONJUMP_INSN_P (insn))
1197               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1198                                                 optimize_this_for_speed_p);
1199             if (dump_file)
1200               fprintf (dump_file, "insn_cost %d: %d\n",
1201                        INSN_UID (insn), INSN_COST (insn));
1202           }
1203     }
1204
1205   nonzero_sign_valid = 1;
1206
1207   /* Now scan all the insns in forward order.  */
1208   label_tick = label_tick_ebb_start = 1;
1209   init_reg_last ();
1210   setup_incoming_promotions (first);
1211   last_bb = ENTRY_BLOCK_PTR;
1212
1213   FOR_EACH_BB (this_basic_block)
1214     {
1215       rtx last_combined_insn = NULL_RTX;
1216       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217       last_call_luid = 0;
1218       mem_last_set = -1;
1219
1220       label_tick++;
1221       if (!single_pred_p (this_basic_block)
1222           || single_pred (this_basic_block) != last_bb)
1223         label_tick_ebb_start = label_tick;
1224       last_bb = this_basic_block;
1225
1226       rtl_profile_for_bb (this_basic_block);
1227       for (insn = BB_HEAD (this_basic_block);
1228            insn != NEXT_INSN (BB_END (this_basic_block));
1229            insn = next ? next : NEXT_INSN (insn))
1230         {
1231           next = 0;
1232           if (NONDEBUG_INSN_P (insn))
1233             {
1234               while (last_combined_insn
1235                      && INSN_DELETED_P (last_combined_insn))
1236                 last_combined_insn = PREV_INSN (last_combined_insn);
1237               if (last_combined_insn == NULL_RTX
1238                   || BARRIER_P (last_combined_insn)
1239                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1240                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1241                 last_combined_insn = insn;
1242
1243               /* See if we know about function return values before this
1244                  insn based upon SUBREG flags.  */
1245               check_promoted_subreg (insn, PATTERN (insn));
1246
1247               /* See if we can find hardregs and subreg of pseudos in
1248                  narrower modes.  This could help turning TRUNCATEs
1249                  into SUBREGs.  */
1250               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1251
1252               /* Try this insn with each insn it links back to.  */
1253
1254               FOR_EACH_LOG_LINK (links, insn)
1255                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1256                                          NULL_RTX, &new_direct_jump_p,
1257                                          last_combined_insn)) != 0)
1258                   goto retry;
1259
1260               /* Try each sequence of three linked insns ending with this one.  */
1261
1262               FOR_EACH_LOG_LINK (links, insn)
1263                 {
1264                   rtx link = links->insn;
1265
1266                   /* If the linked insn has been replaced by a note, then there
1267                      is no point in pursuing this chain any further.  */
1268                   if (NOTE_P (link))
1269                     continue;
1270
1271                   FOR_EACH_LOG_LINK (nextlinks, link)
1272                     if ((next = try_combine (insn, link, nextlinks->insn,
1273                                              NULL_RTX, &new_direct_jump_p,
1274                                              last_combined_insn)) != 0)
1275                       goto retry;
1276                 }
1277
1278 #ifdef HAVE_cc0
1279               /* Try to combine a jump insn that uses CC0
1280                  with a preceding insn that sets CC0, and maybe with its
1281                  logical predecessor as well.
1282                  This is how we make decrement-and-branch insns.
1283                  We need this special code because data flow connections
1284                  via CC0 do not get entered in LOG_LINKS.  */
1285
1286               if (JUMP_P (insn)
1287                   && (prev = prev_nonnote_insn (insn)) != 0
1288                   && NONJUMP_INSN_P (prev)
1289                   && sets_cc0_p (PATTERN (prev)))
1290                 {
1291                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1292                                            &new_direct_jump_p,
1293                                            last_combined_insn)) != 0)
1294                     goto retry;
1295
1296                   FOR_EACH_LOG_LINK (nextlinks, prev)
1297                     if ((next = try_combine (insn, prev, nextlinks->insn,
1298                                              NULL_RTX, &new_direct_jump_p,
1299                                              last_combined_insn)) != 0)
1300                       goto retry;
1301                 }
1302
1303               /* Do the same for an insn that explicitly references CC0.  */
1304               if (NONJUMP_INSN_P (insn)
1305                   && (prev = prev_nonnote_insn (insn)) != 0
1306                   && NONJUMP_INSN_P (prev)
1307                   && sets_cc0_p (PATTERN (prev))
1308                   && GET_CODE (PATTERN (insn)) == SET
1309                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1310                 {
1311                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1312                                            &new_direct_jump_p,
1313                                            last_combined_insn)) != 0)
1314                     goto retry;
1315
1316                   FOR_EACH_LOG_LINK (nextlinks, prev)
1317                     if ((next = try_combine (insn, prev, nextlinks->insn,
1318                                              NULL_RTX, &new_direct_jump_p,
1319                                              last_combined_insn)) != 0)
1320                       goto retry;
1321                 }
1322
1323               /* Finally, see if any of the insns that this insn links to
1324                  explicitly references CC0.  If so, try this insn, that insn,
1325                  and its predecessor if it sets CC0.  */
1326               FOR_EACH_LOG_LINK (links, insn)
1327                 if (NONJUMP_INSN_P (links->insn)
1328                     && GET_CODE (PATTERN (links->insn)) == SET
1329                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1330                     && (prev = prev_nonnote_insn (links->insn)) != 0
1331                     && NONJUMP_INSN_P (prev)
1332                     && sets_cc0_p (PATTERN (prev))
1333                     && (next = try_combine (insn, links->insn,
1334                                             prev, NULL_RTX, &new_direct_jump_p,
1335                                             last_combined_insn)) != 0)
1336                   goto retry;
1337 #endif
1338
1339               /* Try combining an insn with two different insns whose results it
1340                  uses.  */
1341               FOR_EACH_LOG_LINK (links, insn)
1342                 for (nextlinks = links->next; nextlinks;
1343                      nextlinks = nextlinks->next)
1344                   if ((next = try_combine (insn, links->insn,
1345                                            nextlinks->insn, NULL_RTX,
1346                                            &new_direct_jump_p,
1347                                            last_combined_insn)) != 0)
1348                     goto retry;
1349
1350               /* Try four-instruction combinations.  */
1351               FOR_EACH_LOG_LINK (links, insn)
1352                 {
1353                   struct insn_link *next1;
1354                   rtx link = links->insn;
1355
1356                   /* If the linked insn has been replaced by a note, then there
1357                      is no point in pursuing this chain any further.  */
1358                   if (NOTE_P (link))
1359                     continue;
1360
1361                   FOR_EACH_LOG_LINK (next1, link)
1362                     {
1363                       rtx link1 = next1->insn;
1364                       if (NOTE_P (link1))
1365                         continue;
1366                       /* I0 -> I1 -> I2 -> I3.  */
1367                       FOR_EACH_LOG_LINK (nextlinks, link1)
1368                         if ((next = try_combine (insn, link, link1,
1369                                                  nextlinks->insn,
1370                                                  &new_direct_jump_p,
1371                                                  last_combined_insn)) != 0)
1372                           goto retry;
1373                       /* I0, I1 -> I2, I2 -> I3.  */
1374                       for (nextlinks = next1->next; nextlinks;
1375                            nextlinks = nextlinks->next)
1376                         if ((next = try_combine (insn, link, link1,
1377                                                  nextlinks->insn,
1378                                                  &new_direct_jump_p,
1379                                                  last_combined_insn)) != 0)
1380                           goto retry;
1381                     }
1382
1383                   for (next1 = links->next; next1; next1 = next1->next)
1384                     {
1385                       rtx link1 = next1->insn;
1386                       if (NOTE_P (link1))
1387                         continue;
1388                       /* I0 -> I2; I1, I2 -> I3.  */
1389                       FOR_EACH_LOG_LINK (nextlinks, link)
1390                         if ((next = try_combine (insn, link, link1,
1391                                                  nextlinks->insn,
1392                                                  &new_direct_jump_p,
1393                                                  last_combined_insn)) != 0)
1394                           goto retry;
1395                       /* I0 -> I1; I1, I2 -> I3.  */
1396                       FOR_EACH_LOG_LINK (nextlinks, link1)
1397                         if ((next = try_combine (insn, link, link1,
1398                                                  nextlinks->insn,
1399                                                  &new_direct_jump_p,
1400                                                  last_combined_insn)) != 0)
1401                           goto retry;
1402                     }
1403                 }
1404
1405               /* Try this insn with each REG_EQUAL note it links back to.  */
1406               FOR_EACH_LOG_LINK (links, insn)
1407                 {
1408                   rtx set, note;
1409                   rtx temp = links->insn;
1410                   if ((set = single_set (temp)) != 0
1411                       && (note = find_reg_equal_equiv_note (temp)) != 0
1412                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1413                       /* Avoid using a register that may already been marked
1414                          dead by an earlier instruction.  */
1415                       && ! unmentioned_reg_p (note, SET_SRC (set))
1416                       && (GET_MODE (note) == VOIDmode
1417                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1418                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1419                     {
1420                       /* Temporarily replace the set's source with the
1421                          contents of the REG_EQUAL note.  The insn will
1422                          be deleted or recognized by try_combine.  */
1423                       rtx orig = SET_SRC (set);
1424                       SET_SRC (set) = note;
1425                       i2mod = temp;
1426                       i2mod_old_rhs = copy_rtx (orig);
1427                       i2mod_new_rhs = copy_rtx (note);
1428                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1429                                           &new_direct_jump_p,
1430                                           last_combined_insn);
1431                       i2mod = NULL_RTX;
1432                       if (next)
1433                         goto retry;
1434                       SET_SRC (set) = orig;
1435                     }
1436                 }
1437
1438               if (!NOTE_P (insn))
1439                 record_dead_and_set_regs (insn);
1440
1441             retry:
1442               ;
1443             }
1444         }
1445     }
1446
1447   default_rtl_profile ();
1448   clear_bb_flags ();
1449   new_direct_jump_p |= purge_all_dead_edges ();
1450   delete_noop_moves ();
1451
1452   /* Clean up.  */
1453   obstack_free (&insn_link_obstack, NULL);
1454   free (uid_log_links);
1455   free (uid_insn_cost);
1456   reg_stat.release ();
1457
1458   {
1459     struct undo *undo, *next;
1460     for (undo = undobuf.frees; undo; undo = next)
1461       {
1462         next = undo->next;
1463         free (undo);
1464       }
1465     undobuf.frees = 0;
1466   }
1467
1468   total_attempts += combine_attempts;
1469   total_merges += combine_merges;
1470   total_extras += combine_extras;
1471   total_successes += combine_successes;
1472
1473   nonzero_sign_valid = 0;
1474   rtl_hooks = general_rtl_hooks;
1475
1476   /* Make recognizer allow volatile MEMs again.  */
1477   init_recog ();
1478
1479   return new_direct_jump_p;
1480 }
1481
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1483
1484 static void
1485 init_reg_last (void)
1486 {
1487   unsigned int i;
1488   reg_stat_type *p;
1489
1490   FOR_EACH_VEC_ELT (reg_stat, i, p)
1491     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1492 }
1493 \f
1494 /* Set up any promoted values for incoming argument registers.  */
1495
1496 static void
1497 setup_incoming_promotions (rtx first)
1498 {
1499   tree arg;
1500   bool strictly_local = false;
1501
1502   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1503        arg = DECL_CHAIN (arg))
1504     {
1505       rtx x, reg = DECL_INCOMING_RTL (arg);
1506       int uns1, uns3;
1507       enum machine_mode mode1, mode2, mode3, mode4;
1508
1509       /* Only continue if the incoming argument is in a register.  */
1510       if (!REG_P (reg))
1511         continue;
1512
1513       /* Determine, if possible, whether all call sites of the current
1514          function lie within the current compilation unit.  (This does
1515          take into account the exporting of a function via taking its
1516          address, and so forth.)  */
1517       strictly_local = cgraph_local_info (current_function_decl)->local;
1518
1519       /* The mode and signedness of the argument before any promotions happen
1520          (equal to the mode of the pseudo holding it at that stage).  */
1521       mode1 = TYPE_MODE (TREE_TYPE (arg));
1522       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1523
1524       /* The mode and signedness of the argument after any source language and
1525          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1526       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1527       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1528
1529       /* The mode and signedness of the argument as it is actually passed,
1530          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1531       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1532                                      TREE_TYPE (cfun->decl), 0);
1533
1534       /* The mode of the register in which the argument is being passed.  */
1535       mode4 = GET_MODE (reg);
1536
1537       /* Eliminate sign extensions in the callee when:
1538          (a) A mode promotion has occurred;  */
1539       if (mode1 == mode3)
1540         continue;
1541       /* (b) The mode of the register is the same as the mode of
1542              the argument as it is passed; */
1543       if (mode3 != mode4)
1544         continue;
1545       /* (c) There's no language level extension;  */
1546       if (mode1 == mode2)
1547         ;
1548       /* (c.1) All callers are from the current compilation unit.  If that's
1549          the case we don't have to rely on an ABI, we only have to know
1550          what we're generating right now, and we know that we will do the
1551          mode1 to mode2 promotion with the given sign.  */
1552       else if (!strictly_local)
1553         continue;
1554       /* (c.2) The combination of the two promotions is useful.  This is
1555          true when the signs match, or if the first promotion is unsigned.
1556          In the later case, (sign_extend (zero_extend x)) is the same as
1557          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1558       else if (uns1)
1559         uns3 = true;
1560       else if (uns3)
1561         continue;
1562
1563       /* Record that the value was promoted from mode1 to mode3,
1564          so that any sign extension at the head of the current
1565          function may be eliminated.  */
1566       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1567       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1568       record_value_for_reg (reg, first, x);
1569     }
1570 }
1571
1572 /* Called via note_stores.  If X is a pseudo that is narrower than
1573    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1574
1575    If we are setting only a portion of X and we can't figure out what
1576    portion, assume all bits will be used since we don't know what will
1577    be happening.
1578
1579    Similarly, set how many bits of X are known to be copies of the sign bit
1580    at all locations in the function.  This is the smallest number implied
1581    by any set of X.  */
1582
1583 static void
1584 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1585 {
1586   rtx insn = (rtx) data;
1587   unsigned int num;
1588
1589   if (REG_P (x)
1590       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1591       /* If this register is undefined at the start of the file, we can't
1592          say what its contents were.  */
1593       && ! REGNO_REG_SET_P
1594            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1595       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1596     {
1597       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1598
1599       if (set == 0 || GET_CODE (set) == CLOBBER)
1600         {
1601           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1602           rsp->sign_bit_copies = 1;
1603           return;
1604         }
1605
1606       /* If this register is being initialized using itself, and the
1607          register is uninitialized in this basic block, and there are
1608          no LOG_LINKS which set the register, then part of the
1609          register is uninitialized.  In that case we can't assume
1610          anything about the number of nonzero bits.
1611
1612          ??? We could do better if we checked this in
1613          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1614          could avoid making assumptions about the insn which initially
1615          sets the register, while still using the information in other
1616          insns.  We would have to be careful to check every insn
1617          involved in the combination.  */
1618
1619       if (insn
1620           && reg_referenced_p (x, PATTERN (insn))
1621           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1622                                REGNO (x)))
1623         {
1624           struct insn_link *link;
1625
1626           FOR_EACH_LOG_LINK (link, insn)
1627             if (dead_or_set_p (link->insn, x))
1628               break;
1629           if (!link)
1630             {
1631               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1632               rsp->sign_bit_copies = 1;
1633               return;
1634             }
1635         }
1636
1637       /* If this is a complex assignment, see if we can convert it into a
1638          simple assignment.  */
1639       set = expand_field_assignment (set);
1640
1641       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642          set what we know about X.  */
1643
1644       if (SET_DEST (set) == x
1645           || (paradoxical_subreg_p (SET_DEST (set))
1646               && SUBREG_REG (SET_DEST (set)) == x))
1647         {
1648           rtx src = SET_SRC (set);
1649
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651           /* If X is narrower than a word and SRC is a non-negative
1652              constant that would appear negative in the mode of X,
1653              sign-extend it for use in reg_stat[].nonzero_bits because some
1654              machines (maybe most) will actually do the sign-extension
1655              and this is the conservative approach.
1656
1657              ??? For 2.5, try to tighten up the MD files in this regard
1658              instead of this kludge.  */
1659
1660           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1661               && CONST_INT_P (src)
1662               && INTVAL (src) > 0
1663               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1664             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1665 #endif
1666
1667           /* Don't call nonzero_bits if it cannot change anything.  */
1668           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1669             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1670           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1671           if (rsp->sign_bit_copies == 0
1672               || rsp->sign_bit_copies > num)
1673             rsp->sign_bit_copies = num;
1674         }
1675       else
1676         {
1677           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1678           rsp->sign_bit_copies = 1;
1679         }
1680     }
1681 }
1682 \f
1683 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1684    optionally insns that were previously combined into I3 or that will be
1685    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1686    INSN, SUCC, SUCC2, I3.
1687
1688    Return 0 if the combination is not allowed for any reason.
1689
1690    If the combination is allowed, *PDEST will be set to the single
1691    destination of INSN and *PSRC to the single source, and this function
1692    will return 1.  */
1693
1694 static int
1695 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1696                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1697                rtx *pdest, rtx *psrc)
1698 {
1699   int i;
1700   const_rtx set = 0;
1701   rtx src, dest;
1702   rtx p;
1703 #ifdef AUTO_INC_DEC
1704   rtx link;
1705 #endif
1706   bool all_adjacent = true;
1707   int (*is_volatile_p) (const_rtx);
1708
1709   if (succ)
1710     {
1711       if (succ2)
1712         {
1713           if (next_active_insn (succ2) != i3)
1714             all_adjacent = false;
1715           if (next_active_insn (succ) != succ2)
1716             all_adjacent = false;
1717         }
1718       else if (next_active_insn (succ) != i3)
1719         all_adjacent = false;
1720       if (next_active_insn (insn) != succ)
1721         all_adjacent = false;
1722     }
1723   else if (next_active_insn (insn) != i3)
1724     all_adjacent = false;
1725
1726   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727      or a PARALLEL consisting of such a SET and CLOBBERs.
1728
1729      If INSN has CLOBBER parallel parts, ignore them for our processing.
1730      By definition, these happen during the execution of the insn.  When it
1731      is merged with another insn, all bets are off.  If they are, in fact,
1732      needed and aren't also supplied in I3, they may be added by
1733      recog_for_combine.  Otherwise, it won't match.
1734
1735      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1736      note.
1737
1738      Get the source and destination of INSN.  If more than one, can't
1739      combine.  */
1740
1741   if (GET_CODE (PATTERN (insn)) == SET)
1742     set = PATTERN (insn);
1743   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1744            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1745     {
1746       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1747         {
1748           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1749
1750           switch (GET_CODE (elt))
1751             {
1752             /* This is important to combine floating point insns
1753                for the SH4 port.  */
1754             case USE:
1755               /* Combining an isolated USE doesn't make sense.
1756                  We depend here on combinable_i3pat to reject them.  */
1757               /* The code below this loop only verifies that the inputs of
1758                  the SET in INSN do not change.  We call reg_set_between_p
1759                  to verify that the REG in the USE does not change between
1760                  I3 and INSN.
1761                  If the USE in INSN was for a pseudo register, the matching
1762                  insn pattern will likely match any register; combining this
1763                  with any other USE would only be safe if we knew that the
1764                  used registers have identical values, or if there was
1765                  something to tell them apart, e.g. different modes.  For
1766                  now, we forgo such complicated tests and simply disallow
1767                  combining of USES of pseudo registers with any other USE.  */
1768               if (REG_P (XEXP (elt, 0))
1769                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1770                 {
1771                   rtx i3pat = PATTERN (i3);
1772                   int i = XVECLEN (i3pat, 0) - 1;
1773                   unsigned int regno = REGNO (XEXP (elt, 0));
1774
1775                   do
1776                     {
1777                       rtx i3elt = XVECEXP (i3pat, 0, i);
1778
1779                       if (GET_CODE (i3elt) == USE
1780                           && REG_P (XEXP (i3elt, 0))
1781                           && (REGNO (XEXP (i3elt, 0)) == regno
1782                               ? reg_set_between_p (XEXP (elt, 0),
1783                                                    PREV_INSN (insn), i3)
1784                               : regno >= FIRST_PSEUDO_REGISTER))
1785                         return 0;
1786                     }
1787                   while (--i >= 0);
1788                 }
1789               break;
1790
1791               /* We can ignore CLOBBERs.  */
1792             case CLOBBER:
1793               break;
1794
1795             case SET:
1796               /* Ignore SETs whose result isn't used but not those that
1797                  have side-effects.  */
1798               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1799                   && insn_nothrow_p (insn)
1800                   && !side_effects_p (elt))
1801                 break;
1802
1803               /* If we have already found a SET, this is a second one and
1804                  so we cannot combine with this insn.  */
1805               if (set)
1806                 return 0;
1807
1808               set = elt;
1809               break;
1810
1811             default:
1812               /* Anything else means we can't combine.  */
1813               return 0;
1814             }
1815         }
1816
1817       if (set == 0
1818           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819              so don't do anything with it.  */
1820           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1821         return 0;
1822     }
1823   else
1824     return 0;
1825
1826   if (set == 0)
1827     return 0;
1828
1829   /* The simplification in expand_field_assignment may call back to
1830      get_last_value, so set safe guard here.  */
1831   subst_low_luid = DF_INSN_LUID (insn);
1832
1833   set = expand_field_assignment (set);
1834   src = SET_SRC (set), dest = SET_DEST (set);
1835
1836   /* Don't eliminate a store in the stack pointer.  */
1837   if (dest == stack_pointer_rtx
1838       /* Don't combine with an insn that sets a register to itself if it has
1839          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1840       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1841       /* Can't merge an ASM_OPERANDS.  */
1842       || GET_CODE (src) == ASM_OPERANDS
1843       /* Can't merge a function call.  */
1844       || GET_CODE (src) == CALL
1845       /* Don't eliminate a function call argument.  */
1846       || (CALL_P (i3)
1847           && (find_reg_fusage (i3, USE, dest)
1848               || (REG_P (dest)
1849                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1850                   && global_regs[REGNO (dest)])))
1851       /* Don't substitute into an incremented register.  */
1852       || FIND_REG_INC_NOTE (i3, dest)
1853       || (succ && FIND_REG_INC_NOTE (succ, dest))
1854       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1855       /* Don't substitute into a non-local goto, this confuses CFG.  */
1856       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1857       /* Make sure that DEST is not used after SUCC but before I3.  */
1858       || (!all_adjacent
1859           && ((succ2
1860                && (reg_used_between_p (dest, succ2, i3)
1861                    || reg_used_between_p (dest, succ, succ2)))
1862               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1863       /* Make sure that the value that is to be substituted for the register
1864          does not use any registers whose values alter in between.  However,
1865          If the insns are adjacent, a use can't cross a set even though we
1866          think it might (this can happen for a sequence of insns each setting
1867          the same destination; last_set of that register might point to
1868          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1869          equivalent to the memory so the substitution is valid even if there
1870          are intervening stores.  Also, don't move a volatile asm or
1871          UNSPEC_VOLATILE across any other insns.  */
1872       || (! all_adjacent
1873           && (((!MEM_P (src)
1874                 || ! find_reg_note (insn, REG_EQUIV, src))
1875                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1876               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1877               || GET_CODE (src) == UNSPEC_VOLATILE))
1878       /* Don't combine across a CALL_INSN, because that would possibly
1879          change whether the life span of some REGs crosses calls or not,
1880          and it is a pain to update that information.
1881          Exception: if source is a constant, moving it later can't hurt.
1882          Accept that as a special case.  */
1883       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1884     return 0;
1885
1886   /* DEST must either be a REG or CC0.  */
1887   if (REG_P (dest))
1888     {
1889       /* If register alignment is being enforced for multi-word items in all
1890          cases except for parameters, it is possible to have a register copy
1891          insn referencing a hard register that is not allowed to contain the
1892          mode being copied and which would not be valid as an operand of most
1893          insns.  Eliminate this problem by not combining with such an insn.
1894
1895          Also, on some machines we don't want to extend the life of a hard
1896          register.  */
1897
1898       if (REG_P (src)
1899           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1900                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1901               /* Don't extend the life of a hard register unless it is
1902                  user variable (if we have few registers) or it can't
1903                  fit into the desired register (meaning something special
1904                  is going on).
1905                  Also avoid substituting a return register into I3, because
1906                  reload can't handle a conflict with constraints of other
1907                  inputs.  */
1908               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1909                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1910         return 0;
1911     }
1912   else if (GET_CODE (dest) != CC0)
1913     return 0;
1914
1915
1916   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1917     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1918       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1919         {
1920           /* Don't substitute for a register intended as a clobberable
1921              operand.  */
1922           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1923           if (rtx_equal_p (reg, dest))
1924             return 0;
1925
1926           /* If the clobber represents an earlyclobber operand, we must not
1927              substitute an expression containing the clobbered register.
1928              As we do not analyze the constraint strings here, we have to
1929              make the conservative assumption.  However, if the register is
1930              a fixed hard reg, the clobber cannot represent any operand;
1931              we leave it up to the machine description to either accept or
1932              reject use-and-clobber patterns.  */
1933           if (!REG_P (reg)
1934               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1935               || !fixed_regs[REGNO (reg)])
1936             if (reg_overlap_mentioned_p (reg, src))
1937               return 0;
1938         }
1939
1940   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941      or not), reject, unless nothing volatile comes between it and I3 */
1942
1943   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1944     {
1945       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1946       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1947         return 0;
1948       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1949         return 0;
1950       /* We'll check insns between INSN and I3 below.  */
1951     }
1952
1953   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954      to be an explicit register variable, and was chosen for a reason.  */
1955
1956   if (GET_CODE (src) == ASM_OPERANDS
1957       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1958     return 0;
1959
1960   /* If INSN contains volatile references (specifically volatile MEMs),
1961      we cannot combine across any other volatile references.
1962      Even if INSN doesn't contain volatile references, any intervening
1963      volatile insn might affect machine state.  */
1964
1965   is_volatile_p = volatile_refs_p (PATTERN (insn))
1966     ? volatile_refs_p
1967     : volatile_insn_p;
1968
1969   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1970     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1971       return 0;
1972
1973   /* If INSN contains an autoincrement or autodecrement, make sure that
1974      register is not used between there and I3, and not already used in
1975      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1976      Also insist that I3 not be a jump; if it were one
1977      and the incremented register were spilled, we would lose.  */
1978
1979 #ifdef AUTO_INC_DEC
1980   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1981     if (REG_NOTE_KIND (link) == REG_INC
1982         && (JUMP_P (i3)
1983             || reg_used_between_p (XEXP (link, 0), insn, i3)
1984             || (pred != NULL_RTX
1985                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1986             || (pred2 != NULL_RTX
1987                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1988             || (succ != NULL_RTX
1989                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1990             || (succ2 != NULL_RTX
1991                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1992             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1993       return 0;
1994 #endif
1995
1996 #ifdef HAVE_cc0
1997   /* Don't combine an insn that follows a CC0-setting insn.
1998      An insn that uses CC0 must not be separated from the one that sets it.
1999      We do, however, allow I2 to follow a CC0-setting insn if that insn
2000      is passed as I1; in that case it will be deleted also.
2001      We also allow combining in this case if all the insns are adjacent
2002      because that would leave the two CC0 insns adjacent as well.
2003      It would be more logical to test whether CC0 occurs inside I1 or I2,
2004      but that would be much slower, and this ought to be equivalent.  */
2005
2006   p = prev_nonnote_insn (insn);
2007   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2008       && ! all_adjacent)
2009     return 0;
2010 #endif
2011
2012   /* If we get here, we have passed all the tests and the combination is
2013      to be allowed.  */
2014
2015   *pdest = dest;
2016   *psrc = src;
2017
2018   return 1;
2019 }
2020 \f
2021 /* LOC is the location within I3 that contains its pattern or the component
2022    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2023
2024    One problem is if I3 modifies its output, as opposed to replacing it
2025    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026    doing so would produce an insn that is not equivalent to the original insns.
2027
2028    Consider:
2029
2030          (set (reg:DI 101) (reg:DI 100))
2031          (set (subreg:SI (reg:DI 101) 0) <foo>)
2032
2033    This is NOT equivalent to:
2034
2035          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036                     (set (reg:DI 101) (reg:DI 100))])
2037
2038    Not only does this modify 100 (in which case it might still be valid
2039    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2040
2041    We can also run into a problem if I2 sets a register that I1
2042    uses and I1 gets directly substituted into I3 (not via I2).  In that
2043    case, we would be getting the wrong value of I2DEST into I3, so we
2044    must reject the combination.  This case occurs when I2 and I1 both
2045    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047    of a SET must prevent combination from occurring.  The same situation
2048    can occur for I0, in which case I0_NOT_IN_SRC is set.
2049
2050    Before doing the above check, we first try to expand a field assignment
2051    into a set of logical operations.
2052
2053    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054    we place a register that is both set and used within I3.  If more than one
2055    such register is detected, we fail.
2056
2057    Return 1 if the combination is valid, zero otherwise.  */
2058
2059 static int
2060 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2061                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2062 {
2063   rtx x = *loc;
2064
2065   if (GET_CODE (x) == SET)
2066     {
2067       rtx set = x ;
2068       rtx dest = SET_DEST (set);
2069       rtx src = SET_SRC (set);
2070       rtx inner_dest = dest;
2071       rtx subdest;
2072
2073       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2074              || GET_CODE (inner_dest) == SUBREG
2075              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2076         inner_dest = XEXP (inner_dest, 0);
2077
2078       /* Check for the case where I3 modifies its output, as discussed
2079          above.  We don't want to prevent pseudos from being combined
2080          into the address of a MEM, so only prevent the combination if
2081          i1 or i2 set the same MEM.  */
2082       if ((inner_dest != dest &&
2083            (!MEM_P (inner_dest)
2084             || rtx_equal_p (i2dest, inner_dest)
2085             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2086             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2087            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2088                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2089                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2090
2091           /* This is the same test done in can_combine_p except we can't test
2092              all_adjacent; we don't have to, since this instruction will stay
2093              in place, thus we are not considering increasing the lifetime of
2094              INNER_DEST.
2095
2096              Also, if this insn sets a function argument, combining it with
2097              something that might need a spill could clobber a previous
2098              function argument; the all_adjacent test in can_combine_p also
2099              checks this; here, we do a more specific test for this case.  */
2100
2101           || (REG_P (inner_dest)
2102               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2103               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2104                                         GET_MODE (inner_dest))))
2105           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2106           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2107         return 0;
2108
2109       /* If DEST is used in I3, it is being killed in this insn, so
2110          record that for later.  We have to consider paradoxical
2111          subregs here, since they kill the whole register, but we
2112          ignore partial subregs, STRICT_LOW_PART, etc.
2113          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114          STACK_POINTER_REGNUM, since these are always considered to be
2115          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2116       subdest = dest;
2117       if (GET_CODE (subdest) == SUBREG
2118           && (GET_MODE_SIZE (GET_MODE (subdest))
2119               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2120         subdest = SUBREG_REG (subdest);
2121       if (pi3dest_killed
2122           && REG_P (subdest)
2123           && reg_referenced_p (subdest, PATTERN (i3))
2124           && REGNO (subdest) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2127 #endif
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129           && (REGNO (subdest) != ARG_POINTER_REGNUM
2130               || ! fixed_regs [REGNO (subdest)])
2131 #endif
2132           && REGNO (subdest) != STACK_POINTER_REGNUM)
2133         {
2134           if (*pi3dest_killed)
2135             return 0;
2136
2137           *pi3dest_killed = subdest;
2138         }
2139     }
2140
2141   else if (GET_CODE (x) == PARALLEL)
2142     {
2143       int i;
2144
2145       for (i = 0; i < XVECLEN (x, 0); i++)
2146         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2147                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2148           return 0;
2149     }
2150
2151   return 1;
2152 }
2153 \f
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155    and division.  We don't count multiplications by powers of two here.  */
2156
2157 static int
2158 contains_muldiv (rtx x)
2159 {
2160   switch (GET_CODE (x))
2161     {
2162     case MOD:  case DIV:  case UMOD:  case UDIV:
2163       return 1;
2164
2165     case MULT:
2166       return ! (CONST_INT_P (XEXP (x, 1))
2167                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2168     default:
2169       if (BINARY_P (x))
2170         return contains_muldiv (XEXP (x, 0))
2171             || contains_muldiv (XEXP (x, 1));
2172
2173       if (UNARY_P (x))
2174         return contains_muldiv (XEXP (x, 0));
2175
2176       return 0;
2177     }
2178 }
2179 \f
2180 /* Determine whether INSN can be used in a combination.  Return nonzero if
2181    not.  This is used in try_combine to detect early some cases where we
2182    can't perform combinations.  */
2183
2184 static int
2185 cant_combine_insn_p (rtx insn)
2186 {
2187   rtx set;
2188   rtx src, dest;
2189
2190   /* If this isn't really an insn, we can't do anything.
2191      This can occur when flow deletes an insn that it has merged into an
2192      auto-increment address.  */
2193   if (! INSN_P (insn))
2194     return 1;
2195
2196   /* Never combine loads and stores involving hard regs that are likely
2197      to be spilled.  The register allocator can usually handle such
2198      reg-reg moves by tying.  If we allow the combiner to make
2199      substitutions of likely-spilled regs, reload might die.
2200      As an exception, we allow combinations involving fixed regs; these are
2201      not available to the register allocator so there's no risk involved.  */
2202
2203   set = single_set (insn);
2204   if (! set)
2205     return 0;
2206   src = SET_SRC (set);
2207   dest = SET_DEST (set);
2208   if (GET_CODE (src) == SUBREG)
2209     src = SUBREG_REG (src);
2210   if (GET_CODE (dest) == SUBREG)
2211     dest = SUBREG_REG (dest);
2212   if (REG_P (src) && REG_P (dest)
2213       && ((HARD_REGISTER_P (src)
2214            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2215            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2216           || (HARD_REGISTER_P (dest)
2217               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2218               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2219     return 1;
2220
2221   return 0;
2222 }
2223
2224 struct likely_spilled_retval_info
2225 {
2226   unsigned regno, nregs;
2227   unsigned mask;
2228 };
2229
2230 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2231    hard registers that are known to be written to / clobbered in full.  */
2232 static void
2233 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2234 {
2235   struct likely_spilled_retval_info *const info =
2236     (struct likely_spilled_retval_info *) data;
2237   unsigned regno, nregs;
2238   unsigned new_mask;
2239
2240   if (!REG_P (XEXP (set, 0)))
2241     return;
2242   regno = REGNO (x);
2243   if (regno >= info->regno + info->nregs)
2244     return;
2245   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2246   if (regno + nregs <= info->regno)
2247     return;
2248   new_mask = (2U << (nregs - 1)) - 1;
2249   if (regno < info->regno)
2250     new_mask >>= info->regno - regno;
2251   else
2252     new_mask <<= regno - info->regno;
2253   info->mask &= ~new_mask;
2254 }
2255
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257    it is likely spilled.  This can happen when more than one insn is needed
2258    to copy the return value, e.g. when we consider to combine into the
2259    second copy insn for a complex value.  */
2260
2261 static int
2262 likely_spilled_retval_p (rtx insn)
2263 {
2264   rtx use = BB_END (this_basic_block);
2265   rtx reg, p;
2266   unsigned regno, nregs;
2267   /* We assume here that no machine mode needs more than
2268      32 hard registers when the value overlaps with a register
2269      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2270   unsigned mask;
2271   struct likely_spilled_retval_info info;
2272
2273   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2274     return 0;
2275   reg = XEXP (PATTERN (use), 0);
2276   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2277     return 0;
2278   regno = REGNO (reg);
2279   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2280   if (nregs == 1)
2281     return 0;
2282   mask = (2U << (nregs - 1)) - 1;
2283
2284   /* Disregard parts of the return value that are set later.  */
2285   info.regno = regno;
2286   info.nregs = nregs;
2287   info.mask = mask;
2288   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2289     if (INSN_P (p))
2290       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2291   mask = info.mask;
2292
2293   /* Check if any of the (probably) live return value registers is
2294      likely spilled.  */
2295   nregs --;
2296   do
2297     {
2298       if ((mask & 1 << nregs)
2299           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2300         return 1;
2301     } while (nregs--);
2302   return 0;
2303 }
2304
2305 /* Adjust INSN after we made a change to its destination.
2306
2307    Changing the destination can invalidate notes that say something about
2308    the results of the insn and a LOG_LINK pointing to the insn.  */
2309
2310 static void
2311 adjust_for_new_dest (rtx insn)
2312 {
2313   /* For notes, be conservative and simply remove them.  */
2314   remove_reg_equal_equiv_notes (insn);
2315
2316   /* The new insn will have a destination that was previously the destination
2317      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2318      the next use of that destination.  */
2319   distribute_links (alloc_insn_link (insn, NULL));
2320
2321   df_insn_rescan (insn);
2322 }
2323
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325    ADDED_SETS is nonzero if the original set is still required.  */
2326 static bool
2327 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2328 {
2329   unsigned int regno;
2330
2331   if (!REG_P (x))
2332     return false;
2333
2334   regno = REGNO (x);
2335   /* Allow hard registers if the new mode is legal, and occupies no more
2336      registers than the old mode.  */
2337   if (regno < FIRST_PSEUDO_REGISTER)
2338     return (HARD_REGNO_MODE_OK (regno, mode)
2339             && (hard_regno_nregs[regno][GET_MODE (x)]
2340                 >= hard_regno_nregs[regno][mode]));
2341
2342   /* Or a pseudo that is only used once.  */
2343   return (REG_N_SETS (regno) == 1 && !added_sets
2344           && !REG_USERVAR_P (x));
2345 }
2346
2347
2348 /* Check whether X, the destination of a set, refers to part of
2349    the register specified by REG.  */
2350
2351 static bool
2352 reg_subword_p (rtx x, rtx reg)
2353 {
2354   /* Check that reg is an integer mode register.  */
2355   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2356     return false;
2357
2358   if (GET_CODE (x) == STRICT_LOW_PART
2359       || GET_CODE (x) == ZERO_EXTRACT)
2360     x = XEXP (x, 0);
2361
2362   return GET_CODE (x) == SUBREG
2363          && SUBREG_REG (x) == reg
2364          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2365 }
2366
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368    Note that the INSN should be deleted *after* removing dead edges, so
2369    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370    but not for a (set (pc) (label_ref FOO)).  */
2371
2372 static void
2373 update_cfg_for_uncondjump (rtx insn)
2374 {
2375   basic_block bb = BLOCK_FOR_INSN (insn);
2376   gcc_assert (BB_END (bb) == insn);
2377
2378   purge_dead_edges (bb);
2379
2380   delete_insn (insn);
2381   if (EDGE_COUNT (bb->succs) == 1)
2382     {
2383       rtx insn;
2384
2385       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2386
2387       /* Remove barriers from the footer if there are any.  */
2388       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2389         if (BARRIER_P (insn))
2390           {
2391             if (PREV_INSN (insn))
2392               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2393             else
2394               BB_FOOTER (bb) = NEXT_INSN (insn);
2395             if (NEXT_INSN (insn))
2396               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2397           }
2398         else if (LABEL_P (insn))
2399           break;
2400     }
2401 }
2402
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404    Here I0, I1 and I2 appear earlier than I3.
2405    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2406    I3.
2407
2408    If we are combining more than two insns and the resulting insn is not
2409    recognized, try splitting it into two insns.  If that happens, I2 and I3
2410    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411    Otherwise, I0, I1 and I2 are pseudo-deleted.
2412
2413    Return 0 if the combination does not work.  Then nothing is changed.
2414    If we did the combination, return the insn at which combine should
2415    resume scanning.
2416
2417    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418    new direct jump instruction.
2419
2420    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421    been I3 passed to an earlier try_combine within the same basic
2422    block.  */
2423
2424 static rtx
2425 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2426              rtx last_combined_insn)
2427 {
2428   /* New patterns for I3 and I2, respectively.  */
2429   rtx newpat, newi2pat = 0;
2430   rtvec newpat_vec_with_clobbers = 0;
2431   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2432   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2433      dead.  */
2434   int added_sets_0, added_sets_1, added_sets_2;
2435   /* Total number of SETs to put into I3.  */
2436   int total_sets;
2437   /* Nonzero if I2's or I1's body now appears in I3.  */
2438   int i2_is_used = 0, i1_is_used = 0;
2439   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2440   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2441   /* Contains I3 if the destination of I3 is used in its source, which means
2442      that the old life of I3 is being killed.  If that usage is placed into
2443      I2 and not in I3, a REG_DEAD note must be made.  */
2444   rtx i3dest_killed = 0;
2445   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2446   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2447   /* Copy of SET_SRC of I1 and I0, if needed.  */
2448   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2449   /* Set if I2DEST was reused as a scratch register.  */
2450   bool i2scratch = false;
2451   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2452   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2453   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2454   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2455   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2456   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2457   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2458   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2459   rtx new_i3_notes, new_i2_notes;
2460   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2461   int i3_subst_into_i2 = 0;
2462   /* Notes that I1, I2 or I3 is a MULT operation.  */
2463   int have_mult = 0;
2464   int swap_i2i3 = 0;
2465   int changed_i3_dest = 0;
2466
2467   int maxreg;
2468   rtx temp;
2469   struct insn_link *link;
2470   rtx other_pat = 0;
2471   rtx new_other_notes;
2472   int i;
2473
2474   /* Only try four-insn combinations when there's high likelihood of
2475      success.  Look for simple insns, such as loads of constants or
2476      binary operations involving a constant.  */
2477   if (i0)
2478     {
2479       int i;
2480       int ngood = 0;
2481       int nshift = 0;
2482
2483       if (!flag_expensive_optimizations)
2484         return 0;
2485
2486       for (i = 0; i < 4; i++)
2487         {
2488           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2489           rtx set = single_set (insn);
2490           rtx src;
2491           if (!set)
2492             continue;
2493           src = SET_SRC (set);
2494           if (CONSTANT_P (src))
2495             {
2496               ngood += 2;
2497               break;
2498             }
2499           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2500             ngood++;
2501           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2502                    || GET_CODE (src) == LSHIFTRT)
2503             nshift++;
2504         }
2505       if (ngood < 2 && nshift < 2)
2506         return 0;
2507     }
2508
2509   /* Exit early if one of the insns involved can't be used for
2510      combinations.  */
2511   if (cant_combine_insn_p (i3)
2512       || cant_combine_insn_p (i2)
2513       || (i1 && cant_combine_insn_p (i1))
2514       || (i0 && cant_combine_insn_p (i0))
2515       || likely_spilled_retval_p (i3))
2516     return 0;
2517
2518   combine_attempts++;
2519   undobuf.other_insn = 0;
2520
2521   /* Reset the hard register usage information.  */
2522   CLEAR_HARD_REG_SET (newpat_used_regs);
2523
2524   if (dump_file && (dump_flags & TDF_DETAILS))
2525     {
2526       if (i0)
2527         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2528                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2529       else if (i1)
2530         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2531                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2532       else
2533         fprintf (dump_file, "\nTrying %d -> %d:\n",
2534                  INSN_UID (i2), INSN_UID (i3));
2535     }
2536
2537   /* If multiple insns feed into one of I2 or I3, they can be in any
2538      order.  To simplify the code below, reorder them in sequence.  */
2539   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2540     temp = i2, i2 = i0, i0 = temp;
2541   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2542     temp = i1, i1 = i0, i0 = temp;
2543   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2544     temp = i1, i1 = i2, i2 = temp;
2545
2546   added_links_insn = 0;
2547
2548   /* First check for one important special case that the code below will
2549      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2550      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2551      we may be able to replace that destination with the destination of I3.
2552      This occurs in the common code where we compute both a quotient and
2553      remainder into a structure, in which case we want to do the computation
2554      directly into the structure to avoid register-register copies.
2555
2556      Note that this case handles both multiple sets in I2 and also cases
2557      where I2 has a number of CLOBBERs inside the PARALLEL.
2558
2559      We make very conservative checks below and only try to handle the
2560      most common cases of this.  For example, we only handle the case
2561      where I2 and I3 are adjacent to avoid making difficult register
2562      usage tests.  */
2563
2564   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2565       && REG_P (SET_SRC (PATTERN (i3)))
2566       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2567       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2568       && GET_CODE (PATTERN (i2)) == PARALLEL
2569       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2570       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571          below would need to check what is inside (and reg_overlap_mentioned_p
2572          doesn't support those codes anyway).  Don't allow those destinations;
2573          the resulting insn isn't likely to be recognized anyway.  */
2574       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2575       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2576       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2577                                     SET_DEST (PATTERN (i3)))
2578       && next_active_insn (i2) == i3)
2579     {
2580       rtx p2 = PATTERN (i2);
2581
2582       /* Make sure that the destination of I3,
2583          which we are going to substitute into one output of I2,
2584          is not used within another output of I2.  We must avoid making this:
2585          (parallel [(set (mem (reg 69)) ...)
2586                     (set (reg 69) ...)])
2587          which is not well-defined as to order of actions.
2588          (Besides, reload can't handle output reloads for this.)
2589
2590          The problem can also happen if the dest of I3 is a memory ref,
2591          if another dest in I2 is an indirect memory ref.  */
2592       for (i = 0; i < XVECLEN (p2, 0); i++)
2593         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2594              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2595             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2596                                         SET_DEST (XVECEXP (p2, 0, i))))
2597           break;
2598
2599       if (i == XVECLEN (p2, 0))
2600         for (i = 0; i < XVECLEN (p2, 0); i++)
2601           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2602               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2603             {
2604               combine_merges++;
2605
2606               subst_insn = i3;
2607               subst_low_luid = DF_INSN_LUID (i2);
2608
2609               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2610               i2src = SET_SRC (XVECEXP (p2, 0, i));
2611               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2612               i2dest_killed = dead_or_set_p (i2, i2dest);
2613
2614               /* Replace the dest in I2 with our dest and make the resulting
2615                  insn the new pattern for I3.  Then skip to where we validate
2616                  the pattern.  Everything was set up above.  */
2617               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2618               newpat = p2;
2619               i3_subst_into_i2 = 1;
2620               goto validate_replacement;
2621             }
2622     }
2623
2624   /* If I2 is setting a pseudo to a constant and I3 is setting some
2625      sub-part of it to another constant, merge them by making a new
2626      constant.  */
2627   if (i1 == 0
2628       && (temp = single_set (i2)) != 0
2629       && CONST_SCALAR_INT_P (SET_SRC (temp))
2630       && GET_CODE (PATTERN (i3)) == SET
2631       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2632       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2633     {
2634       rtx dest = SET_DEST (PATTERN (i3));
2635       int offset = -1;
2636       int width = 0;
2637
2638       if (GET_CODE (dest) == ZERO_EXTRACT)
2639         {
2640           if (CONST_INT_P (XEXP (dest, 1))
2641               && CONST_INT_P (XEXP (dest, 2)))
2642             {
2643               width = INTVAL (XEXP (dest, 1));
2644               offset = INTVAL (XEXP (dest, 2));
2645               dest = XEXP (dest, 0);
2646               if (BITS_BIG_ENDIAN)
2647                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2648             }
2649         }
2650       else
2651         {
2652           if (GET_CODE (dest) == STRICT_LOW_PART)
2653             dest = XEXP (dest, 0);
2654           width = GET_MODE_PRECISION (GET_MODE (dest));
2655           offset = 0;
2656         }
2657
2658       if (offset >= 0)
2659         {
2660           /* If this is the low part, we're done.  */
2661           if (subreg_lowpart_p (dest))
2662             ;
2663           /* Handle the case where inner is twice the size of outer.  */
2664           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2665                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2666             offset += GET_MODE_PRECISION (GET_MODE (dest));
2667           /* Otherwise give up for now.  */
2668           else
2669             offset = -1;
2670         }
2671
2672       if (offset >= 0
2673           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2674               <= HOST_BITS_PER_DOUBLE_INT))
2675         {
2676           double_int m, o, i;
2677           rtx inner = SET_SRC (PATTERN (i3));
2678           rtx outer = SET_SRC (temp);
2679
2680           o = rtx_to_double_int (outer);
2681           i = rtx_to_double_int (inner);
2682
2683           m = double_int::mask (width);
2684           i &= m;
2685           m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2686           i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2687           o = o.and_not (m) | i;
2688
2689           combine_merges++;
2690           subst_insn = i3;
2691           subst_low_luid = DF_INSN_LUID (i2);
2692           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2693           i2dest = SET_DEST (temp);
2694           i2dest_killed = dead_or_set_p (i2, i2dest);
2695
2696           /* Replace the source in I2 with the new constant and make the
2697              resulting insn the new pattern for I3.  Then skip to where we
2698              validate the pattern.  Everything was set up above.  */
2699           SUBST (SET_SRC (temp),
2700                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2701
2702           newpat = PATTERN (i2);
2703
2704           /* The dest of I3 has been replaced with the dest of I2.  */
2705           changed_i3_dest = 1;
2706           goto validate_replacement;
2707         }
2708     }
2709
2710 #ifndef HAVE_cc0
2711   /* If we have no I1 and I2 looks like:
2712         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2713                    (set Y OP)])
2714      make up a dummy I1 that is
2715         (set Y OP)
2716      and change I2 to be
2717         (set (reg:CC X) (compare:CC Y (const_int 0)))
2718
2719      (We can ignore any trailing CLOBBERs.)
2720
2721      This undoes a previous combination and allows us to match a branch-and-
2722      decrement insn.  */
2723
2724   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2725       && XVECLEN (PATTERN (i2), 0) >= 2
2726       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2727       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2728           == MODE_CC)
2729       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2730       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2731       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2732       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2733       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2734                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2735     {
2736       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2737         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2738           break;
2739
2740       if (i == 1)
2741         {
2742           /* We make I1 with the same INSN_UID as I2.  This gives it
2743              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2744              never appear in the insn stream so giving it the same INSN_UID
2745              as I2 will not cause a problem.  */
2746
2747           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2748                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2749                              INSN_LOCATION (i2), -1, NULL_RTX);
2750
2751           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2752           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2753                  SET_DEST (PATTERN (i1)));
2754           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2755         }
2756     }
2757 #endif
2758
2759   /* Verify that I2 and I1 are valid for combining.  */
2760   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2761       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2762                                  &i1dest, &i1src))
2763       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2764                                  &i0dest, &i0src)))
2765     {
2766       undo_all ();
2767       return 0;
2768     }
2769
2770   /* Record whether I2DEST is used in I2SRC and similarly for the other
2771      cases.  Knowing this will help in register status updating below.  */
2772   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2773   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2774   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2775   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2776   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2777   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2778   i2dest_killed = dead_or_set_p (i2, i2dest);
2779   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2780   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2781
2782   /* For the earlier insns, determine which of the subsequent ones they
2783      feed.  */
2784   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2785   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2786   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2787                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2788                              && reg_overlap_mentioned_p (i0dest, i2src))));
2789
2790   /* Ensure that I3's pattern can be the destination of combines.  */
2791   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2792                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2793                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2794                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2795                           &i3dest_killed))
2796     {
2797       undo_all ();
2798       return 0;
2799     }
2800
2801   /* See if any of the insns is a MULT operation.  Unless one is, we will
2802      reject a combination that is, since it must be slower.  Be conservative
2803      here.  */
2804   if (GET_CODE (i2src) == MULT
2805       || (i1 != 0 && GET_CODE (i1src) == MULT)
2806       || (i0 != 0 && GET_CODE (i0src) == MULT)
2807       || (GET_CODE (PATTERN (i3)) == SET
2808           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2809     have_mult = 1;
2810
2811   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2812      We used to do this EXCEPT in one case: I3 has a post-inc in an
2813      output operand.  However, that exception can give rise to insns like
2814         mov r3,(r3)+
2815      which is a famous insn on the PDP-11 where the value of r3 used as the
2816      source was model-dependent.  Avoid this sort of thing.  */
2817
2818 #if 0
2819   if (!(GET_CODE (PATTERN (i3)) == SET
2820         && REG_P (SET_SRC (PATTERN (i3)))
2821         && MEM_P (SET_DEST (PATTERN (i3)))
2822         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2823             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2824     /* It's not the exception.  */
2825 #endif
2826 #ifdef AUTO_INC_DEC
2827     {
2828       rtx link;
2829       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2830         if (REG_NOTE_KIND (link) == REG_INC
2831             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2832                 || (i1 != 0
2833                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2834           {
2835             undo_all ();
2836             return 0;
2837           }
2838     }
2839 #endif
2840
2841   /* See if the SETs in I1 or I2 need to be kept around in the merged
2842      instruction: whenever the value set there is still needed past I3.
2843      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2844
2845      For the SET in I1, we have two cases: if I1 and I2 independently feed
2846      into I3, the set in I1 needs to be kept around unless I1DEST dies
2847      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2848      in I1 needs to be kept around unless I1DEST dies or is set in either
2849      I2 or I3.  The same considerations apply to I0.  */
2850
2851   added_sets_2 = !dead_or_set_p (i3, i2dest);
2852
2853   if (i1)
2854     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2855                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2856   else
2857     added_sets_1 = 0;
2858
2859   if (i0)
2860     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2861                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2862                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2863                           && dead_or_set_p (i2, i0dest)));
2864   else
2865     added_sets_0 = 0;
2866
2867   /* We are about to copy insns for the case where they need to be kept
2868      around.  Check that they can be copied in the merged instruction.  */
2869
2870   if (targetm.cannot_copy_insn_p
2871       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2872           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2873           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2874     {
2875       undo_all ();
2876       return 0;
2877     }
2878
2879   /* If the set in I2 needs to be kept around, we must make a copy of
2880      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2881      PATTERN (I2), we are only substituting for the original I1DEST, not into
2882      an already-substituted copy.  This also prevents making self-referential
2883      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2884      I2DEST.  */
2885
2886   if (added_sets_2)
2887     {
2888       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2889         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2890       else
2891         i2pat = copy_rtx (PATTERN (i2));
2892     }
2893
2894   if (added_sets_1)
2895     {
2896       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2897         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2898       else
2899         i1pat = copy_rtx (PATTERN (i1));
2900     }
2901
2902   if (added_sets_0)
2903     {
2904       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2905         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2906       else
2907         i0pat = copy_rtx (PATTERN (i0));
2908     }
2909
2910   combine_merges++;
2911
2912   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2913
2914   maxreg = max_reg_num ();
2915
2916   subst_insn = i3;
2917
2918 #ifndef HAVE_cc0
2919   /* Many machines that don't use CC0 have insns that can both perform an
2920      arithmetic operation and set the condition code.  These operations will
2921      be represented as a PARALLEL with the first element of the vector
2922      being a COMPARE of an arithmetic operation with the constant zero.
2923      The second element of the vector will set some pseudo to the result
2924      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2925      match such a pattern and so will generate an extra insn.   Here we test
2926      for this case, where both the comparison and the operation result are
2927      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2928      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2929
2930   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2931       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2932       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2933       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2934     {
2935       rtx newpat_dest;
2936       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2937       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2938       enum machine_mode compare_mode, orig_compare_mode;
2939       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2940
2941       newpat = PATTERN (i3);
2942       newpat_dest = SET_DEST (newpat);
2943       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2944
2945       if (undobuf.other_insn == 0
2946           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2947                                             &cc_use_insn)))
2948         {
2949           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2950           compare_code = simplify_compare_const (compare_code,
2951                                                  op0, &op1);
2952           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2953         }
2954
2955       /* Do the rest only if op1 is const0_rtx, which may be the
2956          result of simplification.  */
2957       if (op1 == const0_rtx)
2958         {
2959           /* If a single use of the CC is found, prepare to modify it
2960              when SELECT_CC_MODE returns a new CC-class mode, or when
2961              the above simplify_compare_const() returned a new comparison
2962              operator.  undobuf.other_insn is assigned the CC use insn
2963              when modifying it.  */
2964           if (cc_use_loc)
2965             {
2966 #ifdef SELECT_CC_MODE
2967               enum machine_mode new_mode
2968                 = SELECT_CC_MODE (compare_code, op0, op1);
2969               if (new_mode != orig_compare_mode
2970                   && can_change_dest_mode (SET_DEST (newpat),
2971                                            added_sets_2, new_mode))
2972                 {
2973                   unsigned int regno = REGNO (newpat_dest);
2974                   compare_mode = new_mode;
2975                   if (regno < FIRST_PSEUDO_REGISTER)
2976                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2977                   else
2978                     {
2979                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2980                       newpat_dest = regno_reg_rtx[regno];
2981                     }
2982                 }
2983 #endif
2984               /* Cases for modifying the CC-using comparison.  */
2985               if (compare_code != orig_compare_code
2986                   /* ??? Do we need to verify the zero rtx?  */
2987                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2988                 {
2989                   /* Replace cc_use_loc with entire new RTX.  */
2990                   SUBST (*cc_use_loc,
2991                          gen_rtx_fmt_ee (compare_code, compare_mode,
2992                                          newpat_dest, const0_rtx));
2993                   undobuf.other_insn = cc_use_insn;
2994                 }
2995               else if (compare_mode != orig_compare_mode)
2996                 {
2997                   /* Just replace the CC reg with a new mode.  */
2998                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
2999                   undobuf.other_insn = cc_use_insn;
3000                 }
3001             }
3002
3003           /* Now we modify the current newpat:
3004              First, SET_DEST(newpat) is updated if the CC mode has been
3005              altered. For targets without SELECT_CC_MODE, this should be
3006              optimized away.  */
3007           if (compare_mode != orig_compare_mode)
3008             SUBST (SET_DEST (newpat), newpat_dest);
3009           /* This is always done to propagate i2src into newpat.  */
3010           SUBST (SET_SRC (newpat),
3011                  gen_rtx_COMPARE (compare_mode, op0, op1));
3012           /* Create new version of i2pat if needed; the below PARALLEL
3013              creation needs this to work correctly.  */
3014           if (! rtx_equal_p (i2src, op0))
3015             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3016           i2_is_used = 1;
3017         }
3018     }
3019 #endif
3020
3021   if (i2_is_used == 0)
3022     {
3023       /* It is possible that the source of I2 or I1 may be performing
3024          an unneeded operation, such as a ZERO_EXTEND of something
3025          that is known to have the high part zero.  Handle that case
3026          by letting subst look at the inner insns.
3027
3028          Another way to do this would be to have a function that tries
3029          to simplify a single insn instead of merging two or more
3030          insns.  We don't do this because of the potential of infinite
3031          loops and because of the potential extra memory required.
3032          However, doing it the way we are is a bit of a kludge and
3033          doesn't catch all cases.
3034
3035          But only do this if -fexpensive-optimizations since it slows
3036          things down and doesn't usually win.
3037
3038          This is not done in the COMPARE case above because the
3039          unmodified I2PAT is used in the PARALLEL and so a pattern
3040          with a modified I2SRC would not match.  */
3041
3042       if (flag_expensive_optimizations)
3043         {
3044           /* Pass pc_rtx so no substitutions are done, just
3045              simplifications.  */
3046           if (i1)
3047             {
3048               subst_low_luid = DF_INSN_LUID (i1);
3049               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3050             }
3051
3052           subst_low_luid = DF_INSN_LUID (i2);
3053           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3054         }
3055
3056       n_occurrences = 0;                /* `subst' counts here */
3057       subst_low_luid = DF_INSN_LUID (i2);
3058
3059       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3060          copy of I2SRC each time we substitute it, in order to avoid creating
3061          self-referential RTL when we will be substituting I1SRC for I1DEST
3062          later.  Likewise if I0 feeds into I2, either directly or indirectly
3063          through I1, and I0DEST is in I0SRC.  */
3064       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3065                       (i1_feeds_i2_n && i1dest_in_i1src)
3066                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3067                           && i0dest_in_i0src));
3068       substed_i2 = 1;
3069
3070       /* Record whether I2's body now appears within I3's body.  */
3071       i2_is_used = n_occurrences;
3072     }
3073
3074   /* If we already got a failure, don't try to do more.  Otherwise, try to
3075      substitute I1 if we have it.  */
3076
3077   if (i1 && GET_CODE (newpat) != CLOBBER)
3078     {
3079       /* Check that an autoincrement side-effect on I1 has not been lost.
3080          This happens if I1DEST is mentioned in I2 and dies there, and
3081          has disappeared from the new pattern.  */
3082       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3083            && i1_feeds_i2_n
3084            && dead_or_set_p (i2, i1dest)
3085            && !reg_overlap_mentioned_p (i1dest, newpat))
3086            /* Before we can do this substitution, we must redo the test done
3087               above (see detailed comments there) that ensures I1DEST isn't
3088               mentioned in any SETs in NEWPAT that are field assignments.  */
3089           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3090                                 0, 0, 0))
3091         {
3092           undo_all ();
3093           return 0;
3094         }
3095
3096       n_occurrences = 0;
3097       subst_low_luid = DF_INSN_LUID (i1);
3098
3099       /* If the following substitution will modify I1SRC, make a copy of it
3100          for the case where it is substituted for I1DEST in I2PAT later.  */
3101       if (added_sets_2 && i1_feeds_i2_n)
3102         i1src_copy = copy_rtx (i1src);
3103
3104       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3105          copy of I1SRC each time we substitute it, in order to avoid creating
3106          self-referential RTL when we will be substituting I0SRC for I0DEST
3107          later.  */
3108       newpat = subst (newpat, i1dest, i1src, 0, 0,
3109                       i0_feeds_i1_n && i0dest_in_i0src);
3110       substed_i1 = 1;
3111
3112       /* Record whether I1's body now appears within I3's body.  */
3113       i1_is_used = n_occurrences;
3114     }
3115
3116   /* Likewise for I0 if we have it.  */
3117
3118   if (i0 && GET_CODE (newpat) != CLOBBER)
3119     {
3120       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3121            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3122                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3123            && !reg_overlap_mentioned_p (i0dest, newpat))
3124           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3125                                 0, 0, 0))
3126         {
3127           undo_all ();
3128           return 0;
3129         }
3130
3131       /* If the following substitution will modify I0SRC, make a copy of it
3132          for the case where it is substituted for I0DEST in I1PAT later.  */
3133       if (added_sets_1 && i0_feeds_i1_n)
3134         i0src_copy = copy_rtx (i0src);
3135       /* And a copy for I0DEST in I2PAT substitution.  */
3136       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3137                            || (i0_feeds_i2_n)))
3138         i0src_copy2 = copy_rtx (i0src);
3139
3140       n_occurrences = 0;
3141       subst_low_luid = DF_INSN_LUID (i0);
3142       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3143       substed_i0 = 1;
3144     }
3145
3146   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3147      to count all the ways that I2SRC and I1SRC can be used.  */
3148   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3149        && i2_is_used + added_sets_2 > 1)
3150       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3151           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3152               > 1))
3153       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3154           && (n_occurrences + added_sets_0
3155               + (added_sets_1 && i0_feeds_i1_n)
3156               + (added_sets_2 && i0_feeds_i2_n)
3157               > 1))
3158       /* Fail if we tried to make a new register.  */
3159       || max_reg_num () != maxreg
3160       /* Fail if we couldn't do something and have a CLOBBER.  */
3161       || GET_CODE (newpat) == CLOBBER
3162       /* Fail if this new pattern is a MULT and we didn't have one before
3163          at the outer level.  */
3164       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3165           && ! have_mult))
3166     {
3167       undo_all ();
3168       return 0;
3169     }
3170
3171   /* If the actions of the earlier insns must be kept
3172      in addition to substituting them into the latest one,
3173      we must make a new PARALLEL for the latest insn
3174      to hold additional the SETs.  */
3175
3176   if (added_sets_0 || added_sets_1 || added_sets_2)
3177     {
3178       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3179       combine_extras++;
3180
3181       if (GET_CODE (newpat) == PARALLEL)
3182         {
3183           rtvec old = XVEC (newpat, 0);
3184           total_sets = XVECLEN (newpat, 0) + extra_sets;
3185           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3186           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3187                   sizeof (old->elem[0]) * old->num_elem);
3188         }
3189       else
3190         {
3191           rtx old = newpat;
3192           total_sets = 1 + extra_sets;
3193           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3194           XVECEXP (newpat, 0, 0) = old;
3195         }
3196
3197       if (added_sets_0)
3198         XVECEXP (newpat, 0, --total_sets) = i0pat;
3199
3200       if (added_sets_1)
3201         {
3202           rtx t = i1pat;
3203           if (i0_feeds_i1_n)
3204             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3205
3206           XVECEXP (newpat, 0, --total_sets) = t;
3207         }
3208       if (added_sets_2)
3209         {
3210           rtx t = i2pat;
3211           if (i1_feeds_i2_n)
3212             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3213                        i0_feeds_i1_n && i0dest_in_i0src);
3214           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3215             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3216
3217           XVECEXP (newpat, 0, --total_sets) = t;
3218         }
3219     }
3220
3221  validate_replacement:
3222
3223   /* Note which hard regs this insn has as inputs.  */
3224   mark_used_regs_combine (newpat);
3225
3226   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3227      consider splitting this pattern, we might need these clobbers.  */
3228   if (i1 && GET_CODE (newpat) == PARALLEL
3229       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3230     {
3231       int len = XVECLEN (newpat, 0);
3232
3233       newpat_vec_with_clobbers = rtvec_alloc (len);
3234       for (i = 0; i < len; i++)
3235         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3236     }
3237
3238   /* Is the result of combination a valid instruction?  */
3239   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3240
3241   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242      the second SET's destination is a register that is unused and isn't
3243      marked as an instruction that might trap in an EH region.  In that case,
3244      we just need the first SET.   This can occur when simplifying a divmod
3245      insn.  We *must* test for this case here because the code below that
3246      splits two independent SETs doesn't handle this case correctly when it
3247      updates the register status.
3248
3249      It's pointless doing this if we originally had two sets, one from
3250      i3, and one from i2.  Combining then splitting the parallel results
3251      in the original i2 again plus an invalid insn (which we delete).
3252      The net effect is only to move instructions around, which makes
3253      debug info less accurate.
3254
3255      Also check the case where the first SET's destination is unused.
3256      That would not cause incorrect code, but does cause an unneeded
3257      insn to remain.  */
3258
3259   if (insn_code_number < 0
3260       && !(added_sets_2 && i1 == 0)
3261       && GET_CODE (newpat) == PARALLEL
3262       && XVECLEN (newpat, 0) == 2
3263       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3264       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3265       && asm_noperands (newpat) < 0)
3266     {
3267       rtx set0 = XVECEXP (newpat, 0, 0);
3268       rtx set1 = XVECEXP (newpat, 0, 1);
3269
3270       if (((REG_P (SET_DEST (set1))
3271             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3272            || (GET_CODE (SET_DEST (set1)) == SUBREG
3273                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3274           && insn_nothrow_p (i3)
3275           && !side_effects_p (SET_SRC (set1)))
3276         {
3277           newpat = set0;
3278           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3279         }
3280
3281       else if (((REG_P (SET_DEST (set0))
3282                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3283                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3284                     && find_reg_note (i3, REG_UNUSED,
3285                                       SUBREG_REG (SET_DEST (set0)))))
3286                && insn_nothrow_p (i3)
3287                && !side_effects_p (SET_SRC (set0)))
3288         {
3289           newpat = set1;
3290           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3291
3292           if (insn_code_number >= 0)
3293             changed_i3_dest = 1;
3294         }
3295     }
3296
3297   /* If we were combining three insns and the result is a simple SET
3298      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299      insns.  There are two ways to do this.  It can be split using a
3300      machine-specific method (like when you have an addition of a large
3301      constant) or by combine in the function find_split_point.  */
3302
3303   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3304       && asm_noperands (newpat) < 0)
3305     {
3306       rtx parallel, m_split, *split;
3307
3308       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3309          use I2DEST as a scratch register will help.  In the latter case,
3310          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3311
3312       m_split = combine_split_insns (newpat, i3);
3313
3314       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315          inputs of NEWPAT.  */
3316
3317       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318          possible to try that as a scratch reg.  This would require adding
3319          more code to make it work though.  */
3320
3321       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3322         {
3323           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3324
3325           /* First try to split using the original register as a
3326              scratch register.  */
3327           parallel = gen_rtx_PARALLEL (VOIDmode,
3328                                        gen_rtvec (2, newpat,
3329                                                   gen_rtx_CLOBBER (VOIDmode,
3330                                                                    i2dest)));
3331           m_split = combine_split_insns (parallel, i3);
3332
3333           /* If that didn't work, try changing the mode of I2DEST if
3334              we can.  */
3335           if (m_split == 0
3336               && new_mode != GET_MODE (i2dest)
3337               && new_mode != VOIDmode
3338               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3339             {
3340               enum machine_mode old_mode = GET_MODE (i2dest);
3341               rtx ni2dest;
3342
3343               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3344                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3345               else
3346                 {
3347                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3348                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3349                 }
3350
3351               parallel = (gen_rtx_PARALLEL
3352                           (VOIDmode,
3353                            gen_rtvec (2, newpat,
3354                                       gen_rtx_CLOBBER (VOIDmode,
3355                                                        ni2dest))));
3356               m_split = combine_split_insns (parallel, i3);
3357
3358               if (m_split == 0
3359                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3360                 {
3361                   struct undo *buf;
3362
3363                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3364                   buf = undobuf.undos;
3365                   undobuf.undos = buf->next;
3366                   buf->next = undobuf.frees;
3367                   undobuf.frees = buf;
3368                 }
3369             }
3370
3371           i2scratch = m_split != 0;
3372         }
3373
3374       /* If recog_for_combine has discarded clobbers, try to use them
3375          again for the split.  */
3376       if (m_split == 0 && newpat_vec_with_clobbers)
3377         {
3378           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3379           m_split = combine_split_insns (parallel, i3);
3380         }
3381
3382       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3383         {
3384           m_split = PATTERN (m_split);
3385           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3386           if (insn_code_number >= 0)
3387             newpat = m_split;
3388         }
3389       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3390                && (next_nonnote_nondebug_insn (i2) == i3
3391                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3392         {
3393           rtx i2set, i3set;
3394           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3395           newi2pat = PATTERN (m_split);
3396
3397           i3set = single_set (NEXT_INSN (m_split));
3398           i2set = single_set (m_split);
3399
3400           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3401
3402           /* If I2 or I3 has multiple SETs, we won't know how to track
3403              register status, so don't use these insns.  If I2's destination
3404              is used between I2 and I3, we also can't use these insns.  */
3405
3406           if (i2_code_number >= 0 && i2set && i3set
3407               && (next_nonnote_nondebug_insn (i2) == i3
3408                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3409             insn_code_number = recog_for_combine (&newi3pat, i3,
3410                                                   &new_i3_notes);
3411           if (insn_code_number >= 0)
3412             newpat = newi3pat;
3413
3414           /* It is possible that both insns now set the destination of I3.
3415              If so, we must show an extra use of it.  */
3416
3417           if (insn_code_number >= 0)
3418             {
3419               rtx new_i3_dest = SET_DEST (i3set);
3420               rtx new_i2_dest = SET_DEST (i2set);
3421
3422               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3423                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3424                      || GET_CODE (new_i3_dest) == SUBREG)
3425                 new_i3_dest = XEXP (new_i3_dest, 0);
3426
3427               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3428                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3429                      || GET_CODE (new_i2_dest) == SUBREG)
3430                 new_i2_dest = XEXP (new_i2_dest, 0);
3431
3432               if (REG_P (new_i3_dest)
3433                   && REG_P (new_i2_dest)
3434                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3435                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3436             }
3437         }
3438
3439       /* If we can split it and use I2DEST, go ahead and see if that
3440          helps things be recognized.  Verify that none of the registers
3441          are set between I2 and I3.  */
3442       if (insn_code_number < 0
3443           && (split = find_split_point (&newpat, i3, false)) != 0
3444 #ifdef HAVE_cc0
3445           && REG_P (i2dest)
3446 #endif
3447           /* We need I2DEST in the proper mode.  If it is a hard register
3448              or the only use of a pseudo, we can change its mode.
3449              Make sure we don't change a hard register to have a mode that
3450              isn't valid for it, or change the number of registers.  */
3451           && (GET_MODE (*split) == GET_MODE (i2dest)
3452               || GET_MODE (*split) == VOIDmode
3453               || can_change_dest_mode (i2dest, added_sets_2,
3454                                        GET_MODE (*split)))
3455           && (next_nonnote_nondebug_insn (i2) == i3
3456               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3457           /* We can't overwrite I2DEST if its value is still used by
3458              NEWPAT.  */
3459           && ! reg_referenced_p (i2dest, newpat))
3460         {
3461           rtx newdest = i2dest;
3462           enum rtx_code split_code = GET_CODE (*split);
3463           enum machine_mode split_mode = GET_MODE (*split);
3464           bool subst_done = false;
3465           newi2pat = NULL_RTX;
3466
3467           i2scratch = true;
3468
3469           /* *SPLIT may be part of I2SRC, so make sure we have the
3470              original expression around for later debug processing.
3471              We should not need I2SRC any more in other cases.  */
3472           if (MAY_HAVE_DEBUG_INSNS)
3473             i2src = copy_rtx (i2src);
3474           else
3475             i2src = NULL;
3476
3477           /* Get NEWDEST as a register in the proper mode.  We have already
3478              validated that we can do this.  */
3479           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3480             {
3481               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3482                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3483               else
3484                 {
3485                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3486                   newdest = regno_reg_rtx[REGNO (i2dest)];
3487                 }
3488             }
3489
3490           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491              an ASHIFT.  This can occur if it was inside a PLUS and hence
3492              appeared to be a memory address.  This is a kludge.  */
3493           if (split_code == MULT
3494               && CONST_INT_P (XEXP (*split, 1))
3495               && INTVAL (XEXP (*split, 1)) > 0
3496               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3497             {
3498               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3499                                              XEXP (*split, 0), GEN_INT (i)));
3500               /* Update split_code because we may not have a multiply
3501                  anymore.  */
3502               split_code = GET_CODE (*split);
3503             }
3504
3505 #ifdef INSN_SCHEDULING
3506           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507              be written as a ZERO_EXTEND.  */
3508           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3509             {
3510 #ifdef LOAD_EXTEND_OP
3511               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512                  what it really is.  */
3513               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3514                   == SIGN_EXTEND)
3515                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3516                                                     SUBREG_REG (*split)));
3517               else
3518 #endif
3519                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3520                                                     SUBREG_REG (*split)));
3521             }
3522 #endif
3523
3524           /* Attempt to split binary operators using arithmetic identities.  */
3525           if (BINARY_P (SET_SRC (newpat))
3526               && split_mode == GET_MODE (SET_SRC (newpat))
3527               && ! side_effects_p (SET_SRC (newpat)))
3528             {
3529               rtx setsrc = SET_SRC (newpat);
3530               enum machine_mode mode = GET_MODE (setsrc);
3531               enum rtx_code code = GET_CODE (setsrc);
3532               rtx src_op0 = XEXP (setsrc, 0);
3533               rtx src_op1 = XEXP (setsrc, 1);
3534
3535               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3536               if (rtx_equal_p (src_op0, src_op1))
3537                 {
3538                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3539                   SUBST (XEXP (setsrc, 0), newdest);
3540                   SUBST (XEXP (setsrc, 1), newdest);
3541                   subst_done = true;
3542                 }
3543               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3544               else if ((code == PLUS || code == MULT)
3545                        && GET_CODE (src_op0) == code
3546                        && GET_CODE (XEXP (src_op0, 0)) == code
3547                        && (INTEGRAL_MODE_P (mode)
3548                            || (FLOAT_MODE_P (mode)
3549                                && flag_unsafe_math_optimizations)))
3550                 {
3551                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3552                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3553                   rtx r = XEXP (src_op0, 1);
3554                   rtx s = src_op1;
3555
3556                   /* Split both "((X op Y) op X) op Y" and
3557                      "((X op Y) op Y) op X" as "T op T" where T is
3558                      "X op Y".  */
3559                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3560                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3561                     {
3562                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3563                                               XEXP (src_op0, 0));
3564                       SUBST (XEXP (setsrc, 0), newdest);
3565                       SUBST (XEXP (setsrc, 1), newdest);
3566                       subst_done = true;
3567                     }
3568                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3569                      T is "X op Y".  */
3570                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3571                     {
3572                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3573                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3574                       SUBST (XEXP (setsrc, 0), newdest);
3575                       SUBST (XEXP (setsrc, 1), newdest);
3576                       subst_done = true;
3577                     }
3578                 }
3579             }
3580
3581           if (!subst_done)
3582             {
3583               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3584               SUBST (*split, newdest);
3585             }
3586
3587           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3588
3589           /* recog_for_combine might have added CLOBBERs to newi2pat.
3590              Make sure NEWPAT does not depend on the clobbered regs.  */
3591           if (GET_CODE (newi2pat) == PARALLEL)
3592             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3593               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3594                 {
3595                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3596                   if (reg_overlap_mentioned_p (reg, newpat))
3597                     {
3598                       undo_all ();
3599                       return 0;
3600                     }
3601                 }
3602
3603           /* If the split point was a MULT and we didn't have one before,
3604              don't use one now.  */
3605           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3606             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3607         }
3608     }
3609
3610   /* Check for a case where we loaded from memory in a narrow mode and
3611      then sign extended it, but we need both registers.  In that case,
3612      we have a PARALLEL with both loads from the same memory location.
3613      We can split this into a load from memory followed by a register-register
3614      copy.  This saves at least one insn, more if register allocation can
3615      eliminate the copy.
3616
3617      We cannot do this if the destination of the first assignment is a
3618      condition code register or cc0.  We eliminate this case by making sure
3619      the SET_DEST and SET_SRC have the same mode.
3620
3621      We cannot do this if the destination of the second assignment is
3622      a register that we have already assumed is zero-extended.  Similarly
3623      for a SUBREG of such a register.  */
3624
3625   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3626            && GET_CODE (newpat) == PARALLEL
3627            && XVECLEN (newpat, 0) == 2
3628            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3629            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3630            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3631                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3632            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3633            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3634                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3635            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3636                                    DF_INSN_LUID (i2))
3637            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3638            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3639            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3640                  (REG_P (temp)
3641                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3642                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3643                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3644                   && (reg_stat[REGNO (temp)].nonzero_bits
3645                       != GET_MODE_MASK (word_mode))))
3646            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3647                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3648                      (REG_P (temp)
3649                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3650                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3651                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3652                       && (reg_stat[REGNO (temp)].nonzero_bits
3653                           != GET_MODE_MASK (word_mode)))))
3654            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3655                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3656            && ! find_reg_note (i3, REG_UNUSED,
3657                                SET_DEST (XVECEXP (newpat, 0, 0))))
3658     {
3659       rtx ni2dest;
3660
3661       newi2pat = XVECEXP (newpat, 0, 0);
3662       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3663       newpat = XVECEXP (newpat, 0, 1);
3664       SUBST (SET_SRC (newpat),
3665              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3666       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3667
3668       if (i2_code_number >= 0)
3669         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3670
3671       if (insn_code_number >= 0)
3672         swap_i2i3 = 1;
3673     }
3674
3675   /* Similarly, check for a case where we have a PARALLEL of two independent
3676      SETs but we started with three insns.  In this case, we can do the sets
3677      as two separate insns.  This case occurs when some SET allows two
3678      other insns to combine, but the destination of that SET is still live.  */
3679
3680   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3681            && GET_CODE (newpat) == PARALLEL
3682            && XVECLEN (newpat, 0) == 2
3683            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3684            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3685            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3686            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3687            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3688            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3689            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3690                                   XVECEXP (newpat, 0, 0))
3691            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3692                                   XVECEXP (newpat, 0, 1))
3693            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3694                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3695     {
3696       rtx set0 = XVECEXP (newpat, 0, 0);
3697       rtx set1 = XVECEXP (newpat, 0, 1);
3698
3699       /* Normally, it doesn't matter which of the two is done first,
3700          but the one that references cc0 can't be the second, and
3701          one which uses any regs/memory set in between i2 and i3 can't
3702          be first.  The PARALLEL might also have been pre-existing in i3,
3703          so we need to make sure that we won't wrongly hoist a SET to i2
3704          that would conflict with a death note present in there.  */
3705       if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3706           && !(REG_P (SET_DEST (set1))
3707                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3708           && !(GET_CODE (SET_DEST (set1)) == SUBREG
3709                && find_reg_note (i2, REG_DEAD,
3710                                  SUBREG_REG (SET_DEST (set1))))
3711 #ifdef HAVE_cc0
3712           && !reg_referenced_p (cc0_rtx, set0)
3713 #endif
3714          )
3715         {
3716           newi2pat = set1;
3717           newpat = set0;
3718         }
3719       else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3720                && !(REG_P (SET_DEST (set0))
3721                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3722                && !(GET_CODE (SET_DEST (set0)) == SUBREG
3723                     && find_reg_note (i2, REG_DEAD,
3724                                       SUBREG_REG (SET_DEST (set0))))
3725 #ifdef HAVE_cc0
3726                && !reg_referenced_p (cc0_rtx, set1)
3727 #endif
3728               )
3729         {
3730           newi2pat = set0;
3731           newpat = set1;
3732         }
3733       else
3734         {
3735           undo_all ();
3736           return 0;
3737         }
3738
3739       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3740
3741       if (i2_code_number >= 0)
3742         {
3743           /* recog_for_combine might have added CLOBBERs to newi2pat.
3744              Make sure NEWPAT does not depend on the clobbered regs.  */
3745           if (GET_CODE (newi2pat) == PARALLEL)
3746             {
3747               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3748                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3749                   {
3750                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3751                     if (reg_overlap_mentioned_p (reg, newpat))
3752                       {
3753                         undo_all ();
3754                         return 0;
3755                       }
3756                   }
3757             }
3758
3759           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3760         }
3761     }
3762
3763   /* If it still isn't recognized, fail and change things back the way they
3764      were.  */
3765   if ((insn_code_number < 0
3766        /* Is the result a reasonable ASM_OPERANDS?  */
3767        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3768     {
3769       undo_all ();
3770       return 0;
3771     }
3772
3773   /* If we had to change another insn, make sure it is valid also.  */
3774   if (undobuf.other_insn)
3775     {
3776       CLEAR_HARD_REG_SET (newpat_used_regs);
3777
3778       other_pat = PATTERN (undobuf.other_insn);
3779       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3780                                              &new_other_notes);
3781
3782       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3783         {
3784           undo_all ();
3785           return 0;
3786         }
3787     }
3788
3789 #ifdef HAVE_cc0
3790   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3791      they are adjacent to each other or not.  */
3792   {
3793     rtx p = prev_nonnote_insn (i3);
3794     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3795         && sets_cc0_p (newi2pat))
3796       {
3797         undo_all ();
3798         return 0;
3799       }
3800   }
3801 #endif
3802
3803   /* Only allow this combination if insn_rtx_costs reports that the
3804      replacement instructions are cheaper than the originals.  */
3805   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3806     {
3807       undo_all ();
3808       return 0;
3809     }
3810
3811   if (MAY_HAVE_DEBUG_INSNS)
3812     {
3813       struct undo *undo;
3814
3815       for (undo = undobuf.undos; undo; undo = undo->next)
3816         if (undo->kind == UNDO_MODE)
3817           {
3818             rtx reg = *undo->where.r;
3819             enum machine_mode new_mode = GET_MODE (reg);
3820             enum machine_mode old_mode = undo->old_contents.m;
3821
3822             /* Temporarily revert mode back.  */
3823             adjust_reg_mode (reg, old_mode);
3824
3825             if (reg == i2dest && i2scratch)
3826               {
3827                 /* If we used i2dest as a scratch register with a
3828                    different mode, substitute it for the original
3829                    i2src while its original mode is temporarily
3830                    restored, and then clear i2scratch so that we don't
3831                    do it again later.  */
3832                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3833                                      this_basic_block);
3834                 i2scratch = false;
3835                 /* Put back the new mode.  */
3836                 adjust_reg_mode (reg, new_mode);
3837               }
3838             else
3839               {
3840                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3841                 rtx first, last;
3842
3843                 if (reg == i2dest)
3844                   {
3845                     first = i2;
3846                     last = last_combined_insn;
3847                   }
3848                 else
3849                   {
3850                     first = i3;
3851                     last = undobuf.other_insn;
3852                     gcc_assert (last);
3853                     if (DF_INSN_LUID (last)
3854                         < DF_INSN_LUID (last_combined_insn))
3855                       last = last_combined_insn;
3856                   }
3857
3858                 /* We're dealing with a reg that changed mode but not
3859                    meaning, so we want to turn it into a subreg for
3860                    the new mode.  However, because of REG sharing and
3861                    because its mode had already changed, we have to do
3862                    it in two steps.  First, replace any debug uses of
3863                    reg, with its original mode temporarily restored,
3864                    with this copy we have created; then, replace the
3865                    copy with the SUBREG of the original shared reg,
3866                    once again changed to the new mode.  */
3867                 propagate_for_debug (first, last, reg, tempreg,
3868                                      this_basic_block);
3869                 adjust_reg_mode (reg, new_mode);
3870                 propagate_for_debug (first, last, tempreg,
3871                                      lowpart_subreg (old_mode, reg, new_mode),
3872                                      this_basic_block);
3873               }
3874           }
3875     }
3876
3877   /* If we will be able to accept this, we have made a
3878      change to the destination of I3.  This requires us to
3879      do a few adjustments.  */
3880
3881   if (changed_i3_dest)
3882     {
3883       PATTERN (i3) = newpat;
3884       adjust_for_new_dest (i3);
3885     }
3886
3887   /* We now know that we can do this combination.  Merge the insns and
3888      update the status of registers and LOG_LINKS.  */
3889
3890   if (undobuf.other_insn)
3891     {
3892       rtx note, next;
3893
3894       PATTERN (undobuf.other_insn) = other_pat;
3895
3896       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3897          are still valid.  Then add any non-duplicate notes added by
3898          recog_for_combine.  */
3899       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3900         {
3901           next = XEXP (note, 1);
3902
3903           if (REG_NOTE_KIND (note) == REG_UNUSED
3904               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3905             remove_note (undobuf.other_insn, note);
3906         }
3907
3908       distribute_notes (new_other_notes, undobuf.other_insn,
3909                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3910                         NULL_RTX);
3911     }
3912
3913   if (swap_i2i3)
3914     {
3915       rtx insn;
3916       struct insn_link *link;
3917       rtx ni2dest;
3918
3919       /* I3 now uses what used to be its destination and which is now
3920          I2's destination.  This requires us to do a few adjustments.  */
3921       PATTERN (i3) = newpat;
3922       adjust_for_new_dest (i3);
3923
3924       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3925          so we still will.
3926
3927          However, some later insn might be using I2's dest and have
3928          a LOG_LINK pointing at I3.  We must remove this link.
3929          The simplest way to remove the link is to point it at I1,
3930          which we know will be a NOTE.  */
3931
3932       /* newi2pat is usually a SET here; however, recog_for_combine might
3933          have added some clobbers.  */
3934       if (GET_CODE (newi2pat) == PARALLEL)
3935         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3936       else
3937         ni2dest = SET_DEST (newi2pat);
3938
3939       for (insn = NEXT_INSN (i3);
3940            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3941                     || insn != BB_HEAD (this_basic_block->next_bb));
3942            insn = NEXT_INSN (insn))
3943         {
3944           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3945             {
3946               FOR_EACH_LOG_LINK (link, insn)
3947                 if (link->insn == i3)
3948                   link->insn = i1;
3949
3950               break;
3951             }
3952         }
3953     }
3954
3955   {
3956     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3957     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3958     rtx midnotes = 0;
3959     int from_luid;
3960     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3961        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3962        same as i3dest, in which case newi2pat may be setting i1dest.  */
3963     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3964                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3965                    || !i2dest_killed
3966                    ? 0 : i2dest);
3967     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3968                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3969                    || !i1dest_killed
3970                    ? 0 : i1dest);
3971     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3972                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3973                    || !i0dest_killed
3974                    ? 0 : i0dest);
3975
3976     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3977        clear them.  */
3978     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3979     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3980     if (i1)
3981       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3982     if (i0)
3983       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3984
3985     /* Ensure that we do not have something that should not be shared but
3986        occurs multiple times in the new insns.  Check this by first
3987        resetting all the `used' flags and then copying anything is shared.  */
3988
3989     reset_used_flags (i3notes);
3990     reset_used_flags (i2notes);
3991     reset_used_flags (i1notes);
3992     reset_used_flags (i0notes);
3993     reset_used_flags (newpat);
3994     reset_used_flags (newi2pat);
3995     if (undobuf.other_insn)
3996       reset_used_flags (PATTERN (undobuf.other_insn));
3997
3998     i3notes = copy_rtx_if_shared (i3notes);
3999     i2notes = copy_rtx_if_shared (i2notes);
4000     i1notes = copy_rtx_if_shared (i1notes);
4001     i0notes = copy_rtx_if_shared (i0notes);
4002     newpat = copy_rtx_if_shared (newpat);
4003     newi2pat = copy_rtx_if_shared (newi2pat);
4004     if (undobuf.other_insn)
4005       reset_used_flags (PATTERN (undobuf.other_insn));
4006
4007     INSN_CODE (i3) = insn_code_number;
4008     PATTERN (i3) = newpat;
4009
4010     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4011       {
4012         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4013
4014         reset_used_flags (call_usage);
4015         call_usage = copy_rtx (call_usage);
4016
4017         if (substed_i2)
4018           {
4019             /* I2SRC must still be meaningful at this point.  Some splitting
4020                operations can invalidate I2SRC, but those operations do not
4021                apply to calls.  */
4022             gcc_assert (i2src);
4023             replace_rtx (call_usage, i2dest, i2src);
4024           }
4025
4026         if (substed_i1)
4027           replace_rtx (call_usage, i1dest, i1src);
4028         if (substed_i0)
4029           replace_rtx (call_usage, i0dest, i0src);
4030
4031         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4032       }
4033
4034     if (undobuf.other_insn)
4035       INSN_CODE (undobuf.other_insn) = other_code_number;
4036
4037     /* We had one special case above where I2 had more than one set and
4038        we replaced a destination of one of those sets with the destination
4039        of I3.  In that case, we have to update LOG_LINKS of insns later
4040        in this basic block.  Note that this (expensive) case is rare.
4041
4042        Also, in this case, we must pretend that all REG_NOTEs for I2
4043        actually came from I3, so that REG_UNUSED notes from I2 will be
4044        properly handled.  */
4045
4046     if (i3_subst_into_i2)
4047       {
4048         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4049           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4050                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4051               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4052               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4053               && ! find_reg_note (i2, REG_UNUSED,
4054                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4055             for (temp = NEXT_INSN (i2);
4056                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4057                           || BB_HEAD (this_basic_block) != temp);
4058                  temp = NEXT_INSN (temp))
4059               if (temp != i3 && INSN_P (temp))
4060                 FOR_EACH_LOG_LINK (link, temp)
4061                   if (link->insn == i2)
4062                     link->insn = i3;
4063
4064         if (i3notes)
4065           {
4066             rtx link = i3notes;
4067             while (XEXP (link, 1))
4068               link = XEXP (link, 1);
4069             XEXP (link, 1) = i2notes;
4070           }
4071         else
4072           i3notes = i2notes;
4073         i2notes = 0;
4074       }
4075
4076     LOG_LINKS (i3) = NULL;
4077     REG_NOTES (i3) = 0;
4078     LOG_LINKS (i2) = NULL;
4079     REG_NOTES (i2) = 0;
4080
4081     if (newi2pat)
4082       {
4083         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4084           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4085                                this_basic_block);
4086         INSN_CODE (i2) = i2_code_number;
4087         PATTERN (i2) = newi2pat;
4088       }
4089     else
4090       {
4091         if (MAY_HAVE_DEBUG_INSNS && i2src)
4092           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4093                                this_basic_block);
4094         SET_INSN_DELETED (i2);
4095       }
4096
4097     if (i1)
4098       {
4099         LOG_LINKS (i1) = NULL;
4100         REG_NOTES (i1) = 0;
4101         if (MAY_HAVE_DEBUG_INSNS)
4102           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4103                                this_basic_block);
4104         SET_INSN_DELETED (i1);
4105       }
4106
4107     if (i0)
4108       {
4109         LOG_LINKS (i0) = NULL;
4110         REG_NOTES (i0) = 0;
4111         if (MAY_HAVE_DEBUG_INSNS)
4112           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4113                                this_basic_block);
4114         SET_INSN_DELETED (i0);
4115       }
4116
4117     /* Get death notes for everything that is now used in either I3 or
4118        I2 and used to die in a previous insn.  If we built two new
4119        patterns, move from I1 to I2 then I2 to I3 so that we get the
4120        proper movement on registers that I2 modifies.  */
4121
4122     if (i0)
4123       from_luid = DF_INSN_LUID (i0);
4124     else if (i1)
4125       from_luid = DF_INSN_LUID (i1);
4126     else
4127       from_luid = DF_INSN_LUID (i2);
4128     if (newi2pat)
4129       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4130     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4131
4132     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4133     if (i3notes)
4134       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4135                         elim_i2, elim_i1, elim_i0);
4136     if (i2notes)
4137       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4138                         elim_i2, elim_i1, elim_i0);
4139     if (i1notes)
4140       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4141                         elim_i2, elim_i1, elim_i0);
4142     if (i0notes)
4143       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4144                         elim_i2, elim_i1, elim_i0);
4145     if (midnotes)
4146       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4147                         elim_i2, elim_i1, elim_i0);
4148
4149     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4150        know these are REG_UNUSED and want them to go to the desired insn,
4151        so we always pass it as i3.  */
4152
4153     if (newi2pat && new_i2_notes)
4154       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4155                         NULL_RTX);
4156
4157     if (new_i3_notes)
4158       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4159                         NULL_RTX);
4160
4161     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4162        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4163        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4164        in that case, it might delete I2.  Similarly for I2 and I1.
4165        Show an additional death due to the REG_DEAD note we make here.  If
4166        we discard it in distribute_notes, we will decrement it again.  */
4167
4168     if (i3dest_killed)
4169       {
4170         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4171         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4172           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4173                             elim_i1, elim_i0);
4174         else
4175           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4176                             elim_i2, elim_i1, elim_i0);
4177       }
4178
4179     if (i2dest_in_i2src)
4180       {
4181         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4182         if (newi2pat && reg_set_p (i2dest, newi2pat))
4183           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4184                             NULL_RTX, NULL_RTX);
4185         else
4186           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4187                             NULL_RTX, NULL_RTX, NULL_RTX);
4188       }
4189
4190     if (i1dest_in_i1src)
4191       {
4192         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4193         if (newi2pat && reg_set_p (i1dest, newi2pat))
4194           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4195                             NULL_RTX, NULL_RTX);
4196         else
4197           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4198                             NULL_RTX, NULL_RTX, NULL_RTX);
4199       }
4200
4201     if (i0dest_in_i0src)
4202       {
4203         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4204         if (newi2pat && reg_set_p (i0dest, newi2pat))
4205           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4206                             NULL_RTX, NULL_RTX);
4207         else
4208           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4209                             NULL_RTX, NULL_RTX, NULL_RTX);
4210       }
4211
4212     distribute_links (i3links);
4213     distribute_links (i2links);
4214     distribute_links (i1links);
4215     distribute_links (i0links);
4216
4217     if (REG_P (i2dest))
4218       {
4219         struct insn_link *link;
4220         rtx i2_insn = 0, i2_val = 0, set;
4221
4222         /* The insn that used to set this register doesn't exist, and
4223            this life of the register may not exist either.  See if one of
4224            I3's links points to an insn that sets I2DEST.  If it does,
4225            that is now the last known value for I2DEST. If we don't update
4226            this and I2 set the register to a value that depended on its old
4227            contents, we will get confused.  If this insn is used, thing
4228            will be set correctly in combine_instructions.  */
4229         FOR_EACH_LOG_LINK (link, i3)
4230           if ((set = single_set (link->insn)) != 0
4231               && rtx_equal_p (i2dest, SET_DEST (set)))
4232             i2_insn = link->insn, i2_val = SET_SRC (set);
4233
4234         record_value_for_reg (i2dest, i2_insn, i2_val);
4235
4236         /* If the reg formerly set in I2 died only once and that was in I3,
4237            zero its use count so it won't make `reload' do any work.  */
4238         if (! added_sets_2
4239             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4240             && ! i2dest_in_i2src)
4241           INC_REG_N_SETS (REGNO (i2dest), -1);
4242       }
4243
4244     if (i1 && REG_P (i1dest))
4245       {
4246         struct insn_link *link;
4247         rtx i1_insn = 0, i1_val = 0, set;
4248
4249         FOR_EACH_LOG_LINK (link, i3)
4250           if ((set = single_set (link->insn)) != 0
4251               && rtx_equal_p (i1dest, SET_DEST (set)))
4252             i1_insn = link->insn, i1_val = SET_SRC (set);
4253
4254         record_value_for_reg (i1dest, i1_insn, i1_val);
4255
4256         if (! added_sets_1 && ! i1dest_in_i1src)
4257           INC_REG_N_SETS (REGNO (i1dest), -1);
4258       }
4259
4260     if (i0 && REG_P (i0dest))
4261       {
4262         struct insn_link *link;
4263         rtx i0_insn = 0, i0_val = 0, set;
4264
4265         FOR_EACH_LOG_LINK (link, i3)
4266           if ((set = single_set (link->insn)) != 0
4267               && rtx_equal_p (i0dest, SET_DEST (set)))
4268             i0_insn = link->insn, i0_val = SET_SRC (set);
4269
4270         record_value_for_reg (i0dest, i0_insn, i0_val);
4271
4272         if (! added_sets_0 && ! i0dest_in_i0src)
4273           INC_REG_N_SETS (REGNO (i0dest), -1);
4274       }
4275
4276     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4277        been made to this insn.  The order is important, because newi2pat
4278        can affect nonzero_bits of newpat.  */
4279     if (newi2pat)
4280       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4281     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4282   }
4283
4284   if (undobuf.other_insn != NULL_RTX)
4285     {
4286       if (dump_file)
4287         {
4288           fprintf (dump_file, "modifying other_insn ");
4289           dump_insn_slim (dump_file, undobuf.other_insn);
4290         }
4291       df_insn_rescan (undobuf.other_insn);
4292     }
4293
4294   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4295     {
4296       if (dump_file)
4297         {
4298           fprintf (dump_file, "modifying insn i0 ");
4299           dump_insn_slim (dump_file, i0);
4300         }
4301       df_insn_rescan (i0);
4302     }
4303
4304   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4305     {
4306       if (dump_file)
4307         {
4308           fprintf (dump_file, "modifying insn i1 ");
4309           dump_insn_slim (dump_file, i1);
4310         }
4311       df_insn_rescan (i1);
4312     }
4313
4314   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4315     {
4316       if (dump_file)
4317         {
4318           fprintf (dump_file, "modifying insn i2 ");
4319           dump_insn_slim (dump_file, i2);
4320         }
4321       df_insn_rescan (i2);
4322     }
4323
4324   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4325     {
4326       if (dump_file)
4327         {
4328           fprintf (dump_file, "modifying insn i3 ");
4329           dump_insn_slim (dump_file, i3);
4330         }
4331       df_insn_rescan (i3);
4332     }
4333
4334   /* Set new_direct_jump_p if a new return or simple jump instruction
4335      has been created.  Adjust the CFG accordingly.  */
4336   if (returnjump_p (i3) || any_uncondjump_p (i3))
4337     {
4338       *new_direct_jump_p = 1;
4339       mark_jump_label (PATTERN (i3), i3, 0);
4340       update_cfg_for_uncondjump (i3);
4341     }
4342
4343   if (undobuf.other_insn != NULL_RTX
4344       && (returnjump_p (undobuf.other_insn)
4345           || any_uncondjump_p (undobuf.other_insn)))
4346     {
4347       *new_direct_jump_p = 1;
4348       update_cfg_for_uncondjump (undobuf.other_insn);
4349     }
4350
4351   /* A noop might also need cleaning up of CFG, if it comes from the
4352      simplification of a jump.  */
4353   if (JUMP_P (i3)
4354       && GET_CODE (newpat) == SET
4355       && SET_SRC (newpat) == pc_rtx
4356       && SET_DEST (newpat) == pc_rtx)
4357     {
4358       *new_direct_jump_p = 1;
4359       update_cfg_for_uncondjump (i3);
4360     }
4361
4362   if (undobuf.other_insn != NULL_RTX
4363       && JUMP_P (undobuf.other_insn)
4364       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4365       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4366       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4367     {
4368       *new_direct_jump_p = 1;
4369       update_cfg_for_uncondjump (undobuf.other_insn);
4370     }
4371
4372   combine_successes++;
4373   undo_commit ();
4374
4375   if (added_links_insn
4376       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4377       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4378     return added_links_insn;
4379   else
4380     return newi2pat ? i2 : i3;
4381 }
4382 \f
4383 /* Undo all the modifications recorded in undobuf.  */
4384
4385 static void
4386 undo_all (void)
4387 {
4388   struct undo *undo, *next;
4389
4390   for (undo = undobuf.undos; undo; undo = next)
4391     {
4392       next = undo->next;
4393       switch (undo->kind)
4394         {
4395         case UNDO_RTX:
4396           *undo->where.r = undo->old_contents.r;
4397           break;
4398         case UNDO_INT:
4399           *undo->where.i = undo->old_contents.i;
4400           break;
4401         case UNDO_MODE:
4402           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4403           break;
4404         case UNDO_LINKS:
4405           *undo->where.l = undo->old_contents.l;
4406           break;
4407         default:
4408           gcc_unreachable ();
4409         }
4410
4411       undo->next = undobuf.frees;
4412       undobuf.frees = undo;
4413     }
4414
4415   undobuf.undos = 0;
4416 }
4417
4418 /* We've committed to accepting the changes we made.  Move all
4419    of the undos to the free list.  */
4420
4421 static void
4422 undo_commit (void)
4423 {
4424   struct undo *undo, *next;
4425
4426   for (undo = undobuf.undos; undo; undo = next)
4427     {
4428       next = undo->next;
4429       undo->next = undobuf.frees;
4430       undobuf.frees = undo;
4431     }
4432   undobuf.undos = 0;
4433 }
4434 \f
4435 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4436    where we have an arithmetic expression and return that point.  LOC will
4437    be inside INSN.
4438
4439    try_combine will call this function to see if an insn can be split into
4440    two insns.  */
4441
4442 static rtx *
4443 find_split_point (rtx *loc, rtx insn, bool set_src)
4444 {
4445   rtx x = *loc;
4446   enum rtx_code code = GET_CODE (x);
4447   rtx *split;
4448   unsigned HOST_WIDE_INT len = 0;
4449   HOST_WIDE_INT pos = 0;
4450   int unsignedp = 0;
4451   rtx inner = NULL_RTX;
4452
4453   /* First special-case some codes.  */
4454   switch (code)
4455     {
4456     case SUBREG:
4457 #ifdef INSN_SCHEDULING
4458       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4459          point.  */
4460       if (MEM_P (SUBREG_REG (x)))
4461         return loc;
4462 #endif
4463       return find_split_point (&SUBREG_REG (x), insn, false);
4464
4465     case MEM:
4466 #ifdef HAVE_lo_sum
4467       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4468          using LO_SUM and HIGH.  */
4469       if (GET_CODE (XEXP (x, 0)) == CONST
4470           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4471         {
4472           enum machine_mode address_mode = get_address_mode (x);
4473
4474           SUBST (XEXP (x, 0),
4475                  gen_rtx_LO_SUM (address_mode,
4476                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4477                                  XEXP (x, 0)));
4478           return &XEXP (XEXP (x, 0), 0);
4479         }
4480 #endif
4481
4482       /* If we have a PLUS whose second operand is a constant and the
4483          address is not valid, perhaps will can split it up using
4484          the machine-specific way to split large constants.  We use
4485          the first pseudo-reg (one of the virtual regs) as a placeholder;
4486          it will not remain in the result.  */
4487       if (GET_CODE (XEXP (x, 0)) == PLUS
4488           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4489           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4490                                             MEM_ADDR_SPACE (x)))
4491         {
4492           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4493           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4494                                                       XEXP (x, 0)),
4495                                          subst_insn);
4496
4497           /* This should have produced two insns, each of which sets our
4498              placeholder.  If the source of the second is a valid address,
4499              we can make put both sources together and make a split point
4500              in the middle.  */
4501
4502           if (seq
4503               && NEXT_INSN (seq) != NULL_RTX
4504               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4505               && NONJUMP_INSN_P (seq)
4506               && GET_CODE (PATTERN (seq)) == SET
4507               && SET_DEST (PATTERN (seq)) == reg
4508               && ! reg_mentioned_p (reg,
4509                                     SET_SRC (PATTERN (seq)))
4510               && NONJUMP_INSN_P (NEXT_INSN (seq))
4511               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4512               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4513               && memory_address_addr_space_p
4514                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4515                     MEM_ADDR_SPACE (x)))
4516             {
4517               rtx src1 = SET_SRC (PATTERN (seq));
4518               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4519
4520               /* Replace the placeholder in SRC2 with SRC1.  If we can
4521                  find where in SRC2 it was placed, that can become our
4522                  split point and we can replace this address with SRC2.
4523                  Just try two obvious places.  */
4524
4525               src2 = replace_rtx (src2, reg, src1);
4526               split = 0;
4527               if (XEXP (src2, 0) == src1)
4528                 split = &XEXP (src2, 0);
4529               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4530                        && XEXP (XEXP (src2, 0), 0) == src1)
4531                 split = &XEXP (XEXP (src2, 0), 0);
4532
4533               if (split)
4534                 {
4535                   SUBST (XEXP (x, 0), src2);
4536                   return split;
4537                 }
4538             }
4539
4540           /* If that didn't work, perhaps the first operand is complex and
4541              needs to be computed separately, so make a split point there.
4542              This will occur on machines that just support REG + CONST
4543              and have a constant moved through some previous computation.  */
4544
4545           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4546                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4547                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4548             return &XEXP (XEXP (x, 0), 0);
4549         }
4550
4551       /* If we have a PLUS whose first operand is complex, try computing it
4552          separately by making a split there.  */
4553       if (GET_CODE (XEXP (x, 0)) == PLUS
4554           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4555                                             MEM_ADDR_SPACE (x))
4556           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4557           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4558                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4559         return &XEXP (XEXP (x, 0), 0);
4560       break;
4561
4562     case SET:
4563 #ifdef HAVE_cc0
4564       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4565          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4566          we need to put the operand into a register.  So split at that
4567          point.  */
4568
4569       if (SET_DEST (x) == cc0_rtx
4570           && GET_CODE (SET_SRC (x)) != COMPARE
4571           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4572           && !OBJECT_P (SET_SRC (x))
4573           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4574                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4575         return &SET_SRC (x);
4576 #endif
4577
4578       /* See if we can split SET_SRC as it stands.  */
4579       split = find_split_point (&SET_SRC (x), insn, true);
4580       if (split && split != &SET_SRC (x))
4581         return split;
4582
4583       /* See if we can split SET_DEST as it stands.  */
4584       split = find_split_point (&SET_DEST (x), insn, false);
4585       if (split && split != &SET_DEST (x))
4586         return split;
4587
4588       /* See if this is a bitfield assignment with everything constant.  If
4589          so, this is an IOR of an AND, so split it into that.  */
4590       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4591           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4592           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4593           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4594           && CONST_INT_P (SET_SRC (x))
4595           && ((INTVAL (XEXP (SET_DEST (x), 1))
4596                + INTVAL (XEXP (SET_DEST (x), 2)))
4597               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4598           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4599         {
4600           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4601           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4602           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4603           rtx dest = XEXP (SET_DEST (x), 0);
4604           enum machine_mode mode = GET_MODE (dest);
4605           unsigned HOST_WIDE_INT mask
4606             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4607           rtx or_mask;
4608
4609           if (BITS_BIG_ENDIAN)
4610             pos = GET_MODE_PRECISION (mode) - len - pos;
4611
4612           or_mask = gen_int_mode (src << pos, mode);
4613           if (src == mask)
4614             SUBST (SET_SRC (x),
4615                    simplify_gen_binary (IOR, mode, dest, or_mask));
4616           else
4617             {
4618               rtx negmask = gen_int_mode (~(mask << pos), mode);
4619               SUBST (SET_SRC (x),
4620                      simplify_gen_binary (IOR, mode,
4621                                           simplify_gen_binary (AND, mode,
4622                                                                dest, negmask),
4623                                           or_mask));
4624             }
4625
4626           SUBST (SET_DEST (x), dest);
4627
4628           split = find_split_point (&SET_SRC (x), insn, true);
4629           if (split && split != &SET_SRC (x))
4630             return split;
4631         }
4632
4633       /* Otherwise, see if this is an operation that we can split into two.
4634          If so, try to split that.  */
4635       code = GET_CODE (SET_SRC (x));
4636
4637       switch (code)
4638         {
4639         case AND:
4640           /* If we are AND'ing with a large constant that is only a single
4641              bit and the result is only being used in a context where we
4642              need to know if it is zero or nonzero, replace it with a bit
4643              extraction.  This will avoid the large constant, which might
4644              have taken more than one insn to make.  If the constant were
4645              not a valid argument to the AND but took only one insn to make,
4646              this is no worse, but if it took more than one insn, it will
4647              be better.  */
4648
4649           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4650               && REG_P (XEXP (SET_SRC (x), 0))
4651               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4652               && REG_P (SET_DEST (x))
4653               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4654               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4655               && XEXP (*split, 0) == SET_DEST (x)
4656               && XEXP (*split, 1) == const0_rtx)
4657             {
4658               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4659                                                 XEXP (SET_SRC (x), 0),
4660                                                 pos, NULL_RTX, 1, 1, 0, 0);
4661               if (extraction != 0)
4662                 {
4663                   SUBST (SET_SRC (x), extraction);
4664                   return find_split_point (loc, insn, false);
4665                 }
4666             }
4667           break;
4668
4669         case NE:
4670           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4671              is known to be on, this can be converted into a NEG of a shift.  */
4672           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4673               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4674               && 1 <= (pos = exact_log2
4675                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4676                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4677             {
4678               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4679
4680               SUBST (SET_SRC (x),
4681                      gen_rtx_NEG (mode,
4682                                   gen_rtx_LSHIFTRT (mode,
4683                                                     XEXP (SET_SRC (x), 0),
4684                                                     GEN_INT (pos))));
4685
4686               split = find_split_point (&SET_SRC (x), insn, true);
4687               if (split && split != &SET_SRC (x))
4688                 return split;
4689             }
4690           break;
4691
4692         case SIGN_EXTEND:
4693           inner = XEXP (SET_SRC (x), 0);
4694
4695           /* We can't optimize if either mode is a partial integer
4696              mode as we don't know how many bits are significant
4697              in those modes.  */
4698           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4699               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4700             break;
4701
4702           pos = 0;
4703           len = GET_MODE_PRECISION (GET_MODE (inner));
4704           unsignedp = 0;
4705           break;
4706
4707         case SIGN_EXTRACT:
4708         case ZERO_EXTRACT:
4709           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4710               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4711             {
4712               inner = XEXP (SET_SRC (x), 0);
4713               len = INTVAL (XEXP (SET_SRC (x), 1));
4714               pos = INTVAL (XEXP (SET_SRC (x), 2));
4715
4716               if (BITS_BIG_ENDIAN)
4717                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4718               unsignedp = (code == ZERO_EXTRACT);
4719             }
4720           break;
4721
4722         default:
4723           break;
4724         }
4725
4726       if (len && pos >= 0
4727           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4728         {
4729           enum machine_mode mode = GET_MODE (SET_SRC (x));
4730
4731           /* For unsigned, we have a choice of a shift followed by an
4732              AND or two shifts.  Use two shifts for field sizes where the
4733              constant might be too large.  We assume here that we can
4734              always at least get 8-bit constants in an AND insn, which is
4735              true for every current RISC.  */
4736
4737           if (unsignedp && len <= 8)
4738             {
4739               unsigned HOST_WIDE_INT mask
4740                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4741               SUBST (SET_SRC (x),
4742                      gen_rtx_AND (mode,
4743                                   gen_rtx_LSHIFTRT
4744                                   (mode, gen_lowpart (mode, inner),
4745                                    GEN_INT (pos)),
4746                                   gen_int_mode (mask, mode)));
4747
4748               split = find_split_point (&SET_SRC (x), insn, true);
4749               if (split && split != &SET_SRC (x))
4750                 return split;
4751             }
4752           else
4753             {
4754               SUBST (SET_SRC (x),
4755                      gen_rtx_fmt_ee
4756                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4757                       gen_rtx_ASHIFT (mode,
4758                                       gen_lowpart (mode, inner),
4759                                       GEN_INT (GET_MODE_PRECISION (mode)
4760                                                - len - pos)),
4761                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4762
4763               split = find_split_point (&SET_SRC (x), insn, true);
4764               if (split && split != &SET_SRC (x))
4765                 return split;
4766             }
4767         }
4768
4769       /* See if this is a simple operation with a constant as the second
4770          operand.  It might be that this constant is out of range and hence
4771          could be used as a split point.  */
4772       if (BINARY_P (SET_SRC (x))
4773           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4774           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4775               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4776                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4777         return &XEXP (SET_SRC (x), 1);
4778
4779       /* Finally, see if this is a simple operation with its first operand
4780          not in a register.  The operation might require this operand in a
4781          register, so return it as a split point.  We can always do this
4782          because if the first operand were another operation, we would have
4783          already found it as a split point.  */
4784       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4785           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4786         return &XEXP (SET_SRC (x), 0);
4787
4788       return 0;
4789
4790     case AND:
4791     case IOR:
4792       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4793          it is better to write this as (not (ior A B)) so we can split it.
4794          Similarly for IOR.  */
4795       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4796         {
4797           SUBST (*loc,
4798                  gen_rtx_NOT (GET_MODE (x),
4799                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4800                                               GET_MODE (x),
4801                                               XEXP (XEXP (x, 0), 0),
4802                                               XEXP (XEXP (x, 1), 0))));
4803           return find_split_point (loc, insn, set_src);
4804         }
4805
4806       /* Many RISC machines have a large set of logical insns.  If the
4807          second operand is a NOT, put it first so we will try to split the
4808          other operand first.  */
4809       if (GET_CODE (XEXP (x, 1)) == NOT)
4810         {
4811           rtx tem = XEXP (x, 0);
4812           SUBST (XEXP (x, 0), XEXP (x, 1));
4813           SUBST (XEXP (x, 1), tem);
4814         }
4815       break;
4816
4817     case PLUS:
4818     case MINUS:
4819       /* Canonicalization can produce (minus A (mult B C)), where C is a
4820          constant.  It may be better to try splitting (plus (mult B -C) A)
4821          instead if this isn't a multiply by a power of two.  */
4822       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4823           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4824           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4825         {
4826           enum machine_mode mode = GET_MODE (x);
4827           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4828           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4829           SUBST (*loc, gen_rtx_PLUS (mode,
4830                                      gen_rtx_MULT (mode,
4831                                                    XEXP (XEXP (x, 1), 0),
4832                                                    gen_int_mode (other_int,
4833                                                                  mode)),
4834                                      XEXP (x, 0)));
4835           return find_split_point (loc, insn, set_src);
4836         }
4837
4838       /* Split at a multiply-accumulate instruction.  However if this is
4839          the SET_SRC, we likely do not have such an instruction and it's
4840          worthless to try this split.  */
4841       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4842         return loc;
4843
4844     default:
4845       break;
4846     }
4847
4848   /* Otherwise, select our actions depending on our rtx class.  */
4849   switch (GET_RTX_CLASS (code))
4850     {
4851     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4852     case RTX_TERNARY:
4853       split = find_split_point (&XEXP (x, 2), insn, false);
4854       if (split)
4855         return split;
4856       /* ... fall through ...  */
4857     case RTX_BIN_ARITH:
4858     case RTX_COMM_ARITH:
4859     case RTX_COMPARE:
4860     case RTX_COMM_COMPARE:
4861       split = find_split_point (&XEXP (x, 1), insn, false);
4862       if (split)
4863         return split;
4864       /* ... fall through ...  */
4865     case RTX_UNARY:
4866       /* Some machines have (and (shift ...) ...) insns.  If X is not
4867          an AND, but XEXP (X, 0) is, use it as our split point.  */
4868       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4869         return &XEXP (x, 0);
4870
4871       split = find_split_point (&XEXP (x, 0), insn, false);
4872       if (split)
4873         return split;
4874       return loc;
4875
4876     default:
4877       /* Otherwise, we don't have a split point.  */
4878       return 0;
4879     }
4880 }
4881 \f
4882 /* Throughout X, replace FROM with TO, and return the result.
4883    The result is TO if X is FROM;
4884    otherwise the result is X, but its contents may have been modified.
4885    If they were modified, a record was made in undobuf so that
4886    undo_all will (among other things) return X to its original state.
4887
4888    If the number of changes necessary is too much to record to undo,
4889    the excess changes are not made, so the result is invalid.
4890    The changes already made can still be undone.
4891    undobuf.num_undo is incremented for such changes, so by testing that
4892    the caller can tell whether the result is valid.
4893
4894    `n_occurrences' is incremented each time FROM is replaced.
4895
4896    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4897
4898    IN_COND is nonzero if we are at the top level of a condition.
4899
4900    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4901    by copying if `n_occurrences' is nonzero.  */
4902
4903 static rtx
4904 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4905 {
4906   enum rtx_code code = GET_CODE (x);
4907   enum machine_mode op0_mode = VOIDmode;
4908   const char *fmt;
4909   int len, i;
4910   rtx new_rtx;
4911
4912 /* Two expressions are equal if they are identical copies of a shared
4913    RTX or if they are both registers with the same register number
4914    and mode.  */
4915
4916 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4917   ((X) == (Y)                                           \
4918    || (REG_P (X) && REG_P (Y)   \
4919        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4920
4921   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4922     {
4923       n_occurrences++;
4924       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4925     }
4926
4927   /* If X and FROM are the same register but different modes, they
4928      will not have been seen as equal above.  However, the log links code
4929      will make a LOG_LINKS entry for that case.  If we do nothing, we
4930      will try to rerecognize our original insn and, when it succeeds,
4931      we will delete the feeding insn, which is incorrect.
4932
4933      So force this insn not to match in this (rare) case.  */
4934   if (! in_dest && code == REG && REG_P (from)
4935       && reg_overlap_mentioned_p (x, from))
4936     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4937
4938   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4939      of which may contain things that can be combined.  */
4940   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4941     return x;
4942
4943   /* It is possible to have a subexpression appear twice in the insn.
4944      Suppose that FROM is a register that appears within TO.
4945      Then, after that subexpression has been scanned once by `subst',
4946      the second time it is scanned, TO may be found.  If we were
4947      to scan TO here, we would find FROM within it and create a
4948      self-referent rtl structure which is completely wrong.  */
4949   if (COMBINE_RTX_EQUAL_P (x, to))
4950     return to;
4951
4952   /* Parallel asm_operands need special attention because all of the
4953      inputs are shared across the arms.  Furthermore, unsharing the
4954      rtl results in recognition failures.  Failure to handle this case
4955      specially can result in circular rtl.
4956
4957      Solve this by doing a normal pass across the first entry of the
4958      parallel, and only processing the SET_DESTs of the subsequent
4959      entries.  Ug.  */
4960
4961   if (code == PARALLEL
4962       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4963       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4964     {
4965       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4966
4967       /* If this substitution failed, this whole thing fails.  */
4968       if (GET_CODE (new_rtx) == CLOBBER
4969           && XEXP (new_rtx, 0) == const0_rtx)
4970         return new_rtx;
4971
4972       SUBST (XVECEXP (x, 0, 0), new_rtx);
4973
4974       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4975         {
4976           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4977
4978           if (!REG_P (dest)
4979               && GET_CODE (dest) != CC0
4980               && GET_CODE (dest) != PC)
4981             {
4982               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4983
4984               /* If this substitution failed, this whole thing fails.  */
4985               if (GET_CODE (new_rtx) == CLOBBER
4986                   && XEXP (new_rtx, 0) == const0_rtx)
4987                 return new_rtx;
4988
4989               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4990             }
4991         }
4992     }
4993   else
4994     {
4995       len = GET_RTX_LENGTH (code);
4996       fmt = GET_RTX_FORMAT (code);
4997
4998       /* We don't need to process a SET_DEST that is a register, CC0,
4999          or PC, so set up to skip this common case.  All other cases
5000          where we want to suppress replacing something inside a
5001          SET_SRC are handled via the IN_DEST operand.  */
5002       if (code == SET
5003           && (REG_P (SET_DEST (x))
5004               || GET_CODE (SET_DEST (x)) == CC0
5005               || GET_CODE (SET_DEST (x)) == PC))
5006         fmt = "ie";
5007
5008       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5009          constant.  */
5010       if (fmt[0] == 'e')
5011         op0_mode = GET_MODE (XEXP (x, 0));
5012
5013       for (i = 0; i < len; i++)
5014         {
5015           if (fmt[i] == 'E')
5016             {
5017               int j;
5018               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5019                 {
5020                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5021                     {
5022                       new_rtx = (unique_copy && n_occurrences
5023                              ? copy_rtx (to) : to);
5024                       n_occurrences++;
5025                     }
5026                   else
5027                     {
5028                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5029                                        unique_copy);
5030
5031                       /* If this substitution failed, this whole thing
5032                          fails.  */
5033                       if (GET_CODE (new_rtx) == CLOBBER
5034                           && XEXP (new_rtx, 0) == const0_rtx)
5035                         return new_rtx;
5036                     }
5037
5038                   SUBST (XVECEXP (x, i, j), new_rtx);
5039                 }
5040             }
5041           else if (fmt[i] == 'e')
5042             {
5043               /* If this is a register being set, ignore it.  */
5044               new_rtx = XEXP (x, i);
5045               if (in_dest
5046                   && i == 0
5047                   && (((code == SUBREG || code == ZERO_EXTRACT)
5048                        && REG_P (new_rtx))
5049                       || code == STRICT_LOW_PART))
5050                 ;
5051
5052               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5053                 {
5054                   /* In general, don't install a subreg involving two
5055                      modes not tieable.  It can worsen register
5056                      allocation, and can even make invalid reload
5057                      insns, since the reg inside may need to be copied
5058                      from in the outside mode, and that may be invalid
5059                      if it is an fp reg copied in integer mode.
5060
5061                      We allow two exceptions to this: It is valid if
5062                      it is inside another SUBREG and the mode of that
5063                      SUBREG and the mode of the inside of TO is
5064                      tieable and it is valid if X is a SET that copies
5065                      FROM to CC0.  */
5066
5067                   if (GET_CODE (to) == SUBREG
5068                       && ! MODES_TIEABLE_P (GET_MODE (to),
5069                                             GET_MODE (SUBREG_REG (to)))
5070                       && ! (code == SUBREG
5071                             && MODES_TIEABLE_P (GET_MODE (x),
5072                                                 GET_MODE (SUBREG_REG (to))))
5073 #ifdef HAVE_cc0
5074                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5075 #endif
5076                       )
5077                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5078
5079 #ifdef CANNOT_CHANGE_MODE_CLASS
5080                   if (code == SUBREG
5081                       && REG_P (to)
5082                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5083                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5084                                                    GET_MODE (to),
5085                                                    GET_MODE (x)))
5086                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5087 #endif
5088
5089                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5090                   n_occurrences++;
5091                 }
5092               else
5093                 /* If we are in a SET_DEST, suppress most cases unless we
5094                    have gone inside a MEM, in which case we want to
5095                    simplify the address.  We assume here that things that
5096                    are actually part of the destination have their inner
5097                    parts in the first expression.  This is true for SUBREG,
5098                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5099                    things aside from REG and MEM that should appear in a
5100                    SET_DEST.  */
5101                 new_rtx = subst (XEXP (x, i), from, to,
5102                              (((in_dest
5103                                 && (code == SUBREG || code == STRICT_LOW_PART
5104                                     || code == ZERO_EXTRACT))
5105                                || code == SET)
5106                               && i == 0),
5107                                  code == IF_THEN_ELSE && i == 0,
5108                                  unique_copy);
5109
5110               /* If we found that we will have to reject this combination,
5111                  indicate that by returning the CLOBBER ourselves, rather than
5112                  an expression containing it.  This will speed things up as
5113                  well as prevent accidents where two CLOBBERs are considered
5114                  to be equal, thus producing an incorrect simplification.  */
5115
5116               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5117                 return new_rtx;
5118
5119               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5120                 {
5121                   enum machine_mode mode = GET_MODE (x);
5122
5123                   x = simplify_subreg (GET_MODE (x), new_rtx,
5124                                        GET_MODE (SUBREG_REG (x)),
5125                                        SUBREG_BYTE (x));
5126                   if (! x)
5127                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5128                 }
5129               else if (CONST_INT_P (new_rtx)
5130                        && GET_CODE (x) == ZERO_EXTEND)
5131                 {
5132                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5133                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5134                   gcc_assert (x);
5135                 }
5136               else
5137                 SUBST (XEXP (x, i), new_rtx);
5138             }
5139         }
5140     }
5141
5142   /* Check if we are loading something from the constant pool via float
5143      extension; in this case we would undo compress_float_constant
5144      optimization and degenerate constant load to an immediate value.  */
5145   if (GET_CODE (x) == FLOAT_EXTEND
5146       && MEM_P (XEXP (x, 0))
5147       && MEM_READONLY_P (XEXP (x, 0)))
5148     {
5149       rtx tmp = avoid_constant_pool_reference (x);
5150       if (x != tmp)
5151         return x;
5152     }
5153
5154   /* Try to simplify X.  If the simplification changed the code, it is likely
5155      that further simplification will help, so loop, but limit the number
5156      of repetitions that will be performed.  */
5157
5158   for (i = 0; i < 4; i++)
5159     {
5160       /* If X is sufficiently simple, don't bother trying to do anything
5161          with it.  */
5162       if (code != CONST_INT && code != REG && code != CLOBBER)
5163         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5164
5165       if (GET_CODE (x) == code)
5166         break;
5167
5168       code = GET_CODE (x);
5169
5170       /* We no longer know the original mode of operand 0 since we
5171          have changed the form of X)  */
5172       op0_mode = VOIDmode;
5173     }
5174
5175   return x;
5176 }
5177 \f
5178 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5179    outer level; call `subst' to simplify recursively.  Return the new
5180    expression.
5181
5182    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5183    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5184    of a condition.  */
5185
5186 static rtx
5187 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5188                       int in_cond)
5189 {
5190   enum rtx_code code = GET_CODE (x);
5191   enum machine_mode mode = GET_MODE (x);
5192   rtx temp;
5193   int i;
5194
5195   /* If this is a commutative operation, put a constant last and a complex
5196      expression first.  We don't need to do this for comparisons here.  */
5197   if (COMMUTATIVE_ARITH_P (x)
5198       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5199     {
5200       temp = XEXP (x, 0);
5201       SUBST (XEXP (x, 0), XEXP (x, 1));
5202       SUBST (XEXP (x, 1), temp);
5203     }
5204
5205   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5206      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5207      things.  Check for cases where both arms are testing the same
5208      condition.
5209
5210      Don't do anything if all operands are very simple.  */
5211
5212   if ((BINARY_P (x)
5213        && ((!OBJECT_P (XEXP (x, 0))
5214             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5215                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5216            || (!OBJECT_P (XEXP (x, 1))
5217                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5218                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5219       || (UNARY_P (x)
5220           && (!OBJECT_P (XEXP (x, 0))
5221                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5222                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5223     {
5224       rtx cond, true_rtx, false_rtx;
5225
5226       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5227       if (cond != 0
5228           /* If everything is a comparison, what we have is highly unlikely
5229              to be simpler, so don't use it.  */
5230           && ! (COMPARISON_P (x)
5231                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5232         {
5233           rtx cop1 = const0_rtx;
5234           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5235
5236           if (cond_code == NE && COMPARISON_P (cond))
5237             return x;
5238
5239           /* Simplify the alternative arms; this may collapse the true and
5240              false arms to store-flag values.  Be careful to use copy_rtx
5241              here since true_rtx or false_rtx might share RTL with x as a
5242              result of the if_then_else_cond call above.  */
5243           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5244           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5245
5246           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5247              is unlikely to be simpler.  */
5248           if (general_operand (true_rtx, VOIDmode)
5249               && general_operand (false_rtx, VOIDmode))
5250             {
5251               enum rtx_code reversed;
5252
5253               /* Restarting if we generate a store-flag expression will cause
5254                  us to loop.  Just drop through in this case.  */
5255
5256               /* If the result values are STORE_FLAG_VALUE and zero, we can
5257                  just make the comparison operation.  */
5258               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5259                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5260                                              cond, cop1);
5261               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5262                        && ((reversed = reversed_comparison_code_parts
5263                                         (cond_code, cond, cop1, NULL))
5264                            != UNKNOWN))
5265                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5266                                              cond, cop1);
5267
5268               /* Likewise, we can make the negate of a comparison operation
5269                  if the result values are - STORE_FLAG_VALUE and zero.  */
5270               else if (CONST_INT_P (true_rtx)
5271                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5272                        && false_rtx == const0_rtx)
5273                 x = simplify_gen_unary (NEG, mode,
5274                                         simplify_gen_relational (cond_code,
5275                                                                  mode, VOIDmode,
5276                                                                  cond, cop1),
5277                                         mode);
5278               else if (CONST_INT_P (false_rtx)
5279                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5280                        && true_rtx == const0_rtx
5281                        && ((reversed = reversed_comparison_code_parts
5282                                         (cond_code, cond, cop1, NULL))
5283                            != UNKNOWN))
5284                 x = simplify_gen_unary (NEG, mode,
5285                                         simplify_gen_relational (reversed,
5286                                                                  mode, VOIDmode,
5287                                                                  cond, cop1),
5288                                         mode);
5289               else
5290                 return gen_rtx_IF_THEN_ELSE (mode,
5291                                              simplify_gen_relational (cond_code,
5292                                                                       mode,
5293                                                                       VOIDmode,
5294                                                                       cond,
5295                                                                       cop1),
5296                                              true_rtx, false_rtx);
5297
5298               code = GET_CODE (x);
5299               op0_mode = VOIDmode;
5300             }
5301         }
5302     }
5303
5304   /* Try to fold this expression in case we have constants that weren't
5305      present before.  */
5306   temp = 0;
5307   switch (GET_RTX_CLASS (code))
5308     {
5309     case RTX_UNARY:
5310       if (op0_mode == VOIDmode)
5311         op0_mode = GET_MODE (XEXP (x, 0));
5312       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5313       break;
5314     case RTX_COMPARE:
5315     case RTX_COMM_COMPARE:
5316       {
5317         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5318         if (cmp_mode == VOIDmode)
5319           {
5320             cmp_mode = GET_MODE (XEXP (x, 1));
5321             if (cmp_mode == VOIDmode)
5322               cmp_mode = op0_mode;
5323           }
5324         temp = simplify_relational_operation (code, mode, cmp_mode,
5325                                               XEXP (x, 0), XEXP (x, 1));
5326       }
5327       break;
5328     case RTX_COMM_ARITH:
5329     case RTX_BIN_ARITH:
5330       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5331       break;
5332     case RTX_BITFIELD_OPS:
5333     case RTX_TERNARY:
5334       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5335                                          XEXP (x, 1), XEXP (x, 2));
5336       break;
5337     default:
5338       break;
5339     }
5340
5341   if (temp)
5342     {
5343       x = temp;
5344       code = GET_CODE (temp);
5345       op0_mode = VOIDmode;
5346       mode = GET_MODE (temp);
5347     }
5348
5349   /* First see if we can apply the inverse distributive law.  */
5350   if (code == PLUS || code == MINUS
5351       || code == AND || code == IOR || code == XOR)
5352     {
5353       x = apply_distributive_law (x);
5354       code = GET_CODE (x);
5355       op0_mode = VOIDmode;
5356     }
5357
5358   /* If CODE is an associative operation not otherwise handled, see if we
5359      can associate some operands.  This can win if they are constants or
5360      if they are logically related (i.e. (a & b) & a).  */
5361   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5362        || code == AND || code == IOR || code == XOR
5363        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5364       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5365           || (flag_associative_math && FLOAT_MODE_P (mode))))
5366     {
5367       if (GET_CODE (XEXP (x, 0)) == code)
5368         {
5369           rtx other = XEXP (XEXP (x, 0), 0);
5370           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5371           rtx inner_op1 = XEXP (x, 1);
5372           rtx inner;
5373
5374           /* Make sure we pass the constant operand if any as the second
5375              one if this is a commutative operation.  */
5376           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5377             {
5378               rtx tem = inner_op0;
5379               inner_op0 = inner_op1;
5380               inner_op1 = tem;
5381             }
5382           inner = simplify_binary_operation (code == MINUS ? PLUS
5383                                              : code == DIV ? MULT
5384                                              : code,
5385                                              mode, inner_op0, inner_op1);
5386
5387           /* For commutative operations, try the other pair if that one
5388              didn't simplify.  */
5389           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5390             {
5391               other = XEXP (XEXP (x, 0), 1);
5392               inner = simplify_binary_operation (code, mode,
5393                                                  XEXP (XEXP (x, 0), 0),
5394                                                  XEXP (x, 1));
5395             }
5396
5397           if (inner)
5398             return simplify_gen_binary (code, mode, other, inner);
5399         }
5400     }
5401
5402   /* A little bit of algebraic simplification here.  */
5403   switch (code)
5404     {
5405     case MEM:
5406       /* Ensure that our address has any ASHIFTs converted to MULT in case
5407          address-recognizing predicates are called later.  */
5408       temp = make_compound_operation (XEXP (x, 0), MEM);
5409       SUBST (XEXP (x, 0), temp);
5410       break;
5411
5412     case SUBREG:
5413       if (op0_mode == VOIDmode)
5414         op0_mode = GET_MODE (SUBREG_REG (x));
5415
5416       /* See if this can be moved to simplify_subreg.  */
5417       if (CONSTANT_P (SUBREG_REG (x))
5418           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5419              /* Don't call gen_lowpart if the inner mode
5420                 is VOIDmode and we cannot simplify it, as SUBREG without
5421                 inner mode is invalid.  */
5422           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5423               || gen_lowpart_common (mode, SUBREG_REG (x))))
5424         return gen_lowpart (mode, SUBREG_REG (x));
5425
5426       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5427         break;
5428       {
5429         rtx temp;
5430         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5431                                 SUBREG_BYTE (x));
5432         if (temp)
5433           return temp;
5434
5435         /* If op is known to have all lower bits zero, the result is zero.  */
5436         if (!in_dest
5437             && SCALAR_INT_MODE_P (mode)
5438             && SCALAR_INT_MODE_P (op0_mode)
5439             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5440             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5441             && HWI_COMPUTABLE_MODE_P (op0_mode)
5442             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5443                 & GET_MODE_MASK (mode)) == 0)
5444           return CONST0_RTX (mode);
5445       }
5446
5447       /* Don't change the mode of the MEM if that would change the meaning
5448          of the address.  */
5449       if (MEM_P (SUBREG_REG (x))
5450           && (MEM_VOLATILE_P (SUBREG_REG (x))
5451               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5452                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5453         return gen_rtx_CLOBBER (mode, const0_rtx);
5454
5455       /* Note that we cannot do any narrowing for non-constants since
5456          we might have been counting on using the fact that some bits were
5457          zero.  We now do this in the SET.  */
5458
5459       break;
5460
5461     case NEG:
5462       temp = expand_compound_operation (XEXP (x, 0));
5463
5464       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5465          replaced by (lshiftrt X C).  This will convert
5466          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5467
5468       if (GET_CODE (temp) == ASHIFTRT
5469           && CONST_INT_P (XEXP (temp, 1))
5470           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5471         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5472                                      INTVAL (XEXP (temp, 1)));
5473
5474       /* If X has only a single bit that might be nonzero, say, bit I, convert
5475          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5476          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5477          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5478          or a SUBREG of one since we'd be making the expression more
5479          complex if it was just a register.  */
5480
5481       if (!REG_P (temp)
5482           && ! (GET_CODE (temp) == SUBREG
5483                 && REG_P (SUBREG_REG (temp)))
5484           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5485         {
5486           rtx temp1 = simplify_shift_const
5487             (NULL_RTX, ASHIFTRT, mode,
5488              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5489                                    GET_MODE_PRECISION (mode) - 1 - i),
5490              GET_MODE_PRECISION (mode) - 1 - i);
5491
5492           /* If all we did was surround TEMP with the two shifts, we
5493              haven't improved anything, so don't use it.  Otherwise,
5494              we are better off with TEMP1.  */
5495           if (GET_CODE (temp1) != ASHIFTRT
5496               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5497               || XEXP (XEXP (temp1, 0), 0) != temp)
5498             return temp1;
5499         }
5500       break;
5501
5502     case TRUNCATE:
5503       /* We can't handle truncation to a partial integer mode here
5504          because we don't know the real bitsize of the partial
5505          integer mode.  */
5506       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5507         break;
5508
5509       if (HWI_COMPUTABLE_MODE_P (mode))
5510         SUBST (XEXP (x, 0),
5511                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5512                               GET_MODE_MASK (mode), 0));
5513
5514       /* We can truncate a constant value and return it.  */
5515       if (CONST_INT_P (XEXP (x, 0)))
5516         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5517
5518       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5519          whose value is a comparison can be replaced with a subreg if
5520          STORE_FLAG_VALUE permits.  */
5521       if (HWI_COMPUTABLE_MODE_P (mode)
5522           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5523           && (temp = get_last_value (XEXP (x, 0)))
5524           && COMPARISON_P (temp))
5525         return gen_lowpart (mode, XEXP (x, 0));
5526       break;
5527
5528     case CONST:
5529       /* (const (const X)) can become (const X).  Do it this way rather than
5530          returning the inner CONST since CONST can be shared with a
5531          REG_EQUAL note.  */
5532       if (GET_CODE (XEXP (x, 0)) == CONST)
5533         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5534       break;
5535
5536 #ifdef HAVE_lo_sum
5537     case LO_SUM:
5538       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5539          can add in an offset.  find_split_point will split this address up
5540          again if it doesn't match.  */
5541       if (GET_CODE (XEXP (x, 0)) == HIGH
5542           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5543         return XEXP (x, 1);
5544       break;
5545 #endif
5546
5547     case PLUS:
5548       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5549          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5550          bit-field and can be replaced by either a sign_extend or a
5551          sign_extract.  The `and' may be a zero_extend and the two
5552          <c>, -<c> constants may be reversed.  */
5553       if (GET_CODE (XEXP (x, 0)) == XOR
5554           && CONST_INT_P (XEXP (x, 1))
5555           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5556           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5557           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5558               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5559           && HWI_COMPUTABLE_MODE_P (mode)
5560           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5561                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5562                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5563                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5564               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5565                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5566                       == (unsigned int) i + 1))))
5567         return simplify_shift_const
5568           (NULL_RTX, ASHIFTRT, mode,
5569            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5570                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5571                                  GET_MODE_PRECISION (mode) - (i + 1)),
5572            GET_MODE_PRECISION (mode) - (i + 1));
5573
5574       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5575          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5576          the bitsize of the mode - 1.  This allows simplification of
5577          "a = (b & 8) == 0;"  */
5578       if (XEXP (x, 1) == constm1_rtx
5579           && !REG_P (XEXP (x, 0))
5580           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5581                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5582           && nonzero_bits (XEXP (x, 0), mode) == 1)
5583         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5584            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5585                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5586                                  GET_MODE_PRECISION (mode) - 1),
5587            GET_MODE_PRECISION (mode) - 1);
5588
5589       /* If we are adding two things that have no bits in common, convert
5590          the addition into an IOR.  This will often be further simplified,
5591          for example in cases like ((a & 1) + (a & 2)), which can
5592          become a & 3.  */
5593
5594       if (HWI_COMPUTABLE_MODE_P (mode)
5595           && (nonzero_bits (XEXP (x, 0), mode)
5596               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5597         {
5598           /* Try to simplify the expression further.  */
5599           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5600           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5601
5602           /* If we could, great.  If not, do not go ahead with the IOR
5603              replacement, since PLUS appears in many special purpose
5604              address arithmetic instructions.  */
5605           if (GET_CODE (temp) != CLOBBER
5606               && (GET_CODE (temp) != IOR
5607                   || ((XEXP (temp, 0) != XEXP (x, 0)
5608                        || XEXP (temp, 1) != XEXP (x, 1))
5609                       && (XEXP (temp, 0) != XEXP (x, 1)
5610                           || XEXP (temp, 1) != XEXP (x, 0)))))
5611             return temp;
5612         }
5613       break;
5614
5615     case MINUS:
5616       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5617          (and <foo> (const_int pow2-1))  */
5618       if (GET_CODE (XEXP (x, 1)) == AND
5619           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5620           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5621           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5622         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5623                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5624       break;
5625
5626     case MULT:
5627       /* If we have (mult (plus A B) C), apply the distributive law and then
5628          the inverse distributive law to see if things simplify.  This
5629          occurs mostly in addresses, often when unrolling loops.  */
5630
5631       if (GET_CODE (XEXP (x, 0)) == PLUS)
5632         {
5633           rtx result = distribute_and_simplify_rtx (x, 0);
5634           if (result)
5635             return result;
5636         }
5637
5638       /* Try simplify a*(b/c) as (a*b)/c.  */
5639       if (FLOAT_MODE_P (mode) && flag_associative_math
5640           && GET_CODE (XEXP (x, 0)) == DIV)
5641         {
5642           rtx tem = simplify_binary_operation (MULT, mode,
5643                                                XEXP (XEXP (x, 0), 0),
5644                                                XEXP (x, 1));
5645           if (tem)
5646             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5647         }
5648       break;
5649
5650     case UDIV:
5651       /* If this is a divide by a power of two, treat it as a shift if
5652          its first operand is a shift.  */
5653       if (CONST_INT_P (XEXP (x, 1))
5654           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5655           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5656               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5657               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5658               || GET_CODE (XEXP (x, 0)) == ROTATE
5659               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5660         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5661       break;
5662
5663     case EQ:  case NE:
5664     case GT:  case GTU:  case GE:  case GEU:
5665     case LT:  case LTU:  case LE:  case LEU:
5666     case UNEQ:  case LTGT:
5667     case UNGT:  case UNGE:
5668     case UNLT:  case UNLE:
5669     case UNORDERED: case ORDERED:
5670       /* If the first operand is a condition code, we can't do anything
5671          with it.  */
5672       if (GET_CODE (XEXP (x, 0)) == COMPARE
5673           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5674               && ! CC0_P (XEXP (x, 0))))
5675         {
5676           rtx op0 = XEXP (x, 0);
5677           rtx op1 = XEXP (x, 1);
5678           enum rtx_code new_code;
5679
5680           if (GET_CODE (op0) == COMPARE)
5681             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5682
5683           /* Simplify our comparison, if possible.  */
5684           new_code = simplify_comparison (code, &op0, &op1);
5685
5686           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5687              if only the low-order bit is possibly nonzero in X (such as when
5688              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5689              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5690              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5691              (plus X 1).
5692
5693              Remove any ZERO_EXTRACT we made when thinking this was a
5694              comparison.  It may now be simpler to use, e.g., an AND.  If a
5695              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5696              the call to make_compound_operation in the SET case.
5697
5698              Don't apply these optimizations if the caller would
5699              prefer a comparison rather than a value.
5700              E.g., for the condition in an IF_THEN_ELSE most targets need
5701              an explicit comparison.  */
5702
5703           if (in_cond)
5704             ;
5705
5706           else if (STORE_FLAG_VALUE == 1
5707               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5708               && op1 == const0_rtx
5709               && mode == GET_MODE (op0)
5710               && nonzero_bits (op0, mode) == 1)
5711             return gen_lowpart (mode,
5712                                 expand_compound_operation (op0));
5713
5714           else if (STORE_FLAG_VALUE == 1
5715                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5716                    && op1 == const0_rtx
5717                    && mode == GET_MODE (op0)
5718                    && (num_sign_bit_copies (op0, mode)
5719                        == GET_MODE_PRECISION (mode)))
5720             {
5721               op0 = expand_compound_operation (op0);
5722               return simplify_gen_unary (NEG, mode,
5723                                          gen_lowpart (mode, op0),
5724                                          mode);
5725             }
5726
5727           else if (STORE_FLAG_VALUE == 1
5728                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5729                    && op1 == const0_rtx
5730                    && mode == GET_MODE (op0)
5731                    && nonzero_bits (op0, mode) == 1)
5732             {
5733               op0 = expand_compound_operation (op0);
5734               return simplify_gen_binary (XOR, mode,
5735                                           gen_lowpart (mode, op0),
5736                                           const1_rtx);
5737             }
5738
5739           else if (STORE_FLAG_VALUE == 1
5740                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5741                    && op1 == const0_rtx
5742                    && mode == GET_MODE (op0)
5743                    && (num_sign_bit_copies (op0, mode)
5744                        == GET_MODE_PRECISION (mode)))
5745             {
5746               op0 = expand_compound_operation (op0);
5747               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5748             }
5749
5750           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5751              those above.  */
5752           if (in_cond)
5753             ;
5754
5755           else if (STORE_FLAG_VALUE == -1
5756               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5757               && op1 == const0_rtx
5758               && (num_sign_bit_copies (op0, mode)
5759                   == GET_MODE_PRECISION (mode)))
5760             return gen_lowpart (mode,
5761                                 expand_compound_operation (op0));
5762
5763           else if (STORE_FLAG_VALUE == -1
5764                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5765                    && op1 == const0_rtx
5766                    && mode == GET_MODE (op0)
5767                    && nonzero_bits (op0, mode) == 1)
5768             {
5769               op0 = expand_compound_operation (op0);
5770               return simplify_gen_unary (NEG, mode,
5771                                          gen_lowpart (mode, op0),
5772                                          mode);
5773             }
5774
5775           else if (STORE_FLAG_VALUE == -1
5776                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5777                    && op1 == const0_rtx
5778                    && mode == GET_MODE (op0)
5779                    && (num_sign_bit_copies (op0, mode)
5780                        == GET_MODE_PRECISION (mode)))
5781             {
5782               op0 = expand_compound_operation (op0);
5783               return simplify_gen_unary (NOT, mode,
5784                                          gen_lowpart (mode, op0),
5785                                          mode);
5786             }
5787
5788           /* If X is 0/1, (eq X 0) is X-1.  */
5789           else if (STORE_FLAG_VALUE == -1
5790                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5791                    && op1 == const0_rtx
5792                    && mode == GET_MODE (op0)
5793                    && nonzero_bits (op0, mode) == 1)
5794             {
5795               op0 = expand_compound_operation (op0);
5796               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5797             }
5798
5799           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5800              one bit that might be nonzero, we can convert (ne x 0) to
5801              (ashift x c) where C puts the bit in the sign bit.  Remove any
5802              AND with STORE_FLAG_VALUE when we are done, since we are only
5803              going to test the sign bit.  */
5804           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5805               && HWI_COMPUTABLE_MODE_P (mode)
5806               && val_signbit_p (mode, STORE_FLAG_VALUE)
5807               && op1 == const0_rtx
5808               && mode == GET_MODE (op0)
5809               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5810             {
5811               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5812                                         expand_compound_operation (op0),
5813                                         GET_MODE_PRECISION (mode) - 1 - i);
5814               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5815                 return XEXP (x, 0);
5816               else
5817                 return x;
5818             }
5819
5820           /* If the code changed, return a whole new comparison.
5821              We also need to avoid using SUBST in cases where
5822              simplify_comparison has widened a comparison with a CONST_INT,
5823              since in that case the wider CONST_INT may fail the sanity
5824              checks in do_SUBST.  */
5825           if (new_code != code
5826               || (CONST_INT_P (op1)
5827                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5828                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5829             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5830
5831           /* Otherwise, keep this operation, but maybe change its operands.
5832              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5833           SUBST (XEXP (x, 0), op0);
5834           SUBST (XEXP (x, 1), op1);
5835         }
5836       break;
5837
5838     case IF_THEN_ELSE:
5839       return simplify_if_then_else (x);
5840
5841     case ZERO_EXTRACT:
5842     case SIGN_EXTRACT:
5843     case ZERO_EXTEND:
5844     case SIGN_EXTEND:
5845       /* If we are processing SET_DEST, we are done.  */
5846       if (in_dest)
5847         return x;
5848
5849       return expand_compound_operation (x);
5850
5851     case SET:
5852       return simplify_set (x);
5853
5854     case AND:
5855     case IOR:
5856       return simplify_logical (x);
5857
5858     case ASHIFT:
5859     case LSHIFTRT:
5860     case ASHIFTRT:
5861     case ROTATE:
5862     case ROTATERT:
5863       /* If this is a shift by a constant amount, simplify it.  */
5864       if (CONST_INT_P (XEXP (x, 1)))
5865         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5866                                      INTVAL (XEXP (x, 1)));
5867
5868       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5869         SUBST (XEXP (x, 1),
5870                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5871                               ((unsigned HOST_WIDE_INT) 1
5872                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5873                               - 1,
5874                               0));
5875       break;
5876
5877     default:
5878       break;
5879     }
5880
5881   return x;
5882 }
5883 \f
5884 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5885
5886 static rtx
5887 simplify_if_then_else (rtx x)
5888 {
5889   enum machine_mode mode = GET_MODE (x);
5890   rtx cond = XEXP (x, 0);
5891   rtx true_rtx = XEXP (x, 1);
5892   rtx false_rtx = XEXP (x, 2);
5893   enum rtx_code true_code = GET_CODE (cond);
5894   int comparison_p = COMPARISON_P (cond);
5895   rtx temp;
5896   int i;
5897   enum rtx_code false_code;
5898   rtx reversed;
5899
5900   /* Simplify storing of the truth value.  */
5901   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5902     return simplify_gen_relational (true_code, mode, VOIDmode,
5903                                     XEXP (cond, 0), XEXP (cond, 1));
5904
5905   /* Also when the truth value has to be reversed.  */
5906   if (comparison_p
5907       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5908       && (reversed = reversed_comparison (cond, mode)))
5909     return reversed;
5910
5911   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5912      in it is being compared against certain values.  Get the true and false
5913      comparisons and see if that says anything about the value of each arm.  */
5914
5915   if (comparison_p
5916       && ((false_code = reversed_comparison_code (cond, NULL))
5917           != UNKNOWN)
5918       && REG_P (XEXP (cond, 0)))
5919     {
5920       HOST_WIDE_INT nzb;
5921       rtx from = XEXP (cond, 0);
5922       rtx true_val = XEXP (cond, 1);
5923       rtx false_val = true_val;
5924       int swapped = 0;
5925
5926       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5927
5928       if (false_code == EQ)
5929         {
5930           swapped = 1, true_code = EQ, false_code = NE;
5931           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5932         }
5933
5934       /* If we are comparing against zero and the expression being tested has
5935          only a single bit that might be nonzero, that is its value when it is
5936          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5937
5938       if (true_code == EQ && true_val == const0_rtx
5939           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5940         {
5941           false_code = EQ;
5942           false_val = gen_int_mode (nzb, GET_MODE (from));
5943         }
5944       else if (true_code == EQ && true_val == const0_rtx
5945                && (num_sign_bit_copies (from, GET_MODE (from))
5946                    == GET_MODE_PRECISION (GET_MODE (from))))
5947         {
5948           false_code = EQ;
5949           false_val = constm1_rtx;
5950         }
5951
5952       /* Now simplify an arm if we know the value of the register in the
5953          branch and it is used in the arm.  Be careful due to the potential
5954          of locally-shared RTL.  */
5955
5956       if (reg_mentioned_p (from, true_rtx))
5957         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5958                                       from, true_val),
5959                           pc_rtx, pc_rtx, 0, 0, 0);
5960       if (reg_mentioned_p (from, false_rtx))
5961         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5962                                    from, false_val),
5963                            pc_rtx, pc_rtx, 0, 0, 0);
5964
5965       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5966       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5967
5968       true_rtx = XEXP (x, 1);
5969       false_rtx = XEXP (x, 2);
5970       true_code = GET_CODE (cond);
5971     }
5972
5973   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5974      reversed, do so to avoid needing two sets of patterns for
5975      subtract-and-branch insns.  Similarly if we have a constant in the true
5976      arm, the false arm is the same as the first operand of the comparison, or
5977      the false arm is more complicated than the true arm.  */
5978
5979   if (comparison_p
5980       && reversed_comparison_code (cond, NULL) != UNKNOWN
5981       && (true_rtx == pc_rtx
5982           || (CONSTANT_P (true_rtx)
5983               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5984           || true_rtx == const0_rtx
5985           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5986           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5987               && !OBJECT_P (false_rtx))
5988           || reg_mentioned_p (true_rtx, false_rtx)
5989           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5990     {
5991       true_code = reversed_comparison_code (cond, NULL);
5992       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5993       SUBST (XEXP (x, 1), false_rtx);
5994       SUBST (XEXP (x, 2), true_rtx);
5995
5996       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5997       cond = XEXP (x, 0);
5998
5999       /* It is possible that the conditional has been simplified out.  */
6000       true_code = GET_CODE (cond);
6001       comparison_p = COMPARISON_P (cond);
6002     }
6003
6004   /* If the two arms are identical, we don't need the comparison.  */
6005
6006   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6007     return true_rtx;
6008
6009   /* Convert a == b ? b : a to "a".  */
6010   if (true_code == EQ && ! side_effects_p (cond)
6011       && !HONOR_NANS (mode)
6012       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6013       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6014     return false_rtx;
6015   else if (true_code == NE && ! side_effects_p (cond)
6016            && !HONOR_NANS (mode)
6017            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6018            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6019     return true_rtx;
6020
6021   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6022
6023   if (GET_MODE_CLASS (mode) == MODE_INT
6024       && comparison_p
6025       && XEXP (cond, 1) == const0_rtx
6026       && GET_CODE (false_rtx) == NEG
6027       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6028       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6029       && ! side_effects_p (true_rtx))
6030     switch (true_code)
6031       {
6032       case GT:
6033       case GE:
6034         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6035       case LT:
6036       case LE:
6037         return
6038           simplify_gen_unary (NEG, mode,
6039                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6040                               mode);
6041       default:
6042         break;
6043       }
6044
6045   /* Look for MIN or MAX.  */
6046
6047   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6048       && comparison_p
6049       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6050       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6051       && ! side_effects_p (cond))
6052     switch (true_code)
6053       {
6054       case GE:
6055       case GT:
6056         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6057       case LE:
6058       case LT:
6059         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6060       case GEU:
6061       case GTU:
6062         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6063       case LEU:
6064       case LTU:
6065         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6066       default:
6067         break;
6068       }
6069
6070   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6071      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6072      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6073      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6074      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6075      neither 1 or -1, but it isn't worth checking for.  */
6076
6077   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6078       && comparison_p
6079       && GET_MODE_CLASS (mode) == MODE_INT
6080       && ! side_effects_p (x))
6081     {
6082       rtx t = make_compound_operation (true_rtx, SET);
6083       rtx f = make_compound_operation (false_rtx, SET);
6084       rtx cond_op0 = XEXP (cond, 0);
6085       rtx cond_op1 = XEXP (cond, 1);
6086       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6087       enum machine_mode m = mode;
6088       rtx z = 0, c1 = NULL_RTX;
6089
6090       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6091            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6092            || GET_CODE (t) == ASHIFT
6093            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6094           && rtx_equal_p (XEXP (t, 0), f))
6095         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6096
6097       /* If an identity-zero op is commutative, check whether there
6098          would be a match if we swapped the operands.  */
6099       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6100                 || GET_CODE (t) == XOR)
6101                && rtx_equal_p (XEXP (t, 1), f))
6102         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6103       else if (GET_CODE (t) == SIGN_EXTEND
6104                && (GET_CODE (XEXP (t, 0)) == PLUS
6105                    || GET_CODE (XEXP (t, 0)) == MINUS
6106                    || GET_CODE (XEXP (t, 0)) == IOR
6107                    || GET_CODE (XEXP (t, 0)) == XOR
6108                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6109                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6110                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6111                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6112                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6113                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6114                && (num_sign_bit_copies (f, GET_MODE (f))
6115                    > (unsigned int)
6116                      (GET_MODE_PRECISION (mode)
6117                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6118         {
6119           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6120           extend_op = SIGN_EXTEND;
6121           m = GET_MODE (XEXP (t, 0));
6122         }
6123       else if (GET_CODE (t) == SIGN_EXTEND
6124                && (GET_CODE (XEXP (t, 0)) == PLUS
6125                    || GET_CODE (XEXP (t, 0)) == IOR
6126                    || GET_CODE (XEXP (t, 0)) == XOR)
6127                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6128                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6129                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6130                && (num_sign_bit_copies (f, GET_MODE (f))
6131                    > (unsigned int)
6132                      (GET_MODE_PRECISION (mode)
6133                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6134         {
6135           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6136           extend_op = SIGN_EXTEND;
6137           m = GET_MODE (XEXP (t, 0));
6138         }
6139       else if (GET_CODE (t) == ZERO_EXTEND
6140                && (GET_CODE (XEXP (t, 0)) == PLUS
6141                    || GET_CODE (XEXP (t, 0)) == MINUS
6142                    || GET_CODE (XEXP (t, 0)) == IOR
6143                    || GET_CODE (XEXP (t, 0)) == XOR
6144                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6145                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6146                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6147                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6148                && HWI_COMPUTABLE_MODE_P (mode)
6149                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6150                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6151                && ((nonzero_bits (f, GET_MODE (f))
6152                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6153                    == 0))
6154         {
6155           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6156           extend_op = ZERO_EXTEND;
6157           m = GET_MODE (XEXP (t, 0));
6158         }
6159       else if (GET_CODE (t) == ZERO_EXTEND
6160                && (GET_CODE (XEXP (t, 0)) == PLUS
6161                    || GET_CODE (XEXP (t, 0)) == IOR
6162                    || GET_CODE (XEXP (t, 0)) == XOR)
6163                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6164                && HWI_COMPUTABLE_MODE_P (mode)
6165                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6166                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6167                && ((nonzero_bits (f, GET_MODE (f))
6168                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6169                    == 0))
6170         {
6171           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6172           extend_op = ZERO_EXTEND;
6173           m = GET_MODE (XEXP (t, 0));
6174         }
6175
6176       if (z)
6177         {
6178           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6179                                                  cond_op0, cond_op1),
6180                         pc_rtx, pc_rtx, 0, 0, 0);
6181           temp = simplify_gen_binary (MULT, m, temp,
6182                                       simplify_gen_binary (MULT, m, c1,
6183                                                            const_true_rtx));
6184           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6185           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6186
6187           if (extend_op != UNKNOWN)
6188             temp = simplify_gen_unary (extend_op, mode, temp, m);
6189
6190           return temp;
6191         }
6192     }
6193
6194   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6195      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6196      negation of a single bit, we can convert this operation to a shift.  We
6197      can actually do this more generally, but it doesn't seem worth it.  */
6198
6199   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6200       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6201       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6202            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6203           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6204                == GET_MODE_PRECISION (mode))
6205               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6206     return
6207       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6208                             gen_lowpart (mode, XEXP (cond, 0)), i);
6209
6210   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6211   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6212       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6213       && GET_MODE (XEXP (cond, 0)) == mode
6214       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6215           == nonzero_bits (XEXP (cond, 0), mode)
6216       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6217     return XEXP (cond, 0);
6218
6219   return x;
6220 }
6221 \f
6222 /* Simplify X, a SET expression.  Return the new expression.  */
6223
6224 static rtx
6225 simplify_set (rtx x)
6226 {
6227   rtx src = SET_SRC (x);
6228   rtx dest = SET_DEST (x);
6229   enum machine_mode mode
6230     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6231   rtx other_insn;
6232   rtx *cc_use;
6233
6234   /* (set (pc) (return)) gets written as (return).  */
6235   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6236     return src;
6237
6238   /* Now that we know for sure which bits of SRC we are using, see if we can
6239      simplify the expression for the object knowing that we only need the
6240      low-order bits.  */
6241
6242   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6243     {
6244       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6245       SUBST (SET_SRC (x), src);
6246     }
6247
6248   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6249      the comparison result and try to simplify it unless we already have used
6250      undobuf.other_insn.  */
6251   if ((GET_MODE_CLASS (mode) == MODE_CC
6252        || GET_CODE (src) == COMPARE
6253        || CC0_P (dest))
6254       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6255       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6256       && COMPARISON_P (*cc_use)
6257       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6258     {
6259       enum rtx_code old_code = GET_CODE (*cc_use);
6260       enum rtx_code new_code;
6261       rtx op0, op1, tmp;
6262       int other_changed = 0;
6263       rtx inner_compare = NULL_RTX;
6264       enum machine_mode compare_mode = GET_MODE (dest);
6265
6266       if (GET_CODE (src) == COMPARE)
6267         {
6268           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6269           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6270             {
6271               inner_compare = op0;
6272               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6273             }
6274         }
6275       else
6276         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6277
6278       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6279                                            op0, op1);
6280       if (!tmp)
6281         new_code = old_code;
6282       else if (!CONSTANT_P (tmp))
6283         {
6284           new_code = GET_CODE (tmp);
6285           op0 = XEXP (tmp, 0);
6286           op1 = XEXP (tmp, 1);
6287         }
6288       else
6289         {
6290           rtx pat = PATTERN (other_insn);
6291           undobuf.other_insn = other_insn;
6292           SUBST (*cc_use, tmp);
6293
6294           /* Attempt to simplify CC user.  */
6295           if (GET_CODE (pat) == SET)
6296             {
6297               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6298               if (new_rtx != NULL_RTX)
6299                 SUBST (SET_SRC (pat), new_rtx);
6300             }
6301
6302           /* Convert X into a no-op move.  */
6303           SUBST (SET_DEST (x), pc_rtx);
6304           SUBST (SET_SRC (x), pc_rtx);
6305           return x;
6306         }
6307
6308       /* Simplify our comparison, if possible.  */
6309       new_code = simplify_comparison (new_code, &op0, &op1);
6310
6311 #ifdef SELECT_CC_MODE
6312       /* If this machine has CC modes other than CCmode, check to see if we
6313          need to use a different CC mode here.  */
6314       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6315         compare_mode = GET_MODE (op0);
6316       else if (inner_compare
6317                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6318                && new_code == old_code
6319                && op0 == XEXP (inner_compare, 0)
6320                && op1 == XEXP (inner_compare, 1))
6321         compare_mode = GET_MODE (inner_compare);
6322       else
6323         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6324
6325 #ifndef HAVE_cc0
6326       /* If the mode changed, we have to change SET_DEST, the mode in the
6327          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6328          a hard register, just build new versions with the proper mode.  If it
6329          is a pseudo, we lose unless it is only time we set the pseudo, in
6330          which case we can safely change its mode.  */
6331       if (compare_mode != GET_MODE (dest))
6332         {
6333           if (can_change_dest_mode (dest, 0, compare_mode))
6334             {
6335               unsigned int regno = REGNO (dest);
6336               rtx new_dest;
6337
6338               if (regno < FIRST_PSEUDO_REGISTER)
6339                 new_dest = gen_rtx_REG (compare_mode, regno);
6340               else
6341                 {
6342                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6343                   new_dest = regno_reg_rtx[regno];
6344                 }
6345
6346               SUBST (SET_DEST (x), new_dest);
6347               SUBST (XEXP (*cc_use, 0), new_dest);
6348               other_changed = 1;
6349
6350               dest = new_dest;
6351             }
6352         }
6353 #endif  /* cc0 */
6354 #endif  /* SELECT_CC_MODE */
6355
6356       /* If the code changed, we have to build a new comparison in
6357          undobuf.other_insn.  */
6358       if (new_code != old_code)
6359         {
6360           int other_changed_previously = other_changed;
6361           unsigned HOST_WIDE_INT mask;
6362           rtx old_cc_use = *cc_use;
6363
6364           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6365                                           dest, const0_rtx));
6366           other_changed = 1;
6367
6368           /* If the only change we made was to change an EQ into an NE or
6369              vice versa, OP0 has only one bit that might be nonzero, and OP1
6370              is zero, check if changing the user of the condition code will
6371              produce a valid insn.  If it won't, we can keep the original code
6372              in that insn by surrounding our operation with an XOR.  */
6373
6374           if (((old_code == NE && new_code == EQ)
6375                || (old_code == EQ && new_code == NE))
6376               && ! other_changed_previously && op1 == const0_rtx
6377               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6378               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6379             {
6380               rtx pat = PATTERN (other_insn), note = 0;
6381
6382               if ((recog_for_combine (&pat, other_insn, &note) < 0
6383                    && ! check_asm_operands (pat)))
6384                 {
6385                   *cc_use = old_cc_use;
6386                   other_changed = 0;
6387
6388                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6389                                              gen_int_mode (mask,
6390                                                            GET_MODE (op0)));
6391                 }
6392             }
6393         }
6394
6395       if (other_changed)
6396         undobuf.other_insn = other_insn;
6397
6398       /* Otherwise, if we didn't previously have a COMPARE in the
6399          correct mode, we need one.  */
6400       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6401         {
6402           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6403           src = SET_SRC (x);
6404         }
6405       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6406         {
6407           SUBST (SET_SRC (x), op0);
6408           src = SET_SRC (x);
6409         }
6410       /* Otherwise, update the COMPARE if needed.  */
6411       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6412         {
6413           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6414           src = SET_SRC (x);
6415         }
6416     }
6417   else
6418     {
6419       /* Get SET_SRC in a form where we have placed back any
6420          compound expressions.  Then do the checks below.  */
6421       src = make_compound_operation (src, SET);
6422       SUBST (SET_SRC (x), src);
6423     }
6424
6425   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6426      and X being a REG or (subreg (reg)), we may be able to convert this to
6427      (set (subreg:m2 x) (op)).
6428
6429      We can always do this if M1 is narrower than M2 because that means that
6430      we only care about the low bits of the result.
6431
6432      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6433      perform a narrower operation than requested since the high-order bits will
6434      be undefined.  On machine where it is defined, this transformation is safe
6435      as long as M1 and M2 have the same number of words.  */
6436
6437   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6438       && !OBJECT_P (SUBREG_REG (src))
6439       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6440            / UNITS_PER_WORD)
6441           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6442                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6443 #ifndef WORD_REGISTER_OPERATIONS
6444       && (GET_MODE_SIZE (GET_MODE (src))
6445         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6446 #endif
6447 #ifdef CANNOT_CHANGE_MODE_CLASS
6448       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6449             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6450                                          GET_MODE (SUBREG_REG (src)),
6451                                          GET_MODE (src)))
6452 #endif
6453       && (REG_P (dest)
6454           || (GET_CODE (dest) == SUBREG
6455               && REG_P (SUBREG_REG (dest)))))
6456     {
6457       SUBST (SET_DEST (x),
6458              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6459                                       dest));
6460       SUBST (SET_SRC (x), SUBREG_REG (src));
6461
6462       src = SET_SRC (x), dest = SET_DEST (x);
6463     }
6464
6465 #ifdef HAVE_cc0
6466   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6467      in SRC.  */
6468   if (dest == cc0_rtx
6469       && GET_CODE (src) == SUBREG
6470       && subreg_lowpart_p (src)
6471       && (GET_MODE_PRECISION (GET_MODE (src))
6472           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6473     {
6474       rtx inner = SUBREG_REG (src);
6475       enum machine_mode inner_mode = GET_MODE (inner);
6476
6477       /* Here we make sure that we don't have a sign bit on.  */
6478       if (val_signbit_known_clear_p (GET_MODE (src),
6479                                      nonzero_bits (inner, inner_mode)))
6480         {
6481           SUBST (SET_SRC (x), inner);
6482           src = SET_SRC (x);
6483         }
6484     }
6485 #endif
6486
6487 #ifdef LOAD_EXTEND_OP
6488   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6489      would require a paradoxical subreg.  Replace the subreg with a
6490      zero_extend to avoid the reload that would otherwise be required.  */
6491
6492   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6493       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6494       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6495       && SUBREG_BYTE (src) == 0
6496       && paradoxical_subreg_p (src)
6497       && MEM_P (SUBREG_REG (src)))
6498     {
6499       SUBST (SET_SRC (x),
6500              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6501                             GET_MODE (src), SUBREG_REG (src)));
6502
6503       src = SET_SRC (x);
6504     }
6505 #endif
6506
6507   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6508      are comparing an item known to be 0 or -1 against 0, use a logical
6509      operation instead. Check for one of the arms being an IOR of the other
6510      arm with some value.  We compute three terms to be IOR'ed together.  In
6511      practice, at most two will be nonzero.  Then we do the IOR's.  */
6512
6513   if (GET_CODE (dest) != PC
6514       && GET_CODE (src) == IF_THEN_ELSE
6515       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6516       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6517       && XEXP (XEXP (src, 0), 1) == const0_rtx
6518       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6519 #ifdef HAVE_conditional_move
6520       && ! can_conditionally_move_p (GET_MODE (src))
6521 #endif
6522       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6523                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6524           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6525       && ! side_effects_p (src))
6526     {
6527       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6528                       ? XEXP (src, 1) : XEXP (src, 2));
6529       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6530                    ? XEXP (src, 2) : XEXP (src, 1));
6531       rtx term1 = const0_rtx, term2, term3;
6532
6533       if (GET_CODE (true_rtx) == IOR
6534           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6535         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6536       else if (GET_CODE (true_rtx) == IOR
6537                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6538         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6539       else if (GET_CODE (false_rtx) == IOR
6540                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6541         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6542       else if (GET_CODE (false_rtx) == IOR
6543                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6544         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6545
6546       term2 = simplify_gen_binary (AND, GET_MODE (src),
6547                                    XEXP (XEXP (src, 0), 0), true_rtx);
6548       term3 = simplify_gen_binary (AND, GET_MODE (src),
6549                                    simplify_gen_unary (NOT, GET_MODE (src),
6550                                                        XEXP (XEXP (src, 0), 0),
6551                                                        GET_MODE (src)),
6552                                    false_rtx);
6553
6554       SUBST (SET_SRC (x),
6555              simplify_gen_binary (IOR, GET_MODE (src),
6556                                   simplify_gen_binary (IOR, GET_MODE (src),
6557                                                        term1, term2),
6558                                   term3));
6559
6560       src = SET_SRC (x);
6561     }
6562
6563   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6564      whole thing fail.  */
6565   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6566     return src;
6567   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6568     return dest;
6569   else
6570     /* Convert this into a field assignment operation, if possible.  */
6571     return make_field_assignment (x);
6572 }
6573 \f
6574 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6575    result.  */
6576
6577 static rtx
6578 simplify_logical (rtx x)
6579 {
6580   enum machine_mode mode = GET_MODE (x);
6581   rtx op0 = XEXP (x, 0);
6582   rtx op1 = XEXP (x, 1);
6583
6584   switch (GET_CODE (x))
6585     {
6586     case AND:
6587       /* We can call simplify_and_const_int only if we don't lose
6588          any (sign) bits when converting INTVAL (op1) to
6589          "unsigned HOST_WIDE_INT".  */
6590       if (CONST_INT_P (op1)
6591           && (HWI_COMPUTABLE_MODE_P (mode)
6592               || INTVAL (op1) > 0))
6593         {
6594           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6595           if (GET_CODE (x) != AND)
6596             return x;
6597
6598           op0 = XEXP (x, 0);
6599           op1 = XEXP (x, 1);
6600         }
6601
6602       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6603          apply the distributive law and then the inverse distributive
6604          law to see if things simplify.  */
6605       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6606         {
6607           rtx result = distribute_and_simplify_rtx (x, 0);
6608           if (result)
6609             return result;
6610         }
6611       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6612         {
6613           rtx result = distribute_and_simplify_rtx (x, 1);
6614           if (result)
6615             return result;
6616         }
6617       break;
6618
6619     case IOR:
6620       /* If we have (ior (and A B) C), apply the distributive law and then
6621          the inverse distributive law to see if things simplify.  */
6622
6623       if (GET_CODE (op0) == AND)
6624         {
6625           rtx result = distribute_and_simplify_rtx (x, 0);
6626           if (result)
6627             return result;
6628         }
6629
6630       if (GET_CODE (op1) == AND)
6631         {
6632           rtx result = distribute_and_simplify_rtx (x, 1);
6633           if (result)
6634             return result;
6635         }
6636       break;
6637
6638     default:
6639       gcc_unreachable ();
6640     }
6641
6642   return x;
6643 }
6644 \f
6645 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6646    operations" because they can be replaced with two more basic operations.
6647    ZERO_EXTEND is also considered "compound" because it can be replaced with
6648    an AND operation, which is simpler, though only one operation.
6649
6650    The function expand_compound_operation is called with an rtx expression
6651    and will convert it to the appropriate shifts and AND operations,
6652    simplifying at each stage.
6653
6654    The function make_compound_operation is called to convert an expression
6655    consisting of shifts and ANDs into the equivalent compound expression.
6656    It is the inverse of this function, loosely speaking.  */
6657
6658 static rtx
6659 expand_compound_operation (rtx x)
6660 {
6661   unsigned HOST_WIDE_INT pos = 0, len;
6662   int unsignedp = 0;
6663   unsigned int modewidth;
6664   rtx tem;
6665
6666   switch (GET_CODE (x))
6667     {
6668     case ZERO_EXTEND:
6669       unsignedp = 1;
6670     case SIGN_EXTEND:
6671       /* We can't necessarily use a const_int for a multiword mode;
6672          it depends on implicitly extending the value.
6673          Since we don't know the right way to extend it,
6674          we can't tell whether the implicit way is right.
6675
6676          Even for a mode that is no wider than a const_int,
6677          we can't win, because we need to sign extend one of its bits through
6678          the rest of it, and we don't know which bit.  */
6679       if (CONST_INT_P (XEXP (x, 0)))
6680         return x;
6681
6682       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6683          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6684          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6685          reloaded. If not for that, MEM's would very rarely be safe.
6686
6687          Reject MODEs bigger than a word, because we might not be able
6688          to reference a two-register group starting with an arbitrary register
6689          (and currently gen_lowpart might crash for a SUBREG).  */
6690
6691       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6692         return x;
6693
6694       /* Reject MODEs that aren't scalar integers because turning vector
6695          or complex modes into shifts causes problems.  */
6696
6697       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6698         return x;
6699
6700       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6701       /* If the inner object has VOIDmode (the only way this can happen
6702          is if it is an ASM_OPERANDS), we can't do anything since we don't
6703          know how much masking to do.  */
6704       if (len == 0)
6705         return x;
6706
6707       break;
6708
6709     case ZERO_EXTRACT:
6710       unsignedp = 1;
6711
6712       /* ... fall through ...  */
6713
6714     case SIGN_EXTRACT:
6715       /* If the operand is a CLOBBER, just return it.  */
6716       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6717         return XEXP (x, 0);
6718
6719       if (!CONST_INT_P (XEXP (x, 1))
6720           || !CONST_INT_P (XEXP (x, 2))
6721           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6722         return x;
6723
6724       /* Reject MODEs that aren't scalar integers because turning vector
6725          or complex modes into shifts causes problems.  */
6726
6727       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6728         return x;
6729
6730       len = INTVAL (XEXP (x, 1));
6731       pos = INTVAL (XEXP (x, 2));
6732
6733       /* This should stay within the object being extracted, fail otherwise.  */
6734       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6735         return x;
6736
6737       if (BITS_BIG_ENDIAN)
6738         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6739
6740       break;
6741
6742     default:
6743       return x;
6744     }
6745   /* Convert sign extension to zero extension, if we know that the high
6746      bit is not set, as this is easier to optimize.  It will be converted
6747      back to cheaper alternative in make_extraction.  */
6748   if (GET_CODE (x) == SIGN_EXTEND
6749       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6750           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6751                 & ~(((unsigned HOST_WIDE_INT)
6752                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6753                      >> 1))
6754                == 0)))
6755     {
6756       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6757       rtx temp2 = expand_compound_operation (temp);
6758
6759       /* Make sure this is a profitable operation.  */
6760       if (set_src_cost (x, optimize_this_for_speed_p)
6761           > set_src_cost (temp2, optimize_this_for_speed_p))
6762        return temp2;
6763       else if (set_src_cost (x, optimize_this_for_speed_p)
6764                > set_src_cost (temp, optimize_this_for_speed_p))
6765        return temp;
6766       else
6767        return x;
6768     }
6769
6770   /* We can optimize some special cases of ZERO_EXTEND.  */
6771   if (GET_CODE (x) == ZERO_EXTEND)
6772     {
6773       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6774          know that the last value didn't have any inappropriate bits
6775          set.  */
6776       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6777           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6778           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6779           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6780               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6781         return XEXP (XEXP (x, 0), 0);
6782
6783       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6784       if (GET_CODE (XEXP (x, 0)) == SUBREG
6785           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6786           && subreg_lowpart_p (XEXP (x, 0))
6787           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6788           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6789               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6790         return SUBREG_REG (XEXP (x, 0));
6791
6792       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6793          is a comparison and STORE_FLAG_VALUE permits.  This is like
6794          the first case, but it works even when GET_MODE (x) is larger
6795          than HOST_WIDE_INT.  */
6796       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6797           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6798           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6799           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6800               <= HOST_BITS_PER_WIDE_INT)
6801           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6802         return XEXP (XEXP (x, 0), 0);
6803
6804       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6805       if (GET_CODE (XEXP (x, 0)) == SUBREG
6806           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6807           && subreg_lowpart_p (XEXP (x, 0))
6808           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6809           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6810               <= HOST_BITS_PER_WIDE_INT)
6811           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6812         return SUBREG_REG (XEXP (x, 0));
6813
6814     }
6815
6816   /* If we reach here, we want to return a pair of shifts.  The inner
6817      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6818      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6819      logical depending on the value of UNSIGNEDP.
6820
6821      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6822      converted into an AND of a shift.
6823
6824      We must check for the case where the left shift would have a negative
6825      count.  This can happen in a case like (x >> 31) & 255 on machines
6826      that can't shift by a constant.  On those machines, we would first
6827      combine the shift with the AND to produce a variable-position
6828      extraction.  Then the constant of 31 would be substituted in
6829      to produce such a position.  */
6830
6831   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6832   if (modewidth >= pos + len)
6833     {
6834       enum machine_mode mode = GET_MODE (x);
6835       tem = gen_lowpart (mode, XEXP (x, 0));
6836       if (!tem || GET_CODE (tem) == CLOBBER)
6837         return x;
6838       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6839                                   tem, modewidth - pos - len);
6840       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6841                                   mode, tem, modewidth - len);
6842     }
6843   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6844     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6845                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6846                                                         GET_MODE (x),
6847                                                         XEXP (x, 0), pos),
6848                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6849   else
6850     /* Any other cases we can't handle.  */
6851     return x;
6852
6853   /* If we couldn't do this for some reason, return the original
6854      expression.  */
6855   if (GET_CODE (tem) == CLOBBER)
6856     return x;
6857
6858   return tem;
6859 }
6860 \f
6861 /* X is a SET which contains an assignment of one object into
6862    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6863    or certain SUBREGS). If possible, convert it into a series of
6864    logical operations.
6865
6866    We half-heartedly support variable positions, but do not at all
6867    support variable lengths.  */
6868
6869 static const_rtx
6870 expand_field_assignment (const_rtx x)
6871 {
6872   rtx inner;
6873   rtx pos;                      /* Always counts from low bit.  */
6874   int len;
6875   rtx mask, cleared, masked;
6876   enum machine_mode compute_mode;
6877
6878   /* Loop until we find something we can't simplify.  */
6879   while (1)
6880     {
6881       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6882           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6883         {
6884           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6885           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6886           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6887         }
6888       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6889                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6890         {
6891           inner = XEXP (SET_DEST (x), 0);
6892           len = INTVAL (XEXP (SET_DEST (x), 1));
6893           pos = XEXP (SET_DEST (x), 2);
6894
6895           /* A constant position should stay within the width of INNER.  */
6896           if (CONST_INT_P (pos)
6897               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6898             break;
6899
6900           if (BITS_BIG_ENDIAN)
6901             {
6902               if (CONST_INT_P (pos))
6903                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6904                                - INTVAL (pos));
6905               else if (GET_CODE (pos) == MINUS
6906                        && CONST_INT_P (XEXP (pos, 1))
6907                        && (INTVAL (XEXP (pos, 1))
6908                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6909                 /* If position is ADJUST - X, new position is X.  */
6910                 pos = XEXP (pos, 0);
6911               else
6912                 {
6913                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6914                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6915                                              gen_int_mode (prec - len,
6916                                                            GET_MODE (pos)),
6917                                              pos);
6918                 }
6919             }
6920         }
6921
6922       /* A SUBREG between two modes that occupy the same numbers of words
6923          can be done by moving the SUBREG to the source.  */
6924       else if (GET_CODE (SET_DEST (x)) == SUBREG
6925                /* We need SUBREGs to compute nonzero_bits properly.  */
6926                && nonzero_sign_valid
6927                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6928                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6929                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6930                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6931         {
6932           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6933                            gen_lowpart
6934                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6935                             SET_SRC (x)));
6936           continue;
6937         }
6938       else
6939         break;
6940
6941       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6942         inner = SUBREG_REG (inner);
6943
6944       compute_mode = GET_MODE (inner);
6945
6946       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6947       if (! SCALAR_INT_MODE_P (compute_mode))
6948         {
6949           enum machine_mode imode;
6950
6951           /* Don't do anything for vector or complex integral types.  */
6952           if (! FLOAT_MODE_P (compute_mode))
6953             break;
6954
6955           /* Try to find an integral mode to pun with.  */
6956           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6957           if (imode == BLKmode)
6958             break;
6959
6960           compute_mode = imode;
6961           inner = gen_lowpart (imode, inner);
6962         }
6963
6964       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6965       if (len >= HOST_BITS_PER_WIDE_INT)
6966         break;
6967
6968       /* Now compute the equivalent expression.  Make a copy of INNER
6969          for the SET_DEST in case it is a MEM into which we will substitute;
6970          we don't want shared RTL in that case.  */
6971       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
6972                            compute_mode);
6973       cleared = simplify_gen_binary (AND, compute_mode,
6974                                      simplify_gen_unary (NOT, compute_mode,
6975                                        simplify_gen_binary (ASHIFT,
6976                                                             compute_mode,
6977                                                             mask, pos),
6978                                        compute_mode),
6979                                      inner);
6980       masked = simplify_gen_binary (ASHIFT, compute_mode,
6981                                     simplify_gen_binary (
6982                                       AND, compute_mode,
6983                                       gen_lowpart (compute_mode, SET_SRC (x)),
6984                                       mask),
6985                                     pos);
6986
6987       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6988                        simplify_gen_binary (IOR, compute_mode,
6989                                             cleared, masked));
6990     }
6991
6992   return x;
6993 }
6994 \f
6995 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6996    it is an RTX that represents the (variable) starting position; otherwise,
6997    POS is the (constant) starting bit position.  Both are counted from the LSB.
6998
6999    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7000
7001    IN_DEST is nonzero if this is a reference in the destination of a SET.
7002    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7003    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7004    be used.
7005
7006    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7007    ZERO_EXTRACT should be built even for bits starting at bit 0.
7008
7009    MODE is the desired mode of the result (if IN_DEST == 0).
7010
7011    The result is an RTX for the extraction or NULL_RTX if the target
7012    can't handle it.  */
7013
7014 static rtx
7015 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7016                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7017                  int in_dest, int in_compare)
7018 {
7019   /* This mode describes the size of the storage area
7020      to fetch the overall value from.  Within that, we
7021      ignore the POS lowest bits, etc.  */
7022   enum machine_mode is_mode = GET_MODE (inner);
7023   enum machine_mode inner_mode;
7024   enum machine_mode wanted_inner_mode;
7025   enum machine_mode wanted_inner_reg_mode = word_mode;
7026   enum machine_mode pos_mode = word_mode;
7027   enum machine_mode extraction_mode = word_mode;
7028   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7029   rtx new_rtx = 0;
7030   rtx orig_pos_rtx = pos_rtx;
7031   HOST_WIDE_INT orig_pos;
7032
7033   if (pos_rtx && CONST_INT_P (pos_rtx))
7034     pos = INTVAL (pos_rtx), pos_rtx = 0;
7035
7036   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7037     {
7038       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7039          consider just the QI as the memory to extract from.
7040          The subreg adds or removes high bits; its mode is
7041          irrelevant to the meaning of this extraction,
7042          since POS and LEN count from the lsb.  */
7043       if (MEM_P (SUBREG_REG (inner)))
7044         is_mode = GET_MODE (SUBREG_REG (inner));
7045       inner = SUBREG_REG (inner);
7046     }
7047   else if (GET_CODE (inner) == ASHIFT
7048            && CONST_INT_P (XEXP (inner, 1))
7049            && pos_rtx == 0 && pos == 0
7050            && len > UINTVAL (XEXP (inner, 1)))
7051     {
7052       /* We're extracting the least significant bits of an rtx
7053          (ashift X (const_int C)), where LEN > C.  Extract the
7054          least significant (LEN - C) bits of X, giving an rtx
7055          whose mode is MODE, then shift it left C times.  */
7056       new_rtx = make_extraction (mode, XEXP (inner, 0),
7057                              0, 0, len - INTVAL (XEXP (inner, 1)),
7058                              unsignedp, in_dest, in_compare);
7059       if (new_rtx != 0)
7060         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7061     }
7062   else if (GET_CODE (inner) == TRUNCATE)
7063     inner = XEXP (inner, 0);
7064
7065   inner_mode = GET_MODE (inner);
7066
7067   /* See if this can be done without an extraction.  We never can if the
7068      width of the field is not the same as that of some integer mode. For
7069      registers, we can only avoid the extraction if the position is at the
7070      low-order bit and this is either not in the destination or we have the
7071      appropriate STRICT_LOW_PART operation available.
7072
7073      For MEM, we can avoid an extract if the field starts on an appropriate
7074      boundary and we can change the mode of the memory reference.  */
7075
7076   if (tmode != BLKmode
7077       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7078            && !MEM_P (inner)
7079            && (inner_mode == tmode
7080                || !REG_P (inner)
7081                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7082                || reg_truncated_to_mode (tmode, inner))
7083            && (! in_dest
7084                || (REG_P (inner)
7085                    && have_insn_for (STRICT_LOW_PART, tmode))))
7086           || (MEM_P (inner) && pos_rtx == 0
7087               && (pos
7088                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7089                      : BITS_PER_UNIT)) == 0
7090               /* We can't do this if we are widening INNER_MODE (it
7091                  may not be aligned, for one thing).  */
7092               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7093               && (inner_mode == tmode
7094                   || (! mode_dependent_address_p (XEXP (inner, 0),
7095                                                   MEM_ADDR_SPACE (inner))
7096                       && ! MEM_VOLATILE_P (inner))))))
7097     {
7098       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7099          field.  If the original and current mode are the same, we need not
7100          adjust the offset.  Otherwise, we do if bytes big endian.
7101
7102          If INNER is not a MEM, get a piece consisting of just the field
7103          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7104
7105       if (MEM_P (inner))
7106         {
7107           HOST_WIDE_INT offset;
7108
7109           /* POS counts from lsb, but make OFFSET count in memory order.  */
7110           if (BYTES_BIG_ENDIAN)
7111             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7112           else
7113             offset = pos / BITS_PER_UNIT;
7114
7115           new_rtx = adjust_address_nv (inner, tmode, offset);
7116         }
7117       else if (REG_P (inner))
7118         {
7119           if (tmode != inner_mode)
7120             {
7121               /* We can't call gen_lowpart in a DEST since we
7122                  always want a SUBREG (see below) and it would sometimes
7123                  return a new hard register.  */
7124               if (pos || in_dest)
7125                 {
7126                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7127
7128                   if (WORDS_BIG_ENDIAN
7129                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7130                     final_word = ((GET_MODE_SIZE (inner_mode)
7131                                    - GET_MODE_SIZE (tmode))
7132                                   / UNITS_PER_WORD) - final_word;
7133
7134                   final_word *= UNITS_PER_WORD;
7135                   if (BYTES_BIG_ENDIAN &&
7136                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7137                     final_word += (GET_MODE_SIZE (inner_mode)
7138                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7139
7140                   /* Avoid creating invalid subregs, for example when
7141                      simplifying (x>>32)&255.  */
7142                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7143                     return NULL_RTX;
7144
7145                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7146                 }
7147               else
7148                 new_rtx = gen_lowpart (tmode, inner);
7149             }
7150           else
7151             new_rtx = inner;
7152         }
7153       else
7154         new_rtx = force_to_mode (inner, tmode,
7155                              len >= HOST_BITS_PER_WIDE_INT
7156                              ? ~(unsigned HOST_WIDE_INT) 0
7157                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7158                              0);
7159
7160       /* If this extraction is going into the destination of a SET,
7161          make a STRICT_LOW_PART unless we made a MEM.  */
7162
7163       if (in_dest)
7164         return (MEM_P (new_rtx) ? new_rtx
7165                 : (GET_CODE (new_rtx) != SUBREG
7166                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7167                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7168
7169       if (mode == tmode)
7170         return new_rtx;
7171
7172       if (CONST_SCALAR_INT_P (new_rtx))
7173         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7174                                          mode, new_rtx, tmode);
7175
7176       /* If we know that no extraneous bits are set, and that the high
7177          bit is not set, convert the extraction to the cheaper of
7178          sign and zero extension, that are equivalent in these cases.  */
7179       if (flag_expensive_optimizations
7180           && (HWI_COMPUTABLE_MODE_P (tmode)
7181               && ((nonzero_bits (new_rtx, tmode)
7182                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7183                   == 0)))
7184         {
7185           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7186           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7187
7188           /* Prefer ZERO_EXTENSION, since it gives more information to
7189              backends.  */
7190           if (set_src_cost (temp, optimize_this_for_speed_p)
7191               <= set_src_cost (temp1, optimize_this_for_speed_p))
7192             return temp;
7193           return temp1;
7194         }
7195
7196       /* Otherwise, sign- or zero-extend unless we already are in the
7197          proper mode.  */
7198
7199       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7200                              mode, new_rtx));
7201     }
7202
7203   /* Unless this is a COMPARE or we have a funny memory reference,
7204      don't do anything with zero-extending field extracts starting at
7205      the low-order bit since they are simple AND operations.  */
7206   if (pos_rtx == 0 && pos == 0 && ! in_dest
7207       && ! in_compare && unsignedp)
7208     return 0;
7209
7210   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7211      if the position is not a constant and the length is not 1.  In all
7212      other cases, we would only be going outside our object in cases when
7213      an original shift would have been undefined.  */
7214   if (MEM_P (inner)
7215       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7216           || (pos_rtx != 0 && len != 1)))
7217     return 0;
7218
7219   enum extraction_pattern pattern = (in_dest ? EP_insv
7220                                      : unsignedp ? EP_extzv : EP_extv);
7221
7222   /* If INNER is not from memory, we want it to have the mode of a register
7223      extraction pattern's structure operand, or word_mode if there is no
7224      such pattern.  The same applies to extraction_mode and pos_mode
7225      and their respective operands.
7226
7227      For memory, assume that the desired extraction_mode and pos_mode
7228      are the same as for a register operation, since at present we don't
7229      have named patterns for aligned memory structures.  */
7230   struct extraction_insn insn;
7231   if (get_best_reg_extraction_insn (&insn, pattern,
7232                                     GET_MODE_BITSIZE (inner_mode), mode))
7233     {
7234       wanted_inner_reg_mode = insn.struct_mode;
7235       pos_mode = insn.pos_mode;
7236       extraction_mode = insn.field_mode;
7237     }
7238
7239   /* Never narrow an object, since that might not be safe.  */
7240
7241   if (mode != VOIDmode
7242       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7243     extraction_mode = mode;
7244
7245   if (!MEM_P (inner))
7246     wanted_inner_mode = wanted_inner_reg_mode;
7247   else
7248     {
7249       /* Be careful not to go beyond the extracted object and maintain the
7250          natural alignment of the memory.  */
7251       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7252       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7253              > GET_MODE_BITSIZE (wanted_inner_mode))
7254         {
7255           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7256           gcc_assert (wanted_inner_mode != VOIDmode);
7257         }
7258     }
7259
7260   orig_pos = pos;
7261
7262   if (BITS_BIG_ENDIAN)
7263     {
7264       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7265          BITS_BIG_ENDIAN style.  If position is constant, compute new
7266          position.  Otherwise, build subtraction.
7267          Note that POS is relative to the mode of the original argument.
7268          If it's a MEM we need to recompute POS relative to that.
7269          However, if we're extracting from (or inserting into) a register,
7270          we want to recompute POS relative to wanted_inner_mode.  */
7271       int width = (MEM_P (inner)
7272                    ? GET_MODE_BITSIZE (is_mode)
7273                    : GET_MODE_BITSIZE (wanted_inner_mode));
7274
7275       if (pos_rtx == 0)
7276         pos = width - len - pos;
7277       else
7278         pos_rtx
7279           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7280                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7281                            pos_rtx);
7282       /* POS may be less than 0 now, but we check for that below.
7283          Note that it can only be less than 0 if !MEM_P (inner).  */
7284     }
7285
7286   /* If INNER has a wider mode, and this is a constant extraction, try to
7287      make it smaller and adjust the byte to point to the byte containing
7288      the value.  */
7289   if (wanted_inner_mode != VOIDmode
7290       && inner_mode != wanted_inner_mode
7291       && ! pos_rtx
7292       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7293       && MEM_P (inner)
7294       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7295       && ! MEM_VOLATILE_P (inner))
7296     {
7297       int offset = 0;
7298
7299       /* The computations below will be correct if the machine is big
7300          endian in both bits and bytes or little endian in bits and bytes.
7301          If it is mixed, we must adjust.  */
7302
7303       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7304          adjust OFFSET to compensate.  */
7305       if (BYTES_BIG_ENDIAN
7306           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7307         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7308
7309       /* We can now move to the desired byte.  */
7310       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7311                 * GET_MODE_SIZE (wanted_inner_mode);
7312       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7313
7314       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7315           && is_mode != wanted_inner_mode)
7316         offset = (GET_MODE_SIZE (is_mode)
7317                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7318
7319       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7320     }
7321
7322   /* If INNER is not memory, get it into the proper mode.  If we are changing
7323      its mode, POS must be a constant and smaller than the size of the new
7324      mode.  */
7325   else if (!MEM_P (inner))
7326     {
7327       /* On the LHS, don't create paradoxical subregs implicitely truncating
7328          the register unless TRULY_NOOP_TRUNCATION.  */
7329       if (in_dest
7330           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7331                                              wanted_inner_mode))
7332         return NULL_RTX;
7333
7334       if (GET_MODE (inner) != wanted_inner_mode
7335           && (pos_rtx != 0
7336               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7337         return NULL_RTX;
7338
7339       if (orig_pos < 0)
7340         return NULL_RTX;
7341
7342       inner = force_to_mode (inner, wanted_inner_mode,
7343                              pos_rtx
7344                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7345                              ? ~(unsigned HOST_WIDE_INT) 0
7346                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7347                                 << orig_pos),
7348                              0);
7349     }
7350
7351   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7352      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7353   if (pos_rtx != 0
7354       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7355     {
7356       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7357                                      GET_MODE (pos_rtx));
7358
7359       /* If we know that no extraneous bits are set, and that the high
7360          bit is not set, convert extraction to cheaper one - either
7361          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7362          cases.  */
7363       if (flag_expensive_optimizations
7364           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7365               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7366                    & ~(((unsigned HOST_WIDE_INT)
7367                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7368                        >> 1))
7369                   == 0)))
7370         {
7371           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7372                                           GET_MODE (pos_rtx));
7373
7374           /* Prefer ZERO_EXTENSION, since it gives more information to
7375              backends.  */
7376           if (set_src_cost (temp1, optimize_this_for_speed_p)
7377               < set_src_cost (temp, optimize_this_for_speed_p))
7378             temp = temp1;
7379         }
7380       pos_rtx = temp;
7381     }
7382
7383   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7384      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7385      be a CONST_INT.  */
7386   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7387     pos_rtx = orig_pos_rtx;
7388
7389   else if (pos_rtx == 0)
7390     pos_rtx = GEN_INT (pos);
7391
7392   /* Make the required operation.  See if we can use existing rtx.  */
7393   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7394                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7395   if (! in_dest)
7396     new_rtx = gen_lowpart (mode, new_rtx);
7397
7398   return new_rtx;
7399 }
7400 \f
7401 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7402    with any other operations in X.  Return X without that shift if so.  */
7403
7404 static rtx
7405 extract_left_shift (rtx x, int count)
7406 {
7407   enum rtx_code code = GET_CODE (x);
7408   enum machine_mode mode = GET_MODE (x);
7409   rtx tem;
7410
7411   switch (code)
7412     {
7413     case ASHIFT:
7414       /* This is the shift itself.  If it is wide enough, we will return
7415          either the value being shifted if the shift count is equal to
7416          COUNT or a shift for the difference.  */
7417       if (CONST_INT_P (XEXP (x, 1))
7418           && INTVAL (XEXP (x, 1)) >= count)
7419         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7420                                      INTVAL (XEXP (x, 1)) - count);
7421       break;
7422
7423     case NEG:  case NOT:
7424       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7425         return simplify_gen_unary (code, mode, tem, mode);
7426
7427       break;
7428
7429     case PLUS:  case IOR:  case XOR:  case AND:
7430       /* If we can safely shift this constant and we find the inner shift,
7431          make a new operation.  */
7432       if (CONST_INT_P (XEXP (x, 1))
7433           && (UINTVAL (XEXP (x, 1))
7434               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7435           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7436         {
7437           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7438           return simplify_gen_binary (code, mode, tem,
7439                                       gen_int_mode (val, mode));
7440         }
7441       break;
7442
7443     default:
7444       break;
7445     }
7446
7447   return 0;
7448 }
7449 \f
7450 /* Look at the expression rooted at X.  Look for expressions
7451    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7452    Form these expressions.
7453
7454    Return the new rtx, usually just X.
7455
7456    Also, for machines like the VAX that don't have logical shift insns,
7457    try to convert logical to arithmetic shift operations in cases where
7458    they are equivalent.  This undoes the canonicalizations to logical
7459    shifts done elsewhere.
7460
7461    We try, as much as possible, to re-use rtl expressions to save memory.
7462
7463    IN_CODE says what kind of expression we are processing.  Normally, it is
7464    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7465    being kludges), it is MEM.  When processing the arguments of a comparison
7466    or a COMPARE against zero, it is COMPARE.  */
7467
7468 rtx
7469 make_compound_operation (rtx x, enum rtx_code in_code)
7470 {
7471   enum rtx_code code = GET_CODE (x);
7472   enum machine_mode mode = GET_MODE (x);
7473   int mode_width = GET_MODE_PRECISION (mode);
7474   rtx rhs, lhs;
7475   enum rtx_code next_code;
7476   int i, j;
7477   rtx new_rtx = 0;
7478   rtx tem;
7479   const char *fmt;
7480
7481   /* Select the code to be used in recursive calls.  Once we are inside an
7482      address, we stay there.  If we have a comparison, set to COMPARE,
7483      but once inside, go back to our default of SET.  */
7484
7485   next_code = (code == MEM ? MEM
7486                : ((code == PLUS || code == MINUS)
7487                   && SCALAR_INT_MODE_P (mode)) ? MEM
7488                : ((code == COMPARE || COMPARISON_P (x))
7489                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7490                : in_code == COMPARE ? SET : in_code);
7491
7492   /* Process depending on the code of this operation.  If NEW is set
7493      nonzero, it will be returned.  */
7494
7495   switch (code)
7496     {
7497     case ASHIFT:
7498       /* Convert shifts by constants into multiplications if inside
7499          an address.  */
7500       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7501           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7502           && INTVAL (XEXP (x, 1)) >= 0
7503           && SCALAR_INT_MODE_P (mode))
7504         {
7505           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7506           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7507
7508           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7509           if (GET_CODE (new_rtx) == NEG)
7510             {
7511               new_rtx = XEXP (new_rtx, 0);
7512               multval = -multval;
7513             }
7514           multval = trunc_int_for_mode (multval, mode);
7515           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7516         }
7517       break;
7518
7519     case PLUS:
7520       lhs = XEXP (x, 0);
7521       rhs = XEXP (x, 1);
7522       lhs = make_compound_operation (lhs, next_code);
7523       rhs = make_compound_operation (rhs, next_code);
7524       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7525           && SCALAR_INT_MODE_P (mode))
7526         {
7527           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7528                                      XEXP (lhs, 1));
7529           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7530         }
7531       else if (GET_CODE (lhs) == MULT
7532                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7533         {
7534           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7535                                      simplify_gen_unary (NEG, mode,
7536                                                          XEXP (lhs, 1),
7537                                                          mode));
7538           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7539         }
7540       else
7541         {
7542           SUBST (XEXP (x, 0), lhs);
7543           SUBST (XEXP (x, 1), rhs);
7544           goto maybe_swap;
7545         }
7546       x = gen_lowpart (mode, new_rtx);
7547       goto maybe_swap;
7548
7549     case MINUS:
7550       lhs = XEXP (x, 0);
7551       rhs = XEXP (x, 1);
7552       lhs = make_compound_operation (lhs, next_code);
7553       rhs = make_compound_operation (rhs, next_code);
7554       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7555           && SCALAR_INT_MODE_P (mode))
7556         {
7557           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7558                                      XEXP (rhs, 1));
7559           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7560         }
7561       else if (GET_CODE (rhs) == MULT
7562                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7563         {
7564           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7565                                      simplify_gen_unary (NEG, mode,
7566                                                          XEXP (rhs, 1),
7567                                                          mode));
7568           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7569         }
7570       else
7571         {
7572           SUBST (XEXP (x, 0), lhs);
7573           SUBST (XEXP (x, 1), rhs);
7574           return x;
7575         }
7576       return gen_lowpart (mode, new_rtx);
7577
7578     case AND:
7579       /* If the second operand is not a constant, we can't do anything
7580          with it.  */
7581       if (!CONST_INT_P (XEXP (x, 1)))
7582         break;
7583
7584       /* If the constant is a power of two minus one and the first operand
7585          is a logical right shift, make an extraction.  */
7586       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7587           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7588         {
7589           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7590           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7591                                  0, in_code == COMPARE);
7592         }
7593
7594       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7595       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7596                && subreg_lowpart_p (XEXP (x, 0))
7597                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7598                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7599         {
7600           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7601                                          next_code);
7602           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7603                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7604                                  0, in_code == COMPARE);
7605         }
7606       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7607       else if ((GET_CODE (XEXP (x, 0)) == XOR
7608                 || GET_CODE (XEXP (x, 0)) == IOR)
7609                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7610                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7611                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7612         {
7613           /* Apply the distributive law, and then try to make extractions.  */
7614           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7615                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7616                                              XEXP (x, 1)),
7617                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7618                                              XEXP (x, 1)));
7619           new_rtx = make_compound_operation (new_rtx, in_code);
7620         }
7621
7622       /* If we are have (and (rotate X C) M) and C is larger than the number
7623          of bits in M, this is an extraction.  */
7624
7625       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7626                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7627                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7628                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7629         {
7630           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7631           new_rtx = make_extraction (mode, new_rtx,
7632                                  (GET_MODE_PRECISION (mode)
7633                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7634                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7635         }
7636
7637       /* On machines without logical shifts, if the operand of the AND is
7638          a logical shift and our mask turns off all the propagated sign
7639          bits, we can replace the logical shift with an arithmetic shift.  */
7640       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7641                && !have_insn_for (LSHIFTRT, mode)
7642                && have_insn_for (ASHIFTRT, mode)
7643                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7644                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7645                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7646                && mode_width <= HOST_BITS_PER_WIDE_INT)
7647         {
7648           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7649
7650           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7651           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7652             SUBST (XEXP (x, 0),
7653                    gen_rtx_ASHIFTRT (mode,
7654                                      make_compound_operation
7655                                      (XEXP (XEXP (x, 0), 0), next_code),
7656                                      XEXP (XEXP (x, 0), 1)));
7657         }
7658
7659       /* If the constant is one less than a power of two, this might be
7660          representable by an extraction even if no shift is present.
7661          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7662          we are in a COMPARE.  */
7663       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7664         new_rtx = make_extraction (mode,
7665                                make_compound_operation (XEXP (x, 0),
7666                                                         next_code),
7667                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7668
7669       /* If we are in a comparison and this is an AND with a power of two,
7670          convert this into the appropriate bit extract.  */
7671       else if (in_code == COMPARE
7672                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7673         new_rtx = make_extraction (mode,
7674                                make_compound_operation (XEXP (x, 0),
7675                                                         next_code),
7676                                i, NULL_RTX, 1, 1, 0, 1);
7677
7678       break;
7679
7680     case LSHIFTRT:
7681       /* If the sign bit is known to be zero, replace this with an
7682          arithmetic shift.  */
7683       if (have_insn_for (ASHIFTRT, mode)
7684           && ! have_insn_for (LSHIFTRT, mode)
7685           && mode_width <= HOST_BITS_PER_WIDE_INT
7686           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7687         {
7688           new_rtx = gen_rtx_ASHIFTRT (mode,
7689                                   make_compound_operation (XEXP (x, 0),
7690                                                            next_code),
7691                                   XEXP (x, 1));
7692           break;
7693         }
7694
7695       /* ... fall through ...  */
7696
7697     case ASHIFTRT:
7698       lhs = XEXP (x, 0);
7699       rhs = XEXP (x, 1);
7700
7701       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7702          this is a SIGN_EXTRACT.  */
7703       if (CONST_INT_P (rhs)
7704           && GET_CODE (lhs) == ASHIFT
7705           && CONST_INT_P (XEXP (lhs, 1))
7706           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7707           && INTVAL (XEXP (lhs, 1)) >= 0
7708           && INTVAL (rhs) < mode_width)
7709         {
7710           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7711           new_rtx = make_extraction (mode, new_rtx,
7712                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7713                                  NULL_RTX, mode_width - INTVAL (rhs),
7714                                  code == LSHIFTRT, 0, in_code == COMPARE);
7715           break;
7716         }
7717
7718       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7719          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7720          also do this for some cases of SIGN_EXTRACT, but it doesn't
7721          seem worth the effort; the case checked for occurs on Alpha.  */
7722
7723       if (!OBJECT_P (lhs)
7724           && ! (GET_CODE (lhs) == SUBREG
7725                 && (OBJECT_P (SUBREG_REG (lhs))))
7726           && CONST_INT_P (rhs)
7727           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7728           && INTVAL (rhs) < mode_width
7729           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7730         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7731                                0, NULL_RTX, mode_width - INTVAL (rhs),
7732                                code == LSHIFTRT, 0, in_code == COMPARE);
7733
7734       break;
7735
7736     case SUBREG:
7737       /* Call ourselves recursively on the inner expression.  If we are
7738          narrowing the object and it has a different RTL code from
7739          what it originally did, do this SUBREG as a force_to_mode.  */
7740       {
7741         rtx inner = SUBREG_REG (x), simplified;
7742         enum rtx_code subreg_code = in_code;
7743
7744         /* If in_code is COMPARE, it isn't always safe to pass it through
7745            to the recursive make_compound_operation call.  */
7746         if (subreg_code == COMPARE
7747             && (!subreg_lowpart_p (x)
7748                 || GET_CODE (inner) == SUBREG
7749                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7750                    is (const_int 0), rather than
7751                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7752                 || (GET_CODE (inner) == AND
7753                     && CONST_INT_P (XEXP (inner, 1))
7754                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7755                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7756                        >= GET_MODE_BITSIZE (mode))))
7757           subreg_code = SET;
7758
7759         tem = make_compound_operation (inner, subreg_code);
7760
7761         simplified
7762           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7763         if (simplified)
7764           tem = simplified;
7765
7766         if (GET_CODE (tem) != GET_CODE (inner)
7767             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7768             && subreg_lowpart_p (x))
7769           {
7770             rtx newer
7771               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7772
7773             /* If we have something other than a SUBREG, we might have
7774                done an expansion, so rerun ourselves.  */
7775             if (GET_CODE (newer) != SUBREG)
7776               newer = make_compound_operation (newer, in_code);
7777
7778             /* force_to_mode can expand compounds.  If it just re-expanded the
7779                compound, use gen_lowpart to convert to the desired mode.  */
7780             if (rtx_equal_p (newer, x)
7781                 /* Likewise if it re-expanded the compound only partially.
7782                    This happens for SUBREG of ZERO_EXTRACT if they extract
7783                    the same number of bits.  */
7784                 || (GET_CODE (newer) == SUBREG
7785                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7786                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7787                     && GET_CODE (inner) == AND
7788                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7789               return gen_lowpart (GET_MODE (x), tem);
7790
7791             return newer;
7792           }
7793
7794         if (simplified)
7795           return tem;
7796       }
7797       break;
7798
7799     default:
7800       break;
7801     }
7802
7803   if (new_rtx)
7804     {
7805       x = gen_lowpart (mode, new_rtx);
7806       code = GET_CODE (x);
7807     }
7808
7809   /* Now recursively process each operand of this operation.  We need to
7810      handle ZERO_EXTEND specially so that we don't lose track of the
7811      inner mode.  */
7812   if (GET_CODE (x) == ZERO_EXTEND)
7813     {
7814       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7815       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7816                                             new_rtx, GET_MODE (XEXP (x, 0)));
7817       if (tem)
7818         return tem;
7819       SUBST (XEXP (x, 0), new_rtx);
7820       return x;
7821     }
7822
7823   fmt = GET_RTX_FORMAT (code);
7824   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7825     if (fmt[i] == 'e')
7826       {
7827         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7828         SUBST (XEXP (x, i), new_rtx);
7829       }
7830     else if (fmt[i] == 'E')
7831       for (j = 0; j < XVECLEN (x, i); j++)
7832         {
7833           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7834           SUBST (XVECEXP (x, i, j), new_rtx);
7835         }
7836
7837  maybe_swap:
7838   /* If this is a commutative operation, the changes to the operands
7839      may have made it noncanonical.  */
7840   if (COMMUTATIVE_ARITH_P (x)
7841       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7842     {
7843       tem = XEXP (x, 0);
7844       SUBST (XEXP (x, 0), XEXP (x, 1));
7845       SUBST (XEXP (x, 1), tem);
7846     }
7847
7848   return x;
7849 }
7850 \f
7851 /* Given M see if it is a value that would select a field of bits
7852    within an item, but not the entire word.  Return -1 if not.
7853    Otherwise, return the starting position of the field, where 0 is the
7854    low-order bit.
7855
7856    *PLEN is set to the length of the field.  */
7857
7858 static int
7859 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7860 {
7861   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7862   int pos = m ? ctz_hwi (m) : -1;
7863   int len = 0;
7864
7865   if (pos >= 0)
7866     /* Now shift off the low-order zero bits and see if we have a
7867        power of two minus 1.  */
7868     len = exact_log2 ((m >> pos) + 1);
7869
7870   if (len <= 0)
7871     pos = -1;
7872
7873   *plen = len;
7874   return pos;
7875 }
7876 \f
7877 /* If X refers to a register that equals REG in value, replace these
7878    references with REG.  */
7879 static rtx
7880 canon_reg_for_combine (rtx x, rtx reg)
7881 {
7882   rtx op0, op1, op2;
7883   const char *fmt;
7884   int i;
7885   bool copied;
7886
7887   enum rtx_code code = GET_CODE (x);
7888   switch (GET_RTX_CLASS (code))
7889     {
7890     case RTX_UNARY:
7891       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7892       if (op0 != XEXP (x, 0))
7893         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7894                                    GET_MODE (reg));
7895       break;
7896
7897     case RTX_BIN_ARITH:
7898     case RTX_COMM_ARITH:
7899       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7900       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7901       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7902         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7903       break;
7904
7905     case RTX_COMPARE:
7906     case RTX_COMM_COMPARE:
7907       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7908       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7909       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7910         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7911                                         GET_MODE (op0), op0, op1);
7912       break;
7913
7914     case RTX_TERNARY:
7915     case RTX_BITFIELD_OPS:
7916       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7917       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7918       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7919       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7920         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7921                                      GET_MODE (op0), op0, op1, op2);
7922
7923     case RTX_OBJ:
7924       if (REG_P (x))
7925         {
7926           if (rtx_equal_p (get_last_value (reg), x)
7927               || rtx_equal_p (reg, get_last_value (x)))
7928             return reg;
7929           else
7930             break;
7931         }
7932
7933       /* fall through */
7934
7935     default:
7936       fmt = GET_RTX_FORMAT (code);
7937       copied = false;
7938       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7939         if (fmt[i] == 'e')
7940           {
7941             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7942             if (op != XEXP (x, i))
7943               {
7944                 if (!copied)
7945                   {
7946                     copied = true;
7947                     x = copy_rtx (x);
7948                   }
7949                 XEXP (x, i) = op;
7950               }
7951           }
7952         else if (fmt[i] == 'E')
7953           {
7954             int j;
7955             for (j = 0; j < XVECLEN (x, i); j++)
7956               {
7957                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7958                 if (op != XVECEXP (x, i, j))
7959                   {
7960                     if (!copied)
7961                       {
7962                         copied = true;
7963                         x = copy_rtx (x);
7964                       }
7965                     XVECEXP (x, i, j) = op;
7966                   }
7967               }
7968           }
7969
7970       break;
7971     }
7972
7973   return x;
7974 }
7975
7976 /* Return X converted to MODE.  If the value is already truncated to
7977    MODE we can just return a subreg even though in the general case we
7978    would need an explicit truncation.  */
7979
7980 static rtx
7981 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7982 {
7983   if (!CONST_INT_P (x)
7984       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7985       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7986       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7987     {
7988       /* Bit-cast X into an integer mode.  */
7989       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7990         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7991       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7992                               x, GET_MODE (x));
7993     }
7994
7995   return gen_lowpart (mode, x);
7996 }
7997
7998 /* See if X can be simplified knowing that we will only refer to it in
7999    MODE and will only refer to those bits that are nonzero in MASK.
8000    If other bits are being computed or if masking operations are done
8001    that select a superset of the bits in MASK, they can sometimes be
8002    ignored.
8003
8004    Return a possibly simplified expression, but always convert X to
8005    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8006
8007    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8008    are all off in X.  This is used when X will be complemented, by either
8009    NOT, NEG, or XOR.  */
8010
8011 static rtx
8012 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8013                int just_select)
8014 {
8015   enum rtx_code code = GET_CODE (x);
8016   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8017   enum machine_mode op_mode;
8018   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8019   rtx op0, op1, temp;
8020
8021   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8022      code below will do the wrong thing since the mode of such an
8023      expression is VOIDmode.
8024
8025      Also do nothing if X is a CLOBBER; this can happen if X was
8026      the return value from a call to gen_lowpart.  */
8027   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8028     return x;
8029
8030   /* We want to perform the operation is its present mode unless we know
8031      that the operation is valid in MODE, in which case we do the operation
8032      in MODE.  */
8033   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8034               && have_insn_for (code, mode))
8035              ? mode : GET_MODE (x));
8036
8037   /* It is not valid to do a right-shift in a narrower mode
8038      than the one it came in with.  */
8039   if ((code == LSHIFTRT || code == ASHIFTRT)
8040       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8041     op_mode = GET_MODE (x);
8042
8043   /* Truncate MASK to fit OP_MODE.  */
8044   if (op_mode)
8045     mask &= GET_MODE_MASK (op_mode);
8046
8047   /* When we have an arithmetic operation, or a shift whose count we
8048      do not know, we need to assume that all bits up to the highest-order
8049      bit in MASK will be needed.  This is how we form such a mask.  */
8050   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8051     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8052   else
8053     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8054                    - 1);
8055
8056   /* Determine what bits of X are guaranteed to be (non)zero.  */
8057   nonzero = nonzero_bits (x, mode);
8058
8059   /* If none of the bits in X are needed, return a zero.  */
8060   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8061     x = const0_rtx;
8062
8063   /* If X is a CONST_INT, return a new one.  Do this here since the
8064      test below will fail.  */
8065   if (CONST_INT_P (x))
8066     {
8067       if (SCALAR_INT_MODE_P (mode))
8068         return gen_int_mode (INTVAL (x) & mask, mode);
8069       else
8070         {
8071           x = GEN_INT (INTVAL (x) & mask);
8072           return gen_lowpart_common (mode, x);
8073         }
8074     }
8075
8076   /* If X is narrower than MODE and we want all the bits in X's mode, just
8077      get X in the proper mode.  */
8078   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8079       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8080     return gen_lowpart (mode, x);
8081
8082   /* We can ignore the effect of a SUBREG if it narrows the mode or
8083      if the constant masks to zero all the bits the mode doesn't have.  */
8084   if (GET_CODE (x) == SUBREG
8085       && subreg_lowpart_p (x)
8086       && ((GET_MODE_SIZE (GET_MODE (x))
8087            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8088           || (0 == (mask
8089                     & GET_MODE_MASK (GET_MODE (x))
8090                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8091     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8092
8093   /* The arithmetic simplifications here only work for scalar integer modes.  */
8094   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8095     return gen_lowpart_or_truncate (mode, x);
8096
8097   switch (code)
8098     {
8099     case CLOBBER:
8100       /* If X is a (clobber (const_int)), return it since we know we are
8101          generating something that won't match.  */
8102       return x;
8103
8104     case SIGN_EXTEND:
8105     case ZERO_EXTEND:
8106     case ZERO_EXTRACT:
8107     case SIGN_EXTRACT:
8108       x = expand_compound_operation (x);
8109       if (GET_CODE (x) != code)
8110         return force_to_mode (x, mode, mask, next_select);
8111       break;
8112
8113     case TRUNCATE:
8114       /* Similarly for a truncate.  */
8115       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8116
8117     case AND:
8118       /* If this is an AND with a constant, convert it into an AND
8119          whose constant is the AND of that constant with MASK.  If it
8120          remains an AND of MASK, delete it since it is redundant.  */
8121
8122       if (CONST_INT_P (XEXP (x, 1)))
8123         {
8124           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8125                                       mask & INTVAL (XEXP (x, 1)));
8126
8127           /* If X is still an AND, see if it is an AND with a mask that
8128              is just some low-order bits.  If so, and it is MASK, we don't
8129              need it.  */
8130
8131           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8132               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8133                   == mask))
8134             x = XEXP (x, 0);
8135
8136           /* If it remains an AND, try making another AND with the bits
8137              in the mode mask that aren't in MASK turned on.  If the
8138              constant in the AND is wide enough, this might make a
8139              cheaper constant.  */
8140
8141           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8142               && GET_MODE_MASK (GET_MODE (x)) != mask
8143               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8144             {
8145               unsigned HOST_WIDE_INT cval
8146                 = UINTVAL (XEXP (x, 1))
8147                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8148               rtx y;
8149
8150               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8151                                        gen_int_mode (cval, GET_MODE (x)));
8152               if (set_src_cost (y, optimize_this_for_speed_p)
8153                   < set_src_cost (x, optimize_this_for_speed_p))
8154                 x = y;
8155             }
8156
8157           break;
8158         }
8159
8160       goto binop;
8161
8162     case PLUS:
8163       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8164          low-order bits (as in an alignment operation) and FOO is already
8165          aligned to that boundary, mask C1 to that boundary as well.
8166          This may eliminate that PLUS and, later, the AND.  */
8167
8168       {
8169         unsigned int width = GET_MODE_PRECISION (mode);
8170         unsigned HOST_WIDE_INT smask = mask;
8171
8172         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8173            number, sign extend it.  */
8174
8175         if (width < HOST_BITS_PER_WIDE_INT
8176             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8177           smask |= HOST_WIDE_INT_M1U << width;
8178
8179         if (CONST_INT_P (XEXP (x, 1))
8180             && exact_log2 (- smask) >= 0
8181             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8182             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8183           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8184                                                (INTVAL (XEXP (x, 1)) & smask)),
8185                                 mode, smask, next_select);
8186       }
8187
8188       /* ... fall through ...  */
8189
8190     case MULT:
8191       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8192          most significant bit in MASK since carries from those bits will
8193          affect the bits we are interested in.  */
8194       mask = fuller_mask;
8195       goto binop;
8196
8197     case MINUS:
8198       /* If X is (minus C Y) where C's least set bit is larger than any bit
8199          in the mask, then we may replace with (neg Y).  */
8200       if (CONST_INT_P (XEXP (x, 0))
8201           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8202                                         & -INTVAL (XEXP (x, 0))))
8203               > mask))
8204         {
8205           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8206                                   GET_MODE (x));
8207           return force_to_mode (x, mode, mask, next_select);
8208         }
8209
8210       /* Similarly, if C contains every bit in the fuller_mask, then we may
8211          replace with (not Y).  */
8212       if (CONST_INT_P (XEXP (x, 0))
8213           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8214         {
8215           x = simplify_gen_unary (NOT, GET_MODE (x),
8216                                   XEXP (x, 1), GET_MODE (x));
8217           return force_to_mode (x, mode, mask, next_select);
8218         }
8219
8220       mask = fuller_mask;
8221       goto binop;
8222
8223     case IOR:
8224     case XOR:
8225       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8226          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8227          operation which may be a bitfield extraction.  Ensure that the
8228          constant we form is not wider than the mode of X.  */
8229
8230       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8231           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8232           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8233           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8234           && CONST_INT_P (XEXP (x, 1))
8235           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8236                + floor_log2 (INTVAL (XEXP (x, 1))))
8237               < GET_MODE_PRECISION (GET_MODE (x)))
8238           && (UINTVAL (XEXP (x, 1))
8239               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8240         {
8241           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8242                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8243                                GET_MODE (x));
8244           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8245                                       XEXP (XEXP (x, 0), 0), temp);
8246           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8247                                    XEXP (XEXP (x, 0), 1));
8248           return force_to_mode (x, mode, mask, next_select);
8249         }
8250
8251     binop:
8252       /* For most binary operations, just propagate into the operation and
8253          change the mode if we have an operation of that mode.  */
8254
8255       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8256       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8257
8258       /* If we ended up truncating both operands, truncate the result of the
8259          operation instead.  */
8260       if (GET_CODE (op0) == TRUNCATE
8261           && GET_CODE (op1) == TRUNCATE)
8262         {
8263           op0 = XEXP (op0, 0);
8264           op1 = XEXP (op1, 0);
8265         }
8266
8267       op0 = gen_lowpart_or_truncate (op_mode, op0);
8268       op1 = gen_lowpart_or_truncate (op_mode, op1);
8269
8270       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8271         x = simplify_gen_binary (code, op_mode, op0, op1);
8272       break;
8273
8274     case ASHIFT:
8275       /* For left shifts, do the same, but just for the first operand.
8276          However, we cannot do anything with shifts where we cannot
8277          guarantee that the counts are smaller than the size of the mode
8278          because such a count will have a different meaning in a
8279          wider mode.  */
8280
8281       if (! (CONST_INT_P (XEXP (x, 1))
8282              && INTVAL (XEXP (x, 1)) >= 0
8283              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8284           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8285                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8286                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8287         break;
8288
8289       /* If the shift count is a constant and we can do arithmetic in
8290          the mode of the shift, refine which bits we need.  Otherwise, use the
8291          conservative form of the mask.  */
8292       if (CONST_INT_P (XEXP (x, 1))
8293           && INTVAL (XEXP (x, 1)) >= 0
8294           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8295           && HWI_COMPUTABLE_MODE_P (op_mode))
8296         mask >>= INTVAL (XEXP (x, 1));
8297       else
8298         mask = fuller_mask;
8299
8300       op0 = gen_lowpart_or_truncate (op_mode,
8301                                      force_to_mode (XEXP (x, 0), op_mode,
8302                                                     mask, next_select));
8303
8304       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8305         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8306       break;
8307
8308     case LSHIFTRT:
8309       /* Here we can only do something if the shift count is a constant,
8310          this shift constant is valid for the host, and we can do arithmetic
8311          in OP_MODE.  */
8312
8313       if (CONST_INT_P (XEXP (x, 1))
8314           && INTVAL (XEXP (x, 1)) >= 0
8315           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8316           && HWI_COMPUTABLE_MODE_P (op_mode))
8317         {
8318           rtx inner = XEXP (x, 0);
8319           unsigned HOST_WIDE_INT inner_mask;
8320
8321           /* Select the mask of the bits we need for the shift operand.  */
8322           inner_mask = mask << INTVAL (XEXP (x, 1));
8323
8324           /* We can only change the mode of the shift if we can do arithmetic
8325              in the mode of the shift and INNER_MASK is no wider than the
8326              width of X's mode.  */
8327           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8328             op_mode = GET_MODE (x);
8329
8330           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8331
8332           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8333             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8334         }
8335
8336       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8337          shift and AND produces only copies of the sign bit (C2 is one less
8338          than a power of two), we can do this with just a shift.  */
8339
8340       if (GET_CODE (x) == LSHIFTRT
8341           && CONST_INT_P (XEXP (x, 1))
8342           /* The shift puts one of the sign bit copies in the least significant
8343              bit.  */
8344           && ((INTVAL (XEXP (x, 1))
8345                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8346               >= GET_MODE_PRECISION (GET_MODE (x)))
8347           && exact_log2 (mask + 1) >= 0
8348           /* Number of bits left after the shift must be more than the mask
8349              needs.  */
8350           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8351               <= GET_MODE_PRECISION (GET_MODE (x)))
8352           /* Must be more sign bit copies than the mask needs.  */
8353           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8354               >= exact_log2 (mask + 1)))
8355         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8356                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8357                                           - exact_log2 (mask + 1)));
8358
8359       goto shiftrt;
8360
8361     case ASHIFTRT:
8362       /* If we are just looking for the sign bit, we don't need this shift at
8363          all, even if it has a variable count.  */
8364       if (val_signbit_p (GET_MODE (x), mask))
8365         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8366
8367       /* If this is a shift by a constant, get a mask that contains those bits
8368          that are not copies of the sign bit.  We then have two cases:  If
8369          MASK only includes those bits, this can be a logical shift, which may
8370          allow simplifications.  If MASK is a single-bit field not within
8371          those bits, we are requesting a copy of the sign bit and hence can
8372          shift the sign bit to the appropriate location.  */
8373
8374       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8375           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8376         {
8377           int i;
8378
8379           /* If the considered data is wider than HOST_WIDE_INT, we can't
8380              represent a mask for all its bits in a single scalar.
8381              But we only care about the lower bits, so calculate these.  */
8382
8383           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8384             {
8385               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8386
8387               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8388                  is the number of bits a full-width mask would have set.
8389                  We need only shift if these are fewer than nonzero can
8390                  hold.  If not, we must keep all bits set in nonzero.  */
8391
8392               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8393                   < HOST_BITS_PER_WIDE_INT)
8394                 nonzero >>= INTVAL (XEXP (x, 1))
8395                             + HOST_BITS_PER_WIDE_INT
8396                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8397             }
8398           else
8399             {
8400               nonzero = GET_MODE_MASK (GET_MODE (x));
8401               nonzero >>= INTVAL (XEXP (x, 1));
8402             }
8403
8404           if ((mask & ~nonzero) == 0)
8405             {
8406               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8407                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8408               if (GET_CODE (x) != ASHIFTRT)
8409                 return force_to_mode (x, mode, mask, next_select);
8410             }
8411
8412           else if ((i = exact_log2 (mask)) >= 0)
8413             {
8414               x = simplify_shift_const
8415                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8416                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8417
8418               if (GET_CODE (x) != ASHIFTRT)
8419                 return force_to_mode (x, mode, mask, next_select);
8420             }
8421         }
8422
8423       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8424          even if the shift count isn't a constant.  */
8425       if (mask == 1)
8426         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8427                                  XEXP (x, 0), XEXP (x, 1));
8428
8429     shiftrt:
8430
8431       /* If this is a zero- or sign-extension operation that just affects bits
8432          we don't care about, remove it.  Be sure the call above returned
8433          something that is still a shift.  */
8434
8435       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8436           && CONST_INT_P (XEXP (x, 1))
8437           && INTVAL (XEXP (x, 1)) >= 0
8438           && (INTVAL (XEXP (x, 1))
8439               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8440           && GET_CODE (XEXP (x, 0)) == ASHIFT
8441           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8442         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8443                               next_select);
8444
8445       break;
8446
8447     case ROTATE:
8448     case ROTATERT:
8449       /* If the shift count is constant and we can do computations
8450          in the mode of X, compute where the bits we care about are.
8451          Otherwise, we can't do anything.  Don't change the mode of
8452          the shift or propagate MODE into the shift, though.  */
8453       if (CONST_INT_P (XEXP (x, 1))
8454           && INTVAL (XEXP (x, 1)) >= 0)
8455         {
8456           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8457                                             GET_MODE (x),
8458                                             gen_int_mode (mask, GET_MODE (x)),
8459                                             XEXP (x, 1));
8460           if (temp && CONST_INT_P (temp))
8461             SUBST (XEXP (x, 0),
8462                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8463                                   INTVAL (temp), next_select));
8464         }
8465       break;
8466
8467     case NEG:
8468       /* If we just want the low-order bit, the NEG isn't needed since it
8469          won't change the low-order bit.  */
8470       if (mask == 1)
8471         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8472
8473       /* We need any bits less significant than the most significant bit in
8474          MASK since carries from those bits will affect the bits we are
8475          interested in.  */
8476       mask = fuller_mask;
8477       goto unop;
8478
8479     case NOT:
8480       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8481          same as the XOR case above.  Ensure that the constant we form is not
8482          wider than the mode of X.  */
8483
8484       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8485           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8486           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8487           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8488               < GET_MODE_PRECISION (GET_MODE (x)))
8489           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8490         {
8491           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8492                                GET_MODE (x));
8493           temp = simplify_gen_binary (XOR, GET_MODE (x),
8494                                       XEXP (XEXP (x, 0), 0), temp);
8495           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8496                                    temp, XEXP (XEXP (x, 0), 1));
8497
8498           return force_to_mode (x, mode, mask, next_select);
8499         }
8500
8501       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8502          use the full mask inside the NOT.  */
8503       mask = fuller_mask;
8504
8505     unop:
8506       op0 = gen_lowpart_or_truncate (op_mode,
8507                                      force_to_mode (XEXP (x, 0), mode, mask,
8508                                                     next_select));
8509       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8510         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8511       break;
8512
8513     case NE:
8514       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8515          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8516          which is equal to STORE_FLAG_VALUE.  */
8517       if ((mask & ~STORE_FLAG_VALUE) == 0
8518           && XEXP (x, 1) == const0_rtx
8519           && GET_MODE (XEXP (x, 0)) == mode
8520           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8521           && (nonzero_bits (XEXP (x, 0), mode)
8522               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8523         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8524
8525       break;
8526
8527     case IF_THEN_ELSE:
8528       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8529          written in a narrower mode.  We play it safe and do not do so.  */
8530
8531       SUBST (XEXP (x, 1),
8532              gen_lowpart_or_truncate (GET_MODE (x),
8533                                       force_to_mode (XEXP (x, 1), mode,
8534                                                      mask, next_select)));
8535       SUBST (XEXP (x, 2),
8536              gen_lowpart_or_truncate (GET_MODE (x),
8537                                       force_to_mode (XEXP (x, 2), mode,
8538                                                      mask, next_select)));
8539       break;
8540
8541     default:
8542       break;
8543     }
8544
8545   /* Ensure we return a value of the proper mode.  */
8546   return gen_lowpart_or_truncate (mode, x);
8547 }
8548 \f
8549 /* Return nonzero if X is an expression that has one of two values depending on
8550    whether some other value is zero or nonzero.  In that case, we return the
8551    value that is being tested, *PTRUE is set to the value if the rtx being
8552    returned has a nonzero value, and *PFALSE is set to the other alternative.
8553
8554    If we return zero, we set *PTRUE and *PFALSE to X.  */
8555
8556 static rtx
8557 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8558 {
8559   enum machine_mode mode = GET_MODE (x);
8560   enum rtx_code code = GET_CODE (x);
8561   rtx cond0, cond1, true0, true1, false0, false1;
8562   unsigned HOST_WIDE_INT nz;
8563
8564   /* If we are comparing a value against zero, we are done.  */
8565   if ((code == NE || code == EQ)
8566       && XEXP (x, 1) == const0_rtx)
8567     {
8568       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8569       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8570       return XEXP (x, 0);
8571     }
8572
8573   /* If this is a unary operation whose operand has one of two values, apply
8574      our opcode to compute those values.  */
8575   else if (UNARY_P (x)
8576            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8577     {
8578       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8579       *pfalse = simplify_gen_unary (code, mode, false0,
8580                                     GET_MODE (XEXP (x, 0)));
8581       return cond0;
8582     }
8583
8584   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8585      make can't possibly match and would suppress other optimizations.  */
8586   else if (code == COMPARE)
8587     ;
8588
8589   /* If this is a binary operation, see if either side has only one of two
8590      values.  If either one does or if both do and they are conditional on
8591      the same value, compute the new true and false values.  */
8592   else if (BINARY_P (x))
8593     {
8594       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8595       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8596
8597       if ((cond0 != 0 || cond1 != 0)
8598           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8599         {
8600           /* If if_then_else_cond returned zero, then true/false are the
8601              same rtl.  We must copy one of them to prevent invalid rtl
8602              sharing.  */
8603           if (cond0 == 0)
8604             true0 = copy_rtx (true0);
8605           else if (cond1 == 0)
8606             true1 = copy_rtx (true1);
8607
8608           if (COMPARISON_P (x))
8609             {
8610               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8611                                                 true0, true1);
8612               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8613                                                  false0, false1);
8614              }
8615           else
8616             {
8617               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8618               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8619             }
8620
8621           return cond0 ? cond0 : cond1;
8622         }
8623
8624       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8625          operands is zero when the other is nonzero, and vice-versa,
8626          and STORE_FLAG_VALUE is 1 or -1.  */
8627
8628       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8629           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8630               || code == UMAX)
8631           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8632         {
8633           rtx op0 = XEXP (XEXP (x, 0), 1);
8634           rtx op1 = XEXP (XEXP (x, 1), 1);
8635
8636           cond0 = XEXP (XEXP (x, 0), 0);
8637           cond1 = XEXP (XEXP (x, 1), 0);
8638
8639           if (COMPARISON_P (cond0)
8640               && COMPARISON_P (cond1)
8641               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8642                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8643                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8644                   || ((swap_condition (GET_CODE (cond0))
8645                        == reversed_comparison_code (cond1, NULL))
8646                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8647                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8648               && ! side_effects_p (x))
8649             {
8650               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8651               *pfalse = simplify_gen_binary (MULT, mode,
8652                                              (code == MINUS
8653                                               ? simplify_gen_unary (NEG, mode,
8654                                                                     op1, mode)
8655                                               : op1),
8656                                               const_true_rtx);
8657               return cond0;
8658             }
8659         }
8660
8661       /* Similarly for MULT, AND and UMIN, except that for these the result
8662          is always zero.  */
8663       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8664           && (code == MULT || code == AND || code == UMIN)
8665           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8666         {
8667           cond0 = XEXP (XEXP (x, 0), 0);
8668           cond1 = XEXP (XEXP (x, 1), 0);
8669
8670           if (COMPARISON_P (cond0)
8671               && COMPARISON_P (cond1)
8672               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8673                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8674                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8675                   || ((swap_condition (GET_CODE (cond0))
8676                        == reversed_comparison_code (cond1, NULL))
8677                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8678                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8679               && ! side_effects_p (x))
8680             {
8681               *ptrue = *pfalse = const0_rtx;
8682               return cond0;
8683             }
8684         }
8685     }
8686
8687   else if (code == IF_THEN_ELSE)
8688     {
8689       /* If we have IF_THEN_ELSE already, extract the condition and
8690          canonicalize it if it is NE or EQ.  */
8691       cond0 = XEXP (x, 0);
8692       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8693       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8694         return XEXP (cond0, 0);
8695       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8696         {
8697           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8698           return XEXP (cond0, 0);
8699         }
8700       else
8701         return cond0;
8702     }
8703
8704   /* If X is a SUBREG, we can narrow both the true and false values
8705      if the inner expression, if there is a condition.  */
8706   else if (code == SUBREG
8707            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8708                                                &true0, &false0)))
8709     {
8710       true0 = simplify_gen_subreg (mode, true0,
8711                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8712       false0 = simplify_gen_subreg (mode, false0,
8713                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8714       if (true0 && false0)
8715         {
8716           *ptrue = true0;
8717           *pfalse = false0;
8718           return cond0;
8719         }
8720     }
8721
8722   /* If X is a constant, this isn't special and will cause confusions
8723      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8724   else if (CONSTANT_P (x)
8725            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8726     ;
8727
8728   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8729      will be least confusing to the rest of the compiler.  */
8730   else if (mode == BImode)
8731     {
8732       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8733       return x;
8734     }
8735
8736   /* If X is known to be either 0 or -1, those are the true and
8737      false values when testing X.  */
8738   else if (x == constm1_rtx || x == const0_rtx
8739            || (mode != VOIDmode
8740                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8741     {
8742       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8743       return x;
8744     }
8745
8746   /* Likewise for 0 or a single bit.  */
8747   else if (HWI_COMPUTABLE_MODE_P (mode)
8748            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8749     {
8750       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8751       return x;
8752     }
8753
8754   /* Otherwise fail; show no condition with true and false values the same.  */
8755   *ptrue = *pfalse = x;
8756   return 0;
8757 }
8758 \f
8759 /* Return the value of expression X given the fact that condition COND
8760    is known to be true when applied to REG as its first operand and VAL
8761    as its second.  X is known to not be shared and so can be modified in
8762    place.
8763
8764    We only handle the simplest cases, and specifically those cases that
8765    arise with IF_THEN_ELSE expressions.  */
8766
8767 static rtx
8768 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8769 {
8770   enum rtx_code code = GET_CODE (x);
8771   rtx temp;
8772   const char *fmt;
8773   int i, j;
8774
8775   if (side_effects_p (x))
8776     return x;
8777
8778   /* If either operand of the condition is a floating point value,
8779      then we have to avoid collapsing an EQ comparison.  */
8780   if (cond == EQ
8781       && rtx_equal_p (x, reg)
8782       && ! FLOAT_MODE_P (GET_MODE (x))
8783       && ! FLOAT_MODE_P (GET_MODE (val)))
8784     return val;
8785
8786   if (cond == UNEQ && rtx_equal_p (x, reg))
8787     return val;
8788
8789   /* If X is (abs REG) and we know something about REG's relationship
8790      with zero, we may be able to simplify this.  */
8791
8792   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8793     switch (cond)
8794       {
8795       case GE:  case GT:  case EQ:
8796         return XEXP (x, 0);
8797       case LT:  case LE:
8798         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8799                                    XEXP (x, 0),
8800                                    GET_MODE (XEXP (x, 0)));
8801       default:
8802         break;
8803       }
8804
8805   /* The only other cases we handle are MIN, MAX, and comparisons if the
8806      operands are the same as REG and VAL.  */
8807
8808   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8809     {
8810       if (rtx_equal_p (XEXP (x, 0), val))
8811         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8812
8813       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8814         {
8815           if (COMPARISON_P (x))
8816             {
8817               if (comparison_dominates_p (cond, code))
8818                 return const_true_rtx;
8819
8820               code = reversed_comparison_code (x, NULL);
8821               if (code != UNKNOWN
8822                   && comparison_dominates_p (cond, code))
8823                 return const0_rtx;
8824               else
8825                 return x;
8826             }
8827           else if (code == SMAX || code == SMIN
8828                    || code == UMIN || code == UMAX)
8829             {
8830               int unsignedp = (code == UMIN || code == UMAX);
8831
8832               /* Do not reverse the condition when it is NE or EQ.
8833                  This is because we cannot conclude anything about
8834                  the value of 'SMAX (x, y)' when x is not equal to y,
8835                  but we can when x equals y.  */
8836               if ((code == SMAX || code == UMAX)
8837                   && ! (cond == EQ || cond == NE))
8838                 cond = reverse_condition (cond);
8839
8840               switch (cond)
8841                 {
8842                 case GE:   case GT:
8843                   return unsignedp ? x : XEXP (x, 1);
8844                 case LE:   case LT:
8845                   return unsignedp ? x : XEXP (x, 0);
8846                 case GEU:  case GTU:
8847                   return unsignedp ? XEXP (x, 1) : x;
8848                 case LEU:  case LTU:
8849                   return unsignedp ? XEXP (x, 0) : x;
8850                 default:
8851                   break;
8852                 }
8853             }
8854         }
8855     }
8856   else if (code == SUBREG)
8857     {
8858       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8859       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8860
8861       if (SUBREG_REG (x) != r)
8862         {
8863           /* We must simplify subreg here, before we lose track of the
8864              original inner_mode.  */
8865           new_rtx = simplify_subreg (GET_MODE (x), r,
8866                                  inner_mode, SUBREG_BYTE (x));
8867           if (new_rtx)
8868             return new_rtx;
8869           else
8870             SUBST (SUBREG_REG (x), r);
8871         }
8872
8873       return x;
8874     }
8875   /* We don't have to handle SIGN_EXTEND here, because even in the
8876      case of replacing something with a modeless CONST_INT, a
8877      CONST_INT is already (supposed to be) a valid sign extension for
8878      its narrower mode, which implies it's already properly
8879      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8880      story is different.  */
8881   else if (code == ZERO_EXTEND)
8882     {
8883       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8884       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8885
8886       if (XEXP (x, 0) != r)
8887         {
8888           /* We must simplify the zero_extend here, before we lose
8889              track of the original inner_mode.  */
8890           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8891                                           r, inner_mode);
8892           if (new_rtx)
8893             return new_rtx;
8894           else
8895             SUBST (XEXP (x, 0), r);
8896         }
8897
8898       return x;
8899     }
8900
8901   fmt = GET_RTX_FORMAT (code);
8902   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8903     {
8904       if (fmt[i] == 'e')
8905         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8906       else if (fmt[i] == 'E')
8907         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8908           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8909                                                 cond, reg, val));
8910     }
8911
8912   return x;
8913 }
8914 \f
8915 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8916    assignment as a field assignment.  */
8917
8918 static int
8919 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8920 {
8921   if (x == y || rtx_equal_p (x, y))
8922     return 1;
8923
8924   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8925     return 0;
8926
8927   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8928      Note that all SUBREGs of MEM are paradoxical; otherwise they
8929      would have been rewritten.  */
8930   if (MEM_P (x) && GET_CODE (y) == SUBREG
8931       && MEM_P (SUBREG_REG (y))
8932       && rtx_equal_p (SUBREG_REG (y),
8933                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8934     return 1;
8935
8936   if (MEM_P (y) && GET_CODE (x) == SUBREG
8937       && MEM_P (SUBREG_REG (x))
8938       && rtx_equal_p (SUBREG_REG (x),
8939                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8940     return 1;
8941
8942   /* We used to see if get_last_value of X and Y were the same but that's
8943      not correct.  In one direction, we'll cause the assignment to have
8944      the wrong destination and in the case, we'll import a register into this
8945      insn that might have already have been dead.   So fail if none of the
8946      above cases are true.  */
8947   return 0;
8948 }
8949 \f
8950 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8951    Return that assignment if so.
8952
8953    We only handle the most common cases.  */
8954
8955 static rtx
8956 make_field_assignment (rtx x)
8957 {
8958   rtx dest = SET_DEST (x);
8959   rtx src = SET_SRC (x);
8960   rtx assign;
8961   rtx rhs, lhs;
8962   HOST_WIDE_INT c1;
8963   HOST_WIDE_INT pos;
8964   unsigned HOST_WIDE_INT len;
8965   rtx other;
8966   enum machine_mode mode;
8967
8968   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8969      a clear of a one-bit field.  We will have changed it to
8970      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8971      for a SUBREG.  */
8972
8973   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8974       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8975       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8976       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8977     {
8978       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8979                                 1, 1, 1, 0);
8980       if (assign != 0)
8981         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8982       return x;
8983     }
8984
8985   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8986       && subreg_lowpart_p (XEXP (src, 0))
8987       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8988           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8989       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8990       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8991       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8992       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8993     {
8994       assign = make_extraction (VOIDmode, dest, 0,
8995                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8996                                 1, 1, 1, 0);
8997       if (assign != 0)
8998         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8999       return x;
9000     }
9001
9002   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9003      one-bit field.  */
9004   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9005       && XEXP (XEXP (src, 0), 0) == const1_rtx
9006       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9007     {
9008       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9009                                 1, 1, 1, 0);
9010       if (assign != 0)
9011         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9012       return x;
9013     }
9014
9015   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9016      SRC is an AND with all bits of that field set, then we can discard
9017      the AND.  */
9018   if (GET_CODE (dest) == ZERO_EXTRACT
9019       && CONST_INT_P (XEXP (dest, 1))
9020       && GET_CODE (src) == AND
9021       && CONST_INT_P (XEXP (src, 1)))
9022     {
9023       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9024       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9025       unsigned HOST_WIDE_INT ze_mask;
9026
9027       if (width >= HOST_BITS_PER_WIDE_INT)
9028         ze_mask = -1;
9029       else
9030         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9031
9032       /* Complete overlap.  We can remove the source AND.  */
9033       if ((and_mask & ze_mask) == ze_mask)
9034         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9035
9036       /* Partial overlap.  We can reduce the source AND.  */
9037       if ((and_mask & ze_mask) != and_mask)
9038         {
9039           mode = GET_MODE (src);
9040           src = gen_rtx_AND (mode, XEXP (src, 0),
9041                              gen_int_mode (and_mask & ze_mask, mode));
9042           return gen_rtx_SET (VOIDmode, dest, src);
9043         }
9044     }
9045
9046   /* The other case we handle is assignments into a constant-position
9047      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9048      a mask that has all one bits except for a group of zero bits and
9049      OTHER is known to have zeros where C1 has ones, this is such an
9050      assignment.  Compute the position and length from C1.  Shift OTHER
9051      to the appropriate position, force it to the required mode, and
9052      make the extraction.  Check for the AND in both operands.  */
9053
9054   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9055     return x;
9056
9057   rhs = expand_compound_operation (XEXP (src, 0));
9058   lhs = expand_compound_operation (XEXP (src, 1));
9059
9060   if (GET_CODE (rhs) == AND
9061       && CONST_INT_P (XEXP (rhs, 1))
9062       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9063     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9064   else if (GET_CODE (lhs) == AND
9065            && CONST_INT_P (XEXP (lhs, 1))
9066            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9067     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9068   else
9069     return x;
9070
9071   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9072   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9073       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9074       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9075     return x;
9076
9077   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9078   if (assign == 0)
9079     return x;
9080
9081   /* The mode to use for the source is the mode of the assignment, or of
9082      what is inside a possible STRICT_LOW_PART.  */
9083   mode = (GET_CODE (assign) == STRICT_LOW_PART
9084           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9085
9086   /* Shift OTHER right POS places and make it the source, restricting it
9087      to the proper length and mode.  */
9088
9089   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9090                                                      GET_MODE (src),
9091                                                      other, pos),
9092                                dest);
9093   src = force_to_mode (src, mode,
9094                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9095                        ? ~(unsigned HOST_WIDE_INT) 0
9096                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9097                        0);
9098
9099   /* If SRC is masked by an AND that does not make a difference in
9100      the value being stored, strip it.  */
9101   if (GET_CODE (assign) == ZERO_EXTRACT
9102       && CONST_INT_P (XEXP (assign, 1))
9103       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9104       && GET_CODE (src) == AND
9105       && CONST_INT_P (XEXP (src, 1))
9106       && UINTVAL (XEXP (src, 1))
9107          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9108     src = XEXP (src, 0);
9109
9110   return gen_rtx_SET (VOIDmode, assign, src);
9111 }
9112 \f
9113 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9114    if so.  */
9115
9116 static rtx
9117 apply_distributive_law (rtx x)
9118 {
9119   enum rtx_code code = GET_CODE (x);
9120   enum rtx_code inner_code;
9121   rtx lhs, rhs, other;
9122   rtx tem;
9123
9124   /* Distributivity is not true for floating point as it can change the
9125      value.  So we don't do it unless -funsafe-math-optimizations.  */
9126   if (FLOAT_MODE_P (GET_MODE (x))
9127       && ! flag_unsafe_math_optimizations)
9128     return x;
9129
9130   /* The outer operation can only be one of the following:  */
9131   if (code != IOR && code != AND && code != XOR
9132       && code != PLUS && code != MINUS)
9133     return x;
9134
9135   lhs = XEXP (x, 0);
9136   rhs = XEXP (x, 1);
9137
9138   /* If either operand is a primitive we can't do anything, so get out
9139      fast.  */
9140   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9141     return x;
9142
9143   lhs = expand_compound_operation (lhs);
9144   rhs = expand_compound_operation (rhs);
9145   inner_code = GET_CODE (lhs);
9146   if (inner_code != GET_CODE (rhs))
9147     return x;
9148
9149   /* See if the inner and outer operations distribute.  */
9150   switch (inner_code)
9151     {
9152     case LSHIFTRT:
9153     case ASHIFTRT:
9154     case AND:
9155     case IOR:
9156       /* These all distribute except over PLUS.  */
9157       if (code == PLUS || code == MINUS)
9158         return x;
9159       break;
9160
9161     case MULT:
9162       if (code != PLUS && code != MINUS)
9163         return x;
9164       break;
9165
9166     case ASHIFT:
9167       /* This is also a multiply, so it distributes over everything.  */
9168       break;
9169
9170     /* This used to handle SUBREG, but this turned out to be counter-
9171        productive, since (subreg (op ...)) usually is not handled by
9172        insn patterns, and this "optimization" therefore transformed
9173        recognizable patterns into unrecognizable ones.  Therefore the
9174        SUBREG case was removed from here.
9175
9176        It is possible that distributing SUBREG over arithmetic operations
9177        leads to an intermediate result than can then be optimized further,
9178        e.g. by moving the outer SUBREG to the other side of a SET as done
9179        in simplify_set.  This seems to have been the original intent of
9180        handling SUBREGs here.
9181
9182        However, with current GCC this does not appear to actually happen,
9183        at least on major platforms.  If some case is found where removing
9184        the SUBREG case here prevents follow-on optimizations, distributing
9185        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9186
9187     default:
9188       return x;
9189     }
9190
9191   /* Set LHS and RHS to the inner operands (A and B in the example
9192      above) and set OTHER to the common operand (C in the example).
9193      There is only one way to do this unless the inner operation is
9194      commutative.  */
9195   if (COMMUTATIVE_ARITH_P (lhs)
9196       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9197     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9198   else if (COMMUTATIVE_ARITH_P (lhs)
9199            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9200     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9201   else if (COMMUTATIVE_ARITH_P (lhs)
9202            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9203     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9204   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9205     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9206   else
9207     return x;
9208
9209   /* Form the new inner operation, seeing if it simplifies first.  */
9210   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9211
9212   /* There is one exception to the general way of distributing:
9213      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9214   if (code == XOR && inner_code == IOR)
9215     {
9216       inner_code = AND;
9217       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9218     }
9219
9220   /* We may be able to continuing distributing the result, so call
9221      ourselves recursively on the inner operation before forming the
9222      outer operation, which we return.  */
9223   return simplify_gen_binary (inner_code, GET_MODE (x),
9224                               apply_distributive_law (tem), other);
9225 }
9226
9227 /* See if X is of the form (* (+ A B) C), and if so convert to
9228    (+ (* A C) (* B C)) and try to simplify.
9229
9230    Most of the time, this results in no change.  However, if some of
9231    the operands are the same or inverses of each other, simplifications
9232    will result.
9233
9234    For example, (and (ior A B) (not B)) can occur as the result of
9235    expanding a bit field assignment.  When we apply the distributive
9236    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9237    which then simplifies to (and (A (not B))).
9238
9239    Note that no checks happen on the validity of applying the inverse
9240    distributive law.  This is pointless since we can do it in the
9241    few places where this routine is called.
9242
9243    N is the index of the term that is decomposed (the arithmetic operation,
9244    i.e. (+ A B) in the first example above).  !N is the index of the term that
9245    is distributed, i.e. of C in the first example above.  */
9246 static rtx
9247 distribute_and_simplify_rtx (rtx x, int n)
9248 {
9249   enum machine_mode mode;
9250   enum rtx_code outer_code, inner_code;
9251   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9252
9253   /* Distributivity is not true for floating point as it can change the
9254      value.  So we don't do it unless -funsafe-math-optimizations.  */
9255   if (FLOAT_MODE_P (GET_MODE (x))
9256       && ! flag_unsafe_math_optimizations)
9257     return NULL_RTX;
9258
9259   decomposed = XEXP (x, n);
9260   if (!ARITHMETIC_P (decomposed))
9261     return NULL_RTX;
9262
9263   mode = GET_MODE (x);
9264   outer_code = GET_CODE (x);
9265   distributed = XEXP (x, !n);
9266
9267   inner_code = GET_CODE (decomposed);
9268   inner_op0 = XEXP (decomposed, 0);
9269   inner_op1 = XEXP (decomposed, 1);
9270
9271   /* Special case (and (xor B C) (not A)), which is equivalent to
9272      (xor (ior A B) (ior A C))  */
9273   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9274     {
9275       distributed = XEXP (distributed, 0);
9276       outer_code = IOR;
9277     }
9278
9279   if (n == 0)
9280     {
9281       /* Distribute the second term.  */
9282       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9283       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9284     }
9285   else
9286     {
9287       /* Distribute the first term.  */
9288       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9289       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9290     }
9291
9292   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9293                                                      new_op0, new_op1));
9294   if (GET_CODE (tmp) != outer_code
9295       && (set_src_cost (tmp, optimize_this_for_speed_p)
9296           < set_src_cost (x, optimize_this_for_speed_p)))
9297     return tmp;
9298
9299   return NULL_RTX;
9300 }
9301 \f
9302 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9303    in MODE.  Return an equivalent form, if different from (and VAROP
9304    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9305
9306 static rtx
9307 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9308                           unsigned HOST_WIDE_INT constop)
9309 {
9310   unsigned HOST_WIDE_INT nonzero;
9311   unsigned HOST_WIDE_INT orig_constop;
9312   rtx orig_varop;
9313   int i;
9314
9315   orig_varop = varop;
9316   orig_constop = constop;
9317   if (GET_CODE (varop) == CLOBBER)
9318     return NULL_RTX;
9319
9320   /* Simplify VAROP knowing that we will be only looking at some of the
9321      bits in it.
9322
9323      Note by passing in CONSTOP, we guarantee that the bits not set in
9324      CONSTOP are not significant and will never be examined.  We must
9325      ensure that is the case by explicitly masking out those bits
9326      before returning.  */
9327   varop = force_to_mode (varop, mode, constop, 0);
9328
9329   /* If VAROP is a CLOBBER, we will fail so return it.  */
9330   if (GET_CODE (varop) == CLOBBER)
9331     return varop;
9332
9333   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9334      to VAROP and return the new constant.  */
9335   if (CONST_INT_P (varop))
9336     return gen_int_mode (INTVAL (varop) & constop, mode);
9337
9338   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9339      a call to nonzero_bits, here we don't care about bits outside
9340      MODE.  */
9341
9342   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9343
9344   /* Turn off all bits in the constant that are known to already be zero.
9345      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9346      which is tested below.  */
9347
9348   constop &= nonzero;
9349
9350   /* If we don't have any bits left, return zero.  */
9351   if (constop == 0)
9352     return const0_rtx;
9353
9354   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9355      a power of two, we can replace this with an ASHIFT.  */
9356   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9357       && (i = exact_log2 (constop)) >= 0)
9358     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9359
9360   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9361      or XOR, then try to apply the distributive law.  This may eliminate
9362      operations if either branch can be simplified because of the AND.
9363      It may also make some cases more complex, but those cases probably
9364      won't match a pattern either with or without this.  */
9365
9366   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9367     return
9368       gen_lowpart
9369         (mode,
9370          apply_distributive_law
9371          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9372                                simplify_and_const_int (NULL_RTX,
9373                                                        GET_MODE (varop),
9374                                                        XEXP (varop, 0),
9375                                                        constop),
9376                                simplify_and_const_int (NULL_RTX,
9377                                                        GET_MODE (varop),
9378                                                        XEXP (varop, 1),
9379                                                        constop))));
9380
9381   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9382      the AND and see if one of the operands simplifies to zero.  If so, we
9383      may eliminate it.  */
9384
9385   if (GET_CODE (varop) == PLUS
9386       && exact_log2 (constop + 1) >= 0)
9387     {
9388       rtx o0, o1;
9389
9390       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9391       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9392       if (o0 == const0_rtx)
9393         return o1;
9394       if (o1 == const0_rtx)
9395         return o0;
9396     }
9397
9398   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9399   varop = gen_lowpart (mode, varop);
9400   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9401     return NULL_RTX;
9402
9403   /* If we are only masking insignificant bits, return VAROP.  */
9404   if (constop == nonzero)
9405     return varop;
9406
9407   if (varop == orig_varop && constop == orig_constop)
9408     return NULL_RTX;
9409
9410   /* Otherwise, return an AND.  */
9411   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9412 }
9413
9414
9415 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9416    in MODE.
9417
9418    Return an equivalent form, if different from X.  Otherwise, return X.  If
9419    X is zero, we are to always construct the equivalent form.  */
9420
9421 static rtx
9422 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9423                         unsigned HOST_WIDE_INT constop)
9424 {
9425   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9426   if (tem)
9427     return tem;
9428
9429   if (!x)
9430     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9431                              gen_int_mode (constop, mode));
9432   if (GET_MODE (x) != mode)
9433     x = gen_lowpart (mode, x);
9434   return x;
9435 }
9436 \f
9437 /* Given a REG, X, compute which bits in X can be nonzero.
9438    We don't care about bits outside of those defined in MODE.
9439
9440    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9441    a shift, AND, or zero_extract, we can do better.  */
9442
9443 static rtx
9444 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9445                               const_rtx known_x ATTRIBUTE_UNUSED,
9446                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9447                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9448                               unsigned HOST_WIDE_INT *nonzero)
9449 {
9450   rtx tem;
9451   reg_stat_type *rsp;
9452
9453   /* If X is a register whose nonzero bits value is current, use it.
9454      Otherwise, if X is a register whose value we can find, use that
9455      value.  Otherwise, use the previously-computed global nonzero bits
9456      for this register.  */
9457
9458   rsp = &reg_stat[REGNO (x)];
9459   if (rsp->last_set_value != 0
9460       && (rsp->last_set_mode == mode
9461           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9462               && GET_MODE_CLASS (mode) == MODE_INT))
9463       && ((rsp->last_set_label >= label_tick_ebb_start
9464            && rsp->last_set_label < label_tick)
9465           || (rsp->last_set_label == label_tick
9466               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9467           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9468               && REG_N_SETS (REGNO (x)) == 1
9469               && !REGNO_REG_SET_P
9470                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9471     {
9472       *nonzero &= rsp->last_set_nonzero_bits;
9473       return NULL;
9474     }
9475
9476   tem = get_last_value (x);
9477
9478   if (tem)
9479     {
9480 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9481       /* If X is narrower than MODE and TEM is a non-negative
9482          constant that would appear negative in the mode of X,
9483          sign-extend it for use in reg_nonzero_bits because some
9484          machines (maybe most) will actually do the sign-extension
9485          and this is the conservative approach.
9486
9487          ??? For 2.5, try to tighten up the MD files in this regard
9488          instead of this kludge.  */
9489
9490       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9491           && CONST_INT_P (tem)
9492           && INTVAL (tem) > 0
9493           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9494         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9495 #endif
9496       return tem;
9497     }
9498   else if (nonzero_sign_valid && rsp->nonzero_bits)
9499     {
9500       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9501
9502       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9503         /* We don't know anything about the upper bits.  */
9504         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9505       *nonzero &= mask;
9506     }
9507
9508   return NULL;
9509 }
9510
9511 /* Return the number of bits at the high-order end of X that are known to
9512    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9513    VOIDmode, X will be used in its own mode.  The returned value  will always
9514    be between 1 and the number of bits in MODE.  */
9515
9516 static rtx
9517 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9518                                      const_rtx known_x ATTRIBUTE_UNUSED,
9519                                      enum machine_mode known_mode
9520                                      ATTRIBUTE_UNUSED,
9521                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9522                                      unsigned int *result)
9523 {
9524   rtx tem;
9525   reg_stat_type *rsp;
9526
9527   rsp = &reg_stat[REGNO (x)];
9528   if (rsp->last_set_value != 0
9529       && rsp->last_set_mode == mode
9530       && ((rsp->last_set_label >= label_tick_ebb_start
9531            && rsp->last_set_label < label_tick)
9532           || (rsp->last_set_label == label_tick
9533               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9534           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9535               && REG_N_SETS (REGNO (x)) == 1
9536               && !REGNO_REG_SET_P
9537                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9538     {
9539       *result = rsp->last_set_sign_bit_copies;
9540       return NULL;
9541     }
9542
9543   tem = get_last_value (x);
9544   if (tem != 0)
9545     return tem;
9546
9547   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9548       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9549     *result = rsp->sign_bit_copies;
9550
9551   return NULL;
9552 }
9553 \f
9554 /* Return the number of "extended" bits there are in X, when interpreted
9555    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9556    unsigned quantities, this is the number of high-order zero bits.
9557    For signed quantities, this is the number of copies of the sign bit
9558    minus 1.  In both case, this function returns the number of "spare"
9559    bits.  For example, if two quantities for which this function returns
9560    at least 1 are added, the addition is known not to overflow.
9561
9562    This function will always return 0 unless called during combine, which
9563    implies that it must be called from a define_split.  */
9564
9565 unsigned int
9566 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9567 {
9568   if (nonzero_sign_valid == 0)
9569     return 0;
9570
9571   return (unsignedp
9572           ? (HWI_COMPUTABLE_MODE_P (mode)
9573              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9574                                - floor_log2 (nonzero_bits (x, mode)))
9575              : 0)
9576           : num_sign_bit_copies (x, mode) - 1);
9577 }
9578
9579 /* This function is called from `simplify_shift_const' to merge two
9580    outer operations.  Specifically, we have already found that we need
9581    to perform operation *POP0 with constant *PCONST0 at the outermost
9582    position.  We would now like to also perform OP1 with constant CONST1
9583    (with *POP0 being done last).
9584
9585    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9586    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9587    complement the innermost operand, otherwise it is unchanged.
9588
9589    MODE is the mode in which the operation will be done.  No bits outside
9590    the width of this mode matter.  It is assumed that the width of this mode
9591    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9592
9593    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9594    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9595    result is simply *PCONST0.
9596
9597    If the resulting operation cannot be expressed as one operation, we
9598    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9599
9600 static int
9601 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9602 {
9603   enum rtx_code op0 = *pop0;
9604   HOST_WIDE_INT const0 = *pconst0;
9605
9606   const0 &= GET_MODE_MASK (mode);
9607   const1 &= GET_MODE_MASK (mode);
9608
9609   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9610   if (op0 == AND)
9611     const1 &= const0;
9612
9613   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9614      if OP0 is SET.  */
9615
9616   if (op1 == UNKNOWN || op0 == SET)
9617     return 1;
9618
9619   else if (op0 == UNKNOWN)
9620     op0 = op1, const0 = const1;
9621
9622   else if (op0 == op1)
9623     {
9624       switch (op0)
9625         {
9626         case AND:
9627           const0 &= const1;
9628           break;
9629         case IOR:
9630           const0 |= const1;
9631           break;
9632         case XOR:
9633           const0 ^= const1;
9634           break;
9635         case PLUS:
9636           const0 += const1;
9637           break;
9638         case NEG:
9639           op0 = UNKNOWN;
9640           break;
9641         default:
9642           break;
9643         }
9644     }
9645
9646   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9647   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9648     return 0;
9649
9650   /* If the two constants aren't the same, we can't do anything.  The
9651      remaining six cases can all be done.  */
9652   else if (const0 != const1)
9653     return 0;
9654
9655   else
9656     switch (op0)
9657       {
9658       case IOR:
9659         if (op1 == AND)
9660           /* (a & b) | b == b */
9661           op0 = SET;
9662         else /* op1 == XOR */
9663           /* (a ^ b) | b == a | b */
9664           {;}
9665         break;
9666
9667       case XOR:
9668         if (op1 == AND)
9669           /* (a & b) ^ b == (~a) & b */
9670           op0 = AND, *pcomp_p = 1;
9671         else /* op1 == IOR */
9672           /* (a | b) ^ b == a & ~b */
9673           op0 = AND, const0 = ~const0;
9674         break;
9675
9676       case AND:
9677         if (op1 == IOR)
9678           /* (a | b) & b == b */
9679         op0 = SET;
9680         else /* op1 == XOR */
9681           /* (a ^ b) & b) == (~a) & b */
9682           *pcomp_p = 1;
9683         break;
9684       default:
9685         break;
9686       }
9687
9688   /* Check for NO-OP cases.  */
9689   const0 &= GET_MODE_MASK (mode);
9690   if (const0 == 0
9691       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9692     op0 = UNKNOWN;
9693   else if (const0 == 0 && op0 == AND)
9694     op0 = SET;
9695   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9696            && op0 == AND)
9697     op0 = UNKNOWN;
9698
9699   *pop0 = op0;
9700
9701   /* ??? Slightly redundant with the above mask, but not entirely.
9702      Moving this above means we'd have to sign-extend the mode mask
9703      for the final test.  */
9704   if (op0 != UNKNOWN && op0 != NEG)
9705     *pconst0 = trunc_int_for_mode (const0, mode);
9706
9707   return 1;
9708 }
9709 \f
9710 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9711    the shift in.  The original shift operation CODE is performed on OP in
9712    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9713    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9714    result of the shift is subject to operation OUTER_CODE with operand
9715    OUTER_CONST.  */
9716
9717 static enum machine_mode
9718 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9719                       enum machine_mode orig_mode, enum machine_mode mode,
9720                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9721 {
9722   if (orig_mode == mode)
9723     return mode;
9724   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9725
9726   /* In general we can't perform in wider mode for right shift and rotate.  */
9727   switch (code)
9728     {
9729     case ASHIFTRT:
9730       /* We can still widen if the bits brought in from the left are identical
9731          to the sign bit of ORIG_MODE.  */
9732       if (num_sign_bit_copies (op, mode)
9733           > (unsigned) (GET_MODE_PRECISION (mode)
9734                         - GET_MODE_PRECISION (orig_mode)))
9735         return mode;
9736       return orig_mode;
9737
9738     case LSHIFTRT:
9739       /* Similarly here but with zero bits.  */
9740       if (HWI_COMPUTABLE_MODE_P (mode)
9741           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9742         return mode;
9743
9744       /* We can also widen if the bits brought in will be masked off.  This
9745          operation is performed in ORIG_MODE.  */
9746       if (outer_code == AND)
9747         {
9748           int care_bits = low_bitmask_len (orig_mode, outer_const);
9749
9750           if (care_bits >= 0
9751               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9752             return mode;
9753         }
9754       /* fall through */
9755
9756     case ROTATE:
9757       return orig_mode;
9758
9759     case ROTATERT:
9760       gcc_unreachable ();
9761
9762     default:
9763       return mode;
9764     }
9765 }
9766
9767 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9768    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9769    if we cannot simplify it.  Otherwise, return a simplified value.
9770
9771    The shift is normally computed in the widest mode we find in VAROP, as
9772    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9773    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9774
9775 static rtx
9776 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9777                         rtx varop, int orig_count)
9778 {
9779   enum rtx_code orig_code = code;
9780   rtx orig_varop = varop;
9781   int count;
9782   enum machine_mode mode = result_mode;
9783   enum machine_mode shift_mode, tmode;
9784   unsigned int mode_words
9785     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9786   /* We form (outer_op (code varop count) (outer_const)).  */
9787   enum rtx_code outer_op = UNKNOWN;
9788   HOST_WIDE_INT outer_const = 0;
9789   int complement_p = 0;
9790   rtx new_rtx, x;
9791
9792   /* Make sure and truncate the "natural" shift on the way in.  We don't
9793      want to do this inside the loop as it makes it more difficult to
9794      combine shifts.  */
9795   if (SHIFT_COUNT_TRUNCATED)
9796     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9797
9798   /* If we were given an invalid count, don't do anything except exactly
9799      what was requested.  */
9800
9801   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9802     return NULL_RTX;
9803
9804   count = orig_count;
9805
9806   /* Unless one of the branches of the `if' in this loop does a `continue',
9807      we will `break' the loop after the `if'.  */
9808
9809   while (count != 0)
9810     {
9811       /* If we have an operand of (clobber (const_int 0)), fail.  */
9812       if (GET_CODE (varop) == CLOBBER)
9813         return NULL_RTX;
9814
9815       /* Convert ROTATERT to ROTATE.  */
9816       if (code == ROTATERT)
9817         {
9818           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9819           code = ROTATE;
9820           if (VECTOR_MODE_P (result_mode))
9821             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9822           else
9823             count = bitsize - count;
9824         }
9825
9826       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9827                                          mode, outer_op, outer_const);
9828
9829       /* Handle cases where the count is greater than the size of the mode
9830          minus 1.  For ASHIFT, use the size minus one as the count (this can
9831          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9832          take the count modulo the size.  For other shifts, the result is
9833          zero.
9834
9835          Since these shifts are being produced by the compiler by combining
9836          multiple operations, each of which are defined, we know what the
9837          result is supposed to be.  */
9838
9839       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9840         {
9841           if (code == ASHIFTRT)
9842             count = GET_MODE_PRECISION (shift_mode) - 1;
9843           else if (code == ROTATE || code == ROTATERT)
9844             count %= GET_MODE_PRECISION (shift_mode);
9845           else
9846             {
9847               /* We can't simply return zero because there may be an
9848                  outer op.  */
9849               varop = const0_rtx;
9850               count = 0;
9851               break;
9852             }
9853         }
9854
9855       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9856          here would cause an infinite loop.  */
9857       if (complement_p)
9858         break;
9859
9860       /* An arithmetic right shift of a quantity known to be -1 or 0
9861          is a no-op.  */
9862       if (code == ASHIFTRT
9863           && (num_sign_bit_copies (varop, shift_mode)
9864               == GET_MODE_PRECISION (shift_mode)))
9865         {
9866           count = 0;
9867           break;
9868         }
9869
9870       /* If we are doing an arithmetic right shift and discarding all but
9871          the sign bit copies, this is equivalent to doing a shift by the
9872          bitsize minus one.  Convert it into that shift because it will often
9873          allow other simplifications.  */
9874
9875       if (code == ASHIFTRT
9876           && (count + num_sign_bit_copies (varop, shift_mode)
9877               >= GET_MODE_PRECISION (shift_mode)))
9878         count = GET_MODE_PRECISION (shift_mode) - 1;
9879
9880       /* We simplify the tests below and elsewhere by converting
9881          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9882          `make_compound_operation' will convert it to an ASHIFTRT for
9883          those machines (such as VAX) that don't have an LSHIFTRT.  */
9884       if (code == ASHIFTRT
9885           && val_signbit_known_clear_p (shift_mode,
9886                                         nonzero_bits (varop, shift_mode)))
9887         code = LSHIFTRT;
9888
9889       if (((code == LSHIFTRT
9890             && HWI_COMPUTABLE_MODE_P (shift_mode)
9891             && !(nonzero_bits (varop, shift_mode) >> count))
9892            || (code == ASHIFT
9893                && HWI_COMPUTABLE_MODE_P (shift_mode)
9894                && !((nonzero_bits (varop, shift_mode) << count)
9895                     & GET_MODE_MASK (shift_mode))))
9896           && !side_effects_p (varop))
9897         varop = const0_rtx;
9898
9899       switch (GET_CODE (varop))
9900         {
9901         case SIGN_EXTEND:
9902         case ZERO_EXTEND:
9903         case SIGN_EXTRACT:
9904         case ZERO_EXTRACT:
9905           new_rtx = expand_compound_operation (varop);
9906           if (new_rtx != varop)
9907             {
9908               varop = new_rtx;
9909               continue;
9910             }
9911           break;
9912
9913         case MEM:
9914           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9915              minus the width of a smaller mode, we can do this with a
9916              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9917           if ((code == ASHIFTRT || code == LSHIFTRT)
9918               && ! mode_dependent_address_p (XEXP (varop, 0),
9919                                              MEM_ADDR_SPACE (varop))
9920               && ! MEM_VOLATILE_P (varop)
9921               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9922                                          MODE_INT, 1)) != BLKmode)
9923             {
9924               new_rtx = adjust_address_nv (varop, tmode,
9925                                        BYTES_BIG_ENDIAN ? 0
9926                                        : count / BITS_PER_UNIT);
9927
9928               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9929                                      : ZERO_EXTEND, mode, new_rtx);
9930               count = 0;
9931               continue;
9932             }
9933           break;
9934
9935         case SUBREG:
9936           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9937              the same number of words as what we've seen so far.  Then store
9938              the widest mode in MODE.  */
9939           if (subreg_lowpart_p (varop)
9940               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9941                   > GET_MODE_SIZE (GET_MODE (varop)))
9942               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9943                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9944                  == mode_words
9945               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9946               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9947             {
9948               varop = SUBREG_REG (varop);
9949               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9950                 mode = GET_MODE (varop);
9951               continue;
9952             }
9953           break;
9954
9955         case MULT:
9956           /* Some machines use MULT instead of ASHIFT because MULT
9957              is cheaper.  But it is still better on those machines to
9958              merge two shifts into one.  */
9959           if (CONST_INT_P (XEXP (varop, 1))
9960               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9961             {
9962               varop
9963                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9964                                        XEXP (varop, 0),
9965                                        GEN_INT (exact_log2 (
9966                                                 UINTVAL (XEXP (varop, 1)))));
9967               continue;
9968             }
9969           break;
9970
9971         case UDIV:
9972           /* Similar, for when divides are cheaper.  */
9973           if (CONST_INT_P (XEXP (varop, 1))
9974               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9975             {
9976               varop
9977                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9978                                        XEXP (varop, 0),
9979                                        GEN_INT (exact_log2 (
9980                                                 UINTVAL (XEXP (varop, 1)))));
9981               continue;
9982             }
9983           break;
9984
9985         case ASHIFTRT:
9986           /* If we are extracting just the sign bit of an arithmetic
9987              right shift, that shift is not needed.  However, the sign
9988              bit of a wider mode may be different from what would be
9989              interpreted as the sign bit in a narrower mode, so, if
9990              the result is narrower, don't discard the shift.  */
9991           if (code == LSHIFTRT
9992               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9993               && (GET_MODE_BITSIZE (result_mode)
9994                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9995             {
9996               varop = XEXP (varop, 0);
9997               continue;
9998             }
9999
10000           /* ... fall through ...  */
10001
10002         case LSHIFTRT:
10003         case ASHIFT:
10004         case ROTATE:
10005           /* Here we have two nested shifts.  The result is usually the
10006              AND of a new shift with a mask.  We compute the result below.  */
10007           if (CONST_INT_P (XEXP (varop, 1))
10008               && INTVAL (XEXP (varop, 1)) >= 0
10009               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10010               && HWI_COMPUTABLE_MODE_P (result_mode)
10011               && HWI_COMPUTABLE_MODE_P (mode)
10012               && !VECTOR_MODE_P (result_mode))
10013             {
10014               enum rtx_code first_code = GET_CODE (varop);
10015               unsigned int first_count = INTVAL (XEXP (varop, 1));
10016               unsigned HOST_WIDE_INT mask;
10017               rtx mask_rtx;
10018
10019               /* We have one common special case.  We can't do any merging if
10020                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10021                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10022                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10023                  we can convert it to
10024                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10025                  This simplifies certain SIGN_EXTEND operations.  */
10026               if (code == ASHIFT && first_code == ASHIFTRT
10027                   && count == (GET_MODE_PRECISION (result_mode)
10028                                - GET_MODE_PRECISION (GET_MODE (varop))))
10029                 {
10030                   /* C3 has the low-order C1 bits zero.  */
10031
10032                   mask = GET_MODE_MASK (mode)
10033                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10034
10035                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10036                                                   XEXP (varop, 0), mask);
10037                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10038                                                 varop, count);
10039                   count = first_count;
10040                   code = ASHIFTRT;
10041                   continue;
10042                 }
10043
10044               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10045                  than C1 high-order bits equal to the sign bit, we can convert
10046                  this to either an ASHIFT or an ASHIFTRT depending on the
10047                  two counts.
10048
10049                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10050
10051               if (code == ASHIFTRT && first_code == ASHIFT
10052                   && GET_MODE (varop) == shift_mode
10053                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10054                       > first_count))
10055                 {
10056                   varop = XEXP (varop, 0);
10057                   count -= first_count;
10058                   if (count < 0)
10059                     {
10060                       count = -count;
10061                       code = ASHIFT;
10062                     }
10063
10064                   continue;
10065                 }
10066
10067               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10068                  we can only do this if FIRST_CODE is also ASHIFTRT.
10069
10070                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10071                  ASHIFTRT.
10072
10073                  If the mode of this shift is not the mode of the outer shift,
10074                  we can't do this if either shift is a right shift or ROTATE.
10075
10076                  Finally, we can't do any of these if the mode is too wide
10077                  unless the codes are the same.
10078
10079                  Handle the case where the shift codes are the same
10080                  first.  */
10081
10082               if (code == first_code)
10083                 {
10084                   if (GET_MODE (varop) != result_mode
10085                       && (code == ASHIFTRT || code == LSHIFTRT
10086                           || code == ROTATE))
10087                     break;
10088
10089                   count += first_count;
10090                   varop = XEXP (varop, 0);
10091                   continue;
10092                 }
10093
10094               if (code == ASHIFTRT
10095                   || (code == ROTATE && first_code == ASHIFTRT)
10096                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10097                   || (GET_MODE (varop) != result_mode
10098                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10099                           || first_code == ROTATE
10100                           || code == ROTATE)))
10101                 break;
10102
10103               /* To compute the mask to apply after the shift, shift the
10104                  nonzero bits of the inner shift the same way the
10105                  outer shift will.  */
10106
10107               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10108                                        result_mode);
10109
10110               mask_rtx
10111                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10112                                                    GEN_INT (count));
10113
10114               /* Give up if we can't compute an outer operation to use.  */
10115               if (mask_rtx == 0
10116                   || !CONST_INT_P (mask_rtx)
10117                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10118                                         INTVAL (mask_rtx),
10119                                         result_mode, &complement_p))
10120                 break;
10121
10122               /* If the shifts are in the same direction, we add the
10123                  counts.  Otherwise, we subtract them.  */
10124               if ((code == ASHIFTRT || code == LSHIFTRT)
10125                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10126                 count += first_count;
10127               else
10128                 count -= first_count;
10129
10130               /* If COUNT is positive, the new shift is usually CODE,
10131                  except for the two exceptions below, in which case it is
10132                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10133                  always be used  */
10134               if (count > 0
10135                   && ((first_code == ROTATE && code == ASHIFT)
10136                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10137                 code = first_code;
10138               else if (count < 0)
10139                 code = first_code, count = -count;
10140
10141               varop = XEXP (varop, 0);
10142               continue;
10143             }
10144
10145           /* If we have (A << B << C) for any shift, we can convert this to
10146              (A << C << B).  This wins if A is a constant.  Only try this if
10147              B is not a constant.  */
10148
10149           else if (GET_CODE (varop) == code
10150                    && CONST_INT_P (XEXP (varop, 0))
10151                    && !CONST_INT_P (XEXP (varop, 1)))
10152             {
10153               rtx new_rtx = simplify_const_binary_operation (code, mode,
10154                                                          XEXP (varop, 0),
10155                                                          GEN_INT (count));
10156               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10157               count = 0;
10158               continue;
10159             }
10160           break;
10161
10162         case NOT:
10163           if (VECTOR_MODE_P (mode))
10164             break;
10165
10166           /* Make this fit the case below.  */
10167           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10168           continue;
10169
10170         case IOR:
10171         case AND:
10172         case XOR:
10173           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10174              with C the size of VAROP - 1 and the shift is logical if
10175              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10176              we have an (le X 0) operation.   If we have an arithmetic shift
10177              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10178              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10179
10180           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10181               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10182               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10183               && (code == LSHIFTRT || code == ASHIFTRT)
10184               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10185               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10186             {
10187               count = 0;
10188               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10189                                   const0_rtx);
10190
10191               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10192                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10193
10194               continue;
10195             }
10196
10197           /* If we have (shift (logical)), move the logical to the outside
10198              to allow it to possibly combine with another logical and the
10199              shift to combine with another shift.  This also canonicalizes to
10200              what a ZERO_EXTRACT looks like.  Also, some machines have
10201              (and (shift)) insns.  */
10202
10203           if (CONST_INT_P (XEXP (varop, 1))
10204               /* We can't do this if we have (ashiftrt (xor))  and the
10205                  constant has its sign bit set in shift_mode.  */
10206               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10207                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10208                                               shift_mode))
10209               && (new_rtx = simplify_const_binary_operation
10210                   (code, result_mode,
10211                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10212                    GEN_INT (count))) != 0
10213               && CONST_INT_P (new_rtx)
10214               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10215                                   INTVAL (new_rtx), result_mode, &complement_p))
10216             {
10217               varop = XEXP (varop, 0);
10218               continue;
10219             }
10220
10221           /* If we can't do that, try to simplify the shift in each arm of the
10222              logical expression, make a new logical expression, and apply
10223              the inverse distributive law.  This also can't be done
10224              for some (ashiftrt (xor)).  */
10225           if (CONST_INT_P (XEXP (varop, 1))
10226              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10227                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10228                                              shift_mode)))
10229             {
10230               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10231                                               XEXP (varop, 0), count);
10232               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10233                                               XEXP (varop, 1), count);
10234
10235               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10236                                            lhs, rhs);
10237               varop = apply_distributive_law (varop);
10238
10239               count = 0;
10240               continue;
10241             }
10242           break;
10243
10244         case EQ:
10245           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10246              says that the sign bit can be tested, FOO has mode MODE, C is
10247              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10248              that may be nonzero.  */
10249           if (code == LSHIFTRT
10250               && XEXP (varop, 1) == const0_rtx
10251               && GET_MODE (XEXP (varop, 0)) == result_mode
10252               && count == (GET_MODE_PRECISION (result_mode) - 1)
10253               && HWI_COMPUTABLE_MODE_P (result_mode)
10254               && STORE_FLAG_VALUE == -1
10255               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10256               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10257                                   &complement_p))
10258             {
10259               varop = XEXP (varop, 0);
10260               count = 0;
10261               continue;
10262             }
10263           break;
10264
10265         case NEG:
10266           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10267              than the number of bits in the mode is equivalent to A.  */
10268           if (code == LSHIFTRT
10269               && count == (GET_MODE_PRECISION (result_mode) - 1)
10270               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10271             {
10272               varop = XEXP (varop, 0);
10273               count = 0;
10274               continue;
10275             }
10276
10277           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10278              NEG outside to allow shifts to combine.  */
10279           if (code == ASHIFT
10280               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10281                                   &complement_p))
10282             {
10283               varop = XEXP (varop, 0);
10284               continue;
10285             }
10286           break;
10287
10288         case PLUS:
10289           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10290              is one less than the number of bits in the mode is
10291              equivalent to (xor A 1).  */
10292           if (code == LSHIFTRT
10293               && count == (GET_MODE_PRECISION (result_mode) - 1)
10294               && XEXP (varop, 1) == constm1_rtx
10295               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10296               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10297                                   &complement_p))
10298             {
10299               count = 0;
10300               varop = XEXP (varop, 0);
10301               continue;
10302             }
10303
10304           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10305              that might be nonzero in BAR are those being shifted out and those
10306              bits are known zero in FOO, we can replace the PLUS with FOO.
10307              Similarly in the other operand order.  This code occurs when
10308              we are computing the size of a variable-size array.  */
10309
10310           if ((code == ASHIFTRT || code == LSHIFTRT)
10311               && count < HOST_BITS_PER_WIDE_INT
10312               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10313               && (nonzero_bits (XEXP (varop, 1), result_mode)
10314                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10315             {
10316               varop = XEXP (varop, 0);
10317               continue;
10318             }
10319           else if ((code == ASHIFTRT || code == LSHIFTRT)
10320                    && count < HOST_BITS_PER_WIDE_INT
10321                    && HWI_COMPUTABLE_MODE_P (result_mode)
10322                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10323                             >> count)
10324                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10325                             & nonzero_bits (XEXP (varop, 1),
10326                                                  result_mode)))
10327             {
10328               varop = XEXP (varop, 1);
10329               continue;
10330             }
10331
10332           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10333           if (code == ASHIFT
10334               && CONST_INT_P (XEXP (varop, 1))
10335               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10336                                                          XEXP (varop, 1),
10337                                                          GEN_INT (count))) != 0
10338               && CONST_INT_P (new_rtx)
10339               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10340                                   INTVAL (new_rtx), result_mode, &complement_p))
10341             {
10342               varop = XEXP (varop, 0);
10343               continue;
10344             }
10345
10346           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10347              signbit', and attempt to change the PLUS to an XOR and move it to
10348              the outer operation as is done above in the AND/IOR/XOR case
10349              leg for shift(logical). See details in logical handling above
10350              for reasoning in doing so.  */
10351           if (code == LSHIFTRT
10352               && CONST_INT_P (XEXP (varop, 1))
10353               && mode_signbit_p (result_mode, XEXP (varop, 1))
10354               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10355                                                          XEXP (varop, 1),
10356                                                          GEN_INT (count))) != 0
10357               && CONST_INT_P (new_rtx)
10358               && merge_outer_ops (&outer_op, &outer_const, XOR,
10359                                   INTVAL (new_rtx), result_mode, &complement_p))
10360             {
10361               varop = XEXP (varop, 0);
10362               continue;
10363             }
10364
10365           break;
10366
10367         case MINUS:
10368           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10369              with C the size of VAROP - 1 and the shift is logical if
10370              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10371              we have a (gt X 0) operation.  If the shift is arithmetic with
10372              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10373              we have a (neg (gt X 0)) operation.  */
10374
10375           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10376               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10377               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10378               && (code == LSHIFTRT || code == ASHIFTRT)
10379               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10380               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10381               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10382             {
10383               count = 0;
10384               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10385                                   const0_rtx);
10386
10387               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10388                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10389
10390               continue;
10391             }
10392           break;
10393
10394         case TRUNCATE:
10395           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10396              if the truncate does not affect the value.  */
10397           if (code == LSHIFTRT
10398               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10399               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10400               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10401                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10402                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10403             {
10404               rtx varop_inner = XEXP (varop, 0);
10405
10406               varop_inner
10407                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10408                                     XEXP (varop_inner, 0),
10409                                     GEN_INT
10410                                     (count + INTVAL (XEXP (varop_inner, 1))));
10411               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10412               count = 0;
10413               continue;
10414             }
10415           break;
10416
10417         default:
10418           break;
10419         }
10420
10421       break;
10422     }
10423
10424   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10425                                      outer_op, outer_const);
10426
10427   /* We have now finished analyzing the shift.  The result should be
10428      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10429      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10430      to the result of the shift.  OUTER_CONST is the relevant constant,
10431      but we must turn off all bits turned off in the shift.  */
10432
10433   if (outer_op == UNKNOWN
10434       && orig_code == code && orig_count == count
10435       && varop == orig_varop
10436       && shift_mode == GET_MODE (varop))
10437     return NULL_RTX;
10438
10439   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10440   varop = gen_lowpart (shift_mode, varop);
10441   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10442     return NULL_RTX;
10443
10444   /* If we have an outer operation and we just made a shift, it is
10445      possible that we could have simplified the shift were it not
10446      for the outer operation.  So try to do the simplification
10447      recursively.  */
10448
10449   if (outer_op != UNKNOWN)
10450     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10451   else
10452     x = NULL_RTX;
10453
10454   if (x == NULL_RTX)
10455     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10456
10457   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10458      turn off all the bits that the shift would have turned off.  */
10459   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10460     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10461                                 GET_MODE_MASK (result_mode) >> orig_count);
10462
10463   /* Do the remainder of the processing in RESULT_MODE.  */
10464   x = gen_lowpart_or_truncate (result_mode, x);
10465
10466   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10467      operation.  */
10468   if (complement_p)
10469     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10470
10471   if (outer_op != UNKNOWN)
10472     {
10473       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10474           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10475         outer_const = trunc_int_for_mode (outer_const, result_mode);
10476
10477       if (outer_op == AND)
10478         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10479       else if (outer_op == SET)
10480         {
10481           /* This means that we have determined that the result is
10482              equivalent to a constant.  This should be rare.  */
10483           if (!side_effects_p (x))
10484             x = GEN_INT (outer_const);
10485         }
10486       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10487         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10488       else
10489         x = simplify_gen_binary (outer_op, result_mode, x,
10490                                  GEN_INT (outer_const));
10491     }
10492
10493   return x;
10494 }
10495
10496 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10497    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10498    return X or, if it is NULL, synthesize the expression with
10499    simplify_gen_binary.  Otherwise, return a simplified value.
10500
10501    The shift is normally computed in the widest mode we find in VAROP, as
10502    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10503    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10504
10505 static rtx
10506 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10507                       rtx varop, int count)
10508 {
10509   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10510   if (tem)
10511     return tem;
10512
10513   if (!x)
10514     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10515   if (GET_MODE (x) != result_mode)
10516     x = gen_lowpart (result_mode, x);
10517   return x;
10518 }
10519
10520 \f
10521 /* Like recog, but we receive the address of a pointer to a new pattern.
10522    We try to match the rtx that the pointer points to.
10523    If that fails, we may try to modify or replace the pattern,
10524    storing the replacement into the same pointer object.
10525
10526    Modifications include deletion or addition of CLOBBERs.
10527
10528    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10529    the CLOBBERs are placed.
10530
10531    The value is the final insn code from the pattern ultimately matched,
10532    or -1.  */
10533
10534 static int
10535 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10536 {
10537   rtx pat = *pnewpat;
10538   rtx pat_without_clobbers;
10539   int insn_code_number;
10540   int num_clobbers_to_add = 0;
10541   int i;
10542   rtx notes = NULL_RTX;
10543   rtx old_notes, old_pat;
10544   int old_icode;
10545
10546   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10547      we use to indicate that something didn't match.  If we find such a
10548      thing, force rejection.  */
10549   if (GET_CODE (pat) == PARALLEL)
10550     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10551       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10552           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10553         return -1;
10554
10555   old_pat = PATTERN (insn);
10556   old_notes = REG_NOTES (insn);
10557   PATTERN (insn) = pat;
10558   REG_NOTES (insn) = NULL_RTX;
10559
10560   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10561   if (dump_file && (dump_flags & TDF_DETAILS))
10562     {
10563       if (insn_code_number < 0)
10564         fputs ("Failed to match this instruction:\n", dump_file);
10565       else
10566         fputs ("Successfully matched this instruction:\n", dump_file);
10567       print_rtl_single (dump_file, pat);
10568     }
10569
10570   /* If it isn't, there is the possibility that we previously had an insn
10571      that clobbered some register as a side effect, but the combined
10572      insn doesn't need to do that.  So try once more without the clobbers
10573      unless this represents an ASM insn.  */
10574
10575   if (insn_code_number < 0 && ! check_asm_operands (pat)
10576       && GET_CODE (pat) == PARALLEL)
10577     {
10578       int pos;
10579
10580       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10581         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10582           {
10583             if (i != pos)
10584               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10585             pos++;
10586           }
10587
10588       SUBST_INT (XVECLEN (pat, 0), pos);
10589
10590       if (pos == 1)
10591         pat = XVECEXP (pat, 0, 0);
10592
10593       PATTERN (insn) = pat;
10594       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10595       if (dump_file && (dump_flags & TDF_DETAILS))
10596         {
10597           if (insn_code_number < 0)
10598             fputs ("Failed to match this instruction:\n", dump_file);
10599           else
10600             fputs ("Successfully matched this instruction:\n", dump_file);
10601           print_rtl_single (dump_file, pat);
10602         }
10603     }
10604
10605   pat_without_clobbers = pat;
10606
10607   PATTERN (insn) = old_pat;
10608   REG_NOTES (insn) = old_notes;
10609
10610   /* Recognize all noop sets, these will be killed by followup pass.  */
10611   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10612     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10613
10614   /* If we had any clobbers to add, make a new pattern than contains
10615      them.  Then check to make sure that all of them are dead.  */
10616   if (num_clobbers_to_add)
10617     {
10618       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10619                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10620                                                   ? (XVECLEN (pat, 0)
10621                                                      + num_clobbers_to_add)
10622                                                   : num_clobbers_to_add + 1));
10623
10624       if (GET_CODE (pat) == PARALLEL)
10625         for (i = 0; i < XVECLEN (pat, 0); i++)
10626           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10627       else
10628         XVECEXP (newpat, 0, 0) = pat;
10629
10630       add_clobbers (newpat, insn_code_number);
10631
10632       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10633            i < XVECLEN (newpat, 0); i++)
10634         {
10635           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10636               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10637             return -1;
10638           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10639             {
10640               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10641               notes = alloc_reg_note (REG_UNUSED,
10642                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10643             }
10644         }
10645       pat = newpat;
10646     }
10647
10648   if (insn_code_number >= 0
10649       && insn_code_number != NOOP_MOVE_INSN_CODE)
10650     {
10651       old_pat = PATTERN (insn);
10652       old_notes = REG_NOTES (insn);
10653       old_icode = INSN_CODE (insn);
10654       PATTERN (insn) = pat;
10655       REG_NOTES (insn) = notes;
10656
10657       /* Allow targets to reject combined insn.  */
10658       if (!targetm.legitimate_combined_insn (insn))
10659         {
10660           if (dump_file && (dump_flags & TDF_DETAILS))
10661             fputs ("Instruction not appropriate for target.",
10662                    dump_file);
10663
10664           /* Callers expect recog_for_combine to strip
10665              clobbers from the pattern on failure.  */
10666           pat = pat_without_clobbers;
10667           notes = NULL_RTX;
10668
10669           insn_code_number = -1;
10670         }
10671
10672       PATTERN (insn) = old_pat;
10673       REG_NOTES (insn) = old_notes;
10674       INSN_CODE (insn) = old_icode;
10675     }
10676
10677   *pnewpat = pat;
10678   *pnotes = notes;
10679
10680   return insn_code_number;
10681 }
10682 \f
10683 /* Like gen_lowpart_general but for use by combine.  In combine it
10684    is not possible to create any new pseudoregs.  However, it is
10685    safe to create invalid memory addresses, because combine will
10686    try to recognize them and all they will do is make the combine
10687    attempt fail.
10688
10689    If for some reason this cannot do its job, an rtx
10690    (clobber (const_int 0)) is returned.
10691    An insn containing that will not be recognized.  */
10692
10693 static rtx
10694 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10695 {
10696   enum machine_mode imode = GET_MODE (x);
10697   unsigned int osize = GET_MODE_SIZE (omode);
10698   unsigned int isize = GET_MODE_SIZE (imode);
10699   rtx result;
10700
10701   if (omode == imode)
10702     return x;
10703
10704   /* We can only support MODE being wider than a word if X is a
10705      constant integer or has a mode the same size.  */
10706   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10707       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10708     goto fail;
10709
10710   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10711      won't know what to do.  So we will strip off the SUBREG here and
10712      process normally.  */
10713   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10714     {
10715       x = SUBREG_REG (x);
10716
10717       /* For use in case we fall down into the address adjustments
10718          further below, we need to adjust the known mode and size of
10719          x; imode and isize, since we just adjusted x.  */
10720       imode = GET_MODE (x);
10721
10722       if (imode == omode)
10723         return x;
10724
10725       isize = GET_MODE_SIZE (imode);
10726     }
10727
10728   result = gen_lowpart_common (omode, x);
10729
10730   if (result)
10731     return result;
10732
10733   if (MEM_P (x))
10734     {
10735       int offset = 0;
10736
10737       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10738          address.  */
10739       if (MEM_VOLATILE_P (x)
10740           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10741         goto fail;
10742
10743       /* If we want to refer to something bigger than the original memref,
10744          generate a paradoxical subreg instead.  That will force a reload
10745          of the original memref X.  */
10746       if (isize < osize)
10747         return gen_rtx_SUBREG (omode, x, 0);
10748
10749       if (WORDS_BIG_ENDIAN)
10750         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10751
10752       /* Adjust the address so that the address-after-the-data is
10753          unchanged.  */
10754       if (BYTES_BIG_ENDIAN)
10755         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10756
10757       return adjust_address_nv (x, omode, offset);
10758     }
10759
10760   /* If X is a comparison operator, rewrite it in a new mode.  This
10761      probably won't match, but may allow further simplifications.  */
10762   else if (COMPARISON_P (x))
10763     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10764
10765   /* If we couldn't simplify X any other way, just enclose it in a
10766      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10767      include an explicit SUBREG or we may simplify it further in combine.  */
10768   else
10769     {
10770       int offset = 0;
10771       rtx res;
10772
10773       offset = subreg_lowpart_offset (omode, imode);
10774       if (imode == VOIDmode)
10775         {
10776           imode = int_mode_for_mode (omode);
10777           x = gen_lowpart_common (imode, x);
10778           if (x == NULL)
10779             goto fail;
10780         }
10781       res = simplify_gen_subreg (omode, x, imode, offset);
10782       if (res)
10783         return res;
10784     }
10785
10786  fail:
10787   return gen_rtx_CLOBBER (omode, const0_rtx);
10788 }
10789 \f
10790 /* Try to simplify a comparison between OP0 and a constant OP1,
10791    where CODE is the comparison code that will be tested, into a
10792    (CODE OP0 const0_rtx) form.
10793
10794    The result is a possibly different comparison code to use.
10795    *POP1 may be updated.  */
10796
10797 static enum rtx_code
10798 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10799 {
10800   enum machine_mode mode = GET_MODE (op0);
10801   unsigned int mode_width = GET_MODE_PRECISION (mode);
10802   HOST_WIDE_INT const_op = INTVAL (*pop1);
10803
10804   /* Get the constant we are comparing against and turn off all bits
10805      not on in our mode.  */
10806   if (mode != VOIDmode)
10807     const_op = trunc_int_for_mode (const_op, mode);
10808
10809   /* If we are comparing against a constant power of two and the value
10810      being compared can only have that single bit nonzero (e.g., it was
10811      `and'ed with that bit), we can replace this with a comparison
10812      with zero.  */
10813   if (const_op
10814       && (code == EQ || code == NE || code == GE || code == GEU
10815           || code == LT || code == LTU)
10816       && mode_width <= HOST_BITS_PER_WIDE_INT
10817       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10818       && (nonzero_bits (op0, mode)
10819           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10820     {
10821       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10822       const_op = 0;
10823     }
10824
10825   /* Similarly, if we are comparing a value known to be either -1 or
10826      0 with -1, change it to the opposite comparison against zero.  */
10827   if (const_op == -1
10828       && (code == EQ || code == NE || code == GT || code == LE
10829           || code == GEU || code == LTU)
10830       && num_sign_bit_copies (op0, mode) == mode_width)
10831     {
10832       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10833       const_op = 0;
10834     }
10835
10836   /* Do some canonicalizations based on the comparison code.  We prefer
10837      comparisons against zero and then prefer equality comparisons.
10838      If we can reduce the size of a constant, we will do that too.  */
10839   switch (code)
10840     {
10841     case LT:
10842       /* < C is equivalent to <= (C - 1) */
10843       if (const_op > 0)
10844         {
10845           const_op -= 1;
10846           code = LE;
10847           /* ... fall through to LE case below.  */
10848         }
10849       else
10850         break;
10851
10852     case LE:
10853       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10854       if (const_op < 0)
10855         {
10856           const_op += 1;
10857           code = LT;
10858         }
10859
10860       /* If we are doing a <= 0 comparison on a value known to have
10861          a zero sign bit, we can replace this with == 0.  */
10862       else if (const_op == 0
10863                && mode_width <= HOST_BITS_PER_WIDE_INT
10864                && (nonzero_bits (op0, mode)
10865                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10866                == 0)
10867         code = EQ;
10868       break;
10869
10870     case GE:
10871       /* >= C is equivalent to > (C - 1).  */
10872       if (const_op > 0)
10873         {
10874           const_op -= 1;
10875           code = GT;
10876           /* ... fall through to GT below.  */
10877         }
10878       else
10879         break;
10880
10881     case GT:
10882       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10883       if (const_op < 0)
10884         {
10885           const_op += 1;
10886           code = GE;
10887         }
10888
10889       /* If we are doing a > 0 comparison on a value known to have
10890          a zero sign bit, we can replace this with != 0.  */
10891       else if (const_op == 0
10892                && mode_width <= HOST_BITS_PER_WIDE_INT
10893                && (nonzero_bits (op0, mode)
10894                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10895                == 0)
10896         code = NE;
10897       break;
10898
10899     case LTU:
10900       /* < C is equivalent to <= (C - 1).  */
10901       if (const_op > 0)
10902         {
10903           const_op -= 1;
10904           code = LEU;
10905           /* ... fall through ...  */
10906         }
10907       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10908       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10909                && (unsigned HOST_WIDE_INT) const_op
10910                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10911         {
10912           const_op = 0;
10913           code = GE;
10914           break;
10915         }
10916       else
10917         break;
10918
10919     case LEU:
10920       /* unsigned <= 0 is equivalent to == 0 */
10921       if (const_op == 0)
10922         code = EQ;
10923       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10924       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10925                && (unsigned HOST_WIDE_INT) const_op
10926                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10927         {
10928           const_op = 0;
10929           code = GE;
10930         }
10931       break;
10932
10933     case GEU:
10934       /* >= C is equivalent to > (C - 1).  */
10935       if (const_op > 1)
10936         {
10937           const_op -= 1;
10938           code = GTU;
10939           /* ... fall through ...  */
10940         }
10941
10942       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10943       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10944                && (unsigned HOST_WIDE_INT) const_op
10945                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10946         {
10947           const_op = 0;
10948           code = LT;
10949           break;
10950         }
10951       else
10952         break;
10953
10954     case GTU:
10955       /* unsigned > 0 is equivalent to != 0 */
10956       if (const_op == 0)
10957         code = NE;
10958       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10959       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10960                && (unsigned HOST_WIDE_INT) const_op
10961                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10962         {
10963           const_op = 0;
10964           code = LT;
10965         }
10966       break;
10967
10968     default:
10969       break;
10970     }
10971
10972   *pop1 = GEN_INT (const_op);
10973   return code;
10974 }
10975 \f
10976 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10977    comparison code that will be tested.
10978
10979    The result is a possibly different comparison code to use.  *POP0 and
10980    *POP1 may be updated.
10981
10982    It is possible that we might detect that a comparison is either always
10983    true or always false.  However, we do not perform general constant
10984    folding in combine, so this knowledge isn't useful.  Such tautologies
10985    should have been detected earlier.  Hence we ignore all such cases.  */
10986
10987 static enum rtx_code
10988 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10989 {
10990   rtx op0 = *pop0;
10991   rtx op1 = *pop1;
10992   rtx tem, tem1;
10993   int i;
10994   enum machine_mode mode, tmode;
10995
10996   /* Try a few ways of applying the same transformation to both operands.  */
10997   while (1)
10998     {
10999 #ifndef WORD_REGISTER_OPERATIONS
11000       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11001          so check specially.  */
11002       if (code != GTU && code != GEU && code != LTU && code != LEU
11003           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11004           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11005           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11006           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11007           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11008           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11009               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11010           && CONST_INT_P (XEXP (op0, 1))
11011           && XEXP (op0, 1) == XEXP (op1, 1)
11012           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11013           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11014           && (INTVAL (XEXP (op0, 1))
11015               == (GET_MODE_PRECISION (GET_MODE (op0))
11016                   - (GET_MODE_PRECISION
11017                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11018         {
11019           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11020           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11021         }
11022 #endif
11023
11024       /* If both operands are the same constant shift, see if we can ignore the
11025          shift.  We can if the shift is a rotate or if the bits shifted out of
11026          this shift are known to be zero for both inputs and if the type of
11027          comparison is compatible with the shift.  */
11028       if (GET_CODE (op0) == GET_CODE (op1)
11029           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11030           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11031               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11032                   && (code != GT && code != LT && code != GE && code != LE))
11033               || (GET_CODE (op0) == ASHIFTRT
11034                   && (code != GTU && code != LTU
11035                       && code != GEU && code != LEU)))
11036           && CONST_INT_P (XEXP (op0, 1))
11037           && INTVAL (XEXP (op0, 1)) >= 0
11038           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11039           && XEXP (op0, 1) == XEXP (op1, 1))
11040         {
11041           enum machine_mode mode = GET_MODE (op0);
11042           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11043           int shift_count = INTVAL (XEXP (op0, 1));
11044
11045           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11046             mask &= (mask >> shift_count) << shift_count;
11047           else if (GET_CODE (op0) == ASHIFT)
11048             mask = (mask & (mask << shift_count)) >> shift_count;
11049
11050           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11051               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11052             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11053           else
11054             break;
11055         }
11056
11057       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11058          SUBREGs are of the same mode, and, in both cases, the AND would
11059          be redundant if the comparison was done in the narrower mode,
11060          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11061          and the operand's possibly nonzero bits are 0xffffff01; in that case
11062          if we only care about QImode, we don't need the AND).  This case
11063          occurs if the output mode of an scc insn is not SImode and
11064          STORE_FLAG_VALUE == 1 (e.g., the 386).
11065
11066          Similarly, check for a case where the AND's are ZERO_EXTEND
11067          operations from some narrower mode even though a SUBREG is not
11068          present.  */
11069
11070       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11071                && CONST_INT_P (XEXP (op0, 1))
11072                && CONST_INT_P (XEXP (op1, 1)))
11073         {
11074           rtx inner_op0 = XEXP (op0, 0);
11075           rtx inner_op1 = XEXP (op1, 0);
11076           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11077           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11078           int changed = 0;
11079
11080           if (paradoxical_subreg_p (inner_op0)
11081               && GET_CODE (inner_op1) == SUBREG
11082               && (GET_MODE (SUBREG_REG (inner_op0))
11083                   == GET_MODE (SUBREG_REG (inner_op1)))
11084               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11085                   <= HOST_BITS_PER_WIDE_INT)
11086               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11087                                              GET_MODE (SUBREG_REG (inner_op0)))))
11088               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11089                                              GET_MODE (SUBREG_REG (inner_op1))))))
11090             {
11091               op0 = SUBREG_REG (inner_op0);
11092               op1 = SUBREG_REG (inner_op1);
11093
11094               /* The resulting comparison is always unsigned since we masked
11095                  off the original sign bit.  */
11096               code = unsigned_condition (code);
11097
11098               changed = 1;
11099             }
11100
11101           else if (c0 == c1)
11102             for (tmode = GET_CLASS_NARROWEST_MODE
11103                  (GET_MODE_CLASS (GET_MODE (op0)));
11104                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11105               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11106                 {
11107                   op0 = gen_lowpart (tmode, inner_op0);
11108                   op1 = gen_lowpart (tmode, inner_op1);
11109                   code = unsigned_condition (code);
11110                   changed = 1;
11111                   break;
11112                 }
11113
11114           if (! changed)
11115             break;
11116         }
11117
11118       /* If both operands are NOT, we can strip off the outer operation
11119          and adjust the comparison code for swapped operands; similarly for
11120          NEG, except that this must be an equality comparison.  */
11121       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11122                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11123                    && (code == EQ || code == NE)))
11124         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11125
11126       else
11127         break;
11128     }
11129
11130   /* If the first operand is a constant, swap the operands and adjust the
11131      comparison code appropriately, but don't do this if the second operand
11132      is already a constant integer.  */
11133   if (swap_commutative_operands_p (op0, op1))
11134     {
11135       tem = op0, op0 = op1, op1 = tem;
11136       code = swap_condition (code);
11137     }
11138
11139   /* We now enter a loop during which we will try to simplify the comparison.
11140      For the most part, we only are concerned with comparisons with zero,
11141      but some things may really be comparisons with zero but not start
11142      out looking that way.  */
11143
11144   while (CONST_INT_P (op1))
11145     {
11146       enum machine_mode mode = GET_MODE (op0);
11147       unsigned int mode_width = GET_MODE_PRECISION (mode);
11148       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11149       int equality_comparison_p;
11150       int sign_bit_comparison_p;
11151       int unsigned_comparison_p;
11152       HOST_WIDE_INT const_op;
11153
11154       /* We only want to handle integral modes.  This catches VOIDmode,
11155          CCmode, and the floating-point modes.  An exception is that we
11156          can handle VOIDmode if OP0 is a COMPARE or a comparison
11157          operation.  */
11158
11159       if (GET_MODE_CLASS (mode) != MODE_INT
11160           && ! (mode == VOIDmode
11161                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11162         break;
11163
11164       /* Try to simplify the compare to constant, possibly changing the
11165          comparison op, and/or changing op1 to zero.  */
11166       code = simplify_compare_const (code, op0, &op1);
11167       const_op = INTVAL (op1);
11168
11169       /* Compute some predicates to simplify code below.  */
11170
11171       equality_comparison_p = (code == EQ || code == NE);
11172       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11173       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11174                                || code == GEU);
11175
11176       /* If this is a sign bit comparison and we can do arithmetic in
11177          MODE, say that we will only be needing the sign bit of OP0.  */
11178       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11179         op0 = force_to_mode (op0, mode,
11180                              (unsigned HOST_WIDE_INT) 1
11181                              << (GET_MODE_PRECISION (mode) - 1),
11182                              0);
11183
11184       /* Now try cases based on the opcode of OP0.  If none of the cases
11185          does a "continue", we exit this loop immediately after the
11186          switch.  */
11187
11188       switch (GET_CODE (op0))
11189         {
11190         case ZERO_EXTRACT:
11191           /* If we are extracting a single bit from a variable position in
11192              a constant that has only a single bit set and are comparing it
11193              with zero, we can convert this into an equality comparison
11194              between the position and the location of the single bit.  */
11195           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11196              have already reduced the shift count modulo the word size.  */
11197           if (!SHIFT_COUNT_TRUNCATED
11198               && CONST_INT_P (XEXP (op0, 0))
11199               && XEXP (op0, 1) == const1_rtx
11200               && equality_comparison_p && const_op == 0
11201               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11202             {
11203               if (BITS_BIG_ENDIAN)
11204                 i = BITS_PER_WORD - 1 - i;
11205
11206               op0 = XEXP (op0, 2);
11207               op1 = GEN_INT (i);
11208               const_op = i;
11209
11210               /* Result is nonzero iff shift count is equal to I.  */
11211               code = reverse_condition (code);
11212               continue;
11213             }
11214
11215           /* ... fall through ...  */
11216
11217         case SIGN_EXTRACT:
11218           tem = expand_compound_operation (op0);
11219           if (tem != op0)
11220             {
11221               op0 = tem;
11222               continue;
11223             }
11224           break;
11225
11226         case NOT:
11227           /* If testing for equality, we can take the NOT of the constant.  */
11228           if (equality_comparison_p
11229               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11230             {
11231               op0 = XEXP (op0, 0);
11232               op1 = tem;
11233               continue;
11234             }
11235
11236           /* If just looking at the sign bit, reverse the sense of the
11237              comparison.  */
11238           if (sign_bit_comparison_p)
11239             {
11240               op0 = XEXP (op0, 0);
11241               code = (code == GE ? LT : GE);
11242               continue;
11243             }
11244           break;
11245
11246         case NEG:
11247           /* If testing for equality, we can take the NEG of the constant.  */
11248           if (equality_comparison_p
11249               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11250             {
11251               op0 = XEXP (op0, 0);
11252               op1 = tem;
11253               continue;
11254             }
11255
11256           /* The remaining cases only apply to comparisons with zero.  */
11257           if (const_op != 0)
11258             break;
11259
11260           /* When X is ABS or is known positive,
11261              (neg X) is < 0 if and only if X != 0.  */
11262
11263           if (sign_bit_comparison_p
11264               && (GET_CODE (XEXP (op0, 0)) == ABS
11265                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11266                       && (nonzero_bits (XEXP (op0, 0), mode)
11267                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11268                          == 0)))
11269             {
11270               op0 = XEXP (op0, 0);
11271               code = (code == LT ? NE : EQ);
11272               continue;
11273             }
11274
11275           /* If we have NEG of something whose two high-order bits are the
11276              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11277           if (num_sign_bit_copies (op0, mode) >= 2)
11278             {
11279               op0 = XEXP (op0, 0);
11280               code = swap_condition (code);
11281               continue;
11282             }
11283           break;
11284
11285         case ROTATE:
11286           /* If we are testing equality and our count is a constant, we
11287              can perform the inverse operation on our RHS.  */
11288           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11289               && (tem = simplify_binary_operation (ROTATERT, mode,
11290                                                    op1, XEXP (op0, 1))) != 0)
11291             {
11292               op0 = XEXP (op0, 0);
11293               op1 = tem;
11294               continue;
11295             }
11296
11297           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11298              a particular bit.  Convert it to an AND of a constant of that
11299              bit.  This will be converted into a ZERO_EXTRACT.  */
11300           if (const_op == 0 && sign_bit_comparison_p
11301               && CONST_INT_P (XEXP (op0, 1))
11302               && mode_width <= HOST_BITS_PER_WIDE_INT)
11303             {
11304               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11305                                             ((unsigned HOST_WIDE_INT) 1
11306                                              << (mode_width - 1
11307                                                  - INTVAL (XEXP (op0, 1)))));
11308               code = (code == LT ? NE : EQ);
11309               continue;
11310             }
11311
11312           /* Fall through.  */
11313
11314         case ABS:
11315           /* ABS is ignorable inside an equality comparison with zero.  */
11316           if (const_op == 0 && equality_comparison_p)
11317             {
11318               op0 = XEXP (op0, 0);
11319               continue;
11320             }
11321           break;
11322
11323         case SIGN_EXTEND:
11324           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11325              (compare FOO CONST) if CONST fits in FOO's mode and we
11326              are either testing inequality or have an unsigned
11327              comparison with ZERO_EXTEND or a signed comparison with
11328              SIGN_EXTEND.  But don't do it if we don't have a compare
11329              insn of the given mode, since we'd have to revert it
11330              later on, and then we wouldn't know whether to sign- or
11331              zero-extend.  */
11332           mode = GET_MODE (XEXP (op0, 0));
11333           if (GET_MODE_CLASS (mode) == MODE_INT
11334               && ! unsigned_comparison_p
11335               && HWI_COMPUTABLE_MODE_P (mode)
11336               && trunc_int_for_mode (const_op, mode) == const_op
11337               && have_insn_for (COMPARE, mode))
11338             {
11339               op0 = XEXP (op0, 0);
11340               continue;
11341             }
11342           break;
11343
11344         case SUBREG:
11345           /* Check for the case where we are comparing A - C1 with C2, that is
11346
11347                (subreg:MODE (plus (A) (-C1))) op (C2)
11348
11349              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11350              comparison in the wider mode.  One of the following two conditions
11351              must be true in order for this to be valid:
11352
11353                1. The mode extension results in the same bit pattern being added
11354                   on both sides and the comparison is equality or unsigned.  As
11355                   C2 has been truncated to fit in MODE, the pattern can only be
11356                   all 0s or all 1s.
11357
11358                2. The mode extension results in the sign bit being copied on
11359                   each side.
11360
11361              The difficulty here is that we have predicates for A but not for
11362              (A - C1) so we need to check that C1 is within proper bounds so
11363              as to perturbate A as little as possible.  */
11364
11365           if (mode_width <= HOST_BITS_PER_WIDE_INT
11366               && subreg_lowpart_p (op0)
11367               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11368               && GET_CODE (SUBREG_REG (op0)) == PLUS
11369               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11370             {
11371               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11372               rtx a = XEXP (SUBREG_REG (op0), 0);
11373               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11374
11375               if ((c1 > 0
11376                    && (unsigned HOST_WIDE_INT) c1
11377                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11378                    && (equality_comparison_p || unsigned_comparison_p)
11379                    /* (A - C1) zero-extends if it is positive and sign-extends
11380                       if it is negative, C2 both zero- and sign-extends.  */
11381                    && ((0 == (nonzero_bits (a, inner_mode)
11382                               & ~GET_MODE_MASK (mode))
11383                         && const_op >= 0)
11384                        /* (A - C1) sign-extends if it is positive and 1-extends
11385                           if it is negative, C2 both sign- and 1-extends.  */
11386                        || (num_sign_bit_copies (a, inner_mode)
11387                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11388                                              - mode_width)
11389                            && const_op < 0)))
11390                   || ((unsigned HOST_WIDE_INT) c1
11391                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11392                       /* (A - C1) always sign-extends, like C2.  */
11393                       && num_sign_bit_copies (a, inner_mode)
11394                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11395                                            - (mode_width - 1))))
11396                 {
11397                   op0 = SUBREG_REG (op0);
11398                   continue;
11399                 }
11400             }
11401
11402           /* If the inner mode is narrower and we are extracting the low part,
11403              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11404           if (subreg_lowpart_p (op0)
11405               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11406             /* Fall through */ ;
11407           else
11408             break;
11409
11410           /* ... fall through ...  */
11411
11412         case ZERO_EXTEND:
11413           mode = GET_MODE (XEXP (op0, 0));
11414           if (GET_MODE_CLASS (mode) == MODE_INT
11415               && (unsigned_comparison_p || equality_comparison_p)
11416               && HWI_COMPUTABLE_MODE_P (mode)
11417               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11418               && const_op >= 0
11419               && have_insn_for (COMPARE, mode))
11420             {
11421               op0 = XEXP (op0, 0);
11422               continue;
11423             }
11424           break;
11425
11426         case PLUS:
11427           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11428              this for equality comparisons due to pathological cases involving
11429              overflows.  */
11430           if (equality_comparison_p
11431               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11432                                                         op1, XEXP (op0, 1))))
11433             {
11434               op0 = XEXP (op0, 0);
11435               op1 = tem;
11436               continue;
11437             }
11438
11439           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11440           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11441               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11442             {
11443               op0 = XEXP (XEXP (op0, 0), 0);
11444               code = (code == LT ? EQ : NE);
11445               continue;
11446             }
11447           break;
11448
11449         case MINUS:
11450           /* We used to optimize signed comparisons against zero, but that
11451              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11452              arrive here as equality comparisons, or (GEU, LTU) are
11453              optimized away.  No need to special-case them.  */
11454
11455           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11456              (eq B (minus A C)), whichever simplifies.  We can only do
11457              this for equality comparisons due to pathological cases involving
11458              overflows.  */
11459           if (equality_comparison_p
11460               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11461                                                         XEXP (op0, 1), op1)))
11462             {
11463               op0 = XEXP (op0, 0);
11464               op1 = tem;
11465               continue;
11466             }
11467
11468           if (equality_comparison_p
11469               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11470                                                         XEXP (op0, 0), op1)))
11471             {
11472               op0 = XEXP (op0, 1);
11473               op1 = tem;
11474               continue;
11475             }
11476
11477           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11478              of bits in X minus 1, is one iff X > 0.  */
11479           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11480               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11481               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11482               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11483             {
11484               op0 = XEXP (op0, 1);
11485               code = (code == GE ? LE : GT);
11486               continue;
11487             }
11488           break;
11489
11490         case XOR:
11491           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11492              if C is zero or B is a constant.  */
11493           if (equality_comparison_p
11494               && 0 != (tem = simplify_binary_operation (XOR, mode,
11495                                                         XEXP (op0, 1), op1)))
11496             {
11497               op0 = XEXP (op0, 0);
11498               op1 = tem;
11499               continue;
11500             }
11501           break;
11502
11503         case EQ:  case NE:
11504         case UNEQ:  case LTGT:
11505         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11506         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11507         case UNORDERED: case ORDERED:
11508           /* We can't do anything if OP0 is a condition code value, rather
11509              than an actual data value.  */
11510           if (const_op != 0
11511               || CC0_P (XEXP (op0, 0))
11512               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11513             break;
11514
11515           /* Get the two operands being compared.  */
11516           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11517             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11518           else
11519             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11520
11521           /* Check for the cases where we simply want the result of the
11522              earlier test or the opposite of that result.  */
11523           if (code == NE || code == EQ
11524               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11525                   && (code == LT || code == GE)))
11526             {
11527               enum rtx_code new_code;
11528               if (code == LT || code == NE)
11529                 new_code = GET_CODE (op0);
11530               else
11531                 new_code = reversed_comparison_code (op0, NULL);
11532
11533               if (new_code != UNKNOWN)
11534                 {
11535                   code = new_code;
11536                   op0 = tem;
11537                   op1 = tem1;
11538                   continue;
11539                 }
11540             }
11541           break;
11542
11543         case IOR:
11544           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11545              iff X <= 0.  */
11546           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11547               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11548               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11549             {
11550               op0 = XEXP (op0, 1);
11551               code = (code == GE ? GT : LE);
11552               continue;
11553             }
11554           break;
11555
11556         case AND:
11557           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11558              will be converted to a ZERO_EXTRACT later.  */
11559           if (const_op == 0 && equality_comparison_p
11560               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11561               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11562             {
11563               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11564                                       XEXP (XEXP (op0, 0), 1));
11565               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11566               continue;
11567             }
11568
11569           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11570              zero and X is a comparison and C1 and C2 describe only bits set
11571              in STORE_FLAG_VALUE, we can compare with X.  */
11572           if (const_op == 0 && equality_comparison_p
11573               && mode_width <= HOST_BITS_PER_WIDE_INT
11574               && CONST_INT_P (XEXP (op0, 1))
11575               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11576               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11577               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11578               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11579             {
11580               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11581                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11582               if ((~STORE_FLAG_VALUE & mask) == 0
11583                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11584                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11585                           && COMPARISON_P (tem))))
11586                 {
11587                   op0 = XEXP (XEXP (op0, 0), 0);
11588                   continue;
11589                 }
11590             }
11591
11592           /* If we are doing an equality comparison of an AND of a bit equal
11593              to the sign bit, replace this with a LT or GE comparison of
11594              the underlying value.  */
11595           if (equality_comparison_p
11596               && const_op == 0
11597               && CONST_INT_P (XEXP (op0, 1))
11598               && mode_width <= HOST_BITS_PER_WIDE_INT
11599               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11600                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11601             {
11602               op0 = XEXP (op0, 0);
11603               code = (code == EQ ? GE : LT);
11604               continue;
11605             }
11606
11607           /* If this AND operation is really a ZERO_EXTEND from a narrower
11608              mode, the constant fits within that mode, and this is either an
11609              equality or unsigned comparison, try to do this comparison in
11610              the narrower mode.
11611
11612              Note that in:
11613
11614              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11615              -> (ne:DI (reg:SI 4) (const_int 0))
11616
11617              unless TRULY_NOOP_TRUNCATION allows it or the register is
11618              known to hold a value of the required mode the
11619              transformation is invalid.  */
11620           if ((equality_comparison_p || unsigned_comparison_p)
11621               && CONST_INT_P (XEXP (op0, 1))
11622               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11623                                    & GET_MODE_MASK (mode))
11624                                   + 1)) >= 0
11625               && const_op >> i == 0
11626               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11627               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11628                   || (REG_P (XEXP (op0, 0))
11629                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11630             {
11631               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11632               continue;
11633             }
11634
11635           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11636              fits in both M1 and M2 and the SUBREG is either paradoxical
11637              or represents the low part, permute the SUBREG and the AND
11638              and try again.  */
11639           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11640             {
11641               unsigned HOST_WIDE_INT c1;
11642               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11643               /* Require an integral mode, to avoid creating something like
11644                  (AND:SF ...).  */
11645               if (SCALAR_INT_MODE_P (tmode)
11646                   /* It is unsafe to commute the AND into the SUBREG if the
11647                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11648                      not defined.  As originally written the upper bits
11649                      have a defined value due to the AND operation.
11650                      However, if we commute the AND inside the SUBREG then
11651                      they no longer have defined values and the meaning of
11652                      the code has been changed.  */
11653                   && (0
11654 #ifdef WORD_REGISTER_OPERATIONS
11655                       || (mode_width > GET_MODE_PRECISION (tmode)
11656                           && mode_width <= BITS_PER_WORD)
11657 #endif
11658                       || (mode_width <= GET_MODE_PRECISION (tmode)
11659                           && subreg_lowpart_p (XEXP (op0, 0))))
11660                   && CONST_INT_P (XEXP (op0, 1))
11661                   && mode_width <= HOST_BITS_PER_WIDE_INT
11662                   && HWI_COMPUTABLE_MODE_P (tmode)
11663                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11664                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11665                   && c1 != mask
11666                   && c1 != GET_MODE_MASK (tmode))
11667                 {
11668                   op0 = simplify_gen_binary (AND, tmode,
11669                                              SUBREG_REG (XEXP (op0, 0)),
11670                                              gen_int_mode (c1, tmode));
11671                   op0 = gen_lowpart (mode, op0);
11672                   continue;
11673                 }
11674             }
11675
11676           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11677           if (const_op == 0 && equality_comparison_p
11678               && XEXP (op0, 1) == const1_rtx
11679               && GET_CODE (XEXP (op0, 0)) == NOT)
11680             {
11681               op0 = simplify_and_const_int (NULL_RTX, mode,
11682                                             XEXP (XEXP (op0, 0), 0), 1);
11683               code = (code == NE ? EQ : NE);
11684               continue;
11685             }
11686
11687           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11688              (eq (and (lshiftrt X) 1) 0).
11689              Also handle the case where (not X) is expressed using xor.  */
11690           if (const_op == 0 && equality_comparison_p
11691               && XEXP (op0, 1) == const1_rtx
11692               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11693             {
11694               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11695               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11696
11697               if (GET_CODE (shift_op) == NOT
11698                   || (GET_CODE (shift_op) == XOR
11699                       && CONST_INT_P (XEXP (shift_op, 1))
11700                       && CONST_INT_P (shift_count)
11701                       && HWI_COMPUTABLE_MODE_P (mode)
11702                       && (UINTVAL (XEXP (shift_op, 1))
11703                           == (unsigned HOST_WIDE_INT) 1
11704                                << INTVAL (shift_count))))
11705                 {
11706                   op0
11707                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11708                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11709                   code = (code == NE ? EQ : NE);
11710                   continue;
11711                 }
11712             }
11713           break;
11714
11715         case ASHIFT:
11716           /* If we have (compare (ashift FOO N) (const_int C)) and
11717              the high order N bits of FOO (N+1 if an inequality comparison)
11718              are known to be zero, we can do this by comparing FOO with C
11719              shifted right N bits so long as the low-order N bits of C are
11720              zero.  */
11721           if (CONST_INT_P (XEXP (op0, 1))
11722               && INTVAL (XEXP (op0, 1)) >= 0
11723               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11724                   < HOST_BITS_PER_WIDE_INT)
11725               && (((unsigned HOST_WIDE_INT) const_op
11726                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11727                       - 1)) == 0)
11728               && mode_width <= HOST_BITS_PER_WIDE_INT
11729               && (nonzero_bits (XEXP (op0, 0), mode)
11730                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11731                                + ! equality_comparison_p))) == 0)
11732             {
11733               /* We must perform a logical shift, not an arithmetic one,
11734                  as we want the top N bits of C to be zero.  */
11735               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11736
11737               temp >>= INTVAL (XEXP (op0, 1));
11738               op1 = gen_int_mode (temp, mode);
11739               op0 = XEXP (op0, 0);
11740               continue;
11741             }
11742
11743           /* If we are doing a sign bit comparison, it means we are testing
11744              a particular bit.  Convert it to the appropriate AND.  */
11745           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11746               && mode_width <= HOST_BITS_PER_WIDE_INT)
11747             {
11748               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11749                                             ((unsigned HOST_WIDE_INT) 1
11750                                              << (mode_width - 1
11751                                                  - INTVAL (XEXP (op0, 1)))));
11752               code = (code == LT ? NE : EQ);
11753               continue;
11754             }
11755
11756           /* If this an equality comparison with zero and we are shifting
11757              the low bit to the sign bit, we can convert this to an AND of the
11758              low-order bit.  */
11759           if (const_op == 0 && equality_comparison_p
11760               && CONST_INT_P (XEXP (op0, 1))
11761               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11762             {
11763               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11764               continue;
11765             }
11766           break;
11767
11768         case ASHIFTRT:
11769           /* If this is an equality comparison with zero, we can do this
11770              as a logical shift, which might be much simpler.  */
11771           if (equality_comparison_p && const_op == 0
11772               && CONST_INT_P (XEXP (op0, 1)))
11773             {
11774               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11775                                           XEXP (op0, 0),
11776                                           INTVAL (XEXP (op0, 1)));
11777               continue;
11778             }
11779
11780           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11781              do the comparison in a narrower mode.  */
11782           if (! unsigned_comparison_p
11783               && CONST_INT_P (XEXP (op0, 1))
11784               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11785               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11786               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11787                                          MODE_INT, 1)) != BLKmode
11788               && (((unsigned HOST_WIDE_INT) const_op
11789                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11790                   <= GET_MODE_MASK (tmode)))
11791             {
11792               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11793               continue;
11794             }
11795
11796           /* Likewise if OP0 is a PLUS of a sign extension with a
11797              constant, which is usually represented with the PLUS
11798              between the shifts.  */
11799           if (! unsigned_comparison_p
11800               && CONST_INT_P (XEXP (op0, 1))
11801               && GET_CODE (XEXP (op0, 0)) == PLUS
11802               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11803               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11804               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11805               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11806                                          MODE_INT, 1)) != BLKmode
11807               && (((unsigned HOST_WIDE_INT) const_op
11808                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11809                   <= GET_MODE_MASK (tmode)))
11810             {
11811               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11812               rtx add_const = XEXP (XEXP (op0, 0), 1);
11813               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11814                                                    add_const, XEXP (op0, 1));
11815
11816               op0 = simplify_gen_binary (PLUS, tmode,
11817                                          gen_lowpart (tmode, inner),
11818                                          new_const);
11819               continue;
11820             }
11821
11822           /* ... fall through ...  */
11823         case LSHIFTRT:
11824           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11825              the low order N bits of FOO are known to be zero, we can do this
11826              by comparing FOO with C shifted left N bits so long as no
11827              overflow occurs.  Even if the low order N bits of FOO aren't known
11828              to be zero, if the comparison is >= or < we can use the same
11829              optimization and for > or <= by setting all the low
11830              order N bits in the comparison constant.  */
11831           if (CONST_INT_P (XEXP (op0, 1))
11832               && INTVAL (XEXP (op0, 1)) > 0
11833               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11834               && mode_width <= HOST_BITS_PER_WIDE_INT
11835               && (((unsigned HOST_WIDE_INT) const_op
11836                    + (GET_CODE (op0) != LSHIFTRT
11837                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11838                          + 1)
11839                       : 0))
11840                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11841             {
11842               unsigned HOST_WIDE_INT low_bits
11843                 = (nonzero_bits (XEXP (op0, 0), mode)
11844                    & (((unsigned HOST_WIDE_INT) 1
11845                        << INTVAL (XEXP (op0, 1))) - 1));
11846               if (low_bits == 0 || !equality_comparison_p)
11847                 {
11848                   /* If the shift was logical, then we must make the condition
11849                      unsigned.  */
11850                   if (GET_CODE (op0) == LSHIFTRT)
11851                     code = unsigned_condition (code);
11852
11853                   const_op <<= INTVAL (XEXP (op0, 1));
11854                   if (low_bits != 0
11855                       && (code == GT || code == GTU
11856                           || code == LE || code == LEU))
11857                     const_op
11858                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11859                   op1 = GEN_INT (const_op);
11860                   op0 = XEXP (op0, 0);
11861                   continue;
11862                 }
11863             }
11864
11865           /* If we are using this shift to extract just the sign bit, we
11866              can replace this with an LT or GE comparison.  */
11867           if (const_op == 0
11868               && (equality_comparison_p || sign_bit_comparison_p)
11869               && CONST_INT_P (XEXP (op0, 1))
11870               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11871             {
11872               op0 = XEXP (op0, 0);
11873               code = (code == NE || code == GT ? LT : GE);
11874               continue;
11875             }
11876           break;
11877
11878         default:
11879           break;
11880         }
11881
11882       break;
11883     }
11884
11885   /* Now make any compound operations involved in this comparison.  Then,
11886      check for an outmost SUBREG on OP0 that is not doing anything or is
11887      paradoxical.  The latter transformation must only be performed when
11888      it is known that the "extra" bits will be the same in op0 and op1 or
11889      that they don't matter.  There are three cases to consider:
11890
11891      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11892      care bits and we can assume they have any convenient value.  So
11893      making the transformation is safe.
11894
11895      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11896      In this case the upper bits of op0 are undefined.  We should not make
11897      the simplification in that case as we do not know the contents of
11898      those bits.
11899
11900      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11901      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11902      also be sure that they are the same as the upper bits of op1.
11903
11904      We can never remove a SUBREG for a non-equality comparison because
11905      the sign bit is in a different place in the underlying object.  */
11906
11907   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11908   op1 = make_compound_operation (op1, SET);
11909
11910   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11911       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11912       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11913       && (code == NE || code == EQ))
11914     {
11915       if (paradoxical_subreg_p (op0))
11916         {
11917           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11918              implemented.  */
11919           if (REG_P (SUBREG_REG (op0)))
11920             {
11921               op0 = SUBREG_REG (op0);
11922               op1 = gen_lowpart (GET_MODE (op0), op1);
11923             }
11924         }
11925       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11926                 <= HOST_BITS_PER_WIDE_INT)
11927                && (nonzero_bits (SUBREG_REG (op0),
11928                                  GET_MODE (SUBREG_REG (op0)))
11929                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11930         {
11931           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11932
11933           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11934                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11935             op0 = SUBREG_REG (op0), op1 = tem;
11936         }
11937     }
11938
11939   /* We now do the opposite procedure: Some machines don't have compare
11940      insns in all modes.  If OP0's mode is an integer mode smaller than a
11941      word and we can't do a compare in that mode, see if there is a larger
11942      mode for which we can do the compare.  There are a number of cases in
11943      which we can use the wider mode.  */
11944
11945   mode = GET_MODE (op0);
11946   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11947       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11948       && ! have_insn_for (COMPARE, mode))
11949     for (tmode = GET_MODE_WIDER_MODE (mode);
11950          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11951          tmode = GET_MODE_WIDER_MODE (tmode))
11952       if (have_insn_for (COMPARE, tmode))
11953         {
11954           int zero_extended;
11955
11956           /* If this is a test for negative, we can make an explicit
11957              test of the sign bit.  Test this first so we can use
11958              a paradoxical subreg to extend OP0.  */
11959
11960           if (op1 == const0_rtx && (code == LT || code == GE)
11961               && HWI_COMPUTABLE_MODE_P (mode))
11962             {
11963               unsigned HOST_WIDE_INT sign
11964                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
11965               op0 = simplify_gen_binary (AND, tmode,
11966                                          gen_lowpart (tmode, op0),
11967                                          gen_int_mode (sign, mode));
11968               code = (code == LT) ? NE : EQ;
11969               break;
11970             }
11971
11972           /* If the only nonzero bits in OP0 and OP1 are those in the
11973              narrower mode and this is an equality or unsigned comparison,
11974              we can use the wider mode.  Similarly for sign-extended
11975              values, in which case it is true for all comparisons.  */
11976           zero_extended = ((code == EQ || code == NE
11977                             || code == GEU || code == GTU
11978                             || code == LEU || code == LTU)
11979                            && (nonzero_bits (op0, tmode)
11980                                & ~GET_MODE_MASK (mode)) == 0
11981                            && ((CONST_INT_P (op1)
11982                                 || (nonzero_bits (op1, tmode)
11983                                     & ~GET_MODE_MASK (mode)) == 0)));
11984
11985           if (zero_extended
11986               || ((num_sign_bit_copies (op0, tmode)
11987                    > (unsigned int) (GET_MODE_PRECISION (tmode)
11988                                      - GET_MODE_PRECISION (mode)))
11989                   && (num_sign_bit_copies (op1, tmode)
11990                       > (unsigned int) (GET_MODE_PRECISION (tmode)
11991                                         - GET_MODE_PRECISION (mode)))))
11992             {
11993               /* If OP0 is an AND and we don't have an AND in MODE either,
11994                  make a new AND in the proper mode.  */
11995               if (GET_CODE (op0) == AND
11996                   && !have_insn_for (AND, mode))
11997                 op0 = simplify_gen_binary (AND, tmode,
11998                                            gen_lowpart (tmode,
11999                                                         XEXP (op0, 0)),
12000                                            gen_lowpart (tmode,
12001                                                         XEXP (op0, 1)));
12002               else
12003                 {
12004                   if (zero_extended)
12005                     {
12006                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12007                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12008                     }
12009                   else
12010                     {
12011                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12012                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12013                     }
12014                   break;
12015                 }
12016             }
12017         }
12018
12019   /* We may have changed the comparison operands.  Re-canonicalize.  */
12020   if (swap_commutative_operands_p (op0, op1))
12021     {
12022       tem = op0, op0 = op1, op1 = tem;
12023       code = swap_condition (code);
12024     }
12025
12026   /* If this machine only supports a subset of valid comparisons, see if we
12027      can convert an unsupported one into a supported one.  */
12028   target_canonicalize_comparison (&code, &op0, &op1, 0);
12029
12030   *pop0 = op0;
12031   *pop1 = op1;
12032
12033   return code;
12034 }
12035 \f
12036 /* Utility function for record_value_for_reg.  Count number of
12037    rtxs in X.  */
12038 static int
12039 count_rtxs (rtx x)
12040 {
12041   enum rtx_code code = GET_CODE (x);
12042   const char *fmt;
12043   int i, j, ret = 1;
12044
12045   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12046       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12047     {
12048       rtx x0 = XEXP (x, 0);
12049       rtx x1 = XEXP (x, 1);
12050
12051       if (x0 == x1)
12052         return 1 + 2 * count_rtxs (x0);
12053
12054       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12055            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12056           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12057         return 2 + 2 * count_rtxs (x0)
12058                + count_rtxs (x == XEXP (x1, 0)
12059                              ? XEXP (x1, 1) : XEXP (x1, 0));
12060
12061       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12062            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12063           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12064         return 2 + 2 * count_rtxs (x1)
12065                + count_rtxs (x == XEXP (x0, 0)
12066                              ? XEXP (x0, 1) : XEXP (x0, 0));
12067     }
12068
12069   fmt = GET_RTX_FORMAT (code);
12070   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12071     if (fmt[i] == 'e')
12072       ret += count_rtxs (XEXP (x, i));
12073     else if (fmt[i] == 'E')
12074       for (j = 0; j < XVECLEN (x, i); j++)
12075         ret += count_rtxs (XVECEXP (x, i, j));
12076
12077   return ret;
12078 }
12079 \f
12080 /* Utility function for following routine.  Called when X is part of a value
12081    being stored into last_set_value.  Sets last_set_table_tick
12082    for each register mentioned.  Similar to mention_regs in cse.c  */
12083
12084 static void
12085 update_table_tick (rtx x)
12086 {
12087   enum rtx_code code = GET_CODE (x);
12088   const char *fmt = GET_RTX_FORMAT (code);
12089   int i, j;
12090
12091   if (code == REG)
12092     {
12093       unsigned int regno = REGNO (x);
12094       unsigned int endregno = END_REGNO (x);
12095       unsigned int r;
12096
12097       for (r = regno; r < endregno; r++)
12098         {
12099           reg_stat_type *rsp = &reg_stat[r];
12100           rsp->last_set_table_tick = label_tick;
12101         }
12102
12103       return;
12104     }
12105
12106   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12107     if (fmt[i] == 'e')
12108       {
12109         /* Check for identical subexpressions.  If x contains
12110            identical subexpression we only have to traverse one of
12111            them.  */
12112         if (i == 0 && ARITHMETIC_P (x))
12113           {
12114             /* Note that at this point x1 has already been
12115                processed.  */
12116             rtx x0 = XEXP (x, 0);
12117             rtx x1 = XEXP (x, 1);
12118
12119             /* If x0 and x1 are identical then there is no need to
12120                process x0.  */
12121             if (x0 == x1)
12122               break;
12123
12124             /* If x0 is identical to a subexpression of x1 then while
12125                processing x1, x0 has already been processed.  Thus we
12126                are done with x.  */
12127             if (ARITHMETIC_P (x1)
12128                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12129               break;
12130
12131             /* If x1 is identical to a subexpression of x0 then we
12132                still have to process the rest of x0.  */
12133             if (ARITHMETIC_P (x0)
12134                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12135               {
12136                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12137                 break;
12138               }
12139           }
12140
12141         update_table_tick (XEXP (x, i));
12142       }
12143     else if (fmt[i] == 'E')
12144       for (j = 0; j < XVECLEN (x, i); j++)
12145         update_table_tick (XVECEXP (x, i, j));
12146 }
12147
12148 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12149    are saying that the register is clobbered and we no longer know its
12150    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12151    only permitted with VALUE also zero and is used to invalidate the
12152    register.  */
12153
12154 static void
12155 record_value_for_reg (rtx reg, rtx insn, rtx value)
12156 {
12157   unsigned int regno = REGNO (reg);
12158   unsigned int endregno = END_REGNO (reg);
12159   unsigned int i;
12160   reg_stat_type *rsp;
12161
12162   /* If VALUE contains REG and we have a previous value for REG, substitute
12163      the previous value.  */
12164   if (value && insn && reg_overlap_mentioned_p (reg, value))
12165     {
12166       rtx tem;
12167
12168       /* Set things up so get_last_value is allowed to see anything set up to
12169          our insn.  */
12170       subst_low_luid = DF_INSN_LUID (insn);
12171       tem = get_last_value (reg);
12172
12173       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12174          it isn't going to be useful and will take a lot of time to process,
12175          so just use the CLOBBER.  */
12176
12177       if (tem)
12178         {
12179           if (ARITHMETIC_P (tem)
12180               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12181               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12182             tem = XEXP (tem, 0);
12183           else if (count_occurrences (value, reg, 1) >= 2)
12184             {
12185               /* If there are two or more occurrences of REG in VALUE,
12186                  prevent the value from growing too much.  */
12187               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12188                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12189             }
12190
12191           value = replace_rtx (copy_rtx (value), reg, tem);
12192         }
12193     }
12194
12195   /* For each register modified, show we don't know its value, that
12196      we don't know about its bitwise content, that its value has been
12197      updated, and that we don't know the location of the death of the
12198      register.  */
12199   for (i = regno; i < endregno; i++)
12200     {
12201       rsp = &reg_stat[i];
12202
12203       if (insn)
12204         rsp->last_set = insn;
12205
12206       rsp->last_set_value = 0;
12207       rsp->last_set_mode = VOIDmode;
12208       rsp->last_set_nonzero_bits = 0;
12209       rsp->last_set_sign_bit_copies = 0;
12210       rsp->last_death = 0;
12211       rsp->truncated_to_mode = VOIDmode;
12212     }
12213
12214   /* Mark registers that are being referenced in this value.  */
12215   if (value)
12216     update_table_tick (value);
12217
12218   /* Now update the status of each register being set.
12219      If someone is using this register in this block, set this register
12220      to invalid since we will get confused between the two lives in this
12221      basic block.  This makes using this register always invalid.  In cse, we
12222      scan the table to invalidate all entries using this register, but this
12223      is too much work for us.  */
12224
12225   for (i = regno; i < endregno; i++)
12226     {
12227       rsp = &reg_stat[i];
12228       rsp->last_set_label = label_tick;
12229       if (!insn
12230           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12231         rsp->last_set_invalid = 1;
12232       else
12233         rsp->last_set_invalid = 0;
12234     }
12235
12236   /* The value being assigned might refer to X (like in "x++;").  In that
12237      case, we must replace it with (clobber (const_int 0)) to prevent
12238      infinite loops.  */
12239   rsp = &reg_stat[regno];
12240   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12241     {
12242       value = copy_rtx (value);
12243       if (!get_last_value_validate (&value, insn, label_tick, 1))
12244         value = 0;
12245     }
12246
12247   /* For the main register being modified, update the value, the mode, the
12248      nonzero bits, and the number of sign bit copies.  */
12249
12250   rsp->last_set_value = value;
12251
12252   if (value)
12253     {
12254       enum machine_mode mode = GET_MODE (reg);
12255       subst_low_luid = DF_INSN_LUID (insn);
12256       rsp->last_set_mode = mode;
12257       if (GET_MODE_CLASS (mode) == MODE_INT
12258           && HWI_COMPUTABLE_MODE_P (mode))
12259         mode = nonzero_bits_mode;
12260       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12261       rsp->last_set_sign_bit_copies
12262         = num_sign_bit_copies (value, GET_MODE (reg));
12263     }
12264 }
12265
12266 /* Called via note_stores from record_dead_and_set_regs to handle one
12267    SET or CLOBBER in an insn.  DATA is the instruction in which the
12268    set is occurring.  */
12269
12270 static void
12271 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12272 {
12273   rtx record_dead_insn = (rtx) data;
12274
12275   if (GET_CODE (dest) == SUBREG)
12276     dest = SUBREG_REG (dest);
12277
12278   if (!record_dead_insn)
12279     {
12280       if (REG_P (dest))
12281         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12282       return;
12283     }
12284
12285   if (REG_P (dest))
12286     {
12287       /* If we are setting the whole register, we know its value.  Otherwise
12288          show that we don't know the value.  We can handle SUBREG in
12289          some cases.  */
12290       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12291         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12292       else if (GET_CODE (setter) == SET
12293                && GET_CODE (SET_DEST (setter)) == SUBREG
12294                && SUBREG_REG (SET_DEST (setter)) == dest
12295                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12296                && subreg_lowpart_p (SET_DEST (setter)))
12297         record_value_for_reg (dest, record_dead_insn,
12298                               gen_lowpart (GET_MODE (dest),
12299                                                        SET_SRC (setter)));
12300       else
12301         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12302     }
12303   else if (MEM_P (dest)
12304            /* Ignore pushes, they clobber nothing.  */
12305            && ! push_operand (dest, GET_MODE (dest)))
12306     mem_last_set = DF_INSN_LUID (record_dead_insn);
12307 }
12308
12309 /* Update the records of when each REG was most recently set or killed
12310    for the things done by INSN.  This is the last thing done in processing
12311    INSN in the combiner loop.
12312
12313    We update reg_stat[], in particular fields last_set, last_set_value,
12314    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12315    last_death, and also the similar information mem_last_set (which insn
12316    most recently modified memory) and last_call_luid (which insn was the
12317    most recent subroutine call).  */
12318
12319 static void
12320 record_dead_and_set_regs (rtx insn)
12321 {
12322   rtx link;
12323   unsigned int i;
12324
12325   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12326     {
12327       if (REG_NOTE_KIND (link) == REG_DEAD
12328           && REG_P (XEXP (link, 0)))
12329         {
12330           unsigned int regno = REGNO (XEXP (link, 0));
12331           unsigned int endregno = END_REGNO (XEXP (link, 0));
12332
12333           for (i = regno; i < endregno; i++)
12334             {
12335               reg_stat_type *rsp;
12336
12337               rsp = &reg_stat[i];
12338               rsp->last_death = insn;
12339             }
12340         }
12341       else if (REG_NOTE_KIND (link) == REG_INC)
12342         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12343     }
12344
12345   if (CALL_P (insn))
12346     {
12347       hard_reg_set_iterator hrsi;
12348       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12349         {
12350           reg_stat_type *rsp;
12351
12352           rsp = &reg_stat[i];
12353           rsp->last_set_invalid = 1;
12354           rsp->last_set = insn;
12355           rsp->last_set_value = 0;
12356           rsp->last_set_mode = VOIDmode;
12357           rsp->last_set_nonzero_bits = 0;
12358           rsp->last_set_sign_bit_copies = 0;
12359           rsp->last_death = 0;
12360           rsp->truncated_to_mode = VOIDmode;
12361         }
12362
12363       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12364
12365       /* We can't combine into a call pattern.  Remember, though, that
12366          the return value register is set at this LUID.  We could
12367          still replace a register with the return value from the
12368          wrong subroutine call!  */
12369       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12370     }
12371   else
12372     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12373 }
12374
12375 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12376    register present in the SUBREG, so for each such SUBREG go back and
12377    adjust nonzero and sign bit information of the registers that are
12378    known to have some zero/sign bits set.
12379
12380    This is needed because when combine blows the SUBREGs away, the
12381    information on zero/sign bits is lost and further combines can be
12382    missed because of that.  */
12383
12384 static void
12385 record_promoted_value (rtx insn, rtx subreg)
12386 {
12387   struct insn_link *links;
12388   rtx set;
12389   unsigned int regno = REGNO (SUBREG_REG (subreg));
12390   enum machine_mode mode = GET_MODE (subreg);
12391
12392   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12393     return;
12394
12395   for (links = LOG_LINKS (insn); links;)
12396     {
12397       reg_stat_type *rsp;
12398
12399       insn = links->insn;
12400       set = single_set (insn);
12401
12402       if (! set || !REG_P (SET_DEST (set))
12403           || REGNO (SET_DEST (set)) != regno
12404           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12405         {
12406           links = links->next;
12407           continue;
12408         }
12409
12410       rsp = &reg_stat[regno];
12411       if (rsp->last_set == insn)
12412         {
12413           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12414             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12415         }
12416
12417       if (REG_P (SET_SRC (set)))
12418         {
12419           regno = REGNO (SET_SRC (set));
12420           links = LOG_LINKS (insn);
12421         }
12422       else
12423         break;
12424     }
12425 }
12426
12427 /* Check if X, a register, is known to contain a value already
12428    truncated to MODE.  In this case we can use a subreg to refer to
12429    the truncated value even though in the generic case we would need
12430    an explicit truncation.  */
12431
12432 static bool
12433 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12434 {
12435   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12436   enum machine_mode truncated = rsp->truncated_to_mode;
12437
12438   if (truncated == 0
12439       || rsp->truncation_label < label_tick_ebb_start)
12440     return false;
12441   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12442     return true;
12443   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12444     return true;
12445   return false;
12446 }
12447
12448 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12449    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12450    might be able to turn a truncate into a subreg using this information.
12451    Return -1 if traversing *P is complete or 0 otherwise.  */
12452
12453 static int
12454 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12455 {
12456   rtx x = *p;
12457   enum machine_mode truncated_mode;
12458   reg_stat_type *rsp;
12459
12460   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12461     {
12462       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12463       truncated_mode = GET_MODE (x);
12464
12465       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12466         return -1;
12467
12468       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12469         return -1;
12470
12471       x = SUBREG_REG (x);
12472     }
12473   /* ??? For hard-regs we now record everything.  We might be able to
12474      optimize this using last_set_mode.  */
12475   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12476     truncated_mode = GET_MODE (x);
12477   else
12478     return 0;
12479
12480   rsp = &reg_stat[REGNO (x)];
12481   if (rsp->truncated_to_mode == 0
12482       || rsp->truncation_label < label_tick_ebb_start
12483       || (GET_MODE_SIZE (truncated_mode)
12484           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12485     {
12486       rsp->truncated_to_mode = truncated_mode;
12487       rsp->truncation_label = label_tick;
12488     }
12489
12490   return -1;
12491 }
12492
12493 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12494    the modes they are used in.  This can help truning TRUNCATEs into
12495    SUBREGs.  */
12496
12497 static void
12498 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12499 {
12500   for_each_rtx (x, record_truncated_value, NULL);
12501 }
12502
12503 /* Scan X for promoted SUBREGs.  For each one found,
12504    note what it implies to the registers used in it.  */
12505
12506 static void
12507 check_promoted_subreg (rtx insn, rtx x)
12508 {
12509   if (GET_CODE (x) == SUBREG
12510       && SUBREG_PROMOTED_VAR_P (x)
12511       && REG_P (SUBREG_REG (x)))
12512     record_promoted_value (insn, x);
12513   else
12514     {
12515       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12516       int i, j;
12517
12518       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12519         switch (format[i])
12520           {
12521           case 'e':
12522             check_promoted_subreg (insn, XEXP (x, i));
12523             break;
12524           case 'V':
12525           case 'E':
12526             if (XVEC (x, i) != 0)
12527               for (j = 0; j < XVECLEN (x, i); j++)
12528                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12529             break;
12530           }
12531     }
12532 }
12533 \f
12534 /* Verify that all the registers and memory references mentioned in *LOC are
12535    still valid.  *LOC was part of a value set in INSN when label_tick was
12536    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12537    the invalid references with (clobber (const_int 0)) and return 1.  This
12538    replacement is useful because we often can get useful information about
12539    the form of a value (e.g., if it was produced by a shift that always
12540    produces -1 or 0) even though we don't know exactly what registers it
12541    was produced from.  */
12542
12543 static int
12544 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12545 {
12546   rtx x = *loc;
12547   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12548   int len = GET_RTX_LENGTH (GET_CODE (x));
12549   int i, j;
12550
12551   if (REG_P (x))
12552     {
12553       unsigned int regno = REGNO (x);
12554       unsigned int endregno = END_REGNO (x);
12555       unsigned int j;
12556
12557       for (j = regno; j < endregno; j++)
12558         {
12559           reg_stat_type *rsp = &reg_stat[j];
12560           if (rsp->last_set_invalid
12561               /* If this is a pseudo-register that was only set once and not
12562                  live at the beginning of the function, it is always valid.  */
12563               || (! (regno >= FIRST_PSEUDO_REGISTER
12564                      && REG_N_SETS (regno) == 1
12565                      && (!REGNO_REG_SET_P
12566                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12567                   && rsp->last_set_label > tick))
12568           {
12569             if (replace)
12570               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12571             return replace;
12572           }
12573         }
12574
12575       return 1;
12576     }
12577   /* If this is a memory reference, make sure that there were no stores after
12578      it that might have clobbered the value.  We don't have alias info, so we
12579      assume any store invalidates it.  Moreover, we only have local UIDs, so
12580      we also assume that there were stores in the intervening basic blocks.  */
12581   else if (MEM_P (x) && !MEM_READONLY_P (x)
12582            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12583     {
12584       if (replace)
12585         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12586       return replace;
12587     }
12588
12589   for (i = 0; i < len; i++)
12590     {
12591       if (fmt[i] == 'e')
12592         {
12593           /* Check for identical subexpressions.  If x contains
12594              identical subexpression we only have to traverse one of
12595              them.  */
12596           if (i == 1 && ARITHMETIC_P (x))
12597             {
12598               /* Note that at this point x0 has already been checked
12599                  and found valid.  */
12600               rtx x0 = XEXP (x, 0);
12601               rtx x1 = XEXP (x, 1);
12602
12603               /* If x0 and x1 are identical then x is also valid.  */
12604               if (x0 == x1)
12605                 return 1;
12606
12607               /* If x1 is identical to a subexpression of x0 then
12608                  while checking x0, x1 has already been checked.  Thus
12609                  it is valid and so as x.  */
12610               if (ARITHMETIC_P (x0)
12611                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12612                 return 1;
12613
12614               /* If x0 is identical to a subexpression of x1 then x is
12615                  valid iff the rest of x1 is valid.  */
12616               if (ARITHMETIC_P (x1)
12617                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12618                 return
12619                   get_last_value_validate (&XEXP (x1,
12620                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12621                                            insn, tick, replace);
12622             }
12623
12624           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12625                                        replace) == 0)
12626             return 0;
12627         }
12628       else if (fmt[i] == 'E')
12629         for (j = 0; j < XVECLEN (x, i); j++)
12630           if (get_last_value_validate (&XVECEXP (x, i, j),
12631                                        insn, tick, replace) == 0)
12632             return 0;
12633     }
12634
12635   /* If we haven't found a reason for it to be invalid, it is valid.  */
12636   return 1;
12637 }
12638
12639 /* Get the last value assigned to X, if known.  Some registers
12640    in the value may be replaced with (clobber (const_int 0)) if their value
12641    is known longer known reliably.  */
12642
12643 static rtx
12644 get_last_value (const_rtx x)
12645 {
12646   unsigned int regno;
12647   rtx value;
12648   reg_stat_type *rsp;
12649
12650   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12651      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12652      we cannot predict what values the "extra" bits might have.  */
12653   if (GET_CODE (x) == SUBREG
12654       && subreg_lowpart_p (x)
12655       && !paradoxical_subreg_p (x)
12656       && (value = get_last_value (SUBREG_REG (x))) != 0)
12657     return gen_lowpart (GET_MODE (x), value);
12658
12659   if (!REG_P (x))
12660     return 0;
12661
12662   regno = REGNO (x);
12663   rsp = &reg_stat[regno];
12664   value = rsp->last_set_value;
12665
12666   /* If we don't have a value, or if it isn't for this basic block and
12667      it's either a hard register, set more than once, or it's a live
12668      at the beginning of the function, return 0.
12669
12670      Because if it's not live at the beginning of the function then the reg
12671      is always set before being used (is never used without being set).
12672      And, if it's set only once, and it's always set before use, then all
12673      uses must have the same last value, even if it's not from this basic
12674      block.  */
12675
12676   if (value == 0
12677       || (rsp->last_set_label < label_tick_ebb_start
12678           && (regno < FIRST_PSEUDO_REGISTER
12679               || REG_N_SETS (regno) != 1
12680               || REGNO_REG_SET_P
12681                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12682     return 0;
12683
12684   /* If the value was set in a later insn than the ones we are processing,
12685      we can't use it even if the register was only set once.  */
12686   if (rsp->last_set_label == label_tick
12687       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12688     return 0;
12689
12690   /* If the value has all its registers valid, return it.  */
12691   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12692     return value;
12693
12694   /* Otherwise, make a copy and replace any invalid register with
12695      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12696
12697   value = copy_rtx (value);
12698   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12699     return value;
12700
12701   return 0;
12702 }
12703 \f
12704 /* Return nonzero if expression X refers to a REG or to memory
12705    that is set in an instruction more recent than FROM_LUID.  */
12706
12707 static int
12708 use_crosses_set_p (const_rtx x, int from_luid)
12709 {
12710   const char *fmt;
12711   int i;
12712   enum rtx_code code = GET_CODE (x);
12713
12714   if (code == REG)
12715     {
12716       unsigned int regno = REGNO (x);
12717       unsigned endreg = END_REGNO (x);
12718
12719 #ifdef PUSH_ROUNDING
12720       /* Don't allow uses of the stack pointer to be moved,
12721          because we don't know whether the move crosses a push insn.  */
12722       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12723         return 1;
12724 #endif
12725       for (; regno < endreg; regno++)
12726         {
12727           reg_stat_type *rsp = &reg_stat[regno];
12728           if (rsp->last_set
12729               && rsp->last_set_label == label_tick
12730               && DF_INSN_LUID (rsp->last_set) > from_luid)
12731             return 1;
12732         }
12733       return 0;
12734     }
12735
12736   if (code == MEM && mem_last_set > from_luid)
12737     return 1;
12738
12739   fmt = GET_RTX_FORMAT (code);
12740
12741   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12742     {
12743       if (fmt[i] == 'E')
12744         {
12745           int j;
12746           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12747             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12748               return 1;
12749         }
12750       else if (fmt[i] == 'e'
12751                && use_crosses_set_p (XEXP (x, i), from_luid))
12752         return 1;
12753     }
12754   return 0;
12755 }
12756 \f
12757 /* Define three variables used for communication between the following
12758    routines.  */
12759
12760 static unsigned int reg_dead_regno, reg_dead_endregno;
12761 static int reg_dead_flag;
12762
12763 /* Function called via note_stores from reg_dead_at_p.
12764
12765    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12766    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12767
12768 static void
12769 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12770 {
12771   unsigned int regno, endregno;
12772
12773   if (!REG_P (dest))
12774     return;
12775
12776   regno = REGNO (dest);
12777   endregno = END_REGNO (dest);
12778   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12779     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12780 }
12781
12782 /* Return nonzero if REG is known to be dead at INSN.
12783
12784    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12785    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12786    live.  Otherwise, see if it is live or dead at the start of the basic
12787    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12788    must be assumed to be always live.  */
12789
12790 static int
12791 reg_dead_at_p (rtx reg, rtx insn)
12792 {
12793   basic_block block;
12794   unsigned int i;
12795
12796   /* Set variables for reg_dead_at_p_1.  */
12797   reg_dead_regno = REGNO (reg);
12798   reg_dead_endregno = END_REGNO (reg);
12799
12800   reg_dead_flag = 0;
12801
12802   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12803      we allow the machine description to decide whether use-and-clobber
12804      patterns are OK.  */
12805   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12806     {
12807       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12808         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12809           return 0;
12810     }
12811
12812   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12813      beginning of basic block.  */
12814   block = BLOCK_FOR_INSN (insn);
12815   for (;;)
12816     {
12817       if (INSN_P (insn))
12818         {
12819           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12820           if (reg_dead_flag)
12821             return reg_dead_flag == 1 ? 1 : 0;
12822
12823           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12824             return 1;
12825         }
12826
12827       if (insn == BB_HEAD (block))
12828         break;
12829
12830       insn = PREV_INSN (insn);
12831     }
12832
12833   /* Look at live-in sets for the basic block that we were in.  */
12834   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12835     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12836       return 0;
12837
12838   return 1;
12839 }
12840 \f
12841 /* Note hard registers in X that are used.  */
12842
12843 static void
12844 mark_used_regs_combine (rtx x)
12845 {
12846   RTX_CODE code = GET_CODE (x);
12847   unsigned int regno;
12848   int i;
12849
12850   switch (code)
12851     {
12852     case LABEL_REF:
12853     case SYMBOL_REF:
12854     case CONST:
12855     CASE_CONST_ANY:
12856     case PC:
12857     case ADDR_VEC:
12858     case ADDR_DIFF_VEC:
12859     case ASM_INPUT:
12860 #ifdef HAVE_cc0
12861     /* CC0 must die in the insn after it is set, so we don't need to take
12862        special note of it here.  */
12863     case CC0:
12864 #endif
12865       return;
12866
12867     case CLOBBER:
12868       /* If we are clobbering a MEM, mark any hard registers inside the
12869          address as used.  */
12870       if (MEM_P (XEXP (x, 0)))
12871         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12872       return;
12873
12874     case REG:
12875       regno = REGNO (x);
12876       /* A hard reg in a wide mode may really be multiple registers.
12877          If so, mark all of them just like the first.  */
12878       if (regno < FIRST_PSEUDO_REGISTER)
12879         {
12880           /* None of this applies to the stack, frame or arg pointers.  */
12881           if (regno == STACK_POINTER_REGNUM
12882 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12883               || regno == HARD_FRAME_POINTER_REGNUM
12884 #endif
12885 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12886               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12887 #endif
12888               || regno == FRAME_POINTER_REGNUM)
12889             return;
12890
12891           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12892         }
12893       return;
12894
12895     case SET:
12896       {
12897         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12898            the address.  */
12899         rtx testreg = SET_DEST (x);
12900
12901         while (GET_CODE (testreg) == SUBREG
12902                || GET_CODE (testreg) == ZERO_EXTRACT
12903                || GET_CODE (testreg) == STRICT_LOW_PART)
12904           testreg = XEXP (testreg, 0);
12905
12906         if (MEM_P (testreg))
12907           mark_used_regs_combine (XEXP (testreg, 0));
12908
12909         mark_used_regs_combine (SET_SRC (x));
12910       }
12911       return;
12912
12913     default:
12914       break;
12915     }
12916
12917   /* Recursively scan the operands of this expression.  */
12918
12919   {
12920     const char *fmt = GET_RTX_FORMAT (code);
12921
12922     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12923       {
12924         if (fmt[i] == 'e')
12925           mark_used_regs_combine (XEXP (x, i));
12926         else if (fmt[i] == 'E')
12927           {
12928             int j;
12929
12930             for (j = 0; j < XVECLEN (x, i); j++)
12931               mark_used_regs_combine (XVECEXP (x, i, j));
12932           }
12933       }
12934   }
12935 }
12936 \f
12937 /* Remove register number REGNO from the dead registers list of INSN.
12938
12939    Return the note used to record the death, if there was one.  */
12940
12941 rtx
12942 remove_death (unsigned int regno, rtx insn)
12943 {
12944   rtx note = find_regno_note (insn, REG_DEAD, regno);
12945
12946   if (note)
12947     remove_note (insn, note);
12948
12949   return note;
12950 }
12951
12952 /* For each register (hardware or pseudo) used within expression X, if its
12953    death is in an instruction with luid between FROM_LUID (inclusive) and
12954    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12955    list headed by PNOTES.
12956
12957    That said, don't move registers killed by maybe_kill_insn.
12958
12959    This is done when X is being merged by combination into TO_INSN.  These
12960    notes will then be distributed as needed.  */
12961
12962 static void
12963 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12964              rtx *pnotes)
12965 {
12966   const char *fmt;
12967   int len, i;
12968   enum rtx_code code = GET_CODE (x);
12969
12970   if (code == REG)
12971     {
12972       unsigned int regno = REGNO (x);
12973       rtx where_dead = reg_stat[regno].last_death;
12974
12975       /* Don't move the register if it gets killed in between from and to.  */
12976       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12977           && ! reg_referenced_p (x, maybe_kill_insn))
12978         return;
12979
12980       if (where_dead
12981           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12982           && DF_INSN_LUID (where_dead) >= from_luid
12983           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12984         {
12985           rtx note = remove_death (regno, where_dead);
12986
12987           /* It is possible for the call above to return 0.  This can occur
12988              when last_death points to I2 or I1 that we combined with.
12989              In that case make a new note.
12990
12991              We must also check for the case where X is a hard register
12992              and NOTE is a death note for a range of hard registers
12993              including X.  In that case, we must put REG_DEAD notes for
12994              the remaining registers in place of NOTE.  */
12995
12996           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12997               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12998                   > GET_MODE_SIZE (GET_MODE (x))))
12999             {
13000               unsigned int deadregno = REGNO (XEXP (note, 0));
13001               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13002               unsigned int ourend = END_HARD_REGNO (x);
13003               unsigned int i;
13004
13005               for (i = deadregno; i < deadend; i++)
13006                 if (i < regno || i >= ourend)
13007                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13008             }
13009
13010           /* If we didn't find any note, or if we found a REG_DEAD note that
13011              covers only part of the given reg, and we have a multi-reg hard
13012              register, then to be safe we must check for REG_DEAD notes
13013              for each register other than the first.  They could have
13014              their own REG_DEAD notes lying around.  */
13015           else if ((note == 0
13016                     || (note != 0
13017                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13018                             < GET_MODE_SIZE (GET_MODE (x)))))
13019                    && regno < FIRST_PSEUDO_REGISTER
13020                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13021             {
13022               unsigned int ourend = END_HARD_REGNO (x);
13023               unsigned int i, offset;
13024               rtx oldnotes = 0;
13025
13026               if (note)
13027                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13028               else
13029                 offset = 1;
13030
13031               for (i = regno + offset; i < ourend; i++)
13032                 move_deaths (regno_reg_rtx[i],
13033                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13034             }
13035
13036           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13037             {
13038               XEXP (note, 1) = *pnotes;
13039               *pnotes = note;
13040             }
13041           else
13042             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13043         }
13044
13045       return;
13046     }
13047
13048   else if (GET_CODE (x) == SET)
13049     {
13050       rtx dest = SET_DEST (x);
13051
13052       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13053
13054       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13055          that accesses one word of a multi-word item, some
13056          piece of everything register in the expression is used by
13057          this insn, so remove any old death.  */
13058       /* ??? So why do we test for equality of the sizes?  */
13059
13060       if (GET_CODE (dest) == ZERO_EXTRACT
13061           || GET_CODE (dest) == STRICT_LOW_PART
13062           || (GET_CODE (dest) == SUBREG
13063               && (((GET_MODE_SIZE (GET_MODE (dest))
13064                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13065                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13066                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13067         {
13068           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13069           return;
13070         }
13071
13072       /* If this is some other SUBREG, we know it replaces the entire
13073          value, so use that as the destination.  */
13074       if (GET_CODE (dest) == SUBREG)
13075         dest = SUBREG_REG (dest);
13076
13077       /* If this is a MEM, adjust deaths of anything used in the address.
13078          For a REG (the only other possibility), the entire value is
13079          being replaced so the old value is not used in this insn.  */
13080
13081       if (MEM_P (dest))
13082         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13083                      to_insn, pnotes);
13084       return;
13085     }
13086
13087   else if (GET_CODE (x) == CLOBBER)
13088     return;
13089
13090   len = GET_RTX_LENGTH (code);
13091   fmt = GET_RTX_FORMAT (code);
13092
13093   for (i = 0; i < len; i++)
13094     {
13095       if (fmt[i] == 'E')
13096         {
13097           int j;
13098           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13099             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13100                          to_insn, pnotes);
13101         }
13102       else if (fmt[i] == 'e')
13103         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13104     }
13105 }
13106 \f
13107 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13108    pattern of an insn.  X must be a REG.  */
13109
13110 static int
13111 reg_bitfield_target_p (rtx x, rtx body)
13112 {
13113   int i;
13114
13115   if (GET_CODE (body) == SET)
13116     {
13117       rtx dest = SET_DEST (body);
13118       rtx target;
13119       unsigned int regno, tregno, endregno, endtregno;
13120
13121       if (GET_CODE (dest) == ZERO_EXTRACT)
13122         target = XEXP (dest, 0);
13123       else if (GET_CODE (dest) == STRICT_LOW_PART)
13124         target = SUBREG_REG (XEXP (dest, 0));
13125       else
13126         return 0;
13127
13128       if (GET_CODE (target) == SUBREG)
13129         target = SUBREG_REG (target);
13130
13131       if (!REG_P (target))
13132         return 0;
13133
13134       tregno = REGNO (target), regno = REGNO (x);
13135       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13136         return target == x;
13137
13138       endtregno = end_hard_regno (GET_MODE (target), tregno);
13139       endregno = end_hard_regno (GET_MODE (x), regno);
13140
13141       return endregno > tregno && regno < endtregno;
13142     }
13143
13144   else if (GET_CODE (body) == PARALLEL)
13145     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13146       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13147         return 1;
13148
13149   return 0;
13150 }
13151 \f
13152 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13153    as appropriate.  I3 and I2 are the insns resulting from the combination
13154    insns including FROM (I2 may be zero).
13155
13156    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13157    not need REG_DEAD notes because they are being substituted for.  This
13158    saves searching in the most common cases.
13159
13160    Each note in the list is either ignored or placed on some insns, depending
13161    on the type of note.  */
13162
13163 static void
13164 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13165                   rtx elim_i1, rtx elim_i0)
13166 {
13167   rtx note, next_note;
13168   rtx tem;
13169
13170   for (note = notes; note; note = next_note)
13171     {
13172       rtx place = 0, place2 = 0;
13173
13174       next_note = XEXP (note, 1);
13175       switch (REG_NOTE_KIND (note))
13176         {
13177         case REG_BR_PROB:
13178         case REG_BR_PRED:
13179           /* Doesn't matter much where we put this, as long as it's somewhere.
13180              It is preferable to keep these notes on branches, which is most
13181              likely to be i3.  */
13182           place = i3;
13183           break;
13184
13185         case REG_NON_LOCAL_GOTO:
13186           if (JUMP_P (i3))
13187             place = i3;
13188           else
13189             {
13190               gcc_assert (i2 && JUMP_P (i2));
13191               place = i2;
13192             }
13193           break;
13194
13195         case REG_EH_REGION:
13196           /* These notes must remain with the call or trapping instruction.  */
13197           if (CALL_P (i3))
13198             place = i3;
13199           else if (i2 && CALL_P (i2))
13200             place = i2;
13201           else
13202             {
13203               gcc_assert (cfun->can_throw_non_call_exceptions);
13204               if (may_trap_p (i3))
13205                 place = i3;
13206               else if (i2 && may_trap_p (i2))
13207                 place = i2;
13208               /* ??? Otherwise assume we've combined things such that we
13209                  can now prove that the instructions can't trap.  Drop the
13210                  note in this case.  */
13211             }
13212           break;
13213
13214         case REG_ARGS_SIZE:
13215           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13216              entire adjustment.  Assert i3 contains at least some adjust.  */
13217           if (!noop_move_p (i3))
13218             {
13219               int old_size, args_size = INTVAL (XEXP (note, 0));
13220               /* fixup_args_size_notes looks at REG_NORETURN note,
13221                  so ensure the note is placed there first.  */
13222               if (CALL_P (i3))
13223                 {
13224                   rtx *np;
13225                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13226                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13227                       {
13228                         rtx n = *np;
13229                         *np = XEXP (n, 1);
13230                         XEXP (n, 1) = REG_NOTES (i3);
13231                         REG_NOTES (i3) = n;
13232                         break;
13233                       }
13234                 }
13235               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13236               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13237                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13238               gcc_assert (old_size != args_size
13239                           || (CALL_P (i3)
13240                               && !ACCUMULATE_OUTGOING_ARGS
13241                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13242             }
13243           break;
13244
13245         case REG_NORETURN:
13246         case REG_SETJMP:
13247         case REG_TM:
13248           /* These notes must remain with the call.  It should not be
13249              possible for both I2 and I3 to be a call.  */
13250           if (CALL_P (i3))
13251             place = i3;
13252           else
13253             {
13254               gcc_assert (i2 && CALL_P (i2));
13255               place = i2;
13256             }
13257           break;
13258
13259         case REG_UNUSED:
13260           /* Any clobbers for i3 may still exist, and so we must process
13261              REG_UNUSED notes from that insn.
13262
13263              Any clobbers from i2 or i1 can only exist if they were added by
13264              recog_for_combine.  In that case, recog_for_combine created the
13265              necessary REG_UNUSED notes.  Trying to keep any original
13266              REG_UNUSED notes from these insns can cause incorrect output
13267              if it is for the same register as the original i3 dest.
13268              In that case, we will notice that the register is set in i3,
13269              and then add a REG_UNUSED note for the destination of i3, which
13270              is wrong.  However, it is possible to have REG_UNUSED notes from
13271              i2 or i1 for register which were both used and clobbered, so
13272              we keep notes from i2 or i1 if they will turn into REG_DEAD
13273              notes.  */
13274
13275           /* If this register is set or clobbered in I3, put the note there
13276              unless there is one already.  */
13277           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13278             {
13279               if (from_insn != i3)
13280                 break;
13281
13282               if (! (REG_P (XEXP (note, 0))
13283                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13284                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13285                 place = i3;
13286             }
13287           /* Otherwise, if this register is used by I3, then this register
13288              now dies here, so we must put a REG_DEAD note here unless there
13289              is one already.  */
13290           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13291                    && ! (REG_P (XEXP (note, 0))
13292                          ? find_regno_note (i3, REG_DEAD,
13293                                             REGNO (XEXP (note, 0)))
13294                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13295             {
13296               PUT_REG_NOTE_KIND (note, REG_DEAD);
13297               place = i3;
13298             }
13299           break;
13300
13301         case REG_EQUAL:
13302         case REG_EQUIV:
13303         case REG_NOALIAS:
13304           /* These notes say something about results of an insn.  We can
13305              only support them if they used to be on I3 in which case they
13306              remain on I3.  Otherwise they are ignored.
13307
13308              If the note refers to an expression that is not a constant, we
13309              must also ignore the note since we cannot tell whether the
13310              equivalence is still true.  It might be possible to do
13311              slightly better than this (we only have a problem if I2DEST
13312              or I1DEST is present in the expression), but it doesn't
13313              seem worth the trouble.  */
13314
13315           if (from_insn == i3
13316               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13317             place = i3;
13318           break;
13319
13320         case REG_INC:
13321           /* These notes say something about how a register is used.  They must
13322              be present on any use of the register in I2 or I3.  */
13323           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13324             place = i3;
13325
13326           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13327             {
13328               if (place)
13329                 place2 = i2;
13330               else
13331                 place = i2;
13332             }
13333           break;
13334
13335         case REG_LABEL_TARGET:
13336         case REG_LABEL_OPERAND:
13337           /* This can show up in several ways -- either directly in the
13338              pattern, or hidden off in the constant pool with (or without?)
13339              a REG_EQUAL note.  */
13340           /* ??? Ignore the without-reg_equal-note problem for now.  */
13341           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13342               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13343                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13344                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13345             place = i3;
13346
13347           if (i2
13348               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13349                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13350                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13351                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13352             {
13353               if (place)
13354                 place2 = i2;
13355               else
13356                 place = i2;
13357             }
13358
13359           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13360              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13361              there.  */
13362           if (place && JUMP_P (place)
13363               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13364               && (JUMP_LABEL (place) == NULL
13365                   || JUMP_LABEL (place) == XEXP (note, 0)))
13366             {
13367               rtx label = JUMP_LABEL (place);
13368
13369               if (!label)
13370                 JUMP_LABEL (place) = XEXP (note, 0);
13371               else if (LABEL_P (label))
13372                 LABEL_NUSES (label)--;
13373             }
13374
13375           if (place2 && JUMP_P (place2)
13376               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13377               && (JUMP_LABEL (place2) == NULL
13378                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13379             {
13380               rtx label = JUMP_LABEL (place2);
13381
13382               if (!label)
13383                 JUMP_LABEL (place2) = XEXP (note, 0);
13384               else if (LABEL_P (label))
13385                 LABEL_NUSES (label)--;
13386               place2 = 0;
13387             }
13388           break;
13389
13390         case REG_NONNEG:
13391           /* This note says something about the value of a register prior
13392              to the execution of an insn.  It is too much trouble to see
13393              if the note is still correct in all situations.  It is better
13394              to simply delete it.  */
13395           break;
13396
13397         case REG_DEAD:
13398           /* If we replaced the right hand side of FROM_INSN with a
13399              REG_EQUAL note, the original use of the dying register
13400              will not have been combined into I3 and I2.  In such cases,
13401              FROM_INSN is guaranteed to be the first of the combined
13402              instructions, so we simply need to search back before
13403              FROM_INSN for the previous use or set of this register,
13404              then alter the notes there appropriately.
13405
13406              If the register is used as an input in I3, it dies there.
13407              Similarly for I2, if it is nonzero and adjacent to I3.
13408
13409              If the register is not used as an input in either I3 or I2
13410              and it is not one of the registers we were supposed to eliminate,
13411              there are two possibilities.  We might have a non-adjacent I2
13412              or we might have somehow eliminated an additional register
13413              from a computation.  For example, we might have had A & B where
13414              we discover that B will always be zero.  In this case we will
13415              eliminate the reference to A.
13416
13417              In both cases, we must search to see if we can find a previous
13418              use of A and put the death note there.  */
13419
13420           if (from_insn
13421               && from_insn == i2mod
13422               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13423             tem = from_insn;
13424           else
13425             {
13426               if (from_insn
13427                   && CALL_P (from_insn)
13428                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13429                 place = from_insn;
13430               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13431                 place = i3;
13432               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13433                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13434                 place = i2;
13435               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13436                         && !(i2mod
13437                              && reg_overlap_mentioned_p (XEXP (note, 0),
13438                                                          i2mod_old_rhs)))
13439                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13440                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13441                 break;
13442               tem = i3;
13443             }
13444
13445           if (place == 0)
13446             {
13447               basic_block bb = this_basic_block;
13448
13449               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13450                 {
13451                   if (!NONDEBUG_INSN_P (tem))
13452                     {
13453                       if (tem == BB_HEAD (bb))
13454                         break;
13455                       continue;
13456                     }
13457
13458                   /* If the register is being set at TEM, see if that is all
13459                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13460                      into a REG_UNUSED note instead. Don't delete sets to
13461                      global register vars.  */
13462                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13463                        || !global_regs[REGNO (XEXP (note, 0))])
13464                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13465                     {
13466                       rtx set = single_set (tem);
13467                       rtx inner_dest = 0;
13468 #ifdef HAVE_cc0
13469                       rtx cc0_setter = NULL_RTX;
13470 #endif
13471
13472                       if (set != 0)
13473                         for (inner_dest = SET_DEST (set);
13474                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13475                               || GET_CODE (inner_dest) == SUBREG
13476                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13477                              inner_dest = XEXP (inner_dest, 0))
13478                           ;
13479
13480                       /* Verify that it was the set, and not a clobber that
13481                          modified the register.
13482
13483                          CC0 targets must be careful to maintain setter/user
13484                          pairs.  If we cannot delete the setter due to side
13485                          effects, mark the user with an UNUSED note instead
13486                          of deleting it.  */
13487
13488                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13489                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13490 #ifdef HAVE_cc0
13491                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13492                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13493                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13494 #endif
13495                           )
13496                         {
13497                           /* Move the notes and links of TEM elsewhere.
13498                              This might delete other dead insns recursively.
13499                              First set the pattern to something that won't use
13500                              any register.  */
13501                           rtx old_notes = REG_NOTES (tem);
13502
13503                           PATTERN (tem) = pc_rtx;
13504                           REG_NOTES (tem) = NULL;
13505
13506                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13507                                             NULL_RTX, NULL_RTX, NULL_RTX);
13508                           distribute_links (LOG_LINKS (tem));
13509
13510                           SET_INSN_DELETED (tem);
13511                           if (tem == i2)
13512                             i2 = NULL_RTX;
13513
13514 #ifdef HAVE_cc0
13515                           /* Delete the setter too.  */
13516                           if (cc0_setter)
13517                             {
13518                               PATTERN (cc0_setter) = pc_rtx;
13519                               old_notes = REG_NOTES (cc0_setter);
13520                               REG_NOTES (cc0_setter) = NULL;
13521
13522                               distribute_notes (old_notes, cc0_setter,
13523                                                 cc0_setter, NULL_RTX,
13524                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13525                               distribute_links (LOG_LINKS (cc0_setter));
13526
13527                               SET_INSN_DELETED (cc0_setter);
13528                               if (cc0_setter == i2)
13529                                 i2 = NULL_RTX;
13530                             }
13531 #endif
13532                         }
13533                       else
13534                         {
13535                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13536
13537                           /*  If there isn't already a REG_UNUSED note, put one
13538                               here.  Do not place a REG_DEAD note, even if
13539                               the register is also used here; that would not
13540                               match the algorithm used in lifetime analysis
13541                               and can cause the consistency check in the
13542                               scheduler to fail.  */
13543                           if (! find_regno_note (tem, REG_UNUSED,
13544                                                  REGNO (XEXP (note, 0))))
13545                             place = tem;
13546                           break;
13547                         }
13548                     }
13549                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13550                            || (CALL_P (tem)
13551                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13552                     {
13553                       place = tem;
13554
13555                       /* If we are doing a 3->2 combination, and we have a
13556                          register which formerly died in i3 and was not used
13557                          by i2, which now no longer dies in i3 and is used in
13558                          i2 but does not die in i2, and place is between i2
13559                          and i3, then we may need to move a link from place to
13560                          i2.  */
13561                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13562                           && from_insn
13563                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13564                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13565                         {
13566                           struct insn_link *links = LOG_LINKS (place);
13567                           LOG_LINKS (place) = NULL;
13568                           distribute_links (links);
13569                         }
13570                       break;
13571                     }
13572
13573                   if (tem == BB_HEAD (bb))
13574                     break;
13575                 }
13576
13577             }
13578
13579           /* If the register is set or already dead at PLACE, we needn't do
13580              anything with this note if it is still a REG_DEAD note.
13581              We check here if it is set at all, not if is it totally replaced,
13582              which is what `dead_or_set_p' checks, so also check for it being
13583              set partially.  */
13584
13585           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13586             {
13587               unsigned int regno = REGNO (XEXP (note, 0));
13588               reg_stat_type *rsp = &reg_stat[regno];
13589
13590               if (dead_or_set_p (place, XEXP (note, 0))
13591                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13592                 {
13593                   /* Unless the register previously died in PLACE, clear
13594                      last_death.  [I no longer understand why this is
13595                      being done.] */
13596                   if (rsp->last_death != place)
13597                     rsp->last_death = 0;
13598                   place = 0;
13599                 }
13600               else
13601                 rsp->last_death = place;
13602
13603               /* If this is a death note for a hard reg that is occupying
13604                  multiple registers, ensure that we are still using all
13605                  parts of the object.  If we find a piece of the object
13606                  that is unused, we must arrange for an appropriate REG_DEAD
13607                  note to be added for it.  However, we can't just emit a USE
13608                  and tag the note to it, since the register might actually
13609                  be dead; so we recourse, and the recursive call then finds
13610                  the previous insn that used this register.  */
13611
13612               if (place && regno < FIRST_PSEUDO_REGISTER
13613                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13614                 {
13615                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13616                   bool all_used = true;
13617                   unsigned int i;
13618
13619                   for (i = regno; i < endregno; i++)
13620                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13621                          && ! find_regno_fusage (place, USE, i))
13622                         || dead_or_set_regno_p (place, i))
13623                       {
13624                         all_used = false;
13625                         break;
13626                       }
13627
13628                   if (! all_used)
13629                     {
13630                       /* Put only REG_DEAD notes for pieces that are
13631                          not already dead or set.  */
13632
13633                       for (i = regno; i < endregno;
13634                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13635                         {
13636                           rtx piece = regno_reg_rtx[i];
13637                           basic_block bb = this_basic_block;
13638
13639                           if (! dead_or_set_p (place, piece)
13640                               && ! reg_bitfield_target_p (piece,
13641                                                           PATTERN (place)))
13642                             {
13643                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13644                                                              NULL_RTX);
13645
13646                               distribute_notes (new_note, place, place,
13647                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13648                                                 NULL_RTX);
13649                             }
13650                           else if (! refers_to_regno_p (i, i + 1,
13651                                                         PATTERN (place), 0)
13652                                    && ! find_regno_fusage (place, USE, i))
13653                             for (tem = PREV_INSN (place); ;
13654                                  tem = PREV_INSN (tem))
13655                               {
13656                                 if (!NONDEBUG_INSN_P (tem))
13657                                   {
13658                                     if (tem == BB_HEAD (bb))
13659                                       break;
13660                                     continue;
13661                                   }
13662                                 if (dead_or_set_p (tem, piece)
13663                                     || reg_bitfield_target_p (piece,
13664                                                               PATTERN (tem)))
13665                                   {
13666                                     add_reg_note (tem, REG_UNUSED, piece);
13667                                     break;
13668                                   }
13669                               }
13670                         }
13671
13672                       place = 0;
13673                     }
13674                 }
13675             }
13676           break;
13677
13678         default:
13679           /* Any other notes should not be present at this point in the
13680              compilation.  */
13681           gcc_unreachable ();
13682         }
13683
13684       if (place)
13685         {
13686           XEXP (note, 1) = REG_NOTES (place);
13687           REG_NOTES (place) = note;
13688         }
13689
13690       if (place2)
13691         add_shallow_copy_of_reg_note (place2, note);
13692     }
13693 }
13694 \f
13695 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13696    I3, I2, and I1 to new locations.  This is also called to add a link
13697    pointing at I3 when I3's destination is changed.  */
13698
13699 static void
13700 distribute_links (struct insn_link *links)
13701 {
13702   struct insn_link *link, *next_link;
13703
13704   for (link = links; link; link = next_link)
13705     {
13706       rtx place = 0;
13707       rtx insn;
13708       rtx set, reg;
13709
13710       next_link = link->next;
13711
13712       /* If the insn that this link points to is a NOTE or isn't a single
13713          set, ignore it.  In the latter case, it isn't clear what we
13714          can do other than ignore the link, since we can't tell which
13715          register it was for.  Such links wouldn't be used by combine
13716          anyway.
13717
13718          It is not possible for the destination of the target of the link to
13719          have been changed by combine.  The only potential of this is if we
13720          replace I3, I2, and I1 by I3 and I2.  But in that case the
13721          destination of I2 also remains unchanged.  */
13722
13723       if (NOTE_P (link->insn)
13724           || (set = single_set (link->insn)) == 0)
13725         continue;
13726
13727       reg = SET_DEST (set);
13728       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13729              || GET_CODE (reg) == STRICT_LOW_PART)
13730         reg = XEXP (reg, 0);
13731
13732       /* A LOG_LINK is defined as being placed on the first insn that uses
13733          a register and points to the insn that sets the register.  Start
13734          searching at the next insn after the target of the link and stop
13735          when we reach a set of the register or the end of the basic block.
13736
13737          Note that this correctly handles the link that used to point from
13738          I3 to I2.  Also note that not much searching is typically done here
13739          since most links don't point very far away.  */
13740
13741       for (insn = NEXT_INSN (link->insn);
13742            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13743                      || BB_HEAD (this_basic_block->next_bb) != insn));
13744            insn = NEXT_INSN (insn))
13745         if (DEBUG_INSN_P (insn))
13746           continue;
13747         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13748           {
13749             if (reg_referenced_p (reg, PATTERN (insn)))
13750               place = insn;
13751             break;
13752           }
13753         else if (CALL_P (insn)
13754                  && find_reg_fusage (insn, USE, reg))
13755           {
13756             place = insn;
13757             break;
13758           }
13759         else if (INSN_P (insn) && reg_set_p (reg, insn))
13760           break;
13761
13762       /* If we found a place to put the link, place it there unless there
13763          is already a link to the same insn as LINK at that point.  */
13764
13765       if (place)
13766         {
13767           struct insn_link *link2;
13768
13769           FOR_EACH_LOG_LINK (link2, place)
13770             if (link2->insn == link->insn)
13771               break;
13772
13773           if (link2 == NULL)
13774             {
13775               link->next = LOG_LINKS (place);
13776               LOG_LINKS (place) = link;
13777
13778               /* Set added_links_insn to the earliest insn we added a
13779                  link to.  */
13780               if (added_links_insn == 0
13781                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13782                 added_links_insn = place;
13783             }
13784         }
13785     }
13786 }
13787 \f
13788 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13789    Check whether the expression pointer to by LOC is a register or
13790    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13791    Otherwise return zero.  */
13792
13793 static int
13794 unmentioned_reg_p_1 (rtx *loc, void *expr)
13795 {
13796   rtx x = *loc;
13797
13798   if (x != NULL_RTX
13799       && (REG_P (x) || MEM_P (x))
13800       && ! reg_mentioned_p (x, (rtx) expr))
13801     return 1;
13802   return 0;
13803 }
13804
13805 /* Check for any register or memory mentioned in EQUIV that is not
13806    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13807    of EXPR where some registers may have been replaced by constants.  */
13808
13809 static bool
13810 unmentioned_reg_p (rtx equiv, rtx expr)
13811 {
13812   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13813 }
13814 \f
13815 DEBUG_FUNCTION void
13816 dump_combine_stats (FILE *file)
13817 {
13818   fprintf
13819     (file,
13820      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13821      combine_attempts, combine_merges, combine_extras, combine_successes);
13822 }
13823
13824 void
13825 dump_combine_total_stats (FILE *file)
13826 {
13827   fprintf
13828     (file,
13829      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13830      total_attempts, total_merges, total_extras, total_successes);
13831 }
13832 \f
13833 static bool
13834 gate_handle_combine (void)
13835 {
13836   return (optimize > 0);
13837 }
13838
13839 /* Try combining insns through substitution.  */
13840 static unsigned int
13841 rest_of_handle_combine (void)
13842 {
13843   int rebuild_jump_labels_after_combine;
13844
13845   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13846   df_note_add_problem ();
13847   df_analyze ();
13848
13849   regstat_init_n_sets_and_refs ();
13850
13851   rebuild_jump_labels_after_combine
13852     = combine_instructions (get_insns (), max_reg_num ());
13853
13854   /* Combining insns may have turned an indirect jump into a
13855      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13856      instructions.  */
13857   if (rebuild_jump_labels_after_combine)
13858     {
13859       timevar_push (TV_JUMP);
13860       rebuild_jump_labels (get_insns ());
13861       cleanup_cfg (0);
13862       timevar_pop (TV_JUMP);
13863     }
13864
13865   regstat_free_n_sets_and_refs ();
13866   return 0;
13867 }
13868
13869 namespace {
13870
13871 const pass_data pass_data_combine =
13872 {
13873   RTL_PASS, /* type */
13874   "combine", /* name */
13875   OPTGROUP_NONE, /* optinfo_flags */
13876   true, /* has_gate */
13877   true, /* has_execute */
13878   TV_COMBINE, /* tv_id */
13879   PROP_cfglayout, /* properties_required */
13880   0, /* properties_provided */
13881   0, /* properties_destroyed */
13882   0, /* todo_flags_start */
13883   ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
13884 };
13885
13886 class pass_combine : public rtl_opt_pass
13887 {
13888 public:
13889   pass_combine (gcc::context *ctxt)
13890     : rtl_opt_pass (pass_data_combine, ctxt)
13891   {}
13892
13893   /* opt_pass methods: */
13894   bool gate () { return gate_handle_combine (); }
13895   unsigned int execute () { return rest_of_handle_combine (); }
13896
13897 }; // class pass_combine
13898
13899 } // anon namespace
13900
13901 rtl_opt_pass *
13902 make_pass_combine (gcc::context *ctxt)
13903 {
13904   return new pass_combine (ctxt);
13905 }