1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; Q -- Memory reference without index register and with short displacement.
51 ;; R -- Memory reference with index register and short displacement.
52 ;; S -- Memory reference without index register but with long displacement.
53 ;; T -- Memory reference with index register and long displacement.
54 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
55 ;; Offsettable memory reference of type specified by second letter.
56 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
57 ;; Memory reference of the type specified by second letter that
58 ;; does *not* refer to a literal pool entry.
59 ;; U -- Pointer with short displacement.
60 ;; W -- Pointer with long displacement.
61 ;; Y -- Shift count operand.
63 ;; Special formats used for outputting 390 instructions.
65 ;; %C: print opcode suffix for branch condition.
66 ;; %D: print opcode suffix for inverse branch condition.
67 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
68 ;; %O: print only the displacement of a memory reference.
69 ;; %R: print only the base register of a memory reference.
70 ;; %S: print S-type memory reference (base+displacement).
71 ;; %N: print the second word of a DImode operand.
72 ;; %M: print the second word of a TImode operand.
74 ;; %b: print integer X as if it's an unsigned byte.
75 ;; %x: print integer X as if it's an unsigned word.
76 ;; %h: print integer X as if it's a signed word.
77 ;; %i: print the first nonzero HImode part of X
78 ;; %j: print the first HImode part unequal to 0xffff of X
81 ;; We have a special constraint for pattern matching.
83 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
96 ; GOT/PLT and lt-relative accesses
97 (UNSPEC_LTREL_OFFSET 100)
98 (UNSPEC_LTREL_BASE 101)
106 (UNSPEC_RELOAD_BASE 210)
107 (UNSPEC_MAIN_BASE 211)
112 ; TLS relocation specifiers
117 (UNSPEC_GOTNTPOFF 504)
118 (UNSPEC_INDNTPOFF 505)
121 (UNSPEC_TLSLDM_NTPOFF 511)
122 (UNSPEC_TLS_LOAD 512)
129 ;; UNSPEC_VOLATILE usage
137 (UNSPECV_TPF_PROLOGUE 20)
138 (UNSPECV_TPF_EPILOGUE 21)
142 (UNSPECV_POOL_SECTION 201)
143 (UNSPECV_POOL_ALIGN 202)
144 (UNSPECV_POOL_ENTRY 203)
145 (UNSPECV_MAIN_POOL 300)
161 ; Sibling call register.
163 ; Literal pool base register.
165 ; Return address register.
167 ; Condition code register.
169 ; Thread local storage pointer register.
174 ;; Instruction operand type as used in the Principles of Operation.
175 ;; Used to determine defaults for length and other attribute values.
177 (define_attr "op_type"
178 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
181 ;; Instruction type attribute used for scheduling.
183 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
184 cs,vs,store,sem,idiv,
185 imulhi,imulsi,imuldi,
186 branch,jsr,fsimpdf,fsimpsf,
187 floaddf,floadsf,fstoredf,fstoresf,
188 fmuldf,fmulsf,fdivdf,fdivsf,
189 ftoi,itof,fsqrtdf,fsqrtsf,
191 (cond [(eq_attr "op_type" "NN") (const_string "other")
192 (eq_attr "op_type" "SS") (const_string "cs")]
193 (const_string "integer")))
195 ;; Another attribute used for scheduling purposes:
196 ;; agen: Instruction uses the address generation unit
197 ;; reg: Instruction does not use the agen unit
199 (define_attr "atype" "agen,reg"
200 (cond [(eq_attr "op_type" "E") (const_string "reg")
201 (eq_attr "op_type" "RR") (const_string "reg")
202 (eq_attr "op_type" "RX") (const_string "agen")
203 (eq_attr "op_type" "RI") (const_string "reg")
204 (eq_attr "op_type" "RRE") (const_string "reg")
205 (eq_attr "op_type" "RS") (const_string "agen")
206 (eq_attr "op_type" "RSI") (const_string "agen")
207 (eq_attr "op_type" "S") (const_string "agen")
208 (eq_attr "op_type" "SI") (const_string "agen")
209 (eq_attr "op_type" "SS") (const_string "agen")
210 (eq_attr "op_type" "SSE") (const_string "agen")
211 (eq_attr "op_type" "RXE") (const_string "agen")
212 (eq_attr "op_type" "RSE") (const_string "agen")
213 (eq_attr "op_type" "RIL") (const_string "agen")
214 (eq_attr "op_type" "RXY") (const_string "agen")
215 (eq_attr "op_type" "RSY") (const_string "agen")
216 (eq_attr "op_type" "SIY") (const_string "agen")]
217 (const_string "agen")))
221 (define_attr "length" ""
222 (cond [(eq_attr "op_type" "E") (const_int 2)
223 (eq_attr "op_type" "RR") (const_int 2)
224 (eq_attr "op_type" "RX") (const_int 4)
225 (eq_attr "op_type" "RI") (const_int 4)
226 (eq_attr "op_type" "RRE") (const_int 4)
227 (eq_attr "op_type" "RS") (const_int 4)
228 (eq_attr "op_type" "RSI") (const_int 4)
229 (eq_attr "op_type" "S") (const_int 4)
230 (eq_attr "op_type" "SI") (const_int 4)
231 (eq_attr "op_type" "SS") (const_int 6)
232 (eq_attr "op_type" "SSE") (const_int 6)
233 (eq_attr "op_type" "RXE") (const_int 6)
234 (eq_attr "op_type" "RSE") (const_int 6)
235 (eq_attr "op_type" "RIL") (const_int 6)
236 (eq_attr "op_type" "RXY") (const_int 6)
237 (eq_attr "op_type" "RSY") (const_int 6)
238 (eq_attr "op_type" "SIY") (const_int 6)]
242 ;; Processor type. This attribute must exactly match the processor_type
243 ;; enumeration in s390.h. The current machine description does not
244 ;; distinguish between g5 and g6, but there are differences between the two
245 ;; CPUs could in theory be modeled.
247 (define_attr "cpu" "g5,g6,z900,z990"
248 (const (symbol_ref "s390_tune")))
250 ;; Pipeline description for z900. For lack of anything better,
251 ;; this description is also used for the g5 and g6.
254 ;; Pipeline description for z990.
258 (include "predicates.md")
263 ;; This mode macro allows DF and SF patterns to be generated from the
265 (define_mode_macro FPR [DF SF])
267 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
268 ;; from the same template.
269 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
270 (define_mode_macro DSI [DI SI])
272 ;; This mode macro allows :P to be used for patterns that operate on
273 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
274 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
276 ;; This mode macro allows the QI and HI patterns to be defined from
277 ;; the same template.
278 (define_mode_macro HQI [HI QI])
280 ;; This mode macro allows the integer patterns to be defined from the
282 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
284 ;; This macro allows to unify all 'bCOND' expander patterns.
285 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
286 ordered uneq unlt ungt unle unge ltgt])
288 ;; This macro allows to unify all 'sCOND' patterns.
289 (define_code_macro SCOND [ltu gtu leu geu])
291 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
292 ;; the same template.
293 (define_code_macro SHIFT [ashift lshiftrt])
296 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
297 ;; and "ltebr" in SFmode.
298 (define_mode_attr de [(DF "d") (SF "e")])
300 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
301 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
302 (define_mode_attr dee [(DF "d") (SF "ee")])
304 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
305 ;; 'ashift' and "srdl" in 'lshiftrt'.
306 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
308 ;; In SHIFT templates, this attribute holds the correct standard name for the
309 ;; pattern itself and the corresponding function calls.
310 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
312 ;; This attribute handles differences in the instruction 'type' and will result
313 ;; in "RRE" for DImode and "RR" for SImode.
314 (define_mode_attr E [(DI "E") (SI "")])
316 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
317 ;; and "lcr" in SImode.
318 (define_mode_attr g [(DI "g") (SI "")])
320 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
321 ;; and "cfdbr" in SImode.
322 (define_mode_attr gf [(DI "g") (SI "f")])
324 ;; ICM mask required to load MODE value into the highest subreg
325 ;; of a SImode register.
326 (define_mode_attr icm_hi [(HI "12") (QI "8")])
328 ;; ICM mask required to load MODE value into the lowest subreg
329 ;; of a SImode register.
330 (define_mode_attr icm_lo [(HI "3") (QI "1")])
332 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
333 ;; HImode and "llgc" in QImode.
334 (define_mode_attr hc [(HI "h") (QI "c")])
336 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
338 (define_mode_attr DBL [(DI "TI") (SI "DI")])
340 ;; Maximum unsigned integer that fits in MODE.
341 (define_mode_attr max_uint [(HI "65535") (QI "255")])
345 ;;- Compare instructions.
348 (define_expand "cmp<mode>"
349 [(set (reg:CC CC_REGNUM)
350 (compare:CC (match_operand:GPR 0 "register_operand" "")
351 (match_operand:GPR 1 "general_operand" "")))]
354 s390_compare_op0 = operands[0];
355 s390_compare_op1 = operands[1];
359 (define_expand "cmp<mode>"
360 [(set (reg:CC CC_REGNUM)
361 (compare:CC (match_operand:FPR 0 "register_operand" "")
362 (match_operand:FPR 1 "general_operand" "")))]
365 s390_compare_op0 = operands[0];
366 s390_compare_op1 = operands[1];
371 ; Test-under-Mask instructions
373 (define_insn "*tmqi_mem"
374 [(set (reg CC_REGNUM)
375 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
376 (match_operand:QI 1 "immediate_operand" "n,n"))
377 (match_operand:QI 2 "immediate_operand" "n,n")))]
378 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
382 [(set_attr "op_type" "SI,SIY")])
384 (define_insn "*tmdi_reg"
385 [(set (reg CC_REGNUM)
386 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
387 (match_operand:DI 1 "immediate_operand"
388 "N0HD0,N1HD0,N2HD0,N3HD0"))
389 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
391 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
392 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
398 [(set_attr "op_type" "RI")])
400 (define_insn "*tmsi_reg"
401 [(set (reg CC_REGNUM)
402 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
403 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
404 (match_operand:SI 2 "immediate_operand" "n,n")))]
405 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
406 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
410 [(set_attr "op_type" "RI")])
412 (define_insn "*tm<mode>_full"
413 [(set (reg CC_REGNUM)
414 (compare (match_operand:HQI 0 "register_operand" "d")
415 (match_operand:HQI 1 "immediate_operand" "n")))]
416 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
418 [(set_attr "op_type" "RI")])
421 ; Load-and-Test instructions
423 (define_insn "*tstdi_sign"
424 [(set (reg CC_REGNUM)
425 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
426 (const_int 32)) (const_int 32))
427 (match_operand:DI 1 "const0_operand" "")))
428 (set (match_operand:DI 2 "register_operand" "=d")
429 (sign_extend:DI (match_dup 0)))]
430 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
432 [(set_attr "op_type" "RRE")])
434 (define_insn "*tstdi"
435 [(set (reg CC_REGNUM)
436 (compare (match_operand:DI 0 "register_operand" "d")
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi_cconly"
445 [(set (reg CC_REGNUM)
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))]
448 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
450 [(set_attr "op_type" "RRE")])
452 (define_insn "*tstdi_cconly_31"
453 [(set (reg CC_REGNUM)
454 (compare (match_operand:DI 0 "register_operand" "d")
455 (match_operand:DI 1 "const0_operand" "")))]
456 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
458 [(set_attr "op_type" "RS")
459 (set_attr "atype" "reg")])
462 (define_insn "*tstsi"
463 [(set (reg CC_REGNUM)
464 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
465 (match_operand:SI 1 "const0_operand" "")))
466 (set (match_operand:SI 2 "register_operand" "=d,d,d")
468 "s390_match_ccmode(insn, CCSmode)"
473 [(set_attr "op_type" "RR,RS,RSY")])
475 (define_insn "*tstsi_cconly"
476 [(set (reg CC_REGNUM)
477 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
478 (match_operand:SI 1 "const0_operand" "")))
479 (clobber (match_scratch:SI 2 "=X,d,d"))]
480 "s390_match_ccmode(insn, CCSmode)"
485 [(set_attr "op_type" "RR,RS,RSY")])
487 (define_insn "*tstsi_cconly2"
488 [(set (reg CC_REGNUM)
489 (compare (match_operand:SI 0 "register_operand" "d")
490 (match_operand:SI 1 "const0_operand" "")))]
491 "s390_match_ccmode(insn, CCSmode)"
493 [(set_attr "op_type" "RR")])
495 (define_insn "*tst<mode>CCT"
496 [(set (reg CC_REGNUM)
497 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
498 (match_operand:HQI 1 "const0_operand" "")))
499 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
501 "s390_match_ccmode(insn, CCTmode)"
504 icmy\t%2,<icm_lo>,%S0
506 [(set_attr "op_type" "RS,RSY,RI")])
508 (define_insn "*tsthiCCT_cconly"
509 [(set (reg CC_REGNUM)
510 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
511 (match_operand:HI 1 "const0_operand" "")))
512 (clobber (match_scratch:HI 2 "=d,d,X"))]
513 "s390_match_ccmode(insn, CCTmode)"
518 [(set_attr "op_type" "RS,RSY,RI")])
520 (define_insn "*tstqiCCT_cconly"
521 [(set (reg CC_REGNUM)
522 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
523 (match_operand:QI 1 "const0_operand" "")))]
524 "s390_match_ccmode(insn, CCTmode)"
529 [(set_attr "op_type" "SI,SIY,RI")])
531 (define_insn "*tst<mode>"
532 [(set (reg CC_REGNUM)
533 (compare (match_operand:HQI 0 "s_operand" "Q,S")
534 (match_operand:HQI 1 "const0_operand" "")))
535 (set (match_operand:HQI 2 "register_operand" "=d,d")
537 "s390_match_ccmode(insn, CCSmode)"
540 icmy\t%2,<icm_lo>,%S0"
541 [(set_attr "op_type" "RS,RSY")])
543 (define_insn "*tst<mode>_cconly"
544 [(set (reg CC_REGNUM)
545 (compare (match_operand:HQI 0 "s_operand" "Q,S")
546 (match_operand:HQI 1 "const0_operand" "")))
547 (clobber (match_scratch:HQI 2 "=d,d"))]
548 "s390_match_ccmode(insn, CCSmode)"
551 icmy\t%2,<icm_lo>,%S0"
552 [(set_attr "op_type" "RS,RSY")])
555 ; Compare (equality) instructions
557 (define_insn "*cmpdi_cct"
558 [(set (reg CC_REGNUM)
559 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
560 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
561 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
567 [(set_attr "op_type" "RRE,RI,RXY,SS")])
569 (define_insn "*cmpsi_cct"
570 [(set (reg CC_REGNUM)
571 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
572 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
573 "s390_match_ccmode (insn, CCTmode)"
580 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
583 ; Compare (signed) instructions
585 (define_insn "*cmpdi_ccs_sign"
586 [(set (reg CC_REGNUM)
587 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
588 (match_operand:DI 0 "register_operand" "d,d")))]
589 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
593 [(set_attr "op_type" "RRE,RXY")])
595 (define_insn "*cmpdi_ccs"
596 [(set (reg CC_REGNUM)
597 (compare (match_operand:DI 0 "register_operand" "d,d,d")
598 (match_operand:DI 1 "general_operand" "d,K,m")))]
599 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
604 [(set_attr "op_type" "RRE,RI,RXY")])
606 (define_insn "*cmpsi_ccs_sign"
607 [(set (reg CC_REGNUM)
608 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
609 (match_operand:SI 0 "register_operand" "d,d")))]
610 "s390_match_ccmode(insn, CCSRmode)"
614 [(set_attr "op_type" "RX,RXY")])
616 (define_insn "*cmpsi_ccs"
617 [(set (reg CC_REGNUM)
618 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
619 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
620 "s390_match_ccmode(insn, CCSmode)"
626 [(set_attr "op_type" "RR,RI,RX,RXY")])
629 ; Compare (unsigned) instructions
631 (define_insn "*cmpdi_ccu_zero"
632 [(set (reg CC_REGNUM)
633 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
634 (match_operand:DI 0 "register_operand" "d,d")))]
635 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
639 [(set_attr "op_type" "RRE,RXY")])
641 (define_insn "*cmpdi_ccu"
642 [(set (reg CC_REGNUM)
643 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
644 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
645 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
651 [(set_attr "op_type" "RRE,RXY,SS,SS")])
653 (define_insn "*cmpsi_ccu"
654 [(set (reg CC_REGNUM)
655 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
656 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
657 "s390_match_ccmode (insn, CCUmode)"
664 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
666 (define_insn "*cmphi_ccu"
667 [(set (reg CC_REGNUM)
668 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
669 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
670 "s390_match_ccmode (insn, CCUmode)
671 && !register_operand (operands[1], HImode)"
677 [(set_attr "op_type" "RS,RSY,SS,SS")])
679 (define_insn "*cmpqi_ccu"
680 [(set (reg CC_REGNUM)
681 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
682 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
683 "s390_match_ccmode (insn, CCUmode)
684 && !register_operand (operands[1], QImode)"
692 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
695 ; Block compare (CLC) instruction patterns.
698 [(set (reg CC_REGNUM)
699 (compare (match_operand:BLK 0 "memory_operand" "Q")
700 (match_operand:BLK 1 "memory_operand" "Q")))
701 (use (match_operand 2 "const_int_operand" "n"))]
702 "s390_match_ccmode (insn, CCUmode)
703 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
704 "clc\t%O0(%2,%R0),%S1"
705 [(set_attr "op_type" "SS")])
708 [(set (reg CC_REGNUM)
709 (compare (match_operand 0 "memory_operand" "")
710 (match_operand 1 "memory_operand" "")))]
712 && s390_match_ccmode (insn, CCUmode)
713 && GET_MODE (operands[0]) == GET_MODE (operands[1])
714 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
716 [(set (match_dup 0) (match_dup 1))
717 (use (match_dup 2))])]
719 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
720 operands[0] = adjust_address (operands[0], BLKmode, 0);
721 operands[1] = adjust_address (operands[1], BLKmode, 0);
723 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
724 operands[0], operands[1]);
725 operands[0] = SET_DEST (PATTERN (curr_insn));
729 ; (DF|SF) instructions
731 (define_insn "*cmp<mode>_ccs_0"
732 [(set (reg CC_REGNUM)
733 (compare (match_operand:FPR 0 "register_operand" "f")
734 (match_operand:FPR 1 "const0_operand" "")))]
735 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
737 [(set_attr "op_type" "RRE")
738 (set_attr "type" "fsimp<mode>")])
740 (define_insn "*cmp<mode>_ccs_0_ibm"
741 [(set (reg CC_REGNUM)
742 (compare (match_operand:FPR 0 "register_operand" "f")
743 (match_operand:FPR 1 "const0_operand" "")))]
744 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
746 [(set_attr "op_type" "RR")
747 (set_attr "type" "fsimp<mode>")])
749 (define_insn "*cmp<mode>_ccs"
750 [(set (reg CC_REGNUM)
751 (compare (match_operand:FPR 0 "register_operand" "f,f")
752 (match_operand:FPR 1 "general_operand" "f,R")))]
753 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
757 [(set_attr "op_type" "RRE,RXE")
758 (set_attr "type" "fsimp<mode>")])
760 (define_insn "*cmp<mode>_ccs_ibm"
761 [(set (reg CC_REGNUM)
762 (compare (match_operand:FPR 0 "register_operand" "f,f")
763 (match_operand:FPR 1 "general_operand" "f,R")))]
764 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
768 [(set_attr "op_type" "RR,RX")
769 (set_attr "type" "fsimp<mode>")])
773 ;;- Move instructions.
777 ; movti instruction pattern(s).
781 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
782 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
790 [(set_attr "op_type" "RSY,RSY,*,*,SS")
791 (set_attr "type" "lm,stm,*,*,*")])
794 [(set (match_operand:TI 0 "nonimmediate_operand" "")
795 (match_operand:TI 1 "general_operand" ""))]
796 "TARGET_64BIT && reload_completed
797 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
798 [(set (match_dup 2) (match_dup 4))
799 (set (match_dup 3) (match_dup 5))]
801 operands[2] = operand_subword (operands[0], 0, 0, TImode);
802 operands[3] = operand_subword (operands[0], 1, 0, TImode);
803 operands[4] = operand_subword (operands[1], 0, 0, TImode);
804 operands[5] = operand_subword (operands[1], 1, 0, TImode);
808 [(set (match_operand:TI 0 "nonimmediate_operand" "")
809 (match_operand:TI 1 "general_operand" ""))]
810 "TARGET_64BIT && reload_completed
811 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
812 [(set (match_dup 2) (match_dup 4))
813 (set (match_dup 3) (match_dup 5))]
815 operands[2] = operand_subword (operands[0], 1, 0, TImode);
816 operands[3] = operand_subword (operands[0], 0, 0, TImode);
817 operands[4] = operand_subword (operands[1], 1, 0, TImode);
818 operands[5] = operand_subword (operands[1], 0, 0, TImode);
822 [(set (match_operand:TI 0 "register_operand" "")
823 (match_operand:TI 1 "memory_operand" ""))]
824 "TARGET_64BIT && reload_completed
825 && !s_operand (operands[1], VOIDmode)"
826 [(set (match_dup 0) (match_dup 1))]
828 rtx addr = operand_subword (operands[0], 1, 0, TImode);
829 s390_load_address (addr, XEXP (operands[1], 0));
830 operands[1] = replace_equiv_address (operands[1], addr);
833 (define_expand "reload_outti"
834 [(parallel [(match_operand:TI 0 "" "")
835 (match_operand:TI 1 "register_operand" "d")
836 (match_operand:DI 2 "register_operand" "=&a")])]
839 gcc_assert (MEM_P (operands[0]));
840 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
841 operands[0] = replace_equiv_address (operands[0], operands[2]);
842 emit_move_insn (operands[0], operands[1]);
847 ; movdi instruction pattern(s).
850 (define_expand "movdi"
851 [(set (match_operand:DI 0 "general_operand" "")
852 (match_operand:DI 1 "general_operand" ""))]
855 /* Handle symbolic constants. */
856 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
857 emit_symbolic_move (operands);
860 (define_insn "*movdi_larl"
861 [(set (match_operand:DI 0 "register_operand" "=d")
862 (match_operand:DI 1 "larl_operand" "X"))]
864 && !FP_REG_P (operands[0])"
866 [(set_attr "op_type" "RIL")
867 (set_attr "type" "larl")])
869 (define_insn "*movdi_64"
870 [(set (match_operand:DI 0 "nonimmediate_operand"
871 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
872 (match_operand:DI 1 "general_operand"
873 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
895 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
896 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
897 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
898 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
901 [(set (match_operand:DI 0 "register_operand" "")
902 (match_operand:DI 1 "register_operand" ""))]
903 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
904 [(set (match_dup 2) (match_dup 3))
905 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
906 (set (strict_low_part (match_dup 2)) (match_dup 4))]
907 "operands[2] = gen_lowpart (SImode, operands[0]);
908 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
911 [(set (match_operand:DI 0 "register_operand" "")
912 (match_operand:DI 1 "register_operand" ""))]
913 "TARGET_64BIT && ACCESS_REG_P (operands[0])
914 && dead_or_set_p (insn, operands[1])"
915 [(set (match_dup 3) (match_dup 2))
916 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
917 (set (match_dup 4) (match_dup 2))]
918 "operands[2] = gen_lowpart (SImode, operands[1]);
919 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
922 [(set (match_operand:DI 0 "register_operand" "")
923 (match_operand:DI 1 "register_operand" ""))]
924 "TARGET_64BIT && ACCESS_REG_P (operands[0])
925 && !dead_or_set_p (insn, operands[1])"
926 [(set (match_dup 3) (match_dup 2))
927 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
928 (set (match_dup 4) (match_dup 2))
929 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
930 "operands[2] = gen_lowpart (SImode, operands[1]);
931 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
933 (define_insn "*movdi_31"
934 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
935 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
948 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
949 (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
952 [(set (match_operand:DI 0 "nonimmediate_operand" "")
953 (match_operand:DI 1 "general_operand" ""))]
954 "!TARGET_64BIT && reload_completed
955 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
956 [(set (match_dup 2) (match_dup 4))
957 (set (match_dup 3) (match_dup 5))]
959 operands[2] = operand_subword (operands[0], 0, 0, DImode);
960 operands[3] = operand_subword (operands[0], 1, 0, DImode);
961 operands[4] = operand_subword (operands[1], 0, 0, DImode);
962 operands[5] = operand_subword (operands[1], 1, 0, DImode);
966 [(set (match_operand:DI 0 "nonimmediate_operand" "")
967 (match_operand:DI 1 "general_operand" ""))]
968 "!TARGET_64BIT && reload_completed
969 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
970 [(set (match_dup 2) (match_dup 4))
971 (set (match_dup 3) (match_dup 5))]
973 operands[2] = operand_subword (operands[0], 1, 0, DImode);
974 operands[3] = operand_subword (operands[0], 0, 0, DImode);
975 operands[4] = operand_subword (operands[1], 1, 0, DImode);
976 operands[5] = operand_subword (operands[1], 0, 0, DImode);
980 [(set (match_operand:DI 0 "register_operand" "")
981 (match_operand:DI 1 "memory_operand" ""))]
982 "!TARGET_64BIT && reload_completed
983 && !FP_REG_P (operands[0])
984 && !s_operand (operands[1], VOIDmode)"
985 [(set (match_dup 0) (match_dup 1))]
987 rtx addr = operand_subword (operands[0], 1, 0, DImode);
988 s390_load_address (addr, XEXP (operands[1], 0));
989 operands[1] = replace_equiv_address (operands[1], addr);
992 (define_expand "reload_outdi"
993 [(parallel [(match_operand:DI 0 "" "")
994 (match_operand:DI 1 "register_operand" "d")
995 (match_operand:SI 2 "register_operand" "=&a")])]
998 gcc_assert (MEM_P (operands[0]));
999 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1000 operands[0] = replace_equiv_address (operands[0], operands[2]);
1001 emit_move_insn (operands[0], operands[1]);
1006 [(set (match_operand:DI 0 "register_operand" "")
1007 (mem:DI (match_operand 1 "address_operand" "")))]
1009 && !FP_REG_P (operands[0])
1010 && GET_CODE (operands[1]) == SYMBOL_REF
1011 && CONSTANT_POOL_ADDRESS_P (operands[1])
1012 && get_pool_mode (operands[1]) == DImode
1013 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1014 [(set (match_dup 0) (match_dup 2))]
1015 "operands[2] = get_pool_constant (operands[1]);")
1017 (define_insn "*la_64"
1018 [(set (match_operand:DI 0 "register_operand" "=d,d")
1019 (match_operand:QI 1 "address_operand" "U,W"))]
1024 [(set_attr "op_type" "RX,RXY")
1025 (set_attr "type" "la")])
1029 [(set (match_operand:DI 0 "register_operand" "")
1030 (match_operand:QI 1 "address_operand" ""))
1031 (clobber (reg:CC CC_REGNUM))])]
1033 && preferred_la_operand_p (operands[1], const0_rtx)"
1034 [(set (match_dup 0) (match_dup 1))]
1038 [(set (match_operand:DI 0 "register_operand" "")
1039 (match_operand:DI 1 "register_operand" ""))
1042 (plus:DI (match_dup 0)
1043 (match_operand:DI 2 "nonmemory_operand" "")))
1044 (clobber (reg:CC CC_REGNUM))])]
1046 && !reg_overlap_mentioned_p (operands[0], operands[2])
1047 && preferred_la_operand_p (operands[1], operands[2])"
1048 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1051 (define_expand "reload_indi"
1052 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1053 (match_operand:DI 1 "s390_plus_operand" "")
1054 (match_operand:DI 2 "register_operand" "=&a")])]
1057 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1062 ; movsi instruction pattern(s).
1065 (define_expand "movsi"
1066 [(set (match_operand:SI 0 "general_operand" "")
1067 (match_operand:SI 1 "general_operand" ""))]
1070 /* Handle symbolic constants. */
1071 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1072 emit_symbolic_move (operands);
1075 (define_insn "*movsi_larl"
1076 [(set (match_operand:SI 0 "register_operand" "=d")
1077 (match_operand:SI 1 "larl_operand" "X"))]
1078 "!TARGET_64BIT && TARGET_CPU_ZARCH
1079 && !FP_REG_P (operands[0])"
1081 [(set_attr "op_type" "RIL")
1082 (set_attr "type" "larl")])
1084 (define_insn "*movsi_zarch"
1085 [(set (match_operand:SI 0 "nonimmediate_operand"
1086 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1087 (match_operand:SI 1 "general_operand"
1088 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1110 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1111 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1112 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1113 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1115 (define_insn "*movsi_esa"
1116 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1117 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1132 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1133 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1136 [(set (match_operand:SI 0 "register_operand" "")
1137 (mem:SI (match_operand 1 "address_operand" "")))]
1138 "!FP_REG_P (operands[0])
1139 && GET_CODE (operands[1]) == SYMBOL_REF
1140 && CONSTANT_POOL_ADDRESS_P (operands[1])
1141 && get_pool_mode (operands[1]) == SImode
1142 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1143 [(set (match_dup 0) (match_dup 2))]
1144 "operands[2] = get_pool_constant (operands[1]);")
1146 (define_insn "*la_31"
1147 [(set (match_operand:SI 0 "register_operand" "=d,d")
1148 (match_operand:QI 1 "address_operand" "U,W"))]
1149 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1153 [(set_attr "op_type" "RX,RXY")
1154 (set_attr "type" "la")])
1158 [(set (match_operand:SI 0 "register_operand" "")
1159 (match_operand:QI 1 "address_operand" ""))
1160 (clobber (reg:CC CC_REGNUM))])]
1162 && preferred_la_operand_p (operands[1], const0_rtx)"
1163 [(set (match_dup 0) (match_dup 1))]
1167 [(set (match_operand:SI 0 "register_operand" "")
1168 (match_operand:SI 1 "register_operand" ""))
1171 (plus:SI (match_dup 0)
1172 (match_operand:SI 2 "nonmemory_operand" "")))
1173 (clobber (reg:CC CC_REGNUM))])]
1175 && !reg_overlap_mentioned_p (operands[0], operands[2])
1176 && preferred_la_operand_p (operands[1], operands[2])"
1177 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1180 (define_insn "*la_31_and"
1181 [(set (match_operand:SI 0 "register_operand" "=d,d")
1182 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1183 (const_int 2147483647)))]
1188 [(set_attr "op_type" "RX,RXY")
1189 (set_attr "type" "la")])
1191 (define_insn_and_split "*la_31_and_cc"
1192 [(set (match_operand:SI 0 "register_operand" "=d")
1193 (and:SI (match_operand:QI 1 "address_operand" "p")
1194 (const_int 2147483647)))
1195 (clobber (reg:CC CC_REGNUM))]
1198 "&& reload_completed"
1200 (and:SI (match_dup 1) (const_int 2147483647)))]
1202 [(set_attr "op_type" "RX")
1203 (set_attr "type" "la")])
1205 (define_insn "force_la_31"
1206 [(set (match_operand:SI 0 "register_operand" "=d,d")
1207 (match_operand:QI 1 "address_operand" "U,W"))
1208 (use (const_int 0))]
1213 [(set_attr "op_type" "RX")
1214 (set_attr "type" "la")])
1216 (define_expand "reload_insi"
1217 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1218 (match_operand:SI 1 "s390_plus_operand" "")
1219 (match_operand:SI 2 "register_operand" "=&a")])]
1222 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1227 ; movhi instruction pattern(s).
1230 (define_expand "movhi"
1231 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1232 (match_operand:HI 1 "general_operand" ""))]
1235 /* Make it explicit that loading a register from memory
1236 always sign-extends (at least) to SImode. */
1237 if (optimize && !no_new_pseudos
1238 && register_operand (operands[0], VOIDmode)
1239 && GET_CODE (operands[1]) == MEM)
1241 rtx tmp = gen_reg_rtx (SImode);
1242 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1243 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1244 operands[1] = gen_lowpart (HImode, tmp);
1248 (define_insn "*movhi"
1249 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1250 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1260 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1261 (set_attr "type" "lr,*,*,*,store,store,*")])
1264 [(set (match_operand:HI 0 "register_operand" "")
1265 (mem:HI (match_operand 1 "address_operand" "")))]
1266 "GET_CODE (operands[1]) == SYMBOL_REF
1267 && CONSTANT_POOL_ADDRESS_P (operands[1])
1268 && get_pool_mode (operands[1]) == HImode
1269 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1270 [(set (match_dup 0) (match_dup 2))]
1271 "operands[2] = get_pool_constant (operands[1]);")
1274 ; movqi instruction pattern(s).
1277 (define_expand "movqi"
1278 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1279 (match_operand:QI 1 "general_operand" ""))]
1282 /* On z/Architecture, zero-extending from memory to register
1283 is just as fast as a QImode load. */
1284 if (TARGET_ZARCH && optimize && !no_new_pseudos
1285 && register_operand (operands[0], VOIDmode)
1286 && GET_CODE (operands[1]) == MEM)
1288 rtx tmp = gen_reg_rtx (word_mode);
1289 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1290 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1291 operands[1] = gen_lowpart (QImode, tmp);
1295 (define_insn "*movqi"
1296 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1297 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1309 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1310 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1313 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1314 (mem:QI (match_operand 1 "address_operand" "")))]
1315 "GET_CODE (operands[1]) == SYMBOL_REF
1316 && CONSTANT_POOL_ADDRESS_P (operands[1])
1317 && get_pool_mode (operands[1]) == QImode
1318 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1319 [(set (match_dup 0) (match_dup 2))]
1320 "operands[2] = get_pool_constant (operands[1]);")
1323 ; movstrictqi instruction pattern(s).
1326 (define_insn "*movstrictqi"
1327 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1328 (match_operand:QI 1 "memory_operand" "R,T"))]
1333 [(set_attr "op_type" "RX,RXY")])
1336 ; movstricthi instruction pattern(s).
1339 (define_insn "*movstricthi"
1340 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1341 (match_operand:HI 1 "memory_operand" "Q,S"))
1342 (clobber (reg:CC CC_REGNUM))]
1347 [(set_attr "op_type" "RS,RSY")])
1350 ; movstrictsi instruction pattern(s).
1353 (define_insn "movstrictsi"
1354 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1355 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1362 [(set_attr "op_type" "RR,RX,RXY,RRE")
1363 (set_attr "type" "lr,load,load,*")])
1366 ; movdf instruction pattern(s).
1369 (define_expand "movdf"
1370 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1371 (match_operand:DF 1 "general_operand" ""))]
1375 (define_insn "*movdf_64"
1376 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1377 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1390 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1391 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1393 (define_insn "*movdf_31"
1394 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
1395 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
1409 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1410 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
1413 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1414 (match_operand:DF 1 "general_operand" ""))]
1415 "!TARGET_64BIT && reload_completed
1416 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1417 [(set (match_dup 2) (match_dup 4))
1418 (set (match_dup 3) (match_dup 5))]
1420 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1421 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1422 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1423 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1427 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1428 (match_operand:DF 1 "general_operand" ""))]
1429 "!TARGET_64BIT && reload_completed
1430 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1431 [(set (match_dup 2) (match_dup 4))
1432 (set (match_dup 3) (match_dup 5))]
1434 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1435 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1436 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1437 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1441 [(set (match_operand:DF 0 "register_operand" "")
1442 (match_operand:DF 1 "memory_operand" ""))]
1443 "!TARGET_64BIT && reload_completed
1444 && !FP_REG_P (operands[0])
1445 && !s_operand (operands[1], VOIDmode)"
1446 [(set (match_dup 0) (match_dup 1))]
1448 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1449 s390_load_address (addr, XEXP (operands[1], 0));
1450 operands[1] = replace_equiv_address (operands[1], addr);
1453 (define_expand "reload_outdf"
1454 [(parallel [(match_operand:DF 0 "" "")
1455 (match_operand:DF 1 "register_operand" "d")
1456 (match_operand:SI 2 "register_operand" "=&a")])]
1459 gcc_assert (MEM_P (operands[0]));
1460 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1461 operands[0] = replace_equiv_address (operands[0], operands[2]);
1462 emit_move_insn (operands[0], operands[1]);
1467 ; movsf instruction pattern(s).
1470 (define_insn "movsf"
1471 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1472 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1487 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1488 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1489 lr,load,load,store,store,*")])
1492 ; movcc instruction pattern
1495 (define_insn "movcc"
1496 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1497 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1507 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1508 (set_attr "type" "lr,*,*,store,store,load,load")])
1511 ; Block move (MVC) patterns.
1515 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1516 (match_operand:BLK 1 "memory_operand" "Q"))
1517 (use (match_operand 2 "const_int_operand" "n"))]
1518 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1519 "mvc\t%O0(%2,%R0),%S1"
1520 [(set_attr "op_type" "SS")])
1523 [(set (match_operand 0 "memory_operand" "")
1524 (match_operand 1 "memory_operand" ""))]
1526 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1527 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1529 [(set (match_dup 0) (match_dup 1))
1530 (use (match_dup 2))])]
1532 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1533 operands[0] = adjust_address (operands[0], BLKmode, 0);
1534 operands[1] = adjust_address (operands[1], BLKmode, 0);
1539 [(set (match_operand:BLK 0 "memory_operand" "")
1540 (match_operand:BLK 1 "memory_operand" ""))
1541 (use (match_operand 2 "const_int_operand" ""))])
1543 [(set (match_operand:BLK 3 "memory_operand" "")
1544 (match_operand:BLK 4 "memory_operand" ""))
1545 (use (match_operand 5 "const_int_operand" ""))])]
1546 "s390_offset_p (operands[0], operands[3], operands[2])
1547 && s390_offset_p (operands[1], operands[4], operands[2])
1548 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1550 [(set (match_dup 6) (match_dup 7))
1551 (use (match_dup 8))])]
1552 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1553 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1554 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1558 ; load_multiple pattern(s).
1560 ; ??? Due to reload problems with replacing registers inside match_parallel
1561 ; we currently support load_multiple/store_multiple only after reload.
1564 (define_expand "load_multiple"
1565 [(match_par_dup 3 [(set (match_operand 0 "" "")
1566 (match_operand 1 "" ""))
1567 (use (match_operand 2 "" ""))])]
1570 enum machine_mode mode;
1576 /* Support only loading a constant number of fixed-point registers from
1577 memory and only bother with this if more than two */
1578 if (GET_CODE (operands[2]) != CONST_INT
1579 || INTVAL (operands[2]) < 2
1580 || INTVAL (operands[2]) > 16
1581 || GET_CODE (operands[1]) != MEM
1582 || GET_CODE (operands[0]) != REG
1583 || REGNO (operands[0]) >= 16)
1586 count = INTVAL (operands[2]);
1587 regno = REGNO (operands[0]);
1588 mode = GET_MODE (operands[0]);
1589 if (mode != SImode && mode != word_mode)
1592 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1595 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1597 from = XEXP (operands[1], 0);
1600 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1601 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1602 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1604 from = XEXP (XEXP (operands[1], 0), 0);
1605 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1612 from = force_reg (Pmode, XEXP (operands[1], 0));
1616 for (i = 0; i < count; i++)
1617 XVECEXP (operands[3], 0, i)
1618 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1619 change_address (operands[1], mode,
1620 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1623 (define_insn "*load_multiple_di"
1624 [(match_parallel 0 "load_multiple_operation"
1625 [(set (match_operand:DI 1 "register_operand" "=r")
1626 (match_operand:DI 2 "s_operand" "QS"))])]
1627 "reload_completed && word_mode == DImode"
1629 int words = XVECLEN (operands[0], 0);
1630 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1631 return "lmg\t%1,%0,%S2";
1633 [(set_attr "op_type" "RSY")
1634 (set_attr "type" "lm")])
1636 (define_insn "*load_multiple_si"
1637 [(match_parallel 0 "load_multiple_operation"
1638 [(set (match_operand:SI 1 "register_operand" "=r,r")
1639 (match_operand:SI 2 "s_operand" "Q,S"))])]
1642 int words = XVECLEN (operands[0], 0);
1643 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1644 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1646 [(set_attr "op_type" "RS,RSY")
1647 (set_attr "type" "lm")])
1650 ; store multiple pattern(s).
1653 (define_expand "store_multiple"
1654 [(match_par_dup 3 [(set (match_operand 0 "" "")
1655 (match_operand 1 "" ""))
1656 (use (match_operand 2 "" ""))])]
1659 enum machine_mode mode;
1665 /* Support only storing a constant number of fixed-point registers to
1666 memory and only bother with this if more than two. */
1667 if (GET_CODE (operands[2]) != CONST_INT
1668 || INTVAL (operands[2]) < 2
1669 || INTVAL (operands[2]) > 16
1670 || GET_CODE (operands[0]) != MEM
1671 || GET_CODE (operands[1]) != REG
1672 || REGNO (operands[1]) >= 16)
1675 count = INTVAL (operands[2]);
1676 regno = REGNO (operands[1]);
1677 mode = GET_MODE (operands[1]);
1678 if (mode != SImode && mode != word_mode)
1681 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1685 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1687 to = XEXP (operands[0], 0);
1690 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1691 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1692 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1694 to = XEXP (XEXP (operands[0], 0), 0);
1695 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1702 to = force_reg (Pmode, XEXP (operands[0], 0));
1706 for (i = 0; i < count; i++)
1707 XVECEXP (operands[3], 0, i)
1708 = gen_rtx_SET (VOIDmode,
1709 change_address (operands[0], mode,
1710 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1711 gen_rtx_REG (mode, regno + i));
1714 (define_insn "*store_multiple_di"
1715 [(match_parallel 0 "store_multiple_operation"
1716 [(set (match_operand:DI 1 "s_operand" "=QS")
1717 (match_operand:DI 2 "register_operand" "r"))])]
1718 "reload_completed && word_mode == DImode"
1720 int words = XVECLEN (operands[0], 0);
1721 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1722 return "stmg\t%2,%0,%S1";
1724 [(set_attr "op_type" "RSY")
1725 (set_attr "type" "stm")])
1728 (define_insn "*store_multiple_si"
1729 [(match_parallel 0 "store_multiple_operation"
1730 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1731 (match_operand:SI 2 "register_operand" "r,r"))])]
1734 int words = XVECLEN (operands[0], 0);
1735 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1736 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1738 [(set_attr "op_type" "RS,RSY")
1739 (set_attr "type" "stm")])
1742 ;; String instructions.
1745 (define_insn "*execute"
1746 [(match_parallel 0 ""
1747 [(unspec [(match_operand 1 "register_operand" "a")
1748 (match_operand:BLK 2 "memory_operand" "R")
1749 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1750 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1751 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1753 [(set_attr "op_type" "RX")
1754 (set_attr "type" "cs")])
1758 ; strlenM instruction pattern(s).
1761 (define_expand "strlen<mode>"
1762 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1765 (unspec:P [(const_int 0)
1766 (match_operand:BLK 1 "memory_operand" "")
1768 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1769 (clobber (scratch:P))
1770 (clobber (reg:CC CC_REGNUM))])
1772 [(set (match_operand:P 0 "register_operand" "")
1773 (minus:P (match_dup 4) (match_dup 5)))
1774 (clobber (reg:CC CC_REGNUM))])]
1777 operands[4] = gen_reg_rtx (Pmode);
1778 operands[5] = gen_reg_rtx (Pmode);
1779 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1780 operands[1] = replace_equiv_address (operands[1], operands[5]);
1783 (define_insn "*strlen<mode>"
1784 [(set (match_operand:P 0 "register_operand" "=a")
1785 (unspec:P [(match_operand:P 2 "general_operand" "0")
1786 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1788 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1789 (clobber (match_scratch:P 1 "=a"))
1790 (clobber (reg:CC CC_REGNUM))]
1792 "srst\t%0,%1\;jo\t.-4"
1793 [(set_attr "length" "8")
1794 (set_attr "type" "vs")])
1797 ; movmemM instruction pattern(s).
1800 (define_expand "movmem<mode>"
1801 [(set (match_operand:BLK 0 "memory_operand" "")
1802 (match_operand:BLK 1 "memory_operand" ""))
1803 (use (match_operand:GPR 2 "general_operand" ""))
1804 (match_operand 3 "" "")]
1806 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1808 ; Move a block that is up to 256 bytes in length.
1809 ; The block length is taken as (operands[2] % 256) + 1.
1811 (define_expand "movmem_short"
1813 [(set (match_operand:BLK 0 "memory_operand" "")
1814 (match_operand:BLK 1 "memory_operand" ""))
1815 (use (match_operand 2 "nonmemory_operand" ""))
1816 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1817 (clobber (match_dup 3))])]
1819 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1821 (define_insn "*movmem_short"
1822 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1823 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1824 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1825 (use (match_operand 3 "immediate_operand" "X,R,X"))
1826 (clobber (match_scratch 4 "=X,X,&a"))]
1827 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1828 && GET_MODE (operands[4]) == Pmode"
1830 [(set_attr "type" "cs")])
1833 [(set (match_operand:BLK 0 "memory_operand" "")
1834 (match_operand:BLK 1 "memory_operand" ""))
1835 (use (match_operand 2 "const_int_operand" ""))
1836 (use (match_operand 3 "immediate_operand" ""))
1837 (clobber (scratch))]
1840 [(set (match_dup 0) (match_dup 1))
1841 (use (match_dup 2))])]
1842 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1845 [(set (match_operand:BLK 0 "memory_operand" "")
1846 (match_operand:BLK 1 "memory_operand" ""))
1847 (use (match_operand 2 "register_operand" ""))
1848 (use (match_operand 3 "memory_operand" ""))
1849 (clobber (scratch))]
1852 [(unspec [(match_dup 2) (match_dup 3)
1853 (const_int 0)] UNSPEC_EXECUTE)
1854 (set (match_dup 0) (match_dup 1))
1855 (use (const_int 1))])]
1859 [(set (match_operand:BLK 0 "memory_operand" "")
1860 (match_operand:BLK 1 "memory_operand" ""))
1861 (use (match_operand 2 "register_operand" ""))
1862 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1863 (clobber (match_operand 3 "register_operand" ""))]
1864 "reload_completed && TARGET_CPU_ZARCH"
1865 [(set (match_dup 3) (label_ref (match_dup 4)))
1867 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1868 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1869 (set (match_dup 0) (match_dup 1))
1870 (use (const_int 1))])]
1871 "operands[4] = gen_label_rtx ();")
1873 ; Move a block of arbitrary length.
1875 (define_expand "movmem_long"
1877 [(clobber (match_dup 2))
1878 (clobber (match_dup 3))
1879 (set (match_operand:BLK 0 "memory_operand" "")
1880 (match_operand:BLK 1 "memory_operand" ""))
1881 (use (match_operand 2 "general_operand" ""))
1883 (clobber (reg:CC CC_REGNUM))])]
1886 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1887 rtx reg0 = gen_reg_rtx (dword_mode);
1888 rtx reg1 = gen_reg_rtx (dword_mode);
1889 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1890 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1891 rtx len0 = gen_lowpart (Pmode, reg0);
1892 rtx len1 = gen_lowpart (Pmode, reg1);
1894 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1895 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1896 emit_move_insn (len0, operands[2]);
1898 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1899 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1900 emit_move_insn (len1, operands[2]);
1902 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1903 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1908 (define_insn "*movmem_long"
1909 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
1910 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
1911 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
1912 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
1915 (clobber (reg:CC CC_REGNUM))]
1917 "mvcle\t%0,%1,0\;jo\t.-4"
1918 [(set_attr "length" "8")
1919 (set_attr "type" "vs")])
1922 ; clrmemM instruction pattern(s).
1925 (define_expand "clrmem<mode>"
1926 [(set (match_operand:BLK 0 "memory_operand" "")
1928 (use (match_operand:GPR 1 "general_operand" ""))
1929 (match_operand 2 "" "")]
1931 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1933 ; Clear a block that is up to 256 bytes in length.
1934 ; The block length is taken as (operands[1] % 256) + 1.
1936 (define_expand "clrmem_short"
1938 [(set (match_operand:BLK 0 "memory_operand" "")
1940 (use (match_operand 1 "nonmemory_operand" ""))
1941 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1942 (clobber (match_dup 2))
1943 (clobber (reg:CC CC_REGNUM))])]
1945 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1947 (define_insn "*clrmem_short"
1948 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1950 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1951 (use (match_operand 2 "immediate_operand" "X,R,X"))
1952 (clobber (match_scratch 3 "=X,X,&a"))
1953 (clobber (reg:CC CC_REGNUM))]
1954 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1955 && GET_MODE (operands[3]) == Pmode"
1957 [(set_attr "type" "cs")])
1960 [(set (match_operand:BLK 0 "memory_operand" "")
1962 (use (match_operand 1 "const_int_operand" ""))
1963 (use (match_operand 2 "immediate_operand" ""))
1965 (clobber (reg:CC CC_REGNUM))]
1968 [(set (match_dup 0) (const_int 0))
1970 (clobber (reg:CC CC_REGNUM))])]
1971 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
1974 [(set (match_operand:BLK 0 "memory_operand" "")
1976 (use (match_operand 1 "register_operand" ""))
1977 (use (match_operand 2 "memory_operand" ""))
1979 (clobber (reg:CC CC_REGNUM))]
1982 [(unspec [(match_dup 1) (match_dup 2)
1983 (const_int 0)] UNSPEC_EXECUTE)
1984 (set (match_dup 0) (const_int 0))
1986 (clobber (reg:CC CC_REGNUM))])]
1990 [(set (match_operand:BLK 0 "memory_operand" "")
1992 (use (match_operand 1 "register_operand" ""))
1993 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1994 (clobber (match_operand 2 "register_operand" ""))
1995 (clobber (reg:CC CC_REGNUM))]
1996 "reload_completed && TARGET_CPU_ZARCH"
1997 [(set (match_dup 2) (label_ref (match_dup 3)))
1999 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2000 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2001 (set (match_dup 0) (const_int 0))
2003 (clobber (reg:CC CC_REGNUM))])]
2004 "operands[3] = gen_label_rtx ();")
2006 ; Clear a block of arbitrary length.
2008 (define_expand "clrmem_long"
2010 [(clobber (match_dup 1))
2011 (set (match_operand:BLK 0 "memory_operand" "")
2013 (use (match_operand 1 "general_operand" ""))
2015 (clobber (reg:CC CC_REGNUM))])]
2018 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2019 rtx reg0 = gen_reg_rtx (dword_mode);
2020 rtx reg1 = gen_reg_rtx (dword_mode);
2021 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2022 rtx len0 = gen_lowpart (Pmode, reg0);
2024 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2025 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2026 emit_move_insn (len0, operands[1]);
2028 emit_move_insn (reg1, const0_rtx);
2030 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2035 (define_insn "*clrmem_long"
2036 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2037 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2040 (use (match_operand:<DBL> 1 "register_operand" "d"))
2041 (clobber (reg:CC CC_REGNUM))]
2043 "mvcle\t%0,%1,0\;jo\t.-4"
2044 [(set_attr "length" "8")
2045 (set_attr "type" "vs")])
2048 ; cmpmemM instruction pattern(s).
2051 (define_expand "cmpmemsi"
2052 [(set (match_operand:SI 0 "register_operand" "")
2053 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2054 (match_operand:BLK 2 "memory_operand" "") ) )
2055 (use (match_operand:SI 3 "general_operand" ""))
2056 (use (match_operand:SI 4 "" ""))]
2058 "s390_expand_cmpmem (operands[0], operands[1],
2059 operands[2], operands[3]); DONE;")
2061 ; Compare a block that is up to 256 bytes in length.
2062 ; The block length is taken as (operands[2] % 256) + 1.
2064 (define_expand "cmpmem_short"
2066 [(set (reg:CCU CC_REGNUM)
2067 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2068 (match_operand:BLK 1 "memory_operand" "")))
2069 (use (match_operand 2 "nonmemory_operand" ""))
2070 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2071 (clobber (match_dup 3))])]
2073 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2075 (define_insn "*cmpmem_short"
2076 [(set (reg:CCU CC_REGNUM)
2077 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2078 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2079 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2080 (use (match_operand 3 "immediate_operand" "X,R,X"))
2081 (clobber (match_scratch 4 "=X,X,&a"))]
2082 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2083 && GET_MODE (operands[4]) == Pmode"
2085 [(set_attr "type" "cs")])
2088 [(set (reg:CCU CC_REGNUM)
2089 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2090 (match_operand:BLK 1 "memory_operand" "")))
2091 (use (match_operand 2 "const_int_operand" ""))
2092 (use (match_operand 3 "immediate_operand" ""))
2093 (clobber (scratch))]
2096 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2097 (use (match_dup 2))])]
2098 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2101 [(set (reg:CCU CC_REGNUM)
2102 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2103 (match_operand:BLK 1 "memory_operand" "")))
2104 (use (match_operand 2 "register_operand" ""))
2105 (use (match_operand 3 "memory_operand" ""))
2106 (clobber (scratch))]
2109 [(unspec [(match_dup 2) (match_dup 3)
2110 (const_int 0)] UNSPEC_EXECUTE)
2111 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2112 (use (const_int 1))])]
2116 [(set (reg:CCU CC_REGNUM)
2117 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2118 (match_operand:BLK 1 "memory_operand" "")))
2119 (use (match_operand 2 "register_operand" ""))
2120 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2121 (clobber (match_operand 3 "register_operand" ""))]
2122 "reload_completed && TARGET_CPU_ZARCH"
2123 [(set (match_dup 3) (label_ref (match_dup 4)))
2125 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2126 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2127 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2128 (use (const_int 1))])]
2129 "operands[4] = gen_label_rtx ();")
2131 ; Compare a block of arbitrary length.
2133 (define_expand "cmpmem_long"
2135 [(clobber (match_dup 2))
2136 (clobber (match_dup 3))
2137 (set (reg:CCU CC_REGNUM)
2138 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2139 (match_operand:BLK 1 "memory_operand" "")))
2140 (use (match_operand 2 "general_operand" ""))
2141 (use (match_dup 3))])]
2144 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2145 rtx reg0 = gen_reg_rtx (dword_mode);
2146 rtx reg1 = gen_reg_rtx (dword_mode);
2147 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2148 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2149 rtx len0 = gen_lowpart (Pmode, reg0);
2150 rtx len1 = gen_lowpart (Pmode, reg1);
2152 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2153 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2154 emit_move_insn (len0, operands[2]);
2156 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2157 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2158 emit_move_insn (len1, operands[2]);
2160 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2161 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2166 (define_insn "*cmpmem_long"
2167 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2168 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2169 (set (reg:CCU CC_REGNUM)
2170 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2171 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2173 (use (match_dup 3))]
2175 "clcle\t%0,%1,0\;jo\t.-4"
2176 [(set_attr "length" "8")
2177 (set_attr "type" "vs")])
2179 ; Convert CCUmode condition code to integer.
2180 ; Result is zero if EQ, positive if LTU, negative if GTU.
2182 (define_insn_and_split "cmpint"
2183 [(set (match_operand:SI 0 "register_operand" "=d")
2184 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2186 (clobber (reg:CC CC_REGNUM))]
2190 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2192 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2193 (clobber (reg:CC CC_REGNUM))])])
2195 (define_insn_and_split "*cmpint_cc"
2196 [(set (reg CC_REGNUM)
2197 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2200 (set (match_operand:SI 0 "register_operand" "=d")
2201 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2202 "s390_match_ccmode (insn, CCSmode)"
2204 "&& reload_completed"
2205 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2207 [(set (match_dup 2) (match_dup 3))
2208 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2210 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2211 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2212 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2215 (define_insn_and_split "*cmpint_sign"
2216 [(set (match_operand:DI 0 "register_operand" "=d")
2217 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2219 (clobber (reg:CC CC_REGNUM))]
2222 "&& reload_completed"
2223 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2225 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2226 (clobber (reg:CC CC_REGNUM))])])
2228 (define_insn_and_split "*cmpint_sign_cc"
2229 [(set (reg CC_REGNUM)
2230 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2231 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2233 (const_int 32)) (const_int 32))
2235 (set (match_operand:DI 0 "register_operand" "=d")
2236 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2237 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2239 "&& reload_completed"
2240 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2242 [(set (match_dup 2) (match_dup 3))
2243 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2245 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2246 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2247 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2252 ;;- Conversion instructions.
2256 (define_insn "*sethigh<mode>si"
2257 [(set (match_operand:SI 0 "register_operand" "=d,d")
2258 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2259 (clobber (reg:CC CC_REGNUM))]
2262 icm\t%0,<icm_hi>,%S1
2263 icmy\t%0,<icm_hi>,%S1"
2264 [(set_attr "op_type" "RS,RSY")])
2266 (define_insn "*sethighqidi_64"
2267 [(set (match_operand:DI 0 "register_operand" "=d")
2268 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2269 (clobber (reg:CC CC_REGNUM))]
2272 [(set_attr "op_type" "RSY")])
2274 (define_insn "*sethighqidi_31"
2275 [(set (match_operand:DI 0 "register_operand" "=d,d")
2276 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2277 (clobber (reg:CC CC_REGNUM))]
2282 [(set_attr "op_type" "RS,RSY")])
2284 (define_insn_and_split "*extractqi"
2285 [(set (match_operand:SI 0 "register_operand" "=d")
2286 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2287 (match_operand 2 "const_int_operand" "n")
2289 (clobber (reg:CC CC_REGNUM))]
2291 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2293 "&& reload_completed"
2295 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2296 (clobber (reg:CC CC_REGNUM))])
2297 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2299 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2300 operands[1] = change_address (operands[1], QImode, 0);
2303 (define_insn_and_split "*extracthi"
2304 [(set (match_operand:SI 0 "register_operand" "=d")
2305 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2306 (match_operand 2 "const_int_operand" "n")
2308 (clobber (reg:CC CC_REGNUM))]
2310 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2312 "&& reload_completed"
2314 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2315 (clobber (reg:CC CC_REGNUM))])
2316 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2318 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2319 operands[1] = change_address (operands[1], HImode, 0);
2323 ; extendsidi2 instruction pattern(s).
2326 (define_expand "extendsidi2"
2327 [(set (match_operand:DI 0 "register_operand" "")
2328 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2334 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2335 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2336 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2337 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2343 (define_insn "*extendsidi2"
2344 [(set (match_operand:DI 0 "register_operand" "=d,d")
2345 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2350 [(set_attr "op_type" "RRE,RXY")])
2353 ; extend(hi|qi)di2 instruction pattern(s).
2356 (define_expand "extend<mode>di2"
2357 [(set (match_operand:DI 0 "register_operand" "")
2358 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2364 rtx tmp = gen_reg_rtx (SImode);
2365 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2366 emit_insn (gen_extendsidi2 (operands[0], tmp));
2371 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2372 GET_MODE_BITSIZE (<MODE>mode));
2373 operands[1] = gen_lowpart (DImode, operands[1]);
2374 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2375 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2381 (define_insn "*extendhidi2"
2382 [(set (match_operand:DI 0 "register_operand" "=d")
2383 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2386 [(set_attr "op_type" "RXY")])
2388 (define_insn "*extendqidi2"
2389 [(set (match_operand:DI 0 "register_operand" "=d")
2390 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2391 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2393 [(set_attr "op_type" "RXY")])
2395 (define_insn_and_split "*extendqidi2_short_displ"
2396 [(set (match_operand:DI 0 "register_operand" "=d")
2397 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2398 (clobber (reg:CC CC_REGNUM))]
2399 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2401 "&& reload_completed"
2403 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2404 (clobber (reg:CC CC_REGNUM))])
2406 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2407 (clobber (reg:CC CC_REGNUM))])]
2411 ; extend(hi|qi)si2 instruction pattern(s).
2414 (define_expand "extend<mode>si2"
2415 [(set (match_operand:SI 0 "register_operand" "")
2416 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2420 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2421 GET_MODE_BITSIZE(<MODE>mode));
2422 operands[1] = gen_lowpart (SImode, operands[1]);
2423 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2424 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2429 (define_insn "*extendhisi2"
2430 [(set (match_operand:SI 0 "register_operand" "=d,d")
2431 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2436 [(set_attr "op_type" "RX,RXY")])
2438 (define_insn "*extendqisi2"
2439 [(set (match_operand:SI 0 "register_operand" "=d")
2440 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2441 "TARGET_LONG_DISPLACEMENT"
2443 [(set_attr "op_type" "RXY")])
2445 (define_insn_and_split "*extendqisi2_short_displ"
2446 [(set (match_operand:SI 0 "register_operand" "=d")
2447 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2448 (clobber (reg:CC CC_REGNUM))]
2449 "!TARGET_LONG_DISPLACEMENT"
2451 "&& reload_completed"
2453 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2454 (clobber (reg:CC CC_REGNUM))])
2456 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2457 (clobber (reg:CC CC_REGNUM))])]
2461 ; extendqihi2 instruction pattern(s).
2466 ; zero_extendsidi2 instruction pattern(s).
2469 (define_expand "zero_extendsidi2"
2470 [(set (match_operand:DI 0 "register_operand" "")
2471 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2477 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2478 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2479 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2485 (define_insn "*zero_extendsidi2"
2486 [(set (match_operand:DI 0 "register_operand" "=d,d")
2487 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2492 [(set_attr "op_type" "RRE,RXY")])
2495 ; zero_extend(hi|qi)di2 instruction pattern(s).
2498 (define_expand "zero_extend<mode>di2"
2499 [(set (match_operand:DI 0 "register_operand" "")
2500 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2506 rtx tmp = gen_reg_rtx (SImode);
2507 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2508 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2513 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2514 GET_MODE_BITSIZE(<MODE>mode));
2515 operands[1] = gen_lowpart (DImode, operands[1]);
2516 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2517 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2523 (define_insn "*zero_extend<mode>di2"
2524 [(set (match_operand:DI 0 "register_operand" "=d")
2525 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2528 [(set_attr "op_type" "RXY")])
2531 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2534 (define_insn "*llgt_sidi"
2535 [(set (match_operand:DI 0 "register_operand" "=d")
2536 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2537 (const_int 2147483647)))]
2540 [(set_attr "op_type" "RXE")])
2542 (define_insn_and_split "*llgt_sidi_split"
2543 [(set (match_operand:DI 0 "register_operand" "=d")
2544 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2545 (const_int 2147483647)))
2546 (clobber (reg:CC CC_REGNUM))]
2549 "&& reload_completed"
2551 (and:DI (subreg:DI (match_dup 1) 0)
2552 (const_int 2147483647)))]
2555 (define_insn "*llgt_sisi"
2556 [(set (match_operand:SI 0 "register_operand" "=d,d")
2557 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2558 (const_int 2147483647)))]
2563 [(set_attr "op_type" "RRE,RXE")])
2565 (define_insn "*llgt_didi"
2566 [(set (match_operand:DI 0 "register_operand" "=d,d")
2567 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2568 (const_int 2147483647)))]
2573 [(set_attr "op_type" "RRE,RXE")])
2576 [(set (match_operand:GPR 0 "register_operand" "")
2577 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2578 (const_int 2147483647)))
2579 (clobber (reg:CC CC_REGNUM))]
2580 "TARGET_64BIT && reload_completed"
2582 (and:GPR (match_dup 1)
2583 (const_int 2147483647)))]
2587 ; zero_extend(hi|qi)si2 instruction pattern(s).
2590 (define_expand "zero_extend<mode>si2"
2591 [(set (match_operand:SI 0 "register_operand" "")
2592 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2596 operands[1] = gen_lowpart (SImode, operands[1]);
2597 emit_insn (gen_andsi3 (operands[0], operands[1],
2598 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2603 (define_insn "*zero_extend<mode>si2_64"
2604 [(set (match_operand:SI 0 "register_operand" "=d")
2605 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2608 [(set_attr "op_type" "RXY")])
2610 (define_insn_and_split "*zero_extendhisi2_31"
2611 [(set (match_operand:SI 0 "register_operand" "=&d")
2612 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2613 (clobber (reg:CC CC_REGNUM))]
2616 "&& reload_completed"
2617 [(set (match_dup 0) (const_int 0))
2619 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2620 (clobber (reg:CC CC_REGNUM))])]
2621 "operands[2] = gen_lowpart (HImode, operands[0]);")
2623 (define_insn_and_split "*zero_extendqisi2_31"
2624 [(set (match_operand:SI 0 "register_operand" "=&d")
2625 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2628 "&& reload_completed"
2629 [(set (match_dup 0) (const_int 0))
2630 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2631 "operands[2] = gen_lowpart (QImode, operands[0]);")
2634 ; zero_extendqihi2 instruction pattern(s).
2637 (define_expand "zero_extendqihi2"
2638 [(set (match_operand:HI 0 "register_operand" "")
2639 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2643 operands[1] = gen_lowpart (HImode, operands[1]);
2644 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2649 (define_insn "*zero_extendqihi2_64"
2650 [(set (match_operand:HI 0 "register_operand" "=d")
2651 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2654 [(set_attr "op_type" "RXY")])
2656 (define_insn_and_split "*zero_extendqihi2_31"
2657 [(set (match_operand:HI 0 "register_operand" "=&d")
2658 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2661 "&& reload_completed"
2662 [(set (match_dup 0) (const_int 0))
2663 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2664 "operands[2] = gen_lowpart (QImode, operands[0]);")
2668 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2671 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2672 [(set (match_operand:GPR 0 "register_operand" "")
2673 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2674 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2676 rtx label1 = gen_label_rtx ();
2677 rtx label2 = gen_label_rtx ();
2678 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2679 REAL_VALUE_TYPE cmp, sub;
2681 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2682 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2683 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2685 emit_insn (gen_cmp<FPR:mode> (operands[1],
2686 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2687 emit_jump_insn (gen_blt (label1));
2688 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2689 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2690 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2694 emit_label (label1);
2695 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2696 operands[1], GEN_INT(5)));
2697 emit_label (label2);
2701 (define_expand "fix_trunc<FPR:mode>di2"
2702 [(set (match_operand:DI 0 "register_operand" "")
2703 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2704 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2706 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2707 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2712 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2713 [(set (match_operand:GPR 0 "register_operand" "=d")
2714 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2715 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2716 (clobber (reg:CC CC_REGNUM))]
2717 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2718 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2719 [(set_attr "op_type" "RRE")
2720 (set_attr "type" "ftoi")])
2723 ; fix_truncdfsi2 instruction pattern(s).
2726 (define_expand "fix_truncdfsi2"
2727 [(set (match_operand:SI 0 "register_operand" "")
2728 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2731 if (TARGET_IBM_FLOAT)
2733 /* This is the algorithm from POP chapter A.5.7.2. */
2735 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2736 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2737 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2739 operands[1] = force_reg (DFmode, operands[1]);
2740 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2741 two31r, two32, temp));
2745 operands[1] = force_reg (DFmode, operands[1]);
2746 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2752 (define_insn "fix_truncdfsi2_ibm"
2753 [(set (match_operand:SI 0 "register_operand" "=d")
2754 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2755 (use (match_operand:DI 2 "immediate_operand" "m"))
2756 (use (match_operand:DI 3 "immediate_operand" "m"))
2757 (use (match_operand:BLK 4 "memory_operand" "m"))
2758 (clobber (reg:CC CC_REGNUM))]
2759 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2761 output_asm_insn ("sd\t%1,%2", operands);
2762 output_asm_insn ("aw\t%1,%3", operands);
2763 output_asm_insn ("std\t%1,%4", operands);
2764 output_asm_insn ("xi\t%N4,128", operands);
2767 [(set_attr "length" "20")])
2770 ; fix_truncsfsi2 instruction pattern(s).
2773 (define_expand "fix_truncsfsi2"
2774 [(set (match_operand:SI 0 "register_operand" "")
2775 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2778 if (TARGET_IBM_FLOAT)
2780 /* Convert to DFmode and then use the POP algorithm. */
2781 rtx temp = gen_reg_rtx (DFmode);
2782 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2783 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2787 operands[1] = force_reg (SFmode, operands[1]);
2788 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2795 ; floatdi(df|sf)2 instruction pattern(s).
2798 (define_insn "floatdi<mode>2"
2799 [(set (match_operand:FPR 0 "register_operand" "=f")
2800 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2801 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2803 [(set_attr "op_type" "RRE")
2804 (set_attr "type" "itof" )])
2807 ; floatsidf2 instruction pattern(s).
2810 (define_expand "floatsidf2"
2811 [(set (match_operand:DF 0 "register_operand" "")
2812 (float:DF (match_operand:SI 1 "register_operand" "")))]
2815 if (TARGET_IBM_FLOAT)
2817 /* This is the algorithm from POP chapter A.5.7.1. */
2819 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2820 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2822 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2827 (define_insn "floatsidf2_ieee"
2828 [(set (match_operand:DF 0 "register_operand" "=f")
2829 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2830 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2832 [(set_attr "op_type" "RRE")
2833 (set_attr "type" "itof" )])
2835 (define_insn "floatsidf2_ibm"
2836 [(set (match_operand:DF 0 "register_operand" "=f")
2837 (float:DF (match_operand:SI 1 "register_operand" "d")))
2838 (use (match_operand:DI 2 "immediate_operand" "m"))
2839 (use (match_operand:BLK 3 "memory_operand" "m"))
2840 (clobber (reg:CC CC_REGNUM))]
2841 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2843 output_asm_insn ("st\t%1,%N3", operands);
2844 output_asm_insn ("xi\t%N3,128", operands);
2845 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2846 output_asm_insn ("ld\t%0,%3", operands);
2849 [(set_attr "length" "20")])
2852 ; floatsisf2 instruction pattern(s).
2855 (define_expand "floatsisf2"
2856 [(set (match_operand:SF 0 "register_operand" "")
2857 (float:SF (match_operand:SI 1 "register_operand" "")))]
2860 if (TARGET_IBM_FLOAT)
2862 /* Use the POP algorithm to convert to DFmode and then truncate. */
2863 rtx temp = gen_reg_rtx (DFmode);
2864 emit_insn (gen_floatsidf2 (temp, operands[1]));
2865 emit_insn (gen_truncdfsf2 (operands[0], temp));
2870 (define_insn "floatsisf2_ieee"
2871 [(set (match_operand:SF 0 "register_operand" "=f")
2872 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2873 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2875 [(set_attr "op_type" "RRE")
2876 (set_attr "type" "itof" )])
2879 ; truncdfsf2 instruction pattern(s).
2882 (define_expand "truncdfsf2"
2883 [(set (match_operand:SF 0 "register_operand" "")
2884 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2888 (define_insn "truncdfsf2_ieee"
2889 [(set (match_operand:SF 0 "register_operand" "=f")
2890 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2891 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2893 [(set_attr "op_type" "RRE")])
2895 (define_insn "truncdfsf2_ibm"
2896 [(set (match_operand:SF 0 "register_operand" "=f,f")
2897 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2898 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2902 [(set_attr "op_type" "RR,RX")
2903 (set_attr "type" "floadsf")])
2906 ; extendsfdf2 instruction pattern(s).
2909 (define_expand "extendsfdf2"
2910 [(set (match_operand:DF 0 "register_operand" "")
2911 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2914 if (TARGET_IBM_FLOAT)
2916 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2921 (define_insn "extendsfdf2_ieee"
2922 [(set (match_operand:DF 0 "register_operand" "=f,f")
2923 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2924 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2928 [(set_attr "op_type" "RRE,RXE")
2929 (set_attr "type" "floadsf")])
2931 (define_insn "extendsfdf2_ibm"
2932 [(set (match_operand:DF 0 "register_operand" "=f,f")
2933 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2934 (clobber (reg:CC CC_REGNUM))]
2935 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2937 sdr\t%0,%0\;ler\t%0,%1
2938 sdr\t%0,%0\;le\t%0,%1"
2939 [(set_attr "length" "4,6")
2940 (set_attr "type" "floadsf")])
2944 ;; ARITHMETIC OPERATIONS
2946 ; arithmetic operations set the ConditionCode,
2947 ; because of unpredictable Bits in Register for Halfword and Byte
2948 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2951 ;;- Add instructions.
2955 ; addti3 instruction pattern(s).
2958 (define_insn_and_split "addti3"
2959 [(set (match_operand:TI 0 "register_operand" "=&d")
2960 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
2961 (match_operand:TI 2 "general_operand" "do") ) )
2962 (clobber (reg:CC CC_REGNUM))]
2965 "&& reload_completed"
2967 [(set (reg:CCL1 CC_REGNUM)
2968 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
2970 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
2972 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
2973 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
2974 (clobber (reg:CC CC_REGNUM))])]
2975 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
2976 operands[4] = operand_subword (operands[1], 0, 0, TImode);
2977 operands[5] = operand_subword (operands[2], 0, 0, TImode);
2978 operands[6] = operand_subword (operands[0], 1, 0, TImode);
2979 operands[7] = operand_subword (operands[1], 1, 0, TImode);
2980 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
2983 ; adddi3 instruction pattern(s).
2986 (define_insn "*adddi3_sign"
2987 [(set (match_operand:DI 0 "register_operand" "=d,d")
2988 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2989 (match_operand:DI 1 "register_operand" "0,0")))
2990 (clobber (reg:CC CC_REGNUM))]
2995 [(set_attr "op_type" "RRE,RXY")])
2997 (define_insn "*adddi3_zero_cc"
2998 [(set (reg CC_REGNUM)
2999 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3000 (match_operand:DI 1 "register_operand" "0,0"))
3002 (set (match_operand:DI 0 "register_operand" "=d,d")
3003 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3004 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3008 [(set_attr "op_type" "RRE,RXY")])
3010 (define_insn "*adddi3_zero_cconly"
3011 [(set (reg CC_REGNUM)
3012 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3013 (match_operand:DI 1 "register_operand" "0,0"))
3015 (clobber (match_scratch:DI 0 "=d,d"))]
3016 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3020 [(set_attr "op_type" "RRE,RXY")])
3022 (define_insn "*adddi3_zero"
3023 [(set (match_operand:DI 0 "register_operand" "=d,d")
3024 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3025 (match_operand:DI 1 "register_operand" "0,0")))
3026 (clobber (reg:CC CC_REGNUM))]
3031 [(set_attr "op_type" "RRE,RXY")])
3033 (define_insn "*adddi3_imm_cc"
3034 [(set (reg CC_REGNUM)
3035 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3036 (match_operand:DI 2 "const_int_operand" "K"))
3038 (set (match_operand:DI 0 "register_operand" "=d")
3039 (plus:DI (match_dup 1) (match_dup 2)))]
3041 && s390_match_ccmode (insn, CCAmode)
3042 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3044 [(set_attr "op_type" "RI")])
3046 (define_insn "*adddi3_carry1_cc"
3047 [(set (reg CC_REGNUM)
3048 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3049 (match_operand:DI 2 "general_operand" "d,m"))
3051 (set (match_operand:DI 0 "register_operand" "=d,d")
3052 (plus:DI (match_dup 1) (match_dup 2)))]
3053 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3057 [(set_attr "op_type" "RRE,RXY")])
3059 (define_insn "*adddi3_carry1_cconly"
3060 [(set (reg CC_REGNUM)
3061 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3062 (match_operand:DI 2 "general_operand" "d,m"))
3064 (clobber (match_scratch:DI 0 "=d,d"))]
3065 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3069 [(set_attr "op_type" "RRE,RXY")])
3071 (define_insn "*adddi3_carry2_cc"
3072 [(set (reg CC_REGNUM)
3073 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3074 (match_operand:DI 2 "general_operand" "d,m"))
3076 (set (match_operand:DI 0 "register_operand" "=d,d")
3077 (plus:DI (match_dup 1) (match_dup 2)))]
3078 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3082 [(set_attr "op_type" "RRE,RXY")])
3084 (define_insn "*adddi3_carry2_cconly"
3085 [(set (reg CC_REGNUM)
3086 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3087 (match_operand:DI 2 "general_operand" "d,m"))
3089 (clobber (match_scratch:DI 0 "=d,d"))]
3090 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3094 [(set_attr "op_type" "RRE,RXY")])
3096 (define_insn "*adddi3_cc"
3097 [(set (reg CC_REGNUM)
3098 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3099 (match_operand:DI 2 "general_operand" "d,m"))
3101 (set (match_operand:DI 0 "register_operand" "=d,d")
3102 (plus:DI (match_dup 1) (match_dup 2)))]
3103 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3107 [(set_attr "op_type" "RRE,RXY")])
3109 (define_insn "*adddi3_cconly"
3110 [(set (reg CC_REGNUM)
3111 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3112 (match_operand:DI 2 "general_operand" "d,m"))
3114 (clobber (match_scratch:DI 0 "=d,d"))]
3115 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3119 [(set_attr "op_type" "RRE,RXY")])
3121 (define_insn "*adddi3_cconly2"
3122 [(set (reg CC_REGNUM)
3123 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3124 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3125 (clobber (match_scratch:DI 0 "=d,d"))]
3126 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3130 [(set_attr "op_type" "RRE,RXY")])
3132 (define_insn "*adddi3_64"
3133 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3134 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3135 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3136 (clobber (reg:CC CC_REGNUM))]
3142 [(set_attr "op_type" "RRE,RI,RXY")])
3144 (define_insn_and_split "*adddi3_31z"
3145 [(set (match_operand:DI 0 "register_operand" "=&d")
3146 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3147 (match_operand:DI 2 "general_operand" "do") ) )
3148 (clobber (reg:CC CC_REGNUM))]
3149 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3151 "&& reload_completed"
3153 [(set (reg:CCL1 CC_REGNUM)
3154 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3156 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3158 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3159 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3160 (clobber (reg:CC CC_REGNUM))])]
3161 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3162 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3163 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3164 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3165 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3166 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3168 (define_insn_and_split "*adddi3_31"
3169 [(set (match_operand:DI 0 "register_operand" "=&d")
3170 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3171 (match_operand:DI 2 "general_operand" "do") ) )
3172 (clobber (reg:CC CC_REGNUM))]
3175 "&& reload_completed"
3177 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3178 (clobber (reg:CC CC_REGNUM))])
3180 [(set (reg:CCL1 CC_REGNUM)
3181 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3183 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3185 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3187 (label_ref (match_dup 9))))
3189 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3190 (clobber (reg:CC CC_REGNUM))])
3192 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3193 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3194 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3195 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3196 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3197 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3198 operands[9] = gen_label_rtx ();")
3200 (define_expand "adddi3"
3202 [(set (match_operand:DI 0 "register_operand" "")
3203 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3204 (match_operand:DI 2 "general_operand" "")))
3205 (clobber (reg:CC CC_REGNUM))])]
3210 ; addsi3 instruction pattern(s).
3213 (define_insn "*addsi3_imm_cc"
3214 [(set (reg CC_REGNUM)
3215 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3216 (match_operand:SI 2 "const_int_operand" "K"))
3218 (set (match_operand:SI 0 "register_operand" "=d")
3219 (plus:SI (match_dup 1) (match_dup 2)))]
3220 "s390_match_ccmode (insn, CCAmode)
3221 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3223 [(set_attr "op_type" "RI")])
3225 (define_insn "*addsi3_carry1_cc"
3226 [(set (reg CC_REGNUM)
3227 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3228 (match_operand:SI 2 "general_operand" "d,R,T"))
3230 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3231 (plus:SI (match_dup 1) (match_dup 2)))]
3232 "s390_match_ccmode (insn, CCL1mode)"
3237 [(set_attr "op_type" "RR,RX,RXY")])
3239 (define_insn "*addsi3_carry1_cconly"
3240 [(set (reg CC_REGNUM)
3241 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3242 (match_operand:SI 2 "general_operand" "d,R,T"))
3244 (clobber (match_scratch:SI 0 "=d,d,d"))]
3245 "s390_match_ccmode (insn, CCL1mode)"
3250 [(set_attr "op_type" "RR,RX,RXY")])
3252 (define_insn "*addsi3_carry2_cc"
3253 [(set (reg CC_REGNUM)
3254 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3255 (match_operand:SI 2 "general_operand" "d,R,T"))
3257 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3258 (plus:SI (match_dup 1) (match_dup 2)))]
3259 "s390_match_ccmode (insn, CCL1mode)"
3264 [(set_attr "op_type" "RR,RX,RXY")])
3266 (define_insn "*addsi3_carry2_cconly"
3267 [(set (reg CC_REGNUM)
3268 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3269 (match_operand:SI 2 "general_operand" "d,R,T"))
3271 (clobber (match_scratch:SI 0 "=d,d,d"))]
3272 "s390_match_ccmode (insn, CCL1mode)"
3277 [(set_attr "op_type" "RR,RX,RXY")])
3279 (define_insn "*addsi3_cc"
3280 [(set (reg CC_REGNUM)
3281 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3282 (match_operand:SI 2 "general_operand" "d,R,T"))
3284 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3285 (plus:SI (match_dup 1) (match_dup 2)))]
3286 "s390_match_ccmode (insn, CCLmode)"
3291 [(set_attr "op_type" "RR,RX,RXY")])
3293 (define_insn "*addsi3_cconly"
3294 [(set (reg CC_REGNUM)
3295 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3296 (match_operand:SI 2 "general_operand" "d,R,T"))
3298 (clobber (match_scratch:SI 0 "=d,d,d"))]
3299 "s390_match_ccmode (insn, CCLmode)"
3304 [(set_attr "op_type" "RR,RX,RXY")])
3306 (define_insn "*addsi3_cconly2"
3307 [(set (reg CC_REGNUM)
3308 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3309 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3310 (clobber (match_scratch:SI 0 "=d,d,d"))]
3311 "s390_match_ccmode (insn, CCLmode)"
3316 [(set_attr "op_type" "RR,RX,RXY")])
3318 (define_insn "*addsi3_sign"
3319 [(set (match_operand:SI 0 "register_operand" "=d,d")
3320 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3321 (match_operand:SI 1 "register_operand" "0,0")))
3322 (clobber (reg:CC CC_REGNUM))]
3327 [(set_attr "op_type" "RX,RXY")])
3329 (define_insn "addsi3"
3330 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3331 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3332 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3333 (clobber (reg:CC CC_REGNUM))]
3340 [(set_attr "op_type" "RR,RI,RX,RXY")])
3343 ; add(df|sf)3 instruction pattern(s).
3346 (define_expand "add<mode>3"
3348 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3349 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3350 (match_operand:FPR 2 "general_operand" "f,R")))
3351 (clobber (reg:CC CC_REGNUM))])]
3355 (define_insn "*add<mode>3"
3356 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3357 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3358 (match_operand:FPR 2 "general_operand" "f,R")))
3359 (clobber (reg:CC CC_REGNUM))]
3360 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3364 [(set_attr "op_type" "RRE,RXE")
3365 (set_attr "type" "fsimp<mode>")])
3367 (define_insn "*add<mode>3_cc"
3368 [(set (reg CC_REGNUM)
3369 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3370 (match_operand:FPR 2 "general_operand" "f,R"))
3371 (match_operand:FPR 3 "const0_operand" "")))
3372 (set (match_operand:FPR 0 "register_operand" "=f,f")
3373 (plus:FPR (match_dup 1) (match_dup 2)))]
3374 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3378 [(set_attr "op_type" "RRE,RXE")
3379 (set_attr "type" "fsimp<mode>")])
3381 (define_insn "*add<mode>3_cconly"
3382 [(set (reg CC_REGNUM)
3383 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3384 (match_operand:FPR 2 "general_operand" "f,R"))
3385 (match_operand:FPR 3 "const0_operand" "")))
3386 (clobber (match_scratch:FPR 0 "=f,f"))]
3387 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3391 [(set_attr "op_type" "RRE,RXE")
3392 (set_attr "type" "fsimp<mode>")])
3394 (define_insn "*add<mode>3_ibm"
3395 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3396 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3397 (match_operand:FPR 2 "general_operand" "f,R")))
3398 (clobber (reg:CC CC_REGNUM))]
3399 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3403 [(set_attr "op_type" "RR,RX")
3404 (set_attr "type" "fsimp<mode>")])
3408 ;;- Subtract instructions.
3412 ; subti3 instruction pattern(s).
3415 (define_insn_and_split "subti3"
3416 [(set (match_operand:TI 0 "register_operand" "=&d")
3417 (minus:TI (match_operand:TI 1 "register_operand" "0")
3418 (match_operand:TI 2 "general_operand" "do") ) )
3419 (clobber (reg:CC CC_REGNUM))]
3422 "&& reload_completed"
3424 [(set (reg:CCL2 CC_REGNUM)
3425 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3427 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3429 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3430 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3431 (clobber (reg:CC CC_REGNUM))])]
3432 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3433 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3434 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3435 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3436 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3437 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3440 ; subdi3 instruction pattern(s).
3443 (define_insn "*subdi3_sign"
3444 [(set (match_operand:DI 0 "register_operand" "=d,d")
3445 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3446 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3447 (clobber (reg:CC CC_REGNUM))]
3452 [(set_attr "op_type" "RRE,RXY")])
3454 (define_insn "*subdi3_zero_cc"
3455 [(set (reg CC_REGNUM)
3456 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3457 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3459 (set (match_operand:DI 0 "register_operand" "=d,d")
3460 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3461 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3465 [(set_attr "op_type" "RRE,RXY")])
3467 (define_insn "*subdi3_zero_cconly"
3468 [(set (reg CC_REGNUM)
3469 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3470 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3472 (clobber (match_scratch:DI 0 "=d,d"))]
3473 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3477 [(set_attr "op_type" "RRE,RXY")])
3479 (define_insn "*subdi3_zero"
3480 [(set (match_operand:DI 0 "register_operand" "=d,d")
3481 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3482 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3483 (clobber (reg:CC CC_REGNUM))]
3488 [(set_attr "op_type" "RRE,RXY")])
3490 (define_insn "*subdi3_borrow_cc"
3491 [(set (reg CC_REGNUM)
3492 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3493 (match_operand:DI 2 "general_operand" "d,m"))
3495 (set (match_operand:DI 0 "register_operand" "=d,d")
3496 (minus:DI (match_dup 1) (match_dup 2)))]
3497 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3501 [(set_attr "op_type" "RRE,RXY")])
3503 (define_insn "*subdi3_borrow_cconly"
3504 [(set (reg CC_REGNUM)
3505 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3506 (match_operand:DI 2 "general_operand" "d,m"))
3508 (clobber (match_scratch:DI 0 "=d,d"))]
3509 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3513 [(set_attr "op_type" "RRE,RXY")])
3515 (define_insn "*subdi3_cc"
3516 [(set (reg CC_REGNUM)
3517 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3518 (match_operand:DI 2 "general_operand" "d,m"))
3520 (set (match_operand:DI 0 "register_operand" "=d,d")
3521 (minus:DI (match_dup 1) (match_dup 2)))]
3522 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3526 [(set_attr "op_type" "RRE,RXY")])
3528 (define_insn "*subdi3_cc2"
3529 [(set (reg CC_REGNUM)
3530 (compare (match_operand:DI 1 "register_operand" "0,0")
3531 (match_operand:DI 2 "general_operand" "d,m")))
3532 (set (match_operand:DI 0 "register_operand" "=d,d")
3533 (minus:DI (match_dup 1) (match_dup 2)))]
3534 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3538 [(set_attr "op_type" "RRE,RXY")])
3540 (define_insn "*subdi3_cconly"
3541 [(set (reg CC_REGNUM)
3542 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3543 (match_operand:DI 2 "general_operand" "d,m"))
3545 (clobber (match_scratch:DI 0 "=d,d"))]
3546 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3550 [(set_attr "op_type" "RRE,RXY")])
3552 (define_insn "*subdi3_cconly2"
3553 [(set (reg CC_REGNUM)
3554 (compare (match_operand:DI 1 "register_operand" "0,0")
3555 (match_operand:DI 2 "general_operand" "d,m")))
3556 (clobber (match_scratch:DI 0 "=d,d"))]
3557 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3561 [(set_attr "op_type" "RRE,RXY")])
3563 (define_insn "*subdi3_64"
3564 [(set (match_operand:DI 0 "register_operand" "=d,d")
3565 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3566 (match_operand:DI 2 "general_operand" "d,m") ) )
3567 (clobber (reg:CC CC_REGNUM))]
3572 [(set_attr "op_type" "RRE,RRE")])
3574 (define_insn_and_split "*subdi3_31z"
3575 [(set (match_operand:DI 0 "register_operand" "=&d")
3576 (minus:DI (match_operand:DI 1 "register_operand" "0")
3577 (match_operand:DI 2 "general_operand" "do") ) )
3578 (clobber (reg:CC CC_REGNUM))]
3579 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3581 "&& reload_completed"
3583 [(set (reg:CCL2 CC_REGNUM)
3584 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3586 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3588 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3589 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3590 (clobber (reg:CC CC_REGNUM))])]
3591 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3592 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3593 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3594 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3595 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3596 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3598 (define_insn_and_split "*subdi3_31"
3599 [(set (match_operand:DI 0 "register_operand" "=&d")
3600 (minus:DI (match_operand:DI 1 "register_operand" "0")
3601 (match_operand:DI 2 "general_operand" "do") ) )
3602 (clobber (reg:CC CC_REGNUM))]
3605 "&& reload_completed"
3607 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3608 (clobber (reg:CC CC_REGNUM))])
3610 [(set (reg:CCL2 CC_REGNUM)
3611 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3613 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3615 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3617 (label_ref (match_dup 9))))
3619 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3620 (clobber (reg:CC CC_REGNUM))])
3622 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3623 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3624 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3625 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3626 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3627 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3628 operands[9] = gen_label_rtx ();")
3630 (define_expand "subdi3"
3632 [(set (match_operand:DI 0 "register_operand" "")
3633 (minus:DI (match_operand:DI 1 "register_operand" "")
3634 (match_operand:DI 2 "general_operand" "")))
3635 (clobber (reg:CC CC_REGNUM))])]
3640 ; subsi3 instruction pattern(s).
3643 (define_insn "*subsi3_borrow_cc"
3644 [(set (reg CC_REGNUM)
3645 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3646 (match_operand:SI 2 "general_operand" "d,R,T"))
3648 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3649 (minus:SI (match_dup 1) (match_dup 2)))]
3650 "s390_match_ccmode (insn, CCL2mode)"
3655 [(set_attr "op_type" "RR,RX,RXY")])
3657 (define_insn "*subsi3_borrow_cconly"
3658 [(set (reg CC_REGNUM)
3659 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3660 (match_operand:SI 2 "general_operand" "d,R,T"))
3662 (clobber (match_scratch:SI 0 "=d,d,d"))]
3663 "s390_match_ccmode (insn, CCL2mode)"
3668 [(set_attr "op_type" "RR,RX,RXY")])
3670 (define_insn "*subsi3_cc"
3671 [(set (reg CC_REGNUM)
3672 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3673 (match_operand:SI 2 "general_operand" "d,R,T"))
3675 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3676 (minus:SI (match_dup 1) (match_dup 2)))]
3677 "s390_match_ccmode (insn, CCLmode)"
3682 [(set_attr "op_type" "RR,RX,RXY")])
3684 (define_insn "*subsi3_cc2"
3685 [(set (reg CC_REGNUM)
3686 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3687 (match_operand:SI 2 "general_operand" "d,R,T")))
3688 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3689 (minus:SI (match_dup 1) (match_dup 2)))]
3690 "s390_match_ccmode (insn, CCL3mode)"
3695 [(set_attr "op_type" "RR,RX,RXY")])
3697 (define_insn "*subsi3_cconly"
3698 [(set (reg CC_REGNUM)
3699 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3700 (match_operand:SI 2 "general_operand" "d,R,T"))
3702 (clobber (match_scratch:SI 0 "=d,d,d"))]
3703 "s390_match_ccmode (insn, CCLmode)"
3708 [(set_attr "op_type" "RR,RX,RXY")])
3710 (define_insn "*subsi3_cconly2"
3711 [(set (reg CC_REGNUM)
3712 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3713 (match_operand:SI 2 "general_operand" "d,R,T")))
3714 (clobber (match_scratch:SI 0 "=d,d,d"))]
3715 "s390_match_ccmode (insn, CCL3mode)"
3720 [(set_attr "op_type" "RR,RX,RXY")])
3722 (define_insn "*subsi3_sign"
3723 [(set (match_operand:SI 0 "register_operand" "=d,d")
3724 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3725 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3726 (clobber (reg:CC CC_REGNUM))]
3731 [(set_attr "op_type" "RX,RXY")])
3733 (define_insn "subsi3"
3734 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3735 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3736 (match_operand:SI 2 "general_operand" "d,R,T")))
3737 (clobber (reg:CC CC_REGNUM))]
3743 [(set_attr "op_type" "RR,RX,RXY")])
3747 ; sub(df|sf)3 instruction pattern(s).
3750 (define_expand "sub<mode>3"
3752 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3753 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3754 (match_operand:FPR 2 "general_operand" "f,R")))
3755 (clobber (reg:CC CC_REGNUM))])]
3759 (define_insn "*sub<mode>3"
3760 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3761 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3762 (match_operand:FPR 2 "general_operand" "f,R")))
3763 (clobber (reg:CC CC_REGNUM))]
3764 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3768 [(set_attr "op_type" "RRE,RXE")
3769 (set_attr "type" "fsimp<mode>")])
3771 (define_insn "*sub<mode>3_cc"
3772 [(set (reg CC_REGNUM)
3773 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3774 (match_operand:FPR 2 "general_operand" "f,R"))
3775 (match_operand:FPR 3 "const0_operand" "")))
3776 (set (match_operand:FPR 0 "register_operand" "=f,f")
3777 (minus:FPR (match_dup 1) (match_dup 2)))]
3778 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3782 [(set_attr "op_type" "RRE,RXE")
3783 (set_attr "type" "fsimp<mode>")])
3785 (define_insn "*sub<mode>3_cconly"
3786 [(set (reg CC_REGNUM)
3787 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3788 (match_operand:FPR 2 "general_operand" "f,R"))
3789 (match_operand:FPR 3 "const0_operand" "")))
3790 (clobber (match_scratch:FPR 0 "=f,f"))]
3791 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3795 [(set_attr "op_type" "RRE,RXE")
3796 (set_attr "type" "fsimp<mode>")])
3798 (define_insn "*sub<mode>3_ibm"
3799 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3800 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3801 (match_operand:FPR 2 "general_operand" "f,R")))
3802 (clobber (reg:CC CC_REGNUM))]
3803 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3807 [(set_attr "op_type" "RR,RX")
3808 (set_attr "type" "fsimp<mode>")])
3812 ;;- Conditional add/subtract instructions.
3816 ; add(di|si)cc instruction pattern(s).
3819 (define_insn "*add<mode>3_alc_cc"
3820 [(set (reg CC_REGNUM)
3822 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3823 (match_operand:GPR 2 "general_operand" "d,m"))
3824 (match_operand:GPR 3 "s390_alc_comparison" ""))
3826 (set (match_operand:GPR 0 "register_operand" "=d,d")
3827 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3828 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3832 [(set_attr "op_type" "RRE,RXY")])
3834 (define_insn "*add<mode>3_alc"
3835 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3836 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3837 (match_operand:GPR 2 "general_operand" "d,m"))
3838 (match_operand:GPR 3 "s390_alc_comparison" "")))
3839 (clobber (reg:CC CC_REGNUM))]
3844 [(set_attr "op_type" "RRE,RXY")])
3846 (define_insn "*sub<mode>3_slb_cc"
3847 [(set (reg CC_REGNUM)
3849 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3850 (match_operand:GPR 2 "general_operand" "d,m"))
3851 (match_operand:GPR 3 "s390_slb_comparison" ""))
3853 (set (match_operand:GPR 0 "register_operand" "=d,d")
3854 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3855 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3859 [(set_attr "op_type" "RRE,RXY")])
3861 (define_insn "*sub<mode>3_slb"
3862 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3863 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3864 (match_operand:GPR 2 "general_operand" "d,m"))
3865 (match_operand:GPR 3 "s390_slb_comparison" "")))
3866 (clobber (reg:CC CC_REGNUM))]
3871 [(set_attr "op_type" "RRE,RXY")])
3873 (define_expand "add<mode>cc"
3874 [(match_operand:GPR 0 "register_operand" "")
3875 (match_operand 1 "comparison_operator" "")
3876 (match_operand:GPR 2 "register_operand" "")
3877 (match_operand:GPR 3 "const_int_operand" "")]
3879 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3880 s390_compare_op0, s390_compare_op1,
3881 operands[0], operands[2],
3882 operands[3])) FAIL; DONE;")
3885 ; scond instruction pattern(s).
3888 (define_insn_and_split "*scond<mode>"
3889 [(set (match_operand:GPR 0 "register_operand" "=&d")
3890 (match_operand:GPR 1 "s390_alc_comparison" ""))
3891 (clobber (reg:CC CC_REGNUM))]
3894 "&& reload_completed"
3895 [(set (match_dup 0) (const_int 0))
3897 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3899 (clobber (reg:CC CC_REGNUM))])]
3902 (define_insn_and_split "*scond<mode>_neg"
3903 [(set (match_operand:GPR 0 "register_operand" "=&d")
3904 (match_operand:GPR 1 "s390_slb_comparison" ""))
3905 (clobber (reg:CC CC_REGNUM))]
3908 "&& reload_completed"
3909 [(set (match_dup 0) (const_int 0))
3911 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3913 (clobber (reg:CC CC_REGNUM))])
3915 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3916 (clobber (reg:CC CC_REGNUM))])]
3920 (define_expand "s<code>"
3921 [(set (match_operand:SI 0 "register_operand" "")
3922 (SCOND (match_dup 0)
3925 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3926 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3930 ;;- Multiply instructions.
3934 ; muldi3 instruction pattern(s).
3937 (define_insn "*muldi3_sign"
3938 [(set (match_operand:DI 0 "register_operand" "=d,d")
3939 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3940 (match_operand:DI 1 "register_operand" "0,0")))]
3945 [(set_attr "op_type" "RRE,RXY")
3946 (set_attr "type" "imuldi")])
3948 (define_insn "muldi3"
3949 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3950 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3951 (match_operand:DI 2 "general_operand" "d,K,m")))]
3957 [(set_attr "op_type" "RRE,RI,RXY")
3958 (set_attr "type" "imuldi")])
3961 ; mulsi3 instruction pattern(s).
3964 (define_insn "*mulsi3_sign"
3965 [(set (match_operand:SI 0 "register_operand" "=d")
3966 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
3967 (match_operand:SI 1 "register_operand" "0")))]
3970 [(set_attr "op_type" "RX")
3971 (set_attr "type" "imulhi")])
3973 (define_insn "mulsi3"
3974 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3975 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3976 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
3983 [(set_attr "op_type" "RRE,RI,RX,RXY")
3984 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
3987 ; mulsidi3 instruction pattern(s).
3990 (define_insn "mulsidi3"
3991 [(set (match_operand:DI 0 "register_operand" "=d,d")
3992 (mult:DI (sign_extend:DI
3993 (match_operand:SI 1 "register_operand" "%0,0"))
3995 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4000 [(set_attr "op_type" "RR,RX")
4001 (set_attr "type" "imulsi")])
4004 ; umulsidi3 instruction pattern(s).
4007 (define_insn "umulsidi3"
4008 [(set (match_operand:DI 0 "register_operand" "=d,d")
4009 (mult:DI (zero_extend:DI
4010 (match_operand:SI 1 "register_operand" "%0,0"))
4012 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4013 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4017 [(set_attr "op_type" "RRE,RXY")
4018 (set_attr "type" "imulsi")])
4021 ; mul(df|sf)3 instruction pattern(s).
4024 (define_expand "mul<mode>3"
4025 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4026 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4027 (match_operand:FPR 2 "general_operand" "f,R")))]
4031 (define_insn "*mul<mode>3"
4032 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4033 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4034 (match_operand:FPR 2 "general_operand" "f,R")))]
4035 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4039 [(set_attr "op_type" "RRE,RXE")
4040 (set_attr "type" "fmul<mode>")])
4042 (define_insn "*mul<mode>3_ibm"
4043 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4044 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4045 (match_operand:FPR 2 "general_operand" "f,R")))]
4046 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4050 [(set_attr "op_type" "RR,RX")
4051 (set_attr "type" "fmul<mode>")])
4053 (define_insn "*fmadd<mode>"
4054 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4055 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4056 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4057 (match_operand:FPR 3 "register_operand" "0,0")))]
4058 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4062 [(set_attr "op_type" "RRE,RXE")
4063 (set_attr "type" "fmul<mode>")])
4065 (define_insn "*fmsub<mode>"
4066 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4067 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4068 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4069 (match_operand:FPR 3 "register_operand" "0,0")))]
4070 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4074 [(set_attr "op_type" "RRE,RXE")
4075 (set_attr "type" "fmul<mode>")])
4078 ;;- Divide and modulo instructions.
4082 ; divmoddi4 instruction pattern(s).
4085 (define_expand "divmoddi4"
4086 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4087 (div:DI (match_operand:DI 1 "register_operand" "")
4088 (match_operand:DI 2 "general_operand" "")))
4089 (set (match_operand:DI 3 "general_operand" "")
4090 (mod:DI (match_dup 1) (match_dup 2)))])
4091 (clobber (match_dup 4))]
4094 rtx insn, div_equal, mod_equal;
4096 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4097 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4099 operands[4] = gen_reg_rtx(TImode);
4100 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4102 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4104 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4106 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4108 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4113 (define_insn "divmodtidi3"
4114 [(set (match_operand:TI 0 "register_operand" "=d,d")
4118 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4119 (match_operand:DI 2 "general_operand" "d,m")))
4121 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4126 [(set_attr "op_type" "RRE,RXY")
4127 (set_attr "type" "idiv")])
4129 (define_insn "divmodtisi3"
4130 [(set (match_operand:TI 0 "register_operand" "=d,d")
4134 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4136 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4139 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4144 [(set_attr "op_type" "RRE,RXY")
4145 (set_attr "type" "idiv")])
4148 ; udivmoddi4 instruction pattern(s).
4151 (define_expand "udivmoddi4"
4152 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4153 (udiv:DI (match_operand:DI 1 "general_operand" "")
4154 (match_operand:DI 2 "nonimmediate_operand" "")))
4155 (set (match_operand:DI 3 "general_operand" "")
4156 (umod:DI (match_dup 1) (match_dup 2)))])
4157 (clobber (match_dup 4))]
4160 rtx insn, div_equal, mod_equal, equal;
4162 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4163 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4164 equal = gen_rtx_IOR (TImode,
4165 gen_rtx_ASHIFT (TImode,
4166 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4168 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4170 operands[4] = gen_reg_rtx(TImode);
4171 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4172 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4173 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4174 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4176 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4178 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4180 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4182 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4184 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4189 (define_insn "udivmodtidi3"
4190 [(set (match_operand:TI 0 "register_operand" "=d,d")
4195 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4197 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4201 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4206 [(set_attr "op_type" "RRE,RXY")
4207 (set_attr "type" "idiv")])
4210 ; divmodsi4 instruction pattern(s).
4213 (define_expand "divmodsi4"
4214 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4215 (div:SI (match_operand:SI 1 "general_operand" "")
4216 (match_operand:SI 2 "nonimmediate_operand" "")))
4217 (set (match_operand:SI 3 "general_operand" "")
4218 (mod:SI (match_dup 1) (match_dup 2)))])
4219 (clobber (match_dup 4))]
4222 rtx insn, div_equal, mod_equal, equal;
4224 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4225 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4226 equal = gen_rtx_IOR (DImode,
4227 gen_rtx_ASHIFT (DImode,
4228 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4230 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4232 operands[4] = gen_reg_rtx(DImode);
4233 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4234 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4236 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4238 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4240 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4242 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4244 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4249 (define_insn "divmoddisi3"
4250 [(set (match_operand:DI 0 "register_operand" "=d,d")
4255 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4257 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4261 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4266 [(set_attr "op_type" "RR,RX")
4267 (set_attr "type" "idiv")])
4270 ; udivsi3 and umodsi3 instruction pattern(s).
4273 (define_expand "udivmodsi4"
4274 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4275 (udiv:SI (match_operand:SI 1 "general_operand" "")
4276 (match_operand:SI 2 "nonimmediate_operand" "")))
4277 (set (match_operand:SI 3 "general_operand" "")
4278 (umod:SI (match_dup 1) (match_dup 2)))])
4279 (clobber (match_dup 4))]
4280 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4282 rtx insn, div_equal, mod_equal, equal;
4284 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4285 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4286 equal = gen_rtx_IOR (DImode,
4287 gen_rtx_ASHIFT (DImode,
4288 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4290 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4292 operands[4] = gen_reg_rtx(DImode);
4293 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4294 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4295 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4296 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4298 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4300 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4302 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4304 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4306 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4311 (define_insn "udivmoddisi3"
4312 [(set (match_operand:DI 0 "register_operand" "=d,d")
4317 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4319 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4323 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4324 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4328 [(set_attr "op_type" "RRE,RXY")
4329 (set_attr "type" "idiv")])
4331 (define_expand "udivsi3"
4332 [(set (match_operand:SI 0 "register_operand" "=d")
4333 (udiv:SI (match_operand:SI 1 "general_operand" "")
4334 (match_operand:SI 2 "general_operand" "")))
4335 (clobber (match_dup 3))]
4336 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4338 rtx insn, udiv_equal, umod_equal, equal;
4340 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4341 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4342 equal = gen_rtx_IOR (DImode,
4343 gen_rtx_ASHIFT (DImode,
4344 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4346 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4348 operands[3] = gen_reg_rtx (DImode);
4350 if (CONSTANT_P (operands[2]))
4352 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4354 rtx label1 = gen_label_rtx ();
4356 operands[1] = make_safe_from (operands[1], operands[0]);
4357 emit_move_insn (operands[0], const0_rtx);
4358 emit_insn (gen_cmpsi (operands[1], operands[2]));
4359 emit_jump_insn (gen_bltu (label1));
4360 emit_move_insn (operands[0], const1_rtx);
4361 emit_label (label1);
4365 operands[2] = force_reg (SImode, operands[2]);
4366 operands[2] = make_safe_from (operands[2], operands[0]);
4368 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4369 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4372 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4374 insn = emit_move_insn (operands[0],
4375 gen_lowpart (SImode, operands[3]));
4377 gen_rtx_EXPR_LIST (REG_EQUAL,
4378 udiv_equal, REG_NOTES (insn));
4383 rtx label1 = gen_label_rtx ();
4384 rtx label2 = gen_label_rtx ();
4385 rtx label3 = gen_label_rtx ();
4387 operands[1] = force_reg (SImode, operands[1]);
4388 operands[1] = make_safe_from (operands[1], operands[0]);
4389 operands[2] = force_reg (SImode, operands[2]);
4390 operands[2] = make_safe_from (operands[2], operands[0]);
4392 emit_move_insn (operands[0], const0_rtx);
4393 emit_insn (gen_cmpsi (operands[2], operands[1]));
4394 emit_jump_insn (gen_bgtu (label3));
4395 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4396 emit_jump_insn (gen_blt (label2));
4397 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4398 emit_jump_insn (gen_beq (label1));
4399 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4400 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4403 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4405 insn = emit_move_insn (operands[0],
4406 gen_lowpart (SImode, operands[3]));
4408 gen_rtx_EXPR_LIST (REG_EQUAL,
4409 udiv_equal, REG_NOTES (insn));
4411 emit_label (label1);
4412 emit_move_insn (operands[0], operands[1]);
4414 emit_label (label2);
4415 emit_move_insn (operands[0], const1_rtx);
4416 emit_label (label3);
4418 emit_move_insn (operands[0], operands[0]);
4422 (define_expand "umodsi3"
4423 [(set (match_operand:SI 0 "register_operand" "=d")
4424 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4425 (match_operand:SI 2 "nonimmediate_operand" "")))
4426 (clobber (match_dup 3))]
4427 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4429 rtx insn, udiv_equal, umod_equal, equal;
4431 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4432 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4433 equal = gen_rtx_IOR (DImode,
4434 gen_rtx_ASHIFT (DImode,
4435 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4437 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4439 operands[3] = gen_reg_rtx (DImode);
4441 if (CONSTANT_P (operands[2]))
4443 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4445 rtx label1 = gen_label_rtx ();
4447 operands[1] = make_safe_from (operands[1], operands[0]);
4448 emit_move_insn (operands[0], operands[1]);
4449 emit_insn (gen_cmpsi (operands[0], operands[2]));
4450 emit_jump_insn (gen_bltu (label1));
4451 emit_insn (gen_abssi2 (operands[0], operands[2]));
4452 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4453 emit_label (label1);
4457 operands[2] = force_reg (SImode, operands[2]);
4458 operands[2] = make_safe_from (operands[2], operands[0]);
4460 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4461 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4464 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4466 insn = emit_move_insn (operands[0],
4467 gen_highpart (SImode, operands[3]));
4469 gen_rtx_EXPR_LIST (REG_EQUAL,
4470 umod_equal, REG_NOTES (insn));
4475 rtx label1 = gen_label_rtx ();
4476 rtx label2 = gen_label_rtx ();
4477 rtx label3 = gen_label_rtx ();
4479 operands[1] = force_reg (SImode, operands[1]);
4480 operands[1] = make_safe_from (operands[1], operands[0]);
4481 operands[2] = force_reg (SImode, operands[2]);
4482 operands[2] = make_safe_from (operands[2], operands[0]);
4484 emit_move_insn(operands[0], operands[1]);
4485 emit_insn (gen_cmpsi (operands[2], operands[1]));
4486 emit_jump_insn (gen_bgtu (label3));
4487 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4488 emit_jump_insn (gen_blt (label2));
4489 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4490 emit_jump_insn (gen_beq (label1));
4491 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4492 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4495 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4497 insn = emit_move_insn (operands[0],
4498 gen_highpart (SImode, operands[3]));
4500 gen_rtx_EXPR_LIST (REG_EQUAL,
4501 umod_equal, REG_NOTES (insn));
4503 emit_label (label1);
4504 emit_move_insn (operands[0], const0_rtx);
4506 emit_label (label2);
4507 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4508 emit_label (label3);
4514 ; div(df|sf)3 instruction pattern(s).
4517 (define_expand "div<mode>3"
4518 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4519 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4520 (match_operand:FPR 2 "general_operand" "f,R")))]
4524 (define_insn "*div<mode>3"
4525 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4526 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4527 (match_operand:FPR 2 "general_operand" "f,R")))]
4528 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4532 [(set_attr "op_type" "RRE,RXE")
4533 (set_attr "type" "fdiv<mode>")])
4535 (define_insn "*div<mode>3_ibm"
4536 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4537 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4538 (match_operand:FPR 2 "general_operand" "f,R")))]
4539 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4543 [(set_attr "op_type" "RR,RX")
4544 (set_attr "type" "fdiv<mode>")])
4548 ;;- And instructions.
4551 (define_expand "and<mode>3"
4552 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4553 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4554 (match_operand:INT 2 "general_operand" "")))
4555 (clobber (reg:CC CC_REGNUM))]
4557 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4560 ; anddi3 instruction pattern(s).
4563 (define_insn "*anddi3_cc"
4564 [(set (reg CC_REGNUM)
4565 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4566 (match_operand:DI 2 "general_operand" "d,m"))
4568 (set (match_operand:DI 0 "register_operand" "=d,d")
4569 (and:DI (match_dup 1) (match_dup 2)))]
4570 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4574 [(set_attr "op_type" "RRE,RXY")])
4576 (define_insn "*anddi3_cconly"
4577 [(set (reg CC_REGNUM)
4578 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4579 (match_operand:DI 2 "general_operand" "d,m"))
4581 (clobber (match_scratch:DI 0 "=d,d"))]
4582 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4583 /* Do not steal TM patterns. */
4584 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4588 [(set_attr "op_type" "RRE,RXY")])
4590 (define_insn "*anddi3"
4591 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4592 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4593 "%d,o,0,0,0,0,0,0,0,0")
4594 (match_operand:DI 2 "general_operand"
4595 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4596 (clobber (reg:CC CC_REGNUM))]
4597 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4609 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4612 [(set (match_operand:DI 0 "s_operand" "")
4613 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4614 (clobber (reg:CC CC_REGNUM))]
4617 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4618 (clobber (reg:CC CC_REGNUM))])]
4619 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4623 ; andsi3 instruction pattern(s).
4626 (define_insn "*andsi3_cc"
4627 [(set (reg CC_REGNUM)
4628 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4629 (match_operand:SI 2 "general_operand" "d,R,T"))
4631 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4632 (and:SI (match_dup 1) (match_dup 2)))]
4633 "s390_match_ccmode(insn, CCTmode)"
4638 [(set_attr "op_type" "RR,RX,RXY")])
4640 (define_insn "*andsi3_cconly"
4641 [(set (reg CC_REGNUM)
4642 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4643 (match_operand:SI 2 "general_operand" "d,R,T"))
4645 (clobber (match_scratch:SI 0 "=d,d,d"))]
4646 "s390_match_ccmode(insn, CCTmode)
4647 /* Do not steal TM patterns. */
4648 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4653 [(set_attr "op_type" "RR,RX,RXY")])
4655 (define_insn "*andsi3_zarch"
4656 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4657 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4658 "%d,o,0,0,0,0,0,0,0")
4659 (match_operand:SI 2 "general_operand"
4660 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4661 (clobber (reg:CC CC_REGNUM))]
4662 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4673 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4675 (define_insn "*andsi3_esa"
4676 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4677 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4678 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4679 (clobber (reg:CC CC_REGNUM))]
4680 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4686 [(set_attr "op_type" "RR,RX,SI,SS")])
4689 [(set (match_operand:SI 0 "s_operand" "")
4690 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4691 (clobber (reg:CC CC_REGNUM))]
4694 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4695 (clobber (reg:CC CC_REGNUM))])]
4696 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4699 ; andhi3 instruction pattern(s).
4702 (define_insn "*andhi3_zarch"
4703 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4704 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4705 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4706 (clobber (reg:CC CC_REGNUM))]
4707 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4713 [(set_attr "op_type" "RR,RI,SI,SS")])
4715 (define_insn "*andhi3_esa"
4716 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4717 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4718 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4719 (clobber (reg:CC CC_REGNUM))]
4720 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4725 [(set_attr "op_type" "RR,SI,SS")])
4728 [(set (match_operand:HI 0 "s_operand" "")
4729 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4730 (clobber (reg:CC CC_REGNUM))]
4733 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4734 (clobber (reg:CC CC_REGNUM))])]
4735 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4738 ; andqi3 instruction pattern(s).
4741 (define_insn "*andqi3_zarch"
4742 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4743 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4744 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4745 (clobber (reg:CC CC_REGNUM))]
4746 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4753 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4755 (define_insn "*andqi3_esa"
4756 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4757 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4758 (match_operand:QI 2 "general_operand" "d,n,Q")))
4759 (clobber (reg:CC CC_REGNUM))]
4760 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4765 [(set_attr "op_type" "RR,SI,SS")])
4768 ; Block and (NC) patterns.
4772 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4773 (and:BLK (match_dup 0)
4774 (match_operand:BLK 1 "memory_operand" "Q")))
4775 (use (match_operand 2 "const_int_operand" "n"))
4776 (clobber (reg:CC CC_REGNUM))]
4777 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4778 "nc\t%O0(%2,%R0),%S1"
4779 [(set_attr "op_type" "SS")])
4782 [(set (match_operand 0 "memory_operand" "")
4784 (match_operand 1 "memory_operand" "")))
4785 (clobber (reg:CC CC_REGNUM))]
4787 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4788 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4790 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4792 (clobber (reg:CC CC_REGNUM))])]
4794 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4795 operands[0] = adjust_address (operands[0], BLKmode, 0);
4796 operands[1] = adjust_address (operands[1], BLKmode, 0);
4801 [(set (match_operand:BLK 0 "memory_operand" "")
4802 (and:BLK (match_dup 0)
4803 (match_operand:BLK 1 "memory_operand" "")))
4804 (use (match_operand 2 "const_int_operand" ""))
4805 (clobber (reg:CC CC_REGNUM))])
4807 [(set (match_operand:BLK 3 "memory_operand" "")
4808 (and:BLK (match_dup 3)
4809 (match_operand:BLK 4 "memory_operand" "")))
4810 (use (match_operand 5 "const_int_operand" ""))
4811 (clobber (reg:CC CC_REGNUM))])]
4812 "s390_offset_p (operands[0], operands[3], operands[2])
4813 && s390_offset_p (operands[1], operands[4], operands[2])
4814 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4816 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4818 (clobber (reg:CC CC_REGNUM))])]
4819 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4820 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4821 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4825 ;;- Bit set (inclusive or) instructions.
4828 (define_expand "ior<mode>3"
4829 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4830 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4831 (match_operand:INT 2 "general_operand" "")))
4832 (clobber (reg:CC CC_REGNUM))]
4834 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4837 ; iordi3 instruction pattern(s).
4840 (define_insn "*iordi3_cc"
4841 [(set (reg CC_REGNUM)
4842 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4843 (match_operand:DI 2 "general_operand" "d,m"))
4845 (set (match_operand:DI 0 "register_operand" "=d,d")
4846 (ior:DI (match_dup 1) (match_dup 2)))]
4847 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4851 [(set_attr "op_type" "RRE,RXY")])
4853 (define_insn "*iordi3_cconly"
4854 [(set (reg CC_REGNUM)
4855 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4856 (match_operand:DI 2 "general_operand" "d,m"))
4858 (clobber (match_scratch:DI 0 "=d,d"))]
4859 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4863 [(set_attr "op_type" "RRE,RXY")])
4865 (define_insn "*iordi3"
4866 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4867 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4868 (match_operand:DI 2 "general_operand"
4869 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4870 (clobber (reg:CC CC_REGNUM))]
4871 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4881 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4884 [(set (match_operand:DI 0 "s_operand" "")
4885 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4886 (clobber (reg:CC CC_REGNUM))]
4889 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4890 (clobber (reg:CC CC_REGNUM))])]
4891 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4894 ; iorsi3 instruction pattern(s).
4897 (define_insn "*iorsi3_cc"
4898 [(set (reg CC_REGNUM)
4899 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4900 (match_operand:SI 2 "general_operand" "d,R,T"))
4902 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4903 (ior:SI (match_dup 1) (match_dup 2)))]
4904 "s390_match_ccmode(insn, CCTmode)"
4909 [(set_attr "op_type" "RR,RX,RXY")])
4911 (define_insn "*iorsi3_cconly"
4912 [(set (reg CC_REGNUM)
4913 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4914 (match_operand:SI 2 "general_operand" "d,R,T"))
4916 (clobber (match_scratch:SI 0 "=d,d,d"))]
4917 "s390_match_ccmode(insn, CCTmode)"
4922 [(set_attr "op_type" "RR,RX,RXY")])
4924 (define_insn "*iorsi3_zarch"
4925 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
4926 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4927 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
4928 (clobber (reg:CC CC_REGNUM))]
4929 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4938 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
4940 (define_insn "*iorsi3_esa"
4941 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4942 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4943 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
4944 (clobber (reg:CC CC_REGNUM))]
4945 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4951 [(set_attr "op_type" "RR,RX,SI,SS")])
4954 [(set (match_operand:SI 0 "s_operand" "")
4955 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4956 (clobber (reg:CC CC_REGNUM))]
4959 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4960 (clobber (reg:CC CC_REGNUM))])]
4961 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4964 ; iorhi3 instruction pattern(s).
4967 (define_insn "*iorhi3_zarch"
4968 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4969 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4970 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
4971 (clobber (reg:CC CC_REGNUM))]
4972 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4978 [(set_attr "op_type" "RR,RI,SI,SS")])
4980 (define_insn "*iorhi3_esa"
4981 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4982 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4983 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
4984 (clobber (reg:CC CC_REGNUM))]
4985 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4990 [(set_attr "op_type" "RR,SI,SS")])
4993 [(set (match_operand:HI 0 "s_operand" "")
4994 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4995 (clobber (reg:CC CC_REGNUM))]
4998 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4999 (clobber (reg:CC CC_REGNUM))])]
5000 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5003 ; iorqi3 instruction pattern(s).
5006 (define_insn "*iorqi3_zarch"
5007 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5008 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5009 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5010 (clobber (reg:CC CC_REGNUM))]
5011 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5018 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5020 (define_insn "*iorqi3_esa"
5021 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5022 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5023 (match_operand:QI 2 "general_operand" "d,n,Q")))
5024 (clobber (reg:CC CC_REGNUM))]
5025 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5030 [(set_attr "op_type" "RR,SI,SS")])
5033 ; Block inclusive or (OC) patterns.
5037 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5038 (ior:BLK (match_dup 0)
5039 (match_operand:BLK 1 "memory_operand" "Q")))
5040 (use (match_operand 2 "const_int_operand" "n"))
5041 (clobber (reg:CC CC_REGNUM))]
5042 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5043 "oc\t%O0(%2,%R0),%S1"
5044 [(set_attr "op_type" "SS")])
5047 [(set (match_operand 0 "memory_operand" "")
5049 (match_operand 1 "memory_operand" "")))
5050 (clobber (reg:CC CC_REGNUM))]
5052 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5053 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5055 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5057 (clobber (reg:CC CC_REGNUM))])]
5059 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5060 operands[0] = adjust_address (operands[0], BLKmode, 0);
5061 operands[1] = adjust_address (operands[1], BLKmode, 0);
5066 [(set (match_operand:BLK 0 "memory_operand" "")
5067 (ior:BLK (match_dup 0)
5068 (match_operand:BLK 1 "memory_operand" "")))
5069 (use (match_operand 2 "const_int_operand" ""))
5070 (clobber (reg:CC CC_REGNUM))])
5072 [(set (match_operand:BLK 3 "memory_operand" "")
5073 (ior:BLK (match_dup 3)
5074 (match_operand:BLK 4 "memory_operand" "")))
5075 (use (match_operand 5 "const_int_operand" ""))
5076 (clobber (reg:CC CC_REGNUM))])]
5077 "s390_offset_p (operands[0], operands[3], operands[2])
5078 && s390_offset_p (operands[1], operands[4], operands[2])
5079 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5081 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5083 (clobber (reg:CC CC_REGNUM))])]
5084 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5085 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5086 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5090 ;;- Xor instructions.
5093 (define_expand "xor<mode>3"
5094 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5095 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5096 (match_operand:INT 2 "general_operand" "")))
5097 (clobber (reg:CC CC_REGNUM))]
5099 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5102 ; xordi3 instruction pattern(s).
5105 (define_insn "*xordi3_cc"
5106 [(set (reg CC_REGNUM)
5107 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5108 (match_operand:DI 2 "general_operand" "d,m"))
5110 (set (match_operand:DI 0 "register_operand" "=d,d")
5111 (xor:DI (match_dup 1) (match_dup 2)))]
5112 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5116 [(set_attr "op_type" "RRE,RXY")])
5118 (define_insn "*xordi3_cconly"
5119 [(set (reg CC_REGNUM)
5120 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5121 (match_operand:DI 2 "general_operand" "d,m"))
5123 (clobber (match_scratch:DI 0 "=d,d"))]
5124 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5128 [(set_attr "op_type" "RRE,RXY")])
5130 (define_insn "*xordi3"
5131 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5132 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5133 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5134 (clobber (reg:CC CC_REGNUM))]
5135 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5141 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5144 [(set (match_operand:DI 0 "s_operand" "")
5145 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5146 (clobber (reg:CC CC_REGNUM))]
5149 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5150 (clobber (reg:CC CC_REGNUM))])]
5151 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5154 ; xorsi3 instruction pattern(s).
5157 (define_insn "*xorsi3_cc"
5158 [(set (reg CC_REGNUM)
5159 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5160 (match_operand:SI 2 "general_operand" "d,R,T"))
5162 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5163 (xor:SI (match_dup 1) (match_dup 2)))]
5164 "s390_match_ccmode(insn, CCTmode)"
5169 [(set_attr "op_type" "RR,RX,RXY")])
5171 (define_insn "*xorsi3_cconly"
5172 [(set (reg CC_REGNUM)
5173 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5174 (match_operand:SI 2 "general_operand" "d,R,T"))
5176 (clobber (match_scratch:SI 0 "=d,d,d"))]
5177 "s390_match_ccmode(insn, CCTmode)"
5182 [(set_attr "op_type" "RR,RX,RXY")])
5184 (define_insn "*xorsi3"
5185 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5186 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5187 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5188 (clobber (reg:CC CC_REGNUM))]
5189 "s390_logical_operator_ok_p (operands)"
5196 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5199 [(set (match_operand:SI 0 "s_operand" "")
5200 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5201 (clobber (reg:CC CC_REGNUM))]
5204 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5205 (clobber (reg:CC CC_REGNUM))])]
5206 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5209 ; xorhi3 instruction pattern(s).
5212 (define_insn "*xorhi3"
5213 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5214 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5215 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5216 (clobber (reg:CC CC_REGNUM))]
5217 "s390_logical_operator_ok_p (operands)"
5222 [(set_attr "op_type" "RR,SI,SS")])
5225 [(set (match_operand:HI 0 "s_operand" "")
5226 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5227 (clobber (reg:CC CC_REGNUM))]
5230 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5231 (clobber (reg:CC CC_REGNUM))])]
5232 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5235 ; xorqi3 instruction pattern(s).
5238 (define_insn "*xorqi3"
5239 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5240 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5241 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5242 (clobber (reg:CC CC_REGNUM))]
5243 "s390_logical_operator_ok_p (operands)"
5249 [(set_attr "op_type" "RR,SI,SIY,SS")])
5252 ; Block exclusive or (XC) patterns.
5256 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5257 (xor:BLK (match_dup 0)
5258 (match_operand:BLK 1 "memory_operand" "Q")))
5259 (use (match_operand 2 "const_int_operand" "n"))
5260 (clobber (reg:CC CC_REGNUM))]
5261 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5262 "xc\t%O0(%2,%R0),%S1"
5263 [(set_attr "op_type" "SS")])
5266 [(set (match_operand 0 "memory_operand" "")
5268 (match_operand 1 "memory_operand" "")))
5269 (clobber (reg:CC CC_REGNUM))]
5271 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5272 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5274 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5276 (clobber (reg:CC CC_REGNUM))])]
5278 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5279 operands[0] = adjust_address (operands[0], BLKmode, 0);
5280 operands[1] = adjust_address (operands[1], BLKmode, 0);
5285 [(set (match_operand:BLK 0 "memory_operand" "")
5286 (xor:BLK (match_dup 0)
5287 (match_operand:BLK 1 "memory_operand" "")))
5288 (use (match_operand 2 "const_int_operand" ""))
5289 (clobber (reg:CC CC_REGNUM))])
5291 [(set (match_operand:BLK 3 "memory_operand" "")
5292 (xor:BLK (match_dup 3)
5293 (match_operand:BLK 4 "memory_operand" "")))
5294 (use (match_operand 5 "const_int_operand" ""))
5295 (clobber (reg:CC CC_REGNUM))])]
5296 "s390_offset_p (operands[0], operands[3], operands[2])
5297 && s390_offset_p (operands[1], operands[4], operands[2])
5298 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5300 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5302 (clobber (reg:CC CC_REGNUM))])]
5303 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5304 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5305 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5308 ; Block xor (XC) patterns with src == dest.
5311 (define_insn "*xc_zero"
5312 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5314 (use (match_operand 1 "const_int_operand" "n"))
5315 (clobber (reg:CC CC_REGNUM))]
5316 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5317 "xc\t%O0(%1,%R0),%S0"
5318 [(set_attr "op_type" "SS")])
5322 [(set (match_operand:BLK 0 "memory_operand" "")
5324 (use (match_operand 1 "const_int_operand" ""))
5325 (clobber (reg:CC CC_REGNUM))])
5327 [(set (match_operand:BLK 2 "memory_operand" "")
5329 (use (match_operand 3 "const_int_operand" ""))
5330 (clobber (reg:CC CC_REGNUM))])]
5331 "s390_offset_p (operands[0], operands[2], operands[1])
5332 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5334 [(set (match_dup 4) (const_int 0))
5336 (clobber (reg:CC CC_REGNUM))])]
5337 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5338 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5342 ;;- Negate instructions.
5346 ; neg(di|si)2 instruction pattern(s).
5349 (define_expand "neg<mode>2"
5351 [(set (match_operand:DSI 0 "register_operand" "=d")
5352 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5353 (clobber (reg:CC CC_REGNUM))])]
5357 (define_insn "*negdi2_sign_cc"
5358 [(set (reg CC_REGNUM)
5359 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5360 (match_operand:SI 1 "register_operand" "d") 0)
5361 (const_int 32)) (const_int 32)))
5363 (set (match_operand:DI 0 "register_operand" "=d")
5364 (neg:DI (sign_extend:DI (match_dup 1))))]
5365 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5367 [(set_attr "op_type" "RRE")])
5369 (define_insn "*negdi2_sign"
5370 [(set (match_operand:DI 0 "register_operand" "=d")
5371 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5372 (clobber (reg:CC CC_REGNUM))]
5375 [(set_attr "op_type" "RRE")])
5377 (define_insn "*neg<mode>2_cc"
5378 [(set (reg CC_REGNUM)
5379 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5381 (set (match_operand:GPR 0 "register_operand" "=d")
5382 (neg:GPR (match_dup 1)))]
5383 "s390_match_ccmode (insn, CCAmode)"
5385 [(set_attr "op_type" "RR<E>")])
5387 (define_insn "*neg<mode>2_cconly"
5388 [(set (reg CC_REGNUM)
5389 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5391 (clobber (match_scratch:GPR 0 "=d"))]
5392 "s390_match_ccmode (insn, CCAmode)"
5394 [(set_attr "op_type" "RR<E>")])
5396 (define_insn "*neg<mode>2"
5397 [(set (match_operand:GPR 0 "register_operand" "=d")
5398 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5399 (clobber (reg:CC CC_REGNUM))]
5402 [(set_attr "op_type" "RR<E>")])
5404 (define_insn_and_split "*negdi2_31"
5405 [(set (match_operand:DI 0 "register_operand" "=d")
5406 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5407 (clobber (reg:CC CC_REGNUM))]
5410 "&& reload_completed"
5412 [(set (match_dup 2) (neg:SI (match_dup 3)))
5413 (clobber (reg:CC CC_REGNUM))])
5415 [(set (reg:CCAP CC_REGNUM)
5416 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5417 (set (match_dup 4) (neg:SI (match_dup 5)))])
5419 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5421 (label_ref (match_dup 6))))
5423 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5424 (clobber (reg:CC CC_REGNUM))])
5426 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5427 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5428 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5429 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5430 operands[6] = gen_label_rtx ();")
5433 ; neg(df|sf)2 instruction pattern(s).
5436 (define_expand "neg<mode>2"
5438 [(set (match_operand:FPR 0 "register_operand" "=f")
5439 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5440 (clobber (reg:CC CC_REGNUM))])]
5444 (define_insn "*neg<mode>2_cc"
5445 [(set (reg CC_REGNUM)
5446 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5447 (match_operand:FPR 2 "const0_operand" "")))
5448 (set (match_operand:FPR 0 "register_operand" "=f")
5449 (neg:FPR (match_dup 1)))]
5450 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5452 [(set_attr "op_type" "RRE")
5453 (set_attr "type" "fsimp<mode>")])
5455 (define_insn "*neg<mode>2_cconly"
5456 [(set (reg CC_REGNUM)
5457 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5458 (match_operand:FPR 2 "const0_operand" "")))
5459 (clobber (match_scratch:FPR 0 "=f"))]
5460 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5462 [(set_attr "op_type" "RRE")
5463 (set_attr "type" "fsimp<mode>")])
5465 (define_insn "*neg<mode>2"
5466 [(set (match_operand:FPR 0 "register_operand" "=f")
5467 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5468 (clobber (reg:CC CC_REGNUM))]
5469 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5471 [(set_attr "op_type" "RRE")
5472 (set_attr "type" "fsimp<mode>")])
5474 (define_insn "*neg<mode>2_ibm"
5475 [(set (match_operand:FPR 0 "register_operand" "=f")
5476 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5477 (clobber (reg:CC CC_REGNUM))]
5478 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5480 [(set_attr "op_type" "RR")
5481 (set_attr "type" "fsimp<mode>")])
5485 ;;- Absolute value instructions.
5489 ; abs(di|si)2 instruction pattern(s).
5492 (define_insn "*absdi2_sign_cc"
5493 [(set (reg CC_REGNUM)
5494 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5495 (match_operand:SI 1 "register_operand" "d") 0)
5496 (const_int 32)) (const_int 32)))
5498 (set (match_operand:DI 0 "register_operand" "=d")
5499 (abs:DI (sign_extend:DI (match_dup 1))))]
5500 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5502 [(set_attr "op_type" "RRE")])
5504 (define_insn "*absdi2_sign"
5505 [(set (match_operand:DI 0 "register_operand" "=d")
5506 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5507 (clobber (reg:CC CC_REGNUM))]
5510 [(set_attr "op_type" "RRE")])
5512 (define_insn "*abs<mode>2_cc"
5513 [(set (reg CC_REGNUM)
5514 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5516 (set (match_operand:GPR 0 "register_operand" "=d")
5517 (abs:GPR (match_dup 1)))]
5518 "s390_match_ccmode (insn, CCAmode)"
5520 [(set_attr "op_type" "RR<E>")])
5522 (define_insn "*abs<mode>2_cconly"
5523 [(set (reg CC_REGNUM)
5524 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5526 (clobber (match_scratch:GPR 0 "=d"))]
5527 "s390_match_ccmode (insn, CCAmode)"
5529 [(set_attr "op_type" "RR<E>")])
5531 (define_insn "abs<mode>2"
5532 [(set (match_operand:GPR 0 "register_operand" "=d")
5533 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5534 (clobber (reg:CC CC_REGNUM))]
5537 [(set_attr "op_type" "RR<E>")])
5540 ; abs(df|sf)2 instruction pattern(s).
5543 (define_expand "abs<mode>2"
5545 [(set (match_operand:FPR 0 "register_operand" "=f")
5546 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5547 (clobber (reg:CC CC_REGNUM))])]
5551 (define_insn "*abs<mode>2_cc"
5552 [(set (reg CC_REGNUM)
5553 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5554 (match_operand:FPR 2 "const0_operand" "")))
5555 (set (match_operand:FPR 0 "register_operand" "=f")
5556 (abs:FPR (match_dup 1)))]
5557 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5559 [(set_attr "op_type" "RRE")
5560 (set_attr "type" "fsimp<mode>")])
5562 (define_insn "*abs<mode>2_cconly"
5563 [(set (reg CC_REGNUM)
5564 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5565 (match_operand:FPR 2 "const0_operand" "")))
5566 (clobber (match_scratch:FPR 0 "=f"))]
5567 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5569 [(set_attr "op_type" "RRE")
5570 (set_attr "type" "fsimp<mode>")])
5572 (define_insn "*abs<mode>2"
5573 [(set (match_operand:FPR 0 "register_operand" "=f")
5574 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5575 (clobber (reg:CC CC_REGNUM))]
5576 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5578 [(set_attr "op_type" "RRE")
5579 (set_attr "type" "fsimp<mode>")])
5581 (define_insn "*abs<mode>2_ibm"
5582 [(set (match_operand:FPR 0 "register_operand" "=f")
5583 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5584 (clobber (reg:CC CC_REGNUM))]
5585 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5587 [(set_attr "op_type" "RR")
5588 (set_attr "type" "fsimp<mode>")])
5591 ;;- Negated absolute value instructions
5598 (define_insn "*negabsdi2_sign_cc"
5599 [(set (reg CC_REGNUM)
5600 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5601 (match_operand:SI 1 "register_operand" "d") 0)
5602 (const_int 32)) (const_int 32))))
5604 (set (match_operand:DI 0 "register_operand" "=d")
5605 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5606 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5608 [(set_attr "op_type" "RRE")])
5610 (define_insn "*negabsdi2_sign"
5611 [(set (match_operand:DI 0 "register_operand" "=d")
5612 (neg:DI (abs:DI (sign_extend:DI
5613 (match_operand:SI 1 "register_operand" "d")))))
5614 (clobber (reg:CC CC_REGNUM))]
5617 [(set_attr "op_type" "RRE")])
5619 (define_insn "*negabs<mode>2_cc"
5620 [(set (reg CC_REGNUM)
5621 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5623 (set (match_operand:GPR 0 "register_operand" "=d")
5624 (neg:GPR (abs:GPR (match_dup 1))))]
5625 "s390_match_ccmode (insn, CCAmode)"
5627 [(set_attr "op_type" "RR<E>")])
5629 (define_insn "*negabs<mode>2_cconly"
5630 [(set (reg CC_REGNUM)
5631 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5633 (clobber (match_scratch:GPR 0 "=d"))]
5634 "s390_match_ccmode (insn, CCAmode)"
5636 [(set_attr "op_type" "RR<E>")])
5638 (define_insn "*negabs<mode>2"
5639 [(set (match_operand:GPR 0 "register_operand" "=d")
5640 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5641 (clobber (reg:CC CC_REGNUM))]
5644 [(set_attr "op_type" "RR<E>")])
5650 (define_insn "*negabs<mode>2_cc"
5651 [(set (reg CC_REGNUM)
5652 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5653 (match_operand:FPR 2 "const0_operand" "")))
5654 (set (match_operand:FPR 0 "register_operand" "=f")
5655 (neg:FPR (abs:FPR (match_dup 1))))]
5656 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5658 [(set_attr "op_type" "RRE")
5659 (set_attr "type" "fsimp<mode>")])
5661 (define_insn "*negabs<mode>2_cconly"
5662 [(set (reg CC_REGNUM)
5663 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5664 (match_operand:FPR 2 "const0_operand" "")))
5665 (clobber (match_scratch:FPR 0 "=f"))]
5666 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5668 [(set_attr "op_type" "RRE")
5669 (set_attr "type" "fsimp<mode>")])
5671 (define_insn "*negabs<mode>2"
5672 [(set (match_operand:FPR 0 "register_operand" "=f")
5673 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5674 (clobber (reg:CC CC_REGNUM))]
5675 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5677 [(set_attr "op_type" "RRE")
5678 (set_attr "type" "fsimp<mode>")])
5681 ;;- Square root instructions.
5685 ; sqrt(df|sf)2 instruction pattern(s).
5688 (define_insn "sqrt<mode>2"
5689 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5690 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5691 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5695 [(set_attr "op_type" "RRE,RXE")
5696 (set_attr "type" "fsqrt<mode>")])
5700 ;;- One complement instructions.
5704 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5707 (define_expand "one_cmpl<mode>2"
5709 [(set (match_operand:INT 0 "register_operand" "")
5710 (xor:INT (match_operand:INT 1 "register_operand" "")
5712 (clobber (reg:CC CC_REGNUM))])]
5718 ;;- Rotate instructions.
5722 ; rotl(di|si)3 instruction pattern(s).
5725 (define_insn "rotl<mode>3"
5726 [(set (match_operand:GPR 0 "register_operand" "=d")
5727 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5728 (match_operand:SI 2 "shift_count_operand" "Y")))]
5731 [(set_attr "op_type" "RSE")
5732 (set_attr "atype" "reg")])
5736 ;;- Shift instructions.
5740 ; (ashl|lshr)di3 instruction pattern(s).
5743 (define_expand "<shift>di3"
5744 [(set (match_operand:DI 0 "register_operand" "")
5745 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5746 (match_operand:SI 2 "shift_count_operand" "")))]
5750 (define_insn "*<shift>di3_31"
5751 [(set (match_operand:DI 0 "register_operand" "=d")
5752 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5753 (match_operand:SI 2 "shift_count_operand" "Y")))]
5756 [(set_attr "op_type" "RS")
5757 (set_attr "atype" "reg")])
5759 (define_insn "*<shift>di3_64"
5760 [(set (match_operand:DI 0 "register_operand" "=d")
5761 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5762 (match_operand:SI 2 "shift_count_operand" "Y")))]
5764 "s<lr>lg\t%0,%1,%Y2"
5765 [(set_attr "op_type" "RSE")
5766 (set_attr "atype" "reg")])
5769 ; ashrdi3 instruction pattern(s).
5772 (define_expand "ashrdi3"
5774 [(set (match_operand:DI 0 "register_operand" "")
5775 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5776 (match_operand:SI 2 "shift_count_operand" "")))
5777 (clobber (reg:CC CC_REGNUM))])]
5781 (define_insn "*ashrdi3_cc_31"
5782 [(set (reg CC_REGNUM)
5783 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5784 (match_operand:SI 2 "shift_count_operand" "Y"))
5786 (set (match_operand:DI 0 "register_operand" "=d")
5787 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5788 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5790 [(set_attr "op_type" "RS")
5791 (set_attr "atype" "reg")])
5793 (define_insn "*ashrdi3_cconly_31"
5794 [(set (reg CC_REGNUM)
5795 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5796 (match_operand:SI 2 "shift_count_operand" "Y"))
5798 (clobber (match_scratch:DI 0 "=d"))]
5799 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5801 [(set_attr "op_type" "RS")
5802 (set_attr "atype" "reg")])
5804 (define_insn "*ashrdi3_31"
5805 [(set (match_operand:DI 0 "register_operand" "=d")
5806 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5807 (match_operand:SI 2 "shift_count_operand" "Y")))
5808 (clobber (reg:CC CC_REGNUM))]
5811 [(set_attr "op_type" "RS")
5812 (set_attr "atype" "reg")])
5814 (define_insn "*ashrdi3_cc_64"
5815 [(set (reg CC_REGNUM)
5816 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5817 (match_operand:SI 2 "shift_count_operand" "Y"))
5819 (set (match_operand:DI 0 "register_operand" "=d")
5820 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5821 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5823 [(set_attr "op_type" "RSE")
5824 (set_attr "atype" "reg")])
5826 (define_insn "*ashrdi3_cconly_64"
5827 [(set (reg CC_REGNUM)
5828 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5829 (match_operand:SI 2 "shift_count_operand" "Y"))
5831 (clobber (match_scratch:DI 0 "=d"))]
5832 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5834 [(set_attr "op_type" "RSE")
5835 (set_attr "atype" "reg")])
5837 (define_insn "*ashrdi3_64"
5838 [(set (match_operand:DI 0 "register_operand" "=d")
5839 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5840 (match_operand:SI 2 "shift_count_operand" "Y")))
5841 (clobber (reg:CC CC_REGNUM))]
5844 [(set_attr "op_type" "RSE")
5845 (set_attr "atype" "reg")])
5849 ; (ashl|lshr)si3 instruction pattern(s).
5852 (define_insn "<shift>si3"
5853 [(set (match_operand:SI 0 "register_operand" "=d")
5854 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5855 (match_operand:SI 2 "shift_count_operand" "Y")))]
5858 [(set_attr "op_type" "RS")
5859 (set_attr "atype" "reg")])
5862 ; ashrsi3 instruction pattern(s).
5865 (define_insn "*ashrsi3_cc"
5866 [(set (reg CC_REGNUM)
5867 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5868 (match_operand:SI 2 "shift_count_operand" "Y"))
5870 (set (match_operand:SI 0 "register_operand" "=d")
5871 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5872 "s390_match_ccmode(insn, CCSmode)"
5874 [(set_attr "op_type" "RS")
5875 (set_attr "atype" "reg")])
5878 (define_insn "*ashrsi3_cconly"
5879 [(set (reg CC_REGNUM)
5880 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5881 (match_operand:SI 2 "shift_count_operand" "Y"))
5883 (clobber (match_scratch:SI 0 "=d"))]
5884 "s390_match_ccmode(insn, CCSmode)"
5886 [(set_attr "op_type" "RS")
5887 (set_attr "atype" "reg")])
5889 (define_insn "ashrsi3"
5890 [(set (match_operand:SI 0 "register_operand" "=d")
5891 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5892 (match_operand:SI 2 "shift_count_operand" "Y")))
5893 (clobber (reg:CC CC_REGNUM))]
5896 [(set_attr "op_type" "RS")
5897 (set_attr "atype" "reg")])
5901 ;; Branch instruction patterns.
5904 (define_expand "b<code>"
5906 (if_then_else (COMPARE (match_operand 0 "" "")
5911 "s390_emit_jump (operands[0],
5912 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
5916 ;;- Conditional jump instructions.
5919 (define_insn "*cjump_64"
5922 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5923 (label_ref (match_operand 0 "" ""))
5927 if (get_attr_length (insn) == 4)
5930 return "jg%C1\t%l0";
5932 [(set_attr "op_type" "RI")
5933 (set_attr "type" "branch")
5934 (set (attr "length")
5935 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5936 (const_int 4) (const_int 6)))])
5938 (define_insn "*cjump_31"
5941 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5942 (label_ref (match_operand 0 "" ""))
5946 gcc_assert (get_attr_length (insn) == 4);
5949 [(set_attr "op_type" "RI")
5950 (set_attr "type" "branch")
5951 (set (attr "length")
5952 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5953 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5954 (const_int 4) (const_int 6))
5955 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5956 (const_int 4) (const_int 8))))])
5958 (define_insn "*cjump_long"
5961 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5962 (match_operand 0 "address_operand" "U")
5966 if (get_attr_op_type (insn) == OP_TYPE_RR)
5971 [(set (attr "op_type")
5972 (if_then_else (match_operand 0 "register_operand" "")
5973 (const_string "RR") (const_string "RX")))
5974 (set_attr "type" "branch")
5975 (set_attr "atype" "agen")])
5979 ;;- Negated conditional jump instructions.
5982 (define_insn "*icjump_64"
5985 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5987 (label_ref (match_operand 0 "" ""))))]
5990 if (get_attr_length (insn) == 4)
5993 return "jg%D1\t%l0";
5995 [(set_attr "op_type" "RI")
5996 (set_attr "type" "branch")
5997 (set (attr "length")
5998 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5999 (const_int 4) (const_int 6)))])
6001 (define_insn "*icjump_31"
6004 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6006 (label_ref (match_operand 0 "" ""))))]
6009 gcc_assert (get_attr_length (insn) == 4);
6012 [(set_attr "op_type" "RI")
6013 (set_attr "type" "branch")
6014 (set (attr "length")
6015 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6016 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6017 (const_int 4) (const_int 6))
6018 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6019 (const_int 4) (const_int 8))))])
6021 (define_insn "*icjump_long"
6024 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6026 (match_operand 0 "address_operand" "U")))]
6029 if (get_attr_op_type (insn) == OP_TYPE_RR)
6034 [(set (attr "op_type")
6035 (if_then_else (match_operand 0 "register_operand" "")
6036 (const_string "RR") (const_string "RX")))
6037 (set_attr "type" "branch")
6038 (set_attr "atype" "agen")])
6041 ;;- Trap instructions.
6045 [(trap_if (const_int 1) (const_int 0))]
6048 [(set_attr "op_type" "RI")
6049 (set_attr "type" "branch")])
6051 (define_expand "conditional_trap"
6052 [(trap_if (match_operand 0 "comparison_operator" "")
6053 (match_operand 1 "general_operand" ""))]
6056 if (operands[1] != const0_rtx) FAIL;
6057 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6058 s390_compare_op0, s390_compare_op1);
6061 (define_insn "*trap"
6062 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6066 [(set_attr "op_type" "RI")
6067 (set_attr "type" "branch")])
6070 ;;- Loop instructions.
6072 ;; This is all complicated by the fact that since this is a jump insn
6073 ;; we must handle our own output reloads.
6075 (define_expand "doloop_end"
6076 [(use (match_operand 0 "" "")) ; loop pseudo
6077 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6078 (use (match_operand 2 "" "")) ; max iterations
6079 (use (match_operand 3 "" "")) ; loop level
6080 (use (match_operand 4 "" ""))] ; label
6083 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6084 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6085 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6086 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6087 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6088 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6095 (define_insn_and_split "doloop_si64"
6098 (ne (match_operand:SI 1 "register_operand" "d,d")
6100 (label_ref (match_operand 0 "" ""))
6102 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6103 (plus:SI (match_dup 1) (const_int -1)))
6104 (clobber (match_scratch:SI 3 "=X,&1"))
6105 (clobber (reg:CC CC_REGNUM))]
6108 if (which_alternative != 0)
6110 else if (get_attr_length (insn) == 4)
6111 return "brct\t%1,%l0";
6113 return "ahi\t%1,-1\;jgne\t%l0";
6115 "&& reload_completed
6116 && (! REG_P (operands[2])
6117 || ! rtx_equal_p (operands[1], operands[2]))"
6118 [(parallel [(set (reg:CCAN CC_REGNUM)
6119 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6121 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6122 (set (match_dup 2) (match_dup 3))
6123 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6124 (label_ref (match_dup 0))
6127 [(set_attr "op_type" "RI")
6128 (set_attr "type" "branch")
6129 (set (attr "length")
6130 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6131 (const_int 4) (const_int 10)))])
6133 (define_insn_and_split "doloop_si31"
6136 (ne (match_operand:SI 1 "register_operand" "d,d")
6138 (label_ref (match_operand 0 "" ""))
6140 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6141 (plus:SI (match_dup 1) (const_int -1)))
6142 (clobber (match_scratch:SI 3 "=X,&1"))
6143 (clobber (reg:CC CC_REGNUM))]
6146 if (which_alternative != 0)
6148 else if (get_attr_length (insn) == 4)
6149 return "brct\t%1,%l0";
6153 "&& reload_completed
6154 && (! REG_P (operands[2])
6155 || ! rtx_equal_p (operands[1], operands[2]))"
6156 [(parallel [(set (reg:CCAN CC_REGNUM)
6157 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6159 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6160 (set (match_dup 2) (match_dup 3))
6161 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6162 (label_ref (match_dup 0))
6165 [(set_attr "op_type" "RI")
6166 (set_attr "type" "branch")
6167 (set (attr "length")
6168 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6169 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6170 (const_int 4) (const_int 6))
6171 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6172 (const_int 4) (const_int 8))))])
6174 (define_insn "*doloop_si_long"
6177 (ne (match_operand:SI 1 "register_operand" "d,d")
6179 (match_operand 0 "address_operand" "U,U")
6181 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6182 (plus:SI (match_dup 1) (const_int -1)))
6183 (clobber (match_scratch:SI 3 "=X,&1"))
6184 (clobber (reg:CC CC_REGNUM))]
6187 if (get_attr_op_type (insn) == OP_TYPE_RR)
6188 return "bctr\t%1,%0";
6190 return "bct\t%1,%a0";
6192 [(set (attr "op_type")
6193 (if_then_else (match_operand 0 "register_operand" "")
6194 (const_string "RR") (const_string "RX")))
6195 (set_attr "type" "branch")
6196 (set_attr "atype" "agen")])
6198 (define_insn_and_split "doloop_di"
6201 (ne (match_operand:DI 1 "register_operand" "d,d")
6203 (label_ref (match_operand 0 "" ""))
6205 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6206 (plus:DI (match_dup 1) (const_int -1)))
6207 (clobber (match_scratch:DI 3 "=X,&1"))
6208 (clobber (reg:CC CC_REGNUM))]
6211 if (which_alternative != 0)
6213 else if (get_attr_length (insn) == 4)
6214 return "brctg\t%1,%l0";
6216 return "aghi\t%1,-1\;jgne\t%l0";
6218 "&& reload_completed
6219 && (! REG_P (operands[2])
6220 || ! rtx_equal_p (operands[1], operands[2]))"
6221 [(parallel [(set (reg:CCAN CC_REGNUM)
6222 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6224 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6225 (set (match_dup 2) (match_dup 3))
6226 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6227 (label_ref (match_dup 0))
6230 [(set_attr "op_type" "RI")
6231 (set_attr "type" "branch")
6232 (set (attr "length")
6233 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6234 (const_int 4) (const_int 10)))])
6237 ;;- Unconditional jump instructions.
6241 ; jump instruction pattern(s).
6244 (define_expand "jump"
6245 [(match_operand 0 "" "")]
6247 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6249 (define_insn "*jump64"
6250 [(set (pc) (label_ref (match_operand 0 "" "")))]
6253 if (get_attr_length (insn) == 4)
6258 [(set_attr "op_type" "RI")
6259 (set_attr "type" "branch")
6260 (set (attr "length")
6261 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6262 (const_int 4) (const_int 6)))])
6264 (define_insn "*jump31"
6265 [(set (pc) (label_ref (match_operand 0 "" "")))]
6268 gcc_assert (get_attr_length (insn) == 4);
6271 [(set_attr "op_type" "RI")
6272 (set_attr "type" "branch")
6273 (set (attr "length")
6274 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6275 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6276 (const_int 4) (const_int 6))
6277 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6278 (const_int 4) (const_int 8))))])
6281 ; indirect-jump instruction pattern(s).
6284 (define_insn "indirect_jump"
6285 [(set (pc) (match_operand 0 "address_operand" "U"))]
6288 if (get_attr_op_type (insn) == OP_TYPE_RR)
6293 [(set (attr "op_type")
6294 (if_then_else (match_operand 0 "register_operand" "")
6295 (const_string "RR") (const_string "RX")))
6296 (set_attr "type" "branch")
6297 (set_attr "atype" "agen")])
6300 ; casesi instruction pattern(s).
6303 (define_insn "casesi_jump"
6304 [(set (pc) (match_operand 0 "address_operand" "U"))
6305 (use (label_ref (match_operand 1 "" "")))]
6308 if (get_attr_op_type (insn) == OP_TYPE_RR)
6313 [(set (attr "op_type")
6314 (if_then_else (match_operand 0 "register_operand" "")
6315 (const_string "RR") (const_string "RX")))
6316 (set_attr "type" "branch")
6317 (set_attr "atype" "agen")])
6319 (define_expand "casesi"
6320 [(match_operand:SI 0 "general_operand" "")
6321 (match_operand:SI 1 "general_operand" "")
6322 (match_operand:SI 2 "general_operand" "")
6323 (label_ref (match_operand 3 "" ""))
6324 (label_ref (match_operand 4 "" ""))]
6327 rtx index = gen_reg_rtx (SImode);
6328 rtx base = gen_reg_rtx (Pmode);
6329 rtx target = gen_reg_rtx (Pmode);
6331 emit_move_insn (index, operands[0]);
6332 emit_insn (gen_subsi3 (index, index, operands[1]));
6333 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6336 if (Pmode != SImode)
6337 index = convert_to_mode (Pmode, index, 1);
6338 if (GET_CODE (index) != REG)
6339 index = copy_to_mode_reg (Pmode, index);
6342 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6344 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6346 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6348 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6349 emit_move_insn (target, index);
6352 target = gen_rtx_PLUS (Pmode, base, target);
6353 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6360 ;;- Jump to subroutine.
6365 ; untyped call instruction pattern(s).
6368 ;; Call subroutine returning any type.
6369 (define_expand "untyped_call"
6370 [(parallel [(call (match_operand 0 "" "")
6372 (match_operand 1 "" "")
6373 (match_operand 2 "" "")])]
6378 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6380 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6382 rtx set = XVECEXP (operands[2], 0, i);
6383 emit_move_insn (SET_DEST (set), SET_SRC (set));
6386 /* The optimizer does not know that the call sets the function value
6387 registers we stored in the result block. We avoid problems by
6388 claiming that all hard registers are used and clobbered at this
6390 emit_insn (gen_blockage ());
6395 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6396 ;; all of memory. This blocks insns from being moved across this point.
6398 (define_insn "blockage"
6399 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6402 [(set_attr "type" "none")
6403 (set_attr "length" "0")])
6409 (define_expand "sibcall"
6410 [(call (match_operand 0 "" "")
6411 (match_operand 1 "" ""))]
6414 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6418 (define_insn "*sibcall_br"
6419 [(call (mem:QI (reg SIBCALL_REGNUM))
6420 (match_operand 0 "const_int_operand" "n"))]
6421 "SIBLING_CALL_P (insn)
6422 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6424 [(set_attr "op_type" "RR")
6425 (set_attr "type" "branch")
6426 (set_attr "atype" "agen")])
6428 (define_insn "*sibcall_brc"
6429 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6430 (match_operand 1 "const_int_operand" "n"))]
6431 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6433 [(set_attr "op_type" "RI")
6434 (set_attr "type" "branch")])
6436 (define_insn "*sibcall_brcl"
6437 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6438 (match_operand 1 "const_int_operand" "n"))]
6439 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6441 [(set_attr "op_type" "RIL")
6442 (set_attr "type" "branch")])
6445 ; sibcall_value patterns
6448 (define_expand "sibcall_value"
6449 [(set (match_operand 0 "" "")
6450 (call (match_operand 1 "" "")
6451 (match_operand 2 "" "")))]
6454 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6458 (define_insn "*sibcall_value_br"
6459 [(set (match_operand 0 "" "")
6460 (call (mem:QI (reg SIBCALL_REGNUM))
6461 (match_operand 1 "const_int_operand" "n")))]
6462 "SIBLING_CALL_P (insn)
6463 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6465 [(set_attr "op_type" "RR")
6466 (set_attr "type" "branch")
6467 (set_attr "atype" "agen")])
6469 (define_insn "*sibcall_value_brc"
6470 [(set (match_operand 0 "" "")
6471 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6472 (match_operand 2 "const_int_operand" "n")))]
6473 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6475 [(set_attr "op_type" "RI")
6476 (set_attr "type" "branch")])
6478 (define_insn "*sibcall_value_brcl"
6479 [(set (match_operand 0 "" "")
6480 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6481 (match_operand 2 "const_int_operand" "n")))]
6482 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6484 [(set_attr "op_type" "RIL")
6485 (set_attr "type" "branch")])
6489 ; call instruction pattern(s).
6492 (define_expand "call"
6493 [(call (match_operand 0 "" "")
6494 (match_operand 1 "" ""))
6495 (use (match_operand 2 "" ""))]
6498 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6499 gen_rtx_REG (Pmode, RETURN_REGNUM));
6503 (define_insn "*bras"
6504 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6505 (match_operand 1 "const_int_operand" "n"))
6506 (clobber (match_operand 2 "register_operand" "=r"))]
6507 "!SIBLING_CALL_P (insn)
6508 && TARGET_SMALL_EXEC
6509 && GET_MODE (operands[2]) == Pmode"
6511 [(set_attr "op_type" "RI")
6512 (set_attr "type" "jsr")])
6514 (define_insn "*brasl"
6515 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6516 (match_operand 1 "const_int_operand" "n"))
6517 (clobber (match_operand 2 "register_operand" "=r"))]
6518 "!SIBLING_CALL_P (insn)
6520 && GET_MODE (operands[2]) == Pmode"
6522 [(set_attr "op_type" "RIL")
6523 (set_attr "type" "jsr")])
6525 (define_insn "*basr"
6526 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6527 (match_operand 1 "const_int_operand" "n"))
6528 (clobber (match_operand 2 "register_operand" "=r"))]
6529 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6531 if (get_attr_op_type (insn) == OP_TYPE_RR)
6532 return "basr\t%2,%0";
6534 return "bas\t%2,%a0";
6536 [(set (attr "op_type")
6537 (if_then_else (match_operand 0 "register_operand" "")
6538 (const_string "RR") (const_string "RX")))
6539 (set_attr "type" "jsr")
6540 (set_attr "atype" "agen")])
6543 ; call_value instruction pattern(s).
6546 (define_expand "call_value"
6547 [(set (match_operand 0 "" "")
6548 (call (match_operand 1 "" "")
6549 (match_operand 2 "" "")))
6550 (use (match_operand 3 "" ""))]
6553 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6554 gen_rtx_REG (Pmode, RETURN_REGNUM));
6558 (define_insn "*bras_r"
6559 [(set (match_operand 0 "" "")
6560 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6561 (match_operand:SI 2 "const_int_operand" "n")))
6562 (clobber (match_operand 3 "register_operand" "=r"))]
6563 "!SIBLING_CALL_P (insn)
6564 && TARGET_SMALL_EXEC
6565 && GET_MODE (operands[3]) == Pmode"
6567 [(set_attr "op_type" "RI")
6568 (set_attr "type" "jsr")])
6570 (define_insn "*brasl_r"
6571 [(set (match_operand 0 "" "")
6572 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6573 (match_operand 2 "const_int_operand" "n")))
6574 (clobber (match_operand 3 "register_operand" "=r"))]
6575 "!SIBLING_CALL_P (insn)
6577 && GET_MODE (operands[3]) == Pmode"
6579 [(set_attr "op_type" "RIL")
6580 (set_attr "type" "jsr")])
6582 (define_insn "*basr_r"
6583 [(set (match_operand 0 "" "")
6584 (call (mem:QI (match_operand 1 "address_operand" "U"))
6585 (match_operand 2 "const_int_operand" "n")))
6586 (clobber (match_operand 3 "register_operand" "=r"))]
6587 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6589 if (get_attr_op_type (insn) == OP_TYPE_RR)
6590 return "basr\t%3,%1";
6592 return "bas\t%3,%a1";
6594 [(set (attr "op_type")
6595 (if_then_else (match_operand 1 "register_operand" "")
6596 (const_string "RR") (const_string "RX")))
6597 (set_attr "type" "jsr")
6598 (set_attr "atype" "agen")])
6601 ;;- Thread-local storage support.
6604 (define_expand "get_tp_64"
6605 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6609 (define_expand "get_tp_31"
6610 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6614 (define_expand "set_tp_64"
6615 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6616 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6620 (define_expand "set_tp_31"
6621 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6622 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6626 (define_insn "*set_tp"
6627 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6630 [(set_attr "type" "none")
6631 (set_attr "length" "0")])
6633 (define_insn "*tls_load_64"
6634 [(set (match_operand:DI 0 "register_operand" "=d")
6635 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6636 (match_operand:DI 2 "" "")]
6640 [(set_attr "op_type" "RXE")])
6642 (define_insn "*tls_load_31"
6643 [(set (match_operand:SI 0 "register_operand" "=d,d")
6644 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6645 (match_operand:SI 2 "" "")]
6651 [(set_attr "op_type" "RX,RXY")])
6653 (define_insn "*bras_tls"
6654 [(set (match_operand 0 "" "")
6655 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6656 (match_operand 2 "const_int_operand" "n")))
6657 (clobber (match_operand 3 "register_operand" "=r"))
6658 (use (match_operand 4 "" ""))]
6659 "!SIBLING_CALL_P (insn)
6660 && TARGET_SMALL_EXEC
6661 && GET_MODE (operands[3]) == Pmode"
6663 [(set_attr "op_type" "RI")
6664 (set_attr "type" "jsr")])
6666 (define_insn "*brasl_tls"
6667 [(set (match_operand 0 "" "")
6668 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6669 (match_operand 2 "const_int_operand" "n")))
6670 (clobber (match_operand 3 "register_operand" "=r"))
6671 (use (match_operand 4 "" ""))]
6672 "!SIBLING_CALL_P (insn)
6674 && GET_MODE (operands[3]) == Pmode"
6676 [(set_attr "op_type" "RIL")
6677 (set_attr "type" "jsr")])
6679 (define_insn "*basr_tls"
6680 [(set (match_operand 0 "" "")
6681 (call (mem:QI (match_operand 1 "address_operand" "U"))
6682 (match_operand 2 "const_int_operand" "n")))
6683 (clobber (match_operand 3 "register_operand" "=r"))
6684 (use (match_operand 4 "" ""))]
6685 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6687 if (get_attr_op_type (insn) == OP_TYPE_RR)
6688 return "basr\t%3,%1%J4";
6690 return "bas\t%3,%a1%J4";
6692 [(set (attr "op_type")
6693 (if_then_else (match_operand 1 "register_operand" "")
6694 (const_string "RR") (const_string "RX")))
6695 (set_attr "type" "jsr")
6696 (set_attr "atype" "agen")])
6699 ;;- Atomic operations
6703 ; memory barrier pattern.
6706 (define_expand "memory_barrier"
6707 [(set (mem:BLK (match_dup 0))
6708 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
6711 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
6712 MEM_VOLATILE_P (operands[0]) = 1;
6715 (define_insn "*memory_barrier"
6716 [(set (match_operand:BLK 0 "" "")
6717 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
6720 [(set_attr "op_type" "RR")])
6723 ; compare and swap patterns.
6726 (define_insn "sync_compare_and_swap<mode>"
6727 [(set (match_operand:GPR 0 "register_operand" "=r")
6728 (match_operand:GPR 1 "memory_operand" "+Q"))
6730 (unspec_volatile:GPR
6732 (match_operand:GPR 2 "register_operand" "0")
6733 (match_operand:GPR 3 "register_operand" "r")]
6735 (clobber (reg:CC CC_REGNUM))]
6738 [(set_attr "op_type" "RS<E>")
6739 (set_attr "type" "sem")])
6741 (define_expand "sync_compare_and_swap_cc<mode>"
6743 [(set (match_operand:GPR 0 "register_operand" "")
6744 (match_operand:GPR 1 "memory_operand" ""))
6746 (unspec_volatile:GPR
6748 (match_operand:GPR 2 "register_operand" "")
6749 (match_operand:GPR 3 "register_operand" "")]
6752 (compare:CCZ (match_dup 1) (match_dup 2)))])]
6755 operands[4] = gen_rtx_REG (CCZmode, CC_REGNUM);
6756 s390_compare_op0 = operands[1];
6757 s390_compare_op1 = operands[2];
6758 s390_compare_emitted = operands[4];
6761 (define_insn "*sync_compare_and_swap_cc<mode>"
6762 [(set (match_operand:GPR 0 "register_operand" "=r")
6763 (match_operand:GPR 1 "memory_operand" "+Q"))
6765 (unspec_volatile:GPR
6767 (match_operand:GPR 2 "register_operand" "0")
6768 (match_operand:GPR 3 "register_operand" "r")]
6770 (set (reg:CCZ CC_REGNUM)
6771 (compare:CCZ (match_dup 1) (match_dup 2)))]
6774 [(set_attr "op_type" "RS<E>")
6775 (set_attr "type" "sem")])
6779 ;;- Miscellaneous instructions.
6783 ; allocate stack instruction pattern(s).
6786 (define_expand "allocate_stack"
6787 [(match_operand 0 "general_operand" "")
6788 (match_operand 1 "general_operand" "")]
6791 rtx temp = gen_reg_rtx (Pmode);
6793 emit_move_insn (temp, s390_back_chain_rtx ());
6794 anti_adjust_stack (operands[1]);
6795 emit_move_insn (s390_back_chain_rtx (), temp);
6797 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6803 ; setjmp instruction pattern.
6806 (define_expand "builtin_setjmp_receiver"
6807 [(match_operand 0 "" "")]
6810 emit_insn (s390_load_got ());
6811 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6815 ;; These patterns say how to save and restore the stack pointer. We need not
6816 ;; save the stack pointer at function level since we are careful to
6817 ;; preserve the backchain. At block level, we have to restore the backchain
6818 ;; when we restore the stack pointer.
6820 ;; For nonlocal gotos, we must save both the stack pointer and its
6821 ;; backchain and restore both. Note that in the nonlocal case, the
6822 ;; save area is a memory location.
6824 (define_expand "save_stack_function"
6825 [(match_operand 0 "general_operand" "")
6826 (match_operand 1 "general_operand" "")]
6830 (define_expand "restore_stack_function"
6831 [(match_operand 0 "general_operand" "")
6832 (match_operand 1 "general_operand" "")]
6836 (define_expand "restore_stack_block"
6837 [(match_operand 0 "register_operand" "")
6838 (match_operand 1 "register_operand" "")]
6841 rtx temp = gen_reg_rtx (Pmode);
6843 emit_move_insn (temp, s390_back_chain_rtx ());
6844 emit_move_insn (operands[0], operands[1]);
6845 emit_move_insn (s390_back_chain_rtx (), temp);
6850 (define_expand "save_stack_nonlocal"
6851 [(match_operand 0 "memory_operand" "")
6852 (match_operand 1 "register_operand" "")]
6855 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6856 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6858 /* Copy the backchain to the first word, sp to the second and the
6859 literal pool base to the third. */
6861 if (TARGET_BACKCHAIN)
6863 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6864 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6867 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6868 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6873 (define_expand "restore_stack_nonlocal"
6874 [(match_operand 0 "register_operand" "")
6875 (match_operand 1 "memory_operand" "")]
6878 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6879 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6880 rtx temp = NULL_RTX;
6882 /* Restore the backchain from the first word, sp from the second and the
6883 literal pool base from the third. */
6885 if (TARGET_BACKCHAIN)
6886 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6888 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6889 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6892 emit_move_insn (s390_back_chain_rtx (), temp);
6894 emit_insn (gen_rtx_USE (VOIDmode, base));
6900 ; nop instruction pattern(s).
6907 [(set_attr "op_type" "RR")])
6911 ; Special literal pool access instruction pattern(s).
6914 (define_insn "*pool_entry"
6915 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
6916 UNSPECV_POOL_ENTRY)]
6919 enum machine_mode mode = GET_MODE (PATTERN (insn));
6920 unsigned int align = GET_MODE_BITSIZE (mode);
6921 s390_output_pool_entry (operands[0], mode, align);
6924 [(set (attr "length")
6925 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
6927 (define_insn "pool_align"
6928 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
6929 UNSPECV_POOL_ALIGN)]
6932 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6934 (define_insn "pool_section_start"
6935 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
6938 [(set_attr "length" "0")])
6940 (define_insn "pool_section_end"
6941 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
6944 [(set_attr "length" "0")])
6946 (define_insn "main_base_31_small"
6947 [(set (match_operand 0 "register_operand" "=a")
6948 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6949 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6951 [(set_attr "op_type" "RR")
6952 (set_attr "type" "la")])
6954 (define_insn "main_base_31_large"
6955 [(set (match_operand 0 "register_operand" "=a")
6956 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
6957 (set (pc) (label_ref (match_operand 2 "" "")))]
6958 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6960 [(set_attr "op_type" "RI")])
6962 (define_insn "main_base_64"
6963 [(set (match_operand 0 "register_operand" "=a")
6964 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6965 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6967 [(set_attr "op_type" "RIL")
6968 (set_attr "type" "larl")])
6970 (define_insn "main_pool"
6971 [(set (match_operand 0 "register_operand" "=a")
6972 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
6973 "GET_MODE (operands[0]) == Pmode"
6978 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
6979 (const_string "larl") (const_string "la")))])
6981 (define_insn "reload_base_31"
6982 [(set (match_operand 0 "register_operand" "=a")
6983 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6984 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6985 "basr\t%0,0\;la\t%0,%1-.(%0)"
6986 [(set_attr "length" "6")
6987 (set_attr "type" "la")])
6989 (define_insn "reload_base_64"
6990 [(set (match_operand 0 "register_operand" "=a")
6991 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6992 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6994 [(set_attr "op_type" "RIL")
6995 (set_attr "type" "larl")])
6998 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7003 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7006 ;; Insns related to generating the function prologue and epilogue.
7010 (define_expand "prologue"
7011 [(use (const_int 0))]
7013 "s390_emit_prologue (); DONE;")
7015 (define_insn "prologue_tpf"
7016 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
7017 (clobber (reg:DI 1))]
7018 "TARGET_TPF_PROFILING"
7019 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
7020 [(set_attr "length" "14")])
7022 (define_expand "epilogue"
7023 [(use (const_int 1))]
7025 "s390_emit_epilogue (false); DONE;")
7027 (define_insn "epilogue_tpf"
7028 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
7029 (clobber (reg:DI 1))]
7030 "TARGET_TPF_PROFILING"
7031 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
7032 [(set_attr "length" "14")])
7034 (define_expand "sibcall_epilogue"
7035 [(use (const_int 0))]
7037 "s390_emit_epilogue (true); DONE;")
7039 (define_insn "*return"
7041 (use (match_operand 0 "register_operand" "a"))]
7042 "GET_MODE (operands[0]) == Pmode"
7044 [(set_attr "op_type" "RR")
7045 (set_attr "type" "jsr")
7046 (set_attr "atype" "agen")])
7049 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7050 ;; pointer. This is used for compatibility.
7052 (define_expand "ptr_extend"
7053 [(set (match_operand:DI 0 "register_operand" "=r")
7054 (match_operand:SI 1 "register_operand" "r"))]
7057 emit_insn (gen_anddi3 (operands[0],
7058 gen_lowpart (DImode, operands[1]),
7059 GEN_INT (0x7fffffff)));
7063 ;; Instruction definition to expand eh_return macro to support
7064 ;; swapping in special linkage return addresses.
7066 (define_expand "eh_return"
7067 [(use (match_operand 0 "register_operand" ""))]
7070 s390_emit_tpf_eh_return (operands[0]);