| blob | 92eec48ae24c12453c5f5507a3ff32e6590784d8 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 ;; MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
54 (UNSPEC_STFIWX 32)
55 (UNSPEC_SYNC 33)
56 (UNSPEC_SYNC_OP 34)
57 (UNSPEC_SYNC_SWAP 35)
58 (UNSPEC_LWSYNC 36)
59 (UNSPEC_ISYNC 37)
60 (UNSPEC_POPCNTB 38)
61 (UNSPEC_FRES 39)
62 ])
64 ;;
65 ;; UNSPEC_VOLATILE usage
66 ;;
68 (define_constants
69 [(UNSPECV_BLOCK 0)
70 (UNSPECV_EH_RR 9) ; eh_reg_restore
71 ])
72 \f
73 ;; Define an insn type attribute. This is used in function unit delay
74 ;; computations.
75 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
76 (const_string "integer"))
78 ;; Length (in bytes).
79 ; '(pc)' in the following doesn't include the instruction itself; it is
80 ; calculated as if the instruction had zero size.
81 (define_attr "length" ""
82 (if_then_else (eq_attr "type" "branch")
83 (if_then_else (and (ge (minus (match_dup 0) (pc))
84 (const_int -32768))
85 (lt (minus (match_dup 0) (pc))
86 (const_int 32764)))
87 (const_int 4)
88 (const_int 8))
89 (const_int 4)))
91 ;; Processor type -- this attribute must exactly match the processor_type
92 ;; enumeration in rs6000.h.
94 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
95 (const (symbol_ref "rs6000_cpu_attr")))
97 (automata_option "ndfa")
99 (include "rios1.md")
100 (include "rios2.md")
101 (include "rs64.md")
102 (include "mpc.md")
103 (include "40x.md")
104 (include "440.md")
105 (include "603.md")
106 (include "6xx.md")
107 (include "7xx.md")
108 (include "7450.md")
109 (include "8540.md")
110 (include "power4.md")
111 (include "power5.md")
113 (include "predicates.md")
115 (include "darwin.md")
117 \f
118 ;; Mode macros
120 ; This mode macro allows :GPR to be used to indicate the allowable size
121 ; of whole values in GPRs.
122 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
124 ; Any supported integer mode.
125 (define_mode_macro INT [QI HI SI DI TI])
127 ; Any supported integer mode that fits in one register.
128 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
130 ; SImode or DImode, even if DImode doesn't fit in GPRs.
131 (define_mode_macro SDI [SI DI])
133 ; The size of a pointer. Also, the size of the value that a record-condition
134 ; (one with a '.') will compare.
135 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
137 ; Any hardware-supported floating-point mode
138 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
139 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
140 (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
141 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
143 ; Various instructions that come in SI and DI forms.
144 ; A generic w/d attribute, for things like cmpw/cmpd.
145 (define_mode_attr wd [(SI "w") (DI "d")])
147 \f
148 ;; Start with fixed-point load and store insns. Here we put only the more
149 ;; complex forms. Basic data transfer is done later.
151 (define_expand "zero_extendqidi2"
152 [(set (match_operand:DI 0 "gpc_reg_operand" "")
153 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
154 "TARGET_POWERPC64"
155 "")
157 (define_insn ""
158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
159 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
160 "TARGET_POWERPC64"
161 "@
162 lbz%U1%X1 %0,%1
163 rldicl %0,%1,0,56"
164 [(set_attr "type" "load,*")])
166 (define_insn ""
167 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
168 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
169 (const_int 0)))
170 (clobber (match_scratch:DI 2 "=r,r"))]
171 "TARGET_64BIT"
172 "@
173 rldicl. %2,%1,0,56
174 #"
175 [(set_attr "type" "compare")
176 (set_attr "length" "4,8")])
178 (define_split
179 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
180 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
181 (const_int 0)))
182 (clobber (match_scratch:DI 2 ""))]
183 "TARGET_POWERPC64 && reload_completed"
184 [(set (match_dup 2)
185 (zero_extend:DI (match_dup 1)))
186 (set (match_dup 0)
187 (compare:CC (match_dup 2)
188 (const_int 0)))]
189 "")
191 (define_insn ""
192 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
193 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
194 (const_int 0)))
195 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
196 (zero_extend:DI (match_dup 1)))]
197 "TARGET_64BIT"
198 "@
199 rldicl. %0,%1,0,56
200 #"
201 [(set_attr "type" "compare")
202 (set_attr "length" "4,8")])
204 (define_split
205 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
206 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
207 (const_int 0)))
208 (set (match_operand:DI 0 "gpc_reg_operand" "")
209 (zero_extend:DI (match_dup 1)))]
210 "TARGET_POWERPC64 && reload_completed"
211 [(set (match_dup 0)
212 (zero_extend:DI (match_dup 1)))
213 (set (match_dup 2)
214 (compare:CC (match_dup 0)
215 (const_int 0)))]
216 "")
218 (define_insn "extendqidi2"
219 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
220 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
221 "TARGET_POWERPC64"
222 "extsb %0,%1")
224 (define_insn ""
225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
226 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
227 (const_int 0)))
228 (clobber (match_scratch:DI 2 "=r,r"))]
229 "TARGET_64BIT"
230 "@
231 extsb. %2,%1
232 #"
233 [(set_attr "type" "compare")
234 (set_attr "length" "4,8")])
236 (define_split
237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
238 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
239 (const_int 0)))
240 (clobber (match_scratch:DI 2 ""))]
241 "TARGET_POWERPC64 && reload_completed"
242 [(set (match_dup 2)
243 (sign_extend:DI (match_dup 1)))
244 (set (match_dup 0)
245 (compare:CC (match_dup 2)
246 (const_int 0)))]
247 "")
249 (define_insn ""
250 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
251 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
252 (const_int 0)))
253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
254 (sign_extend:DI (match_dup 1)))]
255 "TARGET_64BIT"
256 "@
257 extsb. %0,%1
258 #"
259 [(set_attr "type" "compare")
260 (set_attr "length" "4,8")])
262 (define_split
263 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
264 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
265 (const_int 0)))
266 (set (match_operand:DI 0 "gpc_reg_operand" "")
267 (sign_extend:DI (match_dup 1)))]
268 "TARGET_POWERPC64 && reload_completed"
269 [(set (match_dup 0)
270 (sign_extend:DI (match_dup 1)))
271 (set (match_dup 2)
272 (compare:CC (match_dup 0)
273 (const_int 0)))]
274 "")
276 (define_expand "zero_extendhidi2"
277 [(set (match_operand:DI 0 "gpc_reg_operand" "")
278 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
279 "TARGET_POWERPC64"
280 "")
282 (define_insn ""
283 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
284 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
285 "TARGET_POWERPC64"
286 "@
287 lhz%U1%X1 %0,%1
288 rldicl %0,%1,0,48"
289 [(set_attr "type" "load,*")])
291 (define_insn ""
292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
293 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
294 (const_int 0)))
295 (clobber (match_scratch:DI 2 "=r,r"))]
296 "TARGET_64BIT"
297 "@
298 rldicl. %2,%1,0,48
299 #"
300 [(set_attr "type" "compare")
301 (set_attr "length" "4,8")])
303 (define_split
304 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
305 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
306 (const_int 0)))
307 (clobber (match_scratch:DI 2 ""))]
308 "TARGET_POWERPC64 && reload_completed"
309 [(set (match_dup 2)
310 (zero_extend:DI (match_dup 1)))
311 (set (match_dup 0)
312 (compare:CC (match_dup 2)
313 (const_int 0)))]
314 "")
316 (define_insn ""
317 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
318 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
319 (const_int 0)))
320 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
321 (zero_extend:DI (match_dup 1)))]
322 "TARGET_64BIT"
323 "@
324 rldicl. %0,%1,0,48
325 #"
326 [(set_attr "type" "compare")
327 (set_attr "length" "4,8")])
329 (define_split
330 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
331 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
332 (const_int 0)))
333 (set (match_operand:DI 0 "gpc_reg_operand" "")
334 (zero_extend:DI (match_dup 1)))]
335 "TARGET_POWERPC64 && reload_completed"
336 [(set (match_dup 0)
337 (zero_extend:DI (match_dup 1)))
338 (set (match_dup 2)
339 (compare:CC (match_dup 0)
340 (const_int 0)))]
341 "")
343 (define_expand "extendhidi2"
344 [(set (match_operand:DI 0 "gpc_reg_operand" "")
345 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
346 "TARGET_POWERPC64"
347 "")
349 (define_insn ""
350 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
351 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
352 "TARGET_POWERPC64"
353 "@
354 lha%U1%X1 %0,%1
355 extsh %0,%1"
356 [(set_attr "type" "load_ext,*")])
358 (define_insn ""
359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
360 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
361 (const_int 0)))
362 (clobber (match_scratch:DI 2 "=r,r"))]
363 "TARGET_64BIT"
364 "@
365 extsh. %2,%1
366 #"
367 [(set_attr "type" "compare")
368 (set_attr "length" "4,8")])
370 (define_split
371 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
372 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
373 (const_int 0)))
374 (clobber (match_scratch:DI 2 ""))]
375 "TARGET_POWERPC64 && reload_completed"
376 [(set (match_dup 2)
377 (sign_extend:DI (match_dup 1)))
378 (set (match_dup 0)
379 (compare:CC (match_dup 2)
380 (const_int 0)))]
381 "")
383 (define_insn ""
384 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
385 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
386 (const_int 0)))
387 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
388 (sign_extend:DI (match_dup 1)))]
389 "TARGET_64BIT"
390 "@
391 extsh. %0,%1
392 #"
393 [(set_attr "type" "compare")
394 (set_attr "length" "4,8")])
396 (define_split
397 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
398 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
399 (const_int 0)))
400 (set (match_operand:DI 0 "gpc_reg_operand" "")
401 (sign_extend:DI (match_dup 1)))]
402 "TARGET_POWERPC64 && reload_completed"
403 [(set (match_dup 0)
404 (sign_extend:DI (match_dup 1)))
405 (set (match_dup 2)
406 (compare:CC (match_dup 0)
407 (const_int 0)))]
408 "")
410 (define_expand "zero_extendsidi2"
411 [(set (match_operand:DI 0 "gpc_reg_operand" "")
412 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
413 "TARGET_POWERPC64"
414 "")
416 (define_insn ""
417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
418 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
419 "TARGET_POWERPC64"
420 "@
421 lwz%U1%X1 %0,%1
422 rldicl %0,%1,0,32"
423 [(set_attr "type" "load,*")])
425 (define_insn ""
426 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
427 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
428 (const_int 0)))
429 (clobber (match_scratch:DI 2 "=r,r"))]
430 "TARGET_64BIT"
431 "@
432 rldicl. %2,%1,0,32
433 #"
434 [(set_attr "type" "compare")
435 (set_attr "length" "4,8")])
437 (define_split
438 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
439 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
440 (const_int 0)))
441 (clobber (match_scratch:DI 2 ""))]
442 "TARGET_POWERPC64 && reload_completed"
443 [(set (match_dup 2)
444 (zero_extend:DI (match_dup 1)))
445 (set (match_dup 0)
446 (compare:CC (match_dup 2)
447 (const_int 0)))]
448 "")
450 (define_insn ""
451 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
452 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
453 (const_int 0)))
454 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
455 (zero_extend:DI (match_dup 1)))]
456 "TARGET_64BIT"
457 "@
458 rldicl. %0,%1,0,32
459 #"
460 [(set_attr "type" "compare")
461 (set_attr "length" "4,8")])
463 (define_split
464 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
465 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
466 (const_int 0)))
467 (set (match_operand:DI 0 "gpc_reg_operand" "")
468 (zero_extend:DI (match_dup 1)))]
469 "TARGET_POWERPC64 && reload_completed"
470 [(set (match_dup 0)
471 (zero_extend:DI (match_dup 1)))
472 (set (match_dup 2)
473 (compare:CC (match_dup 0)
474 (const_int 0)))]
475 "")
477 (define_expand "extendsidi2"
478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
479 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
480 "TARGET_POWERPC64"
481 "")
483 (define_insn ""
484 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
485 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
486 "TARGET_POWERPC64"
487 "@
488 lwa%U1%X1 %0,%1
489 extsw %0,%1"
490 [(set_attr "type" "load_ext,*")])
492 (define_insn ""
493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
494 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
495 (const_int 0)))
496 (clobber (match_scratch:DI 2 "=r,r"))]
497 "TARGET_64BIT"
498 "@
499 extsw. %2,%1
500 #"
501 [(set_attr "type" "compare")
502 (set_attr "length" "4,8")])
504 (define_split
505 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
506 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
507 (const_int 0)))
508 (clobber (match_scratch:DI 2 ""))]
509 "TARGET_POWERPC64 && reload_completed"
510 [(set (match_dup 2)
511 (sign_extend:DI (match_dup 1)))
512 (set (match_dup 0)
513 (compare:CC (match_dup 2)
514 (const_int 0)))]
515 "")
517 (define_insn ""
518 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
519 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
520 (const_int 0)))
521 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
522 (sign_extend:DI (match_dup 1)))]
523 "TARGET_64BIT"
524 "@
525 extsw. %0,%1
526 #"
527 [(set_attr "type" "compare")
528 (set_attr "length" "4,8")])
530 (define_split
531 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
532 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
533 (const_int 0)))
534 (set (match_operand:DI 0 "gpc_reg_operand" "")
535 (sign_extend:DI (match_dup 1)))]
536 "TARGET_POWERPC64 && reload_completed"
537 [(set (match_dup 0)
538 (sign_extend:DI (match_dup 1)))
539 (set (match_dup 2)
540 (compare:CC (match_dup 0)
541 (const_int 0)))]
542 "")
544 (define_expand "zero_extendqisi2"
545 [(set (match_operand:SI 0 "gpc_reg_operand" "")
546 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
547 ""
548 "")
550 (define_insn ""
551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
552 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
553 ""
554 "@
555 lbz%U1%X1 %0,%1
556 {rlinm|rlwinm} %0,%1,0,0xff"
557 [(set_attr "type" "load,*")])
559 (define_insn ""
560 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
561 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
562 (const_int 0)))
563 (clobber (match_scratch:SI 2 "=r,r"))]
564 ""
565 "@
566 {andil.|andi.} %2,%1,0xff
567 #"
568 [(set_attr "type" "compare")
569 (set_attr "length" "4,8")])
571 (define_split
572 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
573 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
574 (const_int 0)))
575 (clobber (match_scratch:SI 2 ""))]
576 "reload_completed"
577 [(set (match_dup 2)
578 (zero_extend:SI (match_dup 1)))
579 (set (match_dup 0)
580 (compare:CC (match_dup 2)
581 (const_int 0)))]
582 "")
584 (define_insn ""
585 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
586 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
587 (const_int 0)))
588 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
589 (zero_extend:SI (match_dup 1)))]
590 ""
591 "@
592 {andil.|andi.} %0,%1,0xff
593 #"
594 [(set_attr "type" "compare")
595 (set_attr "length" "4,8")])
597 (define_split
598 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
599 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
600 (const_int 0)))
601 (set (match_operand:SI 0 "gpc_reg_operand" "")
602 (zero_extend:SI (match_dup 1)))]
603 "reload_completed"
604 [(set (match_dup 0)
605 (zero_extend:SI (match_dup 1)))
606 (set (match_dup 2)
607 (compare:CC (match_dup 0)
608 (const_int 0)))]
609 "")
611 (define_expand "extendqisi2"
612 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
613 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
614 ""
615 "
616 {
617 if (TARGET_POWERPC)
618 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
619 else if (TARGET_POWER)
620 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
621 else
622 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
623 DONE;
624 }")
626 (define_insn "extendqisi2_ppc"
627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
628 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
629 "TARGET_POWERPC"
630 "extsb %0,%1")
632 (define_insn ""
633 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
634 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
635 (const_int 0)))
636 (clobber (match_scratch:SI 2 "=r,r"))]
637 "TARGET_POWERPC"
638 "@
639 extsb. %2,%1
640 #"
641 [(set_attr "type" "compare")
642 (set_attr "length" "4,8")])
644 (define_split
645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
646 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
647 (const_int 0)))
648 (clobber (match_scratch:SI 2 ""))]
649 "TARGET_POWERPC && reload_completed"
650 [(set (match_dup 2)
651 (sign_extend:SI (match_dup 1)))
652 (set (match_dup 0)
653 (compare:CC (match_dup 2)
654 (const_int 0)))]
655 "")
657 (define_insn ""
658 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
659 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
660 (const_int 0)))
661 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
662 (sign_extend:SI (match_dup 1)))]
663 "TARGET_POWERPC"
664 "@
665 extsb. %0,%1
666 #"
667 [(set_attr "type" "compare")
668 (set_attr "length" "4,8")])
670 (define_split
671 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
672 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
673 (const_int 0)))
674 (set (match_operand:SI 0 "gpc_reg_operand" "")
675 (sign_extend:SI (match_dup 1)))]
676 "TARGET_POWERPC && reload_completed"
677 [(set (match_dup 0)
678 (sign_extend:SI (match_dup 1)))
679 (set (match_dup 2)
680 (compare:CC (match_dup 0)
681 (const_int 0)))]
682 "")
684 (define_expand "extendqisi2_power"
685 [(parallel [(set (match_dup 2)
686 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
687 (const_int 24)))
688 (clobber (scratch:SI))])
689 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
690 (ashiftrt:SI (match_dup 2)
691 (const_int 24)))
692 (clobber (scratch:SI))])]
693 "TARGET_POWER"
694 "
695 { operands[1] = gen_lowpart (SImode, operands[1]);
696 operands[2] = gen_reg_rtx (SImode); }")
698 (define_expand "extendqisi2_no_power"
699 [(set (match_dup 2)
700 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
701 (const_int 24)))
702 (set (match_operand:SI 0 "gpc_reg_operand" "")
703 (ashiftrt:SI (match_dup 2)
704 (const_int 24)))]
705 "! TARGET_POWER && ! TARGET_POWERPC"
706 "
707 { operands[1] = gen_lowpart (SImode, operands[1]);
708 operands[2] = gen_reg_rtx (SImode); }")
710 (define_expand "zero_extendqihi2"
711 [(set (match_operand:HI 0 "gpc_reg_operand" "")
712 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
713 ""
714 "")
716 (define_insn ""
717 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
718 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
719 ""
720 "@
721 lbz%U1%X1 %0,%1
722 {rlinm|rlwinm} %0,%1,0,0xff"
723 [(set_attr "type" "load,*")])
725 (define_insn ""
726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
727 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
728 (const_int 0)))
729 (clobber (match_scratch:HI 2 "=r,r"))]
730 ""
731 "@
732 {andil.|andi.} %2,%1,0xff
733 #"
734 [(set_attr "type" "compare")
735 (set_attr "length" "4,8")])
737 (define_split
738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
739 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
740 (const_int 0)))
741 (clobber (match_scratch:HI 2 ""))]
742 "reload_completed"
743 [(set (match_dup 2)
744 (zero_extend:HI (match_dup 1)))
745 (set (match_dup 0)
746 (compare:CC (match_dup 2)
747 (const_int 0)))]
748 "")
750 (define_insn ""
751 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
752 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
753 (const_int 0)))
754 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
755 (zero_extend:HI (match_dup 1)))]
756 ""
757 "@
758 {andil.|andi.} %0,%1,0xff
759 #"
760 [(set_attr "type" "compare")
761 (set_attr "length" "4,8")])
763 (define_split
764 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
765 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
766 (const_int 0)))
767 (set (match_operand:HI 0 "gpc_reg_operand" "")
768 (zero_extend:HI (match_dup 1)))]
769 "reload_completed"
770 [(set (match_dup 0)
771 (zero_extend:HI (match_dup 1)))
772 (set (match_dup 2)
773 (compare:CC (match_dup 0)
774 (const_int 0)))]
775 "")
777 (define_expand "extendqihi2"
778 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
779 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
780 ""
781 "
782 {
783 if (TARGET_POWERPC)
784 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
785 else if (TARGET_POWER)
786 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
787 else
788 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
789 DONE;
790 }")
792 (define_insn "extendqihi2_ppc"
793 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
794 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
795 "TARGET_POWERPC"
796 "extsb %0,%1")
798 (define_insn ""
799 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
800 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
801 (const_int 0)))
802 (clobber (match_scratch:HI 2 "=r,r"))]
803 "TARGET_POWERPC"
804 "@
805 extsb. %2,%1
806 #"
807 [(set_attr "type" "compare")
808 (set_attr "length" "4,8")])
810 (define_split
811 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
812 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
813 (const_int 0)))
814 (clobber (match_scratch:HI 2 ""))]
815 "TARGET_POWERPC && reload_completed"
816 [(set (match_dup 2)
817 (sign_extend:HI (match_dup 1)))
818 (set (match_dup 0)
819 (compare:CC (match_dup 2)
820 (const_int 0)))]
821 "")
823 (define_insn ""
824 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
825 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
826 (const_int 0)))
827 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
828 (sign_extend:HI (match_dup 1)))]
829 "TARGET_POWERPC"
830 "@
831 extsb. %0,%1
832 #"
833 [(set_attr "type" "compare")
834 (set_attr "length" "4,8")])
836 (define_split
837 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
838 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
839 (const_int 0)))
840 (set (match_operand:HI 0 "gpc_reg_operand" "")
841 (sign_extend:HI (match_dup 1)))]
842 "TARGET_POWERPC && reload_completed"
843 [(set (match_dup 0)
844 (sign_extend:HI (match_dup 1)))
845 (set (match_dup 2)
846 (compare:CC (match_dup 0)
847 (const_int 0)))]
848 "")
850 (define_expand "extendqihi2_power"
851 [(parallel [(set (match_dup 2)
852 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
853 (const_int 24)))
854 (clobber (scratch:SI))])
855 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
856 (ashiftrt:SI (match_dup 2)
857 (const_int 24)))
858 (clobber (scratch:SI))])]
859 "TARGET_POWER"
860 "
861 { operands[0] = gen_lowpart (SImode, operands[0]);
862 operands[1] = gen_lowpart (SImode, operands[1]);
863 operands[2] = gen_reg_rtx (SImode); }")
865 (define_expand "extendqihi2_no_power"
866 [(set (match_dup 2)
867 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
868 (const_int 24)))
869 (set (match_operand:HI 0 "gpc_reg_operand" "")
870 (ashiftrt:SI (match_dup 2)
871 (const_int 24)))]
872 "! TARGET_POWER && ! TARGET_POWERPC"
873 "
874 { operands[0] = gen_lowpart (SImode, operands[0]);
875 operands[1] = gen_lowpart (SImode, operands[1]);
876 operands[2] = gen_reg_rtx (SImode); }")
878 (define_expand "zero_extendhisi2"
879 [(set (match_operand:SI 0 "gpc_reg_operand" "")
880 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
881 ""
882 "")
884 (define_insn ""
885 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
886 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
887 ""
888 "@
889 lhz%U1%X1 %0,%1
890 {rlinm|rlwinm} %0,%1,0,0xffff"
891 [(set_attr "type" "load,*")])
893 (define_insn ""
894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
895 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
896 (const_int 0)))
897 (clobber (match_scratch:SI 2 "=r,r"))]
898 ""
899 "@
900 {andil.|andi.} %2,%1,0xffff
901 #"
902 [(set_attr "type" "compare")
903 (set_attr "length" "4,8")])
905 (define_split
906 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
907 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
908 (const_int 0)))
909 (clobber (match_scratch:SI 2 ""))]
910 "reload_completed"
911 [(set (match_dup 2)
912 (zero_extend:SI (match_dup 1)))
913 (set (match_dup 0)
914 (compare:CC (match_dup 2)
915 (const_int 0)))]
916 "")
918 (define_insn ""
919 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
920 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
921 (const_int 0)))
922 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
923 (zero_extend:SI (match_dup 1)))]
924 ""
925 "@
926 {andil.|andi.} %0,%1,0xffff
927 #"
928 [(set_attr "type" "compare")
929 (set_attr "length" "4,8")])
931 (define_split
932 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
933 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
934 (const_int 0)))
935 (set (match_operand:SI 0 "gpc_reg_operand" "")
936 (zero_extend:SI (match_dup 1)))]
937 "reload_completed"
938 [(set (match_dup 0)
939 (zero_extend:SI (match_dup 1)))
940 (set (match_dup 2)
941 (compare:CC (match_dup 0)
942 (const_int 0)))]
943 "")
945 (define_expand "extendhisi2"
946 [(set (match_operand:SI 0 "gpc_reg_operand" "")
947 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
948 ""
949 "")
951 (define_insn ""
952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
953 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
954 ""
955 "@
956 lha%U1%X1 %0,%1
957 {exts|extsh} %0,%1"
958 [(set_attr "type" "load_ext,*")])
960 (define_insn ""
961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
962 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
963 (const_int 0)))
964 (clobber (match_scratch:SI 2 "=r,r"))]
965 ""
966 "@
967 {exts.|extsh.} %2,%1
968 #"
969 [(set_attr "type" "compare")
970 (set_attr "length" "4,8")])
972 (define_split
973 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
974 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
975 (const_int 0)))
976 (clobber (match_scratch:SI 2 ""))]
977 "reload_completed"
978 [(set (match_dup 2)
979 (sign_extend:SI (match_dup 1)))
980 (set (match_dup 0)
981 (compare:CC (match_dup 2)
982 (const_int 0)))]
983 "")
985 (define_insn ""
986 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
987 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
988 (const_int 0)))
989 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
990 (sign_extend:SI (match_dup 1)))]
991 ""
992 "@
993 {exts.|extsh.} %0,%1
994 #"
995 [(set_attr "type" "compare")
996 (set_attr "length" "4,8")])
997 \f
998 (define_split
999 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1000 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1001 (const_int 0)))
1002 (set (match_operand:SI 0 "gpc_reg_operand" "")
1003 (sign_extend:SI (match_dup 1)))]
1004 "reload_completed"
1005 [(set (match_dup 0)
1006 (sign_extend:SI (match_dup 1)))
1007 (set (match_dup 2)
1008 (compare:CC (match_dup 0)
1009 (const_int 0)))]
1010 "")
1012 ;; Fixed-point arithmetic insns.
1014 (define_expand "add<mode>3"
1015 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1016 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1017 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1018 ""
1019 "
1020 {
1021 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1022 {
1023 if (non_short_cint_operand (operands[2], DImode))
1024 FAIL;
1025 }
1026 else if (GET_CODE (operands[2]) == CONST_INT
1027 && ! add_operand (operands[2], <MODE>mode))
1028 {
1029 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1030 ? operands[0] : gen_reg_rtx (<MODE>mode));
1032 HOST_WIDE_INT val = INTVAL (operands[2]);
1033 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1034 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1036 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1037 FAIL;
1039 /* The ordering here is important for the prolog expander.
1040 When space is allocated from the stack, adding 'low' first may
1041 produce a temporary deallocation (which would be bad). */
1042 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1043 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1044 DONE;
1045 }
1046 }")
1048 ;; Discourage ai/addic because of carry but provide it in an alternative
1049 ;; allowing register zero as source.
1050 (define_insn "*add<mode>3_internal1"
1051 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1052 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1053 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1054 ""
1055 "@
1056 {cax|add} %0,%1,%2
1057 {cal %0,%2(%1)|addi %0,%1,%2}
1058 {ai|addic} %0,%1,%2
1059 {cau|addis} %0,%1,%v2"
1060 [(set_attr "length" "4,4,4,4")])
1062 (define_insn "addsi3_high"
1063 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1064 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1065 (high:SI (match_operand 2 "" ""))))]
1066 "TARGET_MACHO && !TARGET_64BIT"
1067 "{cau|addis} %0,%1,ha16(%2)"
1068 [(set_attr "length" "4")])
1070 (define_insn "*add<mode>3_internal2"
1071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1072 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1073 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1074 (const_int 0)))
1075 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1076 ""
1077 "@
1078 {cax.|add.} %3,%1,%2
1079 {ai.|addic.} %3,%1,%2
1080 #
1081 #"
1082 [(set_attr "type" "fast_compare,compare,compare,compare")
1083 (set_attr "length" "4,4,8,8")])
1085 (define_split
1086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1087 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1088 (match_operand:GPR 2 "reg_or_short_operand" ""))
1089 (const_int 0)))
1090 (clobber (match_scratch:GPR 3 ""))]
1091 "reload_completed"
1092 [(set (match_dup 3)
1093 (plus:GPR (match_dup 1)
1094 (match_dup 2)))
1095 (set (match_dup 0)
1096 (compare:CC (match_dup 3)
1097 (const_int 0)))]
1098 "")
1100 (define_insn "*add<mode>3_internal3"
1101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1102 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1103 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1104 (const_int 0)))
1105 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1106 (plus:P (match_dup 1)
1107 (match_dup 2)))]
1108 ""
1109 "@
1110 {cax.|add.} %0,%1,%2
1111 {ai.|addic.} %0,%1,%2
1112 #
1113 #"
1114 [(set_attr "type" "fast_compare,compare,compare,compare")
1115 (set_attr "length" "4,4,8,8")])
1117 (define_split
1118 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1119 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1120 (match_operand:P 2 "reg_or_short_operand" ""))
1121 (const_int 0)))
1122 (set (match_operand:P 0 "gpc_reg_operand" "")
1123 (plus:P (match_dup 1) (match_dup 2)))]
1124 "reload_completed"
1125 [(set (match_dup 0)
1126 (plus:P (match_dup 1)
1127 (match_dup 2)))
1128 (set (match_dup 3)
1129 (compare:CC (match_dup 0)
1130 (const_int 0)))]
1131 "")
1133 ;; Split an add that we can't do in one insn into two insns, each of which
1134 ;; does one 16-bit part. This is used by combine. Note that the low-order
1135 ;; add should be last in case the result gets used in an address.
1137 (define_split
1138 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1139 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1140 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1141 ""
1142 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1143 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1144 "
1145 {
1146 HOST_WIDE_INT val = INTVAL (operands[2]);
1147 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1148 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1150 operands[4] = GEN_INT (low);
1151 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1152 operands[3] = GEN_INT (rest);
1153 else if (! no_new_pseudos)
1154 {
1155 operands[3] = gen_reg_rtx (DImode);
1156 emit_move_insn (operands[3], operands[2]);
1157 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1158 DONE;
1159 }
1160 else
1161 FAIL;
1162 }")
1164 (define_insn "one_cmpl<mode>2"
1165 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1166 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1167 ""
1168 "nor %0,%1,%1")
1170 (define_insn ""
1171 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1172 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1173 (const_int 0)))
1174 (clobber (match_scratch:P 2 "=r,r"))]
1175 ""
1176 "@
1177 nor. %2,%1,%1
1178 #"
1179 [(set_attr "type" "compare")
1180 (set_attr "length" "4,8")])
1182 (define_split
1183 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1184 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1185 (const_int 0)))
1186 (clobber (match_scratch:P 2 ""))]
1187 "reload_completed"
1188 [(set (match_dup 2)
1189 (not:P (match_dup 1)))
1190 (set (match_dup 0)
1191 (compare:CC (match_dup 2)
1192 (const_int 0)))]
1193 "")
1195 (define_insn ""
1196 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1197 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1198 (const_int 0)))
1199 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1200 (not:P (match_dup 1)))]
1201 ""
1202 "@
1203 nor. %0,%1,%1
1204 #"
1205 [(set_attr "type" "compare")
1206 (set_attr "length" "4,8")])
1208 (define_split
1209 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1210 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1211 (const_int 0)))
1212 (set (match_operand:P 0 "gpc_reg_operand" "")
1213 (not:P (match_dup 1)))]
1214 "reload_completed"
1215 [(set (match_dup 0)
1216 (not:P (match_dup 1)))
1217 (set (match_dup 2)
1218 (compare:CC (match_dup 0)
1219 (const_int 0)))]
1220 "")
1222 (define_insn ""
1223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1224 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1225 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1226 "! TARGET_POWERPC"
1227 "{sf%I1|subf%I1c} %0,%2,%1")
1229 (define_insn ""
1230 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1231 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1232 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1233 "TARGET_POWERPC"
1234 "@
1235 subf %0,%2,%1
1236 subfic %0,%2,%1")
1238 (define_insn ""
1239 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1240 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1241 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1242 (const_int 0)))
1243 (clobber (match_scratch:SI 3 "=r,r"))]
1244 "! TARGET_POWERPC"
1245 "@
1246 {sf.|subfc.} %3,%2,%1
1247 #"
1248 [(set_attr "type" "compare")
1249 (set_attr "length" "4,8")])
1251 (define_insn ""
1252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1253 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1254 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1255 (const_int 0)))
1256 (clobber (match_scratch:P 3 "=r,r"))]
1257 "TARGET_POWERPC"
1258 "@
1259 subf. %3,%2,%1
1260 #"
1261 [(set_attr "type" "fast_compare")
1262 (set_attr "length" "4,8")])
1264 (define_split
1265 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1266 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1267 (match_operand:P 2 "gpc_reg_operand" ""))
1268 (const_int 0)))
1269 (clobber (match_scratch:P 3 ""))]
1270 "reload_completed"
1271 [(set (match_dup 3)
1272 (minus:P (match_dup 1)
1273 (match_dup 2)))
1274 (set (match_dup 0)
1275 (compare:CC (match_dup 3)
1276 (const_int 0)))]
1277 "")
1279 (define_insn ""
1280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1281 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1282 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1283 (const_int 0)))
1284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1285 (minus:SI (match_dup 1) (match_dup 2)))]
1286 "! TARGET_POWERPC"
1287 "@
1288 {sf.|subfc.} %0,%2,%1
1289 #"
1290 [(set_attr "type" "compare")
1291 (set_attr "length" "4,8")])
1293 (define_insn ""
1294 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1295 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1296 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1297 (const_int 0)))
1298 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1299 (minus:P (match_dup 1)
1300 (match_dup 2)))]
1301 "TARGET_POWERPC"
1302 "@
1303 subf. %0,%2,%1
1304 #"
1305 [(set_attr "type" "fast_compare")
1306 (set_attr "length" "4,8")])
1308 (define_split
1309 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1310 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1311 (match_operand:P 2 "gpc_reg_operand" ""))
1312 (const_int 0)))
1313 (set (match_operand:P 0 "gpc_reg_operand" "")
1314 (minus:P (match_dup 1)
1315 (match_dup 2)))]
1316 "reload_completed"
1317 [(set (match_dup 0)
1318 (minus:P (match_dup 1)
1319 (match_dup 2)))
1320 (set (match_dup 3)
1321 (compare:CC (match_dup 0)
1322 (const_int 0)))]
1323 "")
1325 (define_expand "sub<mode>3"
1326 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1327 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1328 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1329 ""
1330 "
1331 {
1332 if (GET_CODE (operands[2]) == CONST_INT)
1333 {
1334 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1335 negate_rtx (<MODE>mode, operands[2])));
1336 DONE;
1337 }
1338 }")
1340 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1341 ;; instruction and some auxiliary computations. Then we just have a single
1342 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1343 ;; combine.
1345 (define_expand "sminsi3"
1346 [(set (match_dup 3)
1347 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1348 (match_operand:SI 2 "reg_or_short_operand" ""))
1349 (const_int 0)
1350 (minus:SI (match_dup 2) (match_dup 1))))
1351 (set (match_operand:SI 0 "gpc_reg_operand" "")
1352 (minus:SI (match_dup 2) (match_dup 3)))]
1353 "TARGET_POWER || TARGET_ISEL"
1354 "
1355 {
1356 if (TARGET_ISEL)
1357 {
1358 operands[2] = force_reg (SImode, operands[2]);
1359 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1360 DONE;
1361 }
1363 operands[3] = gen_reg_rtx (SImode);
1364 }")
1366 (define_split
1367 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1368 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1369 (match_operand:SI 2 "reg_or_short_operand" "")))
1370 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1371 "TARGET_POWER"
1372 [(set (match_dup 3)
1373 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1374 (const_int 0)
1375 (minus:SI (match_dup 2) (match_dup 1))))
1376 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1377 "")
1379 (define_expand "smaxsi3"
1380 [(set (match_dup 3)
1381 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1382 (match_operand:SI 2 "reg_or_short_operand" ""))
1383 (const_int 0)
1384 (minus:SI (match_dup 2) (match_dup 1))))
1385 (set (match_operand:SI 0 "gpc_reg_operand" "")
1386 (plus:SI (match_dup 3) (match_dup 1)))]
1387 "TARGET_POWER || TARGET_ISEL"
1388 "
1389 {
1390 if (TARGET_ISEL)
1391 {
1392 operands[2] = force_reg (SImode, operands[2]);
1393 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1394 DONE;
1395 }
1396 operands[3] = gen_reg_rtx (SImode);
1397 }")
1399 (define_split
1400 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1401 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1402 (match_operand:SI 2 "reg_or_short_operand" "")))
1403 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1404 "TARGET_POWER"
1405 [(set (match_dup 3)
1406 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1407 (const_int 0)
1408 (minus:SI (match_dup 2) (match_dup 1))))
1409 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1410 "")
1412 (define_expand "uminsi3"
1413 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1414 (match_dup 5)))
1415 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1416 (match_dup 5)))
1417 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1418 (const_int 0)
1419 (minus:SI (match_dup 4) (match_dup 3))))
1420 (set (match_operand:SI 0 "gpc_reg_operand" "")
1421 (minus:SI (match_dup 2) (match_dup 3)))]
1422 "TARGET_POWER || TARGET_ISEL"
1423 "
1424 {
1425 if (TARGET_ISEL)
1426 {
1427 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1428 DONE;
1429 }
1430 operands[3] = gen_reg_rtx (SImode);
1431 operands[4] = gen_reg_rtx (SImode);
1432 operands[5] = GEN_INT (-2147483647 - 1);
1433 }")
1435 (define_expand "umaxsi3"
1436 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1437 (match_dup 5)))
1438 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1439 (match_dup 5)))
1440 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1441 (const_int 0)
1442 (minus:SI (match_dup 4) (match_dup 3))))
1443 (set (match_operand:SI 0 "gpc_reg_operand" "")
1444 (plus:SI (match_dup 3) (match_dup 1)))]
1445 "TARGET_POWER || TARGET_ISEL"
1446 "
1447 {
1448 if (TARGET_ISEL)
1449 {
1450 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1451 DONE;
1452 }
1453 operands[3] = gen_reg_rtx (SImode);
1454 operands[4] = gen_reg_rtx (SImode);
1455 operands[5] = GEN_INT (-2147483647 - 1);
1456 }")
1458 (define_insn ""
1459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1460 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1461 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1462 (const_int 0)
1463 (minus:SI (match_dup 2) (match_dup 1))))]
1464 "TARGET_POWER"
1465 "doz%I2 %0,%1,%2")
1467 (define_insn ""
1468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1469 (compare:CC
1470 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1471 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1472 (const_int 0)
1473 (minus:SI (match_dup 2) (match_dup 1)))
1474 (const_int 0)))
1475 (clobber (match_scratch:SI 3 "=r,r"))]
1476 "TARGET_POWER"
1477 "@
1478 doz%I2. %3,%1,%2
1479 #"
1480 [(set_attr "type" "delayed_compare")
1481 (set_attr "length" "4,8")])
1483 (define_split
1484 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1485 (compare:CC
1486 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1487 (match_operand:SI 2 "reg_or_short_operand" ""))
1488 (const_int 0)
1489 (minus:SI (match_dup 2) (match_dup 1)))
1490 (const_int 0)))
1491 (clobber (match_scratch:SI 3 ""))]
1492 "TARGET_POWER && reload_completed"
1493 [(set (match_dup 3)
1494 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1495 (const_int 0)
1496 (minus:SI (match_dup 2) (match_dup 1))))
1497 (set (match_dup 0)
1498 (compare:CC (match_dup 3)
1499 (const_int 0)))]
1500 "")
1502 (define_insn ""
1503 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1504 (compare:CC
1505 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1506 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1507 (const_int 0)
1508 (minus:SI (match_dup 2) (match_dup 1)))
1509 (const_int 0)))
1510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1511 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1512 (const_int 0)
1513 (minus:SI (match_dup 2) (match_dup 1))))]
1514 "TARGET_POWER"
1515 "@
1516 doz%I2. %0,%1,%2
1517 #"
1518 [(set_attr "type" "delayed_compare")
1519 (set_attr "length" "4,8")])
1521 (define_split
1522 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1523 (compare:CC
1524 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1525 (match_operand:SI 2 "reg_or_short_operand" ""))
1526 (const_int 0)
1527 (minus:SI (match_dup 2) (match_dup 1)))
1528 (const_int 0)))
1529 (set (match_operand:SI 0 "gpc_reg_operand" "")
1530 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1531 (const_int 0)
1532 (minus:SI (match_dup 2) (match_dup 1))))]
1533 "TARGET_POWER && reload_completed"
1534 [(set (match_dup 0)
1535 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1536 (const_int 0)
1537 (minus:SI (match_dup 2) (match_dup 1))))
1538 (set (match_dup 3)
1539 (compare:CC (match_dup 0)
1540 (const_int 0)))]
1541 "")
1543 ;; We don't need abs with condition code because such comparisons should
1544 ;; never be done.
1545 (define_expand "abssi2"
1546 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1547 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1548 ""
1549 "
1550 {
1551 if (TARGET_ISEL)
1552 {
1553 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1554 DONE;
1555 }
1556 else if (! TARGET_POWER)
1557 {
1558 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1559 DONE;
1560 }
1561 }")
1563 (define_insn "*abssi2_power"
1564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1565 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1566 "TARGET_POWER"
1567 "abs %0,%1")
1569 (define_insn_and_split "abssi2_isel"
1570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1571 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1572 (clobber (match_scratch:SI 2 "=&b"))
1573 (clobber (match_scratch:CC 3 "=y"))]
1574 "TARGET_ISEL"
1575 "#"
1576 "&& reload_completed"
1577 [(set (match_dup 2) (neg:SI (match_dup 1)))
1578 (set (match_dup 3)
1579 (compare:CC (match_dup 1)
1580 (const_int 0)))
1581 (set (match_dup 0)
1582 (if_then_else:SI (ge (match_dup 3)
1583 (const_int 0))
1584 (match_dup 1)
1585 (match_dup 2)))]
1586 "")
1588 (define_insn_and_split "abssi2_nopower"
1589 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1590 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1591 (clobber (match_scratch:SI 2 "=&r,&r"))]
1592 "! TARGET_POWER && ! TARGET_ISEL"
1593 "#"
1594 "&& reload_completed"
1595 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1596 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1597 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1598 "")
1600 (define_insn "*nabs_power"
1601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1602 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1603 "TARGET_POWER"
1604 "nabs %0,%1")
1606 (define_insn_and_split "*nabs_nopower"
1607 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1608 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1609 (clobber (match_scratch:SI 2 "=&r,&r"))]
1610 "! TARGET_POWER"
1611 "#"
1612 "&& reload_completed"
1613 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1614 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1615 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1616 "")
1618 (define_expand "neg<mode>2"
1619 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1620 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1621 ""
1622 "")
1624 (define_insn "*neg<mode>2_internal"
1625 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1626 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1627 ""
1628 "neg %0,%1")
1630 (define_insn ""
1631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1632 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1633 (const_int 0)))
1634 (clobber (match_scratch:P 2 "=r,r"))]
1635 ""
1636 "@
1637 neg. %2,%1
1638 #"
1639 [(set_attr "type" "fast_compare")
1640 (set_attr "length" "4,8")])
1642 (define_split
1643 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1644 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1645 (const_int 0)))
1646 (clobber (match_scratch:P 2 ""))]
1647 "reload_completed"
1648 [(set (match_dup 2)
1649 (neg:P (match_dup 1)))
1650 (set (match_dup 0)
1651 (compare:CC (match_dup 2)
1652 (const_int 0)))]
1653 "")
1655 (define_insn ""
1656 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1657 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1658 (const_int 0)))
1659 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1660 (neg:P (match_dup 1)))]
1661 ""
1662 "@
1663 neg. %0,%1
1664 #"
1665 [(set_attr "type" "fast_compare")
1666 (set_attr "length" "4,8")])
1668 (define_split
1669 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1670 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1671 (const_int 0)))
1672 (set (match_operand:P 0 "gpc_reg_operand" "")
1673 (neg:P (match_dup 1)))]
1674 "reload_completed"
1675 [(set (match_dup 0)
1676 (neg:P (match_dup 1)))
1677 (set (match_dup 2)
1678 (compare:CC (match_dup 0)
1679 (const_int 0)))]
1680 "")
1682 (define_insn "clz<mode>2"
1683 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1684 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1685 ""
1686 "{cntlz|cntlz<wd>} %0,%1")
1688 (define_expand "ctz<mode>2"
1689 [(set (match_dup 2)
1690 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1691 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1692 (match_dup 2)))
1693 (clobber (scratch:CC))])
1694 (set (match_dup 4) (clz:GPR (match_dup 3)))
1695 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1696 (minus:GPR (match_dup 5) (match_dup 4)))]
1697 ""
1698 {
1699 operands[2] = gen_reg_rtx (<MODE>mode);
1700 operands[3] = gen_reg_rtx (<MODE>mode);
1701 operands[4] = gen_reg_rtx (<MODE>mode);
1702 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1703 })
1705 (define_expand "ffs<mode>2"
1706 [(set (match_dup 2)
1707 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1708 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1709 (match_dup 2)))
1710 (clobber (scratch:CC))])
1711 (set (match_dup 4) (clz:GPR (match_dup 3)))
1712 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1713 (minus:GPR (match_dup 5) (match_dup 4)))]
1714 ""
1715 {
1716 operands[2] = gen_reg_rtx (<MODE>mode);
1717 operands[3] = gen_reg_rtx (<MODE>mode);
1718 operands[4] = gen_reg_rtx (<MODE>mode);
1719 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1720 })
1722 (define_expand "popcount<mode>2"
1723 [(set (match_dup 2)
1724 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1725 UNSPEC_POPCNTB))
1726 (set (match_dup 3)
1727 (mult:GPR (match_dup 2) (match_dup 4)))
1728 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1729 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1730 "TARGET_POPCNTB"
1731 {
1732 operands[2] = gen_reg_rtx (<MODE>mode);
1733 operands[3] = gen_reg_rtx (<MODE>mode);
1734 operands[4] = force_reg (<MODE>mode,
1735 <MODE>mode == SImode
1736 ? GEN_INT (0x01010101)
1737 : GEN_INT ((HOST_WIDE_INT)
1738 0x01010101 << 32 | 0x01010101));
1739 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1740 })
1742 (define_insn "popcntb<mode>2"
1743 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1744 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1745 UNSPEC_POPCNTB))]
1746 "TARGET_POPCNTB"
1747 "popcntb %0,%1")
1749 (define_expand "mulsi3"
1750 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1751 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1752 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1753 ""
1754 "
1755 {
1756 if (TARGET_POWER)
1757 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1758 else
1759 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1760 DONE;
1761 }")
1763 (define_insn "mulsi3_mq"
1764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1765 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1766 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1767 (clobber (match_scratch:SI 3 "=q,q"))]
1768 "TARGET_POWER"
1769 "@
1770 {muls|mullw} %0,%1,%2
1771 {muli|mulli} %0,%1,%2"
1772 [(set (attr "type")
1773 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1774 (const_string "imul3")
1775 (match_operand:SI 2 "short_cint_operand" "")
1776 (const_string "imul2")]
1777 (const_string "imul")))])
1779 (define_insn "mulsi3_no_mq"
1780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1781 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1782 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1783 "! TARGET_POWER"
1784 "@
1785 {muls|mullw} %0,%1,%2
1786 {muli|mulli} %0,%1,%2"
1787 [(set (attr "type")
1788 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1789 (const_string "imul3")
1790 (match_operand:SI 2 "short_cint_operand" "")
1791 (const_string "imul2")]
1792 (const_string "imul")))])
1794 (define_insn "*mulsi3_mq_internal1"
1795 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1796 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1797 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1798 (const_int 0)))
1799 (clobber (match_scratch:SI 3 "=r,r"))
1800 (clobber (match_scratch:SI 4 "=q,q"))]
1801 "TARGET_POWER"
1802 "@
1803 {muls.|mullw.} %3,%1,%2
1804 #"
1805 [(set_attr "type" "imul_compare")
1806 (set_attr "length" "4,8")])
1808 (define_split
1809 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1810 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1811 (match_operand:SI 2 "gpc_reg_operand" ""))
1812 (const_int 0)))
1813 (clobber (match_scratch:SI 3 ""))
1814 (clobber (match_scratch:SI 4 ""))]
1815 "TARGET_POWER && reload_completed"
1816 [(parallel [(set (match_dup 3)
1817 (mult:SI (match_dup 1) (match_dup 2)))
1818 (clobber (match_dup 4))])
1819 (set (match_dup 0)
1820 (compare:CC (match_dup 3)
1821 (const_int 0)))]
1822 "")
1824 (define_insn "*mulsi3_no_mq_internal1"
1825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1826 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1827 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1828 (const_int 0)))
1829 (clobber (match_scratch:SI 3 "=r,r"))]
1830 "! TARGET_POWER"
1831 "@
1832 {muls.|mullw.} %3,%1,%2
1833 #"
1834 [(set_attr "type" "imul_compare")
1835 (set_attr "length" "4,8")])
1837 (define_split
1838 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1839 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1840 (match_operand:SI 2 "gpc_reg_operand" ""))
1841 (const_int 0)))
1842 (clobber (match_scratch:SI 3 ""))]
1843 "! TARGET_POWER && reload_completed"
1844 [(set (match_dup 3)
1845 (mult:SI (match_dup 1) (match_dup 2)))
1846 (set (match_dup 0)
1847 (compare:CC (match_dup 3)
1848 (const_int 0)))]
1849 "")
1851 (define_insn "*mulsi3_mq_internal2"
1852 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1853 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1854 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1855 (const_int 0)))
1856 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1857 (mult:SI (match_dup 1) (match_dup 2)))
1858 (clobber (match_scratch:SI 4 "=q,q"))]
1859 "TARGET_POWER"
1860 "@
1861 {muls.|mullw.} %0,%1,%2
1862 #"
1863 [(set_attr "type" "imul_compare")
1864 (set_attr "length" "4,8")])
1866 (define_split
1867 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1868 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1869 (match_operand:SI 2 "gpc_reg_operand" ""))
1870 (const_int 0)))
1871 (set (match_operand:SI 0 "gpc_reg_operand" "")
1872 (mult:SI (match_dup 1) (match_dup 2)))
1873 (clobber (match_scratch:SI 4 ""))]
1874 "TARGET_POWER && reload_completed"
1875 [(parallel [(set (match_dup 0)
1876 (mult:SI (match_dup 1) (match_dup 2)))
1877 (clobber (match_dup 4))])
1878 (set (match_dup 3)
1879 (compare:CC (match_dup 0)
1880 (const_int 0)))]
1881 "")
1883 (define_insn "*mulsi3_no_mq_internal2"
1884 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1885 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1886 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1887 (const_int 0)))
1888 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1889 (mult:SI (match_dup 1) (match_dup 2)))]
1890 "! TARGET_POWER"
1891 "@
1892 {muls.|mullw.} %0,%1,%2
1893 #"
1894 [(set_attr "type" "imul_compare")
1895 (set_attr "length" "4,8")])
1897 (define_split
1898 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1899 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1900 (match_operand:SI 2 "gpc_reg_operand" ""))
1901 (const_int 0)))
1902 (set (match_operand:SI 0 "gpc_reg_operand" "")
1903 (mult:SI (match_dup 1) (match_dup 2)))]
1904 "! TARGET_POWER && reload_completed"
1905 [(set (match_dup 0)
1906 (mult:SI (match_dup 1) (match_dup 2)))
1907 (set (match_dup 3)
1908 (compare:CC (match_dup 0)
1909 (const_int 0)))]
1910 "")
1912 ;; Operand 1 is divided by operand 2; quotient goes to operand
1913 ;; 0 and remainder to operand 3.
1914 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1916 (define_expand "divmodsi4"
1917 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1918 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1919 (match_operand:SI 2 "gpc_reg_operand" "")))
1920 (set (match_operand:SI 3 "register_operand" "")
1921 (mod:SI (match_dup 1) (match_dup 2)))])]
1922 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1923 "
1924 {
1925 if (! TARGET_POWER && ! TARGET_POWERPC)
1926 {
1927 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1928 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1929 emit_insn (gen_divss_call ());
1930 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1931 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1932 DONE;
1933 }
1934 }")
1936 (define_insn "*divmodsi4_internal"
1937 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1938 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1939 (match_operand:SI 2 "gpc_reg_operand" "r")))
1940 (set (match_operand:SI 3 "register_operand" "=q")
1941 (mod:SI (match_dup 1) (match_dup 2)))]
1942 "TARGET_POWER"
1943 "divs %0,%1,%2"
1944 [(set_attr "type" "idiv")])
1946 (define_expand "udiv<mode>3"
1947 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1948 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1949 (match_operand:GPR 2 "gpc_reg_operand" "")))]
1950 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1951 "
1952 {
1953 if (! TARGET_POWER && ! TARGET_POWERPC)
1954 {
1955 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1956 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1957 emit_insn (gen_quous_call ());
1958 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1959 DONE;
1960 }
1961 else if (TARGET_POWER)
1962 {
1963 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1964 DONE;
1965 }
1966 }")
1968 (define_insn "udivsi3_mq"
1969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1970 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1971 (match_operand:SI 2 "gpc_reg_operand" "r")))
1972 (clobber (match_scratch:SI 3 "=q"))]
1973 "TARGET_POWERPC && TARGET_POWER"
1974 "divwu %0,%1,%2"
1975 [(set_attr "type" "idiv")])
1977 (define_insn "*udivsi3_no_mq"
1978 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1979 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1980 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
1981 "TARGET_POWERPC && ! TARGET_POWER"
1982 "div<wd>u %0,%1,%2"
1983 [(set_attr "type" "idiv")])
1985 ;; For powers of two we can do srai/aze for divide and then adjust for
1986 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1987 ;; used; for PowerPC, force operands into register and do a normal divide;
1988 ;; for AIX common-mode, use quoss call on register operands.
1989 (define_expand "div<mode>3"
1990 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1991 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1992 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1993 ""
1994 "
1995 {
1996 if (GET_CODE (operands[2]) == CONST_INT
1997 && INTVAL (operands[2]) > 0
1998 && exact_log2 (INTVAL (operands[2])) >= 0)
1999 ;
2000 else if (TARGET_POWERPC)
2001 {
2002 operands[2] = force_reg (SImode, operands[2]);
2003 if (TARGET_POWER)
2004 {
2005 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2006 DONE;
2007 }
2008 }
2009 else if (TARGET_POWER)
2010 FAIL;
2011 else
2012 {
2013 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2014 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2015 emit_insn (gen_quoss_call ());
2016 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2017 DONE;
2018 }
2019 }")
2021 (define_insn "divsi3_mq"
2022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2023 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2024 (match_operand:SI 2 "gpc_reg_operand" "r")))
2025 (clobber (match_scratch:SI 3 "=q"))]
2026 "TARGET_POWERPC && TARGET_POWER"
2027 "divw %0,%1,%2"
2028 [(set_attr "type" "idiv")])
2030 (define_insn "*div<mode>3_no_mq"
2031 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2032 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2033 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2034 "TARGET_POWERPC && ! TARGET_POWER"
2035 "div<wd> %0,%1,%2"
2036 [(set_attr "type" "idiv")])
2038 (define_expand "mod<mode>3"
2039 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2040 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2041 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2042 ""
2043 "
2044 {
2045 int i;
2046 rtx temp1;
2047 rtx temp2;
2049 if (GET_CODE (operands[2]) != CONST_INT
2050 || INTVAL (operands[2]) <= 0
2051 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2052 FAIL;
2054 temp1 = gen_reg_rtx (<MODE>mode);
2055 temp2 = gen_reg_rtx (<MODE>mode);
2057 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2058 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2059 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2060 DONE;
2061 }")
2063 (define_insn ""
2064 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2065 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2066 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2067 ""
2068 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2069 [(set_attr "type" "two")
2070 (set_attr "length" "8")])
2072 (define_insn ""
2073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2074 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2075 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2076 (const_int 0)))
2077 (clobber (match_scratch:P 3 "=r,r"))]
2078 ""
2079 "@
2080 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2081 #"
2082 [(set_attr "type" "compare")
2083 (set_attr "length" "8,12")])
2085 (define_split
2086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2087 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2088 (match_operand:GPR 2 "exact_log2_cint_operand"
2089 ""))
2090 (const_int 0)))
2091 (clobber (match_scratch:GPR 3 ""))]
2092 "reload_completed"
2093 [(set (match_dup 3)
2094 (div:<MODE> (match_dup 1) (match_dup 2)))
2095 (set (match_dup 0)
2096 (compare:CC (match_dup 3)
2097 (const_int 0)))]
2098 "")
2100 (define_insn ""
2101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2102 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2103 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2104 (const_int 0)))
2105 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2106 (div:P (match_dup 1) (match_dup 2)))]
2107 ""
2108 "@
2109 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2110 #"
2111 [(set_attr "type" "compare")
2112 (set_attr "length" "8,12")])
2114 (define_split
2115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2116 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2117 (match_operand:GPR 2 "exact_log2_cint_operand"
2118 ""))
2119 (const_int 0)))
2120 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2121 (div:GPR (match_dup 1) (match_dup 2)))]
2122 "reload_completed"
2123 [(set (match_dup 0)
2124 (div:<MODE> (match_dup 1) (match_dup 2)))
2125 (set (match_dup 3)
2126 (compare:CC (match_dup 0)
2127 (const_int 0)))]
2128 "")
2130 (define_insn ""
2131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2132 (udiv:SI
2133 (plus:DI (ashift:DI
2134 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2135 (const_int 32))
2136 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2137 (match_operand:SI 3 "gpc_reg_operand" "r")))
2138 (set (match_operand:SI 2 "register_operand" "=*q")
2139 (umod:SI
2140 (plus:DI (ashift:DI
2141 (zero_extend:DI (match_dup 1)) (const_int 32))
2142 (zero_extend:DI (match_dup 4)))
2143 (match_dup 3)))]
2144 "TARGET_POWER"
2145 "div %0,%1,%3"
2146 [(set_attr "type" "idiv")])
2148 ;; To do unsigned divide we handle the cases of the divisor looking like a
2149 ;; negative number. If it is a constant that is less than 2**31, we don't
2150 ;; have to worry about the branches. So make a few subroutines here.
2151 ;;
2152 ;; First comes the normal case.
2153 (define_expand "udivmodsi4_normal"
2154 [(set (match_dup 4) (const_int 0))
2155 (parallel [(set (match_operand:SI 0 "" "")
2156 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2157 (const_int 32))
2158 (zero_extend:DI (match_operand:SI 1 "" "")))
2159 (match_operand:SI 2 "" "")))
2160 (set (match_operand:SI 3 "" "")
2161 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2162 (const_int 32))
2163 (zero_extend:DI (match_dup 1)))
2164 (match_dup 2)))])]
2165 "TARGET_POWER"
2166 "
2167 { operands[4] = gen_reg_rtx (SImode); }")
2169 ;; This handles the branches.
2170 (define_expand "udivmodsi4_tests"
2171 [(set (match_operand:SI 0 "" "") (const_int 0))
2172 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2173 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2174 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2175 (label_ref (match_operand:SI 4 "" "")) (pc)))
2176 (set (match_dup 0) (const_int 1))
2177 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2178 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2179 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2180 (label_ref (match_dup 4)) (pc)))]
2181 "TARGET_POWER"
2182 "
2183 { operands[5] = gen_reg_rtx (CCUNSmode);
2184 operands[6] = gen_reg_rtx (CCmode);
2185 }")
2187 (define_expand "udivmodsi4"
2188 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2189 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2190 (match_operand:SI 2 "reg_or_cint_operand" "")))
2191 (set (match_operand:SI 3 "gpc_reg_operand" "")
2192 (umod:SI (match_dup 1) (match_dup 2)))])]
2193 ""
2194 "
2195 {
2196 rtx label = 0;
2198 if (! TARGET_POWER)
2199 {
2200 if (! TARGET_POWERPC)
2201 {
2202 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2203 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2204 emit_insn (gen_divus_call ());
2205 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2206 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2207 DONE;
2208 }
2209 else
2210 FAIL;
2211 }
2213 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2214 {
2215 operands[2] = force_reg (SImode, operands[2]);
2216 label = gen_label_rtx ();
2217 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2218 operands[3], label));
2219 }
2220 else
2221 operands[2] = force_reg (SImode, operands[2]);
2223 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2224 operands[3]));
2225 if (label)
2226 emit_label (label);
2228 DONE;
2229 }")
2231 ;; AIX architecture-independent common-mode multiply (DImode),
2232 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2233 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2234 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2235 ;; assumed unused if generating common-mode, so ignore.
2236 (define_insn "mulh_call"
2237 [(set (reg:SI 3)
2238 (truncate:SI
2239 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2240 (sign_extend:DI (reg:SI 4)))
2241 (const_int 32))))
2242 (clobber (match_scratch:SI 0 "=l"))]
2243 "! TARGET_POWER && ! TARGET_POWERPC"
2244 "bla __mulh"
2245 [(set_attr "type" "imul")])
2247 (define_insn "mull_call"
2248 [(set (reg:DI 3)
2249 (mult:DI (sign_extend:DI (reg:SI 3))
2250 (sign_extend:DI (reg:SI 4))))
2251 (clobber (match_scratch:SI 0 "=l"))
2252 (clobber (reg:SI 0))]
2253 "! TARGET_POWER && ! TARGET_POWERPC"
2254 "bla __mull"
2255 [(set_attr "type" "imul")])
2257 (define_insn "divss_call"
2258 [(set (reg:SI 3)
2259 (div:SI (reg:SI 3) (reg:SI 4)))
2260 (set (reg:SI 4)
2261 (mod:SI (reg:SI 3) (reg:SI 4)))
2262 (clobber (match_scratch:SI 0 "=l"))
2263 (clobber (reg:SI 0))]
2264 "! TARGET_POWER && ! TARGET_POWERPC"
2265 "bla __divss"
2266 [(set_attr "type" "idiv")])
2268 (define_insn "divus_call"
2269 [(set (reg:SI 3)
2270 (udiv:SI (reg:SI 3) (reg:SI 4)))
2271 (set (reg:SI 4)
2272 (umod:SI (reg:SI 3) (reg:SI 4)))
2273 (clobber (match_scratch:SI 0 "=l"))
2274 (clobber (reg:SI 0))
2275 (clobber (match_scratch:CC 1 "=x"))
2276 (clobber (reg:CC 69))]
2277 "! TARGET_POWER && ! TARGET_POWERPC"
2278 "bla __divus"
2279 [(set_attr "type" "idiv")])
2281 (define_insn "quoss_call"
2282 [(set (reg:SI 3)
2283 (div:SI (reg:SI 3) (reg:SI 4)))
2284 (clobber (match_scratch:SI 0 "=l"))]
2285 "! TARGET_POWER && ! TARGET_POWERPC"
2286 "bla __quoss"
2287 [(set_attr "type" "idiv")])
2289 (define_insn "quous_call"
2290 [(set (reg:SI 3)
2291 (udiv:SI (reg:SI 3) (reg:SI 4)))
2292 (clobber (match_scratch:SI 0 "=l"))
2293 (clobber (reg:SI 0))
2294 (clobber (match_scratch:CC 1 "=x"))
2295 (clobber (reg:CC 69))]
2296 "! TARGET_POWER && ! TARGET_POWERPC"
2297 "bla __quous"
2298 [(set_attr "type" "idiv")])
2299 \f
2300 ;; Logical instructions
2301 ;; The logical instructions are mostly combined by using match_operator,
2302 ;; but the plain AND insns are somewhat different because there is no
2303 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2304 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2306 (define_insn "andsi3"
2307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2308 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2309 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2310 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2311 ""
2312 "@
2313 and %0,%1,%2
2314 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2315 {andil.|andi.} %0,%1,%b2
2316 {andiu.|andis.} %0,%1,%u2"
2317 [(set_attr "type" "*,*,compare,compare")])
2319 ;; Note to set cr's other than cr0 we do the and immediate and then
2320 ;; the test again -- this avoids a mfcr which on the higher end
2321 ;; machines causes an execution serialization
2323 (define_insn "*andsi3_internal2"
2324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2327 (const_int 0)))
2328 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2329 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2330 "TARGET_32BIT"
2331 "@
2332 and. %3,%1,%2
2333 {andil.|andi.} %3,%1,%b2
2334 {andiu.|andis.} %3,%1,%u2
2335 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2336 #
2337 #
2338 #
2339 #"
2340 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2341 (set_attr "length" "4,4,4,4,8,8,8,8")])
2343 (define_insn "*andsi3_internal3"
2344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2345 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2346 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2347 (const_int 0)))
2348 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2349 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2350 "TARGET_64BIT"
2351 "@
2352 #
2353 {andil.|andi.} %3,%1,%b2
2354 {andiu.|andis.} %3,%1,%u2
2355 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2356 #
2357 #
2358 #
2359 #"
2360 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2361 (set_attr "length" "8,4,4,4,8,8,8,8")])
2363 (define_split
2364 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2365 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2366 (match_operand:GPR 2 "and_operand" ""))
2367 (const_int 0)))
2368 (clobber (match_scratch:GPR 3 ""))
2369 (clobber (match_scratch:CC 4 ""))]
2370 "reload_completed"
2371 [(parallel [(set (match_dup 3)
2372 (and:<MODE> (match_dup 1)
2373 (match_dup 2)))
2374 (clobber (match_dup 4))])
2375 (set (match_dup 0)
2376 (compare:CC (match_dup 3)
2377 (const_int 0)))]
2378 "")
2380 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2381 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2383 (define_split
2384 [(set (match_operand:CC 0 "cc_reg_operand" "")
2385 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2386 (match_operand:SI 2 "gpc_reg_operand" ""))
2387 (const_int 0)))
2388 (clobber (match_scratch:SI 3 ""))
2389 (clobber (match_scratch:CC 4 ""))]
2390 "TARGET_POWERPC64 && reload_completed"
2391 [(parallel [(set (match_dup 3)
2392 (and:SI (match_dup 1)
2393 (match_dup 2)))
2394 (clobber (match_dup 4))])
2395 (set (match_dup 0)
2396 (compare:CC (match_dup 3)
2397 (const_int 0)))]
2398 "")
2400 (define_insn "*andsi3_internal4"
2401 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2402 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2403 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2404 (const_int 0)))
2405 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2406 (and:SI (match_dup 1)
2407 (match_dup 2)))
2408 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2409 "TARGET_32BIT"
2410 "@
2411 and. %0,%1,%2
2412 {andil.|andi.} %0,%1,%b2
2413 {andiu.|andis.} %0,%1,%u2
2414 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2415 #
2416 #
2417 #
2418 #"
2419 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2420 (set_attr "length" "4,4,4,4,8,8,8,8")])
2422 (define_insn "*andsi3_internal5"
2423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2424 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2425 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2426 (const_int 0)))
2427 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2428 (and:SI (match_dup 1)
2429 (match_dup 2)))
2430 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2431 "TARGET_64BIT"
2432 "@
2433 #
2434 {andil.|andi.} %0,%1,%b2
2435 {andiu.|andis.} %0,%1,%u2
2436 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2437 #
2438 #
2439 #
2440 #"
2441 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2442 (set_attr "length" "8,4,4,4,8,8,8,8")])
2444 (define_split
2445 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2446 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2447 (match_operand:SI 2 "and_operand" ""))
2448 (const_int 0)))
2449 (set (match_operand:SI 0 "gpc_reg_operand" "")
2450 (and:SI (match_dup 1)
2451 (match_dup 2)))
2452 (clobber (match_scratch:CC 4 ""))]
2453 "reload_completed"
2454 [(parallel [(set (match_dup 0)
2455 (and:SI (match_dup 1)
2456 (match_dup 2)))
2457 (clobber (match_dup 4))])
2458 (set (match_dup 3)
2459 (compare:CC (match_dup 0)
2460 (const_int 0)))]
2461 "")
2463 (define_split
2464 [(set (match_operand:CC 3 "cc_reg_operand" "")
2465 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2466 (match_operand:SI 2 "gpc_reg_operand" ""))
2467 (const_int 0)))
2468 (set (match_operand:SI 0 "gpc_reg_operand" "")
2469 (and:SI (match_dup 1)
2470 (match_dup 2)))
2471 (clobber (match_scratch:CC 4 ""))]
2472 "TARGET_POWERPC64 && reload_completed"
2473 [(parallel [(set (match_dup 0)
2474 (and:SI (match_dup 1)
2475 (match_dup 2)))
2476 (clobber (match_dup 4))])
2477 (set (match_dup 3)
2478 (compare:CC (match_dup 0)
2479 (const_int 0)))]
2480 "")
2482 ;; Handle the PowerPC64 rlwinm corner case
2484 (define_insn_and_split "*andsi3_internal6"
2485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2486 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2487 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2488 "TARGET_POWERPC64"
2489 "#"
2490 "TARGET_POWERPC64"
2491 [(set (match_dup 0)
2492 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2493 (match_dup 4)))
2494 (set (match_dup 0)
2495 (rotate:SI (match_dup 0) (match_dup 5)))]
2496 "
2497 {
2498 int mb = extract_MB (operands[2]);
2499 int me = extract_ME (operands[2]);
2500 operands[3] = GEN_INT (me + 1);
2501 operands[5] = GEN_INT (32 - (me + 1));
2502 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2503 }"
2504 [(set_attr "length" "8")])
2506 (define_expand "iorsi3"
2507 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2508 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2509 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2510 ""
2511 "
2512 {
2513 if (GET_CODE (operands[2]) == CONST_INT
2514 && ! logical_operand (operands[2], SImode))
2515 {
2516 HOST_WIDE_INT value = INTVAL (operands[2]);
2517 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2518 ? operands[0] : gen_reg_rtx (SImode));
2520 emit_insn (gen_iorsi3 (tmp, operands[1],
2521 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2522 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2523 DONE;
2524 }
2525 }")
2527 (define_expand "xorsi3"
2528 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2529 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2530 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2531 ""
2532 "
2533 {
2534 if (GET_CODE (operands[2]) == CONST_INT
2535 && ! logical_operand (operands[2], SImode))
2536 {
2537 HOST_WIDE_INT value = INTVAL (operands[2]);
2538 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2539 ? operands[0] : gen_reg_rtx (SImode));
2541 emit_insn (gen_xorsi3 (tmp, operands[1],
2542 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2543 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2544 DONE;
2545 }
2546 }")
2548 (define_insn "*boolsi3_internal1"
2549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2550 (match_operator:SI 3 "boolean_or_operator"
2551 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2552 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2553 ""
2554 "@
2555 %q3 %0,%1,%2
2556 {%q3il|%q3i} %0,%1,%b2
2557 {%q3iu|%q3is} %0,%1,%u2")
2559 (define_insn "*boolsi3_internal2"
2560 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2561 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2562 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2563 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2564 (const_int 0)))
2565 (clobber (match_scratch:SI 3 "=r,r"))]
2566 "TARGET_32BIT"
2567 "@
2568 %q4. %3,%1,%2
2569 #"
2570 [(set_attr "type" "compare")
2571 (set_attr "length" "4,8")])
2573 (define_split
2574 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2575 (compare:CC (match_operator:SI 4 "boolean_operator"
2576 [(match_operand:SI 1 "gpc_reg_operand" "")
2577 (match_operand:SI 2 "gpc_reg_operand" "")])
2578 (const_int 0)))
2579 (clobber (match_scratch:SI 3 ""))]
2580 "TARGET_32BIT && reload_completed"
2581 [(set (match_dup 3) (match_dup 4))
2582 (set (match_dup 0)
2583 (compare:CC (match_dup 3)
2584 (const_int 0)))]
2585 "")
2587 (define_insn "*boolsi3_internal3"
2588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2589 (compare:CC (match_operator:SI 4 "boolean_operator"
2590 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2591 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2592 (const_int 0)))
2593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2594 (match_dup 4))]
2595 "TARGET_32BIT"
2596 "@
2597 %q4. %0,%1,%2
2598 #"
2599 [(set_attr "type" "compare")
2600 (set_attr "length" "4,8")])
2602 (define_split
2603 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2604 (compare:CC (match_operator:SI 4 "boolean_operator"
2605 [(match_operand:SI 1 "gpc_reg_operand" "")
2606 (match_operand:SI 2 "gpc_reg_operand" "")])
2607 (const_int 0)))
2608 (set (match_operand:SI 0 "gpc_reg_operand" "")
2609 (match_dup 4))]
2610 "TARGET_32BIT && reload_completed"
2611 [(set (match_dup 0) (match_dup 4))
2612 (set (match_dup 3)
2613 (compare:CC (match_dup 0)
2614 (const_int 0)))]
2615 "")
2617 ;; Split a logical operation that we can't do in one insn into two insns,
2618 ;; each of which does one 16-bit part. This is used by combine.
2620 (define_split
2621 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2622 (match_operator:SI 3 "boolean_or_operator"
2623 [(match_operand:SI 1 "gpc_reg_operand" "")
2624 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2625 ""
2626 [(set (match_dup 0) (match_dup 4))
2627 (set (match_dup 0) (match_dup 5))]
2628 "
2629 {
2630 rtx i;
2631 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2632 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2633 operands[1], i);
2634 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2635 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2636 operands[0], i);
2637 }")
2639 (define_insn "*boolcsi3_internal1"
2640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2641 (match_operator:SI 3 "boolean_operator"
2642 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2643 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2644 ""
2645 "%q3 %0,%2,%1")
2647 (define_insn "*boolcsi3_internal2"
2648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2649 (compare:CC (match_operator:SI 4 "boolean_operator"
2650 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2651 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2652 (const_int 0)))
2653 (clobber (match_scratch:SI 3 "=r,r"))]
2654 "TARGET_32BIT"
2655 "@
2656 %q4. %3,%2,%1
2657 #"
2658 [(set_attr "type" "compare")
2659 (set_attr "length" "4,8")])
2661 (define_split
2662 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2663 (compare:CC (match_operator:SI 4 "boolean_operator"
2664 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2665 (match_operand:SI 2 "gpc_reg_operand" "")])
2666 (const_int 0)))
2667 (clobber (match_scratch:SI 3 ""))]
2668 "TARGET_32BIT && reload_completed"
2669 [(set (match_dup 3) (match_dup 4))
2670 (set (match_dup 0)
2671 (compare:CC (match_dup 3)
2672 (const_int 0)))]
2673 "")
2675 (define_insn "*boolcsi3_internal3"
2676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2677 (compare:CC (match_operator:SI 4 "boolean_operator"
2678 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2679 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2680 (const_int 0)))
2681 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2682 (match_dup 4))]
2683 "TARGET_32BIT"
2684 "@
2685 %q4. %0,%2,%1
2686 #"
2687 [(set_attr "type" "compare")
2688 (set_attr "length" "4,8")])
2690 (define_split
2691 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2692 (compare:CC (match_operator:SI 4 "boolean_operator"
2693 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2694 (match_operand:SI 2 "gpc_reg_operand" "")])
2695 (const_int 0)))
2696 (set (match_operand:SI 0 "gpc_reg_operand" "")
2697 (match_dup 4))]
2698 "TARGET_32BIT && reload_completed"
2699 [(set (match_dup 0) (match_dup 4))
2700 (set (match_dup 3)
2701 (compare:CC (match_dup 0)
2702 (const_int 0)))]
2703 "")
2705 (define_insn "*boolccsi3_internal1"
2706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2707 (match_operator:SI 3 "boolean_operator"
2708 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2709 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2710 ""
2711 "%q3 %0,%1,%2")
2713 (define_insn "*boolccsi3_internal2"
2714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2715 (compare:CC (match_operator:SI 4 "boolean_operator"
2716 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2717 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2718 (const_int 0)))
2719 (clobber (match_scratch:SI 3 "=r,r"))]
2720 "TARGET_32BIT"
2721 "@
2722 %q4. %3,%1,%2
2723 #"
2724 [(set_attr "type" "compare")
2725 (set_attr "length" "4,8")])
2727 (define_split
2728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2729 (compare:CC (match_operator:SI 4 "boolean_operator"
2730 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2731 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2732 (const_int 0)))
2733 (clobber (match_scratch:SI 3 ""))]
2734 "TARGET_32BIT && reload_completed"
2735 [(set (match_dup 3) (match_dup 4))
2736 (set (match_dup 0)
2737 (compare:CC (match_dup 3)
2738 (const_int 0)))]
2739 "")
2741 (define_insn "*boolccsi3_internal3"
2742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2743 (compare:CC (match_operator:SI 4 "boolean_operator"
2744 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2745 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2746 (const_int 0)))
2747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2748 (match_dup 4))]
2749 "TARGET_32BIT"
2750 "@
2751 %q4. %0,%1,%2
2752 #"
2753 [(set_attr "type" "compare")
2754 (set_attr "length" "4,8")])
2756 (define_split
2757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2758 (compare:CC (match_operator:SI 4 "boolean_operator"
2759 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2760 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2761 (const_int 0)))
2762 (set (match_operand:SI 0 "gpc_reg_operand" "")
2763 (match_dup 4))]
2764 "TARGET_32BIT && reload_completed"
2765 [(set (match_dup 0) (match_dup 4))
2766 (set (match_dup 3)
2767 (compare:CC (match_dup 0)
2768 (const_int 0)))]
2769 "")
2771 ;; maskir insn. We need four forms because things might be in arbitrary
2772 ;; orders. Don't define forms that only set CR fields because these
2773 ;; would modify an input register.
2775 (define_insn "*maskir_internal1"
2776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2777 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2778 (match_operand:SI 1 "gpc_reg_operand" "0"))
2779 (and:SI (match_dup 2)
2780 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2781 "TARGET_POWER"
2782 "maskir %0,%3,%2")
2784 (define_insn "*maskir_internal2"
2785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2786 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2787 (match_operand:SI 1 "gpc_reg_operand" "0"))
2788 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2789 (match_dup 2))))]
2790 "TARGET_POWER"
2791 "maskir %0,%3,%2")
2793 (define_insn "*maskir_internal3"
2794 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2795 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2796 (match_operand:SI 3 "gpc_reg_operand" "r"))
2797 (and:SI (not:SI (match_dup 2))
2798 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2799 "TARGET_POWER"
2800 "maskir %0,%3,%2")
2802 (define_insn "*maskir_internal4"
2803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2804 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2805 (match_operand:SI 2 "gpc_reg_operand" "r"))
2806 (and:SI (not:SI (match_dup 2))
2807 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2808 "TARGET_POWER"
2809 "maskir %0,%3,%2")
2811 (define_insn "*maskir_internal5"
2812 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2813 (compare:CC
2814 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2815 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2816 (and:SI (match_dup 2)
2817 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2818 (const_int 0)))
2819 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2820 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2821 (and:SI (match_dup 2) (match_dup 3))))]
2822 "TARGET_POWER"
2823 "@
2824 maskir. %0,%3,%2
2825 #"
2826 [(set_attr "type" "compare")
2827 (set_attr "length" "4,8")])
2829 (define_split
2830 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2831 (compare:CC
2832 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2833 (match_operand:SI 1 "gpc_reg_operand" ""))
2834 (and:SI (match_dup 2)
2835 (match_operand:SI 3 "gpc_reg_operand" "")))
2836 (const_int 0)))
2837 (set (match_operand:SI 0 "gpc_reg_operand" "")
2838 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2839 (and:SI (match_dup 2) (match_dup 3))))]
2840 "TARGET_POWER && reload_completed"
2841 [(set (match_dup 0)
2842 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2843 (and:SI (match_dup 2) (match_dup 3))))
2844 (set (match_dup 4)
2845 (compare:CC (match_dup 0)
2846 (const_int 0)))]
2847 "")
2849 (define_insn "*maskir_internal6"
2850 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2851 (compare:CC
2852 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2853 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2854 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2855 (match_dup 2)))
2856 (const_int 0)))
2857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2858 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2859 (and:SI (match_dup 3) (match_dup 2))))]
2860 "TARGET_POWER"
2861 "@
2862 maskir. %0,%3,%2
2863 #"
2864 [(set_attr "type" "compare")
2865 (set_attr "length" "4,8")])
2867 (define_split
2868 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2869 (compare:CC
2870 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2871 (match_operand:SI 1 "gpc_reg_operand" ""))
2872 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2873 (match_dup 2)))
2874 (const_int 0)))
2875 (set (match_operand:SI 0 "gpc_reg_operand" "")
2876 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2877 (and:SI (match_dup 3) (match_dup 2))))]
2878 "TARGET_POWER && reload_completed"
2879 [(set (match_dup 0)
2880 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2881 (and:SI (match_dup 3) (match_dup 2))))
2882 (set (match_dup 4)
2883 (compare:CC (match_dup 0)
2884 (const_int 0)))]
2885 "")
2887 (define_insn "*maskir_internal7"
2888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2889 (compare:CC
2890 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2891 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2892 (and:SI (not:SI (match_dup 2))
2893 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2894 (const_int 0)))
2895 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2896 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2897 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2898 "TARGET_POWER"
2899 "@
2900 maskir. %0,%3,%2
2901 #"
2902 [(set_attr "type" "compare")
2903 (set_attr "length" "4,8")])
2905 (define_split
2906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2907 (compare:CC
2908 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2909 (match_operand:SI 3 "gpc_reg_operand" ""))
2910 (and:SI (not:SI (match_dup 2))
2911 (match_operand:SI 1 "gpc_reg_operand" "")))
2912 (const_int 0)))
2913 (set (match_operand:SI 0 "gpc_reg_operand" "")
2914 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2915 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2916 "TARGET_POWER && reload_completed"
2917 [(set (match_dup 0)
2918 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2919 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2920 (set (match_dup 4)
2921 (compare:CC (match_dup 0)
2922 (const_int 0)))]
2923 "")
2925 (define_insn "*maskir_internal8"
2926 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2927 (compare:CC
2928 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2929 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2930 (and:SI (not:SI (match_dup 2))
2931 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2932 (const_int 0)))
2933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2934 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2935 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2936 "TARGET_POWER"
2937 "@
2938 maskir. %0,%3,%2
2939 #"
2940 [(set_attr "type" "compare")
2941 (set_attr "length" "4,8")])
2943 (define_split
2944 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2945 (compare:CC
2946 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2947 (match_operand:SI 2 "gpc_reg_operand" ""))
2948 (and:SI (not:SI (match_dup 2))
2949 (match_operand:SI 1 "gpc_reg_operand" "")))
2950 (const_int 0)))
2951 (set (match_operand:SI 0 "gpc_reg_operand" "")
2952 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2953 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2954 "TARGET_POWER && reload_completed"
2955 [(set (match_dup 0)
2956 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2957 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2958 (set (match_dup 4)
2959 (compare:CC (match_dup 0)
2960 (const_int 0)))]
2961 "")
2962 \f
2963 ;; Rotate and shift insns, in all their variants. These support shifts,
2964 ;; field inserts and extracts, and various combinations thereof.
2965 (define_expand "insv"
2966 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2967 (match_operand:SI 1 "const_int_operand" "")
2968 (match_operand:SI 2 "const_int_operand" ""))
2969 (match_operand 3 "gpc_reg_operand" ""))]
2970 ""
2971 "
2972 {
2973 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2974 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2975 compiler if the address of the structure is taken later. */
2976 if (GET_CODE (operands[0]) == SUBREG
2977 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2978 FAIL;
2980 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2981 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2982 else
2983 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2984 DONE;
2985 }")
2987 (define_insn "insvsi"
2988 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2989 (match_operand:SI 1 "const_int_operand" "i")
2990 (match_operand:SI 2 "const_int_operand" "i"))
2991 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2992 ""
2993 "*
2994 {
2995 int start = INTVAL (operands[2]) & 31;
2996 int size = INTVAL (operands[1]) & 31;
2998 operands[4] = GEN_INT (32 - start - size);
2999 operands[1] = GEN_INT (start + size - 1);
3000 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3001 }"
3002 [(set_attr "type" "insert_word")])
3004 (define_insn "*insvsi_internal1"
3005 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3006 (match_operand:SI 1 "const_int_operand" "i")
3007 (match_operand:SI 2 "const_int_operand" "i"))
3008 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3009 (match_operand:SI 4 "const_int_operand" "i")))]
3010 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3011 "*
3012 {
3013 int shift = INTVAL (operands[4]) & 31;
3014 int start = INTVAL (operands[2]) & 31;
3015 int size = INTVAL (operands[1]) & 31;
3017 operands[4] = GEN_INT (shift - start - size);
3018 operands[1] = GEN_INT (start + size - 1);
3019 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3020 }"
3021 [(set_attr "type" "insert_word")])
3023 (define_insn "*insvsi_internal2"
3024 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3025 (match_operand:SI 1 "const_int_operand" "i")
3026 (match_operand:SI 2 "const_int_operand" "i"))
3027 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3028 (match_operand:SI 4 "const_int_operand" "i")))]
3029 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3030 "*
3031 {
3032 int shift = INTVAL (operands[4]) & 31;
3033 int start = INTVAL (operands[2]) & 31;
3034 int size = INTVAL (operands[1]) & 31;
3036 operands[4] = GEN_INT (32 - shift - start - size);
3037 operands[1] = GEN_INT (start + size - 1);
3038 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3039 }"
3040 [(set_attr "type" "insert_word")])
3042 (define_insn "*insvsi_internal3"
3043 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3044 (match_operand:SI 1 "const_int_operand" "i")
3045 (match_operand:SI 2 "const_int_operand" "i"))
3046 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3047 (match_operand:SI 4 "const_int_operand" "i")))]
3048 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3049 "*
3050 {
3051 int shift = INTVAL (operands[4]) & 31;
3052 int start = INTVAL (operands[2]) & 31;
3053 int size = INTVAL (operands[1]) & 31;
3055 operands[4] = GEN_INT (32 - shift - start - size);
3056 operands[1] = GEN_INT (start + size - 1);
3057 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3058 }"
3059 [(set_attr "type" "insert_word")])
3061 (define_insn "*insvsi_internal4"
3062 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3063 (match_operand:SI 1 "const_int_operand" "i")
3064 (match_operand:SI 2 "const_int_operand" "i"))
3065 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3066 (match_operand:SI 4 "const_int_operand" "i")
3067 (match_operand:SI 5 "const_int_operand" "i")))]
3068 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3069 "*
3070 {
3071 int extract_start = INTVAL (operands[5]) & 31;
3072 int extract_size = INTVAL (operands[4]) & 31;
3073 int insert_start = INTVAL (operands[2]) & 31;
3074 int insert_size = INTVAL (operands[1]) & 31;
3076 /* Align extract field with insert field */
3077 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3078 operands[1] = GEN_INT (insert_start + insert_size - 1);
3079 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3080 }"
3081 [(set_attr "type" "insert_word")])
3083 ;; combine patterns for rlwimi
3084 (define_insn "*insvsi_internal5"
3085 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3086 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3087 (match_operand:SI 1 "mask_operand" "i"))
3088 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3089 (match_operand:SI 2 "const_int_operand" "i"))
3090 (match_operand:SI 5 "mask_operand" "i"))))]
3091 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3092 "*
3093 {
3094 int me = extract_ME(operands[5]);
3095 int mb = extract_MB(operands[5]);
3096 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3097 operands[2] = GEN_INT(mb);
3098 operands[1] = GEN_INT(me);
3099 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3100 }"
3101 [(set_attr "type" "insert_word")])
3103 (define_insn "*insvsi_internal6"
3104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3105 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3106 (match_operand:SI 2 "const_int_operand" "i"))
3107 (match_operand:SI 5 "mask_operand" "i"))
3108 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3109 (match_operand:SI 1 "mask_operand" "i"))))]
3110 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3111 "*
3112 {
3113 int me = extract_ME(operands[5]);
3114 int mb = extract_MB(operands[5]);
3115 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3116 operands[2] = GEN_INT(mb);
3117 operands[1] = GEN_INT(me);
3118 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3119 }"
3120 [(set_attr "type" "insert_word")])
3122 (define_insn "insvdi"
3123 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3124 (match_operand:SI 1 "const_int_operand" "i")
3125 (match_operand:SI 2 "const_int_operand" "i"))
3126 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3127 "TARGET_POWERPC64"
3128 "*
3129 {
3130 int start = INTVAL (operands[2]) & 63;
3131 int size = INTVAL (operands[1]) & 63;
3133 operands[1] = GEN_INT (64 - start - size);
3134 return \"rldimi %0,%3,%H1,%H2\";
3135 }")
3137 (define_insn "*insvdi_internal2"
3138 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3139 (match_operand:SI 1 "const_int_operand" "i")
3140 (match_operand:SI 2 "const_int_operand" "i"))
3141 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3142 (match_operand:SI 4 "const_int_operand" "i")))]
3143 "TARGET_POWERPC64
3144 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3145 "*
3146 {
3147 int shift = INTVAL (operands[4]) & 63;
3148 int start = (INTVAL (operands[2]) & 63) - 32;
3149 int size = INTVAL (operands[1]) & 63;
3151 operands[4] = GEN_INT (64 - shift - start - size);
3152 operands[2] = GEN_INT (start);
3153 operands[1] = GEN_INT (start + size - 1);
3154 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3155 }")
3157 (define_insn "*insvdi_internal3"
3158 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3159 (match_operand:SI 1 "const_int_operand" "i")
3160 (match_operand:SI 2 "const_int_operand" "i"))
3161 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3162 (match_operand:SI 4 "const_int_operand" "i")))]
3163 "TARGET_POWERPC64
3164 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3165 "*
3166 {
3167 int shift = INTVAL (operands[4]) & 63;
3168 int start = (INTVAL (operands[2]) & 63) - 32;
3169 int size = INTVAL (operands[1]) & 63;
3171 operands[4] = GEN_INT (64 - shift - start - size);
3172 operands[2] = GEN_INT (start);
3173 operands[1] = GEN_INT (start + size - 1);
3174 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3175 }")
3177 (define_expand "extzv"
3178 [(set (match_operand 0 "gpc_reg_operand" "")
3179 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3180 (match_operand:SI 2 "const_int_operand" "")
3181 (match_operand:SI 3 "const_int_operand" "")))]
3182 ""
3183 "
3184 {
3185 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3186 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3187 compiler if the address of the structure is taken later. */
3188 if (GET_CODE (operands[0]) == SUBREG
3189 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3190 FAIL;
3192 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3193 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3194 else
3195 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3196 DONE;
3197 }")
3199 (define_insn "extzvsi"
3200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3201 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3202 (match_operand:SI 2 "const_int_operand" "i")
3203 (match_operand:SI 3 "const_int_operand" "i")))]
3204 ""
3205 "*
3206 {
3207 int start = INTVAL (operands[3]) & 31;
3208 int size = INTVAL (operands[2]) & 31;
3210 if (start + size >= 32)
3211 operands[3] = const0_rtx;
3212 else
3213 operands[3] = GEN_INT (start + size);
3214 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3215 }")
3217 (define_insn "*extzvsi_internal1"
3218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3219 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3220 (match_operand:SI 2 "const_int_operand" "i,i")
3221 (match_operand:SI 3 "const_int_operand" "i,i"))
3222 (const_int 0)))
3223 (clobber (match_scratch:SI 4 "=r,r"))]
3224 ""
3225 "*
3226 {
3227 int start = INTVAL (operands[3]) & 31;
3228 int size = INTVAL (operands[2]) & 31;
3230 /* Force split for non-cc0 compare. */
3231 if (which_alternative == 1)
3232 return \"#\";
3234 /* If the bit-field being tested fits in the upper or lower half of a
3235 word, it is possible to use andiu. or andil. to test it. This is
3236 useful because the condition register set-use delay is smaller for
3237 andi[ul]. than for rlinm. This doesn't work when the starting bit
3238 position is 0 because the LT and GT bits may be set wrong. */
3240 if ((start > 0 && start + size <= 16) || start >= 16)
3241 {
3242 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3243 - (1 << (16 - (start & 15) - size))));
3244 if (start < 16)
3245 return \"{andiu.|andis.} %4,%1,%3\";
3246 else
3247 return \"{andil.|andi.} %4,%1,%3\";
3248 }
3250 if (start + size >= 32)
3251 operands[3] = const0_rtx;
3252 else
3253 operands[3] = GEN_INT (start + size);
3254 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3255 }"
3256 [(set_attr "type" "compare")
3257 (set_attr "length" "4,8")])
3259 (define_split
3260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3261 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3262 (match_operand:SI 2 "const_int_operand" "")
3263 (match_operand:SI 3 "const_int_operand" ""))
3264 (const_int 0)))
3265 (clobber (match_scratch:SI 4 ""))]
3266 "reload_completed"
3267 [(set (match_dup 4)
3268 (zero_extract:SI (match_dup 1) (match_dup 2)
3269 (match_dup 3)))
3270 (set (match_dup 0)
3271 (compare:CC (match_dup 4)
3272 (const_int 0)))]
3273 "")
3275 (define_insn "*extzvsi_internal2"
3276 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3277 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3278 (match_operand:SI 2 "const_int_operand" "i,i")
3279 (match_operand:SI 3 "const_int_operand" "i,i"))
3280 (const_int 0)))
3281 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3282 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3283 ""
3284 "*
3285 {
3286 int start = INTVAL (operands[3]) & 31;
3287 int size = INTVAL (operands[2]) & 31;
3289 /* Force split for non-cc0 compare. */
3290 if (which_alternative == 1)
3291 return \"#\";
3293 /* Since we are using the output value, we can't ignore any need for
3294 a shift. The bit-field must end at the LSB. */
3295 if (start >= 16 && start + size == 32)
3296 {
3297 operands[3] = GEN_INT ((1 << size) - 1);
3298 return \"{andil.|andi.} %0,%1,%3\";
3299 }
3301 if (start + size >= 32)
3302 operands[3] = const0_rtx;
3303 else
3304 operands[3] = GEN_INT (start + size);
3305 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3306 }"
3307 [(set_attr "type" "compare")
3308 (set_attr "length" "4,8")])
3310 (define_split
3311 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3312 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3313 (match_operand:SI 2 "const_int_operand" "")
3314 (match_operand:SI 3 "const_int_operand" ""))
3315 (const_int 0)))
3316 (set (match_operand:SI 0 "gpc_reg_operand" "")
3317 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3318 "reload_completed"
3319 [(set (match_dup 0)
3320 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3321 (set (match_dup 4)
3322 (compare:CC (match_dup 0)
3323 (const_int 0)))]
3324 "")
3326 (define_insn "extzvdi"
3327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3328 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3329 (match_operand:SI 2 "const_int_operand" "i")
3330 (match_operand:SI 3 "const_int_operand" "i")))]
3331 "TARGET_POWERPC64"
3332 "*
3333 {
3334 int start = INTVAL (operands[3]) & 63;
3335 int size = INTVAL (operands[2]) & 63;
3337 if (start + size >= 64)
3338 operands[3] = const0_rtx;
3339 else
3340 operands[3] = GEN_INT (start + size);
3341 operands[2] = GEN_INT (64 - size);
3342 return \"rldicl %0,%1,%3,%2\";
3343 }")
3345 (define_insn "*extzvdi_internal1"
3346 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3347 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3348 (match_operand:SI 2 "const_int_operand" "i")
3349 (match_operand:SI 3 "const_int_operand" "i"))
3350 (const_int 0)))
3351 (clobber (match_scratch:DI 4 "=r"))]
3352 "TARGET_64BIT"
3353 "*
3354 {
3355 int start = INTVAL (operands[3]) & 63;
3356 int size = INTVAL (operands[2]) & 63;
3358 if (start + size >= 64)
3359 operands[3] = const0_rtx;
3360 else
3361 operands[3] = GEN_INT (start + size);
3362 operands[2] = GEN_INT (64 - size);
3363 return \"rldicl. %4,%1,%3,%2\";
3364 }"
3365 [(set_attr "type" "compare")])
3367 (define_insn "*extzvdi_internal2"
3368 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3369 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3370 (match_operand:SI 2 "const_int_operand" "i")
3371 (match_operand:SI 3 "const_int_operand" "i"))
3372 (const_int 0)))
3373 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3374 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3375 "TARGET_64BIT"
3376 "*
3377 {
3378 int start = INTVAL (operands[3]) & 63;
3379 int size = INTVAL (operands[2]) & 63;
3381 if (start + size >= 64)
3382 operands[3] = const0_rtx;
3383 else
3384 operands[3] = GEN_INT (start + size);
3385 operands[2] = GEN_INT (64 - size);
3386 return \"rldicl. %0,%1,%3,%2\";
3387 }"
3388 [(set_attr "type" "compare")])
3390 (define_insn "rotlsi3"
3391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3392 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3393 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3394 ""
3395 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3397 (define_insn "*rotlsi3_internal2"
3398 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3399 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3400 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3401 (const_int 0)))
3402 (clobber (match_scratch:SI 3 "=r,r"))]
3403 ""
3404 "@
3405 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3406 #"
3407 [(set_attr "type" "delayed_compare")
3408 (set_attr "length" "4,8")])
3410 (define_split
3411 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3412 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3413 (match_operand:SI 2 "reg_or_cint_operand" ""))
3414 (const_int 0)))
3415 (clobber (match_scratch:SI 3 ""))]
3416 "reload_completed"
3417 [(set (match_dup 3)
3418 (rotate:SI (match_dup 1) (match_dup 2)))
3419 (set (match_dup 0)
3420 (compare:CC (match_dup 3)
3421 (const_int 0)))]
3422 "")
3424 (define_insn "*rotlsi3_internal3"
3425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3426 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3427 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3428 (const_int 0)))
3429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3430 (rotate:SI (match_dup 1) (match_dup 2)))]
3431 ""
3432 "@
3433 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3434 #"
3435 [(set_attr "type" "delayed_compare")
3436 (set_attr "length" "4,8")])
3438 (define_split
3439 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3440 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3441 (match_operand:SI 2 "reg_or_cint_operand" ""))
3442 (const_int 0)))
3443 (set (match_operand:SI 0 "gpc_reg_operand" "")
3444 (rotate:SI (match_dup 1) (match_dup 2)))]
3445 "reload_completed"
3446 [(set (match_dup 0)
3447 (rotate:SI (match_dup 1) (match_dup 2)))
3448 (set (match_dup 3)
3449 (compare:CC (match_dup 0)
3450 (const_int 0)))]
3451 "")
3453 (define_insn "*rotlsi3_internal4"
3454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3455 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3456 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3457 (match_operand:SI 3 "mask_operand" "n")))]
3458 ""
3459 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3461 (define_insn "*rotlsi3_internal5"
3462 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3463 (compare:CC (and:SI
3464 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3465 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3466 (match_operand:SI 3 "mask_operand" "n,n"))
3467 (const_int 0)))
3468 (clobber (match_scratch:SI 4 "=r,r"))]
3469 ""
3470 "@
3471 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3472 #"
3473 [(set_attr "type" "delayed_compare")
3474 (set_attr "length" "4,8")])
3476 (define_split
3477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3478 (compare:CC (and:SI
3479 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3480 (match_operand:SI 2 "reg_or_cint_operand" ""))
3481 (match_operand:SI 3 "mask_operand" ""))
3482 (const_int 0)))
3483 (clobber (match_scratch:SI 4 ""))]
3484 "reload_completed"
3485 [(set (match_dup 4)
3486 (and:SI (rotate:SI (match_dup 1)
3487 (match_dup 2))
3488 (match_dup 3)))
3489 (set (match_dup 0)
3490 (compare:CC (match_dup 4)
3491 (const_int 0)))]
3492 "")
3494 (define_insn "*rotlsi3_internal6"
3495 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3496 (compare:CC (and:SI
3497 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3498 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3499 (match_operand:SI 3 "mask_operand" "n,n"))
3500 (const_int 0)))
3501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3502 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3503 ""
3504 "@
3505 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3506 #"
3507 [(set_attr "type" "delayed_compare")
3508 (set_attr "length" "4,8")])
3510 (define_split
3511 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3512 (compare:CC (and:SI
3513 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3514 (match_operand:SI 2 "reg_or_cint_operand" ""))
3515 (match_operand:SI 3 "mask_operand" ""))
3516 (const_int 0)))
3517 (set (match_operand:SI 0 "gpc_reg_operand" "")
3518 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3519 "reload_completed"
3520 [(set (match_dup 0)
3521 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3522 (set (match_dup 4)
3523 (compare:CC (match_dup 0)
3524 (const_int 0)))]
3525 "")
3527 (define_insn "*rotlsi3_internal7"
3528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3529 (zero_extend:SI
3530 (subreg:QI
3531 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3532 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3533 ""
3534 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3536 (define_insn "*rotlsi3_internal8"
3537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3538 (compare:CC (zero_extend:SI
3539 (subreg:QI
3540 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3541 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3542 (const_int 0)))
3543 (clobber (match_scratch:SI 3 "=r,r"))]
3544 ""
3545 "@
3546 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3547 #"
3548 [(set_attr "type" "delayed_compare")
3549 (set_attr "length" "4,8")])
3551 (define_split
3552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3553 (compare:CC (zero_extend:SI
3554 (subreg:QI
3555 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3556 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3557 (const_int 0)))
3558 (clobber (match_scratch:SI 3 ""))]
3559 "reload_completed"
3560 [(set (match_dup 3)
3561 (zero_extend:SI (subreg:QI
3562 (rotate:SI (match_dup 1)
3563 (match_dup 2)) 0)))
3564 (set (match_dup 0)
3565 (compare:CC (match_dup 3)
3566 (const_int 0)))]
3567 "")
3569 (define_insn "*rotlsi3_internal9"
3570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3571 (compare:CC (zero_extend:SI
3572 (subreg:QI
3573 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3574 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3575 (const_int 0)))
3576 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3577 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3578 ""
3579 "@
3580 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3581 #"
3582 [(set_attr "type" "delayed_compare")
3583 (set_attr "length" "4,8")])
3585 (define_split
3586 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3587 (compare:CC (zero_extend:SI
3588 (subreg:QI
3589 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3590 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3591 (const_int 0)))
3592 (set (match_operand:SI 0 "gpc_reg_operand" "")
3593 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3594 "reload_completed"
3595 [(set (match_dup 0)
3596 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3597 (set (match_dup 3)
3598 (compare:CC (match_dup 0)
3599 (const_int 0)))]
3600 "")
3602 (define_insn "*rotlsi3_internal10"
3603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3604 (zero_extend:SI
3605 (subreg:HI
3606 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3607 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3608 ""
3609 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3611 (define_insn "*rotlsi3_internal11"
3612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3613 (compare:CC (zero_extend:SI
3614 (subreg:HI
3615 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3616 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3617 (const_int 0)))
3618 (clobber (match_scratch:SI 3 "=r,r"))]
3619 ""
3620 "@
3621 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3622 #"
3623 [(set_attr "type" "delayed_compare")
3624 (set_attr "length" "4,8")])
3626 (define_split
3627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3628 (compare:CC (zero_extend:SI
3629 (subreg:HI
3630 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3631 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3632 (const_int 0)))
3633 (clobber (match_scratch:SI 3 ""))]
3634 "reload_completed"
3635 [(set (match_dup 3)
3636 (zero_extend:SI (subreg:HI
3637 (rotate:SI (match_dup 1)
3638 (match_dup 2)) 0)))
3639 (set (match_dup 0)
3640 (compare:CC (match_dup 3)
3641 (const_int 0)))]
3642 "")
3644 (define_insn "*rotlsi3_internal12"
3645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3646 (compare:CC (zero_extend:SI
3647 (subreg:HI
3648 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3649 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3650 (const_int 0)))
3651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3652 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3653 ""
3654 "@
3655 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3656 #"
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,8")])
3660 (define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (zero_extend:SI
3663 (subreg:HI
3664 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3665 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3666 (const_int 0)))
3667 (set (match_operand:SI 0 "gpc_reg_operand" "")
3668 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3669 "reload_completed"
3670 [(set (match_dup 0)
3671 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3672 (set (match_dup 3)
3673 (compare:CC (match_dup 0)
3674 (const_int 0)))]
3675 "")
3677 ;; Note that we use "sle." instead of "sl." so that we can set
3678 ;; SHIFT_COUNT_TRUNCATED.
3680 (define_expand "ashlsi3"
3681 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3682 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3683 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3684 ""
3685 "
3686 {
3687 if (TARGET_POWER)
3688 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3689 else
3690 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3691 DONE;
3692 }")
3694 (define_insn "ashlsi3_power"
3695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3696 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3697 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3698 (clobber (match_scratch:SI 3 "=q,X"))]
3699 "TARGET_POWER"
3700 "@
3701 sle %0,%1,%2
3702 {sli|slwi} %0,%1,%h2")
3704 (define_insn "ashlsi3_no_power"
3705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3706 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3707 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3708 "! TARGET_POWER"
3709 "{sl|slw}%I2 %0,%1,%h2")
3711 (define_insn ""
3712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3713 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3714 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3715 (const_int 0)))
3716 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3717 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3718 "TARGET_POWER"
3719 "@
3720 sle. %3,%1,%2
3721 {sli.|slwi.} %3,%1,%h2
3722 #
3723 #"
3724 [(set_attr "type" "delayed_compare")
3725 (set_attr "length" "4,4,8,8")])
3727 (define_split
3728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3729 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3730 (match_operand:SI 2 "reg_or_cint_operand" ""))
3731 (const_int 0)))
3732 (clobber (match_scratch:SI 3 ""))
3733 (clobber (match_scratch:SI 4 ""))]
3734 "TARGET_POWER && reload_completed"
3735 [(parallel [(set (match_dup 3)
3736 (ashift:SI (match_dup 1) (match_dup 2)))
3737 (clobber (match_dup 4))])
3738 (set (match_dup 0)
3739 (compare:CC (match_dup 3)
3740 (const_int 0)))]
3741 "")
3743 (define_insn ""
3744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3745 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3746 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3747 (const_int 0)))
3748 (clobber (match_scratch:SI 3 "=r,r"))]
3749 "! TARGET_POWER && TARGET_32BIT"
3750 "@
3751 {sl|slw}%I2. %3,%1,%h2
3752 #"
3753 [(set_attr "type" "delayed_compare")
3754 (set_attr "length" "4,8")])
3756 (define_split
3757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3758 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3759 (match_operand:SI 2 "reg_or_cint_operand" ""))
3760 (const_int 0)))
3761 (clobber (match_scratch:SI 3 ""))]
3762 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3763 [(set (match_dup 3)
3764 (ashift:SI (match_dup 1) (match_dup 2)))
3765 (set (match_dup 0)
3766 (compare:CC (match_dup 3)
3767 (const_int 0)))]
3768 "")
3770 (define_insn ""
3771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3772 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3773 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3774 (const_int 0)))
3775 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3776 (ashift:SI (match_dup 1) (match_dup 2)))
3777 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3778 "TARGET_POWER"
3779 "@
3780 sle. %0,%1,%2
3781 {sli.|slwi.} %0,%1,%h2
3782 #
3783 #"
3784 [(set_attr "type" "delayed_compare")
3785 (set_attr "length" "4,4,8,8")])
3787 (define_split
3788 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3789 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3790 (match_operand:SI 2 "reg_or_cint_operand" ""))
3791 (const_int 0)))
3792 (set (match_operand:SI 0 "gpc_reg_operand" "")
3793 (ashift:SI (match_dup 1) (match_dup 2)))
3794 (clobber (match_scratch:SI 4 ""))]
3795 "TARGET_POWER && reload_completed"
3796 [(parallel [(set (match_dup 0)
3797 (ashift:SI (match_dup 1) (match_dup 2)))
3798 (clobber (match_dup 4))])
3799 (set (match_dup 3)
3800 (compare:CC (match_dup 0)
3801 (const_int 0)))]
3802 "")
3804 (define_insn ""
3805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3806 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3807 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3808 (const_int 0)))
3809 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3810 (ashift:SI (match_dup 1) (match_dup 2)))]
3811 "! TARGET_POWER && TARGET_32BIT"
3812 "@
3813 {sl|slw}%I2. %0,%1,%h2
3814 #"
3815 [(set_attr "type" "delayed_compare")
3816 (set_attr "length" "4,8")])
3818 (define_split
3819 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3820 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3821 (match_operand:SI 2 "reg_or_cint_operand" ""))
3822 (const_int 0)))
3823 (set (match_operand:SI 0 "gpc_reg_operand" "")
3824 (ashift:SI (match_dup 1) (match_dup 2)))]
3825 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3826 [(set (match_dup 0)
3827 (ashift:SI (match_dup 1) (match_dup 2)))
3828 (set (match_dup 3)
3829 (compare:CC (match_dup 0)
3830 (const_int 0)))]
3831 "")
3833 (define_insn "rlwinm"
3834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3835 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3836 (match_operand:SI 2 "const_int_operand" "i"))
3837 (match_operand:SI 3 "mask_operand" "n")))]
3838 "includes_lshift_p (operands[2], operands[3])"
3839 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3841 (define_insn ""
3842 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3843 (compare:CC
3844 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3845 (match_operand:SI 2 "const_int_operand" "i,i"))
3846 (match_operand:SI 3 "mask_operand" "n,n"))
3847 (const_int 0)))
3848 (clobber (match_scratch:SI 4 "=r,r"))]
3849 "includes_lshift_p (operands[2], operands[3])"
3850 "@
3851 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3852 #"
3853 [(set_attr "type" "delayed_compare")
3854 (set_attr "length" "4,8")])
3856 (define_split
3857 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3858 (compare:CC
3859 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3860 (match_operand:SI 2 "const_int_operand" ""))
3861 (match_operand:SI 3 "mask_operand" ""))
3862 (const_int 0)))
3863 (clobber (match_scratch:SI 4 ""))]
3864 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3865 [(set (match_dup 4)
3866 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3867 (match_dup 3)))
3868 (set (match_dup 0)
3869 (compare:CC (match_dup 4)
3870 (const_int 0)))]
3871 "")
3873 (define_insn ""
3874 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3875 (compare:CC
3876 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3877 (match_operand:SI 2 "const_int_operand" "i,i"))
3878 (match_operand:SI 3 "mask_operand" "n,n"))
3879 (const_int 0)))
3880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3881 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3882 "includes_lshift_p (operands[2], operands[3])"
3883 "@
3884 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3885 #"
3886 [(set_attr "type" "delayed_compare")
3887 (set_attr "length" "4,8")])
3889 (define_split
3890 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3891 (compare:CC
3892 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3893 (match_operand:SI 2 "const_int_operand" ""))
3894 (match_operand:SI 3 "mask_operand" ""))
3895 (const_int 0)))
3896 (set (match_operand:SI 0 "gpc_reg_operand" "")
3897 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3898 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3899 [(set (match_dup 0)
3900 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3901 (set (match_dup 4)
3902 (compare:CC (match_dup 0)
3903 (const_int 0)))]
3904 "")
3906 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3907 ;; "sli x,x,0".
3908 (define_expand "lshrsi3"
3909 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3910 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3911 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3912 ""
3913 "
3914 {
3915 if (TARGET_POWER)
3916 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3917 else
3918 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3919 DONE;
3920 }")
3922 (define_insn "lshrsi3_power"
3923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3924 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3925 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3926 (clobber (match_scratch:SI 3 "=q,X,X"))]
3927 "TARGET_POWER"
3928 "@
3929 sre %0,%1,%2
3930 mr %0,%1
3931 {s%A2i|s%A2wi} %0,%1,%h2")
3933 (define_insn "lshrsi3_no_power"
3934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3935 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3936 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3937 "! TARGET_POWER"
3938 "@
3939 mr %0,%1
3940 {sr|srw}%I2 %0,%1,%h2")
3942 (define_insn ""
3943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3944 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3945 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3946 (const_int 0)))
3947 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3948 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3949 "TARGET_POWER"
3950 "@
3951 sre. %3,%1,%2
3952 mr. %1,%1
3953 {s%A2i.|s%A2wi.} %3,%1,%h2
3954 #
3955 #
3956 #"
3957 [(set_attr "type" "delayed_compare")
3958 (set_attr "length" "4,4,4,8,8,8")])
3960 (define_split
3961 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3962 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3963 (match_operand:SI 2 "reg_or_cint_operand" ""))
3964 (const_int 0)))
3965 (clobber (match_scratch:SI 3 ""))
3966 (clobber (match_scratch:SI 4 ""))]
3967 "TARGET_POWER && reload_completed"
3968 [(parallel [(set (match_dup 3)
3969 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3970 (clobber (match_dup 4))])
3971 (set (match_dup 0)
3972 (compare:CC (match_dup 3)
3973 (const_int 0)))]
3974 "")
3976 (define_insn ""
3977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3978 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3979 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3980 (const_int 0)))
3981 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3982 "! TARGET_POWER && TARGET_32BIT"
3983 "@
3984 mr. %1,%1
3985 {sr|srw}%I2. %3,%1,%h2
3986 #
3987 #"
3988 [(set_attr "type" "delayed_compare")
3989 (set_attr "length" "4,4,8,8")])
3991 (define_split
3992 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3993 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3994 (match_operand:SI 2 "reg_or_cint_operand" ""))
3995 (const_int 0)))
3996 (clobber (match_scratch:SI 3 ""))]
3997 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3998 [(set (match_dup 3)
3999 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4000 (set (match_dup 0)
4001 (compare:CC (match_dup 3)
4002 (const_int 0)))]
4003 "")
4005 (define_insn ""
4006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4007 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4008 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4009 (const_int 0)))
4010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4011 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4012 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4013 "TARGET_POWER"
4014 "@
4015 sre. %0,%1,%2
4016 mr. %0,%1
4017 {s%A2i.|s%A2wi.} %0,%1,%h2
4018 #
4019 #
4020 #"
4021 [(set_attr "type" "delayed_compare")
4022 (set_attr "length" "4,4,4,8,8,8")])
4024 (define_split
4025 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4026 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4027 (match_operand:SI 2 "reg_or_cint_operand" ""))
4028 (const_int 0)))
4029 (set (match_operand:SI 0 "gpc_reg_operand" "")
4030 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4031 (clobber (match_scratch:SI 4 ""))]
4032 "TARGET_POWER && reload_completed"
4033 [(parallel [(set (match_dup 0)
4034 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4035 (clobber (match_dup 4))])
4036 (set (match_dup 3)
4037 (compare:CC (match_dup 0)
4038 (const_int 0)))]
4039 "")
4041 (define_insn ""
4042 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4043 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4044 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4045 (const_int 0)))
4046 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4047 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4048 "! TARGET_POWER && TARGET_32BIT"
4049 "@
4050 mr. %0,%1
4051 {sr|srw}%I2. %0,%1,%h2
4052 #
4053 #"
4054 [(set_attr "type" "delayed_compare")
4055 (set_attr "length" "4,4,8,8")])
4057 (define_split
4058 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4059 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4060 (match_operand:SI 2 "reg_or_cint_operand" ""))
4061 (const_int 0)))
4062 (set (match_operand:SI 0 "gpc_reg_operand" "")
4063 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4064 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4065 [(set (match_dup 0)
4066 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4067 (set (match_dup 3)
4068 (compare:CC (match_dup 0)
4069 (const_int 0)))]
4070 "")
4072 (define_insn ""
4073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4074 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4075 (match_operand:SI 2 "const_int_operand" "i"))
4076 (match_operand:SI 3 "mask_operand" "n")))]
4077 "includes_rshift_p (operands[2], operands[3])"
4078 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4080 (define_insn ""
4081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4082 (compare:CC
4083 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4084 (match_operand:SI 2 "const_int_operand" "i,i"))
4085 (match_operand:SI 3 "mask_operand" "n,n"))
4086 (const_int 0)))
4087 (clobber (match_scratch:SI 4 "=r,r"))]
4088 "includes_rshift_p (operands[2], operands[3])"
4089 "@
4090 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4091 #"
4092 [(set_attr "type" "delayed_compare")
4093 (set_attr "length" "4,8")])
4095 (define_split
4096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4097 (compare:CC
4098 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4099 (match_operand:SI 2 "const_int_operand" ""))
4100 (match_operand:SI 3 "mask_operand" ""))
4101 (const_int 0)))
4102 (clobber (match_scratch:SI 4 ""))]
4103 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4104 [(set (match_dup 4)
4105 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4106 (match_dup 3)))
4107 (set (match_dup 0)
4108 (compare:CC (match_dup 4)
4109 (const_int 0)))]
4110 "")
4112 (define_insn ""
4113 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4114 (compare:CC
4115 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4116 (match_operand:SI 2 "const_int_operand" "i,i"))
4117 (match_operand:SI 3 "mask_operand" "n,n"))
4118 (const_int 0)))
4119 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4120 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4121 "includes_rshift_p (operands[2], operands[3])"
4122 "@
4123 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4124 #"
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4128 (define_split
4129 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4130 (compare:CC
4131 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4132 (match_operand:SI 2 "const_int_operand" ""))
4133 (match_operand:SI 3 "mask_operand" ""))
4134 (const_int 0)))
4135 (set (match_operand:SI 0 "gpc_reg_operand" "")
4136 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4137 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4138 [(set (match_dup 0)
4139 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4140 (set (match_dup 4)
4141 (compare:CC (match_dup 0)
4142 (const_int 0)))]
4143 "")
4145 (define_insn ""
4146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4147 (zero_extend:SI
4148 (subreg:QI
4149 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4150 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4151 "includes_rshift_p (operands[2], GEN_INT (255))"
4152 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4154 (define_insn ""
4155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4156 (compare:CC
4157 (zero_extend:SI
4158 (subreg:QI
4159 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4160 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4161 (const_int 0)))
4162 (clobber (match_scratch:SI 3 "=r,r"))]
4163 "includes_rshift_p (operands[2], GEN_INT (255))"
4164 "@
4165 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4166 #"
4167 [(set_attr "type" "delayed_compare")
4168 (set_attr "length" "4,8")])
4170 (define_split
4171 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4172 (compare:CC
4173 (zero_extend:SI
4174 (subreg:QI
4175 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "const_int_operand" "")) 0))
4177 (const_int 0)))
4178 (clobber (match_scratch:SI 3 ""))]
4179 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4180 [(set (match_dup 3)
4181 (zero_extend:SI (subreg:QI
4182 (lshiftrt:SI (match_dup 1)
4183 (match_dup 2)) 0)))
4184 (set (match_dup 0)
4185 (compare:CC (match_dup 3)
4186 (const_int 0)))]
4187 "")
4189 (define_insn ""
4190 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4191 (compare:CC
4192 (zero_extend:SI
4193 (subreg:QI
4194 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4195 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4196 (const_int 0)))
4197 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4198 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4199 "includes_rshift_p (operands[2], GEN_INT (255))"
4200 "@
4201 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4202 #"
4203 [(set_attr "type" "delayed_compare")
4204 (set_attr "length" "4,8")])
4206 (define_split
4207 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4208 (compare:CC
4209 (zero_extend:SI
4210 (subreg:QI
4211 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4212 (match_operand:SI 2 "const_int_operand" "")) 0))
4213 (const_int 0)))
4214 (set (match_operand:SI 0 "gpc_reg_operand" "")
4215 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4216 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4217 [(set (match_dup 0)
4218 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4219 (set (match_dup 3)
4220 (compare:CC (match_dup 0)
4221 (const_int 0)))]
4222 "")
4224 (define_insn ""
4225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4226 (zero_extend:SI
4227 (subreg:HI
4228 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4229 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4230 "includes_rshift_p (operands[2], GEN_INT (65535))"
4231 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4233 (define_insn ""
4234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4235 (compare:CC
4236 (zero_extend:SI
4237 (subreg:HI
4238 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4239 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4240 (const_int 0)))
4241 (clobber (match_scratch:SI 3 "=r,r"))]
4242 "includes_rshift_p (operands[2], GEN_INT (65535))"
4243 "@
4244 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4245 #"
4246 [(set_attr "type" "delayed_compare")
4247 (set_attr "length" "4,8")])
4249 (define_split
4250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4251 (compare:CC
4252 (zero_extend:SI
4253 (subreg:HI
4254 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4255 (match_operand:SI 2 "const_int_operand" "")) 0))
4256 (const_int 0)))
4257 (clobber (match_scratch:SI 3 ""))]
4258 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4259 [(set (match_dup 3)
4260 (zero_extend:SI (subreg:HI
4261 (lshiftrt:SI (match_dup 1)
4262 (match_dup 2)) 0)))
4263 (set (match_dup 0)
4264 (compare:CC (match_dup 3)
4265 (const_int 0)))]
4266 "")
4268 (define_insn ""
4269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4270 (compare:CC
4271 (zero_extend:SI
4272 (subreg:HI
4273 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4274 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4275 (const_int 0)))
4276 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4277 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4278 "includes_rshift_p (operands[2], GEN_INT (65535))"
4279 "@
4280 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4281 #"
4282 [(set_attr "type" "delayed_compare")
4283 (set_attr "length" "4,8")])
4285 (define_split
4286 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4287 (compare:CC
4288 (zero_extend:SI
4289 (subreg:HI
4290 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4291 (match_operand:SI 2 "const_int_operand" "")) 0))
4292 (const_int 0)))
4293 (set (match_operand:SI 0 "gpc_reg_operand" "")
4294 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4295 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4296 [(set (match_dup 0)
4297 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4298 (set (match_dup 3)
4299 (compare:CC (match_dup 0)
4300 (const_int 0)))]
4301 "")
4303 (define_insn ""
4304 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4305 (const_int 1)
4306 (match_operand:SI 1 "gpc_reg_operand" "r"))
4307 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4308 (const_int 31)))]
4309 "TARGET_POWER"
4310 "rrib %0,%1,%2")
4312 (define_insn ""
4313 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4314 (const_int 1)
4315 (match_operand:SI 1 "gpc_reg_operand" "r"))
4316 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4317 (const_int 31)))]
4318 "TARGET_POWER"
4319 "rrib %0,%1,%2")
4321 (define_insn ""
4322 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4323 (const_int 1)
4324 (match_operand:SI 1 "gpc_reg_operand" "r"))
4325 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4326 (const_int 1)
4327 (const_int 0)))]
4328 "TARGET_POWER"
4329 "rrib %0,%1,%2")
4331 (define_expand "ashrsi3"
4332 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4333 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4334 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4335 ""
4336 "
4337 {
4338 if (TARGET_POWER)
4339 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4340 else
4341 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4342 DONE;
4343 }")
4345 (define_insn "ashrsi3_power"
4346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4347 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4348 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4349 (clobber (match_scratch:SI 3 "=q,X"))]
4350 "TARGET_POWER"
4351 "@
4352 srea %0,%1,%2
4353 {srai|srawi} %0,%1,%h2")
4355 (define_insn "ashrsi3_no_power"
4356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4357 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4358 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4359 "! TARGET_POWER"
4360 "{sra|sraw}%I2 %0,%1,%h2")
4362 (define_insn ""
4363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4364 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4365 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4366 (const_int 0)))
4367 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4368 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4369 "TARGET_POWER"
4370 "@
4371 srea. %3,%1,%2
4372 {srai.|srawi.} %3,%1,%h2
4373 #
4374 #"
4375 [(set_attr "type" "delayed_compare")
4376 (set_attr "length" "4,4,8,8")])
4378 (define_split
4379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4380 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4381 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (const_int 0)))
4383 (clobber (match_scratch:SI 3 ""))
4384 (clobber (match_scratch:SI 4 ""))]
4385 "TARGET_POWER && reload_completed"
4386 [(parallel [(set (match_dup 3)
4387 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4388 (clobber (match_dup 4))])
4389 (set (match_dup 0)
4390 (compare:CC (match_dup 3)
4391 (const_int 0)))]
4392 "")
4394 (define_insn ""
4395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4396 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4397 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4398 (const_int 0)))
4399 (clobber (match_scratch:SI 3 "=r,r"))]
4400 "! TARGET_POWER"
4401 "@
4402 {sra|sraw}%I2. %3,%1,%h2
4403 #"
4404 [(set_attr "type" "delayed_compare")
4405 (set_attr "length" "4,8")])
4407 (define_split
4408 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4409 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4410 (match_operand:SI 2 "reg_or_cint_operand" ""))
4411 (const_int 0)))
4412 (clobber (match_scratch:SI 3 ""))]
4413 "! TARGET_POWER && reload_completed"
4414 [(set (match_dup 3)
4415 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4416 (set (match_dup 0)
4417 (compare:CC (match_dup 3)
4418 (const_int 0)))]
4419 "")
4421 (define_insn ""
4422 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4423 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4424 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4425 (const_int 0)))
4426 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4427 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4428 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4429 "TARGET_POWER"
4430 "@
4431 srea. %0,%1,%2
4432 {srai.|srawi.} %0,%1,%h2
4433 #
4434 #"
4435 [(set_attr "type" "delayed_compare")
4436 (set_attr "length" "4,4,8,8")])
4438 (define_split
4439 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4440 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4441 (match_operand:SI 2 "reg_or_cint_operand" ""))
4442 (const_int 0)))
4443 (set (match_operand:SI 0 "gpc_reg_operand" "")
4444 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4445 (clobber (match_scratch:SI 4 ""))]
4446 "TARGET_POWER && reload_completed"
4447 [(parallel [(set (match_dup 0)
4448 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4449 (clobber (match_dup 4))])
4450 (set (match_dup 3)
4451 (compare:CC (match_dup 0)
4452 (const_int 0)))]
4453 "")
4455 (define_insn ""
4456 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4457 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4458 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4459 (const_int 0)))
4460 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4461 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4462 "! TARGET_POWER"
4463 "@
4464 {sra|sraw}%I2. %0,%1,%h2
4465 #"
4466 [(set_attr "type" "delayed_compare")
4467 (set_attr "length" "4,8")])
4468 \f
4469 (define_split
4470 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4471 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4472 (match_operand:SI 2 "reg_or_cint_operand" ""))
4473 (const_int 0)))
4474 (set (match_operand:SI 0 "gpc_reg_operand" "")
4475 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4476 "! TARGET_POWER && reload_completed"
4477 [(set (match_dup 0)
4478 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4479 (set (match_dup 3)
4480 (compare:CC (match_dup 0)
4481 (const_int 0)))]
4482 "")
4484 ;; Floating-point insns, excluding normal data motion.
4485 ;;
4486 ;; PowerPC has a full set of single-precision floating point instructions.
4487 ;;
4488 ;; For the POWER architecture, we pretend that we have both SFmode and
4489 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4490 ;; The only conversions we will do will be when storing to memory. In that
4491 ;; case, we will use the "frsp" instruction before storing.
4492 ;;
4493 ;; Note that when we store into a single-precision memory location, we need to
4494 ;; use the frsp insn first. If the register being stored isn't dead, we
4495 ;; need a scratch register for the frsp. But this is difficult when the store
4496 ;; is done by reload. It is not incorrect to do the frsp on the register in
4497 ;; this case, we just lose precision that we would have otherwise gotten but
4498 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4500 (define_expand "extendsfdf2"
4501 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4502 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4503 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4504 "")
4506 (define_insn_and_split "*extendsfdf2_fpr"
4507 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4508 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4509 "TARGET_HARD_FLOAT && TARGET_FPRS"
4510 "@
4511 #
4512 fmr %0,%1
4513 lfs%U1%X1 %0,%1"
4514 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4515 [(const_int 0)]
4516 {
4517 emit_note (NOTE_INSN_DELETED);
4518 DONE;
4519 }
4520 [(set_attr "type" "fp,fp,fpload")])
4522 (define_expand "truncdfsf2"
4523 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4524 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4525 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4526 "")
4528 (define_insn "*truncdfsf2_fpr"
4529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4530 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4531 "TARGET_HARD_FLOAT && TARGET_FPRS"
4532 "frsp %0,%1"
4533 [(set_attr "type" "fp")])
4535 (define_insn "aux_truncdfsf2"
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4538 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4539 "frsp %0,%1"
4540 [(set_attr "type" "fp")])
4542 (define_expand "negsf2"
4543 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4544 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4545 "TARGET_HARD_FLOAT"
4546 "")
4548 (define_insn "*negsf2"
4549 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4550 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4551 "TARGET_HARD_FLOAT && TARGET_FPRS"
4552 "fneg %0,%1"
4553 [(set_attr "type" "fp")])
4555 (define_expand "abssf2"
4556 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4557 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4558 "TARGET_HARD_FLOAT"
4559 "")
4561 (define_insn "*abssf2"
4562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4563 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4564 "TARGET_HARD_FLOAT && TARGET_FPRS"
4565 "fabs %0,%1"
4566 [(set_attr "type" "fp")])
4568 (define_insn ""
4569 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4570 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4571 "TARGET_HARD_FLOAT && TARGET_FPRS"
4572 "fnabs %0,%1"
4573 [(set_attr "type" "fp")])
4575 (define_expand "addsf3"
4576 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4577 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4578 (match_operand:SF 2 "gpc_reg_operand" "")))]
4579 "TARGET_HARD_FLOAT"
4580 "")
4582 (define_insn ""
4583 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4584 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4585 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4586 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4587 "fadds %0,%1,%2"
4588 [(set_attr "type" "fp")])
4590 (define_insn ""
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4592 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4593 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4594 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4595 "{fa|fadd} %0,%1,%2"
4596 [(set_attr "type" "fp")])
4598 (define_expand "subsf3"
4599 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4600 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4601 (match_operand:SF 2 "gpc_reg_operand" "")))]
4602 "TARGET_HARD_FLOAT"
4603 "")
4605 (define_insn ""
4606 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4607 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4608 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4609 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4610 "fsubs %0,%1,%2"
4611 [(set_attr "type" "fp")])
4613 (define_insn ""
4614 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4615 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4616 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4617 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4618 "{fs|fsub} %0,%1,%2"
4619 [(set_attr "type" "fp")])
4621 (define_expand "mulsf3"
4622 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4623 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4624 (match_operand:SF 2 "gpc_reg_operand" "")))]
4625 "TARGET_HARD_FLOAT"
4626 "")
4628 (define_insn ""
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4630 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4631 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4632 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4633 "fmuls %0,%1,%2"
4634 [(set_attr "type" "fp")])
4636 (define_insn ""
4637 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4638 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4639 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4640 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4641 "{fm|fmul} %0,%1,%2"
4642 [(set_attr "type" "dmul")])
4644 (define_insn "fres"
4645 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4646 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4647 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4648 "fres %0,%1"
4649 [(set_attr "type" "fp")])
4651 (define_expand "divsf3"
4652 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4653 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4654 (match_operand:SF 2 "gpc_reg_operand" "")))]
4655 "TARGET_HARD_FLOAT"
4656 {
4657 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4658 && flag_finite_math_only && !flag_trapping_math)
4659 {
4660 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4661 DONE;
4662 }
4663 })
4665 (define_insn ""
4666 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4667 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4668 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4669 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4670 "fdivs %0,%1,%2"
4671 [(set_attr "type" "sdiv")])
4673 (define_insn ""
4674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4675 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4676 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4677 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4678 "{fd|fdiv} %0,%1,%2"
4679 [(set_attr "type" "ddiv")])
4681 (define_insn ""
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4683 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4684 (match_operand:SF 2 "gpc_reg_operand" "f"))
4685 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4686 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4687 "fmadds %0,%1,%2,%3"
4688 [(set_attr "type" "fp")])
4690 (define_insn ""
4691 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4692 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4693 (match_operand:SF 2 "gpc_reg_operand" "f"))
4694 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4695 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4696 "{fma|fmadd} %0,%1,%2,%3"
4697 [(set_attr "type" "dmul")])
4699 (define_insn ""
4700 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4701 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4702 (match_operand:SF 2 "gpc_reg_operand" "f"))
4703 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4704 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4705 "fmsubs %0,%1,%2,%3"
4706 [(set_attr "type" "fp")])
4708 (define_insn ""
4709 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4710 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4711 (match_operand:SF 2 "gpc_reg_operand" "f"))
4712 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4713 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4714 "{fms|fmsub} %0,%1,%2,%3"
4715 [(set_attr "type" "dmul")])
4717 (define_insn ""
4718 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4719 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4720 (match_operand:SF 2 "gpc_reg_operand" "f"))
4721 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4722 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4723 && HONOR_SIGNED_ZEROS (SFmode)"
4724 "fnmadds %0,%1,%2,%3"
4725 [(set_attr "type" "fp")])
4727 (define_insn ""
4728 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4729 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4730 (match_operand:SF 2 "gpc_reg_operand" "f"))
4731 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4732 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4733 && ! HONOR_SIGNED_ZEROS (SFmode)"
4734 "fnmadds %0,%1,%2,%3"
4735 [(set_attr "type" "fp")])
4737 (define_insn ""
4738 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4739 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4740 (match_operand:SF 2 "gpc_reg_operand" "f"))
4741 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4742 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4743 "{fnma|fnmadd} %0,%1,%2,%3"
4744 [(set_attr "type" "dmul")])
4746 (define_insn ""
4747 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4748 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4749 (match_operand:SF 2 "gpc_reg_operand" "f"))
4750 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4751 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4752 && ! HONOR_SIGNED_ZEROS (SFmode)"
4753 "{fnma|fnmadd} %0,%1,%2,%3"
4754 [(set_attr "type" "dmul")])
4756 (define_insn ""
4757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4758 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4759 (match_operand:SF 2 "gpc_reg_operand" "f"))
4760 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4761 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4762 && HONOR_SIGNED_ZEROS (SFmode)"
4763 "fnmsubs %0,%1,%2,%3"
4764 [(set_attr "type" "fp")])
4766 (define_insn ""
4767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4768 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4769 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4770 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4771 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4772 && ! HONOR_SIGNED_ZEROS (SFmode)"
4773 "fnmsubs %0,%1,%2,%3"
4774 [(set_attr "type" "fp")])
4776 (define_insn ""
4777 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4778 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4779 (match_operand:SF 2 "gpc_reg_operand" "f"))
4780 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4781 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4782 "{fnms|fnmsub} %0,%1,%2,%3"
4783 [(set_attr "type" "dmul")])
4785 (define_insn ""
4786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4787 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4788 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4789 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4790 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4791 && ! HONOR_SIGNED_ZEROS (SFmode)"
4792 "{fnms|fnmsub} %0,%1,%2,%3"
4793 [(set_attr "type" "fp")])
4795 (define_expand "sqrtsf2"
4796 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4797 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4798 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4799 "")
4801 (define_insn ""
4802 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4803 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4804 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4805 "fsqrts %0,%1"
4806 [(set_attr "type" "ssqrt")])
4808 (define_insn ""
4809 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4810 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4811 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4812 "fsqrt %0,%1"
4813 [(set_attr "type" "dsqrt")])
4815 (define_expand "copysignsf3"
4816 [(set (match_dup 3)
4817 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4818 (set (match_dup 4)
4819 (neg:SF (abs:SF (match_dup 1))))
4820 (set (match_operand:SF 0 "gpc_reg_operand" "")
4821 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4822 (match_dup 5))
4823 (match_dup 3)
4824 (match_dup 4)))]
4825 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4826 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4827 {
4828 operands[3] = gen_reg_rtx (SFmode);
4829 operands[4] = gen_reg_rtx (SFmode);
4830 operands[5] = CONST0_RTX (SFmode);
4831 })
4833 (define_expand "copysigndf3"
4834 [(set (match_dup 3)
4835 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4836 (set (match_dup 4)
4837 (neg:DF (abs:DF (match_dup 1))))
4838 (set (match_operand:DF 0 "gpc_reg_operand" "")
4839 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4840 (match_dup 5))
4841 (match_dup 3)
4842 (match_dup 4)))]
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4844 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4845 {
4846 operands[3] = gen_reg_rtx (DFmode);
4847 operands[4] = gen_reg_rtx (DFmode);
4848 operands[5] = CONST0_RTX (DFmode);
4849 })
4851 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4852 ;; fsel instruction and some auxiliary computations. Then we just have a
4853 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4854 ;; combine.
4855 (define_expand "smaxsf3"
4856 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4857 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4858 (match_operand:SF 2 "gpc_reg_operand" ""))
4859 (match_dup 1)
4860 (match_dup 2)))]
4861 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4862 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4864 (define_expand "sminsf3"
4865 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4866 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4867 (match_operand:SF 2 "gpc_reg_operand" ""))
4868 (match_dup 2)
4869 (match_dup 1)))]
4870 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4871 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4873 (define_split
4874 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4875 (match_operator:SF 3 "min_max_operator"
4876 [(match_operand:SF 1 "gpc_reg_operand" "")
4877 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4878 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4879 [(const_int 0)]
4880 "
4881 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4882 operands[1], operands[2]);
4883 DONE;
4884 }")
4886 (define_expand "movsicc"
4887 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4888 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4889 (match_operand:SI 2 "gpc_reg_operand" "")
4890 (match_operand:SI 3 "gpc_reg_operand" "")))]
4891 "TARGET_ISEL"
4892 "
4893 {
4894 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4895 DONE;
4896 else
4897 FAIL;
4898 }")
4900 ;; We use the BASE_REGS for the isel input operands because, if rA is
4901 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4902 ;; because we may switch the operands and rB may end up being rA.
4903 ;;
4904 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4905 ;; leave out the mode in operand 4 and use one pattern, but reload can
4906 ;; change the mode underneath our feet and then gets confused trying
4907 ;; to reload the value.
4908 (define_insn "isel_signed"
4909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4910 (if_then_else:SI
4911 (match_operator 1 "comparison_operator"
4912 [(match_operand:CC 4 "cc_reg_operand" "y")
4913 (const_int 0)])
4914 (match_operand:SI 2 "gpc_reg_operand" "b")
4915 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4916 "TARGET_ISEL"
4917 "*
4918 { return output_isel (operands); }"
4919 [(set_attr "length" "4")])
4921 (define_insn "isel_unsigned"
4922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4923 (if_then_else:SI
4924 (match_operator 1 "comparison_operator"
4925 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4926 (const_int 0)])
4927 (match_operand:SI 2 "gpc_reg_operand" "b")
4928 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4929 "TARGET_ISEL"
4930 "*
4931 { return output_isel (operands); }"
4932 [(set_attr "length" "4")])
4934 (define_expand "movsfcc"
4935 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4936 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4937 (match_operand:SF 2 "gpc_reg_operand" "")
4938 (match_operand:SF 3 "gpc_reg_operand" "")))]
4939 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4940 "
4941 {
4942 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4943 DONE;
4944 else
4945 FAIL;
4946 }")
4948 (define_insn "*fselsfsf4"
4949 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4950 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4951 (match_operand:SF 4 "zero_fp_constant" "F"))
4952 (match_operand:SF 2 "gpc_reg_operand" "f")
4953 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4954 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4955 "fsel %0,%1,%2,%3"
4956 [(set_attr "type" "fp")])
4958 (define_insn "*fseldfsf4"
4959 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4960 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4961 (match_operand:DF 4 "zero_fp_constant" "F"))
4962 (match_operand:SF 2 "gpc_reg_operand" "f")
4963 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4964 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4965 "fsel %0,%1,%2,%3"
4966 [(set_attr "type" "fp")])
4968 (define_expand "negdf2"
4969 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4970 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4971 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4972 "")
4974 (define_insn "*negdf2_fpr"
4975 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4976 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4977 "TARGET_HARD_FLOAT && TARGET_FPRS"
4978 "fneg %0,%1"
4979 [(set_attr "type" "fp")])
4981 (define_expand "absdf2"
4982 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4983 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4984 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4985 "")
4987 (define_insn "*absdf2_fpr"
4988 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4989 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4990 "TARGET_HARD_FLOAT && TARGET_FPRS"
4991 "fabs %0,%1"
4992 [(set_attr "type" "fp")])
4994 (define_insn "*nabsdf2_fpr"
4995 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4996 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS"
4998 "fnabs %0,%1"
4999 [(set_attr "type" "fp")])
5001 (define_expand "adddf3"
5002 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5003 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5004 (match_operand:DF 2 "gpc_reg_operand" "")))]
5005 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5006 "")
5008 (define_insn "*adddf3_fpr"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5010 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5011 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5012 "TARGET_HARD_FLOAT && TARGET_FPRS"
5013 "{fa|fadd} %0,%1,%2"
5014 [(set_attr "type" "fp")])
5016 (define_expand "subdf3"
5017 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5018 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5019 (match_operand:DF 2 "gpc_reg_operand" "")))]
5020 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5021 "")
5023 (define_insn "*subdf3_fpr"
5024 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5025 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5026 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5027 "TARGET_HARD_FLOAT && TARGET_FPRS"
5028 "{fs|fsub} %0,%1,%2"
5029 [(set_attr "type" "fp")])
5031 (define_expand "muldf3"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" "")))]
5035 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5036 "")
5038 (define_insn "*muldf3_fpr"
5039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5040 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5041 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5042 "TARGET_HARD_FLOAT && TARGET_FPRS"
5043 "{fm|fmul} %0,%1,%2"
5044 [(set_attr "type" "dmul")])
5046 (define_insn "fred"
5047 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5048 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5049 "TARGET_POPCNTB && flag_finite_math_only"
5050 "fre %0,%1"
5051 [(set_attr "type" "fp")])
5053 (define_expand "divdf3"
5054 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5055 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5056 (match_operand:DF 2 "gpc_reg_operand" "")))]
5057 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5058 {
5059 if (swdiv && !optimize_size && TARGET_POPCNTB
5060 && flag_finite_math_only && !flag_trapping_math)
5061 {
5062 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5063 DONE;
5064 }
5065 })
5067 (define_insn "*divdf3_fpr"
5068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5069 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5070 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS"
5072 "{fd|fdiv} %0,%1,%2"
5073 [(set_attr "type" "ddiv")])
5075 (define_insn ""
5076 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5077 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5078 (match_operand:DF 2 "gpc_reg_operand" "f"))
5079 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5080 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5081 "{fma|fmadd} %0,%1,%2,%3"
5082 [(set_attr "type" "dmul")])
5084 (define_insn ""
5085 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5086 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5087 (match_operand:DF 2 "gpc_reg_operand" "f"))
5088 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5089 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5090 "{fms|fmsub} %0,%1,%2,%3"
5091 [(set_attr "type" "dmul")])
5093 (define_insn ""
5094 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5095 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5096 (match_operand:DF 2 "gpc_reg_operand" "f"))
5097 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5098 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5099 && HONOR_SIGNED_ZEROS (DFmode)"
5100 "{fnma|fnmadd} %0,%1,%2,%3"
5101 [(set_attr "type" "dmul")])
5103 (define_insn ""
5104 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5105 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5106 (match_operand:DF 2 "gpc_reg_operand" "f"))
5107 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5108 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5109 && ! HONOR_SIGNED_ZEROS (DFmode)"
5110 "{fnma|fnmadd} %0,%1,%2,%3"
5111 [(set_attr "type" "dmul")])
5113 (define_insn ""
5114 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5115 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5116 (match_operand:DF 2 "gpc_reg_operand" "f"))
5117 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5118 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5119 && HONOR_SIGNED_ZEROS (DFmode)"
5120 "{fnms|fnmsub} %0,%1,%2,%3"
5121 [(set_attr "type" "dmul")])
5123 (define_insn ""
5124 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5125 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5126 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5127 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5128 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5129 && ! HONOR_SIGNED_ZEROS (DFmode)"
5130 "{fnms|fnmsub} %0,%1,%2,%3"
5131 [(set_attr "type" "dmul")])
5133 (define_insn "sqrtdf2"
5134 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5135 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5136 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5137 "fsqrt %0,%1"
5138 [(set_attr "type" "dsqrt")])
5140 ;; The conditional move instructions allow us to perform max and min
5141 ;; operations even when
5143 (define_expand "smaxdf3"
5144 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5145 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5146 (match_operand:DF 2 "gpc_reg_operand" ""))
5147 (match_dup 1)
5148 (match_dup 2)))]
5149 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5150 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5152 (define_expand "smindf3"
5153 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5154 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5155 (match_operand:DF 2 "gpc_reg_operand" ""))
5156 (match_dup 2)
5157 (match_dup 1)))]
5158 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5159 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5161 (define_split
5162 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5163 (match_operator:DF 3 "min_max_operator"
5164 [(match_operand:DF 1 "gpc_reg_operand" "")
5165 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5166 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5167 [(const_int 0)]
5168 "
5169 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5170 operands[1], operands[2]);
5171 DONE;
5172 }")
5174 (define_expand "movdfcc"
5175 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5176 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5177 (match_operand:DF 2 "gpc_reg_operand" "")
5178 (match_operand:DF 3 "gpc_reg_operand" "")))]
5179 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5180 "
5181 {
5182 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5183 DONE;
5184 else
5185 FAIL;
5186 }")
5188 (define_insn "*fseldfdf4"
5189 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5190 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5191 (match_operand:DF 4 "zero_fp_constant" "F"))
5192 (match_operand:DF 2 "gpc_reg_operand" "f")
5193 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5194 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5195 "fsel %0,%1,%2,%3"
5196 [(set_attr "type" "fp")])
5198 (define_insn "*fselsfdf4"
5199 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5200 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5201 (match_operand:SF 4 "zero_fp_constant" "F"))
5202 (match_operand:DF 2 "gpc_reg_operand" "f")
5203 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5204 "TARGET_PPC_GFXOPT"
5205 "fsel %0,%1,%2,%3"
5206 [(set_attr "type" "fp")])
5207 \f
5208 ;; Conversions to and from floating-point.
5210 (define_expand "fixuns_truncsfsi2"
5211 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5212 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5213 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5214 "")
5216 (define_expand "fix_truncsfsi2"
5217 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5218 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5219 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5220 "")
5222 ; For each of these conversions, there is a define_expand, a define_insn
5223 ; with a '#' template, and a define_split (with C code). The idea is
5224 ; to allow constant folding with the template of the define_insn,
5225 ; then to have the insns split later (between sched1 and final).
5227 (define_expand "floatsidf2"
5228 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5229 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5230 (use (match_dup 2))
5231 (use (match_dup 3))
5232 (clobber (match_dup 4))
5233 (clobber (match_dup 5))
5234 (clobber (match_dup 6))])]
5235 "TARGET_HARD_FLOAT && TARGET_FPRS"
5236 "
5237 {
5238 if (TARGET_E500_DOUBLE)
5239 {
5240 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5241 DONE;
5242 }
5243 if (TARGET_POWERPC64)
5244 {
5245 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5246 rtx t1 = gen_reg_rtx (DImode);
5247 rtx t2 = gen_reg_rtx (DImode);
5248 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5249 DONE;
5250 }
5252 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5253 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5254 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5255 operands[5] = gen_reg_rtx (DFmode);
5256 operands[6] = gen_reg_rtx (SImode);
5257 }")
5259 (define_insn_and_split "*floatsidf2_internal"
5260 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5261 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5262 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5263 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5264 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5265 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5266 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5267 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5268 "#"
5269 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5270 [(pc)]
5271 "
5272 {
5273 rtx lowword, highword;
5274 gcc_assert (MEM_P (operands[4]));
5275 highword = adjust_address (operands[4], SImode, 0);
5276 lowword = adjust_address (operands[4], SImode, 4);
5277 if (! WORDS_BIG_ENDIAN)
5278 {
5279 rtx tmp;
5280 tmp = highword; highword = lowword; lowword = tmp;
5281 }
5283 emit_insn (gen_xorsi3 (operands[6], operands[1],
5284 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5285 emit_move_insn (lowword, operands[6]);
5286 emit_move_insn (highword, operands[2]);
5287 emit_move_insn (operands[5], operands[4]);
5288 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5289 DONE;
5290 }"
5291 [(set_attr "length" "24")])
5293 (define_expand "floatunssisf2"
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5295 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5296 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5297 "")
5299 (define_expand "floatunssidf2"
5300 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5301 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5302 (use (match_dup 2))
5303 (use (match_dup 3))
5304 (clobber (match_dup 4))
5305 (clobber (match_dup 5))])]
5306 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5307 "
5308 {
5309 if (TARGET_E500_DOUBLE)
5310 {
5311 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5312 DONE;
5313 }
5314 if (TARGET_POWERPC64)
5315 {
5316 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5317 rtx t1 = gen_reg_rtx (DImode);
5318 rtx t2 = gen_reg_rtx (DImode);
5319 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5320 t1, t2));
5321 DONE;
5322 }
5324 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5325 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5326 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5327 operands[5] = gen_reg_rtx (DFmode);
5328 }")
5330 (define_insn_and_split "*floatunssidf2_internal"
5331 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5332 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5333 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5334 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5335 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5336 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5337 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5338 "#"
5339 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5340 [(pc)]
5341 "
5342 {
5343 rtx lowword, highword;
5344 gcc_assert (MEM_P (operands[4]));
5345 highword = adjust_address (operands[4], SImode, 0);
5346 lowword = adjust_address (operands[4], SImode, 4);
5347 if (! WORDS_BIG_ENDIAN)
5348 {
5349 rtx tmp;
5350 tmp = highword; highword = lowword; lowword = tmp;
5351 }
5353 emit_move_insn (lowword, operands[1]);
5354 emit_move_insn (highword, operands[2]);
5355 emit_move_insn (operands[5], operands[4]);
5356 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5357 DONE;
5358 }"
5359 [(set_attr "length" "20")])
5361 (define_expand "fix_truncdfsi2"
5362 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5363 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5364 (clobber (match_dup 2))
5365 (clobber (match_dup 3))])]
5366 "(TARGET_POWER2 || TARGET_POWERPC)
5367 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5368 "
5369 {
5370 if (TARGET_E500_DOUBLE)
5371 {
5372 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5373 DONE;
5374 }
5375 operands[2] = gen_reg_rtx (DImode);
5376 if (TARGET_PPC_GFXOPT)
5377 {
5378 rtx orig_dest = operands[0];
5379 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5380 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5381 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5382 operands[2]));
5383 if (operands[0] != orig_dest)
5384 emit_move_insn (orig_dest, operands[0]);
5385 DONE;
5386 }
5387 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5388 }")
5390 (define_insn_and_split "*fix_truncdfsi2_internal"
5391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5392 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5393 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5394 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5395 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5396 "#"
5397 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5398 [(pc)]
5399 "
5400 {
5401 rtx lowword;
5402 gcc_assert (MEM_P (operands[3]));
5403 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5405 emit_insn (gen_fctiwz (operands[2], operands[1]));
5406 emit_move_insn (operands[3], operands[2]);
5407 emit_move_insn (operands[0], lowword);
5408 DONE;
5409 }"
5410 [(set_attr "length" "16")])
5412 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5413 [(set (match_operand:SI 0 "memory_operand" "=Z")
5414 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5415 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5416 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5417 && TARGET_PPC_GFXOPT"
5418 "#"
5419 "&& 1"
5420 [(pc)]
5421 "
5422 {
5423 emit_insn (gen_fctiwz (operands[2], operands[1]));
5424 emit_insn (gen_stfiwx (operands[0], operands[2]));
5425 DONE;
5426 }"
5427 [(set_attr "length" "16")])
5429 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5430 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5431 ; because the first makes it clear that operand 0 is not live
5432 ; before the instruction.
5433 (define_insn "fctiwz"
5434 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5435 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5436 UNSPEC_FCTIWZ))]
5437 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5438 "{fcirz|fctiwz} %0,%1"
5439 [(set_attr "type" "fp")])
5441 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5442 (define_insn "stfiwx"
5443 [(set (match_operand:SI 0 "memory_operand" "=Z")
5444 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5445 UNSPEC_STFIWX))]
5446 "TARGET_PPC_GFXOPT"
5447 "stfiwx %1,%y0"
5448 [(set_attr "type" "fpstore")])
5450 (define_expand "floatsisf2"
5451 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5452 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5453 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5454 "")
5456 (define_insn "floatdidf2"
5457 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5458 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5459 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5460 "fcfid %0,%1"
5461 [(set_attr "type" "fp")])
5463 (define_insn_and_split "floatsidf_ppc64"
5464 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5465 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5466 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5467 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5468 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5469 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5470 "#"
5471 "&& 1"
5472 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5473 (set (match_dup 2) (match_dup 3))
5474 (set (match_dup 4) (match_dup 2))
5475 (set (match_dup 0) (float:DF (match_dup 4)))]
5476 "")
5478 (define_insn_and_split "floatunssidf_ppc64"
5479 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5480 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5481 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5482 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5483 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5484 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5485 "#"
5486 "&& 1"
5487 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5488 (set (match_dup 2) (match_dup 3))
5489 (set (match_dup 4) (match_dup 2))
5490 (set (match_dup 0) (float:DF (match_dup 4)))]
5491 "")
5493 (define_insn "fix_truncdfdi2"
5494 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5495 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5496 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5497 "fctidz %0,%1"
5498 [(set_attr "type" "fp")])
5500 (define_expand "floatdisf2"
5501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5502 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5503 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5504 "
5505 {
5506 rtx val = operands[1];
5507 if (!flag_unsafe_math_optimizations)
5508 {
5509 rtx label = gen_label_rtx ();
5510 val = gen_reg_rtx (DImode);
5511 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5512 emit_label (label);
5513 }
5514 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5515 DONE;
5516 }")
5518 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5519 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5520 ;; from double rounding.
5521 (define_insn_and_split "floatdisf2_internal1"
5522 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5523 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5524 (clobber (match_scratch:DF 2 "=f"))]
5525 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5526 "#"
5527 "&& reload_completed"
5528 [(set (match_dup 2)
5529 (float:DF (match_dup 1)))
5530 (set (match_dup 0)
5531 (float_truncate:SF (match_dup 2)))]
5532 "")
5534 ;; Twiddles bits to avoid double rounding.
5535 ;; Bits that might be truncated when converting to DFmode are replaced
5536 ;; by a bit that won't be lost at that stage, but is below the SFmode
5537 ;; rounding position.
5538 (define_expand "floatdisf2_internal2"
5539 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5540 (const_int 53)))
5541 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5542 (const_int 2047)))
5543 (clobber (scratch:CC))])
5544 (set (match_dup 3) (plus:DI (match_dup 3)
5545 (const_int 1)))
5546 (set (match_dup 0) (plus:DI (match_dup 0)
5547 (const_int 2047)))
5548 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5549 (const_int 3)))
5550 (set (match_dup 0) (ior:DI (match_dup 0)
5551 (match_dup 1)))
5552 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5553 (const_int -2048)))
5554 (clobber (scratch:CC))])
5555 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5556 (label_ref (match_operand:DI 2 "" ""))
5557 (pc)))
5558 (set (match_dup 0) (match_dup 1))]
5559 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5560 "
5561 {
5562 operands[3] = gen_reg_rtx (DImode);
5563 operands[4] = gen_reg_rtx (CCUNSmode);
5564 }")
5565 \f
5566 ;; Define the DImode operations that can be done in a small number
5567 ;; of instructions. The & constraints are to prevent the register
5568 ;; allocator from allocating registers that overlap with the inputs
5569 ;; (for example, having an input in 7,8 and an output in 6,7). We
5570 ;; also allow for the output being the same as one of the inputs.
5572 (define_insn "*adddi3_noppc64"
5573 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5574 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5575 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5576 "! TARGET_POWERPC64"
5577 "*
5578 {
5579 if (WORDS_BIG_ENDIAN)
5580 return (GET_CODE (operands[2])) != CONST_INT
5581 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5582 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5583 else
5584 return (GET_CODE (operands[2])) != CONST_INT
5585 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5586 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5587 }"
5588 [(set_attr "type" "two")
5589 (set_attr "length" "8")])
5591 (define_insn "*subdi3_noppc64"
5592 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5593 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5594 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5595 "! TARGET_POWERPC64"
5596 "*
5597 {
5598 if (WORDS_BIG_ENDIAN)
5599 return (GET_CODE (operands[1]) != CONST_INT)
5600 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5601 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5602 else
5603 return (GET_CODE (operands[1]) != CONST_INT)
5604 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5605 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5606 }"
5607 [(set_attr "type" "two")
5608 (set_attr "length" "8")])
5610 (define_insn "*negdi2_noppc64"
5611 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5612 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5613 "! TARGET_POWERPC64"
5614 "*
5615 {
5616 return (WORDS_BIG_ENDIAN)
5617 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5618 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5619 }"
5620 [(set_attr "type" "two")
5621 (set_attr "length" "8")])
5623 (define_expand "mulsidi3"
5624 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5625 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5626 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5627 "! TARGET_POWERPC64"
5628 "
5629 {
5630 if (! TARGET_POWER && ! TARGET_POWERPC)
5631 {
5632 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5633 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5634 emit_insn (gen_mull_call ());
5635 if (WORDS_BIG_ENDIAN)
5636 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5637 else
5638 {
5639 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5640 gen_rtx_REG (SImode, 3));
5641 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5642 gen_rtx_REG (SImode, 4));
5643 }
5644 DONE;
5645 }
5646 else if (TARGET_POWER)
5647 {
5648 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5649 DONE;
5650 }
5651 }")
5653 (define_insn "mulsidi3_mq"
5654 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5655 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5656 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5657 (clobber (match_scratch:SI 3 "=q"))]
5658 "TARGET_POWER"
5659 "mul %0,%1,%2\;mfmq %L0"
5660 [(set_attr "type" "imul")
5661 (set_attr "length" "8")])
5663 (define_insn "*mulsidi3_no_mq"
5664 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5665 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5666 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5667 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5668 "*
5669 {
5670 return (WORDS_BIG_ENDIAN)
5671 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5672 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5673 }"
5674 [(set_attr "type" "imul")
5675 (set_attr "length" "8")])
5677 (define_split
5678 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5679 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5680 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5681 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5682 [(set (match_dup 3)
5683 (truncate:SI
5684 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5685 (sign_extend:DI (match_dup 2)))
5686 (const_int 32))))
5687 (set (match_dup 4)
5688 (mult:SI (match_dup 1)
5689 (match_dup 2)))]
5690 "
5691 {
5692 int endian = (WORDS_BIG_ENDIAN == 0);
5693 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5694 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5695 }")
5697 (define_expand "umulsidi3"
5698 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5699 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5700 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5701 "TARGET_POWERPC && ! TARGET_POWERPC64"
5702 "
5703 {
5704 if (TARGET_POWER)
5705 {
5706 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5707 DONE;
5708 }
5709 }")
5711 (define_insn "umulsidi3_mq"
5712 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5713 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5714 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5715 (clobber (match_scratch:SI 3 "=q"))]
5716 "TARGET_POWERPC && TARGET_POWER"
5717 "*
5718 {
5719 return (WORDS_BIG_ENDIAN)
5720 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5721 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5722 }"
5723 [(set_attr "type" "imul")
5724 (set_attr "length" "8")])
5726 (define_insn "*umulsidi3_no_mq"
5727 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5728 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5729 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5730 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5731 "*
5732 {
5733 return (WORDS_BIG_ENDIAN)
5734 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5735 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5736 }"
5737 [(set_attr "type" "imul")
5738 (set_attr "length" "8")])
5740 (define_split
5741 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5742 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5743 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5744 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5745 [(set (match_dup 3)
5746 (truncate:SI
5747 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5748 (zero_extend:DI (match_dup 2)))
5749 (const_int 32))))
5750 (set (match_dup 4)
5751 (mult:SI (match_dup 1)
5752 (match_dup 2)))]
5753 "
5754 {
5755 int endian = (WORDS_BIG_ENDIAN == 0);
5756 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5757 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5758 }")
5760 (define_expand "smulsi3_highpart"
5761 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5762 (truncate:SI
5763 (lshiftrt:DI (mult:DI (sign_extend:DI
5764 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5765 (sign_extend:DI
5766 (match_operand:SI 2 "gpc_reg_operand" "r")))
5767 (const_int 32))))]
5768 ""
5769 "
5770 {
5771 if (! TARGET_POWER && ! TARGET_POWERPC)
5772 {
5773 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5774 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5775 emit_insn (gen_mulh_call ());
5776 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5777 DONE;
5778 }
5779 else if (TARGET_POWER)
5780 {
5781 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5782 DONE;
5783 }
5784 }")
5786 (define_insn "smulsi3_highpart_mq"
5787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5788 (truncate:SI
5789 (lshiftrt:DI (mult:DI (sign_extend:DI
5790 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5791 (sign_extend:DI
5792 (match_operand:SI 2 "gpc_reg_operand" "r")))
5793 (const_int 32))))
5794 (clobber (match_scratch:SI 3 "=q"))]
5795 "TARGET_POWER"
5796 "mul %0,%1,%2"
5797 [(set_attr "type" "imul")])
5799 (define_insn "*smulsi3_highpart_no_mq"
5800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5801 (truncate:SI
5802 (lshiftrt:DI (mult:DI (sign_extend:DI
5803 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5804 (sign_extend:DI
5805 (match_operand:SI 2 "gpc_reg_operand" "r")))
5806 (const_int 32))))]
5807 "TARGET_POWERPC && ! TARGET_POWER"
5808 "mulhw %0,%1,%2"
5809 [(set_attr "type" "imul")])
5811 (define_expand "umulsi3_highpart"
5812 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5813 (truncate:SI
5814 (lshiftrt:DI (mult:DI (zero_extend:DI
5815 (match_operand:SI 1 "gpc_reg_operand" ""))
5816 (zero_extend:DI
5817 (match_operand:SI 2 "gpc_reg_operand" "")))
5818 (const_int 32))))]
5819 "TARGET_POWERPC"
5820 "
5821 {
5822 if (TARGET_POWER)
5823 {
5824 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5825 DONE;
5826 }
5827 }")
5829 (define_insn "umulsi3_highpart_mq"
5830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5831 (truncate:SI
5832 (lshiftrt:DI (mult:DI (zero_extend:DI
5833 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5834 (zero_extend:DI
5835 (match_operand:SI 2 "gpc_reg_operand" "r")))
5836 (const_int 32))))
5837 (clobber (match_scratch:SI 3 "=q"))]
5838 "TARGET_POWERPC && TARGET_POWER"
5839 "mulhwu %0,%1,%2"
5840 [(set_attr "type" "imul")])
5842 (define_insn "*umulsi3_highpart_no_mq"
5843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5844 (truncate:SI
5845 (lshiftrt:DI (mult:DI (zero_extend:DI
5846 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5847 (zero_extend:DI
5848 (match_operand:SI 2 "gpc_reg_operand" "r")))
5849 (const_int 32))))]
5850 "TARGET_POWERPC && ! TARGET_POWER"
5851 "mulhwu %0,%1,%2"
5852 [(set_attr "type" "imul")])
5854 ;; If operands 0 and 2 are in the same register, we have a problem. But
5855 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5856 ;; why we have the strange constraints below.
5857 (define_insn "ashldi3_power"
5858 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5859 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5860 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5861 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5862 "TARGET_POWER"
5863 "@
5864 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5865 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5866 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5867 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5868 [(set_attr "length" "8")])
5870 (define_insn "lshrdi3_power"
5871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5872 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5873 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5874 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5875 "TARGET_POWER"
5876 "@
5877 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5878 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5879 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5880 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5881 [(set_attr "length" "8")])
5883 ;; Shift by a variable amount is too complex to be worth open-coding. We
5884 ;; just handle shifts by constants.
5885 (define_insn "ashrdi3_power"
5886 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5887 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5888 (match_operand:SI 2 "const_int_operand" "M,i")))
5889 (clobber (match_scratch:SI 3 "=X,q"))]
5890 "TARGET_POWER"
5891 "@
5892 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5893 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5894 [(set_attr "length" "8")])
5896 (define_insn "ashrdi3_no_power"
5897 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5898 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5899 (match_operand:SI 2 "const_int_operand" "M,i")))]
5900 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5901 "@
5902 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5903 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5904 [(set_attr "type" "two,three")
5905 (set_attr "length" "8,12")])
5907 (define_insn "*ashrdisi3_noppc64"
5908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5909 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5910 (const_int 32)) 4))]
5911 "TARGET_32BIT && !TARGET_POWERPC64"
5912 "*
5913 {
5914 if (REGNO (operands[0]) == REGNO (operands[1]))
5915 return \"\";
5916 else
5917 return \"mr %0,%1\";
5918 }"
5919 [(set_attr "length" "4")])
5921 \f
5922 ;; PowerPC64 DImode operations.
5924 (define_insn_and_split "absdi2"
5925 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5926 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5927 (clobber (match_scratch:DI 2 "=&r,&r"))]
5928 "TARGET_POWERPC64"
5929 "#"
5930 "&& reload_completed"
5931 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5932 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5933 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5934 "")
5936 (define_insn_and_split "*nabsdi2"
5937 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5938 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5939 (clobber (match_scratch:DI 2 "=&r,&r"))]
5940 "TARGET_POWERPC64"
5941 "#"
5942 "&& reload_completed"
5943 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5944 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5945 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5946 "")
5948 (define_insn "muldi3"
5949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5950 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5951 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5952 "TARGET_POWERPC64"
5953 "mulld %0,%1,%2"
5954 [(set_attr "type" "lmul")])
5956 (define_insn "*muldi3_internal1"
5957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5958 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5959 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5960 (const_int 0)))
5961 (clobber (match_scratch:DI 3 "=r,r"))]
5962 "TARGET_POWERPC64"
5963 "@
5964 mulld. %3,%1,%2
5965 #"
5966 [(set_attr "type" "lmul_compare")
5967 (set_attr "length" "4,8")])
5969 (define_split
5970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5971 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5972 (match_operand:DI 2 "gpc_reg_operand" ""))
5973 (const_int 0)))
5974 (clobber (match_scratch:DI 3 ""))]
5975 "TARGET_POWERPC64 && reload_completed"
5976 [(set (match_dup 3)
5977 (mult:DI (match_dup 1) (match_dup 2)))
5978 (set (match_dup 0)
5979 (compare:CC (match_dup 3)
5980 (const_int 0)))]
5981 "")
5983 (define_insn "*muldi3_internal2"
5984 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5985 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5986 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5987 (const_int 0)))
5988 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5989 (mult:DI (match_dup 1) (match_dup 2)))]
5990 "TARGET_POWERPC64"
5991 "@
5992 mulld. %0,%1,%2
5993 #"
5994 [(set_attr "type" "lmul_compare")
5995 (set_attr "length" "4,8")])
5997 (define_split
5998 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5999 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6000 (match_operand:DI 2 "gpc_reg_operand" ""))
6001 (const_int 0)))
6002 (set (match_operand:DI 0 "gpc_reg_operand" "")
6003 (mult:DI (match_dup 1) (match_dup 2)))]
6004 "TARGET_POWERPC64 && reload_completed"
6005 [(set (match_dup 0)
6006 (mult:DI (match_dup 1) (match_dup 2)))
6007 (set (match_dup 3)
6008 (compare:CC (match_dup 0)
6009 (const_int 0)))]
6010 "")
6012 (define_insn "smuldi3_highpart"
6013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6014 (truncate:DI
6015 (lshiftrt:TI (mult:TI (sign_extend:TI
6016 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6017 (sign_extend:TI
6018 (match_operand:DI 2 "gpc_reg_operand" "r")))
6019 (const_int 64))))]
6020 "TARGET_POWERPC64"
6021 "mulhd %0,%1,%2"
6022 [(set_attr "type" "lmul")])
6024 (define_insn "umuldi3_highpart"
6025 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6026 (truncate:DI
6027 (lshiftrt:TI (mult:TI (zero_extend:TI
6028 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6029 (zero_extend:TI
6030 (match_operand:DI 2 "gpc_reg_operand" "r")))
6031 (const_int 64))))]
6032 "TARGET_POWERPC64"
6033 "mulhdu %0,%1,%2"
6034 [(set_attr "type" "lmul")])
6036 (define_insn "rotldi3"
6037 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6038 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6039 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6040 "TARGET_POWERPC64"
6041 "rld%I2cl %0,%1,%H2,0")
6043 (define_insn "*rotldi3_internal2"
6044 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6045 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6046 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6047 (const_int 0)))
6048 (clobber (match_scratch:DI 3 "=r,r"))]
6049 "TARGET_64BIT"
6050 "@
6051 rld%I2cl. %3,%1,%H2,0
6052 #"
6053 [(set_attr "type" "delayed_compare")
6054 (set_attr "length" "4,8")])
6056 (define_split
6057 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6058 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6059 (match_operand:DI 2 "reg_or_cint_operand" ""))
6060 (const_int 0)))
6061 (clobber (match_scratch:DI 3 ""))]
6062 "TARGET_POWERPC64 && reload_completed"
6063 [(set (match_dup 3)
6064 (rotate:DI (match_dup 1) (match_dup 2)))
6065 (set (match_dup 0)
6066 (compare:CC (match_dup 3)
6067 (const_int 0)))]
6068 "")
6070 (define_insn "*rotldi3_internal3"
6071 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6072 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6073 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6074 (const_int 0)))
6075 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6076 (rotate:DI (match_dup 1) (match_dup 2)))]
6077 "TARGET_64BIT"
6078 "@
6079 rld%I2cl. %0,%1,%H2,0
6080 #"
6081 [(set_attr "type" "delayed_compare")
6082 (set_attr "length" "4,8")])
6084 (define_split
6085 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6086 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6087 (match_operand:DI 2 "reg_or_cint_operand" ""))
6088 (const_int 0)))
6089 (set (match_operand:DI 0 "gpc_reg_operand" "")
6090 (rotate:DI (match_dup 1) (match_dup 2)))]
6091 "TARGET_POWERPC64 && reload_completed"
6092 [(set (match_dup 0)
6093 (rotate:DI (match_dup 1) (match_dup 2)))
6094 (set (match_dup 3)
6095 (compare:CC (match_dup 0)
6096 (const_int 0)))]
6097 "")
6099 (define_insn "*rotldi3_internal4"
6100 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6101 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6102 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6103 (match_operand:DI 3 "mask_operand" "n")))]
6104 "TARGET_POWERPC64"
6105 "rld%I2c%B3 %0,%1,%H2,%S3")
6107 (define_insn "*rotldi3_internal5"
6108 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6109 (compare:CC (and:DI
6110 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6111 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6112 (match_operand:DI 3 "mask_operand" "n,n"))
6113 (const_int 0)))
6114 (clobber (match_scratch:DI 4 "=r,r"))]
6115 "TARGET_64BIT"
6116 "@
6117 rld%I2c%B3. %4,%1,%H2,%S3
6118 #"
6119 [(set_attr "type" "delayed_compare")
6120 (set_attr "length" "4,8")])
6122 (define_split
6123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6124 (compare:CC (and:DI
6125 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6126 (match_operand:DI 2 "reg_or_cint_operand" ""))
6127 (match_operand:DI 3 "mask_operand" ""))
6128 (const_int 0)))
6129 (clobber (match_scratch:DI 4 ""))]
6130 "TARGET_POWERPC64 && reload_completed"
6131 [(set (match_dup 4)
6132 (and:DI (rotate:DI (match_dup 1)
6133 (match_dup 2))
6134 (match_dup 3)))
6135 (set (match_dup 0)
6136 (compare:CC (match_dup 4)
6137 (const_int 0)))]
6138 "")
6140 (define_insn "*rotldi3_internal6"
6141 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6142 (compare:CC (and:DI
6143 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6144 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6145 (match_operand:DI 3 "mask_operand" "n,n"))
6146 (const_int 0)))
6147 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6148 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6149 "TARGET_64BIT"
6150 "@
6151 rld%I2c%B3. %0,%1,%H2,%S3
6152 #"
6153 [(set_attr "type" "delayed_compare")
6154 (set_attr "length" "4,8")])
6156 (define_split
6157 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6158 (compare:CC (and:DI
6159 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6160 (match_operand:DI 2 "reg_or_cint_operand" ""))
6161 (match_operand:DI 3 "mask_operand" ""))
6162 (const_int 0)))
6163 (set (match_operand:DI 0 "gpc_reg_operand" "")
6164 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6165 "TARGET_POWERPC64 && reload_completed"
6166 [(set (match_dup 0)
6167 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6168 (set (match_dup 4)
6169 (compare:CC (match_dup 0)
6170 (const_int 0)))]
6171 "")
6173 (define_insn "*rotldi3_internal7"
6174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6175 (zero_extend:DI
6176 (subreg:QI
6177 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6178 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6179 "TARGET_POWERPC64"
6180 "rld%I2cl %0,%1,%H2,56")
6182 (define_insn "*rotldi3_internal8"
6183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6184 (compare:CC (zero_extend:DI
6185 (subreg:QI
6186 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6187 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6188 (const_int 0)))
6189 (clobber (match_scratch:DI 3 "=r,r"))]
6190 "TARGET_64BIT"
6191 "@
6192 rld%I2cl. %3,%1,%H2,56
6193 #"
6194 [(set_attr "type" "delayed_compare")
6195 (set_attr "length" "4,8")])
6197 (define_split
6198 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6199 (compare:CC (zero_extend:DI
6200 (subreg:QI
6201 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6202 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6203 (const_int 0)))
6204 (clobber (match_scratch:DI 3 ""))]
6205 "TARGET_POWERPC64 && reload_completed"
6206 [(set (match_dup 3)
6207 (zero_extend:DI (subreg:QI
6208 (rotate:DI (match_dup 1)
6209 (match_dup 2)) 0)))
6210 (set (match_dup 0)
6211 (compare:CC (match_dup 3)
6212 (const_int 0)))]
6213 "")
6215 (define_insn "*rotldi3_internal9"
6216 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6217 (compare:CC (zero_extend:DI
6218 (subreg:QI
6219 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6220 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6221 (const_int 0)))
6222 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6223 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6224 "TARGET_64BIT"
6225 "@
6226 rld%I2cl. %0,%1,%H2,56
6227 #"
6228 [(set_attr "type" "delayed_compare")
6229 (set_attr "length" "4,8")])
6231 (define_split
6232 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6233 (compare:CC (zero_extend:DI
6234 (subreg:QI
6235 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6236 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6237 (const_int 0)))
6238 (set (match_operand:DI 0 "gpc_reg_operand" "")
6239 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6240 "TARGET_POWERPC64 && reload_completed"
6241 [(set (match_dup 0)
6242 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6243 (set (match_dup 3)
6244 (compare:CC (match_dup 0)
6245 (const_int 0)))]
6246 "")
6248 (define_insn "*rotldi3_internal10"
6249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6250 (zero_extend:DI
6251 (subreg:HI
6252 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6253 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6254 "TARGET_POWERPC64"
6255 "rld%I2cl %0,%1,%H2,48")
6257 (define_insn "*rotldi3_internal11"
6258 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6259 (compare:CC (zero_extend:DI
6260 (subreg:HI
6261 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6262 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6263 (const_int 0)))
6264 (clobber (match_scratch:DI 3 "=r,r"))]
6265 "TARGET_64BIT"
6266 "@
6267 rld%I2cl. %3,%1,%H2,48
6268 #"
6269 [(set_attr "type" "delayed_compare")
6270 (set_attr "length" "4,8")])
6272 (define_split
6273 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6274 (compare:CC (zero_extend:DI
6275 (subreg:HI
6276 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6277 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6278 (const_int 0)))
6279 (clobber (match_scratch:DI 3 ""))]
6280 "TARGET_POWERPC64 && reload_completed"
6281 [(set (match_dup 3)
6282 (zero_extend:DI (subreg:HI
6283 (rotate:DI (match_dup 1)
6284 (match_dup 2)) 0)))
6285 (set (match_dup 0)
6286 (compare:CC (match_dup 3)
6287 (const_int 0)))]
6288 "")
6290 (define_insn "*rotldi3_internal12"
6291 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6292 (compare:CC (zero_extend:DI
6293 (subreg:HI
6294 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6295 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6296 (const_int 0)))
6297 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6298 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6299 "TARGET_64BIT"
6300 "@
6301 rld%I2cl. %0,%1,%H2,48
6302 #"
6303 [(set_attr "type" "delayed_compare")
6304 (set_attr "length" "4,8")])
6306 (define_split
6307 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6308 (compare:CC (zero_extend:DI
6309 (subreg:HI
6310 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6311 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6312 (const_int 0)))
6313 (set (match_operand:DI 0 "gpc_reg_operand" "")
6314 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6315 "TARGET_POWERPC64 && reload_completed"
6316 [(set (match_dup 0)
6317 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6318 (set (match_dup 3)
6319 (compare:CC (match_dup 0)
6320 (const_int 0)))]
6321 "")
6323 (define_insn "*rotldi3_internal13"
6324 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6325 (zero_extend:DI
6326 (subreg:SI
6327 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6328 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6329 "TARGET_POWERPC64"
6330 "rld%I2cl %0,%1,%H2,32")
6332 (define_insn "*rotldi3_internal14"
6333 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6334 (compare:CC (zero_extend:DI
6335 (subreg:SI
6336 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6337 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6338 (const_int 0)))
6339 (clobber (match_scratch:DI 3 "=r,r"))]
6340 "TARGET_64BIT"
6341 "@
6342 rld%I2cl. %3,%1,%H2,32
6343 #"
6344 [(set_attr "type" "delayed_compare")
6345 (set_attr "length" "4,8")])
6347 (define_split
6348 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6349 (compare:CC (zero_extend:DI
6350 (subreg:SI
6351 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6352 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6353 (const_int 0)))
6354 (clobber (match_scratch:DI 3 ""))]
6355 "TARGET_POWERPC64 && reload_completed"
6356 [(set (match_dup 3)
6357 (zero_extend:DI (subreg:SI
6358 (rotate:DI (match_dup 1)
6359 (match_dup 2)) 0)))
6360 (set (match_dup 0)
6361 (compare:CC (match_dup 3)
6362 (const_int 0)))]
6363 "")
6365 (define_insn "*rotldi3_internal15"
6366 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6367 (compare:CC (zero_extend:DI
6368 (subreg:SI
6369 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6370 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6371 (const_int 0)))
6372 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6373 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6374 "TARGET_64BIT"
6375 "@
6376 rld%I2cl. %0,%1,%H2,32
6377 #"
6378 [(set_attr "type" "delayed_compare")
6379 (set_attr "length" "4,8")])
6381 (define_split
6382 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6383 (compare:CC (zero_extend:DI
6384 (subreg:SI
6385 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6386 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6387 (const_int 0)))
6388 (set (match_operand:DI 0 "gpc_reg_operand" "")
6389 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6390 "TARGET_POWERPC64 && reload_completed"
6391 [(set (match_dup 0)
6392 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6393 (set (match_dup 3)
6394 (compare:CC (match_dup 0)
6395 (const_int 0)))]
6396 "")
6398 (define_expand "ashldi3"
6399 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6400 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6401 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6402 "TARGET_POWERPC64 || TARGET_POWER"
6403 "
6404 {
6405 if (TARGET_POWERPC64)
6406 ;
6407 else if (TARGET_POWER)
6408 {
6409 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6410 DONE;
6411 }
6412 else
6413 FAIL;
6414 }")
6416 (define_insn "*ashldi3_internal1"
6417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6418 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6419 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6420 "TARGET_POWERPC64"
6421 "sld%I2 %0,%1,%H2")
6423 (define_insn "*ashldi3_internal2"
6424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6425 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6426 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6427 (const_int 0)))
6428 (clobber (match_scratch:DI 3 "=r,r"))]
6429 "TARGET_64BIT"
6430 "@
6431 sld%I2. %3,%1,%H2
6432 #"
6433 [(set_attr "type" "delayed_compare")
6434 (set_attr "length" "4,8")])
6436 (define_split
6437 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6438 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6439 (match_operand:SI 2 "reg_or_cint_operand" ""))
6440 (const_int 0)))
6441 (clobber (match_scratch:DI 3 ""))]
6442 "TARGET_POWERPC64 && reload_completed"
6443 [(set (match_dup 3)
6444 (ashift:DI (match_dup 1) (match_dup 2)))
6445 (set (match_dup 0)
6446 (compare:CC (match_dup 3)
6447 (const_int 0)))]
6448 "")
6450 (define_insn "*ashldi3_internal3"
6451 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6452 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6453 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6454 (const_int 0)))
6455 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6456 (ashift:DI (match_dup 1) (match_dup 2)))]
6457 "TARGET_64BIT"
6458 "@
6459 sld%I2. %0,%1,%H2
6460 #"
6461 [(set_attr "type" "delayed_compare")
6462 (set_attr "length" "4,8")])
6464 (define_split
6465 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6466 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6467 (match_operand:SI 2 "reg_or_cint_operand" ""))
6468 (const_int 0)))
6469 (set (match_operand:DI 0 "gpc_reg_operand" "")
6470 (ashift:DI (match_dup 1) (match_dup 2)))]
6471 "TARGET_POWERPC64 && reload_completed"
6472 [(set (match_dup 0)
6473 (ashift:DI (match_dup 1) (match_dup 2)))
6474 (set (match_dup 3)
6475 (compare:CC (match_dup 0)
6476 (const_int 0)))]
6477 "")
6479 (define_insn "*ashldi3_internal4"
6480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6481 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6482 (match_operand:SI 2 "const_int_operand" "i"))
6483 (match_operand:DI 3 "const_int_operand" "n")))]
6484 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6485 "rldic %0,%1,%H2,%W3")
6487 (define_insn "ashldi3_internal5"
6488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6489 (compare:CC
6490 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6491 (match_operand:SI 2 "const_int_operand" "i,i"))
6492 (match_operand:DI 3 "const_int_operand" "n,n"))
6493 (const_int 0)))
6494 (clobber (match_scratch:DI 4 "=r,r"))]
6495 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6496 "@
6497 rldic. %4,%1,%H2,%W3
6498 #"
6499 [(set_attr "type" "delayed_compare")
6500 (set_attr "length" "4,8")])
6502 (define_split
6503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6504 (compare:CC
6505 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6506 (match_operand:SI 2 "const_int_operand" ""))
6507 (match_operand:DI 3 "const_int_operand" ""))
6508 (const_int 0)))
6509 (clobber (match_scratch:DI 4 ""))]
6510 "TARGET_POWERPC64 && reload_completed
6511 && includes_rldic_lshift_p (operands[2], operands[3])"
6512 [(set (match_dup 4)
6513 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6514 (match_dup 3)))
6515 (set (match_dup 0)
6516 (compare:CC (match_dup 4)
6517 (const_int 0)))]
6518 "")
6520 (define_insn "*ashldi3_internal6"
6521 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6522 (compare:CC
6523 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6524 (match_operand:SI 2 "const_int_operand" "i,i"))
6525 (match_operand:DI 3 "const_int_operand" "n,n"))
6526 (const_int 0)))
6527 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6528 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6529 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6530 "@
6531 rldic. %0,%1,%H2,%W3
6532 #"
6533 [(set_attr "type" "delayed_compare")
6534 (set_attr "length" "4,8")])
6536 (define_split
6537 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6538 (compare:CC
6539 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6540 (match_operand:SI 2 "const_int_operand" ""))
6541 (match_operand:DI 3 "const_int_operand" ""))
6542 (const_int 0)))
6543 (set (match_operand:DI 0 "gpc_reg_operand" "")
6544 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6545 "TARGET_POWERPC64 && reload_completed
6546 && includes_rldic_lshift_p (operands[2], operands[3])"
6547 [(set (match_dup 0)
6548 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6549 (match_dup 3)))
6550 (set (match_dup 4)
6551 (compare:CC (match_dup 0)
6552 (const_int 0)))]
6553 "")
6555 (define_insn "*ashldi3_internal7"
6556 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6557 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6558 (match_operand:SI 2 "const_int_operand" "i"))
6559 (match_operand:DI 3 "mask_operand" "n")))]
6560 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6561 "rldicr %0,%1,%H2,%S3")
6563 (define_insn "ashldi3_internal8"
6564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6565 (compare:CC
6566 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6567 (match_operand:SI 2 "const_int_operand" "i,i"))
6568 (match_operand:DI 3 "mask_operand" "n,n"))
6569 (const_int 0)))
6570 (clobber (match_scratch:DI 4 "=r,r"))]
6571 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6572 "@
6573 rldicr. %4,%1,%H2,%S3
6574 #"
6575 [(set_attr "type" "delayed_compare")
6576 (set_attr "length" "4,8")])
6578 (define_split
6579 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6580 (compare:CC
6581 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6582 (match_operand:SI 2 "const_int_operand" ""))
6583 (match_operand:DI 3 "mask_operand" ""))
6584 (const_int 0)))
6585 (clobber (match_scratch:DI 4 ""))]
6586 "TARGET_POWERPC64 && reload_completed
6587 && includes_rldicr_lshift_p (operands[2], operands[3])"
6588 [(set (match_dup 4)
6589 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6590 (match_dup 3)))
6591 (set (match_dup 0)
6592 (compare:CC (match_dup 4)
6593 (const_int 0)))]
6594 "")
6596 (define_insn "*ashldi3_internal9"
6597 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6598 (compare:CC
6599 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6600 (match_operand:SI 2 "const_int_operand" "i,i"))
6601 (match_operand:DI 3 "mask_operand" "n,n"))
6602 (const_int 0)))
6603 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6604 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6605 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6606 "@
6607 rldicr. %0,%1,%H2,%S3
6608 #"
6609 [(set_attr "type" "delayed_compare")
6610 (set_attr "length" "4,8")])
6612 (define_split
6613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6614 (compare:CC
6615 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6616 (match_operand:SI 2 "const_int_operand" ""))
6617 (match_operand:DI 3 "mask_operand" ""))
6618 (const_int 0)))
6619 (set (match_operand:DI 0 "gpc_reg_operand" "")
6620 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6621 "TARGET_POWERPC64 && reload_completed
6622 && includes_rldicr_lshift_p (operands[2], operands[3])"
6623 [(set (match_dup 0)
6624 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6625 (match_dup 3)))
6626 (set (match_dup 4)
6627 (compare:CC (match_dup 0)
6628 (const_int 0)))]
6629 "")
6631 (define_expand "lshrdi3"
6632 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6633 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6634 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6635 "TARGET_POWERPC64 || TARGET_POWER"
6636 "
6637 {
6638 if (TARGET_POWERPC64)
6639 ;
6640 else if (TARGET_POWER)
6641 {
6642 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6643 DONE;
6644 }
6645 else
6646 FAIL;
6647 }")
6649 (define_insn "*lshrdi3_internal1"
6650 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6651 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6652 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6653 "TARGET_POWERPC64"
6654 "srd%I2 %0,%1,%H2")
6656 (define_insn "*lshrdi3_internal2"
6657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6658 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6659 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6660 (const_int 0)))
6661 (clobber (match_scratch:DI 3 "=r,r"))]
6662 "TARGET_64BIT "
6663 "@
6664 srd%I2. %3,%1,%H2
6665 #"
6666 [(set_attr "type" "delayed_compare")
6667 (set_attr "length" "4,8")])
6669 (define_split
6670 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6671 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6672 (match_operand:SI 2 "reg_or_cint_operand" ""))
6673 (const_int 0)))
6674 (clobber (match_scratch:DI 3 ""))]
6675 "TARGET_POWERPC64 && reload_completed"
6676 [(set (match_dup 3)
6677 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6678 (set (match_dup 0)
6679 (compare:CC (match_dup 3)
6680 (const_int 0)))]
6681 "")
6683 (define_insn "*lshrdi3_internal3"
6684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6685 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6686 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6687 (const_int 0)))
6688 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6689 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6690 "TARGET_64BIT"
6691 "@
6692 srd%I2. %0,%1,%H2
6693 #"
6694 [(set_attr "type" "delayed_compare")
6695 (set_attr "length" "4,8")])
6697 (define_split
6698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6699 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6700 (match_operand:SI 2 "reg_or_cint_operand" ""))
6701 (const_int 0)))
6702 (set (match_operand:DI 0 "gpc_reg_operand" "")
6703 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6704 "TARGET_POWERPC64 && reload_completed"
6705 [(set (match_dup 0)
6706 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6707 (set (match_dup 3)
6708 (compare:CC (match_dup 0)
6709 (const_int 0)))]
6710 "")
6712 (define_expand "ashrdi3"
6713 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6714 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6715 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6716 "WORDS_BIG_ENDIAN"
6717 "
6718 {
6719 if (TARGET_POWERPC64)
6720 ;
6721 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6722 {
6723 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6724 DONE;
6725 }
6726 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6727 && WORDS_BIG_ENDIAN)
6728 {
6729 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6730 DONE;
6731 }
6732 else
6733 FAIL;
6734 }")
6736 (define_insn "*ashrdi3_internal1"
6737 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6738 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6739 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6740 "TARGET_POWERPC64"
6741 "srad%I2 %0,%1,%H2")
6743 (define_insn "*ashrdi3_internal2"
6744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6745 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6746 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6747 (const_int 0)))
6748 (clobber (match_scratch:DI 3 "=r,r"))]
6749 "TARGET_64BIT"
6750 "@
6751 srad%I2. %3,%1,%H2
6752 #"
6753 [(set_attr "type" "delayed_compare")
6754 (set_attr "length" "4,8")])
6756 (define_split
6757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6758 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6759 (match_operand:SI 2 "reg_or_cint_operand" ""))
6760 (const_int 0)))
6761 (clobber (match_scratch:DI 3 ""))]
6762 "TARGET_POWERPC64 && reload_completed"
6763 [(set (match_dup 3)
6764 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6765 (set (match_dup 0)
6766 (compare:CC (match_dup 3)
6767 (const_int 0)))]
6768 "")
6770 (define_insn "*ashrdi3_internal3"
6771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6772 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6773 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6774 (const_int 0)))
6775 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6776 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6777 "TARGET_64BIT"
6778 "@
6779 srad%I2. %0,%1,%H2
6780 #"
6781 [(set_attr "type" "delayed_compare")
6782 (set_attr "length" "4,8")])
6784 (define_split
6785 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6786 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:SI 2 "reg_or_cint_operand" ""))
6788 (const_int 0)))
6789 (set (match_operand:DI 0 "gpc_reg_operand" "")
6790 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6791 "TARGET_POWERPC64 && reload_completed"
6792 [(set (match_dup 0)
6793 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6794 (set (match_dup 3)
6795 (compare:CC (match_dup 0)
6796 (const_int 0)))]
6797 "")
6799 (define_insn "anddi3"
6800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6801 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6802 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6803 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6804 "TARGET_POWERPC64"
6805 "@
6806 and %0,%1,%2
6807 rldic%B2 %0,%1,0,%S2
6808 rlwinm %0,%1,0,%m2,%M2
6809 andi. %0,%1,%b2
6810 andis. %0,%1,%u2
6811 #"
6812 [(set_attr "type" "*,*,*,compare,compare,*")
6813 (set_attr "length" "4,4,4,4,4,8")])
6815 (define_split
6816 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6817 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6818 (match_operand:DI 2 "mask64_2_operand" "")))
6819 (clobber (match_scratch:CC 3 ""))]
6820 "TARGET_POWERPC64
6821 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6822 && !mask_operand (operands[2], DImode)"
6823 [(set (match_dup 0)
6824 (and:DI (rotate:DI (match_dup 1)
6825 (match_dup 4))
6826 (match_dup 5)))
6827 (set (match_dup 0)
6828 (and:DI (rotate:DI (match_dup 0)
6829 (match_dup 6))
6830 (match_dup 7)))]
6831 {
6832 build_mask64_2_operands (operands[2], &operands[4]);
6833 })
6835 (define_insn "*anddi3_internal2"
6836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6837 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6838 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6839 (const_int 0)))
6840 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6841 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6842 "TARGET_64BIT"
6843 "@
6844 and. %3,%1,%2
6845 rldic%B2. %3,%1,0,%S2
6846 andi. %3,%1,%b2
6847 andis. %3,%1,%u2
6848 #
6849 #
6850 #
6851 #
6852 #
6853 #"
6854 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6855 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6857 (define_split
6858 [(set (match_operand:CC 0 "cc_reg_operand" "")
6859 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6860 (match_operand:DI 2 "mask64_2_operand" ""))
6861 (const_int 0)))
6862 (clobber (match_scratch:DI 3 ""))
6863 (clobber (match_scratch:CC 4 ""))]
6864 "TARGET_POWERPC64 && reload_completed
6865 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6866 && !mask_operand (operands[2], DImode)"
6867 [(set (match_dup 3)
6868 (and:DI (rotate:DI (match_dup 1)
6869 (match_dup 5))
6870 (match_dup 6)))
6871 (parallel [(set (match_dup 0)
6872 (compare:CC (and:DI (rotate:DI (match_dup 3)
6873 (match_dup 7))
6874 (match_dup 8))
6875 (const_int 0)))
6876 (clobber (match_dup 3))])]
6877 "
6878 {
6879 build_mask64_2_operands (operands[2], &operands[5]);
6880 }")
6882 (define_insn "*anddi3_internal3"
6883 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6884 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6885 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6886 (const_int 0)))
6887 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
6888 (and:DI (match_dup 1) (match_dup 2)))
6889 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6890 "TARGET_64BIT"
6891 "@
6892 and. %0,%1,%2
6893 rldic%B2. %0,%1,0,%S2
6894 andi. %0,%1,%b2
6895 andis. %0,%1,%u2
6896 #
6897 #
6898 #
6899 #
6900 #
6901 #"
6902 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6903 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6905 (define_split
6906 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6907 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6908 (match_operand:DI 2 "and_operand" ""))
6909 (const_int 0)))
6910 (set (match_operand:DI 0 "gpc_reg_operand" "")
6911 (and:DI (match_dup 1) (match_dup 2)))
6912 (clobber (match_scratch:CC 4 ""))]
6913 "TARGET_POWERPC64 && reload_completed"
6914 [(parallel [(set (match_dup 0)
6915 (and:DI (match_dup 1) (match_dup 2)))
6916 (clobber (match_dup 4))])
6917 (set (match_dup 3)
6918 (compare:CC (match_dup 0)
6919 (const_int 0)))]
6920 "")
6922 (define_split
6923 [(set (match_operand:CC 3 "cc_reg_operand" "")
6924 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6925 (match_operand:DI 2 "mask64_2_operand" ""))
6926 (const_int 0)))
6927 (set (match_operand:DI 0 "gpc_reg_operand" "")
6928 (and:DI (match_dup 1) (match_dup 2)))
6929 (clobber (match_scratch:CC 4 ""))]
6930 "TARGET_POWERPC64 && reload_completed
6931 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6932 && !mask_operand (operands[2], DImode)"
6933 [(set (match_dup 0)
6934 (and:DI (rotate:DI (match_dup 1)
6935 (match_dup 5))
6936 (match_dup 6)))
6937 (parallel [(set (match_dup 3)
6938 (compare:CC (and:DI (rotate:DI (match_dup 0)
6939 (match_dup 7))
6940 (match_dup 8))
6941 (const_int 0)))
6942 (set (match_dup 0)
6943 (and:DI (rotate:DI (match_dup 0)
6944 (match_dup 7))
6945 (match_dup 8)))])]
6946 "
6947 {
6948 build_mask64_2_operands (operands[2], &operands[5]);
6949 }")
6951 (define_expand "iordi3"
6952 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6953 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
6954 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6955 "TARGET_POWERPC64"
6956 "
6957 {
6958 if (non_logical_cint_operand (operands[2], DImode))
6959 {
6960 HOST_WIDE_INT value;
6961 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6962 ? operands[0] : gen_reg_rtx (DImode));
6964 if (GET_CODE (operands[2]) == CONST_INT)
6965 {
6966 value = INTVAL (operands[2]);
6967 emit_insn (gen_iordi3 (tmp, operands[1],
6968 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
6969 }
6970 else
6971 {
6972 value = CONST_DOUBLE_LOW (operands[2]);
6973 emit_insn (gen_iordi3 (tmp, operands[1],
6974 immed_double_const (value
6975 & (~ (HOST_WIDE_INT) 0xffff),
6976 0, DImode)));
6977 }
6979 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
6980 DONE;
6981 }
6982 }")
6984 (define_expand "xordi3"
6985 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6986 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
6987 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
6988 "TARGET_POWERPC64"
6989 "
6990 {
6991 if (non_logical_cint_operand (operands[2], DImode))
6992 {
6993 HOST_WIDE_INT value;
6994 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6995 ? operands[0] : gen_reg_rtx (DImode));
6997 if (GET_CODE (operands[2]) == CONST_INT)
6998 {
6999 value = INTVAL (operands[2]);
7000 emit_insn (gen_xordi3 (tmp, operands[1],
7001 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7002 }
7003 else
7004 {
7005 value = CONST_DOUBLE_LOW (operands[2]);
7006 emit_insn (gen_xordi3 (tmp, operands[1],
7007 immed_double_const (value
7008 & (~ (HOST_WIDE_INT) 0xffff),
7009 0, DImode)));
7010 }
7012 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7013 DONE;
7014 }
7015 }")
7017 (define_insn "*booldi3_internal1"
7018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7019 (match_operator:DI 3 "boolean_or_operator"
7020 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7021 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7022 "TARGET_POWERPC64"
7023 "@
7024 %q3 %0,%1,%2
7025 %q3i %0,%1,%b2
7026 %q3is %0,%1,%u2")
7028 (define_insn "*booldi3_internal2"
7029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7030 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7031 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7032 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7033 (const_int 0)))
7034 (clobber (match_scratch:DI 3 "=r,r"))]
7035 "TARGET_64BIT"
7036 "@
7037 %q4. %3,%1,%2
7038 #"
7039 [(set_attr "type" "compare")
7040 (set_attr "length" "4,8")])
7042 (define_split
7043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7044 (compare:CC (match_operator:DI 4 "boolean_operator"
7045 [(match_operand:DI 1 "gpc_reg_operand" "")
7046 (match_operand:DI 2 "gpc_reg_operand" "")])
7047 (const_int 0)))
7048 (clobber (match_scratch:DI 3 ""))]
7049 "TARGET_POWERPC64 && reload_completed"
7050 [(set (match_dup 3) (match_dup 4))
7051 (set (match_dup 0)
7052 (compare:CC (match_dup 3)
7053 (const_int 0)))]
7054 "")
7056 (define_insn "*booldi3_internal3"
7057 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7058 (compare:CC (match_operator:DI 4 "boolean_operator"
7059 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7060 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7061 (const_int 0)))
7062 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7063 (match_dup 4))]
7064 "TARGET_64BIT"
7065 "@
7066 %q4. %0,%1,%2
7067 #"
7068 [(set_attr "type" "compare")
7069 (set_attr "length" "4,8")])
7071 (define_split
7072 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7073 (compare:CC (match_operator:DI 4 "boolean_operator"
7074 [(match_operand:DI 1 "gpc_reg_operand" "")
7075 (match_operand:DI 2 "gpc_reg_operand" "")])
7076 (const_int 0)))
7077 (set (match_operand:DI 0 "gpc_reg_operand" "")
7078 (match_dup 4))]
7079 "TARGET_POWERPC64 && reload_completed"
7080 [(set (match_dup 0) (match_dup 4))
7081 (set (match_dup 3)
7082 (compare:CC (match_dup 0)
7083 (const_int 0)))]
7084 "")
7086 ;; Split a logical operation that we can't do in one insn into two insns,
7087 ;; each of which does one 16-bit part. This is used by combine.
7089 (define_split
7090 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7091 (match_operator:DI 3 "boolean_or_operator"
7092 [(match_operand:DI 1 "gpc_reg_operand" "")
7093 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7094 "TARGET_POWERPC64"
7095 [(set (match_dup 0) (match_dup 4))
7096 (set (match_dup 0) (match_dup 5))]
7097 "
7098 {
7099 rtx i3,i4;
7101 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7102 {
7103 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7104 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7105 0, DImode);
7106 i4 = GEN_INT (value & 0xffff);
7107 }
7108 else
7109 {
7110 i3 = GEN_INT (INTVAL (operands[2])
7111 & (~ (HOST_WIDE_INT) 0xffff));
7112 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7113 }
7114 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7115 operands[1], i3);
7116 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7117 operands[0], i4);
7118 }")
7120 (define_insn "*boolcdi3_internal1"
7121 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7122 (match_operator:DI 3 "boolean_operator"
7123 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7124 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7125 "TARGET_POWERPC64"
7126 "%q3 %0,%2,%1")
7128 (define_insn "*boolcdi3_internal2"
7129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7130 (compare:CC (match_operator:DI 4 "boolean_operator"
7131 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7132 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7133 (const_int 0)))
7134 (clobber (match_scratch:DI 3 "=r,r"))]
7135 "TARGET_64BIT"
7136 "@
7137 %q4. %3,%2,%1
7138 #"
7139 [(set_attr "type" "compare")
7140 (set_attr "length" "4,8")])
7142 (define_split
7143 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7144 (compare:CC (match_operator:DI 4 "boolean_operator"
7145 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7146 (match_operand:DI 2 "gpc_reg_operand" "")])
7147 (const_int 0)))
7148 (clobber (match_scratch:DI 3 ""))]
7149 "TARGET_POWERPC64 && reload_completed"
7150 [(set (match_dup 3) (match_dup 4))
7151 (set (match_dup 0)
7152 (compare:CC (match_dup 3)
7153 (const_int 0)))]
7154 "")
7156 (define_insn "*boolcdi3_internal3"
7157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7158 (compare:CC (match_operator:DI 4 "boolean_operator"
7159 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7160 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7161 (const_int 0)))
7162 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7163 (match_dup 4))]
7164 "TARGET_64BIT"
7165 "@
7166 %q4. %0,%2,%1
7167 #"
7168 [(set_attr "type" "compare")
7169 (set_attr "length" "4,8")])
7171 (define_split
7172 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7173 (compare:CC (match_operator:DI 4 "boolean_operator"
7174 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7175 (match_operand:DI 2 "gpc_reg_operand" "")])
7176 (const_int 0)))
7177 (set (match_operand:DI 0 "gpc_reg_operand" "")
7178 (match_dup 4))]
7179 "TARGET_POWERPC64 && reload_completed"
7180 [(set (match_dup 0) (match_dup 4))
7181 (set (match_dup 3)
7182 (compare:CC (match_dup 0)
7183 (const_int 0)))]
7184 "")
7186 (define_insn "*boolccdi3_internal1"
7187 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7188 (match_operator:DI 3 "boolean_operator"
7189 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7190 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7191 "TARGET_POWERPC64"
7192 "%q3 %0,%1,%2")
7194 (define_insn "*boolccdi3_internal2"
7195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7196 (compare:CC (match_operator:DI 4 "boolean_operator"
7197 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7198 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7199 (const_int 0)))
7200 (clobber (match_scratch:DI 3 "=r,r"))]
7201 "TARGET_64BIT"
7202 "@
7203 %q4. %3,%1,%2
7204 #"
7205 [(set_attr "type" "compare")
7206 (set_attr "length" "4,8")])
7208 (define_split
7209 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7210 (compare:CC (match_operator:DI 4 "boolean_operator"
7211 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7212 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7213 (const_int 0)))
7214 (clobber (match_scratch:DI 3 ""))]
7215 "TARGET_POWERPC64 && reload_completed"
7216 [(set (match_dup 3) (match_dup 4))
7217 (set (match_dup 0)
7218 (compare:CC (match_dup 3)
7219 (const_int 0)))]
7220 "")
7222 (define_insn "*boolccdi3_internal3"
7223 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7224 (compare:CC (match_operator:DI 4 "boolean_operator"
7225 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7226 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7227 (const_int 0)))
7228 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7229 (match_dup 4))]
7230 "TARGET_64BIT"
7231 "@
7232 %q4. %0,%1,%2
7233 #"
7234 [(set_attr "type" "compare")
7235 (set_attr "length" "4,8")])
7237 (define_split
7238 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7239 (compare:CC (match_operator:DI 4 "boolean_operator"
7240 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7241 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7242 (const_int 0)))
7243 (set (match_operand:DI 0 "gpc_reg_operand" "")
7244 (match_dup 4))]
7245 "TARGET_POWERPC64 && reload_completed"
7246 [(set (match_dup 0) (match_dup 4))
7247 (set (match_dup 3)
7248 (compare:CC (match_dup 0)
7249 (const_int 0)))]
7250 "")
7251 \f
7252 ;; Now define ways of moving data around.
7254 ;; Set up a register with a value from the GOT table
7256 (define_expand "movsi_got"
7257 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7258 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7259 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7260 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7261 "
7262 {
7263 if (GET_CODE (operands[1]) == CONST)
7264 {
7265 rtx offset = const0_rtx;
7266 HOST_WIDE_INT value;
7268 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7269 value = INTVAL (offset);
7270 if (value != 0)
7271 {
7272 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7273 emit_insn (gen_movsi_got (tmp, operands[1]));
7274 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7275 DONE;
7276 }
7277 }
7279 operands[2] = rs6000_got_register (operands[1]);
7280 }")
7282 (define_insn "*movsi_got_internal"
7283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7284 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7285 (match_operand:SI 2 "gpc_reg_operand" "b")]
7286 UNSPEC_MOVSI_GOT))]
7287 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7288 "{l|lwz} %0,%a1@got(%2)"
7289 [(set_attr "type" "load")])
7291 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7292 ;; didn't get allocated to a hard register.
7293 (define_split
7294 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7295 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7296 (match_operand:SI 2 "memory_operand" "")]
7297 UNSPEC_MOVSI_GOT))]
7298 "DEFAULT_ABI == ABI_V4
7299 && flag_pic == 1
7300 && (reload_in_progress || reload_completed)"
7301 [(set (match_dup 0) (match_dup 2))
7302 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7303 UNSPEC_MOVSI_GOT))]
7304 "")
7306 ;; For SI, we special-case integers that can't be loaded in one insn. We
7307 ;; do the load 16-bits at a time. We could do this by loading from memory,
7308 ;; and this is even supposed to be faster, but it is simpler not to get
7309 ;; integers in the TOC.
7310 (define_insn "movsi_low"
7311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7312 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7313 (match_operand 2 "" ""))))]
7314 "TARGET_MACHO && ! TARGET_64BIT"
7315 "{l|lwz} %0,lo16(%2)(%1)"
7316 [(set_attr "type" "load")
7317 (set_attr "length" "4")])
7319 (define_insn "*movsi_internal1"
7320 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7321 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7322 "gpc_reg_operand (operands[0], SImode)
7323 || gpc_reg_operand (operands[1], SImode)"
7324 "@
7325 mr %0,%1
7326 {cal|la} %0,%a1
7327 {l%U1%X1|lwz%U1%X1} %0,%1
7328 {st%U0%X0|stw%U0%X0} %1,%0
7329 {lil|li} %0,%1
7330 {liu|lis} %0,%v1
7331 #
7332 {cal|la} %0,%a1
7333 mf%1 %0
7334 mt%0 %1
7335 mt%0 %1
7336 mt%0 %1
7337 {cror 0,0,0|nop}"
7338 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7339 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7341 ;; Split a load of a large constant into the appropriate two-insn
7342 ;; sequence.
7344 (define_split
7345 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7346 (match_operand:SI 1 "const_int_operand" ""))]
7347 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7348 && (INTVAL (operands[1]) & 0xffff) != 0"
7349 [(set (match_dup 0)
7350 (match_dup 2))
7351 (set (match_dup 0)
7352 (ior:SI (match_dup 0)
7353 (match_dup 3)))]
7354 "
7355 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7357 if (tem == operands[0])
7358 DONE;
7359 else
7360 FAIL;
7361 }")
7363 (define_insn "*mov<mode>_internal2"
7364 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7365 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7366 (const_int 0)))
7367 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7368 ""
7369 "@
7370 {cmpi|cmp<wd>i} %2,%0,0
7371 mr. %0,%1
7372 #"
7373 [(set_attr "type" "cmp,compare,cmp")
7374 (set_attr "length" "4,4,8")])
7376 (define_split
7377 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7378 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7379 (const_int 0)))
7380 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7381 "reload_completed"
7382 [(set (match_dup 0) (match_dup 1))
7383 (set (match_dup 2)
7384 (compare:CC (match_dup 0)
7385 (const_int 0)))]
7386 "")
7387 \f
7388 (define_insn "*movhi_internal"
7389 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7390 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7391 "gpc_reg_operand (operands[0], HImode)
7392 || gpc_reg_operand (operands[1], HImode)"
7393 "@
7394 mr %0,%1
7395 lhz%U1%X1 %0,%1
7396 sth%U0%X0 %1,%0
7397 {lil|li} %0,%w1
7398 mf%1 %0
7399 mt%0 %1
7400 mt%0 %1
7401 {cror 0,0,0|nop}"
7402 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7404 (define_expand "mov<mode>"
7405 [(set (match_operand:INT 0 "general_operand" "")
7406 (match_operand:INT 1 "any_operand" ""))]
7407 ""
7408 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7410 (define_insn "*movqi_internal"
7411 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7412 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7413 "gpc_reg_operand (operands[0], QImode)
7414 || gpc_reg_operand (operands[1], QImode)"
7415 "@
7416 mr %0,%1
7417 lbz%U1%X1 %0,%1
7418 stb%U0%X0 %1,%0
7419 {lil|li} %0,%1
7420 mf%1 %0
7421 mt%0 %1
7422 mt%0 %1
7423 {cror 0,0,0|nop}"
7424 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7425 \f
7426 ;; Here is how to move condition codes around. When we store CC data in
7427 ;; an integer register or memory, we store just the high-order 4 bits.
7428 ;; This lets us not shift in the most common case of CR0.
7429 (define_expand "movcc"
7430 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7431 (match_operand:CC 1 "nonimmediate_operand" ""))]
7432 ""
7433 "")
7435 (define_insn "*movcc_internal1"
7436 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7437 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7438 "register_operand (operands[0], CCmode)
7439 || register_operand (operands[1], CCmode)"
7440 "@
7441 mcrf %0,%1
7442 mtcrf 128,%1
7443 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7444 mfcr %0%Q1
7445 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7446 mr %0,%1
7447 mf%1 %0
7448 mt%0 %1
7449 mt%0 %1
7450 {l%U1%X1|lwz%U1%X1} %0,%1
7451 {st%U0%U1|stw%U0%U1} %1,%0"
7452 [(set (attr "type")
7453 (cond [(eq_attr "alternative" "0")
7454 (const_string "cr_logical")
7455 (eq_attr "alternative" "1,2")
7456 (const_string "mtcr")
7457 (eq_attr "alternative" "5,7")
7458 (const_string "integer")
7459 (eq_attr "alternative" "6")
7460 (const_string "mfjmpr")
7461 (eq_attr "alternative" "8")
7462 (const_string "mtjmpr")
7463 (eq_attr "alternative" "9")
7464 (const_string "load")
7465 (eq_attr "alternative" "10")
7466 (const_string "store")
7467 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7468 (const_string "mfcrf")
7469 ]
7470 (const_string "mfcr")))
7471 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7472 \f
7473 ;; For floating-point, we normally deal with the floating-point registers
7474 ;; unless -msoft-float is used. The sole exception is that parameter passing
7475 ;; can produce floating-point values in fixed-point registers. Unless the
7476 ;; value is a simple constant or already in memory, we deal with this by
7477 ;; allocating memory and copying the value explicitly via that memory location.
7478 (define_expand "movsf"
7479 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7480 (match_operand:SF 1 "any_operand" ""))]
7481 ""
7482 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7484 (define_split
7485 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7486 (match_operand:SF 1 "const_double_operand" ""))]
7487 "reload_completed
7488 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7489 || (GET_CODE (operands[0]) == SUBREG
7490 && GET_CODE (SUBREG_REG (operands[0])) == REG
7491 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7492 [(set (match_dup 2) (match_dup 3))]
7493 "
7494 {
7495 long l;
7496 REAL_VALUE_TYPE rv;
7498 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7499 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7501 if (! TARGET_POWERPC64)
7502 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7503 else
7504 operands[2] = gen_lowpart (SImode, operands[0]);
7506 operands[3] = gen_int_mode (l, SImode);
7507 }")
7509 (define_insn "*movsf_hardfloat"
7510 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7511 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7512 "(gpc_reg_operand (operands[0], SFmode)
7513 || gpc_reg_operand (operands[1], SFmode))
7514 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7515 "@
7516 mr %0,%1
7517 {l%U1%X1|lwz%U1%X1} %0,%1
7518 {st%U0%X0|stw%U0%X0} %1,%0
7519 fmr %0,%1
7520 lfs%U1%X1 %0,%1
7521 stfs%U0%X0 %1,%0
7522 mt%0 %1
7523 mt%0 %1
7524 mf%1 %0
7525 {cror 0,0,0|nop}
7526 #
7527 #"
7528 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7529 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7531 (define_insn "*movsf_softfloat"
7532 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7533 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7534 "(gpc_reg_operand (operands[0], SFmode)
7535 || gpc_reg_operand (operands[1], SFmode))
7536 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7537 "@
7538 mr %0,%1
7539 mt%0 %1
7540 mt%0 %1
7541 mf%1 %0
7542 {l%U1%X1|lwz%U1%X1} %0,%1
7543 {st%U0%X0|stw%U0%X0} %1,%0
7544 {lil|li} %0,%1
7545 {liu|lis} %0,%v1
7546 {cal|la} %0,%a1
7547 #
7548 #
7549 {cror 0,0,0|nop}"
7550 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7551 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7553 \f
7554 (define_expand "movdf"
7555 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7556 (match_operand:DF 1 "any_operand" ""))]
7557 ""
7558 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7560 (define_split
7561 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7562 (match_operand:DF 1 "const_int_operand" ""))]
7563 "! TARGET_POWERPC64 && reload_completed
7564 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7565 || (GET_CODE (operands[0]) == SUBREG
7566 && GET_CODE (SUBREG_REG (operands[0])) == REG
7567 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7568 [(set (match_dup 2) (match_dup 4))
7569 (set (match_dup 3) (match_dup 1))]
7570 "
7571 {
7572 int endian = (WORDS_BIG_ENDIAN == 0);
7573 HOST_WIDE_INT value = INTVAL (operands[1]);
7575 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7576 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7577 #if HOST_BITS_PER_WIDE_INT == 32
7578 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7579 #else
7580 operands[4] = GEN_INT (value >> 32);
7581 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7582 #endif
7583 }")
7585 (define_split
7586 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7587 (match_operand:DF 1 "const_double_operand" ""))]
7588 "! TARGET_POWERPC64 && reload_completed
7589 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7590 || (GET_CODE (operands[0]) == SUBREG
7591 && GET_CODE (SUBREG_REG (operands[0])) == REG
7592 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7593 [(set (match_dup 2) (match_dup 4))
7594 (set (match_dup 3) (match_dup 5))]
7595 "
7596 {
7597 int endian = (WORDS_BIG_ENDIAN == 0);
7598 long l[2];
7599 REAL_VALUE_TYPE rv;
7601 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7602 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7604 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7605 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7606 operands[4] = gen_int_mode (l[endian], SImode);
7607 operands[5] = gen_int_mode (l[1 - endian], SImode);
7608 }")
7610 (define_split
7611 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7612 (match_operand:DF 1 "easy_fp_constant" ""))]
7613 "TARGET_POWERPC64 && reload_completed
7614 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7615 || (GET_CODE (operands[0]) == SUBREG
7616 && GET_CODE (SUBREG_REG (operands[0])) == REG
7617 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7618 [(set (match_dup 2) (match_dup 3))]
7619 "
7620 {
7621 int endian = (WORDS_BIG_ENDIAN == 0);
7622 long l[2];
7623 REAL_VALUE_TYPE rv;
7624 #if HOST_BITS_PER_WIDE_INT >= 64
7625 HOST_WIDE_INT val;
7626 #endif
7628 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7629 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7631 operands[2] = gen_lowpart (DImode, operands[0]);
7632 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7633 #if HOST_BITS_PER_WIDE_INT >= 64
7634 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7635 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7637 operands[3] = gen_int_mode (val, DImode);
7638 #else
7639 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7640 #endif
7641 }")
7643 ;; Don't have reload use general registers to load a constant. First,
7644 ;; it might not work if the output operand is the equivalent of
7645 ;; a non-offsettable memref, but also it is less efficient than loading
7646 ;; the constant into an FP register, since it will probably be used there.
7647 ;; The "??" is a kludge until we can figure out a more reasonable way
7648 ;; of handling these non-offsettable values.
7649 (define_insn "*movdf_hardfloat32"
7650 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7651 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7652 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7653 && (gpc_reg_operand (operands[0], DFmode)
7654 || gpc_reg_operand (operands[1], DFmode))"
7655 "*
7656 {
7657 switch (which_alternative)
7658 {
7659 default:
7660 gcc_unreachable ();
7661 case 0:
7662 /* We normally copy the low-numbered register first. However, if
7663 the first register operand 0 is the same as the second register
7664 of operand 1, we must copy in the opposite order. */
7665 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7666 return \"mr %L0,%L1\;mr %0,%1\";
7667 else
7668 return \"mr %0,%1\;mr %L0,%L1\";
7669 case 1:
7670 if (GET_CODE (operands[1]) == MEM
7671 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7672 reload_completed || reload_in_progress)
7673 || GET_CODE (XEXP (operands[1], 0)) == REG
7674 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7675 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7676 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7677 {
7678 /* If the low-address word is used in the address, we must load
7679 it last. Otherwise, load it first. Note that we cannot have
7680 auto-increment in that case since the address register is
7681 known to be dead. */
7682 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7683 operands[1], 0))
7684 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7685 else
7686 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7687 }
7688 else
7689 {
7690 rtx addreg;
7692 addreg = find_addr_reg (XEXP (operands[1], 0));
7693 if (refers_to_regno_p (REGNO (operands[0]),
7694 REGNO (operands[0]) + 1,
7695 operands[1], 0))
7696 {
7697 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7698 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7699 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7700 return \"{lx|lwzx} %0,%1\";
7701 }
7702 else
7703 {
7704 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7705 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7706 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7707 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7708 return \"\";
7709 }
7710 }
7711 case 2:
7712 if (GET_CODE (operands[0]) == MEM
7713 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7714 reload_completed || reload_in_progress)
7715 || GET_CODE (XEXP (operands[0], 0)) == REG
7716 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7717 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7718 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7719 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7720 else
7721 {
7722 rtx addreg;
7724 addreg = find_addr_reg (XEXP (operands[0], 0));
7725 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7726 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7727 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7728 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7729 return \"\";
7730 }
7731 case 3:
7732 return \"fmr %0,%1\";
7733 case 4:
7734 return \"lfd%U1%X1 %0,%1\";
7735 case 5:
7736 return \"stfd%U0%X0 %1,%0\";
7737 case 6:
7738 case 7:
7739 case 8:
7740 return \"#\";
7741 }
7742 }"
7743 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7744 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7746 (define_insn "*movdf_softfloat32"
7747 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7748 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7749 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7750 && (gpc_reg_operand (operands[0], DFmode)
7751 || gpc_reg_operand (operands[1], DFmode))"
7752 "*
7753 {
7754 switch (which_alternative)
7755 {
7756 default:
7757 gcc_unreachable ();
7758 case 0:
7759 /* We normally copy the low-numbered register first. However, if
7760 the first register operand 0 is the same as the second register of
7761 operand 1, we must copy in the opposite order. */
7762 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7763 return \"mr %L0,%L1\;mr %0,%1\";
7764 else
7765 return \"mr %0,%1\;mr %L0,%L1\";
7766 case 1:
7767 /* If the low-address word is used in the address, we must load
7768 it last. Otherwise, load it first. Note that we cannot have
7769 auto-increment in that case since the address register is
7770 known to be dead. */
7771 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7772 operands[1], 0))
7773 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7774 else
7775 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7776 case 2:
7777 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7778 case 3:
7779 case 4:
7780 case 5:
7781 return \"#\";
7782 }
7783 }"
7784 [(set_attr "type" "two,load,store,*,*,*")
7785 (set_attr "length" "8,8,8,8,12,16")])
7787 ; ld/std require word-aligned displacements -> 'Y' constraint.
7788 ; List Y->r and r->Y before r->r for reload.
7789 (define_insn "*movdf_hardfloat64"
7790 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7791 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7792 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7793 && (gpc_reg_operand (operands[0], DFmode)
7794 || gpc_reg_operand (operands[1], DFmode))"
7795 "@
7796 std%U0%X0 %1,%0
7797 ld%U1%X1 %0,%1
7798 mr %0,%1
7799 fmr %0,%1
7800 lfd%U1%X1 %0,%1
7801 stfd%U0%X0 %1,%0
7802 mt%0 %1
7803 mf%1 %0
7804 {cror 0,0,0|nop}
7805 #
7806 #
7807 #"
7808 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7809 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7811 (define_insn "*movdf_softfloat64"
7812 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7813 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7814 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7815 && (gpc_reg_operand (operands[0], DFmode)
7816 || gpc_reg_operand (operands[1], DFmode))"
7817 "@
7818 ld%U1%X1 %0,%1
7819 std%U0%X0 %1,%0
7820 mr %0,%1
7821 mt%0 %1
7822 mf%1 %0
7823 #
7824 #
7825 #
7826 {cror 0,0,0|nop}"
7827 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7828 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7829 \f
7830 (define_expand "movtf"
7831 [(set (match_operand:TF 0 "general_operand" "")
7832 (match_operand:TF 1 "any_operand" ""))]
7833 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7834 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7835 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7837 ; It's important to list the o->f and f->o moves before f->f because
7838 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7839 ; which doesn't make progress. Likewise r->Y must be before r->r.
7840 (define_insn_and_split "*movtf_internal"
7841 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7842 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7843 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7844 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7845 && (gpc_reg_operand (operands[0], TFmode)
7846 || gpc_reg_operand (operands[1], TFmode))"
7847 "#"
7848 "&& reload_completed"
7849 [(pc)]
7850 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7851 [(set_attr "length" "8,8,8,20,20,16")])
7853 (define_expand "extenddftf2"
7854 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7855 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7856 (use (match_dup 2))])]
7857 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7858 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7859 {
7860 operands[2] = CONST0_RTX (DFmode);
7861 })
7863 (define_insn_and_split "*extenddftf2_internal"
7864 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7865 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7866 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7867 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7868 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7869 "#"
7870 "&& reload_completed"
7871 [(pc)]
7872 {
7873 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7874 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7875 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7876 operands[1]);
7877 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
7878 operands[2]);
7879 DONE;
7880 })
7882 (define_expand "extendsftf2"
7883 [(set (match_operand:TF 0 "nonimmediate_operand" "")
7884 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
7885 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7886 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7887 {
7888 rtx tmp = gen_reg_rtx (DFmode);
7889 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7890 emit_insn (gen_extenddftf2 (operands[0], tmp));
7891 DONE;
7892 })
7894 (define_expand "trunctfdf2"
7895 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7896 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
7897 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7898 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7899 "")
7901 (define_insn_and_split "trunctfdf2_internal1"
7902 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
7903 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
7904 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
7905 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7906 "@
7907 #
7908 fmr %0,%1"
7909 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7910 [(const_int 0)]
7911 {
7912 emit_note (NOTE_INSN_DELETED);
7913 DONE;
7914 }
7915 [(set_attr "type" "fp")])
7917 (define_insn "trunctfdf2_internal2"
7918 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7919 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
7920 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
7921 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7922 "fadd %0,%1,%L1"
7923 [(set_attr "type" "fp")])
7925 (define_insn_and_split "trunctfsf2"
7926 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7927 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
7928 (clobber (match_scratch:DF 2 "=f"))]
7929 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7930 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7931 "#"
7932 "&& reload_completed"
7933 [(set (match_dup 2)
7934 (float_truncate:DF (match_dup 1)))
7935 (set (match_dup 0)
7936 (float_truncate:SF (match_dup 2)))]
7937 "")
7939 (define_expand "floatsitf2"
7940 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
7941 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
7942 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7943 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7944 {
7945 rtx tmp = gen_reg_rtx (DFmode);
7946 expand_float (tmp, operands[1], false);
7947 emit_insn (gen_extenddftf2 (operands[0], tmp));
7948 DONE;
7949 })
7951 ; fadd, but rounding towards zero.
7952 ; This is probably not the optimal code sequence.
7953 (define_insn "fix_trunc_helper"
7954 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
7955 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
7956 UNSPEC_FIX_TRUNC_TF))
7957 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
7958 "TARGET_HARD_FLOAT && TARGET_FPRS"
7959 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7960 [(set_attr "type" "fp")
7961 (set_attr "length" "20")])
7963 (define_expand "fix_trunctfsi2"
7964 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7965 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
7966 (clobber (match_dup 2))
7967 (clobber (match_dup 3))
7968 (clobber (match_dup 4))
7969 (clobber (match_dup 5))])]
7970 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7971 && (TARGET_POWER2 || TARGET_POWERPC)
7972 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7973 {
7974 operands[2] = gen_reg_rtx (DFmode);
7975 operands[3] = gen_reg_rtx (DFmode);
7976 operands[4] = gen_reg_rtx (DImode);
7977 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
7978 })
7980 (define_insn_and_split "*fix_trunctfsi2_internal"
7981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7982 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
7983 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
7984 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
7985 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
7986 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
7987 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7988 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7989 "#"
7990 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
7991 [(pc)]
7992 {
7993 rtx lowword;
7994 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
7996 gcc_assert (MEM_P (operands[5]));
7997 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
7999 emit_insn (gen_fctiwz (operands[4], operands[2]));
8000 emit_move_insn (operands[5], operands[4]);
8001 emit_move_insn (operands[0], lowword);
8002 DONE;
8003 })
8005 (define_insn "negtf2"
8006 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8007 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8008 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8009 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8010 "*
8011 {
8012 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8013 return \"fneg %L0,%L1\;fneg %0,%1\";
8014 else
8015 return \"fneg %0,%1\;fneg %L0,%L1\";
8016 }"
8017 [(set_attr "type" "fp")
8018 (set_attr "length" "8")])
8020 (define_expand "abstf2"
8021 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8022 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8023 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8024 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8025 "
8026 {
8027 rtx label = gen_label_rtx ();
8028 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8029 emit_label (label);
8030 DONE;
8031 }")
8033 (define_expand "abstf2_internal"
8034 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8035 (match_operand:TF 1 "gpc_reg_operand" "f"))
8036 (set (match_dup 3) (match_dup 5))
8037 (set (match_dup 5) (abs:DF (match_dup 5)))
8038 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8039 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8040 (label_ref (match_operand 2 "" ""))
8041 (pc)))
8042 (set (match_dup 6) (neg:DF (match_dup 6)))]
8043 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8044 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8045 "
8046 {
8047 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8048 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8049 operands[3] = gen_reg_rtx (DFmode);
8050 operands[4] = gen_reg_rtx (CCFPmode);
8051 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8052 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8053 }")
8054 \f
8055 ;; Next come the multi-word integer load and store and the load and store
8056 ;; multiple insns.
8058 ; List r->r after r->"o<>", otherwise reload will try to reload a
8059 ; non-offsettable address by using r->r which won't make progress.
8060 (define_insn "*movdi_internal32"
8061 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8062 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8063 "! TARGET_POWERPC64
8064 && (gpc_reg_operand (operands[0], DImode)
8065 || gpc_reg_operand (operands[1], DImode))"
8066 "@
8067 #
8068 #
8069 #
8070 fmr %0,%1
8071 lfd%U1%X1 %0,%1
8072 stfd%U0%X0 %1,%0
8073 #"
8074 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8076 (define_split
8077 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8078 (match_operand:DI 1 "const_int_operand" ""))]
8079 "! TARGET_POWERPC64 && reload_completed"
8080 [(set (match_dup 2) (match_dup 4))
8081 (set (match_dup 3) (match_dup 1))]
8082 "
8083 {
8084 HOST_WIDE_INT value = INTVAL (operands[1]);
8085 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8086 DImode);
8087 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8088 DImode);
8089 #if HOST_BITS_PER_WIDE_INT == 32
8090 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8091 #else
8092 operands[4] = GEN_INT (value >> 32);
8093 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8094 #endif
8095 }")
8097 (define_split
8098 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8099 (match_operand:DI 1 "input_operand" ""))]
8100 "reload_completed && !TARGET_POWERPC64
8101 && gpr_or_gpr_p (operands[0], operands[1])"
8102 [(pc)]
8103 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8105 (define_insn "*movdi_internal64"
8106 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8107 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8108 "TARGET_POWERPC64
8109 && (gpc_reg_operand (operands[0], DImode)
8110 || gpc_reg_operand (operands[1], DImode))"
8111 "@
8112 mr %0,%1
8113 ld%U1%X1 %0,%1
8114 std%U0%X0 %1,%0
8115 li %0,%1
8116 lis %0,%v1
8117 #
8118 {cal|la} %0,%a1
8119 fmr %0,%1
8120 lfd%U1%X1 %0,%1
8121 stfd%U0%X0 %1,%0
8122 mf%1 %0
8123 mt%0 %1
8124 {cror 0,0,0|nop}"
8125 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8126 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8128 ;; immediate value valid for a single instruction hiding in a const_double
8129 (define_insn ""
8130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8131 (match_operand:DI 1 "const_double_operand" "F"))]
8132 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8133 && GET_CODE (operands[1]) == CONST_DOUBLE
8134 && num_insns_constant (operands[1], DImode) == 1"
8135 "*
8136 {
8137 return ((unsigned HOST_WIDE_INT)
8138 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8139 ? \"li %0,%1\" : \"lis %0,%v1\";
8140 }")
8142 ;; Generate all one-bits and clear left or right.
8143 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8144 (define_split
8145 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8146 (match_operand:DI 1 "mask_operand" ""))]
8147 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8148 [(set (match_dup 0) (const_int -1))
8149 (set (match_dup 0)
8150 (and:DI (rotate:DI (match_dup 0)
8151 (const_int 0))
8152 (match_dup 1)))]
8153 "")
8155 ;; Split a load of a large constant into the appropriate five-instruction
8156 ;; sequence. Handle anything in a constant number of insns.
8157 ;; When non-easy constants can go in the TOC, this should use
8158 ;; easy_fp_constant predicate.
8159 (define_split
8160 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8161 (match_operand:DI 1 "const_int_operand" ""))]
8162 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8163 [(set (match_dup 0) (match_dup 2))
8164 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8165 "
8166 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8168 if (tem == operands[0])
8169 DONE;
8170 else
8171 FAIL;
8172 }")
8174 (define_split
8175 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8176 (match_operand:DI 1 "const_double_operand" ""))]
8177 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8178 [(set (match_dup 0) (match_dup 2))
8179 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8180 "
8181 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8183 if (tem == operands[0])
8184 DONE;
8185 else
8186 FAIL;
8187 }")
8188 \f
8189 ;; TImode is similar, except that we usually want to compute the address into
8190 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8191 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8193 ;; We say that MQ is clobbered in the last alternative because the first
8194 ;; alternative would never get used otherwise since it would need a reload
8195 ;; while the 2nd alternative would not. We put memory cases first so they
8196 ;; are preferred. Otherwise, we'd try to reload the output instead of
8197 ;; giving the SCRATCH mq.
8199 (define_insn "*movti_power"
8200 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8201 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8202 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8203 "TARGET_POWER && ! TARGET_POWERPC64
8204 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8205 "*
8206 {
8207 switch (which_alternative)
8208 {
8209 default:
8210 gcc_unreachable ();
8212 case 0:
8213 if (TARGET_STRING)
8214 return \"{stsi|stswi} %1,%P0,16\";
8215 case 1:
8216 case 2:
8217 return \"#\";
8218 case 3:
8219 /* If the address is not used in the output, we can use lsi. Otherwise,
8220 fall through to generating four loads. */
8221 if (TARGET_STRING
8222 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8223 return \"{lsi|lswi} %0,%P1,16\";
8224 /* ... fall through ... */
8225 case 4:
8226 case 5:
8227 return \"#\";
8228 }
8229 }"
8230 [(set_attr "type" "store,store,*,load,load,*")])
8232 (define_insn "*movti_string"
8233 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8234 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8235 "! TARGET_POWER && ! TARGET_POWERPC64
8236 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8237 "*
8238 {
8239 switch (which_alternative)
8240 {
8241 default:
8242 gcc_unreachable ();
8243 case 0:
8244 if (TARGET_STRING)
8245 return \"{stsi|stswi} %1,%P0,16\";
8246 case 1:
8247 case 2:
8248 return \"#\";
8249 case 3:
8250 /* If the address is not used in the output, we can use lsi. Otherwise,
8251 fall through to generating four loads. */
8252 if (TARGET_STRING
8253 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8254 return \"{lsi|lswi} %0,%P1,16\";
8255 /* ... fall through ... */
8256 case 4:
8257 case 5:
8258 return \"#\";
8259 }
8260 }"
8261 [(set_attr "type" "store,store,*,load,load,*")])
8263 (define_insn "*movti_ppc64"
8264 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8265 (match_operand:TI 1 "input_operand" "r,r,m"))]
8266 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8267 || gpc_reg_operand (operands[1], TImode))"
8268 "#"
8269 [(set_attr "type" "*,load,store")])
8271 (define_split
8272 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8273 (match_operand:TI 1 "const_double_operand" ""))]
8274 "TARGET_POWERPC64"
8275 [(set (match_dup 2) (match_dup 4))
8276 (set (match_dup 3) (match_dup 5))]
8277 "
8278 {
8279 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8280 TImode);
8281 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8282 TImode);
8283 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8284 {
8285 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8286 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8287 }
8288 else if (GET_CODE (operands[1]) == CONST_INT)
8289 {
8290 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8291 operands[5] = operands[1];
8292 }
8293 else
8294 FAIL;
8295 }")
8297 (define_split
8298 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8299 (match_operand:TI 1 "input_operand" ""))]
8300 "reload_completed
8301 && gpr_or_gpr_p (operands[0], operands[1])"
8302 [(pc)]
8303 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8304 \f
8305 (define_expand "load_multiple"
8306 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8307 (match_operand:SI 1 "" ""))
8308 (use (match_operand:SI 2 "" ""))])]
8309 "TARGET_STRING && !TARGET_POWERPC64"
8310 "
8311 {
8312 int regno;
8313 int count;
8314 rtx op1;
8315 int i;
8317 /* Support only loading a constant number of fixed-point registers from
8318 memory and only bother with this if more than two; the machine
8319 doesn't support more than eight. */
8320 if (GET_CODE (operands[2]) != CONST_INT
8321 || INTVAL (operands[2]) <= 2
8322 || INTVAL (operands[2]) > 8
8323 || GET_CODE (operands[1]) != MEM
8324 || GET_CODE (operands[0]) != REG
8325 || REGNO (operands[0]) >= 32)
8326 FAIL;
8328 count = INTVAL (operands[2]);
8329 regno = REGNO (operands[0]);
8331 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8332 op1 = replace_equiv_address (operands[1],
8333 force_reg (SImode, XEXP (operands[1], 0)));
8335 for (i = 0; i < count; i++)
8336 XVECEXP (operands[3], 0, i)
8337 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8338 adjust_address_nv (op1, SImode, i * 4));
8339 }")
8341 (define_insn "*ldmsi8"
8342 [(match_parallel 0 "load_multiple_operation"
8343 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8344 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8345 (set (match_operand:SI 3 "gpc_reg_operand" "")
8346 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8347 (set (match_operand:SI 4 "gpc_reg_operand" "")
8348 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8349 (set (match_operand:SI 5 "gpc_reg_operand" "")
8350 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8351 (set (match_operand:SI 6 "gpc_reg_operand" "")
8352 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8353 (set (match_operand:SI 7 "gpc_reg_operand" "")
8354 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8355 (set (match_operand:SI 8 "gpc_reg_operand" "")
8356 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8357 (set (match_operand:SI 9 "gpc_reg_operand" "")
8358 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8359 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8360 "*
8361 { return rs6000_output_load_multiple (operands); }"
8362 [(set_attr "type" "load")
8363 (set_attr "length" "32")])
8365 (define_insn "*ldmsi7"
8366 [(match_parallel 0 "load_multiple_operation"
8367 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8368 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8369 (set (match_operand:SI 3 "gpc_reg_operand" "")
8370 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8371 (set (match_operand:SI 4 "gpc_reg_operand" "")
8372 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8373 (set (match_operand:SI 5 "gpc_reg_operand" "")
8374 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8375 (set (match_operand:SI 6 "gpc_reg_operand" "")
8376 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8377 (set (match_operand:SI 7 "gpc_reg_operand" "")
8378 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8379 (set (match_operand:SI 8 "gpc_reg_operand" "")
8380 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8381 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8382 "*
8383 { return rs6000_output_load_multiple (operands); }"
8384 [(set_attr "type" "load")
8385 (set_attr "length" "32")])
8387 (define_insn "*ldmsi6"
8388 [(match_parallel 0 "load_multiple_operation"
8389 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8390 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8391 (set (match_operand:SI 3 "gpc_reg_operand" "")
8392 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8393 (set (match_operand:SI 4 "gpc_reg_operand" "")
8394 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8395 (set (match_operand:SI 5 "gpc_reg_operand" "")
8396 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8397 (set (match_operand:SI 6 "gpc_reg_operand" "")
8398 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8399 (set (match_operand:SI 7 "gpc_reg_operand" "")
8400 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8401 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8402 "*
8403 { return rs6000_output_load_multiple (operands); }"
8404 [(set_attr "type" "load")
8405 (set_attr "length" "32")])
8407 (define_insn "*ldmsi5"
8408 [(match_parallel 0 "load_multiple_operation"
8409 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8410 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8411 (set (match_operand:SI 3 "gpc_reg_operand" "")
8412 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8413 (set (match_operand:SI 4 "gpc_reg_operand" "")
8414 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8415 (set (match_operand:SI 5 "gpc_reg_operand" "")
8416 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8417 (set (match_operand:SI 6 "gpc_reg_operand" "")
8418 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8419 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8420 "*
8421 { return rs6000_output_load_multiple (operands); }"
8422 [(set_attr "type" "load")
8423 (set_attr "length" "32")])
8425 (define_insn "*ldmsi4"
8426 [(match_parallel 0 "load_multiple_operation"
8427 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8428 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8429 (set (match_operand:SI 3 "gpc_reg_operand" "")
8430 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8431 (set (match_operand:SI 4 "gpc_reg_operand" "")
8432 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8433 (set (match_operand:SI 5 "gpc_reg_operand" "")
8434 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8435 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8436 "*
8437 { return rs6000_output_load_multiple (operands); }"
8438 [(set_attr "type" "load")
8439 (set_attr "length" "32")])
8441 (define_insn "*ldmsi3"
8442 [(match_parallel 0 "load_multiple_operation"
8443 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8444 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8445 (set (match_operand:SI 3 "gpc_reg_operand" "")
8446 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8447 (set (match_operand:SI 4 "gpc_reg_operand" "")
8448 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8449 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8450 "*
8451 { return rs6000_output_load_multiple (operands); }"
8452 [(set_attr "type" "load")
8453 (set_attr "length" "32")])
8455 (define_expand "store_multiple"
8456 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8457 (match_operand:SI 1 "" ""))
8458 (clobber (scratch:SI))
8459 (use (match_operand:SI 2 "" ""))])]
8460 "TARGET_STRING && !TARGET_POWERPC64"
8461 "
8462 {
8463 int regno;
8464 int count;
8465 rtx to;
8466 rtx op0;
8467 int i;
8469 /* Support only storing a constant number of fixed-point registers to
8470 memory and only bother with this if more than two; the machine
8471 doesn't support more than eight. */
8472 if (GET_CODE (operands[2]) != CONST_INT
8473 || INTVAL (operands[2]) <= 2
8474 || INTVAL (operands[2]) > 8
8475 || GET_CODE (operands[0]) != MEM
8476 || GET_CODE (operands[1]) != REG
8477 || REGNO (operands[1]) >= 32)
8478 FAIL;
8480 count = INTVAL (operands[2]);
8481 regno = REGNO (operands[1]);
8483 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8484 to = force_reg (SImode, XEXP (operands[0], 0));
8485 op0 = replace_equiv_address (operands[0], to);
8487 XVECEXP (operands[3], 0, 0)
8488 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8489 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8490 gen_rtx_SCRATCH (SImode));
8492 for (i = 1; i < count; i++)
8493 XVECEXP (operands[3], 0, i + 1)
8494 = gen_rtx_SET (VOIDmode,
8495 adjust_address_nv (op0, SImode, i * 4),
8496 gen_rtx_REG (SImode, regno + i));
8497 }")
8499 (define_insn "*store_multiple_power"
8500 [(match_parallel 0 "store_multiple_operation"
8501 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8502 (match_operand:SI 2 "gpc_reg_operand" "r"))
8503 (clobber (match_scratch:SI 3 "=q"))])]
8504 "TARGET_STRING && TARGET_POWER"
8505 "{stsi|stswi} %2,%P1,%O0"
8506 [(set_attr "type" "store")])
8508 (define_insn "*stmsi8"
8509 [(match_parallel 0 "store_multiple_operation"
8510 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8511 (match_operand:SI 2 "gpc_reg_operand" "r"))
8512 (clobber (match_scratch:SI 3 "X"))
8513 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8514 (match_operand:SI 4 "gpc_reg_operand" "r"))
8515 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8516 (match_operand:SI 5 "gpc_reg_operand" "r"))
8517 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8518 (match_operand:SI 6 "gpc_reg_operand" "r"))
8519 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8520 (match_operand:SI 7 "gpc_reg_operand" "r"))
8521 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8522 (match_operand:SI 8 "gpc_reg_operand" "r"))
8523 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8524 (match_operand:SI 9 "gpc_reg_operand" "r"))
8525 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8526 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8527 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8528 "{stsi|stswi} %2,%1,%O0"
8529 [(set_attr "type" "store")])
8531 (define_insn "*stmsi7"
8532 [(match_parallel 0 "store_multiple_operation"
8533 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8534 (match_operand:SI 2 "gpc_reg_operand" "r"))
8535 (clobber (match_scratch:SI 3 "X"))
8536 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8537 (match_operand:SI 4 "gpc_reg_operand" "r"))
8538 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8539 (match_operand:SI 5 "gpc_reg_operand" "r"))
8540 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8541 (match_operand:SI 6 "gpc_reg_operand" "r"))
8542 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8543 (match_operand:SI 7 "gpc_reg_operand" "r"))
8544 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8545 (match_operand:SI 8 "gpc_reg_operand" "r"))
8546 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8547 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8548 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8549 "{stsi|stswi} %2,%1,%O0"
8550 [(set_attr "type" "store")])
8552 (define_insn "*stmsi6"
8553 [(match_parallel 0 "store_multiple_operation"
8554 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8555 (match_operand:SI 2 "gpc_reg_operand" "r"))
8556 (clobber (match_scratch:SI 3 "X"))
8557 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8558 (match_operand:SI 4 "gpc_reg_operand" "r"))
8559 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8560 (match_operand:SI 5 "gpc_reg_operand" "r"))
8561 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8562 (match_operand:SI 6 "gpc_reg_operand" "r"))
8563 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8564 (match_operand:SI 7 "gpc_reg_operand" "r"))
8565 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8566 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8567 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8568 "{stsi|stswi} %2,%1,%O0"
8569 [(set_attr "type" "store")])
8571 (define_insn "*stmsi5"
8572 [(match_parallel 0 "store_multiple_operation"
8573 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8574 (match_operand:SI 2 "gpc_reg_operand" "r"))
8575 (clobber (match_scratch:SI 3 "X"))
8576 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8577 (match_operand:SI 4 "gpc_reg_operand" "r"))
8578 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8579 (match_operand:SI 5 "gpc_reg_operand" "r"))
8580 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8581 (match_operand:SI 6 "gpc_reg_operand" "r"))
8582 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8583 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8584 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8585 "{stsi|stswi} %2,%1,%O0"
8586 [(set_attr "type" "store")])
8588 (define_insn "*stmsi4"
8589 [(match_parallel 0 "store_multiple_operation"
8590 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8591 (match_operand:SI 2 "gpc_reg_operand" "r"))
8592 (clobber (match_scratch:SI 3 "X"))
8593 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8594 (match_operand:SI 4 "gpc_reg_operand" "r"))
8595 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8596 (match_operand:SI 5 "gpc_reg_operand" "r"))
8597 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8598 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8599 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8600 "{stsi|stswi} %2,%1,%O0"
8601 [(set_attr "type" "store")])
8603 (define_insn "*stmsi3"
8604 [(match_parallel 0 "store_multiple_operation"
8605 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8606 (match_operand:SI 2 "gpc_reg_operand" "r"))
8607 (clobber (match_scratch:SI 3 "X"))
8608 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8609 (match_operand:SI 4 "gpc_reg_operand" "r"))
8610 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8611 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8612 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8613 "{stsi|stswi} %2,%1,%O0"
8614 [(set_attr "type" "store")])
8615 \f
8616 (define_expand "clrmemsi"
8617 [(parallel [(set (match_operand:BLK 0 "" "")
8618 (const_int 0))
8619 (use (match_operand:SI 1 "" ""))
8620 (use (match_operand:SI 2 "" ""))])]
8621 ""
8622 "
8623 {
8624 if (expand_block_clear (operands))
8625 DONE;
8626 else
8627 FAIL;
8628 }")
8630 ;; String/block move insn.
8631 ;; Argument 0 is the destination
8632 ;; Argument 1 is the source
8633 ;; Argument 2 is the length
8634 ;; Argument 3 is the alignment
8636 (define_expand "movmemsi"
8637 [(parallel [(set (match_operand:BLK 0 "" "")
8638 (match_operand:BLK 1 "" ""))
8639 (use (match_operand:SI 2 "" ""))
8640 (use (match_operand:SI 3 "" ""))])]
8641 ""
8642 "
8643 {
8644 if (expand_block_move (operands))
8645 DONE;
8646 else
8647 FAIL;
8648 }")
8650 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8651 ;; register allocator doesn't have a clue about allocating 8 word registers.
8652 ;; rD/rS = r5 is preferred, efficient form.
8653 (define_expand "movmemsi_8reg"
8654 [(parallel [(set (match_operand 0 "" "")
8655 (match_operand 1 "" ""))
8656 (use (match_operand 2 "" ""))
8657 (use (match_operand 3 "" ""))
8658 (clobber (reg:SI 5))
8659 (clobber (reg:SI 6))
8660 (clobber (reg:SI 7))
8661 (clobber (reg:SI 8))
8662 (clobber (reg:SI 9))
8663 (clobber (reg:SI 10))
8664 (clobber (reg:SI 11))
8665 (clobber (reg:SI 12))
8666 (clobber (match_scratch:SI 4 ""))])]
8667 "TARGET_STRING"
8668 "")
8670 (define_insn ""
8671 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8672 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8673 (use (match_operand:SI 2 "immediate_operand" "i"))
8674 (use (match_operand:SI 3 "immediate_operand" "i"))
8675 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8676 (clobber (reg:SI 6))
8677 (clobber (reg:SI 7))
8678 (clobber (reg:SI 8))
8679 (clobber (reg:SI 9))
8680 (clobber (reg:SI 10))
8681 (clobber (reg:SI 11))
8682 (clobber (reg:SI 12))
8683 (clobber (match_scratch:SI 5 "=q"))]
8684 "TARGET_STRING && TARGET_POWER
8685 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8686 || INTVAL (operands[2]) == 0)
8687 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8688 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8689 && REGNO (operands[4]) == 5"
8690 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8691 [(set_attr "type" "load")
8692 (set_attr "length" "8")])
8694 (define_insn ""
8695 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8696 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8697 (use (match_operand:SI 2 "immediate_operand" "i"))
8698 (use (match_operand:SI 3 "immediate_operand" "i"))
8699 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8700 (clobber (reg:SI 6))
8701 (clobber (reg:SI 7))
8702 (clobber (reg:SI 8))
8703 (clobber (reg:SI 9))
8704 (clobber (reg:SI 10))
8705 (clobber (reg:SI 11))
8706 (clobber (reg:SI 12))
8707 (clobber (match_scratch:SI 5 "X"))]
8708 "TARGET_STRING && ! TARGET_POWER
8709 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8710 || INTVAL (operands[2]) == 0)
8711 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8712 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8713 && REGNO (operands[4]) == 5"
8714 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8715 [(set_attr "type" "load")
8716 (set_attr "length" "8")])
8718 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8719 ;; register allocator doesn't have a clue about allocating 6 word registers.
8720 ;; rD/rS = r5 is preferred, efficient form.
8721 (define_expand "movmemsi_6reg"
8722 [(parallel [(set (match_operand 0 "" "")
8723 (match_operand 1 "" ""))
8724 (use (match_operand 2 "" ""))
8725 (use (match_operand 3 "" ""))
8726 (clobber (reg:SI 5))
8727 (clobber (reg:SI 6))
8728 (clobber (reg:SI 7))
8729 (clobber (reg:SI 8))
8730 (clobber (reg:SI 9))
8731 (clobber (reg:SI 10))
8732 (clobber (match_scratch:SI 4 ""))])]
8733 "TARGET_STRING"
8734 "")
8736 (define_insn ""
8737 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8738 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8739 (use (match_operand:SI 2 "immediate_operand" "i"))
8740 (use (match_operand:SI 3 "immediate_operand" "i"))
8741 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8742 (clobber (reg:SI 6))
8743 (clobber (reg:SI 7))
8744 (clobber (reg:SI 8))
8745 (clobber (reg:SI 9))
8746 (clobber (reg:SI 10))
8747 (clobber (match_scratch:SI 5 "=q"))]
8748 "TARGET_STRING && TARGET_POWER
8749 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8750 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8751 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8752 && REGNO (operands[4]) == 5"
8753 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8754 [(set_attr "type" "load")
8755 (set_attr "length" "8")])
8757 (define_insn ""
8758 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8759 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8760 (use (match_operand:SI 2 "immediate_operand" "i"))
8761 (use (match_operand:SI 3 "immediate_operand" "i"))
8762 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8763 (clobber (reg:SI 6))
8764 (clobber (reg:SI 7))
8765 (clobber (reg:SI 8))
8766 (clobber (reg:SI 9))
8767 (clobber (reg:SI 10))
8768 (clobber (match_scratch:SI 5 "X"))]
8769 "TARGET_STRING && ! TARGET_POWER
8770 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8771 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8772 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8773 && REGNO (operands[4]) == 5"
8774 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8775 [(set_attr "type" "load")
8776 (set_attr "length" "8")])
8778 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8779 ;; problems with TImode.
8780 ;; rD/rS = r5 is preferred, efficient form.
8781 (define_expand "movmemsi_4reg"
8782 [(parallel [(set (match_operand 0 "" "")
8783 (match_operand 1 "" ""))
8784 (use (match_operand 2 "" ""))
8785 (use (match_operand 3 "" ""))
8786 (clobber (reg:SI 5))
8787 (clobber (reg:SI 6))
8788 (clobber (reg:SI 7))
8789 (clobber (reg:SI 8))
8790 (clobber (match_scratch:SI 4 ""))])]
8791 "TARGET_STRING"
8792 "")
8794 (define_insn ""
8795 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8796 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8797 (use (match_operand:SI 2 "immediate_operand" "i"))
8798 (use (match_operand:SI 3 "immediate_operand" "i"))
8799 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8800 (clobber (reg:SI 6))
8801 (clobber (reg:SI 7))
8802 (clobber (reg:SI 8))
8803 (clobber (match_scratch:SI 5 "=q"))]
8804 "TARGET_STRING && TARGET_POWER
8805 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8806 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8807 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8808 && REGNO (operands[4]) == 5"
8809 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8810 [(set_attr "type" "load")
8811 (set_attr "length" "8")])
8813 (define_insn ""
8814 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8815 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8816 (use (match_operand:SI 2 "immediate_operand" "i"))
8817 (use (match_operand:SI 3 "immediate_operand" "i"))
8818 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8819 (clobber (reg:SI 6))
8820 (clobber (reg:SI 7))
8821 (clobber (reg:SI 8))
8822 (clobber (match_scratch:SI 5 "X"))]
8823 "TARGET_STRING && ! TARGET_POWER
8824 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8825 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8826 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8827 && REGNO (operands[4]) == 5"
8828 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8829 [(set_attr "type" "load")
8830 (set_attr "length" "8")])
8832 ;; Move up to 8 bytes at a time.
8833 (define_expand "movmemsi_2reg"
8834 [(parallel [(set (match_operand 0 "" "")
8835 (match_operand 1 "" ""))
8836 (use (match_operand 2 "" ""))
8837 (use (match_operand 3 "" ""))
8838 (clobber (match_scratch:DI 4 ""))
8839 (clobber (match_scratch:SI 5 ""))])]
8840 "TARGET_STRING && ! TARGET_POWERPC64"
8841 "")
8843 (define_insn ""
8844 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8845 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8846 (use (match_operand:SI 2 "immediate_operand" "i"))
8847 (use (match_operand:SI 3 "immediate_operand" "i"))
8848 (clobber (match_scratch:DI 4 "=&r"))
8849 (clobber (match_scratch:SI 5 "=q"))]
8850 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8851 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8852 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8853 [(set_attr "type" "load")
8854 (set_attr "length" "8")])
8856 (define_insn ""
8857 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8858 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8859 (use (match_operand:SI 2 "immediate_operand" "i"))
8860 (use (match_operand:SI 3 "immediate_operand" "i"))
8861 (clobber (match_scratch:DI 4 "=&r"))
8862 (clobber (match_scratch:SI 5 "X"))]
8863 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8864 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8865 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8866 [(set_attr "type" "load")
8867 (set_attr "length" "8")])
8869 ;; Move up to 4 bytes at a time.
8870 (define_expand "movmemsi_1reg"
8871 [(parallel [(set (match_operand 0 "" "")
8872 (match_operand 1 "" ""))
8873 (use (match_operand 2 "" ""))
8874 (use (match_operand 3 "" ""))
8875 (clobber (match_scratch:SI 4 ""))
8876 (clobber (match_scratch:SI 5 ""))])]
8877 "TARGET_STRING"
8878 "")
8880 (define_insn ""
8881 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8882 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8883 (use (match_operand:SI 2 "immediate_operand" "i"))
8884 (use (match_operand:SI 3 "immediate_operand" "i"))
8885 (clobber (match_scratch:SI 4 "=&r"))
8886 (clobber (match_scratch:SI 5 "=q"))]
8887 "TARGET_STRING && TARGET_POWER
8888 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8889 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8890 [(set_attr "type" "load")
8891 (set_attr "length" "8")])
8893 (define_insn ""
8894 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8895 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8896 (use (match_operand:SI 2 "immediate_operand" "i"))
8897 (use (match_operand:SI 3 "immediate_operand" "i"))
8898 (clobber (match_scratch:SI 4 "=&r"))
8899 (clobber (match_scratch:SI 5 "X"))]
8900 "TARGET_STRING && ! TARGET_POWER
8901 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8902 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8903 [(set_attr "type" "load")
8904 (set_attr "length" "8")])
8905 \f
8906 ;; Define insns that do load or store with update. Some of these we can
8907 ;; get by using pre-decrement or pre-increment, but the hardware can also
8908 ;; do cases where the increment is not the size of the object.
8909 ;;
8910 ;; In all these cases, we use operands 0 and 1 for the register being
8911 ;; incremented because those are the operands that local-alloc will
8912 ;; tie and these are the pair most likely to be tieable (and the ones
8913 ;; that will benefit the most).
8915 (define_insn "*movdi_update1"
8916 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8917 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8918 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8919 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8920 (plus:DI (match_dup 1) (match_dup 2)))]
8921 "TARGET_POWERPC64 && TARGET_UPDATE"
8922 "@
8923 ldux %3,%0,%2
8924 ldu %3,%2(%0)"
8925 [(set_attr "type" "load_ux,load_u")])
8927 (define_insn "movdi_<mode>_update"
8928 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8929 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8930 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8931 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8932 (plus:P (match_dup 1) (match_dup 2)))]
8933 "TARGET_POWERPC64 && TARGET_UPDATE"
8934 "@
8935 stdux %3,%0,%2
8936 stdu %3,%2(%0)"
8937 [(set_attr "type" "store_ux,store_u")])
8939 (define_insn "*movsi_update1"
8940 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8941 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8942 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8943 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8944 (plus:SI (match_dup 1) (match_dup 2)))]
8945 "TARGET_UPDATE"
8946 "@
8947 {lux|lwzux} %3,%0,%2
8948 {lu|lwzu} %3,%2(%0)"
8949 [(set_attr "type" "load_ux,load_u")])
8951 (define_insn "*movsi_update2"
8952 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8953 (sign_extend:DI
8954 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8955 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8956 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8957 (plus:DI (match_dup 1) (match_dup 2)))]
8958 "TARGET_POWERPC64"
8959 "lwaux %3,%0,%2"
8960 [(set_attr "type" "load_ext_ux")])
8962 (define_insn "movsi_update"
8963 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8964 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8965 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8966 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8967 (plus:SI (match_dup 1) (match_dup 2)))]
8968 "TARGET_UPDATE"
8969 "@
8970 {stux|stwux} %3,%0,%2
8971 {stu|stwu} %3,%2(%0)"
8972 [(set_attr "type" "store_ux,store_u")])
8974 (define_insn "*movhi_update1"
8975 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8976 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8977 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8978 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8979 (plus:SI (match_dup 1) (match_dup 2)))]
8980 "TARGET_UPDATE"
8981 "@
8982 lhzux %3,%0,%2
8983 lhzu %3,%2(%0)"
8984 [(set_attr "type" "load_ux,load_u")])
8986 (define_insn "*movhi_update2"
8987 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8988 (zero_extend:SI
8989 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8990 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8991 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8992 (plus:SI (match_dup 1) (match_dup 2)))]
8993 "TARGET_UPDATE"
8994 "@
8995 lhzux %3,%0,%2
8996 lhzu %3,%2(%0)"
8997 [(set_attr "type" "load_ux,load_u")])
8999 (define_insn "*movhi_update3"
9000 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9001 (sign_extend:SI
9002 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9003 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9004 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9005 (plus:SI (match_dup 1) (match_dup 2)))]
9006 "TARGET_UPDATE"
9007 "@
9008 lhaux %3,%0,%2
9009 lhau %3,%2(%0)"
9010 [(set_attr "type" "load_ext_ux,load_ext_u")])
9012 (define_insn "*movhi_update4"
9013 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9014 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9015 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9016 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9017 (plus:SI (match_dup 1) (match_dup 2)))]
9018 "TARGET_UPDATE"
9019 "@
9020 sthux %3,%0,%2
9021 sthu %3,%2(%0)"
9022 [(set_attr "type" "store_ux,store_u")])
9024 (define_insn "*movqi_update1"
9025 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9026 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9027 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9028 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9029 (plus:SI (match_dup 1) (match_dup 2)))]
9030 "TARGET_UPDATE"
9031 "@
9032 lbzux %3,%0,%2
9033 lbzu %3,%2(%0)"
9034 [(set_attr "type" "load_ux,load_u")])
9036 (define_insn "*movqi_update2"
9037 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9038 (zero_extend:SI
9039 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9040 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9041 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9042 (plus:SI (match_dup 1) (match_dup 2)))]
9043 "TARGET_UPDATE"
9044 "@
9045 lbzux %3,%0,%2
9046 lbzu %3,%2(%0)"
9047 [(set_attr "type" "load_ux,load_u")])
9049 (define_insn "*movqi_update3"
9050 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9051 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9052 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9053 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9054 (plus:SI (match_dup 1) (match_dup 2)))]
9055 "TARGET_UPDATE"
9056 "@
9057 stbux %3,%0,%2
9058 stbu %3,%2(%0)"
9059 [(set_attr "type" "store_ux,store_u")])
9061 (define_insn "*movsf_update1"
9062 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9063 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9064 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9065 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9066 (plus:SI (match_dup 1) (match_dup 2)))]
9067 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9068 "@
9069 lfsux %3,%0,%2
9070 lfsu %3,%2(%0)"
9071 [(set_attr "type" "fpload_ux,fpload_u")])
9073 (define_insn "*movsf_update2"
9074 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9075 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9076 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9077 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9078 (plus:SI (match_dup 1) (match_dup 2)))]
9079 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9080 "@
9081 stfsux %3,%0,%2
9082 stfsu %3,%2(%0)"
9083 [(set_attr "type" "fpstore_ux,fpstore_u")])
9085 (define_insn "*movsf_update3"
9086 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9087 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9088 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9089 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9090 (plus:SI (match_dup 1) (match_dup 2)))]
9091 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9092 "@
9093 {lux|lwzux} %3,%0,%2
9094 {lu|lwzu} %3,%2(%0)"
9095 [(set_attr "type" "load_ux,load_u")])
9097 (define_insn "*movsf_update4"
9098 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9099 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9100 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9101 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9102 (plus:SI (match_dup 1) (match_dup 2)))]
9103 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9104 "@
9105 {stux|stwux} %3,%0,%2
9106 {stu|stwu} %3,%2(%0)"
9107 [(set_attr "type" "store_ux,store_u")])
9109 (define_insn "*movdf_update1"
9110 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9111 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9112 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9113 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9114 (plus:SI (match_dup 1) (match_dup 2)))]
9115 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9116 "@
9117 lfdux %3,%0,%2
9118 lfdu %3,%2(%0)"
9119 [(set_attr "type" "fpload_ux,fpload_u")])
9121 (define_insn "*movdf_update2"
9122 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9123 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9124 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9125 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9126 (plus:SI (match_dup 1) (match_dup 2)))]
9127 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9128 "@
9129 stfdux %3,%0,%2
9130 stfdu %3,%2(%0)"
9131 [(set_attr "type" "fpstore_ux,fpstore_u")])
9133 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9135 (define_insn "*lfq_power2"
9136 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9137 (match_operand:TF 1 "memory_operand" ""))]
9138 "TARGET_POWER2
9139 && TARGET_HARD_FLOAT && TARGET_FPRS"
9140 "lfq%U1%X1 %0,%1")
9142 (define_peephole2
9143 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9144 (match_operand:DF 1 "memory_operand" ""))
9145 (set (match_operand:DF 2 "gpc_reg_operand" "")
9146 (match_operand:DF 3 "memory_operand" ""))]
9147 "TARGET_POWER2
9148 && TARGET_HARD_FLOAT && TARGET_FPRS
9149 && registers_ok_for_quad_peep (operands[0], operands[2])
9150 && mems_ok_for_quad_peep (operands[1], operands[3])"
9151 [(set (match_dup 0)
9152 (match_dup 1))]
9153 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9154 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9156 (define_insn "*stfq_power2"
9157 [(set (match_operand:TF 0 "memory_operand" "")
9158 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9159 "TARGET_POWER2
9160 && TARGET_HARD_FLOAT && TARGET_FPRS"
9161 "stfq%U0%X0 %1,%0")
9164 (define_peephole2
9165 [(set (match_operand:DF 0 "memory_operand" "")
9166 (match_operand:DF 1 "gpc_reg_operand" ""))
9167 (set (match_operand:DF 2 "memory_operand" "")
9168 (match_operand:DF 3 "gpc_reg_operand" ""))]
9169 "TARGET_POWER2
9170 && TARGET_HARD_FLOAT && TARGET_FPRS
9171 && registers_ok_for_quad_peep (operands[1], operands[3])
9172 && mems_ok_for_quad_peep (operands[0], operands[2])"
9173 [(set (match_dup 0)
9174 (match_dup 1))]
9175 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9176 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9178 ;; after inserting conditional returns we can sometimes have
9179 ;; unnecessary register moves. Unfortunately we cannot have a
9180 ;; modeless peephole here, because some single SImode sets have early
9181 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9182 ;; sequences, using get_attr_length here will smash the operands
9183 ;; array. Neither is there an early_cobbler_p predicate.
9184 (define_peephole2
9185 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9186 (match_operand:DF 1 "any_operand" ""))
9187 (set (match_operand:DF 2 "gpc_reg_operand" "")
9188 (match_dup 0))]
9189 "peep2_reg_dead_p (2, operands[0])"
9190 [(set (match_dup 2) (match_dup 1))])
9192 (define_peephole2
9193 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9194 (match_operand:SF 1 "any_operand" ""))
9195 (set (match_operand:SF 2 "gpc_reg_operand" "")
9196 (match_dup 0))]
9197 "peep2_reg_dead_p (2, operands[0])"
9198 [(set (match_dup 2) (match_dup 1))])
9200 \f
9201 ;; TLS support.
9203 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9204 (define_insn "tls_gd_32"
9205 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9206 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9207 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9208 UNSPEC_TLSGD))]
9209 "HAVE_AS_TLS && !TARGET_64BIT"
9210 "addi %0,%1,%2@got@tlsgd")
9212 (define_insn "tls_gd_64"
9213 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9214 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9215 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9216 UNSPEC_TLSGD))]
9217 "HAVE_AS_TLS && TARGET_64BIT"
9218 "addi %0,%1,%2@got@tlsgd")
9220 (define_insn "tls_ld_32"
9221 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9222 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9223 UNSPEC_TLSLD))]
9224 "HAVE_AS_TLS && !TARGET_64BIT"
9225 "addi %0,%1,%&@got@tlsld")
9227 (define_insn "tls_ld_64"
9228 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9229 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9230 UNSPEC_TLSLD))]
9231 "HAVE_AS_TLS && TARGET_64BIT"
9232 "addi %0,%1,%&@got@tlsld")
9234 (define_insn "tls_dtprel_32"
9235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9236 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9237 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9238 UNSPEC_TLSDTPREL))]
9239 "HAVE_AS_TLS && !TARGET_64BIT"
9240 "addi %0,%1,%2@dtprel")
9242 (define_insn "tls_dtprel_64"
9243 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9244 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9245 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9246 UNSPEC_TLSDTPREL))]
9247 "HAVE_AS_TLS && TARGET_64BIT"
9248 "addi %0,%1,%2@dtprel")
9250 (define_insn "tls_dtprel_ha_32"
9251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9252 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9253 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9254 UNSPEC_TLSDTPRELHA))]
9255 "HAVE_AS_TLS && !TARGET_64BIT"
9256 "addis %0,%1,%2@dtprel@ha")
9258 (define_insn "tls_dtprel_ha_64"
9259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9260 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9261 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9262 UNSPEC_TLSDTPRELHA))]
9263 "HAVE_AS_TLS && TARGET_64BIT"
9264 "addis %0,%1,%2@dtprel@ha")
9266 (define_insn "tls_dtprel_lo_32"
9267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9268 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9269 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9270 UNSPEC_TLSDTPRELLO))]
9271 "HAVE_AS_TLS && !TARGET_64BIT"
9272 "addi %0,%1,%2@dtprel@l")
9274 (define_insn "tls_dtprel_lo_64"
9275 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9276 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9277 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9278 UNSPEC_TLSDTPRELLO))]
9279 "HAVE_AS_TLS && TARGET_64BIT"
9280 "addi %0,%1,%2@dtprel@l")
9282 (define_insn "tls_got_dtprel_32"
9283 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9284 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9285 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9286 UNSPEC_TLSGOTDTPREL))]
9287 "HAVE_AS_TLS && !TARGET_64BIT"
9288 "lwz %0,%2@got@dtprel(%1)")
9290 (define_insn "tls_got_dtprel_64"
9291 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9292 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9293 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9294 UNSPEC_TLSGOTDTPREL))]
9295 "HAVE_AS_TLS && TARGET_64BIT"
9296 "ld %0,%2@got@dtprel(%1)")
9298 (define_insn "tls_tprel_32"
9299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9300 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9301 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9302 UNSPEC_TLSTPREL))]
9303 "HAVE_AS_TLS && !TARGET_64BIT"
9304 "addi %0,%1,%2@tprel")
9306 (define_insn "tls_tprel_64"
9307 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9308 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9309 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9310 UNSPEC_TLSTPREL))]
9311 "HAVE_AS_TLS && TARGET_64BIT"
9312 "addi %0,%1,%2@tprel")
9314 (define_insn "tls_tprel_ha_32"
9315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9316 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9317 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9318 UNSPEC_TLSTPRELHA))]
9319 "HAVE_AS_TLS && !TARGET_64BIT"
9320 "addis %0,%1,%2@tprel@ha")
9322 (define_insn "tls_tprel_ha_64"
9323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9324 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9325 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9326 UNSPEC_TLSTPRELHA))]
9327 "HAVE_AS_TLS && TARGET_64BIT"
9328 "addis %0,%1,%2@tprel@ha")
9330 (define_insn "tls_tprel_lo_32"
9331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9332 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9333 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9334 UNSPEC_TLSTPRELLO))]
9335 "HAVE_AS_TLS && !TARGET_64BIT"
9336 "addi %0,%1,%2@tprel@l")
9338 (define_insn "tls_tprel_lo_64"
9339 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9340 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9341 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9342 UNSPEC_TLSTPRELLO))]
9343 "HAVE_AS_TLS && TARGET_64BIT"
9344 "addi %0,%1,%2@tprel@l")
9346 ;; "b" output constraint here and on tls_tls input to support linker tls
9347 ;; optimization. The linker may edit the instructions emitted by a
9348 ;; tls_got_tprel/tls_tls pair to addis,addi.
9349 (define_insn "tls_got_tprel_32"
9350 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9351 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9352 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9353 UNSPEC_TLSGOTTPREL))]
9354 "HAVE_AS_TLS && !TARGET_64BIT"
9355 "lwz %0,%2@got@tprel(%1)")
9357 (define_insn "tls_got_tprel_64"
9358 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9359 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9360 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9361 UNSPEC_TLSGOTTPREL))]
9362 "HAVE_AS_TLS && TARGET_64BIT"
9363 "ld %0,%2@got@tprel(%1)")
9365 (define_insn "tls_tls_32"
9366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9367 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9368 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9369 UNSPEC_TLSTLS))]
9370 "HAVE_AS_TLS && !TARGET_64BIT"
9371 "add %0,%1,%2@tls")
9373 (define_insn "tls_tls_64"
9374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9375 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9376 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9377 UNSPEC_TLSTLS))]
9378 "HAVE_AS_TLS && TARGET_64BIT"
9379 "add %0,%1,%2@tls")
9380 \f
9381 ;; Next come insns related to the calling sequence.
9382 ;;
9383 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9384 ;; We move the back-chain and decrement the stack pointer.
9386 (define_expand "allocate_stack"
9387 [(set (match_operand 0 "gpc_reg_operand" "=r")
9388 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9389 (set (reg 1)
9390 (minus (reg 1) (match_dup 1)))]
9391 ""
9392 "
9393 { rtx chain = gen_reg_rtx (Pmode);
9394 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9395 rtx neg_op0;
9397 emit_move_insn (chain, stack_bot);
9399 /* Check stack bounds if necessary. */
9400 if (current_function_limit_stack)
9401 {
9402 rtx available;
9403 available = expand_binop (Pmode, sub_optab,
9404 stack_pointer_rtx, stack_limit_rtx,
9405 NULL_RTX, 1, OPTAB_WIDEN);
9406 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9407 }
9409 if (GET_CODE (operands[1]) != CONST_INT
9410 || INTVAL (operands[1]) < -32767
9411 || INTVAL (operands[1]) > 32768)
9412 {
9413 neg_op0 = gen_reg_rtx (Pmode);
9414 if (TARGET_32BIT)
9415 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9416 else
9417 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9418 }
9419 else
9420 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9422 if (TARGET_UPDATE)
9423 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9424 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9426 else
9427 {
9428 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9429 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9430 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9431 }
9433 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9434 DONE;
9435 }")
9437 ;; These patterns say how to save and restore the stack pointer. We need not
9438 ;; save the stack pointer at function level since we are careful to
9439 ;; preserve the backchain. At block level, we have to restore the backchain
9440 ;; when we restore the stack pointer.
9441 ;;
9442 ;; For nonlocal gotos, we must save both the stack pointer and its
9443 ;; backchain and restore both. Note that in the nonlocal case, the
9444 ;; save area is a memory location.
9446 (define_expand "save_stack_function"
9447 [(match_operand 0 "any_operand" "")
9448 (match_operand 1 "any_operand" "")]
9449 ""
9450 "DONE;")
9452 (define_expand "restore_stack_function"
9453 [(match_operand 0 "any_operand" "")
9454 (match_operand 1 "any_operand" "")]
9455 ""
9456 "DONE;")
9458 (define_expand "restore_stack_block"
9459 [(use (match_operand 0 "register_operand" ""))
9460 (set (match_dup 2) (match_dup 3))
9461 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9462 (set (match_dup 3) (match_dup 2))]
9463 ""
9464 "
9465 {
9466 operands[2] = gen_reg_rtx (Pmode);
9467 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9468 }")
9470 (define_expand "save_stack_nonlocal"
9471 [(match_operand 0 "memory_operand" "")
9472 (match_operand 1 "register_operand" "")]
9473 ""
9474 "
9475 {
9476 rtx temp = gen_reg_rtx (Pmode);
9477 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9479 /* Copy the backchain to the first word, sp to the second. */
9480 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9481 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9482 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9483 operands[1]);
9484 DONE;
9485 }")
9487 (define_expand "restore_stack_nonlocal"
9488 [(match_operand 0 "register_operand" "")
9489 (match_operand 1 "memory_operand" "")]
9490 ""
9491 "
9492 {
9493 rtx temp = gen_reg_rtx (Pmode);
9494 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9496 /* Restore the backchain from the first word, sp from the second. */
9497 emit_move_insn (temp,
9498 adjust_address_nv (operands[1], Pmode, 0));
9499 emit_move_insn (operands[0],
9500 adjust_address_nv (operands[1], Pmode, units_per_word));
9501 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9502 DONE;
9503 }")
9504 \f
9505 ;; TOC register handling.
9507 ;; Code to initialize the TOC register...
9509 (define_insn "load_toc_aix_si"
9510 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9511 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9512 (use (reg:SI 2))])]
9513 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9514 "*
9515 {
9516 char buf[30];
9517 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9518 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9519 operands[2] = gen_rtx_REG (Pmode, 2);
9520 return \"{l|lwz} %0,%1(%2)\";
9521 }"
9522 [(set_attr "type" "load")])
9524 (define_insn "load_toc_aix_di"
9525 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9526 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9527 (use (reg:DI 2))])]
9528 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9529 "*
9530 {
9531 char buf[30];
9532 #ifdef TARGET_RELOCATABLE
9533 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9534 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9535 #else
9536 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9537 #endif
9538 if (TARGET_ELF)
9539 strcat (buf, \"@toc\");
9540 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9541 operands[2] = gen_rtx_REG (Pmode, 2);
9542 return \"ld %0,%1(%2)\";
9543 }"
9544 [(set_attr "type" "load")])
9546 (define_insn "load_toc_v4_pic_si"
9547 [(set (match_operand:SI 0 "register_operand" "=l")
9548 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9549 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9550 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9551 [(set_attr "type" "branch")
9552 (set_attr "length" "4")])
9554 (define_insn "load_toc_v4_PIC_1"
9555 [(set (match_operand:SI 0 "register_operand" "=l")
9556 (match_operand:SI 1 "immediate_operand" "s"))
9557 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9558 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9559 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9560 "bcl 20,31,%1\\n%1:"
9561 [(set_attr "type" "branch")
9562 (set_attr "length" "4")])
9564 (define_insn "load_toc_v4_PIC_1b"
9565 [(set (match_operand:SI 0 "register_operand" "=l")
9566 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9567 UNSPEC_TOCPTR))]
9568 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9569 "bcl 20,31,$+8\\n\\t.long %1-$"
9570 [(set_attr "type" "branch")
9571 (set_attr "length" "8")])
9573 (define_insn "load_toc_v4_PIC_2"
9574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9575 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9576 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9577 (match_operand:SI 3 "immediate_operand" "s")))))]
9578 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9579 "{l|lwz} %0,%2-%3(%1)"
9580 [(set_attr "type" "load")])
9582 (define_insn "load_toc_v4_PIC_3b"
9583 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9584 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9585 (high:SI
9586 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9587 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9588 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9589 "{cau|addis} %0,%1,%2-%3@ha")
9591 (define_insn "load_toc_v4_PIC_3c"
9592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9593 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9594 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9595 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9596 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9597 "{cal|addi} %0,%1,%2-%3@l")
9599 ;; If the TOC is shared over a translation unit, as happens with all
9600 ;; the kinds of PIC that we support, we need to restore the TOC
9601 ;; pointer only when jumping over units of translation.
9602 ;; On Darwin, we need to reload the picbase.
9604 (define_expand "builtin_setjmp_receiver"
9605 [(use (label_ref (match_operand 0 "" "")))]
9606 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9607 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9608 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9609 "
9610 {
9611 #if TARGET_MACHO
9612 if (DEFAULT_ABI == ABI_DARWIN)
9613 {
9614 const char *picbase = machopic_function_base_name ();
9615 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9616 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9617 rtx tmplabrtx;
9618 char tmplab[20];
9620 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9621 CODE_LABEL_NUMBER (operands[0]));
9622 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9624 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9625 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9626 }
9627 else
9628 #endif
9629 rs6000_emit_load_toc_table (FALSE);
9630 DONE;
9631 }")
9633 ;; Elf specific ways of loading addresses for non-PIC code.
9634 ;; The output of this could be r0, but we make a very strong
9635 ;; preference for a base register because it will usually
9636 ;; be needed there.
9637 (define_insn "elf_high"
9638 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9639 (high:SI (match_operand 1 "" "")))]
9640 "TARGET_ELF && ! TARGET_64BIT"
9641 "{liu|lis} %0,%1@ha")
9643 (define_insn "elf_low"
9644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9645 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9646 (match_operand 2 "" "")))]
9647 "TARGET_ELF && ! TARGET_64BIT"
9648 "@
9649 {cal|la} %0,%2@l(%1)
9650 {ai|addic} %0,%1,%K2")
9651 \f
9652 ;; A function pointer under AIX is a pointer to a data area whose first word
9653 ;; contains the actual address of the function, whose second word contains a
9654 ;; pointer to its TOC, and whose third word contains a value to place in the
9655 ;; static chain register (r11). Note that if we load the static chain, our
9656 ;; "trampoline" need not have any executable code.
9658 (define_expand "call_indirect_aix32"
9659 [(set (match_dup 2)
9660 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9661 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9662 (reg:SI 2))
9663 (set (reg:SI 2)
9664 (mem:SI (plus:SI (match_dup 0)
9665 (const_int 4))))
9666 (set (reg:SI 11)
9667 (mem:SI (plus:SI (match_dup 0)
9668 (const_int 8))))
9669 (parallel [(call (mem:SI (match_dup 2))
9670 (match_operand 1 "" ""))
9671 (use (reg:SI 2))
9672 (use (reg:SI 11))
9673 (set (reg:SI 2)
9674 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9675 (clobber (scratch:SI))])]
9676 "TARGET_32BIT"
9677 "
9678 { operands[2] = gen_reg_rtx (SImode); }")
9680 (define_expand "call_indirect_aix64"
9681 [(set (match_dup 2)
9682 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9683 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9684 (reg:DI 2))
9685 (set (reg:DI 2)
9686 (mem:DI (plus:DI (match_dup 0)
9687 (const_int 8))))
9688 (set (reg:DI 11)
9689 (mem:DI (plus:DI (match_dup 0)
9690 (const_int 16))))
9691 (parallel [(call (mem:SI (match_dup 2))
9692 (match_operand 1 "" ""))
9693 (use (reg:DI 2))
9694 (use (reg:DI 11))
9695 (set (reg:DI 2)
9696 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9697 (clobber (scratch:SI))])]
9698 "TARGET_64BIT"
9699 "
9700 { operands[2] = gen_reg_rtx (DImode); }")
9702 (define_expand "call_value_indirect_aix32"
9703 [(set (match_dup 3)
9704 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9705 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9706 (reg:SI 2))
9707 (set (reg:SI 2)
9708 (mem:SI (plus:SI (match_dup 1)
9709 (const_int 4))))
9710 (set (reg:SI 11)
9711 (mem:SI (plus:SI (match_dup 1)
9712 (const_int 8))))
9713 (parallel [(set (match_operand 0 "" "")
9714 (call (mem:SI (match_dup 3))
9715 (match_operand 2 "" "")))
9716 (use (reg:SI 2))
9717 (use (reg:SI 11))
9718 (set (reg:SI 2)
9719 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9720 (clobber (scratch:SI))])]
9721 "TARGET_32BIT"
9722 "
9723 { operands[3] = gen_reg_rtx (SImode); }")
9725 (define_expand "call_value_indirect_aix64"
9726 [(set (match_dup 3)
9727 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9728 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9729 (reg:DI 2))
9730 (set (reg:DI 2)
9731 (mem:DI (plus:DI (match_dup 1)
9732 (const_int 8))))
9733 (set (reg:DI 11)
9734 (mem:DI (plus:DI (match_dup 1)
9735 (const_int 16))))
9736 (parallel [(set (match_operand 0 "" "")
9737 (call (mem:SI (match_dup 3))
9738 (match_operand 2 "" "")))
9739 (use (reg:DI 2))
9740 (use (reg:DI 11))
9741 (set (reg:DI 2)
9742 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9743 (clobber (scratch:SI))])]
9744 "TARGET_64BIT"
9745 "
9746 { operands[3] = gen_reg_rtx (DImode); }")
9748 ;; Now the definitions for the call and call_value insns
9749 (define_expand "call"
9750 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9751 (match_operand 1 "" ""))
9752 (use (match_operand 2 "" ""))
9753 (clobber (scratch:SI))])]
9754 ""
9755 "
9756 {
9757 #if TARGET_MACHO
9758 if (MACHOPIC_INDIRECT)
9759 operands[0] = machopic_indirect_call_target (operands[0]);
9760 #endif
9762 gcc_assert (GET_CODE (operands[0]) == MEM);
9763 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
9765 operands[0] = XEXP (operands[0], 0);
9767 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9768 && flag_pic
9769 && GET_CODE (operands[0]) == SYMBOL_REF
9770 && !SYMBOL_REF_LOCAL_P (operands[0]))
9771 {
9772 rtx call;
9773 rtvec tmp;
9775 tmp = gen_rtvec (3,
9776 gen_rtx_CALL (VOIDmode,
9777 gen_rtx_MEM (SImode, operands[0]),
9778 operands[1]),
9779 gen_rtx_USE (VOIDmode, operands[2]),
9780 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9781 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9782 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9783 DONE;
9784 }
9786 if (GET_CODE (operands[0]) != SYMBOL_REF
9787 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
9788 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
9789 {
9790 if (INTVAL (operands[2]) & CALL_LONG)
9791 operands[0] = rs6000_longcall_ref (operands[0]);
9793 switch (DEFAULT_ABI)
9794 {
9795 case ABI_V4:
9796 case ABI_DARWIN:
9797 operands[0] = force_reg (Pmode, operands[0]);
9798 break;
9800 case ABI_AIX:
9801 /* AIX function pointers are really pointers to a three word
9802 area. */
9803 emit_call_insn (TARGET_32BIT
9804 ? gen_call_indirect_aix32 (force_reg (SImode,
9805 operands[0]),
9806 operands[1])
9807 : gen_call_indirect_aix64 (force_reg (DImode,
9808 operands[0]),
9809 operands[1]));
9810 DONE;
9812 default:
9813 gcc_unreachable ();
9814 }
9815 }
9816 }")
9818 (define_expand "call_value"
9819 [(parallel [(set (match_operand 0 "" "")
9820 (call (mem:SI (match_operand 1 "address_operand" ""))
9821 (match_operand 2 "" "")))
9822 (use (match_operand 3 "" ""))
9823 (clobber (scratch:SI))])]
9824 ""
9825 "
9826 {
9827 #if TARGET_MACHO
9828 if (MACHOPIC_INDIRECT)
9829 operands[1] = machopic_indirect_call_target (operands[1]);
9830 #endif
9832 gcc_assert (GET_CODE (operands[1]) == MEM);
9833 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
9835 operands[1] = XEXP (operands[1], 0);
9837 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
9838 && flag_pic
9839 && GET_CODE (operands[1]) == SYMBOL_REF
9840 && !SYMBOL_REF_LOCAL_P (operands[1]))
9841 {
9842 rtx call;
9843 rtvec tmp;
9845 tmp = gen_rtvec (3,
9846 gen_rtx_SET (VOIDmode,
9847 operands[0],
9848 gen_rtx_CALL (VOIDmode,
9849 gen_rtx_MEM (SImode,
9850 operands[1]),
9851 operands[2])),
9852 gen_rtx_USE (VOIDmode, operands[3]),
9853 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
9854 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
9855 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
9856 DONE;
9857 }
9859 if (GET_CODE (operands[1]) != SYMBOL_REF
9860 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
9861 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
9862 {
9863 if (INTVAL (operands[3]) & CALL_LONG)
9864 operands[1] = rs6000_longcall_ref (operands[1]);
9866 switch (DEFAULT_ABI)
9867 {
9868 case ABI_V4:
9869 case ABI_DARWIN:
9870 operands[1] = force_reg (Pmode, operands[1]);
9871 break;
9873 case ABI_AIX:
9874 /* AIX function pointers are really pointers to a three word
9875 area. */
9876 emit_call_insn (TARGET_32BIT
9877 ? gen_call_value_indirect_aix32 (operands[0],
9878 force_reg (SImode,
9879 operands[1]),
9880 operands[2])
9881 : gen_call_value_indirect_aix64 (operands[0],
9882 force_reg (DImode,
9883 operands[1]),
9884 operands[2]));
9885 DONE;
9887 default:
9888 gcc_unreachable ();
9889 }
9890 }
9891 }")
9893 ;; Call to function in current module. No TOC pointer reload needed.
9894 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9895 ;; either the function was not prototyped, or it was prototyped as a
9896 ;; variable argument function. It is > 0 if FP registers were passed
9897 ;; and < 0 if they were not.
9899 (define_insn "*call_local32"
9900 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9901 (match_operand 1 "" "g,g"))
9902 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9903 (clobber (match_scratch:SI 3 "=l,l"))]
9904 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9905 "*
9906 {
9907 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9908 output_asm_insn (\"crxor 6,6,6\", operands);
9910 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9911 output_asm_insn (\"creqv 6,6,6\", operands);
9913 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9914 }"
9915 [(set_attr "type" "branch")
9916 (set_attr "length" "4,8")])
9918 (define_insn "*call_local64"
9919 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9920 (match_operand 1 "" "g,g"))
9921 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9922 (clobber (match_scratch:SI 3 "=l,l"))]
9923 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9924 "*
9925 {
9926 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9927 output_asm_insn (\"crxor 6,6,6\", operands);
9929 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9930 output_asm_insn (\"creqv 6,6,6\", operands);
9932 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9933 }"
9934 [(set_attr "type" "branch")
9935 (set_attr "length" "4,8")])
9937 (define_insn "*call_value_local32"
9938 [(set (match_operand 0 "" "")
9939 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9940 (match_operand 2 "" "g,g")))
9941 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9942 (clobber (match_scratch:SI 4 "=l,l"))]
9943 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9944 "*
9945 {
9946 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9947 output_asm_insn (\"crxor 6,6,6\", operands);
9949 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9950 output_asm_insn (\"creqv 6,6,6\", operands);
9952 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9953 }"
9954 [(set_attr "type" "branch")
9955 (set_attr "length" "4,8")])
9958 (define_insn "*call_value_local64"
9959 [(set (match_operand 0 "" "")
9960 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9961 (match_operand 2 "" "g,g")))
9962 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9963 (clobber (match_scratch:SI 4 "=l,l"))]
9964 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9965 "*
9966 {
9967 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9968 output_asm_insn (\"crxor 6,6,6\", operands);
9970 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9971 output_asm_insn (\"creqv 6,6,6\", operands);
9973 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9974 }"
9975 [(set_attr "type" "branch")
9976 (set_attr "length" "4,8")])
9978 ;; Call to function which may be in another module. Restore the TOC
9979 ;; pointer (r2) after the call unless this is System V.
9980 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
9981 ;; either the function was not prototyped, or it was prototyped as a
9982 ;; variable argument function. It is > 0 if FP registers were passed
9983 ;; and < 0 if they were not.
9985 (define_insn "*call_indirect_nonlocal_aix32"
9986 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
9987 (match_operand 1 "" "g,g"))
9988 (use (reg:SI 2))
9989 (use (reg:SI 11))
9990 (set (reg:SI 2)
9991 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9992 (clobber (match_scratch:SI 2 "=l,l"))]
9993 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9994 "b%T0l\;{l|lwz} 2,20(1)"
9995 [(set_attr "type" "jmpreg")
9996 (set_attr "length" "8")])
9998 (define_insn "*call_nonlocal_aix32"
9999 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10000 (match_operand 1 "" "g"))
10001 (use (match_operand:SI 2 "immediate_operand" "O"))
10002 (clobber (match_scratch:SI 3 "=l"))]
10003 "TARGET_32BIT
10004 && DEFAULT_ABI == ABI_AIX
10005 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10006 "bl %z0\;%."
10007 [(set_attr "type" "branch")
10008 (set_attr "length" "8")])
10010 (define_insn "*call_indirect_nonlocal_aix64"
10011 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10012 (match_operand 1 "" "g,g"))
10013 (use (reg:DI 2))
10014 (use (reg:DI 11))
10015 (set (reg:DI 2)
10016 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10017 (clobber (match_scratch:SI 2 "=l,l"))]
10018 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10019 "b%T0l\;ld 2,40(1)"
10020 [(set_attr "type" "jmpreg")
10021 (set_attr "length" "8")])
10023 (define_insn "*call_nonlocal_aix64"
10024 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10025 (match_operand 1 "" "g"))
10026 (use (match_operand:SI 2 "immediate_operand" "O"))
10027 (clobber (match_scratch:SI 3 "=l"))]
10028 "TARGET_64BIT
10029 && DEFAULT_ABI == ABI_AIX
10030 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10031 "bl %z0\;%."
10032 [(set_attr "type" "branch")
10033 (set_attr "length" "8")])
10035 (define_insn "*call_value_indirect_nonlocal_aix32"
10036 [(set (match_operand 0 "" "")
10037 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10038 (match_operand 2 "" "g,g")))
10039 (use (reg:SI 2))
10040 (use (reg:SI 11))
10041 (set (reg:SI 2)
10042 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10043 (clobber (match_scratch:SI 3 "=l,l"))]
10044 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10045 "b%T1l\;{l|lwz} 2,20(1)"
10046 [(set_attr "type" "jmpreg")
10047 (set_attr "length" "8")])
10049 (define_insn "*call_value_nonlocal_aix32"
10050 [(set (match_operand 0 "" "")
10051 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10052 (match_operand 2 "" "g")))
10053 (use (match_operand:SI 3 "immediate_operand" "O"))
10054 (clobber (match_scratch:SI 4 "=l"))]
10055 "TARGET_32BIT
10056 && DEFAULT_ABI == ABI_AIX
10057 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10058 "bl %z1\;%."
10059 [(set_attr "type" "branch")
10060 (set_attr "length" "8")])
10062 (define_insn "*call_value_indirect_nonlocal_aix64"
10063 [(set (match_operand 0 "" "")
10064 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10065 (match_operand 2 "" "g,g")))
10066 (use (reg:DI 2))
10067 (use (reg:DI 11))
10068 (set (reg:DI 2)
10069 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10070 (clobber (match_scratch:SI 3 "=l,l"))]
10071 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10072 "b%T1l\;ld 2,40(1)"
10073 [(set_attr "type" "jmpreg")
10074 (set_attr "length" "8")])
10076 (define_insn "*call_value_nonlocal_aix64"
10077 [(set (match_operand 0 "" "")
10078 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10079 (match_operand 2 "" "g")))
10080 (use (match_operand:SI 3 "immediate_operand" "O"))
10081 (clobber (match_scratch:SI 4 "=l"))]
10082 "TARGET_64BIT
10083 && DEFAULT_ABI == ABI_AIX
10084 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10085 "bl %z1\;%."
10086 [(set_attr "type" "branch")
10087 (set_attr "length" "8")])
10089 ;; A function pointer under System V is just a normal pointer
10090 ;; operands[0] is the function pointer
10091 ;; operands[1] is the stack size to clean up
10092 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10093 ;; which indicates how to set cr1
10095 (define_insn "*call_indirect_nonlocal_sysv"
10096 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10097 (match_operand 1 "" "g,g,g,g"))
10098 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10099 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10100 "DEFAULT_ABI == ABI_V4
10101 || DEFAULT_ABI == ABI_DARWIN"
10102 {
10103 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10104 output_asm_insn ("crxor 6,6,6", operands);
10106 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10107 output_asm_insn ("creqv 6,6,6", operands);
10109 return "b%T0l";
10110 }
10111 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10112 (set_attr "length" "4,4,8,8")])
10114 (define_insn "*call_nonlocal_sysv"
10115 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10116 (match_operand 1 "" "g,g"))
10117 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10118 (clobber (match_scratch:SI 3 "=l,l"))]
10119 "(DEFAULT_ABI == ABI_DARWIN
10120 || (DEFAULT_ABI == ABI_V4
10121 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10122 {
10123 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10124 output_asm_insn ("crxor 6,6,6", operands);
10126 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10127 output_asm_insn ("creqv 6,6,6", operands);
10129 #if TARGET_MACHO
10130 return output_call(insn, operands, 0, 2);
10131 #else
10132 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10133 {
10134 if (TARGET_SECURE_PLT && flag_pic == 2)
10135 /* The magic 32768 offset here and in the other sysv call insns
10136 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10137 See sysv4.h:toc_section. */
10138 return "bl %z0+32768@plt";
10139 else
10140 return "bl %z0@plt";
10141 }
10142 else
10143 return "bl %z0";
10144 #endif
10145 }
10146 [(set_attr "type" "branch,branch")
10147 (set_attr "length" "4,8")])
10149 (define_insn "*call_value_indirect_nonlocal_sysv"
10150 [(set (match_operand 0 "" "")
10151 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10152 (match_operand 2 "" "g,g,g,g")))
10153 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10154 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10155 "DEFAULT_ABI == ABI_V4
10156 || DEFAULT_ABI == ABI_DARWIN"
10157 {
10158 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10159 output_asm_insn ("crxor 6,6,6", operands);
10161 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10162 output_asm_insn ("creqv 6,6,6", operands);
10164 return "b%T1l";
10165 }
10166 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10167 (set_attr "length" "4,4,8,8")])
10169 (define_insn "*call_value_nonlocal_sysv"
10170 [(set (match_operand 0 "" "")
10171 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10172 (match_operand 2 "" "g,g")))
10173 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10174 (clobber (match_scratch:SI 4 "=l,l"))]
10175 "(DEFAULT_ABI == ABI_DARWIN
10176 || (DEFAULT_ABI == ABI_V4
10177 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10178 {
10179 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10180 output_asm_insn ("crxor 6,6,6", operands);
10182 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10183 output_asm_insn ("creqv 6,6,6", operands);
10185 #if TARGET_MACHO
10186 return output_call(insn, operands, 1, 3);
10187 #else
10188 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10189 {
10190 if (TARGET_SECURE_PLT && flag_pic == 2)
10191 return "bl %z1+32768@plt";
10192 else
10193 return "bl %z1@plt";
10194 }
10195 else
10196 return "bl %z1";
10197 #endif
10198 }
10199 [(set_attr "type" "branch,branch")
10200 (set_attr "length" "4,8")])
10202 ;; Call subroutine returning any type.
10203 (define_expand "untyped_call"
10204 [(parallel [(call (match_operand 0 "" "")
10205 (const_int 0))
10206 (match_operand 1 "" "")
10207 (match_operand 2 "" "")])]
10208 ""
10209 "
10210 {
10211 int i;
10213 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10215 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10216 {
10217 rtx set = XVECEXP (operands[2], 0, i);
10218 emit_move_insn (SET_DEST (set), SET_SRC (set));
10219 }
10221 /* The optimizer does not know that the call sets the function value
10222 registers we stored in the result block. We avoid problems by
10223 claiming that all hard registers are used and clobbered at this
10224 point. */
10225 emit_insn (gen_blockage ());
10227 DONE;
10228 }")
10230 ;; sibling call patterns
10231 (define_expand "sibcall"
10232 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10233 (match_operand 1 "" ""))
10234 (use (match_operand 2 "" ""))
10235 (use (match_operand 3 "" ""))
10236 (return)])]
10237 ""
10238 "
10239 {
10240 #if TARGET_MACHO
10241 if (MACHOPIC_INDIRECT)
10242 operands[0] = machopic_indirect_call_target (operands[0]);
10243 #endif
10245 gcc_assert (GET_CODE (operands[0]) == MEM);
10246 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10248 operands[0] = XEXP (operands[0], 0);
10249 operands[3] = gen_reg_rtx (SImode);
10251 }")
10253 ;; this and similar patterns must be marked as using LR, otherwise
10254 ;; dataflow will try to delete the store into it. This is true
10255 ;; even when the actual reg to jump to is in CTR, when LR was
10256 ;; saved and restored around the PIC-setting BCL.
10257 (define_insn "*sibcall_local32"
10258 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10259 (match_operand 1 "" "g,g"))
10260 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10261 (use (match_operand:SI 3 "register_operand" "l,l"))
10262 (return)]
10263 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10264 "*
10265 {
10266 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10267 output_asm_insn (\"crxor 6,6,6\", operands);
10269 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10270 output_asm_insn (\"creqv 6,6,6\", operands);
10272 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10273 }"
10274 [(set_attr "type" "branch")
10275 (set_attr "length" "4,8")])
10277 (define_insn "*sibcall_local64"
10278 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10279 (match_operand 1 "" "g,g"))
10280 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10281 (use (match_operand:SI 3 "register_operand" "l,l"))
10282 (return)]
10283 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10284 "*
10285 {
10286 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10287 output_asm_insn (\"crxor 6,6,6\", operands);
10289 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10290 output_asm_insn (\"creqv 6,6,6\", operands);
10292 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10293 }"
10294 [(set_attr "type" "branch")
10295 (set_attr "length" "4,8")])
10297 (define_insn "*sibcall_value_local32"
10298 [(set (match_operand 0 "" "")
10299 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10300 (match_operand 2 "" "g,g")))
10301 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10302 (use (match_operand:SI 4 "register_operand" "l,l"))
10303 (return)]
10304 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10305 "*
10306 {
10307 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10308 output_asm_insn (\"crxor 6,6,6\", operands);
10310 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10311 output_asm_insn (\"creqv 6,6,6\", operands);
10313 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10314 }"
10315 [(set_attr "type" "branch")
10316 (set_attr "length" "4,8")])
10319 (define_insn "*sibcall_value_local64"
10320 [(set (match_operand 0 "" "")
10321 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10322 (match_operand 2 "" "g,g")))
10323 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10324 (use (match_operand:SI 4 "register_operand" "l,l"))
10325 (return)]
10326 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10327 "*
10328 {
10329 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10330 output_asm_insn (\"crxor 6,6,6\", operands);
10332 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10333 output_asm_insn (\"creqv 6,6,6\", operands);
10335 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10336 }"
10337 [(set_attr "type" "branch")
10338 (set_attr "length" "4,8")])
10340 (define_insn "*sibcall_nonlocal_aix32"
10341 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10342 (match_operand 1 "" "g"))
10343 (use (match_operand:SI 2 "immediate_operand" "O"))
10344 (use (match_operand:SI 3 "register_operand" "l"))
10345 (return)]
10346 "TARGET_32BIT
10347 && DEFAULT_ABI == ABI_AIX
10348 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10349 "b %z0"
10350 [(set_attr "type" "branch")
10351 (set_attr "length" "4")])
10353 (define_insn "*sibcall_nonlocal_aix64"
10354 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10355 (match_operand 1 "" "g"))
10356 (use (match_operand:SI 2 "immediate_operand" "O"))
10357 (use (match_operand:SI 3 "register_operand" "l"))
10358 (return)]
10359 "TARGET_64BIT
10360 && DEFAULT_ABI == ABI_AIX
10361 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10362 "b %z0"
10363 [(set_attr "type" "branch")
10364 (set_attr "length" "4")])
10366 (define_insn "*sibcall_value_nonlocal_aix32"
10367 [(set (match_operand 0 "" "")
10368 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10369 (match_operand 2 "" "g")))
10370 (use (match_operand:SI 3 "immediate_operand" "O"))
10371 (use (match_operand:SI 4 "register_operand" "l"))
10372 (return)]
10373 "TARGET_32BIT
10374 && DEFAULT_ABI == ABI_AIX
10375 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10376 "b %z1"
10377 [(set_attr "type" "branch")
10378 (set_attr "length" "4")])
10380 (define_insn "*sibcall_value_nonlocal_aix64"
10381 [(set (match_operand 0 "" "")
10382 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10383 (match_operand 2 "" "g")))
10384 (use (match_operand:SI 3 "immediate_operand" "O"))
10385 (use (match_operand:SI 4 "register_operand" "l"))
10386 (return)]
10387 "TARGET_64BIT
10388 && DEFAULT_ABI == ABI_AIX
10389 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10390 "b %z1"
10391 [(set_attr "type" "branch")
10392 (set_attr "length" "4")])
10394 (define_insn "*sibcall_nonlocal_sysv"
10395 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10396 (match_operand 1 "" ""))
10397 (use (match_operand 2 "immediate_operand" "O,n"))
10398 (use (match_operand:SI 3 "register_operand" "l,l"))
10399 (return)]
10400 "(DEFAULT_ABI == ABI_DARWIN
10401 || DEFAULT_ABI == ABI_V4)
10402 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10403 "*
10404 {
10405 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10406 output_asm_insn (\"crxor 6,6,6\", operands);
10408 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10409 output_asm_insn (\"creqv 6,6,6\", operands);
10411 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10412 {
10413 if (TARGET_SECURE_PLT && flag_pic == 2)
10414 return \"b %z0+32768@plt\";
10415 else
10416 return \"b %z0@plt\";
10417 }
10418 else
10419 return \"b %z0\";
10420 }"
10421 [(set_attr "type" "branch,branch")
10422 (set_attr "length" "4,8")])
10424 (define_expand "sibcall_value"
10425 [(parallel [(set (match_operand 0 "register_operand" "")
10426 (call (mem:SI (match_operand 1 "address_operand" ""))
10427 (match_operand 2 "" "")))
10428 (use (match_operand 3 "" ""))
10429 (use (match_operand 4 "" ""))
10430 (return)])]
10431 ""
10432 "
10433 {
10434 #if TARGET_MACHO
10435 if (MACHOPIC_INDIRECT)
10436 operands[1] = machopic_indirect_call_target (operands[1]);
10437 #endif
10439 gcc_assert (GET_CODE (operands[1]) == MEM);
10440 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10442 operands[1] = XEXP (operands[1], 0);
10443 operands[4] = gen_reg_rtx (SImode);
10445 }")
10447 (define_insn "*sibcall_value_nonlocal_sysv"
10448 [(set (match_operand 0 "" "")
10449 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10450 (match_operand 2 "" "")))
10451 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10452 (use (match_operand:SI 4 "register_operand" "l,l"))
10453 (return)]
10454 "(DEFAULT_ABI == ABI_DARWIN
10455 || DEFAULT_ABI == ABI_V4)
10456 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10457 "*
10458 {
10459 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10460 output_asm_insn (\"crxor 6,6,6\", operands);
10462 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10463 output_asm_insn (\"creqv 6,6,6\", operands);
10465 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10466 {
10467 if (TARGET_SECURE_PLT && flag_pic == 2)
10468 return \"b %z1+32768@plt\";
10469 else
10470 return \"b %z1@plt\";
10471 }
10472 else
10473 return \"b %z1\";
10474 }"
10475 [(set_attr "type" "branch,branch")
10476 (set_attr "length" "4,8")])
10478 (define_expand "sibcall_epilogue"
10479 [(use (const_int 0))]
10480 "TARGET_SCHED_PROLOG"
10481 "
10482 {
10483 rs6000_emit_epilogue (TRUE);
10484 DONE;
10485 }")
10487 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10488 ;; all of memory. This blocks insns from being moved across this point.
10490 (define_insn "blockage"
10491 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10492 ""
10493 "")
10494 \f
10495 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10496 ;; signed & unsigned, and one type of branch.
10497 ;;
10498 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10499 ;; insns, and branches. We store the operands of compares until we see
10500 ;; how it is used.
10501 (define_expand "cmp<mode>"
10502 [(set (cc0)
10503 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
10504 (match_operand:GPR 1 "reg_or_short_operand" "")))]
10505 ""
10506 "
10507 {
10508 /* Take care of the possibility that operands[1] might be negative but
10509 this might be a logical operation. That insn doesn't exist. */
10510 if (GET_CODE (operands[1]) == CONST_INT
10511 && INTVAL (operands[1]) < 0)
10512 operands[1] = force_reg (<MODE>mode, operands[1]);
10514 rs6000_compare_op0 = operands[0];
10515 rs6000_compare_op1 = operands[1];
10516 rs6000_compare_fp_p = 0;
10517 DONE;
10518 }")
10520 (define_expand "cmp<mode>"
10521 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
10522 (match_operand:FP 1 "gpc_reg_operand" "")))]
10523 ""
10524 "
10525 {
10526 rs6000_compare_op0 = operands[0];
10527 rs6000_compare_op1 = operands[1];
10528 rs6000_compare_fp_p = 1;
10529 DONE;
10530 }")
10532 (define_expand "beq"
10533 [(use (match_operand 0 "" ""))]
10534 ""
10535 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10537 (define_expand "bne"
10538 [(use (match_operand 0 "" ""))]
10539 ""
10540 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10542 (define_expand "bge"
10543 [(use (match_operand 0 "" ""))]
10544 ""
10545 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10547 (define_expand "bgt"
10548 [(use (match_operand 0 "" ""))]
10549 ""
10550 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10552 (define_expand "ble"
10553 [(use (match_operand 0 "" ""))]
10554 ""
10555 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10557 (define_expand "blt"
10558 [(use (match_operand 0 "" ""))]
10559 ""
10560 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10562 (define_expand "bgeu"
10563 [(use (match_operand 0 "" ""))]
10564 ""
10565 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10567 (define_expand "bgtu"
10568 [(use (match_operand 0 "" ""))]
10569 ""
10570 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10572 (define_expand "bleu"
10573 [(use (match_operand 0 "" ""))]
10574 ""
10575 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10577 (define_expand "bltu"
10578 [(use (match_operand 0 "" ""))]
10579 ""
10580 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10582 (define_expand "bunordered"
10583 [(use (match_operand 0 "" ""))]
10584 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10585 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10587 (define_expand "bordered"
10588 [(use (match_operand 0 "" ""))]
10589 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10590 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10592 (define_expand "buneq"
10593 [(use (match_operand 0 "" ""))]
10594 ""
10595 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10597 (define_expand "bunge"
10598 [(use (match_operand 0 "" ""))]
10599 ""
10600 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10602 (define_expand "bungt"
10603 [(use (match_operand 0 "" ""))]
10604 ""
10605 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10607 (define_expand "bunle"
10608 [(use (match_operand 0 "" ""))]
10609 ""
10610 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10612 (define_expand "bunlt"
10613 [(use (match_operand 0 "" ""))]
10614 ""
10615 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10617 (define_expand "bltgt"
10618 [(use (match_operand 0 "" ""))]
10619 ""
10620 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10622 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10623 ;; For SEQ, likewise, except that comparisons with zero should be done
10624 ;; with an scc insns. However, due to the order that combine see the
10625 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10626 ;; the cases we don't want to handle.
10627 (define_expand "seq"
10628 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10629 ""
10630 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10632 (define_expand "sne"
10633 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10634 ""
10635 "
10636 {
10637 if (! rs6000_compare_fp_p)
10638 FAIL;
10640 rs6000_emit_sCOND (NE, operands[0]);
10641 DONE;
10642 }")
10644 ;; A >= 0 is best done the portable way for A an integer.
10645 (define_expand "sge"
10646 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10647 ""
10648 "
10649 {
10650 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10651 FAIL;
10653 rs6000_emit_sCOND (GE, operands[0]);
10654 DONE;
10655 }")
10657 ;; A > 0 is best done using the portable sequence, so fail in that case.
10658 (define_expand "sgt"
10659 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10660 ""
10661 "
10662 {
10663 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10664 FAIL;
10666 rs6000_emit_sCOND (GT, operands[0]);
10667 DONE;
10668 }")
10670 ;; A <= 0 is best done the portable way for A an integer.
10671 (define_expand "sle"
10672 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10673 ""
10674 "
10675 {
10676 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10677 FAIL;
10679 rs6000_emit_sCOND (LE, operands[0]);
10680 DONE;
10681 }")
10683 ;; A < 0 is best done in the portable way for A an integer.
10684 (define_expand "slt"
10685 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10686 ""
10687 "
10688 {
10689 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10690 FAIL;
10692 rs6000_emit_sCOND (LT, operands[0]);
10693 DONE;
10694 }")
10696 (define_expand "sgeu"
10697 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10698 ""
10699 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10701 (define_expand "sgtu"
10702 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10703 ""
10704 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10706 (define_expand "sleu"
10707 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10708 ""
10709 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10711 (define_expand "sltu"
10712 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10713 ""
10714 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10716 (define_expand "sunordered"
10717 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10718 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10719 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
10721 (define_expand "sordered"
10722 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10723 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10724 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
10726 (define_expand "suneq"
10727 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10728 ""
10729 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
10731 (define_expand "sunge"
10732 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10733 ""
10734 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
10736 (define_expand "sungt"
10737 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10738 ""
10739 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
10741 (define_expand "sunle"
10742 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10743 ""
10744 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
10746 (define_expand "sunlt"
10747 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10748 ""
10749 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
10751 (define_expand "sltgt"
10752 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10753 ""
10754 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
10756 \f
10757 ;; Here are the actual compare insns.
10758 (define_insn "*cmp<mode>_internal1"
10759 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10760 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
10761 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
10762 ""
10763 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
10764 [(set_attr "type" "cmp")])
10766 ;; If we are comparing a register for equality with a large constant,
10767 ;; we can do this with an XOR followed by a compare. But we need a scratch
10768 ;; register for the result of the XOR.
10770 (define_split
10771 [(set (match_operand:CC 0 "cc_reg_operand" "")
10772 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10773 (match_operand:SI 2 "non_short_cint_operand" "")))
10774 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10775 "find_single_use (operands[0], insn, 0)
10776 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10777 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10778 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10779 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10780 "
10781 {
10782 /* Get the constant we are comparing against, C, and see what it looks like
10783 sign-extended to 16 bits. Then see what constant could be XOR'ed
10784 with C to get the sign-extended value. */
10786 HOST_WIDE_INT c = INTVAL (operands[2]);
10787 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
10788 HOST_WIDE_INT xorv = c ^ sextc;
10790 operands[4] = GEN_INT (xorv);
10791 operands[5] = GEN_INT (sextc);
10792 }")
10794 (define_insn "*cmpsi_internal2"
10795 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10796 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10797 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10798 ""
10799 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10800 [(set_attr "type" "cmp")])
10802 (define_insn "*cmpdi_internal2"
10803 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10804 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10805 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10806 ""
10807 "cmpld%I2 %0,%1,%b2"
10808 [(set_attr "type" "cmp")])
10810 ;; The following two insns don't exist as single insns, but if we provide
10811 ;; them, we can swap an add and compare, which will enable us to overlap more
10812 ;; of the required delay between a compare and branch. We generate code for
10813 ;; them by splitting.
10815 (define_insn ""
10816 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10817 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10818 (match_operand:SI 2 "short_cint_operand" "i")))
10819 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10820 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10821 ""
10822 "#"
10823 [(set_attr "length" "8")])
10825 (define_insn ""
10826 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10827 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10828 (match_operand:SI 2 "u_short_cint_operand" "i")))
10829 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10830 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10831 ""
10832 "#"
10833 [(set_attr "length" "8")])
10835 (define_split
10836 [(set (match_operand:CC 3 "cc_reg_operand" "")
10837 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10838 (match_operand:SI 2 "short_cint_operand" "")))
10839 (set (match_operand:SI 0 "gpc_reg_operand" "")
10840 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10841 ""
10842 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10843 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10845 (define_split
10846 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10847 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10848 (match_operand:SI 2 "u_short_cint_operand" "")))
10849 (set (match_operand:SI 0 "gpc_reg_operand" "")
10850 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10851 ""
10852 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10853 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10855 (define_insn "*cmpsf_internal1"
10856 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10857 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10858 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10859 "TARGET_HARD_FLOAT && TARGET_FPRS"
10860 "fcmpu %0,%1,%2"
10861 [(set_attr "type" "fpcompare")])
10863 (define_insn "*cmpdf_internal1"
10864 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10865 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10866 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10867 "TARGET_HARD_FLOAT && TARGET_FPRS"
10868 "fcmpu %0,%1,%2"
10869 [(set_attr "type" "fpcompare")])
10871 ;; Only need to compare second words if first words equal
10872 (define_insn "*cmptf_internal1"
10873 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10874 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10875 (match_operand:TF 2 "gpc_reg_operand" "f")))]
10876 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
10877 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10878 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
10879 [(set_attr "type" "fpcompare")
10880 (set_attr "length" "12")])
10882 (define_insn_and_split "*cmptf_internal2"
10883 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10884 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
10885 (match_operand:TF 2 "gpc_reg_operand" "f")))
10886 (clobber (match_scratch:DF 3 "=f"))
10887 (clobber (match_scratch:DF 4 "=f"))
10888 (clobber (match_scratch:DF 5 "=f"))
10889 (clobber (match_scratch:DF 6 "=f"))
10890 (clobber (match_scratch:DF 7 "=f"))
10891 (clobber (match_scratch:DF 8 "=f"))
10892 (clobber (match_scratch:DF 9 "=f"))
10893 (clobber (match_scratch:DF 10 "=f"))]
10894 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
10895 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10896 "#"
10897 "&& reload_completed"
10898 [(set (match_dup 3) (match_dup 13))
10899 (set (match_dup 4) (match_dup 14))
10900 (set (match_dup 9) (abs:DF (match_dup 5)))
10901 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
10902 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
10903 (label_ref (match_dup 11))
10904 (pc)))
10905 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
10906 (set (pc) (label_ref (match_dup 12)))
10907 (match_dup 11)
10908 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
10909 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
10910 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
10911 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
10912 (match_dup 12)]
10913 {
10914 REAL_VALUE_TYPE rv;
10915 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10916 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10918 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
10919 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
10920 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
10921 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
10922 operands[11] = gen_label_rtx ();
10923 operands[12] = gen_label_rtx ();
10924 real_inf (&rv);
10925 operands[13] = force_const_mem (DFmode,
10926 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
10927 operands[14] = force_const_mem (DFmode,
10928 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
10929 DFmode));
10930 if (TARGET_TOC)
10931 {
10932 operands[13] = gen_const_mem (DFmode,
10933 create_TOC_reference (XEXP (operands[13], 0)));
10934 operands[14] = gen_const_mem (DFmode,
10935 create_TOC_reference (XEXP (operands[14], 0)));
10936 set_mem_alias_set (operands[13], get_TOC_alias_set ());
10937 set_mem_alias_set (operands[14], get_TOC_alias_set ());
10938 }
10939 })
10940 \f
10941 ;; Now we have the scc insns. We can do some combinations because of the
10942 ;; way the machine works.
10943 ;;
10944 ;; Note that this is probably faster if we can put an insn between the
10945 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10946 ;; cases the insns below which don't use an intermediate CR field will
10947 ;; be used instead.
10948 (define_insn ""
10949 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10950 (match_operator:SI 1 "scc_comparison_operator"
10951 [(match_operand 2 "cc_reg_operand" "y")
10952 (const_int 0)]))]
10953 ""
10954 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10955 [(set (attr "type")
10956 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10957 (const_string "mfcrf")
10958 ]
10959 (const_string "mfcr")))
10960 (set_attr "length" "8")])
10962 ;; Same as above, but get the GT bit.
10963 (define_insn "move_from_CR_gt_bit"
10964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10965 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
10966 "TARGET_E500"
10967 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
10968 [(set_attr "type" "mfcr")
10969 (set_attr "length" "8")])
10971 ;; Same as above, but get the OV/ORDERED bit.
10972 (define_insn "move_from_CR_ov_bit"
10973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10974 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
10975 "TARGET_ISEL"
10976 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
10977 [(set_attr "type" "mfcr")
10978 (set_attr "length" "8")])
10980 (define_insn ""
10981 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10982 (match_operator:DI 1 "scc_comparison_operator"
10983 [(match_operand 2 "cc_reg_operand" "y")
10984 (const_int 0)]))]
10985 "TARGET_POWERPC64"
10986 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
10987 [(set (attr "type")
10988 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
10989 (const_string "mfcrf")
10990 ]
10991 (const_string "mfcr")))
10992 (set_attr "length" "8")])
10994 (define_insn ""
10995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10996 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10997 [(match_operand 2 "cc_reg_operand" "y,y")
10998 (const_int 0)])
10999 (const_int 0)))
11000 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11001 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11002 "TARGET_32BIT"
11003 "@
11004 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11005 #"
11006 [(set_attr "type" "delayed_compare")
11007 (set_attr "length" "8,16")])
11009 (define_split
11010 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11011 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11012 [(match_operand 2 "cc_reg_operand" "")
11013 (const_int 0)])
11014 (const_int 0)))
11015 (set (match_operand:SI 3 "gpc_reg_operand" "")
11016 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11017 "TARGET_32BIT && reload_completed"
11018 [(set (match_dup 3)
11019 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11020 (set (match_dup 0)
11021 (compare:CC (match_dup 3)
11022 (const_int 0)))]
11023 "")
11025 (define_insn ""
11026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11027 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11028 [(match_operand 2 "cc_reg_operand" "y")
11029 (const_int 0)])
11030 (match_operand:SI 3 "const_int_operand" "n")))]
11031 ""
11032 "*
11033 {
11034 int is_bit = ccr_bit (operands[1], 1);
11035 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11036 int count;
11038 if (is_bit >= put_bit)
11039 count = is_bit - put_bit;
11040 else
11041 count = 32 - (put_bit - is_bit);
11043 operands[4] = GEN_INT (count);
11044 operands[5] = GEN_INT (put_bit);
11046 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11047 }"
11048 [(set (attr "type")
11049 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11050 (const_string "mfcrf")
11051 ]
11052 (const_string "mfcr")))
11053 (set_attr "length" "8")])
11055 (define_insn ""
11056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11057 (compare:CC
11058 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11059 [(match_operand 2 "cc_reg_operand" "y,y")
11060 (const_int 0)])
11061 (match_operand:SI 3 "const_int_operand" "n,n"))
11062 (const_int 0)))
11063 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11064 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11065 (match_dup 3)))]
11066 ""
11067 "*
11068 {
11069 int is_bit = ccr_bit (operands[1], 1);
11070 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11071 int count;
11073 /* Force split for non-cc0 compare. */
11074 if (which_alternative == 1)
11075 return \"#\";
11077 if (is_bit >= put_bit)
11078 count = is_bit - put_bit;
11079 else
11080 count = 32 - (put_bit - is_bit);
11082 operands[5] = GEN_INT (count);
11083 operands[6] = GEN_INT (put_bit);
11085 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11086 }"
11087 [(set_attr "type" "delayed_compare")
11088 (set_attr "length" "8,16")])
11090 (define_split
11091 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11092 (compare:CC
11093 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11094 [(match_operand 2 "cc_reg_operand" "")
11095 (const_int 0)])
11096 (match_operand:SI 3 "const_int_operand" ""))
11097 (const_int 0)))
11098 (set (match_operand:SI 4 "gpc_reg_operand" "")
11099 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11100 (match_dup 3)))]
11101 "reload_completed"
11102 [(set (match_dup 4)
11103 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11104 (match_dup 3)))
11105 (set (match_dup 0)
11106 (compare:CC (match_dup 4)
11107 (const_int 0)))]
11108 "")
11110 ;; There is a 3 cycle delay between consecutive mfcr instructions
11111 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11113 (define_peephole
11114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11115 (match_operator:SI 1 "scc_comparison_operator"
11116 [(match_operand 2 "cc_reg_operand" "y")
11117 (const_int 0)]))
11118 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11119 (match_operator:SI 4 "scc_comparison_operator"
11120 [(match_operand 5 "cc_reg_operand" "y")
11121 (const_int 0)]))]
11122 "REGNO (operands[2]) != REGNO (operands[5])"
11123 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11124 [(set_attr "type" "mfcr")
11125 (set_attr "length" "12")])
11127 (define_peephole
11128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11129 (match_operator:DI 1 "scc_comparison_operator"
11130 [(match_operand 2 "cc_reg_operand" "y")
11131 (const_int 0)]))
11132 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11133 (match_operator:DI 4 "scc_comparison_operator"
11134 [(match_operand 5 "cc_reg_operand" "y")
11135 (const_int 0)]))]
11136 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11137 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11138 [(set_attr "type" "mfcr")
11139 (set_attr "length" "12")])
11141 ;; There are some scc insns that can be done directly, without a compare.
11142 ;; These are faster because they don't involve the communications between
11143 ;; the FXU and branch units. In fact, we will be replacing all of the
11144 ;; integer scc insns here or in the portable methods in emit_store_flag.
11145 ;;
11146 ;; Also support (neg (scc ..)) since that construct is used to replace
11147 ;; branches, (plus (scc ..) ..) since that construct is common and
11148 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11149 ;; cases where it is no more expensive than (neg (scc ..)).
11151 ;; Have reload force a constant into a register for the simple insns that
11152 ;; otherwise won't accept constants. We do this because it is faster than
11153 ;; the cmp/mfcr sequence we would otherwise generate.
11155 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11156 (DI "rKJI")])
11158 (define_insn_and_split "*eq<mode>"
11159 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11160 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11161 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
11162 (clobber (match_scratch:GPR 3 "=r"))
11163 (clobber (match_scratch:GPR 4 "=r"))]
11164 ""
11165 "#"
11166 "reload_completed"
11167 [(set (match_dup 3)
11168 (clz:GPR (match_dup 4)))
11169 (set (match_dup 0)
11170 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
11171 {
11172 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11173 {
11174 if (logical_operand (operands[2], <MODE>mode))
11175 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11176 gen_rtx_XOR (<MODE>mode,
11177 operands[1], operands[2])));
11178 else
11179 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11180 gen_rtx_PLUS (<MODE>mode, operands[1],
11181 negate_rtx (<MODE>mode,
11182 operands[2]))));
11183 }
11184 else
11185 operands[4] = operands[1];
11187 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11188 })
11190 (define_insn_and_split "*eq<mode>_compare"
11191 [(set (match_operand:CC 5 "cc_reg_operand" "=y")
11192 (compare:CC
11193 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11194 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11195 (const_int 0)))
11196 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11197 (eq:P (match_dup 1) (match_dup 2)))
11198 (clobber (match_scratch:P 3 "=r"))
11199 (clobber (match_scratch:P 4 "=r"))]
11200 ""
11201 "#"
11202 "reload_completed"
11203 [(set (match_dup 3)
11204 (clz:P (match_dup 4)))
11205 (parallel [(set (match_dup 5)
11206 (compare:CC (lshiftrt:P (match_dup 3) (match_dup 6))
11207 (const_int 0)))
11208 (set (match_dup 0)
11209 (lshiftrt:P (match_dup 3) (match_dup 6)))])]
11210 {
11211 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11212 {
11213 if (logical_operand (operands[2], <MODE>mode))
11214 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11215 gen_rtx_XOR (<MODE>mode,
11216 operands[1], operands[2])));
11217 else
11218 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11219 gen_rtx_PLUS (<MODE>mode, operands[1],
11220 negate_rtx (<MODE>mode,
11221 operands[2]))));
11222 }
11223 else
11224 operands[4] = operands[1];
11226 operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11227 })
11229 ;; We have insns of the form shown by the first define_insn below. If
11230 ;; there is something inside the comparison operation, we must split it.
11231 (define_split
11232 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11233 (plus:SI (match_operator 1 "comparison_operator"
11234 [(match_operand:SI 2 "" "")
11235 (match_operand:SI 3
11236 "reg_or_cint_operand" "")])
11237 (match_operand:SI 4 "gpc_reg_operand" "")))
11238 (clobber (match_operand:SI 5 "register_operand" ""))]
11239 "! gpc_reg_operand (operands[2], SImode)"
11240 [(set (match_dup 5) (match_dup 2))
11241 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11242 (match_dup 4)))])
11244 (define_insn ""
11245 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11246 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11247 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11248 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11249 "TARGET_32BIT"
11250 "@
11251 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11252 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11253 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11254 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11255 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11256 [(set_attr "type" "three,two,three,three,three")
11257 (set_attr "length" "12,8,12,12,12")])
11259 (define_insn ""
11260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11261 (compare:CC
11262 (plus:SI
11263 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11264 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11265 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11266 (const_int 0)))
11267 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11268 "TARGET_32BIT"
11269 "@
11270 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11271 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11272 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11273 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11274 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11275 #
11276 #
11277 #
11278 #
11279 #"
11280 [(set_attr "type" "compare")
11281 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11283 (define_split
11284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11285 (compare:CC
11286 (plus:SI
11287 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11288 (match_operand:SI 2 "scc_eq_operand" ""))
11289 (match_operand:SI 3 "gpc_reg_operand" ""))
11290 (const_int 0)))
11291 (clobber (match_scratch:SI 4 ""))]
11292 "TARGET_32BIT && reload_completed"
11293 [(set (match_dup 4)
11294 (plus:SI (eq:SI (match_dup 1)
11295 (match_dup 2))
11296 (match_dup 3)))
11297 (set (match_dup 0)
11298 (compare:CC (match_dup 4)
11299 (const_int 0)))]
11300 "")
11302 (define_insn ""
11303 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11304 (compare:CC
11305 (plus:SI
11306 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11307 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11308 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11309 (const_int 0)))
11310 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11311 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11312 "TARGET_32BIT"
11313 "@
11314 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11315 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11316 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11317 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11318 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11319 #
11320 #
11321 #
11322 #
11323 #"
11324 [(set_attr "type" "compare")
11325 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11327 (define_split
11328 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11329 (compare:CC
11330 (plus:SI
11331 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11332 (match_operand:SI 2 "scc_eq_operand" ""))
11333 (match_operand:SI 3 "gpc_reg_operand" ""))
11334 (const_int 0)))
11335 (set (match_operand:SI 0 "gpc_reg_operand" "")
11336 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11337 "TARGET_32BIT && reload_completed"
11338 [(set (match_dup 0)
11339 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11340 (set (match_dup 4)
11341 (compare:CC (match_dup 0)
11342 (const_int 0)))]
11343 "")
11345 (define_insn ""
11346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11347 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11348 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))]
11349 "TARGET_32BIT"
11350 "@
11351 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11352 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11353 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11354 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11355 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11356 [(set_attr "type" "three,two,three,three,three")
11357 (set_attr "length" "12,8,12,12,12")])
11359 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11360 ;; since it nabs/sr is just as fast.
11361 (define_insn "*ne0"
11362 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11363 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11364 (const_int 31)))
11365 (clobber (match_scratch:SI 2 "=&r"))]
11366 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11367 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11368 [(set_attr "type" "two")
11369 (set_attr "length" "8")])
11371 (define_insn ""
11372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11373 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11374 (const_int 63)))
11375 (clobber (match_scratch:DI 2 "=&r"))]
11376 "TARGET_64BIT"
11377 "addic %2,%1,-1\;subfe %0,%2,%1"
11378 [(set_attr "type" "two")
11379 (set_attr "length" "8")])
11381 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11382 (define_insn ""
11383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11384 (plus:SI (lshiftrt:SI
11385 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11386 (const_int 31))
11387 (match_operand:SI 2 "gpc_reg_operand" "r")))
11388 (clobber (match_scratch:SI 3 "=&r"))]
11389 "TARGET_32BIT"
11390 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11391 [(set_attr "type" "two")
11392 (set_attr "length" "8")])
11394 (define_insn ""
11395 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11396 (plus:DI (lshiftrt:DI
11397 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11398 (const_int 63))
11399 (match_operand:DI 2 "gpc_reg_operand" "r")))
11400 (clobber (match_scratch:DI 3 "=&r"))]
11401 "TARGET_64BIT"
11402 "addic %3,%1,-1\;addze %0,%2"
11403 [(set_attr "type" "two")
11404 (set_attr "length" "8")])
11406 (define_insn ""
11407 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11408 (compare:CC
11409 (plus:SI (lshiftrt:SI
11410 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11411 (const_int 31))
11412 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11413 (const_int 0)))
11414 (clobber (match_scratch:SI 3 "=&r,&r"))
11415 (clobber (match_scratch:SI 4 "=X,&r"))]
11416 "TARGET_32BIT"
11417 "@
11418 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11419 #"
11420 [(set_attr "type" "compare")
11421 (set_attr "length" "8,12")])
11423 (define_split
11424 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11425 (compare:CC
11426 (plus:SI (lshiftrt:SI
11427 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11428 (const_int 31))
11429 (match_operand:SI 2 "gpc_reg_operand" ""))
11430 (const_int 0)))
11431 (clobber (match_scratch:SI 3 ""))
11432 (clobber (match_scratch:SI 4 ""))]
11433 "TARGET_32BIT && reload_completed"
11434 [(parallel [(set (match_dup 3)
11435 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11436 (const_int 31))
11437 (match_dup 2)))
11438 (clobber (match_dup 4))])
11439 (set (match_dup 0)
11440 (compare:CC (match_dup 3)
11441 (const_int 0)))]
11442 "")
11444 (define_insn ""
11445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11446 (compare:CC
11447 (plus:DI (lshiftrt:DI
11448 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11449 (const_int 63))
11450 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11451 (const_int 0)))
11452 (clobber (match_scratch:DI 3 "=&r,&r"))]
11453 "TARGET_64BIT"
11454 "@
11455 addic %3,%1,-1\;addze. %3,%2
11456 #"
11457 [(set_attr "type" "compare")
11458 (set_attr "length" "8,12")])
11460 (define_split
11461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11462 (compare:CC
11463 (plus:DI (lshiftrt:DI
11464 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11465 (const_int 63))
11466 (match_operand:DI 2 "gpc_reg_operand" ""))
11467 (const_int 0)))
11468 (clobber (match_scratch:DI 3 ""))]
11469 "TARGET_64BIT && reload_completed"
11470 [(set (match_dup 3)
11471 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11472 (const_int 63))
11473 (match_dup 2)))
11474 (set (match_dup 0)
11475 (compare:CC (match_dup 3)
11476 (const_int 0)))]
11477 "")
11479 (define_insn ""
11480 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11481 (compare:CC
11482 (plus:SI (lshiftrt:SI
11483 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11484 (const_int 31))
11485 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11486 (const_int 0)))
11487 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11488 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11489 (match_dup 2)))
11490 (clobber (match_scratch:SI 3 "=&r,&r"))]
11491 "TARGET_32BIT"
11492 "@
11493 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11494 #"
11495 [(set_attr "type" "compare")
11496 (set_attr "length" "8,12")])
11498 (define_split
11499 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11500 (compare:CC
11501 (plus:SI (lshiftrt:SI
11502 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11503 (const_int 31))
11504 (match_operand:SI 2 "gpc_reg_operand" ""))
11505 (const_int 0)))
11506 (set (match_operand:SI 0 "gpc_reg_operand" "")
11507 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11508 (match_dup 2)))
11509 (clobber (match_scratch:SI 3 ""))]
11510 "TARGET_32BIT && reload_completed"
11511 [(parallel [(set (match_dup 0)
11512 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11513 (match_dup 2)))
11514 (clobber (match_dup 3))])
11515 (set (match_dup 4)
11516 (compare:CC (match_dup 0)
11517 (const_int 0)))]
11518 "")
11520 (define_insn ""
11521 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11522 (compare:CC
11523 (plus:DI (lshiftrt:DI
11524 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11525 (const_int 63))
11526 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11527 (const_int 0)))
11528 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11529 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11530 (match_dup 2)))
11531 (clobber (match_scratch:DI 3 "=&r,&r"))]
11532 "TARGET_64BIT"
11533 "@
11534 addic %3,%1,-1\;addze. %0,%2
11535 #"
11536 [(set_attr "type" "compare")
11537 (set_attr "length" "8,12")])
11539 (define_split
11540 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11541 (compare:CC
11542 (plus:DI (lshiftrt:DI
11543 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11544 (const_int 63))
11545 (match_operand:DI 2 "gpc_reg_operand" ""))
11546 (const_int 0)))
11547 (set (match_operand:DI 0 "gpc_reg_operand" "")
11548 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11549 (match_dup 2)))
11550 (clobber (match_scratch:DI 3 ""))]
11551 "TARGET_64BIT && reload_completed"
11552 [(parallel [(set (match_dup 0)
11553 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11554 (match_dup 2)))
11555 (clobber (match_dup 3))])
11556 (set (match_dup 4)
11557 (compare:CC (match_dup 0)
11558 (const_int 0)))]
11559 "")
11561 (define_insn ""
11562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11563 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11564 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11565 (clobber (match_scratch:SI 3 "=r,X"))]
11566 "TARGET_POWER"
11567 "@
11568 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11569 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11570 [(set_attr "length" "12")])
11572 (define_insn ""
11573 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11574 (compare:CC
11575 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11576 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11577 (const_int 0)))
11578 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11579 (le:SI (match_dup 1) (match_dup 2)))
11580 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11581 "TARGET_POWER"
11582 "@
11583 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11584 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11585 #
11586 #"
11587 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11588 (set_attr "length" "12,12,16,16")])
11590 (define_split
11591 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11592 (compare:CC
11593 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11594 (match_operand:SI 2 "reg_or_short_operand" ""))
11595 (const_int 0)))
11596 (set (match_operand:SI 0 "gpc_reg_operand" "")
11597 (le:SI (match_dup 1) (match_dup 2)))
11598 (clobber (match_scratch:SI 3 ""))]
11599 "TARGET_POWER && reload_completed"
11600 [(parallel [(set (match_dup 0)
11601 (le:SI (match_dup 1) (match_dup 2)))
11602 (clobber (match_dup 3))])
11603 (set (match_dup 4)
11604 (compare:CC (match_dup 0)
11605 (const_int 0)))]
11606 "")
11608 (define_insn ""
11609 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11610 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11611 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11612 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11613 "TARGET_POWER"
11614 "@
11615 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11616 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11617 [(set_attr "length" "12")])
11619 (define_insn ""
11620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11621 (compare:CC
11622 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11623 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11624 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11625 (const_int 0)))
11626 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11627 "TARGET_POWER"
11628 "@
11629 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11630 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11631 #
11632 #"
11633 [(set_attr "type" "compare")
11634 (set_attr "length" "12,12,16,16")])
11636 (define_split
11637 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11638 (compare:CC
11639 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11640 (match_operand:SI 2 "reg_or_short_operand" ""))
11641 (match_operand:SI 3 "gpc_reg_operand" ""))
11642 (const_int 0)))
11643 (clobber (match_scratch:SI 4 ""))]
11644 "TARGET_POWER && reload_completed"
11645 [(set (match_dup 4)
11646 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11647 (match_dup 3)))
11648 (set (match_dup 0)
11649 (compare:CC (match_dup 4)
11650 (const_int 0)))]
11651 "")
11653 (define_insn ""
11654 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11655 (compare:CC
11656 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11657 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11658 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11659 (const_int 0)))
11660 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11661 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11662 "TARGET_POWER"
11663 "@
11664 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11665 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11666 #
11667 #"
11668 [(set_attr "type" "compare")
11669 (set_attr "length" "12,12,16,16")])
11671 (define_split
11672 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11673 (compare:CC
11674 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11675 (match_operand:SI 2 "reg_or_short_operand" ""))
11676 (match_operand:SI 3 "gpc_reg_operand" ""))
11677 (const_int 0)))
11678 (set (match_operand:SI 0 "gpc_reg_operand" "")
11679 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11680 "TARGET_POWER && reload_completed"
11681 [(set (match_dup 0)
11682 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11683 (set (match_dup 4)
11684 (compare:CC (match_dup 0)
11685 (const_int 0)))]
11686 "")
11688 (define_insn ""
11689 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11690 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11691 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11692 "TARGET_POWER"
11693 "@
11694 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11695 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11696 [(set_attr "length" "12")])
11698 (define_insn ""
11699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11700 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11701 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11702 "TARGET_32BIT"
11703 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11704 [(set_attr "type" "three")
11705 (set_attr "length" "12")])
11707 (define_insn ""
11708 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11709 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11710 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11711 "TARGET_64BIT"
11712 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11713 [(set_attr "type" "three")
11714 (set_attr "length" "12")])
11716 (define_insn ""
11717 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11718 (compare:CC
11719 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11720 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
11721 (const_int 0)))
11722 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11723 (leu:DI (match_dup 1) (match_dup 2)))]
11724 "TARGET_64BIT"
11725 "@
11726 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11727 #"
11728 [(set_attr "type" "compare")
11729 (set_attr "length" "12,16")])
11731 (define_split
11732 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11733 (compare:CC
11734 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11735 (match_operand:DI 2 "reg_or_short_operand" ""))
11736 (const_int 0)))
11737 (set (match_operand:DI 0 "gpc_reg_operand" "")
11738 (leu:DI (match_dup 1) (match_dup 2)))]
11739 "TARGET_64BIT && reload_completed"
11740 [(set (match_dup 0)
11741 (leu:DI (match_dup 1) (match_dup 2)))
11742 (set (match_dup 3)
11743 (compare:CC (match_dup 0)
11744 (const_int 0)))]
11745 "")
11747 (define_insn ""
11748 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11749 (compare:CC
11750 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11751 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11752 (const_int 0)))
11753 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11754 (leu:SI (match_dup 1) (match_dup 2)))]
11755 "TARGET_32BIT"
11756 "@
11757 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11758 #"
11759 [(set_attr "type" "compare")
11760 (set_attr "length" "12,16")])
11762 (define_split
11763 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11764 (compare:CC
11765 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11766 (match_operand:SI 2 "reg_or_short_operand" ""))
11767 (const_int 0)))
11768 (set (match_operand:SI 0 "gpc_reg_operand" "")
11769 (leu:SI (match_dup 1) (match_dup 2)))]
11770 "TARGET_32BIT && reload_completed"
11771 [(set (match_dup 0)
11772 (leu:SI (match_dup 1) (match_dup 2)))
11773 (set (match_dup 3)
11774 (compare:CC (match_dup 0)
11775 (const_int 0)))]
11776 "")
11778 (define_insn ""
11779 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11780 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11781 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11782 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11783 "TARGET_32BIT"
11784 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
11785 [(set_attr "type" "two")
11786 (set_attr "length" "8")])
11788 (define_insn ""
11789 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11790 (compare:CC
11791 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11792 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11793 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11794 (const_int 0)))
11795 (clobber (match_scratch:SI 4 "=&r,&r"))]
11796 "TARGET_32BIT"
11797 "@
11798 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11799 #"
11800 [(set_attr "type" "compare")
11801 (set_attr "length" "8,12")])
11803 (define_split
11804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11805 (compare:CC
11806 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11807 (match_operand:SI 2 "reg_or_short_operand" ""))
11808 (match_operand:SI 3 "gpc_reg_operand" ""))
11809 (const_int 0)))
11810 (clobber (match_scratch:SI 4 ""))]
11811 "TARGET_32BIT && reload_completed"
11812 [(set (match_dup 4)
11813 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11814 (match_dup 3)))
11815 (set (match_dup 0)
11816 (compare:CC (match_dup 4)
11817 (const_int 0)))]
11818 "")
11820 (define_insn ""
11821 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11822 (compare:CC
11823 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11824 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11825 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11826 (const_int 0)))
11827 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11828 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11829 "TARGET_32BIT"
11830 "@
11831 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
11832 #"
11833 [(set_attr "type" "compare")
11834 (set_attr "length" "8,12")])
11836 (define_split
11837 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11838 (compare:CC
11839 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11840 (match_operand:SI 2 "reg_or_short_operand" ""))
11841 (match_operand:SI 3 "gpc_reg_operand" ""))
11842 (const_int 0)))
11843 (set (match_operand:SI 0 "gpc_reg_operand" "")
11844 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11845 "TARGET_32BIT && reload_completed"
11846 [(set (match_dup 0)
11847 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11848 (set (match_dup 4)
11849 (compare:CC (match_dup 0)
11850 (const_int 0)))]
11851 "")
11853 (define_insn ""
11854 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11855 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11856 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11857 "TARGET_32BIT"
11858 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11859 [(set_attr "type" "three")
11860 (set_attr "length" "12")])
11862 (define_insn ""
11863 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11864 (and:SI (neg:SI
11865 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11866 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11867 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11868 "TARGET_32BIT"
11869 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
11870 [(set_attr "type" "three")
11871 (set_attr "length" "12")])
11873 (define_insn ""
11874 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11875 (compare:CC
11876 (and:SI (neg:SI
11877 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11878 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11879 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11880 (const_int 0)))
11881 (clobber (match_scratch:SI 4 "=&r,&r"))]
11882 "TARGET_32BIT"
11883 "@
11884 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11885 #"
11886 [(set_attr "type" "compare")
11887 (set_attr "length" "12,16")])
11889 (define_split
11890 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11891 (compare:CC
11892 (and:SI (neg:SI
11893 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11894 (match_operand:SI 2 "reg_or_short_operand" "")))
11895 (match_operand:SI 3 "gpc_reg_operand" ""))
11896 (const_int 0)))
11897 (clobber (match_scratch:SI 4 ""))]
11898 "TARGET_32BIT && reload_completed"
11899 [(set (match_dup 4)
11900 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11901 (match_dup 3)))
11902 (set (match_dup 0)
11903 (compare:CC (match_dup 4)
11904 (const_int 0)))]
11905 "")
11907 (define_insn ""
11908 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11909 (compare:CC
11910 (and:SI (neg:SI
11911 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11912 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11913 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11914 (const_int 0)))
11915 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11916 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11917 "TARGET_32BIT"
11918 "@
11919 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
11920 #"
11921 [(set_attr "type" "compare")
11922 (set_attr "length" "12,16")])
11924 (define_split
11925 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11926 (compare:CC
11927 (and:SI (neg:SI
11928 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11929 (match_operand:SI 2 "reg_or_short_operand" "")))
11930 (match_operand:SI 3 "gpc_reg_operand" ""))
11931 (const_int 0)))
11932 (set (match_operand:SI 0 "gpc_reg_operand" "")
11933 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
11934 "TARGET_32BIT && reload_completed"
11935 [(set (match_dup 0)
11936 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
11937 (match_dup 3)))
11938 (set (match_dup 4)
11939 (compare:CC (match_dup 0)
11940 (const_int 0)))]
11941 "")
11943 (define_insn ""
11944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11945 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11946 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11947 "TARGET_POWER"
11948 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11949 [(set_attr "length" "12")])
11951 (define_insn ""
11952 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11953 (compare:CC
11954 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11955 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11956 (const_int 0)))
11957 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11958 (lt:SI (match_dup 1) (match_dup 2)))]
11959 "TARGET_POWER"
11960 "@
11961 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11962 #"
11963 [(set_attr "type" "delayed_compare")
11964 (set_attr "length" "12,16")])
11966 (define_split
11967 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11968 (compare:CC
11969 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11970 (match_operand:SI 2 "reg_or_short_operand" ""))
11971 (const_int 0)))
11972 (set (match_operand:SI 0 "gpc_reg_operand" "")
11973 (lt:SI (match_dup 1) (match_dup 2)))]
11974 "TARGET_POWER && reload_completed"
11975 [(set (match_dup 0)
11976 (lt:SI (match_dup 1) (match_dup 2)))
11977 (set (match_dup 3)
11978 (compare:CC (match_dup 0)
11979 (const_int 0)))]
11980 "")
11982 (define_insn ""
11983 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11984 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11985 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11986 (match_operand:SI 3 "gpc_reg_operand" "r")))]
11987 "TARGET_POWER"
11988 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
11989 [(set_attr "length" "12")])
11991 (define_insn ""
11992 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11993 (compare:CC
11994 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11995 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11996 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11997 (const_int 0)))
11998 (clobber (match_scratch:SI 4 "=&r,&r"))]
11999 "TARGET_POWER"
12000 "@
12001 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12002 #"
12003 [(set_attr "type" "compare")
12004 (set_attr "length" "12,16")])
12006 (define_split
12007 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12008 (compare:CC
12009 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12010 (match_operand:SI 2 "reg_or_short_operand" ""))
12011 (match_operand:SI 3 "gpc_reg_operand" ""))
12012 (const_int 0)))
12013 (clobber (match_scratch:SI 4 ""))]
12014 "TARGET_POWER && reload_completed"
12015 [(set (match_dup 4)
12016 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12017 (match_dup 3)))
12018 (set (match_dup 0)
12019 (compare:CC (match_dup 4)
12020 (const_int 0)))]
12021 "")
12023 (define_insn ""
12024 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12025 (compare:CC
12026 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12027 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12028 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12029 (const_int 0)))
12030 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12031 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12032 "TARGET_POWER"
12033 "@
12034 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12035 #"
12036 [(set_attr "type" "compare")
12037 (set_attr "length" "12,16")])
12039 (define_split
12040 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12041 (compare:CC
12042 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12043 (match_operand:SI 2 "reg_or_short_operand" ""))
12044 (match_operand:SI 3 "gpc_reg_operand" ""))
12045 (const_int 0)))
12046 (set (match_operand:SI 0 "gpc_reg_operand" "")
12047 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12048 "TARGET_POWER && reload_completed"
12049 [(set (match_dup 0)
12050 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12051 (set (match_dup 4)
12052 (compare:CC (match_dup 0)
12053 (const_int 0)))]
12054 "")
12056 (define_insn ""
12057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12058 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12059 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12060 "TARGET_POWER"
12061 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12062 [(set_attr "length" "12")])
12064 (define_insn_and_split ""
12065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12066 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12067 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12068 "TARGET_32BIT"
12069 "#"
12070 "TARGET_32BIT"
12071 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12072 (set (match_dup 0) (neg:SI (match_dup 0)))]
12073 "")
12075 (define_insn_and_split ""
12076 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12077 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12078 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12079 "TARGET_64BIT"
12080 "#"
12081 "TARGET_64BIT"
12082 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12083 (set (match_dup 0) (neg:DI (match_dup 0)))]
12084 "")
12086 (define_insn ""
12087 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12088 (compare:CC
12089 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12090 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12091 (const_int 0)))
12092 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12093 (ltu:SI (match_dup 1) (match_dup 2)))]
12094 "TARGET_32BIT"
12095 "@
12096 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12097 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12098 #
12099 #"
12100 [(set_attr "type" "compare")
12101 (set_attr "length" "12,12,16,16")])
12103 (define_split
12104 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12105 (compare:CC
12106 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12107 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12108 (const_int 0)))
12109 (set (match_operand:SI 0 "gpc_reg_operand" "")
12110 (ltu:SI (match_dup 1) (match_dup 2)))]
12111 "TARGET_32BIT && reload_completed"
12112 [(set (match_dup 0)
12113 (ltu:SI (match_dup 1) (match_dup 2)))
12114 (set (match_dup 3)
12115 (compare:CC (match_dup 0)
12116 (const_int 0)))]
12117 "")
12119 (define_insn_and_split ""
12120 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12121 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12122 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12123 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12124 "TARGET_32BIT"
12125 "#"
12126 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12127 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12128 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12129 "")
12131 (define_insn_and_split ""
12132 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12133 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12134 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12135 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12136 "TARGET_64BIT"
12137 "#"
12138 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12139 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12140 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12141 "")
12143 (define_insn ""
12144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12145 (compare:CC
12146 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12147 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12148 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12149 (const_int 0)))
12150 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12151 "TARGET_32BIT"
12152 "@
12153 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12154 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12155 #
12156 #"
12157 [(set_attr "type" "compare")
12158 (set_attr "length" "12,12,16,16")])
12160 (define_split
12161 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12162 (compare:CC
12163 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12164 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12165 (match_operand:SI 3 "gpc_reg_operand" ""))
12166 (const_int 0)))
12167 (clobber (match_scratch:SI 4 ""))]
12168 "TARGET_32BIT && reload_completed"
12169 [(set (match_dup 4)
12170 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12171 (match_dup 3)))
12172 (set (match_dup 0)
12173 (compare:CC (match_dup 4)
12174 (const_int 0)))]
12175 "")
12177 (define_insn ""
12178 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12179 (compare:CC
12180 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12181 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12182 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12183 (const_int 0)))
12184 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12185 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12186 "TARGET_32BIT"
12187 "@
12188 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12189 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12190 #
12191 #"
12192 [(set_attr "type" "compare")
12193 (set_attr "length" "12,12,16,16")])
12195 (define_split
12196 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12197 (compare:CC
12198 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12199 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12200 (match_operand:SI 3 "gpc_reg_operand" ""))
12201 (const_int 0)))
12202 (set (match_operand:SI 0 "gpc_reg_operand" "")
12203 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12204 "TARGET_32BIT && reload_completed"
12205 [(set (match_dup 0)
12206 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12207 (set (match_dup 4)
12208 (compare:CC (match_dup 0)
12209 (const_int 0)))]
12210 "")
12212 (define_insn ""
12213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12214 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12215 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12216 "TARGET_32BIT"
12217 "@
12218 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12219 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12220 [(set_attr "type" "two")
12221 (set_attr "length" "8")])
12223 (define_insn ""
12224 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12225 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12226 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12227 "TARGET_64BIT"
12228 "@
12229 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12230 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12231 [(set_attr "type" "two")
12232 (set_attr "length" "8")])
12234 (define_insn ""
12235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12236 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12237 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12238 (clobber (match_scratch:SI 3 "=r"))]
12239 "TARGET_POWER"
12240 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12241 [(set_attr "length" "12")])
12243 (define_insn ""
12244 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12245 (compare:CC
12246 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12247 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12248 (const_int 0)))
12249 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12250 (ge:SI (match_dup 1) (match_dup 2)))
12251 (clobber (match_scratch:SI 3 "=r,r"))]
12252 "TARGET_POWER"
12253 "@
12254 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12255 #"
12256 [(set_attr "type" "compare")
12257 (set_attr "length" "12,16")])
12259 (define_split
12260 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12261 (compare:CC
12262 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12263 (match_operand:SI 2 "reg_or_short_operand" ""))
12264 (const_int 0)))
12265 (set (match_operand:SI 0 "gpc_reg_operand" "")
12266 (ge:SI (match_dup 1) (match_dup 2)))
12267 (clobber (match_scratch:SI 3 ""))]
12268 "TARGET_POWER && reload_completed"
12269 [(parallel [(set (match_dup 0)
12270 (ge:SI (match_dup 1) (match_dup 2)))
12271 (clobber (match_dup 3))])
12272 (set (match_dup 4)
12273 (compare:CC (match_dup 0)
12274 (const_int 0)))]
12275 "")
12277 (define_insn ""
12278 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12279 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12280 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12281 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12282 "TARGET_POWER"
12283 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12284 [(set_attr "length" "12")])
12286 (define_insn ""
12287 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12288 (compare:CC
12289 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12290 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12291 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12292 (const_int 0)))
12293 (clobber (match_scratch:SI 4 "=&r,&r"))]
12294 "TARGET_POWER"
12295 "@
12296 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12297 #"
12298 [(set_attr "type" "compare")
12299 (set_attr "length" "12,16")])
12301 (define_split
12302 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12303 (compare:CC
12304 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12305 (match_operand:SI 2 "reg_or_short_operand" ""))
12306 (match_operand:SI 3 "gpc_reg_operand" ""))
12307 (const_int 0)))
12308 (clobber (match_scratch:SI 4 ""))]
12309 "TARGET_POWER && reload_completed"
12310 [(set (match_dup 4)
12311 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12312 (match_dup 3)))
12313 (set (match_dup 0)
12314 (compare:CC (match_dup 4)
12315 (const_int 0)))]
12316 "")
12318 (define_insn ""
12319 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12320 (compare:CC
12321 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12322 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12323 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12324 (const_int 0)))
12325 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12326 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12327 "TARGET_POWER"
12328 "@
12329 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12330 #"
12331 [(set_attr "type" "compare")
12332 (set_attr "length" "12,16")])
12334 (define_split
12335 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12336 (compare:CC
12337 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12338 (match_operand:SI 2 "reg_or_short_operand" ""))
12339 (match_operand:SI 3 "gpc_reg_operand" ""))
12340 (const_int 0)))
12341 (set (match_operand:SI 0 "gpc_reg_operand" "")
12342 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12343 "TARGET_POWER && reload_completed"
12344 [(set (match_dup 0)
12345 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12346 (set (match_dup 4)
12347 (compare:CC (match_dup 0)
12348 (const_int 0)))]
12349 "")
12351 (define_insn ""
12352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12353 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12354 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12355 "TARGET_POWER"
12356 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12357 [(set_attr "length" "12")])
12359 (define_insn ""
12360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12361 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12362 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12363 "TARGET_32BIT"
12364 "@
12365 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12366 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12367 [(set_attr "type" "three")
12368 (set_attr "length" "12")])
12370 (define_insn ""
12371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12372 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12373 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12374 "TARGET_64BIT"
12375 "@
12376 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12377 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12378 [(set_attr "type" "three")
12379 (set_attr "length" "12")])
12381 (define_insn ""
12382 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12383 (compare:CC
12384 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12385 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12386 (const_int 0)))
12387 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12388 (geu:SI (match_dup 1) (match_dup 2)))]
12389 "TARGET_32BIT"
12390 "@
12391 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12392 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12393 #
12394 #"
12395 [(set_attr "type" "compare")
12396 (set_attr "length" "12,12,16,16")])
12398 (define_split
12399 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12400 (compare:CC
12401 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12402 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12403 (const_int 0)))
12404 (set (match_operand:SI 0 "gpc_reg_operand" "")
12405 (geu:SI (match_dup 1) (match_dup 2)))]
12406 "TARGET_32BIT && reload_completed"
12407 [(set (match_dup 0)
12408 (geu:SI (match_dup 1) (match_dup 2)))
12409 (set (match_dup 3)
12410 (compare:CC (match_dup 0)
12411 (const_int 0)))]
12412 "")
12414 (define_insn ""
12415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12416 (compare:CC
12417 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12418 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12419 (const_int 0)))
12420 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12421 (geu:DI (match_dup 1) (match_dup 2)))]
12422 "TARGET_64BIT"
12423 "@
12424 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12425 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12426 #
12427 #"
12428 [(set_attr "type" "compare")
12429 (set_attr "length" "12,12,16,16")])
12431 (define_split
12432 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12433 (compare:CC
12434 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12435 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12436 (const_int 0)))
12437 (set (match_operand:DI 0 "gpc_reg_operand" "")
12438 (geu:DI (match_dup 1) (match_dup 2)))]
12439 "TARGET_64BIT && reload_completed"
12440 [(set (match_dup 0)
12441 (geu:DI (match_dup 1) (match_dup 2)))
12442 (set (match_dup 3)
12443 (compare:CC (match_dup 0)
12444 (const_int 0)))]
12445 "")
12447 (define_insn ""
12448 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12449 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12450 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12451 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12452 "TARGET_32BIT"
12453 "@
12454 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12455 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12456 [(set_attr "type" "two")
12457 (set_attr "length" "8")])
12459 (define_insn ""
12460 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12461 (compare:CC
12462 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12463 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12464 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12465 (const_int 0)))
12466 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12467 "TARGET_32BIT"
12468 "@
12469 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12470 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12471 #
12472 #"
12473 [(set_attr "type" "compare")
12474 (set_attr "length" "8,8,12,12")])
12476 (define_split
12477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12478 (compare:CC
12479 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12480 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12481 (match_operand:SI 3 "gpc_reg_operand" ""))
12482 (const_int 0)))
12483 (clobber (match_scratch:SI 4 ""))]
12484 "TARGET_32BIT && reload_completed"
12485 [(set (match_dup 4)
12486 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12487 (match_dup 3)))
12488 (set (match_dup 0)
12489 (compare:CC (match_dup 4)
12490 (const_int 0)))]
12491 "")
12493 (define_insn ""
12494 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12495 (compare:CC
12496 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12497 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12498 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12499 (const_int 0)))
12500 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12501 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12502 "TARGET_32BIT"
12503 "@
12504 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12505 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12506 #
12507 #"
12508 [(set_attr "type" "compare")
12509 (set_attr "length" "8,8,12,12")])
12511 (define_split
12512 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12513 (compare:CC
12514 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12515 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12516 (match_operand:SI 3 "gpc_reg_operand" ""))
12517 (const_int 0)))
12518 (set (match_operand:SI 0 "gpc_reg_operand" "")
12519 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12520 "TARGET_32BIT && reload_completed"
12521 [(set (match_dup 0)
12522 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12523 (set (match_dup 4)
12524 (compare:CC (match_dup 0)
12525 (const_int 0)))]
12526 "")
12528 (define_insn ""
12529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12530 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12531 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12532 "TARGET_32BIT"
12533 "@
12534 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12535 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12536 [(set_attr "type" "three")
12537 (set_attr "length" "12")])
12539 (define_insn ""
12540 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12541 (and:SI (neg:SI
12542 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12543 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12544 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12545 "TARGET_32BIT"
12546 "@
12547 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12548 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12549 [(set_attr "type" "three")
12550 (set_attr "length" "12")])
12552 (define_insn ""
12553 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12554 (compare:CC
12555 (and:SI (neg:SI
12556 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12557 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12558 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12559 (const_int 0)))
12560 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12561 "TARGET_32BIT"
12562 "@
12563 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12564 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12565 #
12566 #"
12567 [(set_attr "type" "compare")
12568 (set_attr "length" "12,12,16,16")])
12570 (define_split
12571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12572 (compare:CC
12573 (and:SI (neg:SI
12574 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12575 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12576 (match_operand:SI 3 "gpc_reg_operand" ""))
12577 (const_int 0)))
12578 (clobber (match_scratch:SI 4 ""))]
12579 "TARGET_32BIT && reload_completed"
12580 [(set (match_dup 4)
12581 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12582 (match_dup 3)))
12583 (set (match_dup 0)
12584 (compare:CC (match_dup 4)
12585 (const_int 0)))]
12586 "")
12588 (define_insn ""
12589 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12590 (compare:CC
12591 (and:SI (neg:SI
12592 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12593 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12594 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12595 (const_int 0)))
12596 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12597 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12598 "TARGET_32BIT"
12599 "@
12600 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12601 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12602 #
12603 #"
12604 [(set_attr "type" "compare")
12605 (set_attr "length" "12,12,16,16")])
12607 (define_split
12608 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12609 (compare:CC
12610 (and:SI (neg:SI
12611 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12612 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12613 (match_operand:SI 3 "gpc_reg_operand" ""))
12614 (const_int 0)))
12615 (set (match_operand:SI 0 "gpc_reg_operand" "")
12616 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12617 "TARGET_32BIT && reload_completed"
12618 [(set (match_dup 0)
12619 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12620 (set (match_dup 4)
12621 (compare:CC (match_dup 0)
12622 (const_int 0)))]
12623 "")
12625 (define_insn ""
12626 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12627 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12628 (const_int 0)))]
12629 "TARGET_32BIT"
12630 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12631 [(set_attr "type" "three")
12632 (set_attr "length" "12")])
12634 (define_insn ""
12635 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12636 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12637 (const_int 0)))]
12638 "TARGET_64BIT"
12639 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12640 [(set_attr "type" "three")
12641 (set_attr "length" "12")])
12643 (define_insn ""
12644 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12645 (compare:CC
12646 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12647 (const_int 0))
12648 (const_int 0)))
12649 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12650 (gt:SI (match_dup 1) (const_int 0)))]
12651 "TARGET_32BIT"
12652 "@
12653 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12654 #"
12655 [(set_attr "type" "delayed_compare")
12656 (set_attr "length" "12,16")])
12658 (define_split
12659 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12660 (compare:CC
12661 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12662 (const_int 0))
12663 (const_int 0)))
12664 (set (match_operand:SI 0 "gpc_reg_operand" "")
12665 (gt:SI (match_dup 1) (const_int 0)))]
12666 "TARGET_32BIT && reload_completed"
12667 [(set (match_dup 0)
12668 (gt:SI (match_dup 1) (const_int 0)))
12669 (set (match_dup 2)
12670 (compare:CC (match_dup 0)
12671 (const_int 0)))]
12672 "")
12674 (define_insn ""
12675 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12676 (compare:CC
12677 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12678 (const_int 0))
12679 (const_int 0)))
12680 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12681 (gt:DI (match_dup 1) (const_int 0)))]
12682 "TARGET_64BIT"
12683 "@
12684 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12685 #"
12686 [(set_attr "type" "delayed_compare")
12687 (set_attr "length" "12,16")])
12689 (define_split
12690 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12691 (compare:CC
12692 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12693 (const_int 0))
12694 (const_int 0)))
12695 (set (match_operand:DI 0 "gpc_reg_operand" "")
12696 (gt:DI (match_dup 1) (const_int 0)))]
12697 "TARGET_64BIT && reload_completed"
12698 [(set (match_dup 0)
12699 (gt:DI (match_dup 1) (const_int 0)))
12700 (set (match_dup 2)
12701 (compare:CC (match_dup 0)
12702 (const_int 0)))]
12703 "")
12705 (define_insn ""
12706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12707 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12708 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12709 "TARGET_POWER"
12710 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12711 [(set_attr "length" "12")])
12713 (define_insn ""
12714 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12715 (compare:CC
12716 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12717 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12718 (const_int 0)))
12719 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12720 (gt:SI (match_dup 1) (match_dup 2)))]
12721 "TARGET_POWER"
12722 "@
12723 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12724 #"
12725 [(set_attr "type" "delayed_compare")
12726 (set_attr "length" "12,16")])
12728 (define_split
12729 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12730 (compare:CC
12731 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12732 (match_operand:SI 2 "reg_or_short_operand" ""))
12733 (const_int 0)))
12734 (set (match_operand:SI 0 "gpc_reg_operand" "")
12735 (gt:SI (match_dup 1) (match_dup 2)))]
12736 "TARGET_POWER && reload_completed"
12737 [(set (match_dup 0)
12738 (gt:SI (match_dup 1) (match_dup 2)))
12739 (set (match_dup 3)
12740 (compare:CC (match_dup 0)
12741 (const_int 0)))]
12742 "")
12744 (define_insn ""
12745 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12746 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12747 (const_int 0))
12748 (match_operand:SI 2 "gpc_reg_operand" "r")))]
12749 "TARGET_32BIT"
12750 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
12751 [(set_attr "type" "three")
12752 (set_attr "length" "12")])
12754 (define_insn ""
12755 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
12756 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12757 (const_int 0))
12758 (match_operand:DI 2 "gpc_reg_operand" "r")))]
12759 "TARGET_64BIT"
12760 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12761 [(set_attr "type" "three")
12762 (set_attr "length" "12")])
12764 (define_insn ""
12765 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12766 (compare:CC
12767 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12768 (const_int 0))
12769 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12770 (const_int 0)))
12771 (clobber (match_scratch:SI 3 "=&r,&r"))]
12772 "TARGET_32BIT"
12773 "@
12774 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12775 #"
12776 [(set_attr "type" "compare")
12777 (set_attr "length" "12,16")])
12779 (define_split
12780 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12781 (compare:CC
12782 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12783 (const_int 0))
12784 (match_operand:SI 2 "gpc_reg_operand" ""))
12785 (const_int 0)))
12786 (clobber (match_scratch:SI 3 ""))]
12787 "TARGET_32BIT && reload_completed"
12788 [(set (match_dup 3)
12789 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12790 (match_dup 2)))
12791 (set (match_dup 0)
12792 (compare:CC (match_dup 3)
12793 (const_int 0)))]
12794 "")
12796 (define_insn ""
12797 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12798 (compare:CC
12799 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12800 (const_int 0))
12801 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12802 (const_int 0)))
12803 (clobber (match_scratch:DI 3 "=&r,&r"))]
12804 "TARGET_64BIT"
12805 "@
12806 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12807 #"
12808 [(set_attr "type" "compare")
12809 (set_attr "length" "12,16")])
12811 (define_split
12812 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12813 (compare:CC
12814 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12815 (const_int 0))
12816 (match_operand:DI 2 "gpc_reg_operand" ""))
12817 (const_int 0)))
12818 (clobber (match_scratch:DI 3 ""))]
12819 "TARGET_64BIT && reload_completed"
12820 [(set (match_dup 3)
12821 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12822 (match_dup 2)))
12823 (set (match_dup 0)
12824 (compare:CC (match_dup 3)
12825 (const_int 0)))]
12826 "")
12828 (define_insn ""
12829 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12830 (compare:CC
12831 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12832 (const_int 0))
12833 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12834 (const_int 0)))
12835 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12836 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12837 "TARGET_32BIT"
12838 "@
12839 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
12840 #"
12841 [(set_attr "type" "compare")
12842 (set_attr "length" "12,16")])
12844 (define_split
12845 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12846 (compare:CC
12847 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12848 (const_int 0))
12849 (match_operand:SI 2 "gpc_reg_operand" ""))
12850 (const_int 0)))
12851 (set (match_operand:SI 0 "gpc_reg_operand" "")
12852 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12853 "TARGET_32BIT && reload_completed"
12854 [(set (match_dup 0)
12855 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12856 (set (match_dup 3)
12857 (compare:CC (match_dup 0)
12858 (const_int 0)))]
12859 "")
12861 (define_insn ""
12862 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12863 (compare:CC
12864 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12865 (const_int 0))
12866 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12867 (const_int 0)))
12868 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12869 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12870 "TARGET_64BIT"
12871 "@
12872 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12873 #"
12874 [(set_attr "type" "compare")
12875 (set_attr "length" "12,16")])
12877 (define_split
12878 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12879 (compare:CC
12880 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12881 (const_int 0))
12882 (match_operand:DI 2 "gpc_reg_operand" ""))
12883 (const_int 0)))
12884 (set (match_operand:DI 0 "gpc_reg_operand" "")
12885 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12886 "TARGET_64BIT && reload_completed"
12887 [(set (match_dup 0)
12888 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12889 (set (match_dup 3)
12890 (compare:CC (match_dup 0)
12891 (const_int 0)))]
12892 "")
12894 (define_insn ""
12895 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12896 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12897 (match_operand:SI 2 "reg_or_short_operand" "r"))
12898 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12899 "TARGET_POWER"
12900 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12901 [(set_attr "length" "12")])
12903 (define_insn ""
12904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12905 (compare:CC
12906 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12907 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12908 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12909 (const_int 0)))
12910 (clobber (match_scratch:SI 4 "=&r,&r"))]
12911 "TARGET_POWER"
12912 "@
12913 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12914 #"
12915 [(set_attr "type" "compare")
12916 (set_attr "length" "12,16")])
12918 (define_split
12919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12920 (compare:CC
12921 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12922 (match_operand:SI 2 "reg_or_short_operand" ""))
12923 (match_operand:SI 3 "gpc_reg_operand" ""))
12924 (const_int 0)))
12925 (clobber (match_scratch:SI 4 ""))]
12926 "TARGET_POWER && reload_completed"
12927 [(set (match_dup 4)
12928 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12929 (set (match_dup 0)
12930 (compare:CC (match_dup 4)
12931 (const_int 0)))]
12932 "")
12934 (define_insn ""
12935 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12936 (compare:CC
12937 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12938 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12939 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12940 (const_int 0)))
12941 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12942 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12943 "TARGET_POWER"
12944 "@
12945 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12946 #"
12947 [(set_attr "type" "compare")
12948 (set_attr "length" "12,16")])
12950 (define_split
12951 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12952 (compare:CC
12953 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12954 (match_operand:SI 2 "reg_or_short_operand" ""))
12955 (match_operand:SI 3 "gpc_reg_operand" ""))
12956 (const_int 0)))
12957 (set (match_operand:SI 0 "gpc_reg_operand" "")
12958 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12959 "TARGET_POWER && reload_completed"
12960 [(set (match_dup 0)
12961 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12962 (set (match_dup 4)
12963 (compare:CC (match_dup 0)
12964 (const_int 0)))]
12965 "")
12967 (define_insn ""
12968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12969 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12970 (const_int 0))))]
12971 "TARGET_32BIT"
12972 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
12973 [(set_attr "type" "three")
12974 (set_attr "length" "12")])
12976 (define_insn ""
12977 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12978 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12979 (const_int 0))))]
12980 "TARGET_64BIT"
12981 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
12982 [(set_attr "type" "three")
12983 (set_attr "length" "12")])
12985 (define_insn ""
12986 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12987 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12988 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12989 "TARGET_POWER"
12990 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12991 [(set_attr "length" "12")])
12993 (define_insn_and_split ""
12994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12995 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12996 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12997 "TARGET_32BIT"
12998 "#"
12999 "TARGET_32BIT"
13000 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13001 (set (match_dup 0) (neg:SI (match_dup 0)))]
13002 "")
13004 (define_insn_and_split ""
13005 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13006 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13007 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13008 "TARGET_64BIT"
13009 "#"
13010 "TARGET_64BIT"
13011 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13012 (set (match_dup 0) (neg:DI (match_dup 0)))]
13013 "")
13015 (define_insn ""
13016 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13017 (compare:CC
13018 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13019 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13020 (const_int 0)))
13021 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13022 (gtu:SI (match_dup 1) (match_dup 2)))]
13023 "TARGET_32BIT"
13024 "@
13025 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13026 #"
13027 [(set_attr "type" "compare")
13028 (set_attr "length" "12,16")])
13030 (define_split
13031 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13032 (compare:CC
13033 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13034 (match_operand:SI 2 "reg_or_short_operand" ""))
13035 (const_int 0)))
13036 (set (match_operand:SI 0 "gpc_reg_operand" "")
13037 (gtu:SI (match_dup 1) (match_dup 2)))]
13038 "TARGET_32BIT && reload_completed"
13039 [(set (match_dup 0)
13040 (gtu:SI (match_dup 1) (match_dup 2)))
13041 (set (match_dup 3)
13042 (compare:CC (match_dup 0)
13043 (const_int 0)))]
13044 "")
13046 (define_insn ""
13047 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13048 (compare:CC
13049 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13050 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13051 (const_int 0)))
13052 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13053 (gtu:DI (match_dup 1) (match_dup 2)))]
13054 "TARGET_64BIT"
13055 "@
13056 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13057 #"
13058 [(set_attr "type" "compare")
13059 (set_attr "length" "12,16")])
13061 (define_split
13062 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13063 (compare:CC
13064 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13065 (match_operand:DI 2 "reg_or_short_operand" ""))
13066 (const_int 0)))
13067 (set (match_operand:DI 0 "gpc_reg_operand" "")
13068 (gtu:DI (match_dup 1) (match_dup 2)))]
13069 "TARGET_64BIT && reload_completed"
13070 [(set (match_dup 0)
13071 (gtu:DI (match_dup 1) (match_dup 2)))
13072 (set (match_dup 3)
13073 (compare:CC (match_dup 0)
13074 (const_int 0)))]
13075 "")
13077 (define_insn_and_split ""
13078 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13079 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13080 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13081 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13082 "TARGET_32BIT"
13083 "#"
13084 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13085 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13086 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13087 "")
13089 (define_insn_and_split ""
13090 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13091 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13092 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13093 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13094 "TARGET_64BIT"
13095 "#"
13096 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13097 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13098 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13099 "")
13101 (define_insn ""
13102 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13103 (compare:CC
13104 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13105 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13106 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13107 (const_int 0)))
13108 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13109 "TARGET_32BIT"
13110 "@
13111 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13112 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13113 #
13114 #"
13115 [(set_attr "type" "compare")
13116 (set_attr "length" "8,12,12,16")])
13118 (define_split
13119 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13120 (compare:CC
13121 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13122 (match_operand:SI 2 "reg_or_short_operand" ""))
13123 (match_operand:SI 3 "gpc_reg_operand" ""))
13124 (const_int 0)))
13125 (clobber (match_scratch:SI 4 ""))]
13126 "TARGET_32BIT && reload_completed"
13127 [(set (match_dup 4)
13128 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13129 (match_dup 3)))
13130 (set (match_dup 0)
13131 (compare:CC (match_dup 4)
13132 (const_int 0)))]
13133 "")
13135 (define_insn ""
13136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13137 (compare:CC
13138 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13139 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13140 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13141 (const_int 0)))
13142 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13143 "TARGET_64BIT"
13144 "@
13145 addic %4,%1,%k2\;addze. %4,%3
13146 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13147 #
13148 #"
13149 [(set_attr "type" "compare")
13150 (set_attr "length" "8,12,12,16")])
13152 (define_split
13153 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13154 (compare:CC
13155 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13156 (match_operand:DI 2 "reg_or_short_operand" ""))
13157 (match_operand:DI 3 "gpc_reg_operand" ""))
13158 (const_int 0)))
13159 (clobber (match_scratch:DI 4 ""))]
13160 "TARGET_64BIT && reload_completed"
13161 [(set (match_dup 4)
13162 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13163 (match_dup 3)))
13164 (set (match_dup 0)
13165 (compare:CC (match_dup 4)
13166 (const_int 0)))]
13167 "")
13169 (define_insn ""
13170 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13171 (compare:CC
13172 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13173 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13174 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13175 (const_int 0)))
13176 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13177 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13178 "TARGET_32BIT"
13179 "@
13180 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13181 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13182 #
13183 #"
13184 [(set_attr "type" "compare")
13185 (set_attr "length" "8,12,12,16")])
13187 (define_split
13188 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13189 (compare:CC
13190 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13191 (match_operand:SI 2 "reg_or_short_operand" ""))
13192 (match_operand:SI 3 "gpc_reg_operand" ""))
13193 (const_int 0)))
13194 (set (match_operand:SI 0 "gpc_reg_operand" "")
13195 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13196 "TARGET_32BIT && reload_completed"
13197 [(set (match_dup 0)
13198 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13199 (set (match_dup 4)
13200 (compare:CC (match_dup 0)
13201 (const_int 0)))]
13202 "")
13204 (define_insn ""
13205 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13206 (compare:CC
13207 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13208 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13209 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13210 (const_int 0)))
13211 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13212 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13213 "TARGET_64BIT"
13214 "@
13215 addic %0,%1,%k2\;addze. %0,%3
13216 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13217 #
13218 #"
13219 [(set_attr "type" "compare")
13220 (set_attr "length" "8,12,12,16")])
13222 (define_split
13223 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13224 (compare:CC
13225 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13226 (match_operand:DI 2 "reg_or_short_operand" ""))
13227 (match_operand:DI 3 "gpc_reg_operand" ""))
13228 (const_int 0)))
13229 (set (match_operand:DI 0 "gpc_reg_operand" "")
13230 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13231 "TARGET_64BIT && reload_completed"
13232 [(set (match_dup 0)
13233 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13234 (set (match_dup 4)
13235 (compare:CC (match_dup 0)
13236 (const_int 0)))]
13237 "")
13239 (define_insn ""
13240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13241 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13242 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13243 "TARGET_32BIT"
13244 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13245 [(set_attr "type" "two")
13246 (set_attr "length" "8")])
13248 (define_insn ""
13249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13250 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13251 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13252 "TARGET_64BIT"
13253 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13254 [(set_attr "type" "two")
13255 (set_attr "length" "8")])
13256 \f
13257 ;; Define both directions of branch and return. If we need a reload
13258 ;; register, we'd rather use CR0 since it is much easier to copy a
13259 ;; register CC value to there.
13261 (define_insn ""
13262 [(set (pc)
13263 (if_then_else (match_operator 1 "branch_comparison_operator"
13264 [(match_operand 2
13265 "cc_reg_operand" "y")
13266 (const_int 0)])
13267 (label_ref (match_operand 0 "" ""))
13268 (pc)))]
13269 ""
13270 "*
13271 {
13272 return output_cbranch (operands[1], \"%l0\", 0, insn);
13273 }"
13274 [(set_attr "type" "branch")])
13276 (define_insn ""
13277 [(set (pc)
13278 (if_then_else (match_operator 0 "branch_comparison_operator"
13279 [(match_operand 1
13280 "cc_reg_operand" "y")
13281 (const_int 0)])
13282 (return)
13283 (pc)))]
13284 "direct_return ()"
13285 "*
13286 {
13287 return output_cbranch (operands[0], NULL, 0, insn);
13288 }"
13289 [(set_attr "type" "branch")
13290 (set_attr "length" "4")])
13292 (define_insn ""
13293 [(set (pc)
13294 (if_then_else (match_operator 1 "branch_comparison_operator"
13295 [(match_operand 2
13296 "cc_reg_operand" "y")
13297 (const_int 0)])
13298 (pc)
13299 (label_ref (match_operand 0 "" ""))))]
13300 ""
13301 "*
13302 {
13303 return output_cbranch (operands[1], \"%l0\", 1, insn);
13304 }"
13305 [(set_attr "type" "branch")])
13307 (define_insn ""
13308 [(set (pc)
13309 (if_then_else (match_operator 0 "branch_comparison_operator"
13310 [(match_operand 1
13311 "cc_reg_operand" "y")
13312 (const_int 0)])
13313 (pc)
13314 (return)))]
13315 "direct_return ()"
13316 "*
13317 {
13318 return output_cbranch (operands[0], NULL, 1, insn);
13319 }"
13320 [(set_attr "type" "branch")
13321 (set_attr "length" "4")])
13323 ;; Logic on condition register values.
13325 ; This pattern matches things like
13326 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13327 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13328 ; (const_int 1)))
13329 ; which are generated by the branch logic.
13330 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13332 (define_insn "*cceq_ior_compare"
13333 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13334 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13335 [(match_operator:SI 2
13336 "branch_positive_comparison_operator"
13337 [(match_operand 3
13338 "cc_reg_operand" "y,y")
13339 (const_int 0)])
13340 (match_operator:SI 4
13341 "branch_positive_comparison_operator"
13342 [(match_operand 5
13343 "cc_reg_operand" "0,y")
13344 (const_int 0)])])
13345 (const_int 1)))]
13346 ""
13347 "cr%q1 %E0,%j2,%j4"
13348 [(set_attr "type" "cr_logical,delayed_cr")])
13350 ; Why is the constant -1 here, but 1 in the previous pattern?
13351 ; Because ~1 has all but the low bit set.
13352 (define_insn ""
13353 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13354 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13355 [(not:SI (match_operator:SI 2
13356 "branch_positive_comparison_operator"
13357 [(match_operand 3
13358 "cc_reg_operand" "y,y")
13359 (const_int 0)]))
13360 (match_operator:SI 4
13361 "branch_positive_comparison_operator"
13362 [(match_operand 5
13363 "cc_reg_operand" "0,y")
13364 (const_int 0)])])
13365 (const_int -1)))]
13366 ""
13367 "cr%q1 %E0,%j2,%j4"
13368 [(set_attr "type" "cr_logical,delayed_cr")])
13370 (define_insn "*cceq_rev_compare"
13371 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13372 (compare:CCEQ (match_operator:SI 1
13373 "branch_positive_comparison_operator"
13374 [(match_operand 2
13375 "cc_reg_operand" "0,y")
13376 (const_int 0)])
13377 (const_int 0)))]
13378 ""
13379 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13380 [(set_attr "type" "cr_logical,delayed_cr")])
13382 ;; If we are comparing the result of two comparisons, this can be done
13383 ;; using creqv or crxor.
13385 (define_insn_and_split ""
13386 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13387 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13388 [(match_operand 2 "cc_reg_operand" "y")
13389 (const_int 0)])
13390 (match_operator 3 "branch_comparison_operator"
13391 [(match_operand 4 "cc_reg_operand" "y")
13392 (const_int 0)])))]
13393 ""
13394 "#"
13395 ""
13396 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13397 (match_dup 5)))]
13398 "
13399 {
13400 int positive_1, positive_2;
13402 positive_1 = branch_positive_comparison_operator (operands[1],
13403 GET_MODE (operands[1]));
13404 positive_2 = branch_positive_comparison_operator (operands[3],
13405 GET_MODE (operands[3]));
13407 if (! positive_1)
13408 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13409 GET_CODE (operands[1])),
13410 SImode,
13411 operands[2], const0_rtx);
13412 else if (GET_MODE (operands[1]) != SImode)
13413 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13414 operands[2], const0_rtx);
13416 if (! positive_2)
13417 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13418 GET_CODE (operands[3])),
13419 SImode,
13420 operands[4], const0_rtx);
13421 else if (GET_MODE (operands[3]) != SImode)
13422 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13423 operands[4], const0_rtx);
13425 if (positive_1 == positive_2)
13426 {
13427 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13428 operands[5] = constm1_rtx;
13429 }
13430 else
13431 {
13432 operands[5] = const1_rtx;
13433 }
13434 }")
13436 ;; Unconditional branch and return.
13438 (define_insn "jump"
13439 [(set (pc)
13440 (label_ref (match_operand 0 "" "")))]
13441 ""
13442 "b %l0"
13443 [(set_attr "type" "branch")])
13445 (define_insn "return"
13446 [(return)]
13447 "direct_return ()"
13448 "{br|blr}"
13449 [(set_attr "type" "jmpreg")])
13451 (define_expand "indirect_jump"
13452 [(set (pc) (match_operand 0 "register_operand" ""))])
13454 (define_insn "*indirect_jump<mode>"
13455 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13456 ""
13457 "@
13458 bctr
13459 {br|blr}"
13460 [(set_attr "type" "jmpreg")])
13462 ;; Table jump for switch statements:
13463 (define_expand "tablejump"
13464 [(use (match_operand 0 "" ""))
13465 (use (label_ref (match_operand 1 "" "")))]
13466 ""
13467 "
13468 {
13469 if (TARGET_32BIT)
13470 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13471 else
13472 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13473 DONE;
13474 }")
13476 (define_expand "tablejumpsi"
13477 [(set (match_dup 3)
13478 (plus:SI (match_operand:SI 0 "" "")
13479 (match_dup 2)))
13480 (parallel [(set (pc) (match_dup 3))
13481 (use (label_ref (match_operand 1 "" "")))])]
13482 "TARGET_32BIT"
13483 "
13484 { operands[0] = force_reg (SImode, operands[0]);
13485 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13486 operands[3] = gen_reg_rtx (SImode);
13487 }")
13489 (define_expand "tablejumpdi"
13490 [(set (match_dup 4)
13491 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13492 (set (match_dup 3)
13493 (plus:DI (match_dup 4)
13494 (match_dup 2)))
13495 (parallel [(set (pc) (match_dup 3))
13496 (use (label_ref (match_operand 1 "" "")))])]
13497 "TARGET_64BIT"
13498 "
13499 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13500 operands[3] = gen_reg_rtx (DImode);
13501 operands[4] = gen_reg_rtx (DImode);
13502 }")
13504 (define_insn ""
13505 [(set (pc)
13506 (match_operand:P 0 "register_operand" "c,*l"))
13507 (use (label_ref (match_operand 1 "" "")))]
13508 ""
13509 "@
13510 bctr
13511 {br|blr}"
13512 [(set_attr "type" "jmpreg")])
13514 (define_insn "nop"
13515 [(const_int 0)]
13516 ""
13517 "{cror 0,0,0|nop}")
13518 \f
13519 ;; Define the subtract-one-and-jump insns, starting with the template
13520 ;; so loop.c knows what to generate.
13522 (define_expand "doloop_end"
13523 [(use (match_operand 0 "" "")) ; loop pseudo
13524 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13525 (use (match_operand 2 "" "")) ; max iterations
13526 (use (match_operand 3 "" "")) ; loop level
13527 (use (match_operand 4 "" ""))] ; label
13528 ""
13529 "
13530 {
13531 /* Only use this on innermost loops. */
13532 if (INTVAL (operands[3]) > 1)
13533 FAIL;
13534 if (TARGET_64BIT)
13535 {
13536 if (GET_MODE (operands[0]) != DImode)
13537 FAIL;
13538 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13539 }
13540 else
13541 {
13542 if (GET_MODE (operands[0]) != SImode)
13543 FAIL;
13544 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13545 }
13546 DONE;
13547 }")
13549 (define_expand "ctr<mode>"
13550 [(parallel [(set (pc)
13551 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13552 (const_int 1))
13553 (label_ref (match_operand 1 "" ""))
13554 (pc)))
13555 (set (match_dup 0)
13556 (plus:P (match_dup 0)
13557 (const_int -1)))
13558 (clobber (match_scratch:CC 2 ""))
13559 (clobber (match_scratch:P 3 ""))])]
13560 ""
13561 "")
13563 ;; We need to be able to do this for any operand, including MEM, or we
13564 ;; will cause reload to blow up since we don't allow output reloads on
13565 ;; JUMP_INSNs.
13566 ;; For the length attribute to be calculated correctly, the
13567 ;; label MUST be operand 0.
13569 (define_insn "*ctr<mode>_internal1"
13570 [(set (pc)
13571 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13572 (const_int 1))
13573 (label_ref (match_operand 0 "" ""))
13574 (pc)))
13575 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13576 (plus:P (match_dup 1)
13577 (const_int -1)))
13578 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13579 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13580 ""
13581 "*
13582 {
13583 if (which_alternative != 0)
13584 return \"#\";
13585 else if (get_attr_length (insn) == 4)
13586 return \"{bdn|bdnz} %l0\";
13587 else
13588 return \"bdz $+8\;b %l0\";
13589 }"
13590 [(set_attr "type" "branch")
13591 (set_attr "length" "*,12,16,16")])
13593 (define_insn "*ctr<mode>_internal2"
13594 [(set (pc)
13595 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13596 (const_int 1))
13597 (pc)
13598 (label_ref (match_operand 0 "" ""))))
13599 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13600 (plus:P (match_dup 1)
13601 (const_int -1)))
13602 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13603 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13604 ""
13605 "*
13606 {
13607 if (which_alternative != 0)
13608 return \"#\";
13609 else if (get_attr_length (insn) == 4)
13610 return \"bdz %l0\";
13611 else
13612 return \"{bdn|bdnz} $+8\;b %l0\";
13613 }"
13614 [(set_attr "type" "branch")
13615 (set_attr "length" "*,12,16,16")])
13617 ;; Similar but use EQ
13619 (define_insn "*ctr<mode>_internal5"
13620 [(set (pc)
13621 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13622 (const_int 1))
13623 (label_ref (match_operand 0 "" ""))
13624 (pc)))
13625 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13626 (plus:P (match_dup 1)
13627 (const_int -1)))
13628 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13629 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13630 ""
13631 "*
13632 {
13633 if (which_alternative != 0)
13634 return \"#\";
13635 else if (get_attr_length (insn) == 4)
13636 return \"bdz %l0\";
13637 else
13638 return \"{bdn|bdnz} $+8\;b %l0\";
13639 }"
13640 [(set_attr "type" "branch")
13641 (set_attr "length" "*,12,16,16")])
13643 (define_insn "*ctr<mode>_internal6"
13644 [(set (pc)
13645 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13646 (const_int 1))
13647 (pc)
13648 (label_ref (match_operand 0 "" ""))))
13649 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13650 (plus:P (match_dup 1)
13651 (const_int -1)))
13652 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13653 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13654 ""
13655 "*
13656 {
13657 if (which_alternative != 0)
13658 return \"#\";
13659 else if (get_attr_length (insn) == 4)
13660 return \"{bdn|bdnz} %l0\";
13661 else
13662 return \"bdz $+8\;b %l0\";
13663 }"
13664 [(set_attr "type" "branch")
13665 (set_attr "length" "*,12,16,16")])
13667 ;; Now the splitters if we could not allocate the CTR register
13669 (define_split
13670 [(set (pc)
13671 (if_then_else (match_operator 2 "comparison_operator"
13672 [(match_operand:P 1 "gpc_reg_operand" "")
13673 (const_int 1)])
13674 (match_operand 5 "" "")
13675 (match_operand 6 "" "")))
13676 (set (match_operand:P 0 "gpc_reg_operand" "")
13677 (plus:P (match_dup 1) (const_int -1)))
13678 (clobber (match_scratch:CC 3 ""))
13679 (clobber (match_scratch:P 4 ""))]
13680 "reload_completed"
13681 [(parallel [(set (match_dup 3)
13682 (compare:CC (plus:P (match_dup 1)
13683 (const_int -1))
13684 (const_int 0)))
13685 (set (match_dup 0)
13686 (plus:P (match_dup 1)
13687 (const_int -1)))])
13688 (set (pc) (if_then_else (match_dup 7)
13689 (match_dup 5)
13690 (match_dup 6)))]
13691 "
13692 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13693 operands[3], const0_rtx); }")
13695 (define_split
13696 [(set (pc)
13697 (if_then_else (match_operator 2 "comparison_operator"
13698 [(match_operand:P 1 "gpc_reg_operand" "")
13699 (const_int 1)])
13700 (match_operand 5 "" "")
13701 (match_operand 6 "" "")))
13702 (set (match_operand:P 0 "nonimmediate_operand" "")
13703 (plus:P (match_dup 1) (const_int -1)))
13704 (clobber (match_scratch:CC 3 ""))
13705 (clobber (match_scratch:P 4 ""))]
13706 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13707 [(parallel [(set (match_dup 3)
13708 (compare:CC (plus:P (match_dup 1)
13709 (const_int -1))
13710 (const_int 0)))
13711 (set (match_dup 4)
13712 (plus:P (match_dup 1)
13713 (const_int -1)))])
13714 (set (match_dup 0)
13715 (match_dup 4))
13716 (set (pc) (if_then_else (match_dup 7)
13717 (match_dup 5)
13718 (match_dup 6)))]
13719 "
13720 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13721 operands[3], const0_rtx); }")
13722 \f
13723 (define_insn "trap"
13724 [(trap_if (const_int 1) (const_int 0))]
13725 ""
13726 "{t 31,0,0|trap}")
13728 (define_expand "conditional_trap"
13729 [(trap_if (match_operator 0 "trap_comparison_operator"
13730 [(match_dup 2) (match_dup 3)])
13731 (match_operand 1 "const_int_operand" ""))]
13732 ""
13733 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13734 operands[2] = rs6000_compare_op0;
13735 operands[3] = rs6000_compare_op1;")
13737 (define_insn ""
13738 [(trap_if (match_operator 0 "trap_comparison_operator"
13739 [(match_operand:GPR 1 "register_operand" "r")
13740 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13741 (const_int 0))]
13742 ""
13743 "{t|t<wd>}%V0%I2 %1,%2")
13744 \f
13745 ;; Insns related to generating the function prologue and epilogue.
13747 (define_expand "prologue"
13748 [(use (const_int 0))]
13749 "TARGET_SCHED_PROLOG"
13750 "
13751 {
13752 rs6000_emit_prologue ();
13753 DONE;
13754 }")
13756 (define_insn "*movesi_from_cr_one"
13757 [(match_parallel 0 "mfcr_operation"
13758 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13759 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13760 (match_operand 3 "immediate_operand" "n")]
13761 UNSPEC_MOVESI_FROM_CR))])]
13762 "TARGET_MFCRF"
13763 "*
13764 {
13765 int mask = 0;
13766 int i;
13767 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13768 {
13769 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13770 operands[4] = GEN_INT (mask);
13771 output_asm_insn (\"mfcr %1,%4\", operands);
13772 }
13773 return \"\";
13774 }"
13775 [(set_attr "type" "mfcrf")])
13777 (define_insn "movesi_from_cr"
13778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13779 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13780 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
13781 UNSPEC_MOVESI_FROM_CR))]
13782 ""
13783 "mfcr %0"
13784 [(set_attr "type" "mfcr")])
13786 (define_insn "*stmw"
13787 [(match_parallel 0 "stmw_operation"
13788 [(set (match_operand:SI 1 "memory_operand" "=m")
13789 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13790 "TARGET_MULTIPLE"
13791 "{stm|stmw} %2,%1")
13793 (define_insn "*save_fpregs_<mode>"
13794 [(match_parallel 0 "any_parallel_operand"
13795 [(clobber (match_operand:P 1 "register_operand" "=l"))
13796 (use (match_operand:P 2 "call_operand" "s"))
13797 (set (match_operand:DF 3 "memory_operand" "=m")
13798 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13799 ""
13800 "bl %z2"
13801 [(set_attr "type" "branch")
13802 (set_attr "length" "4")])
13804 ; These are to explain that changes to the stack pointer should
13805 ; not be moved over stores to stack memory.
13806 (define_insn "stack_tie"
13807 [(set (match_operand:BLK 0 "memory_operand" "+m")
13808 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
13809 ""
13810 ""
13811 [(set_attr "length" "0")])
13814 (define_expand "epilogue"
13815 [(use (const_int 0))]
13816 "TARGET_SCHED_PROLOG"
13817 "
13818 {
13819 rs6000_emit_epilogue (FALSE);
13820 DONE;
13821 }")
13823 ; On some processors, doing the mtcrf one CC register at a time is
13824 ; faster (like on the 604e). On others, doing them all at once is
13825 ; faster; for instance, on the 601 and 750.
13827 (define_expand "movsi_to_cr_one"
13828 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13829 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13830 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13831 ""
13832 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13834 (define_insn "*movsi_to_cr"
13835 [(match_parallel 0 "mtcrf_operation"
13836 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13837 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13838 (match_operand 3 "immediate_operand" "n")]
13839 UNSPEC_MOVESI_TO_CR))])]
13840 ""
13841 "*
13842 {
13843 int mask = 0;
13844 int i;
13845 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13846 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13847 operands[4] = GEN_INT (mask);
13848 return \"mtcrf %4,%2\";
13849 }"
13850 [(set_attr "type" "mtcr")])
13852 (define_insn "*mtcrfsi"
13853 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13854 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13855 (match_operand 2 "immediate_operand" "n")]
13856 UNSPEC_MOVESI_TO_CR))]
13857 "GET_CODE (operands[0]) == REG
13858 && CR_REGNO_P (REGNO (operands[0]))
13859 && GET_CODE (operands[2]) == CONST_INT
13860 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13861 "mtcrf %R0,%1"
13862 [(set_attr "type" "mtcr")])
13864 ; The load-multiple instructions have similar properties.
13865 ; Note that "load_multiple" is a name known to the machine-independent
13866 ; code that actually corresponds to the powerpc load-string.
13868 (define_insn "*lmw"
13869 [(match_parallel 0 "lmw_operation"
13870 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13871 (match_operand:SI 2 "memory_operand" "m"))])]
13872 "TARGET_MULTIPLE"
13873 "{lm|lmw} %1,%2")
13875 (define_insn "*return_internal_<mode>"
13876 [(return)
13877 (use (match_operand:P 0 "register_operand" "lc"))]
13878 ""
13879 "b%T0"
13880 [(set_attr "type" "jmpreg")])
13882 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13883 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13885 (define_insn "*return_and_restore_fpregs_<mode>"
13886 [(match_parallel 0 "any_parallel_operand"
13887 [(return)
13888 (use (match_operand:P 1 "register_operand" "l"))
13889 (use (match_operand:P 2 "call_operand" "s"))
13890 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13891 (match_operand:DF 4 "memory_operand" "m"))])]
13892 ""
13893 "b %z2")
13895 ; This is used in compiling the unwind routines.
13896 (define_expand "eh_return"
13897 [(use (match_operand 0 "general_operand" ""))]
13898 ""
13899 "
13900 {
13901 if (TARGET_32BIT)
13902 emit_insn (gen_eh_set_lr_si (operands[0]));
13903 else
13904 emit_insn (gen_eh_set_lr_di (operands[0]));
13905 DONE;
13906 }")
13908 ; We can't expand this before we know where the link register is stored.
13909 (define_insn "eh_set_lr_<mode>"
13910 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13911 UNSPECV_EH_RR)
13912 (clobber (match_scratch:P 1 "=&b"))]
13913 ""
13914 "#")
13916 (define_split
13917 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13918 (clobber (match_scratch 1 ""))]
13919 "reload_completed"
13920 [(const_int 0)]
13921 "
13922 {
13923 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13924 DONE;
13925 }")
13927 (define_insn "prefetch"
13928 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
13929 (match_operand:SI 1 "const_int_operand" "n")
13930 (match_operand:SI 2 "const_int_operand" "n"))]
13931 "TARGET_POWERPC"
13932 "*
13933 {
13934 if (GET_CODE (operands[0]) == REG)
13935 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13936 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13937 }"
13938 [(set_attr "type" "load")])
13939 \f
13941 (include "sync.md")
13942 (include "altivec.md")
13943 (include "spe.md")