?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Update FSF address.
[official-gcc.git] / gcc / config / mips / mips.h
blob5e594c7e7c11511aa17f996cc189786812ad0255
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
25
26
27 /* MIPS external variables defined in mips.c. */
28
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
33
34 enum processor_type {
35 PROCESSOR_R3000,
36 PROCESSOR_4KC,
37 PROCESSOR_4KP,
38 PROCESSOR_5KC,
39 PROCESSOR_20KC,
40 PROCESSOR_24K,
41 PROCESSOR_24KX,
42 PROCESSOR_M4K,
43 PROCESSOR_R3900,
44 PROCESSOR_R6000,
45 PROCESSOR_R4000,
46 PROCESSOR_R4100,
47 PROCESSOR_R4111,
48 PROCESSOR_R4120,
49 PROCESSOR_R4130,
50 PROCESSOR_R4300,
51 PROCESSOR_R4600,
52 PROCESSOR_R4650,
53 PROCESSOR_R5000,
54 PROCESSOR_R5400,
55 PROCESSOR_R5500,
56 PROCESSOR_R7000,
57 PROCESSOR_R8000,
58 PROCESSOR_R9000,
59 PROCESSOR_SB1,
60 PROCESSOR_SR71000,
61 PROCESSOR_MAX
62 };
63
64 /* Costs of various operations on the different architectures. */
65
66 struct mips_rtx_cost_data
67 {
68 unsigned short fp_add;
69 unsigned short fp_mult_sf;
70 unsigned short fp_mult_df;
71 unsigned short fp_div_sf;
72 unsigned short fp_div_df;
73 unsigned short int_mult_si;
74 unsigned short int_mult_di;
75 unsigned short int_div_si;
76 unsigned short int_div_di;
77 unsigned short branch_cost;
78 unsigned short memory_latency;
79 };
80
81 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
82 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
83 to work on a 64 bit machine. */
84
85 #define ABI_32 0
86 #define ABI_N32 1
87 #define ABI_64 2
88 #define ABI_EABI 3
89 #define ABI_O64 4
90
91 /* Information about one recognized processor. Defined here for the
92 benefit of TARGET_CPU_CPP_BUILTINS. */
93 struct mips_cpu_info {
94 /* The 'canonical' name of the processor as far as GCC is concerned.
95 It's typically a manufacturer's prefix followed by a numerical
96 designation. It should be lower case. */
97 const char *name;
98
99 /* The internal processor number that most closely matches this
100 entry. Several processors can have the same value, if there's no
101 difference between them from GCC's point of view. */
102 enum processor_type cpu;
103
104 /* The ISA level that the processor implements. */
105 int isa;
106 };
107
108 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
109 extern const char *current_function_file; /* filename current function is in */
110 extern int num_source_filenames; /* current .file # */
111 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
112 extern int sym_lineno; /* sgi next label # for each stmt */
113 extern int set_noreorder; /* # of nested .set noreorder's */
114 extern int set_nomacro; /* # of nested .set nomacro's */
115 extern int set_noat; /* # of nested .set noat's */
116 extern int set_volatile; /* # of nested .set volatile's */
117 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
118 extern int mips_dbx_regno[]; /* Map register # to debug register # */
119 extern GTY(()) rtx cmp_operands[2];
120 extern enum processor_type mips_arch; /* which cpu to codegen for */
121 extern enum processor_type mips_tune; /* which cpu to schedule for */
122 extern int mips_isa; /* architectural level */
123 extern int mips_abi; /* which ABI to use */
124 extern int mips16_hard_float; /* mips16 without -msoft-float */
125 extern const struct mips_cpu_info mips_cpu_info_table[];
126 extern const struct mips_cpu_info *mips_arch_info;
127 extern const struct mips_cpu_info *mips_tune_info;
128 extern const struct mips_rtx_cost_data *mips_cost;
129
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
132
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
136
137 \f
138 /* Run-time compilation parameters selecting different hardware subsets. */
139
140 /* True if the call patterns should be split into a jalr followed by
141 an instruction to restore $gp. This is only ever true for SVR4 PIC,
142 in which $gp is call-clobbered. It is only safe to split the load
143 from the call when every use of $gp is explicit. */
144
145 #define TARGET_SPLIT_CALLS \
146 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
147
148 /* True if we can optimize sibling calls. For simplicity, we only
149 handle cases in which call_insn_operand will reject invalid
150 sibcall addresses. There are two cases in which this isn't true:
151
152 - TARGET_MIPS16. call_insn_operand accepts constant addresses
153 but there is no direct jump instruction. It isn't worth
154 using sibling calls in this case anyway; they would usually
155 be longer than normal calls.
156
157 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
158 accepts global constants, but "jr $25" is the only allowed
159 sibcall. */
160
161 #define TARGET_SIBCALLS \
162 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
163
164 /* True if .gpword or .gpdword should be used for switch tables.
165
166 Although GAS does understand .gpdword, the SGI linker mishandles
167 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
168 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
169 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
170
171 /* Generate mips16 code */
172 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
173 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
174 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
175
176 /* Generic ISA defines. */
177 #define ISA_MIPS1 (mips_isa == 1)
178 #define ISA_MIPS2 (mips_isa == 2)
179 #define ISA_MIPS3 (mips_isa == 3)
180 #define ISA_MIPS4 (mips_isa == 4)
181 #define ISA_MIPS32 (mips_isa == 32)
182 #define ISA_MIPS32R2 (mips_isa == 33)
183 #define ISA_MIPS64 (mips_isa == 64)
184
185 /* Architecture target defines. */
186 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
187 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
188 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
189 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
190 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
191 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
192 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
193 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
194 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
195 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
196
197 /* Scheduling target defines. */
198 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
199 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
200 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
201 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
202 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
203 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
204 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
205 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
206 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
207 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
208 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
209 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
210
211 /* True if the pre-reload scheduler should try to create chains of
212 multiply-add or multiply-subtract instructions. For example,
213 suppose we have:
214
215 t1 = a * b
216 t2 = t1 + c * d
217 t3 = e * f
218 t4 = t3 - g * h
219
220 t1 will have a higher priority than t2 and t3 will have a higher
221 priority than t4. However, before reload, there is no dependence
222 between t1 and t3, and they can often have similar priorities.
223 The scheduler will then tend to prefer:
224
225 t1 = a * b
226 t3 = e * f
227 t2 = t1 + c * d
228 t4 = t3 - g * h
229
230 which stops us from making full use of macc/madd-style instructions.
231 This sort of situation occurs frequently in Fourier transforms and
232 in unrolled loops.
233
234 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
235 queue so that chained multiply-add and multiply-subtract instructions
236 appear ahead of any other instruction that is likely to clobber lo.
237 In the example above, if t2 and t3 become ready at the same time,
238 the code ensures that t2 is scheduled first.
239
240 Multiply-accumulate instructions are a bigger win for some targets
241 than others, so this macro is defined on an opt-in basis. */
242 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
243 || TUNE_MIPS4120 \
244 || TUNE_MIPS4130)
245
246 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
247 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
248
249 /* IRIX specific stuff. */
250 #define TARGET_IRIX 0
251 #define TARGET_IRIX6 0
252
253 /* Define preprocessor macros for the -march and -mtune options.
254 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
255 processor. If INFO's canonical name is "foo", define PREFIX to
256 be "foo", and define an additional macro PREFIX_FOO. */
257 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
258 do \
259 { \
260 char *macro, *p; \
261 \
262 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
263 for (p = macro; *p != 0; p++) \
264 *p = TOUPPER (*p); \
265 \
266 builtin_define (macro); \
267 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
268 free (macro); \
269 } \
270 while (0)
271
272 /* Target CPU builtins. */
273 #define TARGET_CPU_CPP_BUILTINS() \
274 do \
275 { \
276 /* Everyone but IRIX defines this to mips. */ \
277 if (!TARGET_IRIX) \
278 builtin_assert ("machine=mips"); \
279 \
280 builtin_assert ("cpu=mips"); \
281 builtin_define ("__mips__"); \
282 builtin_define ("_mips"); \
283 \
284 /* We do this here because __mips is defined below \
285 and so we can't use builtin_define_std. */ \
286 if (!flag_iso) \
287 builtin_define ("mips"); \
288 \
289 if (TARGET_64BIT) \
290 builtin_define ("__mips64"); \
291 \
292 if (!TARGET_IRIX) \
293 { \
294 /* Treat _R3000 and _R4000 like register-size \
295 defines, which is how they've historically \
296 been used. */ \
297 if (TARGET_64BIT) \
298 { \
299 builtin_define_std ("R4000"); \
300 builtin_define ("_R4000"); \
301 } \
302 else \
303 { \
304 builtin_define_std ("R3000"); \
305 builtin_define ("_R3000"); \
306 } \
307 } \
308 if (TARGET_FLOAT64) \
309 builtin_define ("__mips_fpr=64"); \
310 else \
311 builtin_define ("__mips_fpr=32"); \
312 \
313 if (TARGET_MIPS16) \
314 builtin_define ("__mips16"); \
315 \
316 if (TARGET_MIPS3D) \
317 builtin_define ("__mips3d"); \
318 \
319 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
320 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
321 \
322 if (ISA_MIPS1) \
323 { \
324 builtin_define ("__mips=1"); \
325 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
326 } \
327 else if (ISA_MIPS2) \
328 { \
329 builtin_define ("__mips=2"); \
330 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
331 } \
332 else if (ISA_MIPS3) \
333 { \
334 builtin_define ("__mips=3"); \
335 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
336 } \
337 else if (ISA_MIPS4) \
338 { \
339 builtin_define ("__mips=4"); \
340 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
341 } \
342 else if (ISA_MIPS32) \
343 { \
344 builtin_define ("__mips=32"); \
345 builtin_define ("__mips_isa_rev=1"); \
346 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
347 } \
348 else if (ISA_MIPS32R2) \
349 { \
350 builtin_define ("__mips=32"); \
351 builtin_define ("__mips_isa_rev=2"); \
352 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
353 } \
354 else if (ISA_MIPS64) \
355 { \
356 builtin_define ("__mips=64"); \
357 builtin_define ("__mips_isa_rev=1"); \
358 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
359 } \
360 \
361 if (TARGET_HARD_FLOAT) \
362 builtin_define ("__mips_hard_float"); \
363 else if (TARGET_SOFT_FLOAT) \
364 builtin_define ("__mips_soft_float"); \
365 \
366 if (TARGET_SINGLE_FLOAT) \
367 builtin_define ("__mips_single_float"); \
368 \
369 if (TARGET_PAIRED_SINGLE_FLOAT) \
370 builtin_define ("__mips_paired_single_float"); \
371 \
372 if (TARGET_BIG_ENDIAN) \
373 { \
374 builtin_define_std ("MIPSEB"); \
375 builtin_define ("_MIPSEB"); \
376 } \
377 else \
378 { \
379 builtin_define_std ("MIPSEL"); \
380 builtin_define ("_MIPSEL"); \
381 } \
382 \
383 /* Macros dependent on the C dialect. */ \
384 if (preprocessing_asm_p ()) \
385 { \
386 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
387 builtin_define ("_LANGUAGE_ASSEMBLY"); \
388 } \
389 else if (c_dialect_cxx ()) \
390 { \
391 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
392 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
393 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
394 } \
395 else \
396 { \
397 builtin_define_std ("LANGUAGE_C"); \
398 builtin_define ("_LANGUAGE_C"); \
399 } \
400 if (c_dialect_objc ()) \
401 { \
402 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
403 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
404 /* Bizarre, but needed at least for Irix. */ \
405 builtin_define_std ("LANGUAGE_C"); \
406 builtin_define ("_LANGUAGE_C"); \
407 } \
408 \
409 if (mips_abi == ABI_EABI) \
410 builtin_define ("__mips_eabi"); \
411 \
412 } while (0)
413
414 /* Default target_flags if no switches are specified */
415
416 #ifndef TARGET_DEFAULT
417 #define TARGET_DEFAULT 0
418 #endif
419
420 #ifndef TARGET_CPU_DEFAULT
421 #define TARGET_CPU_DEFAULT 0
422 #endif
423
424 #ifndef TARGET_ENDIAN_DEFAULT
425 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
426 #endif
427
428 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
429 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
430 #endif
431
432 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
433 #ifndef MIPS_ISA_DEFAULT
434 #ifndef MIPS_CPU_STRING_DEFAULT
435 #define MIPS_CPU_STRING_DEFAULT "from-abi"
436 #endif
437 #endif
438
439 #ifdef IN_LIBGCC2
440 #undef TARGET_64BIT
441 /* Make this compile time constant for libgcc2 */
442 #ifdef __mips64
443 #define TARGET_64BIT 1
444 #else
445 #define TARGET_64BIT 0
446 #endif
447 #endif /* IN_LIBGCC2 */
448
449 #ifndef MULTILIB_ENDIAN_DEFAULT
450 #if TARGET_ENDIAN_DEFAULT == 0
451 #define MULTILIB_ENDIAN_DEFAULT "EL"
452 #else
453 #define MULTILIB_ENDIAN_DEFAULT "EB"
454 #endif
455 #endif
456
457 #ifndef MULTILIB_ISA_DEFAULT
458 # if MIPS_ISA_DEFAULT == 1
459 # define MULTILIB_ISA_DEFAULT "mips1"
460 # else
461 # if MIPS_ISA_DEFAULT == 2
462 # define MULTILIB_ISA_DEFAULT "mips2"
463 # else
464 # if MIPS_ISA_DEFAULT == 3
465 # define MULTILIB_ISA_DEFAULT "mips3"
466 # else
467 # if MIPS_ISA_DEFAULT == 4
468 # define MULTILIB_ISA_DEFAULT "mips4"
469 # else
470 # if MIPS_ISA_DEFAULT == 32
471 # define MULTILIB_ISA_DEFAULT "mips32"
472 # else
473 # if MIPS_ISA_DEFAULT == 33
474 # define MULTILIB_ISA_DEFAULT "mips32r2"
475 # else
476 # if MIPS_ISA_DEFAULT == 64
477 # define MULTILIB_ISA_DEFAULT "mips64"
478 # else
479 # define MULTILIB_ISA_DEFAULT "mips1"
480 # endif
481 # endif
482 # endif
483 # endif
484 # endif
485 # endif
486 # endif
487 #endif
488
489 #ifndef MULTILIB_DEFAULTS
490 #define MULTILIB_DEFAULTS \
491 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
492 #endif
493
494 /* We must pass -EL to the linker by default for little endian embedded
495 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
496 linker will default to using big-endian output files. The OUTPUT_FORMAT
497 line must be in the linker script, otherwise -EB/-EL will not work. */
498
499 #ifndef ENDIAN_SPEC
500 #if TARGET_ENDIAN_DEFAULT == 0
501 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
502 #else
503 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
504 #endif
505 #endif
506
507 /* Support for a compile-time default CPU, et cetera. The rules are:
508 --with-arch is ignored if -march is specified or a -mips is specified
509 (other than -mips16).
510 --with-tune is ignored if -mtune is specified.
511 --with-abi is ignored if -mabi is specified.
512 --with-float is ignored if -mhard-float or -msoft-float are
513 specified.
514 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
515 specified. */
516 #define OPTION_DEFAULT_SPECS \
517 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
518 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
519 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
520 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
521 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
522
523
524 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
525 && ISA_HAS_COND_TRAP)
526
527 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
528 && !TARGET_SR71K \
529 && !TARGET_MIPS16)
530
531 /* Generate three-operand multiply instructions for SImode. */
532 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
533 || TARGET_MIPS5400 \
534 || TARGET_MIPS5500 \
535 || TARGET_MIPS7000 \
536 || TARGET_MIPS9000 \
537 || TARGET_MAD \
538 || ISA_MIPS32 \
539 || ISA_MIPS32R2 \
540 || ISA_MIPS64) \
541 && !TARGET_MIPS16)
542
543 /* Generate three-operand multiply instructions for DImode. */
544 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
545 && !TARGET_MIPS16)
546
547 /* True if the ABI can only work with 64-bit integer registers. We
548 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
549 otherwise floating-point registers must also be 64-bit. */
550 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
551
552 /* Likewise for 32-bit regs. */
553 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
554
555 /* True if symbols are 64 bits wide. At present, n64 is the only
556 ABI for which this is true. */
557 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
558
559 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
560 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
561 || ISA_MIPS4 \
562 || ISA_MIPS64)
563
564 /* ISA has branch likely instructions (e.g. mips2). */
565 /* Disable branchlikely for tx39 until compare rewrite. They haven't
566 been generated up to this point. */
567 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
568
569 /* ISA has the conditional move instructions introduced in mips4. */
570 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
571 || ISA_MIPS32 \
572 || ISA_MIPS32R2 \
573 || ISA_MIPS64) \
574 && !TARGET_MIPS5500 \
575 && !TARGET_MIPS16)
576
577 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
578 branch on CC, and move (both FP and non-FP) on CC. */
579 #define ISA_HAS_8CC (ISA_MIPS4 \
580 || ISA_MIPS32 \
581 || ISA_MIPS32R2 \
582 || ISA_MIPS64)
583
584 /* This is a catch all for other mips4 instructions: indexed load, the
585 FP madd and msub instructions, and the FP recip and recip sqrt
586 instructions. */
587 #define ISA_HAS_FP4 ((ISA_MIPS4 \
588 || ISA_MIPS64) \
589 && !TARGET_MIPS16)
590
591 /* ISA has conditional trap instructions. */
592 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
593 && !TARGET_MIPS16)
594
595 /* ISA has integer multiply-accumulate instructions, madd and msub. */
596 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
597 || ISA_MIPS32R2 \
598 || ISA_MIPS64 \
599 ) && !TARGET_MIPS16)
600
601 /* ISA has floating-point nmadd and nmsub instructions. */
602 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
603 || ISA_MIPS64) \
604 && (!TARGET_MIPS5400 || TARGET_MAD) \
605 && ! TARGET_MIPS16)
606
607 /* ISA has count leading zeroes/ones instruction (not implemented). */
608 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
609 || ISA_MIPS32R2 \
610 || ISA_MIPS64 \
611 ) && !TARGET_MIPS16)
612
613 /* ISA has double-word count leading zeroes/ones instruction (not
614 implemented). */
615 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
616 && !TARGET_MIPS16)
617
618 /* ISA has three operand multiply instructions that put
619 the high part in an accumulator: mulhi or mulhiu. */
620 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
621 || TARGET_MIPS5500 \
622 || TARGET_SR71K \
623 )
624
625 /* ISA has three operand multiply instructions that
626 negates the result and puts the result in an accumulator. */
627 #define ISA_HAS_MULS (TARGET_MIPS5400 \
628 || TARGET_MIPS5500 \
629 || TARGET_SR71K \
630 )
631
632 /* ISA has three operand multiply instructions that subtracts the
633 result from a 4th operand and puts the result in an accumulator. */
634 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
635 || TARGET_MIPS5500 \
636 || TARGET_SR71K \
637 )
638 /* ISA has three operand multiply instructions that the result
639 from a 4th operand and puts the result in an accumulator. */
640 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
641 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
642 || TARGET_MIPS5400 \
643 || TARGET_MIPS5500 \
644 || TARGET_SR71K \
645 )
646
647 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
648 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \
649 && (TARGET_MIPS4120 \
650 || TARGET_MIPS4130))
651
652 /* ISA has 32-bit rotate right instruction. */
653 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
654 && (ISA_MIPS32R2 \
655 || TARGET_MIPS5400 \
656 || TARGET_MIPS5500 \
657 || TARGET_SR71K \
658 ))
659
660 /* ISA has 64-bit rotate right instruction. */
661 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
662 && !TARGET_MIPS16 \
663 && (TARGET_MIPS5400 \
664 || TARGET_MIPS5500 \
665 || TARGET_SR71K \
666 ))
667
668 /* ISA has data prefetch instructions. This controls use of 'pref'. */
669 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
670 || ISA_MIPS32 \
671 || ISA_MIPS32R2 \
672 || ISA_MIPS64) \
673 && !TARGET_MIPS16)
674
675 /* ISA has data indexed prefetch instructions. This controls use of
676 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
677 (prefx is a cop1x instruction, so can only be used if FP is
678 enabled.) */
679 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
680 || ISA_MIPS64) \
681 && !TARGET_MIPS16)
682
683 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
684 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
685 also requires TARGET_DOUBLE_FLOAT. */
686 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
687
688 /* ISA includes the MIPS32r2 seb and seh instructions. */
689 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
690 && (ISA_MIPS32R2 \
691 ))
692
693 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
694 #define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
695 && (ISA_MIPS32R2 \
696 ))
697
698 /* True if the result of a load is not available to the next instruction.
699 A nop will then be needed between instructions like "lw $4,..."
700 and "addiu $4,$4,1". */
701 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
702 && !TARGET_MIPS3900 \
703 && !TARGET_MIPS16)
704
705 /* Likewise mtc1 and mfc1. */
706 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
707
708 /* Likewise floating-point comparisons. */
709 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
710
711 /* True if mflo and mfhi can be immediately followed by instructions
712 which write to the HI and LO registers.
713
714 According to MIPS specifications, MIPS ISAs I, II, and III need
715 (at least) two instructions between the reads of HI/LO and
716 instructions which write them, and later ISAs do not. Contradicting
717 the MIPS specifications, some MIPS IV processor user manuals (e.g.
718 the UM for the NEC Vr5000) document needing the instructions between
719 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
720 MIPS64 and later ISAs to have the interlocks, plus any specific
721 earlier-ISA CPUs for which CPU documentation declares that the
722 instructions are really interlocked. */
723 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
724 || ISA_MIPS32R2 \
725 || ISA_MIPS64 \
726 || TARGET_MIPS5500)
727 \f
728 /* Add -G xx support. */
729
730 #undef SWITCH_TAKES_ARG
731 #define SWITCH_TAKES_ARG(CHAR) \
732 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
733
734 #define OVERRIDE_OPTIONS override_options ()
735
736 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
737
738 /* Show we can debug even without a frame pointer. */
739 #define CAN_DEBUG_WITHOUT_FP
740 \f
741 /* Tell collect what flags to pass to nm. */
742 #ifndef NM_FLAGS
743 #define NM_FLAGS "-Bn"
744 #endif
745
746 \f
747 #ifndef MIPS_ABI_DEFAULT
748 #define MIPS_ABI_DEFAULT ABI_32
749 #endif
750
751 /* Use the most portable ABI flag for the ASM specs. */
752
753 #if MIPS_ABI_DEFAULT == ABI_32
754 #define MULTILIB_ABI_DEFAULT "mabi=32"
755 #endif
756
757 #if MIPS_ABI_DEFAULT == ABI_O64
758 #define MULTILIB_ABI_DEFAULT "mabi=o64"
759 #endif
760
761 #if MIPS_ABI_DEFAULT == ABI_N32
762 #define MULTILIB_ABI_DEFAULT "mabi=n32"
763 #endif
764
765 #if MIPS_ABI_DEFAULT == ABI_64
766 #define MULTILIB_ABI_DEFAULT "mabi=64"
767 #endif
768
769 #if MIPS_ABI_DEFAULT == ABI_EABI
770 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
771 #endif
772
773 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
774 to the assembler. It may be overridden by subtargets. */
775 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
776 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
777 %{noasmopt:-O0} \
778 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
779 #endif
780
781 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
782 the assembler. It may be overridden by subtargets.
783
784 Beginning with gas 2.13, -mdebug must be passed to correctly handle
785 COFF debugging info. */
786
787 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
788 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
789 %{g} %{g0} %{g1} %{g2} %{g3} \
790 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
791 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
792 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
793 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
794 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
795 #endif
796
797 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
798 overridden by subtargets. */
799
800 #ifndef SUBTARGET_ASM_SPEC
801 #define SUBTARGET_ASM_SPEC ""
802 #endif
803
804 #undef ASM_SPEC
805 #define ASM_SPEC "\
806 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
807 %{mips32} %{mips32r2} %{mips64} \
808 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
809 %{mips3d:-mips3d} \
810 %{mfix-vr4120} %{mfix-vr4130} \
811 %(subtarget_asm_optimizing_spec) \
812 %(subtarget_asm_debugging_spec) \
813 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
814 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
815 %{msym32} %{mno-sym32} \
816 %{mtune=*} %{v} \
817 %(subtarget_asm_spec)"
818
819 /* Extra switches sometimes passed to the linker. */
820 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
821 will interpret it as a -b option. */
822
823 #ifndef LINK_SPEC
824 #define LINK_SPEC "\
825 %(endian_spec) \
826 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
827 %{bestGnum} %{shared} %{non_shared}"
828 #endif /* LINK_SPEC defined */
829
830
831 /* Specs for the compiler proper */
832
833 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
834 overridden by subtargets. */
835 #ifndef SUBTARGET_CC1_SPEC
836 #define SUBTARGET_CC1_SPEC ""
837 #endif
838
839 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
840
841 #ifndef CC1_SPEC
842 #define CC1_SPEC "\
843 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
844 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
845 %{save-temps: } \
846 %(subtarget_cc1_spec)"
847 #endif
848
849 /* Preprocessor specs. */
850
851 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
852 overridden by subtargets. */
853 #ifndef SUBTARGET_CPP_SPEC
854 #define SUBTARGET_CPP_SPEC ""
855 #endif
856
857 #define CPP_SPEC "%(subtarget_cpp_spec)"
858
859 /* This macro defines names of additional specifications to put in the specs
860 that can be used in various specifications like CC1_SPEC. Its definition
861 is an initializer with a subgrouping for each command option.
862
863 Each subgrouping contains a string constant, that defines the
864 specification name, and a string constant that used by the GCC driver
865 program.
866
867 Do not define this macro if it does not need to do anything. */
868
869 #define EXTRA_SPECS \
870 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
871 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
872 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
873 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
874 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
875 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
876 { "endian_spec", ENDIAN_SPEC }, \
877 SUBTARGET_EXTRA_SPECS
878
879 #ifndef SUBTARGET_EXTRA_SPECS
880 #define SUBTARGET_EXTRA_SPECS
881 #endif
882 \f
883 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
884 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
885 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
886
887 #ifndef PREFERRED_DEBUGGING_TYPE
888 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
889 #endif
890
891 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
892
893 /* By default, turn on GDB extensions. */
894 #define DEFAULT_GDB_EXTENSIONS 1
895
896 /* Local compiler-generated symbols must have a prefix that the assembler
897 understands. By default, this is $, although some targets (e.g.,
898 NetBSD-ELF) need to override this. */
899
900 #ifndef LOCAL_LABEL_PREFIX
901 #define LOCAL_LABEL_PREFIX "$"
902 #endif
903
904 /* By default on the mips, external symbols do not have an underscore
905 prepended, but some targets (e.g., NetBSD) require this. */
906
907 #ifndef USER_LABEL_PREFIX
908 #define USER_LABEL_PREFIX ""
909 #endif
910
911 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
912 since the length can run past this up to a continuation point. */
913 #undef DBX_CONTIN_LENGTH
914 #define DBX_CONTIN_LENGTH 1500
915
916 /* How to renumber registers for dbx and gdb. */
917 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
918
919 /* The mapping from gcc register number to DWARF 2 CFA column number. */
920 #define DWARF_FRAME_REGNUM(REG) (REG)
921
922 /* The DWARF 2 CFA column which tracks the return address. */
923 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
924
925 /* The DWARF 2 CFA column which tracks the return address from a
926 signal handler context. */
927 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
928
929 /* Before the prologue, RA lives in r31. */
930 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
931
932 /* Describe how we implement __builtin_eh_return. */
933 #define EH_RETURN_DATA_REGNO(N) \
934 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
935
936 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
937
938 /* Offsets recorded in opcodes are a multiple of this alignment factor.
939 The default for this in 64-bit mode is 8, which causes problems with
940 SFmode register saves. */
941 #define DWARF_CIE_DATA_ALIGNMENT -4
942
943 /* Correct the offset of automatic variables and arguments. Note that
944 the MIPS debug format wants all automatic variables and arguments
945 to be in terms of the virtual frame pointer (stack pointer before
946 any adjustment in the function), while the MIPS 3.0 linker wants
947 the frame pointer to be the stack pointer after the initial
948 adjustment. */
949
950 #define DEBUGGER_AUTO_OFFSET(X) \
951 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
952 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
953 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
954 \f
955 /* Target machine storage layout */
956
957 #define BITS_BIG_ENDIAN 0
958 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
959 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
960
961 /* Define this to set the endianness to use in libgcc2.c, which can
962 not depend on target_flags. */
963 #if !defined(MIPSEL) && !defined(__MIPSEL__)
964 #define LIBGCC2_WORDS_BIG_ENDIAN 1
965 #else
966 #define LIBGCC2_WORDS_BIG_ENDIAN 0
967 #endif
968
969 #define MAX_BITS_PER_WORD 64
970
971 /* Width of a word, in units (bytes). */
972 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
973 #define MIN_UNITS_PER_WORD 4
974
975 /* For MIPS, width of a floating point register. */
976 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
977
978 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
979 the next available register. */
980 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
981
982 /* The largest size of value that can be held in floating-point
983 registers and moved with a single instruction. */
984 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
985
986 /* The largest size of value that can be held in floating-point
987 registers. */
988 #define UNITS_PER_FPVALUE \
989 (TARGET_SOFT_FLOAT ? 0 \
990 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
991 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
992
993 /* The number of bytes in a double. */
994 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
995
996 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
997
998 /* Set the sizes of the core types. */
999 #define SHORT_TYPE_SIZE 16
1000 #define INT_TYPE_SIZE 32
1001 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1002 #define LONG_LONG_TYPE_SIZE 64
1003
1004 #define FLOAT_TYPE_SIZE 32
1005 #define DOUBLE_TYPE_SIZE 64
1006 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1007
1008 /* long double is not a fixed mode, but the idea is that, if we
1009 support long double, we also want a 128-bit integer type. */
1010 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1011
1012 #ifdef IN_LIBGCC2
1013 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1014 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1015 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1016 # else
1017 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1018 # endif
1019 #endif
1020
1021 /* Width in bits of a pointer. */
1022 #ifndef POINTER_SIZE
1023 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1024 #endif
1025
1026 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1027 #define PARM_BOUNDARY BITS_PER_WORD
1028
1029 /* Allocation boundary (in *bits*) for the code of a function. */
1030 #define FUNCTION_BOUNDARY 32
1031
1032 /* Alignment of field after `int : 0' in a structure. */
1033 #define EMPTY_FIELD_BOUNDARY 32
1034
1035 /* Every structure's size must be a multiple of this. */
1036 /* 8 is observed right on a DECstation and on riscos 4.02. */
1037 #define STRUCTURE_SIZE_BOUNDARY 8
1038
1039 /* There is no point aligning anything to a rounder boundary than this. */
1040 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1041
1042 /* All accesses must be aligned. */
1043 #define STRICT_ALIGNMENT 1
1044
1045 /* Define this if you wish to imitate the way many other C compilers
1046 handle alignment of bitfields and the structures that contain
1047 them.
1048
1049 The behavior is that the type written for a bit-field (`int',
1050 `short', or other integer type) imposes an alignment for the
1051 entire structure, as if the structure really did contain an
1052 ordinary field of that type. In addition, the bit-field is placed
1053 within the structure so that it would fit within such a field,
1054 not crossing a boundary for it.
1055
1056 Thus, on most machines, a bit-field whose type is written as `int'
1057 would not cross a four-byte boundary, and would force four-byte
1058 alignment for the whole structure. (The alignment used may not
1059 be four bytes; it is controlled by the other alignment
1060 parameters.)
1061
1062 If the macro is defined, its definition should be a C expression;
1063 a nonzero value for the expression enables this behavior. */
1064
1065 #define PCC_BITFIELD_TYPE_MATTERS 1
1066
1067 /* If defined, a C expression to compute the alignment given to a
1068 constant that is being placed in memory. CONSTANT is the constant
1069 and ALIGN is the alignment that the object would ordinarily have.
1070 The value of this macro is used instead of that alignment to align
1071 the object.
1072
1073 If this macro is not defined, then ALIGN is used.
1074
1075 The typical use of this macro is to increase alignment for string
1076 constants to be word aligned so that `strcpy' calls that copy
1077 constants can be done inline. */
1078
1079 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1080 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1081 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1082
1083 /* If defined, a C expression to compute the alignment for a static
1084 variable. TYPE is the data type, and ALIGN is the alignment that
1085 the object would ordinarily have. The value of this macro is used
1086 instead of that alignment to align the object.
1087
1088 If this macro is not defined, then ALIGN is used.
1089
1090 One use of this macro is to increase alignment of medium-size
1091 data to make it all fit in fewer cache lines. Another is to
1092 cause character arrays to be word-aligned so that `strcpy' calls
1093 that copy constants to character arrays can be done inline. */
1094
1095 #undef DATA_ALIGNMENT
1096 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1097 ((((ALIGN) < BITS_PER_WORD) \
1098 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1099 || TREE_CODE (TYPE) == UNION_TYPE \
1100 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1101
1102
1103 #define PAD_VARARGS_DOWN \
1104 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1105
1106 /* Define if operations between registers always perform the operation
1107 on the full register even if a narrower mode is specified. */
1108 #define WORD_REGISTER_OPERATIONS
1109
1110 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1111 moves. All other references are zero extended. */
1112 #define LOAD_EXTEND_OP(MODE) \
1113 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1114 ? SIGN_EXTEND : ZERO_EXTEND)
1115
1116 /* Define this macro if it is advisable to hold scalars in registers
1117 in a wider mode than that declared by the program. In such cases,
1118 the value is constrained to be within the bounds of the declared
1119 type, but kept valid in the wider mode. The signedness of the
1120 extension may differ from that of the type. */
1121
1122 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1123 if (GET_MODE_CLASS (MODE) == MODE_INT \
1124 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1125 { \
1126 if ((MODE) == SImode) \
1127 (UNSIGNEDP) = 0; \
1128 (MODE) = Pmode; \
1129 }
1130
1131 /* Define if loading short immediate values into registers sign extends. */
1132 #define SHORT_IMMEDIATES_SIGN_EXTEND
1133 \f
1134 /* Standard register usage. */
1135
1136 /* Number of hardware registers. We have:
1137
1138 - 32 integer registers
1139 - 32 floating point registers
1140 - 8 condition code registers
1141 - 2 accumulator registers (hi and lo)
1142 - 32 registers each for coprocessors 0, 2 and 3
1143 - 3 fake registers:
1144 - ARG_POINTER_REGNUM
1145 - FRAME_POINTER_REGNUM
1146 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1147 - 3 dummy entries that were used at various times in the past. */
1148
1149 #define FIRST_PSEUDO_REGISTER 176
1150
1151 /* By default, fix the kernel registers ($26 and $27), the global
1152 pointer ($28) and the stack pointer ($29). This can change
1153 depending on the command-line options.
1154
1155 Regarding coprocessor registers: without evidence to the contrary,
1156 it's best to assume that each coprocessor register has a unique
1157 use. This can be overridden, in, e.g., override_options() or
1158 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1159 for a particular target. */
1160
1161 #define FIXED_REGISTERS \
1162 { \
1163 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1164 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1165 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1166 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1167 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1168 /* COP0 registers */ \
1169 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1170 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1171 /* COP2 registers */ \
1172 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1173 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1174 /* COP3 registers */ \
1175 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1176 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1177 }
1178
1179
1180 /* Set up this array for o32 by default.
1181
1182 Note that we don't mark $31 as a call-clobbered register. The idea is
1183 that it's really the call instructions themselves which clobber $31.
1184 We don't care what the called function does with it afterwards.
1185
1186 This approach makes it easier to implement sibcalls. Unlike normal
1187 calls, sibcalls don't clobber $31, so the register reaches the
1188 called function in tact. EPILOGUE_USES says that $31 is useful
1189 to the called function. */
1190
1191 #define CALL_USED_REGISTERS \
1192 { \
1193 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1194 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1195 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1196 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1197 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1198 /* COP0 registers */ \
1199 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1200 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1201 /* COP2 registers */ \
1202 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1203 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1204 /* COP3 registers */ \
1205 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1206 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1207 }
1208
1209
1210 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1211
1212 #define CALL_REALLY_USED_REGISTERS \
1213 { /* General registers. */ \
1214 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1215 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1216 /* Floating-point registers. */ \
1217 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1218 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1219 /* Others. */ \
1220 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1221 /* COP0 registers */ \
1222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1224 /* COP2 registers */ \
1225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1227 /* COP3 registers */ \
1228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1230 }
1231
1232 /* Internal macros to classify a register number as to whether it's a
1233 general purpose register, a floating point register, a
1234 multiply/divide register, or a status register. */
1235
1236 #define GP_REG_FIRST 0
1237 #define GP_REG_LAST 31
1238 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1239 #define GP_DBX_FIRST 0
1240
1241 #define FP_REG_FIRST 32
1242 #define FP_REG_LAST 63
1243 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1244 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1245
1246 #define MD_REG_FIRST 64
1247 #define MD_REG_LAST 65
1248 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1249 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1250
1251 #define ST_REG_FIRST 67
1252 #define ST_REG_LAST 74
1253 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1254
1255
1256 /* FIXME: renumber. */
1257 #define COP0_REG_FIRST 80
1258 #define COP0_REG_LAST 111
1259 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1260
1261 #define COP2_REG_FIRST 112
1262 #define COP2_REG_LAST 143
1263 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1264
1265 #define COP3_REG_FIRST 144
1266 #define COP3_REG_LAST 175
1267 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1268 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1269 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1270
1271 #define AT_REGNUM (GP_REG_FIRST + 1)
1272 #define HI_REGNUM (MD_REG_FIRST + 0)
1273 #define LO_REGNUM (MD_REG_FIRST + 1)
1274
1275 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1276 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1277 should be used instead. */
1278 #define FPSW_REGNUM ST_REG_FIRST
1279
1280 #define GP_REG_P(REGNO) \
1281 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1282 #define M16_REG_P(REGNO) \
1283 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1284 #define FP_REG_P(REGNO) \
1285 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1286 #define MD_REG_P(REGNO) \
1287 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1288 #define ST_REG_P(REGNO) \
1289 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1290 #define COP0_REG_P(REGNO) \
1291 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1292 #define COP2_REG_P(REGNO) \
1293 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1294 #define COP3_REG_P(REGNO) \
1295 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1296 #define ALL_COP_REG_P(REGNO) \
1297 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1298
1299 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1300
1301 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1302 to initialize the mips16 gp pseudo register. */
1303 #define CONST_GP_P(X) \
1304 (GET_CODE (X) == CONST \
1305 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1306 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1307
1308 /* Return coprocessor number from register number. */
1309
1310 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1311 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1312 : COP3_REG_P (REGNO) ? '3' : '?')
1313
1314
1315 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1316
1317 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1318 array built in override_options. Because machmodes.h is not yet
1319 included before this file is processed, the MODE bound can't be
1320 expressed here. */
1321
1322 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1323
1324 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1325 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1326
1327 /* Value is 1 if it is a good idea to tie two pseudo registers
1328 when one has mode MODE1 and one has mode MODE2.
1329 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1330 for any hard reg, then this must be 0 for correct output. */
1331 #define MODES_TIEABLE_P(MODE1, MODE2) \
1332 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1333 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1334 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1335 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1336
1337 /* Register to use for pushing function arguments. */
1338 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1339
1340 /* These two registers don't really exist: they get eliminated to either
1341 the stack or hard frame pointer. */
1342 #define ARG_POINTER_REGNUM 77
1343 #define FRAME_POINTER_REGNUM 78
1344
1345 /* $30 is not available on the mips16, so we use $17 as the frame
1346 pointer. */
1347 #define HARD_FRAME_POINTER_REGNUM \
1348 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1349
1350 /* Value should be nonzero if functions must have frame pointers.
1351 Zero means the frame pointer need not be set up (and parms
1352 may be accessed via the stack pointer) in functions that seem suitable.
1353 This is computed in `reload', in reload1.c. */
1354 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1355
1356 /* Register in which static-chain is passed to a function. */
1357 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1358
1359 /* Registers used as temporaries in prologue/epilogue code. If we're
1360 generating mips16 code, these registers must come from the core set
1361 of 8. The prologue register mustn't conflict with any incoming
1362 arguments, the static chain pointer, or the frame pointer. The
1363 epilogue temporary mustn't conflict with the return registers, the
1364 frame pointer, the EH stack adjustment, or the EH data registers. */
1365
1366 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1367 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1368
1369 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1370 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1371
1372 /* Define this macro if it is as good or better to call a constant
1373 function address than to call an address kept in a register. */
1374 #define NO_FUNCTION_CSE 1
1375
1376 /* The ABI-defined global pointer. Sometimes we use a different
1377 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1378 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1379
1380 /* We normally use $28 as the global pointer. However, when generating
1381 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1382 register instead. They can then avoid saving and restoring $28
1383 and perhaps avoid using a frame at all.
1384
1385 When a leaf function uses something other than $28, mips_expand_prologue
1386 will modify pic_offset_table_rtx in place. Take the register number
1387 from there after reload. */
1388 #define PIC_OFFSET_TABLE_REGNUM \
1389 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1390
1391 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1392 \f
1393 /* Define the classes of registers for register constraints in the
1394 machine description. Also define ranges of constants.
1395
1396 One of the classes must always be named ALL_REGS and include all hard regs.
1397 If there is more than one class, another class must be named NO_REGS
1398 and contain no registers.
1399
1400 The name GENERAL_REGS must be the name of a class (or an alias for
1401 another name such as ALL_REGS). This is the class of registers
1402 that is allowed by "g" or "r" in a register constraint.
1403 Also, registers outside this class are allocated only when
1404 instructions express preferences for them.
1405
1406 The classes must be numbered in nondecreasing order; that is,
1407 a larger-numbered class must never be contained completely
1408 in a smaller-numbered class.
1409
1410 For any two classes, it is very desirable that there be another
1411 class that represents their union. */
1412
1413 enum reg_class
1414 {
1415 NO_REGS, /* no registers in set */
1416 M16_NA_REGS, /* mips16 regs not used to pass args */
1417 M16_REGS, /* mips16 directly accessible registers */
1418 T_REG, /* mips16 T register ($24) */
1419 M16_T_REGS, /* mips16 registers plus T register */
1420 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1421 V1_REG, /* Register $v1 ($3) used for TLS access. */
1422 LEA_REGS, /* Every GPR except $25 */
1423 GR_REGS, /* integer registers */
1424 FP_REGS, /* floating point registers */
1425 HI_REG, /* hi register */
1426 LO_REG, /* lo register */
1427 MD_REGS, /* multiply/divide registers (hi/lo) */
1428 COP0_REGS, /* generic coprocessor classes */
1429 COP2_REGS,
1430 COP3_REGS,
1431 HI_AND_GR_REGS, /* union classes */
1432 LO_AND_GR_REGS,
1433 HI_AND_FP_REGS,
1434 COP0_AND_GR_REGS,
1435 COP2_AND_GR_REGS,
1436 COP3_AND_GR_REGS,
1437 ALL_COP_REGS,
1438 ALL_COP_AND_GR_REGS,
1439 ST_REGS, /* status registers (fp status) */
1440 ALL_REGS, /* all registers */
1441 LIM_REG_CLASSES /* max value + 1 */
1442 };
1443
1444 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1445
1446 #define GENERAL_REGS GR_REGS
1447
1448 /* An initializer containing the names of the register classes as C
1449 string constants. These names are used in writing some of the
1450 debugging dumps. */
1451
1452 #define REG_CLASS_NAMES \
1453 { \
1454 "NO_REGS", \
1455 "M16_NA_REGS", \
1456 "M16_REGS", \
1457 "T_REG", \
1458 "M16_T_REGS", \
1459 "PIC_FN_ADDR_REG", \
1460 "V1_REG", \
1461 "LEA_REGS", \
1462 "GR_REGS", \
1463 "FP_REGS", \
1464 "HI_REG", \
1465 "LO_REG", \
1466 "MD_REGS", \
1467 /* coprocessor registers */ \
1468 "COP0_REGS", \
1469 "COP2_REGS", \
1470 "COP3_REGS", \
1471 "HI_AND_GR_REGS", \
1472 "LO_AND_GR_REGS", \
1473 "HI_AND_FP_REGS", \
1474 "COP0_AND_GR_REGS", \
1475 "COP2_AND_GR_REGS", \
1476 "COP3_AND_GR_REGS", \
1477 "ALL_COP_REGS", \
1478 "ALL_COP_AND_GR_REGS", \
1479 "ST_REGS", \
1480 "ALL_REGS" \
1481 }
1482
1483 /* An initializer containing the contents of the register classes,
1484 as integers which are bit masks. The Nth integer specifies the
1485 contents of class N. The way the integer MASK is interpreted is
1486 that register R is in the class if `MASK & (1 << R)' is 1.
1487
1488 When the machine has more than 32 registers, an integer does not
1489 suffice. Then the integers are replaced by sub-initializers,
1490 braced groupings containing several integers. Each
1491 sub-initializer must be suitable as an initializer for the type
1492 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1493
1494 #define REG_CLASS_CONTENTS \
1495 { \
1496 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1497 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1498 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1499 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1500 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1501 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1502 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1503 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1504 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1505 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1506 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1507 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1508 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1509 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1510 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1511 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1512 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1513 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1514 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1515 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1516 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1517 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1518 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1519 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1520 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1521 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1522 }
1523
1524
1525 /* A C expression whose value is a register class containing hard
1526 register REGNO. In general there is more that one such class;
1527 choose a class which is "minimal", meaning that no smaller class
1528 also contains the register. */
1529
1530 extern const enum reg_class mips_regno_to_class[];
1531
1532 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1533
1534 /* A macro whose definition is the name of the class to which a
1535 valid base register must belong. A base register is one used in
1536 an address which is the register value plus a displacement. */
1537
1538 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1539
1540 /* A macro whose definition is the name of the class to which a
1541 valid index register must belong. An index register is one used
1542 in an address where its value is either multiplied by a scale
1543 factor or added to another register (as well as added to a
1544 displacement). */
1545
1546 #define INDEX_REG_CLASS NO_REGS
1547
1548 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1549 registers explicitly used in the rtl to be used as spill registers
1550 but prevents the compiler from extending the lifetime of these
1551 registers. */
1552
1553 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1554
1555 /* This macro is used later on in the file. */
1556 #define GR_REG_CLASS_P(CLASS) \
1557 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1558 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1559 || (CLASS) == V1_REG \
1560 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1561
1562 /* This macro is also used later on in the file. */
1563 #define COP_REG_CLASS_P(CLASS) \
1564 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1565
1566 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1567 is the default value (allocate the registers in numeric order). We
1568 define it just so that we can override it for the mips16 target in
1569 ORDER_REGS_FOR_LOCAL_ALLOC. */
1570
1571 #define REG_ALLOC_ORDER \
1572 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1573 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1574 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1575 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1576 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1577 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1578 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1579 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1580 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1581 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1582 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1583 }
1584
1585 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1586 to be rearranged based on a particular function. On the mips16, we
1587 want to allocate $24 (T_REG) before other registers for
1588 instructions for which it is possible. */
1589
1590 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1591
1592 /* REGISTER AND CONSTANT CLASSES */
1593
1594 /* Get reg_class from a letter such as appears in the machine
1595 description.
1596
1597 DEFINED REGISTER CLASSES:
1598
1599 'd' General (aka integer) registers
1600 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1601 'y' General registers (in both mips16 and non mips16 mode)
1602 'e' Effective address registers (general registers except $25)
1603 't' mips16 temporary register ($24)
1604 'f' Floating point registers
1605 'h' Hi register
1606 'l' Lo register
1607 'v' $v1 only
1608 'x' Multiply/divide registers
1609 'z' FP Status register
1610 'B' Cop0 register
1611 'C' Cop2 register
1612 'D' Cop3 register
1613 'b' All registers */
1614
1615 extern enum reg_class mips_char_to_class[256];
1616
1617 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1618
1619 /* True if VALUE is a signed 16-bit number. */
1620
1621 #define SMALL_OPERAND(VALUE) \
1622 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1623
1624 /* True if VALUE is an unsigned 16-bit number. */
1625
1626 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1627 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1628
1629 /* True if VALUE can be loaded into a register using LUI. */
1630
1631 #define LUI_OPERAND(VALUE) \
1632 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1633 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1634
1635 /* Return a value X with the low 16 bits clear, and such that
1636 VALUE - X is a signed 16-bit value. */
1637
1638 #define CONST_HIGH_PART(VALUE) \
1639 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1640
1641 #define CONST_LOW_PART(VALUE) \
1642 ((VALUE) - CONST_HIGH_PART (VALUE))
1643
1644 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1645 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1646 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1647
1648 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1649 string can be used to stand for particular ranges of immediate
1650 operands. This macro defines what the ranges are. C is the
1651 letter, and VALUE is a constant value. Return 1 if VALUE is
1652 in the range specified by C. */
1653
1654 /* For MIPS:
1655
1656 `I' is used for the range of constants an arithmetic insn can
1657 actually contain (16 bits signed integers).
1658
1659 `J' is used for the range which is just zero (i.e., $r0).
1660
1661 `K' is used for the range of constants a logical insn can actually
1662 contain (16 bit zero-extended integers).
1663
1664 `L' is used for the range of constants that be loaded with lui
1665 (i.e., the bottom 16 bits are zero).
1666
1667 `M' is used for the range of constants that take two words to load
1668 (i.e., not matched by `I', `K', and `L').
1669
1670 `N' is used for negative 16 bit constants other than -65536.
1671
1672 `O' is a 15 bit signed integer.
1673
1674 `P' is used for positive 16 bit constants. */
1675
1676 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1677 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1678 : (C) == 'J' ? ((VALUE) == 0) \
1679 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1680 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1681 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1682 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1683 && !LUI_OPERAND (VALUE)) \
1684 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1685 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1686 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1687 : 0)
1688
1689 /* Similar, but for floating constants, and defining letters G and H.
1690 Here VALUE is the CONST_DOUBLE rtx itself. */
1691
1692 /* For Mips
1693
1694 'G' : Floating point 0 */
1695
1696 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1697 ((C) == 'G' \
1698 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1699
1700 /* Letters in the range `Q' through `U' may be defined in a
1701 machine-dependent fashion to stand for arbitrary operand types.
1702 The machine description macro `EXTRA_CONSTRAINT' is passed the
1703 operand as its first argument and the constraint letter as its
1704 second operand.
1705
1706 `Q' is for signed 16-bit constants.
1707 `R' is for single-instruction memory references. Note that this
1708 constraint has often been used in linux and glibc code.
1709 `S' is for legitimate constant call addresses.
1710 `T' is for constant move_operands that cannot be safely loaded into $25.
1711 `U' is for constant move_operands that can be safely loaded into $25.
1712 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1713 This is true for all non-mips16 references (although it can sometimes
1714 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1715 stack and constant-pool references.
1716 `YG' is for 0 valued vector constants. */
1717
1718 #define EXTRA_CONSTRAINT_Y(OP,STR) \
1719 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
1720 && (OP) == CONST0_RTX (GET_MODE (OP))) \
1721 : FALSE)
1722
1723
1724 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
1725 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
1726 : ((CODE) == 'R') ? (MEM_P (OP) \
1727 && mips_fetch_insns (OP) == 1) \
1728 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
1729 && call_insn_operand (OP, VOIDmode)) \
1730 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
1731 && move_operand (OP, VOIDmode) \
1732 && mips_dangerous_for_la25_p (OP)) \
1733 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
1734 && move_operand (OP, VOIDmode) \
1735 && !mips_dangerous_for_la25_p (OP)) \
1736 : ((CODE) == 'W') ? (MEM_P (OP) \
1737 && memory_operand (OP, VOIDmode) \
1738 && (!TARGET_MIPS16 \
1739 || (!stack_operand (OP, VOIDmode) \
1740 && !CONSTANT_P (XEXP (OP, 0))))) \
1741 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
1742 : FALSE)
1743
1744 /* Y is the only multi-letter constraint, and has length 2. */
1745
1746 #define CONSTRAINT_LEN(C,STR) \
1747 (((C) == 'Y') ? 2 \
1748 : DEFAULT_CONSTRAINT_LEN (C, STR))
1749
1750 /* Say which of the above are memory constraints. */
1751 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
1752
1753 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1754 mips_preferred_reload_class (X, CLASS)
1755
1756 /* Certain machines have the property that some registers cannot be
1757 copied to some other registers without using memory. Define this
1758 macro on those machines to be a C expression that is nonzero if
1759 objects of mode MODE in registers of CLASS1 can only be copied to
1760 registers of class CLASS2 by storing a register of CLASS1 into
1761 memory and loading that memory location into a register of CLASS2.
1762
1763 Do not define this macro if its value would always be zero. */
1764 #if 0
1765 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1766 ((!TARGET_DEBUG_H_MODE \
1767 && GET_MODE_CLASS (MODE) == MODE_INT \
1768 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1769 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1770 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1771 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1772 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1773 #endif
1774 /* The HI and LO registers can only be reloaded via the general
1775 registers. Condition code registers can only be loaded to the
1776 general registers, and from the floating point registers. */
1777
1778 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1779 mips_secondary_reload_class (CLASS, MODE, X, 1)
1780 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1781 mips_secondary_reload_class (CLASS, MODE, X, 0)
1782
1783 /* Return the maximum number of consecutive registers
1784 needed to represent mode MODE in a register of class CLASS. */
1785
1786 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1787
1788 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1789 mips_cannot_change_mode_class (FROM, TO, CLASS)
1790 \f
1791 /* Stack layout; function entry, exit and calling. */
1792
1793 #define STACK_GROWS_DOWNWARD
1794
1795 /* The offset of the first local variable from the beginning of the frame.
1796 See compute_frame_size for details about the frame layout.
1797
1798 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1799 we assume that we will need 16 bytes of argument space. This is because
1800 the value profiling code may emit calls to cmpdi2 in leaf functions.
1801 Without this hack, the local variables will start at sp+8 and the gp save
1802 area will be at sp+16, and thus they will overlap. compute_frame_size is
1803 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1804 will end up as 24 instead of 8. This won't be needed if profiling code is
1805 inserted before virtual register instantiation. */
1806
1807 #define STARTING_FRAME_OFFSET \
1808 ((flag_profile_values && ! TARGET_64BIT \
1809 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1810 : current_function_outgoing_args_size) \
1811 + (TARGET_ABICALLS && !TARGET_NEWABI \
1812 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1813
1814 #define RETURN_ADDR_RTX mips_return_addr
1815
1816 /* Since the mips16 ISA mode is encoded in the least-significant bit
1817 of the address, mask it off return addresses for purposes of
1818 finding exception handling regions. */
1819
1820 #define MASK_RETURN_ADDR GEN_INT (-2)
1821
1822
1823 /* Similarly, don't use the least-significant bit to tell pointers to
1824 code from vtable index. */
1825
1826 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1827
1828 /* The eliminations to $17 are only used for mips16 code. See the
1829 definition of HARD_FRAME_POINTER_REGNUM. */
1830
1831 #define ELIMINABLE_REGS \
1832 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1833 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1834 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1835 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1836 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1837 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1838
1839 /* We can always eliminate to the hard frame pointer. We can eliminate
1840 to the stack pointer unless a frame pointer is needed.
1841
1842 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1843 reload may be unable to compute the address of a local variable,
1844 since there is no way to add a large constant to the stack pointer
1845 without using a temporary register. */
1846 #define CAN_ELIMINATE(FROM, TO) \
1847 ((TO) == HARD_FRAME_POINTER_REGNUM \
1848 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1849 && (!TARGET_MIPS16 \
1850 || compute_frame_size (get_frame_size ()) < 32768)))
1851
1852 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1853 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1854
1855 /* Allocate stack space for arguments at the beginning of each function. */
1856 #define ACCUMULATE_OUTGOING_ARGS 1
1857
1858 /* The argument pointer always points to the first argument. */
1859 #define FIRST_PARM_OFFSET(FNDECL) 0
1860
1861 /* o32 and o64 reserve stack space for all argument registers. */
1862 #define REG_PARM_STACK_SPACE(FNDECL) \
1863 (TARGET_OLDABI \
1864 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1865 : 0)
1866
1867 /* Define this if it is the responsibility of the caller to
1868 allocate the area reserved for arguments passed in registers.
1869 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1870 of this macro is to determine whether the space is included in
1871 `current_function_outgoing_args_size'. */
1872 #define OUTGOING_REG_PARM_STACK_SPACE
1873
1874 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1875 \f
1876 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1877
1878 /* Symbolic macros for the registers used to return integer and floating
1879 point values. */
1880
1881 #define GP_RETURN (GP_REG_FIRST + 2)
1882 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1883
1884 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1885
1886 /* Symbolic macros for the first/last argument registers. */
1887
1888 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1889 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1890 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1891 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1892
1893 #define LIBCALL_VALUE(MODE) \
1894 mips_function_value (NULL_TREE, NULL, (MODE))
1895
1896 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1897 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1898
1899 /* 1 if N is a possible register number for a function value.
1900 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1901 Currently, R2 and F0 are only implemented here (C has no complex type) */
1902
1903 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1904 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1905 && (N) == FP_RETURN + 2))
1906
1907 /* 1 if N is a possible register number for function argument passing.
1908 We have no FP argument registers when soft-float. When FP registers
1909 are 32 bits, we can't directly reference the odd numbered ones. */
1910
1911 #define FUNCTION_ARG_REGNO_P(N) \
1912 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1913 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1914 && !fixed_regs[N])
1915 \f
1916 /* This structure has to cope with two different argument allocation
1917 schemes. Most MIPS ABIs view the arguments as a structure, of which
1918 the first N words go in registers and the rest go on the stack. If I
1919 < N, the Ith word might go in Ith integer argument register or in a
1920 floating-point register. For these ABIs, we only need to remember
1921 the offset of the current argument into the structure.
1922
1923 The EABI instead allocates the integer and floating-point arguments
1924 separately. The first N words of FP arguments go in FP registers,
1925 the rest go on the stack. Likewise, the first N words of the other
1926 arguments go in integer registers, and the rest go on the stack. We
1927 need to maintain three counts: the number of integer registers used,
1928 the number of floating-point registers used, and the number of words
1929 passed on the stack.
1930
1931 We could keep separate information for the two ABIs (a word count for
1932 the standard ABIs, and three separate counts for the EABI). But it
1933 seems simpler to view the standard ABIs as forms of EABI that do not
1934 allocate floating-point registers.
1935
1936 So for the standard ABIs, the first N words are allocated to integer
1937 registers, and function_arg decides on an argument-by-argument basis
1938 whether that argument should really go in an integer register, or in
1939 a floating-point one. */
1940
1941 typedef struct mips_args {
1942 /* Always true for varargs functions. Otherwise true if at least
1943 one argument has been passed in an integer register. */
1944 int gp_reg_found;
1945
1946 /* The number of arguments seen so far. */
1947 unsigned int arg_number;
1948
1949 /* The number of integer registers used so far. For all ABIs except
1950 EABI, this is the number of words that have been added to the
1951 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1952 unsigned int num_gprs;
1953
1954 /* For EABI, the number of floating-point registers used so far. */
1955 unsigned int num_fprs;
1956
1957 /* The number of words passed on the stack. */
1958 unsigned int stack_words;
1959
1960 /* On the mips16, we need to keep track of which floating point
1961 arguments were passed in general registers, but would have been
1962 passed in the FP regs if this were a 32 bit function, so that we
1963 can move them to the FP regs if we wind up calling a 32 bit
1964 function. We record this information in fp_code, encoded in base
1965 four. A zero digit means no floating point argument, a one digit
1966 means an SFmode argument, and a two digit means a DFmode argument,
1967 and a three digit is not used. The low order digit is the first
1968 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1969 an SFmode argument. ??? A more sophisticated approach will be
1970 needed if MIPS_ABI != ABI_32. */
1971 int fp_code;
1972
1973 /* True if the function has a prototype. */
1974 int prototype;
1975 } CUMULATIVE_ARGS;
1976
1977 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1978 for a call to a function whose data type is FNTYPE.
1979 For a library call, FNTYPE is 0. */
1980
1981 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1982 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1983
1984 /* Update the data in CUM to advance over an argument
1985 of mode MODE and data type TYPE.
1986 (TYPE is null for libcalls where that information may not be available.) */
1987
1988 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1989 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1990
1991 /* Determine where to put an argument to a function.
1992 Value is zero to push the argument on the stack,
1993 or a hard register in which to store the argument.
1994
1995 MODE is the argument's machine mode.
1996 TYPE is the data type of the argument (as a tree).
1997 This is null for libcalls where that information may
1998 not be available.
1999 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2000 the preceding args and about the function being called.
2001 NAMED is nonzero if this argument is a named parameter
2002 (otherwise it is an extra parameter matching an ellipsis). */
2003
2004 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2005 function_arg( &CUM, MODE, TYPE, NAMED)
2006
2007 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2008
2009 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2010 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2011
2012 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2013 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2014
2015 /* True if using EABI and varargs can be passed in floating-point
2016 registers. Under these conditions, we need a more complex form
2017 of va_list, which tracks GPR, FPR and stack arguments separately. */
2018 #define EABI_FLOAT_VARARGS_P \
2019 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2020
2021 \f
2022 /* Say that the epilogue uses the return address register. Note that
2023 in the case of sibcalls, the values "used by the epilogue" are
2024 considered live at the start of the called function. */
2025 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2026
2027 /* Treat LOC as a byte offset from the stack pointer and round it up
2028 to the next fully-aligned offset. */
2029 #define MIPS_STACK_ALIGN(LOC) \
2030 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2031
2032 \f
2033 /* Implement `va_start' for varargs and stdarg. */
2034 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2035 mips_va_start (valist, nextarg)
2036 \f
2037 /* Output assembler code to FILE to increment profiler label # LABELNO
2038 for profiling a function entry. */
2039
2040 #define FUNCTION_PROFILER(FILE, LABELNO) \
2041 { \
2042 if (TARGET_MIPS16) \
2043 sorry ("mips16 function profiling"); \
2044 fprintf (FILE, "\t.set\tnoat\n"); \
2045 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2046 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2047 if (!TARGET_NEWABI) \
2048 { \
2049 fprintf (FILE, \
2050 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2051 TARGET_64BIT ? "dsubu" : "subu", \
2052 reg_names[STACK_POINTER_REGNUM], \
2053 reg_names[STACK_POINTER_REGNUM], \
2054 Pmode == DImode ? 16 : 8); \
2055 } \
2056 fprintf (FILE, "\tjal\t_mcount\n"); \
2057 fprintf (FILE, "\t.set\tat\n"); \
2058 }
2059
2060 /* No mips port has ever used the profiler counter word, so don't emit it
2061 or the label for it. */
2062
2063 #define NO_PROFILE_COUNTERS 1
2064
2065 /* Define this macro if the code for function profiling should come
2066 before the function prologue. Normally, the profiling code comes
2067 after. */
2068
2069 /* #define PROFILE_BEFORE_PROLOGUE */
2070
2071 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2072 the stack pointer does not matter. The value is tested only in
2073 functions that have frame pointers.
2074 No definition is equivalent to always zero. */
2075
2076 #define EXIT_IGNORE_STACK 1
2077
2078 \f
2079 /* A C statement to output, on the stream FILE, assembler code for a
2080 block of data that contains the constant parts of a trampoline.
2081 This code should not include a label--the label is taken care of
2082 automatically. */
2083
2084 #define TRAMPOLINE_TEMPLATE(STREAM) \
2085 { \
2086 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2087 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2088 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2089 if (ptr_mode == DImode) \
2090 { \
2091 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2092 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2093 } \
2094 else \
2095 { \
2096 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2097 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2098 } \
2099 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2100 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2101 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2102 if (ptr_mode == DImode) \
2103 { \
2104 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2105 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2106 } \
2107 else \
2108 { \
2109 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2110 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2111 } \
2112 }
2113
2114 /* A C expression for the size in bytes of the trampoline, as an
2115 integer. */
2116
2117 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2118
2119 /* Alignment required for trampolines, in bits. */
2120
2121 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2122
2123 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2124 program and data caches. */
2125
2126 #ifndef CACHE_FLUSH_FUNC
2127 #define CACHE_FLUSH_FUNC "_flush_cache"
2128 #endif
2129
2130 /* A C statement to initialize the variable parts of a trampoline.
2131 ADDR is an RTX for the address of the trampoline; FNADDR is an
2132 RTX for the address of the nested function; STATIC_CHAIN is an
2133 RTX for the static chain value that should be passed to the
2134 function when it is called. */
2135
2136 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2137 { \
2138 rtx func_addr, chain_addr; \
2139 \
2140 func_addr = plus_constant (ADDR, 32); \
2141 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2142 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2143 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2144 \
2145 /* Flush both caches. We need to flush the data cache in case \
2146 the system has a write-back cache. */ \
2147 /* ??? Should check the return value for errors. */ \
2148 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2149 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2150 0, VOIDmode, 3, ADDR, Pmode, \
2151 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2152 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2153 }
2154 \f
2155 /* Addressing modes, and classification of registers for them. */
2156
2157 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2158 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2159 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2160
2161 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2162 and check its validity for a certain class.
2163 We have two alternate definitions for each of them.
2164 The usual definition accepts all pseudo regs; the other rejects them all.
2165 The symbol REG_OK_STRICT causes the latter definition to be used.
2166
2167 Most source files want to accept pseudo regs in the hope that
2168 they will get allocated to the class that the insn wants them to be in.
2169 Some source files that are used after register allocation
2170 need to be strict. */
2171
2172 #ifndef REG_OK_STRICT
2173 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2174 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2175 #else
2176 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2177 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2178 #endif
2179
2180 #define REG_OK_FOR_INDEX_P(X) 0
2181
2182 \f
2183 /* Maximum number of registers that can appear in a valid memory address. */
2184
2185 #define MAX_REGS_PER_ADDRESS 1
2186
2187 #ifdef REG_OK_STRICT
2188 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2189 { \
2190 if (mips_legitimate_address_p (MODE, X, 1)) \
2191 goto ADDR; \
2192 }
2193 #else
2194 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2195 { \
2196 if (mips_legitimate_address_p (MODE, X, 0)) \
2197 goto ADDR; \
2198 }
2199 #endif
2200
2201 /* Check for constness inline but use mips_legitimate_address_p
2202 to check whether a constant really is an address. */
2203
2204 #define CONSTANT_ADDRESS_P(X) \
2205 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2206
2207 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2208
2209 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2210 do { \
2211 if (mips_legitimize_address (&(X), MODE)) \
2212 goto WIN; \
2213 } while (0)
2214
2215
2216 /* A C statement or compound statement with a conditional `goto
2217 LABEL;' executed if memory address X (an RTX) can have different
2218 meanings depending on the machine mode of the memory reference it
2219 is used for.
2220
2221 Autoincrement and autodecrement addresses typically have
2222 mode-dependent effects because the amount of the increment or
2223 decrement is the size of the operand being addressed. Some
2224 machines have other mode-dependent addresses. Many RISC machines
2225 have no mode-dependent addresses.
2226
2227 You may assume that ADDR is a valid address for the machine. */
2228
2229 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2230
2231 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2232 'the start of the function that this code is output in'. */
2233
2234 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2235 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2236 asm_fprintf ((FILE), "%U%s", \
2237 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2238 else \
2239 asm_fprintf ((FILE), "%U%s", (NAME))
2240 \f
2241 /* Specify the machine mode that this machine uses
2242 for the index in the tablejump instruction.
2243 ??? Using HImode in mips16 mode can cause overflow. */
2244 #define CASE_VECTOR_MODE \
2245 (TARGET_MIPS16 ? HImode : ptr_mode)
2246
2247 /* Define as C expression which evaluates to nonzero if the tablejump
2248 instruction expects the table to contain offsets from the address of the
2249 table.
2250 Do not define this if the table should contain absolute addresses. */
2251 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2252
2253 /* Define this as 1 if `char' should by default be signed; else as 0. */
2254 #ifndef DEFAULT_SIGNED_CHAR
2255 #define DEFAULT_SIGNED_CHAR 1
2256 #endif
2257
2258 /* Max number of bytes we can move from memory to memory
2259 in one reasonably fast instruction. */
2260 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2261 #define MAX_MOVE_MAX 8
2262
2263 /* Define this macro as a C expression which is nonzero if
2264 accessing less than a word of memory (i.e. a `char' or a
2265 `short') is no faster than accessing a word of memory, i.e., if
2266 such access require more than one instruction or if there is no
2267 difference in cost between byte and (aligned) word loads.
2268
2269 On RISC machines, it tends to generate better code to define
2270 this as 1, since it avoids making a QI or HI mode register. */
2271 #define SLOW_BYTE_ACCESS 1
2272
2273 /* Define this to be nonzero if shift instructions ignore all but the low-order
2274 few bits. */
2275 #define SHIFT_COUNT_TRUNCATED 1
2276
2277 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2278 is done just by pretending it is already truncated. */
2279 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2280 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2281
2282
2283 /* Specify the machine mode that pointers have.
2284 After generation of rtl, the compiler makes no further distinction
2285 between pointers and any other objects of this machine mode. */
2286
2287 #ifndef Pmode
2288 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2289 #endif
2290
2291 /* Give call MEMs SImode since it is the "most permissive" mode
2292 for both 32-bit and 64-bit targets. */
2293
2294 #define FUNCTION_MODE SImode
2295
2296 \f
2297 /* The cost of loading values from the constant pool. It should be
2298 larger than the cost of any constant we want to synthesize in-line. */
2299
2300 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2301
2302 /* A C expression for the cost of moving data from a register in
2303 class FROM to one in class TO. The classes are expressed using
2304 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2305 the default; other values are interpreted relative to that.
2306
2307 It is not required that the cost always equal 2 when FROM is the
2308 same as TO; on some machines it is expensive to move between
2309 registers if they are not general registers.
2310
2311 If reload sees an insn consisting of a single `set' between two
2312 hard registers, and if `REGISTER_MOVE_COST' applied to their
2313 classes returns a value of 2, reload does not check to ensure
2314 that the constraints of the insn are met. Setting a cost of
2315 other than 2 will allow reload to verify that the constraints are
2316 met. You should do this if the `movM' pattern's constraints do
2317 not allow such copying. */
2318
2319 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2320 mips_register_move_cost (MODE, FROM, TO)
2321
2322 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2323 (mips_cost->memory_latency \
2324 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2325
2326 /* Define if copies to/from condition code registers should be avoided.
2327
2328 This is needed for the MIPS because reload_outcc is not complete;
2329 it needs to handle cases where the source is a general or another
2330 condition code register. */
2331 #define AVOID_CCMODE_COPIES
2332
2333 /* A C expression for the cost of a branch instruction. A value of
2334 1 is the default; other values are interpreted relative to that. */
2335
2336 #define BRANCH_COST mips_cost->branch_cost
2337 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2338
2339 /* If defined, modifies the length assigned to instruction INSN as a
2340 function of the context in which it is used. LENGTH is an lvalue
2341 that contains the initially computed length of the insn and should
2342 be updated with the correct length of the insn. */
2343 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2344 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2345 \f
2346 /* Control the assembler format that we output. */
2347
2348 /* Output to assembler file text saying following lines
2349 may contain character constants, extra white space, comments, etc. */
2350
2351 #ifndef ASM_APP_ON
2352 #define ASM_APP_ON " #APP\n"
2353 #endif
2354
2355 /* Output to assembler file text saying following lines
2356 no longer contain unusual constructs. */
2357
2358 #ifndef ASM_APP_OFF
2359 #define ASM_APP_OFF " #NO_APP\n"
2360 #endif
2361
2362 #define REGISTER_NAMES \
2363 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2364 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2365 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2366 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2367 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2368 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2369 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2370 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2371 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2372 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2373 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2374 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2375 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2376 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2377 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2378 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2379 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2380 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2381 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2382 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2383 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2384 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2385
2386 /* List the "software" names for each register. Also list the numerical
2387 names for $fp and $sp. */
2388
2389 #define ADDITIONAL_REGISTER_NAMES \
2390 { \
2391 { "$29", 29 + GP_REG_FIRST }, \
2392 { "$30", 30 + GP_REG_FIRST }, \
2393 { "at", 1 + GP_REG_FIRST }, \
2394 { "v0", 2 + GP_REG_FIRST }, \
2395 { "v1", 3 + GP_REG_FIRST }, \
2396 { "a0", 4 + GP_REG_FIRST }, \
2397 { "a1", 5 + GP_REG_FIRST }, \
2398 { "a2", 6 + GP_REG_FIRST }, \
2399 { "a3", 7 + GP_REG_FIRST }, \
2400 { "t0", 8 + GP_REG_FIRST }, \
2401 { "t1", 9 + GP_REG_FIRST }, \
2402 { "t2", 10 + GP_REG_FIRST }, \
2403 { "t3", 11 + GP_REG_FIRST }, \
2404 { "t4", 12 + GP_REG_FIRST }, \
2405 { "t5", 13 + GP_REG_FIRST }, \
2406 { "t6", 14 + GP_REG_FIRST }, \
2407 { "t7", 15 + GP_REG_FIRST }, \
2408 { "s0", 16 + GP_REG_FIRST }, \
2409 { "s1", 17 + GP_REG_FIRST }, \
2410 { "s2", 18 + GP_REG_FIRST }, \
2411 { "s3", 19 + GP_REG_FIRST }, \
2412 { "s4", 20 + GP_REG_FIRST }, \
2413 { "s5", 21 + GP_REG_FIRST }, \
2414 { "s6", 22 + GP_REG_FIRST }, \
2415 { "s7", 23 + GP_REG_FIRST }, \
2416 { "t8", 24 + GP_REG_FIRST }, \
2417 { "t9", 25 + GP_REG_FIRST }, \
2418 { "k0", 26 + GP_REG_FIRST }, \
2419 { "k1", 27 + GP_REG_FIRST }, \
2420 { "gp", 28 + GP_REG_FIRST }, \
2421 { "sp", 29 + GP_REG_FIRST }, \
2422 { "fp", 30 + GP_REG_FIRST }, \
2423 { "ra", 31 + GP_REG_FIRST }, \
2424 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2425 }
2426
2427 /* This is meant to be redefined in the host dependent files. It is a
2428 set of alternative names and regnums for mips coprocessors. */
2429
2430 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2431
2432 /* A C compound statement to output to stdio stream STREAM the
2433 assembler syntax for an instruction operand X. X is an RTL
2434 expression.
2435
2436 CODE is a value that can be used to specify one of several ways
2437 of printing the operand. It is used when identical operands
2438 must be printed differently depending on the context. CODE
2439 comes from the `%' specification that was used to request
2440 printing of the operand. If the specification was just `%DIGIT'
2441 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2442 is the ASCII code for LTR.
2443
2444 If X is a register, this macro should print the register's name.
2445 The names can be found in an array `reg_names' whose type is
2446 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2447
2448 When the machine description has a specification `%PUNCT' (a `%'
2449 followed by a punctuation character), this macro is called with
2450 a null pointer for X and the punctuation character for CODE.
2451
2452 See mips.c for the MIPS specific codes. */
2453
2454 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2455
2456 /* A C expression which evaluates to true if CODE is a valid
2457 punctuation character for use in the `PRINT_OPERAND' macro. If
2458 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2459 punctuation characters (except for the standard one, `%') are
2460 used in this way. */
2461
2462 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2463
2464 /* A C compound statement to output to stdio stream STREAM the
2465 assembler syntax for an instruction operand that is a memory
2466 reference whose address is ADDR. ADDR is an RTL expression. */
2467
2468 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2469
2470
2471 /* A C statement, to be executed after all slot-filler instructions
2472 have been output. If necessary, call `dbr_sequence_length' to
2473 determine the number of slots filled in a sequence (zero if not
2474 currently outputting a sequence), to decide how many no-ops to
2475 output, or whatever.
2476
2477 Don't define this macro if it has nothing to do, but it is
2478 helpful in reading assembly output if the extent of the delay
2479 sequence is made explicit (e.g. with white space).
2480
2481 Note that output routines for instructions with delay slots must
2482 be prepared to deal with not being output as part of a sequence
2483 (i.e. when the scheduling pass is not run, or when no slot
2484 fillers could be found.) The variable `final_sequence' is null
2485 when not processing a sequence, otherwise it contains the
2486 `sequence' rtx being output. */
2487
2488 #define DBR_OUTPUT_SEQEND(STREAM) \
2489 do \
2490 { \
2491 if (set_nomacro > 0 && --set_nomacro == 0) \
2492 fputs ("\t.set\tmacro\n", STREAM); \
2493 \
2494 if (set_noreorder > 0 && --set_noreorder == 0) \
2495 fputs ("\t.set\treorder\n", STREAM); \
2496 \
2497 fputs ("\n", STREAM); \
2498 } \
2499 while (0)
2500
2501
2502 /* How to tell the debugger about changes of source files. */
2503 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2504 mips_output_filename (STREAM, NAME)
2505
2506 /* mips-tfile does not understand .stabd directives. */
2507 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2508 dbxout_begin_stabn_sline (LINE); \
2509 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2510 } while (0)
2511
2512 /* Use .loc directives for SDB line numbers. */
2513 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2514 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2515
2516 /* The MIPS implementation uses some labels for its own purpose. The
2517 following lists what labels are created, and are all formed by the
2518 pattern $L[a-z].*. The machine independent portion of GCC creates
2519 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2520
2521 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2522 $Lb[0-9]+ Begin blocks for MIPS debug support
2523 $Lc[0-9]+ Label for use in s<xx> operation.
2524 $Le[0-9]+ End blocks for MIPS debug support */
2525
2526 #undef ASM_DECLARE_OBJECT_NAME
2527 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2528 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2529
2530 /* Globalizing directive for a label. */
2531 #define GLOBAL_ASM_OP "\t.globl\t"
2532
2533 /* This says how to define a global common symbol. */
2534
2535 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2536
2537 /* This says how to define a local common symbol (i.e., not visible to
2538 linker). */
2539
2540 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2541 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2542 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2543 #endif
2544
2545 /* This says how to output an external. It would be possible not to
2546 output anything and let undefined symbol become external. However
2547 the assembler uses length information on externals to allocate in
2548 data/sdata bss/sbss, thereby saving exec time. */
2549
2550 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2551 mips_output_external(STREAM,DECL,NAME)
2552
2553 /* This is how to declare a function name. The actual work of
2554 emitting the label is moved to function_prologue, so that we can
2555 get the line number correctly emitted before the .ent directive,
2556 and after any .file directives. Define as empty so that the function
2557 is not declared before the .ent directive elsewhere. */
2558
2559 #undef ASM_DECLARE_FUNCTION_NAME
2560 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2561
2562 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2563 #define FUNCTION_NAME_ALREADY_DECLARED 0
2564 #endif
2565
2566 /* This is how to store into the string LABEL
2567 the symbol_ref name of an internal numbered label where
2568 PREFIX is the class of label and NUM is the number within the class.
2569 This is suitable for output with `assemble_name'. */
2570
2571 #undef ASM_GENERATE_INTERNAL_LABEL
2572 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2573 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2574
2575 /* This is how to output an element of a case-vector that is absolute. */
2576
2577 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2578 fprintf (STREAM, "\t%s\t%sL%d\n", \
2579 ptr_mode == DImode ? ".dword" : ".word", \
2580 LOCAL_LABEL_PREFIX, \
2581 VALUE)
2582
2583 /* This is how to output an element of a case-vector. We can make the
2584 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2585 is supported. */
2586
2587 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2588 do { \
2589 if (TARGET_MIPS16) \
2590 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2591 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2592 else if (TARGET_GPWORD) \
2593 fprintf (STREAM, "\t%s\t%sL%d\n", \
2594 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2595 LOCAL_LABEL_PREFIX, VALUE); \
2596 else \
2597 fprintf (STREAM, "\t%s\t%sL%d\n", \
2598 ptr_mode == DImode ? ".dword" : ".word", \
2599 LOCAL_LABEL_PREFIX, VALUE); \
2600 } while (0)
2601
2602 /* When generating MIPS16 code, we want the jump table to be in the text
2603 section so that we can load its address using a PC-relative addition. */
2604 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2605
2606 /* This is how to output an assembler line
2607 that says to advance the location counter
2608 to a multiple of 2**LOG bytes. */
2609
2610 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2611 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2612
2613 /* This is how to output an assembler line to advance the location
2614 counter by SIZE bytes. */
2615
2616 #undef ASM_OUTPUT_SKIP
2617 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2618 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2619
2620 /* This is how to output a string. */
2621 #undef ASM_OUTPUT_ASCII
2622 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2623 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2624
2625 /* Output #ident as a in the read-only data section. */
2626 #undef ASM_OUTPUT_IDENT
2627 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2628 { \
2629 const char *p = STRING; \
2630 int size = strlen (p) + 1; \
2631 readonly_data_section (); \
2632 assemble_string (p, size); \
2633 }
2634 \f
2635 /* Default to -G 8 */
2636 #ifndef MIPS_DEFAULT_GVALUE
2637 #define MIPS_DEFAULT_GVALUE 8
2638 #endif
2639
2640 /* Define the strings to put out for each section in the object file. */
2641 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2642 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2643 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2644
2645 #undef READONLY_DATA_SECTION_ASM_OP
2646 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2647 \f
2648 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2649 do \
2650 { \
2651 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2652 TARGET_64BIT ? "dsubu" : "subu", \
2653 reg_names[STACK_POINTER_REGNUM], \
2654 reg_names[STACK_POINTER_REGNUM], \
2655 TARGET_64BIT ? "sd" : "sw", \
2656 reg_names[REGNO], \
2657 reg_names[STACK_POINTER_REGNUM]); \
2658 } \
2659 while (0)
2660
2661 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2662 do \
2663 { \
2664 if (! set_noreorder) \
2665 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2666 \
2667 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2668 TARGET_64BIT ? "ld" : "lw", \
2669 reg_names[REGNO], \
2670 reg_names[STACK_POINTER_REGNUM], \
2671 TARGET_64BIT ? "daddu" : "addu", \
2672 reg_names[STACK_POINTER_REGNUM], \
2673 reg_names[STACK_POINTER_REGNUM]); \
2674 \
2675 if (! set_noreorder) \
2676 fprintf (STREAM, "\t.set\treorder\n"); \
2677 } \
2678 while (0)
2679
2680 /* How to start an assembler comment.
2681 The leading space is important (the mips native assembler requires it). */
2682 #ifndef ASM_COMMENT_START
2683 #define ASM_COMMENT_START " #"
2684 #endif
2685 \f
2686 /* Default definitions for size_t and ptrdiff_t. We must override the
2687 definitions from ../svr4.h on mips-*-linux-gnu. */
2688
2689 #undef SIZE_TYPE
2690 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2691
2692 #undef PTRDIFF_TYPE
2693 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2694 \f
2695 #ifndef __mips16
2696 /* Since the bits of the _init and _fini function is spread across
2697 many object files, each potentially with its own GP, we must assume
2698 we need to load our GP. We don't preserve $gp or $ra, since each
2699 init/fini chunk is supposed to initialize $gp, and crti/crtn
2700 already take care of preserving $ra and, when appropriate, $gp. */
2701 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2702 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2703 asm (SECTION_OP "\n\
2704 .set noreorder\n\
2705 bal 1f\n\
2706 nop\n\
2707 1: .cpload $31\n\
2708 .set reorder\n\
2709 jal " USER_LABEL_PREFIX #FUNC "\n\
2710 " TEXT_SECTION_ASM_OP);
2711 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2712 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2713 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2714 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2715 asm (SECTION_OP "\n\
2716 .set noreorder\n\
2717 bal 1f\n\
2718 nop\n\
2719 1: .set reorder\n\
2720 .cpsetup $31, $2, 1b\n\
2721 jal " USER_LABEL_PREFIX #FUNC "\n\
2722 " TEXT_SECTION_ASM_OP);
2723 #endif
2724 #endif
2725
2726 #ifndef HAVE_AS_TLS
2727 #define HAVE_AS_TLS 0
2728 #endif
Mirror of the offical gcc git repository hosted at gcc.gnu.org