1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
56 /* This is used for communication between ASM_OUTPUT_LABEL and
57 ASM_OUTPUT_LABELREF. */
58 int ia64_asm_output_label
= 0;
60 /* Define the information needed to generate branch and scc insns. This is
61 stored from the compare operation. */
62 struct rtx_def
* ia64_compare_op0
;
63 struct rtx_def
* ia64_compare_op1
;
65 /* Register names for ia64_expand_prologue. */
66 static const char * const ia64_reg_numbers
[96] =
67 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
68 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
69 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
70 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
71 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
72 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
73 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
74 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
75 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
76 "r104","r105","r106","r107","r108","r109","r110","r111",
77 "r112","r113","r114","r115","r116","r117","r118","r119",
78 "r120","r121","r122","r123","r124","r125","r126","r127"};
80 /* ??? These strings could be shared with REGISTER_NAMES. */
81 static const char * const ia64_input_reg_names
[8] =
82 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
84 /* ??? These strings could be shared with REGISTER_NAMES. */
85 static const char * const ia64_local_reg_names
[80] =
86 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
87 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
88 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
89 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
90 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
91 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
92 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
93 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
94 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
95 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_output_reg_names
[8] =
99 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
101 /* Which cpu are we scheduling for. */
102 enum processor_type ia64_tune
= PROCESSOR_ITANIUM2
;
104 /* Determines whether we run our final scheduling pass or not. We always
105 avoid the normal second scheduling pass. */
106 static int ia64_flag_schedule_insns2
;
108 /* Determines whether we run variable tracking in machine dependent
110 static int ia64_flag_var_tracking
;
112 /* Variables which are this size or smaller are put in the sdata/sbss
115 unsigned int ia64_section_threshold
;
117 /* The following variable is used by the DFA insn scheduler. The value is
118 TRUE if we do insn bundling instead of insn scheduling. */
121 /* Structure to be filled in by ia64_compute_frame_size with register
122 save masks and offsets for the current function. */
124 struct ia64_frame_info
126 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
127 the caller's scratch area. */
128 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
129 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
130 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
131 HARD_REG_SET mask
; /* mask of saved registers. */
132 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
133 registers or long-term scratches. */
134 int n_spilled
; /* number of spilled registers. */
135 int reg_fp
; /* register for fp. */
136 int reg_save_b0
; /* save register for b0. */
137 int reg_save_pr
; /* save register for prs. */
138 int reg_save_ar_pfs
; /* save register for ar.pfs. */
139 int reg_save_ar_unat
; /* save register for ar.unat. */
140 int reg_save_ar_lc
; /* save register for ar.lc. */
141 int reg_save_gp
; /* save register for gp. */
142 int n_input_regs
; /* number of input registers used. */
143 int n_local_regs
; /* number of local registers used. */
144 int n_output_regs
; /* number of output registers used. */
145 int n_rotate_regs
; /* number of rotating registers used. */
147 char need_regstk
; /* true if a .regstk directive needed. */
148 char initialized
; /* true if the data is finalized. */
151 /* Current frame information calculated by ia64_compute_frame_size. */
152 static struct ia64_frame_info current_frame_info
;
154 static int ia64_first_cycle_multipass_dfa_lookahead (void);
155 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
156 static void ia64_init_dfa_pre_cycle_insn (void);
157 static rtx
ia64_dfa_pre_cycle_insn (void);
158 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
159 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
160 static rtx
gen_tls_get_addr (void);
161 static rtx
gen_thread_pointer (void);
162 static int find_gr_spill (int);
163 static int next_scratch_gr_reg (void);
164 static void mark_reg_gr_used_mask (rtx
, void *);
165 static void ia64_compute_frame_size (HOST_WIDE_INT
);
166 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
167 static void finish_spill_pointers (void);
168 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
169 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
170 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
171 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
172 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
173 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
175 static enum machine_mode
hfa_element_mode (tree
, bool);
176 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
178 static bool ia64_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
180 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
182 static bool ia64_function_ok_for_sibcall (tree
, tree
);
183 static bool ia64_return_in_memory (tree
, tree
);
184 static bool ia64_rtx_costs (rtx
, int, int, int *);
185 static void fix_range (const char *);
186 static bool ia64_handle_option (size_t, const char *, int);
187 static struct machine_function
* ia64_init_machine_status (void);
188 static void emit_insn_group_barriers (FILE *);
189 static void emit_all_insn_group_barriers (FILE *);
190 static void final_emit_insn_group_barriers (FILE *);
191 static void emit_predicate_relation_info (void);
192 static void ia64_reorg (void);
193 static bool ia64_in_small_data_p (tree
);
194 static void process_epilogue (void);
195 static int process_set (FILE *, rtx
);
197 static bool ia64_assemble_integer (rtx
, unsigned int, int);
198 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
199 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
200 static void ia64_output_function_end_prologue (FILE *);
202 static int ia64_issue_rate (void);
203 static int ia64_adjust_cost (rtx
, rtx
, rtx
, int);
204 static void ia64_sched_init (FILE *, int, int);
205 static void ia64_sched_finish (FILE *, int);
206 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
207 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
208 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
209 static int ia64_variable_issue (FILE *, int, rtx
, int);
211 static struct bundle_state
*get_free_bundle_state (void);
212 static void free_bundle_state (struct bundle_state
*);
213 static void initiate_bundle_states (void);
214 static void finish_bundle_states (void);
215 static unsigned bundle_state_hash (const void *);
216 static int bundle_state_eq_p (const void *, const void *);
217 static int insert_bundle_state (struct bundle_state
*);
218 static void initiate_bundle_state_table (void);
219 static void finish_bundle_state_table (void);
220 static int try_issue_nops (struct bundle_state
*, int);
221 static int try_issue_insn (struct bundle_state
*, rtx
);
222 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
223 static int get_max_pos (state_t
);
224 static int get_template (state_t
, int);
226 static rtx
get_next_important_insn (rtx
, rtx
);
227 static void bundling (FILE *, int, rtx
, rtx
);
229 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
230 HOST_WIDE_INT
, tree
);
231 static void ia64_file_start (void);
233 static void ia64_select_rtx_section (enum machine_mode
, rtx
,
234 unsigned HOST_WIDE_INT
);
235 static void ia64_output_dwarf_dtprel (FILE *, int, rtx
)
237 static void ia64_rwreloc_select_section (tree
, int, unsigned HOST_WIDE_INT
)
239 static void ia64_rwreloc_unique_section (tree
, int)
241 static void ia64_rwreloc_select_rtx_section (enum machine_mode
, rtx
,
242 unsigned HOST_WIDE_INT
)
244 static unsigned int ia64_section_type_flags (tree
, const char *, int);
245 static void ia64_hpux_add_extern_decl (tree decl
)
247 static void ia64_hpux_file_end (void)
249 static void ia64_init_libfuncs (void)
251 static void ia64_hpux_init_libfuncs (void)
253 static void ia64_sysv4_init_libfuncs (void)
255 static void ia64_vms_init_libfuncs (void)
258 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
259 static void ia64_encode_section_info (tree
, rtx
, int);
260 static rtx
ia64_struct_value_rtx (tree
, int);
261 static tree
ia64_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
262 static bool ia64_scalar_mode_supported_p (enum machine_mode mode
);
263 static bool ia64_vector_mode_supported_p (enum machine_mode mode
);
264 static bool ia64_cannot_force_const_mem (rtx
);
265 static const char *ia64_mangle_fundamental_type (tree
);
267 /* Table of valid machine attributes. */
268 static const struct attribute_spec ia64_attribute_table
[] =
270 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
271 { "syscall_linkage", 0, 0, false, true, true, NULL
},
272 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
},
273 { NULL
, 0, 0, false, false, false, NULL
}
276 /* Initialize the GCC target structure. */
277 #undef TARGET_ATTRIBUTE_TABLE
278 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
280 #undef TARGET_INIT_BUILTINS
281 #define TARGET_INIT_BUILTINS ia64_init_builtins
283 #undef TARGET_EXPAND_BUILTIN
284 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
286 #undef TARGET_ASM_BYTE_OP
287 #define TARGET_ASM_BYTE_OP "\tdata1\t"
288 #undef TARGET_ASM_ALIGNED_HI_OP
289 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
290 #undef TARGET_ASM_ALIGNED_SI_OP
291 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
292 #undef TARGET_ASM_ALIGNED_DI_OP
293 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
294 #undef TARGET_ASM_UNALIGNED_HI_OP
295 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
296 #undef TARGET_ASM_UNALIGNED_SI_OP
297 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
298 #undef TARGET_ASM_UNALIGNED_DI_OP
299 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
300 #undef TARGET_ASM_INTEGER
301 #define TARGET_ASM_INTEGER ia64_assemble_integer
303 #undef TARGET_ASM_FUNCTION_PROLOGUE
304 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
305 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
306 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
307 #undef TARGET_ASM_FUNCTION_EPILOGUE
308 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
310 #undef TARGET_IN_SMALL_DATA_P
311 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
313 #undef TARGET_SCHED_ADJUST_COST
314 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
315 #undef TARGET_SCHED_ISSUE_RATE
316 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
317 #undef TARGET_SCHED_VARIABLE_ISSUE
318 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
319 #undef TARGET_SCHED_INIT
320 #define TARGET_SCHED_INIT ia64_sched_init
321 #undef TARGET_SCHED_FINISH
322 #define TARGET_SCHED_FINISH ia64_sched_finish
323 #undef TARGET_SCHED_REORDER
324 #define TARGET_SCHED_REORDER ia64_sched_reorder
325 #undef TARGET_SCHED_REORDER2
326 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
328 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
329 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
331 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
332 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
334 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
335 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
336 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
337 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
339 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
340 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
341 ia64_first_cycle_multipass_dfa_lookahead_guard
343 #undef TARGET_SCHED_DFA_NEW_CYCLE
344 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
346 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
347 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
348 #undef TARGET_PASS_BY_REFERENCE
349 #define TARGET_PASS_BY_REFERENCE ia64_pass_by_reference
350 #undef TARGET_ARG_PARTIAL_BYTES
351 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
353 #undef TARGET_ASM_OUTPUT_MI_THUNK
354 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
355 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
356 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
358 #undef TARGET_ASM_FILE_START
359 #define TARGET_ASM_FILE_START ia64_file_start
361 #undef TARGET_RTX_COSTS
362 #define TARGET_RTX_COSTS ia64_rtx_costs
363 #undef TARGET_ADDRESS_COST
364 #define TARGET_ADDRESS_COST hook_int_rtx_0
366 #undef TARGET_MACHINE_DEPENDENT_REORG
367 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
369 #undef TARGET_ENCODE_SECTION_INFO
370 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
372 #undef TARGET_SECTION_TYPE_FLAGS
373 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
376 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
377 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
380 /* ??? ABI doesn't allow us to define this. */
382 #undef TARGET_PROMOTE_FUNCTION_ARGS
383 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
386 /* ??? ABI doesn't allow us to define this. */
388 #undef TARGET_PROMOTE_FUNCTION_RETURN
389 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
392 /* ??? Investigate. */
394 #undef TARGET_PROMOTE_PROTOTYPES
395 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
398 #undef TARGET_STRUCT_VALUE_RTX
399 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
400 #undef TARGET_RETURN_IN_MEMORY
401 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
402 #undef TARGET_SETUP_INCOMING_VARARGS
403 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
404 #undef TARGET_STRICT_ARGUMENT_NAMING
405 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
406 #undef TARGET_MUST_PASS_IN_STACK
407 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
409 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
410 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
412 #undef TARGET_UNWIND_EMIT
413 #define TARGET_UNWIND_EMIT process_for_unwind_directive
415 #undef TARGET_SCALAR_MODE_SUPPORTED_P
416 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
417 #undef TARGET_VECTOR_MODE_SUPPORTED_P
418 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
420 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
421 in an order different from the specified program order. */
422 #undef TARGET_RELAXED_ORDERING
423 #define TARGET_RELAXED_ORDERING true
425 #undef TARGET_DEFAULT_TARGET_FLAGS
426 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
427 #undef TARGET_HANDLE_OPTION
428 #define TARGET_HANDLE_OPTION ia64_handle_option
430 #undef TARGET_CANNOT_FORCE_CONST_MEM
431 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
433 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
434 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ia64_mangle_fundamental_type
436 struct gcc_target targetm
= TARGET_INITIALIZER
;
440 ADDR_AREA_NORMAL
, /* normal address area */
441 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
445 static GTY(()) tree small_ident1
;
446 static GTY(()) tree small_ident2
;
451 if (small_ident1
== 0)
453 small_ident1
= get_identifier ("small");
454 small_ident2
= get_identifier ("__small__");
458 /* Retrieve the address area that has been chosen for the given decl. */
460 static ia64_addr_area
461 ia64_get_addr_area (tree decl
)
465 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
471 id
= TREE_VALUE (TREE_VALUE (model_attr
));
472 if (id
== small_ident1
|| id
== small_ident2
)
473 return ADDR_AREA_SMALL
;
475 return ADDR_AREA_NORMAL
;
479 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
,
480 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
482 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
484 tree arg
, decl
= *node
;
487 arg
= TREE_VALUE (args
);
488 if (arg
== small_ident1
|| arg
== small_ident2
)
490 addr_area
= ADDR_AREA_SMALL
;
494 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
495 IDENTIFIER_POINTER (name
));
496 *no_add_attrs
= true;
499 switch (TREE_CODE (decl
))
502 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
504 && !TREE_STATIC (decl
))
506 error ("%Jan address area attribute cannot be specified for "
507 "local variables", decl
, decl
);
508 *no_add_attrs
= true;
510 area
= ia64_get_addr_area (decl
);
511 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
513 error ("%Jaddress area of '%s' conflicts with previous "
514 "declaration", decl
, decl
);
515 *no_add_attrs
= true;
520 error ("%Jaddress area attribute cannot be specified for functions",
522 *no_add_attrs
= true;
526 warning (OPT_Wattributes
, "%qs attribute ignored",
527 IDENTIFIER_POINTER (name
));
528 *no_add_attrs
= true;
536 ia64_encode_addr_area (tree decl
, rtx symbol
)
540 flags
= SYMBOL_REF_FLAGS (symbol
);
541 switch (ia64_get_addr_area (decl
))
543 case ADDR_AREA_NORMAL
: break;
544 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
545 default: gcc_unreachable ();
547 SYMBOL_REF_FLAGS (symbol
) = flags
;
551 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
553 default_encode_section_info (decl
, rtl
, first
);
555 /* Careful not to prod global register variables. */
556 if (TREE_CODE (decl
) == VAR_DECL
557 && GET_CODE (DECL_RTL (decl
)) == MEM
558 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
559 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
560 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
563 /* Implement CONST_OK_FOR_LETTER_P. */
566 ia64_const_ok_for_letter_p (HOST_WIDE_INT value
, char c
)
571 return CONST_OK_FOR_I (value
);
573 return CONST_OK_FOR_J (value
);
575 return CONST_OK_FOR_K (value
);
577 return CONST_OK_FOR_L (value
);
579 return CONST_OK_FOR_M (value
);
581 return CONST_OK_FOR_N (value
);
583 return CONST_OK_FOR_O (value
);
585 return CONST_OK_FOR_P (value
);
591 /* Implement CONST_DOUBLE_OK_FOR_LETTER_P. */
594 ia64_const_double_ok_for_letter_p (rtx value
, char c
)
599 return CONST_DOUBLE_OK_FOR_G (value
);
605 /* Implement EXTRA_CONSTRAINT. */
608 ia64_extra_constraint (rtx value
, char c
)
613 /* Non-volatile memory for FP_REG loads/stores. */
614 return memory_operand(value
, VOIDmode
) && !MEM_VOLATILE_P (value
);
617 /* 1..4 for shladd arguments. */
618 return (GET_CODE (value
) == CONST_INT
619 && INTVAL (value
) >= 1 && INTVAL (value
) <= 4);
622 /* Non-post-inc memory for asms and other unsavory creatures. */
623 return (GET_CODE (value
) == MEM
624 && GET_RTX_CLASS (GET_CODE (XEXP (value
, 0))) != RTX_AUTOINC
625 && (reload_in_progress
|| memory_operand (value
, VOIDmode
)));
628 /* Symbol ref to small-address-area. */
629 return small_addr_symbolic_operand (value
, VOIDmode
);
633 return value
== CONST0_RTX (GET_MODE (value
));
636 /* An integer vector, such that conversion to an integer yields a
637 value appropriate for an integer 'J' constraint. */
638 if (GET_CODE (value
) == CONST_VECTOR
639 && GET_MODE_CLASS (GET_MODE (value
)) == MODE_VECTOR_INT
)
641 value
= simplify_subreg (DImode
, value
, GET_MODE (value
), 0);
642 return ia64_const_ok_for_letter_p (INTVAL (value
), 'J');
647 /* A V2SF vector containing elements that satisfy 'G'. */
649 (GET_CODE (value
) == CONST_VECTOR
650 && GET_MODE (value
) == V2SFmode
651 && ia64_const_double_ok_for_letter_p (XVECEXP (value
, 0, 0), 'G')
652 && ia64_const_double_ok_for_letter_p (XVECEXP (value
, 0, 1), 'G'));
659 /* Return 1 if the operands of a move are ok. */
662 ia64_move_ok (rtx dst
, rtx src
)
664 /* If we're under init_recog_no_volatile, we'll not be able to use
665 memory_operand. So check the code directly and don't worry about
666 the validity of the underlying address, which should have been
667 checked elsewhere anyway. */
668 if (GET_CODE (dst
) != MEM
)
670 if (GET_CODE (src
) == MEM
)
672 if (register_operand (src
, VOIDmode
))
675 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
676 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
677 return src
== const0_rtx
;
679 return GET_CODE (src
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (src
);
683 addp4_optimize_ok (rtx op1
, rtx op2
)
685 return (basereg_operand (op1
, GET_MODE(op1
)) !=
686 basereg_operand (op2
, GET_MODE(op2
)));
689 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
690 Return the length of the field, or <= 0 on failure. */
693 ia64_depz_field_mask (rtx rop
, rtx rshift
)
695 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
696 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
698 /* Get rid of the zero bits we're shifting in. */
701 /* We must now have a solid block of 1's at bit 0. */
702 return exact_log2 (op
+ 1);
705 /* Return the TLS model to use for ADDR. */
707 static enum tls_model
708 tls_symbolic_operand_type (rtx addr
)
710 enum tls_model tls_kind
= 0;
712 if (GET_CODE (addr
) == CONST
)
714 if (GET_CODE (XEXP (addr
, 0)) == PLUS
715 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
716 tls_kind
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr
, 0), 0));
718 else if (GET_CODE (addr
) == SYMBOL_REF
)
719 tls_kind
= SYMBOL_REF_TLS_MODEL (addr
);
724 /* Return true if X is a constant that is valid for some immediate
725 field in an instruction. */
728 ia64_legitimate_constant_p (rtx x
)
730 switch (GET_CODE (x
))
737 if (GET_MODE (x
) == VOIDmode
)
739 return CONST_DOUBLE_OK_FOR_G (x
);
743 return tls_symbolic_operand_type (x
) == 0;
747 enum machine_mode mode
= GET_MODE (x
);
749 if (mode
== V2SFmode
)
750 return ia64_extra_constraint (x
, 'Y');
752 return (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
753 && GET_MODE_SIZE (mode
) <= 8);
761 /* Don't allow TLS addresses to get spilled to memory. */
764 ia64_cannot_force_const_mem (rtx x
)
766 return tls_symbolic_operand_type (x
) != 0;
769 /* Expand a symbolic constant load. */
772 ia64_expand_load_address (rtx dest
, rtx src
)
774 gcc_assert (GET_CODE (dest
) == REG
);
776 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
777 having to pointer-extend the value afterward. Other forms of address
778 computation below are also more natural to compute as 64-bit quantities.
779 If we've been given an SImode destination register, change it. */
780 if (GET_MODE (dest
) != Pmode
)
781 dest
= gen_rtx_REG_offset (dest
, Pmode
, REGNO (dest
), 0);
785 if (small_addr_symbolic_operand (src
, VOIDmode
))
789 emit_insn (gen_load_gprel64 (dest
, src
));
790 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
791 emit_insn (gen_load_fptr (dest
, src
));
792 else if (sdata_symbolic_operand (src
, VOIDmode
))
793 emit_insn (gen_load_gprel (dest
, src
));
796 HOST_WIDE_INT addend
= 0;
799 /* We did split constant offsets in ia64_expand_move, and we did try
800 to keep them split in move_operand, but we also allowed reload to
801 rematerialize arbitrary constants rather than spill the value to
802 the stack and reload it. So we have to be prepared here to split
804 if (GET_CODE (src
) == CONST
)
806 HOST_WIDE_INT hi
, lo
;
808 hi
= INTVAL (XEXP (XEXP (src
, 0), 1));
809 lo
= ((hi
& 0x3fff) ^ 0x2000) - 0x2000;
815 src
= plus_constant (XEXP (XEXP (src
, 0), 0), hi
);
819 tmp
= gen_rtx_HIGH (Pmode
, src
);
820 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
821 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
823 tmp
= gen_rtx_LO_SUM (Pmode
, dest
, src
);
824 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
828 tmp
= gen_rtx_PLUS (Pmode
, dest
, GEN_INT (addend
));
829 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
836 static GTY(()) rtx gen_tls_tga
;
838 gen_tls_get_addr (void)
841 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
845 static GTY(()) rtx thread_pointer_rtx
;
847 gen_thread_pointer (void)
849 if (!thread_pointer_rtx
)
850 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
851 return thread_pointer_rtx
;
855 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
,
856 HOST_WIDE_INT addend
)
858 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
859 rtx orig_op0
= op0
, orig_op1
= op1
;
860 HOST_WIDE_INT addend_lo
, addend_hi
;
862 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
863 addend_hi
= addend
- addend_lo
;
867 case TLS_MODEL_GLOBAL_DYNAMIC
:
870 tga_op1
= gen_reg_rtx (Pmode
);
871 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
873 tga_op2
= gen_reg_rtx (Pmode
);
874 emit_insn (gen_load_dtprel (tga_op2
, op1
));
876 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
877 LCT_CONST
, Pmode
, 2, tga_op1
,
878 Pmode
, tga_op2
, Pmode
);
880 insns
= get_insns ();
883 if (GET_MODE (op0
) != Pmode
)
885 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
888 case TLS_MODEL_LOCAL_DYNAMIC
:
889 /* ??? This isn't the completely proper way to do local-dynamic
890 If the call to __tls_get_addr is used only by a single symbol,
891 then we should (somehow) move the dtprel to the second arg
892 to avoid the extra add. */
895 tga_op1
= gen_reg_rtx (Pmode
);
896 emit_insn (gen_load_dtpmod (tga_op1
, op1
));
898 tga_op2
= const0_rtx
;
900 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
901 LCT_CONST
, Pmode
, 2, tga_op1
,
902 Pmode
, tga_op2
, Pmode
);
904 insns
= get_insns ();
907 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
909 tmp
= gen_reg_rtx (Pmode
);
910 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
912 if (!register_operand (op0
, Pmode
))
913 op0
= gen_reg_rtx (Pmode
);
916 emit_insn (gen_load_dtprel (op0
, op1
));
917 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
920 emit_insn (gen_add_dtprel (op0
, op1
, tmp
));
923 case TLS_MODEL_INITIAL_EXEC
:
924 op1
= plus_constant (op1
, addend_hi
);
927 tmp
= gen_reg_rtx (Pmode
);
928 emit_insn (gen_load_tprel (tmp
, op1
));
930 if (!register_operand (op0
, Pmode
))
931 op0
= gen_reg_rtx (Pmode
);
932 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
935 case TLS_MODEL_LOCAL_EXEC
:
936 if (!register_operand (op0
, Pmode
))
937 op0
= gen_reg_rtx (Pmode
);
943 emit_insn (gen_load_tprel (op0
, op1
));
944 emit_insn (gen_adddi3 (op0
, op0
, gen_thread_pointer ()));
947 emit_insn (gen_add_tprel (op0
, op1
, gen_thread_pointer ()));
955 op0
= expand_simple_binop (Pmode
, PLUS
, op0
, GEN_INT (addend
),
956 orig_op0
, 1, OPTAB_DIRECT
);
959 if (GET_MODE (orig_op0
) == Pmode
)
961 return gen_lowpart (GET_MODE (orig_op0
), op0
);
965 ia64_expand_move (rtx op0
, rtx op1
)
967 enum machine_mode mode
= GET_MODE (op0
);
969 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
970 op1
= force_reg (mode
, op1
);
972 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
974 HOST_WIDE_INT addend
= 0;
975 enum tls_model tls_kind
;
978 if (GET_CODE (op1
) == CONST
979 && GET_CODE (XEXP (op1
, 0)) == PLUS
980 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
)
982 addend
= INTVAL (XEXP (XEXP (op1
, 0), 1));
983 sym
= XEXP (XEXP (op1
, 0), 0);
986 tls_kind
= tls_symbolic_operand_type (sym
);
988 return ia64_expand_tls_address (tls_kind
, op0
, sym
, addend
);
990 if (any_offset_symbol_operand (sym
, mode
))
992 else if (aligned_offset_symbol_operand (sym
, mode
))
994 HOST_WIDE_INT addend_lo
, addend_hi
;
996 addend_lo
= ((addend
& 0x3fff) ^ 0x2000) - 0x2000;
997 addend_hi
= addend
- addend_lo
;
1001 op1
= plus_constant (sym
, addend_hi
);
1010 if (reload_completed
)
1012 /* We really should have taken care of this offset earlier. */
1013 gcc_assert (addend
== 0);
1014 if (ia64_expand_load_address (op0
, op1
))
1020 rtx subtarget
= no_new_pseudos
? op0
: gen_reg_rtx (mode
);
1022 emit_insn (gen_rtx_SET (VOIDmode
, subtarget
, op1
));
1024 op1
= expand_simple_binop (mode
, PLUS
, subtarget
,
1025 GEN_INT (addend
), op0
, 1, OPTAB_DIRECT
);
1034 /* Split a move from OP1 to OP0 conditional on COND. */
1037 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1039 rtx insn
, first
= get_last_insn ();
1041 emit_move_insn (op0
, op1
);
1043 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1045 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1049 /* Split a post-reload TImode or TFmode reference into two DImode
1050 components. This is made extra difficult by the fact that we do
1051 not get any scratch registers to work with, because reload cannot
1052 be prevented from giving us a scratch that overlaps the register
1053 pair involved. So instead, when addressing memory, we tweak the
1054 pointer register up and back down with POST_INCs. Or up and not
1055 back down when we can get away with it.
1057 REVERSED is true when the loads must be done in reversed order
1058 (high word first) for correctness. DEAD is true when the pointer
1059 dies with the second insn we generate and therefore the second
1060 address must not carry a postmodify.
1062 May return an insn which is to be emitted after the moves. */
1065 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1069 switch (GET_CODE (in
))
1072 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1073 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1078 /* Cannot occur reversed. */
1079 gcc_assert (!reversed
);
1081 if (GET_MODE (in
) != TFmode
)
1082 split_double (in
, &out
[0], &out
[1]);
1084 /* split_double does not understand how to split a TFmode
1085 quantity into a pair of DImode constants. */
1088 unsigned HOST_WIDE_INT p
[2];
1089 long l
[4]; /* TFmode is 128 bits */
1091 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1092 real_to_target (l
, &r
, TFmode
);
1094 if (FLOAT_WORDS_BIG_ENDIAN
)
1096 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1097 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1101 p
[0] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1102 p
[1] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1104 out
[0] = GEN_INT (p
[0]);
1105 out
[1] = GEN_INT (p
[1]);
1111 rtx base
= XEXP (in
, 0);
1114 switch (GET_CODE (base
))
1119 out
[0] = adjust_automodify_address
1120 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1121 out
[1] = adjust_automodify_address
1122 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1126 /* Reversal requires a pre-increment, which can only
1127 be done as a separate insn. */
1128 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1129 out
[0] = adjust_automodify_address
1130 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1131 out
[1] = adjust_address (in
, DImode
, 0);
1136 gcc_assert (!reversed
&& !dead
);
1138 /* Just do the increment in two steps. */
1139 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1140 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1144 gcc_assert (!reversed
&& !dead
);
1146 /* Add 8, subtract 24. */
1147 base
= XEXP (base
, 0);
1148 out
[0] = adjust_automodify_address
1149 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1150 out
[1] = adjust_automodify_address
1152 gen_rtx_POST_MODIFY (Pmode
, base
, plus_constant (base
, -24)),
1157 gcc_assert (!reversed
&& !dead
);
1159 /* Extract and adjust the modification. This case is
1160 trickier than the others, because we might have an
1161 index register, or we might have a combined offset that
1162 doesn't fit a signed 9-bit displacement field. We can
1163 assume the incoming expression is already legitimate. */
1164 offset
= XEXP (base
, 1);
1165 base
= XEXP (base
, 0);
1167 out
[0] = adjust_automodify_address
1168 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1170 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1172 /* Can't adjust the postmodify to match. Emit the
1173 original, then a separate addition insn. */
1174 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1175 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1179 gcc_assert (GET_CODE (XEXP (offset
, 1)) == CONST_INT
);
1180 if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1182 /* Again the postmodify cannot be made to match,
1183 but in this case it's more efficient to get rid
1184 of the postmodify entirely and fix up with an
1186 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1188 (base
, base
, GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1192 /* Combined offset still fits in the displacement field.
1193 (We cannot overflow it at the high end.) */
1194 out
[1] = adjust_automodify_address
1195 (in
, DImode
, gen_rtx_POST_MODIFY
1196 (Pmode
, base
, gen_rtx_PLUS
1198 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1217 /* Split a TImode or TFmode move instruction after reload.
1218 This is used by *movtf_internal and *movti_internal. */
1220 ia64_split_tmode_move (rtx operands
[])
1222 rtx in
[2], out
[2], insn
;
1225 bool reversed
= false;
1227 /* It is possible for reload to decide to overwrite a pointer with
1228 the value it points to. In that case we have to do the loads in
1229 the appropriate order so that the pointer is not destroyed too
1230 early. Also we must not generate a postmodify for that second
1231 load, or rws_access_regno will die. */
1232 if (GET_CODE (operands
[1]) == MEM
1233 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1235 rtx base
= XEXP (operands
[1], 0);
1236 while (GET_CODE (base
) != REG
)
1237 base
= XEXP (base
, 0);
1239 if (REGNO (base
) == REGNO (operands
[0]))
1243 /* Another reason to do the moves in reversed order is if the first
1244 element of the target register pair is also the second element of
1245 the source register pair. */
1246 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1247 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1250 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1251 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1253 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1254 if (GET_CODE (EXP) == MEM \
1255 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1256 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1257 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1258 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1259 XEXP (XEXP (EXP, 0), 0), \
1262 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1263 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1264 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1266 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1267 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1268 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1271 emit_insn (fixup
[0]);
1273 emit_insn (fixup
[1]);
1275 #undef MAYBE_ADD_REG_INC_NOTE
1278 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1279 through memory plus an extra GR scratch register. Except that you can
1280 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1281 SECONDARY_RELOAD_CLASS, but not both.
1283 We got into problems in the first place by allowing a construct like
1284 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1285 This solution attempts to prevent this situation from occurring. When
1286 we see something like the above, we spill the inner register to memory. */
1289 spill_xfmode_operand (rtx in
, int force
)
1291 if (GET_CODE (in
) == SUBREG
1292 && GET_MODE (SUBREG_REG (in
)) == TImode
1293 && GET_CODE (SUBREG_REG (in
)) == REG
)
1295 rtx memt
= assign_stack_temp (TImode
, 16, 0);
1296 emit_move_insn (memt
, SUBREG_REG (in
));
1297 return adjust_address (memt
, XFmode
, 0);
1299 else if (force
&& GET_CODE (in
) == REG
)
1301 rtx memx
= assign_stack_temp (XFmode
, 16, 0);
1302 emit_move_insn (memx
, in
);
1309 /* Emit comparison instruction if necessary, returning the expression
1310 that holds the compare result in the proper mode. */
1312 static GTY(()) rtx cmptf_libfunc
;
1315 ia64_expand_compare (enum rtx_code code
, enum machine_mode mode
)
1317 rtx op0
= ia64_compare_op0
, op1
= ia64_compare_op1
;
1320 /* If we have a BImode input, then we already have a compare result, and
1321 do not need to emit another comparison. */
1322 if (GET_MODE (op0
) == BImode
)
1324 gcc_assert ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
);
1327 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1328 magic number as its third argument, that indicates what to do.
1329 The return value is an integer to be compared against zero. */
1330 else if (GET_MODE (op0
) == TFmode
)
1333 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1339 enum rtx_code ncode
;
1342 gcc_assert (cmptf_libfunc
&& GET_MODE (op1
) == TFmode
);
1345 /* 1 = equal, 0 = not equal. Equality operators do
1346 not raise FP_INVALID when given an SNaN operand. */
1347 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1348 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1349 /* isunordered() from C99. */
1350 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1351 case ORDERED
: magic
= QCMP_UNORD
; ncode
= EQ
; break;
1352 /* Relational operators raise FP_INVALID when given
1354 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1355 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1356 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1357 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1358 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1359 Expanders for buneq etc. weuld have to be added to ia64.md
1360 for this to be useful. */
1361 default: gcc_unreachable ();
1366 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1367 op0
, TFmode
, op1
, TFmode
,
1368 GEN_INT (magic
), DImode
);
1369 cmp
= gen_reg_rtx (BImode
);
1370 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1371 gen_rtx_fmt_ee (ncode
, BImode
,
1374 insns
= get_insns ();
1377 emit_libcall_block (insns
, cmp
, cmp
,
1378 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
));
1383 cmp
= gen_reg_rtx (BImode
);
1384 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1385 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
)));
1389 return gen_rtx_fmt_ee (code
, mode
, cmp
, const0_rtx
);
1392 /* Generate an integral vector comparison. */
1395 ia64_expand_vecint_compare (enum rtx_code code
, enum machine_mode mode
,
1396 rtx dest
, rtx op0
, rtx op1
)
1398 bool negate
= false;
1433 rtx w0h
, w0l
, w1h
, w1l
, ch
, cl
;
1434 enum machine_mode wmode
;
1435 rtx (*unpack_l
) (rtx
, rtx
, rtx
);
1436 rtx (*unpack_h
) (rtx
, rtx
, rtx
);
1437 rtx (*pack
) (rtx
, rtx
, rtx
);
1439 /* We don't have native unsigned comparisons, but we can generate
1440 them better than generic code can. */
1442 gcc_assert (mode
!= V2SImode
);
1447 pack
= gen_pack2_sss
;
1448 unpack_l
= gen_unpack1_l
;
1449 unpack_h
= gen_unpack1_h
;
1454 pack
= gen_pack4_sss
;
1455 unpack_l
= gen_unpack2_l
;
1456 unpack_h
= gen_unpack2_h
;
1463 /* Unpack into wider vectors, zero extending the elements. */
1465 w0l
= gen_reg_rtx (wmode
);
1466 w0h
= gen_reg_rtx (wmode
);
1467 w1l
= gen_reg_rtx (wmode
);
1468 w1h
= gen_reg_rtx (wmode
);
1469 emit_insn (unpack_l (gen_lowpart (mode
, w0l
), op0
, CONST0_RTX (mode
)));
1470 emit_insn (unpack_h (gen_lowpart (mode
, w0h
), op0
, CONST0_RTX (mode
)));
1471 emit_insn (unpack_l (gen_lowpart (mode
, w1l
), op1
, CONST0_RTX (mode
)));
1472 emit_insn (unpack_h (gen_lowpart (mode
, w1h
), op1
, CONST0_RTX (mode
)));
1474 /* Compare in the wider mode. */
1476 cl
= gen_reg_rtx (wmode
);
1477 ch
= gen_reg_rtx (wmode
);
1478 code
= signed_condition (code
);
1479 ia64_expand_vecint_compare (code
, wmode
, cl
, w0l
, w1l
);
1480 negate
= ia64_expand_vecint_compare (code
, wmode
, ch
, w0h
, w1h
);
1482 /* Repack into a single narrower vector. */
1484 emit_insn (pack (dest
, cl
, ch
));
1492 x
= gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
1493 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
1499 ia64_expand_vcondu_v2si (enum rtx_code code
, rtx operands
[])
1501 rtx dl
, dh
, bl
, bh
, op1l
, op1h
, op2l
, op2h
, op4l
, op4h
, op5l
, op5h
, x
;
1503 /* In this case, we extract the two SImode quantities and generate
1504 normal comparisons for each of them. */
1506 op1l
= gen_lowpart (SImode
, operands
[1]);
1507 op2l
= gen_lowpart (SImode
, operands
[2]);
1508 op4l
= gen_lowpart (SImode
, operands
[4]);
1509 op5l
= gen_lowpart (SImode
, operands
[5]);
1511 op1h
= gen_reg_rtx (SImode
);
1512 op2h
= gen_reg_rtx (SImode
);
1513 op4h
= gen_reg_rtx (SImode
);
1514 op5h
= gen_reg_rtx (SImode
);
1516 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op1h
),
1517 gen_lowpart (DImode
, operands
[1]), GEN_INT (32)));
1518 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op2h
),
1519 gen_lowpart (DImode
, operands
[2]), GEN_INT (32)));
1520 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op4h
),
1521 gen_lowpart (DImode
, operands
[4]), GEN_INT (32)));
1522 emit_insn (gen_lshrdi3 (gen_lowpart (DImode
, op5h
),
1523 gen_lowpart (DImode
, operands
[5]), GEN_INT (32)));
1525 bl
= gen_reg_rtx (BImode
);
1526 x
= gen_rtx_fmt_ee (code
, BImode
, op4l
, op5l
);
1527 emit_insn (gen_rtx_SET (VOIDmode
, bl
, x
));
1529 bh
= gen_reg_rtx (BImode
);
1530 x
= gen_rtx_fmt_ee (code
, BImode
, op4h
, op5h
);
1531 emit_insn (gen_rtx_SET (VOIDmode
, bh
, x
));
1533 /* With the results of the comparisons, emit conditional moves. */
1535 dl
= gen_reg_rtx (SImode
);
1536 x
= gen_rtx_IF_THEN_ELSE (SImode
, bl
, op1l
, op2l
);
1537 emit_insn (gen_rtx_SET (VOIDmode
, dl
, x
));
1539 dh
= gen_reg_rtx (SImode
);
1540 x
= gen_rtx_IF_THEN_ELSE (SImode
, bh
, op1h
, op2h
);
1541 emit_insn (gen_rtx_SET (VOIDmode
, dh
, x
));
1543 /* Merge the two partial results back into a vector. */
1545 x
= gen_rtx_VEC_CONCAT (V2SImode
, dl
, dh
);
1546 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1549 /* Emit an integral vector conditional move. */
1552 ia64_expand_vecint_cmov (rtx operands
[])
1554 enum machine_mode mode
= GET_MODE (operands
[0]);
1555 enum rtx_code code
= GET_CODE (operands
[3]);
1559 /* Since we don't have unsigned V2SImode comparisons, it's more efficient
1560 to special-case them entirely. */
1561 if (mode
== V2SImode
1562 && (code
== GTU
|| code
== GEU
|| code
== LEU
|| code
== LTU
))
1564 ia64_expand_vcondu_v2si (code
, operands
);
1568 cmp
= gen_reg_rtx (mode
);
1569 negate
= ia64_expand_vecint_compare (code
, mode
, cmp
,
1570 operands
[4], operands
[5]);
1572 ot
= operands
[1+negate
];
1573 of
= operands
[2-negate
];
1575 if (ot
== CONST0_RTX (mode
))
1577 if (of
== CONST0_RTX (mode
))
1579 emit_move_insn (operands
[0], ot
);
1583 x
= gen_rtx_NOT (mode
, cmp
);
1584 x
= gen_rtx_AND (mode
, x
, of
);
1585 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1587 else if (of
== CONST0_RTX (mode
))
1589 x
= gen_rtx_AND (mode
, cmp
, ot
);
1590 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1596 t
= gen_reg_rtx (mode
);
1597 x
= gen_rtx_AND (mode
, cmp
, operands
[1+negate
]);
1598 emit_insn (gen_rtx_SET (VOIDmode
, t
, x
));
1600 f
= gen_reg_rtx (mode
);
1601 x
= gen_rtx_NOT (mode
, cmp
);
1602 x
= gen_rtx_AND (mode
, x
, operands
[2-negate
]);
1603 emit_insn (gen_rtx_SET (VOIDmode
, f
, x
));
1605 x
= gen_rtx_IOR (mode
, t
, f
);
1606 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], x
));
1610 /* Emit an integral vector min or max operation. Return true if all done. */
1613 ia64_expand_vecint_minmax (enum rtx_code code
, enum machine_mode mode
,
1618 /* These four combinations are supported directly. */
1619 if (mode
== V8QImode
&& (code
== UMIN
|| code
== UMAX
))
1621 if (mode
== V4HImode
&& (code
== SMIN
|| code
== SMAX
))
1624 /* Everything else implemented via vector comparisons. */
1625 xops
[0] = operands
[0];
1626 xops
[4] = xops
[1] = operands
[1];
1627 xops
[5] = xops
[2] = operands
[2];
1646 xops
[3] = gen_rtx_fmt_ee (code
, VOIDmode
, operands
[1], operands
[2]);
1648 ia64_expand_vecint_cmov (xops
);
1652 /* Emit the appropriate sequence for a call. */
1655 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
1660 addr
= XEXP (addr
, 0);
1661 addr
= convert_memory_address (DImode
, addr
);
1662 b0
= gen_rtx_REG (DImode
, R_BR (0));
1664 /* ??? Should do this for functions known to bind local too. */
1665 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
1668 insn
= gen_sibcall_nogp (addr
);
1670 insn
= gen_call_nogp (addr
, b0
);
1672 insn
= gen_call_value_nogp (retval
, addr
, b0
);
1673 insn
= emit_call_insn (insn
);
1678 insn
= gen_sibcall_gp (addr
);
1680 insn
= gen_call_gp (addr
, b0
);
1682 insn
= gen_call_value_gp (retval
, addr
, b0
);
1683 insn
= emit_call_insn (insn
);
1685 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
1689 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
1693 ia64_reload_gp (void)
1697 if (current_frame_info
.reg_save_gp
)
1698 tmp
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_gp
);
1701 HOST_WIDE_INT offset
;
1703 offset
= (current_frame_info
.spill_cfa_off
1704 + current_frame_info
.spill_size
);
1705 if (frame_pointer_needed
)
1707 tmp
= hard_frame_pointer_rtx
;
1712 tmp
= stack_pointer_rtx
;
1713 offset
= current_frame_info
.total_size
- offset
;
1716 if (CONST_OK_FOR_I (offset
))
1717 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1718 tmp
, GEN_INT (offset
)));
1721 emit_move_insn (pic_offset_table_rtx
, GEN_INT (offset
));
1722 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1723 pic_offset_table_rtx
, tmp
));
1726 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
1729 emit_move_insn (pic_offset_table_rtx
, tmp
);
1733 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
1734 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
1737 bool is_desc
= false;
1739 /* If we find we're calling through a register, then we're actually
1740 calling through a descriptor, so load up the values. */
1741 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
1746 /* ??? We are currently constrained to *not* use peep2, because
1747 we can legitimately change the global lifetime of the GP
1748 (in the form of killing where previously live). This is
1749 because a call through a descriptor doesn't use the previous
1750 value of the GP, while a direct call does, and we do not
1751 commit to either form until the split here.
1753 That said, this means that we lack precise life info for
1754 whether ADDR is dead after this call. This is not terribly
1755 important, since we can fix things up essentially for free
1756 with the POST_DEC below, but it's nice to not use it when we
1757 can immediately tell it's not necessary. */
1758 addr_dead_p
= ((noreturn_p
|| sibcall_p
1759 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
1761 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
1763 /* Load the code address into scratch_b. */
1764 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
1765 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1766 emit_move_insn (scratch_r
, tmp
);
1767 emit_move_insn (scratch_b
, scratch_r
);
1769 /* Load the GP address. If ADDR is not dead here, then we must
1770 revert the change made above via the POST_INCREMENT. */
1772 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
1775 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1776 emit_move_insn (pic_offset_table_rtx
, tmp
);
1783 insn
= gen_sibcall_nogp (addr
);
1785 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
1787 insn
= gen_call_nogp (addr
, retaddr
);
1788 emit_call_insn (insn
);
1790 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
1794 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
1796 This differs from the generic code in that we know about the zero-extending
1797 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
1798 also know that ld.acq+cmpxchg.rel equals a full barrier.
1800 The loop we want to generate looks like
1805 new_reg = cmp_reg op val;
1806 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
1807 if (cmp_reg != old_reg)
1810 Note that we only do the plain load from memory once. Subsequent
1811 iterations use the value loaded by the compare-and-swap pattern. */
1814 ia64_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
1815 rtx old_dst
, rtx new_dst
)
1817 enum machine_mode mode
= GET_MODE (mem
);
1818 rtx old_reg
, new_reg
, cmp_reg
, ar_ccv
, label
;
1819 enum insn_code icode
;
1821 /* Special case for using fetchadd. */
1822 if ((mode
== SImode
|| mode
== DImode
) && fetchadd_operand (val
, mode
))
1825 old_dst
= gen_reg_rtx (mode
);
1827 emit_insn (gen_memory_barrier ());
1830 icode
= CODE_FOR_fetchadd_acq_si
;
1832 icode
= CODE_FOR_fetchadd_acq_di
;
1833 emit_insn (GEN_FCN (icode
) (old_dst
, mem
, val
));
1837 new_reg
= expand_simple_binop (mode
, PLUS
, old_dst
, val
, new_dst
,
1839 if (new_reg
!= new_dst
)
1840 emit_move_insn (new_dst
, new_reg
);
1845 /* Because of the volatile mem read, we get an ld.acq, which is the
1846 front half of the full barrier. The end half is the cmpxchg.rel. */
1847 gcc_assert (MEM_VOLATILE_P (mem
));
1849 old_reg
= gen_reg_rtx (DImode
);
1850 cmp_reg
= gen_reg_rtx (DImode
);
1851 label
= gen_label_rtx ();
1855 val
= simplify_gen_subreg (DImode
, val
, mode
, 0);
1856 emit_insn (gen_extend_insn (cmp_reg
, mem
, DImode
, mode
, 1));
1859 emit_move_insn (cmp_reg
, mem
);
1863 ar_ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
1864 emit_move_insn (old_reg
, cmp_reg
);
1865 emit_move_insn (ar_ccv
, cmp_reg
);
1868 emit_move_insn (old_dst
, gen_lowpart (mode
, cmp_reg
));
1873 new_reg
= expand_simple_unop (DImode
, NOT
, new_reg
, NULL_RTX
, true);
1876 new_reg
= expand_simple_binop (DImode
, code
, new_reg
, val
, NULL_RTX
,
1877 true, OPTAB_DIRECT
);
1880 new_reg
= gen_lowpart (mode
, new_reg
);
1882 emit_move_insn (new_dst
, new_reg
);
1886 case QImode
: icode
= CODE_FOR_cmpxchg_rel_qi
; break;
1887 case HImode
: icode
= CODE_FOR_cmpxchg_rel_hi
; break;
1888 case SImode
: icode
= CODE_FOR_cmpxchg_rel_si
; break;
1889 case DImode
: icode
= CODE_FOR_cmpxchg_rel_di
; break;
1894 emit_insn (GEN_FCN (icode
) (cmp_reg
, mem
, ar_ccv
, new_reg
));
1896 emit_cmp_and_jump_insns (cmp_reg
, old_reg
, EQ
, NULL
, DImode
, true, label
);
1899 /* Begin the assembly file. */
1902 ia64_file_start (void)
1904 /* Variable tracking should be run after all optimizations which change order
1905 of insns. It also needs a valid CFG. This can't be done in
1906 ia64_override_options, because flag_var_tracking is finalized after
1908 ia64_flag_var_tracking
= flag_var_tracking
;
1909 flag_var_tracking
= 0;
1911 default_file_start ();
1912 emit_safe_across_calls ();
1916 emit_safe_across_calls (void)
1918 unsigned int rs
, re
;
1925 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
1929 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
1933 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
1937 fputc (',', asm_out_file
);
1939 fprintf (asm_out_file
, "p%u", rs
);
1941 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
1945 fputc ('\n', asm_out_file
);
1948 /* Helper function for ia64_compute_frame_size: find an appropriate general
1949 register to spill some special register to. SPECIAL_SPILL_MASK contains
1950 bits in GR0 to GR31 that have already been allocated by this routine.
1951 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1954 find_gr_spill (int try_locals
)
1958 /* If this is a leaf function, first try an otherwise unused
1959 call-clobbered register. */
1960 if (current_function_is_leaf
)
1962 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1963 if (! regs_ever_live
[regno
]
1964 && call_used_regs
[regno
]
1965 && ! fixed_regs
[regno
]
1966 && ! global_regs
[regno
]
1967 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1969 current_frame_info
.gr_used_mask
|= 1 << regno
;
1976 regno
= current_frame_info
.n_local_regs
;
1977 /* If there is a frame pointer, then we can't use loc79, because
1978 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1979 reg_name switching code in ia64_expand_prologue. */
1980 if (regno
< (80 - frame_pointer_needed
))
1982 current_frame_info
.n_local_regs
= regno
+ 1;
1983 return LOC_REG (0) + regno
;
1987 /* Failed to find a general register to spill to. Must use stack. */
1991 /* In order to make for nice schedules, we try to allocate every temporary
1992 to a different register. We must of course stay away from call-saved,
1993 fixed, and global registers. We must also stay away from registers
1994 allocated in current_frame_info.gr_used_mask, since those include regs
1995 used all through the prologue.
1997 Any register allocated here must be used immediately. The idea is to
1998 aid scheduling, not to solve data flow problems. */
2000 static int last_scratch_gr_reg
;
2003 next_scratch_gr_reg (void)
2007 for (i
= 0; i
< 32; ++i
)
2009 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
2010 if (call_used_regs
[regno
]
2011 && ! fixed_regs
[regno
]
2012 && ! global_regs
[regno
]
2013 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
2015 last_scratch_gr_reg
= regno
;
2020 /* There must be _something_ available. */
2024 /* Helper function for ia64_compute_frame_size, called through
2025 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2028 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2030 unsigned int regno
= REGNO (reg
);
2033 unsigned int i
, n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2034 for (i
= 0; i
< n
; ++i
)
2035 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2039 /* Returns the number of bytes offset between the frame pointer and the stack
2040 pointer for the current function. SIZE is the number of bytes of space
2041 needed for local variables. */
2044 ia64_compute_frame_size (HOST_WIDE_INT size
)
2046 HOST_WIDE_INT total_size
;
2047 HOST_WIDE_INT spill_size
= 0;
2048 HOST_WIDE_INT extra_spill_size
= 0;
2049 HOST_WIDE_INT pretend_args_size
;
2052 int spilled_gr_p
= 0;
2053 int spilled_fr_p
= 0;
2057 if (current_frame_info
.initialized
)
2060 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2061 CLEAR_HARD_REG_SET (mask
);
2063 /* Don't allocate scratches to the return register. */
2064 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2066 /* Don't allocate scratches to the EH scratch registers. */
2067 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2068 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2069 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2070 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2072 /* Find the size of the register stack frame. We have only 80 local
2073 registers, because we reserve 8 for the inputs and 8 for the
2076 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2077 since we'll be adjusting that down later. */
2078 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2079 for (; regno
>= LOC_REG (0); regno
--)
2080 if (regs_ever_live
[regno
])
2082 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2084 /* For functions marked with the syscall_linkage attribute, we must mark
2085 all eight input registers as in use, so that locals aren't visible to
2088 if (cfun
->machine
->n_varargs
> 0
2089 || lookup_attribute ("syscall_linkage",
2090 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2091 current_frame_info
.n_input_regs
= 8;
2094 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2095 if (regs_ever_live
[regno
])
2097 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2100 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2101 if (regs_ever_live
[regno
])
2103 i
= regno
- OUT_REG (0) + 1;
2105 #ifndef PROFILE_HOOK
2106 /* When -p profiling, we need one output register for the mcount argument.
2107 Likewise for -a profiling for the bb_init_func argument. For -ax
2108 profiling, we need two output registers for the two bb_init_trace_func
2110 if (current_function_profile
)
2113 current_frame_info
.n_output_regs
= i
;
2115 /* ??? No rotating register support yet. */
2116 current_frame_info
.n_rotate_regs
= 0;
2118 /* Discover which registers need spilling, and how much room that
2119 will take. Begin with floating point and general registers,
2120 which will always wind up on the stack. */
2122 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2123 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2125 SET_HARD_REG_BIT (mask
, regno
);
2131 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2132 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2134 SET_HARD_REG_BIT (mask
, regno
);
2140 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2141 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2143 SET_HARD_REG_BIT (mask
, regno
);
2148 /* Now come all special registers that might get saved in other
2149 general registers. */
2151 if (frame_pointer_needed
)
2153 current_frame_info
.reg_fp
= find_gr_spill (1);
2154 /* If we did not get a register, then we take LOC79. This is guaranteed
2155 to be free, even if regs_ever_live is already set, because this is
2156 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2157 as we don't count loc79 above. */
2158 if (current_frame_info
.reg_fp
== 0)
2160 current_frame_info
.reg_fp
= LOC_REG (79);
2161 current_frame_info
.n_local_regs
++;
2165 if (! current_function_is_leaf
)
2167 /* Emit a save of BR0 if we call other functions. Do this even
2168 if this function doesn't return, as EH depends on this to be
2169 able to unwind the stack. */
2170 SET_HARD_REG_BIT (mask
, BR_REG (0));
2172 current_frame_info
.reg_save_b0
= find_gr_spill (1);
2173 if (current_frame_info
.reg_save_b0
== 0)
2179 /* Similarly for ar.pfs. */
2180 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2181 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
2182 if (current_frame_info
.reg_save_ar_pfs
== 0)
2184 extra_spill_size
+= 8;
2188 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2189 registers are clobbered, so we fall back to the stack. */
2190 current_frame_info
.reg_save_gp
2191 = (current_function_calls_setjmp
? 0 : find_gr_spill (1));
2192 if (current_frame_info
.reg_save_gp
== 0)
2194 SET_HARD_REG_BIT (mask
, GR_REG (1));
2201 if (regs_ever_live
[BR_REG (0)] && ! call_used_regs
[BR_REG (0)])
2203 SET_HARD_REG_BIT (mask
, BR_REG (0));
2208 if (regs_ever_live
[AR_PFS_REGNUM
])
2210 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2211 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
2212 if (current_frame_info
.reg_save_ar_pfs
== 0)
2214 extra_spill_size
+= 8;
2220 /* Unwind descriptor hackery: things are most efficient if we allocate
2221 consecutive GR save registers for RP, PFS, FP in that order. However,
2222 it is absolutely critical that FP get the only hard register that's
2223 guaranteed to be free, so we allocated it first. If all three did
2224 happen to be allocated hard regs, and are consecutive, rearrange them
2225 into the preferred order now. */
2226 if (current_frame_info
.reg_fp
!= 0
2227 && current_frame_info
.reg_save_b0
== current_frame_info
.reg_fp
+ 1
2228 && current_frame_info
.reg_save_ar_pfs
== current_frame_info
.reg_fp
+ 2)
2230 current_frame_info
.reg_save_b0
= current_frame_info
.reg_fp
;
2231 current_frame_info
.reg_save_ar_pfs
= current_frame_info
.reg_fp
+ 1;
2232 current_frame_info
.reg_fp
= current_frame_info
.reg_fp
+ 2;
2235 /* See if we need to store the predicate register block. */
2236 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2237 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2239 if (regno
<= PR_REG (63))
2241 SET_HARD_REG_BIT (mask
, PR_REG (0));
2242 current_frame_info
.reg_save_pr
= find_gr_spill (1);
2243 if (current_frame_info
.reg_save_pr
== 0)
2245 extra_spill_size
+= 8;
2249 /* ??? Mark them all as used so that register renaming and such
2250 are free to use them. */
2251 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2252 regs_ever_live
[regno
] = 1;
2255 /* If we're forced to use st8.spill, we're forced to save and restore
2256 ar.unat as well. The check for existing liveness allows inline asm
2257 to touch ar.unat. */
2258 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2259 || regs_ever_live
[AR_UNAT_REGNUM
])
2261 regs_ever_live
[AR_UNAT_REGNUM
] = 1;
2262 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2263 current_frame_info
.reg_save_ar_unat
= find_gr_spill (spill_size
== 0);
2264 if (current_frame_info
.reg_save_ar_unat
== 0)
2266 extra_spill_size
+= 8;
2271 if (regs_ever_live
[AR_LC_REGNUM
])
2273 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2274 current_frame_info
.reg_save_ar_lc
= find_gr_spill (spill_size
== 0);
2275 if (current_frame_info
.reg_save_ar_lc
== 0)
2277 extra_spill_size
+= 8;
2282 /* If we have an odd number of words of pretend arguments written to
2283 the stack, then the FR save area will be unaligned. We round the
2284 size of this area up to keep things 16 byte aligned. */
2286 pretend_args_size
= IA64_STACK_ALIGN (current_function_pretend_args_size
);
2288 pretend_args_size
= current_function_pretend_args_size
;
2290 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2291 + current_function_outgoing_args_size
);
2292 total_size
= IA64_STACK_ALIGN (total_size
);
2294 /* We always use the 16-byte scratch area provided by the caller, but
2295 if we are a leaf function, there's no one to which we need to provide
2297 if (current_function_is_leaf
)
2298 total_size
= MAX (0, total_size
- 16);
2300 current_frame_info
.total_size
= total_size
;
2301 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2302 current_frame_info
.spill_size
= spill_size
;
2303 current_frame_info
.extra_spill_size
= extra_spill_size
;
2304 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2305 current_frame_info
.n_spilled
= n_spilled
;
2306 current_frame_info
.initialized
= reload_completed
;
2309 /* Compute the initial difference between the specified pair of registers. */
2312 ia64_initial_elimination_offset (int from
, int to
)
2314 HOST_WIDE_INT offset
;
2316 ia64_compute_frame_size (get_frame_size ());
2319 case FRAME_POINTER_REGNUM
:
2322 case HARD_FRAME_POINTER_REGNUM
:
2323 if (current_function_is_leaf
)
2324 offset
= -current_frame_info
.total_size
;
2326 offset
= -(current_frame_info
.total_size
2327 - current_function_outgoing_args_size
- 16);
2330 case STACK_POINTER_REGNUM
:
2331 if (current_function_is_leaf
)
2334 offset
= 16 + current_function_outgoing_args_size
;
2342 case ARG_POINTER_REGNUM
:
2343 /* Arguments start above the 16 byte save area, unless stdarg
2344 in which case we store through the 16 byte save area. */
2347 case HARD_FRAME_POINTER_REGNUM
:
2348 offset
= 16 - current_function_pretend_args_size
;
2351 case STACK_POINTER_REGNUM
:
2352 offset
= (current_frame_info
.total_size
2353 + 16 - current_function_pretend_args_size
);
2368 /* If there are more than a trivial number of register spills, we use
2369 two interleaved iterators so that we can get two memory references
2372 In order to simplify things in the prologue and epilogue expanders,
2373 we use helper functions to fix up the memory references after the
2374 fact with the appropriate offsets to a POST_MODIFY memory mode.
2375 The following data structure tracks the state of the two iterators
2376 while insns are being emitted. */
2378 struct spill_fill_data
2380 rtx init_after
; /* point at which to emit initializations */
2381 rtx init_reg
[2]; /* initial base register */
2382 rtx iter_reg
[2]; /* the iterator registers */
2383 rtx
*prev_addr
[2]; /* address of last memory use */
2384 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2385 HOST_WIDE_INT prev_off
[2]; /* last offset */
2386 int n_iter
; /* number of iterators in use */
2387 int next_iter
; /* next iterator to use */
2388 unsigned int save_gr_used_mask
;
2391 static struct spill_fill_data spill_fill_data
;
2394 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2398 spill_fill_data
.init_after
= get_last_insn ();
2399 spill_fill_data
.init_reg
[0] = init_reg
;
2400 spill_fill_data
.init_reg
[1] = init_reg
;
2401 spill_fill_data
.prev_addr
[0] = NULL
;
2402 spill_fill_data
.prev_addr
[1] = NULL
;
2403 spill_fill_data
.prev_insn
[0] = NULL
;
2404 spill_fill_data
.prev_insn
[1] = NULL
;
2405 spill_fill_data
.prev_off
[0] = cfa_off
;
2406 spill_fill_data
.prev_off
[1] = cfa_off
;
2407 spill_fill_data
.next_iter
= 0;
2408 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2410 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2411 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2413 int regno
= next_scratch_gr_reg ();
2414 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2415 current_frame_info
.gr_used_mask
|= 1 << regno
;
2420 finish_spill_pointers (void)
2422 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2426 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
2428 int iter
= spill_fill_data
.next_iter
;
2429 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2430 rtx disp_rtx
= GEN_INT (disp
);
2433 if (spill_fill_data
.prev_addr
[iter
])
2435 if (CONST_OK_FOR_N (disp
))
2437 *spill_fill_data
.prev_addr
[iter
]
2438 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2439 gen_rtx_PLUS (DImode
,
2440 spill_fill_data
.iter_reg
[iter
],
2442 REG_NOTES (spill_fill_data
.prev_insn
[iter
])
2443 = gen_rtx_EXPR_LIST (REG_INC
, spill_fill_data
.iter_reg
[iter
],
2444 REG_NOTES (spill_fill_data
.prev_insn
[iter
]));
2448 /* ??? Could use register post_modify for loads. */
2449 if (! CONST_OK_FOR_I (disp
))
2451 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2452 emit_move_insn (tmp
, disp_rtx
);
2455 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2456 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2459 /* Micro-optimization: if we've created a frame pointer, it's at
2460 CFA 0, which may allow the real iterator to be initialized lower,
2461 slightly increasing parallelism. Also, if there are few saves
2462 it may eliminate the iterator entirely. */
2464 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2465 && frame_pointer_needed
)
2467 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2468 set_mem_alias_set (mem
, get_varargs_alias_set ());
2476 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2477 spill_fill_data
.init_reg
[iter
]);
2482 if (! CONST_OK_FOR_I (disp
))
2484 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2485 emit_move_insn (tmp
, disp_rtx
);
2489 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2490 spill_fill_data
.init_reg
[iter
],
2497 /* Careful for being the first insn in a sequence. */
2498 if (spill_fill_data
.init_after
)
2499 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2502 rtx first
= get_insns ();
2504 insn
= emit_insn_before (seq
, first
);
2506 insn
= emit_insn (seq
);
2508 spill_fill_data
.init_after
= insn
;
2510 /* If DISP is 0, we may or may not have a further adjustment
2511 afterward. If we do, then the load/store insn may be modified
2512 to be a post-modify. If we don't, then this copy may be
2513 eliminated by copyprop_hardreg_forward, which makes this
2514 insn garbage, which runs afoul of the sanity check in
2515 propagate_one_insn. So mark this insn as legal to delete. */
2517 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
2521 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
2523 /* ??? Not all of the spills are for varargs, but some of them are.
2524 The rest of the spills belong in an alias set of their own. But
2525 it doesn't actually hurt to include them here. */
2526 set_mem_alias_set (mem
, get_varargs_alias_set ());
2528 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
2529 spill_fill_data
.prev_off
[iter
] = cfa_off
;
2531 if (++iter
>= spill_fill_data
.n_iter
)
2533 spill_fill_data
.next_iter
= iter
;
2539 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
2542 int iter
= spill_fill_data
.next_iter
;
2545 mem
= spill_restore_mem (reg
, cfa_off
);
2546 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
2547 spill_fill_data
.prev_insn
[iter
] = insn
;
2554 RTX_FRAME_RELATED_P (insn
) = 1;
2556 /* Don't even pretend that the unwind code can intuit its way
2557 through a pair of interleaved post_modify iterators. Just
2558 provide the correct answer. */
2560 if (frame_pointer_needed
)
2562 base
= hard_frame_pointer_rtx
;
2567 base
= stack_pointer_rtx
;
2568 off
= current_frame_info
.total_size
- cfa_off
;
2572 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2573 gen_rtx_SET (VOIDmode
,
2574 gen_rtx_MEM (GET_MODE (reg
),
2575 plus_constant (base
, off
)),
2582 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
2584 int iter
= spill_fill_data
.next_iter
;
2587 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
2588 GEN_INT (cfa_off
)));
2589 spill_fill_data
.prev_insn
[iter
] = insn
;
2592 /* Wrapper functions that discards the CONST_INT spill offset. These
2593 exist so that we can give gr_spill/gr_fill the offset they need and
2594 use a consistent function interface. */
2597 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2599 return gen_movdi (dest
, src
);
2603 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2605 return gen_fr_spill (dest
, src
);
2609 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2611 return gen_fr_restore (dest
, src
);
2614 /* Called after register allocation to add any instructions needed for the
2615 prologue. Using a prologue insn is favored compared to putting all of the
2616 instructions in output_function_prologue(), since it allows the scheduler
2617 to intermix instructions with the saves of the caller saved registers. In
2618 some cases, it might be necessary to emit a barrier instruction as the last
2619 insn to prevent such scheduling.
2621 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2622 so that the debug info generation code can handle them properly.
2624 The register save area is layed out like so:
2626 [ varargs spill area ]
2627 [ fr register spill area ]
2628 [ br register spill area ]
2629 [ ar register spill area ]
2630 [ pr register spill area ]
2631 [ gr register spill area ] */
2633 /* ??? Get inefficient code when the frame size is larger than can fit in an
2634 adds instruction. */
2637 ia64_expand_prologue (void)
2639 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
2640 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
2643 ia64_compute_frame_size (get_frame_size ());
2644 last_scratch_gr_reg
= 15;
2646 /* If there is no epilogue, then we don't need some prologue insns.
2647 We need to avoid emitting the dead prologue insns, because flow
2648 will complain about them. */
2654 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
2655 if ((e
->flags
& EDGE_FAKE
) == 0
2656 && (e
->flags
& EDGE_FALLTHRU
) != 0)
2658 epilogue_p
= (e
!= NULL
);
2663 /* Set the local, input, and output register names. We need to do this
2664 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2665 half. If we use in/loc/out register names, then we get assembler errors
2666 in crtn.S because there is no alloc insn or regstk directive in there. */
2667 if (! TARGET_REG_NAMES
)
2669 int inputs
= current_frame_info
.n_input_regs
;
2670 int locals
= current_frame_info
.n_local_regs
;
2671 int outputs
= current_frame_info
.n_output_regs
;
2673 for (i
= 0; i
< inputs
; i
++)
2674 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
2675 for (i
= 0; i
< locals
; i
++)
2676 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
2677 for (i
= 0; i
< outputs
; i
++)
2678 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
2681 /* Set the frame pointer register name. The regnum is logically loc79,
2682 but of course we'll not have allocated that many locals. Rather than
2683 worrying about renumbering the existing rtxs, we adjust the name. */
2684 /* ??? This code means that we can never use one local register when
2685 there is a frame pointer. loc79 gets wasted in this case, as it is
2686 renamed to a register that will never be used. See also the try_locals
2687 code in find_gr_spill. */
2688 if (current_frame_info
.reg_fp
)
2690 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
2691 reg_names
[HARD_FRAME_POINTER_REGNUM
]
2692 = reg_names
[current_frame_info
.reg_fp
];
2693 reg_names
[current_frame_info
.reg_fp
] = tmp
;
2696 /* We don't need an alloc instruction if we've used no outputs or locals. */
2697 if (current_frame_info
.n_local_regs
== 0
2698 && current_frame_info
.n_output_regs
== 0
2699 && current_frame_info
.n_input_regs
<= current_function_args_info
.int_regs
2700 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2702 /* If there is no alloc, but there are input registers used, then we
2703 need a .regstk directive. */
2704 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
2705 ar_pfs_save_reg
= NULL_RTX
;
2709 current_frame_info
.need_regstk
= 0;
2711 if (current_frame_info
.reg_save_ar_pfs
)
2712 regno
= current_frame_info
.reg_save_ar_pfs
;
2714 regno
= next_scratch_gr_reg ();
2715 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
2717 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
2718 GEN_INT (current_frame_info
.n_input_regs
),
2719 GEN_INT (current_frame_info
.n_local_regs
),
2720 GEN_INT (current_frame_info
.n_output_regs
),
2721 GEN_INT (current_frame_info
.n_rotate_regs
)));
2722 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_pfs
!= 0);
2725 /* Set up frame pointer, stack pointer, and spill iterators. */
2727 n_varargs
= cfun
->machine
->n_varargs
;
2728 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
2729 stack_pointer_rtx
, 0);
2731 if (frame_pointer_needed
)
2733 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2734 RTX_FRAME_RELATED_P (insn
) = 1;
2737 if (current_frame_info
.total_size
!= 0)
2739 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
2742 if (CONST_OK_FOR_I (- current_frame_info
.total_size
))
2743 offset
= frame_size_rtx
;
2746 regno
= next_scratch_gr_reg ();
2747 offset
= gen_rtx_REG (DImode
, regno
);
2748 emit_move_insn (offset
, frame_size_rtx
);
2751 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
2752 stack_pointer_rtx
, offset
));
2754 if (! frame_pointer_needed
)
2756 RTX_FRAME_RELATED_P (insn
) = 1;
2757 if (GET_CODE (offset
) != CONST_INT
)
2760 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2761 gen_rtx_SET (VOIDmode
,
2763 gen_rtx_PLUS (DImode
,
2770 /* ??? At this point we must generate a magic insn that appears to
2771 modify the stack pointer, the frame pointer, and all spill
2772 iterators. This would allow the most scheduling freedom. For
2773 now, just hard stop. */
2774 emit_insn (gen_blockage ());
2777 /* Must copy out ar.unat before doing any integer spills. */
2778 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2780 if (current_frame_info
.reg_save_ar_unat
)
2782 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2785 alt_regno
= next_scratch_gr_reg ();
2786 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2787 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2790 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2791 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
2792 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_unat
!= 0);
2794 /* Even if we're not going to generate an epilogue, we still
2795 need to save the register so that EH works. */
2796 if (! epilogue_p
&& current_frame_info
.reg_save_ar_unat
)
2797 emit_insn (gen_prologue_use (ar_unat_save_reg
));
2800 ar_unat_save_reg
= NULL_RTX
;
2802 /* Spill all varargs registers. Do this before spilling any GR registers,
2803 since we want the UNAT bits for the GR registers to override the UNAT
2804 bits from varargs, which we don't care about. */
2807 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
2809 reg
= gen_rtx_REG (DImode
, regno
);
2810 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
2813 /* Locate the bottom of the register save area. */
2814 cfa_off
= (current_frame_info
.spill_cfa_off
2815 + current_frame_info
.spill_size
2816 + current_frame_info
.extra_spill_size
);
2818 /* Save the predicate register block either in a register or in memory. */
2819 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2821 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2822 if (current_frame_info
.reg_save_pr
!= 0)
2824 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2825 insn
= emit_move_insn (alt_reg
, reg
);
2827 /* ??? Denote pr spill/fill by a DImode move that modifies all
2828 64 hard registers. */
2829 RTX_FRAME_RELATED_P (insn
) = 1;
2831 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2832 gen_rtx_SET (VOIDmode
, alt_reg
, reg
),
2835 /* Even if we're not going to generate an epilogue, we still
2836 need to save the register so that EH works. */
2838 emit_insn (gen_prologue_use (alt_reg
));
2842 alt_regno
= next_scratch_gr_reg ();
2843 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2844 insn
= emit_move_insn (alt_reg
, reg
);
2845 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2850 /* Handle AR regs in numerical order. All of them get special handling. */
2851 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
2852 && current_frame_info
.reg_save_ar_unat
== 0)
2854 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2855 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
2859 /* The alloc insn already copied ar.pfs into a general register. The
2860 only thing we have to do now is copy that register to a stack slot
2861 if we'd not allocated a local register for the job. */
2862 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
2863 && current_frame_info
.reg_save_ar_pfs
== 0)
2865 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2866 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
2870 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2872 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2873 if (current_frame_info
.reg_save_ar_lc
!= 0)
2875 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2876 insn
= emit_move_insn (alt_reg
, reg
);
2877 RTX_FRAME_RELATED_P (insn
) = 1;
2879 /* Even if we're not going to generate an epilogue, we still
2880 need to save the register so that EH works. */
2882 emit_insn (gen_prologue_use (alt_reg
));
2886 alt_regno
= next_scratch_gr_reg ();
2887 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2888 emit_move_insn (alt_reg
, reg
);
2889 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2894 if (current_frame_info
.reg_save_gp
)
2896 insn
= emit_move_insn (gen_rtx_REG (DImode
,
2897 current_frame_info
.reg_save_gp
),
2898 pic_offset_table_rtx
);
2899 /* We don't know for sure yet if this is actually needed, since
2900 we've not split the PIC call patterns. If all of the calls
2901 are indirect, and not followed by any uses of the gp, then
2902 this save is dead. Allow it to go away. */
2904 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, REG_NOTES (insn
));
2907 /* We should now be at the base of the gr/br/fr spill area. */
2908 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
2909 + current_frame_info
.spill_size
));
2911 /* Spill all general registers. */
2912 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
2913 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2915 reg
= gen_rtx_REG (DImode
, regno
);
2916 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
2920 /* Handle BR0 specially -- it may be getting stored permanently in
2921 some GR register. */
2922 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2924 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2925 if (current_frame_info
.reg_save_b0
!= 0)
2927 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2928 insn
= emit_move_insn (alt_reg
, reg
);
2929 RTX_FRAME_RELATED_P (insn
) = 1;
2931 /* Even if we're not going to generate an epilogue, we still
2932 need to save the register so that EH works. */
2934 emit_insn (gen_prologue_use (alt_reg
));
2938 alt_regno
= next_scratch_gr_reg ();
2939 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2940 emit_move_insn (alt_reg
, reg
);
2941 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2946 /* Spill the rest of the BR registers. */
2947 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2948 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2950 alt_regno
= next_scratch_gr_reg ();
2951 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2952 reg
= gen_rtx_REG (DImode
, regno
);
2953 emit_move_insn (alt_reg
, reg
);
2954 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2958 /* Align the frame and spill all FR registers. */
2959 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2960 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2962 gcc_assert (!(cfa_off
& 15));
2963 reg
= gen_rtx_REG (XFmode
, regno
);
2964 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
2968 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
2970 finish_spill_pointers ();
2973 /* Called after register allocation to add any instructions needed for the
2974 epilogue. Using an epilogue insn is favored compared to putting all of the
2975 instructions in output_function_prologue(), since it allows the scheduler
2976 to intermix instructions with the saves of the caller saved registers. In
2977 some cases, it might be necessary to emit a barrier instruction as the last
2978 insn to prevent such scheduling. */
2981 ia64_expand_epilogue (int sibcall_p
)
2983 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
2984 int regno
, alt_regno
, cfa_off
;
2986 ia64_compute_frame_size (get_frame_size ());
2988 /* If there is a frame pointer, then we use it instead of the stack
2989 pointer, so that the stack pointer does not need to be valid when
2990 the epilogue starts. See EXIT_IGNORE_STACK. */
2991 if (frame_pointer_needed
)
2992 setup_spill_pointers (current_frame_info
.n_spilled
,
2993 hard_frame_pointer_rtx
, 0);
2995 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
2996 current_frame_info
.total_size
);
2998 if (current_frame_info
.total_size
!= 0)
3000 /* ??? At this point we must generate a magic insn that appears to
3001 modify the spill iterators and the frame pointer. This would
3002 allow the most scheduling freedom. For now, just hard stop. */
3003 emit_insn (gen_blockage ());
3006 /* Locate the bottom of the register save area. */
3007 cfa_off
= (current_frame_info
.spill_cfa_off
3008 + current_frame_info
.spill_size
3009 + current_frame_info
.extra_spill_size
);
3011 /* Restore the predicate registers. */
3012 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
3014 if (current_frame_info
.reg_save_pr
!= 0)
3015 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
3018 alt_regno
= next_scratch_gr_reg ();
3019 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3020 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3023 reg
= gen_rtx_REG (DImode
, PR_REG (0));
3024 emit_move_insn (reg
, alt_reg
);
3027 /* Restore the application registers. */
3029 /* Load the saved unat from the stack, but do not restore it until
3030 after the GRs have been restored. */
3031 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3033 if (current_frame_info
.reg_save_ar_unat
!= 0)
3035 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
3038 alt_regno
= next_scratch_gr_reg ();
3039 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3040 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3041 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3046 ar_unat_save_reg
= NULL_RTX
;
3048 if (current_frame_info
.reg_save_ar_pfs
!= 0)
3050 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_pfs
);
3051 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3052 emit_move_insn (reg
, alt_reg
);
3054 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3056 alt_regno
= next_scratch_gr_reg ();
3057 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3058 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3060 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3061 emit_move_insn (reg
, alt_reg
);
3064 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3066 if (current_frame_info
.reg_save_ar_lc
!= 0)
3067 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
3070 alt_regno
= next_scratch_gr_reg ();
3071 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3072 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3075 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3076 emit_move_insn (reg
, alt_reg
);
3079 /* We should now be at the base of the gr/br/fr spill area. */
3080 gcc_assert (cfa_off
== (current_frame_info
.spill_cfa_off
3081 + current_frame_info
.spill_size
));
3083 /* The GP may be stored on the stack in the prologue, but it's
3084 never restored in the epilogue. Skip the stack slot. */
3085 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3088 /* Restore all general registers. */
3089 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3090 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3092 reg
= gen_rtx_REG (DImode
, regno
);
3093 do_restore (gen_gr_restore
, reg
, cfa_off
);
3097 /* Restore the branch registers. Handle B0 specially, as it may
3098 have gotten stored in some GR register. */
3099 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3101 if (current_frame_info
.reg_save_b0
!= 0)
3102 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3105 alt_regno
= next_scratch_gr_reg ();
3106 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3107 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3110 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3111 emit_move_insn (reg
, alt_reg
);
3114 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3115 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3117 alt_regno
= next_scratch_gr_reg ();
3118 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3119 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3121 reg
= gen_rtx_REG (DImode
, regno
);
3122 emit_move_insn (reg
, alt_reg
);
3125 /* Restore floating point registers. */
3126 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3127 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3129 gcc_assert (!(cfa_off
& 15));
3130 reg
= gen_rtx_REG (XFmode
, regno
);
3131 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
3135 /* Restore ar.unat for real. */
3136 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3138 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3139 emit_move_insn (reg
, ar_unat_save_reg
);
3142 gcc_assert (cfa_off
== current_frame_info
.spill_cfa_off
);
3144 finish_spill_pointers ();
3146 if (current_frame_info
.total_size
|| cfun
->machine
->ia64_eh_epilogue_sp
)
3148 /* ??? At this point we must generate a magic insn that appears to
3149 modify the spill iterators, the stack pointer, and the frame
3150 pointer. This would allow the most scheduling freedom. For now,
3152 emit_insn (gen_blockage ());
3155 if (cfun
->machine
->ia64_eh_epilogue_sp
)
3156 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
3157 else if (frame_pointer_needed
)
3159 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3160 RTX_FRAME_RELATED_P (insn
) = 1;
3162 else if (current_frame_info
.total_size
)
3164 rtx offset
, frame_size_rtx
;
3166 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
3167 if (CONST_OK_FOR_I (current_frame_info
.total_size
))
3168 offset
= frame_size_rtx
;
3171 regno
= next_scratch_gr_reg ();
3172 offset
= gen_rtx_REG (DImode
, regno
);
3173 emit_move_insn (offset
, frame_size_rtx
);
3176 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
3179 RTX_FRAME_RELATED_P (insn
) = 1;
3180 if (GET_CODE (offset
) != CONST_INT
)
3183 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3184 gen_rtx_SET (VOIDmode
,
3186 gen_rtx_PLUS (DImode
,
3193 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
3194 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
3197 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
3200 int fp
= GR_REG (2);
3201 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3202 first available call clobbered register. If there was a frame_pointer
3203 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3204 so we have to make sure we're using the string "r2" when emitting
3205 the register name for the assembler. */
3206 if (current_frame_info
.reg_fp
&& current_frame_info
.reg_fp
== GR_REG (2))
3207 fp
= HARD_FRAME_POINTER_REGNUM
;
3209 /* We must emit an alloc to force the input registers to become output
3210 registers. Otherwise, if the callee tries to pass its parameters
3211 through to another call without an intervening alloc, then these
3213 /* ??? We don't need to preserve all input registers. We only need to
3214 preserve those input registers used as arguments to the sibling call.
3215 It is unclear how to compute that number here. */
3216 if (current_frame_info
.n_input_regs
!= 0)
3218 rtx n_inputs
= GEN_INT (current_frame_info
.n_input_regs
);
3219 insn
= emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
3220 const0_rtx
, const0_rtx
,
3221 n_inputs
, const0_rtx
));
3222 RTX_FRAME_RELATED_P (insn
) = 1;
3227 /* Return 1 if br.ret can do all the work required to return from a
3231 ia64_direct_return (void)
3233 if (reload_completed
&& ! frame_pointer_needed
)
3235 ia64_compute_frame_size (get_frame_size ());
3237 return (current_frame_info
.total_size
== 0
3238 && current_frame_info
.n_spilled
== 0
3239 && current_frame_info
.reg_save_b0
== 0
3240 && current_frame_info
.reg_save_pr
== 0
3241 && current_frame_info
.reg_save_ar_pfs
== 0
3242 && current_frame_info
.reg_save_ar_unat
== 0
3243 && current_frame_info
.reg_save_ar_lc
== 0);
3248 /* Return the magic cookie that we use to hold the return address
3249 during early compilation. */
3252 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
3256 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
3259 /* Split this value after reload, now that we know where the return
3260 address is saved. */
3263 ia64_split_return_addr_rtx (rtx dest
)
3267 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3269 if (current_frame_info
.reg_save_b0
!= 0)
3270 src
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3276 /* Compute offset from CFA for BR0. */
3277 /* ??? Must be kept in sync with ia64_expand_prologue. */
3278 off
= (current_frame_info
.spill_cfa_off
3279 + current_frame_info
.spill_size
);
3280 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3281 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3284 /* Convert CFA offset to a register based offset. */
3285 if (frame_pointer_needed
)
3286 src
= hard_frame_pointer_rtx
;
3289 src
= stack_pointer_rtx
;
3290 off
+= current_frame_info
.total_size
;
3293 /* Load address into scratch register. */
3294 if (CONST_OK_FOR_I (off
))
3295 emit_insn (gen_adddi3 (dest
, src
, GEN_INT (off
)));
3298 emit_move_insn (dest
, GEN_INT (off
));
3299 emit_insn (gen_adddi3 (dest
, src
, dest
));
3302 src
= gen_rtx_MEM (Pmode
, dest
);
3306 src
= gen_rtx_REG (DImode
, BR_REG (0));
3308 emit_move_insn (dest
, src
);
3312 ia64_hard_regno_rename_ok (int from
, int to
)
3314 /* Don't clobber any of the registers we reserved for the prologue. */
3315 if (to
== current_frame_info
.reg_fp
3316 || to
== current_frame_info
.reg_save_b0
3317 || to
== current_frame_info
.reg_save_pr
3318 || to
== current_frame_info
.reg_save_ar_pfs
3319 || to
== current_frame_info
.reg_save_ar_unat
3320 || to
== current_frame_info
.reg_save_ar_lc
)
3323 if (from
== current_frame_info
.reg_fp
3324 || from
== current_frame_info
.reg_save_b0
3325 || from
== current_frame_info
.reg_save_pr
3326 || from
== current_frame_info
.reg_save_ar_pfs
3327 || from
== current_frame_info
.reg_save_ar_unat
3328 || from
== current_frame_info
.reg_save_ar_lc
)
3331 /* Don't use output registers outside the register frame. */
3332 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
3335 /* Retain even/oddness on predicate register pairs. */
3336 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
3337 return (from
& 1) == (to
& 1);
3342 /* Target hook for assembling integer objects. Handle word-sized
3343 aligned objects and detect the cases when @fptr is needed. */
3346 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3348 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
3349 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3350 && GET_CODE (x
) == SYMBOL_REF
3351 && SYMBOL_REF_FUNCTION_P (x
))
3353 static const char * const directive
[2][2] = {
3354 /* 64-bit pointer */ /* 32-bit pointer */
3355 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3356 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3358 fputs (directive
[(aligned_p
!= 0)][POINTER_SIZE
== 32], asm_out_file
);
3359 output_addr_const (asm_out_file
, x
);
3360 fputs (")\n", asm_out_file
);
3363 return default_assemble_integer (x
, size
, aligned_p
);
3366 /* Emit the function prologue. */
3369 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3371 int mask
, grsave
, grsave_prev
;
3373 if (current_frame_info
.need_regstk
)
3374 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3375 current_frame_info
.n_input_regs
,
3376 current_frame_info
.n_local_regs
,
3377 current_frame_info
.n_output_regs
,
3378 current_frame_info
.n_rotate_regs
);
3380 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3383 /* Emit the .prologue directive. */
3386 grsave
= grsave_prev
= 0;
3387 if (current_frame_info
.reg_save_b0
!= 0)
3390 grsave
= grsave_prev
= current_frame_info
.reg_save_b0
;
3392 if (current_frame_info
.reg_save_ar_pfs
!= 0
3393 && (grsave_prev
== 0
3394 || current_frame_info
.reg_save_ar_pfs
== grsave_prev
+ 1))
3397 if (grsave_prev
== 0)
3398 grsave
= current_frame_info
.reg_save_ar_pfs
;
3399 grsave_prev
= current_frame_info
.reg_save_ar_pfs
;
3401 if (current_frame_info
.reg_fp
!= 0
3402 && (grsave_prev
== 0
3403 || current_frame_info
.reg_fp
== grsave_prev
+ 1))
3406 if (grsave_prev
== 0)
3407 grsave
= HARD_FRAME_POINTER_REGNUM
;
3408 grsave_prev
= current_frame_info
.reg_fp
;
3410 if (current_frame_info
.reg_save_pr
!= 0
3411 && (grsave_prev
== 0
3412 || current_frame_info
.reg_save_pr
== grsave_prev
+ 1))
3415 if (grsave_prev
== 0)
3416 grsave
= current_frame_info
.reg_save_pr
;
3419 if (mask
&& TARGET_GNU_AS
)
3420 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3421 ia64_dbx_register_number (grsave
));
3423 fputs ("\t.prologue\n", file
);
3425 /* Emit a .spill directive, if necessary, to relocate the base of
3426 the register spill area. */
3427 if (current_frame_info
.spill_cfa_off
!= -16)
3428 fprintf (file
, "\t.spill %ld\n",
3429 (long) (current_frame_info
.spill_cfa_off
3430 + current_frame_info
.spill_size
));
3433 /* Emit the .body directive at the scheduled end of the prologue. */
3436 ia64_output_function_end_prologue (FILE *file
)
3438 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3441 fputs ("\t.body\n", file
);
3444 /* Emit the function epilogue. */
3447 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
3448 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3452 if (current_frame_info
.reg_fp
)
3454 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3455 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3456 = reg_names
[current_frame_info
.reg_fp
];
3457 reg_names
[current_frame_info
.reg_fp
] = tmp
;
3459 if (! TARGET_REG_NAMES
)
3461 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
3462 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
3463 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
3464 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
3465 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
3466 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
3469 current_frame_info
.initialized
= 0;
3473 ia64_dbx_register_number (int regno
)
3475 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3476 from its home at loc79 to something inside the register frame. We
3477 must perform the same renumbering here for the debug info. */
3478 if (current_frame_info
.reg_fp
)
3480 if (regno
== HARD_FRAME_POINTER_REGNUM
)
3481 regno
= current_frame_info
.reg_fp
;
3482 else if (regno
== current_frame_info
.reg_fp
)
3483 regno
= HARD_FRAME_POINTER_REGNUM
;
3486 if (IN_REGNO_P (regno
))
3487 return 32 + regno
- IN_REG (0);
3488 else if (LOC_REGNO_P (regno
))
3489 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
3490 else if (OUT_REGNO_P (regno
))
3491 return (32 + current_frame_info
.n_input_regs
3492 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
3498 ia64_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
3500 rtx addr_reg
, eight
= GEN_INT (8);
3502 /* The Intel assembler requires that the global __ia64_trampoline symbol
3503 be declared explicitly */
3506 static bool declared_ia64_trampoline
= false;
3508 if (!declared_ia64_trampoline
)
3510 declared_ia64_trampoline
= true;
3511 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
3512 "__ia64_trampoline");
3516 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3517 addr
= convert_memory_address (Pmode
, addr
);
3518 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
3519 static_chain
= convert_memory_address (Pmode
, static_chain
);
3521 /* Load up our iterator. */
3522 addr_reg
= gen_reg_rtx (Pmode
);
3523 emit_move_insn (addr_reg
, addr
);
3525 /* The first two words are the fake descriptor:
3526 __ia64_trampoline, ADDR+16. */
3527 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3528 gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline"));
3529 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3531 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3532 copy_to_reg (plus_constant (addr
, 16)));
3533 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3535 /* The third word is the target descriptor. */
3536 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), fnaddr
);
3537 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3539 /* The fourth word is the static chain. */
3540 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), static_chain
);
3543 /* Do any needed setup for a variadic function. CUM has not been updated
3544 for the last named argument which has type TYPE and mode MODE.
3546 We generate the actual spill instructions during prologue generation. */
3549 ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3550 tree type
, int * pretend_size
,
3551 int second_time ATTRIBUTE_UNUSED
)
3553 CUMULATIVE_ARGS next_cum
= *cum
;
3555 /* Skip the current argument. */
3556 ia64_function_arg_advance (&next_cum
, mode
, type
, 1);
3558 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
3560 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
3561 *pretend_size
= n
* UNITS_PER_WORD
;
3562 cfun
->machine
->n_varargs
= n
;
3566 /* Check whether TYPE is a homogeneous floating point aggregate. If
3567 it is, return the mode of the floating point type that appears
3568 in all leafs. If it is not, return VOIDmode.
3570 An aggregate is a homogeneous floating point aggregate is if all
3571 fields/elements in it have the same floating point type (e.g,
3572 SFmode). 128-bit quad-precision floats are excluded.
3574 Variable sized aggregates should never arrive here, since we should
3575 have already decided to pass them by reference. Top-level zero-sized
3576 aggregates are excluded because our parallels crash the middle-end. */
3578 static enum machine_mode
3579 hfa_element_mode (tree type
, bool nested
)
3581 enum machine_mode element_mode
= VOIDmode
;
3582 enum machine_mode mode
;
3583 enum tree_code code
= TREE_CODE (type
);
3584 int know_element_mode
= 0;
3587 if (!nested
&& (!TYPE_SIZE (type
) || integer_zerop (TYPE_SIZE (type
))))
3592 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
3593 case BOOLEAN_TYPE
: case CHAR_TYPE
: case POINTER_TYPE
:
3594 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
3595 case LANG_TYPE
: case FUNCTION_TYPE
:
3598 /* Fortran complex types are supposed to be HFAs, so we need to handle
3599 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3602 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
3603 && TYPE_MODE (type
) != TCmode
)
3604 return GET_MODE_INNER (TYPE_MODE (type
));
3609 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3610 mode if this is contained within an aggregate. */
3611 if (nested
&& TYPE_MODE (type
) != TFmode
)
3612 return TYPE_MODE (type
);
3617 return hfa_element_mode (TREE_TYPE (type
), 1);
3621 case QUAL_UNION_TYPE
:
3622 for (t
= TYPE_FIELDS (type
); t
; t
= TREE_CHAIN (t
))
3624 if (TREE_CODE (t
) != FIELD_DECL
)
3627 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
3628 if (know_element_mode
)
3630 if (mode
!= element_mode
)
3633 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3637 know_element_mode
= 1;
3638 element_mode
= mode
;
3641 return element_mode
;
3644 /* If we reach here, we probably have some front-end specific type
3645 that the backend doesn't know about. This can happen via the
3646 aggregate_value_p call in init_function_start. All we can do is
3647 ignore unknown tree types. */
3654 /* Return the number of words required to hold a quantity of TYPE and MODE
3655 when passed as an argument. */
3657 ia64_function_arg_words (tree type
, enum machine_mode mode
)
3661 if (mode
== BLKmode
)
3662 words
= int_size_in_bytes (type
);
3664 words
= GET_MODE_SIZE (mode
);
3666 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
3669 /* Return the number of registers that should be skipped so the current
3670 argument (described by TYPE and WORDS) will be properly aligned.
3672 Integer and float arguments larger than 8 bytes start at the next
3673 even boundary. Aggregates larger than 8 bytes start at the next
3674 even boundary if the aggregate has 16 byte alignment. Note that
3675 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3676 but are still to be aligned in registers.
3678 ??? The ABI does not specify how to handle aggregates with
3679 alignment from 9 to 15 bytes, or greater than 16. We handle them
3680 all as if they had 16 byte alignment. Such aggregates can occur
3681 only if gcc extensions are used. */
3683 ia64_function_arg_offset (CUMULATIVE_ARGS
*cum
, tree type
, int words
)
3685 if ((cum
->words
& 1) == 0)
3689 && TREE_CODE (type
) != INTEGER_TYPE
3690 && TREE_CODE (type
) != REAL_TYPE
)
3691 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
3696 /* Return rtx for register where argument is passed, or zero if it is passed
3698 /* ??? 128-bit quad-precision floats are always passed in general
3702 ia64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
3703 int named
, int incoming
)
3705 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
3706 int words
= ia64_function_arg_words (type
, mode
);
3707 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3708 enum machine_mode hfa_mode
= VOIDmode
;
3710 /* If all argument slots are used, then it must go on the stack. */
3711 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3714 /* Check for and handle homogeneous FP aggregates. */
3716 hfa_mode
= hfa_element_mode (type
, 0);
3718 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3719 and unprototyped hfas are passed specially. */
3720 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3724 int fp_regs
= cum
->fp_regs
;
3725 int int_regs
= cum
->words
+ offset
;
3726 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3730 /* If prototyped, pass it in FR regs then GR regs.
3731 If not prototyped, pass it in both FR and GR regs.
3733 If this is an SFmode aggregate, then it is possible to run out of
3734 FR regs while GR regs are still left. In that case, we pass the
3735 remaining part in the GR regs. */
3737 /* Fill the FP regs. We do this always. We stop if we reach the end
3738 of the argument, the last FP register, or the last argument slot. */
3740 byte_size
= ((mode
== BLKmode
)
3741 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3742 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3744 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3745 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
3747 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3748 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
3752 args_byte_size
+= hfa_size
;
3756 /* If no prototype, then the whole thing must go in GR regs. */
3757 if (! cum
->prototype
)
3759 /* If this is an SFmode aggregate, then we might have some left over
3760 that needs to go in GR regs. */
3761 else if (byte_size
!= offset
)
3762 int_regs
+= offset
/ UNITS_PER_WORD
;
3764 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3766 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
3768 enum machine_mode gr_mode
= DImode
;
3769 unsigned int gr_size
;
3771 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3772 then this goes in a GR reg left adjusted/little endian, right
3773 adjusted/big endian. */
3774 /* ??? Currently this is handled wrong, because 4-byte hunks are
3775 always right adjusted/little endian. */
3778 /* If we have an even 4 byte hunk because the aggregate is a
3779 multiple of 4 bytes in size, then this goes in a GR reg right
3780 adjusted/little endian. */
3781 else if (byte_size
- offset
== 4)
3784 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3785 gen_rtx_REG (gr_mode
, (basereg
3789 gr_size
= GET_MODE_SIZE (gr_mode
);
3791 if (gr_size
== UNITS_PER_WORD
3792 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
3794 else if (gr_size
> UNITS_PER_WORD
)
3795 int_regs
+= gr_size
/ UNITS_PER_WORD
;
3797 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3800 /* Integral and aggregates go in general registers. If we have run out of
3801 FR registers, then FP values must also go in general registers. This can
3802 happen when we have a SFmode HFA. */
3803 else if (mode
== TFmode
|| mode
== TCmode
3804 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3806 int byte_size
= ((mode
== BLKmode
)
3807 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3808 if (BYTES_BIG_ENDIAN
3809 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
3810 && byte_size
< UNITS_PER_WORD
3813 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3814 gen_rtx_REG (DImode
,
3815 (basereg
+ cum
->words
3818 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
3821 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3825 /* If there is a prototype, then FP values go in a FR register when
3826 named, and in a GR register when unnamed. */
3827 else if (cum
->prototype
)
3830 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
3831 /* In big-endian mode, an anonymous SFmode value must be represented
3832 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3833 the value into the high half of the general register. */
3834 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
3835 return gen_rtx_PARALLEL (mode
,
3837 gen_rtx_EXPR_LIST (VOIDmode
,
3838 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
3840 /* Similarly, an anonymous XFmode value must be split into two
3841 registers and padded appropriately. */
3842 else if (BYTES_BIG_ENDIAN
&& mode
== XFmode
)
3845 loc
[0] = gen_rtx_EXPR_LIST (VOIDmode
,
3846 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
3848 loc
[1] = gen_rtx_EXPR_LIST (VOIDmode
,
3849 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
+ 1),
3850 GEN_INT (UNITS_PER_WORD
));
3851 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (2, loc
));
3854 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3856 /* If there is no prototype, then FP values go in both FR and GR
3860 /* See comment above. */
3861 enum machine_mode inner_mode
=
3862 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
3864 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3865 gen_rtx_REG (mode
, (FR_ARG_FIRST
3868 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3869 gen_rtx_REG (inner_mode
,
3870 (basereg
+ cum
->words
3874 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
3878 /* Return number of bytes, at the beginning of the argument, that must be
3879 put in registers. 0 is the argument is entirely in registers or entirely
3883 ia64_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3884 tree type
, bool named ATTRIBUTE_UNUSED
)
3886 int words
= ia64_function_arg_words (type
, mode
);
3887 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3889 /* If all argument slots are used, then it must go on the stack. */
3890 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3893 /* It doesn't matter whether the argument goes in FR or GR regs. If
3894 it fits within the 8 argument slots, then it goes entirely in
3895 registers. If it extends past the last argument slot, then the rest
3896 goes on the stack. */
3898 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
3901 return (MAX_ARGUMENT_SLOTS
- cum
->words
- offset
) * UNITS_PER_WORD
;
3904 /* Update CUM to point after this argument. This is patterned after
3905 ia64_function_arg. */
3908 ia64_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3909 tree type
, int named
)
3911 int words
= ia64_function_arg_words (type
, mode
);
3912 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3913 enum machine_mode hfa_mode
= VOIDmode
;
3915 /* If all arg slots are already full, then there is nothing to do. */
3916 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
3919 cum
->words
+= words
+ offset
;
3921 /* Check for and handle homogeneous FP aggregates. */
3923 hfa_mode
= hfa_element_mode (type
, 0);
3925 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3926 and unprototyped hfas are passed specially. */
3927 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3929 int fp_regs
= cum
->fp_regs
;
3930 /* This is the original value of cum->words + offset. */
3931 int int_regs
= cum
->words
- words
;
3932 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3936 /* If prototyped, pass it in FR regs then GR regs.
3937 If not prototyped, pass it in both FR and GR regs.
3939 If this is an SFmode aggregate, then it is possible to run out of
3940 FR regs while GR regs are still left. In that case, we pass the
3941 remaining part in the GR regs. */
3943 /* Fill the FP regs. We do this always. We stop if we reach the end
3944 of the argument, the last FP register, or the last argument slot. */
3946 byte_size
= ((mode
== BLKmode
)
3947 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3948 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3950 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3951 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
3954 args_byte_size
+= hfa_size
;
3958 cum
->fp_regs
= fp_regs
;
3961 /* Integral and aggregates go in general registers. So do TFmode FP values.
3962 If we have run out of FR registers, then other FP values must also go in
3963 general registers. This can happen when we have a SFmode HFA. */
3964 else if (mode
== TFmode
|| mode
== TCmode
3965 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3966 cum
->int_regs
= cum
->words
;
3968 /* If there is a prototype, then FP values go in a FR register when
3969 named, and in a GR register when unnamed. */
3970 else if (cum
->prototype
)
3973 cum
->int_regs
= cum
->words
;
3975 /* ??? Complex types should not reach here. */
3976 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3978 /* If there is no prototype, then FP values go in both FR and GR
3982 /* ??? Complex types should not reach here. */
3983 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3984 cum
->int_regs
= cum
->words
;
3988 /* Arguments with alignment larger than 8 bytes start at the next even
3989 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
3990 even though their normal alignment is 8 bytes. See ia64_function_arg. */
3993 ia64_function_arg_boundary (enum machine_mode mode
, tree type
)
3996 if (mode
== TFmode
&& TARGET_HPUX
&& TARGET_ILP32
)
3997 return PARM_BOUNDARY
* 2;
4001 if (TYPE_ALIGN (type
) > PARM_BOUNDARY
)
4002 return PARM_BOUNDARY
* 2;
4004 return PARM_BOUNDARY
;
4007 if (GET_MODE_BITSIZE (mode
) > PARM_BOUNDARY
)
4008 return PARM_BOUNDARY
* 2;
4010 return PARM_BOUNDARY
;
4013 /* Variable sized types are passed by reference. */
4014 /* ??? At present this is a GCC extension to the IA-64 ABI. */
4017 ia64_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4018 enum machine_mode mode ATTRIBUTE_UNUSED
,
4019 tree type
, bool named ATTRIBUTE_UNUSED
)
4021 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
4024 /* True if it is OK to do sibling call optimization for the specified
4025 call expression EXP. DECL will be the called function, or NULL if
4026 this is an indirect call. */
4028 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
4030 /* We can't perform a sibcall if the current function has the syscall_linkage
4032 if (lookup_attribute ("syscall_linkage",
4033 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
4036 /* We must always return with our current GP. This means we can
4037 only sibcall to functions defined in the current module. */
4038 return decl
&& (*targetm
.binds_local_p
) (decl
);
4042 /* Implement va_arg. */
4045 ia64_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
4047 /* Variable sized types are passed by reference. */
4048 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
4050 tree ptrtype
= build_pointer_type (type
);
4051 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
4052 return build_va_arg_indirect_ref (addr
);
4055 /* Aggregate arguments with alignment larger than 8 bytes start at
4056 the next even boundary. Integer and floating point arguments
4057 do so if they are larger than 8 bytes, whether or not they are
4058 also aligned larger than 8 bytes. */
4059 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
4060 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
4062 tree t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4063 build_int_cst (NULL_TREE
, 2 * UNITS_PER_WORD
- 1));
4064 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4065 build_int_cst (NULL_TREE
, -2 * UNITS_PER_WORD
));
4066 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4067 gimplify_and_add (t
, pre_p
);
4070 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4073 /* Return 1 if function return value returned in memory. Return 0 if it is
4077 ia64_return_in_memory (tree valtype
, tree fntype ATTRIBUTE_UNUSED
)
4079 enum machine_mode mode
;
4080 enum machine_mode hfa_mode
;
4081 HOST_WIDE_INT byte_size
;
4083 mode
= TYPE_MODE (valtype
);
4084 byte_size
= GET_MODE_SIZE (mode
);
4085 if (mode
== BLKmode
)
4087 byte_size
= int_size_in_bytes (valtype
);
4092 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4094 hfa_mode
= hfa_element_mode (valtype
, 0);
4095 if (hfa_mode
!= VOIDmode
)
4097 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4099 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
4104 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
4110 /* Return rtx for register that holds the function return value. */
4113 ia64_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4115 enum machine_mode mode
;
4116 enum machine_mode hfa_mode
;
4118 mode
= TYPE_MODE (valtype
);
4119 hfa_mode
= hfa_element_mode (valtype
, 0);
4121 if (hfa_mode
!= VOIDmode
)
4129 hfa_size
= GET_MODE_SIZE (hfa_mode
);
4130 byte_size
= ((mode
== BLKmode
)
4131 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
4133 for (i
= 0; offset
< byte_size
; i
++)
4135 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4136 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
4140 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4142 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
4143 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
4146 bool need_parallel
= false;
4148 /* In big-endian mode, we need to manage the layout of aggregates
4149 in the registers so that we get the bits properly aligned in
4150 the highpart of the registers. */
4151 if (BYTES_BIG_ENDIAN
4152 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
4153 need_parallel
= true;
4155 /* Something like struct S { long double x; char a[0] } is not an
4156 HFA structure, and therefore doesn't go in fp registers. But
4157 the middle-end will give it XFmode anyway, and XFmode values
4158 don't normally fit in integer registers. So we need to smuggle
4159 the value inside a parallel. */
4160 else if (mode
== XFmode
|| mode
== XCmode
)
4161 need_parallel
= true;
4171 bytesize
= int_size_in_bytes (valtype
);
4172 /* An empty PARALLEL is invalid here, but the return value
4173 doesn't matter for empty structs. */
4175 return gen_rtx_REG (mode
, GR_RET_FIRST
);
4176 for (i
= 0; offset
< bytesize
; i
++)
4178 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4179 gen_rtx_REG (DImode
,
4182 offset
+= UNITS_PER_WORD
;
4184 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4187 return gen_rtx_REG (mode
, GR_RET_FIRST
);
4191 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4192 We need to emit DTP-relative relocations. */
4195 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4197 gcc_assert (size
== 8);
4198 fputs ("\tdata8.ua\t@dtprel(", file
);
4199 output_addr_const (file
, x
);
4203 /* Print a memory address as an operand to reference that memory location. */
4205 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4206 also call this from ia64_print_operand for memory addresses. */
4209 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
4210 rtx address ATTRIBUTE_UNUSED
)
4214 /* Print an operand to an assembler instruction.
4215 C Swap and print a comparison operator.
4216 D Print an FP comparison operator.
4217 E Print 32 - constant, for SImode shifts as extract.
4218 e Print 64 - constant, for DImode rotates.
4219 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4220 a floating point register emitted normally.
4221 I Invert a predicate register by adding 1.
4222 J Select the proper predicate register for a condition.
4223 j Select the inverse predicate register for a condition.
4224 O Append .acq for volatile load.
4225 P Postincrement of a MEM.
4226 Q Append .rel for volatile store.
4227 S Shift amount for shladd instruction.
4228 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4229 for Intel assembler.
4230 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4231 for Intel assembler.
4232 r Print register name, or constant 0 as r0. HP compatibility for
4234 v Print vector constant value as an 8-byte integer value. */
4237 ia64_print_operand (FILE * file
, rtx x
, int code
)
4244 /* Handled below. */
4249 enum rtx_code c
= swap_condition (GET_CODE (x
));
4250 fputs (GET_RTX_NAME (c
), file
);
4255 switch (GET_CODE (x
))
4267 str
= GET_RTX_NAME (GET_CODE (x
));
4274 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
4278 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
4282 if (x
== CONST0_RTX (GET_MODE (x
)))
4283 str
= reg_names
[FR_REG (0)];
4284 else if (x
== CONST1_RTX (GET_MODE (x
)))
4285 str
= reg_names
[FR_REG (1)];
4288 gcc_assert (GET_CODE (x
) == REG
);
4289 str
= reg_names
[REGNO (x
)];
4295 fputs (reg_names
[REGNO (x
) + 1], file
);
4301 unsigned int regno
= REGNO (XEXP (x
, 0));
4302 if (GET_CODE (x
) == EQ
)
4306 fputs (reg_names
[regno
], file
);
4311 if (MEM_VOLATILE_P (x
))
4312 fputs(".acq", file
);
4317 HOST_WIDE_INT value
;
4319 switch (GET_CODE (XEXP (x
, 0)))
4325 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
4326 if (GET_CODE (x
) == CONST_INT
)
4330 gcc_assert (GET_CODE (x
) == REG
);
4331 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
4337 value
= GET_MODE_SIZE (GET_MODE (x
));
4341 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
4345 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
4350 if (MEM_VOLATILE_P (x
))
4351 fputs(".rel", file
);
4355 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
4359 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4361 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
4367 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4369 const char *prefix
= "0x";
4370 if (INTVAL (x
) & 0x80000000)
4372 fprintf (file
, "0xffffffff");
4375 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
4381 /* If this operand is the constant zero, write it as register zero.
4382 Any register, zero, or CONST_INT value is OK here. */
4383 if (GET_CODE (x
) == REG
)
4384 fputs (reg_names
[REGNO (x
)], file
);
4385 else if (x
== CONST0_RTX (GET_MODE (x
)))
4387 else if (GET_CODE (x
) == CONST_INT
)
4388 output_addr_const (file
, x
);
4390 output_operand_lossage ("invalid %%r value");
4394 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
4395 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
4402 /* For conditional branches, returns or calls, substitute
4403 sptk, dptk, dpnt, or spnt for %s. */
4404 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
4407 int pred_val
= INTVAL (XEXP (x
, 0));
4409 /* Guess top and bottom 10% statically predicted. */
4410 if (pred_val
< REG_BR_PROB_BASE
/ 50)
4412 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
4414 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98)
4419 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
4424 fputs (which
, file
);
4429 x
= current_insn_predicate
;
4432 unsigned int regno
= REGNO (XEXP (x
, 0));
4433 if (GET_CODE (x
) == EQ
)
4435 fprintf (file
, "(%s) ", reg_names
[regno
]);
4440 output_operand_lossage ("ia64_print_operand: unknown code");
4444 switch (GET_CODE (x
))
4446 /* This happens for the spill/restore instructions. */
4451 /* ... fall through ... */
4454 fputs (reg_names
[REGNO (x
)], file
);
4459 rtx addr
= XEXP (x
, 0);
4460 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
4461 addr
= XEXP (addr
, 0);
4462 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
4467 output_addr_const (file
, x
);
4474 /* Compute a (partial) cost for rtx X. Return true if the complete
4475 cost has been computed, and false if subexpressions should be
4476 scanned. In either case, *TOTAL contains the cost result. */
4477 /* ??? This is incomplete. */
4480 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4488 *total
= CONST_OK_FOR_J (INTVAL (x
)) ? 0 : COSTS_N_INSNS (1);
4491 if (CONST_OK_FOR_I (INTVAL (x
)))
4493 else if (CONST_OK_FOR_J (INTVAL (x
)))
4496 *total
= COSTS_N_INSNS (1);
4499 if (CONST_OK_FOR_K (INTVAL (x
)) || CONST_OK_FOR_L (INTVAL (x
)))
4502 *total
= COSTS_N_INSNS (1);
4507 *total
= COSTS_N_INSNS (1);
4513 *total
= COSTS_N_INSNS (3);
4517 /* For multiplies wider than HImode, we have to go to the FPU,
4518 which normally involves copies. Plus there's the latency
4519 of the multiply itself, and the latency of the instructions to
4520 transfer integer regs to FP regs. */
4521 /* ??? Check for FP mode. */
4522 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
4523 *total
= COSTS_N_INSNS (10);
4525 *total
= COSTS_N_INSNS (2);
4533 *total
= COSTS_N_INSNS (1);
4540 /* We make divide expensive, so that divide-by-constant will be
4541 optimized to a multiply. */
4542 *total
= COSTS_N_INSNS (60);
4550 /* Calculate the cost of moving data from a register in class FROM to
4551 one in class TO, using MODE. */
4554 ia64_register_move_cost (enum machine_mode mode
, enum reg_class from
,
4557 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4558 if (to
== ADDL_REGS
)
4560 if (from
== ADDL_REGS
)
4563 /* All costs are symmetric, so reduce cases by putting the
4564 lower number class as the destination. */
4567 enum reg_class tmp
= to
;
4568 to
= from
, from
= tmp
;
4571 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4572 so that we get secondary memory reloads. Between FR_REGS,
4573 we have to make this at least as expensive as MEMORY_MOVE_COST
4574 to avoid spectacularly poor register class preferencing. */
4577 if (to
!= GR_REGS
|| from
!= GR_REGS
)
4578 return MEMORY_MOVE_COST (mode
, to
, 0);
4586 /* Moving between PR registers takes two insns. */
4587 if (from
== PR_REGS
)
4589 /* Moving between PR and anything but GR is impossible. */
4590 if (from
!= GR_REGS
)
4591 return MEMORY_MOVE_COST (mode
, to
, 0);
4595 /* Moving between BR and anything but GR is impossible. */
4596 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
4597 return MEMORY_MOVE_COST (mode
, to
, 0);
4602 /* Moving between AR and anything but GR is impossible. */
4603 if (from
!= GR_REGS
)
4604 return MEMORY_MOVE_COST (mode
, to
, 0);
4609 case GR_AND_FR_REGS
:
4610 case GR_AND_BR_REGS
:
4621 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on CLASS
4622 to use when copying X into that class. */
4625 ia64_preferred_reload_class (rtx x
, enum reg_class
class)
4630 /* Don't allow volatile mem reloads into floating point registers.
4631 This is defined to force reload to choose the r/m case instead
4632 of the f/f case when reloading (set (reg fX) (mem/v)). */
4633 if (MEM_P (x
) && MEM_VOLATILE_P (x
))
4636 /* Force all unrecognized constants into the constant pool. */
4654 /* This function returns the register class required for a secondary
4655 register when copying between one of the registers in CLASS, and X,
4656 using MODE. A return value of NO_REGS means that no secondary register
4660 ia64_secondary_reload_class (enum reg_class
class,
4661 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4665 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
4666 regno
= true_regnum (x
);
4673 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4674 interaction. We end up with two pseudos with overlapping lifetimes
4675 both of which are equiv to the same constant, and both which need
4676 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4677 changes depending on the path length, which means the qty_first_reg
4678 check in make_regs_eqv can give different answers at different times.
4679 At some point I'll probably need a reload_indi pattern to handle
4682 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4683 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4684 non-general registers for good measure. */
4685 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
4688 /* This is needed if a pseudo used as a call_operand gets spilled to a
4690 if (GET_CODE (x
) == MEM
)
4695 /* Need to go through general registers to get to other class regs. */
4696 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
4699 /* This can happen when a paradoxical subreg is an operand to the
4701 /* ??? This shouldn't be necessary after instruction scheduling is
4702 enabled, because paradoxical subregs are not accepted by
4703 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4704 stop the paradoxical subreg stupidity in the *_operand functions
4706 if (GET_CODE (x
) == MEM
4707 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
4708 || GET_MODE (x
) == QImode
))
4711 /* This can happen because of the ior/and/etc patterns that accept FP
4712 registers as operands. If the third operand is a constant, then it
4713 needs to be reloaded into a FP register. */
4714 if (GET_CODE (x
) == CONST_INT
)
4717 /* This can happen because of register elimination in a muldi3 insn.
4718 E.g. `26107 * (unsigned long)&u'. */
4719 if (GET_CODE (x
) == PLUS
)
4724 /* ??? This happens if we cse/gcse a BImode value across a call,
4725 and the function has a nonlocal goto. This is because global
4726 does not allocate call crossing pseudos to hard registers when
4727 current_function_has_nonlocal_goto is true. This is relatively
4728 common for C++ programs that use exceptions. To reproduce,
4729 return NO_REGS and compile libstdc++. */
4730 if (GET_CODE (x
) == MEM
)
4733 /* This can happen when we take a BImode subreg of a DImode value,
4734 and that DImode value winds up in some non-GR register. */
4735 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
4747 /* Emit text to declare externally defined variables and functions, because
4748 the Intel assembler does not support undefined externals. */
4751 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
4753 int save_referenced
;
4755 /* GNU as does not need anything here, but the HP linker does need
4756 something for external functions. */
4760 || TREE_CODE (decl
) != FUNCTION_DECL
4761 || strstr (name
, "__builtin_") == name
))
4764 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4765 the linker when we do this, so we need to be careful not to do this for
4766 builtin functions which have no library equivalent. Unfortunately, we
4767 can't tell here whether or not a function will actually be called by
4768 expand_expr, so we pull in library functions even if we may not need
4770 if (! strcmp (name
, "__builtin_next_arg")
4771 || ! strcmp (name
, "alloca")
4772 || ! strcmp (name
, "__builtin_constant_p")
4773 || ! strcmp (name
, "__builtin_args_info"))
4777 ia64_hpux_add_extern_decl (decl
);
4780 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4782 save_referenced
= TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
));
4783 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4784 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
4785 (*targetm
.asm_out
.globalize_label
) (file
, name
);
4786 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)) = save_referenced
;
4790 /* Parse the -mfixed-range= option string. */
4793 fix_range (const char *const_str
)
4796 char *str
, *dash
, *comma
;
4798 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4799 REG2 are either register names or register numbers. The effect
4800 of this option is to mark the registers in the range from REG1 to
4801 REG2 as ``fixed'' so they won't be used by the compiler. This is
4802 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4804 i
= strlen (const_str
);
4805 str
= (char *) alloca (i
+ 1);
4806 memcpy (str
, const_str
, i
+ 1);
4810 dash
= strchr (str
, '-');
4813 warning (0, "value of -mfixed-range must have form REG1-REG2");
4818 comma
= strchr (dash
+ 1, ',');
4822 first
= decode_reg_name (str
);
4825 warning (0, "unknown register name: %s", str
);
4829 last
= decode_reg_name (dash
+ 1);
4832 warning (0, "unknown register name: %s", dash
+ 1);
4840 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
4844 for (i
= first
; i
<= last
; ++i
)
4845 fixed_regs
[i
] = call_used_regs
[i
] = 1;
4855 /* Implement TARGET_HANDLE_OPTION. */
4858 ia64_handle_option (size_t code
, const char *arg
, int value
)
4862 case OPT_mfixed_range_
:
4866 case OPT_mtls_size_
:
4867 if (value
!= 14 && value
!= 22 && value
!= 64)
4868 error ("bad value %<%s%> for -mtls-size= switch", arg
);
4875 const char *name
; /* processor name or nickname. */
4876 enum processor_type processor
;
4878 const processor_alias_table
[] =
4880 {"itanium", PROCESSOR_ITANIUM
},
4881 {"itanium1", PROCESSOR_ITANIUM
},
4882 {"merced", PROCESSOR_ITANIUM
},
4883 {"itanium2", PROCESSOR_ITANIUM2
},
4884 {"mckinley", PROCESSOR_ITANIUM2
},
4886 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
4889 for (i
= 0; i
< pta_size
; i
++)
4890 if (!strcmp (arg
, processor_alias_table
[i
].name
))
4892 ia64_tune
= processor_alias_table
[i
].processor
;
4896 error ("bad value %<%s%> for -mtune= switch", arg
);
4905 /* Implement OVERRIDE_OPTIONS. */
4908 ia64_override_options (void)
4910 if (TARGET_AUTO_PIC
)
4911 target_flags
|= MASK_CONST_GP
;
4913 if (TARGET_INLINE_SQRT
== INL_MIN_LAT
)
4915 warning (0, "not yet implemented: latency-optimized inline square root");
4916 TARGET_INLINE_SQRT
= INL_MAX_THR
;
4919 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
4920 flag_schedule_insns_after_reload
= 0;
4922 ia64_section_threshold
= g_switch_set
? g_switch_value
: IA64_DEFAULT_GVALUE
;
4924 init_machine_status
= ia64_init_machine_status
;
4927 static struct machine_function
*
4928 ia64_init_machine_status (void)
4930 return ggc_alloc_cleared (sizeof (struct machine_function
));
4933 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
4934 static enum attr_type
ia64_safe_type (rtx
);
4936 static enum attr_itanium_class
4937 ia64_safe_itanium_class (rtx insn
)
4939 if (recog_memoized (insn
) >= 0)
4940 return get_attr_itanium_class (insn
);
4942 return ITANIUM_CLASS_UNKNOWN
;
4945 static enum attr_type
4946 ia64_safe_type (rtx insn
)
4948 if (recog_memoized (insn
) >= 0)
4949 return get_attr_type (insn
);
4951 return TYPE_UNKNOWN
;
4954 /* The following collection of routines emit instruction group stop bits as
4955 necessary to avoid dependencies. */
4957 /* Need to track some additional registers as far as serialization is
4958 concerned so we can properly handle br.call and br.ret. We could
4959 make these registers visible to gcc, but since these registers are
4960 never explicitly used in gcc generated code, it seems wasteful to
4961 do so (plus it would make the call and return patterns needlessly
4963 #define REG_RP (BR_REG (0))
4964 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4965 /* This is used for volatile asms which may require a stop bit immediately
4966 before and after them. */
4967 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4968 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4969 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4971 /* For each register, we keep track of how it has been written in the
4972 current instruction group.
4974 If a register is written unconditionally (no qualifying predicate),
4975 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4977 If a register is written if its qualifying predicate P is true, we
4978 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4979 may be written again by the complement of P (P^1) and when this happens,
4980 WRITE_COUNT gets set to 2.
4982 The result of this is that whenever an insn attempts to write a register
4983 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4985 If a predicate register is written by a floating-point insn, we set
4986 WRITTEN_BY_FP to true.
4988 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4989 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4991 struct reg_write_state
4993 unsigned int write_count
: 2;
4994 unsigned int first_pred
: 16;
4995 unsigned int written_by_fp
: 1;
4996 unsigned int written_by_and
: 1;
4997 unsigned int written_by_or
: 1;
5000 /* Cumulative info for the current instruction group. */
5001 struct reg_write_state rws_sum
[NUM_REGS
];
5002 /* Info for the current instruction. This gets copied to rws_sum after a
5003 stop bit is emitted. */
5004 struct reg_write_state rws_insn
[NUM_REGS
];
5006 /* Indicates whether this is the first instruction after a stop bit,
5007 in which case we don't need another stop bit. Without this,
5008 ia64_variable_issue will die when scheduling an alloc. */
5009 static int first_instruction
;
5011 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5012 RTL for one instruction. */
5015 unsigned int is_write
: 1; /* Is register being written? */
5016 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
5017 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
5018 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
5019 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
5020 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
5023 static void rws_update (struct reg_write_state
*, int, struct reg_flags
, int);
5024 static int rws_access_regno (int, struct reg_flags
, int);
5025 static int rws_access_reg (rtx
, struct reg_flags
, int);
5026 static void update_set_flags (rtx
, struct reg_flags
*);
5027 static int set_src_needs_barrier (rtx
, struct reg_flags
, int);
5028 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
5029 static void init_insn_group_barriers (void);
5030 static int group_barrier_needed (rtx
);
5031 static int safe_group_barrier_needed (rtx
);
5033 /* Update *RWS for REGNO, which is being written by the current instruction,
5034 with predicate PRED, and associated register flags in FLAGS. */
5037 rws_update (struct reg_write_state
*rws
, int regno
, struct reg_flags flags
, int pred
)
5040 rws
[regno
].write_count
++;
5042 rws
[regno
].write_count
= 2;
5043 rws
[regno
].written_by_fp
|= flags
.is_fp
;
5044 /* ??? Not tracking and/or across differing predicates. */
5045 rws
[regno
].written_by_and
= flags
.is_and
;
5046 rws
[regno
].written_by_or
= flags
.is_or
;
5047 rws
[regno
].first_pred
= pred
;
5050 /* Handle an access to register REGNO of type FLAGS using predicate register
5051 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
5052 a dependency with an earlier instruction in the same group. */
5055 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
5057 int need_barrier
= 0;
5059 gcc_assert (regno
< NUM_REGS
);
5061 if (! PR_REGNO_P (regno
))
5062 flags
.is_and
= flags
.is_or
= 0;
5068 /* One insn writes same reg multiple times? */
5069 gcc_assert (!rws_insn
[regno
].write_count
);
5071 /* Update info for current instruction. */
5072 rws_update (rws_insn
, regno
, flags
, pred
);
5073 write_count
= rws_sum
[regno
].write_count
;
5075 switch (write_count
)
5078 /* The register has not been written yet. */
5079 rws_update (rws_sum
, regno
, flags
, pred
);
5083 /* The register has been written via a predicate. If this is
5084 not a complementary predicate, then we need a barrier. */
5085 /* ??? This assumes that P and P+1 are always complementary
5086 predicates for P even. */
5087 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5089 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5091 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5093 rws_update (rws_sum
, regno
, flags
, pred
);
5097 /* The register has been unconditionally written already. We
5099 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5101 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5105 rws_sum
[regno
].written_by_and
= flags
.is_and
;
5106 rws_sum
[regno
].written_by_or
= flags
.is_or
;
5115 if (flags
.is_branch
)
5117 /* Branches have several RAW exceptions that allow to avoid
5120 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
5121 /* RAW dependencies on branch regs are permissible as long
5122 as the writer is a non-branch instruction. Since we
5123 never generate code that uses a branch register written
5124 by a branch instruction, handling this case is
5128 if (REGNO_REG_CLASS (regno
) == PR_REGS
5129 && ! rws_sum
[regno
].written_by_fp
)
5130 /* The predicates of a branch are available within the
5131 same insn group as long as the predicate was written by
5132 something other than a floating-point instruction. */
5136 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5138 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5141 switch (rws_sum
[regno
].write_count
)
5144 /* The register has not been written yet. */
5148 /* The register has been written via a predicate. If this is
5149 not a complementary predicate, then we need a barrier. */
5150 /* ??? This assumes that P and P+1 are always complementary
5151 predicates for P even. */
5152 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5157 /* The register has been unconditionally written already. We
5167 return need_barrier
;
5171 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
5173 int regno
= REGNO (reg
);
5174 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
5177 return rws_access_regno (regno
, flags
, pred
);
5180 int need_barrier
= 0;
5182 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
5183 return need_barrier
;
5187 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5188 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5191 update_set_flags (rtx x
, struct reg_flags
*pflags
)
5193 rtx src
= SET_SRC (x
);
5195 switch (GET_CODE (src
))
5201 /* There are three cases here:
5202 (1) The destination is (pc), in which case this is a branch,
5203 nothing here applies.
5204 (2) The destination is ar.lc, in which case this is a
5205 doloop_end_internal,
5206 (3) The destination is an fp register, in which case this is
5207 an fselect instruction.
5208 In all cases, nothing we do in this function applies. */
5212 if (COMPARISON_P (src
)
5213 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src
, 0))))
5214 /* Set pflags->is_fp to 1 so that we know we're dealing
5215 with a floating point comparison when processing the
5216 destination of the SET. */
5219 /* Discover if this is a parallel comparison. We only handle
5220 and.orcm and or.andcm at present, since we must retain a
5221 strict inverse on the predicate pair. */
5222 else if (GET_CODE (src
) == AND
)
5224 else if (GET_CODE (src
) == IOR
)
5231 /* Subroutine of rtx_needs_barrier; this function determines whether the
5232 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5233 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5237 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
5239 int need_barrier
= 0;
5241 rtx src
= SET_SRC (x
);
5243 if (GET_CODE (src
) == CALL
)
5244 /* We don't need to worry about the result registers that
5245 get written by subroutine call. */
5246 return rtx_needs_barrier (src
, flags
, pred
);
5247 else if (SET_DEST (x
) == pc_rtx
)
5249 /* X is a conditional branch. */
5250 /* ??? This seems redundant, as the caller sets this bit for
5252 flags
.is_branch
= 1;
5253 return rtx_needs_barrier (src
, flags
, pred
);
5256 need_barrier
= rtx_needs_barrier (src
, flags
, pred
);
5259 if (GET_CODE (dst
) == ZERO_EXTRACT
)
5261 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
5262 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
5263 dst
= XEXP (dst
, 0);
5265 return need_barrier
;
5268 /* Handle an access to rtx X of type FLAGS using predicate register
5269 PRED. Return 1 if this access creates a dependency with an earlier
5270 instruction in the same group. */
5273 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
5276 int is_complemented
= 0;
5277 int need_barrier
= 0;
5278 const char *format_ptr
;
5279 struct reg_flags new_flags
;
5287 switch (GET_CODE (x
))
5290 update_set_flags (x
, &new_flags
);
5291 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
);
5292 if (GET_CODE (SET_SRC (x
)) != CALL
)
5294 new_flags
.is_write
= 1;
5295 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
5300 new_flags
.is_write
= 0;
5301 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5303 /* Avoid multiple register writes, in case this is a pattern with
5304 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5305 if (! flags
.is_sibcall
&& ! rws_insn
[REG_AR_CFM
].write_count
)
5307 new_flags
.is_write
= 1;
5308 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
5309 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
5310 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5315 /* X is a predicated instruction. */
5317 cond
= COND_EXEC_TEST (x
);
5319 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
5321 if (GET_CODE (cond
) == EQ
)
5322 is_complemented
= 1;
5323 cond
= XEXP (cond
, 0);
5324 gcc_assert (GET_CODE (cond
) == REG
5325 && REGNO_REG_CLASS (REGNO (cond
)) == PR_REGS
);
5326 pred
= REGNO (cond
);
5327 if (is_complemented
)
5330 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
5331 return need_barrier
;
5335 /* Clobber & use are for earlier compiler-phases only. */
5340 /* We always emit stop bits for traditional asms. We emit stop bits
5341 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5342 if (GET_CODE (x
) != ASM_OPERANDS
5343 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
5345 /* Avoid writing the register multiple times if we have multiple
5346 asm outputs. This avoids a failure in rws_access_reg. */
5347 if (! rws_insn
[REG_VOLATILE
].write_count
)
5349 new_flags
.is_write
= 1;
5350 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
5355 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5356 We cannot just fall through here since then we would be confused
5357 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5358 traditional asms unlike their normal usage. */
5360 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
5361 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
5366 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5368 rtx pat
= XVECEXP (x
, 0, i
);
5369 switch (GET_CODE (pat
))
5372 update_set_flags (pat
, &new_flags
);
5373 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
);
5379 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5390 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5392 rtx pat
= XVECEXP (x
, 0, i
);
5393 if (GET_CODE (pat
) == SET
)
5395 if (GET_CODE (SET_SRC (pat
)) != CALL
)
5397 new_flags
.is_write
= 1;
5398 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
5402 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
5403 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5408 need_barrier
|= rtx_needs_barrier (SUBREG_REG (x
), flags
, pred
);
5411 if (REGNO (x
) == AR_UNAT_REGNUM
)
5413 for (i
= 0; i
< 64; ++i
)
5414 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
5417 need_barrier
= rws_access_reg (x
, flags
, pred
);
5421 /* Find the regs used in memory address computation. */
5422 new_flags
.is_write
= 0;
5423 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5426 case CONST_INT
: case CONST_DOUBLE
: case CONST_VECTOR
:
5427 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
5430 /* Operators with side-effects. */
5431 case POST_INC
: case POST_DEC
:
5432 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
5434 new_flags
.is_write
= 0;
5435 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5436 new_flags
.is_write
= 1;
5437 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5441 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
5443 new_flags
.is_write
= 0;
5444 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5445 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5446 new_flags
.is_write
= 1;
5447 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5450 /* Handle common unary and binary ops for efficiency. */
5451 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
5452 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
5453 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
5454 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5455 case NE
: case EQ
: case GE
: case GT
: case LE
:
5456 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
5457 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5458 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5461 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
5462 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
5463 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
5464 case SQRT
: case FFS
: case POPCOUNT
:
5465 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5469 /* VEC_SELECT's second argument is a PARALLEL with integers that
5470 describe the elements selected. On ia64, those integers are
5471 always constants. Avoid walking the PARALLEL so that we don't
5472 get confused with "normal" parallels and then die. */
5473 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5477 switch (XINT (x
, 1))
5479 case UNSPEC_LTOFF_DTPMOD
:
5480 case UNSPEC_LTOFF_DTPREL
:
5482 case UNSPEC_LTOFF_TPREL
:
5484 case UNSPEC_PRED_REL_MUTEX
:
5485 case UNSPEC_PIC_CALL
:
5487 case UNSPEC_FETCHADD_ACQ
:
5488 case UNSPEC_BSP_VALUE
:
5489 case UNSPEC_FLUSHRS
:
5490 case UNSPEC_BUNDLE_SELECTOR
:
5493 case UNSPEC_GR_SPILL
:
5494 case UNSPEC_GR_RESTORE
:
5496 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
5497 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
5499 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5500 new_flags
.is_write
= (XINT (x
, 1) == UNSPEC_GR_SPILL
);
5501 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
5506 case UNSPEC_FR_SPILL
:
5507 case UNSPEC_FR_RESTORE
:
5508 case UNSPEC_GETF_EXP
:
5509 case UNSPEC_SETF_EXP
:
5511 case UNSPEC_FR_SQRT_RECIP_APPROX
:
5512 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5515 case UNSPEC_FR_RECIP_APPROX
:
5517 case UNSPEC_COPYSIGN
:
5518 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5519 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5522 case UNSPEC_CMPXCHG_ACQ
:
5523 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5524 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
5532 case UNSPEC_VOLATILE
:
5533 switch (XINT (x
, 1))
5536 /* Alloc must always be the first instruction of a group.
5537 We force this by always returning true. */
5538 /* ??? We might get better scheduling if we explicitly check for
5539 input/local/output register dependencies, and modify the
5540 scheduler so that alloc is always reordered to the start of
5541 the current group. We could then eliminate all of the
5542 first_instruction code. */
5543 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5545 new_flags
.is_write
= 1;
5546 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5549 case UNSPECV_SET_BSP
:
5553 case UNSPECV_BLOCKAGE
:
5554 case UNSPECV_INSN_GROUP_BARRIER
:
5556 case UNSPECV_PSAC_ALL
:
5557 case UNSPECV_PSAC_NORMAL
:
5566 new_flags
.is_write
= 0;
5567 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
5568 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5570 new_flags
.is_write
= 1;
5571 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5572 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5576 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
5577 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5578 switch (format_ptr
[i
])
5580 case '0': /* unused field */
5581 case 'i': /* integer */
5582 case 'n': /* note */
5583 case 'w': /* wide integer */
5584 case 's': /* pointer to string */
5585 case 'S': /* optional pointer to string */
5589 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
5594 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
5595 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
5604 return need_barrier
;
5607 /* Clear out the state for group_barrier_needed at the start of a
5608 sequence of insns. */
5611 init_insn_group_barriers (void)
5613 memset (rws_sum
, 0, sizeof (rws_sum
));
5614 first_instruction
= 1;
5617 /* Given the current state, determine whether a group barrier (a stop bit) is
5618 necessary before INSN. Return nonzero if so. This modifies the state to
5619 include the effects of INSN as a side-effect. */
5622 group_barrier_needed (rtx insn
)
5625 int need_barrier
= 0;
5626 struct reg_flags flags
;
5628 memset (&flags
, 0, sizeof (flags
));
5629 switch (GET_CODE (insn
))
5635 /* A barrier doesn't imply an instruction group boundary. */
5639 memset (rws_insn
, 0, sizeof (rws_insn
));
5643 flags
.is_branch
= 1;
5644 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
5645 memset (rws_insn
, 0, sizeof (rws_insn
));
5647 /* Don't bundle a call following another call. */
5648 if ((pat
= prev_active_insn (insn
))
5649 && GET_CODE (pat
) == CALL_INSN
)
5655 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
5659 flags
.is_branch
= 1;
5661 /* Don't bundle a jump following a call. */
5662 if ((pat
= prev_active_insn (insn
))
5663 && GET_CODE (pat
) == CALL_INSN
)
5671 if (GET_CODE (PATTERN (insn
)) == USE
5672 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5673 /* Don't care about USE and CLOBBER "insns"---those are used to
5674 indicate to the optimizer that it shouldn't get rid of
5675 certain operations. */
5678 pat
= PATTERN (insn
);
5680 /* Ug. Hack hacks hacked elsewhere. */
5681 switch (recog_memoized (insn
))
5683 /* We play dependency tricks with the epilogue in order
5684 to get proper schedules. Undo this for dv analysis. */
5685 case CODE_FOR_epilogue_deallocate_stack
:
5686 case CODE_FOR_prologue_allocate_stack
:
5687 pat
= XVECEXP (pat
, 0, 0);
5690 /* The pattern we use for br.cloop confuses the code above.
5691 The second element of the vector is representative. */
5692 case CODE_FOR_doloop_end_internal
:
5693 pat
= XVECEXP (pat
, 0, 1);
5696 /* Doesn't generate code. */
5697 case CODE_FOR_pred_rel_mutex
:
5698 case CODE_FOR_prologue_use
:
5705 memset (rws_insn
, 0, sizeof (rws_insn
));
5706 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
5708 /* Check to see if the previous instruction was a volatile
5711 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
5718 if (first_instruction
&& INSN_P (insn
)
5719 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
5720 && GET_CODE (PATTERN (insn
)) != USE
5721 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5724 first_instruction
= 0;
5727 return need_barrier
;
5730 /* Like group_barrier_needed, but do not clobber the current state. */
5733 safe_group_barrier_needed (rtx insn
)
5735 struct reg_write_state rws_saved
[NUM_REGS
];
5736 int saved_first_instruction
;
5739 memcpy (rws_saved
, rws_sum
, NUM_REGS
* sizeof *rws_saved
);
5740 saved_first_instruction
= first_instruction
;
5742 t
= group_barrier_needed (insn
);
5744 memcpy (rws_sum
, rws_saved
, NUM_REGS
* sizeof *rws_saved
);
5745 first_instruction
= saved_first_instruction
;
5750 /* Scan the current function and insert stop bits as necessary to
5751 eliminate dependencies. This function assumes that a final
5752 instruction scheduling pass has been run which has already
5753 inserted most of the necessary stop bits. This function only
5754 inserts new ones at basic block boundaries, since these are
5755 invisible to the scheduler. */
5758 emit_insn_group_barriers (FILE *dump
)
5762 int insns_since_last_label
= 0;
5764 init_insn_group_barriers ();
5766 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5768 if (GET_CODE (insn
) == CODE_LABEL
)
5770 if (insns_since_last_label
)
5772 insns_since_last_label
= 0;
5774 else if (GET_CODE (insn
) == NOTE
5775 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
5777 if (insns_since_last_label
)
5779 insns_since_last_label
= 0;
5781 else if (GET_CODE (insn
) == INSN
5782 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
5783 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
5785 init_insn_group_barriers ();
5788 else if (INSN_P (insn
))
5790 insns_since_last_label
= 1;
5792 if (group_barrier_needed (insn
))
5797 fprintf (dump
, "Emitting stop before label %d\n",
5798 INSN_UID (last_label
));
5799 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
5802 init_insn_group_barriers ();
5810 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5811 This function has to emit all necessary group barriers. */
5814 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
5818 init_insn_group_barriers ();
5820 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5822 if (GET_CODE (insn
) == BARRIER
)
5824 rtx last
= prev_active_insn (insn
);
5828 if (GET_CODE (last
) == JUMP_INSN
5829 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
5830 last
= prev_active_insn (last
);
5831 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
5832 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
5834 init_insn_group_barriers ();
5836 else if (INSN_P (insn
))
5838 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
5839 init_insn_group_barriers ();
5840 else if (group_barrier_needed (insn
))
5842 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5843 init_insn_group_barriers ();
5844 group_barrier_needed (insn
);
5852 /* Instruction scheduling support. */
5854 #define NR_BUNDLES 10
5856 /* A list of names of all available bundles. */
5858 static const char *bundle_name
[NR_BUNDLES
] =
5864 #if NR_BUNDLES == 10
5874 /* Nonzero if we should insert stop bits into the schedule. */
5876 int ia64_final_schedule
= 0;
5878 /* Codes of the corresponding queried units: */
5880 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
5881 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
5883 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
5884 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
5886 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
5888 /* The following variable value is an insn group barrier. */
5890 static rtx dfa_stop_insn
;
5892 /* The following variable value is the last issued insn. */
5894 static rtx last_scheduled_insn
;
5896 /* The following variable value is size of the DFA state. */
5898 static size_t dfa_state_size
;
5900 /* The following variable value is pointer to a DFA state used as
5901 temporary variable. */
5903 static state_t temp_dfa_state
= NULL
;
5905 /* The following variable value is DFA state after issuing the last
5908 static state_t prev_cycle_state
= NULL
;
5910 /* The following array element values are TRUE if the corresponding
5911 insn requires to add stop bits before it. */
5913 static char *stops_p
;
5915 /* The following variable is used to set up the mentioned above array. */
5917 static int stop_before_p
= 0;
5919 /* The following variable value is length of the arrays `clocks' and
5922 static int clocks_length
;
5924 /* The following array element values are cycles on which the
5925 corresponding insn will be issued. The array is used only for
5930 /* The following array element values are numbers of cycles should be
5931 added to improve insn scheduling for MM_insns for Itanium1. */
5933 static int *add_cycles
;
5935 static rtx
ia64_single_set (rtx
);
5936 static void ia64_emit_insn_before (rtx
, rtx
);
5938 /* Map a bundle number to its pseudo-op. */
5941 get_bundle_name (int b
)
5943 return bundle_name
[b
];
5947 /* Return the maximum number of instructions a cpu can issue. */
5950 ia64_issue_rate (void)
5955 /* Helper function - like single_set, but look inside COND_EXEC. */
5958 ia64_single_set (rtx insn
)
5960 rtx x
= PATTERN (insn
), ret
;
5961 if (GET_CODE (x
) == COND_EXEC
)
5962 x
= COND_EXEC_CODE (x
);
5963 if (GET_CODE (x
) == SET
)
5966 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5967 Although they are not classical single set, the second set is there just
5968 to protect it from moving past FP-relative stack accesses. */
5969 switch (recog_memoized (insn
))
5971 case CODE_FOR_prologue_allocate_stack
:
5972 case CODE_FOR_epilogue_deallocate_stack
:
5973 ret
= XVECEXP (x
, 0, 0);
5977 ret
= single_set_2 (insn
, x
);
5984 /* Adjust the cost of a scheduling dependency. Return the new cost of
5985 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5988 ia64_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5990 enum attr_itanium_class dep_class
;
5991 enum attr_itanium_class insn_class
;
5993 if (REG_NOTE_KIND (link
) != REG_DEP_OUTPUT
)
5996 insn_class
= ia64_safe_itanium_class (insn
);
5997 dep_class
= ia64_safe_itanium_class (dep_insn
);
5998 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
5999 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
6005 /* Like emit_insn_before, but skip cycle_display notes.
6006 ??? When cycle display notes are implemented, update this. */
6009 ia64_emit_insn_before (rtx insn
, rtx before
)
6011 emit_insn_before (insn
, before
);
6014 /* The following function marks insns who produce addresses for load
6015 and store insns. Such insns will be placed into M slots because it
6016 decrease latency time for Itanium1 (see function
6017 `ia64_produce_address_p' and the DFA descriptions). */
6020 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
6022 rtx insn
, link
, next
, next_tail
;
6024 /* Before reload, which_alternative is not set, which means that
6025 ia64_safe_itanium_class will produce wrong results for (at least)
6026 move instructions. */
6027 if (!reload_completed
)
6030 next_tail
= NEXT_INSN (tail
);
6031 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6034 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6036 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
6038 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
6040 if (REG_NOTE_KIND (link
) != REG_DEP_TRUE
)
6042 next
= XEXP (link
, 0);
6043 if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_ST
6044 || ia64_safe_itanium_class (next
) == ITANIUM_CLASS_STF
)
6045 && ia64_st_address_bypass_p (insn
, next
))
6047 else if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_LD
6048 || ia64_safe_itanium_class (next
)
6049 == ITANIUM_CLASS_FLD
)
6050 && ia64_ld_address_bypass_p (insn
, next
))
6053 insn
->call
= link
!= 0;
6057 /* We're beginning a new block. Initialize data structures as necessary. */
6060 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
6061 int sched_verbose ATTRIBUTE_UNUSED
,
6062 int max_ready ATTRIBUTE_UNUSED
)
6064 #ifdef ENABLE_CHECKING
6067 if (reload_completed
)
6068 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
6069 insn
!= current_sched_info
->next_tail
;
6070 insn
= NEXT_INSN (insn
))
6071 gcc_assert (!SCHED_GROUP_P (insn
));
6073 last_scheduled_insn
= NULL_RTX
;
6074 init_insn_group_barriers ();
6077 /* We are about to being issuing insns for this clock cycle.
6078 Override the default sort algorithm to better slot instructions. */
6081 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
6082 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
,
6086 int n_ready
= *pn_ready
;
6087 rtx
*e_ready
= ready
+ n_ready
;
6091 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
6093 if (reorder_type
== 0)
6095 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6097 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
6098 if (insnp
< e_ready
)
6101 enum attr_type t
= ia64_safe_type (insn
);
6102 if (t
== TYPE_UNKNOWN
)
6104 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6105 || asm_noperands (PATTERN (insn
)) >= 0)
6107 rtx lowest
= ready
[n_asms
];
6108 ready
[n_asms
] = insn
;
6114 rtx highest
= ready
[n_ready
- 1];
6115 ready
[n_ready
- 1] = insn
;
6122 if (n_asms
< n_ready
)
6124 /* Some normal insns to process. Skip the asms. */
6128 else if (n_ready
> 0)
6132 if (ia64_final_schedule
)
6135 int nr_need_stop
= 0;
6137 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
6138 if (safe_group_barrier_needed (*insnp
))
6141 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
6143 if (reorder_type
== 0)
6146 /* Move down everything that needs a stop bit, preserving
6148 while (insnp
-- > ready
+ deleted
)
6149 while (insnp
>= ready
+ deleted
)
6152 if (! safe_group_barrier_needed (insn
))
6154 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
6165 /* We are about to being issuing insns for this clock cycle. Override
6166 the default sort algorithm to better slot instructions. */
6169 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
6172 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
6173 pn_ready
, clock_var
, 0);
6176 /* Like ia64_sched_reorder, but called after issuing each insn.
6177 Override the default sort algorithm to better slot instructions. */
6180 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
6181 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
6182 int *pn_ready
, int clock_var
)
6184 if (ia64_tune
== PROCESSOR_ITANIUM
&& reload_completed
&& last_scheduled_insn
)
6185 clocks
[INSN_UID (last_scheduled_insn
)] = clock_var
;
6186 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
6190 /* We are about to issue INSN. Return the number of insns left on the
6191 ready queue that can be issued this cycle. */
6194 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
6195 int sched_verbose ATTRIBUTE_UNUSED
,
6196 rtx insn ATTRIBUTE_UNUSED
,
6197 int can_issue_more ATTRIBUTE_UNUSED
)
6199 last_scheduled_insn
= insn
;
6200 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
6201 if (reload_completed
)
6203 int needed
= group_barrier_needed (insn
);
6205 gcc_assert (!needed
);
6206 if (GET_CODE (insn
) == CALL_INSN
)
6207 init_insn_group_barriers ();
6208 stops_p
[INSN_UID (insn
)] = stop_before_p
;
6214 /* We are choosing insn from the ready queue. Return nonzero if INSN
6218 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
6220 gcc_assert (insn
&& INSN_P (insn
));
6221 return (!reload_completed
6222 || !safe_group_barrier_needed (insn
));
6225 /* The following variable value is pseudo-insn used by the DFA insn
6226 scheduler to change the DFA state when the simulated clock is
6229 static rtx dfa_pre_cycle_insn
;
6231 /* We are about to being issuing INSN. Return nonzero if we cannot
6232 issue it on given cycle CLOCK and return zero if we should not sort
6233 the ready queue on the next clock start. */
6236 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
6237 int clock
, int *sort_p
)
6239 int setup_clocks_p
= FALSE
;
6241 gcc_assert (insn
&& INSN_P (insn
));
6242 if ((reload_completed
&& safe_group_barrier_needed (insn
))
6243 || (last_scheduled_insn
6244 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
6245 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6246 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
6248 init_insn_group_barriers ();
6249 if (verbose
&& dump
)
6250 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
6251 last_clock
== clock
? " + cycle advance" : "");
6253 if (last_clock
== clock
)
6255 state_transition (curr_state
, dfa_stop_insn
);
6256 if (TARGET_EARLY_STOP_BITS
)
6257 *sort_p
= (last_scheduled_insn
== NULL_RTX
6258 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
6263 else if (reload_completed
)
6264 setup_clocks_p
= TRUE
;
6265 if (GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6266 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)
6267 state_reset (curr_state
);
6270 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
6271 state_transition (curr_state
, dfa_stop_insn
);
6272 state_transition (curr_state
, dfa_pre_cycle_insn
);
6273 state_transition (curr_state
, NULL
);
6276 else if (reload_completed
)
6277 setup_clocks_p
= TRUE
;
6278 if (setup_clocks_p
&& ia64_tune
== PROCESSOR_ITANIUM
6279 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6280 && asm_noperands (PATTERN (insn
)) < 0)
6282 enum attr_itanium_class c
= ia64_safe_itanium_class (insn
);
6284 if (c
!= ITANIUM_CLASS_MMMUL
&& c
!= ITANIUM_CLASS_MMSHF
)
6289 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6290 if (REG_NOTE_KIND (link
) == 0)
6292 enum attr_itanium_class dep_class
;
6293 rtx dep_insn
= XEXP (link
, 0);
6295 dep_class
= ia64_safe_itanium_class (dep_insn
);
6296 if ((dep_class
== ITANIUM_CLASS_MMMUL
6297 || dep_class
== ITANIUM_CLASS_MMSHF
)
6298 && last_clock
- clocks
[INSN_UID (dep_insn
)] < 4
6300 || last_clock
- clocks
[INSN_UID (dep_insn
)] < d
))
6301 d
= last_clock
- clocks
[INSN_UID (dep_insn
)];
6304 add_cycles
[INSN_UID (insn
)] = 3 - d
;
6312 /* The following page contains abstract data `bundle states' which are
6313 used for bundling insns (inserting nops and template generation). */
6315 /* The following describes state of insn bundling. */
6319 /* Unique bundle state number to identify them in the debugging
6322 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
6323 /* number nops before and after the insn */
6324 short before_nops_num
, after_nops_num
;
6325 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
6327 int cost
; /* cost of the state in cycles */
6328 int accumulated_insns_num
; /* number of all previous insns including
6329 nops. L is considered as 2 insns */
6330 int branch_deviation
; /* deviation of previous branches from 3rd slots */
6331 struct bundle_state
*next
; /* next state with the same insn_num */
6332 struct bundle_state
*originator
; /* originator (previous insn state) */
6333 /* All bundle states are in the following chain. */
6334 struct bundle_state
*allocated_states_chain
;
6335 /* The DFA State after issuing the insn and the nops. */
6339 /* The following is map insn number to the corresponding bundle state. */
6341 static struct bundle_state
**index_to_bundle_states
;
6343 /* The unique number of next bundle state. */
6345 static int bundle_states_num
;
6347 /* All allocated bundle states are in the following chain. */
6349 static struct bundle_state
*allocated_bundle_states_chain
;
6351 /* All allocated but not used bundle states are in the following
6354 static struct bundle_state
*free_bundle_state_chain
;
6357 /* The following function returns a free bundle state. */
6359 static struct bundle_state
*
6360 get_free_bundle_state (void)
6362 struct bundle_state
*result
;
6364 if (free_bundle_state_chain
!= NULL
)
6366 result
= free_bundle_state_chain
;
6367 free_bundle_state_chain
= result
->next
;
6371 result
= xmalloc (sizeof (struct bundle_state
));
6372 result
->dfa_state
= xmalloc (dfa_state_size
);
6373 result
->allocated_states_chain
= allocated_bundle_states_chain
;
6374 allocated_bundle_states_chain
= result
;
6376 result
->unique_num
= bundle_states_num
++;
6381 /* The following function frees given bundle state. */
6384 free_bundle_state (struct bundle_state
*state
)
6386 state
->next
= free_bundle_state_chain
;
6387 free_bundle_state_chain
= state
;
6390 /* Start work with abstract data `bundle states'. */
6393 initiate_bundle_states (void)
6395 bundle_states_num
= 0;
6396 free_bundle_state_chain
= NULL
;
6397 allocated_bundle_states_chain
= NULL
;
6400 /* Finish work with abstract data `bundle states'. */
6403 finish_bundle_states (void)
6405 struct bundle_state
*curr_state
, *next_state
;
6407 for (curr_state
= allocated_bundle_states_chain
;
6409 curr_state
= next_state
)
6411 next_state
= curr_state
->allocated_states_chain
;
6412 free (curr_state
->dfa_state
);
6417 /* Hash table of the bundle states. The key is dfa_state and insn_num
6418 of the bundle states. */
6420 static htab_t bundle_state_table
;
6422 /* The function returns hash of BUNDLE_STATE. */
6425 bundle_state_hash (const void *bundle_state
)
6427 const struct bundle_state
*state
= (struct bundle_state
*) bundle_state
;
6430 for (result
= i
= 0; i
< dfa_state_size
; i
++)
6431 result
+= (((unsigned char *) state
->dfa_state
) [i
]
6432 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
6433 return result
+ state
->insn_num
;
6436 /* The function returns nonzero if the bundle state keys are equal. */
6439 bundle_state_eq_p (const void *bundle_state_1
, const void *bundle_state_2
)
6441 const struct bundle_state
* state1
= (struct bundle_state
*) bundle_state_1
;
6442 const struct bundle_state
* state2
= (struct bundle_state
*) bundle_state_2
;
6444 return (state1
->insn_num
== state2
->insn_num
6445 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
6446 dfa_state_size
) == 0);
6449 /* The function inserts the BUNDLE_STATE into the hash table. The
6450 function returns nonzero if the bundle has been inserted into the
6451 table. The table contains the best bundle state with given key. */
6454 insert_bundle_state (struct bundle_state
*bundle_state
)
6458 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, 1);
6459 if (*entry_ptr
== NULL
)
6461 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
6462 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
6463 *entry_ptr
= (void *) bundle_state
;
6466 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
6467 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
6468 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
6469 > bundle_state
->accumulated_insns_num
6470 || (((struct bundle_state
*)
6471 *entry_ptr
)->accumulated_insns_num
6472 == bundle_state
->accumulated_insns_num
6473 && ((struct bundle_state
*)
6474 *entry_ptr
)->branch_deviation
6475 > bundle_state
->branch_deviation
))))
6478 struct bundle_state temp
;
6480 temp
= *(struct bundle_state
*) *entry_ptr
;
6481 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
6482 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
6483 *bundle_state
= temp
;
6488 /* Start work with the hash table. */
6491 initiate_bundle_state_table (void)
6493 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
6497 /* Finish work with the hash table. */
6500 finish_bundle_state_table (void)
6502 htab_delete (bundle_state_table
);
6507 /* The following variable is a insn `nop' used to check bundle states
6508 with different number of inserted nops. */
6510 static rtx ia64_nop
;
6512 /* The following function tries to issue NOPS_NUM nops for the current
6513 state without advancing processor cycle. If it failed, the
6514 function returns FALSE and frees the current state. */
6517 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
6521 for (i
= 0; i
< nops_num
; i
++)
6522 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
6524 free_bundle_state (curr_state
);
6530 /* The following function tries to issue INSN for the current
6531 state without advancing processor cycle. If it failed, the
6532 function returns FALSE and frees the current state. */
6535 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
6537 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
6539 free_bundle_state (curr_state
);
6545 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6546 starting with ORIGINATOR without advancing processor cycle. If
6547 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6548 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6549 If it was successful, the function creates new bundle state and
6550 insert into the hash table and into `index_to_bundle_states'. */
6553 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
6554 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
6556 struct bundle_state
*curr_state
;
6558 curr_state
= get_free_bundle_state ();
6559 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
6560 curr_state
->insn
= insn
;
6561 curr_state
->insn_num
= originator
->insn_num
+ 1;
6562 curr_state
->cost
= originator
->cost
;
6563 curr_state
->originator
= originator
;
6564 curr_state
->before_nops_num
= before_nops_num
;
6565 curr_state
->after_nops_num
= 0;
6566 curr_state
->accumulated_insns_num
6567 = originator
->accumulated_insns_num
+ before_nops_num
;
6568 curr_state
->branch_deviation
= originator
->branch_deviation
;
6570 if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
6572 gcc_assert (GET_MODE (insn
) != TImode
);
6573 if (!try_issue_nops (curr_state
, before_nops_num
))
6575 if (!try_issue_insn (curr_state
, insn
))
6577 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
6578 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
6579 && curr_state
->accumulated_insns_num
% 3 != 0)
6581 free_bundle_state (curr_state
);
6585 else if (GET_MODE (insn
) != TImode
)
6587 if (!try_issue_nops (curr_state
, before_nops_num
))
6589 if (!try_issue_insn (curr_state
, insn
))
6591 curr_state
->accumulated_insns_num
++;
6592 gcc_assert (GET_CODE (PATTERN (insn
)) != ASM_INPUT
6593 && asm_noperands (PATTERN (insn
)) < 0);
6595 if (ia64_safe_type (insn
) == TYPE_L
)
6596 curr_state
->accumulated_insns_num
++;
6600 /* If this is an insn that must be first in a group, then don't allow
6601 nops to be emitted before it. Currently, alloc is the only such
6602 supported instruction. */
6603 /* ??? The bundling automatons should handle this for us, but they do
6604 not yet have support for the first_insn attribute. */
6605 if (before_nops_num
> 0 && get_attr_first_insn (insn
) == FIRST_INSN_YES
)
6607 free_bundle_state (curr_state
);
6611 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
6612 state_transition (curr_state
->dfa_state
, NULL
);
6614 if (!try_issue_nops (curr_state
, before_nops_num
))
6616 if (!try_issue_insn (curr_state
, insn
))
6618 curr_state
->accumulated_insns_num
++;
6619 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6620 || asm_noperands (PATTERN (insn
)) >= 0)
6622 /* Finish bundle containing asm insn. */
6623 curr_state
->after_nops_num
6624 = 3 - curr_state
->accumulated_insns_num
% 3;
6625 curr_state
->accumulated_insns_num
6626 += 3 - curr_state
->accumulated_insns_num
% 3;
6628 else if (ia64_safe_type (insn
) == TYPE_L
)
6629 curr_state
->accumulated_insns_num
++;
6631 if (ia64_safe_type (insn
) == TYPE_B
)
6632 curr_state
->branch_deviation
6633 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
6634 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
6636 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
6639 struct bundle_state
*curr_state1
;
6640 struct bundle_state
*allocated_states_chain
;
6642 curr_state1
= get_free_bundle_state ();
6643 dfa_state
= curr_state1
->dfa_state
;
6644 allocated_states_chain
= curr_state1
->allocated_states_chain
;
6645 *curr_state1
= *curr_state
;
6646 curr_state1
->dfa_state
= dfa_state
;
6647 curr_state1
->allocated_states_chain
= allocated_states_chain
;
6648 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
6650 curr_state
= curr_state1
;
6652 if (!try_issue_nops (curr_state
,
6653 3 - curr_state
->accumulated_insns_num
% 3))
6655 curr_state
->after_nops_num
6656 = 3 - curr_state
->accumulated_insns_num
% 3;
6657 curr_state
->accumulated_insns_num
6658 += 3 - curr_state
->accumulated_insns_num
% 3;
6660 if (!insert_bundle_state (curr_state
))
6661 free_bundle_state (curr_state
);
6665 /* The following function returns position in the two window bundle
6669 get_max_pos (state_t state
)
6671 if (cpu_unit_reservation_p (state
, pos_6
))
6673 else if (cpu_unit_reservation_p (state
, pos_5
))
6675 else if (cpu_unit_reservation_p (state
, pos_4
))
6677 else if (cpu_unit_reservation_p (state
, pos_3
))
6679 else if (cpu_unit_reservation_p (state
, pos_2
))
6681 else if (cpu_unit_reservation_p (state
, pos_1
))
6687 /* The function returns code of a possible template for given position
6688 and state. The function should be called only with 2 values of
6689 position equal to 3 or 6. We avoid generating F NOPs by putting
6690 templates containing F insns at the end of the template search
6691 because undocumented anomaly in McKinley derived cores which can
6692 cause stalls if an F-unit insn (including a NOP) is issued within a
6693 six-cycle window after reading certain application registers (such
6694 as ar.bsp). Furthermore, power-considerations also argue against
6695 the use of F-unit instructions unless they're really needed. */
6698 get_template (state_t state
, int pos
)
6703 if (cpu_unit_reservation_p (state
, _0mmi_
))
6705 else if (cpu_unit_reservation_p (state
, _0mii_
))
6707 else if (cpu_unit_reservation_p (state
, _0mmb_
))
6709 else if (cpu_unit_reservation_p (state
, _0mib_
))
6711 else if (cpu_unit_reservation_p (state
, _0mbb_
))
6713 else if (cpu_unit_reservation_p (state
, _0bbb_
))
6715 else if (cpu_unit_reservation_p (state
, _0mmf_
))
6717 else if (cpu_unit_reservation_p (state
, _0mfi_
))
6719 else if (cpu_unit_reservation_p (state
, _0mfb_
))
6721 else if (cpu_unit_reservation_p (state
, _0mlx_
))
6726 if (cpu_unit_reservation_p (state
, _1mmi_
))
6728 else if (cpu_unit_reservation_p (state
, _1mii_
))
6730 else if (cpu_unit_reservation_p (state
, _1mmb_
))
6732 else if (cpu_unit_reservation_p (state
, _1mib_
))
6734 else if (cpu_unit_reservation_p (state
, _1mbb_
))
6736 else if (cpu_unit_reservation_p (state
, _1bbb_
))
6738 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
6740 else if (cpu_unit_reservation_p (state
, _1mfi_
))
6742 else if (cpu_unit_reservation_p (state
, _1mfb_
))
6744 else if (cpu_unit_reservation_p (state
, _1mlx_
))
6753 /* The following function returns an insn important for insn bundling
6754 followed by INSN and before TAIL. */
6757 get_next_important_insn (rtx insn
, rtx tail
)
6759 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
6761 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6762 && GET_CODE (PATTERN (insn
)) != USE
6763 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6768 /* The following function does insn bundling. Bundling means
6769 inserting templates and nop insns to fit insn groups into permitted
6770 templates. Instruction scheduling uses NDFA (non-deterministic
6771 finite automata) encoding informations about the templates and the
6772 inserted nops. Nondeterminism of the automata permits follows
6773 all possible insn sequences very fast.
6775 Unfortunately it is not possible to get information about inserting
6776 nop insns and used templates from the automata states. The
6777 automata only says that we can issue an insn possibly inserting
6778 some nops before it and using some template. Therefore insn
6779 bundling in this function is implemented by using DFA
6780 (deterministic finite automata). We follows all possible insn
6781 sequences by inserting 0-2 nops (that is what the NDFA describe for
6782 insn scheduling) before/after each insn being bundled. We know the
6783 start of simulated processor cycle from insn scheduling (insn
6784 starting a new cycle has TImode).
6786 Simple implementation of insn bundling would create enormous
6787 number of possible insn sequences satisfying information about new
6788 cycle ticks taken from the insn scheduling. To make the algorithm
6789 practical we use dynamic programming. Each decision (about
6790 inserting nops and implicitly about previous decisions) is described
6791 by structure bundle_state (see above). If we generate the same
6792 bundle state (key is automaton state after issuing the insns and
6793 nops for it), we reuse already generated one. As consequence we
6794 reject some decisions which cannot improve the solution and
6795 reduce memory for the algorithm.
6797 When we reach the end of EBB (extended basic block), we choose the
6798 best sequence and then, moving back in EBB, insert templates for
6799 the best alternative. The templates are taken from querying
6800 automaton state for each insn in chosen bundle states.
6802 So the algorithm makes two (forward and backward) passes through
6803 EBB. There is an additional forward pass through EBB for Itanium1
6804 processor. This pass inserts more nops to make dependency between
6805 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6808 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
6810 struct bundle_state
*curr_state
, *next_state
, *best_state
;
6811 rtx insn
, next_insn
;
6813 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
6814 int pos
= 0, max_pos
, template0
, template1
;
6817 enum attr_type type
;
6820 /* Count insns in the EBB. */
6821 for (insn
= NEXT_INSN (prev_head_insn
);
6822 insn
&& insn
!= tail
;
6823 insn
= NEXT_INSN (insn
))
6829 dfa_clean_insn_cache ();
6830 initiate_bundle_state_table ();
6831 index_to_bundle_states
= xmalloc ((insn_num
+ 2)
6832 * sizeof (struct bundle_state
*));
6833 /* First (forward) pass -- generation of bundle states. */
6834 curr_state
= get_free_bundle_state ();
6835 curr_state
->insn
= NULL
;
6836 curr_state
->before_nops_num
= 0;
6837 curr_state
->after_nops_num
= 0;
6838 curr_state
->insn_num
= 0;
6839 curr_state
->cost
= 0;
6840 curr_state
->accumulated_insns_num
= 0;
6841 curr_state
->branch_deviation
= 0;
6842 curr_state
->next
= NULL
;
6843 curr_state
->originator
= NULL
;
6844 state_reset (curr_state
->dfa_state
);
6845 index_to_bundle_states
[0] = curr_state
;
6847 /* Shift cycle mark if it is put on insn which could be ignored. */
6848 for (insn
= NEXT_INSN (prev_head_insn
);
6850 insn
= NEXT_INSN (insn
))
6852 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6853 || GET_CODE (PATTERN (insn
)) == USE
6854 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6855 && GET_MODE (insn
) == TImode
)
6857 PUT_MODE (insn
, VOIDmode
);
6858 for (next_insn
= NEXT_INSN (insn
);
6860 next_insn
= NEXT_INSN (next_insn
))
6861 if (INSN_P (next_insn
)
6862 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
6863 && GET_CODE (PATTERN (next_insn
)) != USE
6864 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
6866 PUT_MODE (next_insn
, TImode
);
6870 /* Froward pass: generation of bundle states. */
6871 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6875 gcc_assert (INSN_P (insn
)
6876 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6877 && GET_CODE (PATTERN (insn
)) != USE
6878 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
6879 type
= ia64_safe_type (insn
);
6880 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6882 index_to_bundle_states
[insn_num
] = NULL
;
6883 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
6885 curr_state
= next_state
)
6887 pos
= curr_state
->accumulated_insns_num
% 3;
6888 next_state
= curr_state
->next
;
6889 /* We must fill up the current bundle in order to start a
6890 subsequent asm insn in a new bundle. Asm insn is always
6891 placed in a separate bundle. */
6893 = (next_insn
!= NULL_RTX
6894 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
6895 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
6896 /* We may fill up the current bundle if it is the cycle end
6897 without a group barrier. */
6899 = (only_bundle_end_p
|| next_insn
== NULL_RTX
6900 || (GET_MODE (next_insn
) == TImode
6901 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
6902 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
6904 /* We need to insert 2 nops for cases like M_MII. To
6905 guarantee issuing all insns on the same cycle for
6906 Itanium 1, we need to issue 2 nops after the first M
6907 insn (MnnMII where n is a nop insn). */
6908 || ((type
== TYPE_M
|| type
== TYPE_A
)
6909 && ia64_tune
== PROCESSOR_ITANIUM
6910 && !bundle_end_p
&& pos
== 1))
6911 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
6913 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
6915 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
6918 gcc_assert (index_to_bundle_states
[insn_num
]);
6919 for (curr_state
= index_to_bundle_states
[insn_num
];
6921 curr_state
= curr_state
->next
)
6922 if (verbose
>= 2 && dump
)
6924 /* This structure is taken from generated code of the
6925 pipeline hazard recognizer (see file insn-attrtab.c).
6926 Please don't forget to change the structure if a new
6927 automaton is added to .md file. */
6930 unsigned short one_automaton_state
;
6931 unsigned short oneb_automaton_state
;
6932 unsigned short two_automaton_state
;
6933 unsigned short twob_automaton_state
;
6938 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6939 curr_state
->unique_num
,
6940 (curr_state
->originator
== NULL
6941 ? -1 : curr_state
->originator
->unique_num
),
6943 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6944 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6945 (ia64_tune
== PROCESSOR_ITANIUM
6946 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6947 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6952 /* We should find a solution because the 2nd insn scheduling has
6954 gcc_assert (index_to_bundle_states
[insn_num
]);
6955 /* Find a state corresponding to the best insn sequence. */
6957 for (curr_state
= index_to_bundle_states
[insn_num
];
6959 curr_state
= curr_state
->next
)
6960 /* We are just looking at the states with fully filled up last
6961 bundle. The first we prefer insn sequences with minimal cost
6962 then with minimal inserted nops and finally with branch insns
6963 placed in the 3rd slots. */
6964 if (curr_state
->accumulated_insns_num
% 3 == 0
6965 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
6966 || (best_state
->cost
== curr_state
->cost
6967 && (curr_state
->accumulated_insns_num
6968 < best_state
->accumulated_insns_num
6969 || (curr_state
->accumulated_insns_num
6970 == best_state
->accumulated_insns_num
6971 && curr_state
->branch_deviation
6972 < best_state
->branch_deviation
)))))
6973 best_state
= curr_state
;
6974 /* Second (backward) pass: adding nops and templates. */
6975 insn_num
= best_state
->before_nops_num
;
6976 template0
= template1
= -1;
6977 for (curr_state
= best_state
;
6978 curr_state
->originator
!= NULL
;
6979 curr_state
= curr_state
->originator
)
6981 insn
= curr_state
->insn
;
6982 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6983 || asm_noperands (PATTERN (insn
)) >= 0);
6985 if (verbose
>= 2 && dump
)
6989 unsigned short one_automaton_state
;
6990 unsigned short oneb_automaton_state
;
6991 unsigned short two_automaton_state
;
6992 unsigned short twob_automaton_state
;
6997 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6998 curr_state
->unique_num
,
6999 (curr_state
->originator
== NULL
7000 ? -1 : curr_state
->originator
->unique_num
),
7002 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
7003 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
7004 (ia64_tune
== PROCESSOR_ITANIUM
7005 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
7006 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
7009 /* Find the position in the current bundle window. The window can
7010 contain at most two bundles. Two bundle window means that
7011 the processor will make two bundle rotation. */
7012 max_pos
= get_max_pos (curr_state
->dfa_state
);
7014 /* The following (negative template number) means that the
7015 processor did one bundle rotation. */
7016 || (max_pos
== 3 && template0
< 0))
7018 /* We are at the end of the window -- find template(s) for
7022 template0
= get_template (curr_state
->dfa_state
, 3);
7025 template1
= get_template (curr_state
->dfa_state
, 3);
7026 template0
= get_template (curr_state
->dfa_state
, 6);
7029 if (max_pos
> 3 && template1
< 0)
7030 /* It may happen when we have the stop inside a bundle. */
7032 gcc_assert (pos
<= 3);
7033 template1
= get_template (curr_state
->dfa_state
, 3);
7037 /* Emit nops after the current insn. */
7038 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
7041 emit_insn_after (nop
, insn
);
7043 gcc_assert (pos
>= 0);
7046 /* We are at the start of a bundle: emit the template
7047 (it should be defined). */
7048 gcc_assert (template0
>= 0);
7049 b
= gen_bundle_selector (GEN_INT (template0
));
7050 ia64_emit_insn_before (b
, nop
);
7051 /* If we have two bundle window, we make one bundle
7052 rotation. Otherwise template0 will be undefined
7053 (negative value). */
7054 template0
= template1
;
7058 /* Move the position backward in the window. Group barrier has
7059 no slot. Asm insn takes all bundle. */
7060 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
7061 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
7062 && asm_noperands (PATTERN (insn
)) < 0)
7064 /* Long insn takes 2 slots. */
7065 if (ia64_safe_type (insn
) == TYPE_L
)
7067 gcc_assert (pos
>= 0);
7069 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
7070 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
7071 && asm_noperands (PATTERN (insn
)) < 0)
7073 /* The current insn is at the bundle start: emit the
7075 gcc_assert (template0
>= 0);
7076 b
= gen_bundle_selector (GEN_INT (template0
));
7077 ia64_emit_insn_before (b
, insn
);
7078 b
= PREV_INSN (insn
);
7080 /* See comment above in analogous place for emitting nops
7082 template0
= template1
;
7085 /* Emit nops after the current insn. */
7086 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
7089 ia64_emit_insn_before (nop
, insn
);
7090 nop
= PREV_INSN (insn
);
7093 gcc_assert (pos
>= 0);
7096 /* See comment above in analogous place for emitting nops
7098 gcc_assert (template0
>= 0);
7099 b
= gen_bundle_selector (GEN_INT (template0
));
7100 ia64_emit_insn_before (b
, insn
);
7101 b
= PREV_INSN (insn
);
7103 template0
= template1
;
7108 if (ia64_tune
== PROCESSOR_ITANIUM
)
7109 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7110 Itanium1 has a strange design, if the distance between an insn
7111 and dependent MM-insn is less 4 then we have a 6 additional
7112 cycles stall. So we make the distance equal to 4 cycles if it
7114 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
7118 gcc_assert (INSN_P (insn
)
7119 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
7120 && GET_CODE (PATTERN (insn
)) != USE
7121 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
7122 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
7123 if (INSN_UID (insn
) < clocks_length
&& add_cycles
[INSN_UID (insn
)])
7124 /* We found a MM-insn which needs additional cycles. */
7130 /* Now we are searching for a template of the bundle in
7131 which the MM-insn is placed and the position of the
7132 insn in the bundle (0, 1, 2). Also we are searching
7133 for that there is a stop before the insn. */
7134 last
= prev_active_insn (insn
);
7135 pred_stop_p
= recog_memoized (last
) == CODE_FOR_insn_group_barrier
;
7137 last
= prev_active_insn (last
);
7139 for (;; last
= prev_active_insn (last
))
7140 if (recog_memoized (last
) == CODE_FOR_bundle_selector
)
7142 template0
= XINT (XVECEXP (PATTERN (last
), 0, 0), 0);
7144 /* The insn is in MLX bundle. Change the template
7145 onto MFI because we will add nops before the
7146 insn. It simplifies subsequent code a lot. */
7148 = gen_bundle_selector (const2_rtx
); /* -> MFI */
7151 else if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
7152 && (ia64_safe_itanium_class (last
)
7153 != ITANIUM_CLASS_IGNORE
))
7155 /* Some check of correctness: the stop is not at the
7156 bundle start, there are no more 3 insns in the bundle,
7157 and the MM-insn is not at the start of bundle with
7159 gcc_assert ((!pred_stop_p
|| n
)
7161 && (template0
!= 9 || !n
));
7162 /* Put nops after the insn in the bundle. */
7163 for (j
= 3 - n
; j
> 0; j
--)
7164 ia64_emit_insn_before (gen_nop (), insn
);
7165 /* It takes into account that we will add more N nops
7166 before the insn lately -- please see code below. */
7167 add_cycles
[INSN_UID (insn
)]--;
7168 if (!pred_stop_p
|| add_cycles
[INSN_UID (insn
)])
7169 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7172 add_cycles
[INSN_UID (insn
)]--;
7173 for (i
= add_cycles
[INSN_UID (insn
)]; i
> 0; i
--)
7175 /* Insert "MII;" template. */
7176 ia64_emit_insn_before (gen_bundle_selector (const0_rtx
),
7178 ia64_emit_insn_before (gen_nop (), insn
);
7179 ia64_emit_insn_before (gen_nop (), insn
);
7182 /* To decrease code size, we use "MI;I;"
7184 ia64_emit_insn_before
7185 (gen_insn_group_barrier (GEN_INT (3)), insn
);
7188 ia64_emit_insn_before (gen_nop (), insn
);
7189 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7192 /* Put the MM-insn in the same slot of a bundle with the
7193 same template as the original one. */
7194 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0
)),
7196 /* To put the insn in the same slot, add necessary number
7198 for (j
= n
; j
> 0; j
--)
7199 ia64_emit_insn_before (gen_nop (), insn
);
7200 /* Put the stop if the original bundle had it. */
7202 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7206 free (index_to_bundle_states
);
7207 finish_bundle_state_table ();
7209 dfa_clean_insn_cache ();
7212 /* The following function is called at the end of scheduling BB or
7213 EBB. After reload, it inserts stop bits and does insn bundling. */
7216 ia64_sched_finish (FILE *dump
, int sched_verbose
)
7219 fprintf (dump
, "// Finishing schedule.\n");
7220 if (!reload_completed
)
7222 if (reload_completed
)
7224 final_emit_insn_group_barriers (dump
);
7225 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
7226 current_sched_info
->next_tail
);
7227 if (sched_verbose
&& dump
)
7228 fprintf (dump
, "// finishing %d-%d\n",
7229 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
7230 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
7236 /* The following function inserts stop bits in scheduled BB or EBB. */
7239 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
7242 int need_barrier_p
= 0;
7243 rtx prev_insn
= NULL_RTX
;
7245 init_insn_group_barriers ();
7247 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7248 insn
!= current_sched_info
->next_tail
;
7249 insn
= NEXT_INSN (insn
))
7251 if (GET_CODE (insn
) == BARRIER
)
7253 rtx last
= prev_active_insn (insn
);
7257 if (GET_CODE (last
) == JUMP_INSN
7258 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
7259 last
= prev_active_insn (last
);
7260 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7261 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
7263 init_insn_group_barriers ();
7265 prev_insn
= NULL_RTX
;
7267 else if (INSN_P (insn
))
7269 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
7271 init_insn_group_barriers ();
7273 prev_insn
= NULL_RTX
;
7275 else if (need_barrier_p
|| group_barrier_needed (insn
))
7277 if (TARGET_EARLY_STOP_BITS
)
7282 last
!= current_sched_info
->prev_head
;
7283 last
= PREV_INSN (last
))
7284 if (INSN_P (last
) && GET_MODE (last
) == TImode
7285 && stops_p
[INSN_UID (last
)])
7287 if (last
== current_sched_info
->prev_head
)
7289 last
= prev_active_insn (last
);
7291 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7292 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7294 init_insn_group_barriers ();
7295 for (last
= NEXT_INSN (last
);
7297 last
= NEXT_INSN (last
))
7299 group_barrier_needed (last
);
7303 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7305 init_insn_group_barriers ();
7307 group_barrier_needed (insn
);
7308 prev_insn
= NULL_RTX
;
7310 else if (recog_memoized (insn
) >= 0)
7312 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
7313 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
7314 || asm_noperands (PATTERN (insn
)) >= 0);
7321 /* If the following function returns TRUE, we will use the the DFA
7325 ia64_first_cycle_multipass_dfa_lookahead (void)
7327 return (reload_completed
? 6 : 4);
7330 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7333 ia64_init_dfa_pre_cycle_insn (void)
7335 if (temp_dfa_state
== NULL
)
7337 dfa_state_size
= state_size ();
7338 temp_dfa_state
= xmalloc (dfa_state_size
);
7339 prev_cycle_state
= xmalloc (dfa_state_size
);
7341 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
7342 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
7343 recog_memoized (dfa_pre_cycle_insn
);
7344 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7345 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
7346 recog_memoized (dfa_stop_insn
);
7349 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7350 used by the DFA insn scheduler. */
7353 ia64_dfa_pre_cycle_insn (void)
7355 return dfa_pre_cycle_insn
;
7358 /* The following function returns TRUE if PRODUCER (of type ilog or
7359 ld) produces address for CONSUMER (of type st or stf). */
7362 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
7366 gcc_assert (producer
&& consumer
);
7367 dest
= ia64_single_set (producer
);
7369 reg
= SET_DEST (dest
);
7371 if (GET_CODE (reg
) == SUBREG
)
7372 reg
= SUBREG_REG (reg
);
7373 gcc_assert (GET_CODE (reg
) == REG
);
7375 dest
= ia64_single_set (consumer
);
7377 mem
= SET_DEST (dest
);
7378 gcc_assert (mem
&& GET_CODE (mem
) == MEM
);
7379 return reg_mentioned_p (reg
, mem
);
7382 /* The following function returns TRUE if PRODUCER (of type ilog or
7383 ld) produces address for CONSUMER (of type ld or fld). */
7386 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
7388 rtx dest
, src
, reg
, mem
;
7390 gcc_assert (producer
&& consumer
);
7391 dest
= ia64_single_set (producer
);
7393 reg
= SET_DEST (dest
);
7395 if (GET_CODE (reg
) == SUBREG
)
7396 reg
= SUBREG_REG (reg
);
7397 gcc_assert (GET_CODE (reg
) == REG
);
7399 src
= ia64_single_set (consumer
);
7401 mem
= SET_SRC (src
);
7403 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
7404 mem
= XVECEXP (mem
, 0, 0);
7405 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
7406 mem
= XEXP (mem
, 0);
7408 /* Note that LO_SUM is used for GOT loads. */
7409 gcc_assert (GET_CODE (mem
) == LO_SUM
|| GET_CODE (mem
) == MEM
);
7411 return reg_mentioned_p (reg
, mem
);
7414 /* The following function returns TRUE if INSN produces address for a
7415 load/store insn. We will place such insns into M slot because it
7416 decreases its latency time. */
7419 ia64_produce_address_p (rtx insn
)
7425 /* Emit pseudo-ops for the assembler to describe predicate relations.
7426 At present this assumes that we only consider predicate pairs to
7427 be mutex, and that the assembler can deduce proper values from
7428 straight-line code. */
7431 emit_predicate_relation_info (void)
7435 FOR_EACH_BB_REVERSE (bb
)
7438 rtx head
= BB_HEAD (bb
);
7440 /* We only need such notes at code labels. */
7441 if (GET_CODE (head
) != CODE_LABEL
)
7443 if (GET_CODE (NEXT_INSN (head
)) == NOTE
7444 && NOTE_LINE_NUMBER (NEXT_INSN (head
)) == NOTE_INSN_BASIC_BLOCK
)
7445 head
= NEXT_INSN (head
);
7447 /* Skip p0, which may be thought to be live due to (reg:DI p0)
7448 grabbing the entire block of predicate registers. */
7449 for (r
= PR_REG (2); r
< PR_REG (64); r
+= 2)
7450 if (REGNO_REG_SET_P (bb
->il
.rtl
->global_live_at_start
, r
))
7452 rtx p
= gen_rtx_REG (BImode
, r
);
7453 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
7454 if (head
== BB_END (bb
))
7460 /* Look for conditional calls that do not return, and protect predicate
7461 relations around them. Otherwise the assembler will assume the call
7462 returns, and complain about uses of call-clobbered predicates after
7464 FOR_EACH_BB_REVERSE (bb
)
7466 rtx insn
= BB_HEAD (bb
);
7470 if (GET_CODE (insn
) == CALL_INSN
7471 && GET_CODE (PATTERN (insn
)) == COND_EXEC
7472 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
7474 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
7475 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
7476 if (BB_HEAD (bb
) == insn
)
7478 if (BB_END (bb
) == insn
)
7482 if (insn
== BB_END (bb
))
7484 insn
= NEXT_INSN (insn
);
7489 /* Perform machine dependent operations on the rtl chain INSNS. */
7494 /* We are freeing block_for_insn in the toplev to keep compatibility
7495 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7496 compute_bb_for_insn ();
7498 /* If optimizing, we'll have split before scheduling. */
7500 split_all_insns (0);
7502 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7503 non-optimizing bootstrap. */
7504 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
7506 if (ia64_flag_schedule_insns2
)
7508 timevar_push (TV_SCHED2
);
7509 ia64_final_schedule
= 1;
7511 initiate_bundle_states ();
7512 ia64_nop
= make_insn_raw (gen_nop ());
7513 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
7514 recog_memoized (ia64_nop
);
7515 clocks_length
= get_max_uid () + 1;
7516 stops_p
= xcalloc (1, clocks_length
);
7517 if (ia64_tune
== PROCESSOR_ITANIUM
)
7519 clocks
= xcalloc (clocks_length
, sizeof (int));
7520 add_cycles
= xcalloc (clocks_length
, sizeof (int));
7522 if (ia64_tune
== PROCESSOR_ITANIUM2
)
7524 pos_1
= get_cpu_unit_code ("2_1");
7525 pos_2
= get_cpu_unit_code ("2_2");
7526 pos_3
= get_cpu_unit_code ("2_3");
7527 pos_4
= get_cpu_unit_code ("2_4");
7528 pos_5
= get_cpu_unit_code ("2_5");
7529 pos_6
= get_cpu_unit_code ("2_6");
7530 _0mii_
= get_cpu_unit_code ("2b_0mii.");
7531 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
7532 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
7533 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
7534 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
7535 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
7536 _0mib_
= get_cpu_unit_code ("2b_0mib.");
7537 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
7538 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
7539 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
7540 _1mii_
= get_cpu_unit_code ("2b_1mii.");
7541 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
7542 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
7543 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
7544 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
7545 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
7546 _1mib_
= get_cpu_unit_code ("2b_1mib.");
7547 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
7548 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
7549 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
7553 pos_1
= get_cpu_unit_code ("1_1");
7554 pos_2
= get_cpu_unit_code ("1_2");
7555 pos_3
= get_cpu_unit_code ("1_3");
7556 pos_4
= get_cpu_unit_code ("1_4");
7557 pos_5
= get_cpu_unit_code ("1_5");
7558 pos_6
= get_cpu_unit_code ("1_6");
7559 _0mii_
= get_cpu_unit_code ("1b_0mii.");
7560 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
7561 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
7562 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
7563 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
7564 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
7565 _0mib_
= get_cpu_unit_code ("1b_0mib.");
7566 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
7567 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
7568 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
7569 _1mii_
= get_cpu_unit_code ("1b_1mii.");
7570 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
7571 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
7572 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
7573 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
7574 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
7575 _1mib_
= get_cpu_unit_code ("1b_1mib.");
7576 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
7577 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
7578 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
7580 schedule_ebbs (dump_file
);
7581 finish_bundle_states ();
7582 if (ia64_tune
== PROCESSOR_ITANIUM
)
7588 emit_insn_group_barriers (dump_file
);
7590 ia64_final_schedule
= 0;
7591 timevar_pop (TV_SCHED2
);
7594 emit_all_insn_group_barriers (dump_file
);
7596 /* A call must not be the last instruction in a function, so that the
7597 return address is still within the function, so that unwinding works
7598 properly. Note that IA-64 differs from dwarf2 on this point. */
7599 if (flag_unwind_tables
|| (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7604 insn
= get_last_insn ();
7605 if (! INSN_P (insn
))
7606 insn
= prev_active_insn (insn
);
7607 /* Skip over insns that expand to nothing. */
7608 while (GET_CODE (insn
) == INSN
&& get_attr_empty (insn
) == EMPTY_YES
)
7610 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
7611 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
7613 insn
= prev_active_insn (insn
);
7615 if (GET_CODE (insn
) == CALL_INSN
)
7618 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7619 emit_insn (gen_break_f ());
7620 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7624 emit_predicate_relation_info ();
7626 if (ia64_flag_var_tracking
)
7628 timevar_push (TV_VAR_TRACKING
);
7629 variable_tracking_main ();
7630 timevar_pop (TV_VAR_TRACKING
);
7634 /* Return true if REGNO is used by the epilogue. */
7637 ia64_epilogue_uses (int regno
)
7642 /* With a call to a function in another module, we will write a new
7643 value to "gp". After returning from such a call, we need to make
7644 sure the function restores the original gp-value, even if the
7645 function itself does not use the gp anymore. */
7646 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
7648 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7649 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7650 /* For functions defined with the syscall_linkage attribute, all
7651 input registers are marked as live at all function exits. This
7652 prevents the register allocator from using the input registers,
7653 which in turn makes it possible to restart a system call after
7654 an interrupt without having to save/restore the input registers.
7655 This also prevents kernel data from leaking to application code. */
7656 return lookup_attribute ("syscall_linkage",
7657 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
7660 /* Conditional return patterns can't represent the use of `b0' as
7661 the return address, so we force the value live this way. */
7665 /* Likewise for ar.pfs, which is used by br.ret. */
7673 /* Return true if REGNO is used by the frame unwinder. */
7676 ia64_eh_uses (int regno
)
7678 if (! reload_completed
)
7681 if (current_frame_info
.reg_save_b0
7682 && regno
== current_frame_info
.reg_save_b0
)
7684 if (current_frame_info
.reg_save_pr
7685 && regno
== current_frame_info
.reg_save_pr
)
7687 if (current_frame_info
.reg_save_ar_pfs
7688 && regno
== current_frame_info
.reg_save_ar_pfs
)
7690 if (current_frame_info
.reg_save_ar_unat
7691 && regno
== current_frame_info
.reg_save_ar_unat
)
7693 if (current_frame_info
.reg_save_ar_lc
7694 && regno
== current_frame_info
.reg_save_ar_lc
)
7700 /* Return true if this goes in small data/bss. */
7702 /* ??? We could also support own long data here. Generating movl/add/ld8
7703 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7704 code faster because there is one less load. This also includes incomplete
7705 types which can't go in sdata/sbss. */
7708 ia64_in_small_data_p (tree exp
)
7710 if (TARGET_NO_SDATA
)
7713 /* We want to merge strings, so we never consider them small data. */
7714 if (TREE_CODE (exp
) == STRING_CST
)
7717 /* Functions are never small data. */
7718 if (TREE_CODE (exp
) == FUNCTION_DECL
)
7721 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
7723 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
7725 if (strcmp (section
, ".sdata") == 0
7726 || strncmp (section
, ".sdata.", 7) == 0
7727 || strncmp (section
, ".gnu.linkonce.s.", 16) == 0
7728 || strcmp (section
, ".sbss") == 0
7729 || strncmp (section
, ".sbss.", 6) == 0
7730 || strncmp (section
, ".gnu.linkonce.sb.", 17) == 0)
7735 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
7737 /* If this is an incomplete type with size 0, then we can't put it
7738 in sdata because it might be too big when completed. */
7739 if (size
> 0 && size
<= ia64_section_threshold
)
7746 /* Output assembly directives for prologue regions. */
7748 /* The current basic block number. */
7750 static bool last_block
;
7752 /* True if we need a copy_state command at the start of the next block. */
7754 static bool need_copy_state
;
7756 /* The function emits unwind directives for the start of an epilogue. */
7759 process_epilogue (void)
7761 /* If this isn't the last block of the function, then we need to label the
7762 current state, and copy it back in at the start of the next block. */
7766 fprintf (asm_out_file
, "\t.label_state %d\n",
7767 ++cfun
->machine
->state_num
);
7768 need_copy_state
= true;
7771 fprintf (asm_out_file
, "\t.restore sp\n");
7774 /* This function processes a SET pattern looking for specific patterns
7775 which result in emitting an assembly directive required for unwinding. */
7778 process_set (FILE *asm_out_file
, rtx pat
)
7780 rtx src
= SET_SRC (pat
);
7781 rtx dest
= SET_DEST (pat
);
7782 int src_regno
, dest_regno
;
7784 /* Look for the ALLOC insn. */
7785 if (GET_CODE (src
) == UNSPEC_VOLATILE
7786 && XINT (src
, 1) == UNSPECV_ALLOC
7787 && GET_CODE (dest
) == REG
)
7789 dest_regno
= REGNO (dest
);
7791 /* If this is the final destination for ar.pfs, then this must
7792 be the alloc in the prologue. */
7793 if (dest_regno
== current_frame_info
.reg_save_ar_pfs
)
7794 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
7795 ia64_dbx_register_number (dest_regno
));
7798 /* This must be an alloc before a sibcall. We must drop the
7799 old frame info. The easiest way to drop the old frame
7800 info is to ensure we had a ".restore sp" directive
7801 followed by a new prologue. If the procedure doesn't
7802 have a memory-stack frame, we'll issue a dummy ".restore
7804 if (current_frame_info
.total_size
== 0 && !frame_pointer_needed
)
7805 /* if haven't done process_epilogue() yet, do it now */
7806 process_epilogue ();
7807 fprintf (asm_out_file
, "\t.prologue\n");
7812 /* Look for SP = .... */
7813 if (GET_CODE (dest
) == REG
&& REGNO (dest
) == STACK_POINTER_REGNUM
)
7815 if (GET_CODE (src
) == PLUS
)
7817 rtx op0
= XEXP (src
, 0);
7818 rtx op1
= XEXP (src
, 1);
7820 gcc_assert (op0
== dest
&& GET_CODE (op1
) == CONST_INT
);
7822 if (INTVAL (op1
) < 0)
7823 fprintf (asm_out_file
, "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
7826 process_epilogue ();
7830 gcc_assert (GET_CODE (src
) == REG
7831 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
);
7832 process_epilogue ();
7838 /* Register move we need to look at. */
7839 if (GET_CODE (dest
) == REG
&& GET_CODE (src
) == REG
)
7841 src_regno
= REGNO (src
);
7842 dest_regno
= REGNO (dest
);
7847 /* Saving return address pointer. */
7848 gcc_assert (dest_regno
== current_frame_info
.reg_save_b0
);
7849 fprintf (asm_out_file
, "\t.save rp, r%d\n",
7850 ia64_dbx_register_number (dest_regno
));
7854 gcc_assert (dest_regno
== current_frame_info
.reg_save_pr
);
7855 fprintf (asm_out_file
, "\t.save pr, r%d\n",
7856 ia64_dbx_register_number (dest_regno
));
7859 case AR_UNAT_REGNUM
:
7860 gcc_assert (dest_regno
== current_frame_info
.reg_save_ar_unat
);
7861 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
7862 ia64_dbx_register_number (dest_regno
));
7866 gcc_assert (dest_regno
== current_frame_info
.reg_save_ar_lc
);
7867 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
7868 ia64_dbx_register_number (dest_regno
));
7871 case STACK_POINTER_REGNUM
:
7872 gcc_assert (dest_regno
== HARD_FRAME_POINTER_REGNUM
7873 && frame_pointer_needed
);
7874 fprintf (asm_out_file
, "\t.vframe r%d\n",
7875 ia64_dbx_register_number (dest_regno
));
7879 /* Everything else should indicate being stored to memory. */
7884 /* Memory store we need to look at. */
7885 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
7891 if (GET_CODE (XEXP (dest
, 0)) == REG
)
7893 base
= XEXP (dest
, 0);
7898 gcc_assert (GET_CODE (XEXP (dest
, 0)) == PLUS
7899 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
);
7900 base
= XEXP (XEXP (dest
, 0), 0);
7901 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
7904 if (base
== hard_frame_pointer_rtx
)
7906 saveop
= ".savepsp";
7911 gcc_assert (base
== stack_pointer_rtx
);
7915 src_regno
= REGNO (src
);
7919 gcc_assert (!current_frame_info
.reg_save_b0
);
7920 fprintf (asm_out_file
, "\t%s rp, %ld\n", saveop
, off
);
7924 gcc_assert (!current_frame_info
.reg_save_pr
);
7925 fprintf (asm_out_file
, "\t%s pr, %ld\n", saveop
, off
);
7929 gcc_assert (!current_frame_info
.reg_save_ar_lc
);
7930 fprintf (asm_out_file
, "\t%s ar.lc, %ld\n", saveop
, off
);
7934 gcc_assert (!current_frame_info
.reg_save_ar_pfs
);
7935 fprintf (asm_out_file
, "\t%s ar.pfs, %ld\n", saveop
, off
);
7938 case AR_UNAT_REGNUM
:
7939 gcc_assert (!current_frame_info
.reg_save_ar_unat
);
7940 fprintf (asm_out_file
, "\t%s ar.unat, %ld\n", saveop
, off
);
7947 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
7948 1 << (src_regno
- GR_REG (4)));
7956 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
7957 1 << (src_regno
- BR_REG (1)));
7964 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
7965 1 << (src_regno
- FR_REG (2)));
7968 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7969 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7970 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7971 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7972 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
7973 1 << (src_regno
- FR_REG (12)));
7985 /* This function looks at a single insn and emits any directives
7986 required to unwind this insn. */
7988 process_for_unwind_directive (FILE *asm_out_file
, rtx insn
)
7990 if (flag_unwind_tables
7991 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7995 if (GET_CODE (insn
) == NOTE
7996 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
7998 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
8000 /* Restore unwind state from immediately before the epilogue. */
8001 if (need_copy_state
)
8003 fprintf (asm_out_file
, "\t.body\n");
8004 fprintf (asm_out_file
, "\t.copy_state %d\n",
8005 cfun
->machine
->state_num
);
8006 need_copy_state
= false;
8010 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
8013 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
8015 pat
= XEXP (pat
, 0);
8017 pat
= PATTERN (insn
);
8019 switch (GET_CODE (pat
))
8022 process_set (asm_out_file
, pat
);
8028 int limit
= XVECLEN (pat
, 0);
8029 for (par_index
= 0; par_index
< limit
; par_index
++)
8031 rtx x
= XVECEXP (pat
, 0, par_index
);
8032 if (GET_CODE (x
) == SET
)
8033 process_set (asm_out_file
, x
);
8048 IA64_BUILTIN_FLUSHRS
8052 ia64_init_builtins (void)
8057 /* The __fpreg type. */
8058 fpreg_type
= make_node (REAL_TYPE
);
8059 /* ??? The back end should know to load/save __fpreg variables using
8060 the ldf.fill and stf.spill instructions. */
8061 TYPE_PRECISION (fpreg_type
) = 80;
8062 layout_type (fpreg_type
);
8063 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
8065 /* The __float80 type. */
8066 float80_type
= make_node (REAL_TYPE
);
8067 TYPE_PRECISION (float80_type
) = 80;
8068 layout_type (float80_type
);
8069 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
8071 /* The __float128 type. */
8074 tree float128_type
= make_node (REAL_TYPE
);
8075 TYPE_PRECISION (float128_type
) = 128;
8076 layout_type (float128_type
);
8077 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
8080 /* Under HPUX, this is a synonym for "long double". */
8081 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
8084 #define def_builtin(name, type, code) \
8085 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, \
8088 def_builtin ("__builtin_ia64_bsp",
8089 build_function_type (ptr_type_node
, void_list_node
),
8092 def_builtin ("__builtin_ia64_flushrs",
8093 build_function_type (void_type_node
, void_list_node
),
8094 IA64_BUILTIN_FLUSHRS
);
8100 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8101 enum machine_mode mode ATTRIBUTE_UNUSED
,
8102 int ignore ATTRIBUTE_UNUSED
)
8104 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8105 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8109 case IA64_BUILTIN_BSP
:
8110 if (! target
|| ! register_operand (target
, DImode
))
8111 target
= gen_reg_rtx (DImode
);
8112 emit_insn (gen_bsp_value (target
));
8113 #ifdef POINTERS_EXTEND_UNSIGNED
8114 target
= convert_memory_address (ptr_mode
, target
);
8118 case IA64_BUILTIN_FLUSHRS
:
8119 emit_insn (gen_flushrs ());
8129 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8130 most significant bits of the stack slot. */
8133 ia64_hpux_function_arg_padding (enum machine_mode mode
, tree type
)
8135 /* Exception to normal case for structures/unions/etc. */
8137 if (type
&& AGGREGATE_TYPE_P (type
)
8138 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
8141 /* Fall back to the default. */
8142 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8145 /* Linked list of all external functions that are to be emitted by GCC.
8146 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8147 order to avoid putting out names that are never really used. */
8149 struct extern_func_list
GTY(())
8151 struct extern_func_list
*next
;
8155 static GTY(()) struct extern_func_list
*extern_func_head
;
8158 ia64_hpux_add_extern_decl (tree decl
)
8160 struct extern_func_list
*p
= ggc_alloc (sizeof (struct extern_func_list
));
8163 p
->next
= extern_func_head
;
8164 extern_func_head
= p
;
8167 /* Print out the list of used global functions. */
8170 ia64_hpux_file_end (void)
8172 struct extern_func_list
*p
;
8174 for (p
= extern_func_head
; p
; p
= p
->next
)
8176 tree decl
= p
->decl
;
8177 tree id
= DECL_ASSEMBLER_NAME (decl
);
8181 if (!TREE_ASM_WRITTEN (decl
) && TREE_SYMBOL_REFERENCED (id
))
8183 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8185 TREE_ASM_WRITTEN (decl
) = 1;
8186 (*targetm
.asm_out
.globalize_label
) (asm_out_file
, name
);
8187 fputs (TYPE_ASM_OP
, asm_out_file
);
8188 assemble_name (asm_out_file
, name
);
8189 fprintf (asm_out_file
, "," TYPE_OPERAND_FMT
"\n", "function");
8193 extern_func_head
= 0;
8196 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
8197 modes of word_mode and larger. Rename the TFmode libfuncs using the
8198 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
8199 backward compatibility. */
8202 ia64_init_libfuncs (void)
8204 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
8205 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
8206 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
8207 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
8209 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
8210 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
8211 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
8212 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
8213 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
8215 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
8216 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
8217 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
8218 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
8219 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
8220 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
8222 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
8223 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
8224 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
8225 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
8227 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
8228 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
8231 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8234 ia64_hpux_init_libfuncs (void)
8236 ia64_init_libfuncs ();
8238 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
8239 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
8240 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
8242 /* ia64_expand_compare uses this. */
8243 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
8245 /* These should never be used. */
8246 set_optab_libfunc (eq_optab
, TFmode
, 0);
8247 set_optab_libfunc (ne_optab
, TFmode
, 0);
8248 set_optab_libfunc (gt_optab
, TFmode
, 0);
8249 set_optab_libfunc (ge_optab
, TFmode
, 0);
8250 set_optab_libfunc (lt_optab
, TFmode
, 0);
8251 set_optab_libfunc (le_optab
, TFmode
, 0);
8254 /* Rename the division and modulus functions in VMS. */
8257 ia64_vms_init_libfuncs (void)
8259 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
8260 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
8261 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
8262 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
8263 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
8264 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
8265 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
8266 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
8269 /* Rename the TFmode libfuncs available from soft-fp in glibc using
8270 the HPUX conventions. */
8273 ia64_sysv4_init_libfuncs (void)
8275 ia64_init_libfuncs ();
8277 /* These functions are not part of the HPUX TFmode interface. We
8278 use them instead of _U_Qfcmp, which doesn't work the way we
8280 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
8281 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
8282 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
8283 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
8284 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
8285 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
8287 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
8288 glibc doesn't have them. */
8291 /* Switch to the section to which we should output X. The only thing
8292 special we do here is to honor small data. */
8295 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
8296 unsigned HOST_WIDE_INT align
)
8298 if (GET_MODE_SIZE (mode
) > 0
8299 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
)
8302 default_elf_select_rtx_section (mode
, x
, align
);
8305 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8306 Pretend flag_pic is always set. */
8309 ia64_rwreloc_select_section (tree exp
, int reloc
, unsigned HOST_WIDE_INT align
)
8311 default_elf_select_section_1 (exp
, reloc
, align
, true);
8315 ia64_rwreloc_unique_section (tree decl
, int reloc
)
8317 default_unique_section_1 (decl
, reloc
, true);
8321 ia64_rwreloc_select_rtx_section (enum machine_mode mode
, rtx x
,
8322 unsigned HOST_WIDE_INT align
)
8324 int save_pic
= flag_pic
;
8326 ia64_select_rtx_section (mode
, x
, align
);
8327 flag_pic
= save_pic
;
8330 #ifndef TARGET_RWRELOC
8331 #define TARGET_RWRELOC flag_pic
8335 ia64_section_type_flags (tree decl
, const char *name
, int reloc
)
8337 unsigned int flags
= 0;
8339 if (strcmp (name
, ".sdata") == 0
8340 || strncmp (name
, ".sdata.", 7) == 0
8341 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
8342 || strncmp (name
, ".sdata2.", 8) == 0
8343 || strncmp (name
, ".gnu.linkonce.s2.", 17) == 0
8344 || strcmp (name
, ".sbss") == 0
8345 || strncmp (name
, ".sbss.", 6) == 0
8346 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
8347 flags
= SECTION_SMALL
;
8349 flags
|= default_section_type_flags_1 (decl
, name
, reloc
, TARGET_RWRELOC
);
8353 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8354 structure type and that the address of that type should be passed
8355 in out0, rather than in r8. */
8358 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
8360 tree ret_type
= TREE_TYPE (fntype
);
8362 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8363 as the structure return address parameter, if the return value
8364 type has a non-trivial copy constructor or destructor. It is not
8365 clear if this same convention should be used for other
8366 programming languages. Until G++ 3.4, we incorrectly used r8 for
8367 these return values. */
8368 return (abi_version_at_least (2)
8370 && TYPE_MODE (ret_type
) == BLKmode
8371 && TREE_ADDRESSABLE (ret_type
)
8372 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
8375 /* Output the assembler code for a thunk function. THUNK_DECL is the
8376 declaration for the thunk function itself, FUNCTION is the decl for
8377 the target function. DELTA is an immediate constant offset to be
8378 added to THIS. If VCALL_OFFSET is nonzero, the word at
8379 *(*this + vcall_offset) should be added to THIS. */
8382 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8383 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8386 rtx
this, insn
, funexp
;
8387 unsigned int this_parmno
;
8388 unsigned int this_regno
;
8390 reload_completed
= 1;
8391 epilogue_completed
= 1;
8393 reset_block_changes ();
8395 /* Set things up as ia64_expand_prologue might. */
8396 last_scratch_gr_reg
= 15;
8398 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
8399 current_frame_info
.spill_cfa_off
= -16;
8400 current_frame_info
.n_input_regs
= 1;
8401 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
8403 /* Mark the end of the (empty) prologue. */
8404 emit_note (NOTE_INSN_PROLOGUE_END
);
8406 /* Figure out whether "this" will be the first parameter (the
8407 typical case) or the second parameter (as happens when the
8408 virtual function returns certain class objects). */
8410 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
8412 this_regno
= IN_REG (this_parmno
);
8413 if (!TARGET_REG_NAMES
)
8414 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
8416 this = gen_rtx_REG (Pmode
, this_regno
);
8419 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
8420 REG_POINTER (tmp
) = 1;
8421 if (delta
&& CONST_OK_FOR_I (delta
))
8423 emit_insn (gen_ptr_extend_plus_imm (this, tmp
, GEN_INT (delta
)));
8427 emit_insn (gen_ptr_extend (this, tmp
));
8430 /* Apply the constant offset, if required. */
8433 rtx delta_rtx
= GEN_INT (delta
);
8435 if (!CONST_OK_FOR_I (delta
))
8437 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8438 emit_move_insn (tmp
, delta_rtx
);
8441 emit_insn (gen_adddi3 (this, this, delta_rtx
));
8444 /* Apply the offset from the vtable, if required. */
8447 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8448 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8452 rtx t
= gen_rtx_REG (ptr_mode
, 2);
8453 REG_POINTER (t
) = 1;
8454 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this));
8455 if (CONST_OK_FOR_I (vcall_offset
))
8457 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
,
8462 emit_insn (gen_ptr_extend (tmp
, t
));
8465 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8469 if (!CONST_OK_FOR_J (vcall_offset
))
8471 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
8472 emit_move_insn (tmp2
, vcall_offset_rtx
);
8473 vcall_offset_rtx
= tmp2
;
8475 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
8479 emit_move_insn (gen_rtx_REG (ptr_mode
, 2),
8480 gen_rtx_MEM (ptr_mode
, tmp
));
8482 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
8484 emit_insn (gen_adddi3 (this, this, tmp
));
8487 /* Generate a tail call to the target function. */
8488 if (! TREE_USED (function
))
8490 assemble_external (function
);
8491 TREE_USED (function
) = 1;
8493 funexp
= XEXP (DECL_RTL (function
), 0);
8494 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8495 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
8496 insn
= get_last_insn ();
8497 SIBLING_CALL_P (insn
) = 1;
8499 /* Code generation for calls relies on splitting. */
8500 reload_completed
= 1;
8501 epilogue_completed
= 1;
8502 try_split (PATTERN (insn
), insn
, 0);
8506 /* Run just enough of rest_of_compilation to get the insns emitted.
8507 There's not really enough bulk here to make other passes such as
8508 instruction scheduling worth while. Note that use_thunk calls
8509 assemble_start_function and assemble_end_function. */
8511 insn_locators_initialize ();
8512 emit_all_insn_group_barriers (NULL
);
8513 insn
= get_insns ();
8514 shorten_branches (insn
);
8515 final_start_function (insn
, file
, 1);
8516 final (insn
, file
, 1);
8517 final_end_function ();
8519 reload_completed
= 0;
8520 epilogue_completed
= 0;
8524 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8527 ia64_struct_value_rtx (tree fntype
,
8528 int incoming ATTRIBUTE_UNUSED
)
8530 if (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
))
8532 return gen_rtx_REG (Pmode
, GR_REG (8));
8536 ia64_scalar_mode_supported_p (enum machine_mode mode
)
8561 ia64_vector_mode_supported_p (enum machine_mode mode
)
8579 ia64_output_function_profiler (FILE *file
, int labelno
)
8582 fputs ("\t.prologue 4, r40\n", file
);
8584 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file
);
8585 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file
);
8587 if (NO_PROFILE_COUNTERS
)
8588 fputs ("\tmov out3 = r0\n\t;;\n", file
);
8592 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8594 if (TARGET_AUTO_PIC
)
8595 fputs ("\tmovl out3 = @gprel(", file
);
8597 fputs ("\taddl out3 = @ltoff(", file
);
8598 assemble_name (file
, buf
);
8599 if (TARGET_AUTO_PIC
)
8600 fputs (")\n\t;;\n", file
);
8602 fputs ("), r1\n\t;;\n", file
);
8605 fputs ("\t.save rp, r42\n", file
);
8606 fputs ("\tmov out2 = b0\n", file
);
8607 fputs ("\t.body\n", file
);
8608 fputs ("\tmov out1 = r1\n", file
);
8609 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file
);
8612 static GTY(()) rtx mcount_func_rtx
;
8614 gen_mcount_func_rtx (void)
8616 if (!mcount_func_rtx
)
8617 mcount_func_rtx
= init_one_libfunc ("_mcount");
8618 return mcount_func_rtx
;
8622 ia64_profile_hook (int labelno
)
8626 if (NO_PROFILE_COUNTERS
)
8631 const char *label_name
;
8632 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8633 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
8634 label
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
8635 SYMBOL_REF_FLAGS (label
) = SYMBOL_FLAG_LOCAL
;
8637 ip
= gen_reg_rtx (Pmode
);
8638 emit_insn (gen_ip_value (ip
));
8639 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL
,
8641 gen_rtx_REG (Pmode
, BR_REG (0)), Pmode
,
8646 /* Return the mangling of TYPE if it is an extended fundamental type. */
8649 ia64_mangle_fundamental_type (tree type
)
8651 /* On HP-UX, "long double" is mangled as "e" so __float128 is
8653 if (!TARGET_HPUX
&& TYPE_MODE (type
) == TFmode
)
8655 /* On HP-UX, "e" is not available as a mangling of __float80 so use
8656 an extended mangling. Elsewhere, "e" is available since long
8657 double is 80 bits. */
8658 if (TYPE_MODE (type
) == XFmode
)
8659 return TARGET_HPUX
? "u9__float80" : "e";
8663 #include "gt-ia64.h"