| blob | 0b32f11d4692951009ef60c93b6eca2eb1364814 |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_INSXH 2)
30 (UNSPEC_MSKXH 3)
31 (UNSPEC_CVTQL 4)
32 (UNSPEC_CVTLQ 5)
33 (UNSPEC_UMK_LAUM 6)
34 (UNSPEC_UMK_LALM 7)
35 (UNSPEC_UMK_LAL 8)
36 (UNSPEC_UMK_LOAD_CIW 9)
37 (UNSPEC_LDGP2 10)
38 (UNSPEC_LITERAL 11)
39 (UNSPEC_LITUSE 12)
40 (UNSPEC_SIBCALL 13)
41 (UNSPEC_SYMBOL 14)
43 ;; TLS Support
44 (UNSPEC_TLSGD_CALL 15)
45 (UNSPEC_TLSLDM_CALL 16)
46 (UNSPEC_TLSGD 17)
47 (UNSPEC_TLSLDM 18)
48 (UNSPEC_DTPREL 19)
49 (UNSPEC_TPREL 20)
50 (UNSPEC_TP 21)
52 ;; Builtins
53 (UNSPEC_CMPBGE 22)
54 (UNSPEC_ZAP 23)
55 (UNSPEC_AMASK 24)
56 (UNSPEC_IMPLVER 25)
57 (UNSPEC_PERR 26)
58 (UNSPEC_COPYSIGN 27)
59 ])
61 ;; UNSPEC_VOLATILE:
63 (define_constants
64 [(UNSPECV_IMB 0)
65 (UNSPECV_BLOCKAGE 1)
66 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
67 (UNSPECV_LONGJMP 3) ; builtin_longjmp
68 (UNSPECV_TRAPB 4)
69 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
70 (UNSPECV_REALIGN 6)
71 (UNSPECV_EHR 7) ; exception_receiver
72 (UNSPECV_MCOUNT 8)
73 (UNSPECV_FORCE_MOV 9)
74 (UNSPECV_LDGP1 10)
75 (UNSPECV_PLDGP2 11) ; prologue ldgp
76 (UNSPECV_SET_TP 12)
77 (UNSPECV_RPCC 13)
78 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
79 (UNSPECV_MB 15)
80 (UNSPECV_LL 16) ; load-locked
81 (UNSPECV_SC 17) ; store-conditional
82 (UNSPECV_ATOMIC 18)
83 (UNSPECV_CMPXCHG 19)
84 (UNSPECV_XCHG 20)
85 ])
87 ;; Where necessary, the suffixes _le and _be are used to distinguish between
88 ;; little-endian and big-endian patterns.
89 ;;
90 ;; Note that the Unicos/Mk assembler does not support the following
91 ;; opcodes: mov, fmov, nop, fnop, unop.
92 \f
93 ;; Processor type -- this attribute must exactly match the processor_type
94 ;; enumeration in alpha.h.
96 (define_attr "tune" "ev4,ev5,ev6"
97 (const (symbol_ref "alpha_tune")))
99 ;; Define an insn type attribute. This is used in function unit delay
100 ;; computations, among other purposes. For the most part, we use the names
101 ;; defined in the EV4 documentation, but add a few that we have to know about
102 ;; separately.
104 (define_attr "type"
105 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
106 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
107 multi,none"
108 (const_string "iadd"))
110 ;; Describe a user's asm statement.
111 (define_asm_attributes
112 [(set_attr "type" "multi")])
114 ;; Define the operand size an insn operates on. Used primarily by mul
115 ;; and div operations that have size dependent timings.
117 (define_attr "opsize" "si,di,udi"
118 (const_string "di"))
120 ;; The TRAP attribute marks instructions that may generate traps
121 ;; (which are imprecise and may need a trapb if software completion
122 ;; is desired).
124 (define_attr "trap" "no,yes"
125 (const_string "no"))
127 ;; The ROUND_SUFFIX attribute marks which instructions require a
128 ;; rounding-mode suffix. The value NONE indicates no suffix,
129 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
131 (define_attr "round_suffix" "none,normal,c"
132 (const_string "none"))
134 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
135 ;; NONE no suffix
136 ;; SU accepts only /su (cmpt et al)
137 ;; SUI accepts only /sui (cvtqt and cvtqs)
138 ;; V_SV accepts /v and /sv (cvtql only)
139 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
140 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
141 ;;
142 ;; The actual suffix emitted is controlled by alpha_fptm.
144 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
145 (const_string "none"))
147 ;; The length of an instruction sequence in bytes.
149 (define_attr "length" ""
150 (const_int 4))
152 ;; The USEGP attribute marks instructions that have relocations that use
153 ;; the GP.
155 (define_attr "usegp" "no,yes"
156 (cond [(eq_attr "type" "ldsym,jsr")
157 (const_string "yes")
158 (eq_attr "type" "ild,fld,ist,fst")
159 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
160 ]
161 (const_string "no")))
163 ;; The CANNOT_COPY attribute marks instructions with relocations that
164 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
165 ;; since they have to stay in 1-1 correspondence with one another. This
166 ;; also includes jsr insns, since they must stay in correspondence with
167 ;; the immediately following gpdisp instructions.
169 (define_attr "cannot_copy" "false,true"
170 (const_string "false"))
171 \f
172 ;; Include scheduling descriptions.
174 (include "ev4.md")
175 (include "ev5.md")
176 (include "ev6.md")
178 \f
179 ;; Include predicate definitions
181 (include "predicates.md")
183 \f
184 ;; First define the arithmetic insns. Note that the 32-bit forms also
185 ;; sign-extend.
187 ;; Handle 32-64 bit extension from memory to a floating point register
188 ;; specially, since this occurs frequently in int->double conversions.
189 ;;
190 ;; Note that while we must retain the =f case in the insn for reload's
191 ;; benefit, it should be eliminated after reload, so we should never emit
192 ;; code for that case. But we don't reject the possibility.
194 (define_expand "extendsidi2"
195 [(set (match_operand:DI 0 "register_operand" "")
196 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
197 ""
198 "")
200 (define_insn "*cvtlq"
201 [(set (match_operand:DI 0 "register_operand" "=f")
202 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
203 UNSPEC_CVTLQ))]
204 ""
205 "cvtlq %1,%0"
206 [(set_attr "type" "fadd")])
208 (define_insn "*extendsidi2_1"
209 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
210 (sign_extend:DI
211 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
212 ""
213 "@
214 addl $31,%1,%0
215 ldl %0,%1
216 lds %0,%1\;cvtlq %0,%0"
217 [(set_attr "type" "iadd,ild,fld")
218 (set_attr "length" "*,*,8")])
220 (define_split
221 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
222 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
223 "reload_completed"
224 [(set (match_dup 2) (match_dup 1))
225 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
226 {
227 operands[1] = adjust_address (operands[1], SFmode, 0);
228 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
229 })
231 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
232 ;; reload when converting fp->int.
234 (define_peephole2
235 [(set (match_operand:SI 0 "hard_int_register_operand" "")
236 (match_operand:SI 1 "memory_operand" ""))
237 (set (match_operand:DI 2 "hard_int_register_operand" "")
238 (sign_extend:DI (match_dup 0)))]
239 "true_regnum (operands[0]) == true_regnum (operands[2])
240 || peep2_reg_dead_p (2, operands[0])"
241 [(set (match_dup 2)
242 (sign_extend:DI (match_dup 1)))]
243 "")
245 ;; Don't say we have addsi3 if optimizing. This generates better code. We
246 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
247 (define_expand "addsi3"
248 [(set (match_operand:SI 0 "register_operand" "")
249 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
250 (match_operand:SI 2 "add_operand" "")))]
251 "! optimize"
252 "")
254 (define_insn "*addsi_internal"
255 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
256 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
257 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
258 ""
259 "@
260 addl %r1,%2,%0
261 subl %r1,%n2,%0
262 lda %0,%2(%r1)
263 ldah %0,%h2(%r1)")
265 (define_split
266 [(set (match_operand:SI 0 "register_operand" "")
267 (plus:SI (match_operand:SI 1 "register_operand" "")
268 (match_operand:SI 2 "const_int_operand" "")))]
269 "! add_operand (operands[2], SImode)"
270 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
271 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
272 {
273 HOST_WIDE_INT val = INTVAL (operands[2]);
274 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
275 HOST_WIDE_INT rest = val - low;
277 operands[3] = GEN_INT (rest);
278 operands[4] = GEN_INT (low);
279 })
281 (define_insn "*addsi_se"
282 [(set (match_operand:DI 0 "register_operand" "=r,r")
283 (sign_extend:DI
284 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
285 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
286 ""
287 "@
288 addl %r1,%2,%0
289 subl %r1,%n2,%0")
291 (define_insn "*addsi_se2"
292 [(set (match_operand:DI 0 "register_operand" "=r,r")
293 (sign_extend:DI
294 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
295 (match_operand:DI 2 "sext_add_operand" "rI,O"))
296 0)))]
297 ""
298 "@
299 addl %r1,%2,%0
300 subl %r1,%n2,%0")
302 (define_split
303 [(set (match_operand:DI 0 "register_operand" "")
304 (sign_extend:DI
305 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
306 (match_operand:SI 2 "const_int_operand" ""))))
307 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
308 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
309 && INTVAL (operands[2]) % 4 == 0"
310 [(set (match_dup 3) (match_dup 4))
311 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
312 (match_dup 5))
313 (match_dup 1))))]
314 {
315 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
316 int mult = 4;
318 if (val % 2 == 0)
319 val /= 2, mult = 8;
321 operands[4] = GEN_INT (val);
322 operands[5] = GEN_INT (mult);
323 })
325 (define_split
326 [(set (match_operand:DI 0 "register_operand" "")
327 (sign_extend:DI
328 (plus:SI (match_operator:SI 1 "comparison_operator"
329 [(match_operand 2 "" "")
330 (match_operand 3 "" "")])
331 (match_operand:SI 4 "add_operand" ""))))
332 (clobber (match_operand:DI 5 "register_operand" ""))]
333 ""
334 [(set (match_dup 5) (match_dup 6))
335 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
336 {
337 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
338 operands[2], operands[3]);
339 operands[7] = gen_lowpart (SImode, operands[5]);
340 })
342 (define_insn "addvsi3"
343 [(set (match_operand:SI 0 "register_operand" "=r,r")
344 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
345 (match_operand:SI 2 "sext_add_operand" "rI,O")))
346 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
347 (sign_extend:DI (match_dup 2)))
348 (sign_extend:DI (plus:SI (match_dup 1)
349 (match_dup 2))))
350 (const_int 0))]
351 ""
352 "@
353 addlv %r1,%2,%0
354 sublv %r1,%n2,%0")
356 (define_expand "adddi3"
357 [(set (match_operand:DI 0 "register_operand" "")
358 (plus:DI (match_operand:DI 1 "register_operand" "")
359 (match_operand:DI 2 "add_operand" "")))]
360 ""
361 "")
363 (define_insn "*adddi_er_lo16_dtp"
364 [(set (match_operand:DI 0 "register_operand" "=r")
365 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
366 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
367 "HAVE_AS_TLS"
368 "lda %0,%2(%1)\t\t!dtprel")
370 (define_insn "*adddi_er_hi32_dtp"
371 [(set (match_operand:DI 0 "register_operand" "=r")
372 (plus:DI (match_operand:DI 1 "register_operand" "r")
373 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
374 "HAVE_AS_TLS"
375 "ldah %0,%2(%1)\t\t!dtprelhi")
377 (define_insn "*adddi_er_lo32_dtp"
378 [(set (match_operand:DI 0 "register_operand" "=r")
379 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
380 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
381 "HAVE_AS_TLS"
382 "lda %0,%2(%1)\t\t!dtprello")
384 (define_insn "*adddi_er_lo16_tp"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
387 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
388 "HAVE_AS_TLS"
389 "lda %0,%2(%1)\t\t!tprel")
391 (define_insn "*adddi_er_hi32_tp"
392 [(set (match_operand:DI 0 "register_operand" "=r")
393 (plus:DI (match_operand:DI 1 "register_operand" "r")
394 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
395 "HAVE_AS_TLS"
396 "ldah %0,%2(%1)\t\t!tprelhi")
398 (define_insn "*adddi_er_lo32_tp"
399 [(set (match_operand:DI 0 "register_operand" "=r")
400 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
401 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
402 "HAVE_AS_TLS"
403 "lda %0,%2(%1)\t\t!tprello")
405 (define_insn "*adddi_er_high_l"
406 [(set (match_operand:DI 0 "register_operand" "=r")
407 (plus:DI (match_operand:DI 1 "register_operand" "r")
408 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
409 "TARGET_EXPLICIT_RELOCS && reload_completed"
410 "ldah %0,%2(%1)\t\t!gprelhigh"
411 [(set_attr "usegp" "yes")])
413 (define_split
414 [(set (match_operand:DI 0 "register_operand" "")
415 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
416 "TARGET_EXPLICIT_RELOCS && reload_completed"
417 [(set (match_dup 0)
418 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
419 "operands[2] = pic_offset_table_rtx;")
421 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
422 ;; With complications like
423 ;;
424 ;; The NT stack unwind code can't handle a subq to adjust the stack
425 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
426 ;; the exception handling code will loop if a subq is used and an
427 ;; exception occurs.
428 ;;
429 ;; The 19980616 change to emit prologues as RTL also confused some
430 ;; versions of GDB, which also interprets prologues. This has been
431 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
432 ;; use lda here.
433 ;;
434 ;; and the fact that the three insns schedule exactly the same, it's
435 ;; just not worth the effort.
437 (define_insn "*adddi_internal"
438 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
439 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
440 (match_operand:DI 2 "add_operand" "r,K,L")))]
441 ""
442 "@
443 addq %1,%2,%0
444 lda %0,%2(%1)
445 ldah %0,%h2(%1)")
447 ;; ??? Allow large constants when basing off the frame pointer or some
448 ;; virtual register that may eliminate to the frame pointer. This is
449 ;; done because register elimination offsets will change the hi/lo split,
450 ;; and if we split before reload, we will require additional instructions.
452 (define_insn "*adddi_fp_hack"
453 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
454 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
455 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
456 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
457 && INTVAL (operands[2]) >= 0
458 /* This is the largest constant an lda+ldah pair can add, minus
459 an upper bound on the displacement between SP and AP during
460 register elimination. See INITIAL_ELIMINATION_OFFSET. */
461 && INTVAL (operands[2])
462 < (0x7fff8000
463 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
464 - ALPHA_ROUND(current_function_outgoing_args_size)
465 - (ALPHA_ROUND (get_frame_size ()
466 + max_reg_num () * UNITS_PER_WORD
467 + current_function_pretend_args_size)
468 - current_function_pretend_args_size))"
469 "@
470 lda %0,%2(%1)
471 ldah %0,%h2(%1)
472 #")
474 ;; Don't do this if we are adjusting SP since we don't want to do it
475 ;; in two steps. Don't split FP sources for the reason listed above.
476 (define_split
477 [(set (match_operand:DI 0 "register_operand" "")
478 (plus:DI (match_operand:DI 1 "register_operand" "")
479 (match_operand:DI 2 "const_int_operand" "")))]
480 "! add_operand (operands[2], DImode)
481 && operands[0] != stack_pointer_rtx
482 && operands[1] != frame_pointer_rtx
483 && operands[1] != arg_pointer_rtx"
484 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
485 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
486 {
487 HOST_WIDE_INT val = INTVAL (operands[2]);
488 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
489 HOST_WIDE_INT rest = val - low;
491 operands[4] = GEN_INT (low);
492 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
493 operands[3] = GEN_INT (rest);
494 else if (! no_new_pseudos)
495 {
496 operands[3] = gen_reg_rtx (DImode);
497 emit_move_insn (operands[3], operands[2]);
498 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
499 DONE;
500 }
501 else
502 FAIL;
503 })
505 (define_insn "*saddl"
506 [(set (match_operand:SI 0 "register_operand" "=r,r")
507 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
508 (match_operand:SI 2 "const48_operand" "I,I"))
509 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
510 ""
511 "@
512 s%2addl %1,%3,%0
513 s%2subl %1,%n3,%0")
515 (define_insn "*saddl_se"
516 [(set (match_operand:DI 0 "register_operand" "=r,r")
517 (sign_extend:DI
518 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
519 (match_operand:SI 2 "const48_operand" "I,I"))
520 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
521 ""
522 "@
523 s%2addl %1,%3,%0
524 s%2subl %1,%n3,%0")
526 (define_split
527 [(set (match_operand:DI 0 "register_operand" "")
528 (sign_extend:DI
529 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
530 [(match_operand 2 "" "")
531 (match_operand 3 "" "")])
532 (match_operand:SI 4 "const48_operand" ""))
533 (match_operand:SI 5 "sext_add_operand" ""))))
534 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
535 ""
536 [(set (match_dup 6) (match_dup 7))
537 (set (match_dup 0)
538 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
539 (match_dup 5))))]
540 {
541 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
542 operands[2], operands[3]);
543 operands[8] = gen_lowpart (SImode, operands[6]);
544 })
546 (define_insn "*saddq"
547 [(set (match_operand:DI 0 "register_operand" "=r,r")
548 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
549 (match_operand:DI 2 "const48_operand" "I,I"))
550 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
551 ""
552 "@
553 s%2addq %1,%3,%0
554 s%2subq %1,%n3,%0")
556 (define_insn "addvdi3"
557 [(set (match_operand:DI 0 "register_operand" "=r,r")
558 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
559 (match_operand:DI 2 "sext_add_operand" "rI,O")))
560 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
561 (sign_extend:TI (match_dup 2)))
562 (sign_extend:TI (plus:DI (match_dup 1)
563 (match_dup 2))))
564 (const_int 0))]
565 ""
566 "@
567 addqv %r1,%2,%0
568 subqv %r1,%n2,%0")
570 (define_insn "negsi2"
571 [(set (match_operand:SI 0 "register_operand" "=r")
572 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
573 ""
574 "subl $31,%1,%0")
576 (define_insn "*negsi_se"
577 [(set (match_operand:DI 0 "register_operand" "=r")
578 (sign_extend:DI (neg:SI
579 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
580 ""
581 "subl $31,%1,%0")
583 (define_insn "negvsi2"
584 [(set (match_operand:SI 0 "register_operand" "=r")
585 (neg:SI (match_operand:SI 1 "register_operand" "r")))
586 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
587 (sign_extend:DI (neg:SI (match_dup 1))))
588 (const_int 0))]
589 ""
590 "sublv $31,%1,%0")
592 (define_insn "negdi2"
593 [(set (match_operand:DI 0 "register_operand" "=r")
594 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
595 ""
596 "subq $31,%1,%0")
598 (define_insn "negvdi2"
599 [(set (match_operand:DI 0 "register_operand" "=r")
600 (neg:DI (match_operand:DI 1 "register_operand" "r")))
601 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
602 (sign_extend:TI (neg:DI (match_dup 1))))
603 (const_int 0))]
604 ""
605 "subqv $31,%1,%0")
607 (define_expand "subsi3"
608 [(set (match_operand:SI 0 "register_operand" "")
609 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
610 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
611 "! optimize"
612 "")
614 (define_insn "*subsi_internal"
615 [(set (match_operand:SI 0 "register_operand" "=r")
616 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
617 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
618 ""
619 "subl %r1,%2,%0")
621 (define_insn "*subsi_se"
622 [(set (match_operand:DI 0 "register_operand" "=r")
623 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
624 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
625 ""
626 "subl %r1,%2,%0")
628 (define_insn "*subsi_se2"
629 [(set (match_operand:DI 0 "register_operand" "=r")
630 (sign_extend:DI
631 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
632 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
633 0)))]
634 ""
635 "subl %r1,%2,%0")
637 (define_insn "subvsi3"
638 [(set (match_operand:SI 0 "register_operand" "=r")
639 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
640 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
641 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
642 (sign_extend:DI (match_dup 2)))
643 (sign_extend:DI (minus:SI (match_dup 1)
644 (match_dup 2))))
645 (const_int 0))]
646 ""
647 "sublv %r1,%2,%0")
649 (define_insn "subdi3"
650 [(set (match_operand:DI 0 "register_operand" "=r")
651 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
652 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
653 ""
654 "subq %r1,%2,%0")
656 (define_insn "*ssubl"
657 [(set (match_operand:SI 0 "register_operand" "=r")
658 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
659 (match_operand:SI 2 "const48_operand" "I"))
660 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
661 ""
662 "s%2subl %1,%3,%0")
664 (define_insn "*ssubl_se"
665 [(set (match_operand:DI 0 "register_operand" "=r")
666 (sign_extend:DI
667 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
668 (match_operand:SI 2 "const48_operand" "I"))
669 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
670 ""
671 "s%2subl %1,%3,%0")
673 (define_insn "*ssubq"
674 [(set (match_operand:DI 0 "register_operand" "=r")
675 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
676 (match_operand:DI 2 "const48_operand" "I"))
677 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
678 ""
679 "s%2subq %1,%3,%0")
681 (define_insn "subvdi3"
682 [(set (match_operand:DI 0 "register_operand" "=r")
683 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
684 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
685 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
686 (sign_extend:TI (match_dup 2)))
687 (sign_extend:TI (minus:DI (match_dup 1)
688 (match_dup 2))))
689 (const_int 0))]
690 ""
691 "subqv %r1,%2,%0")
693 ;; The Unicos/Mk assembler doesn't support mull.
695 (define_insn "mulsi3"
696 [(set (match_operand:SI 0 "register_operand" "=r")
697 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
698 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
699 "!TARGET_ABI_UNICOSMK"
700 "mull %r1,%2,%0"
701 [(set_attr "type" "imul")
702 (set_attr "opsize" "si")])
704 (define_insn "*mulsi_se"
705 [(set (match_operand:DI 0 "register_operand" "=r")
706 (sign_extend:DI
707 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
708 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
709 "!TARGET_ABI_UNICOSMK"
710 "mull %r1,%2,%0"
711 [(set_attr "type" "imul")
712 (set_attr "opsize" "si")])
714 (define_insn "mulvsi3"
715 [(set (match_operand:SI 0 "register_operand" "=r")
716 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
717 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
718 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
719 (sign_extend:DI (match_dup 2)))
720 (sign_extend:DI (mult:SI (match_dup 1)
721 (match_dup 2))))
722 (const_int 0))]
723 "!TARGET_ABI_UNICOSMK"
724 "mullv %r1,%2,%0"
725 [(set_attr "type" "imul")
726 (set_attr "opsize" "si")])
728 (define_insn "muldi3"
729 [(set (match_operand:DI 0 "register_operand" "=r")
730 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
731 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
732 ""
733 "mulq %r1,%2,%0"
734 [(set_attr "type" "imul")])
736 (define_insn "mulvdi3"
737 [(set (match_operand:DI 0 "register_operand" "=r")
738 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
739 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
740 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
741 (sign_extend:TI (match_dup 2)))
742 (sign_extend:TI (mult:DI (match_dup 1)
743 (match_dup 2))))
744 (const_int 0))]
745 ""
746 "mulqv %r1,%2,%0"
747 [(set_attr "type" "imul")])
749 (define_expand "umuldi3_highpart"
750 [(set (match_operand:DI 0 "register_operand" "")
751 (truncate:DI
752 (lshiftrt:TI
753 (mult:TI (zero_extend:TI
754 (match_operand:DI 1 "register_operand" ""))
755 (match_operand:DI 2 "reg_or_8bit_operand" ""))
756 (const_int 64))))]
757 ""
758 {
759 if (REG_P (operands[2]))
760 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
761 })
763 (define_insn "*umuldi3_highpart_reg"
764 [(set (match_operand:DI 0 "register_operand" "=r")
765 (truncate:DI
766 (lshiftrt:TI
767 (mult:TI (zero_extend:TI
768 (match_operand:DI 1 "register_operand" "r"))
769 (zero_extend:TI
770 (match_operand:DI 2 "register_operand" "r")))
771 (const_int 64))))]
772 ""
773 "umulh %1,%2,%0"
774 [(set_attr "type" "imul")
775 (set_attr "opsize" "udi")])
777 (define_insn "*umuldi3_highpart_const"
778 [(set (match_operand:DI 0 "register_operand" "=r")
779 (truncate:DI
780 (lshiftrt:TI
781 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
782 (match_operand:TI 2 "cint8_operand" "I"))
783 (const_int 64))))]
784 ""
785 "umulh %1,%2,%0"
786 [(set_attr "type" "imul")
787 (set_attr "opsize" "udi")])
788 \f
789 ;; The divide and remainder operations take their inputs from r24 and
790 ;; r25, put their output in r27, and clobber r23 and r28 on all
791 ;; systems except Unicos/Mk. On Unicos, the standard library provides
792 ;; subroutines which use the standard calling convention and work on
793 ;; DImode operands.
795 ;; ??? Force sign-extension here because some versions of OSF/1 and
796 ;; Interix/NT don't do the right thing if the inputs are not properly
797 ;; sign-extended. But Linux, for instance, does not have this
798 ;; problem. Is it worth the complication here to eliminate the sign
799 ;; extension?
801 (define_expand "divsi3"
802 [(set (match_dup 3)
803 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
804 (set (match_dup 4)
805 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
806 (parallel [(set (match_dup 5)
807 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
808 (clobber (reg:DI 23))
809 (clobber (reg:DI 28))])
810 (set (match_operand:SI 0 "nonimmediate_operand" "")
811 (subreg:SI (match_dup 5) 0))]
812 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
813 {
814 operands[3] = gen_reg_rtx (DImode);
815 operands[4] = gen_reg_rtx (DImode);
816 operands[5] = gen_reg_rtx (DImode);
817 })
819 (define_expand "udivsi3"
820 [(set (match_dup 3)
821 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
822 (set (match_dup 4)
823 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
824 (parallel [(set (match_dup 5)
825 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
826 (clobber (reg:DI 23))
827 (clobber (reg:DI 28))])
828 (set (match_operand:SI 0 "nonimmediate_operand" "")
829 (subreg:SI (match_dup 5) 0))]
830 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
831 {
832 operands[3] = gen_reg_rtx (DImode);
833 operands[4] = gen_reg_rtx (DImode);
834 operands[5] = gen_reg_rtx (DImode);
835 })
837 (define_expand "modsi3"
838 [(set (match_dup 3)
839 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
840 (set (match_dup 4)
841 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
842 (parallel [(set (match_dup 5)
843 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
844 (clobber (reg:DI 23))
845 (clobber (reg:DI 28))])
846 (set (match_operand:SI 0 "nonimmediate_operand" "")
847 (subreg:SI (match_dup 5) 0))]
848 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
849 {
850 operands[3] = gen_reg_rtx (DImode);
851 operands[4] = gen_reg_rtx (DImode);
852 operands[5] = gen_reg_rtx (DImode);
853 })
855 (define_expand "umodsi3"
856 [(set (match_dup 3)
857 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
858 (set (match_dup 4)
859 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
860 (parallel [(set (match_dup 5)
861 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
862 (clobber (reg:DI 23))
863 (clobber (reg:DI 28))])
864 (set (match_operand:SI 0 "nonimmediate_operand" "")
865 (subreg:SI (match_dup 5) 0))]
866 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
867 {
868 operands[3] = gen_reg_rtx (DImode);
869 operands[4] = gen_reg_rtx (DImode);
870 operands[5] = gen_reg_rtx (DImode);
871 })
873 (define_expand "divdi3"
874 [(parallel [(set (match_operand:DI 0 "register_operand" "")
875 (div:DI (match_operand:DI 1 "register_operand" "")
876 (match_operand:DI 2 "register_operand" "")))
877 (clobber (reg:DI 23))
878 (clobber (reg:DI 28))])]
879 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
880 "")
882 (define_expand "udivdi3"
883 [(parallel [(set (match_operand:DI 0 "register_operand" "")
884 (udiv:DI (match_operand:DI 1 "register_operand" "")
885 (match_operand:DI 2 "register_operand" "")))
886 (clobber (reg:DI 23))
887 (clobber (reg:DI 28))])]
888 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
889 "")
891 (define_expand "moddi3"
892 [(use (match_operand:DI 0 "register_operand" ""))
893 (use (match_operand:DI 1 "register_operand" ""))
894 (use (match_operand:DI 2 "register_operand" ""))]
895 "!TARGET_ABI_OPEN_VMS"
896 {
897 if (TARGET_ABI_UNICOSMK)
898 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
899 else
900 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
901 DONE;
902 })
904 (define_expand "moddi3_dft"
905 [(parallel [(set (match_operand:DI 0 "register_operand" "")
906 (mod:DI (match_operand:DI 1 "register_operand" "")
907 (match_operand:DI 2 "register_operand" "")))
908 (clobber (reg:DI 23))
909 (clobber (reg:DI 28))])]
910 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
911 "")
913 ;; On Unicos/Mk, we do as the system's C compiler does:
914 ;; compute the quotient, multiply and subtract.
916 (define_expand "moddi3_umk"
917 [(use (match_operand:DI 0 "register_operand" ""))
918 (use (match_operand:DI 1 "register_operand" ""))
919 (use (match_operand:DI 2 "register_operand" ""))]
920 "TARGET_ABI_UNICOSMK"
921 {
922 rtx div, mul = gen_reg_rtx (DImode);
924 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
925 NULL_RTX, 0, OPTAB_LIB);
926 div = force_reg (DImode, div);
927 emit_insn (gen_muldi3 (mul, operands[2], div));
928 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
929 DONE;
930 })
932 (define_expand "umoddi3"
933 [(use (match_operand:DI 0 "register_operand" ""))
934 (use (match_operand:DI 1 "register_operand" ""))
935 (use (match_operand:DI 2 "register_operand" ""))]
936 "! TARGET_ABI_OPEN_VMS"
937 {
938 if (TARGET_ABI_UNICOSMK)
939 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
940 else
941 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
942 DONE;
943 })
945 (define_expand "umoddi3_dft"
946 [(parallel [(set (match_operand:DI 0 "register_operand" "")
947 (umod:DI (match_operand:DI 1 "register_operand" "")
948 (match_operand:DI 2 "register_operand" "")))
949 (clobber (reg:DI 23))
950 (clobber (reg:DI 28))])]
951 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
952 "")
954 (define_expand "umoddi3_umk"
955 [(use (match_operand:DI 0 "register_operand" ""))
956 (use (match_operand:DI 1 "register_operand" ""))
957 (use (match_operand:DI 2 "register_operand" ""))]
958 "TARGET_ABI_UNICOSMK"
959 {
960 rtx div, mul = gen_reg_rtx (DImode);
962 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
963 NULL_RTX, 1, OPTAB_LIB);
964 div = force_reg (DImode, div);
965 emit_insn (gen_muldi3 (mul, operands[2], div));
966 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
967 DONE;
968 })
970 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
971 ;; expanded by the assembler.
973 (define_insn_and_split "*divmodsi_internal_er"
974 [(set (match_operand:DI 0 "register_operand" "=c")
975 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
976 [(match_operand:DI 1 "register_operand" "a")
977 (match_operand:DI 2 "register_operand" "b")])))
978 (clobber (reg:DI 23))
979 (clobber (reg:DI 28))]
980 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
981 "#"
982 "&& reload_completed"
983 [(parallel [(set (match_dup 0)
984 (sign_extend:DI (match_dup 3)))
985 (use (match_dup 0))
986 (use (match_dup 4))
987 (clobber (reg:DI 23))
988 (clobber (reg:DI 28))])]
989 {
990 const char *str;
991 switch (GET_CODE (operands[3]))
992 {
993 case DIV:
994 str = "__divl";
995 break;
996 case UDIV:
997 str = "__divlu";
998 break;
999 case MOD:
1000 str = "__reml";
1001 break;
1002 case UMOD:
1003 str = "__remlu";
1004 break;
1005 default:
1006 gcc_unreachable ();
1007 }
1008 operands[4] = GEN_INT (alpha_next_sequence_number++);
1009 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1010 gen_rtx_SYMBOL_REF (DImode, str),
1011 operands[4]));
1012 }
1013 [(set_attr "type" "jsr")
1014 (set_attr "length" "8")])
1016 (define_insn "*divmodsi_internal_er_1"
1017 [(set (match_operand:DI 0 "register_operand" "=c")
1018 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1019 [(match_operand:DI 1 "register_operand" "a")
1020 (match_operand:DI 2 "register_operand" "b")])))
1021 (use (match_operand:DI 4 "register_operand" "c"))
1022 (use (match_operand 5 "const_int_operand" ""))
1023 (clobber (reg:DI 23))
1024 (clobber (reg:DI 28))]
1025 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1026 "jsr $23,($27),__%E3%j5"
1027 [(set_attr "type" "jsr")
1028 (set_attr "length" "4")])
1030 (define_insn "*divmodsi_internal"
1031 [(set (match_operand:DI 0 "register_operand" "=c")
1032 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1033 [(match_operand:DI 1 "register_operand" "a")
1034 (match_operand:DI 2 "register_operand" "b")])))
1035 (clobber (reg:DI 23))
1036 (clobber (reg:DI 28))]
1037 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1038 "%E3 %1,%2,%0"
1039 [(set_attr "type" "jsr")
1040 (set_attr "length" "8")])
1042 (define_insn_and_split "*divmoddi_internal_er"
1043 [(set (match_operand:DI 0 "register_operand" "=c")
1044 (match_operator:DI 3 "divmod_operator"
1045 [(match_operand:DI 1 "register_operand" "a")
1046 (match_operand:DI 2 "register_operand" "b")]))
1047 (clobber (reg:DI 23))
1048 (clobber (reg:DI 28))]
1049 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1050 "#"
1051 "&& reload_completed"
1052 [(parallel [(set (match_dup 0) (match_dup 3))
1053 (use (match_dup 0))
1054 (use (match_dup 4))
1055 (clobber (reg:DI 23))
1056 (clobber (reg:DI 28))])]
1057 {
1058 const char *str;
1059 switch (GET_CODE (operands[3]))
1060 {
1061 case DIV:
1062 str = "__divq";
1063 break;
1064 case UDIV:
1065 str = "__divqu";
1066 break;
1067 case MOD:
1068 str = "__remq";
1069 break;
1070 case UMOD:
1071 str = "__remqu";
1072 break;
1073 default:
1074 gcc_unreachable ();
1075 }
1076 operands[4] = GEN_INT (alpha_next_sequence_number++);
1077 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1078 gen_rtx_SYMBOL_REF (DImode, str),
1079 operands[4]));
1080 }
1081 [(set_attr "type" "jsr")
1082 (set_attr "length" "8")])
1084 (define_insn "*divmoddi_internal_er_1"
1085 [(set (match_operand:DI 0 "register_operand" "=c")
1086 (match_operator:DI 3 "divmod_operator"
1087 [(match_operand:DI 1 "register_operand" "a")
1088 (match_operand:DI 2 "register_operand" "b")]))
1089 (use (match_operand:DI 4 "register_operand" "c"))
1090 (use (match_operand 5 "const_int_operand" ""))
1091 (clobber (reg:DI 23))
1092 (clobber (reg:DI 28))]
1093 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1094 "jsr $23,($27),__%E3%j5"
1095 [(set_attr "type" "jsr")
1096 (set_attr "length" "4")])
1098 (define_insn "*divmoddi_internal"
1099 [(set (match_operand:DI 0 "register_operand" "=c")
1100 (match_operator:DI 3 "divmod_operator"
1101 [(match_operand:DI 1 "register_operand" "a")
1102 (match_operand:DI 2 "register_operand" "b")]))
1103 (clobber (reg:DI 23))
1104 (clobber (reg:DI 28))]
1105 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1106 "%E3 %1,%2,%0"
1107 [(set_attr "type" "jsr")
1108 (set_attr "length" "8")])
1109 \f
1110 ;; Next are the basic logical operations. We only expose the DImode operations
1111 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1112 ;; the atomic operation splitters.
1114 (define_insn "*andsi_internal"
1115 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1116 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1117 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1118 ""
1119 "@
1120 and %r1,%2,%0
1121 bic %r1,%N2,%0
1122 zapnot %r1,%m2,%0"
1123 [(set_attr "type" "ilog,ilog,shift")])
1125 (define_insn "anddi3"
1126 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1127 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1128 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1129 ""
1130 "@
1131 and %r1,%2,%0
1132 bic %r1,%N2,%0
1133 zapnot %r1,%m2,%0"
1134 [(set_attr "type" "ilog,ilog,shift")])
1136 ;; There are times when we can split an AND into two AND insns. This occurs
1137 ;; when we can first clear any bytes and then clear anything else. For
1138 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1139 ;; Only do this when running on 64-bit host since the computations are
1140 ;; too messy otherwise.
1142 (define_split
1143 [(set (match_operand:DI 0 "register_operand" "")
1144 (and:DI (match_operand:DI 1 "register_operand" "")
1145 (match_operand:DI 2 "const_int_operand" "")))]
1146 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1147 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1148 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1149 {
1150 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1151 unsigned HOST_WIDE_INT mask2 = mask1;
1152 int i;
1154 /* For each byte that isn't all zeros, make it all ones. */
1155 for (i = 0; i < 64; i += 8)
1156 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1157 mask1 |= (HOST_WIDE_INT) 0xff << i;
1159 /* Now turn on any bits we've just turned off. */
1160 mask2 |= ~ mask1;
1162 operands[3] = GEN_INT (mask1);
1163 operands[4] = GEN_INT (mask2);
1164 })
1166 (define_expand "zero_extendqihi2"
1167 [(set (match_operand:HI 0 "register_operand" "")
1168 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1169 ""
1170 {
1171 if (! TARGET_BWX)
1172 operands[1] = force_reg (QImode, operands[1]);
1173 })
1175 (define_insn "*zero_extendqihi2_bwx"
1176 [(set (match_operand:HI 0 "register_operand" "=r,r")
1177 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1178 "TARGET_BWX"
1179 "@
1180 and %1,0xff,%0
1181 ldbu %0,%1"
1182 [(set_attr "type" "ilog,ild")])
1184 (define_insn "*zero_extendqihi2_nobwx"
1185 [(set (match_operand:HI 0 "register_operand" "=r")
1186 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1187 "! TARGET_BWX"
1188 "and %1,0xff,%0"
1189 [(set_attr "type" "ilog")])
1191 (define_expand "zero_extendqisi2"
1192 [(set (match_operand:SI 0 "register_operand" "")
1193 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1194 ""
1195 {
1196 if (! TARGET_BWX)
1197 operands[1] = force_reg (QImode, operands[1]);
1198 })
1200 (define_insn "*zero_extendqisi2_bwx"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1203 "TARGET_BWX"
1204 "@
1205 and %1,0xff,%0
1206 ldbu %0,%1"
1207 [(set_attr "type" "ilog,ild")])
1209 (define_insn "*zero_extendqisi2_nobwx"
1210 [(set (match_operand:SI 0 "register_operand" "=r")
1211 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1212 "! TARGET_BWX"
1213 "and %1,0xff,%0"
1214 [(set_attr "type" "ilog")])
1216 (define_expand "zero_extendqidi2"
1217 [(set (match_operand:DI 0 "register_operand" "")
1218 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1219 ""
1220 {
1221 if (! TARGET_BWX)
1222 operands[1] = force_reg (QImode, operands[1]);
1223 })
1225 (define_insn "*zero_extendqidi2_bwx"
1226 [(set (match_operand:DI 0 "register_operand" "=r,r")
1227 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1228 "TARGET_BWX"
1229 "@
1230 and %1,0xff,%0
1231 ldbu %0,%1"
1232 [(set_attr "type" "ilog,ild")])
1234 (define_insn "*zero_extendqidi2_nobwx"
1235 [(set (match_operand:DI 0 "register_operand" "=r")
1236 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1237 "! TARGET_BWX"
1238 "and %1,0xff,%0"
1239 [(set_attr "type" "ilog")])
1241 (define_expand "zero_extendhisi2"
1242 [(set (match_operand:SI 0 "register_operand" "")
1243 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1244 ""
1245 {
1246 if (! TARGET_BWX)
1247 operands[1] = force_reg (HImode, operands[1]);
1248 })
1250 (define_insn "*zero_extendhisi2_bwx"
1251 [(set (match_operand:SI 0 "register_operand" "=r,r")
1252 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1253 "TARGET_BWX"
1254 "@
1255 zapnot %1,3,%0
1256 ldwu %0,%1"
1257 [(set_attr "type" "shift,ild")])
1259 (define_insn "*zero_extendhisi2_nobwx"
1260 [(set (match_operand:SI 0 "register_operand" "=r")
1261 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1262 "! TARGET_BWX"
1263 "zapnot %1,3,%0"
1264 [(set_attr "type" "shift")])
1266 (define_expand "zero_extendhidi2"
1267 [(set (match_operand:DI 0 "register_operand" "")
1268 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1269 ""
1270 {
1271 if (! TARGET_BWX)
1272 operands[1] = force_reg (HImode, operands[1]);
1273 })
1275 (define_insn "*zero_extendhidi2_bwx"
1276 [(set (match_operand:DI 0 "register_operand" "=r,r")
1277 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1278 "TARGET_BWX"
1279 "@
1280 zapnot %1,3,%0
1281 ldwu %0,%1"
1282 [(set_attr "type" "shift,ild")])
1284 (define_insn "*zero_extendhidi2_nobwx"
1285 [(set (match_operand:DI 0 "register_operand" "=r")
1286 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1287 ""
1288 "zapnot %1,3,%0"
1289 [(set_attr "type" "shift")])
1291 (define_insn "zero_extendsidi2"
1292 [(set (match_operand:DI 0 "register_operand" "=r")
1293 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1294 ""
1295 "zapnot %1,15,%0"
1296 [(set_attr "type" "shift")])
1298 (define_insn "*andnotsi3"
1299 [(set (match_operand:SI 0 "register_operand" "=r")
1300 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1301 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1302 ""
1303 "bic %r2,%1,%0"
1304 [(set_attr "type" "ilog")])
1306 (define_insn "andnotdi3"
1307 [(set (match_operand:DI 0 "register_operand" "=r")
1308 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1309 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1310 ""
1311 "bic %r2,%1,%0"
1312 [(set_attr "type" "ilog")])
1314 (define_insn "*iorsi_internal"
1315 [(set (match_operand:SI 0 "register_operand" "=r,r")
1316 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1317 (match_operand:SI 2 "or_operand" "rI,N")))]
1318 ""
1319 "@
1320 bis %r1,%2,%0
1321 ornot %r1,%N2,%0"
1322 [(set_attr "type" "ilog")])
1324 (define_insn "iordi3"
1325 [(set (match_operand:DI 0 "register_operand" "=r,r")
1326 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1327 (match_operand:DI 2 "or_operand" "rI,N")))]
1328 ""
1329 "@
1330 bis %r1,%2,%0
1331 ornot %r1,%N2,%0"
1332 [(set_attr "type" "ilog")])
1334 (define_insn "*one_cmplsi_internal"
1335 [(set (match_operand:SI 0 "register_operand" "=r")
1336 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1337 ""
1338 "ornot $31,%1,%0"
1339 [(set_attr "type" "ilog")])
1341 (define_insn "one_cmpldi2"
1342 [(set (match_operand:DI 0 "register_operand" "=r")
1343 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1344 ""
1345 "ornot $31,%1,%0"
1346 [(set_attr "type" "ilog")])
1348 (define_insn "*iornotsi3"
1349 [(set (match_operand:SI 0 "register_operand" "=r")
1350 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1351 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1352 ""
1353 "ornot %r2,%1,%0"
1354 [(set_attr "type" "ilog")])
1356 (define_insn "*iornotdi3"
1357 [(set (match_operand:DI 0 "register_operand" "=r")
1358 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1359 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1360 ""
1361 "ornot %r2,%1,%0"
1362 [(set_attr "type" "ilog")])
1364 (define_insn "*xorsi_internal"
1365 [(set (match_operand:SI 0 "register_operand" "=r,r")
1366 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1367 (match_operand:SI 2 "or_operand" "rI,N")))]
1368 ""
1369 "@
1370 xor %r1,%2,%0
1371 eqv %r1,%N2,%0"
1372 [(set_attr "type" "ilog")])
1374 (define_insn "xordi3"
1375 [(set (match_operand:DI 0 "register_operand" "=r,r")
1376 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1377 (match_operand:DI 2 "or_operand" "rI,N")))]
1378 ""
1379 "@
1380 xor %r1,%2,%0
1381 eqv %r1,%N2,%0"
1382 [(set_attr "type" "ilog")])
1384 (define_insn "*xornotsi3"
1385 [(set (match_operand:SI 0 "register_operand" "=r")
1386 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1387 (match_operand:SI 2 "register_operand" "rI"))))]
1388 ""
1389 "eqv %r1,%2,%0"
1390 [(set_attr "type" "ilog")])
1392 (define_insn "*xornotdi3"
1393 [(set (match_operand:DI 0 "register_operand" "=r")
1394 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1395 (match_operand:DI 2 "register_operand" "rI"))))]
1396 ""
1397 "eqv %r1,%2,%0"
1398 [(set_attr "type" "ilog")])
1399 \f
1400 ;; Handle FFS and related insns iff we support CIX.
1402 (define_expand "ffsdi2"
1403 [(set (match_dup 2)
1404 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1405 (set (match_dup 3)
1406 (plus:DI (match_dup 2) (const_int 1)))
1407 (set (match_operand:DI 0 "register_operand" "")
1408 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1409 (const_int 0) (match_dup 3)))]
1410 "TARGET_CIX"
1411 {
1412 operands[2] = gen_reg_rtx (DImode);
1413 operands[3] = gen_reg_rtx (DImode);
1414 })
1416 (define_insn "clzdi2"
1417 [(set (match_operand:DI 0 "register_operand" "=r")
1418 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1419 "TARGET_CIX"
1420 "ctlz %1,%0"
1421 [(set_attr "type" "mvi")])
1423 (define_insn "ctzdi2"
1424 [(set (match_operand:DI 0 "register_operand" "=r")
1425 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1426 "TARGET_CIX"
1427 "cttz %1,%0"
1428 [(set_attr "type" "mvi")])
1430 (define_insn "popcountdi2"
1431 [(set (match_operand:DI 0 "register_operand" "=r")
1432 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1433 "TARGET_CIX"
1434 "ctpop %1,%0"
1435 [(set_attr "type" "mvi")])
1436 \f
1437 ;; Next come the shifts and the various extract and insert operations.
1439 (define_insn "ashldi3"
1440 [(set (match_operand:DI 0 "register_operand" "=r,r")
1441 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1442 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1443 ""
1444 {
1445 switch (which_alternative)
1446 {
1447 case 0:
1448 if (operands[2] == const1_rtx)
1449 return "addq %r1,%r1,%0";
1450 else
1451 return "s%P2addq %r1,0,%0";
1452 case 1:
1453 return "sll %r1,%2,%0";
1454 default:
1455 gcc_unreachable ();
1456 }
1457 }
1458 [(set_attr "type" "iadd,shift")])
1460 (define_insn "*ashldi_se"
1461 [(set (match_operand:DI 0 "register_operand" "=r")
1462 (sign_extend:DI
1463 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1464 (match_operand:DI 2 "const_int_operand" "P"))
1465 0)))]
1466 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1467 {
1468 if (operands[2] == const1_rtx)
1469 return "addl %r1,%r1,%0";
1470 else
1471 return "s%P2addl %r1,0,%0";
1472 }
1473 [(set_attr "type" "iadd")])
1475 (define_insn "lshrdi3"
1476 [(set (match_operand:DI 0 "register_operand" "=r")
1477 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1478 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1479 ""
1480 "srl %r1,%2,%0"
1481 [(set_attr "type" "shift")])
1483 (define_insn "ashrdi3"
1484 [(set (match_operand:DI 0 "register_operand" "=r")
1485 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1486 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1487 ""
1488 "sra %r1,%2,%0"
1489 [(set_attr "type" "shift")])
1491 (define_expand "extendqihi2"
1492 [(set (match_dup 2)
1493 (ashift:DI (match_operand:QI 1 "some_operand" "")
1494 (const_int 56)))
1495 (set (match_operand:HI 0 "register_operand" "")
1496 (ashiftrt:DI (match_dup 2)
1497 (const_int 56)))]
1498 ""
1499 {
1500 if (TARGET_BWX)
1501 {
1502 emit_insn (gen_extendqihi2x (operands[0],
1503 force_reg (QImode, operands[1])));
1504 DONE;
1505 }
1507 /* If we have an unaligned MEM, extend to DImode (which we do
1508 specially) and then copy to the result. */
1509 if (unaligned_memory_operand (operands[1], HImode))
1510 {
1511 rtx temp = gen_reg_rtx (DImode);
1513 emit_insn (gen_extendqidi2 (temp, operands[1]));
1514 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1515 DONE;
1516 }
1518 operands[0] = gen_lowpart (DImode, operands[0]);
1519 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1520 operands[2] = gen_reg_rtx (DImode);
1521 })
1523 (define_insn "extendqidi2x"
1524 [(set (match_operand:DI 0 "register_operand" "=r")
1525 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1526 "TARGET_BWX"
1527 "sextb %1,%0"
1528 [(set_attr "type" "shift")])
1530 (define_insn "extendhidi2x"
1531 [(set (match_operand:DI 0 "register_operand" "=r")
1532 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1533 "TARGET_BWX"
1534 "sextw %1,%0"
1535 [(set_attr "type" "shift")])
1537 (define_insn "extendqisi2x"
1538 [(set (match_operand:SI 0 "register_operand" "=r")
1539 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1540 "TARGET_BWX"
1541 "sextb %1,%0"
1542 [(set_attr "type" "shift")])
1544 (define_insn "extendhisi2x"
1545 [(set (match_operand:SI 0 "register_operand" "=r")
1546 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1547 "TARGET_BWX"
1548 "sextw %1,%0"
1549 [(set_attr "type" "shift")])
1551 (define_insn "extendqihi2x"
1552 [(set (match_operand:HI 0 "register_operand" "=r")
1553 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1554 "TARGET_BWX"
1555 "sextb %1,%0"
1556 [(set_attr "type" "shift")])
1558 (define_expand "extendqisi2"
1559 [(set (match_dup 2)
1560 (ashift:DI (match_operand:QI 1 "some_operand" "")
1561 (const_int 56)))
1562 (set (match_operand:SI 0 "register_operand" "")
1563 (ashiftrt:DI (match_dup 2)
1564 (const_int 56)))]
1565 ""
1566 {
1567 if (TARGET_BWX)
1568 {
1569 emit_insn (gen_extendqisi2x (operands[0],
1570 force_reg (QImode, operands[1])));
1571 DONE;
1572 }
1574 /* If we have an unaligned MEM, extend to a DImode form of
1575 the result (which we do specially). */
1576 if (unaligned_memory_operand (operands[1], QImode))
1577 {
1578 rtx temp = gen_reg_rtx (DImode);
1580 emit_insn (gen_extendqidi2 (temp, operands[1]));
1581 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1582 DONE;
1583 }
1585 operands[0] = gen_lowpart (DImode, operands[0]);
1586 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1587 operands[2] = gen_reg_rtx (DImode);
1588 })
1590 (define_expand "extendqidi2"
1591 [(set (match_dup 2)
1592 (ashift:DI (match_operand:QI 1 "some_operand" "")
1593 (const_int 56)))
1594 (set (match_operand:DI 0 "register_operand" "")
1595 (ashiftrt:DI (match_dup 2)
1596 (const_int 56)))]
1597 ""
1598 {
1599 if (TARGET_BWX)
1600 {
1601 emit_insn (gen_extendqidi2x (operands[0],
1602 force_reg (QImode, operands[1])));
1603 DONE;
1604 }
1606 if (unaligned_memory_operand (operands[1], QImode))
1607 {
1608 rtx seq
1609 = gen_unaligned_extendqidi (operands[0],
1610 get_unaligned_address (operands[1], 1));
1612 alpha_set_memflags (seq, operands[1]);
1613 emit_insn (seq);
1614 DONE;
1615 }
1617 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1618 operands[2] = gen_reg_rtx (DImode);
1619 })
1621 (define_expand "extendhisi2"
1622 [(set (match_dup 2)
1623 (ashift:DI (match_operand:HI 1 "some_operand" "")
1624 (const_int 48)))
1625 (set (match_operand:SI 0 "register_operand" "")
1626 (ashiftrt:DI (match_dup 2)
1627 (const_int 48)))]
1628 ""
1629 {
1630 if (TARGET_BWX)
1631 {
1632 emit_insn (gen_extendhisi2x (operands[0],
1633 force_reg (HImode, operands[1])));
1634 DONE;
1635 }
1637 /* If we have an unaligned MEM, extend to a DImode form of
1638 the result (which we do specially). */
1639 if (unaligned_memory_operand (operands[1], HImode))
1640 {
1641 rtx temp = gen_reg_rtx (DImode);
1643 emit_insn (gen_extendhidi2 (temp, operands[1]));
1644 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1645 DONE;
1646 }
1648 operands[0] = gen_lowpart (DImode, operands[0]);
1649 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1650 operands[2] = gen_reg_rtx (DImode);
1651 })
1653 (define_expand "extendhidi2"
1654 [(set (match_dup 2)
1655 (ashift:DI (match_operand:HI 1 "some_operand" "")
1656 (const_int 48)))
1657 (set (match_operand:DI 0 "register_operand" "")
1658 (ashiftrt:DI (match_dup 2)
1659 (const_int 48)))]
1660 ""
1661 {
1662 if (TARGET_BWX)
1663 {
1664 emit_insn (gen_extendhidi2x (operands[0],
1665 force_reg (HImode, operands[1])));
1666 DONE;
1667 }
1669 if (unaligned_memory_operand (operands[1], HImode))
1670 {
1671 rtx seq
1672 = gen_unaligned_extendhidi (operands[0],
1673 get_unaligned_address (operands[1], 2));
1675 alpha_set_memflags (seq, operands[1]);
1676 emit_insn (seq);
1677 DONE;
1678 }
1680 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1681 operands[2] = gen_reg_rtx (DImode);
1682 })
1684 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1685 ;; as a pattern saves one instruction. The code is similar to that for
1686 ;; the unaligned loads (see below).
1687 ;;
1688 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1689 (define_expand "unaligned_extendqidi"
1690 [(use (match_operand:QI 0 "register_operand" ""))
1691 (use (match_operand:DI 1 "address_operand" ""))]
1692 ""
1693 {
1694 if (WORDS_BIG_ENDIAN)
1695 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1696 else
1697 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1698 DONE;
1699 })
1701 (define_expand "unaligned_extendqidi_le"
1702 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1703 (set (match_dup 3)
1704 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1705 (const_int -8))))
1706 (set (match_dup 4)
1707 (ashift:DI (match_dup 3)
1708 (minus:DI (const_int 64)
1709 (ashift:DI
1710 (and:DI (match_dup 2) (const_int 7))
1711 (const_int 3)))))
1712 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1713 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1714 "! WORDS_BIG_ENDIAN"
1715 {
1716 operands[2] = gen_reg_rtx (DImode);
1717 operands[3] = gen_reg_rtx (DImode);
1718 operands[4] = gen_reg_rtx (DImode);
1719 })
1721 (define_expand "unaligned_extendqidi_be"
1722 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1723 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1724 (set (match_dup 4)
1725 (mem:DI (and:DI (match_dup 3)
1726 (const_int -8))))
1727 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1728 (set (match_dup 6)
1729 (ashift:DI (match_dup 4)
1730 (ashift:DI
1731 (and:DI
1732 (plus:DI (match_dup 5) (const_int 1))
1733 (const_int 7))
1734 (const_int 3))))
1735 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1736 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1737 "WORDS_BIG_ENDIAN"
1738 {
1739 operands[2] = gen_reg_rtx (DImode);
1740 operands[3] = gen_reg_rtx (DImode);
1741 operands[4] = gen_reg_rtx (DImode);
1742 operands[5] = gen_reg_rtx (DImode);
1743 operands[6] = gen_reg_rtx (DImode);
1744 })
1746 (define_expand "unaligned_extendhidi"
1747 [(use (match_operand:QI 0 "register_operand" ""))
1748 (use (match_operand:DI 1 "address_operand" ""))]
1749 ""
1750 {
1751 operands[0] = gen_lowpart (DImode, operands[0]);
1752 emit_insn ((WORDS_BIG_ENDIAN
1753 ? gen_unaligned_extendhidi_be
1754 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1755 DONE;
1756 })
1758 (define_expand "unaligned_extendhidi_le"
1759 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1760 (set (match_dup 3)
1761 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1762 (const_int -8))))
1763 (set (match_dup 4)
1764 (ashift:DI (match_dup 3)
1765 (minus:DI (const_int 64)
1766 (ashift:DI
1767 (and:DI (match_dup 2) (const_int 7))
1768 (const_int 3)))))
1769 (set (match_operand:DI 0 "register_operand" "")
1770 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1771 "! WORDS_BIG_ENDIAN"
1772 {
1773 operands[2] = gen_reg_rtx (DImode);
1774 operands[3] = gen_reg_rtx (DImode);
1775 operands[4] = gen_reg_rtx (DImode);
1776 })
1778 (define_expand "unaligned_extendhidi_be"
1779 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1780 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1781 (set (match_dup 4)
1782 (mem:DI (and:DI (match_dup 3)
1783 (const_int -8))))
1784 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1785 (set (match_dup 6)
1786 (ashift:DI (match_dup 4)
1787 (ashift:DI
1788 (and:DI
1789 (plus:DI (match_dup 5) (const_int 1))
1790 (const_int 7))
1791 (const_int 3))))
1792 (set (match_operand:DI 0 "register_operand" "")
1793 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1794 "WORDS_BIG_ENDIAN"
1795 {
1796 operands[2] = gen_reg_rtx (DImode);
1797 operands[3] = gen_reg_rtx (DImode);
1798 operands[4] = gen_reg_rtx (DImode);
1799 operands[5] = gen_reg_rtx (DImode);
1800 operands[6] = gen_reg_rtx (DImode);
1801 })
1803 (define_insn "*extxl_const"
1804 [(set (match_operand:DI 0 "register_operand" "=r")
1805 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1806 (match_operand:DI 2 "mode_width_operand" "n")
1807 (match_operand:DI 3 "mul8_operand" "I")))]
1808 ""
1809 "ext%M2l %r1,%s3,%0"
1810 [(set_attr "type" "shift")])
1812 (define_insn "extxl_le"
1813 [(set (match_operand:DI 0 "register_operand" "=r")
1814 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1815 (match_operand:DI 2 "mode_width_operand" "n")
1816 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1817 (const_int 3))))]
1818 "! WORDS_BIG_ENDIAN"
1819 "ext%M2l %r1,%3,%0"
1820 [(set_attr "type" "shift")])
1822 (define_insn "extxl_be"
1823 [(set (match_operand:DI 0 "register_operand" "=r")
1824 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1825 (match_operand:DI 2 "mode_width_operand" "n")
1826 (minus:DI
1827 (const_int 56)
1828 (ashift:DI
1829 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1830 (const_int 3)))))]
1831 "WORDS_BIG_ENDIAN"
1832 "ext%M2l %r1,%3,%0"
1833 [(set_attr "type" "shift")])
1835 ;; Combine has some strange notion of preserving existing undefined behavior
1836 ;; in shifts larger than a word size. So capture these patterns that it
1837 ;; should have turned into zero_extracts.
1839 (define_insn "*extxl_1_le"
1840 [(set (match_operand:DI 0 "register_operand" "=r")
1841 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1842 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1843 (const_int 3)))
1844 (match_operand:DI 3 "mode_mask_operand" "n")))]
1845 "! WORDS_BIG_ENDIAN"
1846 "ext%U3l %1,%2,%0"
1847 [(set_attr "type" "shift")])
1849 (define_insn "*extxl_1_be"
1850 [(set (match_operand:DI 0 "register_operand" "=r")
1851 (and:DI (lshiftrt:DI
1852 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1853 (minus:DI (const_int 56)
1854 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1855 (const_int 3))))
1856 (match_operand:DI 3 "mode_mask_operand" "n")))]
1857 "WORDS_BIG_ENDIAN"
1858 "ext%U3l %1,%2,%0"
1859 [(set_attr "type" "shift")])
1861 (define_insn "*extql_2_le"
1862 [(set (match_operand:DI 0 "register_operand" "=r")
1863 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1864 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1865 (const_int 3))))]
1866 "! WORDS_BIG_ENDIAN"
1867 "extql %1,%2,%0"
1868 [(set_attr "type" "shift")])
1870 (define_insn "*extql_2_be"
1871 [(set (match_operand:DI 0 "register_operand" "=r")
1872 (lshiftrt:DI
1873 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1874 (minus:DI (const_int 56)
1875 (ashift:DI
1876 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1877 (const_int 3)))))]
1878 "WORDS_BIG_ENDIAN"
1879 "extql %1,%2,%0"
1880 [(set_attr "type" "shift")])
1882 (define_insn "extqh_le"
1883 [(set (match_operand:DI 0 "register_operand" "=r")
1884 (ashift:DI
1885 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1886 (minus:DI (const_int 64)
1887 (ashift:DI
1888 (and:DI
1889 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1890 (const_int 7))
1891 (const_int 3)))))]
1892 "! WORDS_BIG_ENDIAN"
1893 "extqh %r1,%2,%0"
1894 [(set_attr "type" "shift")])
1896 (define_insn "extqh_be"
1897 [(set (match_operand:DI 0 "register_operand" "=r")
1898 (ashift:DI
1899 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1900 (ashift:DI
1901 (and:DI
1902 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1903 (const_int 1))
1904 (const_int 7))
1905 (const_int 3))))]
1906 "WORDS_BIG_ENDIAN"
1907 "extqh %r1,%2,%0"
1908 [(set_attr "type" "shift")])
1910 (define_insn "extlh_le"
1911 [(set (match_operand:DI 0 "register_operand" "=r")
1912 (ashift:DI
1913 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1914 (const_int 2147483647))
1915 (minus:DI (const_int 64)
1916 (ashift:DI
1917 (and:DI
1918 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1919 (const_int 7))
1920 (const_int 3)))))]
1921 "! WORDS_BIG_ENDIAN"
1922 "extlh %r1,%2,%0"
1923 [(set_attr "type" "shift")])
1925 (define_insn "extlh_be"
1926 [(set (match_operand:DI 0 "register_operand" "=r")
1927 (and:DI
1928 (ashift:DI
1929 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1930 (ashift:DI
1931 (and:DI
1932 (plus:DI
1933 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1934 (const_int 1))
1935 (const_int 7))
1936 (const_int 3)))
1937 (const_int 2147483647)))]
1938 "WORDS_BIG_ENDIAN"
1939 "extlh %r1,%2,%0"
1940 [(set_attr "type" "shift")])
1942 (define_insn "extwh_le"
1943 [(set (match_operand:DI 0 "register_operand" "=r")
1944 (ashift:DI
1945 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1946 (const_int 65535))
1947 (minus:DI (const_int 64)
1948 (ashift:DI
1949 (and:DI
1950 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1951 (const_int 7))
1952 (const_int 3)))))]
1953 "! WORDS_BIG_ENDIAN"
1954 "extwh %r1,%2,%0"
1955 [(set_attr "type" "shift")])
1957 (define_insn "extwh_be"
1958 [(set (match_operand:DI 0 "register_operand" "=r")
1959 (and:DI
1960 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1961 (ashift:DI
1962 (and:DI
1963 (plus:DI
1964 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1965 (const_int 1))
1966 (const_int 7))
1967 (const_int 3)))
1968 (const_int 65535)))]
1969 "WORDS_BIG_ENDIAN"
1970 "extwh %r1,%2,%0"
1971 [(set_attr "type" "shift")])
1973 ;; This converts an extXl into an extXh with an appropriate adjustment
1974 ;; to the address calculation.
1976 ;;(define_split
1977 ;; [(set (match_operand:DI 0 "register_operand" "")
1978 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1979 ;; (match_operand:DI 2 "mode_width_operand" "")
1980 ;; (ashift:DI (match_operand:DI 3 "" "")
1981 ;; (const_int 3)))
1982 ;; (match_operand:DI 4 "const_int_operand" "")))
1983 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1984 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1985 ;; [(set (match_dup 5) (match_dup 6))
1986 ;; (set (match_dup 0)
1987 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1988 ;; (ashift:DI (plus:DI (match_dup 5)
1989 ;; (match_dup 7))
1990 ;; (const_int 3)))
1991 ;; (match_dup 4)))]
1992 ;; "
1993 ;;{
1994 ;; operands[6] = plus_constant (operands[3],
1995 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1996 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1997 ;;}")
1999 (define_insn "*insbl_const"
2000 [(set (match_operand:DI 0 "register_operand" "=r")
2001 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2002 (match_operand:DI 2 "mul8_operand" "I")))]
2003 ""
2004 "insbl %1,%s2,%0"
2005 [(set_attr "type" "shift")])
2007 (define_insn "*inswl_const"
2008 [(set (match_operand:DI 0 "register_operand" "=r")
2009 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2010 (match_operand:DI 2 "mul8_operand" "I")))]
2011 ""
2012 "inswl %1,%s2,%0"
2013 [(set_attr "type" "shift")])
2015 (define_insn "*insll_const"
2016 [(set (match_operand:DI 0 "register_operand" "=r")
2017 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2018 (match_operand:DI 2 "mul8_operand" "I")))]
2019 ""
2020 "insll %1,%s2,%0"
2021 [(set_attr "type" "shift")])
2023 (define_insn "insbl_le"
2024 [(set (match_operand:DI 0 "register_operand" "=r")
2025 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2026 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2027 (const_int 3))))]
2028 "! WORDS_BIG_ENDIAN"
2029 "insbl %1,%2,%0"
2030 [(set_attr "type" "shift")])
2032 (define_insn "insbl_be"
2033 [(set (match_operand:DI 0 "register_operand" "=r")
2034 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2035 (minus:DI (const_int 56)
2036 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2037 (const_int 3)))))]
2038 "WORDS_BIG_ENDIAN"
2039 "insbl %1,%2,%0"
2040 [(set_attr "type" "shift")])
2042 (define_insn "inswl_le"
2043 [(set (match_operand:DI 0 "register_operand" "=r")
2044 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2045 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2046 (const_int 3))))]
2047 "! WORDS_BIG_ENDIAN"
2048 "inswl %1,%2,%0"
2049 [(set_attr "type" "shift")])
2051 (define_insn "inswl_be"
2052 [(set (match_operand:DI 0 "register_operand" "=r")
2053 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2054 (minus:DI (const_int 56)
2055 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2056 (const_int 3)))))]
2057 "WORDS_BIG_ENDIAN"
2058 "inswl %1,%2,%0"
2059 [(set_attr "type" "shift")])
2061 (define_insn "insll_le"
2062 [(set (match_operand:DI 0 "register_operand" "=r")
2063 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2064 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2065 (const_int 3))))]
2066 "! WORDS_BIG_ENDIAN"
2067 "insll %1,%2,%0"
2068 [(set_attr "type" "shift")])
2070 (define_insn "insll_be"
2071 [(set (match_operand:DI 0 "register_operand" "=r")
2072 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2073 (minus:DI (const_int 56)
2074 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2075 (const_int 3)))))]
2076 "WORDS_BIG_ENDIAN"
2077 "insll %1,%2,%0"
2078 [(set_attr "type" "shift")])
2080 (define_insn "insql_le"
2081 [(set (match_operand:DI 0 "register_operand" "=r")
2082 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2083 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2084 (const_int 3))))]
2085 "! WORDS_BIG_ENDIAN"
2086 "insql %1,%2,%0"
2087 [(set_attr "type" "shift")])
2089 (define_insn "insql_be"
2090 [(set (match_operand:DI 0 "register_operand" "=r")
2091 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2092 (minus:DI (const_int 56)
2093 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2094 (const_int 3)))))]
2095 "WORDS_BIG_ENDIAN"
2096 "insql %1,%2,%0"
2097 [(set_attr "type" "shift")])
2099 ;; Combine has this sometimes habit of moving the and outside of the
2100 ;; shift, making life more interesting.
2102 (define_insn "*insxl"
2103 [(set (match_operand:DI 0 "register_operand" "=r")
2104 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2105 (match_operand:DI 2 "mul8_operand" "I"))
2106 (match_operand:DI 3 "immediate_operand" "i")))]
2107 "HOST_BITS_PER_WIDE_INT == 64
2108 && GET_CODE (operands[3]) == CONST_INT
2109 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2110 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2111 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2112 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2113 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2114 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2115 {
2116 #if HOST_BITS_PER_WIDE_INT == 64
2117 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2118 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2119 return "insbl %1,%s2,%0";
2120 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2121 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2122 return "inswl %1,%s2,%0";
2123 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2124 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2125 return "insll %1,%s2,%0";
2126 #endif
2127 gcc_unreachable ();
2128 }
2129 [(set_attr "type" "shift")])
2131 ;; We do not include the insXh insns because they are complex to express
2132 ;; and it does not appear that we would ever want to generate them.
2133 ;;
2134 ;; Since we need them for block moves, though, cop out and use unspec.
2136 (define_insn "insxh"
2137 [(set (match_operand:DI 0 "register_operand" "=r")
2138 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2139 (match_operand:DI 2 "mode_width_operand" "n")
2140 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2141 UNSPEC_INSXH))]
2142 ""
2143 "ins%M2h %1,%3,%0"
2144 [(set_attr "type" "shift")])
2146 (define_insn "mskxl_le"
2147 [(set (match_operand:DI 0 "register_operand" "=r")
2148 (and:DI (not:DI (ashift:DI
2149 (match_operand:DI 2 "mode_mask_operand" "n")
2150 (ashift:DI
2151 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2152 (const_int 3))))
2153 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2154 "! WORDS_BIG_ENDIAN"
2155 "msk%U2l %r1,%3,%0"
2156 [(set_attr "type" "shift")])
2158 (define_insn "mskxl_be"
2159 [(set (match_operand:DI 0 "register_operand" "=r")
2160 (and:DI (not:DI (ashift:DI
2161 (match_operand:DI 2 "mode_mask_operand" "n")
2162 (minus:DI (const_int 56)
2163 (ashift:DI
2164 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2165 (const_int 3)))))
2166 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2167 "WORDS_BIG_ENDIAN"
2168 "msk%U2l %r1,%3,%0"
2169 [(set_attr "type" "shift")])
2171 ;; We do not include the mskXh insns because it does not appear we would
2172 ;; ever generate one.
2173 ;;
2174 ;; Again, we do for block moves and we use unspec again.
2176 (define_insn "mskxh"
2177 [(set (match_operand:DI 0 "register_operand" "=r")
2178 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2179 (match_operand:DI 2 "mode_width_operand" "n")
2180 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2181 UNSPEC_MSKXH))]
2182 ""
2183 "msk%M2h %1,%3,%0"
2184 [(set_attr "type" "shift")])
2186 ;; Prefer AND + NE over LSHIFTRT + AND.
2188 (define_insn_and_split "*ze_and_ne"
2189 [(set (match_operand:DI 0 "register_operand" "=r")
2190 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2191 (const_int 1)
2192 (match_operand 2 "const_int_operand" "I")))]
2193 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2194 "#"
2195 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2196 [(set (match_dup 0)
2197 (and:DI (match_dup 1) (match_dup 3)))
2198 (set (match_dup 0)
2199 (ne:DI (match_dup 0) (const_int 0)))]
2200 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2201 \f
2202 ;; Floating-point operations. All the double-precision insns can extend
2203 ;; from single, so indicate that. The exception are the ones that simply
2204 ;; play with the sign bits; it's not clear what to do there.
2206 (define_insn "abssf2"
2207 [(set (match_operand:SF 0 "register_operand" "=f")
2208 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2209 "TARGET_FP"
2210 "cpys $f31,%R1,%0"
2211 [(set_attr "type" "fcpys")])
2213 (define_insn "*nabssf2"
2214 [(set (match_operand:SF 0 "register_operand" "=f")
2215 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2216 "TARGET_FP"
2217 "cpysn $f31,%R1,%0"
2218 [(set_attr "type" "fadd")])
2220 (define_insn "absdf2"
2221 [(set (match_operand:DF 0 "register_operand" "=f")
2222 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2223 "TARGET_FP"
2224 "cpys $f31,%R1,%0"
2225 [(set_attr "type" "fcpys")])
2227 (define_insn "*nabsdf2"
2228 [(set (match_operand:DF 0 "register_operand" "=f")
2229 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2230 "TARGET_FP"
2231 "cpysn $f31,%R1,%0"
2232 [(set_attr "type" "fadd")])
2234 (define_expand "abstf2"
2235 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2236 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2237 (use (match_dup 2))])]
2238 "TARGET_HAS_XFLOATING_LIBS"
2239 {
2240 #if HOST_BITS_PER_WIDE_INT >= 64
2241 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2242 #else
2243 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2244 #endif
2245 })
2247 (define_insn_and_split "*abstf_internal"
2248 [(set (match_operand:TF 0 "register_operand" "=r")
2249 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2250 (use (match_operand:DI 2 "register_operand" "r"))]
2251 "TARGET_HAS_XFLOATING_LIBS"
2252 "#"
2253 "&& reload_completed"
2254 [(const_int 0)]
2255 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2257 (define_insn "negsf2"
2258 [(set (match_operand:SF 0 "register_operand" "=f")
2259 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2260 "TARGET_FP"
2261 "cpysn %R1,%R1,%0"
2262 [(set_attr "type" "fadd")])
2264 (define_insn "negdf2"
2265 [(set (match_operand:DF 0 "register_operand" "=f")
2266 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2267 "TARGET_FP"
2268 "cpysn %R1,%R1,%0"
2269 [(set_attr "type" "fadd")])
2271 (define_expand "negtf2"
2272 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2273 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2274 (use (match_dup 2))])]
2275 "TARGET_HAS_XFLOATING_LIBS"
2276 {
2277 #if HOST_BITS_PER_WIDE_INT >= 64
2278 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2279 #else
2280 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2281 #endif
2282 })
2284 (define_insn_and_split "*negtf_internal"
2285 [(set (match_operand:TF 0 "register_operand" "=r")
2286 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2287 (use (match_operand:DI 2 "register_operand" "r"))]
2288 "TARGET_HAS_XFLOATING_LIBS"
2289 "#"
2290 "&& reload_completed"
2291 [(const_int 0)]
2292 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2294 (define_insn "copysignsf3"
2295 [(set (match_operand:SF 0 "register_operand" "=f")
2296 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2297 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2298 UNSPEC_COPYSIGN))]
2299 "TARGET_FP"
2300 "cpys %R2,%R1,%0"
2301 [(set_attr "type" "fadd")])
2303 (define_insn "*ncopysignsf3"
2304 [(set (match_operand:SF 0 "register_operand" "=f")
2305 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2306 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2307 UNSPEC_COPYSIGN)))]
2308 "TARGET_FP"
2309 "cpysn %R2,%R1,%0"
2310 [(set_attr "type" "fadd")])
2312 (define_insn "copysigndf3"
2313 [(set (match_operand:DF 0 "register_operand" "=f")
2314 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2315 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2316 UNSPEC_COPYSIGN))]
2317 "TARGET_FP"
2318 "cpys %R2,%R1,%0"
2319 [(set_attr "type" "fadd")])
2321 (define_insn "*ncopysigndf3"
2322 [(set (match_operand:DF 0 "register_operand" "=f")
2323 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2324 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2325 UNSPEC_COPYSIGN)))]
2326 "TARGET_FP"
2327 "cpysn %R2,%R1,%0"
2328 [(set_attr "type" "fadd")])
2330 (define_insn "*addsf_ieee"
2331 [(set (match_operand:SF 0 "register_operand" "=&f")
2332 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2333 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2334 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2335 "add%,%/ %R1,%R2,%0"
2336 [(set_attr "type" "fadd")
2337 (set_attr "trap" "yes")
2338 (set_attr "round_suffix" "normal")
2339 (set_attr "trap_suffix" "u_su_sui")])
2341 (define_insn "addsf3"
2342 [(set (match_operand:SF 0 "register_operand" "=f")
2343 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2344 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2345 "TARGET_FP"
2346 "add%,%/ %R1,%R2,%0"
2347 [(set_attr "type" "fadd")
2348 (set_attr "trap" "yes")
2349 (set_attr "round_suffix" "normal")
2350 (set_attr "trap_suffix" "u_su_sui")])
2352 (define_insn "*adddf_ieee"
2353 [(set (match_operand:DF 0 "register_operand" "=&f")
2354 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2355 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2356 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2357 "add%-%/ %R1,%R2,%0"
2358 [(set_attr "type" "fadd")
2359 (set_attr "trap" "yes")
2360 (set_attr "round_suffix" "normal")
2361 (set_attr "trap_suffix" "u_su_sui")])
2363 (define_insn "adddf3"
2364 [(set (match_operand:DF 0 "register_operand" "=f")
2365 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2366 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2367 "TARGET_FP"
2368 "add%-%/ %R1,%R2,%0"
2369 [(set_attr "type" "fadd")
2370 (set_attr "trap" "yes")
2371 (set_attr "round_suffix" "normal")
2372 (set_attr "trap_suffix" "u_su_sui")])
2374 (define_insn "*adddf_ext1"
2375 [(set (match_operand:DF 0 "register_operand" "=f")
2376 (plus:DF (float_extend:DF
2377 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2378 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2379 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2380 "add%-%/ %R1,%R2,%0"
2381 [(set_attr "type" "fadd")
2382 (set_attr "trap" "yes")
2383 (set_attr "round_suffix" "normal")
2384 (set_attr "trap_suffix" "u_su_sui")])
2386 (define_insn "*adddf_ext2"
2387 [(set (match_operand:DF 0 "register_operand" "=f")
2388 (plus:DF (float_extend:DF
2389 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2390 (float_extend:DF
2391 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2392 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2393 "add%-%/ %R1,%R2,%0"
2394 [(set_attr "type" "fadd")
2395 (set_attr "trap" "yes")
2396 (set_attr "round_suffix" "normal")
2397 (set_attr "trap_suffix" "u_su_sui")])
2399 (define_expand "addtf3"
2400 [(use (match_operand 0 "register_operand" ""))
2401 (use (match_operand 1 "general_operand" ""))
2402 (use (match_operand 2 "general_operand" ""))]
2403 "TARGET_HAS_XFLOATING_LIBS"
2404 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2406 ;; Define conversion operators between DFmode and SImode, using the cvtql
2407 ;; instruction. To allow combine et al to do useful things, we keep the
2408 ;; operation as a unit until after reload, at which point we split the
2409 ;; instructions.
2410 ;;
2411 ;; Note that we (attempt to) only consider this optimization when the
2412 ;; ultimate destination is memory. If we will be doing further integer
2413 ;; processing, it is cheaper to do the truncation in the int regs.
2415 (define_insn "*cvtql"
2416 [(set (match_operand:SF 0 "register_operand" "=f")
2417 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2418 UNSPEC_CVTQL))]
2419 "TARGET_FP"
2420 "cvtql%/ %R1,%0"
2421 [(set_attr "type" "fadd")
2422 (set_attr "trap" "yes")
2423 (set_attr "trap_suffix" "v_sv")])
2425 (define_insn_and_split "*fix_truncdfsi_ieee"
2426 [(set (match_operand:SI 0 "memory_operand" "=m")
2427 (subreg:SI
2428 (match_operator:DI 4 "fix_operator"
2429 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2430 (clobber (match_scratch:DI 2 "=&f"))
2431 (clobber (match_scratch:SF 3 "=&f"))]
2432 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2433 "#"
2434 "&& reload_completed"
2435 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2436 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2437 (set (match_dup 5) (match_dup 3))]
2438 {
2439 operands[5] = adjust_address (operands[0], SFmode, 0);
2440 }
2441 [(set_attr "type" "fadd")
2442 (set_attr "trap" "yes")])
2444 (define_insn_and_split "*fix_truncdfsi_internal"
2445 [(set (match_operand:SI 0 "memory_operand" "=m")
2446 (subreg:SI
2447 (match_operator:DI 3 "fix_operator"
2448 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2449 (clobber (match_scratch:DI 2 "=f"))]
2450 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2451 "#"
2452 "&& reload_completed"
2453 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2454 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2455 (set (match_dup 5) (match_dup 4))]
2456 {
2457 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2458 operands[5] = adjust_address (operands[0], SFmode, 0);
2459 }
2460 [(set_attr "type" "fadd")
2461 (set_attr "trap" "yes")])
2463 (define_insn "*fix_truncdfdi_ieee"
2464 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2465 (match_operator:DI 2 "fix_operator"
2466 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2467 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2468 "cvt%-q%/ %R1,%0"
2469 [(set_attr "type" "fadd")
2470 (set_attr "trap" "yes")
2471 (set_attr "round_suffix" "c")
2472 (set_attr "trap_suffix" "v_sv_svi")])
2474 (define_insn "*fix_truncdfdi2"
2475 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2476 (match_operator:DI 2 "fix_operator"
2477 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2478 "TARGET_FP"
2479 "cvt%-q%/ %R1,%0"
2480 [(set_attr "type" "fadd")
2481 (set_attr "trap" "yes")
2482 (set_attr "round_suffix" "c")
2483 (set_attr "trap_suffix" "v_sv_svi")])
2485 (define_expand "fix_truncdfdi2"
2486 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2487 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2488 "TARGET_FP"
2489 "")
2491 (define_expand "fixuns_truncdfdi2"
2492 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2493 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2494 "TARGET_FP"
2495 "")
2497 ;; Likewise between SFmode and SImode.
2499 (define_insn_and_split "*fix_truncsfsi_ieee"
2500 [(set (match_operand:SI 0 "memory_operand" "=m")
2501 (subreg:SI
2502 (match_operator:DI 4 "fix_operator"
2503 [(float_extend:DF
2504 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2505 (clobber (match_scratch:DI 2 "=&f"))
2506 (clobber (match_scratch:SF 3 "=&f"))]
2507 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2508 "#"
2509 "&& reload_completed"
2510 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2511 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2512 (set (match_dup 5) (match_dup 3))]
2513 {
2514 operands[5] = adjust_address (operands[0], SFmode, 0);
2515 }
2516 [(set_attr "type" "fadd")
2517 (set_attr "trap" "yes")])
2519 (define_insn_and_split "*fix_truncsfsi_internal"
2520 [(set (match_operand:SI 0 "memory_operand" "=m")
2521 (subreg:SI
2522 (match_operator:DI 3 "fix_operator"
2523 [(float_extend:DF
2524 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2525 (clobber (match_scratch:DI 2 "=f"))]
2526 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2527 "#"
2528 "&& reload_completed"
2529 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2530 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2531 (set (match_dup 5) (match_dup 4))]
2532 {
2533 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2534 operands[5] = adjust_address (operands[0], SFmode, 0);
2535 }
2536 [(set_attr "type" "fadd")
2537 (set_attr "trap" "yes")])
2539 (define_insn "*fix_truncsfdi_ieee"
2540 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2541 (match_operator:DI 2 "fix_operator"
2542 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2543 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2544 "cvt%-q%/ %R1,%0"
2545 [(set_attr "type" "fadd")
2546 (set_attr "trap" "yes")
2547 (set_attr "round_suffix" "c")
2548 (set_attr "trap_suffix" "v_sv_svi")])
2550 (define_insn "*fix_truncsfdi2"
2551 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2552 (match_operator:DI 2 "fix_operator"
2553 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2554 "TARGET_FP"
2555 "cvt%-q%/ %R1,%0"
2556 [(set_attr "type" "fadd")
2557 (set_attr "trap" "yes")
2558 (set_attr "round_suffix" "c")
2559 (set_attr "trap_suffix" "v_sv_svi")])
2561 (define_expand "fix_truncsfdi2"
2562 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2563 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2564 "TARGET_FP"
2565 "")
2567 (define_expand "fixuns_truncsfdi2"
2568 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2569 (unsigned_fix:DI
2570 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2571 "TARGET_FP"
2572 "")
2574 (define_expand "fix_trunctfdi2"
2575 [(use (match_operand:DI 0 "register_operand" ""))
2576 (use (match_operand:TF 1 "general_operand" ""))]
2577 "TARGET_HAS_XFLOATING_LIBS"
2578 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2580 (define_expand "fixuns_trunctfdi2"
2581 [(use (match_operand:DI 0 "register_operand" ""))
2582 (use (match_operand:TF 1 "general_operand" ""))]
2583 "TARGET_HAS_XFLOATING_LIBS"
2584 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2586 (define_insn "*floatdisf_ieee"
2587 [(set (match_operand:SF 0 "register_operand" "=&f")
2588 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2589 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2590 "cvtq%,%/ %1,%0"
2591 [(set_attr "type" "fadd")
2592 (set_attr "trap" "yes")
2593 (set_attr "round_suffix" "normal")
2594 (set_attr "trap_suffix" "sui")])
2596 (define_insn "floatdisf2"
2597 [(set (match_operand:SF 0 "register_operand" "=f")
2598 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2599 "TARGET_FP"
2600 "cvtq%,%/ %1,%0"
2601 [(set_attr "type" "fadd")
2602 (set_attr "trap" "yes")
2603 (set_attr "round_suffix" "normal")
2604 (set_attr "trap_suffix" "sui")])
2606 (define_insn_and_split "*floatsisf2_ieee"
2607 [(set (match_operand:SF 0 "register_operand" "=&f")
2608 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2609 (clobber (match_scratch:DI 2 "=&f"))
2610 (clobber (match_scratch:SF 3 "=&f"))]
2611 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2612 "#"
2613 "&& reload_completed"
2614 [(set (match_dup 3) (match_dup 1))
2615 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2616 (set (match_dup 0) (float:SF (match_dup 2)))]
2617 {
2618 operands[1] = adjust_address (operands[1], SFmode, 0);
2619 })
2621 (define_insn_and_split "*floatsisf2"
2622 [(set (match_operand:SF 0 "register_operand" "=f")
2623 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2624 "TARGET_FP"
2625 "#"
2626 "&& reload_completed"
2627 [(set (match_dup 0) (match_dup 1))
2628 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2629 (set (match_dup 0) (float:SF (match_dup 2)))]
2630 {
2631 operands[1] = adjust_address (operands[1], SFmode, 0);
2632 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2633 })
2635 (define_insn "*floatdidf_ieee"
2636 [(set (match_operand:DF 0 "register_operand" "=&f")
2637 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2638 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2639 "cvtq%-%/ %1,%0"
2640 [(set_attr "type" "fadd")
2641 (set_attr "trap" "yes")
2642 (set_attr "round_suffix" "normal")
2643 (set_attr "trap_suffix" "sui")])
2645 (define_insn "floatdidf2"
2646 [(set (match_operand:DF 0 "register_operand" "=f")
2647 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2648 "TARGET_FP"
2649 "cvtq%-%/ %1,%0"
2650 [(set_attr "type" "fadd")
2651 (set_attr "trap" "yes")
2652 (set_attr "round_suffix" "normal")
2653 (set_attr "trap_suffix" "sui")])
2655 (define_insn_and_split "*floatsidf2_ieee"
2656 [(set (match_operand:DF 0 "register_operand" "=&f")
2657 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2658 (clobber (match_scratch:DI 2 "=&f"))
2659 (clobber (match_scratch:SF 3 "=&f"))]
2660 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2661 "#"
2662 "&& reload_completed"
2663 [(set (match_dup 3) (match_dup 1))
2664 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2665 (set (match_dup 0) (float:DF (match_dup 2)))]
2666 {
2667 operands[1] = adjust_address (operands[1], SFmode, 0);
2668 })
2670 (define_insn_and_split "*floatsidf2"
2671 [(set (match_operand:DF 0 "register_operand" "=f")
2672 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2673 "TARGET_FP"
2674 "#"
2675 "&& reload_completed"
2676 [(set (match_dup 3) (match_dup 1))
2677 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2678 (set (match_dup 0) (float:DF (match_dup 2)))]
2679 {
2680 operands[1] = adjust_address (operands[1], SFmode, 0);
2681 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2682 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2683 })
2685 (define_expand "floatditf2"
2686 [(use (match_operand:TF 0 "register_operand" ""))
2687 (use (match_operand:DI 1 "general_operand" ""))]
2688 "TARGET_HAS_XFLOATING_LIBS"
2689 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2691 (define_expand "floatunsdisf2"
2692 [(use (match_operand:SF 0 "register_operand" ""))
2693 (use (match_operand:DI 1 "register_operand" ""))]
2694 "TARGET_FP"
2695 "alpha_emit_floatuns (operands); DONE;")
2697 (define_expand "floatunsdidf2"
2698 [(use (match_operand:DF 0 "register_operand" ""))
2699 (use (match_operand:DI 1 "register_operand" ""))]
2700 "TARGET_FP"
2701 "alpha_emit_floatuns (operands); DONE;")
2703 (define_expand "floatunsditf2"
2704 [(use (match_operand:TF 0 "register_operand" ""))
2705 (use (match_operand:DI 1 "general_operand" ""))]
2706 "TARGET_HAS_XFLOATING_LIBS"
2707 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2709 (define_expand "extendsfdf2"
2710 [(set (match_operand:DF 0 "register_operand" "")
2711 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2712 "TARGET_FP"
2713 {
2714 if (alpha_fptm >= ALPHA_FPTM_SU)
2715 operands[1] = force_reg (SFmode, operands[1]);
2716 })
2718 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2719 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2721 (define_insn "*extendsfdf2_ieee"
2722 [(set (match_operand:DF 0 "register_operand" "=&f")
2723 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2724 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2725 "cvtsts %1,%0"
2726 [(set_attr "type" "fadd")
2727 (set_attr "trap" "yes")])
2729 (define_insn "*extendsfdf2_internal"
2730 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2731 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2732 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2733 "@
2734 cpys %1,%1,%0
2735 ld%, %0,%1
2736 st%- %1,%0"
2737 [(set_attr "type" "fcpys,fld,fst")])
2739 ;; Use register_operand for operand 1 to prevent compress_float_constant
2740 ;; from doing something silly. When optimizing we'll put things back
2741 ;; together anyway.
2742 (define_expand "extendsftf2"
2743 [(use (match_operand:TF 0 "register_operand" ""))
2744 (use (match_operand:SF 1 "register_operand" ""))]
2745 "TARGET_HAS_XFLOATING_LIBS"
2746 {
2747 rtx tmp = gen_reg_rtx (DFmode);
2748 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2749 emit_insn (gen_extenddftf2 (operands[0], tmp));
2750 DONE;
2751 })
2753 (define_expand "extenddftf2"
2754 [(use (match_operand:TF 0 "register_operand" ""))
2755 (use (match_operand:DF 1 "register_operand" ""))]
2756 "TARGET_HAS_XFLOATING_LIBS"
2757 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2759 (define_insn "*truncdfsf2_ieee"
2760 [(set (match_operand:SF 0 "register_operand" "=&f")
2761 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2762 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2763 "cvt%-%,%/ %R1,%0"
2764 [(set_attr "type" "fadd")
2765 (set_attr "trap" "yes")
2766 (set_attr "round_suffix" "normal")
2767 (set_attr "trap_suffix" "u_su_sui")])
2769 (define_insn "truncdfsf2"
2770 [(set (match_operand:SF 0 "register_operand" "=f")
2771 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2772 "TARGET_FP"
2773 "cvt%-%,%/ %R1,%0"
2774 [(set_attr "type" "fadd")
2775 (set_attr "trap" "yes")
2776 (set_attr "round_suffix" "normal")
2777 (set_attr "trap_suffix" "u_su_sui")])
2779 (define_expand "trunctfdf2"
2780 [(use (match_operand:DF 0 "register_operand" ""))
2781 (use (match_operand:TF 1 "general_operand" ""))]
2782 "TARGET_HAS_XFLOATING_LIBS"
2783 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2785 (define_expand "trunctfsf2"
2786 [(use (match_operand:SF 0 "register_operand" ""))
2787 (use (match_operand:TF 1 "general_operand" ""))]
2788 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2789 {
2790 rtx tmpf, sticky, arg, lo, hi;
2792 tmpf = gen_reg_rtx (DFmode);
2793 sticky = gen_reg_rtx (DImode);
2794 arg = copy_to_mode_reg (TFmode, operands[1]);
2795 lo = gen_lowpart (DImode, arg);
2796 hi = gen_highpart (DImode, arg);
2798 /* Convert the low word of the TFmode value into a sticky rounding bit,
2799 then or it into the low bit of the high word. This leaves the sticky
2800 bit at bit 48 of the fraction, which is representable in DFmode,
2801 which prevents rounding error in the final conversion to SFmode. */
2803 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2804 gen_rtx_NE (DImode, lo, const0_rtx)));
2805 emit_insn (gen_iordi3 (hi, hi, sticky));
2806 emit_insn (gen_trunctfdf2 (tmpf, arg));
2807 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2808 DONE;
2809 })
2811 (define_insn "*divsf3_ieee"
2812 [(set (match_operand:SF 0 "register_operand" "=&f")
2813 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2814 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2815 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2816 "div%,%/ %R1,%R2,%0"
2817 [(set_attr "type" "fdiv")
2818 (set_attr "opsize" "si")
2819 (set_attr "trap" "yes")
2820 (set_attr "round_suffix" "normal")
2821 (set_attr "trap_suffix" "u_su_sui")])
2823 (define_insn "divsf3"
2824 [(set (match_operand:SF 0 "register_operand" "=f")
2825 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2826 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2827 "TARGET_FP"
2828 "div%,%/ %R1,%R2,%0"
2829 [(set_attr "type" "fdiv")
2830 (set_attr "opsize" "si")
2831 (set_attr "trap" "yes")
2832 (set_attr "round_suffix" "normal")
2833 (set_attr "trap_suffix" "u_su_sui")])
2835 (define_insn "*divdf3_ieee"
2836 [(set (match_operand:DF 0 "register_operand" "=&f")
2837 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2838 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2839 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2840 "div%-%/ %R1,%R2,%0"
2841 [(set_attr "type" "fdiv")
2842 (set_attr "trap" "yes")
2843 (set_attr "round_suffix" "normal")
2844 (set_attr "trap_suffix" "u_su_sui")])
2846 (define_insn "divdf3"
2847 [(set (match_operand:DF 0 "register_operand" "=f")
2848 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2849 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2850 "TARGET_FP"
2851 "div%-%/ %R1,%R2,%0"
2852 [(set_attr "type" "fdiv")
2853 (set_attr "trap" "yes")
2854 (set_attr "round_suffix" "normal")
2855 (set_attr "trap_suffix" "u_su_sui")])
2857 (define_insn "*divdf_ext1"
2858 [(set (match_operand:DF 0 "register_operand" "=f")
2859 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2860 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2861 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2862 "div%-%/ %R1,%R2,%0"
2863 [(set_attr "type" "fdiv")
2864 (set_attr "trap" "yes")
2865 (set_attr "round_suffix" "normal")
2866 (set_attr "trap_suffix" "u_su_sui")])
2868 (define_insn "*divdf_ext2"
2869 [(set (match_operand:DF 0 "register_operand" "=f")
2870 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2871 (float_extend:DF
2872 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2873 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2874 "div%-%/ %R1,%R2,%0"
2875 [(set_attr "type" "fdiv")
2876 (set_attr "trap" "yes")
2877 (set_attr "round_suffix" "normal")
2878 (set_attr "trap_suffix" "u_su_sui")])
2880 (define_insn "*divdf_ext3"
2881 [(set (match_operand:DF 0 "register_operand" "=f")
2882 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2883 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2884 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2885 "div%-%/ %R1,%R2,%0"
2886 [(set_attr "type" "fdiv")
2887 (set_attr "trap" "yes")
2888 (set_attr "round_suffix" "normal")
2889 (set_attr "trap_suffix" "u_su_sui")])
2891 (define_expand "divtf3"
2892 [(use (match_operand 0 "register_operand" ""))
2893 (use (match_operand 1 "general_operand" ""))
2894 (use (match_operand 2 "general_operand" ""))]
2895 "TARGET_HAS_XFLOATING_LIBS"
2896 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2898 (define_insn "*mulsf3_ieee"
2899 [(set (match_operand:SF 0 "register_operand" "=&f")
2900 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2901 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2902 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2903 "mul%,%/ %R1,%R2,%0"
2904 [(set_attr "type" "fmul")
2905 (set_attr "trap" "yes")
2906 (set_attr "round_suffix" "normal")
2907 (set_attr "trap_suffix" "u_su_sui")])
2909 (define_insn "mulsf3"
2910 [(set (match_operand:SF 0 "register_operand" "=f")
2911 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2912 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2913 "TARGET_FP"
2914 "mul%,%/ %R1,%R2,%0"
2915 [(set_attr "type" "fmul")
2916 (set_attr "trap" "yes")
2917 (set_attr "round_suffix" "normal")
2918 (set_attr "trap_suffix" "u_su_sui")])
2920 (define_insn "*muldf3_ieee"
2921 [(set (match_operand:DF 0 "register_operand" "=&f")
2922 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2923 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2924 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2925 "mul%-%/ %R1,%R2,%0"
2926 [(set_attr "type" "fmul")
2927 (set_attr "trap" "yes")
2928 (set_attr "round_suffix" "normal")
2929 (set_attr "trap_suffix" "u_su_sui")])
2931 (define_insn "muldf3"
2932 [(set (match_operand:DF 0 "register_operand" "=f")
2933 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2934 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2935 "TARGET_FP"
2936 "mul%-%/ %R1,%R2,%0"
2937 [(set_attr "type" "fmul")
2938 (set_attr "trap" "yes")
2939 (set_attr "round_suffix" "normal")
2940 (set_attr "trap_suffix" "u_su_sui")])
2942 (define_insn "*muldf_ext1"
2943 [(set (match_operand:DF 0 "register_operand" "=f")
2944 (mult:DF (float_extend:DF
2945 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2946 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2947 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2948 "mul%-%/ %R1,%R2,%0"
2949 [(set_attr "type" "fmul")
2950 (set_attr "trap" "yes")
2951 (set_attr "round_suffix" "normal")
2952 (set_attr "trap_suffix" "u_su_sui")])
2954 (define_insn "*muldf_ext2"
2955 [(set (match_operand:DF 0 "register_operand" "=f")
2956 (mult:DF (float_extend:DF
2957 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2958 (float_extend:DF
2959 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2960 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2961 "mul%-%/ %R1,%R2,%0"
2962 [(set_attr "type" "fmul")
2963 (set_attr "trap" "yes")
2964 (set_attr "round_suffix" "normal")
2965 (set_attr "trap_suffix" "u_su_sui")])
2967 (define_expand "multf3"
2968 [(use (match_operand 0 "register_operand" ""))
2969 (use (match_operand 1 "general_operand" ""))
2970 (use (match_operand 2 "general_operand" ""))]
2971 "TARGET_HAS_XFLOATING_LIBS"
2972 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2974 (define_insn "*subsf3_ieee"
2975 [(set (match_operand:SF 0 "register_operand" "=&f")
2976 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2977 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2978 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2979 "sub%,%/ %R1,%R2,%0"
2980 [(set_attr "type" "fadd")
2981 (set_attr "trap" "yes")
2982 (set_attr "round_suffix" "normal")
2983 (set_attr "trap_suffix" "u_su_sui")])
2985 (define_insn "subsf3"
2986 [(set (match_operand:SF 0 "register_operand" "=f")
2987 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2988 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2989 "TARGET_FP"
2990 "sub%,%/ %R1,%R2,%0"
2991 [(set_attr "type" "fadd")
2992 (set_attr "trap" "yes")
2993 (set_attr "round_suffix" "normal")
2994 (set_attr "trap_suffix" "u_su_sui")])
2996 (define_insn "*subdf3_ieee"
2997 [(set (match_operand:DF 0 "register_operand" "=&f")
2998 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2999 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3000 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3001 "sub%-%/ %R1,%R2,%0"
3002 [(set_attr "type" "fadd")
3003 (set_attr "trap" "yes")
3004 (set_attr "round_suffix" "normal")
3005 (set_attr "trap_suffix" "u_su_sui")])
3007 (define_insn "subdf3"
3008 [(set (match_operand:DF 0 "register_operand" "=f")
3009 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3010 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3011 "TARGET_FP"
3012 "sub%-%/ %R1,%R2,%0"
3013 [(set_attr "type" "fadd")
3014 (set_attr "trap" "yes")
3015 (set_attr "round_suffix" "normal")
3016 (set_attr "trap_suffix" "u_su_sui")])
3018 (define_insn "*subdf_ext1"
3019 [(set (match_operand:DF 0 "register_operand" "=f")
3020 (minus:DF (float_extend:DF
3021 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3022 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3023 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3024 "sub%-%/ %R1,%R2,%0"
3025 [(set_attr "type" "fadd")
3026 (set_attr "trap" "yes")
3027 (set_attr "round_suffix" "normal")
3028 (set_attr "trap_suffix" "u_su_sui")])
3030 (define_insn "*subdf_ext2"
3031 [(set (match_operand:DF 0 "register_operand" "=f")
3032 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3033 (float_extend:DF
3034 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3035 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3036 "sub%-%/ %R1,%R2,%0"
3037 [(set_attr "type" "fadd")
3038 (set_attr "trap" "yes")
3039 (set_attr "round_suffix" "normal")
3040 (set_attr "trap_suffix" "u_su_sui")])
3042 (define_insn "*subdf_ext3"
3043 [(set (match_operand:DF 0 "register_operand" "=f")
3044 (minus:DF (float_extend:DF
3045 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3046 (float_extend:DF
3047 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3048 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3049 "sub%-%/ %R1,%R2,%0"
3050 [(set_attr "type" "fadd")
3051 (set_attr "trap" "yes")
3052 (set_attr "round_suffix" "normal")
3053 (set_attr "trap_suffix" "u_su_sui")])
3055 (define_expand "subtf3"
3056 [(use (match_operand 0 "register_operand" ""))
3057 (use (match_operand 1 "general_operand" ""))
3058 (use (match_operand 2 "general_operand" ""))]
3059 "TARGET_HAS_XFLOATING_LIBS"
3060 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3062 (define_insn "*sqrtsf2_ieee"
3063 [(set (match_operand:SF 0 "register_operand" "=&f")
3064 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3065 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3066 "sqrt%,%/ %R1,%0"
3067 [(set_attr "type" "fsqrt")
3068 (set_attr "opsize" "si")
3069 (set_attr "trap" "yes")
3070 (set_attr "round_suffix" "normal")
3071 (set_attr "trap_suffix" "u_su_sui")])
3073 (define_insn "sqrtsf2"
3074 [(set (match_operand:SF 0 "register_operand" "=f")
3075 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3076 "TARGET_FP && TARGET_FIX"
3077 "sqrt%,%/ %R1,%0"
3078 [(set_attr "type" "fsqrt")
3079 (set_attr "opsize" "si")
3080 (set_attr "trap" "yes")
3081 (set_attr "round_suffix" "normal")
3082 (set_attr "trap_suffix" "u_su_sui")])
3084 (define_insn "*sqrtdf2_ieee"
3085 [(set (match_operand:DF 0 "register_operand" "=&f")
3086 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3087 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3088 "sqrt%-%/ %R1,%0"
3089 [(set_attr "type" "fsqrt")
3090 (set_attr "trap" "yes")
3091 (set_attr "round_suffix" "normal")
3092 (set_attr "trap_suffix" "u_su_sui")])
3094 (define_insn "sqrtdf2"
3095 [(set (match_operand:DF 0 "register_operand" "=f")
3096 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3097 "TARGET_FP && TARGET_FIX"
3098 "sqrt%-%/ %R1,%0"
3099 [(set_attr "type" "fsqrt")
3100 (set_attr "trap" "yes")
3101 (set_attr "round_suffix" "normal")
3102 (set_attr "trap_suffix" "u_su_sui")])
3103 \f
3104 ;; Next are all the integer comparisons, and conditional moves and branches
3105 ;; and some of the related define_expand's and define_split's.
3107 (define_insn "*setcc_internal"
3108 [(set (match_operand 0 "register_operand" "=r")
3109 (match_operator 1 "alpha_comparison_operator"
3110 [(match_operand:DI 2 "register_operand" "r")
3111 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3112 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3113 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3114 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3115 "cmp%C1 %2,%3,%0"
3116 [(set_attr "type" "icmp")])
3118 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3119 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3120 ;; from cse on.
3121 (define_insn "*setcc_swapped_internal"
3122 [(set (match_operand 0 "register_operand" "=r")
3123 (match_operator 1 "alpha_swapped_comparison_operator"
3124 [(match_operand:DI 2 "register_operand" "r")
3125 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3126 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3127 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3128 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3129 "cmp%c1 %r3,%2,%0"
3130 [(set_attr "type" "icmp")])
3132 ;; Use match_operator rather than ne directly so that we can match
3133 ;; multiple integer modes.
3134 (define_insn "*setne_internal"
3135 [(set (match_operand 0 "register_operand" "=r")
3136 (match_operator 1 "signed_comparison_operator"
3137 [(match_operand:DI 2 "register_operand" "r")
3138 (const_int 0)]))]
3139 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3140 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3141 && GET_CODE (operands[1]) == NE
3142 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3143 "cmpult $31,%2,%0"
3144 [(set_attr "type" "icmp")])
3146 ;; The mode folding trick can't be used with const_int operands, since
3147 ;; reload needs to know the proper mode.
3148 ;;
3149 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3150 ;; in order to create more pairs of constants. As long as we're allowing
3151 ;; two constants at the same time, and will have to reload one of them...
3153 (define_insn "*movqicc_internal"
3154 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3155 (if_then_else:QI
3156 (match_operator 2 "signed_comparison_operator"
3157 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3158 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3159 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3160 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3161 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3162 "@
3163 cmov%C2 %r3,%1,%0
3164 cmov%D2 %r3,%5,%0
3165 cmov%c2 %r4,%1,%0
3166 cmov%d2 %r4,%5,%0"
3167 [(set_attr "type" "icmov")])
3169 (define_insn "*movhicc_internal"
3170 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3171 (if_then_else:HI
3172 (match_operator 2 "signed_comparison_operator"
3173 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3174 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3175 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3176 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3177 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3178 "@
3179 cmov%C2 %r3,%1,%0
3180 cmov%D2 %r3,%5,%0
3181 cmov%c2 %r4,%1,%0
3182 cmov%d2 %r4,%5,%0"
3183 [(set_attr "type" "icmov")])
3185 (define_insn "*movsicc_internal"
3186 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3187 (if_then_else:SI
3188 (match_operator 2 "signed_comparison_operator"
3189 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3190 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3191 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3192 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3193 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3194 "@
3195 cmov%C2 %r3,%1,%0
3196 cmov%D2 %r3,%5,%0
3197 cmov%c2 %r4,%1,%0
3198 cmov%d2 %r4,%5,%0"
3199 [(set_attr "type" "icmov")])
3201 (define_insn "*movdicc_internal"
3202 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3203 (if_then_else:DI
3204 (match_operator 2 "signed_comparison_operator"
3205 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3206 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3207 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3208 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3209 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3210 "@
3211 cmov%C2 %r3,%1,%0
3212 cmov%D2 %r3,%5,%0
3213 cmov%c2 %r4,%1,%0
3214 cmov%d2 %r4,%5,%0"
3215 [(set_attr "type" "icmov")])
3217 (define_insn "*movqicc_lbc"
3218 [(set (match_operand:QI 0 "register_operand" "=r,r")
3219 (if_then_else:QI
3220 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3221 (const_int 1)
3222 (const_int 0))
3223 (const_int 0))
3224 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3225 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3226 ""
3227 "@
3228 cmovlbc %r2,%1,%0
3229 cmovlbs %r2,%3,%0"
3230 [(set_attr "type" "icmov")])
3232 (define_insn "*movhicc_lbc"
3233 [(set (match_operand:HI 0 "register_operand" "=r,r")
3234 (if_then_else:HI
3235 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3236 (const_int 1)
3237 (const_int 0))
3238 (const_int 0))
3239 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3240 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3241 ""
3242 "@
3243 cmovlbc %r2,%1,%0
3244 cmovlbs %r2,%3,%0"
3245 [(set_attr "type" "icmov")])
3247 (define_insn "*movsicc_lbc"
3248 [(set (match_operand:SI 0 "register_operand" "=r,r")
3249 (if_then_else:SI
3250 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3251 (const_int 1)
3252 (const_int 0))
3253 (const_int 0))
3254 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3255 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3256 ""
3257 "@
3258 cmovlbc %r2,%1,%0
3259 cmovlbs %r2,%3,%0"
3260 [(set_attr "type" "icmov")])
3262 (define_insn "*movdicc_lbc"
3263 [(set (match_operand:DI 0 "register_operand" "=r,r")
3264 (if_then_else:DI
3265 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3266 (const_int 1)
3267 (const_int 0))
3268 (const_int 0))
3269 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3270 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3271 ""
3272 "@
3273 cmovlbc %r2,%1,%0
3274 cmovlbs %r2,%3,%0"
3275 [(set_attr "type" "icmov")])
3277 (define_insn "*movqicc_lbs"
3278 [(set (match_operand:QI 0 "register_operand" "=r,r")
3279 (if_then_else:QI
3280 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3281 (const_int 1)
3282 (const_int 0))
3283 (const_int 0))
3284 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3285 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3286 ""
3287 "@
3288 cmovlbs %r2,%1,%0
3289 cmovlbc %r2,%3,%0"
3290 [(set_attr "type" "icmov")])
3292 (define_insn "*movhicc_lbs"
3293 [(set (match_operand:HI 0 "register_operand" "=r,r")
3294 (if_then_else:HI
3295 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3296 (const_int 1)
3297 (const_int 0))
3298 (const_int 0))
3299 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3300 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3301 ""
3302 "@
3303 cmovlbs %r2,%1,%0
3304 cmovlbc %r2,%3,%0"
3305 [(set_attr "type" "icmov")])
3307 (define_insn "*movsicc_lbs"
3308 [(set (match_operand:SI 0 "register_operand" "=r,r")
3309 (if_then_else:SI
3310 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3311 (const_int 1)
3312 (const_int 0))
3313 (const_int 0))
3314 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3315 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3316 ""
3317 "@
3318 cmovlbs %r2,%1,%0
3319 cmovlbc %r2,%3,%0"
3320 [(set_attr "type" "icmov")])
3322 (define_insn "*movdicc_lbs"
3323 [(set (match_operand:DI 0 "register_operand" "=r,r")
3324 (if_then_else:DI
3325 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3326 (const_int 1)
3327 (const_int 0))
3328 (const_int 0))
3329 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3330 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3331 ""
3332 "@
3333 cmovlbs %r2,%1,%0
3334 cmovlbc %r2,%3,%0"
3335 [(set_attr "type" "icmov")])
3337 ;; For ABS, we have two choices, depending on whether the input and output
3338 ;; registers are the same or not.
3339 (define_expand "absdi2"
3340 [(set (match_operand:DI 0 "register_operand" "")
3341 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3342 ""
3343 {
3344 if (rtx_equal_p (operands[0], operands[1]))
3345 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3346 else
3347 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3348 DONE;
3349 })
3351 (define_expand "absdi2_same"
3352 [(set (match_operand:DI 1 "register_operand" "")
3353 (neg:DI (match_operand:DI 0 "register_operand" "")))
3354 (set (match_dup 0)
3355 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3356 (match_dup 0)
3357 (match_dup 1)))]
3358 ""
3359 "")
3361 (define_expand "absdi2_diff"
3362 [(set (match_operand:DI 0 "register_operand" "")
3363 (neg:DI (match_operand:DI 1 "register_operand" "")))
3364 (set (match_dup 0)
3365 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3366 (match_dup 0)
3367 (match_dup 1)))]
3368 ""
3369 "")
3371 (define_split
3372 [(set (match_operand:DI 0 "register_operand" "")
3373 (abs:DI (match_dup 0)))
3374 (clobber (match_operand:DI 1 "register_operand" ""))]
3375 ""
3376 [(set (match_dup 1) (neg:DI (match_dup 0)))
3377 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3378 (match_dup 0) (match_dup 1)))]
3379 "")
3381 (define_split
3382 [(set (match_operand:DI 0 "register_operand" "")
3383 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3384 "! rtx_equal_p (operands[0], operands[1])"
3385 [(set (match_dup 0) (neg:DI (match_dup 1)))
3386 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3387 (match_dup 0) (match_dup 1)))]
3388 "")
3390 (define_split
3391 [(set (match_operand:DI 0 "register_operand" "")
3392 (neg:DI (abs:DI (match_dup 0))))
3393 (clobber (match_operand:DI 1 "register_operand" ""))]
3394 ""
3395 [(set (match_dup 1) (neg:DI (match_dup 0)))
3396 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3397 (match_dup 0) (match_dup 1)))]
3398 "")
3400 (define_split
3401 [(set (match_operand:DI 0 "register_operand" "")
3402 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3403 "! rtx_equal_p (operands[0], operands[1])"
3404 [(set (match_dup 0) (neg:DI (match_dup 1)))
3405 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3406 (match_dup 0) (match_dup 1)))]
3407 "")
3409 (define_insn "sminqi3"
3410 [(set (match_operand:QI 0 "register_operand" "=r")
3411 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3412 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3413 "TARGET_MAX"
3414 "minsb8 %r1,%2,%0"
3415 [(set_attr "type" "mvi")])
3417 (define_insn "uminqi3"
3418 [(set (match_operand:QI 0 "register_operand" "=r")
3419 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3420 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3421 "TARGET_MAX"
3422 "minub8 %r1,%2,%0"
3423 [(set_attr "type" "mvi")])
3425 (define_insn "smaxqi3"
3426 [(set (match_operand:QI 0 "register_operand" "=r")
3427 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3428 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3429 "TARGET_MAX"
3430 "maxsb8 %r1,%2,%0"
3431 [(set_attr "type" "mvi")])
3433 (define_insn "umaxqi3"
3434 [(set (match_operand:QI 0 "register_operand" "=r")
3435 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3436 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3437 "TARGET_MAX"
3438 "maxub8 %r1,%2,%0"
3439 [(set_attr "type" "mvi")])
3441 (define_insn "sminhi3"
3442 [(set (match_operand:HI 0 "register_operand" "=r")
3443 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3444 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3445 "TARGET_MAX"
3446 "minsw4 %r1,%2,%0"
3447 [(set_attr "type" "mvi")])
3449 (define_insn "uminhi3"
3450 [(set (match_operand:HI 0 "register_operand" "=r")
3451 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3452 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3453 "TARGET_MAX"
3454 "minuw4 %r1,%2,%0"
3455 [(set_attr "type" "mvi")])
3457 (define_insn "smaxhi3"
3458 [(set (match_operand:HI 0 "register_operand" "=r")
3459 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3460 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3461 "TARGET_MAX"
3462 "maxsw4 %r1,%2,%0"
3463 [(set_attr "type" "mvi")])
3465 (define_insn "umaxhi3"
3466 [(set (match_operand:HI 0 "register_operand" "=r")
3467 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3468 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3469 "TARGET_MAX"
3470 "maxuw4 %r1,%2,%0"
3471 [(set_attr "type" "mvi")])
3473 (define_expand "smaxdi3"
3474 [(set (match_dup 3)
3475 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3476 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3477 (set (match_operand:DI 0 "register_operand" "")
3478 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3479 (match_dup 1) (match_dup 2)))]
3480 ""
3481 { operands[3] = gen_reg_rtx (DImode); })
3483 (define_split
3484 [(set (match_operand:DI 0 "register_operand" "")
3485 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3486 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3487 (clobber (match_operand:DI 3 "register_operand" ""))]
3488 "operands[2] != const0_rtx"
3489 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3490 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3491 (match_dup 1) (match_dup 2)))]
3492 "")
3494 (define_insn "*smax_const0"
3495 [(set (match_operand:DI 0 "register_operand" "=r")
3496 (smax:DI (match_operand:DI 1 "register_operand" "0")
3497 (const_int 0)))]
3498 ""
3499 "cmovlt %0,0,%0"
3500 [(set_attr "type" "icmov")])
3502 (define_expand "smindi3"
3503 [(set (match_dup 3)
3504 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3505 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3506 (set (match_operand:DI 0 "register_operand" "")
3507 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3508 (match_dup 1) (match_dup 2)))]
3509 ""
3510 { operands[3] = gen_reg_rtx (DImode); })
3512 (define_split
3513 [(set (match_operand:DI 0 "register_operand" "")
3514 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3515 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3516 (clobber (match_operand:DI 3 "register_operand" ""))]
3517 "operands[2] != const0_rtx"
3518 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3519 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3520 (match_dup 1) (match_dup 2)))]
3521 "")
3523 (define_insn "*smin_const0"
3524 [(set (match_operand:DI 0 "register_operand" "=r")
3525 (smin:DI (match_operand:DI 1 "register_operand" "0")
3526 (const_int 0)))]
3527 ""
3528 "cmovgt %0,0,%0"
3529 [(set_attr "type" "icmov")])
3531 (define_expand "umaxdi3"
3532 [(set (match_dup 3)
3533 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3534 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3535 (set (match_operand:DI 0 "register_operand" "")
3536 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3537 (match_dup 1) (match_dup 2)))]
3538 ""
3539 "operands[3] = gen_reg_rtx (DImode);")
3541 (define_split
3542 [(set (match_operand:DI 0 "register_operand" "")
3543 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3544 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3545 (clobber (match_operand:DI 3 "register_operand" ""))]
3546 "operands[2] != const0_rtx"
3547 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3548 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3549 (match_dup 1) (match_dup 2)))]
3550 "")
3552 (define_expand "umindi3"
3553 [(set (match_dup 3)
3554 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3555 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3556 (set (match_operand:DI 0 "register_operand" "")
3557 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3558 (match_dup 1) (match_dup 2)))]
3559 ""
3560 "operands[3] = gen_reg_rtx (DImode);")
3562 (define_split
3563 [(set (match_operand:DI 0 "register_operand" "")
3564 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3565 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3566 (clobber (match_operand:DI 3 "register_operand" ""))]
3567 "operands[2] != const0_rtx"
3568 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3569 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3570 (match_dup 1) (match_dup 2)))]
3571 "")
3573 (define_insn "*bcc_normal"
3574 [(set (pc)
3575 (if_then_else
3576 (match_operator 1 "signed_comparison_operator"
3577 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3578 (const_int 0)])
3579 (label_ref (match_operand 0 "" ""))
3580 (pc)))]
3581 ""
3582 "b%C1 %r2,%0"
3583 [(set_attr "type" "ibr")])
3585 (define_insn "*bcc_reverse"
3586 [(set (pc)
3587 (if_then_else
3588 (match_operator 1 "signed_comparison_operator"
3589 [(match_operand:DI 2 "register_operand" "r")
3590 (const_int 0)])
3592 (pc)
3593 (label_ref (match_operand 0 "" ""))))]
3594 ""
3595 "b%c1 %2,%0"
3596 [(set_attr "type" "ibr")])
3598 (define_insn "*blbs_normal"
3599 [(set (pc)
3600 (if_then_else
3601 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3602 (const_int 1)
3603 (const_int 0))
3604 (const_int 0))
3605 (label_ref (match_operand 0 "" ""))
3606 (pc)))]
3607 ""
3608 "blbs %r1,%0"
3609 [(set_attr "type" "ibr")])
3611 (define_insn "*blbc_normal"
3612 [(set (pc)
3613 (if_then_else
3614 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3615 (const_int 1)
3616 (const_int 0))
3617 (const_int 0))
3618 (label_ref (match_operand 0 "" ""))
3619 (pc)))]
3620 ""
3621 "blbc %r1,%0"
3622 [(set_attr "type" "ibr")])
3624 (define_split
3625 [(parallel
3626 [(set (pc)
3627 (if_then_else
3628 (match_operator 1 "comparison_operator"
3629 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3630 (const_int 1)
3631 (match_operand:DI 3 "const_int_operand" ""))
3632 (const_int 0)])
3633 (label_ref (match_operand 0 "" ""))
3634 (pc)))
3635 (clobber (match_operand:DI 4 "register_operand" ""))])]
3636 "INTVAL (operands[3]) != 0"
3637 [(set (match_dup 4)
3638 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3639 (set (pc)
3640 (if_then_else (match_op_dup 1
3641 [(zero_extract:DI (match_dup 4)
3642 (const_int 1)
3643 (const_int 0))
3644 (const_int 0)])
3645 (label_ref (match_dup 0))
3646 (pc)))]
3647 "")
3648 \f
3649 ;; The following are the corresponding floating-point insns. Recall
3650 ;; we need to have variants that expand the arguments from SFmode
3651 ;; to DFmode.
3653 (define_insn "*cmpdf_ieee"
3654 [(set (match_operand:DF 0 "register_operand" "=&f")
3655 (match_operator:DF 1 "alpha_fp_comparison_operator"
3656 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3657 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3658 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3659 "cmp%-%C1%/ %R2,%R3,%0"
3660 [(set_attr "type" "fadd")
3661 (set_attr "trap" "yes")
3662 (set_attr "trap_suffix" "su")])
3664 (define_insn "*cmpdf_internal"
3665 [(set (match_operand:DF 0 "register_operand" "=f")
3666 (match_operator:DF 1 "alpha_fp_comparison_operator"
3667 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3668 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3669 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3670 "cmp%-%C1%/ %R2,%R3,%0"
3671 [(set_attr "type" "fadd")
3672 (set_attr "trap" "yes")
3673 (set_attr "trap_suffix" "su")])
3675 (define_insn "*cmpdf_ieee_ext1"
3676 [(set (match_operand:DF 0 "register_operand" "=&f")
3677 (match_operator:DF 1 "alpha_fp_comparison_operator"
3678 [(float_extend:DF
3679 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3680 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3681 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3682 "cmp%-%C1%/ %R2,%R3,%0"
3683 [(set_attr "type" "fadd")
3684 (set_attr "trap" "yes")
3685 (set_attr "trap_suffix" "su")])
3687 (define_insn "*cmpdf_ext1"
3688 [(set (match_operand:DF 0 "register_operand" "=f")
3689 (match_operator:DF 1 "alpha_fp_comparison_operator"
3690 [(float_extend:DF
3691 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3692 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3693 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3694 "cmp%-%C1%/ %R2,%R3,%0"
3695 [(set_attr "type" "fadd")
3696 (set_attr "trap" "yes")
3697 (set_attr "trap_suffix" "su")])
3699 (define_insn "*cmpdf_ieee_ext2"
3700 [(set (match_operand:DF 0 "register_operand" "=&f")
3701 (match_operator:DF 1 "alpha_fp_comparison_operator"
3702 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3703 (float_extend:DF
3704 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3705 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3706 "cmp%-%C1%/ %R2,%R3,%0"
3707 [(set_attr "type" "fadd")
3708 (set_attr "trap" "yes")
3709 (set_attr "trap_suffix" "su")])
3711 (define_insn "*cmpdf_ext2"
3712 [(set (match_operand:DF 0 "register_operand" "=f")
3713 (match_operator:DF 1 "alpha_fp_comparison_operator"
3714 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3715 (float_extend:DF
3716 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3717 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3718 "cmp%-%C1%/ %R2,%R3,%0"
3719 [(set_attr "type" "fadd")
3720 (set_attr "trap" "yes")
3721 (set_attr "trap_suffix" "su")])
3723 (define_insn "*cmpdf_ieee_ext3"
3724 [(set (match_operand:DF 0 "register_operand" "=&f")
3725 (match_operator:DF 1 "alpha_fp_comparison_operator"
3726 [(float_extend:DF
3727 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3728 (float_extend:DF
3729 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3730 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3731 "cmp%-%C1%/ %R2,%R3,%0"
3732 [(set_attr "type" "fadd")
3733 (set_attr "trap" "yes")
3734 (set_attr "trap_suffix" "su")])
3736 (define_insn "*cmpdf_ext3"
3737 [(set (match_operand:DF 0 "register_operand" "=f")
3738 (match_operator:DF 1 "alpha_fp_comparison_operator"
3739 [(float_extend:DF
3740 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3741 (float_extend:DF
3742 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3743 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3744 "cmp%-%C1%/ %R2,%R3,%0"
3745 [(set_attr "type" "fadd")
3746 (set_attr "trap" "yes")
3747 (set_attr "trap_suffix" "su")])
3749 (define_insn "*movdfcc_internal"
3750 [(set (match_operand:DF 0 "register_operand" "=f,f")
3751 (if_then_else:DF
3752 (match_operator 3 "signed_comparison_operator"
3753 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3754 (match_operand:DF 2 "const0_operand" "G,G")])
3755 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3756 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3757 "TARGET_FP"
3758 "@
3759 fcmov%C3 %R4,%R1,%0
3760 fcmov%D3 %R4,%R5,%0"
3761 [(set_attr "type" "fcmov")])
3763 (define_insn "*movsfcc_internal"
3764 [(set (match_operand:SF 0 "register_operand" "=f,f")
3765 (if_then_else:SF
3766 (match_operator 3 "signed_comparison_operator"
3767 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3768 (match_operand:DF 2 "const0_operand" "G,G")])
3769 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3770 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3771 "TARGET_FP"
3772 "@
3773 fcmov%C3 %R4,%R1,%0
3774 fcmov%D3 %R4,%R5,%0"
3775 [(set_attr "type" "fcmov")])
3777 (define_insn "*movdfcc_ext1"
3778 [(set (match_operand:DF 0 "register_operand" "=f,f")
3779 (if_then_else:DF
3780 (match_operator 3 "signed_comparison_operator"
3781 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3782 (match_operand:DF 2 "const0_operand" "G,G")])
3783 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3784 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3785 "TARGET_FP"
3786 "@
3787 fcmov%C3 %R4,%R1,%0
3788 fcmov%D3 %R4,%R5,%0"
3789 [(set_attr "type" "fcmov")])
3791 (define_insn "*movdfcc_ext2"
3792 [(set (match_operand:DF 0 "register_operand" "=f,f")
3793 (if_then_else:DF
3794 (match_operator 3 "signed_comparison_operator"
3795 [(float_extend:DF
3796 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3797 (match_operand:DF 2 "const0_operand" "G,G")])
3798 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3799 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3800 "TARGET_FP"
3801 "@
3802 fcmov%C3 %R4,%R1,%0
3803 fcmov%D3 %R4,%R5,%0"
3804 [(set_attr "type" "fcmov")])
3806 (define_insn "*movdfcc_ext3"
3807 [(set (match_operand:SF 0 "register_operand" "=f,f")
3808 (if_then_else:SF
3809 (match_operator 3 "signed_comparison_operator"
3810 [(float_extend:DF
3811 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3812 (match_operand:DF 2 "const0_operand" "G,G")])
3813 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3814 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3815 "TARGET_FP"
3816 "@
3817 fcmov%C3 %R4,%R1,%0
3818 fcmov%D3 %R4,%R5,%0"
3819 [(set_attr "type" "fcmov")])
3821 (define_insn "*movdfcc_ext4"
3822 [(set (match_operand:DF 0 "register_operand" "=f,f")
3823 (if_then_else:DF
3824 (match_operator 3 "signed_comparison_operator"
3825 [(float_extend:DF
3826 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3827 (match_operand:DF 2 "const0_operand" "G,G")])
3828 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3829 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3830 "TARGET_FP"
3831 "@
3832 fcmov%C3 %R4,%R1,%0
3833 fcmov%D3 %R4,%R5,%0"
3834 [(set_attr "type" "fcmov")])
3836 (define_expand "smaxdf3"
3837 [(set (match_dup 3)
3838 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3839 (match_operand:DF 2 "reg_or_0_operand" "")))
3840 (set (match_operand:DF 0 "register_operand" "")
3841 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3842 (match_dup 1) (match_dup 2)))]
3843 "TARGET_FP"
3844 {
3845 operands[3] = gen_reg_rtx (DFmode);
3846 operands[4] = CONST0_RTX (DFmode);
3847 })
3849 (define_expand "smindf3"
3850 [(set (match_dup 3)
3851 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3852 (match_operand:DF 2 "reg_or_0_operand" "")))
3853 (set (match_operand:DF 0 "register_operand" "")
3854 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3855 (match_dup 1) (match_dup 2)))]
3856 "TARGET_FP"
3857 {
3858 operands[3] = gen_reg_rtx (DFmode);
3859 operands[4] = CONST0_RTX (DFmode);
3860 })
3862 (define_expand "smaxsf3"
3863 [(set (match_dup 3)
3864 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3865 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3866 (set (match_operand:SF 0 "register_operand" "")
3867 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3868 (match_dup 1) (match_dup 2)))]
3869 "TARGET_FP"
3870 {
3871 operands[3] = gen_reg_rtx (DFmode);
3872 operands[4] = CONST0_RTX (DFmode);
3873 })
3875 (define_expand "sminsf3"
3876 [(set (match_dup 3)
3877 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3878 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3879 (set (match_operand:SF 0 "register_operand" "")
3880 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3881 (match_dup 1) (match_dup 2)))]
3882 "TARGET_FP"
3883 {
3884 operands[3] = gen_reg_rtx (DFmode);
3885 operands[4] = CONST0_RTX (DFmode);
3886 })
3888 (define_insn "*fbcc_normal"
3889 [(set (pc)
3890 (if_then_else
3891 (match_operator 1 "signed_comparison_operator"
3892 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3893 (match_operand:DF 3 "const0_operand" "G")])
3894 (label_ref (match_operand 0 "" ""))
3895 (pc)))]
3896 "TARGET_FP"
3897 "fb%C1 %R2,%0"
3898 [(set_attr "type" "fbr")])
3900 (define_insn "*fbcc_ext_normal"
3901 [(set (pc)
3902 (if_then_else
3903 (match_operator 1 "signed_comparison_operator"
3904 [(float_extend:DF
3905 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3906 (match_operand:DF 3 "const0_operand" "G")])
3907 (label_ref (match_operand 0 "" ""))
3908 (pc)))]
3909 "TARGET_FP"
3910 "fb%C1 %R2,%0"
3911 [(set_attr "type" "fbr")])
3912 \f
3913 ;; These are the main define_expand's used to make conditional branches
3914 ;; and compares.
3916 (define_expand "cmpdf"
3917 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3918 (match_operand:DF 1 "reg_or_0_operand" "")))]
3919 "TARGET_FP"
3920 {
3921 alpha_compare.op0 = operands[0];
3922 alpha_compare.op1 = operands[1];
3923 alpha_compare.fp_p = 1;
3924 DONE;
3925 })
3927 (define_expand "cmptf"
3928 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3929 (match_operand:TF 1 "general_operand" "")))]
3930 "TARGET_HAS_XFLOATING_LIBS"
3931 {
3932 alpha_compare.op0 = operands[0];
3933 alpha_compare.op1 = operands[1];
3934 alpha_compare.fp_p = 1;
3935 DONE;
3936 })
3938 (define_expand "cmpdi"
3939 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3940 (match_operand:DI 1 "some_operand" "")))]
3941 ""
3942 {
3943 alpha_compare.op0 = operands[0];
3944 alpha_compare.op1 = operands[1];
3945 alpha_compare.fp_p = 0;
3946 DONE;
3947 })
3949 (define_expand "beq"
3950 [(set (pc)
3951 (if_then_else (match_dup 1)
3952 (label_ref (match_operand 0 "" ""))
3953 (pc)))]
3954 ""
3955 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3957 (define_expand "bne"
3958 [(set (pc)
3959 (if_then_else (match_dup 1)
3960 (label_ref (match_operand 0 "" ""))
3961 (pc)))]
3962 ""
3963 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3965 (define_expand "blt"
3966 [(set (pc)
3967 (if_then_else (match_dup 1)
3968 (label_ref (match_operand 0 "" ""))
3969 (pc)))]
3970 ""
3971 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3973 (define_expand "ble"
3974 [(set (pc)
3975 (if_then_else (match_dup 1)
3976 (label_ref (match_operand 0 "" ""))
3977 (pc)))]
3978 ""
3979 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3981 (define_expand "bgt"
3982 [(set (pc)
3983 (if_then_else (match_dup 1)
3984 (label_ref (match_operand 0 "" ""))
3985 (pc)))]
3986 ""
3987 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3989 (define_expand "bge"
3990 [(set (pc)
3991 (if_then_else (match_dup 1)
3992 (label_ref (match_operand 0 "" ""))
3993 (pc)))]
3994 ""
3995 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3997 (define_expand "bltu"
3998 [(set (pc)
3999 (if_then_else (match_dup 1)
4000 (label_ref (match_operand 0 "" ""))
4001 (pc)))]
4002 ""
4003 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4005 (define_expand "bleu"
4006 [(set (pc)
4007 (if_then_else (match_dup 1)
4008 (label_ref (match_operand 0 "" ""))
4009 (pc)))]
4010 ""
4011 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4013 (define_expand "bgtu"
4014 [(set (pc)
4015 (if_then_else (match_dup 1)
4016 (label_ref (match_operand 0 "" ""))
4017 (pc)))]
4018 ""
4019 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4021 (define_expand "bgeu"
4022 [(set (pc)
4023 (if_then_else (match_dup 1)
4024 (label_ref (match_operand 0 "" ""))
4025 (pc)))]
4026 ""
4027 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4029 (define_expand "bunordered"
4030 [(set (pc)
4031 (if_then_else (match_dup 1)
4032 (label_ref (match_operand 0 "" ""))
4033 (pc)))]
4034 ""
4035 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4037 (define_expand "bordered"
4038 [(set (pc)
4039 (if_then_else (match_dup 1)
4040 (label_ref (match_operand 0 "" ""))
4041 (pc)))]
4042 ""
4043 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4045 (define_expand "seq"
4046 [(set (match_operand:DI 0 "register_operand" "")
4047 (match_dup 1))]
4048 ""
4049 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4051 (define_expand "sne"
4052 [(set (match_operand:DI 0 "register_operand" "")
4053 (match_dup 1))]
4054 ""
4055 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4057 (define_expand "slt"
4058 [(set (match_operand:DI 0 "register_operand" "")
4059 (match_dup 1))]
4060 ""
4061 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4063 (define_expand "sle"
4064 [(set (match_operand:DI 0 "register_operand" "")
4065 (match_dup 1))]
4066 ""
4067 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4069 (define_expand "sgt"
4070 [(set (match_operand:DI 0 "register_operand" "")
4071 (match_dup 1))]
4072 ""
4073 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4075 (define_expand "sge"
4076 [(set (match_operand:DI 0 "register_operand" "")
4077 (match_dup 1))]
4078 ""
4079 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4081 (define_expand "sltu"
4082 [(set (match_operand:DI 0 "register_operand" "")
4083 (match_dup 1))]
4084 ""
4085 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4087 (define_expand "sleu"
4088 [(set (match_operand:DI 0 "register_operand" "")
4089 (match_dup 1))]
4090 ""
4091 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4093 (define_expand "sgtu"
4094 [(set (match_operand:DI 0 "register_operand" "")
4095 (match_dup 1))]
4096 ""
4097 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4099 (define_expand "sgeu"
4100 [(set (match_operand:DI 0 "register_operand" "")
4101 (match_dup 1))]
4102 ""
4103 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4105 (define_expand "sunordered"
4106 [(set (match_operand:DI 0 "register_operand" "")
4107 (match_dup 1))]
4108 ""
4109 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4111 (define_expand "sordered"
4112 [(set (match_operand:DI 0 "register_operand" "")
4113 (match_dup 1))]
4114 ""
4115 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4116 \f
4117 ;; These are the main define_expand's used to make conditional moves.
4119 (define_expand "movsicc"
4120 [(set (match_operand:SI 0 "register_operand" "")
4121 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4122 (match_operand:SI 2 "reg_or_8bit_operand" "")
4123 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4124 ""
4125 {
4126 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4127 FAIL;
4128 })
4130 (define_expand "movdicc"
4131 [(set (match_operand:DI 0 "register_operand" "")
4132 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4133 (match_operand:DI 2 "reg_or_8bit_operand" "")
4134 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4135 ""
4136 {
4137 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4138 FAIL;
4139 })
4141 (define_expand "movsfcc"
4142 [(set (match_operand:SF 0 "register_operand" "")
4143 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4144 (match_operand:SF 2 "reg_or_8bit_operand" "")
4145 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4146 ""
4147 {
4148 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4149 FAIL;
4150 })
4152 (define_expand "movdfcc"
4153 [(set (match_operand:DF 0 "register_operand" "")
4154 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4155 (match_operand:DF 2 "reg_or_8bit_operand" "")
4156 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4157 ""
4158 {
4159 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4160 FAIL;
4161 })
4162 \f
4163 ;; These define_split definitions are used in cases when comparisons have
4164 ;; not be stated in the correct way and we need to reverse the second
4165 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4166 ;; comparison that tests the result being reversed. We have one define_split
4167 ;; for each use of a comparison. They do not match valid insns and need
4168 ;; not generate valid insns.
4169 ;;
4170 ;; We can also handle equality comparisons (and inequality comparisons in
4171 ;; cases where the resulting add cannot overflow) by doing an add followed by
4172 ;; a comparison with zero. This is faster since the addition takes one
4173 ;; less cycle than a compare when feeding into a conditional move.
4174 ;; For this case, we also have an SImode pattern since we can merge the add
4175 ;; and sign extend and the order doesn't matter.
4176 ;;
4177 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4178 ;; operation could have been generated.
4180 (define_split
4181 [(set (match_operand:DI 0 "register_operand" "")
4182 (if_then_else:DI
4183 (match_operator 1 "comparison_operator"
4184 [(match_operand:DI 2 "reg_or_0_operand" "")
4185 (match_operand:DI 3 "reg_or_cint_operand" "")])
4186 (match_operand:DI 4 "reg_or_cint_operand" "")
4187 (match_operand:DI 5 "reg_or_cint_operand" "")))
4188 (clobber (match_operand:DI 6 "register_operand" ""))]
4189 "operands[3] != const0_rtx"
4190 [(set (match_dup 6) (match_dup 7))
4191 (set (match_dup 0)
4192 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4193 {
4194 enum rtx_code code = GET_CODE (operands[1]);
4195 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4197 /* If we are comparing for equality with a constant and that constant
4198 appears in the arm when the register equals the constant, use the
4199 register since that is more likely to match (and to produce better code
4200 if both would). */
4202 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4203 && rtx_equal_p (operands[4], operands[3]))
4204 operands[4] = operands[2];
4206 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4207 && rtx_equal_p (operands[5], operands[3]))
4208 operands[5] = operands[2];
4210 if (code == NE || code == EQ
4211 || (extended_count (operands[2], DImode, unsignedp) >= 1
4212 && extended_count (operands[3], DImode, unsignedp) >= 1))
4213 {
4214 if (GET_CODE (operands[3]) == CONST_INT)
4215 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4216 GEN_INT (- INTVAL (operands[3])));
4217 else
4218 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4220 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4221 }
4223 else if (code == EQ || code == LE || code == LT
4224 || code == LEU || code == LTU)
4225 {
4226 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4227 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4228 }
4229 else
4230 {
4231 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4232 operands[2], operands[3]);
4233 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4234 }
4235 })
4237 (define_split
4238 [(set (match_operand:DI 0 "register_operand" "")
4239 (if_then_else:DI
4240 (match_operator 1 "comparison_operator"
4241 [(match_operand:SI 2 "reg_or_0_operand" "")
4242 (match_operand:SI 3 "reg_or_cint_operand" "")])
4243 (match_operand:DI 4 "reg_or_8bit_operand" "")
4244 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4245 (clobber (match_operand:DI 6 "register_operand" ""))]
4246 "operands[3] != const0_rtx
4247 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4248 [(set (match_dup 6) (match_dup 7))
4249 (set (match_dup 0)
4250 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4251 {
4252 enum rtx_code code = GET_CODE (operands[1]);
4253 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4254 rtx tem;
4256 if ((code != NE && code != EQ
4257 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4258 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4259 FAIL;
4261 if (GET_CODE (operands[3]) == CONST_INT)
4262 tem = gen_rtx_PLUS (SImode, operands[2],
4263 GEN_INT (- INTVAL (operands[3])));
4264 else
4265 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4267 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4268 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4269 operands[6], const0_rtx);
4270 })
4272 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4274 (define_split
4275 [(set (match_operand 0 "register_operand" "")
4276 (if_then_else (match_operator 1 "signed_comparison_operator"
4277 [(match_operand:DI 2 "reg_or_0_operand" "")
4278 (const_int 0)])
4279 (match_operand 3 "const_int_operand" "")
4280 (match_operand 4 "const_int_operand" "")))]
4281 ""
4282 [(const_int 0)]
4283 {
4284 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4285 operands[2], operands[3], operands[4]))
4286 DONE;
4287 else
4288 FAIL;
4289 })
4291 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4292 ;; Oh well, we match it in movcc, so it must be partially our fault.
4293 (define_split
4294 [(set (match_operand 0 "register_operand" "")
4295 (if_then_else (match_operator 1 "signed_comparison_operator"
4296 [(const_int 0)
4297 (match_operand:DI 2 "reg_or_0_operand" "")])
4298 (match_operand 3 "const_int_operand" "")
4299 (match_operand 4 "const_int_operand" "")))]
4300 ""
4301 [(const_int 0)]
4302 {
4303 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4304 operands[0], operands[2], operands[3],
4305 operands[4]))
4306 DONE;
4307 else
4308 FAIL;
4309 })
4311 (define_insn_and_split "*cmp_sadd_di"
4312 [(set (match_operand:DI 0 "register_operand" "=r")
4313 (plus:DI (if_then_else:DI
4314 (match_operator 1 "alpha_zero_comparison_operator"
4315 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4316 (const_int 0)])
4317 (match_operand:DI 3 "const48_operand" "I")
4318 (const_int 0))
4319 (match_operand:DI 4 "sext_add_operand" "rIO")))
4320 (clobber (match_scratch:DI 5 "=r"))]
4321 ""
4322 "#"
4323 "! no_new_pseudos || reload_completed"
4324 [(set (match_dup 5)
4325 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4326 (set (match_dup 0)
4327 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4328 (match_dup 4)))]
4329 {
4330 if (! no_new_pseudos)
4331 operands[5] = gen_reg_rtx (DImode);
4332 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4333 operands[5] = operands[0];
4334 })
4336 (define_insn_and_split "*cmp_sadd_si"
4337 [(set (match_operand:SI 0 "register_operand" "=r")
4338 (plus:SI (if_then_else:SI
4339 (match_operator 1 "alpha_zero_comparison_operator"
4340 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4341 (const_int 0)])
4342 (match_operand:SI 3 "const48_operand" "I")
4343 (const_int 0))
4344 (match_operand:SI 4 "sext_add_operand" "rIO")))
4345 (clobber (match_scratch:SI 5 "=r"))]
4346 ""
4347 "#"
4348 "! no_new_pseudos || reload_completed"
4349 [(set (match_dup 5)
4350 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4351 (set (match_dup 0)
4352 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4353 (match_dup 4)))]
4354 {
4355 if (! no_new_pseudos)
4356 operands[5] = gen_reg_rtx (DImode);
4357 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4358 operands[5] = operands[0];
4359 })
4361 (define_insn_and_split "*cmp_sadd_sidi"
4362 [(set (match_operand:DI 0 "register_operand" "=r")
4363 (sign_extend:DI
4364 (plus:SI (if_then_else:SI
4365 (match_operator 1 "alpha_zero_comparison_operator"
4366 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4367 (const_int 0)])
4368 (match_operand:SI 3 "const48_operand" "I")
4369 (const_int 0))
4370 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4371 (clobber (match_scratch:SI 5 "=r"))]
4372 ""
4373 "#"
4374 "! no_new_pseudos || reload_completed"
4375 [(set (match_dup 5)
4376 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4377 (set (match_dup 0)
4378 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4379 (match_dup 4))))]
4380 {
4381 if (! no_new_pseudos)
4382 operands[5] = gen_reg_rtx (DImode);
4383 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4384 operands[5] = operands[0];
4385 })
4387 (define_insn_and_split "*cmp_ssub_di"
4388 [(set (match_operand:DI 0 "register_operand" "=r")
4389 (minus:DI (if_then_else:DI
4390 (match_operator 1 "alpha_zero_comparison_operator"
4391 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4392 (const_int 0)])
4393 (match_operand:DI 3 "const48_operand" "I")
4394 (const_int 0))
4395 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4396 (clobber (match_scratch:DI 5 "=r"))]
4397 ""
4398 "#"
4399 "! no_new_pseudos || reload_completed"
4400 [(set (match_dup 5)
4401 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4402 (set (match_dup 0)
4403 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4404 (match_dup 4)))]
4405 {
4406 if (! no_new_pseudos)
4407 operands[5] = gen_reg_rtx (DImode);
4408 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4409 operands[5] = operands[0];
4410 })
4412 (define_insn_and_split "*cmp_ssub_si"
4413 [(set (match_operand:SI 0 "register_operand" "=r")
4414 (minus:SI (if_then_else:SI
4415 (match_operator 1 "alpha_zero_comparison_operator"
4416 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4417 (const_int 0)])
4418 (match_operand:SI 3 "const48_operand" "I")
4419 (const_int 0))
4420 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4421 (clobber (match_scratch:SI 5 "=r"))]
4422 ""
4423 "#"
4424 "! no_new_pseudos || reload_completed"
4425 [(set (match_dup 5)
4426 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4427 (set (match_dup 0)
4428 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4429 (match_dup 4)))]
4430 {
4431 if (! no_new_pseudos)
4432 operands[5] = gen_reg_rtx (DImode);
4433 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4434 operands[5] = operands[0];
4435 })
4437 (define_insn_and_split "*cmp_ssub_sidi"
4438 [(set (match_operand:DI 0 "register_operand" "=r")
4439 (sign_extend:DI
4440 (minus:SI (if_then_else:SI
4441 (match_operator 1 "alpha_zero_comparison_operator"
4442 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4443 (const_int 0)])
4444 (match_operand:SI 3 "const48_operand" "I")
4445 (const_int 0))
4446 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4447 (clobber (match_scratch:SI 5 "=r"))]
4448 ""
4449 "#"
4450 "! no_new_pseudos || reload_completed"
4451 [(set (match_dup 5)
4452 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4453 (set (match_dup 0)
4454 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4455 (match_dup 4))))]
4456 {
4457 if (! no_new_pseudos)
4458 operands[5] = gen_reg_rtx (DImode);
4459 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4460 operands[5] = operands[0];
4461 })
4462 \f
4463 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4464 ;; work differently, so we have different patterns for each.
4466 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4467 ;; call. The CIW contains information about arguments passed in registers
4468 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4469 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4470 ;; in the presence of inlining since the CIWs for calls performed by the
4471 ;; inlined function must be stored in the SSIB of the function it is inlined
4472 ;; into as well. We encode the CIW in an unspec and append it to the list
4473 ;; of the CIWs for the current function only when the instruction for loading
4474 ;; $25 is generated.
4476 (define_expand "call"
4477 [(use (match_operand:DI 0 "" ""))
4478 (use (match_operand 1 "" ""))
4479 (use (match_operand 2 "" ""))
4480 (use (match_operand 3 "" ""))]
4481 ""
4482 {
4483 if (TARGET_ABI_WINDOWS_NT)
4484 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4485 else if (TARGET_ABI_OPEN_VMS)
4486 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4487 else if (TARGET_ABI_UNICOSMK)
4488 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4489 else
4490 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4491 DONE;
4492 })
4494 (define_expand "sibcall"
4495 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4496 (match_operand 1 "" ""))
4497 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4498 "TARGET_ABI_OSF"
4499 {
4500 gcc_assert (GET_CODE (operands[0]) == MEM);
4501 operands[0] = XEXP (operands[0], 0);
4502 })
4504 (define_expand "call_osf"
4505 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4506 (match_operand 1 "" ""))
4507 (use (reg:DI 29))
4508 (clobber (reg:DI 26))])]
4509 ""
4510 {
4511 gcc_assert (GET_CODE (operands[0]) == MEM);
4513 operands[0] = XEXP (operands[0], 0);
4514 if (! call_operand (operands[0], Pmode))
4515 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4516 })
4518 (define_expand "call_nt"
4519 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4520 (match_operand 1 "" ""))
4521 (clobber (reg:DI 26))])]
4522 ""
4523 {
4524 gcc_assert (GET_CODE (operands[0]) == MEM);
4526 operands[0] = XEXP (operands[0], 0);
4527 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4528 operands[0] = force_reg (DImode, operands[0]);
4529 })
4531 ;; Calls on Unicos/Mk are always indirect.
4532 ;; op 0: symbol ref for called function
4533 ;; op 1: CIW for $25 represented by an unspec
4535 (define_expand "call_umk"
4536 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4537 (match_operand 1 "" ""))
4538 (use (reg:DI 25))
4539 (clobber (reg:DI 26))])]
4540 ""
4541 {
4542 gcc_assert (GET_CODE (operands[0]) == MEM);
4544 /* Always load the address of the called function into a register;
4545 load the CIW in $25. */
4547 operands[0] = XEXP (operands[0], 0);
4548 if (GET_CODE (operands[0]) != REG)
4549 operands[0] = force_reg (DImode, operands[0]);
4551 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4552 })
4554 ;;
4555 ;; call openvms/alpha
4556 ;; op 0: symbol ref for called function
4557 ;; op 1: next_arg_reg (argument information value for R25)
4558 ;;
4559 (define_expand "call_vms"
4560 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4561 (match_operand 1 "" ""))
4562 (use (match_dup 2))
4563 (use (reg:DI 25))
4564 (use (reg:DI 26))
4565 (clobber (reg:DI 27))])]
4566 ""
4567 {
4568 gcc_assert (GET_CODE (operands[0]) == MEM);
4570 operands[0] = XEXP (operands[0], 0);
4572 /* Always load AI with argument information, then handle symbolic and
4573 indirect call differently. Load RA and set operands[2] to PV in
4574 both cases. */
4576 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4577 if (GET_CODE (operands[0]) == SYMBOL_REF)
4578 {
4579 alpha_need_linkage (XSTR (operands[0], 0), 0);
4581 operands[2] = const0_rtx;
4582 }
4583 else
4584 {
4585 emit_move_insn (gen_rtx_REG (Pmode, 26),
4586 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4587 operands[2] = operands[0];
4588 }
4590 })
4592 (define_expand "call_value"
4593 [(use (match_operand 0 "" ""))
4594 (use (match_operand:DI 1 "" ""))
4595 (use (match_operand 2 "" ""))
4596 (use (match_operand 3 "" ""))
4597 (use (match_operand 4 "" ""))]
4598 ""
4599 {
4600 if (TARGET_ABI_WINDOWS_NT)
4601 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4602 else if (TARGET_ABI_OPEN_VMS)
4603 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4604 operands[3]));
4605 else if (TARGET_ABI_UNICOSMK)
4606 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4607 operands[3]));
4608 else
4609 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4610 operands[2]));
4611 DONE;
4612 })
4614 (define_expand "sibcall_value"
4615 [(parallel [(set (match_operand 0 "" "")
4616 (call (mem:DI (match_operand 1 "" ""))
4617 (match_operand 2 "" "")))
4618 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4619 "TARGET_ABI_OSF"
4620 {
4621 gcc_assert (GET_CODE (operands[1]) == MEM);
4622 operands[1] = XEXP (operands[1], 0);
4623 })
4625 (define_expand "call_value_osf"
4626 [(parallel [(set (match_operand 0 "" "")
4627 (call (mem:DI (match_operand 1 "" ""))
4628 (match_operand 2 "" "")))
4629 (use (reg:DI 29))
4630 (clobber (reg:DI 26))])]
4631 ""
4632 {
4633 gcc_assert (GET_CODE (operands[1]) == MEM);
4635 operands[1] = XEXP (operands[1], 0);
4636 if (! call_operand (operands[1], Pmode))
4637 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4638 })
4640 (define_expand "call_value_nt"
4641 [(parallel [(set (match_operand 0 "" "")
4642 (call (mem:DI (match_operand 1 "" ""))
4643 (match_operand 2 "" "")))
4644 (clobber (reg:DI 26))])]
4645 ""
4646 {
4647 gcc_assert (GET_CODE (operands[1]) == MEM);
4649 operands[1] = XEXP (operands[1], 0);
4650 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4651 operands[1] = force_reg (DImode, operands[1]);
4652 })
4654 (define_expand "call_value_vms"
4655 [(parallel [(set (match_operand 0 "" "")
4656 (call (mem:DI (match_operand:DI 1 "" ""))
4657 (match_operand 2 "" "")))
4658 (use (match_dup 3))
4659 (use (reg:DI 25))
4660 (use (reg:DI 26))
4661 (clobber (reg:DI 27))])]
4662 ""
4663 {
4664 gcc_assert (GET_CODE (operands[1]) == MEM);
4666 operands[1] = XEXP (operands[1], 0);
4668 /* Always load AI with argument information, then handle symbolic and
4669 indirect call differently. Load RA and set operands[3] to PV in
4670 both cases. */
4672 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4673 if (GET_CODE (operands[1]) == SYMBOL_REF)
4674 {
4675 alpha_need_linkage (XSTR (operands[1], 0), 0);
4677 operands[3] = const0_rtx;
4678 }
4679 else
4680 {
4681 emit_move_insn (gen_rtx_REG (Pmode, 26),
4682 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4683 operands[3] = operands[1];
4684 }
4685 })
4687 (define_expand "call_value_umk"
4688 [(parallel [(set (match_operand 0 "" "")
4689 (call (mem:DI (match_operand 1 "" ""))
4690 (match_operand 2 "" "")))
4691 (use (reg:DI 25))
4692 (clobber (reg:DI 26))])]
4693 ""
4694 {
4695 gcc_assert (GET_CODE (operands[1]) == MEM);
4697 operands[1] = XEXP (operands[1], 0);
4698 if (GET_CODE (operands[1]) != REG)
4699 operands[1] = force_reg (DImode, operands[1]);
4701 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4702 })
4704 (define_insn "*call_osf_1_er"
4705 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4706 (match_operand 1 "" ""))
4707 (use (reg:DI 29))
4708 (clobber (reg:DI 26))]
4709 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4710 "@
4711 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4712 bsr $26,%0\t\t!samegp
4713 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4714 [(set_attr "type" "jsr")
4715 (set_attr "length" "12,*,16")])
4717 ;; We must use peep2 instead of a split because we need accurate life
4718 ;; information for $gp. Consider the case of { bar(); while (1); }.
4719 (define_peephole2
4720 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4721 (match_operand 1 "" ""))
4722 (use (reg:DI 29))
4723 (clobber (reg:DI 26))])]
4724 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4725 && ! samegp_function_operand (operands[0], Pmode)
4726 && (peep2_regno_dead_p (1, 29)
4727 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4728 [(parallel [(call (mem:DI (match_dup 2))
4729 (match_dup 1))
4730 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4731 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4732 (use (match_dup 0))
4733 (use (match_dup 3))])]
4734 {
4735 if (CONSTANT_P (operands[0]))
4736 {
4737 operands[2] = gen_rtx_REG (Pmode, 27);
4738 operands[3] = GEN_INT (alpha_next_sequence_number++);
4739 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4740 operands[0], operands[3]));
4741 }
4742 else
4743 {
4744 operands[2] = operands[0];
4745 operands[0] = const0_rtx;
4746 operands[3] = const0_rtx;
4747 }
4748 })
4750 (define_peephole2
4751 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4752 (match_operand 1 "" ""))
4753 (use (reg:DI 29))
4754 (clobber (reg:DI 26))])]
4755 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4756 && ! samegp_function_operand (operands[0], Pmode)
4757 && ! (peep2_regno_dead_p (1, 29)
4758 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4759 [(parallel [(call (mem:DI (match_dup 2))
4760 (match_dup 1))
4761 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4762 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4763 (use (match_dup 0))
4764 (use (match_dup 4))])
4765 (set (reg:DI 29)
4766 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4767 (set (reg:DI 29)
4768 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4769 {
4770 if (CONSTANT_P (operands[0]))
4771 {
4772 operands[2] = gen_rtx_REG (Pmode, 27);
4773 operands[4] = GEN_INT (alpha_next_sequence_number++);
4774 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4775 operands[0], operands[4]));
4776 }
4777 else
4778 {
4779 operands[2] = operands[0];
4780 operands[0] = const0_rtx;
4781 operands[4] = const0_rtx;
4782 }
4783 operands[3] = GEN_INT (alpha_next_sequence_number++);
4784 })
4786 ;; We add a blockage unspec_volatile to prevent insns from moving down
4787 ;; from above the call to in between the call and the ldah gpdisp.
4789 (define_insn "*call_osf_2_er"
4790 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4791 (match_operand 1 "" ""))
4792 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4793 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4794 (use (match_operand 2 "" ""))
4795 (use (match_operand 3 "const_int_operand" ""))]
4796 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4797 "jsr $26,(%0),%2%J3"
4798 [(set_attr "type" "jsr")
4799 (set_attr "cannot_copy" "true")])
4801 ;; We output a nop after noreturn calls at the very end of the function to
4802 ;; ensure that the return address always remains in the caller's code range,
4803 ;; as not doing so might confuse unwinding engines.
4804 ;;
4805 ;; The potential change in insn length is not reflected in the length
4806 ;; attributes at this stage. Since the extra space is only actually added at
4807 ;; the very end of the compilation process (via final/print_operand), it
4808 ;; really seems harmless and not worth the trouble of some extra computation
4809 ;; cost and complexity.
4811 (define_insn "*call_osf_1_noreturn"
4812 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4813 (match_operand 1 "" ""))
4814 (use (reg:DI 29))
4815 (clobber (reg:DI 26))]
4816 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4817 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4818 "@
4819 jsr $26,($27),0%+
4820 bsr $26,$%0..ng%+
4821 jsr $26,%0%+"
4822 [(set_attr "type" "jsr")
4823 (set_attr "length" "*,*,8")])
4825 (define_insn "*call_osf_1"
4826 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4827 (match_operand 1 "" ""))
4828 (use (reg:DI 29))
4829 (clobber (reg:DI 26))]
4830 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4831 "@
4832 jsr $26,($27),0\;ldgp $29,0($26)
4833 bsr $26,$%0..ng
4834 jsr $26,%0\;ldgp $29,0($26)"
4835 [(set_attr "type" "jsr")
4836 (set_attr "length" "12,*,16")])
4838 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4839 ;; doesn't do what we want.
4840 (define_insn "*sibcall_osf_1_er"
4841 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4842 (match_operand 1 "" ""))
4843 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4844 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4845 "@
4846 br $31,%0\t\t!samegp
4847 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4848 [(set_attr "type" "jsr")
4849 (set_attr "length" "*,8")])
4851 (define_insn "*sibcall_osf_1"
4852 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4853 (match_operand 1 "" ""))
4854 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4855 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4856 "@
4857 br $31,$%0..ng
4858 lda $27,%0\;jmp $31,($27),%0"
4859 [(set_attr "type" "jsr")
4860 (set_attr "length" "*,8")])
4862 (define_insn "*call_nt_1"
4863 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4864 (match_operand 1 "" ""))
4865 (clobber (reg:DI 26))]
4866 "TARGET_ABI_WINDOWS_NT"
4867 "@
4868 jsr $26,(%0)
4869 bsr $26,%0
4870 jsr $26,%0"
4871 [(set_attr "type" "jsr")
4872 (set_attr "length" "*,*,12")])
4874 ; GAS relies on the order and position of instructions output below in order
4875 ; to generate relocs for VMS link to potentially optimize the call.
4876 ; Please do not molest.
4877 (define_insn "*call_vms_1"
4878 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4879 (match_operand 1 "" ""))
4880 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4881 (use (reg:DI 25))
4882 (use (reg:DI 26))
4883 (clobber (reg:DI 27))]
4884 "TARGET_ABI_OPEN_VMS"
4885 {
4886 switch (which_alternative)
4887 {
4888 case 0:
4889 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4890 case 1:
4891 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4892 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4893 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4894 default:
4895 gcc_unreachable ();
4896 }
4897 }
4898 [(set_attr "type" "jsr")
4899 (set_attr "length" "12,16")])
4901 (define_insn "*call_umk_1"
4902 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4903 (match_operand 1 "" ""))
4904 (use (reg:DI 25))
4905 (clobber (reg:DI 26))]
4906 "TARGET_ABI_UNICOSMK"
4907 "jsr $26,(%0)"
4908 [(set_attr "type" "jsr")])
4910 ;; Call subroutine returning any type.
4912 (define_expand "untyped_call"
4913 [(parallel [(call (match_operand 0 "" "")
4914 (const_int 0))
4915 (match_operand 1 "" "")
4916 (match_operand 2 "" "")])]
4917 ""
4918 {
4919 int i;
4921 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4923 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4924 {
4925 rtx set = XVECEXP (operands[2], 0, i);
4926 emit_move_insn (SET_DEST (set), SET_SRC (set));
4927 }
4929 /* The optimizer does not know that the call sets the function value
4930 registers we stored in the result block. We avoid problems by
4931 claiming that all hard registers are used and clobbered at this
4932 point. */
4933 emit_insn (gen_blockage ());
4935 DONE;
4936 })
4938 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4939 ;; all of memory. This blocks insns from being moved across this point.
4941 (define_insn "blockage"
4942 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4943 ""
4944 ""
4945 [(set_attr "length" "0")
4946 (set_attr "type" "none")])
4948 (define_insn "jump"
4949 [(set (pc)
4950 (label_ref (match_operand 0 "" "")))]
4951 ""
4952 "br $31,%l0"
4953 [(set_attr "type" "ibr")])
4955 (define_expand "return"
4956 [(return)]
4957 "direct_return ()"
4958 "")
4960 (define_insn "*return_internal"
4961 [(return)]
4962 "reload_completed"
4963 "ret $31,($26),1"
4964 [(set_attr "type" "ibr")])
4966 (define_insn "indirect_jump"
4967 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4968 ""
4969 "jmp $31,(%0),0"
4970 [(set_attr "type" "ibr")])
4972 (define_expand "tablejump"
4973 [(parallel [(set (pc)
4974 (match_operand 0 "register_operand" ""))
4975 (use (label_ref:DI (match_operand 1 "" "")))])]
4976 ""
4977 {
4978 if (TARGET_ABI_WINDOWS_NT)
4979 {
4980 rtx dest = gen_reg_rtx (DImode);
4981 emit_insn (gen_extendsidi2 (dest, operands[0]));
4982 operands[0] = dest;
4983 }
4984 else if (TARGET_ABI_OSF)
4985 {
4986 rtx dest = gen_reg_rtx (DImode);
4987 emit_insn (gen_extendsidi2 (dest, operands[0]));
4988 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4989 operands[0] = dest;
4990 }
4991 })
4993 (define_insn "*tablejump_osf_nt_internal"
4994 [(set (pc)
4995 (match_operand:DI 0 "register_operand" "r"))
4996 (use (label_ref:DI (match_operand 1 "" "")))]
4997 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4998 && alpha_tablejump_addr_vec (insn)"
4999 {
5000 operands[2] = alpha_tablejump_best_label (insn);
5001 return "jmp $31,(%0),%2";
5002 }
5003 [(set_attr "type" "ibr")])
5005 (define_insn "*tablejump_internal"
5006 [(set (pc)
5007 (match_operand:DI 0 "register_operand" "r"))
5008 (use (label_ref (match_operand 1 "" "")))]
5009 ""
5010 "jmp $31,(%0),0"
5011 [(set_attr "type" "ibr")])
5013 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5014 ;; want to have to include pal.h in our .s file.
5015 ;;
5016 ;; Technically the type for call_pal is jsr, but we use that for determining
5017 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5018 ;; characteristics.
5019 (define_insn "imb"
5020 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5021 ""
5022 "call_pal 0x86"
5023 [(set_attr "type" "callpal")])
5025 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5026 ;; NT does not document anything at 0x81 -- presumably it would generate
5027 ;; the equivalent of SIGILL, but this isn't that important.
5028 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5029 (define_insn "trap"
5030 [(trap_if (const_int 1) (const_int 0))]
5031 "!TARGET_ABI_WINDOWS_NT"
5032 "call_pal 0x81"
5033 [(set_attr "type" "callpal")])
5035 ;; For userland, we load the thread pointer from the TCB.
5036 ;; For the kernel, we load the per-cpu private value.
5038 (define_insn "load_tp"
5039 [(set (match_operand:DI 0 "register_operand" "=v")
5040 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5041 "TARGET_ABI_OSF"
5042 {
5043 if (TARGET_TLS_KERNEL)
5044 return "call_pal 0x32";
5045 else
5046 return "call_pal 0x9e";
5047 }
5048 [(set_attr "type" "callpal")])
5050 ;; For completeness, and possibly a __builtin function, here's how to
5051 ;; set the thread pointer. Since we don't describe enough of this
5052 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5053 ;; not much point in creating an R16_REG register class.
5055 (define_expand "set_tp"
5056 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5057 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5058 "TARGET_ABI_OSF"
5059 "")
5061 (define_insn "*set_tp"
5062 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5063 "TARGET_ABI_OSF"
5064 {
5065 if (TARGET_TLS_KERNEL)
5066 return "call_pal 0x31";
5067 else
5068 return "call_pal 0x9f";
5069 }
5070 [(set_attr "type" "callpal")])
5071 \f
5072 ;; Finally, we have the basic data motion insns. The byte and word insns
5073 ;; are done via define_expand. Start with the floating-point insns, since
5074 ;; they are simpler.
5076 (define_insn "*movsf_nofix"
5077 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5078 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5079 "TARGET_FPREGS && ! TARGET_FIX
5080 && (register_operand (operands[0], SFmode)
5081 || reg_or_0_operand (operands[1], SFmode))"
5082 "@
5083 cpys %R1,%R1,%0
5084 ld%, %0,%1
5085 bis $31,%r1,%0
5086 ldl %0,%1
5087 st%, %R1,%0
5088 stl %r1,%0"
5089 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5091 (define_insn "*movsf_fix"
5092 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5093 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5094 "TARGET_FPREGS && TARGET_FIX
5095 && (register_operand (operands[0], SFmode)
5096 || reg_or_0_operand (operands[1], SFmode))"
5097 "@
5098 cpys %R1,%R1,%0
5099 ld%, %0,%1
5100 bis $31,%r1,%0
5101 ldl %0,%1
5102 st%, %R1,%0
5103 stl %r1,%0
5104 itofs %1,%0
5105 ftois %1,%0"
5106 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5108 (define_insn "*movsf_nofp"
5109 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5110 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5111 "! TARGET_FPREGS
5112 && (register_operand (operands[0], SFmode)
5113 || reg_or_0_operand (operands[1], SFmode))"
5114 "@
5115 bis $31,%r1,%0
5116 ldl %0,%1
5117 stl %r1,%0"
5118 [(set_attr "type" "ilog,ild,ist")])
5120 (define_insn "*movdf_nofix"
5121 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5122 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5123 "TARGET_FPREGS && ! TARGET_FIX
5124 && (register_operand (operands[0], DFmode)
5125 || reg_or_0_operand (operands[1], DFmode))"
5126 "@
5127 cpys %R1,%R1,%0
5128 ld%- %0,%1
5129 bis $31,%r1,%0
5130 ldq %0,%1
5131 st%- %R1,%0
5132 stq %r1,%0"
5133 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5135 (define_insn "*movdf_fix"
5136 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5137 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5138 "TARGET_FPREGS && TARGET_FIX
5139 && (register_operand (operands[0], DFmode)
5140 || reg_or_0_operand (operands[1], DFmode))"
5141 "@
5142 cpys %R1,%R1,%0
5143 ld%- %0,%1
5144 bis $31,%r1,%0
5145 ldq %0,%1
5146 st%- %R1,%0
5147 stq %r1,%0
5148 itoft %1,%0
5149 ftoit %1,%0"
5150 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5152 (define_insn "*movdf_nofp"
5153 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5154 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5155 "! TARGET_FPREGS
5156 && (register_operand (operands[0], DFmode)
5157 || reg_or_0_operand (operands[1], DFmode))"
5158 "@
5159 bis $31,%r1,%0
5160 ldq %0,%1
5161 stq %r1,%0"
5162 [(set_attr "type" "ilog,ild,ist")])
5164 ;; Subregs suck for register allocation. Pretend we can move TFmode
5165 ;; data between general registers until after reload.
5167 (define_insn_and_split "*movtf_internal"
5168 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5169 (match_operand:TF 1 "input_operand" "roG,rG"))]
5170 "register_operand (operands[0], TFmode)
5171 || reg_or_0_operand (operands[1], TFmode)"
5172 "#"
5173 "reload_completed"
5174 [(set (match_dup 0) (match_dup 2))
5175 (set (match_dup 1) (match_dup 3))]
5176 {
5177 alpha_split_tfmode_pair (operands);
5178 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5179 {
5180 rtx tmp;
5181 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5182 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5183 }
5184 })
5186 (define_expand "movsf"
5187 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5188 (match_operand:SF 1 "general_operand" ""))]
5189 ""
5190 {
5191 if (GET_CODE (operands[0]) == MEM
5192 && ! reg_or_0_operand (operands[1], SFmode))
5193 operands[1] = force_reg (SFmode, operands[1]);
5194 })
5196 (define_expand "movdf"
5197 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5198 (match_operand:DF 1 "general_operand" ""))]
5199 ""
5200 {
5201 if (GET_CODE (operands[0]) == MEM
5202 && ! reg_or_0_operand (operands[1], DFmode))
5203 operands[1] = force_reg (DFmode, operands[1]);
5204 })
5206 (define_expand "movtf"
5207 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5208 (match_operand:TF 1 "general_operand" ""))]
5209 ""
5210 {
5211 if (GET_CODE (operands[0]) == MEM
5212 && ! reg_or_0_operand (operands[1], TFmode))
5213 operands[1] = force_reg (TFmode, operands[1]);
5214 })
5216 (define_insn "*movsi"
5217 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5218 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5219 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5220 && (register_operand (operands[0], SImode)
5221 || reg_or_0_operand (operands[1], SImode))"
5222 "@
5223 bis $31,%r1,%0
5224 lda %0,%1($31)
5225 ldah %0,%h1($31)
5226 #
5227 ldl %0,%1
5228 stl %r1,%0"
5229 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5231 (define_insn "*movsi_nt_vms"
5232 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5233 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5234 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5235 && (register_operand (operands[0], SImode)
5236 || reg_or_0_operand (operands[1], SImode))"
5237 "@
5238 bis $31,%1,%0
5239 lda %0,%1
5240 ldah %0,%h1
5241 lda %0,%1
5242 #
5243 ldl %0,%1
5244 stl %r1,%0"
5245 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5247 (define_insn "*movhi_nobwx"
5248 [(set (match_operand:HI 0 "register_operand" "=r,r")
5249 (match_operand:HI 1 "input_operand" "rJ,n"))]
5250 "! TARGET_BWX
5251 && (register_operand (operands[0], HImode)
5252 || register_operand (operands[1], HImode))"
5253 "@
5254 bis $31,%r1,%0
5255 lda %0,%L1($31)"
5256 [(set_attr "type" "ilog,iadd")])
5258 (define_insn "*movhi_bwx"
5259 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5260 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5261 "TARGET_BWX
5262 && (register_operand (operands[0], HImode)
5263 || reg_or_0_operand (operands[1], HImode))"
5264 "@
5265 bis $31,%r1,%0
5266 lda %0,%L1($31)
5267 ldwu %0,%1
5268 stw %r1,%0"
5269 [(set_attr "type" "ilog,iadd,ild,ist")])
5271 (define_insn "*movqi_nobwx"
5272 [(set (match_operand:QI 0 "register_operand" "=r,r")
5273 (match_operand:QI 1 "input_operand" "rJ,n"))]
5274 "! TARGET_BWX
5275 && (register_operand (operands[0], QImode)
5276 || register_operand (operands[1], QImode))"
5277 "@
5278 bis $31,%r1,%0
5279 lda %0,%L1($31)"
5280 [(set_attr "type" "ilog,iadd")])
5282 (define_insn "*movqi_bwx"
5283 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5284 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5285 "TARGET_BWX
5286 && (register_operand (operands[0], QImode)
5287 || reg_or_0_operand (operands[1], QImode))"
5288 "@
5289 bis $31,%r1,%0
5290 lda %0,%L1($31)
5291 ldbu %0,%1
5292 stb %r1,%0"
5293 [(set_attr "type" "ilog,iadd,ild,ist")])
5295 ;; We do two major things here: handle mem->mem and construct long
5296 ;; constants.
5298 (define_expand "movsi"
5299 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5300 (match_operand:SI 1 "general_operand" ""))]
5301 ""
5302 {
5303 if (alpha_expand_mov (SImode, operands))
5304 DONE;
5305 })
5307 ;; Split a load of a large constant into the appropriate two-insn
5308 ;; sequence.
5310 (define_split
5311 [(set (match_operand:SI 0 "register_operand" "")
5312 (match_operand:SI 1 "non_add_const_operand" ""))]
5313 ""
5314 [(const_int 0)]
5315 {
5316 if (alpha_split_const_mov (SImode, operands))
5317 DONE;
5318 else
5319 FAIL;
5320 })
5322 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5323 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5324 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5325 ;; notes and update LABEL_NUSES because this is not done automatically.
5326 ;; Labels may be incorrectly deleted if we don't do this.
5327 ;;
5328 ;; Describing what the individual instructions do correctly is too complicated
5329 ;; so use UNSPECs for each of the three parts of an address.
5331 (define_split
5332 [(set (match_operand:DI 0 "register_operand" "")
5333 (match_operand:DI 1 "symbolic_operand" ""))]
5334 "TARGET_ABI_UNICOSMK && reload_completed"
5335 [(const_int 0)]
5336 {
5337 rtx insn1, insn2, insn3;
5339 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5340 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5341 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5342 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5343 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5344 REG_NOTES (insn3));
5345 if (GET_CODE (operands[1]) == LABEL_REF)
5346 {
5347 rtx label;
5349 label = XEXP (operands[1], 0);
5350 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5351 REG_NOTES (insn1));
5352 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5353 REG_NOTES (insn2));
5354 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5355 REG_NOTES (insn3));
5356 LABEL_NUSES (label) += 3;
5357 }
5358 DONE;
5359 })
5361 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5363 (define_insn "umk_laum"
5364 [(set (match_operand:DI 0 "register_operand" "=r")
5365 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5366 UNSPEC_UMK_LAUM))]
5367 "TARGET_ABI_UNICOSMK"
5368 "laum %r0,%t1($31)"
5369 [(set_attr "type" "iadd")])
5371 (define_insn "umk_lalm"
5372 [(set (match_operand:DI 0 "register_operand" "=r")
5373 (plus:DI (match_operand:DI 1 "register_operand" "r")
5374 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5375 UNSPEC_UMK_LALM)))]
5376 "TARGET_ABI_UNICOSMK"
5377 "lalm %r0,%t2(%r1)"
5378 [(set_attr "type" "iadd")])
5380 (define_insn "umk_lal"
5381 [(set (match_operand:DI 0 "register_operand" "=r")
5382 (plus:DI (match_operand:DI 1 "register_operand" "r")
5383 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5384 UNSPEC_UMK_LAL)))]
5385 "TARGET_ABI_UNICOSMK"
5386 "lal %r0,%t2(%r1)"
5387 [(set_attr "type" "iadd")])
5389 ;; Add a new call information word to the current function's list of CIWs
5390 ;; and load its index into $25. Doing it here ensures that the CIW will be
5391 ;; associated with the correct function even in the presence of inlining.
5393 (define_insn "*umk_load_ciw"
5394 [(set (reg:DI 25)
5395 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5396 "TARGET_ABI_UNICOSMK"
5397 {
5398 operands[0] = unicosmk_add_call_info_word (operands[0]);
5399 return "lda $25,%0";
5400 }
5401 [(set_attr "type" "iadd")])
5403 (define_insn "*movdi_er_low_l"
5404 [(set (match_operand:DI 0 "register_operand" "=r")
5405 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5406 (match_operand:DI 2 "local_symbolic_operand" "")))]
5407 "TARGET_EXPLICIT_RELOCS"
5408 {
5409 if (true_regnum (operands[1]) == 29)
5410 return "lda %0,%2(%1)\t\t!gprel";
5411 else
5412 return "lda %0,%2(%1)\t\t!gprellow";
5413 }
5414 [(set_attr "usegp" "yes")])
5416 (define_split
5417 [(set (match_operand:DI 0 "register_operand" "")
5418 (match_operand:DI 1 "small_symbolic_operand" ""))]
5419 "TARGET_EXPLICIT_RELOCS && reload_completed"
5420 [(set (match_dup 0)
5421 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5422 "operands[2] = pic_offset_table_rtx;")
5424 (define_split
5425 [(set (match_operand:DI 0 "register_operand" "")
5426 (match_operand:DI 1 "local_symbolic_operand" ""))]
5427 "TARGET_EXPLICIT_RELOCS && reload_completed"
5428 [(set (match_dup 0)
5429 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5430 (set (match_dup 0)
5431 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5432 "operands[2] = pic_offset_table_rtx;")
5434 (define_split
5435 [(match_operand 0 "some_small_symbolic_operand" "")]
5436 ""
5437 [(match_dup 0)]
5438 "operands[0] = split_small_symbolic_operand (operands[0]);")
5440 ;; Accepts any symbolic, not just global, since function calls that
5441 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5442 (define_insn "movdi_er_high_g"
5443 [(set (match_operand:DI 0 "register_operand" "=r")
5444 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5445 (match_operand:DI 2 "symbolic_operand" "")
5446 (match_operand 3 "const_int_operand" "")]
5447 UNSPEC_LITERAL))]
5448 "TARGET_EXPLICIT_RELOCS"
5449 {
5450 if (INTVAL (operands[3]) == 0)
5451 return "ldq %0,%2(%1)\t\t!literal";
5452 else
5453 return "ldq %0,%2(%1)\t\t!literal!%3";
5454 }
5455 [(set_attr "type" "ldsym")])
5457 (define_split
5458 [(set (match_operand:DI 0 "register_operand" "")
5459 (match_operand:DI 1 "global_symbolic_operand" ""))]
5460 "TARGET_EXPLICIT_RELOCS && reload_completed"
5461 [(set (match_dup 0)
5462 (unspec:DI [(match_dup 2)
5463 (match_dup 1)
5464 (const_int 0)] UNSPEC_LITERAL))]
5465 "operands[2] = pic_offset_table_rtx;")
5467 (define_insn "movdi_er_tlsgd"
5468 [(set (match_operand:DI 0 "register_operand" "=r")
5469 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5470 (match_operand:DI 2 "symbolic_operand" "")
5471 (match_operand 3 "const_int_operand" "")]
5472 UNSPEC_TLSGD))]
5473 "HAVE_AS_TLS"
5474 {
5475 if (INTVAL (operands[3]) == 0)
5476 return "lda %0,%2(%1)\t\t!tlsgd";
5477 else
5478 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5479 })
5481 (define_insn "movdi_er_tlsldm"
5482 [(set (match_operand:DI 0 "register_operand" "=r")
5483 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5484 (match_operand 2 "const_int_operand" "")]
5485 UNSPEC_TLSLDM))]
5486 "HAVE_AS_TLS"
5487 {
5488 if (INTVAL (operands[2]) == 0)
5489 return "lda %0,%&(%1)\t\t!tlsldm";
5490 else
5491 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5492 })
5494 (define_insn "*movdi_er_gotdtp"
5495 [(set (match_operand:DI 0 "register_operand" "=r")
5496 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5497 (match_operand:DI 2 "symbolic_operand" "")]
5498 UNSPEC_DTPREL))]
5499 "HAVE_AS_TLS"
5500 "ldq %0,%2(%1)\t\t!gotdtprel"
5501 [(set_attr "type" "ild")
5502 (set_attr "usegp" "yes")])
5504 (define_split
5505 [(set (match_operand:DI 0 "register_operand" "")
5506 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5507 "HAVE_AS_TLS && reload_completed"
5508 [(set (match_dup 0)
5509 (unspec:DI [(match_dup 2)
5510 (match_dup 1)] UNSPEC_DTPREL))]
5511 {
5512 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5513 operands[2] = pic_offset_table_rtx;
5514 })
5516 (define_insn "*movdi_er_gottp"
5517 [(set (match_operand:DI 0 "register_operand" "=r")
5518 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5519 (match_operand:DI 2 "symbolic_operand" "")]
5520 UNSPEC_TPREL))]
5521 "HAVE_AS_TLS"
5522 "ldq %0,%2(%1)\t\t!gottprel"
5523 [(set_attr "type" "ild")
5524 (set_attr "usegp" "yes")])
5526 (define_split
5527 [(set (match_operand:DI 0 "register_operand" "")
5528 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5529 "HAVE_AS_TLS && reload_completed"
5530 [(set (match_dup 0)
5531 (unspec:DI [(match_dup 2)
5532 (match_dup 1)] UNSPEC_TPREL))]
5533 {
5534 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5535 operands[2] = pic_offset_table_rtx;
5536 })
5538 (define_insn "*movdi_er_nofix"
5539 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5540 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5541 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5542 && (register_operand (operands[0], DImode)
5543 || reg_or_0_operand (operands[1], DImode))"
5544 "@
5545 mov %r1,%0
5546 lda %0,%1($31)
5547 ldah %0,%h1($31)
5548 #
5549 #
5550 #
5551 ldq%A1 %0,%1
5552 stq%A0 %r1,%0
5553 fmov %R1,%0
5554 ldt %0,%1
5555 stt %R1,%0"
5556 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5557 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5559 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5560 ;; have been split up by the rules above but we shouldn't reject the
5561 ;; possibility of them getting through.
5563 (define_insn "*movdi_nofix"
5564 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5565 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5566 "! TARGET_FIX
5567 && (register_operand (operands[0], DImode)
5568 || reg_or_0_operand (operands[1], DImode))"
5569 "@
5570 bis $31,%r1,%0
5571 lda %0,%1($31)
5572 ldah %0,%h1($31)
5573 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5574 lda %0,%1
5575 #
5576 ldq%A1 %0,%1
5577 stq%A0 %r1,%0
5578 cpys %R1,%R1,%0
5579 ldt %0,%1
5580 stt %R1,%0"
5581 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5582 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5584 (define_insn "*movdi_er_fix"
5585 [(set (match_operand:DI 0 "nonimmediate_operand"
5586 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5587 (match_operand:DI 1 "input_operand"
5588 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5589 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5590 && (register_operand (operands[0], DImode)
5591 || reg_or_0_operand (operands[1], DImode))"
5592 "@
5593 mov %r1,%0
5594 lda %0,%1($31)
5595 ldah %0,%h1($31)
5596 #
5597 #
5598 #
5599 ldq%A1 %0,%1
5600 stq%A0 %r1,%0
5601 fmov %R1,%0
5602 ldt %0,%1
5603 stt %R1,%0
5604 ftoit %1,%0
5605 itoft %1,%0"
5606 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5607 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5609 (define_insn "*movdi_fix"
5610 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5611 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5612 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5613 && (register_operand (operands[0], DImode)
5614 || reg_or_0_operand (operands[1], DImode))"
5615 "@
5616 bis $31,%r1,%0
5617 lda %0,%1($31)
5618 ldah %0,%h1($31)
5619 lda %0,%1
5620 #
5621 ldq%A1 %0,%1
5622 stq%A0 %r1,%0
5623 cpys %R1,%R1,%0
5624 ldt %0,%1
5625 stt %R1,%0
5626 ftoit %1,%0
5627 itoft %1,%0"
5628 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5630 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5631 ;; often appears dead to the life analysis code, at which point we
5632 ;; die for emitting dead prologue instructions. Force this live.
5634 (define_insn "force_movdi"
5635 [(set (match_operand:DI 0 "register_operand" "=r")
5636 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5637 UNSPECV_FORCE_MOV))]
5638 ""
5639 "mov %1,%0"
5640 [(set_attr "type" "ilog")])
5642 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5643 ;; memory, and construct long 32-bit constants.
5645 (define_expand "movdi"
5646 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5647 (match_operand:DI 1 "general_operand" ""))]
5648 ""
5649 {
5650 if (alpha_expand_mov (DImode, operands))
5651 DONE;
5652 })
5654 ;; Split a load of a large constant into the appropriate two-insn
5655 ;; sequence.
5657 (define_split
5658 [(set (match_operand:DI 0 "register_operand" "")
5659 (match_operand:DI 1 "non_add_const_operand" ""))]
5660 ""
5661 [(const_int 0)]
5662 {
5663 if (alpha_split_const_mov (DImode, operands))
5664 DONE;
5665 else
5666 FAIL;
5667 })
5669 ;; These are the partial-word cases.
5670 ;;
5671 ;; First we have the code to load an aligned word. Operand 0 is the register
5672 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5673 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5674 ;; number of bits within the word that the value is. Operand 3 is an SImode
5675 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5676 ;; same register. It is allowed to conflict with operand 1 as well.
5678 (define_expand "aligned_loadqi"
5679 [(set (match_operand:SI 3 "register_operand" "")
5680 (match_operand:SI 1 "memory_operand" ""))
5681 (set (match_operand:DI 0 "register_operand" "")
5682 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5683 (const_int 8)
5684 (match_operand:DI 2 "const_int_operand" "")))]
5686 ""
5687 "")
5689 (define_expand "aligned_loadhi"
5690 [(set (match_operand:SI 3 "register_operand" "")
5691 (match_operand:SI 1 "memory_operand" ""))
5692 (set (match_operand:DI 0 "register_operand" "")
5693 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5694 (const_int 16)
5695 (match_operand:DI 2 "const_int_operand" "")))]
5697 ""
5698 "")
5700 ;; Similar for unaligned loads, where we use the sequence from the
5701 ;; Alpha Architecture manual. We have to distinguish between little-endian
5702 ;; and big-endian systems as the sequences are different.
5703 ;;
5704 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5705 ;; operand 3 can overlap the input and output registers.
5707 (define_expand "unaligned_loadqi"
5708 [(use (match_operand:DI 0 "register_operand" ""))
5709 (use (match_operand:DI 1 "address_operand" ""))
5710 (use (match_operand:DI 2 "register_operand" ""))
5711 (use (match_operand:DI 3 "register_operand" ""))]
5712 ""
5713 {
5714 if (WORDS_BIG_ENDIAN)
5715 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5716 operands[2], operands[3]));
5717 else
5718 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5719 operands[2], operands[3]));
5720 DONE;
5721 })
5723 (define_expand "unaligned_loadqi_le"
5724 [(set (match_operand:DI 2 "register_operand" "")
5725 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5726 (const_int -8))))
5727 (set (match_operand:DI 3 "register_operand" "")
5728 (match_dup 1))
5729 (set (match_operand:DI 0 "register_operand" "")
5730 (zero_extract:DI (match_dup 2)
5731 (const_int 8)
5732 (ashift:DI (match_dup 3) (const_int 3))))]
5733 "! WORDS_BIG_ENDIAN"
5734 "")
5736 (define_expand "unaligned_loadqi_be"
5737 [(set (match_operand:DI 2 "register_operand" "")
5738 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5739 (const_int -8))))
5740 (set (match_operand:DI 3 "register_operand" "")
5741 (match_dup 1))
5742 (set (match_operand:DI 0 "register_operand" "")
5743 (zero_extract:DI (match_dup 2)
5744 (const_int 8)
5745 (minus:DI
5746 (const_int 56)
5747 (ashift:DI (match_dup 3) (const_int 3)))))]
5748 "WORDS_BIG_ENDIAN"
5749 "")
5751 (define_expand "unaligned_loadhi"
5752 [(use (match_operand:DI 0 "register_operand" ""))
5753 (use (match_operand:DI 1 "address_operand" ""))
5754 (use (match_operand:DI 2 "register_operand" ""))
5755 (use (match_operand:DI 3 "register_operand" ""))]
5756 ""
5757 {
5758 if (WORDS_BIG_ENDIAN)
5759 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5760 operands[2], operands[3]));
5761 else
5762 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5763 operands[2], operands[3]));
5764 DONE;
5765 })
5767 (define_expand "unaligned_loadhi_le"
5768 [(set (match_operand:DI 2 "register_operand" "")
5769 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5770 (const_int -8))))
5771 (set (match_operand:DI 3 "register_operand" "")
5772 (match_dup 1))
5773 (set (match_operand:DI 0 "register_operand" "")
5774 (zero_extract:DI (match_dup 2)
5775 (const_int 16)
5776 (ashift:DI (match_dup 3) (const_int 3))))]
5777 "! WORDS_BIG_ENDIAN"
5778 "")
5780 (define_expand "unaligned_loadhi_be"
5781 [(set (match_operand:DI 2 "register_operand" "")
5782 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5783 (const_int -8))))
5784 (set (match_operand:DI 3 "register_operand" "")
5785 (plus:DI (match_dup 1) (const_int 1)))
5786 (set (match_operand:DI 0 "register_operand" "")
5787 (zero_extract:DI (match_dup 2)
5788 (const_int 16)
5789 (minus:DI
5790 (const_int 56)
5791 (ashift:DI (match_dup 3) (const_int 3)))))]
5792 "WORDS_BIG_ENDIAN"
5793 "")
5795 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5796 ;; aligned SImode MEM. Operand 1 is the register containing the
5797 ;; byte or word to store. Operand 2 is the number of bits within the word that
5798 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5800 (define_expand "aligned_store"
5801 [(set (match_operand:SI 3 "register_operand" "")
5802 (match_operand:SI 0 "memory_operand" ""))
5803 (set (subreg:DI (match_dup 3) 0)
5804 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5805 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5806 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5807 (match_operand:DI 2 "const_int_operand" "")))
5808 (set (subreg:DI (match_dup 4) 0)
5809 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5810 (set (match_dup 0) (match_dup 4))]
5811 ""
5812 {
5813 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5814 << INTVAL (operands[2])));
5815 })
5817 ;; For the unaligned byte and halfword cases, we use code similar to that
5818 ;; in the ;; Architecture book, but reordered to lower the number of registers
5819 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5820 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5821 ;; be the same temporary, if desired. If the address is in a register,
5822 ;; operand 2 can be that register.
5824 (define_expand "unaligned_storeqi"
5825 [(use (match_operand:DI 0 "address_operand" ""))
5826 (use (match_operand:QI 1 "register_operand" ""))
5827 (use (match_operand:DI 2 "register_operand" ""))
5828 (use (match_operand:DI 3 "register_operand" ""))
5829 (use (match_operand:DI 4 "register_operand" ""))]
5830 ""
5831 {
5832 if (WORDS_BIG_ENDIAN)
5833 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5834 operands[2], operands[3],
5835 operands[4]));
5836 else
5837 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5838 operands[2], operands[3],
5839 operands[4]));
5840 DONE;
5841 })
5843 (define_expand "unaligned_storeqi_le"
5844 [(set (match_operand:DI 3 "register_operand" "")
5845 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5846 (const_int -8))))
5847 (set (match_operand:DI 2 "register_operand" "")
5848 (match_dup 0))
5849 (set (match_dup 3)
5850 (and:DI (not:DI (ashift:DI (const_int 255)
5851 (ashift:DI (match_dup 2) (const_int 3))))
5852 (match_dup 3)))
5853 (set (match_operand:DI 4 "register_operand" "")
5854 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5855 (ashift:DI (match_dup 2) (const_int 3))))
5856 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5857 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5858 (match_dup 4))]
5859 "! WORDS_BIG_ENDIAN"
5860 "")
5862 (define_expand "unaligned_storeqi_be"
5863 [(set (match_operand:DI 3 "register_operand" "")
5864 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5865 (const_int -8))))
5866 (set (match_operand:DI 2 "register_operand" "")
5867 (match_dup 0))
5868 (set (match_dup 3)
5869 (and:DI (not:DI (ashift:DI (const_int 255)
5870 (minus:DI (const_int 56)
5871 (ashift:DI (match_dup 2) (const_int 3)))))
5872 (match_dup 3)))
5873 (set (match_operand:DI 4 "register_operand" "")
5874 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5875 (minus:DI (const_int 56)
5876 (ashift:DI (match_dup 2) (const_int 3)))))
5877 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5878 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5879 (match_dup 4))]
5880 "WORDS_BIG_ENDIAN"
5881 "")
5883 (define_expand "unaligned_storehi"
5884 [(use (match_operand:DI 0 "address_operand" ""))
5885 (use (match_operand:HI 1 "register_operand" ""))
5886 (use (match_operand:DI 2 "register_operand" ""))
5887 (use (match_operand:DI 3 "register_operand" ""))
5888 (use (match_operand:DI 4 "register_operand" ""))]
5889 ""
5890 {
5891 if (WORDS_BIG_ENDIAN)
5892 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5893 operands[2], operands[3],
5894 operands[4]));
5895 else
5896 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5897 operands[2], operands[3],
5898 operands[4]));
5899 DONE;
5900 })
5902 (define_expand "unaligned_storehi_le"
5903 [(set (match_operand:DI 3 "register_operand" "")
5904 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5905 (const_int -8))))
5906 (set (match_operand:DI 2 "register_operand" "")
5907 (match_dup 0))
5908 (set (match_dup 3)
5909 (and:DI (not:DI (ashift:DI (const_int 65535)
5910 (ashift:DI (match_dup 2) (const_int 3))))
5911 (match_dup 3)))
5912 (set (match_operand:DI 4 "register_operand" "")
5913 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5914 (ashift:DI (match_dup 2) (const_int 3))))
5915 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5916 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5917 (match_dup 4))]
5918 "! WORDS_BIG_ENDIAN"
5919 "")
5921 (define_expand "unaligned_storehi_be"
5922 [(set (match_operand:DI 3 "register_operand" "")
5923 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5924 (const_int -8))))
5925 (set (match_operand:DI 2 "register_operand" "")
5926 (plus:DI (match_dup 0) (const_int 1)))
5927 (set (match_dup 3)
5928 (and:DI (not:DI (ashift:DI
5929 (const_int 65535)
5930 (minus:DI (const_int 56)
5931 (ashift:DI (match_dup 2) (const_int 3)))))
5932 (match_dup 3)))
5933 (set (match_operand:DI 4 "register_operand" "")
5934 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5935 (minus:DI (const_int 56)
5936 (ashift:DI (match_dup 2) (const_int 3)))))
5937 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5938 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5939 (match_dup 4))]
5940 "WORDS_BIG_ENDIAN"
5941 "")
5942 \f
5943 ;; Here are the define_expand's for QI and HI moves that use the above
5944 ;; patterns. We have the normal sets, plus the ones that need scratch
5945 ;; registers for reload.
5947 (define_expand "movqi"
5948 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5949 (match_operand:QI 1 "general_operand" ""))]
5950 ""
5951 {
5952 if (TARGET_BWX
5953 ? alpha_expand_mov (QImode, operands)
5954 : alpha_expand_mov_nobwx (QImode, operands))
5955 DONE;
5956 })
5958 (define_expand "movhi"
5959 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5960 (match_operand:HI 1 "general_operand" ""))]
5961 ""
5962 {
5963 if (TARGET_BWX
5964 ? alpha_expand_mov (HImode, operands)
5965 : alpha_expand_mov_nobwx (HImode, operands))
5966 DONE;
5967 })
5969 ;; Here are the versions for reload. Note that in the unaligned cases
5970 ;; we know that the operand must not be a pseudo-register because stack
5971 ;; slots are always aligned references.
5973 (define_expand "reload_inqi"
5974 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5975 (match_operand:QI 1 "any_memory_operand" "m")
5976 (match_operand:TI 2 "register_operand" "=&r")])]
5977 "! TARGET_BWX"
5978 {
5979 rtx scratch, seq;
5981 if (aligned_memory_operand (operands[1], QImode))
5982 {
5983 seq = gen_reload_inqi_help (operands[0], operands[1],
5984 gen_rtx_REG (SImode, REGNO (operands[2])));
5985 }
5986 else
5987 {
5988 rtx addr;
5990 /* It is possible that one of the registers we got for operands[2]
5991 might coincide with that of operands[0] (which is why we made
5992 it TImode). Pick the other one to use as our scratch. */
5993 if (REGNO (operands[0]) == REGNO (operands[2]))
5994 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5995 else
5996 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5998 addr = get_unaligned_address (operands[1], 0);
5999 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6000 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
6001 alpha_set_memflags (seq, operands[1]);
6002 }
6003 emit_insn (seq);
6004 DONE;
6005 })
6007 (define_expand "reload_inhi"
6008 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6009 (match_operand:HI 1 "any_memory_operand" "m")
6010 (match_operand:TI 2 "register_operand" "=&r")])]
6011 "! TARGET_BWX"
6012 {
6013 rtx scratch, seq;
6015 if (aligned_memory_operand (operands[1], HImode))
6016 {
6017 seq = gen_reload_inhi_help (operands[0], operands[1],
6018 gen_rtx_REG (SImode, REGNO (operands[2])));
6019 }
6020 else
6021 {
6022 rtx addr;
6024 /* It is possible that one of the registers we got for operands[2]
6025 might coincide with that of operands[0] (which is why we made
6026 it TImode). Pick the other one to use as our scratch. */
6027 if (REGNO (operands[0]) == REGNO (operands[2]))
6028 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6029 else
6030 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6032 addr = get_unaligned_address (operands[1], 0);
6033 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6034 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
6035 alpha_set_memflags (seq, operands[1]);
6036 }
6037 emit_insn (seq);
6038 DONE;
6039 })
6041 (define_expand "reload_outqi"
6042 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6043 (match_operand:QI 1 "register_operand" "r")
6044 (match_operand:TI 2 "register_operand" "=&r")])]
6045 "! TARGET_BWX"
6046 {
6047 if (aligned_memory_operand (operands[0], QImode))
6048 {
6049 emit_insn (gen_reload_outqi_help
6050 (operands[0], operands[1],
6051 gen_rtx_REG (SImode, REGNO (operands[2])),
6052 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6053 }
6054 else
6055 {
6056 rtx addr = get_unaligned_address (operands[0], 0);
6057 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6058 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6059 rtx scratch3 = scratch1;
6060 rtx seq;
6062 if (GET_CODE (addr) == REG)
6063 scratch1 = addr;
6065 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6066 scratch2, scratch3);
6067 alpha_set_memflags (seq, operands[0]);
6068 emit_insn (seq);
6069 }
6070 DONE;
6071 })
6073 (define_expand "reload_outhi"
6074 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6075 (match_operand:HI 1 "register_operand" "r")
6076 (match_operand:TI 2 "register_operand" "=&r")])]
6077 "! TARGET_BWX"
6078 {
6079 if (aligned_memory_operand (operands[0], HImode))
6080 {
6081 emit_insn (gen_reload_outhi_help
6082 (operands[0], operands[1],
6083 gen_rtx_REG (SImode, REGNO (operands[2])),
6084 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6085 }
6086 else
6087 {
6088 rtx addr = get_unaligned_address (operands[0], 0);
6089 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6090 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6091 rtx scratch3 = scratch1;
6092 rtx seq;
6094 if (GET_CODE (addr) == REG)
6095 scratch1 = addr;
6097 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6098 scratch2, scratch3);
6099 alpha_set_memflags (seq, operands[0]);
6100 emit_insn (seq);
6101 }
6102 DONE;
6103 })
6105 ;; Helpers for the above. The way reload is structured, we can't
6106 ;; always get a proper address for a stack slot during reload_foo
6107 ;; expansion, so we must delay our address manipulations until after.
6109 (define_insn_and_split "reload_inqi_help"
6110 [(set (match_operand:QI 0 "register_operand" "=r")
6111 (match_operand:QI 1 "memory_operand" "m"))
6112 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6113 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6114 "#"
6115 "! TARGET_BWX && reload_completed"
6116 [(const_int 0)]
6117 {
6118 rtx aligned_mem, bitnum;
6119 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6120 operands[0] = gen_lowpart (DImode, operands[0]);
6121 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6122 operands[2]));
6123 DONE;
6124 })
6126 (define_insn_and_split "reload_inhi_help"
6127 [(set (match_operand:HI 0 "register_operand" "=r")
6128 (match_operand:HI 1 "memory_operand" "m"))
6129 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6130 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6131 "#"
6132 "! TARGET_BWX && reload_completed"
6133 [(const_int 0)]
6134 {
6135 rtx aligned_mem, bitnum;
6136 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6137 operands[0] = gen_lowpart (DImode, operands[0]);
6138 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6139 operands[2]));
6140 DONE;
6141 })
6143 (define_insn_and_split "reload_outqi_help"
6144 [(set (match_operand:QI 0 "memory_operand" "=m")
6145 (match_operand:QI 1 "register_operand" "r"))
6146 (clobber (match_operand:SI 2 "register_operand" "=r"))
6147 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6148 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6149 "#"
6150 "! TARGET_BWX && reload_completed"
6151 [(const_int 0)]
6152 {
6153 rtx aligned_mem, bitnum;
6154 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6155 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6156 operands[2], operands[3]));
6157 DONE;
6158 })
6160 (define_insn_and_split "reload_outhi_help"
6161 [(set (match_operand:HI 0 "memory_operand" "=m")
6162 (match_operand:HI 1 "register_operand" "r"))
6163 (clobber (match_operand:SI 2 "register_operand" "=r"))
6164 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6165 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6166 "#"
6167 "! TARGET_BWX && reload_completed"
6168 [(const_int 0)]
6169 {
6170 rtx aligned_mem, bitnum;
6171 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6172 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6173 operands[2], operands[3]));
6174 DONE;
6175 })
6176 \f
6177 ;; Vector operations
6179 (define_mode_macro VEC [V8QI V4HI V2SI])
6181 (define_expand "mov<mode>"
6182 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6183 (match_operand:VEC 1 "general_operand" ""))]
6184 ""
6185 {
6186 if (alpha_expand_mov (<MODE>mode, operands))
6187 DONE;
6188 })
6190 (define_split
6191 [(set (match_operand:VEC 0 "register_operand" "")
6192 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6193 ""
6194 [(const_int 0)]
6195 {
6196 if (alpha_split_const_mov (<MODE>mode, operands))
6197 DONE;
6198 else
6199 FAIL;
6200 })
6203 (define_expand "movmisalign<mode>"
6204 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6205 (match_operand:VEC 1 "general_operand" ""))]
6206 ""
6207 {
6208 alpha_expand_movmisalign (<MODE>mode, operands);
6209 DONE;
6210 })
6212 (define_insn "*mov<mode>_fix"
6213 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6214 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6215 "TARGET_FIX
6216 && (register_operand (operands[0], <MODE>mode)
6217 || reg_or_0_operand (operands[1], <MODE>mode))"
6218 "@
6219 bis $31,%r1,%0
6220 #
6221 ldq %0,%1
6222 stq %r1,%0
6223 cpys %R1,%R1,%0
6224 ldt %0,%1
6225 stt %R1,%0
6226 ftoit %1,%0
6227 itoft %1,%0"
6228 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6230 (define_insn "*mov<mode>_nofix"
6231 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6232 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6233 "! TARGET_FIX
6234 && (register_operand (operands[0], <MODE>mode)
6235 || reg_or_0_operand (operands[1], <MODE>mode))"
6236 "@
6237 bis $31,%r1,%0
6238 #
6239 ldq %0,%1
6240 stq %r1,%0
6241 cpys %R1,%R1,%0
6242 ldt %0,%1
6243 stt %R1,%0"
6244 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6246 (define_insn "uminv8qi3"
6247 [(set (match_operand:V8QI 0 "register_operand" "=r")
6248 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6249 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6250 "TARGET_MAX"
6251 "minub8 %r1,%r2,%0"
6252 [(set_attr "type" "mvi")])
6254 (define_insn "sminv8qi3"
6255 [(set (match_operand:V8QI 0 "register_operand" "=r")
6256 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6257 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6258 "TARGET_MAX"
6259 "minsb8 %r1,%r2,%0"
6260 [(set_attr "type" "mvi")])
6262 (define_insn "uminv4hi3"
6263 [(set (match_operand:V4HI 0 "register_operand" "=r")
6264 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6265 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6266 "TARGET_MAX"
6267 "minuw4 %r1,%r2,%0"
6268 [(set_attr "type" "mvi")])
6270 (define_insn "sminv4hi3"
6271 [(set (match_operand:V4HI 0 "register_operand" "=r")
6272 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6273 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6274 "TARGET_MAX"
6275 "minsw4 %r1,%r2,%0"
6276 [(set_attr "type" "mvi")])
6278 (define_insn "umaxv8qi3"
6279 [(set (match_operand:V8QI 0 "register_operand" "=r")
6280 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6281 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6282 "TARGET_MAX"
6283 "maxub8 %r1,%r2,%0"
6284 [(set_attr "type" "mvi")])
6286 (define_insn "smaxv8qi3"
6287 [(set (match_operand:V8QI 0 "register_operand" "=r")
6288 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6289 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6290 "TARGET_MAX"
6291 "maxsb8 %r1,%r2,%0"
6292 [(set_attr "type" "mvi")])
6294 (define_insn "umaxv4hi3"
6295 [(set (match_operand:V4HI 0 "register_operand" "=r")
6296 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6297 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6298 "TARGET_MAX"
6299 "maxuw4 %r1,%r2,%0"
6300 [(set_attr "type" "mvi")])
6302 (define_insn "smaxv4hi3"
6303 [(set (match_operand:V4HI 0 "register_operand" "=r")
6304 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6305 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6306 "TARGET_MAX"
6307 "maxsw4 %r1,%r2,%0"
6308 [(set_attr "type" "mvi")])
6310 (define_insn "one_cmpl<mode>2"
6311 [(set (match_operand:VEC 0 "register_operand" "=r")
6312 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6313 ""
6314 "ornot $31,%1,%0"
6315 [(set_attr "type" "ilog")])
6317 (define_insn "and<mode>3"
6318 [(set (match_operand:VEC 0 "register_operand" "=r")
6319 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6320 (match_operand:VEC 2 "register_operand" "r")))]
6321 ""
6322 "and %1,%2,%0"
6323 [(set_attr "type" "ilog")])
6325 (define_insn "*andnot<mode>3"
6326 [(set (match_operand:VEC 0 "register_operand" "=r")
6327 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6328 (match_operand:VEC 2 "register_operand" "r")))]
6329 ""
6330 "bic %2,%1,%0"
6331 [(set_attr "type" "ilog")])
6333 (define_insn "ior<mode>3"
6334 [(set (match_operand:VEC 0 "register_operand" "=r")
6335 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6336 (match_operand:VEC 2 "register_operand" "r")))]
6337 ""
6338 "bis %1,%2,%0"
6339 [(set_attr "type" "ilog")])
6341 (define_insn "*iornot<mode>3"
6342 [(set (match_operand:VEC 0 "register_operand" "=r")
6343 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6344 (match_operand:VEC 2 "register_operand" "r")))]
6345 ""
6346 "ornot %2,%1,%0"
6347 [(set_attr "type" "ilog")])
6349 (define_insn "xor<mode>3"
6350 [(set (match_operand:VEC 0 "register_operand" "=r")
6351 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6352 (match_operand:VEC 2 "register_operand" "r")))]
6353 ""
6354 "xor %1,%2,%0"
6355 [(set_attr "type" "ilog")])
6357 (define_insn "*xornot<mode>3"
6358 [(set (match_operand:VEC 0 "register_operand" "=r")
6359 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6360 (match_operand:VEC 2 "register_operand" "r"))))]
6361 ""
6362 "eqv %1,%2,%0"
6363 [(set_attr "type" "ilog")])
6364 \f
6365 ;; Bit field extract patterns which use ext[wlq][lh]
6367 (define_expand "extv"
6368 [(set (match_operand:DI 0 "register_operand" "")
6369 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6370 (match_operand:DI 2 "immediate_operand" "")
6371 (match_operand:DI 3 "immediate_operand" "")))]
6372 ""
6373 {
6374 int ofs;
6376 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6377 if (INTVAL (operands[3]) % 8 != 0
6378 || (INTVAL (operands[2]) != 16
6379 && INTVAL (operands[2]) != 32
6380 && INTVAL (operands[2]) != 64))
6381 FAIL;
6383 /* From mips.md: extract_bit_field doesn't verify that our source
6384 matches the predicate, so we force it to be a MEM here. */
6385 if (GET_CODE (operands[1]) != MEM)
6386 FAIL;
6388 /* The bit number is relative to the mode of operand 1 which is
6389 usually QImode (this might actually be a bug in expmed.c). Note
6390 that the bit number is negative in big-endian mode in this case.
6391 We have to convert that to the offset. */
6392 if (WORDS_BIG_ENDIAN)
6393 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6394 - INTVAL (operands[2]) - INTVAL (operands[3]);
6395 else
6396 ofs = INTVAL (operands[3]);
6398 ofs = ofs / 8;
6400 alpha_expand_unaligned_load (operands[0], operands[1],
6401 INTVAL (operands[2]) / 8,
6402 ofs, 1);
6403 DONE;
6404 })
6406 (define_expand "extzv"
6407 [(set (match_operand:DI 0 "register_operand" "")
6408 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6409 (match_operand:DI 2 "immediate_operand" "")
6410 (match_operand:DI 3 "immediate_operand" "")))]
6411 ""
6412 {
6413 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6414 if (INTVAL (operands[3]) % 8 != 0
6415 || (INTVAL (operands[2]) != 8
6416 && INTVAL (operands[2]) != 16
6417 && INTVAL (operands[2]) != 32
6418 && INTVAL (operands[2]) != 64))
6419 FAIL;
6421 if (GET_CODE (operands[1]) == MEM)
6422 {
6423 int ofs;
6425 /* Fail 8 bit fields, falling back on a simple byte load. */
6426 if (INTVAL (operands[2]) == 8)
6427 FAIL;
6429 /* The bit number is relative to the mode of operand 1 which is
6430 usually QImode (this might actually be a bug in expmed.c). Note
6431 that the bit number is negative in big-endian mode in this case.
6432 We have to convert that to the offset. */
6433 if (WORDS_BIG_ENDIAN)
6434 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6435 - INTVAL (operands[2]) - INTVAL (operands[3]);
6436 else
6437 ofs = INTVAL (operands[3]);
6439 ofs = ofs / 8;
6441 alpha_expand_unaligned_load (operands[0], operands[1],
6442 INTVAL (operands[2]) / 8,
6443 ofs, 0);
6444 DONE;
6445 }
6446 })
6448 (define_expand "insv"
6449 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6450 (match_operand:DI 1 "immediate_operand" "")
6451 (match_operand:DI 2 "immediate_operand" ""))
6452 (match_operand:DI 3 "register_operand" ""))]
6453 ""
6454 {
6455 int ofs;
6457 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6458 if (INTVAL (operands[2]) % 8 != 0
6459 || (INTVAL (operands[1]) != 16
6460 && INTVAL (operands[1]) != 32
6461 && INTVAL (operands[1]) != 64))
6462 FAIL;
6464 /* From mips.md: store_bit_field doesn't verify that our source
6465 matches the predicate, so we force it to be a MEM here. */
6466 if (GET_CODE (operands[0]) != MEM)
6467 FAIL;
6469 /* The bit number is relative to the mode of operand 1 which is
6470 usually QImode (this might actually be a bug in expmed.c). Note
6471 that the bit number is negative in big-endian mode in this case.
6472 We have to convert that to the offset. */
6473 if (WORDS_BIG_ENDIAN)
6474 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6475 - INTVAL (operands[1]) - INTVAL (operands[2]);
6476 else
6477 ofs = INTVAL (operands[2]);
6479 ofs = ofs / 8;
6481 alpha_expand_unaligned_store (operands[0], operands[3],
6482 INTVAL (operands[1]) / 8, ofs);
6483 DONE;
6484 })
6486 ;; Block move/clear, see alpha.c for more details.
6487 ;; Argument 0 is the destination
6488 ;; Argument 1 is the source
6489 ;; Argument 2 is the length
6490 ;; Argument 3 is the alignment
6492 (define_expand "movmemqi"
6493 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6494 (match_operand:BLK 1 "memory_operand" ""))
6495 (use (match_operand:DI 2 "immediate_operand" ""))
6496 (use (match_operand:DI 3 "immediate_operand" ""))])]
6497 ""
6498 {
6499 if (alpha_expand_block_move (operands))
6500 DONE;
6501 else
6502 FAIL;
6503 })
6505 (define_expand "movmemdi"
6506 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6507 (match_operand:BLK 1 "memory_operand" ""))
6508 (use (match_operand:DI 2 "immediate_operand" ""))
6509 (use (match_operand:DI 3 "immediate_operand" ""))
6510 (use (match_dup 4))
6511 (clobber (reg:DI 25))
6512 (clobber (reg:DI 16))
6513 (clobber (reg:DI 17))
6514 (clobber (reg:DI 18))
6515 (clobber (reg:DI 19))
6516 (clobber (reg:DI 20))
6517 (clobber (reg:DI 26))
6518 (clobber (reg:DI 27))])]
6519 "TARGET_ABI_OPEN_VMS"
6520 {
6521 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6522 alpha_need_linkage (XSTR (operands[4], 0), 0);
6523 })
6525 (define_insn "*movmemdi_1"
6526 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6527 (match_operand:BLK 1 "memory_operand" "m,m"))
6528 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6529 (use (match_operand:DI 3 "immediate_operand" ""))
6530 (use (match_operand:DI 4 "call_operand" "i,i"))
6531 (clobber (reg:DI 25))
6532 (clobber (reg:DI 16))
6533 (clobber (reg:DI 17))
6534 (clobber (reg:DI 18))
6535 (clobber (reg:DI 19))
6536 (clobber (reg:DI 20))
6537 (clobber (reg:DI 26))
6538 (clobber (reg:DI 27))]
6539 "TARGET_ABI_OPEN_VMS"
6540 {
6541 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6542 switch (which_alternative)
6543 {
6544 case 0:
6545 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6546 case 1:
6547 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6548 default:
6549 gcc_unreachable ();
6550 }
6551 }
6552 [(set_attr "type" "multi")
6553 (set_attr "length" "28")])
6555 (define_expand "clrmemqi"
6556 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6557 (const_int 0))
6558 (use (match_operand:DI 1 "immediate_operand" ""))
6559 (use (match_operand:DI 2 "immediate_operand" ""))])]
6560 ""
6561 {
6562 if (alpha_expand_block_clear (operands))
6563 DONE;
6564 else
6565 FAIL;
6566 })
6568 (define_expand "clrmemdi"
6569 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6570 (const_int 0))
6571 (use (match_operand:DI 1 "immediate_operand" ""))
6572 (use (match_operand:DI 2 "immediate_operand" ""))
6573 (use (match_dup 3))
6574 (clobber (reg:DI 25))
6575 (clobber (reg:DI 16))
6576 (clobber (reg:DI 17))
6577 (clobber (reg:DI 26))
6578 (clobber (reg:DI 27))])]
6579 "TARGET_ABI_OPEN_VMS"
6580 {
6581 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6582 alpha_need_linkage (XSTR (operands[3], 0), 0);
6583 })
6585 (define_insn "*clrmemdi_1"
6586 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6587 (const_int 0))
6588 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6589 (use (match_operand:DI 2 "immediate_operand" ""))
6590 (use (match_operand:DI 3 "call_operand" "i,i"))
6591 (clobber (reg:DI 25))
6592 (clobber (reg:DI 16))
6593 (clobber (reg:DI 17))
6594 (clobber (reg:DI 26))
6595 (clobber (reg:DI 27))]
6596 "TARGET_ABI_OPEN_VMS"
6597 {
6598 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6599 switch (which_alternative)
6600 {
6601 case 0:
6602 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6603 case 1:
6604 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6605 default:
6606 gcc_unreachable ();
6607 }
6608 }
6609 [(set_attr "type" "multi")
6610 (set_attr "length" "24")])
6612 \f
6613 ;; Subroutine of stack space allocation. Perform a stack probe.
6614 (define_expand "probe_stack"
6615 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6616 ""
6617 {
6618 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6619 INTVAL (operands[0])));
6620 MEM_VOLATILE_P (operands[1]) = 1;
6622 operands[0] = const0_rtx;
6623 })
6625 ;; This is how we allocate stack space. If we are allocating a
6626 ;; constant amount of space and we know it is less than 4096
6627 ;; bytes, we need do nothing.
6628 ;;
6629 ;; If it is more than 4096 bytes, we need to probe the stack
6630 ;; periodically.
6631 (define_expand "allocate_stack"
6632 [(set (reg:DI 30)
6633 (plus:DI (reg:DI 30)
6634 (match_operand:DI 1 "reg_or_cint_operand" "")))
6635 (set (match_operand:DI 0 "register_operand" "=r")
6636 (match_dup 2))]
6637 ""
6638 {
6639 if (GET_CODE (operands[1]) == CONST_INT
6640 && INTVAL (operands[1]) < 32768)
6641 {
6642 if (INTVAL (operands[1]) >= 4096)
6643 {
6644 /* We do this the same way as in the prologue and generate explicit
6645 probes. Then we update the stack by the constant. */
6647 int probed = 4096;
6649 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6650 while (probed + 8192 < INTVAL (operands[1]))
6651 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6653 if (probed + 4096 < INTVAL (operands[1]))
6654 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6655 }
6657 operands[1] = GEN_INT (- INTVAL (operands[1]));
6658 operands[2] = virtual_stack_dynamic_rtx;
6659 }
6660 else
6661 {
6662 rtx out_label = 0;
6663 rtx loop_label = gen_label_rtx ();
6664 rtx want = gen_reg_rtx (Pmode);
6665 rtx tmp = gen_reg_rtx (Pmode);
6666 rtx memref;
6668 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6669 force_reg (Pmode, operands[1])));
6670 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6672 if (GET_CODE (operands[1]) != CONST_INT)
6673 {
6674 out_label = gen_label_rtx ();
6675 emit_insn (gen_cmpdi (want, tmp));
6676 emit_jump_insn (gen_bgeu (out_label));
6677 }
6679 emit_label (loop_label);
6680 memref = gen_rtx_MEM (DImode, tmp);
6681 MEM_VOLATILE_P (memref) = 1;
6682 emit_move_insn (memref, const0_rtx);
6683 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6684 emit_insn (gen_cmpdi (tmp, want));
6685 emit_jump_insn (gen_bgtu (loop_label));
6687 memref = gen_rtx_MEM (DImode, want);
6688 MEM_VOLATILE_P (memref) = 1;
6689 emit_move_insn (memref, const0_rtx);
6691 if (out_label)
6692 emit_label (out_label);
6694 emit_move_insn (stack_pointer_rtx, want);
6695 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6696 DONE;
6697 }
6698 })
6700 ;; This is used by alpha_expand_prolog to do the same thing as above,
6701 ;; except we cannot at that time generate new basic blocks, so we hide
6702 ;; the loop in this one insn.
6704 (define_insn "prologue_stack_probe_loop"
6705 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6706 (match_operand:DI 1 "register_operand" "r")]
6707 UNSPECV_PSPL)]
6708 ""
6709 {
6710 operands[2] = gen_label_rtx ();
6711 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6712 CODE_LABEL_NUMBER (operands[2]));
6714 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6715 }
6716 [(set_attr "length" "16")
6717 (set_attr "type" "multi")])
6719 (define_expand "prologue"
6720 [(clobber (const_int 0))]
6721 ""
6722 {
6723 alpha_expand_prologue ();
6724 DONE;
6725 })
6727 ;; These take care of emitting the ldgp insn in the prologue. This will be
6728 ;; an lda/ldah pair and we want to align them properly. So we have two
6729 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6730 ;; and the second of which emits nothing. However, both are marked as type
6731 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6732 ;; with them.
6734 (define_expand "prologue_ldgp"
6735 [(set (match_dup 0)
6736 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6737 (set (match_dup 0)
6738 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6739 ""
6740 {
6741 operands[0] = pic_offset_table_rtx;
6742 operands[1] = gen_rtx_REG (Pmode, 27);
6743 operands[2] = (TARGET_EXPLICIT_RELOCS
6744 ? GEN_INT (alpha_next_sequence_number++)
6745 : const0_rtx);
6746 })
6748 (define_insn "*ldgp_er_1"
6749 [(set (match_operand:DI 0 "register_operand" "=r")
6750 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6751 (match_operand 2 "const_int_operand" "")]
6752 UNSPECV_LDGP1))]
6753 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6754 "ldah %0,0(%1)\t\t!gpdisp!%2"
6755 [(set_attr "cannot_copy" "true")])
6757 (define_insn "*ldgp_er_2"
6758 [(set (match_operand:DI 0 "register_operand" "=r")
6759 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6760 (match_operand 2 "const_int_operand" "")]
6761 UNSPEC_LDGP2))]
6762 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6763 "lda %0,0(%1)\t\t!gpdisp!%2"
6764 [(set_attr "cannot_copy" "true")])
6766 (define_insn "*prologue_ldgp_er_2"
6767 [(set (match_operand:DI 0 "register_operand" "=r")
6768 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6769 (match_operand 2 "const_int_operand" "")]
6770 UNSPECV_PLDGP2))]
6771 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6772 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6773 [(set_attr "cannot_copy" "true")])
6775 (define_insn "*prologue_ldgp_1"
6776 [(set (match_operand:DI 0 "register_operand" "=r")
6777 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6778 (match_operand 2 "const_int_operand" "")]
6779 UNSPECV_LDGP1))]
6780 ""
6781 "ldgp %0,0(%1)\n$%~..ng:"
6782 [(set_attr "cannot_copy" "true")])
6784 (define_insn "*prologue_ldgp_2"
6785 [(set (match_operand:DI 0 "register_operand" "=r")
6786 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6787 (match_operand 2 "const_int_operand" "")]
6788 UNSPECV_PLDGP2))]
6789 ""
6790 "")
6792 ;; The _mcount profiling hook has special calling conventions, and
6793 ;; does not clobber all the registers that a normal call would. So
6794 ;; hide the fact this is a call at all.
6796 (define_insn "prologue_mcount"
6797 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6798 ""
6799 {
6800 if (TARGET_EXPLICIT_RELOCS)
6801 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6802 cannot be called via the PLT. */
6803 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6804 else
6805 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6806 }
6807 [(set_attr "type" "multi")
6808 (set_attr "length" "8")])
6810 (define_insn "init_fp"
6811 [(set (match_operand:DI 0 "register_operand" "=r")
6812 (match_operand:DI 1 "register_operand" "r"))
6813 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6814 ""
6815 "bis $31,%1,%0")
6817 (define_expand "epilogue"
6818 [(return)]
6819 ""
6820 {
6821 alpha_expand_epilogue ();
6822 })
6824 (define_expand "sibcall_epilogue"
6825 [(return)]
6826 "TARGET_ABI_OSF"
6827 {
6828 alpha_expand_epilogue ();
6829 DONE;
6830 })
6832 (define_expand "builtin_longjmp"
6833 [(use (match_operand:DI 0 "register_operand" "r"))]
6834 "TARGET_ABI_OSF"
6835 {
6836 /* The elements of the buffer are, in order: */
6837 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6838 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6839 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6840 rtx pv = gen_rtx_REG (Pmode, 27);
6842 /* This bit is the same as expand_builtin_longjmp. */
6843 emit_move_insn (hard_frame_pointer_rtx, fp);
6844 emit_move_insn (pv, lab);
6845 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6846 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6847 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6849 /* Load the label we are jumping through into $27 so that we know
6850 where to look for it when we get back to setjmp's function for
6851 restoring the gp. */
6852 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6853 emit_barrier ();
6854 DONE;
6855 })
6857 ;; This is effectively a copy of indirect_jump, but constrained such
6858 ;; that register renaming cannot foil our cunning plan with $27.
6859 (define_insn "builtin_longjmp_internal"
6860 [(set (pc)
6861 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6862 UNSPECV_LONGJMP))]
6863 ""
6864 "jmp $31,(%0),0"
6865 [(set_attr "type" "ibr")])
6867 (define_expand "builtin_setjmp_receiver"
6868 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6869 "TARGET_ABI_OSF"
6870 "")
6872 (define_insn_and_split "*builtin_setjmp_receiver_1"
6873 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6874 "TARGET_ABI_OSF"
6875 {
6876 if (TARGET_EXPLICIT_RELOCS)
6877 return "#";
6878 else
6879 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6880 }
6881 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6882 [(set (match_dup 1)
6883 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6884 (set (match_dup 1)
6885 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6886 {
6887 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6888 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6889 UNSPECV_SETJMPR_ER));
6890 operands[1] = pic_offset_table_rtx;
6891 operands[2] = gen_rtx_REG (Pmode, 27);
6892 operands[3] = GEN_INT (alpha_next_sequence_number++);
6893 }
6894 [(set_attr "length" "12")
6895 (set_attr "type" "multi")])
6897 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6898 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6899 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6900 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6902 (define_insn "*builtin_setjmp_receiver_er_1"
6903 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6904 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
6905 "br $27,$LSJ%=\n$LSJ%=:"
6906 [(set_attr "type" "ibr")])
6908 (define_expand "exception_receiver"
6909 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6910 "TARGET_ABI_OSF"
6911 {
6912 if (TARGET_LD_BUGGY_LDGP)
6913 operands[0] = alpha_gp_save_rtx ();
6914 else
6915 operands[0] = const0_rtx;
6916 })
6918 (define_insn "*exception_receiver_2"
6919 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6920 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
6921 "ldq $29,%0"
6922 [(set_attr "type" "ild")])
6924 (define_insn_and_split "*exception_receiver_1"
6925 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6926 "TARGET_ABI_OSF"
6927 {
6928 if (TARGET_EXPLICIT_RELOCS)
6929 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
6930 else
6931 return "ldgp $29,0($26)";
6932 }
6933 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6934 [(set (match_dup 0)
6935 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6936 (set (match_dup 0)
6937 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6938 {
6939 operands[0] = pic_offset_table_rtx;
6940 operands[1] = gen_rtx_REG (Pmode, 26);
6941 operands[2] = GEN_INT (alpha_next_sequence_number++);
6942 }
6943 [(set_attr "length" "8")
6944 (set_attr "type" "multi")])
6946 (define_expand "nonlocal_goto_receiver"
6947 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6948 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6949 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6950 (use (reg:DI 27))]
6951 "TARGET_ABI_OPEN_VMS"
6952 "")
6954 (define_insn "arg_home"
6955 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6956 (use (reg:DI 1))
6957 (use (reg:DI 25))
6958 (use (reg:DI 16))
6959 (use (reg:DI 17))
6960 (use (reg:DI 18))
6961 (use (reg:DI 19))
6962 (use (reg:DI 20))
6963 (use (reg:DI 21))
6964 (use (reg:DI 48))
6965 (use (reg:DI 49))
6966 (use (reg:DI 50))
6967 (use (reg:DI 51))
6968 (use (reg:DI 52))
6969 (use (reg:DI 53))
6970 (clobber (mem:BLK (const_int 0)))
6971 (clobber (reg:DI 24))
6972 (clobber (reg:DI 25))
6973 (clobber (reg:DI 0))]
6974 "TARGET_ABI_OPEN_VMS"
6975 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6976 [(set_attr "length" "16")
6977 (set_attr "type" "multi")])
6979 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6981 (define_expand "umk_mismatch_args"
6982 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6983 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6984 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6985 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6986 (const_int 8))
6987 (match_dup 2)))
6988 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6989 "TARGET_ABI_UNICOSMK"
6990 {
6991 operands[1] = gen_reg_rtx (DImode);
6992 operands[2] = gen_reg_rtx (DImode);
6993 operands[3] = gen_reg_rtx (DImode);
6994 })
6996 (define_insn "arg_home_umk"
6997 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6998 (use (reg:DI 1))
6999 (use (reg:DI 2))
7000 (use (reg:DI 16))
7001 (use (reg:DI 17))
7002 (use (reg:DI 18))
7003 (use (reg:DI 19))
7004 (use (reg:DI 20))
7005 (use (reg:DI 21))
7006 (use (reg:DI 48))
7007 (use (reg:DI 49))
7008 (use (reg:DI 50))
7009 (use (reg:DI 51))
7010 (use (reg:DI 52))
7011 (use (reg:DI 53))
7012 (clobber (mem:BLK (const_int 0)))
7013 (parallel [
7014 (clobber (reg:DI 22))
7015 (clobber (reg:DI 23))
7016 (clobber (reg:DI 24))
7017 (clobber (reg:DI 0))
7018 (clobber (reg:DI 1))
7019 (clobber (reg:DI 2))
7020 (clobber (reg:DI 3))
7021 (clobber (reg:DI 4))
7022 (clobber (reg:DI 5))
7023 (clobber (reg:DI 6))
7024 (clobber (reg:DI 7))
7025 (clobber (reg:DI 8))])]
7026 "TARGET_ABI_UNICOSMK"
7027 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7028 [(set_attr "length" "16")
7029 (set_attr "type" "multi")])
7031 ;; Prefetch data.
7032 ;;
7033 ;; On EV4, these instructions are nops -- no load occurs.
7034 ;;
7035 ;; On EV5, these instructions act as a normal load, and thus can trap
7036 ;; if the address is invalid. The OS may (or may not) handle this in
7037 ;; the entMM fault handler and suppress the fault. If so, then this
7038 ;; has the effect of a read prefetch instruction.
7039 ;;
7040 ;; On EV6, these become official prefetch instructions.
7042 (define_insn "prefetch"
7043 [(prefetch (match_operand:DI 0 "address_operand" "p")
7044 (match_operand:DI 1 "const_int_operand" "n")
7045 (match_operand:DI 2 "const_int_operand" "n"))]
7046 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7047 {
7048 /* Interpret "no temporal locality" as this data should be evicted once
7049 it is used. The "evict next" alternatives load the data into the cache
7050 and leave the LRU eviction counter pointing to that block. */
7051 static const char * const alt[2][2] = {
7052 {
7053 "ldq $31,%a0", /* read, evict next */
7054 "ldl $31,%a0", /* read, evict last */
7055 },
7056 {
7057 "ldt $f31,%a0", /* write, evict next */
7058 "lds $f31,%a0", /* write, evict last */
7059 }
7060 };
7062 bool write = INTVAL (operands[1]) != 0;
7063 bool lru = INTVAL (operands[2]) != 0;
7065 return alt[write][lru];
7066 }
7067 [(set_attr "type" "ild")])
7069 ;; Close the trap shadow of preceding instructions. This is generated
7070 ;; by alpha_reorg.
7072 (define_insn "trapb"
7073 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7074 ""
7075 "trapb"
7076 [(set_attr "type" "misc")])
7078 ;; No-op instructions used by machine-dependent reorg to preserve
7079 ;; alignment for instruction issue.
7080 ;; The Unicos/Mk assembler does not support these opcodes.
7082 (define_insn "nop"
7083 [(const_int 0)]
7084 ""
7085 "bis $31,$31,$31"
7086 [(set_attr "type" "ilog")])
7088 (define_insn "fnop"
7089 [(const_int 1)]
7090 "TARGET_FP"
7091 "cpys $f31,$f31,$f31"
7092 [(set_attr "type" "fcpys")])
7094 (define_insn "unop"
7095 [(const_int 2)]
7096 ""
7097 "ldq_u $31,0($30)")
7099 ;; On Unicos/Mk we use a macro for aligning code.
7101 (define_insn "realign"
7102 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7103 UNSPECV_REALIGN)]
7104 ""
7105 {
7106 if (TARGET_ABI_UNICOSMK)
7107 return "gcc@code@align %0";
7108 else
7109 return ".align %0 #realign";
7110 })
7111 \f
7112 ;; Instructions to be emitted from __builtins.
7114 (define_insn "builtin_cmpbge"
7115 [(set (match_operand:DI 0 "register_operand" "=r")
7116 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7117 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7118 UNSPEC_CMPBGE))]
7119 ""
7120 "cmpbge %r1,%2,%0"
7121 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7122 ;; actually differentiate between ILOG and ICMP in the schedule.
7123 [(set_attr "type" "icmp")])
7125 (define_expand "builtin_extbl"
7126 [(match_operand:DI 0 "register_operand" "")
7127 (match_operand:DI 1 "reg_or_0_operand" "")
7128 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7129 ""
7130 {
7131 rtx (*gen) (rtx, rtx, rtx, rtx);
7132 if (WORDS_BIG_ENDIAN)
7133 gen = gen_extxl_be;
7134 else
7135 gen = gen_extxl_le;
7136 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7137 DONE;
7138 })
7140 (define_expand "builtin_extwl"
7141 [(match_operand:DI 0 "register_operand" "")
7142 (match_operand:DI 1 "reg_or_0_operand" "")
7143 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7144 ""
7145 {
7146 rtx (*gen) (rtx, rtx, rtx, rtx);
7147 if (WORDS_BIG_ENDIAN)
7148 gen = gen_extxl_be;
7149 else
7150 gen = gen_extxl_le;
7151 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7152 DONE;
7153 })
7155 (define_expand "builtin_extll"
7156 [(match_operand:DI 0 "register_operand" "")
7157 (match_operand:DI 1 "reg_or_0_operand" "")
7158 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7159 ""
7160 {
7161 rtx (*gen) (rtx, rtx, rtx, rtx);
7162 if (WORDS_BIG_ENDIAN)
7163 gen = gen_extxl_be;
7164 else
7165 gen = gen_extxl_le;
7166 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7167 DONE;
7168 })
7170 (define_expand "builtin_extql"
7171 [(match_operand:DI 0 "register_operand" "")
7172 (match_operand:DI 1 "reg_or_0_operand" "")
7173 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7174 ""
7175 {
7176 rtx (*gen) (rtx, rtx, rtx, rtx);
7177 if (WORDS_BIG_ENDIAN)
7178 gen = gen_extxl_be;
7179 else
7180 gen = gen_extxl_le;
7181 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7182 DONE;
7183 })
7185 (define_expand "builtin_extwh"
7186 [(match_operand:DI 0 "register_operand" "")
7187 (match_operand:DI 1 "reg_or_0_operand" "")
7188 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7189 ""
7190 {
7191 rtx (*gen) (rtx, rtx, rtx);
7192 if (WORDS_BIG_ENDIAN)
7193 gen = gen_extwh_be;
7194 else
7195 gen = gen_extwh_le;
7196 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7197 DONE;
7198 })
7200 (define_expand "builtin_extlh"
7201 [(match_operand:DI 0 "register_operand" "")
7202 (match_operand:DI 1 "reg_or_0_operand" "")
7203 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7204 ""
7205 {
7206 rtx (*gen) (rtx, rtx, rtx);
7207 if (WORDS_BIG_ENDIAN)
7208 gen = gen_extlh_be;
7209 else
7210 gen = gen_extlh_le;
7211 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7212 DONE;
7213 })
7215 (define_expand "builtin_extqh"
7216 [(match_operand:DI 0 "register_operand" "")
7217 (match_operand:DI 1 "reg_or_0_operand" "")
7218 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7219 ""
7220 {
7221 rtx (*gen) (rtx, rtx, rtx);
7222 if (WORDS_BIG_ENDIAN)
7223 gen = gen_extqh_be;
7224 else
7225 gen = gen_extqh_le;
7226 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7227 DONE;
7228 })
7230 (define_expand "builtin_insbl"
7231 [(match_operand:DI 0 "register_operand" "")
7232 (match_operand:DI 1 "register_operand" "")
7233 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7234 ""
7235 {
7236 rtx (*gen) (rtx, rtx, rtx);
7237 if (WORDS_BIG_ENDIAN)
7238 gen = gen_insbl_be;
7239 else
7240 gen = gen_insbl_le;
7241 operands[1] = gen_lowpart (QImode, operands[1]);
7242 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7243 DONE;
7244 })
7246 (define_expand "builtin_inswl"
7247 [(match_operand:DI 0 "register_operand" "")
7248 (match_operand:DI 1 "register_operand" "")
7249 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7250 ""
7251 {
7252 rtx (*gen) (rtx, rtx, rtx);
7253 if (WORDS_BIG_ENDIAN)
7254 gen = gen_inswl_be;
7255 else
7256 gen = gen_inswl_le;
7257 operands[1] = gen_lowpart (HImode, operands[1]);
7258 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7259 DONE;
7260 })
7262 (define_expand "builtin_insll"
7263 [(match_operand:DI 0 "register_operand" "")
7264 (match_operand:DI 1 "register_operand" "")
7265 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7266 ""
7267 {
7268 rtx (*gen) (rtx, rtx, rtx);
7269 if (WORDS_BIG_ENDIAN)
7270 gen = gen_insll_be;
7271 else
7272 gen = gen_insll_le;
7273 operands[1] = gen_lowpart (SImode, operands[1]);
7274 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7275 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7276 DONE;
7277 })
7279 (define_expand "builtin_insql"
7280 [(match_operand:DI 0 "register_operand" "")
7281 (match_operand:DI 1 "reg_or_0_operand" "")
7282 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7283 ""
7284 {
7285 rtx (*gen) (rtx, rtx, rtx);
7286 if (WORDS_BIG_ENDIAN)
7287 gen = gen_insql_be;
7288 else
7289 gen = gen_insql_le;
7290 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7291 DONE;
7292 })
7294 (define_expand "builtin_inswh"
7295 [(match_operand:DI 0 "register_operand" "")
7296 (match_operand:DI 1 "register_operand" "")
7297 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7298 ""
7299 {
7300 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7301 DONE;
7302 })
7304 (define_expand "builtin_inslh"
7305 [(match_operand:DI 0 "register_operand" "")
7306 (match_operand:DI 1 "register_operand" "")
7307 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7308 ""
7309 {
7310 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7311 DONE;
7312 })
7314 (define_expand "builtin_insqh"
7315 [(match_operand:DI 0 "register_operand" "")
7316 (match_operand:DI 1 "register_operand" "")
7317 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7318 ""
7319 {
7320 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7321 DONE;
7322 })
7324 (define_expand "builtin_mskbl"
7325 [(match_operand:DI 0 "register_operand" "")
7326 (match_operand:DI 1 "reg_or_0_operand" "")
7327 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7328 ""
7329 {
7330 rtx (*gen) (rtx, rtx, rtx, rtx);
7331 rtx mask;
7332 if (WORDS_BIG_ENDIAN)
7333 gen = gen_mskxl_be;
7334 else
7335 gen = gen_mskxl_le;
7336 mask = GEN_INT (0xff);
7337 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7338 DONE;
7339 })
7341 (define_expand "builtin_mskwl"
7342 [(match_operand:DI 0 "register_operand" "")
7343 (match_operand:DI 1 "reg_or_0_operand" "")
7344 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7345 ""
7346 {
7347 rtx (*gen) (rtx, rtx, rtx, rtx);
7348 rtx mask;
7349 if (WORDS_BIG_ENDIAN)
7350 gen = gen_mskxl_be;
7351 else
7352 gen = gen_mskxl_le;
7353 mask = GEN_INT (0xffff);
7354 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7355 DONE;
7356 })
7358 (define_expand "builtin_mskll"
7359 [(match_operand:DI 0 "register_operand" "")
7360 (match_operand:DI 1 "reg_or_0_operand" "")
7361 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7362 ""
7363 {
7364 rtx (*gen) (rtx, rtx, rtx, rtx);
7365 rtx mask;
7366 if (WORDS_BIG_ENDIAN)
7367 gen = gen_mskxl_be;
7368 else
7369 gen = gen_mskxl_le;
7370 mask = immed_double_const (0xffffffff, 0, DImode);
7371 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7372 DONE;
7373 })
7375 (define_expand "builtin_mskql"
7376 [(match_operand:DI 0 "register_operand" "")
7377 (match_operand:DI 1 "reg_or_0_operand" "")
7378 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7379 ""
7380 {
7381 rtx (*gen) (rtx, rtx, rtx, rtx);
7382 rtx mask;
7383 if (WORDS_BIG_ENDIAN)
7384 gen = gen_mskxl_be;
7385 else
7386 gen = gen_mskxl_le;
7387 mask = constm1_rtx;
7388 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7389 DONE;
7390 })
7392 (define_expand "builtin_mskwh"
7393 [(match_operand:DI 0 "register_operand" "")
7394 (match_operand:DI 1 "register_operand" "")
7395 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7396 ""
7397 {
7398 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7399 DONE;
7400 })
7402 (define_expand "builtin_msklh"
7403 [(match_operand:DI 0 "register_operand" "")
7404 (match_operand:DI 1 "register_operand" "")
7405 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7406 ""
7407 {
7408 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7409 DONE;
7410 })
7412 (define_expand "builtin_mskqh"
7413 [(match_operand:DI 0 "register_operand" "")
7414 (match_operand:DI 1 "register_operand" "")
7415 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7416 ""
7417 {
7418 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7419 DONE;
7420 })
7422 (define_expand "builtin_zap"
7423 [(set (match_operand:DI 0 "register_operand" "")
7424 (and:DI (unspec:DI
7425 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7426 UNSPEC_ZAP)
7427 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7428 ""
7429 {
7430 if (GET_CODE (operands[2]) == CONST_INT)
7431 {
7432 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7434 if (mask == const0_rtx)
7435 {
7436 emit_move_insn (operands[0], const0_rtx);
7437 DONE;
7438 }
7439 if (mask == constm1_rtx)
7440 {
7441 emit_move_insn (operands[0], operands[1]);
7442 DONE;
7443 }
7445 operands[1] = force_reg (DImode, operands[1]);
7446 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7447 DONE;
7448 }
7450 operands[1] = force_reg (DImode, operands[1]);
7451 operands[2] = gen_lowpart (QImode, operands[2]);
7452 })
7454 (define_insn "*builtin_zap_1"
7455 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7456 (and:DI (unspec:DI
7457 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7458 UNSPEC_ZAP)
7459 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7460 ""
7461 "@
7462 #
7463 #
7464 bis $31,$31,%0
7465 zap %r1,%2,%0"
7466 [(set_attr "type" "shift,shift,ilog,shift")])
7468 (define_split
7469 [(set (match_operand:DI 0 "register_operand" "")
7470 (and:DI (unspec:DI
7471 [(match_operand:QI 2 "const_int_operand" "")]
7472 UNSPEC_ZAP)
7473 (match_operand:DI 1 "const_int_operand" "")))]
7474 ""
7475 [(const_int 0)]
7476 {
7477 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7478 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7479 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7480 else
7481 {
7482 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7483 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7484 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7485 c_hi & CONST_DOUBLE_HIGH (mask),
7486 DImode);
7487 }
7488 emit_move_insn (operands[0], operands[1]);
7489 DONE;
7490 })
7492 (define_split
7493 [(set (match_operand:DI 0 "register_operand" "")
7494 (and:DI (unspec:DI
7495 [(match_operand:QI 2 "const_int_operand" "")]
7496 UNSPEC_ZAP)
7497 (match_operand:DI 1 "register_operand" "")))]
7498 ""
7499 [(set (match_dup 0)
7500 (and:DI (match_dup 1) (match_dup 2)))]
7501 {
7502 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7503 if (operands[2] == const0_rtx)
7504 {
7505 emit_move_insn (operands[0], const0_rtx);
7506 DONE;
7507 }
7508 if (operands[2] == constm1_rtx)
7509 {
7510 emit_move_insn (operands[0], operands[1]);
7511 DONE;
7512 }
7513 })
7515 (define_expand "builtin_zapnot"
7516 [(set (match_operand:DI 0 "register_operand" "")
7517 (and:DI (unspec:DI
7518 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7519 UNSPEC_ZAP)
7520 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7521 ""
7522 {
7523 if (GET_CODE (operands[2]) == CONST_INT)
7524 {
7525 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7527 if (mask == const0_rtx)
7528 {
7529 emit_move_insn (operands[0], const0_rtx);
7530 DONE;
7531 }
7532 if (mask == constm1_rtx)
7533 {
7534 emit_move_insn (operands[0], operands[1]);
7535 DONE;
7536 }
7538 operands[1] = force_reg (DImode, operands[1]);
7539 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7540 DONE;
7541 }
7543 operands[1] = force_reg (DImode, operands[1]);
7544 operands[2] = gen_lowpart (QImode, operands[2]);
7545 })
7547 (define_insn "*builtin_zapnot_1"
7548 [(set (match_operand:DI 0 "register_operand" "=r")
7549 (and:DI (unspec:DI
7550 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7551 UNSPEC_ZAP)
7552 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7553 ""
7554 "zapnot %r1,%2,%0"
7555 [(set_attr "type" "shift")])
7557 (define_insn "builtin_amask"
7558 [(set (match_operand:DI 0 "register_operand" "=r")
7559 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7560 UNSPEC_AMASK))]
7561 ""
7562 "amask %1,%0"
7563 [(set_attr "type" "ilog")])
7565 (define_insn "builtin_implver"
7566 [(set (match_operand:DI 0 "register_operand" "=r")
7567 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7568 ""
7569 "implver %0"
7570 [(set_attr "type" "ilog")])
7572 (define_insn "builtin_rpcc"
7573 [(set (match_operand:DI 0 "register_operand" "=r")
7574 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7575 ""
7576 "rpcc %0"
7577 [(set_attr "type" "ilog")])
7579 (define_expand "builtin_minub8"
7580 [(match_operand:DI 0 "register_operand" "")
7581 (match_operand:DI 1 "reg_or_0_operand" "")
7582 (match_operand:DI 2 "reg_or_0_operand" "")]
7583 "TARGET_MAX"
7584 {
7585 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7586 operands[1], operands[2]);
7587 DONE;
7588 })
7590 (define_expand "builtin_minsb8"
7591 [(match_operand:DI 0 "register_operand" "")
7592 (match_operand:DI 1 "reg_or_0_operand" "")
7593 (match_operand:DI 2 "reg_or_0_operand" "")]
7594 "TARGET_MAX"
7595 {
7596 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7597 operands[1], operands[2]);
7598 DONE;
7599 })
7601 (define_expand "builtin_minuw4"
7602 [(match_operand:DI 0 "register_operand" "")
7603 (match_operand:DI 1 "reg_or_0_operand" "")
7604 (match_operand:DI 2 "reg_or_0_operand" "")]
7605 "TARGET_MAX"
7606 {
7607 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7608 operands[1], operands[2]);
7609 DONE;
7610 })
7612 (define_expand "builtin_minsw4"
7613 [(match_operand:DI 0 "register_operand" "")
7614 (match_operand:DI 1 "reg_or_0_operand" "")
7615 (match_operand:DI 2 "reg_or_0_operand" "")]
7616 "TARGET_MAX"
7617 {
7618 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7619 operands[1], operands[2]);
7620 DONE;
7621 })
7623 (define_expand "builtin_maxub8"
7624 [(match_operand:DI 0 "register_operand" "")
7625 (match_operand:DI 1 "reg_or_0_operand" "")
7626 (match_operand:DI 2 "reg_or_0_operand" "")]
7627 "TARGET_MAX"
7628 {
7629 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7630 operands[1], operands[2]);
7631 DONE;
7632 })
7634 (define_expand "builtin_maxsb8"
7635 [(match_operand:DI 0 "register_operand" "")
7636 (match_operand:DI 1 "reg_or_0_operand" "")
7637 (match_operand:DI 2 "reg_or_0_operand" "")]
7638 "TARGET_MAX"
7639 {
7640 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7641 operands[1], operands[2]);
7642 DONE;
7643 })
7645 (define_expand "builtin_maxuw4"
7646 [(match_operand:DI 0 "register_operand" "")
7647 (match_operand:DI 1 "reg_or_0_operand" "")
7648 (match_operand:DI 2 "reg_or_0_operand" "")]
7649 "TARGET_MAX"
7650 {
7651 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7652 operands[1], operands[2]);
7653 DONE;
7654 })
7656 (define_expand "builtin_maxsw4"
7657 [(match_operand:DI 0 "register_operand" "")
7658 (match_operand:DI 1 "reg_or_0_operand" "")
7659 (match_operand:DI 2 "reg_or_0_operand" "")]
7660 "TARGET_MAX"
7661 {
7662 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7663 operands[1], operands[2]);
7664 DONE;
7665 })
7667 (define_insn "builtin_perr"
7668 [(set (match_operand:DI 0 "register_operand" "=r")
7669 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7670 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7671 UNSPEC_PERR))]
7672 "TARGET_MAX"
7673 "perr %r1,%r2,%0"
7674 [(set_attr "type" "mvi")])
7676 (define_expand "builtin_pklb"
7677 [(set (match_operand:DI 0 "register_operand" "")
7678 (vec_concat:V8QI
7679 (vec_concat:V4QI
7680 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7681 (match_dup 2))
7682 (match_dup 3)))]
7683 "TARGET_MAX"
7684 {
7685 operands[0] = gen_lowpart (V8QImode, operands[0]);
7686 operands[1] = gen_lowpart (V2SImode, operands[1]);
7687 operands[2] = CONST0_RTX (V2QImode);
7688 operands[3] = CONST0_RTX (V4QImode);
7689 })
7691 (define_insn "*pklb"
7692 [(set (match_operand:V8QI 0 "register_operand" "=r")
7693 (vec_concat:V8QI
7694 (vec_concat:V4QI
7695 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7696 (match_operand:V2QI 2 "const0_operand" ""))
7697 (match_operand:V4QI 3 "const0_operand" "")))]
7698 "TARGET_MAX"
7699 "pklb %r1,%0"
7700 [(set_attr "type" "mvi")])
7702 (define_expand "builtin_pkwb"
7703 [(set (match_operand:DI 0 "register_operand" "")
7704 (vec_concat:V8QI
7705 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7706 (match_dup 2)))]
7707 "TARGET_MAX"
7708 {
7709 operands[0] = gen_lowpart (V8QImode, operands[0]);
7710 operands[1] = gen_lowpart (V4HImode, operands[1]);
7711 operands[2] = CONST0_RTX (V4QImode);
7712 })
7714 (define_insn "*pkwb"
7715 [(set (match_operand:V8QI 0 "register_operand" "=r")
7716 (vec_concat:V8QI
7717 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7718 (match_operand:V4QI 2 "const0_operand" "")))]
7719 "TARGET_MAX"
7720 "pkwb %r1,%0"
7721 [(set_attr "type" "mvi")])
7723 (define_expand "builtin_unpkbl"
7724 [(set (match_operand:DI 0 "register_operand" "")
7725 (zero_extend:V2SI
7726 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7727 (parallel [(const_int 0) (const_int 1)]))))]
7728 "TARGET_MAX"
7729 {
7730 operands[0] = gen_lowpart (V2SImode, operands[0]);
7731 operands[1] = gen_lowpart (V8QImode, operands[1]);
7732 })
7734 (define_insn "*unpkbl"
7735 [(set (match_operand:V2SI 0 "register_operand" "=r")
7736 (zero_extend:V2SI
7737 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7738 (parallel [(const_int 0) (const_int 1)]))))]
7739 "TARGET_MAX"
7740 "unpkbl %r1,%0"
7741 [(set_attr "type" "mvi")])
7743 (define_expand "builtin_unpkbw"
7744 [(set (match_operand:DI 0 "register_operand" "")
7745 (zero_extend:V4HI
7746 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7747 (parallel [(const_int 0)
7748 (const_int 1)
7749 (const_int 2)
7750 (const_int 3)]))))]
7751 "TARGET_MAX"
7752 {
7753 operands[0] = gen_lowpart (V4HImode, operands[0]);
7754 operands[1] = gen_lowpart (V8QImode, operands[1]);
7755 })
7757 (define_insn "*unpkbw"
7758 [(set (match_operand:V4HI 0 "register_operand" "=r")
7759 (zero_extend:V4HI
7760 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7761 (parallel [(const_int 0)
7762 (const_int 1)
7763 (const_int 2)
7764 (const_int 3)]))))]
7765 "TARGET_MAX"
7766 "unpkbw %r1,%0"
7767 [(set_attr "type" "mvi")])
7768 \f
7769 (include "sync.md")
7770 \f
7771 ;; The call patterns are at the end of the file because their
7772 ;; wildcard operand0 interferes with nice recognition.
7774 (define_insn "*call_value_osf_1_er"
7775 [(set (match_operand 0 "" "")
7776 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7777 (match_operand 2 "" "")))
7778 (use (reg:DI 29))
7779 (clobber (reg:DI 26))]
7780 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7781 "@
7782 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7783 bsr $26,%1\t\t!samegp
7784 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7785 [(set_attr "type" "jsr")
7786 (set_attr "length" "12,*,16")])
7788 ;; We must use peep2 instead of a split because we need accurate life
7789 ;; information for $gp. Consider the case of { bar(); while (1); }.
7790 (define_peephole2
7791 [(parallel [(set (match_operand 0 "" "")
7792 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7793 (match_operand 2 "" "")))
7794 (use (reg:DI 29))
7795 (clobber (reg:DI 26))])]
7796 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7797 && ! samegp_function_operand (operands[1], Pmode)
7798 && (peep2_regno_dead_p (1, 29)
7799 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7800 [(parallel [(set (match_dup 0)
7801 (call (mem:DI (match_dup 3))
7802 (match_dup 2)))
7803 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7804 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7805 (use (match_dup 1))
7806 (use (match_dup 4))])]
7807 {
7808 if (CONSTANT_P (operands[1]))
7809 {
7810 operands[3] = gen_rtx_REG (Pmode, 27);
7811 operands[4] = GEN_INT (alpha_next_sequence_number++);
7812 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7813 operands[1], operands[4]));
7814 }
7815 else
7816 {
7817 operands[3] = operands[1];
7818 operands[1] = const0_rtx;
7819 operands[4] = const0_rtx;
7820 }
7821 })
7823 (define_peephole2
7824 [(parallel [(set (match_operand 0 "" "")
7825 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7826 (match_operand 2 "" "")))
7827 (use (reg:DI 29))
7828 (clobber (reg:DI 26))])]
7829 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7830 && ! samegp_function_operand (operands[1], Pmode)
7831 && ! (peep2_regno_dead_p (1, 29)
7832 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7833 [(parallel [(set (match_dup 0)
7834 (call (mem:DI (match_dup 3))
7835 (match_dup 2)))
7836 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7837 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7838 (use (match_dup 1))
7839 (use (match_dup 5))])
7840 (set (reg:DI 29)
7841 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7842 (set (reg:DI 29)
7843 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7844 {
7845 if (CONSTANT_P (operands[1]))
7846 {
7847 operands[3] = gen_rtx_REG (Pmode, 27);
7848 operands[5] = GEN_INT (alpha_next_sequence_number++);
7849 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7850 operands[1], operands[5]));
7851 }
7852 else
7853 {
7854 operands[3] = operands[1];
7855 operands[1] = const0_rtx;
7856 operands[5] = const0_rtx;
7857 }
7858 operands[4] = GEN_INT (alpha_next_sequence_number++);
7859 })
7861 ;; We add a blockage unspec_volatile to prevent insns from moving down
7862 ;; from above the call to in between the call and the ldah gpdisp.
7863 (define_insn "*call_value_osf_2_er"
7864 [(set (match_operand 0 "" "")
7865 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7866 (match_operand 2 "" "")))
7867 (set (reg:DI 26)
7868 (plus:DI (pc) (const_int 4)))
7869 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7870 (use (match_operand 3 "" ""))
7871 (use (match_operand 4 "" ""))]
7872 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7873 "jsr $26,(%1),%3%J4"
7874 [(set_attr "type" "jsr")
7875 (set_attr "cannot_copy" "true")])
7877 (define_insn "*call_value_osf_1_noreturn"
7878 [(set (match_operand 0 "" "")
7879 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7880 (match_operand 2 "" "")))
7881 (use (reg:DI 29))
7882 (clobber (reg:DI 26))]
7883 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7884 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7885 "@
7886 jsr $26,($27),0%+
7887 bsr $26,$%1..ng%+
7888 jsr $26,%1%+"
7889 [(set_attr "type" "jsr")
7890 (set_attr "length" "*,*,8")])
7892 (define_insn_and_split "call_value_osf_tlsgd"
7893 [(set (match_operand 0 "" "")
7894 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7895 (const_int 0)))
7896 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7897 (use (reg:DI 29))
7898 (clobber (reg:DI 26))]
7899 "HAVE_AS_TLS"
7900 "#"
7901 "&& reload_completed"
7902 [(set (match_dup 3)
7903 (unspec:DI [(match_dup 5)
7904 (match_dup 1)
7905 (match_dup 2)] UNSPEC_LITERAL))
7906 (parallel [(set (match_dup 0)
7907 (call (mem:DI (match_dup 3))
7908 (const_int 0)))
7909 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7910 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7911 (use (match_dup 1))
7912 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7913 (set (match_dup 5)
7914 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7915 (set (match_dup 5)
7916 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7917 {
7918 operands[3] = gen_rtx_REG (Pmode, 27);
7919 operands[4] = GEN_INT (alpha_next_sequence_number++);
7920 operands[5] = pic_offset_table_rtx;
7921 }
7922 [(set_attr "type" "multi")])
7924 (define_insn_and_split "call_value_osf_tlsldm"
7925 [(set (match_operand 0 "" "")
7926 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7927 (const_int 0)))
7928 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7929 (use (reg:DI 29))
7930 (clobber (reg:DI 26))]
7931 "HAVE_AS_TLS"
7932 "#"
7933 "&& reload_completed"
7934 [(set (match_dup 3)
7935 (unspec:DI [(match_dup 5)
7936 (match_dup 1)
7937 (match_dup 2)] UNSPEC_LITERAL))
7938 (parallel [(set (match_dup 0)
7939 (call (mem:DI (match_dup 3))
7940 (const_int 0)))
7941 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7942 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7943 (use (match_dup 1))
7944 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7945 (set (reg:DI 29)
7946 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7947 (set (reg:DI 29)
7948 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7949 {
7950 operands[3] = gen_rtx_REG (Pmode, 27);
7951 operands[4] = GEN_INT (alpha_next_sequence_number++);
7952 operands[5] = pic_offset_table_rtx;
7953 }
7954 [(set_attr "type" "multi")])
7956 (define_insn "*call_value_osf_1"
7957 [(set (match_operand 0 "" "")
7958 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7959 (match_operand 2 "" "")))
7960 (use (reg:DI 29))
7961 (clobber (reg:DI 26))]
7962 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7963 "@
7964 jsr $26,($27),0\;ldgp $29,0($26)
7965 bsr $26,$%1..ng
7966 jsr $26,%1\;ldgp $29,0($26)"
7967 [(set_attr "type" "jsr")
7968 (set_attr "length" "12,*,16")])
7970 (define_insn "*sibcall_value_osf_1_er"
7971 [(set (match_operand 0 "" "")
7972 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7973 (match_operand 2 "" "")))
7974 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7975 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7976 "@
7977 br $31,%1\t\t!samegp
7978 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7979 [(set_attr "type" "jsr")
7980 (set_attr "length" "*,8")])
7982 (define_insn "*sibcall_value_osf_1"
7983 [(set (match_operand 0 "" "")
7984 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7985 (match_operand 2 "" "")))
7986 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7987 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7988 "@
7989 br $31,$%1..ng
7990 lda $27,%1\;jmp $31,($27),%1"
7991 [(set_attr "type" "jsr")
7992 (set_attr "length" "*,8")])
7994 (define_insn "*call_value_nt_1"
7995 [(set (match_operand 0 "" "")
7996 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7997 (match_operand 2 "" "")))
7998 (clobber (reg:DI 26))]
7999 "TARGET_ABI_WINDOWS_NT"
8000 "@
8001 jsr $26,(%1)
8002 bsr $26,%1
8003 jsr $26,%1"
8004 [(set_attr "type" "jsr")
8005 (set_attr "length" "*,*,12")])
8007 ; GAS relies on the order and position of instructions output below in order
8008 ; to generate relocs for VMS link to potentially optimize the call.
8009 ; Please do not molest.
8010 (define_insn "*call_value_vms_1"
8011 [(set (match_operand 0 "" "")
8012 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8013 (match_operand 2 "" "")))
8014 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8015 (use (reg:DI 25))
8016 (use (reg:DI 26))
8017 (clobber (reg:DI 27))]
8018 "TARGET_ABI_OPEN_VMS"
8019 {
8020 switch (which_alternative)
8021 {
8022 case 0:
8023 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8024 case 1:
8025 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8026 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8027 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8028 default:
8029 gcc_unreachable ();
8030 }
8031 }
8032 [(set_attr "type" "jsr")
8033 (set_attr "length" "12,16")])
8035 (define_insn "*call_value_umk"
8036 [(set (match_operand 0 "" "")
8037 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8038 (match_operand 2 "" "")))
8039 (use (reg:DI 25))
8040 (clobber (reg:DI 26))]
8041 "TARGET_ABI_UNICOSMK"
8042 "jsr $26,(%1)"
8043 [(set_attr "type" "jsr")])