gcc/ChangeLog

   1 2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>
   2
   3         PR target/82420
   4         PR target/111279
   5         * calls.cc (emit_library_call_value_1): Pass valid TYPE
   6         to emit_push_insn.
   7         * expr.cc (emit_push_insn): Likewise.
   8
   9 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
  10
  11         * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
  12         correcction version of last change.
  13
  14 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
  15
  16         * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
  17         fix bugs in signature.
  18
  19 2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
  20             Richard Biener  <rguenther@suse.de>
  21
  22         PR rtl-optimization/111267
  23         * fwprop.cc (fwprop_propagation::profitabe_p): Rename
  24         profitable_p method to likely_profitable_p.
  25         (try_fwprop_subst_node): Update call to likely_profitable_p.
  26         Only bail-out early when !prop.likely_profitable_p for instructions
  27         that are not single sets.  When comparing costs, bail-out if the
  28         cost is unchanged and !prop.likely_profitable_p.
  29
  30 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
  31
  32         PR c++/90464
  33         * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
  34         isn't enabled by -Wunused unless -Wextra is provided, and that
  35         -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
  36         -Wunused doesn't enable -Wunused-* options documented as behaving
  37         otherwise, and list them explicitly.
  38
  39 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
  40
  41         PR c/109708
  42         * doc/invoke.texi (Warning Options): Fix broken example and
  43         clean up/reorganize the others.  Also describe what the short-form
  44         options mean.
  45
  46 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
  47
  48         PR c/102998
  49         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
  50         (Warning Options): Correct/edit discussion of -Warray-parameter
  51         to make the first example less confusing, and fill in missing info.
  52
  53 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
  54
  55         PR tree-optimization/113462
  56         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
  57         Handle rhs1 INTEGER_CST like SSA_NAME.
  58
  59 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
  60
  61         PR tree-optimization/113491
  62         * tree-switch-conversion.cc (switch_conversion::build_constructors):
  63         If elt.index has precision higher than sizetype, fold_convert it to
  64         sizetype.
  65         (switch_conversion::array_value_type): Return type if type is
  66         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
  67         (switch_conversion::build_arrays): Use unsigned_type_for rather than
  68         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
  69         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
  70         higher than sizetype, use sizetype as tidx type and fold_convert the
  71         subtraction to sizetype.
  72
  73 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
  74
  75         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
  76         (riscv_vector_mode_supported_any_target_p): Ditto.
  77
  78 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
  79
  80         PR target/110934
  81         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
  82         (TARGET_ZERO_CALL_USED_REGS): Define.
  83
  84 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
  85
  86         PR target/108640
  87         * config/m68k/m68k.cc (output_andsi3): Use QImode for
  88         address adjusted for 1-byte RMW access.
  89         (output_iorsi3): Likewise.
  90         (output_xorsi3): Likewise.
  91
  92 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
  93
  94         * doc/invoke.texi (RISC-V Options): Add list of supported
  95         extensions.
  96
  97 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
  98
  99         PR target/113495
 100         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
 101         (RVV_VUNDEF): Ditto.
 102         * config/riscv/riscv-vsetvl.cc: Add timevar.
 103
 104 2024-01-19  Richard Biener  <rguenther@suse.de>
 105
 106         PR debug/113488
 107         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
 108         an early DIE but there should be, do not pretend there is.
 109
 110 2024-01-19  Richard Biener  <rguenther@suse.de>
 111
 112         PR tree-optimization/113494
 113         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 114         Handle endless loop on exit.  Handle re-allocated PHI.
 115
 116 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
 117
 118         PR tree-optimization/113464
 119         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
 120         optimize loads into GIMPLE_ASM stmts.
 121
 122 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
 123
 124         PR tree-optimization/113463
 125         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
 126         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
 127         lhs.
 128
 129 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
 130
 131         PR tree-optimization/113459
 132         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
 133         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
 134         of SCALAR_INT_TYPE_MODE if type has BLKmode.
 135         (vn_reference_lookup_3): Likewise.  Formatting fix.
 136
 137 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
 138             Richard Biener  <rguenther@suse.de>
 139
 140         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
 141         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
 142         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
 143         but adjust_address also for BLKmode mode and MEM op0.
 144
 145 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
 146
 147         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
 148         extensions.
 149
 150 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 151
 152         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
 153
 154 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 155
 156         * common/config/riscv/riscv-common.cc
 157         (riscv_subset_list::parse_std_ext): Remove.
 158         (riscv_subset_list::parse_multiletter_ext): Remove.
 159         * config/riscv/riscv-subset.h
 160         (riscv_subset_list::parse_std_ext): Remove.
 161         (riscv_subset_list::parse_multiletter_ext): Remove.
 162
 163 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 164
 165         * common/config/riscv/riscv-common.cc
 166         (riscv_subset_list::parse_single_std_ext): New parameter.
 167         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
 168         (riscv_subset_list::parse_single_ext): Ditto.
 169         (riscv_subset_list::parse): Relax the order for the input of ISA
 170         string.
 171         * config/riscv/riscv-subset.h
 172         (riscv_subset_list::parse_single_std_ext): New parameter.
 173         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
 174         (riscv_subset_list::parse_single_ext): Ditto.
 175
 176 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 177
 178         * common/config/riscv/riscv-common.cc
 179         (riscv_subset_list::parse_base_ext): New.
 180         (riscv_subset_list::parse): Extract part of logic into
 181         riscv_subset_list::parse_base_ext.
 182         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
 183         New.
 184
 185 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
 186
 187         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
 188         sorry message.
 189
 190 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
 191
 192         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
 193         UNSPEC_CLMUL_VC.
 194
 195 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
 196
 197         PR c/110029
 198         * doc/extend.texi (Common Variable Attributes): Explain what
 199         happens when multiple variables with cleanups are in the same scope.
 200
 201 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 202
 203         PR ipa/108470
 204         * doc/extend.texi (Common Function Attributes): Document that
 205         noinline also disables some interprocedural optimizations and
 206         improve flow to the part about using inline asm instead to
 207         disable calls from being optimized away completely.  Remove the
 208         sentence that says noipa is mainly for internal compiler testing.
 209
 210 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
 211
 212         PR tree-optimization/69807
 213         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
 214
 215 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
 216
 217         PR target/108521
 218         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
 219         from x86 Windows Options.
 220
 221 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 222
 223         PR c/107942
 224         * doc/extend.texi (C Extensions): Add new section to menu.
 225         (Function Attributes):  Move dangling index entries to....
 226         (Const and Volatile Functions): New section.
 227
 228 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
 229
 230         PR middle-end/112684
 231         * toplev.cc (toplev::main): Don't ICE in
 232         -fdiagnostics-generate-patch when exiting after options,
 233         since no edit context will have been created.
 234
 235 2024-01-18  Richard Biener  <rguenther@suse.de>
 236
 237         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
 238         operands vector.
 239
 240 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 241
 242         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
 243         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
 244
 245 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 246             Jin Ma  <jinma@linux.alibaba.com>
 247             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 248             Christoph Müllner  <christoph.muellner@vrull.eu>
 249
 250         * config/riscv/thead.cc
 251         (th_asm_output_opcode): Rewrite some instructions.
 252
 253 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 254             Jin Ma  <jinma@linux.alibaba.com>
 255             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 256             Christoph Müllner  <christoph.muellner@vrull.eu>
 257
 258         * config/riscv/riscv.md (none,thv,rvv): New attribute.
 259         (no,yes): Add an attribute to disable alternative
 260         for xtheadvector or RVV1.0.
 261         * config/riscv/vector.md:
 262         Disable alternatives that destination register overlaps
 263         source register group for xtheadvector.
 264
 265 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 266             Jin Ma  <jinma@linux.alibaba.com>
 267             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 268             Christoph Müllner  <christoph.muellner@vrull.eu>
 269
 270         * config/riscv/riscv-vector-builtins-bases.cc
 271         (class th_loadstore_width): Define new builtin bases.
 272         (class th_extract): Define new builtin bases.
 273         (BASE): Define new builtin bases.
 274         * config/riscv/riscv-vector-builtins-bases.h:
 275         Define new builtin class.
 276         * config/riscv/riscv-vector-builtins-shapes.cc
 277         (struct th_loadstore_width_def): Define new builtin shapes.
 278         (struct th_indexed_loadstore_width_def):
 279         Define new builtin shapes.
 280         (struct th_extract_def): Define new builtin shapes.
 281         (SHAPE): Define new builtin shapes.
 282         * config/riscv/riscv-vector-builtins-shapes.h:
 283         Define new builtin shapes.
 284         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
 285         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
 286         * config/riscv/riscv-vector-builtins.h
 287         (enum required_ext): Add new XTheadVector member.
 288         (struct function_group_info): Likewise.
 289         * config/riscv/t-riscv:
 290         Add thead-vector-builtins-functions.def
 291         * config/riscv/thead-vector.md
 292         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
 293         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
 294         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
 295         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
 296         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
 297         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
 298         (@pred_th_extract<mode>): Likewise.
 299         (*pred_th_extract<mode>): Likewise.
 300         * config/riscv/thead-vector-builtins-functions.def: New file.
 301
 302 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 303             Jin Ma  <jinma@linux.alibaba.com>
 304             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 305             Christoph Müllner  <christoph.muellner@vrull.eu>
 306
 307         * config.gcc:  Add files for XTheadVector intrinsics.
 308         * config/riscv/autovec.md: Guard XTheadVector.
 309         * config/riscv/predicates.md: Disable immediate vl
 310         for XTheadVector.
 311         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
 312         Add pragma for XTheadVector.
 313         * config/riscv/riscv-string.cc (riscv_expand_block_move):
 314         Guard XTheadVector.
 315         * config/riscv/riscv-v.cc (vls_mode_valid_p):
 316         Avoid autovec.
 317         * config/riscv/riscv-vector-builtins-bases.cc:
 318         Do not normalize vsetvl instructions for XTheadVector.
 319         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
 320         New check type function.
 321         (build_one): Adjust for XTheadVector.
 322         * config/riscv/riscv-vector-switch.def (ENTRY):
 323         Disable fractional mode for the XTheadVector extension.
 324         (TUPLE_ENTRY): Likewise.
 325         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
 326         Guard XTheadVector.
 327         (riscv_preferred_simd_mode): Likewsie.
 328         (riscv_autovectorize_vector_modes): Likewise.
 329         (riscv_vector_mode_supported_any_target_p): Likewise.
 330         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
 331         * config/riscv/thead.cc (th_asm_output_opcode):
 332         Rewrite vsetvl instructions.
 333         * config/riscv/vector.md:
 334         Include thead-vector.md and change fractional LMUL
 335         into 1 for vbool.
 336         * config/riscv/riscv_th_vector.h: New file.
 337         * config/riscv/thead-vector.md: New file.
 338
 339 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 340             Jin Ma  <jinma@linux.alibaba.com>
 341             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 342             Christoph Müllner  <christoph.muellner@vrull.eu>
 343
 344         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
 345         Add new function to add assembler insn code prefix/suffix.
 346         (th_asm_output_opcode):
 347         Add Thead function to add assembler insn code prefix/suffix.
 348         * config/riscv/riscv.cc (riscv_asm_output_opcode):
 349         Implement function to add assembler insn code prefix/suffix.
 350         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
 351         Add new function to add assembler insn code prefix/suffix.
 352         * config/riscv/thead.cc (th_asm_output_opcode):
 353         Implement Thead function to add assembler insn code
 354         prefix/suffix.
 355
 356 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 357             Jin Ma  <jinma@linux.alibaba.com>
 358             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 359             Christoph Müllner  <christoph.muellner@vrull.eu>
 360
 361         * common/config/riscv/riscv-common.cc
 362         (riscv_subset_list::parse): Add new vendor extension.
 363         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
 364         Add test marco.
 365         * config/riscv/riscv.opt:  Add new mask.
 366
 367 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 368
 369         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
 370         to be conditional on macosx-version-min.
 371
 372 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 373
 374         * config/darwin.cc (darwin_objc1_section): Use the correct
 375         meta-data version for constant strings.
 376         (machopic_select_section): Assert if we fail to handle CFString
 377         sections as Obejctive-C meta-data or drectly.
 378
 379 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 380
 381         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
 382         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
 383         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
 384         versions when the object format is Mach-O.
 385
 386 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 387
 388         PR target/105522
 389         * config/darwin.cc (machopic_select_section): Handle C and C++
 390         CFStrings.
 391         (darwin_rename_builtins): Move this out of the CFString code.
 392         (darwin_libc_has_function): Likewise.
 393         (darwin_build_constant_cfstring): Create an anonymous var to
 394         hold each CFString.
 395         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
 396         CFstrings.
 397
 398 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
 399
 400         PR bootstrap/113445
 401         * haifa-sched.cc (dep_list_size): Make global.
 402         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
 403         * sched-int.h (dep_list_size): Declare.
 404
 405 2024-01-18  Martin Jambor  <mjambor@suse.cz>
 406
 407         PR tree-optimization/110422
 408         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
 409         gotos.
 410
 411 2024-01-18  Richard Biener  <rguenther@suse.de>
 412
 413         PR tree-optimization/113475
 414         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
 415         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
 416         (phi_analyzer::~phi_analyzer): Deallocate and free collected
 417         phi_grous.
 418         (phi_analyzer::process_phi): Record allocated phi_groups.
 419
 420 2024-01-18  Richard Biener  <rguenther@suse.de>
 421
 422         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
 423         storage for gvec_oprnds elements.
 424
 425 2024-01-18  Richard Biener  <rguenther@suse.de>
 426
 427         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
 428         prefer all later exits we can handle.
 429         (vect_analyze_loop_form): Free the allocated loop body.
 430         Adjust comments.
 431
 432 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 433
 434         * config/avr/avr-log.cc: Tabify.
 435
 436 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 437
 438         * config/riscv/autovec.md: Support vi variant.
 439
 440 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 441
 442         * config/avr/avr-devices.cc: Tabify.
 443
 444 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 445
 446         * config/avr/avr-c.cc: Tabify.
 447
 448 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 449
 450         * config/avr/driver-avr.cc: Tabify.
 451
 452 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 453
 454         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
 455
 456 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 457
 458         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
 459
 460 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 461
 462         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
 463         minline-strcmp, minline-strncmp, minline-strlen,
 464         -param=riscv-vector-abi): Remove Bool keywords.
 465
 466 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 467
 468         PR target/113122
 469         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
 470         support.  Add missing space after , in emitted assembly in some
 471         cases.  Formatting fixes.
 472
 473 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
 474
 475         * config/loongarch/loongarch.md (movsi_internal): Remove
 476         constraint z.
 477
 478 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 479
 480         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
 481         in the diagnostic, and capitalize the device name.
 482         (print_mcu): Generate specs such that:
 483         <*check_rodata_in_ram>: New.
 484         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
 485         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
 486         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
 487
 488 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 489
 490         PR other/113399
 491         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
 492         Common and Optimization.
 493
 494 2024-01-18  Richard Biener  <rguenther@suse.de>
 495
 496         PR tree-optimization/113431
 497         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
 498         When there is an invariant load we might not preserve
 499         scalar order.
 500
 501 2024-01-18  Richard Biener  <rguenther@suse.de>
 502
 503         PR tree-optimization/113374
 504         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
 505         * tree-vect-loop.cc (move_early_exit_stmts): Update
 506         virtual LC PHIs.
 507         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 508         Refactor.  Preserve virtual LC PHIs on all exits.
 509
 510 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
 511
 512         * config/loongarch/loongarch.cc (loongarch_split_symbol):
 513         Assign the '/u' attribute to the mem.
 514
 515 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 516
 517         PR middle-end/110847
 518         * doc/invoke.texi (Option Summary): Document negative forms of
 519         -Wtsan and -Wxor-used-as-pow.
 520         (Warning Options): Likewise.
 521
 522 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 523
 524         PR target/113429
 525         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
 526
 527 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 528
 529         * doc/extend.texi (Common Function Attributes): Re-alphabetize
 530         the table.
 531         (Common Variable Attributes): Likewise.
 532         (Common Type Attributes): Likewise.
 533
 534 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 535
 536         PR middle-end/111659
 537         * doc/extend.texi (Common Variable Attributes): Fix long lines
 538         in documentation of strict_flex_array + other minor copy-editing.
 539         Add a cross-reference to -Wstrict-flex-arrays.
 540         * doc/invoke.texi (Option Summary): Fix whitespace in tables
 541         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
 542         (C Dialect Options): Combine the docs for the two
 543         -fstrict-flex-arrays forms into a single entry.  Note this option
 544         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
 545         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
 546         Minor copy-editing.  Add cross references to the strict_flex_array
 547         attribute and -fstrict-flex-arrays option.  Add note that this
 548         option depends on -ftree-vrp.
 549
 550 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
 551
 552         PR target/113221
 553         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
 554         only allow REG operands instead of allowing all.
 555
 556 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
 557
 558         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
 559         Remove redundant checks in else condition for readablity.
 560         (earliest_fuse_vsetvl_info) Print iteration count in debug
 561         prints.
 562         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
 563         dump details in certain cases.
 564
 565 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
 566
 567         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
 568         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
 569         * config/riscv/riscv-vsetvl.cc
 570         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
 571         (pass_vsetvl::execute): Use vsetvl_strategy.
 572
 573 2024-01-17  Jan Hubicka  <jh@suse.cz>
 574
 575         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
 576         accidental hack reseting offset.
 577
 578 2024-01-17  Jan Hubicka  <jh@suse.cz>
 579
 580         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
 581         handling of X86_TUNE_AVOID_512FMA_CHAINS.
 582
 583 2024-01-17  Jan Hubicka  <jh@suse.cz>
 584             Jakub Jelinek  <jakub@redhat.com>
 585
 586         PR tree-optimization/110852
 587         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
 588         binary operations
 589         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
 590         PRED_COMBINED_VALUE_PREDICTIONS_PHI
 591         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
 592         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
 593
 594 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 595
 596         PR tree-optimization/113421
 597         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
 598         comment.
 599         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
 600         formatting.  Start at vop rather than cvop even if stmt is a store
 601         and needs_operand_addr.
 602
 603 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 604
 605         PR middle-end/113410
 606         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
 607         If access_nelts is integral with larger precision than sizetype,
 608         fold_convert it to sizetype.
 609
 610 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 611
 612         PR tree-optimization/113408
 613         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
 614         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
 615         to handle_cast.
 616
 617 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 618
 619         PR middle-end/113406
 620         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
 621         regardless of whether is_gimple_reg_type (restype) or not.
 622
 623 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 624
 625         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
 626         funcions -> functions, and use were instead of was.
 627         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
 628         and guaranteee -> guarantee.
 629         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
 630
 631 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 632
 633         PR middle-end/113409
 634         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
 635         INTEGER_TYPE.
 636         (omp_extract_for_data): Use build_bitint_type rather than
 637         build_nonstandard_integer_type if either iter_type or loop->v type
 638         is BITINT_TYPE.
 639         * omp-expand.cc (expand_omp_for_generic,
 640         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
 641         BITINT_TYPE like INTEGER_TYPE.
 642
 643 2024-01-17  Richard Biener  <rguenther@suse.de>
 644
 645         PR tree-optimization/113371
 646         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
 647         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
 648         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
 649         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
 650
 651 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
 652
 653         PR rtl-optimization/96388
 654         PR rtl-optimization/111554
 655         * sched-deps.cc (find_inc): Avoid exponential behavior.
 656
 657 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 658
 659         PR c/111693
 660         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
 661         from C++ Language Options to Warning Options.  Add entry for
 662         -Wuse-after-free.
 663         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
 664         from here....
 665         (Warning Options): ...to here.  Minor copy-editing to fix typo
 666         and grammar.
 667
 668 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
 669
 670         * config/mips/mips.cc (mips_compute_frame_info): If another
 671         register is used as global_pointer, mark $GP live false.
 672
 673 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 674
 675         PR target/112973
 676         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
 677         give the section a light copy-editing pass.
 678
 679 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 680
 681         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
 682         * config/aarch64/aarch64-tune.md: Regenerated.
 683         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
 684
 685 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 686
 687         PR target/112573
 688         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
 689         badly formed CONST expressions.
 690
 691 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
 692
 693         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
 694
 695 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
 696
 697         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
 698         * config/sparc/sync.md (membar_storeload): Turn into named insn
 699         and add GR712RC errata workaround.
 700         (membar_v8): Add GR712RC errata workaround.
 701
 702 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
 703
 704         * config/sparc/sync.md (*membar_storeload_leon3): Remove
 705         (*membar_storeload): Enable for LEON
 706
 707 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
 708
 709         PR tree-optimization/113372
 710         PR middle-end/90348
 711         PR middle-end/110115
 712         PR middle-end/111422
 713         * cfgexpand.cc (add_scope_conflicts_2): New function.
 714         (add_scope_conflicts_1): Use it.
 715
 716 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
 717
 718         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
 719         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
 720         * doc/avr-mmcu.texi: Regenerate.
 721
 722 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
 723
 724         PR tree-optimization/113091
 725         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
 726         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
 727         scalar use with new function.
 728         (vect_bb_slp_mark_live_stmts): New function as entry to existing
 729         overriden functions with same name.
 730         (vect_slp_analyze_operations): Call new entry function to mark
 731         live statements.
 732
 733 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 734
 735         PR target/113404
 736         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
 737         for RVV in big-endian mode.
 738
 739 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
 740
 741         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
 742         (riscv_pass_in_vector_p): Delete.
 743         (riscv_init_cumulative_args): Delete the checking.
 744         (riscv_get_arg_info): Delete the checking.
 745         (riscv_function_value): Delete the checking.
 746         * config/riscv/riscv.h: Delete the member for checking.
 747
 748 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
 749
 750         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
 751
 752 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
 753
 754         * config.gcc: Include riscv_bitmanip.h.
 755         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
 756         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
 757         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
 758         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
 759         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
 760         * config/riscv/riscv-ftypes.def (2): New ftypes.
 761         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
 762         (RISCV_BUILTIN_NO_PREFIX): Likewise.
 763         * config/riscv/riscv_bitmanip.h: New file.
 764
 765 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
 766
 767         * config.gcc: Include riscv_crypto.h.
 768         * config/riscv/riscv_crypto.h: New file.
 769
 770 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
 771
 772         PR middle-end/113354
 773         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
 774         in the insn if the corresponding operand does not require hard
 775         register anymore.
 776
 777 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
 778
 779         PR target/107201
 780         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
 781         * config/avr/driver-avr.cc (avr_no_devlib): New function.
 782         (avr_devicespecs_file): Use it to remove -nodevicelib from the
 783         options for cores only.
 784         * config/avr/avr-arch.h (avr_get_parch): New prototype.
 785         * config/avr/avr-devices.cc (avr_get_parch): New function.
 786
 787 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 788
 789         PR target/113247
 790         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
 791         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
 792         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
 793
 794 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 795
 796         PR target/113281
 797         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
 798         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
 799         * config/riscv/riscv-vector-costs.h: New function.
 800
 801 2024-01-15  Richard Biener  <rguenther@suse.de>
 802
 803         PR tree-optimization/113385
 804         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 805         First redirect, then split the exit edge.
 806
 807 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 808
 809         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
 810         Remove m_num_vector_iterations.
 811         * config/riscv/riscv-vector-costs.h: Ditto.
 812
 813 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
 814
 815         PR target/113156
 816         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
 817         (-mbranch-cost): Set "Optimization" flag.
 818
 819 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
 820
 821         PR tree-optimization/113370
 822         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
 823         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
 824         set it to just prec % limb_prec.
 825
 826 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 827
 828         PR target/113393
 829         * config/riscv/vector.md: Fix ternary attributes.
 830
 831 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
 832
 833         PR target/112944
 834         * configure.ac [target=avr]: Check availability of emulations
 835         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
 836         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
 837         * configure: Regenerate.
 838         * config.in: Regenerate.
 839         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
 840         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
 841         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
 842         * config/avr/avr-arch.h (enum avr_device_specific_features):
 843         Add AVR_ISA_FLMAP.
 844         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
 845         AVR_ISA_FLMAP.
 846         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
 847         (avr_set_core_architecture): Set avr_arch_index.
 848         (have_avrxmega2_flmap, have_avrxmega4_flmap)
 849         (have_avrxmega3_rodata_in_flash): Set new static const bool according
 850         to configure results.
 851         (avr_rodata_in_flash_p): New function using them.
 852         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
 853         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
 854         (avr_asm_named_section): Track avr_has_rodata_p.
 855         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
 856         and not avr_rodata_in_flash_p ().
 857         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
 858         (LINK_SPEC): Add %(link_rodata_in_ram).
 859         (LINK_ARCH_SPEC): Remove.
 860         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
 861         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
 862         const bool according to configure results.
 863         (diagnose_mrodata_in_ram): New function.
 864         (print_mcu): Generate specs with the following changes:
 865         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
 866         need to extend avr/specs.h each time we add a new bell or whistle.
 867         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
 868         -m[no-]rodata-in-ram.
 869         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
 870         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
 871         <*cpp>: Add %(cpp_rodata_in_ram).
 872         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
 873         requested.
 874         <*self_spec>: Add -mflmap or %<mflmap as needed.
 875
 876 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
 877
 878         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
 879         not the GPR iterator.  Adjust pattern name and mode attribute
 880         accordingly.
 881
 882 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
 883
 884         PR tree-optimization/113361
 885         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
 886         Fix up determination of the type for > limb_prec constants.
 887
 888 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 889
 890         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
 891         Add web-link to the avr-gcc wiki.
 892
 893 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 894
 895         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
 896         documentation for a version without argument, which is not supported.
 897
 898 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 899
 900         * config/arm/arm_neon.h
 901         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
 902         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
 903         (vld1_f16_x4, vld1_f32_x4): New.
 904         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
 905         (vld1_bf16_x4): New.
 906         (vld1q_types_x4): Updated to use vld1q_x4
 907         from arm_neon_builtins.def
 908         * config/arm/arm_neon_builtins.def
 909         (vld1_x4): Updated entries.
 910         (vld1q_x4): New entries, but comes from the old vld1_x4
 911         * config/arm/neon.md
 912         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
 913
 914 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 915
 916         * config/arm/arm_neon.h
 917         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
 918         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
 919         (vld1_f16_x3, vld1_f32_x3): New.
 920         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
 921         (vld1_bf16_x3): New.
 922         (vld1q_types_x3): Updated to use vld1q_x3 from
 923         arm_neon_builtins.def
 924         * config/arm/arm_neon_builtins.def
 925         (vld1_x3): Updated entries.
 926         (vld1q_x3): New entries, but comes from the old vld1_x2
 927         * config/arm/neon.md
 928         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
 929
 930 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 931
 932         * config/arm/arm_neon.h
 933         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
 934         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
 935         (vld1_f16_x2, vld1_f32_x2): New.
 936         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
 937         (vld1_bf16_x2): New.
 938         (vld1q_types_x2): Updated to use vld1q_x2 from
 939         arm_neon_builtins.def
 940         * config/arm/arm_neon_builtins.def
 941         (vld1_x2): Updated entries.
 942         (vld1q_x2): New entries, but comes from the old vld1_x2
 943         * config/arm/neon.md
 944         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 945         neon_vld1_x2<mode>.
 946
 947 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 948
 949         * config/arm/arm_neon.h
 950         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
 951         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
 952         (vst1q_f16_x4, vst1q_f32_x4): New.
 953         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
 954         (vst1q_bf16_x4): New.
 955         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
 956         * config/arm/neon.md
 957         (neon_vst1q_x4<mode>): New.
 958         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
 959         * config/arm/unspecs.md
 960         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
 961
 962 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 963
 964         * config/arm/arm_neon.h
 965         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
 966         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
 967         (vst1q_f16_x3, vst1q_f32_x3): New.
 968         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
 969         (vst1q_bf16_x3): New.
 970         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
 971         * config/arm/neon.md
 972         (neon_vst1q_x3<mode>): New.
 973         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
 974         * config/arm/unspecs.md
 975         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
 976
 977 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 978
 979         * config/arm/arm_neon.h
 980         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
 981         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
 982         (vst1q_f16_x2, vst1q_f32_x2): New.
 983         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
 984         (vst1q_bf16_x2): New.
 985         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
 986         * config/arm/neon.md
 987         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 988         neon_vst1_x2<mode>.
 989         * config/arm/iterators.md
 990         (VMEMX2): New mode iterator.
 991         (VMEMX2_q): New mode attribute.
 992
 993 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 994
 995         * config/arm/arm_neon.h
 996         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
 997         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
 998         (vst1_f16_x4, vst1_f32_x4): New.
 999         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
1000         (vst1_bf16_x4): New.
1001         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
1002         * config/arm/neon.md (vst1_x4<mode>): New.
1003
1004 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
1005
1006         * config/arm/arm_neon.h
1007         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
1008         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
1009         (vst1_f16_x3, vst1_f32_x3): New.
1010         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
1011         (vst1_bf16_x3): New.
1012         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
1013         * config/arm/neon.md (vst1_x3<mode>): New.
1014
1015 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
1016
1017         * config/arm/arm_neon.h
1018         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
1019         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
1020         (vst1_f16_x2, vst1_f32_x2): New.
1021         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
1022         (vst1_bf16_x2): New.
1023         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
1024         * config/arm/neon.md (vst1_x2<mode>): New.
1025
1026 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
1027
1028         * config/arm/arm_neon.h
1029         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
1030         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
1031         (vld1q_f16_x4, vld1q_f32_x4): New.
1032         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
1033         (vld1q_bf16_x4): New.
1034         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
1035         * config/arm/neon.md
1036         (neon_vld1_x4<mode>): New.
1037         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
1038         * config/arm/unspecs.md
1039         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
1040
1041 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
1042
1043         * config/arm/arm_neon.h
1044         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
1045         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
1046         (vld1q_f16_x3, vld1q_f32_x3): New.
1047         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
1048         (vld1q_bf16_x3): New.
1049         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
1050         * config/arm/neon.md
1051         (neon_vld1_x3<mode>): New.
1052         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
1053         * config/arm/unspecs.md
1054         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
1055
1056 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
1057
1058         * config/arm/arm_neon.h
1059         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
1060         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
1061         (vld1q_f16_x2, vld1q_f32_x2): New.
1062         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
1063         (vld1q_bf16_x2): New.
1064         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
1065         * config/arm/neon.md (vld1_x2<mode>): New.
1066
1067 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1068
1069         PR tree-optimization/113287
1070         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
1071
1072 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1073
1074         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
1075         * tree-vect-loop.cc (vect_transform_loop): Likewise.
1076
1077 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1078
1079         PR tree-optimization/113178
1080         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
1081         alternate exits.
1082
1083 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1084
1085         PR tree-optimization/113237
1086         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
1087         existing LCSSA variable for exit when all exits are early break.
1088
1089 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1090
1091         PR tree-optimization/113137
1092         PR tree-optimization/113136
1093         PR tree-optimization/113172
1094         PR tree-optimization/113178
1095         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1096         Maintain PHIs on inverted loops.
1097         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
1098         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
1099         latch.
1100         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
1101
1102 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
1103
1104         PR tree-optimization/113135
1105         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
1106         dependency analysis.
1107
1108 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
1109
1110         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
1111         diagnostics class member name for abort of error.
1112
1113 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
1114
1115         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
1116         format string to %s argument.
1117
1118 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
1119             Jakub Jelinek  <jakub@redhat.com>
1120
1121         PR middle-end/113182
1122         * varasm.cc (process_pending_assemble_externals,
1123         assemble_external_libcall): Use targetm.strip_name_encoding
1124         before calling get_identifier.
1125
1126 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1127
1128         PR target/113196
1129         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
1130         New member variable.
1131         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
1132         Declare.
1133         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
1134         * config/aarch64/aarch64-simd.md
1135         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
1136         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
1137         zip2 for zero-extends to...
1138         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
1139         instruction.  Fix big-endian handling.
1140         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
1141         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
1142         zip1 for zero-extends to...
1143         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
1144         Fix big-endian handling.
1145         (*aarch64_zip1_uxtl): New pattern.
1146         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
1147         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
1148         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
1149         (aarch64_gen_shareable_zero): Use it.
1150         (aarch64_split_simd_shift_p): New function.
1151
1152 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1153
1154         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
1155         (function_beg_insn): New macro.
1156         * function.cc (expand_function_start): Initialize function_beg_insn.
1157
1158 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1159
1160         PR target/112989
1161         * config/aarch64/aarch64-sve-builtins.h
1162         (function_builder::m_overload_names): Replace with...
1163         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
1164         new global.
1165         (add_overloaded_function): Update accordingly, using get_identifier
1166         to get a GGC-friendly record of the name.
1167
1168 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
1169
1170         PR target/112989
1171         * config/aarch64/aarch64-sve-builtins.def: Don't include
1172         aarch64-sve-builtins-sme.def.
1173         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
1174         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
1175         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
1176         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
1177         requires AARCH64_FL_SME2.
1178         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
1179         AARCH64_FL_SME adjustment here.
1180         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
1181         include SME intrinsics.
1182         (sme_function_groups): New array.
1183         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
1184         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
1185
1186 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1187
1188         PR target/113281
1189         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
1190         (struct cpu_vector_cost): Add regmove struct.
1191         (get_vector_costs): Export as global.
1192         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
1193         (costs::add_stmt_cost): Ditto.
1194         * config/riscv/riscv.cc (get_common_costs): Export global function.
1195
1196 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1197
1198         PR tree-optimization/113334
1199         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
1200         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
1201         to determine if number should be extended by all ones rather than zero
1202         extended.
1203
1204 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1205
1206         PR tree-optimization/113330
1207         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
1208         too large size.
1209
1210 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1211
1212         PR tree-optimization/113323
1213         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
1214         check for lhs being large/huge _BitInt not in m_names.
1215
1216 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1217
1218         PR tree-optimization/113316
1219         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
1220         uninitialized large/huge _BitInt arguments to calls.
1221
1222 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1223
1224         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
1225         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
1226         CEIL (TYPE_PRECISION (t), limb_prec).
1227         (bitint_large_huge::handle_cast): Likewise.
1228
1229 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
1230
1231         PR sanitizer/113284
1232         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1233         Use assemble_function_label_final () for Power ELF V1 ABI.
1234         * output.h (assemble_function_label_final): New function.
1235         * varasm.cc (assemble_function_label_raw): Use
1236         assemble_function_label_final ().
1237         (assemble_function_label_final): New function.
1238
1239 2024-01-12  Richard Biener  <rguenther@suse.de>
1240
1241         PR middle-end/113344
1242         * match.pd ((double)float CMP (double)float -> float CMP float):
1243         Perform result type check only for vectors.
1244         * fold-const.cc (fold_binary_loc): Likewise.
1245
1246 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
1247
1248         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
1249         (usdot_prod<mode>): Ditto.
1250         (sdot_prod<mode>): Ditto.
1251         (udot_prod<mode>): Ditto.
1252
1253 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
1254
1255         PR target/113288
1256         * config/i386/i386-c.cc (ix86_target_macros_internal):
1257         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
1258
1259 2024-01-12  Richard Biener  <rguenther@suse.de>
1260
1261         PR target/112280
1262         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
1263         Do not generate code when d.testing_p.
1264
1265 2024-01-12  liuhongt  <hongtao.liu@intel.com>
1266
1267         PR target/113039
1268         * doc/invoke.texi (fcf-protection=): Update documents.
1269
1270 2024-01-12  Pan Li  <pan2.li@intel.com>
1271
1272         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
1273         comments of predicate func riscv_v_ext_mode_p.
1274
1275 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
1276
1277         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
1278                         Modify ABI-name length of vfloat16m8_t
1279
1280 2024-01-12  Li Wei  <liwei@loongson.cn>
1281
1282         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
1283         Adjust.
1284
1285 2024-01-12  Li Wei  <liwei@loongson.cn>
1286
1287         * config/loongarch/loongarch.md (add<mode>3): Removed.
1288         (*addsi3): New.
1289         (addsi3): Ditto.
1290         (adddi3): Ditto.
1291         (*addsi3_extended): Removed.
1292         (addsi3_extended): New.
1293
1294 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
1295
1296         * config/riscv/thead.md: Add limits for splits.
1297
1298 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
1299
1300         PR middle-end/113322
1301         * expr.cc (do_store_flag): Don't try single bit tests with
1302         comparison on vector types.
1303
1304 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
1305
1306         PR tree-optimization/113301
1307         * match.pd (`1/x`): Delay signed case until late.
1308
1309 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
1310
1311         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
1312         and -msp8 to...
1313         (AVR Internal Options): ...this new @subsubsection.
1314
1315 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
1316
1317         PR rtl-optimization/112918
1318         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
1319         (in_class_p): Restrict condition for narrowing class in case of
1320         allow_all_reload_class_changes_p.
1321         (process_alt_operands): Try to match operand without and with
1322         narrowing reg class.  Discourage narrowing the class.  Finish insn
1323         matching only if there is no class narrowing.
1324         (curr_insn_transform): Pass true to in_class_p for reg operand win.
1325
1326 2024-01-11  Richard Biener  <rguenther@suse.de>
1327
1328         PR tree-optimization/112505
1329         * tree-vect-loop.cc (vectorizable_induction): Reject
1330         bit-precision induction.
1331
1332 2024-01-11  Richard Biener  <rguenther@suse.de>
1333
1334         PR tree-optimization/113126
1335         * match.pd ((double)float CMP (double)float -> float CMP float):
1336         Make sure the boolean type is the same.
1337         * fold-const.cc (fold_binary_loc): Likewise.
1338
1339 2024-01-11  Richard Biener  <rguenther@suse.de>
1340
1341         PR tree-optimization/112636
1342         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
1343         estimate_numbers_of_iterations before querying
1344         get_max_loop_iterations_int.
1345         (pass_ch::execute): Initialize SCEV and loops appropriately.
1346
1347 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
1348
1349         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
1350         Reduced Tiny.
1351         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
1352         * doc/extend.texi (AVR Variable Attributes): Improve documentation
1353         of io, io_low and address attributes.
1354         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
1355         * doc/avr-mmcu.texi: Rebuild.
1356
1357 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
1358
1359         PR target/113233
1360         * config/loongarch/genopts/loongarch.opt.in: Mark options with
1361         the "Save" property.
1362         * config/loongarch/loongarch.opt: Same.
1363         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
1364         according to la_target.
1365         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
1366         RESTORE} for the la_target structure; Rename option conditions
1367         to have the same "la_" prefix.
1368         * config/loongarch/loongarch.h: Same.
1369
1370 2024-01-11  Pan Li  <pan2.li@intel.com>
1371
1372         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
1373         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
1374
1375 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
1376
1377         PR target/113077
1378         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
1379         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
1380         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
1381         synthesize these if needed.  Update caller ...
1382         (ldp_bb_info::fuse_pair): ... here.
1383         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
1384         and either insn is frame-related.
1385         (find_trailing_add): Punt on frame-related insns.
1386         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
1387         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
1388
1389 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
1390
1391         * config/mips/mips.cc (mips_start_function_definition):
1392         Add ATTRIBUTE_UNUSED.
1393
1394 2024-01-11  Richard Biener  <rguenther@suse.de>
1395
1396         PR middle-end/112740
1397         * expr.cc (store_constructor): Check the integer vector
1398         mask has a single bit per element before using sign-extension
1399         to expand an uniform vector.
1400
1401 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1402
1403         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
1404         preempt VLS on unknown NITERS loop.
1405
1406 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
1407
1408         * doc/invoke.texi: Add -mevex512.
1409
1410 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
1411
1412         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
1413         (*nor<mode>3): Likewise.
1414         (nor<mode>3): Likewise.
1415         (*negsi2_extended): New template.
1416         (*<optab>si3_internal): Likewise.
1417         (*one_cmplsi2_internal): Likewise.
1418         (*norsi3_internal): Likewise.
1419         (*<optab>nsi_internal): Likewise.
1420         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
1421         modified bit operation to make the optimization work.
1422
1423 2024-01-11  liuhongt  <hongtao.liu@intel.com>
1424
1425         PR target/104401
1426         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
1427
1428 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1429
1430         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
1431         (get_vector_costs): Ditto.
1432         (riscv_builtin_vectorization_cost): Ditto.
1433
1434 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1435
1436         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
1437
1438 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
1439
1440         PR jit/111396
1441         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
1442         ipa_free_size_summary.
1443         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
1444         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
1445         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
1446         * ipa-prop.h (ipa_prop_cc_finalize): New function.
1447         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
1448         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
1449         ipa_sra_cc_finalize): New functions.
1450         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
1451         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
1452         ipa_sra_cc_finalize
1453         Include ipa-utils.h.
1454
1455 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
1456
1457         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
1458         (th_int_get_save_adjustment): Likewise.
1459         (th_int_adjust_cfi_prologue): Likewise.
1460         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
1461         (TH_INT_INTERRUPT): New macro.
1462         (riscv_expand_prologue): Add the processing of XTheadInt.
1463         (riscv_expand_epilogue): Likewise.
1464         * config/riscv/riscv.h (BITSET_P): Moved to here.
1465         * config/riscv/riscv.md: New unspec.
1466         * config/riscv/thead.cc (th_int_get_mask): New function.
1467         (th_int_get_save_adjustment): Likewise.
1468         (th_int_adjust_cfi_prologue): Likewise.
1469         * config/riscv/thead.md (th_int_push): New pattern.
1470         (th_int_pop): new pattern.
1471
1472 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1473
1474         PR tree-optimization/112468
1475         * doc/sourcebuild.texi: Document ifn_copysign.
1476         * match.pd: Only apply transformation if target supports the IFN.
1477
1478 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
1479
1480         PR tree-optimization/112581
1481         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
1482         mark_ssa_maybe_undefs.
1483         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
1484         variables can not be reassociated.
1485         (init_range_entry): Check for uninitialized variables too.
1486         (init_reassoc): Call mark_ssa_maybe_undefs.
1487
1488 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
1489
1490         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
1491         Also handle sign extension.
1492
1493 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
1494
1495         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
1496         to 0.
1497         (-mlate-ldp-fusion): Likewise.
1498
1499 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1500
1501         PR tree-optimization/113287
1502         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
1503         instead of using BRANCH_EDGE to determine true edge.
1504
1505 2024-01-10  Richard Biener  <rguenther@suse.de>
1506
1507         PR tree-optimization/113078
1508         * tree-vect-loop.cc (check_reduction_path): Canonicalize
1509         .COND_SUB to .COND_ADD.
1510
1511 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1512
1513         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
1514         Handle prefix mappings before calling find_opt.
1515         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
1516         "-fno-"-prefixed command-line option.
1517         * opts-common.cc (get_option_prefix_remapping): New.
1518         * opts.h (get_option_prefix_remapping): New decl.
1519
1520 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1521
1522         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
1523         m_urlifier to pp_output_formatted_text.
1524         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
1525         (obstack_append_string): New overload, taking a length.
1526         (urlify_quoted_string): Pass in an obstack ptr, rather than using
1527         that of the pp's buffer.  Generalize to handle trailing text in
1528         the buffer beyond the run of quoted text.
1529         (class quoting_info): New.
1530         (on_begin_quote): New.
1531         (on_end_quote): New.
1532         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
1533         it to calls to on_begin_quote and on_end_quote.
1534         (struct auto_obstack): New.
1535         (quoting_info::handle_phase_3): New.
1536         (pp_output_formatted_text): Add urlifier param.  Use it if there
1537         is deferred urlification.  Delete m_quotes.
1538         (selftest::pp_printf_with_urlifier): Pass urlifier to
1539         pp_output_formatted_text.
1540         (selftest::test_urlification): Update results for the existing
1541         case of quoted text stradding chunks; add more such test cases.
1542         * pretty-print.h (class quoting_info): New forward decl.
1543         (chunk_info::m_quotes): New field.
1544         (pp_output_formatted_text): Add optional urlifier param.
1545
1546 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1547
1548         * pretty-print.cc (selftest::test_pp_format): Add selftest
1549         coverage for numbered args.
1550
1551 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1552
1553         PR tree-optimization/113144
1554         PR tree-optimization/113145
1555         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1556         Update all BB that the original exits dominated.
1557
1558 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
1559
1560         * dwarf2out.cc (modified_type_die): Extend the support of reverse
1561         storage order to enumeration types if -gstrict-dwarf is not passed.
1562         (gen_enumeration_type_die): Add REVERSE parameter and generate the
1563         DIE immediately after the existing one if it is true.
1564         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
1565         call to gen_enumeration_type_die.
1566         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
1567         first recursive call as well as the call to gen_tagged_type_die.
1568         (gen_type_die): Add REVERSE parameter and pass it in the call to
1569         gen_type_die_with_usage.
1570
1571 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
1572
1573         PR tree-optimization/113120
1574         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
1575         with root->size TYPE_PRECISION don't build anything new.
1576         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
1577         rather than build_nonstandard_integer_type.
1578
1579 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
1580
1581         * config/i386/i386.opt: Adjust document.
1582         * doc/invoke.texi: Add description for
1583         -mapx-inline-asm-use-gpr32.
1584
1585 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1586
1587         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
1588         (avg<v_double_trunc>3_floor): New pattern.
1589         (<u>avg<v_double_trunc>3_ceil): Remove.
1590         (avg<v_double_trunc>3_ceil): New pattern.
1591         (uavg<mode>3_floor): Ditto.
1592         (uavg<mode>3_ceil): Ditto.
1593         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
1594         (enum insn_type): Ditto.
1595         * config/riscv/riscv-v.cc: Ditto.
1596         * config/riscv/vector-iterators.md (ashiftrt): Remove.
1597         (ASHIFTRT): Ditto.
1598         * config/riscv/vector.md: Add VLS modes.
1599
1600 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1601
1602         PR target/111480
1603         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
1604         (vczlsbb_char): New int attribute.
1605         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
1606         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
1607         (*vctzlsbb_zext_<mode>): Rename to ...
1608         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
1609         cover vclzlsbb.
1610
1611 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1612
1613         PR target/112606
1614         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
1615         of the last argument from altivec_register_operand to any_operand.  If
1616         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
1617         otherwise if it doesn't satisfy altivec_register_operand, force it to
1618         REG using copy_to_mode_reg.
1619
1620 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1621
1622         PR middle-end/113100
1623         * builtins.cc (expand_builtin_stack_address): Guard stack point
1624         adjustment with SPARC_STACK_BOUNDARY_HACK.
1625
1626 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1627
1628         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
1629         argument string definitions.
1630         * config/loongarch/loongarch-str.h: Same.
1631         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
1632         as aliases to -mexplicit-relocs={always,none}
1633         * config/loongarch/loongarch.opt: Regenerate.
1634         * config/loongarch/loongarch.cc: Same.
1635
1636 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1637
1638         * config/loongarch/loongarch-def.h: Define constants with
1639         enums instead of Macros.
1640
1641 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1642
1643         * config/loongarch/genopts/loongarch-strings: Rename.
1644         * config/loongarch/genopts/loongarch.opt.in: Same.
1645         * config/loongarch/loongarch-cpu.cc: Same.
1646         * config/loongarch/loongarch-def.cc: Same.
1647         * config/loongarch/loongarch-def.h: Same.
1648         * config/loongarch/loongarch-opts.cc: Same.
1649         * config/loongarch/loongarch-opts.h: Same.
1650         * config/loongarch/loongarch-str.h: Same.
1651         * config/loongarch/loongarch.opt: Same.
1652
1653 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1654
1655         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
1656         variable with the common la_ prefix.
1657         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
1658         flags as saved using TargetVariable.
1659         * config/loongarch/loongarch.opt: Same.
1660         * config/loongarch/loongarch-def.h: Define evolution_set to
1661         mark changes to the -march default.
1662         * config/loongarch/loongarch-driver.cc: Same.
1663         * config/loongarch/loongarch-opts.cc: Same.
1664         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
1665         conditions around the la_target structure.
1666         * config/loongarch/loongarch.cc: Same.
1667         * config/loongarch/loongarch.md: Same.
1668         * config/loongarch/loongarch-builtins.cc: Same.
1669         * config/loongarch/loongarch-c.cc: Same.
1670         * config/loongarch/lasx.md: Same.
1671         * config/loongarch/lsx.md: Same.
1672         * config/loongarch/sync.md: Same.
1673
1674 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
1675
1676         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
1677         no less.
1678
1679 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
1680
1681         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
1682
1683 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1684
1685         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
1686         restart_loop.
1687         (vectorizable_live_operation): Likewise.
1688
1689 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1690
1691         PR tree-optimization/113199
1692         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
1693         BIT_FIELD_REF.
1694
1695 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
1696
1697         PR target/113270
1698         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
1699         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
1700         GTY(()) declaration before the definition, drop GTY(()) drom the
1701         definition.
1702
1703 2024-01-09  Richard Biener  <rguenther@suse.de>
1704
1705         PR tree-optimization/113026
1706         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
1707         redundant and wrong niter bound setting.  Move niter
1708         bound adjustment down.
1709
1710 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1711
1712         PR middle-end/113163
1713         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
1714         Reject non-linear inductions that aren't supported.
1715
1716 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
1717
1718         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
1719         left shift implementation strategies.
1720         (arc_shift_info): Type for each entry of the shift strategy table.
1721         (arc_shift_context_idx): Return a integer value for each code
1722         generation context, used as an index
1723         (arc_ashl_alg): Table indexed by context and shifted bit count.
1724         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
1725         left shift implementation.
1726         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
1727         provide accurate costs, when optimizing for speed or size.
1728
1729 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1730
1731         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
1732
1733 2024-01-09  Julian Brown  <julian@codesourcery.com>
1734
1735         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
1736         processed out before gimplification.
1737         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
1738         * tree.def (OMP_ARRAY_SECTION): New tree code.
1739
1740 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
1741
1742         PR tree-optimization/113210
1743         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
1744         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
1745         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
1746         minus 1.
1747
1748 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
1749
1750         PR rtl-optimization/113140
1751         * reorg.cc (fill_slots_from_thread): If we are to branch after the
1752         last instruction of the function, create an end label.
1753
1754 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
1755             Hongtao Liu  <hongtao.liu@intel.com>
1756
1757         PR target/112992
1758         * config/i386/i386-expand.cc
1759         (ix86_convert_const_wide_int_to_broadcast): Allow call to
1760         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
1761         (ix86_broadcast_from_constant): Revert recent change; Return a
1762         suitable MEMREF independently of mode/target combinations.
1763         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
1764         to decide whether expansion is possible/preferrable.  Only try
1765         forcing DImode constants to memory (and trying again) if calling
1766         ix86_expand_vector_init_duplicate fails with an DImode immediate
1767         constant.
1768         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
1769         V4SImode for suitable immediate constants.
1770         <case E_V4DImode>: Try using V8SImode for suitable constants.
1771         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
1772         <case E_V2HImode>: Likewise.
1773         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
1774         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
1775         <label widen>: Handle CONT_INTs via simplify_binary_operation.
1776         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
1777         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
1778         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
1779         (ix86_expand_vector_init): Move try using a broadcast for all_same
1780         with ix86_expand_vector_init_duplicate before using constant pool.
1781
1782 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
1783
1784         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
1785
1786 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
1787
1788         * config/arm/arm-cpus.in (cortex-m52): New cpu.
1789         * config/arm/arm-tables.opt: Regenerate.
1790         * config/arm/arm-tune.md: Regenerate.
1791
1792 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
1793
1794         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
1795         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
1796         (@vec_concatz<mode>): New insn pattern.
1797         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
1798         Handle VALS containing two vectors.
1799
1800 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1801
1802         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
1803         (vundefined): Ditto.
1804
1805 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
1806
1807         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1808                                 Add new function_base for crypto vector.
1809         (class bitmanip): Ditto.
1810         (class b_reverse):Ditto.
1811         (class vwsll):   Ditto.
1812         (class clmul):   Ditto.
1813         (class vg_nhab):  Ditto.
1814         (class crypto_vv):Ditto.
1815         (class crypto_vi):Ditto.
1816         (class vaeskf2_vsm3c):Ditto.
1817         (class vsm3me): Ditto.
1818         (BASE): Add BASE declaration for crypto vector.
1819         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1820         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1821                                 Add crypto vector intrinsic definition.
1822         (vbrev): Ditto.
1823         (vclz): Ditto.
1824         (vctz): Ditto.
1825         (vwsll): Ditto.
1826         (vandn): Ditto.
1827         (vbrev8): Ditto.
1828         (vrev8): Ditto.
1829         (vrol): Ditto.
1830         (vror): Ditto.
1831         (vclmul): Ditto.
1832         (vclmulh): Ditto.
1833         (vghsh): Ditto.
1834         (vgmul): Ditto.
1835         (vaesef): Ditto.
1836         (vaesem): Ditto.
1837         (vaesdf): Ditto.
1838         (vaesdm): Ditto.
1839         (vaesz): Ditto.
1840         (vaeskf1): Ditto.
1841         (vaeskf2): Ditto.
1842         (vsha2ms): Ditto.
1843         (vsha2ch): Ditto.
1844         (vsha2cl): Ditto.
1845         (vsm4k): Ditto.
1846         (vsm4r): Ditto.
1847         (vsm3me): Ditto.
1848         (vsm3c): Ditto.
1849         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1850                                 Add new function_shape for crypto vector.
1851         (struct crypto_vi_def): Ditto.
1852         (struct crypto_vv_no_op_type_def): Ditto.
1853         (SHAPE): Add SHAPE declaration of crypto vector.
1854         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1855         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1856                                 Add new data type for crypto vector.
1857         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1858         (vuint32mf2_t): Ditto.
1859         (vuint32m1_t): Ditto.
1860         (vuint32m2_t): Ditto.
1861         (vuint32m4_t): Ditto.
1862         (vuint32m8_t): Ditto.
1863         (vuint64m1_t): Ditto.
1864         (vuint64m2_t): Ditto.
1865         (vuint64m4_t): Ditto.
1866         (vuint64m8_t): Ditto.
1867         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1868                                 Add new data struct for crypto vector.
1869         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1870         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1871         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1872
1873 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
1874
1875         PR sanitizer/113251
1876         * varasm.cc (assemble_function_label_raw): Do not call
1877         asan_function_start () without the current function.
1878
1879 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1880
1881         PR target/113225
1882         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
1883         extern and kernel_helper attributed function decls.
1884
1885 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1886
1887         * btfout.cc (output_btf_strs): Changed.
1888
1889 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1890
1891         * config/gcn/mkoffload.cc (main): Handle gfx1100
1892         when setting the default XNACK.
1893
1894 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1895
1896         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
1897         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
1898         (ASM_SPEC): Handle gfx1100.
1899         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
1900         (enum gcn_isa): Add ISA_RDNA3.
1901         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
1902         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1903         * config/gcn/gcn.cc (gcn_option_override,
1904         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
1905         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
1906         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1907         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
1908         with gfx1100.
1909         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
1910         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
1911         __gfx1100__.
1912         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1913         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
1914         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
1915         (isa_has_combined_avgprs, main): Handle gfx1100.
1916         * config/gcn/t-omp-device (isa): Add gfx1100.
1917
1918 2024-01-08  Richard Biener  <rguenther@suse.de>
1919
1920         * doc/invoke.texi (-mmovbe): Clarify.
1921
1922 2024-01-08  Richard Biener  <rguenther@suse.de>
1923
1924         PR tree-optimization/113026
1925         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
1926         Avoid an epilog in more cases.
1927         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
1928         epilogues niter upper bounds and estimates.
1929
1930 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1931
1932         PR tree-optimization/113228
1933         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
1934
1935 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1936
1937         PR tree-optimization/113120
1938         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
1939         large _BitInt zero INTEGER_CST PHI argument.
1940
1941 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1942
1943         PR tree-optimization/113119
1944         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
1945         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
1946         is before REALPART_EXPR.
1947
1948 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
1949
1950         PR target/112952
1951         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
1952         range when diagnosing attribute "io" and "io_low" are out of range.
1953         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
1954         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
1955         in contexts other than static storage.
1956         (avr_asm_output_aligned_decl_common): Move output of decls with
1957         attribute "address", "io", and "io_low" to...
1958         (avr_output_addr_attrib): ...this new function.
1959         (avr_asm_asm_output_aligned_bss): Remove output for decls with
1960         attribute "address", "io", and "io_low".
1961         (avr_encode_section_info): Rectify handling of decls with attribute
1962         "address", "io", and "io_low".
1963
1964 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1965
1966         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
1967         (elf_flags): Remove XNACK from the default value.
1968         (main): Set a default XNACK according to the arch.
1969
1970 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1971
1972         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
1973         (process_asm): Don't count avgprs.
1974
1975 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
1976
1977         * config/i386/i386.opt: Add supported sub-features.
1978         * doc/extend.texi: Add description for target attribute.
1979
1980 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
1981
1982         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
1983
1984 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
1985             Uros Bizjak  <ubizjak@gmail.com>
1986
1987         PR target/113231
1988         * config/i386/i386-features.cc (compute_convert_gain): Include
1989         the overhead of explicit load and store (movd) instructions when
1990         converting non-store scalar operations with memory destinations.
1991         Various indentation whitespace fixes.
1992
1993 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
1994
1995         * config/arm/neon.md (cbranch<mode>4): New.
1996
1997 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1998
1999         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
2000
2001 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
2002
2003         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
2004
2005 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2006
2007         PR target/113248
2008         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
2009         Update the MAX_SEW.
2010
2011 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2012
2013         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
2014         (variable_vectorized_p): Teach loop invariant.
2015         (has_unexpected_spills_p): Ditto.
2016
2017 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2018
2019         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
2020         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
2021         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
2022
2023 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
2024
2025         PR target/113104
2026         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
2027         (aarch64-vect-compare-costs): ...this.
2028         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
2029         Replace with...
2030         (-param=aarch64-vect-compare-costs=): ...this new param.
2031         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
2032         Don't disable it when vectorizing for Advanced SIMD only.
2033         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
2034         whenever aarch64_vect_compare_costs is true.
2035
2036 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
2037
2038         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
2039         Modify the method of determining the memory offset of [x]vld/[x]vst.
2040         (lasx_mxst_<lasxfmt_f>): Likewise.
2041         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
2042         (loongarch_address_insns): Likewise.
2043         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
2044         (lsx_st_<lsxfmt_f>): Likewise.
2045         * config/loongarch/predicates.md (aq10b_operand): Likewise.
2046         (aq10h_operand): Likewise.
2047         (aq10w_operand): Likewise.
2048         (aq10d_operand): Likewise.
2049
2050 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
2051
2052         PR target/113217
2053         * config/aarch64/aarch64-ldp-fusion.cc
2054         (ldp_bb_info::try_fuse_pair): If the second access can throw,
2055         narrow the move range to exactly that insn.
2056
2057 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
2058
2059         * asan.cc (asan_function_start): Drop switch_to_section ().
2060         (asan_emit_stack_protection): Set .LASANPC alignment.
2061         * config/i386/i386.cc: Use assemble_function_label_raw ()
2062         instead of ASM_OUTPUT_LABEL ().
2063         * config/s390/s390.cc (s390_asm_output_function_label):
2064         Likewise.
2065         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
2066         * final.cc (final_start_function_1): Drop
2067         asan_function_start ().
2068         * output.h (assemble_function_label_raw): New function.
2069         * varasm.cc (assemble_function_label_raw): Likewise.
2070
2071 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
2072
2073         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
2074         Use ASM_OUTPUT_FUNCTION_LABEL ().
2075         * config/alpha/alpha.cc (alpha_start_function): Likewise.
2076         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2077         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
2078         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2079         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2080         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
2081         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
2082         * config/ia64/ia64.cc (ia64_start_function): Likewise.
2083         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
2084         Likewise.
2085         * config/microblaze/microblaze.cc (microblaze_function_prologue):
2086         Likewise.
2087         * config/mips/mips.cc (mips_start_unique_function): Return the
2088         tree.
2089         (mips_start_function_definition): Use
2090         ASM_OUTPUT_FUNCTION_LABEL ().
2091         (mips_finish_stub): Pass the tree to
2092         mips_start_function_definition ().
2093         (mips16_build_function_stub): Likewise.
2094         (mips16_build_call_stub): Likewise.
2095         (mips_output_function_prologue): Likewise.
2096         * config/pa/pa.cc (pa_output_function_label): Use
2097         ASM_OUTPUT_FUNCTION_LABEL ().
2098         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
2099         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
2100         Likewise.
2101         (rs6000_xcoff_declare_function_name): Likewise.
2102
2103 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
2104
2105         PR tree-optimization/113201
2106         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
2107         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
2108
2109 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
2110
2111         PR tree-optimization/90693
2112         * tree-ssa-math-opts.cc (match_single_bit_test): If
2113         tree_expr_nonzero_p (arg), remember it in the second argument to
2114         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
2115         arg ^ (arg - 1) > arg - 1.
2116         * internal-fn.cc (expand_POPCOUNT): If second argument to
2117         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
2118         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
2119
2120 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
2121
2122         * config/riscv/riscv-v.cc (expand_load_store):
2123         Remove `value`.
2124         (expand_cond_len_op): Ditto.
2125         (expand_gather_scatter): Ditto.
2126         (expand_lanes_load_store): Ditto.
2127         (expand_fold_extract_last): Ditto.
2128
2129 2024-01-05  Pan Li  <pan2.li@intel.com>
2130
2131         Revert:
2132         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
2133
2134         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2135                                 Add new function_base for crypto vector.
2136         (class bitmanip): Ditto.
2137         (class b_reverse):Ditto.
2138         (class vwsll):   Ditto.
2139         (class clmul):   Ditto.
2140         (class vg_nhab):  Ditto.
2141         (class crypto_vv):Ditto.
2142         (class crypto_vi):Ditto.
2143         (class vaeskf2_vsm3c):Ditto.
2144         (class vsm3me): Ditto.
2145         (BASE): Add BASE declaration for crypto vector.
2146         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2147         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2148                                 Add crypto vector intrinsic definition.
2149         (vbrev): Ditto.
2150         (vclz): Ditto.
2151         (vctz): Ditto.
2152         (vwsll): Ditto.
2153         (vandn): Ditto.
2154         (vbrev8): Ditto.
2155         (vrev8): Ditto.
2156         (vrol): Ditto.
2157         (vror): Ditto.
2158         (vclmul): Ditto.
2159         (vclmulh): Ditto.
2160         (vghsh): Ditto.
2161         (vgmul): Ditto.
2162         (vaesef): Ditto.
2163         (vaesem): Ditto.
2164         (vaesdf): Ditto.
2165         (vaesdm): Ditto.
2166         (vaesz): Ditto.
2167         (vaeskf1): Ditto.
2168         (vaeskf2): Ditto.
2169         (vsha2ms): Ditto.
2170         (vsha2ch): Ditto.
2171         (vsha2cl): Ditto.
2172         (vsm4k): Ditto.
2173         (vsm4r): Ditto.
2174         (vsm3me): Ditto.
2175         (vsm3c): Ditto.
2176         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2177                                 Add new function_shape for crypto vector.
2178         (struct crypto_vi_def): Ditto.
2179         (struct crypto_vv_no_op_type_def): Ditto.
2180         (SHAPE): Add SHAPE declaration of crypto vector.
2181         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2182         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2183                                 Add new data type for crypto vector.
2184         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2185         (vuint32mf2_t): Ditto.
2186         (vuint32m1_t): Ditto.
2187         (vuint32m2_t): Ditto.
2188         (vuint32m4_t): Ditto.
2189         (vuint32m8_t): Ditto.
2190         (vuint64m1_t): Ditto.
2191         (vuint64m2_t): Ditto.
2192         (vuint64m4_t): Ditto.
2193         (vuint64m8_t): Ditto.
2194         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2195                                 Add new data struct for crypto vector.
2196         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2197         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2198         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2199
2200 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
2201
2202         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2203                                 Add new function_base for crypto vector.
2204         (class bitmanip): Ditto.
2205         (class b_reverse):Ditto.
2206         (class vwsll):   Ditto.
2207         (class clmul):   Ditto.
2208         (class vg_nhab):  Ditto.
2209         (class crypto_vv):Ditto.
2210         (class crypto_vi):Ditto.
2211         (class vaeskf2_vsm3c):Ditto.
2212         (class vsm3me): Ditto.
2213         (BASE): Add BASE declaration for crypto vector.
2214         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2215         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2216                                 Add crypto vector intrinsic definition.
2217         (vbrev): Ditto.
2218         (vclz): Ditto.
2219         (vctz): Ditto.
2220         (vwsll): Ditto.
2221         (vandn): Ditto.
2222         (vbrev8): Ditto.
2223         (vrev8): Ditto.
2224         (vrol): Ditto.
2225         (vror): Ditto.
2226         (vclmul): Ditto.
2227         (vclmulh): Ditto.
2228         (vghsh): Ditto.
2229         (vgmul): Ditto.
2230         (vaesef): Ditto.
2231         (vaesem): Ditto.
2232         (vaesdf): Ditto.
2233         (vaesdm): Ditto.
2234         (vaesz): Ditto.
2235         (vaeskf1): Ditto.
2236         (vaeskf2): Ditto.
2237         (vsha2ms): Ditto.
2238         (vsha2ch): Ditto.
2239         (vsha2cl): Ditto.
2240         (vsm4k): Ditto.
2241         (vsm4r): Ditto.
2242         (vsm3me): Ditto.
2243         (vsm3c): Ditto.
2244         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2245                                 Add new function_shape for crypto vector.
2246         (struct crypto_vi_def): Ditto.
2247         (struct crypto_vv_no_op_type_def): Ditto.
2248         (SHAPE): Add SHAPE declaration of crypto vector.
2249         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2250         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2251                                 Add new data type for crypto vector.
2252         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2253         (vuint32mf2_t): Ditto.
2254         (vuint32m1_t): Ditto.
2255         (vuint32m2_t): Ditto.
2256         (vuint32m4_t): Ditto.
2257         (vuint32m8_t): Ditto.
2258         (vuint64m1_t): Ditto.
2259         (vuint64m2_t): Ditto.
2260         (vuint64m4_t): Ditto.
2261         (vuint64m8_t): Ditto.
2262         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2263                                 Add new data struct for crypto vector.
2264         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2265         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2266         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2267
2268 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2269
2270         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2271
2272 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
2273
2274         PR tree-optimization/113186
2275         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
2276         Match `^` with the `==` for 1bit integral types.
2277         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
2278         integral types.
2279
2280 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2281
2282         * toplev.cc (general_init): Pass lang_mask to urlifier.
2283
2284 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2285
2286         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
2287         param.
2288         (diagnostic_context::make_option_url): Update for lang_mask param.
2289         * gcc-urlifier.cc: Include "opts.h" and "options.h".
2290         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
2291         (gcc_urlifier::m_lang_mask): New field.
2292         (doc_urls): Make static.
2293         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
2294         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2295         Look for an option by name before trying a binary search in
2296         doc_urls.
2297         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2298         (gcc_urlifier::get_url_suffix_for_option): New.
2299         (make_gcc_urlifier): Add lang_mask param.
2300         (selftest::gcc_urlifier_cc_tests): Update for above changes.
2301         Verify that a URL is found for "-fpack-struct".
2302         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
2303         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
2304         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
2305         to make_gcc_urlifier.
2306         * opts-diagnostic.h (get_option_url): Add lang_mask param.
2307         * opts.cc (get_option_html_page): Remove special-casing for
2308         analyzer and LTO.
2309         (get_option_url_suffix): New.
2310         (get_option_url): Reimplement.
2311         (selftest::test_get_option_html_page): Rename to...
2312         (selftest::test_get_option_url_suffix): ...this and update for
2313         above changes.
2314         (selftest::opts_cc_tests): Update for renaming.
2315         * opts.h: Include "rich-location.h".
2316         (get_option_url_suffix): New decl.
2317
2318 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2319
2320         * Makefile.in (ALL_OPT_URL_FILES): New.
2321         (GCC_OBJS): Add options-urls.o.
2322         (OBJS): Likewise.
2323         (OBJS-libcommon): Likewise.
2324         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
2325         inputs to opt-gather.awk.
2326         (options-urls.cc): New Makefile target.
2327         * opt-functions.awk (url_suffix): New function.
2328         (lang_url_suffix): New function.
2329         * options-urls-cc-gen.awk: New file.
2330         * opts.h (get_opt_url_suffix): New decl.
2331
2332 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2333
2334         * params.opt.urls: New file, autogenerated by
2335         regenerate-opt-urls.py.
2336
2337 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2338
2339         * common.opt.urls: New file, autogenerated by
2340         regenerate-opt-urls.py.
2341         * config/aarch64/aarch64.opt.urls: Likewise.
2342         * config/alpha/alpha.opt.urls: Likewise.
2343         * config/alpha/elf.opt.urls: Likewise.
2344         * config/arc/arc-tables.opt.urls: Likewise.
2345         * config/arc/arc.opt.urls: Likewise.
2346         * config/arm/arm-tables.opt.urls: Likewise.
2347         * config/arm/arm.opt.urls: Likewise.
2348         * config/arm/vxworks.opt.urls: Likewise.
2349         * config/avr/avr.opt.urls: Likewise.
2350         * config/bpf/bpf.opt.urls: Likewise.
2351         * config/c6x/c6x-tables.opt.urls: Likewise.
2352         * config/c6x/c6x.opt.urls: Likewise.
2353         * config/cris/cris.opt.urls: Likewise.
2354         * config/cris/elf.opt.urls: Likewise.
2355         * config/csky/csky.opt.urls: Likewise.
2356         * config/csky/csky_tables.opt.urls: Likewise.
2357         * config/darwin.opt.urls: Likewise.
2358         * config/dragonfly.opt.urls: Likewise.
2359         * config/epiphany/epiphany.opt.urls: Likewise.
2360         * config/fr30/fr30.opt.urls: Likewise.
2361         * config/freebsd.opt.urls: Likewise.
2362         * config/frv/frv.opt.urls: Likewise.
2363         * config/ft32/ft32.opt.urls: Likewise.
2364         * config/fused-madd.opt.urls: Likewise.
2365         * config/g.opt.urls: Likewise.
2366         * config/gcn/gcn.opt.urls: Likewise.
2367         * config/gnu-user.opt.urls: Likewise.
2368         * config/h8300/h8300.opt.urls: Likewise.
2369         * config/hpux11.opt.urls: Likewise.
2370         * config/i386/cygming.opt.urls: Likewise.
2371         * config/i386/cygwin.opt.urls: Likewise.
2372         * config/i386/djgpp.opt.urls: Likewise.
2373         * config/i386/i386.opt.urls: Likewise.
2374         * config/i386/mingw-w64.opt.urls: Likewise.
2375         * config/i386/mingw.opt.urls: Likewise.
2376         * config/i386/nto.opt.urls: Likewise.
2377         * config/ia64/ia64.opt.urls: Likewise.
2378         * config/ia64/ilp32.opt.urls: Likewise.
2379         * config/ia64/vms.opt.urls: Likewise.
2380         * config/iq2000/iq2000.opt.urls: Likewise.
2381         * config/linux-android.opt.urls: Likewise.
2382         * config/linux.opt.urls: Likewise.
2383         * config/lm32/lm32.opt.urls: Likewise.
2384         * config/loongarch/loongarch.opt.urls: Likewise.
2385         * config/lynx.opt.urls: Likewise.
2386         * config/m32c/m32c.opt.urls: Likewise.
2387         * config/m32r/m32r.opt.urls: Likewise.
2388         * config/m68k/ieee.opt.urls: Likewise.
2389         * config/m68k/m68k-tables.opt.urls: Likewise.
2390         * config/m68k/m68k.opt.urls: Likewise.
2391         * config/m68k/uclinux.opt.urls: Likewise.
2392         * config/mcore/mcore.opt.urls: Likewise.
2393         * config/microblaze/microblaze.opt.urls: Likewise.
2394         * config/mips/mips-tables.opt.urls: Likewise.
2395         * config/mips/mips.opt.urls: Likewise.
2396         * config/mips/sde.opt.urls: Likewise.
2397         * config/mmix/mmix.opt.urls: Likewise.
2398         * config/mn10300/mn10300.opt.urls: Likewise.
2399         * config/moxie/moxie.opt.urls: Likewise.
2400         * config/msp430/msp430.opt.urls: Likewise.
2401         * config/nds32/nds32-elf.opt.urls: Likewise.
2402         * config/nds32/nds32-linux.opt.urls: Likewise.
2403         * config/nds32/nds32.opt.urls: Likewise.
2404         * config/netbsd-elf.opt.urls: Likewise.
2405         * config/netbsd.opt.urls: Likewise.
2406         * config/nios2/elf.opt.urls: Likewise.
2407         * config/nios2/nios2.opt.urls: Likewise.
2408         * config/nvptx/nvptx-gen.opt.urls: Likewise.
2409         * config/nvptx/nvptx.opt.urls: Likewise.
2410         * config/openbsd.opt.urls: Likewise.
2411         * config/or1k/elf.opt.urls: Likewise.
2412         * config/or1k/or1k.opt.urls: Likewise.
2413         * config/pa/pa-hpux.opt.urls: Likewise.
2414         * config/pa/pa-hpux1010.opt.urls: Likewise.
2415         * config/pa/pa-hpux1111.opt.urls: Likewise.
2416         * config/pa/pa-hpux1131.opt.urls: Likewise.
2417         * config/pa/pa.opt.urls: Likewise.
2418         * config/pa/pa64-hpux.opt.urls: Likewise.
2419         * config/pdp11/pdp11.opt.urls: Likewise.
2420         * config/pru/pru.opt.urls: Likewise.
2421         * config/riscv/riscv.opt.urls: Likewise.
2422         * config/rl78/rl78.opt.urls: Likewise.
2423         * config/rpath.opt.urls: Likewise.
2424         * config/rs6000/476.opt.urls: Likewise.
2425         * config/rs6000/aix64.opt.urls: Likewise.
2426         * config/rs6000/darwin.opt.urls: Likewise.
2427         * config/rs6000/linux64.opt.urls: Likewise.
2428         * config/rs6000/rs6000-tables.opt.urls: Likewise.
2429         * config/rs6000/rs6000.opt.urls: Likewise.
2430         * config/rs6000/sysv4.opt.urls: Likewise.
2431         * config/rtems.opt.urls: Likewise.
2432         * config/rx/elf.opt.urls: Likewise.
2433         * config/rx/rx.opt.urls: Likewise.
2434         * config/s390/s390.opt.urls: Likewise.
2435         * config/s390/tpf.opt.urls: Likewise.
2436         * config/sh/sh.opt.urls: Likewise.
2437         * config/sh/superh.opt.urls: Likewise.
2438         * config/sol2.opt.urls: Likewise.
2439         * config/sparc/long-double-switch.opt.urls: Likewise.
2440         * config/sparc/sparc.opt.urls: Likewise.
2441         * config/stormy16/stormy16.opt.urls: Likewise.
2442         * config/v850/v850.opt.urls: Likewise.
2443         * config/vax/elf.opt.urls: Likewise.
2444         * config/vax/vax.opt.urls: Likewise.
2445         * config/visium/visium.opt.urls: Likewise.
2446         * config/vms/vms.opt.urls: Likewise.
2447         * config/vxworks-smp.opt.urls: Likewise.
2448         * config/vxworks.opt.urls: Likewise.
2449         * config/xtensa/elf.opt.urls: Likewise.
2450         * config/xtensa/uclinux.opt.urls: Likewise.
2451         * config/xtensa/xtensa.opt.urls: Likewise.
2452         * config/bfin/bfin.opt.urls: New file.
2453
2454 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2455
2456         * Makefile.in (OPT_URLS_HTML_DEPS): New.
2457         (regenerate-opt-urls): New target.
2458         (regenerate-opt-urls-unit-test): New target.
2459         * doc/options.texi (Option properties): Add UrlSuffix and
2460         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
2461         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
2462         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
2463         and Makefile.in's OPT_URLS_HTML_DEPS.
2464         (Anatomy of a Target Back End): Add
2465         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
2466         * regenerate-opt-urls.py: New file.
2467
2468 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2469
2470         * diagnostic-format-sarif.cc
2471         (sarif_builder::make_logical_location_object): Convert to...
2472         (make_sarif_logical_location_object): ...this.
2473         (sarif_builder::set_any_logical_locs_arr): Update for above
2474         change.
2475         (sarif_builder::make_thread_flow_location_object): Call
2476         maybe_add_sarif_properties on each diagnostic_event.
2477         * diagnostic-format-sarif.h (class logical_location): New forward
2478         decl.
2479         (make_sarif_logical_location_object): New decl.
2480         * diagnostic-path.h (class sarif_object): New forward decl.
2481         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
2482
2483 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
2484             Patrick Lin  <patrick@andestech.com>
2485             Rufus Chen  <rufus@andestech.com>
2486             Monk Chiang  <monk.chiang@sifive.com>
2487
2488         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
2489         with Nan-boxing value.
2490         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
2491
2492 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
2493             Jeff Law  <jlaw@ventanamicro.com>
2494
2495         PR rtl-optimization/104914
2496         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
2497         a sign or zero extension is only required if the modified field
2498         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
2499         targets, don't refer to the temporarily incorrectly extended value
2500         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
2501
2502 2024-01-04  Pan Li  <pan2.li@intel.com>
2503
2504         Revert:
2505         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2506
2507         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2508
2509 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2510
2511         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2512
2513 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
2514
2515         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
2516         offset of fcsr.
2517
2518 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2519
2520         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
2521         (compute_nregs_for_mode): Refine LMUL.
2522         (max_number_of_live_regs): Ditto.
2523         (compute_estimated_lmul): Ditto.
2524         (has_unexpected_spills_p): Ditto.
2525
2526 2024-01-04  Li Wei  <liwei@loongson.cn>
2527
2528         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
2529         Remove useless forward declaration.
2530         (loongarch_is_even_extraction): Remove useless forward declaration.
2531         (loongarch_try_expand_lsx_vshuf_const): Removed.
2532         (loongarch_expand_vec_perm_const_1): Merged.
2533         (loongarch_is_double_duplicate): Removed.
2534         (loongarch_is_center_extraction): Ditto.
2535         (loongarch_is_reversing_permutation): Ditto.
2536         (loongarch_is_di_misalign_extract): Ditto.
2537         (loongarch_is_si_misalign_extract): Ditto.
2538         (loongarch_is_lasx_lowpart_extract): Ditto.
2539         (loongarch_is_op_reverse_perm): Ditto.
2540         (loongarch_is_single_op_perm): Ditto.
2541         (loongarch_is_divisible_perm): Ditto.
2542         (loongarch_is_triple_stride_extract): Ditto.
2543         (loongarch_expand_vec_perm_const_2): Merged.
2544         (loongarch_expand_vec_perm_const): New.
2545         (loongarch_vectorize_vec_perm_const): Adjust.
2546
2547 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
2548
2549         * omp-general.cc: Fix comment typos and misplaced/confusing
2550         comments.  Delete redundant include of omp-general.h.
2551
2552 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2553
2554         PR rtl-optimization/104914
2555         * config/mips/mips.md (insqisi_extended): New patterns.
2556         (inshisi_extended): Ditto.
2557
2558 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2559
2560         * config/mips/mips.cc (mips_insn_cost): New function.
2561
2562 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2563
2564         * config/mips/mips.md (perf_ratio): New attribute.
2565
2566 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2567
2568         PR target/113206
2569         PR target/113209
2570         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
2571         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
2572         blocks belong to infinite loop.
2573         (pre_vsetvl::emit_vsetvl): Remove fake edges.
2574         * config/riscv/t-riscv: Add a new include file.
2575
2576 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2577
2578         * config/riscv/vector.md: Fix indent.
2579
2580 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
2581
2582         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
2583         OMP_CLAUSE__SIMDUID_.
2584         * tree.cc (omp_clause_num_ops): Update position of entry for
2585         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
2586         (omp_clause_code_name): Likewise.
2587
2588 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
2589
2590         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
2591         printing of FUNC_MAP/IND_FUNC_MAP labels.
2592
2593 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
2594
2595         * gcc.cc (process_command): Update copyright notice dates.
2596         * gcov-dump.cc (print_version): Ditto.
2597         * gcov.cc (print_version): Ditto.
2598         * gcov-tool.cc (print_version): Ditto.
2599         * gengtype.cc (create_file): Ditto.
2600         * doc/cpp.texi: Bump @copying's copyright year.
2601         * doc/cppinternals.texi: Ditto.
2602         * doc/gcc.texi: Ditto.
2603         * doc/gccint.texi: Ditto.
2604         * doc/gcov.texi: Ditto.
2605         * doc/install.texi: Ditto.
2606         * doc/invoke.texi: Ditto.
2607
2608 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
2609
2610         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
2611         (fmin<mode>3): Likewise.
2612         (reduc_fmax_scal_<mode>3): New define_expand.
2613         (reduc_fmin_scal_<mode>3): Likewise.
2614
2615 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2616
2617         PR target/113112
2618         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
2619         (max_number_of_live_regs): Ditto.
2620         (has_unexpected_spills_p): Ditto.
2621
2622 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2623             Jin Ma  <jinma@linux.alibaba.com>
2624             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2625             Christoph Müllner  <christoph.muellner@vrull.eu>
2626
2627         * config/riscv/vector.md:
2628         Use vector_length_operand for vsetvl patterns.
2629
2630 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2631
2632         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
2633         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
2634
2635 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
2636
2637         * config/aarch64/aarch64-tuning-flags.def
2638         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
2639         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
2640         * config/aarch64/aarch64.cc
2641         (aarch64_override_options_internal): Set
2642         param_fully_pipelined_fma according to tuning option.
2643         * config/aarch64/tuning_models/ampere1.h: Add
2644         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
2645         * config/aarch64/tuning_models/ampere1a.h: Likewise.
2646         * config/aarch64/tuning_models/ampere1b.h: Likewise.
2647
2648 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
2649
2650         * config/riscv/vector-crypto.md: Modify copyright year.
2651
2652 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2653
2654         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
2655
2656 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
2657
2658         * config.in: Regenerate.
2659         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
2660         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
2661         Added TLS Le Relax support.
2662         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
2663         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
2664         * configure: Regenerate.
2665         * configure.ac: Check if binutils supports TLS le relax.
2666
2667 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
2668
2669         * config/riscv/iterators.md: Add rotate insn name.
2670         * config/riscv/riscv.md: Add new insns name for crypto vector.
2671         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
2672         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
2673         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
2674
2675 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2676
2677         PR target/113112
2678         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
2679         pointer type liveness count.
2680 \f
2681 Copyright (C) 2024 Free Software Foundation, Inc.
2682
2683 Copying and distribution of this file, with or without modification,
2684 are permitted in any medium without royalty provided the copyright
2685 notice and this notice are preserved.