gcc-4_9/gcc/testsuite/gcc.target/mips/msa.c

   1 /* Test MIPS MSA ASE instructions */
   2 /* { dg-do compile } */
   3 /* { dg-options "-mfp64 -mhard-float -mmsa" } */
   4 /* { dg-skip-if "madd and msub need combine" { *-*-* } { "-O0" "-flto" } { "" } } */
   5
   6 /* { dg-final { scan-assembler-times "\t.comm\tv16i8_\\d+,16,16" 3 } } */
   7 /* { dg-final { scan-assembler-times "\t.comm\tv8i16_\\d+,16,16" 3 } } */
   8 /* { dg-final { scan-assembler-times "\t.comm\tv4i32_\\d+,16,16" 3 } } */
   9 /* { dg-final { scan-assembler-times "\t.comm\tv2i64_\\d+,16,16" 3 } } */
  10 /* { dg-final { scan-assembler-times "\t.comm\tv16u8_\\d+,16,16" 3 } } */
  11 /* { dg-final { scan-assembler-times "\t.comm\tv8u16_\\d+,16,16" 3 } } */
  12 /* { dg-final { scan-assembler-times "\t.comm\tv4u32_\\d+,16,16" 3 } } */
  13 /* { dg-final { scan-assembler-times "\t.comm\tv2u64_\\d+,16,16" 3 } } */
  14 /* { dg-final { scan-assembler-times "\t.comm\tv4f32_\\d+,16,16" 3 } } */
  15 /* { dg-final { scan-assembler-times "\t.comm\tv2f64_\\d+,16,16" 3 } } */
  16
  17 /* { dg-final { scan-assembler "test0_v16i8.*:.*v16i8_0.*test0_v16i8" } } */
  18 /* { dg-final { scan-assembler "test0_v8i16.*:.*v8i16_0.*test0_v8i16" } } */
  19 /* { dg-final { scan-assembler "test0_v4i32.*:.*v4i32_0.*test0_v4i32" } } */
  20 /* { dg-final { scan-assembler "test0_v2i64.*:.*v2i64_0.*test0_v2i64" } } */
  21 /* { dg-final { scan-assembler "test0_v16u8.*:.*v16u8_0.*test0_v16u8" } } */
  22 /* { dg-final { scan-assembler "test0_v8u16.*:.*v8u16_0.*test0_v8u16" } } */
  23 /* { dg-final { scan-assembler "test0_v4u32.*:.*v4u32_0.*test0_v4u32" } } */
  24 /* { dg-final { scan-assembler "test0_v2u64.*:.*v2u64_0.*test0_v2u64" } } */
  25 /* { dg-final { scan-assembler "test0_v4f32.*:.*v4f32_0.*test0_v4f32" } } */
  26 /* { dg-final { scan-assembler "test0_v2f64.*:.*v2f64_0.*test0_v2f64" } } */
  27 /* { dg-final { scan-assembler "test1_v16i8.*:.*st.b.*test1_v16i8" } } */
  28 /* { dg-final { scan-assembler "test1_v8i16.*:.*st.h.*test1_v8i16" } } */
  29 /* { dg-final { scan-assembler "test1_v4i32.*:.*st.w.*test1_v4i32" } } */
  30 /* { dg-final { scan-assembler "test1_v2i64.*:.*st.d.*test1_v2i64" } } */
  31 /* { dg-final { scan-assembler "test1_v16u8.*:.*st.b.*test1_v16u8" } } */
  32 /* { dg-final { scan-assembler "test1_v8u16.*:.*st.h.*test1_v8u16" } } */
  33 /* { dg-final { scan-assembler "test1_v4u32.*:.*st.w.*test1_v4u32" } } */
  34 /* { dg-final { scan-assembler "test1_v2u64.*:.*st.d.*test1_v2u64" } } */
  35 /* { dg-final { scan-assembler "test1_v4f32.*:.*st.w.*test1_v4f32" } } */
  36 /* { dg-final { scan-assembler "test1_v2f64.*:.*st.d.*test1_v2f64" } } */
  37 /* { dg-final { scan-assembler "test2_v16i8.*:.*addv.b.*test2_v16i8" } } */
  38 /* { dg-final { scan-assembler "test2_v8i16.*:.*addv.h.*test2_v8i16" } } */
  39 /* { dg-final { scan-assembler "test2_v4i32.*:.*addv.w.*test2_v4i32" } } */
  40 /* { dg-final { scan-assembler "test2_v2i64.*:.*addv.d.*test2_v2i64" } } */
  41 /* { dg-final { scan-assembler "test2_v16u8.*:.*addv.b.*test2_v16u8" } } */
  42 /* { dg-final { scan-assembler "test2_v8u16.*:.*addv.h.*test2_v8u16" } } */
  43 /* { dg-final { scan-assembler "test2_v4u32.*:.*addv.w.*test2_v4u32" } } */
  44 /* { dg-final { scan-assembler "test2_v2u64.*:.*addv.d.*test2_v2u64" } } */
  45 /* { dg-final { scan-assembler "test2_v4f32.*:.*fadd.w.*test2_v4f32" } } */
  46 /* { dg-final { scan-assembler "test2_v2f64.*:.*fadd.d.*test2_v2f64" } } */
  47 /* { dg-final { scan-assembler "test3_v16i8.*:.*subv.b.*test3_v16i8" } } */
  48 /* { dg-final { scan-assembler "test3_v8i16.*:.*subv.h.*test3_v8i16" } } */
  49 /* { dg-final { scan-assembler "test3_v4i32.*:.*subv.w.*test3_v4i32" } } */
  50 /* { dg-final { scan-assembler "test3_v2i64.*:.*subv.d.*test3_v2i64" } } */
  51 /* { dg-final { scan-assembler "test3_v16u8.*:.*subv.b.*test3_v16u8" } } */
  52 /* { dg-final { scan-assembler "test3_v8u16.*:.*subv.h.*test3_v8u16" } } */
  53 /* { dg-final { scan-assembler "test3_v4u32.*:.*subv.w.*test3_v4u32" } } */
  54 /* { dg-final { scan-assembler "test3_v2u64.*:.*subv.d.*test3_v2u64" } } */
  55 /* { dg-final { scan-assembler "test3_v4f32.*:.*fsub.w.*test3_v4f32" } } */
  56 /* { dg-final { scan-assembler "test3_v2f64.*:.*fsub.d.*test3_v2f64" } } */
  57 /* { dg-final { scan-assembler "test4_v16i8.*:.*mulv.b.*test4_v16i8" } } */
  58 /* { dg-final { scan-assembler "test4_v8i16.*:.*mulv.h.*test4_v8i16" } } */
  59 /* { dg-final { scan-assembler "test4_v4i32.*:.*mulv.w.*test4_v4i32" } } */
  60 /* { dg-final { scan-assembler "test4_v2i64.*:.*mulv.d.*test4_v2i64" } } */
  61 /* { dg-final { scan-assembler "test4_v16u8.*:.*mulv.b.*test4_v16u8" } } */
  62 /* { dg-final { scan-assembler "test4_v8u16.*:.*mulv.h.*test4_v8u16" } } */
  63 /* { dg-final { scan-assembler "test4_v4u32.*:.*mulv.w.*test4_v4u32" } } */
  64 /* { dg-final { scan-assembler "test4_v2u64.*:.*mulv.d.*test4_v2u64" } } */
  65 /* { dg-final { scan-assembler "test4_v4f32.*:.*fmul.w.*test4_v4f32" } } */
  66 /* { dg-final { scan-assembler "test4_v2f64.*:.*fmul.d.*test4_v2f64" } } */
  67 /* { dg-final { scan-assembler "test5_v16i8.*:.*div_s.b.*test5_v16i8" } } */
  68 /* { dg-final { scan-assembler "test5_v8i16.*:.*div_s.h.*test5_v8i16" } } */
  69 /* { dg-final { scan-assembler "test5_v4i32.*:.*div_s.w.*test5_v4i32" } } */
  70 /* { dg-final { scan-assembler "test5_v2i64.*:.*div_s.d.*test5_v2i64" } } */
  71 /* { dg-final { scan-assembler "test5_v16u8.*:.*div_u.b.*test5_v16u8" } } */
  72 /* { dg-final { scan-assembler "test5_v8u16.*:.*div_u.h.*test5_v8u16" } } */
  73 /* { dg-final { scan-assembler "test5_v4u32.*:.*div_u.w.*test5_v4u32" } } */
  74 /* { dg-final { scan-assembler "test5_v2u64.*:.*div_u.d.*test5_v2u64" } } */
  75 /* { dg-final { scan-assembler "test5_v4f32.*:.*fdiv.w.*test5_v4f32" } } */
  76 /* { dg-final { scan-assembler "test5_v2f64.*:.*fdiv.d.*test5_v2f64" } } */
  77 /* { dg-final { scan-assembler "test6_v16i8.*:.*mod_s.b.*test6_v16i8" } } */
  78 /* { dg-final { scan-assembler "test6_v8i16.*:.*mod_s.h.*test6_v8i16" } } */
  79 /* { dg-final { scan-assembler "test6_v4i32.*:.*mod_s.w.*test6_v4i32" } } */
  80 /* { dg-final { scan-assembler "test6_v2i64.*:.*mod_s.d.*test6_v2i64" } } */
  81 /* { dg-final { scan-assembler "test6_v16u8.*:.*mod_u.b.*test6_v16u8" } } */
  82 /* { dg-final { scan-assembler "test6_v8u16.*:.*mod_u.h.*test6_v8u16" } } */
  83 /* { dg-final { scan-assembler "test6_v4u32.*:.*mod_u.w.*test6_v4u32" } } */
  84 /* { dg-final { scan-assembler "test6_v2u64.*:.*mod_u.d.*test6_v2u64" } } */
  85 /* { dg-final { scan-assembler "test7_v16i8.*:.*subv.b.*test7_v16i8" } } */
  86 /* { dg-final { scan-assembler "test7_v8i16.*:.*subv.h.*test7_v8i16" } } */
  87 /* { dg-final { scan-assembler "test7_v4i32.*:.*subv.w.*test7_v4i32" } } */
  88 /* { dg-final { scan-assembler "test7_v2i64.*:.*subv.d.*test7_v2i64" } } */
  89 /* { dg-final { scan-assembler "test7_v16u8.*:.*subv.b.*test7_v16u8" } } */
  90 /* { dg-final { scan-assembler "test7_v8u16.*:.*subv.h.*test7_v8u16" } } */
  91 /* { dg-final { scan-assembler "test7_v4u32.*:.*subv.w.*test7_v4u32" } } */
  92 /* { dg-final { scan-assembler "test7_v2u64.*:.*subv.d.*test7_v2u64" } } */
  93 /* { dg-final { scan-assembler "test7_v4f32.*:.*fsub.w.*test7_v4f32" } } */
  94 /* { dg-final { scan-assembler "test7_v2f64.*:.*fsub.d.*test7_v2f64" } } */
  95 /* { dg-final { scan-assembler "test8_v16i8.*:.*xor.v.*test8_v16i8" } } */
  96 /* { dg-final { scan-assembler "test8_v8i16.*:.*xor.v.*test8_v8i16" } } */
  97 /* { dg-final { scan-assembler "test8_v4i32.*:.*xor.v.*test8_v4i32" } } */
  98 /* { dg-final { scan-assembler "test8_v2i64.*:.*xor.v.*test8_v2i64" } } */
  99 /* { dg-final { scan-assembler "test8_v16u8.*:.*xor.v.*test8_v16u8" } } */
 100 /* { dg-final { scan-assembler "test8_v8u16.*:.*xor.v.*test8_v8u16" } } */
 101 /* { dg-final { scan-assembler "test8_v4u32.*:.*xor.v.*test8_v4u32" } } */
 102 /* { dg-final { scan-assembler "test8_v2u64.*:.*xor.v.*test8_v2u64" } } */
 103 /* { dg-final { scan-assembler "test9_v16i8.*:.*or.v.*test9_v16i8" } } */
 104 /* { dg-final { scan-assembler "test9_v8i16.*:.*or.v.*test9_v8i16" } } */
 105 /* { dg-final { scan-assembler "test9_v4i32.*:.*or.v.*test9_v4i32" } } */
 106 /* { dg-final { scan-assembler "test9_v2i64.*:.*or.v.*test9_v2i64" } } */
 107 /* { dg-final { scan-assembler "test9_v16u8.*:.*or.v.*test9_v16u8" } } */
 108 /* { dg-final { scan-assembler "test9_v8u16.*:.*or.v.*test9_v8u16" } } */
 109 /* { dg-final { scan-assembler "test9_v4u32.*:.*or.v.*test9_v4u32" } } */
 110 /* { dg-final { scan-assembler "test9_v2u64.*:.*or.v.*test9_v2u64" } } */
 111 /* { dg-final { scan-assembler "test10_v16i8.*:.*and.v.*test10_v16i8" } } */
 112 /* { dg-final { scan-assembler "test10_v8i16.*:.*and.v.*test10_v8i16" } } */
 113 /* { dg-final { scan-assembler "test10_v4i32.*:.*and.v.*test10_v4i32" } } */
 114 /* { dg-final { scan-assembler "test10_v2i64.*:.*and.v.*test10_v2i64" } } */
 115 /* { dg-final { scan-assembler "test10_v16u8.*:.*and.v.*test10_v16u8" } } */
 116 /* { dg-final { scan-assembler "test10_v8u16.*:.*and.v.*test10_v8u16" } } */
 117 /* { dg-final { scan-assembler "test10_v4u32.*:.*and.v.*test10_v4u32" } } */
 118 /* { dg-final { scan-assembler "test10_v2u64.*:.*and.v.*test10_v2u64" } } */
 119 /* { dg-final { scan-assembler "test11_v16i8.*:.*nor.v.*test11_v16i8" } } */
 120 /* { dg-final { scan-assembler "test11_v8i16.*:.*nor.v.*test11_v8i16" } } */
 121 /* { dg-final { scan-assembler "test11_v4i32.*:.*nor.v.*test11_v4i32" } } */
 122 /* { dg-final { scan-assembler "test11_v2i64.*:.*nor.v.*test11_v2i64" } } */
 123 /* { dg-final { scan-assembler "test11_v16u8.*:.*nor.v.*test11_v16u8" } } */
 124 /* { dg-final { scan-assembler "test11_v8u16.*:.*nor.v.*test11_v8u16" } } */
 125 /* { dg-final { scan-assembler "test11_v4u32.*:.*nor.v.*test11_v4u32" } } */
 126 /* { dg-final { scan-assembler "test11_v2u64.*:.*nor.v.*test11_v2u64" } } */
 127 /* { dg-final { scan-assembler "test12_v16i8.*:.*sra.b.*test12_v16i8" } } */
 128 /* { dg-final { scan-assembler "test12_v8i16.*:.*sra.h.*test12_v8i16" } } */
 129 /* { dg-final { scan-assembler "test12_v4i32.*:.*sra.w.*test12_v4i32" } } */
 130 /* { dg-final { scan-assembler "test12_v2i64.*:.*sra.d.*test12_v2i64" } } */
 131 /* { dg-final { scan-assembler "test12_v16u8.*:.*srl.b.*test12_v16u8" } } */
 132 /* { dg-final { scan-assembler "test12_v8u16.*:.*srl.h.*test12_v8u16" } } */
 133 /* { dg-final { scan-assembler "test12_v4u32.*:.*srl.w.*test12_v4u32" } } */
 134 /* { dg-final { scan-assembler "test12_v2u64.*:.*srl.d.*test12_v2u64" } } */
 135 /* { dg-final { scan-assembler "test13_v16i8.*:.*sll.b.*test13_v16i8" } } */
 136 /* { dg-final { scan-assembler "test13_v8i16.*:.*sll.h.*test13_v8i16" } } */
 137 /* { dg-final { scan-assembler "test13_v4i32.*:.*sll.w.*test13_v4i32" } } */
 138 /* { dg-final { scan-assembler "test13_v2i64.*:.*sll.d.*test13_v2i64" } } */
 139 /* { dg-final { scan-assembler "test13_v16u8.*:.*sll.b.*test13_v16u8" } } */
 140 /* { dg-final { scan-assembler "test13_v8u16.*:.*sll.h.*test13_v8u16" } } */
 141 /* { dg-final { scan-assembler "test13_v4u32.*:.*sll.w.*test13_v4u32" } } */
 142 /* { dg-final { scan-assembler "test13_v2u64.*:.*sll.d.*test13_v2u64" } } */
 143 /* { dg-final { scan-assembler "test14_v16i8.*:.*ceq.b.*test14_v16i8" } } */
 144 /* { dg-final { scan-assembler "test14_v8i16.*:.*ceq.h.*test14_v8i16" } } */
 145 /* { dg-final { scan-assembler "test14_v4i32.*:.*ceq.w.*test14_v4i32" } } */
 146 /* { dg-final { scan-assembler "test14_v2i64.*:.*ceq.d.*test14_v2i64" } } */
 147 /* { dg-final { scan-assembler "test14_v16u8.*:.*ceq.b.*test14_v16u8" } } */
 148 /* { dg-final { scan-assembler "test14_v8u16.*:.*ceq.h.*test14_v8u16" } } */
 149 /* { dg-final { scan-assembler "test14_v4u32.*:.*ceq.w.*test14_v4u32" } } */
 150 /* { dg-final { scan-assembler "test14_v2u64.*:.*ceq.d.*test14_v2u64" } } */
 151 /* { dg-final { scan-assembler "test14_v4f32.*:.*fceq.w.*test14_v4f32" } } */
 152 /* { dg-final { scan-assembler "test14_v2f64.*:.*fceq.d.*test14_v2f64" } } */
 153 /* { dg-final { scan-assembler "test15_v16i8.*:.*ceq.b.*nor.v.*test15_v16i8" } } */
 154 /* { dg-final { scan-assembler "test15_v8i16.*:.*ceq.h.*nor.v.*test15_v8i16" } } */
 155 /* { dg-final { scan-assembler "test15_v4i32.*:.*ceq.w.*nor.v.*test15_v4i32" } } */
 156 /* { dg-final { scan-assembler "test15_v2i64.*:.*ceq.d.*nor.v.*test15_v2i64" } } */
 157 /* { dg-final { scan-assembler "test15_v16u8.*:.*ceq.b.*nor.v.*test15_v16u8" } } */
 158 /* { dg-final { scan-assembler "test15_v8u16.*:.*ceq.h.*nor.v.*test15_v8u16" } } */
 159 /* { dg-final { scan-assembler "test15_v4u32.*:.*ceq.w.*nor.v.*test15_v4u32" } } */
 160 /* { dg-final { scan-assembler "test15_v2u64.*:.*ceq.d.*nor.v.*test15_v2u64" } } */
 161 /* { dg-final { scan-assembler "test15_v4f32.*:.*fcne.w.*test15_v4f32" } } */
 162 /* { dg-final { scan-assembler "test15_v2f64.*:.*fcne.d.*test15_v2f64" } } */
 163 /* { dg-final { scan-assembler "test16_v16i8.*:.*clt_s.b.*test16_v16i8" { target mips64 } } } */
 164 /* { dg-final { scan-assembler "test16_v8i16.*:.*clt_s.h.*test16_v8i16" { target mips64 } } } */
 165 /* { dg-final { scan-assembler "test16_v4i32.*:.*clt_s.w.*test16_v4i32" { target mips64 } } } */
 166 /* { dg-final { scan-assembler "test16_v2i64.*:.*clt_s.d.*test16_v2i64" { target mips64 } } } */
 167 /* { dg-final { scan-assembler "test16_v16u8.*:.*clt_u.b.*test16_v16u8" { target mips64 } } } */
 168 /* { dg-final { scan-assembler "test16_v8u16.*:.*clt_u.h.*test16_v8u16" { target mips64 } } } */
 169 /* { dg-final { scan-assembler "test16_v4u32.*:.*clt_u.w.*test16_v4u32" { target mips64 } } } */
 170 /* { dg-final { scan-assembler "test16_v2u64.*:.*clt_u.d.*test16_v2u64" { target mips64 } } } */
 171 /* { dg-final { scan-assembler "test16_v4f32.*:.*fslt.w.*test16_v4f32" { target mips64 } } } */
 172 /* { dg-final { scan-assembler "test16_v2f64.*:.*fslt.d.*test16_v2f64" { target mips64 } } } */
 173 /* { dg-final { scan-assembler "test16_v16i8.*:.*clt_s.b.*test16_v16i8" { target {! mips64 } } } } */
 174 /* { dg-final { scan-assembler "test16_v8i16.*:.*clt_s.h.*test16_v8i16" { target {! mips64 } } } } */
 175 /* { dg-final { scan-assembler "test16_v4i32.*:.*clt_s.w.*test16_v4i32" { target {! mips64 } } } } */
 176 /* { dg-final { scan-assembler "test16_v2i64.*:.*clt_s.d.*test16_v2i64" { target {! mips64 } } } } */
 177 /* { dg-final { scan-assembler "test16_v16u8.*:.*clt_u.b.*test16_v16u8" { target {! mips64 } } } } */
 178 /* { dg-final { scan-assembler "test16_v8u16.*:.*clt_u.h.*test16_v8u16" { target {! mips64 } } } } */
 179 /* { dg-final { scan-assembler "test16_v4u32.*:.*clt_u.w.*test16_v4u32" { target {! mips64 } } } } */
 180 /* { dg-final { scan-assembler "test16_v2u64.*:.*clt_u.d.*test16_v2u64" { target {! mips64 } } } } */
 181 /* { dg-final { scan-assembler "test16_v4f32.*:.*fslt.w.*test16_v4f32" { target {! mips64 } } } } */
 182 /* { dg-final { scan-assembler "test16_v2f64.*:.*fslt.d.*test16_v2f64" { target {! mips64 } } } } */
 183 /* { dg-final { scan-assembler "test17_v16i8.*:.*cle_s.b.*test17_v16i8" { target mips64 } } } */
 184 /* { dg-final { scan-assembler "test17_v8i16.*:.*cle_s.h.*test17_v8i16" { target mips64 } } } */
 185 /* { dg-final { scan-assembler "test17_v4i32.*:.*cle_s.w.*test17_v4i32" { target mips64 } } } */
 186 /* { dg-final { scan-assembler "test17_v2i64.*:.*cle_s.d.*test17_v2i64" { target mips64 } } } */
 187 /* { dg-final { scan-assembler "test17_v16u8.*:.*cle_u.b.*test17_v16u8" { target mips64 } } } */
 188 /* { dg-final { scan-assembler "test17_v8u16.*:.*cle_u.h.*test17_v8u16" { target mips64 } } } */
 189 /* { dg-final { scan-assembler "test17_v4u32.*:.*cle_u.w.*test17_v4u32" { target mips64 } } } */
 190 /* { dg-final { scan-assembler "test17_v2u64.*:.*cle_u.d.*test17_v2u64" { target mips64 } } } */
 191 /* { dg-final { scan-assembler "test17_v4f32.*:.*fsle.w.*test17_v4f32" { target mips64 } } } */
 192 /* { dg-final { scan-assembler "test17_v2f64.*:.*fsle.d.*test17_v2f64" { target mips64 } } } */
 193 /* { dg-final { scan-assembler "test17_v16i8.*:.*cle_s.b.*test17_v16i8" { target {! mips64 } } } } */
 194 /* { dg-final { scan-assembler "test17_v8i16.*:.*cle_s.h.*test17_v8i16" { target {! mips64 } } } } */
 195 /* { dg-final { scan-assembler "test17_v4i32.*:.*cle_s.w.*test17_v4i32" { target {! mips64 } } } } */
 196 /* { dg-final { scan-assembler "test17_v2i64.*:.*cle_s.d.*test17_v2i64" { target {! mips64 } } } } */
 197 /* { dg-final { scan-assembler "test17_v16u8.*:.*cle_u.b.*test17_v16u8" { target {! mips64 } } } } */
 198 /* { dg-final { scan-assembler "test17_v8u16.*:.*cle_u.h.*test17_v8u16" { target {! mips64 } } } } */
 199 /* { dg-final { scan-assembler "test17_v4u32.*:.*cle_u.w.*test17_v4u32" { target {! mips64 } } } } */
 200 /* { dg-final { scan-assembler "test17_v2u64.*:.*cle_u.d.*test17_v2u64" { target {! mips64 } } } } */
 201 /* { dg-final { scan-assembler "test17_v4f32.*:.*fsle.w.*test17_v4f32" { target {! mips64 } } } } */
 202 /* { dg-final { scan-assembler "test17_v2f64.*:.*fsle.d.*test17_v2f64" { target {! mips64 } } } } */
 203 /* Note: For reversed comparison the compare instruction is the same with vectors swapped.  */
 204 /* { dg-final { scan-assembler "test18_v16i8.*:.*clt_s.b.*test18_v16i8" { target mips64 } } } */
 205 /* { dg-final { scan-assembler "test18_v8i16.*:.*clt_s.h.*test18_v8i16" { target mips64 } } } */
 206 /* { dg-final { scan-assembler "test18_v4i32.*:.*clt_s.w.*test18_v4i32" { target mips64 } } } */
 207 /* { dg-final { scan-assembler "test18_v2i64.*:.*clt_s.d.*test18_v2i64" { target mips64 } } } */
 208 /* { dg-final { scan-assembler "test18_v16u8.*:.*clt_u.b.*test18_v16u8" { target mips64 } } } */
 209 /* { dg-final { scan-assembler "test18_v8u16.*:.*clt_u.h.*test18_v8u16" { target mips64 } } } */
 210 /* { dg-final { scan-assembler "test18_v4u32.*:.*clt_u.w.*test18_v4u32" { target mips64 } } } */
 211 /* { dg-final { scan-assembler "test18_v2u64.*:.*clt_u.d.*test18_v2u64" { target mips64 } } } */
 212 /* { dg-final { scan-assembler "test18_v4f32.*:.*fslt.w.*test18_v4f32" { target mips64 } } } */
 213 /* { dg-final { scan-assembler "test18_v2f64.*:.*fslt.d.*test18_v2f64" { target mips64 } } } */
 214 /* { dg-final { scan-assembler "test18_v16i8.*:.*clt_s.b.*test18_v16i8" { target {! mips64 } } } } */
 215 /* { dg-final { scan-assembler "test18_v8i16.*:.*clt_s.h.*test18_v8i16" { target {! mips64 } } } } */
 216 /* { dg-final { scan-assembler "test18_v4i32.*:.*clt_s.w.*test18_v4i32" { target {! mips64 } } } } */
 217 /* { dg-final { scan-assembler "test18_v2i64.*:.*clt_s.d.*test18_v2i64" { target {! mips64 } } } } */
 218 /* { dg-final { scan-assembler "test18_v16u8.*:.*clt_u.b.*test18_v16u8" { target {! mips64 } } } } */
 219 /* { dg-final { scan-assembler "test18_v8u16.*:.*clt_u.h.*test18_v8u16" { target {! mips64 } } } } */
 220 /* { dg-final { scan-assembler "test18_v4u32.*:.*clt_u.w.*test18_v4u32" { target {! mips64 } } } } */
 221 /* { dg-final { scan-assembler "test18_v2u64.*:.*clt_u.d.*test18_v2u64" { target {! mips64 } } } } */
 222 /* { dg-final { scan-assembler "test18_v4f32.*:.*fslt.w.*test18_v4f32" { target {! mips64 } } } } */
 223 /* { dg-final { scan-assembler "test18_v2f64.*:.*fslt.d.*test18_v2f64" { target {! mips64 } } } } */
 224 /* { dg-final { scan-assembler "test19_v16i8.*:.*cle_s.b.*test19_v16i8" { target mips64 } } } */
 225 /* { dg-final { scan-assembler "test19_v8i16.*:.*cle_s.h.*test19_v8i16" { target mips64 } } } */
 226 /* { dg-final { scan-assembler "test19_v4i32.*:.*cle_s.w.*test19_v4i32" { target mips64 } } } */
 227 /* { dg-final { scan-assembler "test19_v2i64.*:.*cle_s.d.*test19_v2i64" { target mips64 } } } */
 228 /* { dg-final { scan-assembler "test19_v16u8.*:.*cle_u.b.*test19_v16u8" { target mips64 } } } */
 229 /* { dg-final { scan-assembler "test19_v8u16.*:.*cle_u.h.*test19_v8u16" { target mips64 } } } */
 230 /* { dg-final { scan-assembler "test19_v4u32.*:.*cle_u.w.*test19_v4u32" { target mips64 } } } */
 231 /* { dg-final { scan-assembler "test19_v2u64.*:.*cle_u.d.*test19_v2u64" { target mips64 } } } */
 232 /* { dg-final { scan-assembler "test19_v4f32.*:.*fsle.w.*test19_v4f32" { target mips64 } } } */
 233 /* { dg-final { scan-assembler "test19_v2f64.*:.*fsle.d.*test19_v2f64" { target mips64 } } } */
 234 /* { dg-final { scan-assembler "test19_v16i8.*:.*cle_s.b.*test19_v16i8" { target {! mips64 } } } } */
 235 /* { dg-final { scan-assembler "test19_v8i16.*:.*cle_s.h.*test19_v8i16" { target {! mips64 } } } } */
 236 /* { dg-final { scan-assembler "test19_v4i32.*:.*cle_s.w.*test19_v4i32" { target {! mips64 } } } } */
 237 /* { dg-final { scan-assembler "test19_v2i64.*:.*cle_s.d.*test19_v2i64" { target {! mips64 } } } } */
 238 /* { dg-final { scan-assembler "test19_v16u8.*:.*cle_u.b.*test19_v16u8" { target {! mips64 } } } } */
 239 /* { dg-final { scan-assembler "test19_v8u16.*:.*cle_u.h.*test19_v8u16" { target {! mips64 } } } } */
 240 /* { dg-final { scan-assembler "test19_v4u32.*:.*cle_u.w.*test19_v4u32" { target {! mips64 } } } } */
 241 /* { dg-final { scan-assembler "test19_v2u64.*:.*cle_u.d.*test19_v2u64" { target {! mips64 } } } } */
 242 /* { dg-final { scan-assembler "test19_v4f32.*:.*fsle.w.*test19_v4f32" { target {! mips64 } } } } */
 243 /* { dg-final { scan-assembler "test19_v2f64.*:.*fsle.d.*test19_v2f64" { target {! mips64 } } } } */
 244 /* { dg-final { scan-assembler "test20_v16i8.*:.*addvi.b.*test20_v16i8" } } */
 245 /* { dg-final { scan-assembler "test20_v8i16.*:.*addvi.h.*test20_v8i16" } } */
 246 /* { dg-final { scan-assembler "test20_v4i32.*:.*addvi.w.*test20_v4i32" } } */
 247 /* { dg-final { scan-assembler "test20_v2i64.*:.*addvi.d.*test20_v2i64" } } */
 248 /* { dg-final { scan-assembler "test20_v16u8.*:.*addvi.b.*test20_v16u8" } } */
 249 /* { dg-final { scan-assembler "test20_v8u16.*:.*addvi.h.*test20_v8u16" } } */
 250 /* { dg-final { scan-assembler "test20_v4u32.*:.*addvi.w.*test20_v4u32" } } */
 251 /* { dg-final { scan-assembler "test20_v2u64.*:.*addvi.d.*test20_v2u64" } } */
 252 /* { dg-final { scan-assembler "test21_v16i8.*:.*subvi.b.*test21_v16i8" } } */
 253 /* { dg-final { scan-assembler "test21_v8i16.*:.*subvi.h.*test21_v8i16" } } */
 254 /* { dg-final { scan-assembler "test21_v4i32.*:.*subvi.w.*test21_v4i32" } } */
 255 /* { dg-final { scan-assembler "test21_v2i64.*:.*subvi.d.*test21_v2i64" } } */
 256 /* { dg-final { scan-assembler "test21_v16u8.*:.*subvi.b.*test21_v16u8" } } */
 257 /* { dg-final { scan-assembler "test21_v8u16.*:.*subvi.h.*test21_v8u16" } } */
 258 /* { dg-final { scan-assembler "test21_v4u32.*:.*subvi.w.*test21_v4u32" } } */
 259 /* { dg-final { scan-assembler "test21_v2u64.*:.*subvi.d.*test21_v2u64" } } */
 260 /* Note: the output varies across optimizations levels but limited to two variants.  */
 261 /* { dg-final { scan-assembler "test22_v16i8.*:.*(ldi.b.*37.*mulv.b|slli.b.*addv.b).*test22_v16i8" } } */
 262 /* { dg-final { scan-assembler "test22_v8i16.*:.*(ldi.h.*37.*mulv.h|slli.h.*addv.h).*test22_v8i16" } } */
 263 /* { dg-final { scan-assembler "test22_v4i32.*:.*(ldi.w.*37.*mulv.w|slli.w.*addv.w).*test22_v4i32" } } */
 264 /* { dg-final { scan-assembler "test22_v2i64.*:.*(ldi.d.*37.*mulv.d|slli.d.*addv.d).*test22_v2i64" } } */
 265 /* { dg-final { scan-assembler "test22_v16u8.*:.*(ldi.b.*37.*mulv.b|slli.b.*addv.b).*test22_v16u8" } } */
 266 /* { dg-final { scan-assembler "test22_v8u16.*:.*(ldi.h.*37.*mulv.h|slli.h.*addv.h).*test22_v8u16" } } */
 267 /* { dg-final { scan-assembler "test22_v4u32.*:.*(ldi.w.*37.*mulv.w|slli.w.*addv.w).*test22_v4u32" } } */
 268 /* { dg-final { scan-assembler "test22_v2u64.*:.*(ldi.d.*37.*mulv.d|slli.d.*addv.d).*test22_v2u64" } } */
 269 /* { dg-final { scan-assembler "test23_v16i8.*:.*ldi.b\t\\\$w\\d+,37.*div_s.b.*test23_v16i8" } } */
 270 /* { dg-final { scan-assembler "test23_v8i16.*:.*ldi.h\t\\\$w\\d+,37.*div_s.h.*test23_v8i16" } } */
 271 /* { dg-final { scan-assembler "test23_v4i32.*:.*ldi.w\t\\\$w\\d+,37.*div_s.w.*test23_v4i32" } } */
 272 /* { dg-final { scan-assembler "test23_v2i64.*:.*ldi.d\t\\\$w\\d+,37.*div_s.d.*test23_v2i64" } } */
 273 /* { dg-final { scan-assembler "test23_v16u8.*:.*ldi.b\t\\\$w\\d+,37.*div_u.b.*test23_v16u8" } } */
 274 /* { dg-final { scan-assembler "test23_v8u16.*:.*ldi.h\t\\\$w\\d+,37.*div_u.h.*test23_v8u16" } } */
 275 /* { dg-final { scan-assembler "test23_v4u32.*:.*ldi.w\t\\\$w\\d+,37.*div_u.w.*test23_v4u32" } } */
 276 /* { dg-final { scan-assembler "test23_v2u64.*:.*ldi.d\t\\\$w\\d+,37.*div_u.d.*test23_v2u64" } } */
 277 /* { dg-final { scan-assembler "test24_v16i8.*:.*ldi.b\t\\\$w\\d+,37.*mod_s.b.*test24_v16i8" } } */
 278 /* { dg-final { scan-assembler "test24_v8i16.*:.*ldi.h\t\\\$w\\d+,37.*mod_s.h.*test24_v8i16" } } */
 279 /* { dg-final { scan-assembler "test24_v4i32.*:.*ldi.w\t\\\$w\\d+,37.*mod_s.w.*test24_v4i32" } } */
 280 /* { dg-final { scan-assembler "test24_v2i64.*:.*ldi.d\t\\\$w\\d+,37.*mod_s.d.*test24_v2i64" } } */
 281 /* { dg-final { scan-assembler "test24_v16u8.*:.*ldi.b\t\\\$w\\d+,37.*mod_u.b.*test24_v16u8" } } */
 282 /* { dg-final { scan-assembler "test24_v8u16.*:.*ldi.h\t\\\$w\\d+,37.*mod_u.h.*test24_v8u16" } } */
 283 /* { dg-final { scan-assembler "test24_v4u32.*:.*ldi.w\t\\\$w\\d+,37.*mod_u.w.*test24_v4u32" } } */
 284 /* { dg-final { scan-assembler "test24_v2u64.*:.*ldi.d\t\\\$w\\d+,37.*mod_u.d.*test24_v2u64" } } */
 285 /* { dg-final { scan-assembler "test25_v16i8.*:.*xori.b.*test25_v16i8" } } */
 286 /* { dg-final { scan-assembler "test25_v8i16.*:.*ldi.h\t\\\$w\\d+,37.*xor.v.*test25_v8i16" } } */
 287 /* { dg-final { scan-assembler "test25_v4i32.*:.*ldi.w\t\\\$w\\d+,37.*xor.v.*test25_v4i32" } } */
 288 /* { dg-final { scan-assembler "test25_v2i64.*:.*ldi.d\t\\\$w\\d+,37.*xor.v.*test25_v2i64" } } */
 289 /* { dg-final { scan-assembler "test25_v16u8.*:.*xori.b.*test25_v16u8" } } */
 290 /* { dg-final { scan-assembler "test25_v8u16.*:.*ldi.h\t\\\$w\\d+,37.*xor.v.*test25_v8u16" } } */
 291 /* { dg-final { scan-assembler "test25_v4u32.*:.*ldi.w\t\\\$w\\d+,37.*xor.v.*test25_v4u32" } } */
 292 /* { dg-final { scan-assembler "test25_v2u64.*:.*ldi.d\t\\\$w\\d+,37.*xor.v.*test25_v2u64" } } */
 293 /* { dg-final { scan-assembler "test26_v16i8.*:.*ori.b.*test26_v16i8" } } */
 294 /* { dg-final { scan-assembler "test26_v8i16.*:.*ldi.h\t\\\$w\\d+,37.*or.v.*test26_v8i16" } } */
 295 /* { dg-final { scan-assembler "test26_v4i32.*:.*ldi.w\t\\\$w\\d+,37.*or.v.*test26_v4i32" } } */
 296 /* { dg-final { scan-assembler "test26_v2i64.*:.*ldi.d\t\\\$w\\d+,37.*or.v.*test26_v2i64" } } */
 297 /* { dg-final { scan-assembler "test26_v16u8.*:.*ori.b.*test26_v16u8" } } */
 298 /* { dg-final { scan-assembler "test26_v8u16.*:.*ldi.h\t\\\$w\\d+,37.*or.v.*test26_v8u16" } } */
 299 /* { dg-final { scan-assembler "test26_v4u32.*:.*ldi.w\t\\\$w\\d+,37.*or.v.*test26_v4u32" } } */
 300 /* { dg-final { scan-assembler "test26_v2u64.*:.*ldi.d\t\\\$w\\d+,37.*or.v.*test26_v2u64" } } */
 301 /* { dg-final { scan-assembler "test27_v16i8.*:.*andi.b.*test27_v16i8" } } */
 302 /* { dg-final { scan-assembler "test27_v8i16.*:.*ldi.h\t\\\$w\\d+,37.*and.v.*test27_v8i16" } } */
 303 /* { dg-final { scan-assembler "test27_v4i32.*:.*ldi.w\t\\\$w\\d+,37.*and.v.*test27_v4i32" } } */
 304 /* { dg-final { scan-assembler "test27_v2i64.*:.*ldi.d\t\\\$w\\d+,37.*and.v.*test27_v2i64" } } */
 305 /* { dg-final { scan-assembler "test27_v16u8.*:.*andi.b.*test27_v16u8" } } */
 306 /* { dg-final { scan-assembler "test27_v8u16.*:.*ldi.h\t\\\$w\\d+,37.*and.v.*test27_v8u16" } } */
 307 /* { dg-final { scan-assembler "test27_v4u32.*:.*ldi.w\t\\\$w\\d+,37.*and.v.*test27_v4u32" } } */
 308 /* { dg-final { scan-assembler "test27_v2u64.*:.*ldi.d\t\\\$w\\d+,37.*and.v.*test27_v2u64" } } */
 309 /* { dg-final { scan-assembler "test28_v16i8.*:.*srai.b.*test28_v16i8" } } */
 310 /* { dg-final { scan-assembler "test28_v8i16.*:.*srai.h.*test28_v8i16" } } */
 311 /* { dg-final { scan-assembler "test28_v4i32.*:.*srai.w.*test28_v4i32" } } */
 312 /* { dg-final { scan-assembler "test28_v2i64.*:.*srai.d.*test28_v2i64" } } */
 313 /* { dg-final { scan-assembler "test28_v16u8.*:.*srli.b.*test28_v16u8" } } */
 314 /* { dg-final { scan-assembler "test28_v8u16.*:.*srli.h.*test28_v8u16" } } */
 315 /* { dg-final { scan-assembler "test28_v4u32.*:.*srli.w.*test28_v4u32" } } */
 316 /* { dg-final { scan-assembler "test28_v2u64.*:.*srli.d.*test28_v2u64" } } */
 317 /* { dg-final { scan-assembler "test29_v16i8.*:.*slli.b.*test29_v16i8" } } */
 318 /* { dg-final { scan-assembler "test29_v8i16.*:.*slli.h.*test29_v8i16" } } */
 319 /* { dg-final { scan-assembler "test29_v4i32.*:.*slli.w.*test29_v4i32" } } */
 320 /* { dg-final { scan-assembler "test29_v2i64.*:.*slli.d.*test29_v2i64" } } */
 321 /* { dg-final { scan-assembler "test29_v16u8.*:.*slli.b.*test29_v16u8" } } */
 322 /* { dg-final { scan-assembler "test29_v8u16.*:.*slli.h.*test29_v8u16" } } */
 323 /* { dg-final { scan-assembler "test29_v4u32.*:.*slli.w.*test29_v4u32" } } */
 324 /* { dg-final { scan-assembler "test29_v2u64.*:.*slli.d.*test29_v2u64" } } */
 325 /* { dg-final { scan-assembler "test30_v16i8.*:.*ceqi.b.*test30_v16i8" } } */
 326 /* { dg-final { scan-assembler "test30_v8i16.*:.*ceqi.h.*test30_v8i16" } } */
 327 /* { dg-final { scan-assembler "test30_v4i32.*:.*ceqi.w.*test30_v4i32" } } */
 328 /* { dg-final { scan-assembler "test30_v2i64.*:.*ceqi.d.*test30_v2i64" } } */
 329 /* { dg-final { scan-assembler "test30_v16u8.*:.*ceqi.b.*test30_v16u8" } } */
 330 /* { dg-final { scan-assembler "test30_v8u16.*:.*ceqi.h.*test30_v8u16" } } */
 331 /* { dg-final { scan-assembler "test30_v4u32.*:.*ceqi.w.*test30_v4u32" } } */
 332 /* { dg-final { scan-assembler "test30_v2u64.*:.*ceqi.d.*test30_v2u64" } } */
 333 /* { dg-final { scan-assembler "test31_s_v16i8.*:.*clti_s.b.*test31_s_v16i8" } } */
 334 /* { dg-final { scan-assembler "test31_s_v8i16.*:.*clti_s.h.*test31_s_v8i16" } } */
 335 /* { dg-final { scan-assembler "test31_s_v4i32.*:.*clti_s.w.*test31_s_v4i32" } } */
 336 /* { dg-final { scan-assembler "test31_s_v2i64.*:.*clti_s.d.*test31_s_v2i64" } } */
 337 /* { dg-final { scan-assembler "test31_u_v16u8.*:.*clti_u.b.*test31_u_v16u8" } } */
 338 /* { dg-final { scan-assembler "test31_u_v8u16.*:.*clti_u.h.*test31_u_v8u16" } } */
 339 /* { dg-final { scan-assembler "test31_u_v4u32.*:.*clti_u.w.*test31_u_v4u32" } } */
 340 /* { dg-final { scan-assembler "test31_u_v2u64.*:.*clti_u.d.*test31_u_v2u64" } } */
 341 /* { dg-final { scan-assembler "test32_s_v16i8.*:.*clei_s.b.*test32_s_v16i8" } } */
 342 /* { dg-final { scan-assembler "test32_s_v8i16.*:.*clei_s.h.*test32_s_v8i16" } } */
 343 /* { dg-final { scan-assembler "test32_s_v4i32.*:.*clei_s.w.*test32_s_v4i32" } } */
 344 /* { dg-final { scan-assembler "test32_s_v2i64.*:.*clei_s.d.*test32_s_v2i64" } } */
 345 /* { dg-final { scan-assembler "test32_u_v16u8.*:.*clei_u.b.*test32_u_v16u8" } } */
 346 /* { dg-final { scan-assembler "test32_u_v8u16.*:.*clei_u.h.*test32_u_v8u16" } } */
 347 /* { dg-final { scan-assembler "test32_u_v4u32.*:.*clei_u.w.*test32_u_v4u32" } } */
 348 /* { dg-final { scan-assembler "test32_u_v2u64.*:.*clei_u.d.*test32_u_v2u64" } } */
 349 /* { dg-final { scan-assembler "test33_v4f32.*:.*fadd.w.*test33_v4f32" } } */
 350 /* { dg-final { scan-assembler "test33_v2f64.*:.*fadd.d.*test33_v2f64" } } */
 351 /* { dg-final { scan-assembler "test34_v4f32.*:.*fsub.w.*test34_v4f32" } } */
 352 /* { dg-final { scan-assembler "test34_v2f64.*:.*fsub.d.*test34_v2f64" } } */
 353 /* { dg-final { scan-assembler "test35_v4f32.*:.*fmul.w.*test35_v4f32" } } */
 354 /* { dg-final { scan-assembler "test35_v2f64.*:.*fmul.d.*test35_v2f64" } } */
 355 /* { dg-final { scan-assembler "test36_v4f32.*:.*fdiv.w.*test36_v4f32" } } */
 356 /* { dg-final { scan-assembler "test36_v2f64.*:.*fdiv.d.*test36_v2f64" } } */
 357 /* { dg-final { scan-assembler "test37_v16i8.*:.*maddv.b.*test37_v16i8" } } */
 358 /* { dg-final { scan-assembler "test37_v8i16.*:.*maddv.h.*test37_v8i16" } } */
 359 /* { dg-final { scan-assembler "test37_v4i32.*:.*maddv.w.*test37_v4i32" } } */
 360 /* { dg-final { scan-assembler "test37_v2i64.*:.*maddv.d.*test37_v2i64" } } */
 361 /* { dg-final { scan-assembler "test37_v16u8.*:.*maddv.b.*test37_v16u8" } } */
 362 /* { dg-final { scan-assembler "test37_v8u16.*:.*maddv.h.*test37_v8u16" } } */
 363 /* { dg-final { scan-assembler "test37_v4u32.*:.*maddv.w.*test37_v4u32" } } */
 364 /* { dg-final { scan-assembler "test37_v2u64.*:.*maddv.d.*test37_v2u64" } } */
 365 /* { dg-final { scan-assembler "test37_v4f32.*:.*fmadd.w.*test37_v4f32" } } */
 366 /* { dg-final { scan-assembler "test37_v2f64.*:.*fmadd.d.*test37_v2f64" } } */
 367 /* { dg-final { scan-assembler "test38_v16i8.*:.*msubv.b.*test38_v16i8" } } */
 368 /* { dg-final { scan-assembler "test38_v8i16.*:.*msubv.h.*test38_v8i16" } } */
 369 /* { dg-final { scan-assembler "test38_v4i32.*:.*msubv.w.*test38_v4i32" } } */
 370 /* { dg-final { scan-assembler "test38_v2i64.*:.*msubv.d.*test38_v2i64" } } */
 371 /* { dg-final { scan-assembler "test38_v16u8.*:.*msubv.b.*test38_v16u8" } } */
 372 /* { dg-final { scan-assembler "test38_v8u16.*:.*msubv.h.*test38_v8u16" } } */
 373 /* { dg-final { scan-assembler "test38_v4u32.*:.*msubv.w.*test38_v4u32" } } */
 374 /* { dg-final { scan-assembler "test38_v2u64.*:.*msubv.d.*test38_v2u64" } } */
 375 /* { dg-final { scan-assembler "test38_v4f32.*:.*fmsub.w.*test38_v4f32" } } */
 376 /* { dg-final { scan-assembler "test38_v2f64.*:.*fmsub.d.*test38_v2f64" } } */
 377 /* { dg-final { scan-assembler "test39_v16i8.*:.*ld.b.*test39_v16i8" } } */
 378 /* { dg-final { scan-assembler "test39_v8i16.*:.*ld.h.*test39_v8i16" } } */
 379 /* { dg-final { scan-assembler "test39_v4i32.*:.*ld.w.*test39_v4i32" } } */
 380 /* { dg-final { scan-assembler "test39_v2i64.*:.*ld.d.*test39_v2i64" } } */
 381 /* { dg-final { scan-assembler "test40_min_v16i8.*:.*ldi.b\t\\\$w\\d+,-128.*test40_min_v16i8" } } */
 382 /* { dg-final { scan-assembler "test40_min_v8i16.*:.*ldi.h\t\\\$w\\d+,-512.*test40_min_v8i16" } } */
 383 /* { dg-final { scan-assembler "test40_min_v4i32.*:.*ldi.w\t\\\$w\\d+,-512.*test40_min_v4i32" } } */
 384 /* { dg-final { scan-assembler "test40_min_v2i64.*:.*ldi.d\t\\\$w\\d+,-512.*test40_min_v2i64" } } */
 385 /* { dg-final { scan-assembler "test40_max_v16i8.*:.*ldi.b\t\\\$w\\d+,127.*test40_max_v16i8" } } */
 386 /* { dg-final { scan-assembler "test40_max_v8i16.*:.*ldi.h\t\\\$w\\d+,511.*test40_max_v8i16" } } */
 387 /* { dg-final { scan-assembler "test40_max_v4i32.*:.*ldi.w\t\\\$w\\d+,511.*test40_max_v4i32" } } */
 388 /* { dg-final { scan-assembler "test40_max_v2i64.*:.*ldi.d\t\\\$w\\d+,511.*test40_max_v2i64" } } */
 389 /* { dg-final { scan-assembler "test41_v16i8.*:.*fill.b.*test41_v16i8" } } */
 390 /* { dg-final { scan-assembler "test41_v8i16.*:.*fill.h.*test41_v8i16" } } */
 391 /* { dg-final { scan-assembler "test41_v4i32.*:.*fill.w.*test41_v4i32" } } */
 392 /* Note: fill.d only available on MIPS64, replaced with equivalent on MIPS32.  */
 393 /* { dg-final { scan-assembler "test41_v2i64.*:.*fill.d.*test41_v2i64" { target mips64 } } } */
 394 /* { dg-final { scan-assembler "test41_v2i64.*:.*fill.w.*insert.w.*test41_v2i64" { target {! mips64 } } } } */
 395 /* { dg-final { scan-assembler "test42_v16i8.*:.*insert.b.*test42_v16i8" } } */
 396 /* { dg-final { scan-assembler "test42_v8i16.*:.*insert.h.*test42_v8i16" } } */
 397 /* { dg-final { scan-assembler "test42_v4i32.*:.*insert.w.*test42_v4i32" } } */
 398 /* Note: insert.d only available on MIPS64, replaced with equivalent on MIPS32.  */
 399 /* { dg-final { scan-assembler "test42_v2i64.*:.*insert.d.*test42_v2i64" { target mips64 } } } */
 400 /* { dg-final { scan-assembler "test42_v2i64.*:.*\(.*insert.w\)\{2\}.*test42_v2i64" { target {! mips64 } } } } */
 401 /* { dg-final { scan-assembler "test43_v16i8.*:.*insve.b.*test43_v16i8" } } */
 402 /* { dg-final { scan-assembler "test43_v8i16.*:.*insve.h.*test43_v8i16" } } */
 403 /* { dg-final { scan-assembler "test43_v4i32.*:.*insve.w.*test43_v4i32" } } */
 404 /* { dg-final { scan-assembler "test43_v2i64.*:.*insve.d.*test43_v2i64" } } */
 405 /* { dg-final { scan-assembler "test44_v16i8.*:.*copy_s.b.*test44_v16i8" } } */
 406 /* { dg-final { scan-assembler "test44_v8i16.*:.*copy_s.h.*test44_v8i16" } } */
 407 /* { dg-final { scan-assembler "test44_v4i32.*:.*copy_\(s|u\).w.*test44_v4i32" { target {! mips64 } } } } */
 408 /* { dg-final { scan-assembler "test44_v4i32.*:.*copy_s.w.*test44_v4i32" { target mips64 } } } */
 409 /* Note: insert.d only available on MIPS64, replaced with equivalent on MIPS32.  */
 410 /* { dg-final { scan-assembler "test44_v2i64.*:.*copy_s.d.*test44_v2i64" { target mips64 } } } */
 411 /* { dg-final { scan-assembler "test44_v2i64.*:.*\(.*copy_s.w\)\{2\}.*test44_v2i64" { target {! mips64 } } } } */
 412 /* Note: two outputs are possible for unsigned return types, copy unsigned or
 413    copy signed followed by logical AND. For targets where the width of elements
 414    is equal to the register size for that target, logical AND is not emitted/needed.  */
 415 /* { dg-final { scan-assembler "test45_v16u8.*:.*\(copy_u.b|copy_s.b.*andi.*0x\(00\)?ff\).*test45_v16u8" } } */
 416 /* { dg-final { scan-assembler "test45_v8u16.*:.*\(copy_u.h|copy_s.h.*andi.*0xffff\).*test45_v8u16" } } */
 417 /* { dg-final { scan-assembler "test45_v4u32.*:.*\(copy_u.w|copy_s.w\).*test45_v4u32" } } */
 418 /* { dg-final { scan-assembler "test45_v2u64.*:.*\(copy_u.d|copy_s.d\).*test45_v2u64" { target mips64 } } } */
 419 /* { dg-final { scan-assembler "test45_v2u64.*:.*\(\(copy_u|copy_s\).w.*\)\{2\}.*test45_v2u64" { target {! mips64 } } } } */
 420 /* { dg-final { scan-assembler "test46_v16i8.*:.*st.b.*test46_v16i8" } } */
 421 /* { dg-final { scan-assembler "test46_v8i16.*:.*st.h.*test46_v8i16" } } */
 422 /* { dg-final { scan-assembler "test46_v4i32.*:.*st.w.*test46_v4i32" } } */
 423 /* { dg-final { scan-assembler "test46_v2i64.*:.*st.d.*test46_v2i64" } } */
 424
 425 typedef signed char v16i8 __attribute__ ((vector_size(16)));
 426 typedef short v8i16 __attribute__ ((vector_size(16)));
 427 typedef int v4i32 __attribute__ ((vector_size(16)));
 428 typedef long long v2i64 __attribute__ ((vector_size(16)));
 429 typedef unsigned char v16u8 __attribute__ ((vector_size(16)));
 430 typedef unsigned short v8u16 __attribute__ ((vector_size(16)));
 431 typedef unsigned int v4u32 __attribute__ ((vector_size(16)));
 432 typedef unsigned long long v2u64 __attribute__ ((vector_size(16)));
 433 typedef float v4f32 __attribute__ ((vector_size(16)));
 434 typedef double v2f64 __attribute__ ((vector_size(16)));
 435
 436 float imm_f = 37.0;
 437
 438 #define v16i8_DF b
 439 #define v8i16_DF h
 440 #define v4i32_DF w
 441 #define v2i64_DF d
 442 #define v16u8_DF b
 443 #define v8u16_DF h
 444 #define v4u32_DF w
 445 #define v2u64_DF d
 446
 447 #define v16i8_IN int
 448 #define v8i16_IN int
 449 #define v4i32_IN int
 450 #define v2i64_IN long long
 451 #define v16u8_IN int
 452 #define v8u16_IN int
 453 #define v4u32_IN int
 454 #define v2u64_IN long long
 455
 456 #define v16i8_INITV V16
 457 #define v8i16_INITV V8
 458 #define v4i32_INITV V4
 459 #define v2i64_INITV V2
 460 #define v16u8_INITV V16
 461 #define v8u16_INITV V8
 462 #define v4u32_INITV V4
 463 #define v2u64_INITV V2
 464
 465 #define v16i8_LDI_MIN -128
 466 #define v16i8_LDI_MAX 127
 467 #define v8i16_LDI_MIN -512
 468 #define v8i16_LDI_MAX 511
 469 #define v4i32_LDI_MIN -512
 470 #define v4i32_LDI_MAX 511
 471 #define v2i64_LDI_MIN -512
 472 #define v2i64_LDI_MAX 511
 473
 474 #define VE2(VALUE) (VALUE), (VALUE)
 475 #define VE4(VALUE) VE2(VALUE), VE2(VALUE)
 476 #define VE8(VALUE) VE4(VALUE), VE4(VALUE)
 477 #define VE16(VALUE) VE8(VALUE), VE8(VALUE)
 478
 479 #define V16(TYPE, VALUE) (TYPE) { VE16(VALUE) }
 480 #define V8(TYPE, VALUE) (TYPE) { VE8(VALUE) }
 481 #define V4(TYPE, VALUE) (TYPE) { VE4(VALUE) }
 482 #define V2(TYPE, VALUE) (TYPE) { VE2(VALUE) }
 483
 484 #define INIT_VECTOR(TYPE, VALUE) TYPE ## _INITV (TYPE, VALUE)
 485
 486
 487 #define DECLARE(TYPE) TYPE TYPE ## _0, TYPE ## _1, TYPE ## _2;
 488 #define RETURN(TYPE) NOMIPS16 TYPE test0_ ## TYPE () { return TYPE ## _0; }
 489 #define ASSIGN(TYPE) NOMIPS16 void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; }
 490 #define ADD(TYPE) NOMIPS16 TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; }
 491 #define SUB(TYPE) NOMIPS16 TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; }
 492 #define MUL(TYPE) NOMIPS16 TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; }
 493 #define DIV(TYPE) TYPE test5_ ## TYPE (TYPE i, TYPE j) { return i / j; }
 494 #define MOD(TYPE) TYPE test6_ ## TYPE (TYPE i, TYPE j) { return i % j; }
 495 #define MINUS(TYPE) TYPE test7_ ## TYPE (TYPE i) { return -i; }
 496 #define XOR(TYPE) TYPE test8_ ## TYPE (TYPE i, TYPE j) { return i ^ j; }
 497 #define OR(TYPE) TYPE test9_ ## TYPE (TYPE i, TYPE j) { return i | j; }
 498 #define AND(TYPE) TYPE test10_ ## TYPE (TYPE i, TYPE j) { return i & j; }
 499 #define BIT_COMPLEMENT(TYPE) TYPE test11_ ## TYPE (TYPE i) { return ~i; }
 500 #define SHIFT_RIGHT(TYPE) TYPE test12_ ## TYPE (TYPE i, TYPE j) { return i >> j; }
 501 #define SHIFT_LEFT(TYPE) TYPE test13_ ## TYPE (TYPE i, TYPE j) { return i << j; }
 502 #define EQ(TYPE) TYPE test14_ ## TYPE (TYPE i, TYPE j) { return i == j; }
 503 #define NEQ(TYPE) TYPE test15_ ## TYPE (TYPE i, TYPE j) { return i != j; }
 504 #define LT(TYPE) TYPE test16_ ## TYPE (TYPE i, TYPE j) { return i < j; }
 505 #define LEQ(TYPE) TYPE test17_ ## TYPE (TYPE i, TYPE j) { return i <= j; }
 506 #define GT(TYPE) TYPE test18_ ## TYPE (TYPE i, TYPE j) { return i > j; }
 507 #define GEQ(TYPE) TYPE test19_ ## TYPE (TYPE i, TYPE j) { return i >= j; }
 508
 509 #define ADD_I(TYPE) TYPE test20_ ## TYPE (TYPE i) { return i + 31; }
 510 #define SUB_I(TYPE) TYPE test21_ ## TYPE (TYPE i) { return i - 31; }
 511 #define MUL_I(TYPE) TYPE test22_ ## TYPE (TYPE i) { return i * 37; }
 512 #define DIV_I(TYPE) TYPE test23_ ## TYPE (TYPE i) { return i / 37; }
 513 #define MOD_I(TYPE) TYPE test24_ ## TYPE (TYPE i) { return i % 37; }
 514 #define XOR_I(TYPE) TYPE test25_ ## TYPE (TYPE i) { return i ^ 37; }
 515 #define OR_I(TYPE) TYPE test26_ ## TYPE (TYPE i) { return i | 37; }
 516 #define AND_I(TYPE) TYPE test27_ ## TYPE (TYPE i) { return i & 37; }
 517 #define SHIFT_RIGHT_I(TYPE) TYPE test28_ ## TYPE (TYPE i) { return i >> 3; }
 518 #define SHIFT_LEFT_I(TYPE) TYPE test29_ ## TYPE (TYPE i) { return i << 3; }
 519 #define EQ_I(TYPE) TYPE test30_ ## TYPE (TYPE i) { return i == 5; }
 520 #define LT_S_I(TYPE) TYPE test31_s_ ## TYPE (TYPE i) { return i < 5; }
 521 #define LT_U_I(TYPE) TYPE test31_u_ ## TYPE (TYPE i) { return i < (unsigned) 5; }
 522 #define LEQ_S_I(TYPE) TYPE test32_s_ ## TYPE (TYPE i) { return i <= 5; }
 523 #define LEQ_U_I(TYPE) TYPE test32_u_ ## TYPE (TYPE i) { return i <= (unsigned) 5; }
 524
 525 #define ADD_F(TYPE) TYPE test33_ ## TYPE (TYPE i) { return i + imm_f; }
 526 #define SUB_F(TYPE) TYPE test34_ ## TYPE (TYPE i) { return i - imm_f; }
 527 #define MUL_F(TYPE) TYPE test35_ ## TYPE (TYPE i) { return i * imm_f; }
 528 #define DIV_F(TYPE) TYPE test36_ ## TYPE (TYPE i) { return i / imm_f; }
 529
 530 #define MADD(TYPE) TYPE test37_ ## TYPE (TYPE i, TYPE j, TYPE k) { return i * j + k; }
 531 #define MSUB(TYPE) TYPE test38_ ## TYPE (TYPE i, TYPE j, TYPE k) { return k - i * j; }
 532
 533 /* MSA Load/Store and Move instructions */
 534 #define LOAD_V(TYPE) TYPE test39_ ## TYPE (TYPE *i) { return *i; }
 535 #define LOAD_I_MIN(TYPE) TYPE test40_min_ ## TYPE (TYPE *i) { return INIT_VECTOR(TYPE, TYPE ## _LDI_MIN); }
 536 #define LOAD_I_MAX(TYPE) TYPE test40_max_ ## TYPE (TYPE *i) { return INIT_VECTOR(TYPE, TYPE ## _LDI_MAX); }
 537 #define FILL(TYPE) TYPE test41_ ## TYPE (TYPE ## _IN i) { return INIT_VECTOR(TYPE, i); }
 538 #define INSERT(TYPE) TYPE test42_ ## TYPE (TYPE ## _IN i) { TYPE a = INIT_VECTOR(TYPE, 0); a[1] = i; return a; }
 539 #define INSVE(TYPE) TYPE test43_ ## TYPE (TYPE i) { TYPE a = INIT_VECTOR(TYPE, 0); a[1] = i[0]; return a; }
 540 #define COPY_S(TYPE) TYPE ## _IN test44_ ## TYPE (TYPE i) { return i[1]; }
 541 #define COPY_U(TYPE) TYPE ## _IN test45_ ## TYPE (TYPE i) { return i[1]; }
 542 #define STORE_V(TYPE) void test46_ ## TYPE (TYPE i) { TYPE ## _0 = i; }
 543
 544 #define ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(FUNC) \
 545   FUNC (v16i8) \
 546   FUNC (v8i16) \
 547   FUNC (v4i32) \
 548   FUNC (v2i64)
 549
 550 #define ITERATE_FOR_ALL_UNSIGNED_INT_VECTOR_TYPES(FUNC) \
 551   FUNC (v16u8) \
 552   FUNC (v8u16) \
 553   FUNC (v4u32) \
 554   FUNC (v2u64)
 555
 556 #define ITERATE_FOR_ALL_INT_VECTOR_TYPES(FUNC) \
 557  ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(FUNC) \
 558  ITERATE_FOR_ALL_UNSIGNED_INT_VECTOR_TYPES(FUNC)
 559
 560 #define ITERATE_FOR_ALL_INT_TYPES(FUNC) \
 561   ITERATE_FOR_ALL_INT_VECTOR_TYPES(FUNC) \
 562
 563 #define ITERATE_FOR_ALL_REAL_VECTOR_TYPES(FUNC) \
 564   FUNC (v4f32) \
 565   FUNC (v2f64) \
 566
 567 #define ITERATE_FOR_ALL_REAL_SCALAR_TYPES(FUNC) \
 568   FUNC (f64) \
 569   FUNC (f32)
 570
 571 #define ITERATE_FOR_ALL_REAL_TYPES(FUNC) \
 572   ITERATE_FOR_ALL_REAL_VECTOR_TYPES(FUNC) \
 573
 574 #define ITERATE_FOR_ALL_TYPES(FUNC) \
 575   ITERATE_FOR_ALL_INT_TYPES(FUNC) \
 576   ITERATE_FOR_ALL_REAL_TYPES(FUNC)
 577
 578 ITERATE_FOR_ALL_TYPES (ADD)
 579 ITERATE_FOR_ALL_TYPES (SUB)
 580 ITERATE_FOR_ALL_TYPES (MUL)
 581 ITERATE_FOR_ALL_TYPES (DIV)
 582 ITERATE_FOR_ALL_INT_TYPES (MOD)
 583 ITERATE_FOR_ALL_INT_TYPES (XOR)
 584 ITERATE_FOR_ALL_INT_TYPES (OR)
 585 ITERATE_FOR_ALL_INT_TYPES (AND)
 586 ITERATE_FOR_ALL_INT_TYPES (SHIFT_RIGHT)
 587 ITERATE_FOR_ALL_INT_TYPES (SHIFT_LEFT)
 588 ITERATE_FOR_ALL_TYPES (MINUS)
 589 ITERATE_FOR_ALL_INT_TYPES (BIT_COMPLEMENT)
 590 ITERATE_FOR_ALL_TYPES (MADD)
 591 ITERATE_FOR_ALL_TYPES (MSUB)
 592
 593 ITERATE_FOR_ALL_TYPES (DECLARE)
 594 ITERATE_FOR_ALL_TYPES (RETURN)
 595 ITERATE_FOR_ALL_TYPES (ASSIGN)
 596 ITERATE_FOR_ALL_INT_TYPES (ADD_I)
 597 ITERATE_FOR_ALL_INT_TYPES (SUB_I)
 598 ITERATE_FOR_ALL_INT_TYPES (MUL_I)
 599 ITERATE_FOR_ALL_INT_TYPES (DIV_I)
 600 ITERATE_FOR_ALL_INT_TYPES (MOD_I)
 601 ITERATE_FOR_ALL_INT_TYPES (XOR_I)
 602 ITERATE_FOR_ALL_INT_TYPES (OR_I)
 603 ITERATE_FOR_ALL_INT_TYPES (AND_I)
 604 ITERATE_FOR_ALL_INT_TYPES (SHIFT_RIGHT_I)
 605 ITERATE_FOR_ALL_INT_TYPES (SHIFT_LEFT_I)
 606 ITERATE_FOR_ALL_REAL_TYPES (ADD_F)
 607 ITERATE_FOR_ALL_REAL_TYPES (SUB_F)
 608 ITERATE_FOR_ALL_REAL_TYPES (MUL_F)
 609 ITERATE_FOR_ALL_REAL_TYPES (DIV_F)
 610 ITERATE_FOR_ALL_TYPES (EQ)
 611 ITERATE_FOR_ALL_TYPES (EQ_I)
 612 ITERATE_FOR_ALL_TYPES (NEQ)
 613 ITERATE_FOR_ALL_TYPES (LT)
 614 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(LT_S_I)
 615 ITERATE_FOR_ALL_UNSIGNED_INT_VECTOR_TYPES(LT_U_I)
 616 ITERATE_FOR_ALL_TYPES (LEQ)
 617 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(LEQ_S_I)
 618 ITERATE_FOR_ALL_UNSIGNED_INT_VECTOR_TYPES(LEQ_U_I)
 619 ITERATE_FOR_ALL_TYPES (GT)
 620 ITERATE_FOR_ALL_TYPES (GEQ)
 621
 622 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(LOAD_V)
 623 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(LOAD_I_MIN)
 624 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(LOAD_I_MAX)
 625 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(FILL)
 626 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(INSERT)
 627 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(INSVE)
 628 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(COPY_S)
 629 ITERATE_FOR_ALL_UNSIGNED_INT_VECTOR_TYPES(COPY_U)
 630 ITERATE_FOR_ALL_SIGNED_INT_VECTOR_TYPES(STORE_V)