1 ;; Constraint definitions for SPARC.
2 ;; Copyright (C) 2008, 2010 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
25 ;; Register constraints
27 (define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)"
28 "Any floating-point register in VIS mode")
30 (define_register_constraint "c" "FPCC_REGS"
31 "Floating-point condition code register")
33 (define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)"
34 "Lower floating-point register in VIS mode")
36 ;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
37 ;; MD file for V8 and V9.
38 (define_register_constraint "e" "(TARGET_FPU ? (TARGET_V9 ? EXTRA_FP_REGS : FP_REGS) : NO_REGS)"
39 "Any floating-point register")
41 (define_register_constraint "f" "(TARGET_FPU ? FP_REGS : NO_REGS)"
42 "Lower floating-point register")
44 (define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
45 "64-bit global or out register in V8+ mode")
48 ;; Floating-point constant constraints
50 (define_constraint "G"
51 "The floating-point zero constant"
52 (and (match_code "const_double")
53 (match_test "const_zero_operand (op, mode)")))
56 ;; Integer constant constraints
58 (define_constraint "H"
59 "Valid operand of double arithmetic operation"
60 (and (match_code "const_double")
61 (match_test "arith_double_operand (op, DImode)")))
63 (define_constraint "I"
64 "Signed 13-bit integer constant"
65 (and (match_code "const_int")
66 (match_test "SPARC_SIMM13_P (ival)")))
68 (define_constraint "J"
69 "The integer zero constant"
70 (and (match_code "const_int")
71 (match_test "ival == 0")))
73 (define_constraint "K"
74 "Signed 32-bit constant that can be loaded with a sethi instruction"
75 (and (match_code "const_int")
76 (match_test "SPARC_SETHI32_P (ival)")))
78 (define_constraint "L"
79 "Signed 11-bit integer constant"
80 (and (match_code "const_int")
81 (match_test "SPARC_SIMM11_P (ival)")))
83 (define_constraint "M"
84 "Signed 10-bit integer constant"
85 (and (match_code "const_int")
86 (match_test "SPARC_SIMM10_P (ival)")))
88 (define_constraint "N"
89 "Signed constant that can be loaded with a sethi instruction"
90 (and (match_code "const_int")
91 (match_test "SPARC_SETHI_P (ival)")))
93 (define_constraint "O"
95 (and (match_code "const_int")
96 (match_test "ival == 4096")))
100 ;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
101 ;; i.e. accept pseudo-registers during reload.
103 (define_constraint "D"
105 (and (match_code "const_vector")
106 (match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT")))
108 (define_constraint "Q"
109 "Floating-point constant that can be loaded with a sethi instruction"
110 (and (match_code "const_double")
111 (match_test "fp_sethi_p (op)")))
113 (define_constraint "R"
114 "Floating-point constant that can be loaded with a move instruction"
115 (and (match_code "const_double")
116 (match_test "fp_mov_p (op)")))
118 (define_constraint "S"
119 "Floating-point constant that can be loaded with a high/lo_sum sequence"
120 (and (match_code "const_double")
121 (match_test "fp_high_losum_p (op)")))
123 ;; Not needed in 64-bit mode
124 (define_constraint "T"
125 "Memory reference whose address is aligned to 8-byte boundary"
126 (and (match_test "TARGET_ARCH32")
127 (match_code "mem,reg")
128 (match_test "memory_ok_for_ldd (op)")))
130 ;; Not needed in 64-bit mode
131 (define_constraint "U"
132 "Pseudo-register or hard even-numbered integer register"
133 (and (match_test "TARGET_ARCH32")
135 (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
136 (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
137 (match_test "register_ok_for_ldd (op)")))
139 ;; Equivalent to 'T' but available in 64-bit mode
140 (define_constraint "W"
141 "Memory reference for 'e' constraint floating-point register"
142 (and (match_code "mem,reg")
143 (match_test "memory_ok_for_ldd (op)")))
145 (define_constraint "Y"
146 "The vector zero constant"
147 (and (match_code "const_vector")
148 (match_test "const_zero_operand (op, mode)")))