1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005, 2007, 2008, 2010
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; move, push, extend, etc.
24 ;; Be careful to never create an alternative that has memory as both
25 ;; src and dest, as that makes gcc think that mem-mem moves in general
26 ;; are supported. While the chip does support this, it only has two
27 ;; address registers and sometimes gcc requires more than that. One
28 ;; example is code like this: a = *b where both a and b are spilled to
31 (define_insn "mov<mode>_far_op1"
32 [(set (match_operand:QHI 0 "register_operand" "=Rhi")
33 (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "Ra0"))
34 (match_operand 2 "immediate_operand" "si"))))
37 "lde.<bwl>\t%D2[%1],%0"
38 [(set_attr "flags" "sz")]
41 (define_insn "mov<mode>_far_op2"
42 [(set (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "Ra0"))
43 (match_operand 1 "immediate_operand" "si")))
44 (match_operand:QHI 2 "register_operand"
48 "ste.<bwl>\t%2,%D1[%0]"
49 [(set_attr "flags" "sz")]
52 ;; Match push/pop before mov.b for passing char as arg,
53 ;; e.g. stdlib/efgcvt.c.
54 (define_insn "movqi_op"
55 [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
56 "=SF,Rhi*Rmm, Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
57 (match_operand:QI 1 "m32c_any_operand"
58 "Rhi*Rmm,SF, iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
59 "m32c_mov_ok (operands, QImode)"
69 [(set_attr "flags" "sz,sz,sz,*,*,sz,sz,sz")]
72 (define_expand "movqi"
73 [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
74 (match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
76 "if (m32c_prepare_move (operands, QImode)) DONE;"
80 (define_insn "movhi_op"
81 [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
82 "=SF,Rhi*Rmm, Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
83 (match_operand:HI 1 "m32c_any_operand"
84 " Rhi*Rmm,SF, iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
85 "m32c_mov_ok (operands, HImode)"
98 [(set_attr "flags" "sz,sz,sz,sz,sz,n,n,n,n,n,n")]
101 (define_expand "movhi"
102 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
103 (match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
105 "if (m32c_prepare_move (operands, HImode)) DONE;"
109 (define_insn "movpsi_op"
110 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
111 "=Raa, SdRmmRpi, Rcl, RpiSd*Rmm, <, <, Rcl, RpiRaa*Rmm")
112 (match_operand:PSI 1 "m32c_any_operand"
113 "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
114 "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
124 [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
128 ;; The intention here is to combine the add with the move to create an
129 ;; indexed move. GCC doesn't always figure this out itself.
132 [(set (match_operand:HPSI 0 "register_operand" "")
133 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
134 (match_operand:HPSI 2 "immediate_operand" "")))
135 (set (match_operand:QHSI 3 "nonimmediate_operand" "")
136 (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
137 "REGNO (operands[0]) == REGNO (operands[1])
138 && REGNO (operands[0]) == REGNO (operands[4])
139 && (rtx_equal_p (operands[0], operands[3])
140 || (dead_or_set_p (peep2_next_insn (1), operands[4])
141 && ! reg_mentioned_p (operands[0], operands[3])))"
143 (mem:QHSI (plus:HPSI (match_dup 1)
148 [(set (match_operand:HPSI 0 "register_operand" "")
149 (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
150 (match_operand:HPSI 2 "immediate_operand" "")))
151 (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
152 (match_operand:QHSI 3 "m32c_any_operand" ""))]
153 "REGNO (operands[0]) == REGNO (operands[1])
154 && REGNO (operands[0]) == REGNO (operands[4])
155 && dead_or_set_p (peep2_next_insn (1), operands[4])
156 && ! reg_mentioned_p (operands[0], operands[3])"
157 [(set (mem:QHSI (plus:HPSI (match_dup 1)
162 ; Peephole to generate SImode mov instructions for storing an
163 ; immediate double data to a memory location.
165 [(set (match_operand:HI 0 "memory_operand" "")
166 (match_operand 1 "const_int_operand" ""))
167 (set (match_operand:HI 2 "memory_operand" "")
168 (match_operand 3 "const_int_operand" ""))]
169 "TARGET_A24 && m32c_immd_dbl_mov (operands, HImode)"
170 [(set (match_dup 4) (match_dup 5))]
174 ; Some PSI moves must be split.
176 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
177 (match_operand:PSI 1 "m32c_any_operand" ""))]
178 "reload_completed && m32c_split_psi_p (operands)"
183 "m32c_split_move (operands, PSImode, 3);"
186 (define_expand "movpsi"
187 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
188 (match_operand:PSI 1 "m32c_any_operand" ""))]
190 "if (m32c_prepare_move (operands, PSImode)) DONE;"
195 (define_expand "movsi"
196 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
197 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
199 "if (m32c_split_move (operands, SImode, 0)) DONE;"
202 ; All SI moves are split if TARGET_A16
203 (define_insn_and_split "movsi_splittable"
204 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiRaa<*Rmm, RsiRaaSd*Rmm, Ss")
205 (match_operand:SI 1 "m32c_any_operand" "iRsiRaaSd*Rmm, iRsiRaa>*Rmm, RsiRaa*Rmm"))]
210 "m32c_split_move (operands, SImode, 1); DONE;"
213 ; The movsi pattern doesn't always match because sometimes the modes
215 (define_insn "push_a01_l"
216 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
217 (match_operand 0 "a_operand" "Raa"))]
220 [(set_attr "flags" "n")]
223 (define_insn "movsi_24"
224 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi*Rmm, Sd, RsiSd*Rmm, <")
225 (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
232 [(set_attr "flags" "sz,sz,*,n")]
235 (define_expand "movdi"
236 [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
237 (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
239 "if (m32c_split_move (operands, DImode, 0)) DONE;"
242 (define_insn_and_split "movdi_splittable"
243 [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
244 (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
249 "m32c_split_move (operands, DImode, 1); DONE;"
255 (define_insn "pushqi"
256 [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
257 (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
260 [(set_attr "flags" "n")]
263 (define_expand "pushhi"
264 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
265 (match_operand:HI 0 "" ""))]
268 gen_pushhi_16 (operands[0]);
270 gen_pushhi_24 (operands[0]);
274 (define_insn "pushhi_16"
275 [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
276 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
281 [(set_attr "flags" "n,n")]
284 (define_insn "pushhi_24"
285 [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
286 (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
289 [(set_attr "flags" "n")]
292 ;(define_insn "pushpi"
293 ; [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
294 ; (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
301 (define_insn "pushsi"
302 [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
303 (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
306 [(set_attr "flags" "n")]
309 (define_expand "pophi"
310 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
311 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
314 gen_pophi_16 (operands[0]);
316 gen_pophi_24 (operands[0]);
320 (define_insn "pophi_16"
321 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
322 (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
327 [(set_attr "flags" "n,n")]
330 (define_insn "pophi_24"
331 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
332 (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
335 [(set_attr "flags" "n")]
338 (define_insn "poppsi"
339 [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
340 (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
343 [(set_attr "flags" "n")]
347 ;; Rhl used here as an HI-mode Rxl
348 (define_insn "extendqihi2"
349 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
350 (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
353 [(set_attr "flags" "sz")]
356 (define_insn "extendhisi2"
357 [(set (match_operand:SI 0 "register_operand" "=R03")
358 (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
361 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
362 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
363 [(set_attr "flags" "x")]
366 (define_insn "extendhipsi2"
367 [(set (match_operand:PSI 0 "register_operand" "=R03")
368 (sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
371 if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
372 else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
373 [(set_attr "flags" "x")]
376 (define_insn "extendpsisi2"
377 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
378 (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
380 "; expand psi %1 to si %0"
381 [(set_attr "flags" "n")]
384 (define_insn "zero_extendpsisi2"
385 [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
386 (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
388 "; expand psi %1 to si %0"
389 [(set_attr "flags" "n")]
392 (define_insn "zero_extendhipsi2"
393 [(set (match_operand:PSI 0 "register_operand" "=Raa")
394 (truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
397 [(set_attr "flags" "sz")]
400 (define_insn "zero_extendhisi2"
401 [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
402 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
405 [(set_attr "flags" "x")]
408 (define_insn "zero_extendqihi2"
409 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
410 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
415 [(set_attr "flags" "x,x")]
418 (define_insn "truncsipsi2_16"
419 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
420 (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
423 ; no-op trunc si %1 to psi %0
427 [(set_attr "flags" "n,*,n,n")]
430 (define_insn "trunchiqi2"
431 [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
432 (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
434 "; no-op trunc hi %1 to qi %0"
435 [(set_attr "flags" "n")]
438 (define_insn "truncsipsi2_24"
439 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
440 (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
443 ; no-op trunc si %1 to psi %0
447 [(set_attr "flags" "n,sz,n,n")]
450 (define_expand "truncsipsi2"
451 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
452 (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
457 (define_expand "reload_inqi"
458 [(set (match_operand:QI 2 "" "=&Rqi")
459 (match_operand:QI 1 "" ""))
460 (set (match_operand:QI 0 "" "")
466 (define_expand "reload_outqi"
467 [(set (match_operand:QI 2 "" "=&Rqi")
468 (match_operand:QI 1 "" ""))
469 (set (match_operand:QI 0 "" "")
475 (define_expand "reload_inhi"
476 [(set (match_operand:HI 2 "" "=&Rhi")
477 (match_operand:HI 1 "" ""))
478 (set (match_operand:HI 0 "" "")
484 (define_expand "reload_outhi"
485 [(set (match_operand:HI 2 "" "=&Rhi")
486 (match_operand:HI 1 "" ""))
487 (set (match_operand:HI 0 "" "")