1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005, 2007, 2010
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
25 [(set (match_operand:QI 0 "mra_or_sp_operand"
26 "=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm")
27 (plus:QI (match_operand:QI 1 "mra_operand"
29 (match_operand:QI 2 "mrai_operand"
30 "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))]
33 [(set_attr "flags" "oszc")]
37 [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
38 "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp")
39 (plus:HI (match_operand:HI 1 "m32c_any_operand"
40 "%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0")
41 (match_operand:HI 2 "m32c_any_operand"
42 "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))]
55 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")]
58 (define_insn "addpsi3"
59 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi")
60 (plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad")
61 (match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))]
71 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")]
74 (define_expand "addsi3"
75 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
76 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
77 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
78 "TARGET_A24 ||TARGET_A16"
82 (define_insn "addsi3_1"
83 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
84 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
85 (match_operand 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
89 switch (which_alternative)
92 return \"add.w %X2,%h0\;adcf.w %H0\";
94 return \"add.w %X2,%h0\;adcf.w %H0\";
96 if (GET_CODE (operands[2]) == SYMBOL_REF)
98 output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
99 return \"adc.w #%%hi(%d2),%H0\";
103 output_asm_insn (\"add.w %X2,%h0\",operands);
104 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
105 return \"adc.w %X2,%H0\";
108 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
110 output_asm_insn (\"add.w %X2,%h0\",operands);
111 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
112 return \"adc.w %X2,%H0\";
114 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
116 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
118 return \"add.w %h2,%h0\;adc.w %H2,%H0\";
122 [(set_attr "flags" "x,x,x,x,x,x,x,x")]
125 (define_insn "addsi3_2"
126 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
127 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0")
128 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
131 [(set_attr "flags" "oszc")]
134 (define_insn "subqi3"
135 [(set (match_operand:QI 0 "mra_or_sp_operand"
136 "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp")
137 (minus:QI (match_operand:QI 1 "mra_operand"
138 "0,0,0,0, 0,0,0,0, 0")
139 (match_operand:QI 2 "mrai_operand"
140 "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))]
143 [(set_attr "flags" "oszc")]
146 (define_insn "subhi3"
147 [(set (match_operand:HI 0 "mra_operand"
148 "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm")
149 (minus:HI (match_operand:HI 1 "mras_operand"
151 (match_operand:HI 2 "mrai_operand"
152 "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))]
161 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")]
164 (define_insn "subpsi3"
165 [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm")
166 (minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0")
167 (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))]
170 [(set_attr "flags" "oszc")]
173 (define_expand "subsi3"
174 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
175 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
176 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
177 "TARGET_A24 ||TARGET_A16"
181 (define_insn "subsi3_1"
182 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
183 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0")
184 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
187 switch (which_alternative)
190 output_asm_insn (\"sub.w %X2,%h0\",operands);
191 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
192 return \"sbb.w %X2,%H0\";
194 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
196 output_asm_insn (\"sub.w %X2,%h0\",operands);
197 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
198 return \"sbb.w %X2,%H0\";
200 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
202 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
204 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\";
208 [(set_attr "flags" "x,x,x,x,x,x")]
211 (define_insn "subsi3_2"
212 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
213 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0")
214 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))]
217 [(set_attr "flags" "oszc,oszc,oszc,oszc")]
220 (define_insn "negqi2"
221 [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm")
222 (neg:QI (match_operand:QI 1 "mra_operand" "0,0")))]
225 [(set_attr "flags" "oszc,oszc")]
228 (define_insn "neghi2"
229 [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm")
230 (neg:HI (match_operand:HI 1 "mra_operand" "0,0")))]
233 [(set_attr "flags" "oszc,oszc")]
236 ; We can negate an SImode by operating on the subparts. GCC deals
237 ; with this itself for larger modes, but not SI.
238 (define_insn "negsi2"
239 [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm")
240 (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))]
242 "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0"
243 [(set_attr "flags" "x")]
246 (define_insn "absqi2"
247 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
248 (abs:QI (match_operand:QI 1 "mra_operand" "0,0")))]
251 [(set_attr "flags" "oszc")]
254 (define_insn "abshi2"
255 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
256 (abs:HI (match_operand:HI 1 "mra_operand" "0,0")))]
259 [(set_attr "flags" "oszc")]