| blob | b5c0c184a62724dc77ae195b2918bf27c3a7a1b4 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 machine_mode,
422 machine_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1218 }
1219 }
1223 /* Now scan all the insns in forward order. */
1231 {
1237 label_tick++;
1247 {
1261 /* See if we know about function return values before this
1262 insn based upon SUBREG flags. */
1265 /* See if we can find hardregs and subreg of pseudos in
1266 narrower modes. This could help turning TRUNCATEs
1267 into SUBREGs. */
1270 /* Try this insn with each insn it links back to. */
1276 {
1279 }
1281 /* Try each sequence of three linked insns ending with this one. */
1285 {
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1297 {
1300 }
1301 }
1303 /* Try to combine a jump insn that uses CC0
1304 with a preceding insn that sets CC0, and maybe with its
1305 logical predecessor as well.
1306 This is how we make decrement-and-branch insns.
1307 We need this special code because data flow connections
1308 via CC0 do not get entered in LOG_LINKS. */
1315 {
1326 }
1328 /* Do the same for an insn that explicitly references CC0. */
1335 {
1346 }
1348 /* Finally, see if any of the insns that this insn links to
1349 explicitly references CC0. If so, try this insn, that insn,
1350 and its predecessor if it sets CC0. */
1352 {
1364 }
1366 /* Try combining an insn with two different insns whose results it
1367 uses. */
1377 {
1380 }
1382 /* Try four-instruction combinations. */
1385 {
1389 /* If the linked insn has been replaced by a note, then there
1390 is no point in pursuing this chain any further. */
1395 {
1399 /* I0 -> I1 -> I2 -> I3. */
1405 {
1408 }
1409 /* I0, I1 -> I2, I2 -> I3. */
1416 {
1419 }
1420 }
1423 {
1427 /* I0 -> I2; I1, I2 -> I3. */
1433 {
1436 }
1437 /* I0 -> I1; I1, I2 -> I3. */
1443 {
1446 }
1447 }
1448 }
1450 /* Try this insn with each REG_EQUAL note it links back to. */
1452 {
1458 /* Avoid using a register that may already been marked
1459 dead by an earlier instruction. */
1467 {
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1481 last_combined_insn);
1484 {
1487 }
1490 }
1491 }
1496 retry:
1497 ;
1498 }
1499 }
1506 /* Clean up. */
1512 {
1515 {
1518 }
1520 }
1530 /* Make recognizer allow volatile MEMs again. */
1534 }
1536 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1538 static void
1540 {
1546 }
1547 \f
1548 /* Set up any promoted values for incoming argument registers. */
1550 static void
1552 {
1553 tree arg;
1558 {
1563 /* Only continue if the incoming argument is in a register. */
1567 /* Determine, if possible, whether all call sites of the current
1568 function lie within the current compilation unit. (This does
1569 take into account the exporting of a function via taking its
1570 address, and so forth.) */
1573 /* The mode and signedness of the argument before any promotions happen
1574 (equal to the mode of the pseudo holding it at that stage). */
1578 /* The mode and signedness of the argument after any source language and
1579 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1583 /* The mode and signedness of the argument as it is actually passed,
1584 see assign_parm_setup_reg in function.c. */
1588 /* The mode of the register in which the argument is being passed. */
1591 /* Eliminate sign extensions in the callee when:
1592 (a) A mode promotion has occurred; */
1595 /* (b) The mode of the register is the same as the mode of
1596 the argument as it is passed; */
1599 /* (c) There's no language level extension; */
1601 ;
1602 /* (c.1) All callers are from the current compilation unit. If that's
1603 the case we don't have to rely on an ABI, we only have to know
1604 what we're generating right now, and we know that we will do the
1605 mode1 to mode2 promotion with the given sign. */
1608 /* (c.2) The combination of the two promotions is useful. This is
1609 true when the signs match, or if the first promotion is unsigned.
1610 In the later case, (sign_extend (zero_extend x)) is the same as
1611 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1617 /* Record that the value was promoted from mode1 to mode3,
1618 so that any sign extension at the head of the current
1619 function may be eliminated. */
1623 }
1624 }
1626 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1627 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1628 because some machines (maybe most) will actually do the sign-extension and
1629 this is the conservative approach.
1631 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1632 kludge. */
1634 static rtx
1636 {
1644 }
1646 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1647 and SET. */
1649 static void
1651 rtx x)
1652 {
1662 {
1666 }
1668 /* Don't call nonzero_bits if it cannot change anything. */
1670 {
1675 }
1677 /* Don't call num_sign_bit_copies if it cannot change anything. */
1679 {
1682 {
1686 }
1689 }
1690 }
1692 /* Called via note_stores. If X is a pseudo that is narrower than
1693 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1695 If we are setting only a portion of X and we can't figure out what
1696 portion, assume all bits will be used since we don't know what will
1697 be happening.
1699 Similarly, set how many bits of X are known to be copies of the sign bit
1700 at all locations in the function. This is the smallest number implied
1701 by any set of X. */
1703 static void
1705 {
1710 /* If this register is undefined at the start of the file, we can't
1711 say what its contents were. */
1712 && ! REGNO_REG_SET_P
1715 {
1719 {
1723 }
1725 /* If this register is being initialized using itself, and the
1726 register is uninitialized in this basic block, and there are
1727 no LOG_LINKS which set the register, then part of the
1728 register is uninitialized. In that case we can't assume
1729 anything about the number of nonzero bits.
1731 ??? We could do better if we checked this in
1732 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1733 could avoid making assumptions about the insn which initially
1734 sets the register, while still using the information in other
1735 insns. We would have to be careful to check every insn
1736 involved in the combination. */
1742 {
1749 {
1753 }
1754 }
1756 /* If this is a complex assignment, see if we can convert it into a
1757 simple assignment. */
1760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1761 set what we know about X. */
1767 else
1768 {
1771 }
1772 }
1773 }
1774 \f
1775 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1776 optionally insns that were previously combined into I3 or that will be
1777 combined into the merger of INSN and I3. The order is PRED, PRED2,
1778 INSN, SUCC, SUCC2, I3.
1780 Return 0 if the combination is not allowed for any reason.
1782 If the combination is allowed, *PDEST will be set to the single
1783 destination of INSN and *PSRC to the single source, and this function
1784 will return 1. */
1786 static int
1790 {
1795 rtx link;
1800 {
1802 {
1807 }
1812 }
1816 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1817 or a PARALLEL consisting of such a SET and CLOBBERs.
1819 If INSN has CLOBBER parallel parts, ignore them for our processing.
1820 By definition, these happen during the execution of the insn. When it
1821 is merged with another insn, all bets are off. If they are, in fact,
1822 needed and aren't also supplied in I3, they may be added by
1823 recog_for_combine. Otherwise, it won't match.
1825 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1826 note.
1828 Get the source and destination of INSN. If more than one, can't
1829 combine. */
1835 {
1837 {
1841 {
1842 /* This is important to combine floating point insns
1843 for the SH4 port. */
1845 /* Combining an isolated USE doesn't make sense.
1846 We depend here on combinable_i3pat to reject them. */
1847 /* The code below this loop only verifies that the inputs of
1848 the SET in INSN do not change. We call reg_set_between_p
1849 to verify that the REG in the USE does not change between
1850 I3 and INSN.
1851 If the USE in INSN was for a pseudo register, the matching
1852 insn pattern will likely match any register; combining this
1853 with any other USE would only be safe if we knew that the
1854 used registers have identical values, or if there was
1855 something to tell them apart, e.g. different modes. For
1856 now, we forgo such complicated tests and simply disallow
1857 combining of USES of pseudo registers with any other USE. */
1860 {
1865 do
1866 {
1876 }
1878 }
1881 /* We can ignore CLOBBERs. */
1886 /* Ignore SETs whose result isn't used but not those that
1887 have side-effects. */
1893 /* If we have already found a SET, this is a second one and
1894 so we cannot combine with this insn. */
1902 /* Anything else means we can't combine. */
1904 }
1905 }
1908 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1909 so don't do anything with it. */
1912 }
1913 else
1919 /* The simplification in expand_field_assignment may call back to
1920 get_last_value, so set safe guard here. */
1926 /* Do not eliminate user-specified register if it is in an
1927 asm input because we may break the register asm usage defined
1928 in GCC manual if allow to do so.
1929 Be aware that this may cover more cases than we expect but this
1930 should be harmless. */
1935 /* Don't eliminate a store in the stack pointer. */
1937 /* Don't combine with an insn that sets a register to itself if it has
1938 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1940 /* Can't merge an ASM_OPERANDS. */
1942 /* Can't merge a function call. */
1944 /* Don't eliminate a function call argument. */
1950 /* Don't substitute into an incremented register. */
1954 /* Don't substitute into a non-local goto, this confuses CFG. */
1956 /* Make sure that DEST is not used after SUCC but before I3. */
1957 || (!all_adjacent
1958 && ((succ2
1962 /* Make sure that the value that is to be substituted for the register
1963 does not use any registers whose values alter in between. However,
1964 If the insns are adjacent, a use can't cross a set even though we
1965 think it might (this can happen for a sequence of insns each setting
1966 the same destination; last_set of that register might point to
1967 a NOTE). If INSN has a REG_EQUIV note, the register is always
1968 equivalent to the memory so the substitution is valid even if there
1969 are intervening stores. Also, don't move a volatile asm or
1970 UNSPEC_VOLATILE across any other insns. */
1971 || (! all_adjacent
1977 /* Don't combine across a CALL_INSN, because that would possibly
1978 change whether the life span of some REGs crosses calls or not,
1979 and it is a pain to update that information.
1980 Exception: if source is a constant, moving it later can't hurt.
1981 Accept that as a special case. */
1985 /* DEST must either be a REG or CC0. */
1987 {
1988 /* If register alignment is being enforced for multi-word items in all
1989 cases except for parameters, it is possible to have a register copy
1990 insn referencing a hard register that is not allowed to contain the
1991 mode being copied and which would not be valid as an operand of most
1992 insns. Eliminate this problem by not combining with such an insn.
1994 Also, on some machines we don't want to extend the life of a hard
1995 register. */
2000 /* Don't extend the life of a hard register unless it is
2001 user variable (if we have few registers) or it can't
2002 fit into the desired register (meaning something special
2003 is going on).
2004 Also avoid substituting a return register into I3, because
2005 reload can't handle a conflict with constraints of other
2006 inputs. */
2010 }
2018 {
2021 /* If the clobber represents an earlyclobber operand, we must not
2022 substitute an expression containing the clobbered register.
2023 As we do not analyze the constraint strings here, we have to
2024 make the conservative assumption. However, if the register is
2025 a fixed hard reg, the clobber cannot represent any operand;
2026 we leave it up to the machine description to either accept or
2027 reject use-and-clobber patterns. */
2033 }
2035 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2036 or not), reject, unless nothing volatile comes between it and I3 */
2039 {
2040 /* Make sure neither succ nor succ2 contains a volatile reference. */
2045 /* We'll check insns between INSN and I3 below. */
2046 }
2048 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2049 to be an explicit register variable, and was chosen for a reason. */
2055 /* If INSN contains volatile references (specifically volatile MEMs),
2056 we cannot combine across any other volatile references.
2057 Even if INSN doesn't contain volatile references, any intervening
2058 volatile insn might affect machine state. */
2061 ? volatile_refs_p
2068 /* If INSN contains an autoincrement or autodecrement, make sure that
2069 register is not used between there and I3, and not already used in
2070 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2071 Also insist that I3 not be a jump; if it were one
2072 and the incremented register were spilled, we would lose. */
2090 /* Don't combine an insn that follows a CC0-setting insn.
2091 An insn that uses CC0 must not be separated from the one that sets it.
2092 We do, however, allow I2 to follow a CC0-setting insn if that insn
2093 is passed as I1; in that case it will be deleted also.
2094 We also allow combining in this case if all the insns are adjacent
2095 because that would leave the two CC0 insns adjacent as well.
2096 It would be more logical to test whether CC0 occurs inside I1 or I2,
2097 but that would be much slower, and this ought to be equivalent. */
2100 {
2105 }
2107 /* If we get here, we have passed all the tests and the combination is
2108 to be allowed. */
2114 }
2115 \f
2116 /* LOC is the location within I3 that contains its pattern or the component
2117 of a PARALLEL of the pattern. We validate that it is valid for combining.
2119 One problem is if I3 modifies its output, as opposed to replacing it
2120 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2121 doing so would produce an insn that is not equivalent to the original insns.
2123 Consider:
2125 (set (reg:DI 101) (reg:DI 100))
2126 (set (subreg:SI (reg:DI 101) 0) <foo>)
2128 This is NOT equivalent to:
2130 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2131 (set (reg:DI 101) (reg:DI 100))])
2133 Not only does this modify 100 (in which case it might still be valid
2134 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2136 We can also run into a problem if I2 sets a register that I1
2137 uses and I1 gets directly substituted into I3 (not via I2). In that
2138 case, we would be getting the wrong value of I2DEST into I3, so we
2139 must reject the combination. This case occurs when I2 and I1 both
2140 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2141 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2142 of a SET must prevent combination from occurring. The same situation
2143 can occur for I0, in which case I0_NOT_IN_SRC is set.
2145 Before doing the above check, we first try to expand a field assignment
2146 into a set of logical operations.
2148 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2149 we place a register that is both set and used within I3. If more than one
2150 such register is detected, we fail.
2152 Return 1 if the combination is valid, zero otherwise. */
2154 static int
2157 {
2161 {
2166 rtx subdest;
2173 /* Check for the case where I3 modifies its output, as discussed
2174 above. We don't want to prevent pseudos from being combined
2175 into the address of a MEM, so only prevent the combination if
2176 i1 or i2 set the same MEM. */
2186 /* This is the same test done in can_combine_p except we can't test
2187 all_adjacent; we don't have to, since this instruction will stay
2188 in place, thus we are not considering increasing the lifetime of
2189 INNER_DEST.
2191 Also, if this insn sets a function argument, combining it with
2192 something that might need a spill could clobber a previous
2193 function argument; the all_adjacent test in can_combine_p also
2194 checks this; here, we do a more specific test for this case. */
2204 /* If DEST is used in I3, it is being killed in this insn, so
2205 record that for later. We have to consider paradoxical
2206 subregs here, since they kill the whole register, but we
2207 ignore partial subregs, STRICT_LOW_PART, etc.
2208 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2209 STACK_POINTER_REGNUM, since these are always considered to be
2210 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2220 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2226 {
2231 }
2232 }
2235 {
2242 }
2245 }
2246 \f
2247 /* Return 1 if X is an arithmetic expression that contains a multiplication
2248 and division. We don't count multiplications by powers of two here. */
2250 static int
2252 {
2254 {
2270 }
2271 }
2272 \f
2273 /* Determine whether INSN can be used in a combination. Return nonzero if
2274 not. This is used in try_combine to detect early some cases where we
2275 can't perform combinations. */
2277 static int
2279 {
2280 rtx set;
2283 /* If this isn't really an insn, we can't do anything.
2284 This can occur when flow deletes an insn that it has merged into an
2285 auto-increment address. */
2289 /* Never combine loads and stores involving hard regs that are likely
2290 to be spilled. The register allocator can usually handle such
2291 reg-reg moves by tying. If we allow the combiner to make
2292 substitutions of likely-spilled regs, reload might die.
2293 As an exception, we allow combinations involving fixed regs; these are
2294 not available to the register allocator so there's no risk involved. */
2315 }
2317 struct likely_spilled_retval_info
2318 {
2321 };
2323 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2324 hard registers that are known to be written to / clobbered in full. */
2325 static void
2327 {
2344 else
2347 }
2349 /* Return nonzero iff part of the return value is live during INSN, and
2350 it is likely spilled. This can happen when more than one insn is needed
2351 to copy the return value, e.g. when we consider to combine into the
2352 second copy insn for a complex value. */
2354 static int
2356 {
2358 rtx reg;
2361 /* We assume here that no machine mode needs more than
2362 32 hard registers when the value overlaps with a register
2363 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2378 /* Disregard parts of the return value that are set later. */
2387 /* Check if any of the (probably) live return value registers is
2388 likely spilled. */
2389 nregs --;
2390 do
2391 {
2397 }
2399 /* Adjust INSN after we made a change to its destination.
2401 Changing the destination can invalidate notes that say something about
2402 the results of the insn and a LOG_LINK pointing to the insn. */
2404 static void
2406 {
2407 /* For notes, be conservative and simply remove them. */
2410 /* The new insn will have a destination that was previously the destination
2411 of an insn just above it. Call distribute_links to make a LOG_LINK from
2412 the next use of that destination. */
2428 }
2430 /* Return TRUE if combine can reuse reg X in mode MODE.
2431 ADDED_SETS is nonzero if the original set is still required. */
2432 static bool
2434 {
2441 /* Allow hard registers if the new mode is legal, and occupies no more
2442 registers than the old mode. */
2447 /* Or a pseudo that is only used once. */
2450 && !added_sets
2452 }
2455 /* Check whether X, the destination of a set, refers to part of
2456 the register specified by REG. */
2458 static bool
2460 {
2461 /* Check that reg is an integer mode register. */
2472 }
2474 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2475 Note that the INSN should be deleted *after* removing dead edges, so
2476 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2477 but not for a (set (pc) (label_ref FOO)). */
2479 static void
2481 {
2489 {
2494 /* Remove barriers from the footer if there are any. */
2497 {
2500 else
2504 }
2507 }
2508 }
2510 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2511 by an arbitrary number of CLOBBERs. */
2512 static bool
2514 {
2533 }
2535 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2536 CLOBBERs), can be split into individual SETs in that order, without
2537 changing semantics. */
2538 static bool
2540 {
2548 {
2557 }
2560 }
2562 /* Try to combine the insns I0, I1 and I2 into I3.
2563 Here I0, I1 and I2 appear earlier than I3.
2564 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2565 I3.
2567 If we are combining more than two insns and the resulting insn is not
2568 recognized, try splitting it into two insns. If that happens, I2 and I3
2569 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2570 Otherwise, I0, I1 and I2 are pseudo-deleted.
2572 Return 0 if the combination does not work. Then nothing is changed.
2573 If we did the combination, return the insn at which combine should
2574 resume scanning.
2576 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2577 new direct jump instruction.
2579 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2580 been I3 passed to an earlier try_combine within the same basic
2581 block. */
2586 {
2587 /* New patterns for I3 and I2, respectively. */
2591 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2592 dead. */
2594 /* Total number of SETs to put into I3. */
2596 /* Nonzero if I2's or I1's body now appears in I3. */
2598 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2600 /* Contains I3 if the destination of I3 is used in its source, which means
2601 that the old life of I3 is being killed. If that usage is placed into
2602 I2 and not in I3, a REG_DEAD note must be made. */
2604 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2606 /* Copy of SET_SRC of I1 and I0, if needed. */
2608 /* Set if I2DEST was reused as a scratch register. */
2610 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2612 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2617 /* Notes that must be added to REG_NOTES in I3 and I2. */
2619 /* Notes that we substituted I3 into I2 instead of the normal case. */
2621 /* Notes that I1, I2 or I3 is a MULT operation. */
2628 rtx temp_expr;
2631 rtx new_other_notes;
2634 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2635 never be). */
2639 /* Only try four-insn combinations when there's high likelihood of
2640 success. Look for simple insns, such as loads of constants or
2641 binary operations involving a constant. */
2643 {
2653 {
2656 rtx src;
2661 {
2664 }
2666 ngood++;
2669 nshift++;
2670 }
2672 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2673 are likely manipulating its value. Ideally we'll be able to combine
2674 all four insns into a bitfield insertion of some kind.
2676 Note the source in I0 might be inside a sign/zero extension and the
2677 memory modes in I0 and I3 might be different. So extract the address
2678 from the destination of I3 and search for it in the source of I0.
2680 In the event that there's a match but the source/dest do not actually
2681 refer to the same memory, the worst that happens is we try some
2682 combinations that we wouldn't have otherwise. */
2684 /* Ensure the source of SET0 is a MEM, possibly buried inside
2685 an extension. */
2691 /* Ensure the destination of SET3 is a MEM. */
2693 /* Would it be better to extract the base address for the MEM
2694 in SET3 and look for that? I don't have cases where it matters
2695 but I could envision such cases. */
2701 }
2703 /* Exit early if one of the insns involved can't be used for
2704 combinations. */
2715 combine_attempts++;
2718 /* Reset the hard register usage information. */
2722 {
2729 else
2732 }
2734 /* If multiple insns feed into one of I2 or I3, they can be in any
2735 order. To simplify the code below, reorder them in sequence. */
2745 /* First check for one important special case that the code below will
2746 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2747 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2748 we may be able to replace that destination with the destination of I3.
2749 This occurs in the common code where we compute both a quotient and
2750 remainder into a structure, in which case we want to do the computation
2751 directly into the structure to avoid register-register copies.
2753 Note that this case handles both multiple sets in I2 and also cases
2754 where I2 has a number of CLOBBERs inside the PARALLEL.
2756 We make very conservative checks below and only try to handle the
2757 most common cases of this. For example, we only handle the case
2758 where I2 and I3 are adjacent to avoid making difficult register
2759 usage tests. */
2767 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2768 below would need to check what is inside (and reg_overlap_mentioned_p
2769 doesn't support those codes anyway). Don't allow those destinations;
2770 the resulting insn isn't likely to be recognized anyway. */
2776 {
2779 /* Make sure that the destination of I3,
2780 which we are going to substitute into one output of I2,
2781 is not used within another output of I2. We must avoid making this:
2782 (parallel [(set (mem (reg 69)) ...)
2783 (set (reg 69) ...)])
2784 which is not well-defined as to order of actions.
2785 (Besides, reload can't handle output reloads for this.)
2787 The problem can also happen if the dest of I3 is a memory ref,
2788 if another dest in I2 is an indirect memory ref.
2790 Neither can this PARALLEL be an asm. We do not allow combining
2791 that usually (see can_combine_p), so do not here either. */
2794 {
2803 }
2809 {
2810 combine_merges++;
2820 /* Replace the dest in I2 with our dest and make the resulting
2821 insn the new pattern for I3. Then skip to where we validate
2822 the pattern. Everything was set up above. */
2827 }
2828 }
2830 /* If I2 is setting a pseudo to a constant and I3 is setting some
2831 sub-part of it to another constant, merge them by making a new
2832 constant. */
2839 {
2845 {
2848 {
2854 }
2855 }
2856 else
2857 {
2862 }
2865 {
2866 /* If this is the low part, we're done. */
2868 ;
2869 /* Handle the case where inner is twice the size of outer. */
2873 /* Otherwise give up for now. */
2874 else
2876 }
2879 {
2883 wide_int o
2888 combine_merges++;
2895 /* Replace the source in I2 with the new constant and make the
2896 resulting insn the new pattern for I3. Then skip to where we
2897 validate the pattern. Everything was set up above. */
2903 /* The dest of I3 has been replaced with the dest of I2. */
2906 }
2907 }
2909 /* If we have no I1 and I2 looks like:
2910 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2911 (set Y OP)])
2912 make up a dummy I1 that is
2913 (set Y OP)
2914 and change I2 to be
2915 (set (reg:CC X) (compare:CC Y (const_int 0)))
2917 (We can ignore any trailing CLOBBERs.)
2919 This undoes a previous combination and allows us to match a branch-and-
2920 decrement insn. */
2932 {
2933 /* We make I1 with the same INSN_UID as I2. This gives it
2934 the same DF_INSN_LUID for value tracking. Our fake I1 will
2935 never appear in the insn stream so giving it the same INSN_UID
2936 as I2 will not cause a problem. */
2949 }
2951 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2952 make those two SETs separate I1 and I2 insns, and make an I0 that is
2953 the original I1. */
2959 {
2960 /* If there is no I1, there is no I0 either. */
2963 /* We make I1 with the same INSN_UID as I2. This gives it
2964 the same DF_INSN_LUID for value tracking. Our fake I1 will
2965 never appear in the insn stream so giving it the same INSN_UID
2966 as I2 will not cause a problem. */
2974 }
2976 /* Verify that I2 and I1 are valid for combining. */
2982 {
2985 }
2987 /* Record whether I2DEST is used in I2SRC and similarly for the other
2988 cases. Knowing this will help in register status updating below. */
2999 /* For the earlier insns, determine which of the subsequent ones they
3000 feed. */
3007 /* Ensure that I3's pattern can be the destination of combines. */
3013 {
3016 }
3018 /* See if any of the insns is a MULT operation. Unless one is, we will
3019 reject a combination that is, since it must be slower. Be conservative
3020 here. */
3028 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3029 We used to do this EXCEPT in one case: I3 has a post-inc in an
3030 output operand. However, that exception can give rise to insns like
3031 mov r3,(r3)+
3032 which is a famous insn on the PDP-11 where the value of r3 used as the
3033 source was model-dependent. Avoid this sort of thing. */
3035 #if 0
3041 /* It's not the exception. */
3042 #endif
3044 {
3045 rtx link;
3051 {
3054 }
3055 }
3057 /* See if the SETs in I1 or I2 need to be kept around in the merged
3058 instruction: whenever the value set there is still needed past I3.
3059 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3061 For the SET in I1, we have two cases: if I1 and I2 independently feed
3062 into I3, the set in I1 needs to be kept around unless I1DEST dies
3063 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3064 in I1 needs to be kept around unless I1DEST dies or is set in either
3065 I2 or I3. The same considerations apply to I0. */
3072 else
3080 else
3083 /* We are about to copy insns for the case where they need to be kept
3084 around. Check that they can be copied in the merged instruction. */
3090 {
3093 }
3095 /* If the set in I2 needs to be kept around, we must make a copy of
3096 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3097 PATTERN (I2), we are only substituting for the original I1DEST, not into
3098 an already-substituted copy. This also prevents making self-referential
3099 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3100 I2DEST. */
3103 {
3106 else
3108 }
3111 {
3114 else
3116 }
3119 {
3122 else
3124 }
3126 combine_merges++;
3128 /* Substitute in the latest insn for the regs set by the earlier ones. */
3134 /* Many machines that don't use CC0 have insns that can both perform an
3135 arithmetic operation and set the condition code. These operations will
3136 be represented as a PARALLEL with the first element of the vector
3137 being a COMPARE of an arithmetic operation with the constant zero.
3138 The second element of the vector will set some pseudo to the result
3139 of the same arithmetic operation. If we simplify the COMPARE, we won't
3140 match such a pattern and so will generate an extra insn. Here we test
3141 for this case, where both the comparison and the operation result are
3142 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3143 I2SRC. Later we will make the PARALLEL that contains I2. */
3149 {
3150 rtx newpat_dest;
3164 {
3169 }
3171 /* Do the rest only if op1 is const0_rtx, which may be the
3172 result of simplification. */
3174 {
3175 /* If a single use of the CC is found, prepare to modify it
3176 when SELECT_CC_MODE returns a new CC-class mode, or when
3177 the above simplify_compare_const() returned a new comparison
3178 operator. undobuf.other_insn is assigned the CC use insn
3179 when modifying it. */
3181 {
3182 #ifdef SELECT_CC_MODE
3183 machine_mode new_mode
3188 {
3193 else
3194 {
3197 }
3198 }
3199 #endif
3200 /* Cases for modifying the CC-using comparison. */
3202 /* ??? Do we need to verify the zero rtx? */
3204 {
3205 /* Replace cc_use_loc with entire new RTX. */
3210 }
3212 {
3213 /* Just replace the CC reg with a new mode. */
3216 }
3217 }
3219 /* Now we modify the current newpat:
3220 First, SET_DEST(newpat) is updated if the CC mode has been
3221 altered. For targets without SELECT_CC_MODE, this should be
3222 optimized away. */
3225 /* This is always done to propagate i2src into newpat. */
3228 /* Create new version of i2pat if needed; the below PARALLEL
3229 creation needs this to work correctly. */
3233 }
3234 }
3237 {
3238 /* It is possible that the source of I2 or I1 may be performing
3239 an unneeded operation, such as a ZERO_EXTEND of something
3240 that is known to have the high part zero. Handle that case
3241 by letting subst look at the inner insns.
3243 Another way to do this would be to have a function that tries
3244 to simplify a single insn instead of merging two or more
3245 insns. We don't do this because of the potential of infinite
3246 loops and because of the potential extra memory required.
3247 However, doing it the way we are is a bit of a kludge and
3248 doesn't catch all cases.
3250 But only do this if -fexpensive-optimizations since it slows
3251 things down and doesn't usually win.
3253 This is not done in the COMPARE case above because the
3254 unmodified I2PAT is used in the PARALLEL and so a pattern
3255 with a modified I2SRC would not match. */
3258 {
3259 /* Pass pc_rtx so no substitutions are done, just
3260 simplifications. */
3262 {
3265 }
3269 }
3274 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3275 copy of I2SRC each time we substitute it, in order to avoid creating
3276 self-referential RTL when we will be substituting I1SRC for I1DEST
3277 later. Likewise if I0 feeds into I2, either directly or indirectly
3278 through I1, and I0DEST is in I0SRC. */
3285 /* Record whether I2's body now appears within I3's body. */
3287 }
3289 /* If we already got a failure, don't try to do more. Otherwise, try to
3290 substitute I1 if we have it. */
3293 {
3294 /* Check that an autoincrement side-effect on I1 has not been lost.
3295 This happens if I1DEST is mentioned in I2 and dies there, and
3296 has disappeared from the new pattern. */
3298 && i1_feeds_i2_n
3301 /* Before we can do this substitution, we must redo the test done
3302 above (see detailed comments there) that ensures I1DEST isn't
3303 mentioned in any SETs in NEWPAT that are field assignments. */
3306 {
3309 }
3314 /* If the following substitution will modify I1SRC, make a copy of it
3315 for the case where it is substituted for I1DEST in I2PAT later. */
3319 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3320 copy of I1SRC each time we substitute it, in order to avoid creating
3321 self-referential RTL when we will be substituting I0SRC for I0DEST
3322 later. */
3327 /* Record whether I1's body now appears within I3's body. */
3329 }
3331 /* Likewise for I0 if we have it. */
3334 {
3341 {
3344 }
3346 /* If the following substitution will modify I0SRC, make a copy of it
3347 for the case where it is substituted for I0DEST in I1PAT later. */
3350 /* And a copy for I0DEST in I2PAT substitution. */
3359 }
3361 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3362 to count all the ways that I2SRC and I1SRC can be used. */
3373 /* Fail if we tried to make a new register. */
3375 /* Fail if we couldn't do something and have a CLOBBER. */
3377 /* Fail if this new pattern is a MULT and we didn't have one before
3378 at the outer level. */
3381 {
3384 }
3386 /* If the actions of the earlier insns must be kept
3387 in addition to substituting them into the latest one,
3388 we must make a new PARALLEL for the latest insn
3389 to hold additional the SETs. */
3392 {
3394 combine_extras++;
3397 {
3403 }
3404 else
3405 {
3410 }
3416 {
3422 }
3424 {
3433 }
3434 }
3436 validate_replacement:
3438 /* Note which hard regs this insn has as inputs. */
3441 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3442 consider splitting this pattern, we might need these clobbers. */
3445 {
3451 }
3453 /* We have recognized nothing yet. */
3456 /* See if this is a PARALLEL of two SETs where one SET's destination is
3457 a register that is unused and this isn't marked as an instruction that
3458 might trap in an EH region. In that case, we just need the other SET.
3459 We prefer this over the PARALLEL.
3461 This can occur when simplifying a divmod insn. We *must* test for this
3462 case here because the code below that splits two independent SETs doesn't
3463 handle this case correctly when it updates the register status.
3465 It's pointless doing this if we originally had two sets, one from
3466 i3, and one from i2. Combining then splitting the parallel results
3467 in the original i2 again plus an invalid insn (which we delete).
3468 The net effect is only to move instructions around, which makes
3469 debug info less accurate. */
3474 {
3485 {
3488 }
3497 {
3503 }
3507 }
3509 /* Is the result of combination a valid instruction? */
3513 /* If we were combining three insns and the result is a simple SET
3514 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3515 insns. There are two ways to do this. It can be split using a
3516 machine-specific method (like when you have an addition of a large
3517 constant) or by combine in the function find_split_point. */
3521 {
3525 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3526 use I2DEST as a scratch register will help. In the latter case,
3527 convert I2DEST to the mode of the source of NEWPAT if we can. */
3531 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3532 inputs of NEWPAT. */
3534 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3535 possible to try that as a scratch reg. This would require adding
3536 more code to make it work though. */
3539 {
3542 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3543 (temporarily, until we are committed to this instruction
3544 combination) does not work: for example, any call to nonzero_bits
3545 on the register (from a splitter in the MD file, for example)
3546 will get the old information, which is invalid.
3548 Since nowadays we can create registers during combine just fine,
3549 we should just create a new one here, not reuse i2dest. */
3551 /* First try to split using the original register as a
3552 scratch register. */
3556 i2dest)));
3559 /* If that didn't work, try changing the mode of I2DEST if
3560 we can. */
3565 {
3567 rtx ni2dest;
3571 else
3572 {
3575 }
3577 parallel = (gen_rtx_PARALLEL
3581 ni2dest))));
3586 {
3594 }
3595 }
3598 }
3600 /* If recog_for_combine has discarded clobbers, try to use them
3601 again for the split. */
3603 {
3606 }
3609 {
3614 }
3618 {
3628 /* If I2 or I3 has multiple SETs, we won't know how to track
3629 register status, so don't use these insns. If I2's destination
3630 is used between I2 and I3, we also can't use these insns. */
3640 /* It is possible that both insns now set the destination of I3.
3641 If so, we must show an extra use of it. */
3644 {
3663 }
3664 }
3666 /* If we can split it and use I2DEST, go ahead and see if that
3667 helps things be recognized. Verify that none of the registers
3668 are set between I2 and I3. */
3672 /* We need I2DEST in the proper mode. If it is a hard register
3673 or the only use of a pseudo, we can change its mode.
3674 Make sure we don't change a hard register to have a mode that
3675 isn't valid for it, or change the number of registers. */
3682 /* We can't overwrite I2DEST if its value is still used by
3683 NEWPAT. */
3685 {
3694 /* *SPLIT may be part of I2SRC, so make sure we have the
3695 original expression around for later debug processing.
3696 We should not need I2SRC any more in other cases. */
3699 else
3702 /* Get NEWDEST as a register in the proper mode. We have already
3703 validated that we can do this. */
3705 {
3708 else
3709 {
3712 }
3713 }
3715 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3716 an ASHIFT. This can occur if it was inside a PLUS and hence
3717 appeared to be a memory address. This is a kludge. */
3722 {
3725 /* Update split_code because we may not have a multiply
3726 anymore. */
3728 }
3730 /* Similarly for (plus (mult FOO (const_int pow2))). */
3736 {
3740 /* Update split_code because we may not have a multiply
3741 anymore. */
3743 }
3745 #ifdef INSN_SCHEDULING
3746 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3747 be written as a ZERO_EXTEND. */
3749 {
3750 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3751 what it really is. */
3756 else
3759 }
3760 #endif
3762 /* Attempt to split binary operators using arithmetic identities. */
3766 {
3773 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3775 {
3780 }
3781 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3788 {
3794 /* Split both "((X op Y) op X) op Y" and
3795 "((X op Y) op Y) op X" as "T op T" where T is
3796 "X op Y". */
3799 {
3804 }
3805 /* Split "((X op X) op Y) op Y)" as "T op T" where
3806 T is "X op Y". */
3808 {
3814 }
3815 }
3816 }
3819 {
3822 }
3826 /* recog_for_combine might have added CLOBBERs to newi2pat.
3827 Make sure NEWPAT does not depend on the clobbered regs. */
3831 {
3834 {
3837 }
3838 }
3840 /* If the split point was a MULT and we didn't have one before,
3841 don't use one now. */
3844 }
3845 }
3847 /* Check for a case where we loaded from memory in a narrow mode and
3848 then sign extended it, but we need both registers. In that case,
3849 we have a PARALLEL with both loads from the same memory location.
3850 We can split this into a load from memory followed by a register-register
3851 copy. This saves at least one insn, more if register allocation can
3852 eliminate the copy.
3854 We cannot do this if the destination of the first assignment is a
3855 condition code register or cc0. We eliminate this case by making sure
3856 the SET_DEST and SET_SRC have the same mode.
3858 We cannot do this if the destination of the second assignment is
3859 a register that we have already assumed is zero-extended. Similarly
3860 for a SUBREG of such a register. */
3895 {
3896 rtx ni2dest;
3910 }
3912 /* Similarly, check for a case where we have a PARALLEL of two independent
3913 SETs but we started with three insns. In this case, we can do the sets
3914 as two separate insns. This case occurs when some SET allows two
3915 other insns to combine, but the destination of that SET is still live.
3917 Also do this if we started with two insns and (at least) one of the
3918 resulting sets is a noop; this noop will be deleted later. */
3937 {
3941 /* Normally, it doesn't matter which of the two is done first,
3942 but the one that references cc0 can't be the second, and
3943 one which uses any regs/memory set in between i2 and i3 can't
3944 be first. The PARALLEL might also have been pre-existing in i3,
3945 so we need to make sure that we won't wrongly hoist a SET to i2
3946 that would conflict with a death note present in there. */
3954 /* If I3 is a jump, ensure that set0 is a jump so that
3955 we do not create invalid RTL. */
3957 )
3958 {
3961 }
3969 /* If I3 is a jump, ensure that set1 is a jump so that
3970 we do not create invalid RTL. */
3972 )
3973 {
3976 }
3977 else
3978 {
3981 }
3986 {
3987 /* recog_for_combine might have added CLOBBERs to newi2pat.
3988 Make sure NEWPAT does not depend on the clobbered regs. */
3990 {
3993 {
3996 {
3999 }
4000 }
4001 }
4004 }
4005 }
4007 /* If it still isn't recognized, fail and change things back the way they
4008 were. */
4010 /* Is the result a reasonable ASM_OPERANDS? */
4012 {
4015 }
4017 /* If we had to change another insn, make sure it is valid also. */
4019 {
4027 {
4030 }
4031 }
4033 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4034 they are adjacent to each other or not. */
4036 {
4040 {
4043 }
4044 }
4046 /* Only allow this combination if insn_rtx_costs reports that the
4047 replacement instructions are cheaper than the originals. */
4049 {
4052 }
4055 {
4060 {
4065 /* Temporarily revert mode back. */
4069 {
4070 /* If we used i2dest as a scratch register with a
4071 different mode, substitute it for the original
4072 i2src while its original mode is temporarily
4073 restored, and then clear i2scratch so that we don't
4074 do it again later. */
4076 this_basic_block);
4078 /* Put back the new mode. */
4080 }
4081 else
4082 {
4087 {
4090 }
4091 else
4092 {
4099 }
4101 /* We're dealing with a reg that changed mode but not
4102 meaning, so we want to turn it into a subreg for
4103 the new mode. However, because of REG sharing and
4104 because its mode had already changed, we have to do
4105 it in two steps. First, replace any debug uses of
4106 reg, with its original mode temporarily restored,
4107 with this copy we have created; then, replace the
4108 copy with the SUBREG of the original shared reg,
4109 once again changed to the new mode. */
4111 this_basic_block);
4115 this_basic_block);
4116 }
4117 }
4118 }
4120 /* If we will be able to accept this, we have made a
4121 change to the destination of I3. This requires us to
4122 do a few adjustments. */
4125 {
4128 }
4130 /* We now know that we can do this combination. Merge the insns and
4131 update the status of registers and LOG_LINKS. */
4134 {
4139 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4140 ensure that they are still valid. Then add any non-duplicate
4141 notes added by recog_for_combine. */
4143 {
4152 /* Simply drop equal note since it may be no longer valid
4153 for other_insn. It may be possible to record that CC
4154 register is changed and only discard those notes, but
4155 in practice it's unnecessary complication and doesn't
4156 give any meaningful improvement.
4158 See PR78559. */
4162 }
4166 NULL_RTX);
4167 }
4170 {
4173 rtx ni2dest;
4175 /* I3 now uses what used to be its destination and which is now
4176 I2's destination. This requires us to do a few adjustments. */
4180 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4181 so we still will.
4183 However, some later insn might be using I2's dest and have
4184 a LOG_LINK pointing at I3. We must remove this link.
4185 The simplest way to remove the link is to point it at I1,
4186 which we know will be a NOTE. */
4188 /* newi2pat is usually a SET here; however, recog_for_combine might
4189 have added some clobbers. */
4192 else
4199 {
4202 {
4208 }
4209 }
4210 }
4212 {
4217 /* Compute which registers we expect to eliminate. newi2pat may be setting
4218 either i3dest or i2dest, so we must check it. */
4221 || !i2dest_killed
4223 /* For i1, we need to compute both local elimination and global
4224 elimination information with respect to newi2pat because i1dest
4225 may be the same as i3dest, in which case newi2pat may be setting
4226 i1dest. Global information is used when distributing REG_DEAD
4227 note for i2 and i3, in which case it does matter if newi2pat sets
4228 i1dest or not.
4230 Local information is used when distributing REG_DEAD note for i1,
4231 in which case it doesn't matter if newi2pat sets i1dest or not.
4232 See PR62151, if we have four insns combination:
4233 i0: r0 <- i0src
4234 i1: r1 <- i1src (using r0)
4235 REG_DEAD (r0)
4236 i2: r0 <- i2src (using r1)
4237 i3: r3 <- i3src (using r0)
4238 ix: using r0
4239 From i1's point of view, r0 is eliminated, no matter if it is set
4240 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4241 should be discarded.
4243 Note local information only affects cases in forms like "I1->I2->I3",
4244 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4245 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4246 i0dest anyway. */
4248 || !i1dest_killed
4253 /* Same case as i1. */
4260 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4261 clear them. */
4269 /* Ensure that we do not have something that should not be shared but
4270 occurs multiple times in the new insns. Check this by first
4271 resetting all the `used' flags and then copying anything is shared. */
4295 {
4302 {
4303 /* I2SRC must still be meaningful at this point. Some splitting
4304 operations can invalidate I2SRC, but those operations do not
4305 apply to calls. */
4308 }
4316 }
4321 /* We had one special case above where I2 had more than one set and
4322 we replaced a destination of one of those sets with the destination
4323 of I3. In that case, we have to update LOG_LINKS of insns later
4324 in this basic block. Note that this (expensive) case is rare.
4326 Also, in this case, we must pretend that all REG_NOTEs for I2
4327 actually came from I3, so that REG_UNUSED notes from I2 will be
4328 properly handled. */
4331 {
4340 temp_insn
4350 {
4355 }
4356 else
4359 }
4367 {
4370 this_basic_block);
4373 }
4374 else
4375 {
4378 this_basic_block);
4380 }
4383 {
4388 this_basic_block);
4390 }
4393 {
4398 this_basic_block);
4400 }
4402 /* Get death notes for everything that is now used in either I3 or
4403 I2 and used to die in a previous insn. If we built two new
4404 patterns, move from I1 to I2 then I2 to I3 so that we get the
4405 proper movement on registers that I2 modifies. */
4411 else
4417 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4434 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4435 know these are REG_UNUSED and want them to go to the desired insn,
4436 so we always pass it as i3. */
4440 NULL_RTX);
4444 NULL_RTX);
4446 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4447 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4448 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4449 in that case, it might delete I2. Similarly for I2 and I1.
4450 Show an additional death due to the REG_DEAD note we make here. If
4451 we discard it in distribute_notes, we will decrement it again. */
4454 {
4459 else
4462 }
4465 {
4470 else
4473 }
4476 {
4481 else
4484 }
4487 {
4492 else
4495 }
4503 {
4508 /* The insn that used to set this register doesn't exist, and
4509 this life of the register may not exist either. See if one of
4510 I3's links points to an insn that sets I2DEST. If it does,
4511 that is now the last known value for I2DEST. If we don't update
4512 this and I2 set the register to a value that depended on its old
4513 contents, we will get confused. If this insn is used, thing
4514 will be set correctly in combine_instructions. */
4522 /* If the reg formerly set in I2 died only once and that was in I3,
4523 zero its use count so it won't make `reload' do any work. */
4526 && ! i2dest_in_i2src
4529 }
4532 {
4545 && ! i1dest_in_i1src
4548 }
4551 {
4564 && ! i0dest_in_i0src
4567 }
4569 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4570 been made to this insn. The order is important, because newi2pat
4571 can affect nonzero_bits of newpat. */
4575 }
4578 {
4580 {
4583 }
4585 }
4588 {
4590 {
4593 }
4595 }
4598 {
4600 {
4603 }
4605 }
4608 {
4610 {
4613 }
4615 }
4618 {
4620 {
4623 }
4625 }
4627 /* Set new_direct_jump_p if a new return or simple jump instruction
4628 has been created. Adjust the CFG accordingly. */
4630 {
4634 }
4639 {
4642 }
4646 {
4652 }
4657 {
4663 }
4665 /* A noop might also need cleaning up of CFG, if it comes from the
4666 simplification of a jump. */
4671 {
4674 }
4681 {
4684 }
4686 combine_successes++;
4693 else
4695 }
4696 \f
4697 /* Get a marker for undoing to the current state. */
4701 {
4703 }
4705 /* Undo the modifications up to the marker. */
4707 static void
4709 {
4713 {
4718 {
4733 }
4737 }
4740 }
4742 /* Undo all the modifications recorded in undobuf. */
4744 static void
4746 {
4748 }
4750 /* We've committed to accepting the changes we made. Move all
4751 of the undos to the free list. */
4753 static void
4755 {
4759 {
4763 }
4765 }
4766 \f
4767 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4768 where we have an arithmetic expression and return that point. LOC will
4769 be inside INSN.
4771 try_combine will call this function to see if an insn can be split into
4772 two insns. */
4776 {
4785 /* First special-case some codes. */
4787 {
4789 #ifdef INSN_SCHEDULING
4790 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4791 point. */
4794 #endif
4798 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4799 using LO_SUM and HIGH. */
4802 {
4810 }
4812 /* If we have a PLUS whose second operand is a constant and the
4813 address is not valid, perhaps will can split it up using
4814 the machine-specific way to split large constants. We use
4815 the first pseudo-reg (one of the virtual regs) as a placeholder;
4816 it will not remain in the result. */
4821 {
4824 subst_insn);
4826 /* This should have produced two insns, each of which sets our
4827 placeholder. If the source of the second is a valid address,
4828 we can make put both sources together and make a split point
4829 in the middle. */
4842 && memory_address_addr_space_p
4845 {
4849 /* Replace the placeholder in SRC2 with SRC1. If we can
4850 find where in SRC2 it was placed, that can become our
4851 split point and we can replace this address with SRC2.
4852 Just try two obvious places. */
4863 {
4866 }
4867 }
4869 /* If that didn't work, perhaps the first operand is complex and
4870 needs to be computed separately, so make a split point there.
4871 This will occur on machines that just support REG + CONST
4872 and have a constant moved through some previous computation. */
4878 }
4880 /* If we have a PLUS whose first operand is complex, try computing it
4881 separately by making a split there. */
4892 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4893 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4894 we need to put the operand into a register. So split at that
4895 point. */
4905 /* See if we can split SET_SRC as it stands. */
4910 /* See if we can split SET_DEST as it stands. */
4915 /* See if this is a bitfield assignment with everything constant. If
4916 so, this is an IOR of an AND, so split it into that. */
4926 {
4932 unsigned HOST_WIDE_INT mask
4934 rtx or_mask;
4943 else
4944 {
4950 or_mask));
4951 }
4958 }
4960 /* Otherwise, see if this is an operation that we can split into two.
4961 If so, try to split that. */
4965 {
4967 /* If we are AND'ing with a large constant that is only a single
4968 bit and the result is only being used in a context where we
4969 need to know if it is zero or nonzero, replace it with a bit
4970 extraction. This will avoid the large constant, which might
4971 have taken more than one insn to make. If the constant were
4972 not a valid argument to the AND but took only one insn to make,
4973 this is no worse, but if it took more than one insn, it will
4974 be better. */
4984 {
4989 {
4992 }
4993 }
4997 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4998 is known to be on, this can be converted into a NEG of a shift. */
5004 {
5016 }
5022 /* We can't optimize if either mode is a partial integer
5023 mode as we don't know how many bits are significant
5024 in those modes. */
5038 {
5046 }
5051 }
5055 {
5058 /* For unsigned, we have a choice of a shift followed by an
5059 AND or two shifts. Use two shifts for field sizes where the
5060 constant might be too large. We assume here that we can
5061 always at least get 8-bit constants in an AND insn, which is
5062 true for every current RISC. */
5065 {
5066 unsigned HOST_WIDE_INT mask
5070 gen_rtx_LSHIFTRT
5078 }
5079 else
5080 {
5082 gen_rtx_fmt_ee
5093 }
5094 }
5096 /* See if this is a simple operation with a constant as the second
5097 operand. It might be that this constant is out of range and hence
5098 could be used as a split point. */
5106 /* Finally, see if this is a simple operation with its first operand
5107 not in a register. The operation might require this operand in a
5108 register, so return it as a split point. We can always do this
5109 because if the first operand were another operation, we would have
5110 already found it as a split point. */
5119 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5120 it is better to write this as (not (ior A B)) so we can split it.
5121 Similarly for IOR. */
5123 {
5131 }
5133 /* Many RISC machines have a large set of logical insns. If the
5134 second operand is a NOT, put it first so we will try to split the
5135 other operand first. */
5137 {
5141 }
5146 /* Canonicalization can produce (minus A (mult B C)), where C is a
5147 constant. It may be better to try splitting (plus (mult B -C) A)
5148 instead if this isn't a multiply by a power of two. */
5152 {
5160 mode)),
5163 }
5165 /* Split at a multiply-accumulate instruction. However if this is
5166 the SET_SRC, we likely do not have such an instruction and it's
5167 worthless to try this split. */
5176 }
5178 /* Otherwise, select our actions depending on our rtx class. */
5180 {
5186 /* fall through */
5194 /* fall through */
5196 /* Some machines have (and (shift ...) ...) insns. If X is not
5197 an AND, but XEXP (X, 0) is, use it as our split point. */
5207 /* Otherwise, we don't have a split point. */
5209 }
5210 }
5211 \f
5212 /* Throughout X, replace FROM with TO, and return the result.
5213 The result is TO if X is FROM;
5214 otherwise the result is X, but its contents may have been modified.
5215 If they were modified, a record was made in undobuf so that
5216 undo_all will (among other things) return X to its original state.
5218 If the number of changes necessary is too much to record to undo,
5219 the excess changes are not made, so the result is invalid.
5220 The changes already made can still be undone.
5221 undobuf.num_undo is incremented for such changes, so by testing that
5222 the caller can tell whether the result is valid.
5224 `n_occurrences' is incremented each time FROM is replaced.
5226 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5228 IN_COND is nonzero if we are at the top level of a condition.
5230 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5231 by copying if `n_occurrences' is nonzero. */
5233 static rtx
5235 {
5240 rtx new_rtx;
5242 /* Two expressions are equal if they are identical copies of a shared
5243 RTX or if they are both registers with the same register number
5244 and mode. */
5246 #define COMBINE_RTX_EQUAL_P(X,Y) \
5247 ((X) == (Y) \
5248 || (REG_P (X) && REG_P (Y) \
5249 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5251 /* Do not substitute into clobbers of regs -- this will never result in
5252 valid RTL. */
5257 {
5258 n_occurrences++;
5260 }
5262 /* If X and FROM are the same register but different modes, they
5263 will not have been seen as equal above. However, the log links code
5264 will make a LOG_LINKS entry for that case. If we do nothing, we
5265 will try to rerecognize our original insn and, when it succeeds,
5266 we will delete the feeding insn, which is incorrect.
5268 So force this insn not to match in this (rare) case. */
5273 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5274 of which may contain things that can be combined. */
5278 /* It is possible to have a subexpression appear twice in the insn.
5279 Suppose that FROM is a register that appears within TO.
5280 Then, after that subexpression has been scanned once by `subst',
5281 the second time it is scanned, TO may be found. If we were
5282 to scan TO here, we would find FROM within it and create a
5283 self-referent rtl structure which is completely wrong. */
5287 /* Parallel asm_operands need special attention because all of the
5288 inputs are shared across the arms. Furthermore, unsharing the
5289 rtl results in recognition failures. Failure to handle this case
5290 specially can result in circular rtl.
5292 Solve this by doing a normal pass across the first entry of the
5293 parallel, and only processing the SET_DESTs of the subsequent
5294 entries. Ug. */
5299 {
5302 /* If this substitution failed, this whole thing fails. */
5310 {
5316 {
5319 /* If this substitution failed, this whole thing fails. */
5325 }
5326 }
5327 }
5328 else
5329 {
5333 /* We don't need to process a SET_DEST that is a register, CC0,
5334 or PC, so set up to skip this common case. All other cases
5335 where we want to suppress replacing something inside a
5336 SET_SRC are handled via the IN_DEST operand. */
5343 /* Trying to simplify the operands of a widening MULT is not likely
5344 to create RTL matching a machine insn. */
5356 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5357 constant. */
5362 {
5364 {
5367 {
5369 {
5372 n_occurrences++;
5373 }
5374 else
5375 {
5377 unique_copy);
5379 /* If this substitution failed, this whole thing
5380 fails. */
5384 }
5387 }
5388 }
5390 {
5391 /* If this is a register being set, ignore it. */
5398 ;
5401 {
5402 /* In general, don't install a subreg involving two
5403 modes not tieable. It can worsen register
5404 allocation, and can even make invalid reload
5405 insns, since the reg inside may need to be copied
5406 from in the outside mode, and that may be invalid
5407 if it is an fp reg copied in integer mode.
5409 We allow two exceptions to this: It is valid if
5410 it is inside another SUBREG and the mode of that
5411 SUBREG and the mode of the inside of TO is
5412 tieable and it is valid if X is a SET that copies
5413 FROM to CC0. */
5421 && (!HAVE_cc0
5436 n_occurrences++;
5437 }
5438 else
5439 /* If we are in a SET_DEST, suppress most cases unless we
5440 have gone inside a MEM, in which case we want to
5441 simplify the address. We assume here that things that
5442 are actually part of the destination have their inner
5443 parts in the first expression. This is true for SUBREG,
5444 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5445 things aside from REG and MEM that should appear in a
5446 SET_DEST. */
5448 (((in_dest
5454 unique_copy);
5456 /* If we found that we will have to reject this combination,
5457 indicate that by returning the CLOBBER ourselves, rather than
5458 an expression containing it. This will speed things up as
5459 well as prevent accidents where two CLOBBERs are considered
5460 to be equal, thus producing an incorrect simplification. */
5466 {
5474 }
5477 {
5481 }
5482 else
5484 }
5485 }
5486 }
5488 /* Check if we are loading something from the constant pool via float
5489 extension; in this case we would undo compress_float_constant
5490 optimization and degenerate constant load to an immediate value. */
5494 {
5498 }
5500 /* Try to simplify X. If the simplification changed the code, it is likely
5501 that further simplification will help, so loop, but limit the number
5502 of repetitions that will be performed. */
5505 {
5506 /* If X is sufficiently simple, don't bother trying to do anything
5507 with it. */
5516 /* We no longer know the original mode of operand 0 since we
5517 have changed the form of X) */
5519 }
5522 }
5523 \f
5524 /* If X is a commutative operation whose operands are not in the canonical
5525 order, use substitutions to swap them. */
5527 static void
5529 {
5532 {
5536 }
5537 }
5539 /* Simplify X, a piece of RTL. We just operate on the expression at the
5540 outer level; call `subst' to simplify recursively. Return the new
5541 expression.
5543 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5544 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5545 of a condition. */
5547 static rtx
5550 {
5553 rtx temp;
5556 /* If this is a commutative operation, put a constant last and a complex
5557 expression first. We don't need to do this for comparisons here. */
5560 /* Try to fold this expression in case we have constants that weren't
5561 present before. */
5564 {
5572 {
5575 {
5579 }
5582 }
5595 }
5598 {
5603 }
5605 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5606 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5607 things. Check for cases where both arms are testing the same
5608 condition.
5610 Don't do anything if all operands are very simple. */
5623 {
5628 /* If everything is a comparison, what we have is highly unlikely
5629 to be simpler, so don't use it. */
5632 {
5639 /* Simplify the alternative arms; this may collapse the true and
5640 false arms to store-flag values. Be careful to use copy_rtx
5641 here since true_rtx or false_rtx might share RTL with x as a
5642 result of the if_then_else_cond call above. */
5646 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5647 is unlikely to be simpler. */
5650 {
5653 /* Restarting if we generate a store-flag expression will cause
5654 us to loop. Just drop through in this case. */
5656 /* If the result values are STORE_FLAG_VALUE and zero, we can
5657 just make the comparison operation. */
5668 /* Likewise, we can make the negate of a comparison operation
5669 if the result values are - STORE_FLAG_VALUE and zero. */
5677 mode);
5688 mode);
5689 else
5692 mode,
5693 VOIDmode,
5694 cond,
5695 cop1),
5700 }
5701 }
5702 }
5704 /* First see if we can apply the inverse distributive law. */
5707 {
5711 }
5713 /* If CODE is an associative operation not otherwise handled, see if we
5714 can associate some operands. This can win if they are constants or
5715 if they are logically related (i.e. (a & b) & a). */
5721 {
5723 {
5727 rtx inner;
5729 /* Make sure we pass the constant operand if any as the second
5730 one if this is a commutative operation. */
5738 /* For commutative operations, try the other pair if that one
5739 didn't simplify. */
5741 {
5746 }
5750 }
5751 }
5753 /* A little bit of algebraic simplification here. */
5755 {
5757 /* Ensure that our address has any ASHIFTs converted to MULT in case
5758 address-recognizing predicates are called later. */
5767 /* See if this can be moved to simplify_subreg. */
5770 /* Don't call gen_lowpart if the inner mode
5771 is VOIDmode and we cannot simplify it, as SUBREG without
5772 inner mode is invalid. */
5779 {
5780 rtx temp;
5786 /* If op is known to have all lower bits zero, the result is zero. */
5796 }
5798 /* Don't change the mode of the MEM if that would change the meaning
5799 of the address. */
5806 /* Note that we cannot do any narrowing for non-constants since
5807 we might have been counting on using the fact that some bits were
5808 zero. We now do this in the SET. */
5815 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5816 replaced by (lshiftrt X C). This will convert
5817 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5825 /* If X has only a single bit that might be nonzero, say, bit I, convert
5826 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5827 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5828 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5829 or a SUBREG of one since we'd be making the expression more
5830 complex if it was just a register. */
5836 {
5837 rtx temp1 = simplify_shift_const
5843 /* If all we did was surround TEMP with the two shifts, we
5844 haven't improved anything, so don't use it. Otherwise,
5845 we are better off with TEMP1. */
5850 }
5854 /* We can't handle truncation to a partial integer mode here
5855 because we don't know the real bitsize of the partial
5856 integer mode. */
5865 /* We can truncate a constant value and return it. */
5869 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5870 whose value is a comparison can be replaced with a subreg if
5871 STORE_FLAG_VALUE permits. */
5880 /* (const (const X)) can become (const X). Do it this way rather than
5881 returning the inner CONST since CONST can be shared with a
5882 REG_EQUAL note. */
5888 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5889 can add in an offset. find_split_point will split this address up
5890 again if it doesn't match. */
5897 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5898 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5899 bit-field and can be replaced by either a sign_extend or a
5900 sign_extract. The `and' may be a zero_extend and the two
5901 <c>, -<c> constants may be reversed. */
5916 return simplify_shift_const
5923 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5924 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5925 the bitsize of the mode - 1. This allows simplification of
5926 "a = (b & 8) == 0;" */
5938 /* If we are adding two things that have no bits in common, convert
5939 the addition into an IOR. This will often be further simplified,
5940 for example in cases like ((a & 1) + (a & 2)), which can
5941 become a & 3. */
5946 {
5947 /* Try to simplify the expression further. */
5951 /* If we could, great. If not, do not go ahead with the IOR
5952 replacement, since PLUS appears in many special purpose
5953 address arithmetic instructions. */
5961 }
5963 /* Canonicalize x + x into x << 1. */
5972 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5973 (and <foo> (const_int pow2-1)) */
5983 /* If we have (mult (plus A B) C), apply the distributive law and then
5984 the inverse distributive law to see if things simplify. This
5985 occurs mostly in addresses, often when unrolling loops. */
5988 {
5992 }
5994 /* Try simplify a*(b/c) as (a*b)/c. */
5997 {
6003 }
6007 /* If this is a divide by a power of two, treat it as a shift if
6008 its first operand is a shift. */
6026 /* If the first operand is a condition code, we can't do anything
6027 with it. */
6031 {
6039 /* Simplify our comparison, if possible. */
6042 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6043 if only the low-order bit is possibly nonzero in X (such as when
6044 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6045 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6046 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6047 (plus X 1).
6049 Remove any ZERO_EXTRACT we made when thinking this was a
6050 comparison. It may now be simpler to use, e.g., an AND. If a
6051 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6052 the call to make_compound_operation in the SET case.
6054 Don't apply these optimizations if the caller would
6055 prefer a comparison rather than a value.
6056 E.g., for the condition in an IF_THEN_ELSE most targets need
6057 an explicit comparison. */
6060 ;
6076 {
6080 mode);
6081 }
6088 {
6092 const1_rtx);
6093 }
6101 {
6104 }
6106 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6107 those above. */
6109 ;
6125 {
6129 mode);
6130 }
6138 {
6142 mode);
6143 }
6145 /* If X is 0/1, (eq X 0) is X-1. */
6151 {
6154 }
6156 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6157 one bit that might be nonzero, we can convert (ne x 0) to
6158 (ashift x c) where C puts the bit in the sign bit. Remove any
6159 AND with STORE_FLAG_VALUE when we are done, since we are only
6160 going to test the sign bit. */
6167 {
6173 else
6175 }
6177 /* If the code changed, return a whole new comparison.
6178 We also need to avoid using SUBST in cases where
6179 simplify_comparison has widened a comparison with a CONST_INT,
6180 since in that case the wider CONST_INT may fail the sanity
6181 checks in do_SUBST. */
6188 /* Otherwise, keep this operation, but maybe change its operands.
6189 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6192 }
6202 /* If we are processing SET_DEST, we are done. */
6220 /* If this is a shift by a constant amount, simplify it. */
6228 (HOST_WIDE_INT_1U
6236 }
6239 }
6240 \f
6241 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6243 static rtx
6245 {
6252 rtx temp;
6255 rtx reversed;
6257 /* Simplify storing of the truth value. */
6262 /* Also when the truth value has to be reversed. */
6268 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6269 in it is being compared against certain values. Get the true and false
6270 comparisons and see if that says anything about the value of each arm. */
6276 {
6277 HOST_WIDE_INT nzb;
6283 /* If FALSE_CODE is EQ, swap the codes and arms. */
6286 {
6289 }
6291 /* If we are comparing against zero and the expression being tested has
6292 only a single bit that might be nonzero, that is its value when it is
6293 not equal to zero. Similarly if it is known to be -1 or 0. */
6297 {
6300 }
6304 {
6307 }
6309 /* Now simplify an arm if we know the value of the register in the
6310 branch and it is used in the arm. Be careful due to the potential
6311 of locally-shared RTL. */
6328 }
6330 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6331 reversed, do so to avoid needing two sets of patterns for
6332 subtract-and-branch insns. Similarly if we have a constant in the true
6333 arm, the false arm is the same as the first operand of the comparison, or
6334 the false arm is more complicated than the true arm. */
6347 {
6356 /* It is possible that the conditional has been simplified out. */
6359 }
6361 /* If the two arms are identical, we don't need the comparison. */
6366 /* Convert a == b ? b : a to "a". */
6378 /* Look for cases where we have (abs x) or (neg (abs X)). */
6381 && comparison_p
6388 {
6394 return
6397 mode);
6400 }
6402 /* Look for MIN or MAX. */
6405 && comparison_p
6410 {
6425 }
6427 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6428 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6429 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6430 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6431 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6432 neither 1 or -1, but it isn't worth checking for. */
6435 && comparison_p
6438 {
6454 /* If an identity-zero op is commutative, check whether there
6455 would be a match if we swapped the operands. */
6475 {
6479 }
6491 {
6495 }
6511 {
6515 }
6527 {
6531 }
6534 {
6540 const_true_rtx));
6548 }
6549 }
6551 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6552 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6553 negation of a single bit, we can convert this operation to a shift. We
6554 can actually do this more generally, but it doesn't seem worth it. */
6563 return
6567 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6568 non-zero bit in A is C1. */
6575 {
6582 }
6585 }
6586 \f
6587 /* Simplify X, a SET expression. Return the new expression. */
6589 static rtx
6591 {
6594 machine_mode mode
6599 /* (set (pc) (return)) gets written as (return). */
6603 /* Now that we know for sure which bits of SRC we are using, see if we can
6604 simplify the expression for the object knowing that we only need the
6605 low-order bits. */
6608 {
6611 }
6613 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6614 the comparison result and try to simplify it unless we already have used
6615 undobuf.other_insn. */
6623 {
6632 {
6635 {
6638 }
6639 }
6640 else
6648 {
6652 }
6653 else
6654 {
6659 /* Attempt to simplify CC user. */
6661 {
6665 }
6667 /* Convert X into a no-op move. */
6671 }
6673 /* Simplify our comparison, if possible. */
6676 #ifdef SELECT_CC_MODE
6677 /* If this machine has CC modes other than CCmode, check to see if we
6678 need to use a different CC mode here. */
6687 else
6690 /* If the mode changed, we have to change SET_DEST, the mode in the
6691 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6692 a hard register, just build new versions with the proper mode. If it
6693 is a pseudo, we lose unless it is only time we set the pseudo, in
6694 which case we can safely change its mode. */
6696 {
6698 {
6700 rtx new_dest;
6704 else
6705 {
6708 }
6715 }
6716 }
6719 /* If the code changed, we have to build a new comparison in
6720 undobuf.other_insn. */
6722 {
6731 /* If the only change we made was to change an EQ into an NE or
6732 vice versa, OP0 has only one bit that might be nonzero, and OP1
6733 is zero, check if changing the user of the condition code will
6734 produce a valid insn. If it won't, we can keep the original code
6735 in that insn by surrounding our operation with an XOR. */
6742 {
6747 {
6754 }
6755 }
6756 }
6761 /* Don't generate a compare of a CC with 0, just use that CC. */
6763 {
6766 }
6767 /* Otherwise, if we didn't previously have the same COMPARE we
6768 want, create it from scratch. */
6771 {
6774 }
6775 }
6776 else
6777 {
6778 /* Get SET_SRC in a form where we have placed back any
6779 compound expressions. Then do the checks below. */
6782 }
6784 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6785 and X being a REG or (subreg (reg)), we may be able to convert this to
6786 (set (subreg:m2 x) (op)).
6788 We can always do this if M1 is narrower than M2 because that means that
6789 we only care about the low bits of the result.
6791 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6792 perform a narrower operation than requested since the high-order bits will
6793 be undefined. On machine where it is defined, this transformation is safe
6794 as long as M1 and M2 have the same number of words. */
6802 && (WORD_REGISTER_OPERATIONS
6805 #ifdef CANNOT_CHANGE_MODE_CLASS
6810 #endif
6814 {
6817 dest));
6821 }
6823 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6824 in SRC. */
6830 {
6834 /* Here we make sure that we don't have a sign bit on. */
6837 {
6840 }
6841 }
6843 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6844 would require a paradoxical subreg. Replace the subreg with a
6845 zero_extend to avoid the reload that would otherwise be required. */
6851 {
6856 }
6858 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6859 are comparing an item known to be 0 or -1 against 0, use a logical
6860 operation instead. Check for one of the arms being an IOR of the other
6861 arm with some value. We compute three terms to be IOR'ed together. In
6862 practice, at most two will be nonzero. Then we do the IOR's. */
6870 && (!HAVE_conditional_move
6876 {
6902 false_rtx);
6908 term3));
6911 }
6913 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6914 whole thing fail. */
6919 else
6920 /* Convert this into a field assignment operation, if possible. */
6922 }
6923 \f
6924 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6925 result. */
6927 static rtx
6929 {
6935 {
6937 /* We can call simplify_and_const_int only if we don't lose
6938 any (sign) bits when converting INTVAL (op1) to
6939 "unsigned HOST_WIDE_INT". */
6943 {
6950 }
6952 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6953 apply the distributive law and then the inverse distributive
6954 law to see if things simplify. */
6956 {
6960 }
6962 {
6966 }
6970 /* If we have (ior (and A B) C), apply the distributive law and then
6971 the inverse distributive law to see if things simplify. */
6974 {
6978 }
6981 {
6985 }
6990 }
6993 }
6994 \f
6995 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6996 operations" because they can be replaced with two more basic operations.
6997 ZERO_EXTEND is also considered "compound" because it can be replaced with
6998 an AND operation, which is simpler, though only one operation.
7000 The function expand_compound_operation is called with an rtx expression
7001 and will convert it to the appropriate shifts and AND operations,
7002 simplifying at each stage.
7004 The function make_compound_operation is called to convert an expression
7005 consisting of shifts and ANDs into the equivalent compound expression.
7006 It is the inverse of this function, loosely speaking. */
7008 static rtx
7010 {
7014 rtx tem;
7017 {
7020 /* FALLTHRU */
7022 /* We can't necessarily use a const_int for a multiword mode;
7023 it depends on implicitly extending the value.
7024 Since we don't know the right way to extend it,
7025 we can't tell whether the implicit way is right.
7027 Even for a mode that is no wider than a const_int,
7028 we can't win, because we need to sign extend one of its bits through
7029 the rest of it, and we don't know which bit. */
7033 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7034 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7035 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7036 reloaded. If not for that, MEM's would very rarely be safe.
7038 Reject MODEs bigger than a word, because we might not be able
7039 to reference a two-register group starting with an arbitrary register
7040 (and currently gen_lowpart might crash for a SUBREG). */
7045 /* Reject MODEs that aren't scalar integers because turning vector
7046 or complex modes into shifts causes problems. */
7052 /* If the inner object has VOIDmode (the only way this can happen
7053 is if it is an ASM_OPERANDS), we can't do anything since we don't
7054 know how much masking to do. */
7063 /* fall through */
7066 /* If the operand is a CLOBBER, just return it. */
7075 /* Reject MODEs that aren't scalar integers because turning vector
7076 or complex modes into shifts causes problems. */
7084 /* This should stay within the object being extracted, fail otherwise. */
7095 }
7096 /* Convert sign extension to zero extension, if we know that the high
7097 bit is not set, as this is easier to optimize. It will be converted
7098 back to cheaper alternative in make_extraction. */
7106 {
7111 /* Make sure this is a profitable operation. */
7118 else
7120 }
7122 /* We can optimize some special cases of ZERO_EXTEND. */
7124 {
7125 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7126 know that the last value didn't have any inappropriate bits
7127 set. */
7135 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7144 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7145 is a comparison and STORE_FLAG_VALUE permits. This is like
7146 the first case, but it works even when GET_MODE (x) is larger
7147 than HOST_WIDE_INT. */
7156 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7166 }
7168 /* If we reach here, we want to return a pair of shifts. The inner
7169 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7170 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7171 logical depending on the value of UNSIGNEDP.
7173 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7174 converted into an AND of a shift.
7176 We must check for the case where the left shift would have a negative
7177 count. This can happen in a case like (x >> 31) & 255 on machines
7178 that can't shift by a constant. On those machines, we would first
7179 combine the shift with the AND to produce a variable-position
7180 extraction. Then the constant of 31 would be substituted in
7181 to produce such a position. */
7185 {
7194 }
7201 else
7202 /* Any other cases we can't handle. */
7205 /* If we couldn't do this for some reason, return the original
7206 expression. */
7211 }
7212 \f
7213 /* X is a SET which contains an assignment of one object into
7214 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7215 or certain SUBREGS). If possible, convert it into a series of
7216 logical operations.
7218 We half-heartedly support variable positions, but do not at all
7219 support variable lengths. */
7221 static const_rtx
7223 {
7224 rtx inner;
7228 machine_mode compute_mode;
7230 /* Loop until we find something we can't simplify. */
7232 {
7235 {
7239 }
7242 {
7247 /* A constant position should stay within the width of INNER. */
7253 {
7261 /* If position is ADJUST - X, new position is X. */
7263 else
7264 {
7269 pos);
7270 }
7271 }
7272 }
7274 /* A SUBREG between two modes that occupy the same numbers of words
7275 can be done by moving the SUBREG to the source. */
7277 /* We need SUBREGs to compute nonzero_bits properly. */
7278 && nonzero_sign_valid
7283 {
7285 gen_lowpart
7289 }
7290 else
7298 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7300 {
7301 machine_mode imode;
7303 /* Don't do anything for vector or complex integral types. */
7307 /* Try to find an integral mode to pun with. */
7314 }
7316 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7320 /* Don't try to compute in too wide unsupported modes. */
7324 /* Now compute the equivalent expression. Make a copy of INNER
7325 for the SET_DEST in case it is a MEM into which we will substitute;
7326 we don't want shared RTL in that case. */
7328 compute_mode);
7332 compute_mode,
7334 compute_mode),
7335 inner);
7340 mask),
7341 pos);
7346 }
7349 }
7350 \f
7351 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7352 it is an RTX that represents the (variable) starting position; otherwise,
7353 POS is the (constant) starting bit position. Both are counted from the LSB.
7355 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7357 IN_DEST is nonzero if this is a reference in the destination of a SET.
7358 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7359 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7360 be used.
7362 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7363 ZERO_EXTRACT should be built even for bits starting at bit 0.
7365 MODE is the desired mode of the result (if IN_DEST == 0).
7367 The result is an RTX for the extraction or NULL_RTX if the target
7368 can't handle it. */
7370 static rtx
7374 {
7375 /* This mode describes the size of the storage area
7376 to fetch the overall value from. Within that, we
7377 ignore the POS lowest bits, etc. */
7379 machine_mode inner_mode;
7380 machine_mode wanted_inner_mode;
7387 HOST_WIDE_INT orig_pos;
7393 {
7394 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7395 consider just the QI as the memory to extract from.
7396 The subreg adds or removes high bits; its mode is
7397 irrelevant to the meaning of this extraction,
7398 since POS and LEN count from the lsb. */
7402 }
7407 {
7408 /* We're extracting the least significant bits of an rtx
7409 (ashift X (const_int C)), where LEN > C. Extract the
7410 least significant (LEN - C) bits of X, giving an rtx
7411 whose mode is MODE, then shift it left C times. */
7417 }
7423 /* See if this can be done without an extraction. We never can if the
7424 width of the field is not the same as that of some integer mode. For
7425 registers, we can only avoid the extraction if the position is at the
7426 low-order bit and this is either not in the destination or we have the
7427 appropriate STRICT_LOW_PART operation available.
7429 For MEM, we can avoid an extract if the field starts on an appropriate
7430 boundary and we can change the mode of the memory reference. */
7440 && (! in_dest
7444 && (pos
7447 /* We can't do this if we are widening INNER_MODE (it
7448 may not be aligned, for one thing). */
7454 {
7455 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7456 field. If the original and current mode are the same, we need not
7457 adjust the offset. Otherwise, we do if bytes big endian.
7459 If INNER is not a MEM, get a piece consisting of just the field
7460 of interest (in this case POS % BITS_PER_WORD must be 0). */
7463 {
7464 HOST_WIDE_INT offset;
7466 /* POS counts from lsb, but make OFFSET count in memory order. */
7469 else
7473 }
7475 {
7477 {
7478 /* We can't call gen_lowpart in a DEST since we
7479 always want a SUBREG (see below) and it would sometimes
7480 return a new hard register. */
7482 {
7497 /* Avoid creating invalid subregs, for example when
7498 simplifying (x>>32)&255. */
7503 }
7504 else
7506 }
7507 else
7509 }
7510 else
7512 len >= HOST_BITS_PER_WIDE_INT
7513 ? HOST_WIDE_INT_M1U
7516 /* If this extraction is going into the destination of a SET,
7517 make a STRICT_LOW_PART unless we made a MEM. */
7532 /* If we know that no extraneous bits are set, and that the high
7533 bit is not set, convert the extraction to the cheaper of
7534 sign and zero extension, that are equivalent in these cases. */
7540 {
7544 /* Prefer ZERO_EXTENSION, since it gives more information to
7545 backends. */
7550 }
7552 /* Otherwise, sign- or zero-extend unless we already are in the
7553 proper mode. */
7557 }
7559 /* Unless this is a COMPARE or we have a funny memory reference,
7560 don't do anything with zero-extending field extracts starting at
7561 the low-order bit since they are simple AND operations. */
7566 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7567 if the position is not a constant and the length is not 1. In all
7568 other cases, we would only be going outside our object in cases when
7569 an original shift would have been undefined. */
7578 /* If INNER is not from memory, we want it to have the mode of a register
7579 extraction pattern's structure operand, or word_mode if there is no
7580 such pattern. The same applies to extraction_mode and pos_mode
7581 and their respective operands.
7583 For memory, assume that the desired extraction_mode and pos_mode
7584 are the same as for a register operation, since at present we don't
7585 have named patterns for aligned memory structures. */
7589 {
7593 }
7595 /* Never narrow an object, since that might not be safe. */
7603 else
7604 {
7605 /* Be careful not to go beyond the extracted object and maintain the
7606 natural alignment of the memory. */
7610 {
7613 }
7614 }
7619 {
7620 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7621 BITS_BIG_ENDIAN style. If position is constant, compute new
7622 position. Otherwise, build subtraction.
7623 Note that POS is relative to the mode of the original argument.
7624 If it's a MEM we need to recompute POS relative to that.
7625 However, if we're extracting from (or inserting into) a register,
7626 we want to recompute POS relative to wanted_inner_mode. */
7633 else
7634 pos_rtx
7637 pos_rtx);
7638 /* POS may be less than 0 now, but we check for that below.
7639 Note that it can only be less than 0 if !MEM_P (inner). */
7640 }
7642 /* If INNER has a wider mode, and this is a constant extraction, try to
7643 make it smaller and adjust the byte to point to the byte containing
7644 the value. */
7647 && ! pos_rtx
7652 {
7655 /* The computations below will be correct if the machine is big
7656 endian in both bits and bytes or little endian in bits and bytes.
7657 If it is mixed, we must adjust. */
7659 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7660 adjust OFFSET to compensate. */
7665 /* We can now move to the desired byte. */
7676 }
7678 /* If INNER is not memory, get it into the proper mode. If we are changing
7679 its mode, POS must be a constant and smaller than the size of the new
7680 mode. */
7682 {
7683 /* On the LHS, don't create paradoxical subregs implicitely truncating
7684 the register unless TRULY_NOOP_TRUNCATION. */
7687 wanted_inner_mode))
7699 pos_rtx
7701 ? HOST_WIDE_INT_M1U
7705 }
7707 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7708 have to zero extend. Otherwise, we can just use a SUBREG. */
7711 {
7715 /* If we know that no extraneous bits are set, and that the high
7716 bit is not set, convert extraction to cheaper one - either
7717 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7718 cases. */
7726 {
7730 /* Prefer ZERO_EXTENSION, since it gives more information to
7731 backends. */
7735 }
7737 }
7739 /* Make POS_RTX unless we already have it and it is correct. If we don't
7740 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7741 be a CONST_INT. */
7748 /* Make the required operation. See if we can use existing rtx. */
7755 }
7756 \f
7757 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7758 with any other operations in X. Return X without that shift if so. */
7760 static rtx
7762 {
7765 rtx tem;
7768 {
7770 /* This is the shift itself. If it is wide enough, we will return
7771 either the value being shifted if the shift count is equal to
7772 COUNT or a shift for the difference. */
7786 /* If we can safely shift this constant and we find the inner shift,
7787 make a new operation. */
7792 {
7796 }
7801 }
7804 }
7805 \f
7806 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7807 level of the expression and MODE is its mode. IN_CODE is as for
7808 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7809 that should be used when recursing on operands of *X_PTR.
7811 There are two possible actions:
7813 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7814 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7816 - Return a new rtx, which the caller returns directly. */
7818 static rtx
7822 {
7830 rtx tem;
7834 {
7837 }
7839 /* Process depending on the code of this operation. If NEW is set
7840 nonzero, it will be returned. */
7843 {
7845 /* Convert shifts by constants into multiplications if inside
7846 an address. */
7850 {
7856 {
7859 }
7862 }
7871 {
7875 }
7878 {
7882 mode));
7884 }
7885 else
7886 {
7889 }
7899 {
7903 }
7906 {
7910 mode));
7912 }
7913 else
7914 {
7918 }
7921 /* If the second operand is not a constant, we can't do anything
7922 with it. */
7926 /* If the constant is a power of two minus one and the first operand
7927 is a logical right shift, make an extraction. */
7930 {
7934 }
7936 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7941 {
7950 {
7951 /* If we narrowed the mode when dropping the subreg, then
7952 we must zero-extend to keep the semantics of the AND. */
7954 ;
7958 else
7960 }
7962 /* If that didn't give anything, see if the AND simplifies on
7963 its own. */
7965 {
7969 }
7970 }
7971 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7977 {
7978 /* Apply the distributive law, and then try to make extractions. */
7985 }
7987 /* If we are have (and (rotate X C) M) and C is larger than the number
7988 of bits in M, this is an extraction. */
7994 {
8000 }
8002 /* On machines without logical shifts, if the operand of the AND is
8003 a logical shift and our mask turns off all the propagated sign
8004 bits, we can replace the logical shift with an arithmetic shift. */
8012 {
8019 make_compound_operation
8022 }
8024 /* If the constant is one less than a power of two, this might be
8025 representable by an extraction even if no shift is present.
8026 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8027 we are in a COMPARE. */
8031 next_code),
8034 /* If we are in a comparison and this is an AND with a power of two,
8035 convert this into the appropriate bit extract. */
8041 next_code),
8044 /* If the one operand is a paradoxical subreg of a register or memory and
8045 the constant (limited to the smaller mode) has only zero bits where
8046 the sub expression has known zero bits, this can be expressed as
8047 a zero_extend. */
8049 {
8050 rtx sub;
8056 {
8060 /* original AND constant with all the known zero bits set */
8063 {
8068 }
8069 }
8070 }
8075 /* If the sign bit is known to be zero, replace this with an
8076 arithmetic shift. */
8081 {
8084 next_code),
8087 }
8089 /* fall through */
8095 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8096 this is a SIGN_EXTRACT. */
8103 {
8110 }
8112 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8113 If so, try to merge the shifts into a SIGN_EXTEND. We could
8114 also do this for some cases of SIGN_EXTRACT, but it doesn't
8115 seem worth the effort; the case checked for occurs on Alpha. */
8132 /* Call ourselves recursively on the inner expression. If we are
8133 narrowing the object and it has a different RTL code from
8134 what it originally did, do this SUBREG as a force_to_mode. */
8135 {
8139 /* If the SUBREG is masking of a logical right shift,
8140 make an extraction. */
8147 {
8156 }
8158 /* If in_code is COMPARE, it isn't always safe to pass it through
8159 to the recursive make_compound_operation call. */
8163 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8164 is (const_int 0), rather than
8165 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8175 simplified
8183 {
8184 rtx newer
8187 /* If we have something other than a SUBREG, we might have
8188 done an expansion, so rerun ourselves. */
8192 /* force_to_mode can expand compounds. If it just re-expanded the
8193 compound, use gen_lowpart to convert to the desired mode. */
8195 /* Likewise if it re-expanded the compound only partially.
8196 This happens for SUBREG of ZERO_EXTRACT if they extract
8197 the same number of bits. */
8206 }
8210 }
8215 }
8221 }
8223 /* Look at the expression rooted at X. Look for expressions
8224 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8225 Form these expressions.
8227 Return the new rtx, usually just X.
8229 Also, for machines like the VAX that don't have logical shift insns,
8230 try to convert logical to arithmetic shift operations in cases where
8231 they are equivalent. This undoes the canonicalizations to logical
8232 shifts done elsewhere.
8234 We try, as much as possible, to re-use rtl expressions to save memory.
8236 IN_CODE says what kind of expression we are processing. Normally, it is
8237 SET. In a memory address it is MEM. When processing the arguments of
8238 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8239 precisely it is an equality comparison against zero. */
8241 rtx
8243 {
8250 /* Select the code to be used in recursive calls. Once we are inside an
8251 address, we stay there. If we have a comparison, set to COMPARE,
8252 but once inside, go back to our default of SET. */
8260 {
8266 }
8268 /* Now recursively process each operand of this operation. We need to
8269 handle ZERO_EXTEND specially so that we don't lose track of the
8270 inner mode. */
8272 {
8280 }
8285 {
8288 }
8291 {
8294 }
8298 }
8299 \f
8300 /* Given M see if it is a value that would select a field of bits
8301 within an item, but not the entire word. Return -1 if not.
8302 Otherwise, return the starting position of the field, where 0 is the
8303 low-order bit.
8305 *PLEN is set to the length of the field. */
8307 static int
8309 {
8310 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8315 /* Now shift off the low-order zero bits and see if we have a
8316 power of two minus 1. */
8324 }
8325 \f
8326 /* If X refers to a register that equals REG in value, replace these
8327 references with REG. */
8328 static rtx
8330 {
8338 {
8371 /* FALLTHRU */
8375 {
8379 else
8381 }
8383 /* fall through */
8390 {
8393 {
8395 {
8398 }
8400 }
8401 }
8403 {
8406 {
8409 {
8411 {
8414 }
8416 }
8417 }
8418 }
8421 }
8424 }
8426 /* Return X converted to MODE. If the value is already truncated to
8427 MODE we can just return a subreg even though in the general case we
8428 would need an explicit truncation. */
8430 static rtx
8432 {
8437 {
8438 /* Bit-cast X into an integer mode. */
8443 }
8446 }
8448 /* See if X can be simplified knowing that we will only refer to it in
8449 MODE and will only refer to those bits that are nonzero in MASK.
8450 If other bits are being computed or if masking operations are done
8451 that select a superset of the bits in MASK, they can sometimes be
8452 ignored.
8454 Return a possibly simplified expression, but always convert X to
8455 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8457 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8458 are all off in X. This is used when X will be complemented, by either
8459 NOT, NEG, or XOR. */
8461 static rtx
8464 {
8467 machine_mode op_mode;
8471 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8472 code below will do the wrong thing since the mode of such an
8473 expression is VOIDmode.
8475 Also do nothing if X is a CLOBBER; this can happen if X was
8476 the return value from a call to gen_lowpart. */
8480 /* We want to perform the operation in its present mode unless we know
8481 that the operation is valid in MODE, in which case we do the operation
8482 in MODE. */
8487 /* It is not valid to do a right-shift in a narrower mode
8488 than the one it came in with. */
8493 /* Truncate MASK to fit OP_MODE. */
8497 /* When we have an arithmetic operation, or a shift whose count we
8498 do not know, we need to assume that all bits up to the highest-order
8499 bit in MASK will be needed. This is how we form such a mask. */
8502 else
8506 /* Determine what bits of X are guaranteed to be (non)zero. */
8509 /* If none of the bits in X are needed, return a zero. */
8513 /* If X is a CONST_INT, return a new one. Do this here since the
8514 test below will fail. */
8516 {
8519 else
8520 {
8523 }
8524 }
8526 /* If X is narrower than MODE and we want all the bits in X's mode, just
8527 get X in the proper mode. */
8532 /* We can ignore the effect of a SUBREG if it narrows the mode or
8533 if the constant masks to zero all the bits the mode doesn't have. */
8543 /* The arithmetic simplifications here only work for scalar integer modes. */
8548 {
8550 /* If X is a (clobber (const_int)), return it since we know we are
8551 generating something that won't match. */
8564 /* Similarly for a truncate. */
8568 /* If this is an AND with a constant, convert it into an AND
8569 whose constant is the AND of that constant with MASK. If it
8570 remains an AND of MASK, delete it since it is redundant. */
8573 {
8577 /* If X is still an AND, see if it is an AND with a mask that
8578 is just some low-order bits. If so, and it is MASK, we don't
8579 need it. */
8586 /* If it remains an AND, try making another AND with the bits
8587 in the mode mask that aren't in MASK turned on. If the
8588 constant in the AND is wide enough, this might make a
8589 cheaper constant. */
8594 {
8595 unsigned HOST_WIDE_INT cval
8598 rtx y;
8605 }
8608 }
8613 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8614 low-order bits (as in an alignment operation) and FOO is already
8615 aligned to that boundary, mask C1 to that boundary as well.
8616 This may eliminate that PLUS and, later, the AND. */
8618 {
8622 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8623 number, sign extend it. */
8636 }
8638 /* fall through */
8641 /* Substituting into the operands of a widening MULT is not likely to
8642 create RTL matching a machine insn. */
8652 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8653 most significant bit in MASK since carries from those bits will
8654 affect the bits we are interested in. */
8659 /* If X is (minus C Y) where C's least set bit is larger than any bit
8660 in the mask, then we may replace with (neg Y). */
8663 {
8667 }
8669 /* Similarly, if C contains every bit in the fuller_mask, then we may
8670 replace with (not Y). */
8673 {
8677 }
8684 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8685 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8686 operation which may be a bitfield extraction. Ensure that the
8687 constant we form is not wider than the mode of X. */
8699 {
8708 }
8710 binop:
8711 /* For most binary operations, just propagate into the operation and
8712 change the mode if we have an operation of that mode. */
8717 /* If we ended up truncating both operands, truncate the result of the
8718 operation instead. */
8721 {
8724 }
8734 /* For left shifts, do the same, but just for the first operand.
8735 However, we cannot do anything with shifts where we cannot
8736 guarantee that the counts are smaller than the size of the mode
8737 because such a count will have a different meaning in a
8738 wider mode. */
8748 /* If the shift count is a constant and we can do arithmetic in
8749 the mode of the shift, refine which bits we need. Otherwise, use the
8750 conservative form of the mask. */
8756 else
8768 /* Here we can only do something if the shift count is a constant,
8769 this shift constant is valid for the host, and we can do arithmetic
8770 in OP_MODE. */
8776 {
8780 /* Select the mask of the bits we need for the shift operand. */
8783 /* We can only change the mode of the shift if we can do arithmetic
8784 in the mode of the shift and INNER_MASK is no wider than the
8785 width of X's mode. */
8793 }
8795 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8796 shift and AND produces only copies of the sign bit (C2 is one less
8797 than a power of two), we can do this with just a shift. */
8801 /* The shift puts one of the sign bit copies in the least significant
8802 bit. */
8807 /* Number of bits left after the shift must be more than the mask
8808 needs. */
8811 /* Must be more sign bit copies than the mask needs. */
8821 /* If we are just looking for the sign bit, we don't need this shift at
8822 all, even if it has a variable count. */
8826 /* If this is a shift by a constant, get a mask that contains those bits
8827 that are not copies of the sign bit. We then have two cases: If
8828 MASK only includes those bits, this can be a logical shift, which may
8829 allow simplifications. If MASK is a single-bit field not within
8830 those bits, we are requesting a copy of the sign bit and hence can
8831 shift the sign bit to the appropriate location. */
8835 {
8838 /* If the considered data is wider than HOST_WIDE_INT, we can't
8839 represent a mask for all its bits in a single scalar.
8840 But we only care about the lower bits, so calculate these. */
8843 {
8846 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8847 is the number of bits a full-width mask would have set.
8848 We need only shift if these are fewer than nonzero can
8849 hold. If not, we must keep all bits set in nonzero. */
8854 + HOST_BITS_PER_WIDE_INT
8856 }
8857 else
8858 {
8861 }
8864 {
8869 }
8872 {
8873 x = simplify_shift_const
8879 }
8880 }
8882 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8883 even if the shift count isn't a constant. */
8888 shiftrt:
8890 /* If this is a zero- or sign-extension operation that just affects bits
8891 we don't care about, remove it. Be sure the call above returned
8892 something that is still a shift. */
8902 next_select);
8908 /* If the shift count is constant and we can do computations
8909 in the mode of X, compute where the bits we care about are.
8910 Otherwise, we can't do anything. Don't change the mode of
8911 the shift or propagate MODE into the shift, though. */
8914 {
8924 }
8928 /* If we just want the low-order bit, the NEG isn't needed since it
8929 won't change the low-order bit. */
8933 /* We need any bits less significant than the most significant bit in
8934 MASK since carries from those bits will affect the bits we are
8935 interested in. */
8940 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8941 same as the XOR case above. Ensure that the constant we form is not
8942 wider than the mode of X. */
8950 {
8959 }
8961 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8962 use the full mask inside the NOT. */
8965 unop:
8968 next_select));
8974 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8975 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8976 which is equal to STORE_FLAG_VALUE. */
8988 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8989 written in a narrower mode. We play it safe and do not do so. */
9005 }
9007 /* Ensure we return a value of the proper mode. */
9009 }
9010 \f
9011 /* Return nonzero if X is an expression that has one of two values depending on
9012 whether some other value is zero or nonzero. In that case, we return the
9013 value that is being tested, *PTRUE is set to the value if the rtx being
9014 returned has a nonzero value, and *PFALSE is set to the other alternative.
9016 If we return zero, we set *PTRUE and *PFALSE to X. */
9018 static rtx
9020 {
9026 /* If we are comparing a value against zero, we are done. */
9029 {
9033 }
9035 /* If this is a unary operation whose operand has one of two values, apply
9036 our opcode to compute those values. */
9039 {
9044 }
9046 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9047 make can't possibly match and would suppress other optimizations. */
9049 ;
9051 /* If this is a binary operation, see if either side has only one of two
9052 values. If either one does or if both do and they are conditional on
9053 the same value, compute the new true and false values. */
9055 {
9063 {
9064 /* Try to enable a simplification by undoing work done by
9065 if_then_else_cond if it converted a REG into something more
9066 complex. */
9068 {
9071 }
9072 else
9073 {
9076 }
9077 }
9081 {
9082 /* If if_then_else_cond returned zero, then true/false are the
9083 same rtl. We must copy one of them to prevent invalid rtl
9084 sharing. */
9091 {
9096 }
9097 else
9098 {
9101 }
9104 }
9106 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9107 operands is zero when the other is nonzero, and vice-versa,
9108 and STORE_FLAG_VALUE is 1 or -1. */
9114 {
9131 {
9138 const_true_rtx);
9140 }
9141 }
9143 /* Similarly for MULT, AND and UMIN, except that for these the result
9144 is always zero. */
9148 {
9162 {
9165 }
9166 }
9167 }
9170 {
9171 /* If we have IF_THEN_ELSE already, extract the condition and
9172 canonicalize it if it is NE or EQ. */
9178 {
9181 }
9182 else
9184 }
9186 /* If X is a SUBREG, we can narrow both the true and false values
9187 if the inner expression, if there is a condition. */
9191 {
9197 {
9201 }
9202 }
9204 /* If X is a constant, this isn't special and will cause confusions
9205 if we treat it as such. Likewise if it is equivalent to a constant. */
9208 ;
9210 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9211 will be least confusing to the rest of the compiler. */
9213 {
9216 }
9218 /* If X is known to be either 0 or -1, those are the true and
9219 false values when testing X. */
9223 {
9226 }
9228 /* Likewise for 0 or a single bit. */
9231 {
9234 }
9236 /* Otherwise fail; show no condition with true and false values the same. */
9239 }
9240 \f
9241 /* Return the value of expression X given the fact that condition COND
9242 is known to be true when applied to REG as its first operand and VAL
9243 as its second. X is known to not be shared and so can be modified in
9244 place.
9246 We only handle the simplest cases, and specifically those cases that
9247 arise with IF_THEN_ELSE expressions. */
9249 static rtx
9251 {
9259 /* If either operand of the condition is a floating point value,
9260 then we have to avoid collapsing an EQ comparison. */
9270 /* If X is (abs REG) and we know something about REG's relationship
9271 with zero, we may be able to simplify this. */
9275 {
9284 }
9286 /* The only other cases we handle are MIN, MAX, and comparisons if the
9287 operands are the same as REG and VAL. */
9290 {
9292 {
9295 }
9298 {
9300 {
9308 else
9310 }
9313 {
9316 /* Do not reverse the condition when it is NE or EQ.
9317 This is because we cannot conclude anything about
9318 the value of 'SMAX (x, y)' when x is not equal to y,
9319 but we can when x equals y. */
9325 {
9336 }
9337 }
9338 }
9339 }
9341 {
9346 {
9347 /* We must simplify subreg here, before we lose track of the
9348 original inner_mode. */
9353 else
9355 }
9358 }
9359 /* We don't have to handle SIGN_EXTEND here, because even in the
9360 case of replacing something with a modeless CONST_INT, a
9361 CONST_INT is already (supposed to be) a valid sign extension for
9362 its narrower mode, which implies it's already properly
9363 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9364 story is different. */
9366 {
9371 {
9372 /* We must simplify the zero_extend here, before we lose
9373 track of the original inner_mode. */
9378 else
9380 }
9383 }
9387 {
9394 }
9397 }
9398 \f
9399 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9400 assignment as a field assignment. */
9402 static int
9404 {
9406 {
9411 /* For big endian, adjust the memory offset. */
9416 else
9418 }
9426 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9427 Note that all SUBREGs of MEM are paradoxical; otherwise they
9428 would have been rewritten. */
9441 /* We used to see if get_last_value of X and Y were the same but that's
9442 not correct. In one direction, we'll cause the assignment to have
9443 the wrong destination and in the case, we'll import a register into this
9444 insn that might have already have been dead. So fail if none of the
9445 above cases are true. */
9447 }
9448 \f
9449 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9450 Return that assignment if so.
9452 We only handle the most common cases. */
9454 static rtx
9456 {
9459 rtx assign;
9461 HOST_WIDE_INT c1;
9462 HOST_WIDE_INT pos;
9464 rtx other;
9465 machine_mode mode;
9467 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9468 a clear of a one-bit field. We will have changed it to
9469 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9470 for a SUBREG. */
9476 {
9482 }
9492 {
9499 }
9501 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9502 one-bit field. */
9506 {
9512 }
9514 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9515 SRC is an AND with all bits of that field set, then we can discard
9516 the AND. */
9521 {
9528 else
9531 /* Complete overlap. We can remove the source AND. */
9535 /* Partial overlap. We can reduce the source AND. */
9537 {
9542 }
9543 }
9545 /* The other case we handle is assignments into a constant-position
9546 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9547 a mask that has all one bits except for a group of zero bits and
9548 OTHER is known to have zeros where C1 has ones, this is such an
9549 assignment. Compute the position and length from C1. Shift OTHER
9550 to the appropriate position, force it to the required mode, and
9551 make the extraction. Check for the AND in both operands. */
9553 /* One or more SUBREGs might obscure the constant-position field
9554 assignment. The first one we are likely to encounter is an outer
9555 narrowing SUBREG, which we can just strip for the purposes of
9556 identifying the constant-field assignment. */
9570 /* The second SUBREG that might get in the way is a paradoxical
9571 SUBREG around the first operand of the AND. We want to
9572 pretend the operand is as wide as the destination here. We
9573 do this by adjusting the MEM to wider mode for the sole
9574 purpose of the call to rtx_equal_for_field_assignment_p. Also
9575 note this trick only works for MEMs. */
9587 /* The second SUBREG that might get in the way is a paradoxical
9588 SUBREG around the first operand of the AND. We want to
9589 pretend the operand is as wide as the destination here. We
9590 do this by adjusting the MEM to wider mode for the sole
9591 purpose of the call to rtx_equal_for_field_assignment_p. Also
9592 note this trick only works for MEMs. */
9600 else
9613 /* The mode to use for the source is the mode of the assignment, or of
9614 what is inside a possible STRICT_LOW_PART. */
9618 /* Shift OTHER right POS places and make it the source, restricting it
9619 to the proper length and mode. */
9624 dest);
9627 ? HOST_WIDE_INT_M1U
9631 /* If SRC is masked by an AND that does not make a difference in
9632 the value being stored, strip it. */
9643 }
9644 \f
9645 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9646 if so. */
9648 static rtx
9650 {
9654 rtx tem;
9656 /* Distributivity is not true for floating point as it can change the
9657 value. So we don't do it unless -funsafe-math-optimizations. */
9662 /* The outer operation can only be one of the following: */
9670 /* If either operand is a primitive we can't do anything, so get out
9671 fast. */
9681 /* See if the inner and outer operations distribute. */
9683 {
9688 /* These all distribute except over PLUS. */
9699 /* This is also a multiply, so it distributes over everything. */
9702 /* This used to handle SUBREG, but this turned out to be counter-
9703 productive, since (subreg (op ...)) usually is not handled by
9704 insn patterns, and this "optimization" therefore transformed
9705 recognizable patterns into unrecognizable ones. Therefore the
9706 SUBREG case was removed from here.
9708 It is possible that distributing SUBREG over arithmetic operations
9709 leads to an intermediate result than can then be optimized further,
9710 e.g. by moving the outer SUBREG to the other side of a SET as done
9711 in simplify_set. This seems to have been the original intent of
9712 handling SUBREGs here.
9714 However, with current GCC this does not appear to actually happen,
9715 at least on major platforms. If some case is found where removing
9716 the SUBREG case here prevents follow-on optimizations, distributing
9717 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9721 }
9723 /* Set LHS and RHS to the inner operands (A and B in the example
9724 above) and set OTHER to the common operand (C in the example).
9725 There is only one way to do this unless the inner operation is
9726 commutative. */
9738 else
9741 /* Form the new inner operation, seeing if it simplifies first. */
9744 /* There is one exception to the general way of distributing:
9745 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9747 {
9750 }
9752 /* We may be able to continuing distributing the result, so call
9753 ourselves recursively on the inner operation before forming the
9754 outer operation, which we return. */
9757 }
9759 /* See if X is of the form (* (+ A B) C), and if so convert to
9760 (+ (* A C) (* B C)) and try to simplify.
9762 Most of the time, this results in no change. However, if some of
9763 the operands are the same or inverses of each other, simplifications
9764 will result.
9766 For example, (and (ior A B) (not B)) can occur as the result of
9767 expanding a bit field assignment. When we apply the distributive
9768 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9769 which then simplifies to (and (A (not B))).
9771 Note that no checks happen on the validity of applying the inverse
9772 distributive law. This is pointless since we can do it in the
9773 few places where this routine is called.
9775 N is the index of the term that is decomposed (the arithmetic operation,
9776 i.e. (+ A B) in the first example above). !N is the index of the term that
9777 is distributed, i.e. of C in the first example above. */
9778 static rtx
9780 {
9781 machine_mode mode;
9785 /* Distributivity is not true for floating point as it can change the
9786 value. So we don't do it unless -funsafe-math-optimizations. */
9803 /* Special case (and (xor B C) (not A)), which is equivalent to
9804 (xor (ior A B) (ior A C)) */
9806 {
9809 }
9812 {
9813 /* Distribute the second term. */
9816 }
9817 else
9818 {
9819 /* Distribute the first term. */
9822 }
9832 }
9833 \f
9834 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9835 in MODE. Return an equivalent form, if different from (and VAROP
9836 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9838 static rtx
9841 {
9844 rtx orig_varop;
9852 /* Simplify VAROP knowing that we will be only looking at some of the
9853 bits in it.
9855 Note by passing in CONSTOP, we guarantee that the bits not set in
9856 CONSTOP are not significant and will never be examined. We must
9857 ensure that is the case by explicitly masking out those bits
9858 before returning. */
9861 /* If VAROP is a CLOBBER, we will fail so return it. */
9865 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9866 to VAROP and return the new constant. */
9870 /* See what bits may be nonzero in VAROP. Unlike the general case of
9871 a call to nonzero_bits, here we don't care about bits outside
9872 MODE. */
9876 /* Turn off all bits in the constant that are known to already be zero.
9877 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9878 which is tested below. */
9882 /* If we don't have any bits left, return zero. */
9886 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9887 a power of two, we can replace this with an ASHIFT. */
9892 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9893 or XOR, then try to apply the distributive law. This may eliminate
9894 operations if either branch can be simplified because of the AND.
9895 It may also make some cases more complex, but those cases probably
9896 won't match a pattern either with or without this. */
9899 return
9900 gen_lowpart
9902 apply_distributive_law
9907 constop),
9911 constop))));
9913 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9914 the AND and see if one of the operands simplifies to zero. If so, we
9915 may eliminate it. */
9919 {
9928 }
9930 /* Make a SUBREG if necessary. If we can't make it, fail. */
9935 /* If we are only masking insignificant bits, return VAROP. */
9942 /* Otherwise, return an AND. */
9944 }
9947 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9948 in MODE.
9950 Return an equivalent form, if different from X. Otherwise, return X. If
9951 X is zero, we are to always construct the equivalent form. */
9953 static rtx
9956 {
9967 }
9968 \f
9969 /* Given a REG, X, compute which bits in X can be nonzero.
9970 We don't care about bits outside of those defined in MODE.
9972 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9973 a shift, AND, or zero_extract, we can do better. */
9975 static rtx
9977 const_rtx known_x ATTRIBUTE_UNUSED,
9978 machine_mode known_mode ATTRIBUTE_UNUSED,
9981 {
9982 rtx tem;
9985 /* If X is a register whose nonzero bits value is current, use it.
9986 Otherwise, if X is a register whose value we can find, use that
9987 value. Otherwise, use the previously-computed global nonzero bits
9988 for this register. */
10002 && !REGNO_REG_SET_P
10005 {
10006 /* Note that, even if the precision of last_set_mode is lower than that
10007 of mode, record_value_for_reg invoked nonzero_bits on the register
10008 with nonzero_bits_mode (because last_set_mode is necessarily integral
10009 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10010 are all valid, hence in mode too since nonzero_bits_mode is defined
10011 to the largest HWI_COMPUTABLE_MODE_P mode. */
10014 }
10018 {
10024 }
10027 {
10031 /* We don't know anything about the upper bits. */
10035 }
10038 }
10040 /* Return the number of bits at the high-order end of X that are known to
10041 be equal to the sign bit. X will be used in mode MODE; if MODE is
10042 VOIDmode, X will be used in its own mode. The returned value will always
10043 be between 1 and the number of bits in MODE. */
10045 static rtx
10047 const_rtx known_x ATTRIBUTE_UNUSED,
10048 machine_mode known_mode
10049 ATTRIBUTE_UNUSED,
10052 {
10053 rtx tem;
10066 && !REGNO_REG_SET_P
10069 {
10072 }
10083 }
10084 \f
10085 /* Return the number of "extended" bits there are in X, when interpreted
10086 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10087 unsigned quantities, this is the number of high-order zero bits.
10088 For signed quantities, this is the number of copies of the sign bit
10089 minus 1. In both case, this function returns the number of "spare"
10090 bits. For example, if two quantities for which this function returns
10091 at least 1 are added, the addition is known not to overflow.
10093 This function will always return 0 unless called during combine, which
10094 implies that it must be called from a define_split. */
10096 unsigned int
10098 {
10108 }
10110 /* This function is called from `simplify_shift_const' to merge two
10111 outer operations. Specifically, we have already found that we need
10112 to perform operation *POP0 with constant *PCONST0 at the outermost
10113 position. We would now like to also perform OP1 with constant CONST1
10114 (with *POP0 being done last).
10116 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10117 the resulting operation. *PCOMP_P is set to 1 if we would need to
10118 complement the innermost operand, otherwise it is unchanged.
10120 MODE is the mode in which the operation will be done. No bits outside
10121 the width of this mode matter. It is assumed that the width of this mode
10122 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10124 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10125 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10126 result is simply *PCONST0.
10128 If the resulting operation cannot be expressed as one operation, we
10129 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10131 static int
10132 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10133 {
10140 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10144 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10145 if OP0 is SET. */
10154 {
10156 {
10174 }
10175 }
10177 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10181 /* If the two constants aren't the same, we can't do anything. The
10182 remaining six cases can all be done. */
10186 else
10188 {
10191 /* (a & b) | b == b */
10194 /* (a ^ b) | b == a | b */
10195 {;}
10200 /* (a & b) ^ b == (~a) & b */
10203 /* (a | b) ^ b == a & ~b */
10209 /* (a | b) & b == b */
10212 /* (a ^ b) & b) == (~a) & b */
10217 }
10219 /* Check for NO-OP cases. */
10232 /* ??? Slightly redundant with the above mask, but not entirely.
10233 Moving this above means we'd have to sign-extend the mode mask
10234 for the final test. */
10239 }
10240 \f
10241 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10242 the shift in. The original shift operation CODE is performed on OP in
10243 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10244 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10245 result of the shift is subject to operation OUTER_CODE with operand
10246 OUTER_CONST. */
10248 static machine_mode
10252 {
10257 /* In general we can't perform in wider mode for right shift and rotate. */
10259 {
10261 /* We can still widen if the bits brought in from the left are identical
10262 to the sign bit of ORIG_MODE. */
10270 /* Similarly here but with zero bits. */
10275 /* We can also widen if the bits brought in will be masked off. This
10276 operation is performed in ORIG_MODE. */
10278 {
10284 }
10285 /* fall through */
10295 }
10296 }
10298 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10299 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10300 if we cannot simplify it. Otherwise, return a simplified value.
10302 The shift is normally computed in the widest mode we find in VAROP, as
10303 long as it isn't a different number of words than RESULT_MODE. Exceptions
10304 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10306 static rtx
10309 {
10315 unsigned int mode_words
10317 /* We form (outer_op (code varop count) (outer_const)). */
10323 /* Make sure and truncate the "natural" shift on the way in. We don't
10324 want to do this inside the loop as it makes it more difficult to
10325 combine shifts. */
10329 /* If we were given an invalid count, don't do anything except exactly
10330 what was requested. */
10337 /* Unless one of the branches of the `if' in this loop does a `continue',
10338 we will `break' the loop after the `if'. */
10341 {
10342 /* If we have an operand of (clobber (const_int 0)), fail. */
10346 /* Convert ROTATERT to ROTATE. */
10348 {
10352 }
10358 /* Handle cases where the count is greater than the size of the mode
10359 minus 1. For ASHIFT, use the size minus one as the count (this can
10360 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10361 take the count modulo the size. For other shifts, the result is
10362 zero.
10364 Since these shifts are being produced by the compiler by combining
10365 multiple operations, each of which are defined, we know what the
10366 result is supposed to be. */
10369 {
10374 else
10375 {
10376 /* We can't simply return zero because there may be an
10377 outer op. */
10381 }
10382 }
10384 /* If we discovered we had to complement VAROP, leave. Making a NOT
10385 here would cause an infinite loop. */
10390 {
10391 /* An arithmetic right shift of a quantity known to be -1 or 0
10392 is a no-op. */
10396 {
10399 }
10401 /* If we are doing an arithmetic right shift and discarding all but
10402 the sign bit copies, this is equivalent to doing a shift by the
10403 bitsize minus one. Convert it into that shift because it will
10404 often allow other simplifications. */
10411 /* We simplify the tests below and elsewhere by converting
10412 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10413 `make_compound_operation' will convert it to an ASHIFTRT for
10414 those machines (such as VAX) that don't have an LSHIFTRT. */
10419 shift_unit_mode)))
10431 }
10434 {
10441 {
10444 }
10448 /* The following rules apply only to scalars. */
10452 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10453 minus the width of a smaller mode, we can do this with a
10454 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10461 {
10470 }
10474 /* The following rules apply only to scalars. */
10478 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10479 the same number of words as what we've seen so far. Then store
10480 the widest mode in MODE. */
10486 == mode_words
10489 {
10494 }
10498 /* Some machines use MULT instead of ASHIFT because MULT
10499 is cheaper. But it is still better on those machines to
10500 merge two shifts into one. */
10503 {
10504 varop
10510 }
10514 /* Similar, for when divides are cheaper. */
10517 {
10518 varop
10524 }
10528 /* If we are extracting just the sign bit of an arithmetic
10529 right shift, that shift is not needed. However, the sign
10530 bit of a wider mode may be different from what would be
10531 interpreted as the sign bit in a narrower mode, so, if
10532 the result is narrower, don't discard the shift. */
10537 {
10540 }
10542 /* fall through */
10547 /* The following rules apply only to scalars. */
10551 /* Here we have two nested shifts. The result is usually the
10552 AND of a new shift with a mask. We compute the result below. */
10558 {
10562 rtx mask_rtx;
10564 /* We have one common special case. We can't do any merging if
10565 the inner code is an ASHIFTRT of a smaller mode. However, if
10566 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10567 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10568 we can convert it to
10569 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10570 This simplifies certain SIGN_EXTEND operations. */
10574 {
10575 /* C3 has the low-order C1 bits zero. */
10587 }
10589 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10590 than C1 high-order bits equal to the sign bit, we can convert
10591 this to either an ASHIFT or an ASHIFTRT depending on the
10592 two counts.
10594 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10600 {
10604 {
10607 }
10610 }
10612 /* There are some cases we can't do. If CODE is ASHIFTRT,
10613 we can only do this if FIRST_CODE is also ASHIFTRT.
10615 We can't do the case when CODE is ROTATE and FIRST_CODE is
10616 ASHIFTRT.
10618 If the mode of this shift is not the mode of the outer shift,
10619 we can't do this if either shift is a right shift or ROTATE.
10621 Finally, we can't do any of these if the mode is too wide
10622 unless the codes are the same.
10624 Handle the case where the shift codes are the same
10625 first. */
10628 {
10637 }
10648 /* To compute the mask to apply after the shift, shift the
10649 nonzero bits of the inner shift the same way the
10650 outer shift will. */
10653 result_mode);
10655 mask_rtx
10659 /* Give up if we can't compute an outer operation to use. */
10667 /* If the shifts are in the same direction, we add the
10668 counts. Otherwise, we subtract them. */
10672 else
10675 /* If COUNT is positive, the new shift is usually CODE,
10676 except for the two exceptions below, in which case it is
10677 FIRST_CODE. If the count is negative, FIRST_CODE should
10678 always be used */
10688 }
10690 /* If we have (A << B << C) for any shift, we can convert this to
10691 (A << C << B). This wins if A is a constant. Only try this if
10692 B is not a constant. */
10697 {
10698 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10699 sure the result will be masked. See PR70222. */
10707 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10708 up outer sign extension (often left and right shift) is
10709 hardly more efficient than the original. See PR70429. */
10719 }
10723 /* The following rules apply only to scalars. */
10727 /* Make this fit the case below. */
10734 /* The following rules apply only to scalars. */
10738 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10739 with C the size of VAROP - 1 and the shift is logical if
10740 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10741 we have an (le X 0) operation. If we have an arithmetic shift
10742 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10743 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10751 {
10754 const0_rtx);
10760 }
10762 /* If we have (shift (logical)), move the logical to the outside
10763 to allow it to possibly combine with another logical and the
10764 shift to combine with another shift. This also canonicalizes to
10765 what a ZERO_EXTRACT looks like. Also, some machines have
10766 (and (shift)) insns. */
10769 /* We can't do this if we have (ashiftrt (xor)) and the
10770 constant has its sign bit set in shift_mode with shift_mode
10771 wider than result_mode. */
10775 shift_mode))
10783 {
10786 }
10788 /* If we can't do that, try to simplify the shift in each arm of the
10789 logical expression, make a new logical expression, and apply
10790 the inverse distributive law. This also can't be done for
10791 (ashiftrt (xor)) where we've widened the shift and the constant
10792 changes the sign bit. */
10797 shift_mode)))
10798 {
10810 }
10814 /* The following rules apply only to scalars. */
10818 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10819 says that the sign bit can be tested, FOO has mode MODE, C is
10820 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10821 that may be nonzero. */
10831 {
10835 }
10839 /* The following rules apply only to scalars. */
10843 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10844 than the number of bits in the mode is equivalent to A. */
10848 {
10852 }
10854 /* NEG commutes with ASHIFT since it is multiplication. Move the
10855 NEG outside to allow shifts to combine. */
10859 {
10862 }
10866 /* The following rules apply only to scalars. */
10870 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10871 is one less than the number of bits in the mode is
10872 equivalent to (xor A 1). */
10879 {
10883 }
10885 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10886 that might be nonzero in BAR are those being shifted out and those
10887 bits are known zero in FOO, we can replace the PLUS with FOO.
10888 Similarly in the other operand order. This code occurs when
10889 we are computing the size of a variable-size array. */
10896 {
10899 }
10907 result_mode)))
10908 {
10911 }
10913 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10923 {
10926 }
10928 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10929 signbit', and attempt to change the PLUS to an XOR and move it to
10930 the outer operation as is done above in the AND/IOR/XOR case
10931 leg for shift(logical). See details in logical handling above
10932 for reasoning in doing so. */
10943 {
10946 }
10951 /* The following rules apply only to scalars. */
10955 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10956 with C the size of VAROP - 1 and the shift is logical if
10957 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10958 we have a (gt X 0) operation. If the shift is arithmetic with
10959 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10960 we have a (neg (gt X 0)) operation. */
10969 {
10972 const0_rtx);
10978 }
10982 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10983 if the truncate does not affect the value. */
10990 {
10993 varop_inner
10996 GEN_INT
11001 }
11006 }
11009 }
11014 /* We have now finished analyzing the shift. The result should be
11015 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11016 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11017 to the result of the shift. OUTER_CONST is the relevant constant,
11018 but we must turn off all bits turned off in the shift. */
11026 /* Make a SUBREG if necessary. If we can't make it, fail. */
11031 /* If we have an outer operation and we just made a shift, it is
11032 possible that we could have simplified the shift were it not
11033 for the outer operation. So try to do the simplification
11034 recursively. */
11038 else
11044 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11045 turn off all the bits that the shift would have turned off. */
11050 /* Do the remainder of the processing in RESULT_MODE. */
11053 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11054 operation. */
11059 {
11067 {
11068 /* This means that we have determined that the result is
11069 equivalent to a constant. This should be rare. */
11072 }
11075 else
11078 }
11081 }
11083 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11084 The result of the shift is RESULT_MODE. If we cannot simplify it,
11085 return X or, if it is NULL, synthesize the expression with
11086 simplify_gen_binary. Otherwise, return a simplified value.
11088 The shift is normally computed in the widest mode we find in VAROP, as
11089 long as it isn't a different number of words than RESULT_MODE. Exceptions
11090 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11092 static rtx
11095 {
11105 }
11107 \f
11108 /* A subroutine of recog_for_combine. See there for arguments and
11109 return value. */
11111 static int
11113 {
11115 rtx pat_without_clobbers;
11123 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11124 we use to indicate that something didn't match. If we find such a
11125 thing, force rejection. */
11139 {
11142 else
11145 }
11147 /* If it isn't, there is the possibility that we previously had an insn
11148 that clobbered some register as a side effect, but the combined
11149 insn doesn't need to do that. So try once more without the clobbers
11150 unless this represents an ASM insn. */
11154 {
11159 {
11162 pos++;
11163 }
11173 {
11176 else
11179 }
11180 }
11187 /* Recognize all noop sets, these will be killed by followup pass. */
11191 /* If we had any clobbers to add, make a new pattern than contains
11192 them. Then check to make sure that all of them are dead. */
11194 {
11204 else
11211 {
11216 {
11220 }
11221 }
11223 }
11227 {
11235 /* Allow targets to reject combined insn. */
11237 {
11240 dump_file);
11242 /* Callers expect recog_for_combine to strip
11243 clobbers from the pattern on failure. */
11248 }
11253 }
11259 }
11261 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11262 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11263 Return whether anything was so changed. */
11265 static bool
11267 {
11273 {
11284 {
11295 else
11299 }
11306 {
11311 }
11317 {
11320 }
11321 else
11327 {
11330 }
11334 }
11345 {
11360 else
11368 }
11371 }
11373 /* Like recog, but we receive the address of a pointer to a new pattern.
11374 We try to match the rtx that the pointer points to.
11375 If that fails, we may try to modify or replace the pattern,
11376 storing the replacement into the same pointer object.
11378 Modifications include deletion or addition of CLOBBERs. If the
11379 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11380 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11381 (and undo if that fails).
11383 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11384 the CLOBBERs are placed.
11386 The value is the final insn code from the pattern ultimately matched,
11387 or -1. */
11389 static int
11391 {
11403 {
11406 {
11410 }
11411 }
11414 {
11419 }
11422 }
11423 \f
11424 /* Like gen_lowpart_general but for use by combine. In combine it
11425 is not possible to create any new pseudoregs. However, it is
11426 safe to create invalid memory addresses, because combine will
11427 try to recognize them and all they will do is make the combine
11428 attempt fail.
11430 If for some reason this cannot do its job, an rtx
11431 (clobber (const_int 0)) is returned.
11432 An insn containing that will not be recognized. */
11434 static rtx
11436 {
11440 rtx result;
11445 /* We can only support MODE being wider than a word if X is a
11446 constant integer or has a mode the same size. */
11451 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11452 won't know what to do. So we will strip off the SUBREG here and
11453 process normally. */
11455 {
11458 /* For use in case we fall down into the address adjustments
11459 further below, we need to adjust the known mode and size of
11460 x; imode and isize, since we just adjusted x. */
11467 }
11475 {
11478 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11479 address. */
11484 /* If we want to refer to something bigger than the original memref,
11485 generate a paradoxical subreg instead. That will force a reload
11486 of the original memref X. */
11493 /* Adjust the address so that the address-after-the-data is
11494 unchanged. */
11499 }
11501 /* If X is a comparison operator, rewrite it in a new mode. This
11502 probably won't match, but may allow further simplifications. */
11506 /* If we couldn't simplify X any other way, just enclose it in a
11507 SUBREG. Normally, this SUBREG won't match, but some patterns may
11508 include an explicit SUBREG or we may simplify it further in combine. */
11509 else
11510 {
11511 rtx res;
11514 {
11519 }
11523 }
11525 fail:
11527 }
11528 \f
11529 /* Try to simplify a comparison between OP0 and a constant OP1,
11530 where CODE is the comparison code that will be tested, into a
11531 (CODE OP0 const0_rtx) form.
11533 The result is a possibly different comparison code to use.
11534 *POP1 may be updated. */
11536 static enum rtx_code
11539 {
11543 /* Get the constant we are comparing against and turn off all bits
11544 not on in our mode. */
11548 /* If we are comparing against a constant power of two and the value
11549 being compared can only have that single bit nonzero (e.g., it was
11550 `and'ed with that bit), we can replace this with a comparison
11551 with zero. */
11559 {
11562 }
11564 /* Similarly, if we are comparing a value known to be either -1 or
11565 0 with -1, change it to the opposite comparison against zero. */
11570 {
11573 }
11575 /* Do some canonicalizations based on the comparison code. We prefer
11576 comparisons against zero and then prefer equality comparisons.
11577 If we can reduce the size of a constant, we will do that too. */
11579 {
11581 /* < C is equivalent to <= (C - 1) */
11583 {
11586 /* ... fall through to LE case below. */
11588 }
11589 else
11593 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11595 {
11598 }
11600 /* If we are doing a <= 0 comparison on a value known to have
11601 a zero sign bit, we can replace this with == 0. */
11611 /* >= C is equivalent to > (C - 1). */
11613 {
11616 /* ... fall through to GT below. */
11618 }
11619 else
11623 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11625 {
11628 }
11630 /* If we are doing a > 0 comparison on a value known to have
11631 a zero sign bit, we can replace this with != 0. */
11641 /* < C is equivalent to <= (C - 1). */
11643 {
11646 /* ... fall through ... */
11647 }
11648 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11652 {
11656 }
11657 else
11661 /* unsigned <= 0 is equivalent to == 0 */
11664 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11668 {
11671 }
11675 /* >= C is equivalent to > (C - 1). */
11677 {
11680 /* ... fall through ... */
11681 }
11683 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11687 {
11691 }
11692 else
11696 /* unsigned > 0 is equivalent to != 0 */
11699 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11703 {
11706 }
11711 }
11715 }
11716 \f
11717 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11718 comparison code that will be tested.
11720 The result is a possibly different comparison code to use. *POP0 and
11721 *POP1 may be updated.
11723 It is possible that we might detect that a comparison is either always
11724 true or always false. However, we do not perform general constant
11725 folding in combine, so this knowledge isn't useful. Such tautologies
11726 should have been detected earlier. Hence we ignore all such cases. */
11728 static enum rtx_code
11730 {
11737 /* Try a few ways of applying the same transformation to both operands. */
11739 {
11740 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11741 so check specially. */
11757 - (GET_MODE_PRECISION
11759 {
11762 }
11764 /* If both operands are the same constant shift, see if we can ignore the
11765 shift. We can if the shift is a rotate or if the bits shifted out of
11766 this shift are known to be zero for both inputs and if the type of
11767 comparison is compatible with the shift. */
11780 {
11793 else
11795 }
11797 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11798 SUBREGs are of the same mode, and, in both cases, the AND would
11799 be redundant if the comparison was done in the narrower mode,
11800 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11801 and the operand's possibly nonzero bits are 0xffffff01; in that case
11802 if we only care about QImode, we don't need the AND). This case
11803 occurs if the output mode of an scc insn is not SImode and
11804 STORE_FLAG_VALUE == 1 (e.g., the 386).
11806 Similarly, check for a case where the AND's are ZERO_EXTEND
11807 operations from some narrower mode even though a SUBREG is not
11808 present. */
11813 {
11830 {
11834 /* The resulting comparison is always unsigned since we masked
11835 off the original sign bit. */
11839 }
11846 {
11852 }
11856 }
11858 /* If both operands are NOT, we can strip off the outer operation
11859 and adjust the comparison code for swapped operands; similarly for
11860 NEG, except that this must be an equality comparison. */
11866 else
11868 }
11870 /* If the first operand is a constant, swap the operands and adjust the
11871 comparison code appropriately, but don't do this if the second operand
11872 is already a constant integer. */
11874 {
11877 }
11879 /* We now enter a loop during which we will try to simplify the comparison.
11880 For the most part, we only are concerned with comparisons with zero,
11881 but some things may really be comparisons with zero but not start
11882 out looking that way. */
11885 {
11892 HOST_WIDE_INT const_op;
11894 /* We only want to handle integral modes. This catches VOIDmode,
11895 CCmode, and the floating-point modes. An exception is that we
11896 can handle VOIDmode if OP0 is a COMPARE or a comparison
11897 operation. */
11904 /* Try to simplify the compare to constant, possibly changing the
11905 comparison op, and/or changing op1 to zero. */
11909 /* Compute some predicates to simplify code below. */
11916 /* If this is a sign bit comparison and we can do arithmetic in
11917 MODE, say that we will only be needing the sign bit of OP0. */
11920 HOST_WIDE_INT_1U
11924 /* Now try cases based on the opcode of OP0. If none of the cases
11925 does a "continue", we exit this loop immediately after the
11926 switch. */
11929 {
11931 /* If we are extracting a single bit from a variable position in
11932 a constant that has only a single bit set and are comparing it
11933 with zero, we can convert this into an equality comparison
11934 between the position and the location of the single bit. */
11935 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11936 have already reduced the shift count modulo the word size. */
11942 {
11950 /* Result is nonzero iff shift count is equal to I. */
11953 }
11955 /* fall through */
11960 {
11963 }
11967 /* If testing for equality, we can take the NOT of the constant. */
11970 {
11974 }
11976 /* If just looking at the sign bit, reverse the sense of the
11977 comparison. */
11979 {
11983 }
11987 /* If testing for equality, we can take the NEG of the constant. */
11990 {
11994 }
11996 /* The remaining cases only apply to comparisons with zero. */
12000 /* When X is ABS or is known positive,
12001 (neg X) is < 0 if and only if X != 0. */
12009 {
12013 }
12015 /* If we have NEG of something whose two high-order bits are the
12016 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12018 {
12022 }
12026 /* If we are testing equality and our count is a constant, we
12027 can perform the inverse operation on our RHS. */
12031 {
12035 }
12037 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12038 a particular bit. Convert it to an AND of a constant of that
12039 bit. This will be converted into a ZERO_EXTRACT. */
12043 {
12045 (HOST_WIDE_INT_1U
12050 }
12052 /* Fall through. */
12055 /* ABS is ignorable inside an equality comparison with zero. */
12057 {
12060 }
12064 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12065 (compare FOO CONST) if CONST fits in FOO's mode and we
12066 are either testing inequality or have an unsigned
12067 comparison with ZERO_EXTEND or a signed comparison with
12068 SIGN_EXTEND. But don't do it if we don't have a compare
12069 insn of the given mode, since we'd have to revert it
12070 later on, and then we wouldn't know whether to sign- or
12071 zero-extend. */
12074 && ! unsigned_comparison_p
12078 {
12081 }
12085 /* Check for the case where we are comparing A - C1 with C2, that is
12087 (subreg:MODE (plus (A) (-C1))) op (C2)
12089 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12090 comparison in the wider mode. One of the following two conditions
12091 must be true in order for this to be valid:
12093 1. The mode extension results in the same bit pattern being added
12094 on both sides and the comparison is equality or unsigned. As
12095 C2 has been truncated to fit in MODE, the pattern can only be
12096 all 0s or all 1s.
12098 2. The mode extension results in the sign bit being copied on
12099 each side.
12101 The difficulty here is that we have predicates for A but not for
12102 (A - C1) so we need to check that C1 is within proper bounds so
12103 as to perturbate A as little as possible. */
12110 {
12119 /* (A - C1) zero-extends if it is positive and sign-extends
12120 if it is negative, C2 both zero- and sign-extends. */
12124 /* (A - C1) sign-extends if it is positive and 1-extends
12125 if it is negative, C2 both sign- and 1-extends. */
12132 /* (A - C1) always sign-extends, like C2. */
12136 {
12139 }
12140 }
12142 /* If the inner mode is narrower and we are extracting the low part,
12143 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12146 ;
12157 {
12158 /* Remove outer subregs that don't do anything. */
12163 {
12167 }
12169 }
12170 else
12173 /* FALLTHROUGH */
12183 {
12186 }
12190 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12191 this for equality comparisons due to pathological cases involving
12192 overflows. */
12196 {
12200 }
12202 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12205 {
12209 }
12213 /* We used to optimize signed comparisons against zero, but that
12214 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12215 arrive here as equality comparisons, or (GEU, LTU) are
12216 optimized away. No need to special-case them. */
12218 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12219 (eq B (minus A C)), whichever simplifies. We can only do
12220 this for equality comparisons due to pathological cases involving
12221 overflows. */
12225 {
12229 }
12234 {
12238 }
12240 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12241 of bits in X minus 1, is one iff X > 0. */
12246 {
12250 }
12254 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12255 if C is zero or B is a constant. */
12259 {
12263 }
12271 /* We can't do anything if OP0 is a condition code value, rather
12272 than an actual data value. */
12278 /* Get the two operands being compared. */
12281 else
12284 /* Check for the cases where we simply want the result of the
12285 earlier test or the opposite of that result. */
12289 {
12293 else
12297 {
12302 }
12303 }
12307 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12308 iff X <= 0. */
12312 {
12316 }
12320 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12321 will be converted to a ZERO_EXTRACT later. */
12325 {
12330 }
12332 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12333 zero and X is a comparison and C1 and C2 describe only bits set
12334 in STORE_FLAG_VALUE, we can compare with X. */
12342 {
12349 {
12352 }
12353 }
12355 /* If we are doing an equality comparison of an AND of a bit equal
12356 to the sign bit, replace this with a LT or GE comparison of
12357 the underlying value. */
12364 {
12368 }
12370 /* If this AND operation is really a ZERO_EXTEND from a narrower
12371 mode, the constant fits within that mode, and this is either an
12372 equality or unsigned comparison, try to do this comparison in
12373 the narrower mode.
12375 Note that in:
12377 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12378 -> (ne:DI (reg:SI 4) (const_int 0))
12380 unless TRULY_NOOP_TRUNCATION allows it or the register is
12381 known to hold a value of the required mode the
12382 transformation is invalid. */
12390 {
12393 }
12395 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12396 fits in both M1 and M2 and the SUBREG is either paradoxical
12397 or represents the low part, permute the SUBREG and the AND
12398 and try again. */
12401 {
12404 /* Require an integral mode, to avoid creating something like
12405 (AND:SF ...). */
12407 /* It is unsafe to commute the AND into the SUBREG if the
12408 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12409 not defined. As originally written the upper bits
12410 have a defined value due to the AND operation.
12411 However, if we commute the AND inside the SUBREG then
12412 they no longer have defined values and the meaning of
12413 the code has been changed.
12414 Also C1 should not change value in the smaller mode,
12415 see PR67028 (a positive C1 can become negative in the
12416 smaller mode, so that the AND does no longer mask the
12417 upper bits). */
12418 && ((WORD_REGISTER_OPERATIONS
12430 {
12436 }
12437 }
12439 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12443 {
12448 }
12450 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12451 (eq (and (lshiftrt X) 1) 0).
12452 Also handle the case where (not X) is expressed using xor. */
12456 {
12466 == HOST_WIDE_INT_1U
12468 {
12469 op0
12474 }
12475 }
12479 /* If we have (compare (ashift FOO N) (const_int C)) and
12480 the high order N bits of FOO (N+1 if an inequality comparison)
12481 are known to be zero, we can do this by comparing FOO with C
12482 shifted right N bits so long as the low-order N bits of C are
12483 zero. */
12495 {
12496 /* We must perform a logical shift, not an arithmetic one,
12497 as we want the top N bits of C to be zero. */
12504 }
12506 /* If we are doing a sign bit comparison, it means we are testing
12507 a particular bit. Convert it to the appropriate AND. */
12510 {
12512 (HOST_WIDE_INT_1U
12517 }
12519 /* If this an equality comparison with zero and we are shifting
12520 the low bit to the sign bit, we can convert this to an AND of the
12521 low-order bit. */
12525 {
12528 }
12532 /* If this is an equality comparison with zero, we can do this
12533 as a logical shift, which might be much simpler. */
12536 {
12541 }
12543 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12544 do the comparison in a narrower mode. */
12554 {
12557 }
12559 /* Likewise if OP0 is a PLUS of a sign extension with a
12560 constant, which is usually represented with the PLUS
12561 between the shifts. */
12573 {
12581 new_const);
12583 }
12585 /* FALLTHROUGH */
12587 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12588 the low order N bits of FOO are known to be zero, we can do this
12589 by comparing FOO with C shifted left N bits so long as no
12590 overflow occurs. Even if the low order N bits of FOO aren't known
12591 to be zero, if the comparison is >= or < we can use the same
12592 optimization and for > or <= by setting all the low
12593 order N bits in the comparison constant. */
12604 {
12605 unsigned HOST_WIDE_INT low_bits
12607 & ((HOST_WIDE_INT_1U
12610 {
12611 /* If the shift was logical, then we must make the condition
12612 unsigned. */
12621 const_op
12626 }
12627 }
12629 /* If we are using this shift to extract just the sign bit, we
12630 can replace this with an LT or GE comparison. */
12635 {
12639 }
12644 }
12647 }
12649 /* Now make any compound operations involved in this comparison. Then,
12650 check for an outmost SUBREG on OP0 that is not doing anything or is
12651 paradoxical. The latter transformation must only be performed when
12652 it is known that the "extra" bits will be the same in op0 and op1 or
12653 that they don't matter. There are three cases to consider:
12655 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12656 care bits and we can assume they have any convenient value. So
12657 making the transformation is safe.
12659 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12660 In this case the upper bits of op0 are undefined. We should not make
12661 the simplification in that case as we do not know the contents of
12662 those bits.
12664 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12665 In that case we know those bits are zeros or ones. We must also be
12666 sure that they are the same as the upper bits of op1.
12668 We can never remove a SUBREG for a non-equality comparison because
12669 the sign bit is in a different place in the underlying object. */
12682 {
12684 {
12685 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12686 implemented. */
12688 {
12691 }
12692 }
12698 {
12704 }
12705 }
12707 /* We now do the opposite procedure: Some machines don't have compare
12708 insns in all modes. If OP0's mode is an integer mode smaller than a
12709 word and we can't do a compare in that mode, see if there is a larger
12710 mode for which we can do the compare. There are a number of cases in
12711 which we can use the wider mode. */
12721 {
12724 /* If this is a test for negative, we can make an explicit
12725 test of the sign bit. Test this first so we can use
12726 a paradoxical subreg to extend OP0. */
12730 {
12731 unsigned HOST_WIDE_INT sign
12738 }
12740 /* If the only nonzero bits in OP0 and OP1 are those in the
12741 narrower mode and this is an equality or unsigned comparison,
12742 we can use the wider mode. Similarly for sign-extended
12743 values, in which case it is true for all comparisons. */
12760 {
12761 /* If OP0 is an AND and we don't have an AND in MODE either,
12762 make a new AND in the proper mode. */
12770 else
12771 {
12773 {
12776 }
12777 else
12778 {
12781 }
12783 }
12784 }
12785 }
12787 /* We may have changed the comparison operands. Re-canonicalize. */
12789 {
12792 }
12794 /* If this machine only supports a subset of valid comparisons, see if we
12795 can convert an unsupported one into a supported one. */
12802 }
12803 \f
12804 /* Utility function for record_value_for_reg. Count number of
12805 rtxs in X. */
12806 static int
12808 {
12815 {
12835 }
12846 }
12847 \f
12848 /* Utility function for following routine. Called when X is part of a value
12849 being stored into last_set_value. Sets last_set_table_tick
12850 for each register mentioned. Similar to mention_regs in cse.c */
12852 static void
12854 {
12860 {
12866 {
12869 }
12872 }
12876 {
12877 /* Check for identical subexpressions. If x contains
12878 identical subexpression we only have to traverse one of
12879 them. */
12881 {
12882 /* Note that at this point x1 has already been
12883 processed. */
12887 /* If x0 and x1 are identical then there is no need to
12888 process x0. */
12892 /* If x0 is identical to a subexpression of x1 then while
12893 processing x1, x0 has already been processed. Thus we
12894 are done with x. */
12899 /* If x1 is identical to a subexpression of x0 then we
12900 still have to process the rest of x0. */
12903 {
12906 }
12907 }
12910 }
12914 }
12916 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12917 are saying that the register is clobbered and we no longer know its
12918 value. If INSN is zero, don't update reg_stat[].last_set; this is
12919 only permitted with VALUE also zero and is used to invalidate the
12920 register. */
12922 static void
12924 {
12930 /* If VALUE contains REG and we have a previous value for REG, substitute
12931 the previous value. */
12933 {
12934 rtx tem;
12936 /* Set things up so get_last_value is allowed to see anything set up to
12937 our insn. */
12941 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12942 it isn't going to be useful and will take a lot of time to process,
12943 so just use the CLOBBER. */
12946 {
12952 {
12953 /* If there are two or more occurrences of REG in VALUE,
12954 prevent the value from growing too much. */
12957 }
12960 }
12961 }
12963 /* For each register modified, show we don't know its value, that
12964 we don't know about its bitwise content, that its value has been
12965 updated, and that we don't know the location of the death of the
12966 register. */
12968 {
12980 }
12982 /* Mark registers that are being referenced in this value. */
12986 /* Now update the status of each register being set.
12987 If someone is using this register in this block, set this register
12988 to invalid since we will get confused between the two lives in this
12989 basic block. This makes using this register always invalid. In cse, we
12990 scan the table to invalidate all entries using this register, but this
12991 is too much work for us. */
12994 {
13000 else
13002 }
13004 /* The value being assigned might refer to X (like in "x++;"). In that
13005 case, we must replace it with (clobber (const_int 0)) to prevent
13006 infinite loops. */
13009 {
13013 }
13015 /* For the main register being modified, update the value, the mode, the
13016 nonzero bits, and the number of sign bit copies. */
13021 {
13029 rsp->last_set_sign_bit_copies
13031 }
13032 }
13034 /* Called via note_stores from record_dead_and_set_regs to handle one
13035 SET or CLOBBER in an insn. DATA is the instruction in which the
13036 set is occurring. */
13038 static void
13040 {
13047 {
13051 }
13054 {
13055 /* If we are setting the whole register, we know its value. Otherwise
13056 show that we don't know the value. We can handle SUBREG in
13057 some cases. */
13068 else
13070 }
13072 /* Ignore pushes, they clobber nothing. */
13075 }
13077 /* Update the records of when each REG was most recently set or killed
13078 for the things done by INSN. This is the last thing done in processing
13079 INSN in the combiner loop.
13081 We update reg_stat[], in particular fields last_set, last_set_value,
13082 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13083 last_death, and also the similar information mem_last_set (which insn
13084 most recently modified memory) and last_call_luid (which insn was the
13085 most recent subroutine call). */
13087 static void
13089 {
13090 rtx link;
13094 {
13097 {
13102 {
13107 }
13108 }
13111 }
13114 {
13115 hard_reg_set_iterator hrsi;
13117 {
13129 }
13133 /* We can't combine into a call pattern. Remember, though, that
13134 the return value register is set at this LUID. We could
13135 still replace a register with the return value from the
13136 wrong subroutine call! */
13138 }
13139 else
13141 }
13143 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13144 register present in the SUBREG, so for each such SUBREG go back and
13145 adjust nonzero and sign bit information of the registers that are
13146 known to have some zero/sign bits set.
13148 This is needed because when combine blows the SUBREGs away, the
13149 information on zero/sign bits is lost and further combines can be
13150 missed because of that. */
13152 static void
13154 {
13156 rtx set;
13164 {
13173 {
13176 }
13180 {
13183 }
13186 {
13189 }
13190 else
13192 }
13193 }
13195 /* Check if X, a register, is known to contain a value already
13196 truncated to MODE. In this case we can use a subreg to refer to
13197 the truncated value even though in the generic case we would need
13198 an explicit truncation. */
13200 static bool
13202 {
13214 }
13216 /* If X is a hard reg or a subreg record the mode that the register is
13217 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13218 to turn a truncate into a subreg using this information. Return true
13219 if traversing X is complete. */
13221 static bool
13223 {
13224 machine_mode truncated_mode;
13228 {
13239 }
13240 /* ??? For hard-regs we now record everything. We might be able to
13241 optimize this using last_set_mode. */
13244 else
13252 {
13255 }
13258 }
13260 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13261 the modes they are used in. This can help truning TRUNCATEs into
13262 SUBREGs. */
13264 static void
13266 {
13271 }
13273 /* Scan X for promoted SUBREGs. For each one found,
13274 note what it implies to the registers used in it. */
13276 static void
13278 {
13283 else
13284 {
13290 {
13300 }
13301 }
13302 }
13303 \f
13304 /* Verify that all the registers and memory references mentioned in *LOC are
13305 still valid. *LOC was part of a value set in INSN when label_tick was
13306 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13307 the invalid references with (clobber (const_int 0)) and return 1. This
13308 replacement is useful because we often can get useful information about
13309 the form of a value (e.g., if it was produced by a shift that always
13310 produces -1 or 0) even though we don't know exactly what registers it
13311 was produced from. */
13313 static int
13315 {
13322 {
13328 {
13331 /* If this is a pseudo-register that was only set once and not
13332 live at the beginning of the function, it is always valid. */
13336 && (!REGNO_REG_SET_P
13338 regno)))
13340 {
13344 }
13345 }
13348 }
13349 /* If this is a memory reference, make sure that there were no stores after
13350 it that might have clobbered the value. We don't have alias info, so we
13351 assume any store invalidates it. Moreover, we only have local UIDs, so
13352 we also assume that there were stores in the intervening basic blocks. */
13355 {
13359 }
13362 {
13364 {
13365 /* Check for identical subexpressions. If x contains
13366 identical subexpression we only have to traverse one of
13367 them. */
13369 {
13370 /* Note that at this point x0 has already been checked
13371 and found valid. */
13375 /* If x0 and x1 are identical then x is also valid. */
13379 /* If x1 is identical to a subexpression of x0 then
13380 while checking x0, x1 has already been checked. Thus
13381 it is valid and so as x. */
13386 /* If x0 is identical to a subexpression of x1 then x is
13387 valid iff the rest of x1 is valid. */
13390 return
13394 }
13399 }
13405 }
13407 /* If we haven't found a reason for it to be invalid, it is valid. */
13409 }
13411 /* Get the last value assigned to X, if known. Some registers
13412 in the value may be replaced with (clobber (const_int 0)) if their value
13413 is known longer known reliably. */
13415 static rtx
13417 {
13419 rtx value;
13422 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13423 then convert it to the desired mode. If this is a paradoxical SUBREG,
13424 we cannot predict what values the "extra" bits might have. */
13438 /* If we don't have a value, or if it isn't for this basic block and
13439 it's either a hard register, set more than once, or it's a live
13440 at the beginning of the function, return 0.
13442 Because if it's not live at the beginning of the function then the reg
13443 is always set before being used (is never used without being set).
13444 And, if it's set only once, and it's always set before use, then all
13445 uses must have the same last value, even if it's not from this basic
13446 block. */
13453 || REGNO_REG_SET_P
13457 /* If the value was set in a later insn than the ones we are processing,
13458 we can't use it even if the register was only set once. */
13463 /* If fewer bits were set than what we are asked for now, we cannot use
13464 the value. */
13469 /* If the value has all its registers valid, return it. */
13473 /* Otherwise, make a copy and replace any invalid register with
13474 (clobber (const_int 0)). If that fails for some reason, return 0. */
13481 }
13482 \f
13483 /* Return nonzero if expression X refers to a REG or to memory
13484 that is set in an instruction more recent than FROM_LUID. */
13486 static int
13488 {
13494 {
13498 #ifdef PUSH_ROUNDING
13499 /* Don't allow uses of the stack pointer to be moved,
13500 because we don't know whether the move crosses a push insn. */
13503 #endif
13505 {
13511 }
13513 }
13521 {
13523 {
13528 }
13532 }
13534 }
13535 \f
13536 /* Define three variables used for communication between the following
13537 routines. */
13542 /* Function called via note_stores from reg_dead_at_p.
13544 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13545 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13547 static void
13549 {
13559 }
13561 /* Return nonzero if REG is known to be dead at INSN.
13563 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13564 referencing REG, it is dead. If we hit a SET referencing REG, it is
13565 live. Otherwise, see if it is live or dead at the start of the basic
13566 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13567 must be assumed to be always live. */
13569 static int
13571 {
13572 basic_block block;
13575 /* Set variables for reg_dead_at_p_1. */
13581 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13582 we allow the machine description to decide whether use-and-clobber
13583 patterns are OK. */
13585 {
13589 }
13591 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13592 beginning of basic block. */
13595 {
13597 {
13607 }
13613 }
13615 /* Look at live-in sets for the basic block that we were in. */
13621 }
13622 \f
13623 /* Note hard registers in X that are used. */
13625 static void
13627 {
13633 {
13637 CASE_CONST_ANY:
13642 /* CC0 must die in the insn after it is set, so we don't need to take
13643 special note of it here. */
13648 /* If we are clobbering a MEM, mark any hard registers inside the
13649 address as used. */
13656 /* A hard reg in a wide mode may really be multiple registers.
13657 If so, mark all of them just like the first. */
13659 {
13660 /* None of this applies to the stack, frame or arg pointers. */
13662 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13670 }
13674 {
13675 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13676 the address. */
13688 }
13693 }
13695 /* Recursively scan the operands of this expression. */
13697 {
13701 {
13705 {
13710 }
13711 }
13712 }
13713 }
13714 \f
13715 /* Remove register number REGNO from the dead registers list of INSN.
13717 Return the note used to record the death, if there was one. */
13719 rtx
13721 {
13728 }
13730 /* For each register (hardware or pseudo) used within expression X, if its
13731 death is in an instruction with luid between FROM_LUID (inclusive) and
13732 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13733 list headed by PNOTES.
13735 That said, don't move registers killed by maybe_kill_insn.
13737 This is done when X is being merged by combination into TO_INSN. These
13738 notes will then be distributed as needed. */
13740 static void
13743 {
13749 {
13753 /* Don't move the register if it gets killed in between from and to. */
13762 {
13765 /* It is possible for the call above to return 0. This can occur
13766 when last_death points to I2 or I1 that we combined with.
13767 In that case make a new note.
13769 We must also check for the case where X is a hard register
13770 and NOTE is a death note for a range of hard registers
13771 including X. In that case, we must put REG_DEAD notes for
13772 the remaining registers in place of NOTE. */
13777 {
13786 }
13788 /* If we didn't find any note, or if we found a REG_DEAD note that
13789 covers only part of the given reg, and we have a multi-reg hard
13790 register, then to be safe we must check for REG_DEAD notes
13791 for each register other than the first. They could have
13792 their own REG_DEAD notes lying around. */
13799 {
13806 else
13812 }
13815 {
13818 }
13819 else
13821 }
13824 }
13827 {
13832 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13833 that accesses one word of a multi-word item, some
13834 piece of everything register in the expression is used by
13835 this insn, so remove any old death. */
13836 /* ??? So why do we test for equality of the sizes? */
13845 {
13848 }
13850 /* If this is some other SUBREG, we know it replaces the entire
13851 value, so use that as the destination. */
13855 /* If this is a MEM, adjust deaths of anything used in the address.
13856 For a REG (the only other possibility), the entire value is
13857 being replaced so the old value is not used in this insn. */
13863 }
13872 {
13874 {
13879 }
13882 }
13883 }
13884 \f
13885 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13886 pattern of an insn. X must be a REG. */
13888 static int
13890 {
13894 {
13896 rtx target;
13903 else
13920 }
13928 }
13929 \f
13930 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13931 as appropriate. I3 and I2 are the insns resulting from the combination
13932 insns including FROM (I2 may be zero).
13934 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13935 not need REG_DEAD notes because they are being substituted for. This
13936 saves searching in the most common cases.
13938 Each note in the list is either ignored or placed on some insns, depending
13939 on the type of note. */
13941 static void
13944 {
13946 rtx tem_note;
13950 {
13955 {
13958 /* Doesn't matter much where we put this, as long as it's somewhere.
13959 It is preferable to keep these notes on branches, which is most
13960 likely to be i3. */
13967 else
13968 {
13971 }
13975 /* These notes must remain with the call or trapping instruction. */
13980 else
13981 {
13987 /* ??? Otherwise assume we've combined things such that we
13988 can now prove that the instructions can't trap. Drop the
13989 note in this case. */
13990 }
13994 /* ??? How to distribute between i3-i1. Assume i3 contains the
13995 entire adjustment. Assert i3 contains at least some adjust. */
13997 {
13999 /* fixup_args_size_notes looks at REG_NORETURN note,
14000 so ensure the note is placed there first. */
14002 {
14006 {
14012 }
14013 }
14015 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14016 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14019 && !ACCUMULATE_OUTGOING_ARGS
14021 }
14028 /* These notes must remain with the call. It should not be
14029 possible for both I2 and I3 to be a call. */
14032 else
14033 {
14036 }
14040 /* Any clobbers for i3 may still exist, and so we must process
14041 REG_UNUSED notes from that insn.
14043 Any clobbers from i2 or i1 can only exist if they were added by
14044 recog_for_combine. In that case, recog_for_combine created the
14045 necessary REG_UNUSED notes. Trying to keep any original
14046 REG_UNUSED notes from these insns can cause incorrect output
14047 if it is for the same register as the original i3 dest.
14048 In that case, we will notice that the register is set in i3,
14049 and then add a REG_UNUSED note for the destination of i3, which
14050 is wrong. However, it is possible to have REG_UNUSED notes from
14051 i2 or i1 for register which were both used and clobbered, so
14052 we keep notes from i2 or i1 if they will turn into REG_DEAD
14053 notes. */
14055 /* If this register is set or clobbered in I3, put the note there
14056 unless there is one already. */
14058 {
14066 }
14067 /* Otherwise, if this register is used by I3, then this register
14068 now dies here, so we must put a REG_DEAD note here unless there
14069 is one already. */
14075 {
14078 }
14084 /* These notes say something about results of an insn. We can
14085 only support them if they used to be on I3 in which case they
14086 remain on I3. Otherwise they are ignored.
14088 If the note refers to an expression that is not a constant, we
14089 must also ignore the note since we cannot tell whether the
14090 equivalence is still true. It might be possible to do
14091 slightly better than this (we only have a problem if I2DEST
14092 or I1DEST is present in the expression), but it doesn't
14093 seem worth the trouble. */
14101 /* These notes say something about how a register is used. They must
14102 be present on any use of the register in I2 or I3. */
14107 {
14110 else
14112 }
14117 /* This can show up in several ways -- either directly in the
14118 pattern, or hidden off in the constant pool with (or without?)
14119 a REG_EQUAL note. */
14120 /* ??? Ignore the without-reg_equal-note problem for now. */
14132 {
14135 else
14137 }
14139 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14140 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14141 there. */
14146 {
14153 }
14159 {
14167 }
14171 /* This note says something about the value of a register prior
14172 to the execution of an insn. It is too much trouble to see
14173 if the note is still correct in all situations. It is better
14174 to simply delete it. */
14178 /* If we replaced the right hand side of FROM_INSN with a
14179 REG_EQUAL note, the original use of the dying register
14180 will not have been combined into I3 and I2. In such cases,
14181 FROM_INSN is guaranteed to be the first of the combined
14182 instructions, so we simply need to search back before
14183 FROM_INSN for the previous use or set of this register,
14184 then alter the notes there appropriately.
14186 If the register is used as an input in I3, it dies there.
14187 Similarly for I2, if it is nonzero and adjacent to I3.
14189 If the register is not used as an input in either I3 or I2
14190 and it is not one of the registers we were supposed to eliminate,
14191 there are two possibilities. We might have a non-adjacent I2
14192 or we might have somehow eliminated an additional register
14193 from a computation. For example, we might have had A & B where
14194 we discover that B will always be zero. In this case we will
14195 eliminate the reference to A.
14197 In both cases, we must search to see if we can find a previous
14198 use of A and put the death note there. */
14204 else
14205 {
14216 && !(i2mod
14218 i2mod_old_rhs)))
14223 /* If the new I2 sets the same register that is marked dead
14224 in the note, we do not know where to put the note.
14225 Give up. */
14228 }
14231 {
14235 {
14237 {
14241 }
14243 /* If the register is being set at TEM_INSN, see if that is all
14244 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14245 into a REG_UNUSED note instead. Don't delete sets to
14246 global register vars. */
14250 {
14261 ;
14263 /* Verify that it was the set, and not a clobber that
14264 modified the register.
14266 CC0 targets must be careful to maintain setter/user
14267 pairs. If we cannot delete the setter due to side
14268 effects, mark the user with an UNUSED note instead
14269 of deleting it. */
14273 && (!HAVE_cc0
14277 {
14278 /* Move the notes and links of TEM_INSN elsewhere.
14279 This might delete other dead insns recursively.
14280 First set the pattern to something that won't use
14281 any register. */
14300 /* Delete the setter too. */
14302 {
14315 }
14316 }
14317 else
14318 {
14321 /* If there isn't already a REG_UNUSED note, put one
14322 here. Do not place a REG_DEAD note, even if
14323 the register is also used here; that would not
14324 match the algorithm used in lifetime analysis
14325 and can cause the consistency check in the
14326 scheduler to fail. */
14331 }
14332 }
14336 {
14339 /* If we are doing a 3->2 combination, and we have a
14340 register which formerly died in i3 and was not used
14341 by i2, which now no longer dies in i3 and is used in
14342 i2 but does not die in i2, and place is between i2
14343 and i3, then we may need to move a link from place to
14344 i2. */
14346 && from_insn
14349 {
14353 }
14355 }
14359 }
14361 }
14363 /* If the register is set or already dead at PLACE, we needn't do
14364 anything with this note if it is still a REG_DEAD note.
14365 We check here if it is set at all, not if is it totally replaced,
14366 which is what `dead_or_set_p' checks, so also check for it being
14367 set partially. */
14370 {
14376 {
14377 /* Unless the register previously died in PLACE, clear
14378 last_death. [I no longer understand why this is
14379 being done.] */
14383 }
14384 else
14387 /* If this is a death note for a hard reg that is occupying
14388 multiple registers, ensure that we are still using all
14389 parts of the object. If we find a piece of the object
14390 that is unused, we must arrange for an appropriate REG_DEAD
14391 note to be added for it. However, we can't just emit a USE
14392 and tag the note to it, since the register might actually
14393 be dead; so we recourse, and the recursive call then finds
14394 the previous insn that used this register. */
14397 {
14406 {
14409 }
14412 {
14413 /* Put only REG_DEAD notes for pieces that are
14414 not already dead or set. */
14418 {
14425 {
14427 NULL_RTX);
14431 NULL_RTX);
14432 }
14437 {
14439 {
14443 }
14447 {
14450 }
14451 }
14452 }
14455 }
14456 }
14457 }
14461 /* Any other notes should not be present at this point in the
14462 compilation. */
14464 }
14467 {
14470 }
14474 }
14475 }
14476 \f
14477 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14478 I3, I2, and I1 to new locations. This is also called to add a link
14479 pointing at I3 when I3's destination is changed. */
14481 static void
14483 {
14487 {
14494 /* If the insn that this link points to is a NOTE, ignore it. */
14503 {
14506 {
14522 }
14525 }
14526 else
14536 /* A LOG_LINK is defined as being placed on the first insn that uses
14537 a register and points to the insn that sets the register. Start
14538 searching at the next insn after the target of the link and stop
14539 when we reach a set of the register or the end of the basic block.
14541 Note that this correctly handles the link that used to point from
14542 I3 to I2. Also note that not much searching is typically done here
14543 since most links don't point very far away. */
14552 {
14556 }
14559 {
14562 }
14566 /* If we found a place to put the link, place it there unless there
14567 is already a link to the same insn as LINK at that point. */
14570 {
14578 {
14582 /* Set added_links_insn to the earliest insn we added a
14583 link to. */
14587 }
14588 }
14589 }
14590 }
14591 \f
14592 /* Check for any register or memory mentioned in EQUIV that is not
14593 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14594 of EXPR where some registers may have been replaced by constants. */
14596 static bool
14598 {
14601 {
14606 }
14608 }
14609 \f
14610 DEBUG_FUNCTION void
14612 {
14613 fprintf
14615 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14617 }
14619 void
14621 {
14622 fprintf
14624 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14626 }
14627 \f
14628 /* Try combining insns through substitution. */
14629 static unsigned int
14631 {
14641 rebuild_jump_labels_after_combine
14644 /* Combining insns may have turned an indirect jump into a
14645 direct jump. Rebuild the JUMP_LABEL fields of jumping
14646 instructions. */
14648 {
14655 }
14659 }
14664 {
14674 };
14677 {
14681 {}
14683 /* opt_pass methods: */
14686 {
14688 }
14694 rtl_opt_pass *
14696 {
14698 }