Add support for in-order addition reduction using SVE FADDA
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / reduc_strict_2_run.c
blobe59f640dfd361b3697501a9e6bfec6af437a9531
1 /* { dg-do run { target { aarch64_sve_hw } } } */
2 /* { dg-options "-O2 -ftree-vectorize -fno-inline" } */
4 #include "reduc_strict_2.c"
6 #define NROWS 5
8 #define TEST_REDUC_PLUS(TYPE) \
9 { \
10 TYPE a[NROWS][NUM_ELEMS (TYPE)]; \
11 TYPE r[NROWS]; \
12 TYPE expected[NROWS] = {}; \
13 for (int i = 0; i < NROWS; ++i) \
14 for (int j = 0; j < NUM_ELEMS (TYPE); ++j) \
15 { \
16 a[i][j] = (i * 0.1 + j * 0.6) * (j & 1 ? 1 : -1); \
17 expected[i] += a[i][j]; \
18 asm volatile ("" ::: "memory"); \
19 } \
20 reduc_plus_##TYPE (a, r, NROWS); \
21 for (int i = 0; i < NROWS; ++i) \
22 if (r[i] != expected[i]) \
23 __builtin_abort (); \
26 int __attribute__ ((optimize (1)))
27 main ()
29 TEST_ALL (TEST_REDUC_PLUS);
30 return 0;