Add support for in-order addition reduction using SVE FADDA
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / reduc_strict_1_run.c
blob40e0cf0a6dd5c4358fc09ff6972a214c2adee9fc
1 /* { dg-do run { target { aarch64_sve_hw } } } */
2 /* { dg-options "-O2 -ftree-vectorize" } */
4 #include "reduc_strict_1.c"
6 #define TEST_REDUC_PLUS(TYPE) \
7 { \
8 TYPE a[NUM_ELEMS (TYPE)]; \
9 TYPE b[NUM_ELEMS (TYPE)]; \
10 TYPE r = 0, q = 3; \
11 for (int i = 0; i < NUM_ELEMS (TYPE); i++) \
12 { \
13 a[i] = (i * 0.1) * (i & 1 ? 1 : -1); \
14 b[i] = (i * 0.3) * (i & 1 ? 1 : -1); \
15 r += a[i]; \
16 q -= b[i]; \
17 asm volatile ("" ::: "memory"); \
18 } \
19 TYPE res = reduc_plus_##TYPE (a, b); \
20 if (res != r * q) \
21 __builtin_abort (); \
24 int __attribute__ ((optimize (1)))
25 main ()
27 TEST_ALL (TEST_REDUC_PLUS);
28 return 0;