Add support for in-order addition reduction using SVE FADDA
[official-gcc.git] / gcc / testsuite / gcc.dg / vect / vect-reduc-in-order-4.c
blob46d0f3a04648d3493521e81da83e8e63051d82de
1 /* { dg-do run { xfail { { i?86-*-* x86_64-*-* } && ia32 } } } */
2 /* { dg-require-effective-target vect_double } */
3 /* { dg-add-options ieee } */
4 /* { dg-additional-options "-fno-fast-math" } */
6 #include "tree-vect.h"
8 #define N (VECTOR_BITS * 17)
10 double __attribute__ ((noinline, noclone))
11 reduc_plus_double (double *a)
13 double r1 = 0;
14 double r2 = 0;
15 double r3 = 0;
16 double r4 = 0;
17 for (int i = 0; i < N; i += 4)
19 r1 += a[i];
20 r2 += a[i + 1];
21 r3 += a[i + 2];
22 r4 += a[i + 3];
24 return r1 * r2 * r3 * r4;
27 int __attribute__ ((optimize (1)))
28 main ()
30 double a[N];
31 double r[4] = {};
32 for (int i = 0; i < N; i++)
34 a[i] = (i * 0.1) * (i & 1 ? 1 : -1);
35 r[i % 4] += a[i];
36 asm volatile ("" ::: "memory");
38 double res = reduc_plus_double (a);
39 if (res != r[0] * r[1] * r[2] * r[3])
40 __builtin_abort ();
41 return 0;
44 /* { dg-final { scan-tree-dump {in-order unchained SLP reductions not supported} "vect" } } */
45 /* { dg-final { scan-tree-dump-not {vectorizing stmts using SLP} "vect" } } */