| blob | ec3bfe1c8ad2a55eafc540496bd22bc164599afb |
1 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
4 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
5 Don't 'define_constants'.
7 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
9 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
11 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
13 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
14 [TARGET_RDNA3]: Adjust.
16 2024-02-01 Richard Biener <rguenther@suse.de>
18 PR tree-optimization/113693
19 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
20 data when available.
22 2024-02-01 Jakub Jelinek <jakub@redhat.com>
23 Jason Merrill <jason@redhat.com>
25 PR c++/113531
26 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
27 on variables which were promoted to TREE_STATIC.
29 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
30 Richard Biener <rguenther@suse.de>
32 PR target/113560
33 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
34 information via tree_non_zero_bits to check if this operand
35 is suitably extended for a widening (or highpart) multiplication.
36 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
37 isn't already of the claimed type.
39 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
41 Revert:
42 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
44 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
45 (generic_ooo_branch): ditto
46 * config/riscv/generic.md (generic_sfb_alu): ditto
47 (generic_fmul_half): ditto
48 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
49 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
50 (sifive_7_popcount): ditto
51 * config/riscv/vector.md: change rdfrm to fmove
52 * config/riscv/zc.md: change pushpop to load/store
54 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
56 Revert:
57 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
58 Robin Dapp <rdapp.gcc@gmail.com>
60 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
61 (generic_ooo_vec_load): ditto
62 (generic_ooo_vec_store): ditto
63 (generic_ooo_vec_loadstore_seg): ditto
64 (generic_ooo_vec_alu): ditto
65 (generic_ooo_vec_fcmp): ditto
66 (generic_ooo_vec_imul): ditto
67 (generic_ooo_vec_fadd): ditto
68 (generic_ooo_vec_fmul): ditto
69 (generic_ooo_crypto): ditto
70 (generic_ooo_perm): ditto
71 (generic_ooo_vec_reduction): ditto
72 (generic_ooo_vec_ordered_reduction): ditto
73 (generic_ooo_vec_idiv): ditto
74 (generic_ooo_vec_float_divsqrt): ditto
75 (generic_ooo_vec_mask): ditto
76 (generic_ooo_vec_vesetvl): ditto
77 (generic_ooo_vec_setrm): ditto
78 (generic_ooo_vec_readlen): ditto
79 * config/riscv/riscv.md: include generic-vector-ooo
80 * config/riscv/generic-vector-ooo.md: New file. to here
82 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
84 Revert:
85 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
87 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
89 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
91 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
93 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
94 Robin Dapp <rdapp.gcc@gmail.com>
96 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
97 (generic_ooo_vec_load): ditto
98 (generic_ooo_vec_store): ditto
99 (generic_ooo_vec_loadstore_seg): ditto
100 (generic_ooo_vec_alu): ditto
101 (generic_ooo_vec_fcmp): ditto
102 (generic_ooo_vec_imul): ditto
103 (generic_ooo_vec_fadd): ditto
104 (generic_ooo_vec_fmul): ditto
105 (generic_ooo_crypto): ditto
106 (generic_ooo_perm): ditto
107 (generic_ooo_vec_reduction): ditto
108 (generic_ooo_vec_ordered_reduction): ditto
109 (generic_ooo_vec_idiv): ditto
110 (generic_ooo_vec_float_divsqrt): ditto
111 (generic_ooo_vec_mask): ditto
112 (generic_ooo_vec_vesetvl): ditto
113 (generic_ooo_vec_setrm): ditto
114 (generic_ooo_vec_readlen): ditto
115 * config/riscv/riscv.md: include generic-vector-ooo
116 * config/riscv/generic-vector-ooo.md: New file. to here
118 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
120 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
121 (generic_ooo_branch): ditto
122 * config/riscv/generic.md (generic_sfb_alu): ditto
123 (generic_fmul_half): ditto
124 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
125 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
126 (sifive_7_popcount): ditto
127 * config/riscv/vector.md: change rdfrm to fmove
128 * config/riscv/zc.md: change pushpop to load/store
130 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
132 PR target/113657
133 * config/aarch64/aarch64-simd.md (split for movv8di):
134 For strict aligned mode, use DImode instead of TImode.
136 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
138 PR middle-end/113607
139 * match.pd: Make sure else values match when folding a
140 vec_cond into a conditional operation.
142 2024-01-31 Marek Polacek <polacek@redhat.com>
144 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
146 2024-01-31 Tamar Christina <tamar.christina@arm.com>
147 Matthew Malcomson <matthew.malcomson@arm.com>
149 PR sanitizer/112644
150 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
151 memcmp.
152 * builtins.cc (expand_builtin): Include HWASAN when checking for
153 builtin inlining.
155 2024-01-31 Richard Biener <rguenther@suse.de>
157 PR middle-end/110176
158 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
159 to match INTEGER_CST only without outstanding conversion.
161 2024-01-31 Alex Coplan <alex.coplan@arm.com>
163 PR target/111677
164 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
165 V16QImode for the full 16-byte FPR saves in the vector PCS case.
167 2024-01-31 Richard Biener <rguenther@suse.de>
169 PR tree-optimization/111444
170 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
171 vn_reference_lookup_2 when optimistically skipping may-defs.
173 2024-01-31 Richard Biener <rguenther@suse.de>
175 PR tree-optimization/113630
176 * tree-ssa-pre.cc (compute_avail): Avoid registering a
177 reference with a representation with not matching base
178 access size.
180 2024-01-31 Jakub Jelinek <jakub@redhat.com>
182 PR rtl-optimization/113656
183 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
184 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
186 2024-01-31 Jakub Jelinek <jakub@redhat.com>
188 PR debug/113637
189 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
190 with BLKmode are larger than DWARF2_ADDR_SIZE.
192 2024-01-31 Jakub Jelinek <jakub@redhat.com>
194 PR tree-optimization/113639
195 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
196 For VIEW_CONVERT_EXPR set rhs1 to its operand.
198 2024-01-31 Richard Biener <rguenther@suse.de>
200 PR tree-optimization/113670
201 * tree-vect-data-refs.cc (vect_check_gather_scatter):
202 Make sure we can take the address of the reference base.
204 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
206 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
207 ATA5835, ATtiny64AUTO, ATA5700M322.
208 * doc/avr-mmcu.texi: Rebuild.
210 2024-01-31 Alexandre Oliva <oliva@adacore.com>
212 PR debug/113394
213 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
214 caller.
216 2024-01-31 Alexandre Oliva <oliva@adacore.com>
218 PR middle-end/112917
219 PR middle-end/113100
220 * builtins.cc (expand_builtin_stack_address): Use
221 STACK_ADDRESS_OFFSET.
222 * doc/extend.texi (__builtin_stack_address): Adjust.
223 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
224 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
225 * doc/tm.texi: Rebuilt.
227 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
229 PR target/113495
230 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
231 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
232 (pre_vsetvl::compute_transparent): New function.
233 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
235 2024-01-30 Fangrui Song <maskray@google.com>
237 PR target/105576
238 * config/i386/constraints.md: Define constraint "Ws".
239 * doc/md.texi: Document it.
241 2024-01-30 Marek Polacek <polacek@redhat.com>
243 PR c++/110358
244 PR c++/109640
245 * doc/invoke.texi: Update -Wdangling-reference description.
247 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
249 * config/xtensa/constraints.md (R, T, U):
250 Change define_constraint to define_memory_constraint.
251 * config/xtensa/predicates.md (move_operand): Don't check that a
252 constant pool operand size is a multiple of UNITS_PER_WORD.
253 * config/xtensa/xtensa.cc
254 (xtensa_lra_p, TARGET_LRA_P): Remove.
255 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
256 clause as it can no longer be true.
257 (fixup_subreg_mem): Drop function.
258 (xtensa_output_integer_literal_parts): Consider 16-bit wide
259 constants.
260 (xtensa_legitimate_constant_p): Add short-circuit path for
261 integer load instructions. Don't check that mode size is
262 at least UNITS_PER_WORD.
263 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
264 rather reload_in_progress and reload_completed.
265 (doloop_end): Drop operand 2.
266 (movhi_internal): Add alternative loading constant from a
267 literal pool.
268 (define_split for DI register_operand): Don't limit to
269 !TARGET_AUTO_LITPOOLS.
270 * config/xtensa/xtensa.opt (mlra): Change to no effect.
272 2024-01-30 Pan Li <pan2.li@intel.com>
274 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
275 calculate the gpr count required by vls mode.
276 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
277 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
278 for vls mode.
279 (riscv_get_arg_info): Add vls mode handling.
280 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
282 2024-01-30 Richard Biener <rguenther@suse.de>
284 PR tree-optimization/113659
285 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
286 Handle main exit without virtual use.
288 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
290 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
292 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
294 PR libgcc/113403
295 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
296 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
297 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
298 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
299 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
300 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
302 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
304 PR target/113623
305 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
306 Mark all registers that occur in addresses as needing a GPR.
308 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
310 PR target/113636
311 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
312 the containing insn as an extra parameter. Reset debug instructions
313 if they reference a register that is no longer used by real insns.
314 (early_ra::apply_allocation): Update calls accordingly.
316 2024-01-30 Jakub Jelinek <jakub@redhat.com>
318 PR tree-optimization/113603
319 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
320 count_nonzero_bytes call refetch si using get_strinfo in case it
321 has been unshared in the meantime.
323 2024-01-30 Jakub Jelinek <jakub@redhat.com>
325 PR middle-end/101195
326 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
327 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
329 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
331 * config/riscv/thead.cc (th_print_operand_address): Change %ld
332 to %lld.
334 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
335 Manolis Tsamis <manolis.tsamis@vrull.eu>
336 Philipp Tomsich <philipp.tomsich@vrull.eu>
338 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
339 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
340 Likewise.
341 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
342 Call on framework moved later.
344 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
346 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
347 instruction in naked function epilogues.
349 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
351 PR target/113655
352 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
353 gcc_cv_as_mips_explicit_relocs.
354 * configure: Regnerated.
356 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
358 PR target/108933
359 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
360 Correct generated RTL.
361 (arm_rev16si2_alt1): Correctly handle conditional execution.
362 (arm_rev16si2_alt2): Likewise.
364 2024-01-29 Richard Biener <rguenther@suse.de>
366 PR middle-end/113622
367 * expr.cc (expand_assignment): Spill hard registers if
368 we index them with a variable offset.
370 2024-01-29 Richard Biener <rguenther@suse.de>
372 PR middle-end/113622
373 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
374 Also allow DECL_HARD_REGISTER variables.
376 2024-01-29 Alex Coplan <alex.coplan@arm.com>
378 PR target/113616
379 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
380 Use iterate_safely when iterating over debug uses.
381 (fixup_debug_uses): Likewise.
382 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
383 over nondebug insns instead of manually maintaining the next insn.
384 * iterator-utils.h (class safe_iterator): New.
385 (iterate_safely): New.
387 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
389 PR target/38534
390 * config/i386/i386-options.cc (ix86_set_func_type): Save
391 callee-saved registers in noreturn functions for -O0/-Og.
393 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
395 PR target/113615
396 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
397 define for !TARGET_RDNA2_PLUS.
399 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
401 PR target/113281
402 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
403 workaround for right shifts.
404 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
405 (vect_determine_precisions_from_range): Be more selective about
406 which codes can be narrowed based on their input and output ranges.
407 For shifts, require at least one more bit of precision than the
408 maximum shift amount.
410 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
412 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
414 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
416 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
417 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
418 LLVM 13.0.1+.
420 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
422 PR other/111966
423 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
424 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
425 (SET_SRAM_ECC_UNSET): ... this.
426 (copy_early_debug_info): Remove gfx900 special case, now handled as
427 part of the generic handling.
428 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
430 2024-01-29 Jakub Jelinek <jakub@redhat.com>
432 PR tree-optimization/110603
433 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
434 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
435 overwritten anyway). Avoid creating invalid range with minlen
436 larger than maxlen. Formatting fix.
438 2024-01-29 Richard Biener <rguenther@suse.de>
440 PR debug/103047
441 * tree-inline.cc (initialize_inlined_parameters): Reverse
442 the decl chain of inlined parameters.
444 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
446 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
447 alignment of CFString constants by setting DECL_USER_ALIGN.
449 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
450 Jakub Jelinek <jakub@redhat.com>
452 PR libgcc/113402
453 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
454 and BUILT_IN_GCC_NESTED_PTR_DELETED.
455 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
456 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
457 rename the library fallbacks to __gcc_nested_func_ptr_created and
458 __gcc_nested_func_ptr_deleted.
459 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
460 and __gcc_nested_func_ptr_deleted.
461 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
462 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
463 * tree.cc (build_common_builtin_nodes): Build the
464 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
465 builtins only for non-explicit.
467 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
469 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
471 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
473 PR target/38534
474 * config/i386/i386-options.cc (ix86_set_func_type): Don't
475 save and restore callee saved registers for a noreturn function
476 with nothrow or compiled with -fno-exceptions.
478 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
480 PR target/103503
481 PR target/113312
482 * config/i386/i386-expand.cc (ix86_expand_call): Replace
483 no_caller_saved_registers check with call_saved_registers check.
484 Clobber all registers that are not used by the callee with
485 no_callee_saved_registers attribute.
486 * config/i386/i386-options.cc (ix86_set_func_type): Set
487 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
488 noreturn function. Disallow no_callee_saved_registers with
489 interrupt or no_caller_saved_registers attributes together.
490 (ix86_set_current_function): Replace no_caller_saved_registers
491 check with call_saved_registers check.
492 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
493 (ix86_handle_call_saved_registers_attribute): This.
494 (ix86_gnu_attributes): Add
495 ix86_handle_call_saved_registers_attribute.
496 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
497 no_caller_saved_registers check with call_saved_registers check.
498 (ix86_function_ok_for_sibcall): Don't allow callee with
499 no_callee_saved_registers attribute when the calling function
500 has callee-saved registers.
501 (ix86_comp_type_attributes): Also check
502 no_callee_saved_registers.
503 (ix86_epilogue_uses): Replace no_caller_saved_registers check
504 with call_saved_registers check.
505 (ix86_hard_regno_scratch_ok): Likewise.
506 (ix86_save_reg): Replace no_caller_saved_registers check with
507 call_saved_registers check. Don't save any registers for
508 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
509 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
510 no_callee_saved_registers attribute is called.
511 (find_drap_reg): Replace no_caller_saved_registers check with
512 call_saved_registers check.
513 * config/i386/i386.h (call_saved_registers_type): New enum.
514 (machine_function): Replace no_caller_saved_registers with
515 call_saved_registers.
516 * doc/extend.texi: Document no_callee_saved_registers attribute.
518 2024-01-27 Jakub Jelinek <jakub@redhat.com>
520 PR tree-optimization/113614
521 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
522 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
523 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
525 2024-01-27 Jakub Jelinek <jakub@redhat.com>
527 PR tree-optimization/113568
528 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
529 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
530 in the widening extension checks.
532 2024-01-27 Jakub Jelinek <jakub@redhat.com>
534 * gimple-lower-bitint.cc (gimple_lower_bitint): For
535 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
537 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
539 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
540 the warning for an attribute-always_inline without inline declaration.
542 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
544 PR other/113575
545 * genopinit.cc (main): Split init_all_optabs into functions
546 of 1000 patterns each.
548 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
550 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
551 TM_MULTILIB_CONFIG.
552 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
553 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
554 -march/-mtune.
556 2024-01-26 Andrew Stubbs <ams@baylibre.com>
558 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
559 * config/gcn/gcn-valu.md (all_convert): New iterator.
560 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
561 define_expand, and rename the old one to ...
562 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
563 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
564 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
565 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
566 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
567 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
568 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
569 (<u>mulqihi3_scalar): Likewise.
571 2024-01-26 Richard Biener <rguenther@suse.de>
573 PR tree-optimization/113602
574 * tree-data-ref.cc (dr_analyze_innermost): Fail when
575 the base object isn't addressable.
577 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
579 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
580 "--amdhsa-code-object-version=" argument.
581 (ASM_SPEC): Use it; replace previous version of it.
583 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
585 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
586 (pre_vsetvl::emit_vsetvl): Ditto.
588 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
590 * config/loongarch/lasx.md (vec_extract<mode>_0):
591 New define_insn_and_split patten.
593 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
595 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
597 2024-01-26 Li Wei <liwei@loongson.cn>
599 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
601 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
603 PR target/113469
604 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
606 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
608 PR target/100212
609 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
610 undefined shift after the call to exact_log2.
612 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
614 PR target/100204
615 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
616 before taking the negative of it.
618 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
620 PR target/113526
621 * lra-constraints.cc (curr_insn_transform): Change class even for
622 spilled pseudo successfully matched with with NO_REGS.
624 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
626 PR target/113601
627 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
629 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
631 PR target/112987
632 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
633 (aarch64_expand_epilogue): Use the new function.
634 (aarch64_split_compare_and_swap): Likewise.
635 (aarch64_split_atomic_op): Likewise.
637 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
639 PR middle-end/112971
640 * fold-const.cc (simplify_const_binop): New function for binop
641 simplification of two constant vectors when element-wise
642 handling is not necessary.
643 (const_binop): Call new function.
645 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
647 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
648 * config/riscv/constraints.md: Likewise.
649 * config/riscv/corev.def: Likewise.
650 * config/riscv/corev.md: Likewise.
651 * config/riscv/predicates.md: Likewise.
652 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
653 * config/riscv/riscv-ftypes.def: Likewise.
654 * config/riscv/riscv.opt: Likewise.
655 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
656 * doc/extend.texi: Add XCVbitmanip builtin documentation.
657 * doc/sourcebuild.texi: Likewise.
659 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
661 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
663 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
665 PR target/113538
666 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
667 (riscv_fntype_abi): Ditto.
668 * config/riscv/riscv.opt: Ditto.
670 2024-01-25 Jakub Jelinek <jakub@redhat.com>
672 PR middle-end/113574
673 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
674 count against TYPE_PRECISION rather than TYPE_SIZE.
676 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
678 PR target/113572
679 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
680 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
682 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
684 PR target/113550
685 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
686 whether each split instruction is a load that clobbers the source
687 address. Emit that instruction last if so.
689 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
691 PR target/113485
692 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
693 pattern.
694 (<optab><Vnarrowq><mode>2): Use it instead of generating a
695 paradoxical subreg for the input.
697 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
699 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
700 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
701 predecessors dump information.
703 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
705 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
706 redundant full available computation.
707 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
709 2024-01-25 Jakub Jelinek <jakub@redhat.com>
711 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
712 * doc/rtl.texi (CONST_VECTOR): Likewise.
714 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
716 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
717 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
718 (pass_vsetvl::execute): Ditto.
719 * config/riscv/riscv.opt: Ditto.
721 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
723 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
724 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
726 2024-01-25 Richard Biener <rguenther@suse.de>
728 PR tree-optimization/113576
729 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
730 exits with may_be_zero niters when its the last one.
732 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
734 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
735 For symbols of type tls, non-zero Offset is not generated.
737 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
739 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
740 P9 with m32 and mpowerpc64.
742 2024-01-25 liuhongt <hongtao.liu@intel.com>
744 * config/i386/i386-options.cc (ix86_option_override_internal):
745 Enable -mlam=u57 by default when compiled with
746 -fsanitize=hwaddress.
748 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
750 * common/config/riscv/riscv-common.cc (riscv_implied_info):
751 Remove {"ztso", "a"}.
753 2024-01-24 Martin Jambor <mjambor@suse.cz>
755 PR ipa/108007
756 PR ipa/112616
757 * cgraph.h (cgraph_edge): Add a parameter to
758 redirect_call_stmt_to_callee.
759 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
760 parameter to modify_call.
761 (ipa_release_ssas_in_hash): Declare.
762 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
763 parameter killed_ssas, pass it to padjs->modify_call.
764 * ipa-param-manipulation.cc (purge_all_uses): New function.
765 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
766 Instead of substituting uses, invoke purge_all_uses. If
767 hash of killed SSAs has not been provided, create a temporary one
768 and release SSAs that have been added to it.
769 (compare_ssa_versions): New function.
770 (ipa_release_ssas_in_hash): Likewise.
771 * tree-inline.cc (redirect_all_calls): Create
772 id->killed_new_ssa_names earlier, pass it to edge redirection,
773 adjust a comment.
774 (copy_body): Release SSAs in id->killed_new_ssa_names.
776 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
778 PR target/113486
779 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
780 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
782 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
784 PR target/113095
785 * config/riscv/sfb.md: New splitters to rewrite single bit
786 sign extension as the condition to SFB instructions.
788 2024-01-24 Jan Hubicka <jh@suse.cz>
790 PR middle-end/88345
791 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
792 (fmin-function-alignment): New parameter.
793 * doc/invoke.texi: (-fmin-function-alignment): Document.
794 (-falign-functions,-falign-loops,-falign-labels): Mention that
795 aglinments are ignored in cold code.
796 * varasm.cc (assemble_start_function): Handle min-function-alignment.
798 2024-01-24 Tamar Christina <tamar.christina@arm.com>
800 PR target/109636
801 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
802 mulv2di3): Remove.
803 * config/aarch64/iterators.md (VQDIV): Remove.
804 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
805 SVE_I_SIMD_DI): New.
806 (VPRED, sve_lane_con): Add V4SI and V2DI.
807 * config/aarch64/aarch64-sve.md (<optab><mode>3,
808 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
809 (mul<mode>3): New, split from <optab><mode>3.
810 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
811 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
812 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
813 SVE_FULL_HSDI_SIMD_DI.
815 2024-01-24 Tamar Christina <tamar.christina@arm.com>
817 PR tree-optimization/113552
818 * config/aarch64/aarch64.cc
819 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
821 2024-01-24 Martin Jambor <mjambor@suse.cz>
823 PR ipa/113490
824 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
825 count is equal or greater than the limit. Use the limit from the
826 callee.
828 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
830 * configure.ac: Detect the explicit relocs support for
831 mips, and define C macro MIPS_EXPLICIT_RELOCS.
832 * config.in: Regenerated.
833 * configure: Regenerated.
834 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
835 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
836 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
837 !TARGET_EXPLICIT_RELOCS instead of just set it.
838 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
839 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
840 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
841 and define -m(no-)explicit-relocs as aliases.
843 2024-01-24 Alex Coplan <alex.coplan@arm.com>
845 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
846 to 1.
847 (-mlate-ldp-fusion): Likewise.
849 2024-01-24 Tamar Christina <tamar.christina@arm.com>
851 * tree-vect-loop.cc (vect_get_vect_def,
852 vect_create_epilog_for_reduction): Rename main_exit_p to
853 last_val_reduc_p.
855 2024-01-24 Tamar Christina <tamar.christina@arm.com>
857 PR tree-optimization/113364
858 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
859 early exits then we must reduce from the first offset for all of them.
861 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
863 PR target/113495
864 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
865 (get_regno): Ditto.
866 (get_bb_index): Ditto.
867 (pre_vsetvl::compute_avl_def_data): Ditto.
868 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
869 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
871 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
872 Richard Sandiford <richard.sandiford@arm.com>
874 PR target/100942
875 * ccmp.cc (ccmp_candidate_p): Add outer argument.
876 Allow if the outer is true and the lhs is used more
877 than once.
878 (expand_ccmp_expr): Update call to ccmp_candidate_p.
879 * expr.h (expand_expr_real_gassign): Declare.
880 * expr.cc (expand_expr_real_gassign): New function, split out from...
881 (expand_expr_real_1): ...here.
882 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
884 2024-01-23 Alex Coplan <alex.coplan@arm.com>
886 PR target/113089
887 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
888 (fixup_debug_use): New.
889 (fixup_debug_uses_trailing_add): New.
890 (fixup_debug_uses): New. Use it ...
891 (ldp_bb_info::fuse_pair): ... here.
892 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
893 fix up debug uses of the base register that are affected by
894 folding in the trailing add insn.
896 2024-01-23 Alex Coplan <alex.coplan@arm.com>
898 PR target/113089
899 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
900 Update trailing nondebug uses of the base register in the case
901 of cancelling writeback.
903 2024-01-23 Alex Coplan <alex.coplan@arm.com>
905 PR target/113089
906 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
907 (debug_insn_use_iterator): New.
908 (set_info::first_debug_insn_use): New.
909 (set_info::debug_insn_uses): New.
910 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
911 (set_info::first_debug_insn_use): New.
912 (set_info::debug_insn_uses): New.
914 2024-01-23 Alex Coplan <alex.coplan@arm.com>
916 PR target/113356
917 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
918 Don't record hazards against the opposite insn in the pair.
920 2024-01-23 Alex Coplan <alex.coplan@arm.com>
922 PR target/113070
923 * config/aarch64/aarch64-ldp-fusion.cc
924 (struct stp_change_builder): New.
925 (decide_stp_strategy): Reanme to ...
926 (try_repurpose_store): ... this.
927 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
928 construct stp changes. Fix up uses when inserting new stp insns.
930 2024-01-23 Alex Coplan <alex.coplan@arm.com>
932 PR target/113070
933 * rtl-ssa.h: Include hash-set.h.
934 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
935 new_sets parameter and use it to keep track of new user-created sets.
936 (function_info::apply_changes_to_insn): Also call add_def on new sets.
937 (function_info::change_insns): Add hash_set to keep track of new
938 user-created defs. Plumb it through.
939 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
940 apply_changes_to_insn.
942 2024-01-23 Alex Coplan <alex.coplan@arm.com>
944 PR target/113070
945 * rtl-ssa/accesses.cc (function_info::create_use): New.
946 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
947 Ensure new uses end up referring to permanent defs.
948 * rtl-ssa/functions.h (function_info::create_use): Declare.
950 2024-01-23 Alex Coplan <alex.coplan@arm.com>
952 PR target/113070
953 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
954 to finalize_new_accesses from the backwards placement loop, run it
955 forwards in a separate loop.
957 2024-01-23 Richard Biener <rguenther@suse.de>
959 PR tree-optimization/113552
960 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
961 floor_log2 instead of exact_log2 on the number of calls.
963 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
964 Jakub Jelinek <jakub@redhat.com>
966 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
967 decl.
969 2024-01-23 Richard Biener <rguenther@suse.de>
971 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
972 Separate single and multi-exit case when creating PHIs between
973 the main and epilogue.
975 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
977 PR target/112989
978 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
979 MODE_single variants of functions that don't take tuple arguments.
981 2024-01-23 Alex Coplan <alex.coplan@arm.com>
983 PR target/113114
984 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
985 Don't assert recog success, just punt if the writeback pair
986 isn't recognized.
988 2024-01-23 Jakub Jelinek <jakub@redhat.com>
990 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
991 ATTRIBUTE_UNUSED to decl.
993 2024-01-23 Richard Biener <rguenther@suse.de>
995 PR debug/107058
996 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
997 handle unexpected but bogus DIE contexts when not checking
998 enabled.
1000 2024-01-23 Jakub Jelinek <jakub@redhat.com>
1002 PR tree-optimization/113462
1003 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
1004 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
1005 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
1006 sizes between 129 and 8192 bytes.
1008 2024-01-23 Xi Ruoyao <xry111@xry111.site>
1010 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
1011 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
1012 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
1013 (loongarch_call_tls_get_addr): Do not split symbols of
1014 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
1015 EXPLICIT_RELOCS_AUTO.
1017 2024-01-23 Richard Biener <rguenther@suse.de>
1019 * alias.cc (known_base_value_p): Remove.
1020 (find_base_value): Remove PLUS/MINUS handling
1021 when both operands are not CONST_INT_P.
1023 2024-01-23 Richard Biener <rguenther@suse.de>
1025 PR rtl-optimization/113255
1026 * alias.cc (find_base_term): Remove PLUS/MINUS handling
1027 when both operands are not CONST_INT_P.
1029 2024-01-23 Richard Biener <rguenther@suse.de>
1031 PR debug/112718
1032 * dwarf2out.cc (dwarf2out_finish): Reset all type units
1033 for the fat part of an LTO compile.
1035 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
1037 * doc/sourcebuild.texi: Add attributes for keywords.
1039 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
1041 PR c++/90463
1042 * doc/invoke.texi (Warning Options): Correct lists of options
1043 enabled by -Wall and -Wextra by checking against common.opt
1044 and c-family/c.opt.
1046 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
1048 PR target/113030
1049 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
1050 instead of cpu_optaliases.
1051 (check_arch): Use arch_opt_alias instead of arch_optaliases.
1053 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1055 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
1056 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
1057 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
1059 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1061 PR target/109092
1062 * config/riscv/riscv.md: Use reg instead of subreg.
1064 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
1066 PR other/111966
1067 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
1068 to match the compiler default.
1069 (simple_object_copy_lto_debug_sections): Never unlink the outfile
1070 on error as the caller does so.
1071 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
1072 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
1074 2024-01-22 Richard Biener <rguenther@suse.de>
1076 PR tree-optimization/113373
1077 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1078 Create LC PHIs in the exit blocks where necessary.
1079 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
1080 to handle missing LC PHIs.
1081 (find_connected_edge): Remove.
1082 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
1084 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1086 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
1088 2024-01-22 xuli <xuli1@eswincomputing.com>
1090 PR target/113420
1091 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
1092 (registered_function::overloaded_hash):refactor.
1093 (resolve_overloaded_builtin):avoid internal ICE.
1095 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
1097 PR target/82420
1098 PR target/111279
1099 * calls.cc (emit_library_call_value_1): Pass valid TYPE
1100 to emit_push_insn.
1101 * expr.cc (emit_push_insn): Likewise.
1103 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
1105 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
1106 correcction version of last change.
1108 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
1110 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
1111 fix bugs in signature.
1113 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
1114 Richard Biener <rguenther@suse.de>
1116 PR rtl-optimization/111267
1117 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
1118 profitable_p method to likely_profitable_p.
1119 (try_fwprop_subst_node): Update call to likely_profitable_p.
1120 Only bail-out early when !prop.likely_profitable_p for instructions
1121 that are not single sets. When comparing costs, bail-out if the
1122 cost is unchanged and !prop.likely_profitable_p.
1124 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
1126 PR c++/90464
1127 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
1128 isn't enabled by -Wunused unless -Wextra is provided, and that
1129 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
1130 -Wunused doesn't enable -Wunused-* options documented as behaving
1131 otherwise, and list them explicitly.
1133 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
1135 PR c/109708
1136 * doc/invoke.texi (Warning Options): Fix broken example and
1137 clean up/reorganize the others. Also describe what the short-form
1138 options mean.
1140 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
1142 PR c/102998
1143 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
1144 (Warning Options): Correct/edit discussion of -Warray-parameter
1145 to make the first example less confusing, and fill in missing info.
1147 2024-01-20 Jakub Jelinek <jakub@redhat.com>
1149 PR tree-optimization/113462
1150 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
1151 Handle rhs1 INTEGER_CST like SSA_NAME.
1153 2024-01-20 Jakub Jelinek <jakub@redhat.com>
1155 PR tree-optimization/113491
1156 * tree-switch-conversion.cc (switch_conversion::build_constructors):
1157 If elt.index has precision higher than sizetype, fold_convert it to
1158 sizetype.
1159 (switch_conversion::array_value_type): Return type if type is
1160 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
1161 (switch_conversion::build_arrays): Use unsigned_type_for rather than
1162 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
1163 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
1164 higher than sizetype, use sizetype as tidx type and fold_convert the
1165 subtraction to sizetype.
1167 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1169 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
1170 (riscv_vector_mode_supported_any_target_p): Ditto.
1172 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
1174 PR target/110934
1175 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
1176 (TARGET_ZERO_CALL_USED_REGS): Define.
1178 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
1180 PR target/108640
1181 * config/m68k/m68k.cc (output_andsi3): Use QImode for
1182 address adjusted for 1-byte RMW access.
1183 (output_iorsi3): Likewise.
1184 (output_xorsi3): Likewise.
1186 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1188 * doc/invoke.texi (RISC-V Options): Add list of supported
1189 extensions.
1191 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1193 PR target/113495
1194 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
1195 (RVV_VUNDEF): Ditto.
1196 * config/riscv/riscv-vsetvl.cc: Add timevar.
1198 2024-01-19 Richard Biener <rguenther@suse.de>
1200 PR debug/113488
1201 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
1202 an early DIE but there should be, do not pretend there is.
1204 2024-01-19 Richard Biener <rguenther@suse.de>
1206 PR tree-optimization/113494
1207 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1208 Handle endless loop on exit. Handle re-allocated PHI.
1210 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1212 PR tree-optimization/113464
1213 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
1214 optimize loads into GIMPLE_ASM stmts.
1216 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1218 PR tree-optimization/113463
1219 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
1220 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
1221 lhs.
1223 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1225 PR tree-optimization/113459
1226 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
1227 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
1228 of SCALAR_INT_TYPE_MODE if type has BLKmode.
1229 (vn_reference_lookup_3): Likewise. Formatting fix.
1231 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1232 Richard Biener <rguenther@suse.de>
1234 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
1235 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
1236 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
1237 but adjust_address also for BLKmode mode and MEM op0.
1239 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
1241 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
1242 extensions.
1244 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1246 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
1248 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1250 * common/config/riscv/riscv-common.cc
1251 (riscv_subset_list::parse_std_ext): Remove.
1252 (riscv_subset_list::parse_multiletter_ext): Remove.
1253 * config/riscv/riscv-subset.h
1254 (riscv_subset_list::parse_std_ext): Remove.
1255 (riscv_subset_list::parse_multiletter_ext): Remove.
1257 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1259 * common/config/riscv/riscv-common.cc
1260 (riscv_subset_list::parse_single_std_ext): New parameter.
1261 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
1262 (riscv_subset_list::parse_single_ext): Ditto.
1263 (riscv_subset_list::parse): Relax the order for the input of ISA
1264 string.
1265 * config/riscv/riscv-subset.h
1266 (riscv_subset_list::parse_single_std_ext): New parameter.
1267 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
1268 (riscv_subset_list::parse_single_ext): Ditto.
1270 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1272 * common/config/riscv/riscv-common.cc
1273 (riscv_subset_list::parse_base_ext): New.
1274 (riscv_subset_list::parse): Extract part of logic into
1275 riscv_subset_list::parse_base_ext.
1276 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
1277 New.
1279 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1281 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
1282 sorry message.
1284 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
1286 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
1287 UNSPEC_CLMUL_VC.
1289 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
1291 PR c/110029
1292 * doc/extend.texi (Common Variable Attributes): Explain what
1293 happens when multiple variables with cleanups are in the same scope.
1295 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1297 PR ipa/108470
1298 * doc/extend.texi (Common Function Attributes): Document that
1299 noinline also disables some interprocedural optimizations and
1300 improve flow to the part about using inline asm instead to
1301 disable calls from being optimized away completely. Remove the
1302 sentence that says noipa is mainly for internal compiler testing.
1304 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
1306 PR tree-optimization/69807
1307 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
1309 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
1311 PR target/108521
1312 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
1313 from x86 Windows Options.
1315 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1317 PR c/107942
1318 * doc/extend.texi (C Extensions): Add new section to menu.
1319 (Function Attributes): Move dangling index entries to....
1320 (Const and Volatile Functions): New section.
1322 2024-01-18 David Malcolm <dmalcolm@redhat.com>
1324 PR middle-end/112684
1325 * toplev.cc (toplev::main): Don't ICE in
1326 -fdiagnostics-generate-patch when exiting after options,
1327 since no edit context will have been created.
1329 2024-01-18 Richard Biener <rguenther@suse.de>
1331 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
1332 operands vector.
1334 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1336 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
1337 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
1339 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1340 Jin Ma <jinma@linux.alibaba.com>
1341 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1342 Christoph Müllner <christoph.muellner@vrull.eu>
1344 * config/riscv/thead.cc
1345 (th_asm_output_opcode): Rewrite some instructions.
1347 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1348 Jin Ma <jinma@linux.alibaba.com>
1349 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1350 Christoph Müllner <christoph.muellner@vrull.eu>
1352 * config/riscv/riscv.md (none,thv,rvv): New attribute.
1353 (no,yes): Add an attribute to disable alternative
1354 for xtheadvector or RVV1.0.
1355 * config/riscv/vector.md:
1356 Disable alternatives that destination register overlaps
1357 source register group for xtheadvector.
1359 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1360 Jin Ma <jinma@linux.alibaba.com>
1361 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1362 Christoph Müllner <christoph.muellner@vrull.eu>
1364 * config/riscv/riscv-vector-builtins-bases.cc
1365 (class th_loadstore_width): Define new builtin bases.
1366 (class th_extract): Define new builtin bases.
1367 (BASE): Define new builtin bases.
1368 * config/riscv/riscv-vector-builtins-bases.h:
1369 Define new builtin class.
1370 * config/riscv/riscv-vector-builtins-shapes.cc
1371 (struct th_loadstore_width_def): Define new builtin shapes.
1372 (struct th_indexed_loadstore_width_def):
1373 Define new builtin shapes.
1374 (struct th_extract_def): Define new builtin shapes.
1375 (SHAPE): Define new builtin shapes.
1376 * config/riscv/riscv-vector-builtins-shapes.h:
1377 Define new builtin shapes.
1378 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
1379 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
1380 * config/riscv/riscv-vector-builtins.h
1381 (enum required_ext): Add new XTheadVector member.
1382 (struct function_group_info): Likewise.
1383 * config/riscv/t-riscv:
1384 Add thead-vector-builtins-functions.def
1385 * config/riscv/thead-vector.md
1386 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
1387 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
1388 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
1389 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
1390 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
1391 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
1392 (@pred_th_extract<mode>): Likewise.
1393 (*pred_th_extract<mode>): Likewise.
1394 * config/riscv/thead-vector-builtins-functions.def: New file.
1396 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1397 Jin Ma <jinma@linux.alibaba.com>
1398 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1399 Christoph Müllner <christoph.muellner@vrull.eu>
1401 * config.gcc: Add files for XTheadVector intrinsics.
1402 * config/riscv/autovec.md: Guard XTheadVector.
1403 * config/riscv/predicates.md: Disable immediate vl
1404 for XTheadVector.
1405 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
1406 Add pragma for XTheadVector.
1407 * config/riscv/riscv-string.cc (riscv_expand_block_move):
1408 Guard XTheadVector.
1409 * config/riscv/riscv-v.cc (vls_mode_valid_p):
1410 Avoid autovec.
1411 * config/riscv/riscv-vector-builtins-bases.cc:
1412 Do not normalize vsetvl instructions for XTheadVector.
1413 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
1414 New check type function.
1415 (build_one): Adjust for XTheadVector.
1416 * config/riscv/riscv-vector-switch.def (ENTRY):
1417 Disable fractional mode for the XTheadVector extension.
1418 (TUPLE_ENTRY): Likewise.
1419 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
1420 Guard XTheadVector.
1421 (riscv_preferred_simd_mode): Likewsie.
1422 (riscv_autovectorize_vector_modes): Likewise.
1423 (riscv_vector_mode_supported_any_target_p): Likewise.
1424 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
1425 * config/riscv/thead.cc (th_asm_output_opcode):
1426 Rewrite vsetvl instructions.
1427 * config/riscv/vector.md:
1428 Include thead-vector.md and change fractional LMUL
1429 into 1 for vbool.
1430 * config/riscv/riscv_th_vector.h: New file.
1431 * config/riscv/thead-vector.md: New file.
1433 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1434 Jin Ma <jinma@linux.alibaba.com>
1435 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1436 Christoph Müllner <christoph.muellner@vrull.eu>
1438 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
1439 Add new function to add assembler insn code prefix/suffix.
1440 (th_asm_output_opcode):
1441 Add Thead function to add assembler insn code prefix/suffix.
1442 * config/riscv/riscv.cc (riscv_asm_output_opcode):
1443 Implement function to add assembler insn code prefix/suffix.
1444 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
1445 Add new function to add assembler insn code prefix/suffix.
1446 * config/riscv/thead.cc (th_asm_output_opcode):
1447 Implement Thead function to add assembler insn code
1448 prefix/suffix.
1450 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1451 Jin Ma <jinma@linux.alibaba.com>
1452 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1453 Christoph Müllner <christoph.muellner@vrull.eu>
1455 * common/config/riscv/riscv-common.cc
1456 (riscv_subset_list::parse): Add new vendor extension.
1457 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
1458 Add test marco.
1459 * config/riscv/riscv.opt: Add new mask.
1461 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1463 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
1464 to be conditional on macosx-version-min.
1466 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1468 * config/darwin.cc (darwin_objc1_section): Use the correct
1469 meta-data version for constant strings.
1470 (machopic_select_section): Assert if we fail to handle CFString
1471 sections as Obejctive-C meta-data or drectly.
1473 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1475 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
1476 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
1477 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
1478 versions when the object format is Mach-O.
1480 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1482 PR target/105522
1483 * config/darwin.cc (machopic_select_section): Handle C and C++
1484 CFStrings.
1485 (darwin_rename_builtins): Move this out of the CFString code.
1486 (darwin_libc_has_function): Likewise.
1487 (darwin_build_constant_cfstring): Create an anonymous var to
1488 hold each CFString.
1489 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
1490 CFstrings.
1492 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
1494 PR bootstrap/113445
1495 * haifa-sched.cc (dep_list_size): Make global.
1496 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
1497 * sched-int.h (dep_list_size): Declare.
1499 2024-01-18 Martin Jambor <mjambor@suse.cz>
1501 PR tree-optimization/110422
1502 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
1503 gotos.
1505 2024-01-18 Richard Biener <rguenther@suse.de>
1507 PR tree-optimization/113475
1508 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
1509 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
1510 (phi_analyzer::~phi_analyzer): Deallocate and free collected
1511 phi_grous.
1512 (phi_analyzer::process_phi): Record allocated phi_groups.
1514 2024-01-18 Richard Biener <rguenther@suse.de>
1516 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
1517 storage for gvec_oprnds elements.
1519 2024-01-18 Richard Biener <rguenther@suse.de>
1521 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
1522 prefer all later exits we can handle.
1523 (vect_analyze_loop_form): Free the allocated loop body.
1524 Adjust comments.
1526 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1528 * config/avr/avr-log.cc: Tabify.
1530 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1532 * config/riscv/autovec.md: Support vi variant.
1534 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1536 * config/avr/avr-devices.cc: Tabify.
1538 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1540 * config/avr/avr-c.cc: Tabify.
1542 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1544 * config/avr/driver-avr.cc: Tabify.
1546 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1548 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
1550 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1552 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
1554 2024-01-18 Jakub Jelinek <jakub@redhat.com>
1556 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
1557 minline-strcmp, minline-strncmp, minline-strlen,
1558 -param=riscv-vector-abi): Remove Bool keywords.
1560 2024-01-18 Jakub Jelinek <jakub@redhat.com>
1562 PR target/113122
1563 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
1564 support. Add missing space after , in emitted assembly in some
1565 cases. Formatting fixes.
1567 2024-01-18 Xi Ruoyao <xry111@xry111.site>
1569 * config/loongarch/loongarch.md (movsi_internal): Remove
1570 constraint z.
1572 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1574 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
1575 in the diagnostic, and capitalize the device name.
1576 (print_mcu): Generate specs such that:
1577 <*check_rodata_in_ram>: New.
1578 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
1579 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
1580 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
1582 2024-01-18 Jakub Jelinek <jakub@redhat.com>
1584 PR other/113399
1585 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
1586 Common and Optimization.
1588 2024-01-18 Richard Biener <rguenther@suse.de>
1590 PR tree-optimization/113431
1591 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
1592 When there is an invariant load we might not preserve
1593 scalar order.
1595 2024-01-18 Richard Biener <rguenther@suse.de>
1597 PR tree-optimization/113374
1598 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
1599 * tree-vect-loop.cc (move_early_exit_stmts): Update
1600 virtual LC PHIs.
1601 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1602 Refactor. Preserve virtual LC PHIs on all exits.
1604 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
1606 * config/loongarch/loongarch.cc (loongarch_split_symbol):
1607 Assign the '/u' attribute to the mem.
1609 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1611 PR middle-end/110847
1612 * doc/invoke.texi (Option Summary): Document negative forms of
1613 -Wtsan and -Wxor-used-as-pow.
1614 (Warning Options): Likewise.
1616 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1618 PR target/113429
1619 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
1621 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1623 * doc/extend.texi (Common Function Attributes): Re-alphabetize
1624 the table.
1625 (Common Variable Attributes): Likewise.
1626 (Common Type Attributes): Likewise.
1628 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1630 PR middle-end/111659
1631 * doc/extend.texi (Common Variable Attributes): Fix long lines
1632 in documentation of strict_flex_array + other minor copy-editing.
1633 Add a cross-reference to -Wstrict-flex-arrays.
1634 * doc/invoke.texi (Option Summary): Fix whitespace in tables
1635 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
1636 (C Dialect Options): Combine the docs for the two
1637 -fstrict-flex-arrays forms into a single entry. Note this option
1638 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
1639 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
1640 Minor copy-editing. Add cross references to the strict_flex_array
1641 attribute and -fstrict-flex-arrays option. Add note that this
1642 option depends on -ftree-vrp.
1644 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
1646 PR target/113221
1647 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
1648 only allow REG operands instead of allowing all.
1650 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
1652 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
1653 Remove redundant checks in else condition for readablity.
1654 (earliest_fuse_vsetvl_info) Print iteration count in debug
1655 prints.
1656 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
1657 dump details in certain cases.
1659 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
1661 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
1662 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
1663 * config/riscv/riscv-vsetvl.cc
1664 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
1665 (pass_vsetvl::execute): Use vsetvl_strategy.
1667 2024-01-17 Jan Hubicka <jh@suse.cz>
1669 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
1670 accidental hack reseting offset.
1672 2024-01-17 Jan Hubicka <jh@suse.cz>
1674 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
1675 handling of X86_TUNE_AVOID_512FMA_CHAINS.
1677 2024-01-17 Jan Hubicka <jh@suse.cz>
1678 Jakub Jelinek <jakub@redhat.com>
1680 PR tree-optimization/110852
1681 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
1682 binary operations
1683 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
1684 PRED_COMBINED_VALUE_PREDICTIONS_PHI
1685 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
1686 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
1688 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1690 PR tree-optimization/113421
1691 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
1692 comment.
1693 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
1694 formatting. Start at vop rather than cvop even if stmt is a store
1695 and needs_operand_addr.
1697 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1699 PR middle-end/113410
1700 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
1701 If access_nelts is integral with larger precision than sizetype,
1702 fold_convert it to sizetype.
1704 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1706 PR tree-optimization/113408
1707 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
1708 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
1709 to handle_cast.
1711 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1713 PR middle-end/113406
1714 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
1715 regardless of whether is_gimple_reg_type (restype) or not.
1717 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1719 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
1720 funcions -> functions, and use were instead of was.
1721 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
1722 and guaranteee -> guarantee.
1723 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
1725 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1727 PR middle-end/113409
1728 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
1729 INTEGER_TYPE.
1730 (omp_extract_for_data): Use build_bitint_type rather than
1731 build_nonstandard_integer_type if either iter_type or loop->v type
1732 is BITINT_TYPE.
1733 * omp-expand.cc (expand_omp_for_generic,
1734 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
1735 BITINT_TYPE like INTEGER_TYPE.
1737 2024-01-17 Richard Biener <rguenther@suse.de>
1739 PR tree-optimization/113371
1740 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
1741 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
1742 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
1743 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
1745 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
1747 PR rtl-optimization/96388
1748 PR rtl-optimization/111554
1749 * sched-deps.cc (find_inc): Avoid exponential behavior.
1751 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1753 PR c/111693
1754 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
1755 from C++ Language Options to Warning Options. Add entry for
1756 -Wuse-after-free.
1757 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
1758 from here....
1759 (Warning Options): ...to here. Minor copy-editing to fix typo
1760 and grammar.
1762 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
1764 * config/mips/mips.cc (mips_compute_frame_info): If another
1765 register is used as global_pointer, mark $GP live false.
1767 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1769 PR target/112973
1770 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
1771 give the section a light copy-editing pass.
1773 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
1775 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
1776 * config/aarch64/aarch64-tune.md: Regenerated.
1777 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
1779 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
1781 PR target/112573
1782 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
1783 badly formed CONST expressions.
1785 2024-01-16 Daniel Cederman <cederman@gaisler.com>
1787 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
1789 2024-01-16 Daniel Cederman <cederman@gaisler.com>
1791 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
1792 * config/sparc/sync.md (membar_storeload): Turn into named insn
1793 and add GR712RC errata workaround.
1794 (membar_v8): Add GR712RC errata workaround.
1796 2024-01-16 Andreas Larsson <andreas@gaisler.com>
1798 * config/sparc/sync.md (*membar_storeload_leon3): Remove
1799 (*membar_storeload): Enable for LEON
1801 2024-01-16 Jakub Jelinek <jakub@redhat.com>
1803 PR tree-optimization/113372
1804 PR middle-end/90348
1805 PR middle-end/110115
1806 PR middle-end/111422
1807 * cfgexpand.cc (add_scope_conflicts_2): New function.
1808 (add_scope_conflicts_1): Use it.
1810 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
1812 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
1813 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
1814 * doc/avr-mmcu.texi: Regenerate.
1816 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
1818 PR tree-optimization/113091
1819 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
1820 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
1821 scalar use with new function.
1822 (vect_bb_slp_mark_live_stmts): New function as entry to existing
1823 overriden functions with same name.
1824 (vect_slp_analyze_operations): Call new entry function to mark
1825 live statements.
1827 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1829 PR target/113404
1830 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
1831 for RVV in big-endian mode.
1833 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
1835 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
1836 (riscv_pass_in_vector_p): Delete.
1837 (riscv_init_cumulative_args): Delete the checking.
1838 (riscv_get_arg_info): Delete the checking.
1839 (riscv_function_value): Delete the checking.
1840 * config/riscv/riscv.h: Delete the member for checking.
1842 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
1844 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
1846 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
1848 * config.gcc: Include riscv_bitmanip.h.
1849 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
1850 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
1851 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
1852 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
1853 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
1854 * config/riscv/riscv-ftypes.def (2): New ftypes.
1855 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
1856 (RISCV_BUILTIN_NO_PREFIX): Likewise.
1857 * config/riscv/riscv_bitmanip.h: New file.
1859 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
1861 * config.gcc: Include riscv_crypto.h.
1862 * config/riscv/riscv_crypto.h: New file.
1864 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
1866 PR middle-end/113354
1867 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
1868 in the insn if the corresponding operand does not require hard
1869 register anymore.
1871 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
1873 PR target/107201
1874 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
1875 * config/avr/driver-avr.cc (avr_no_devlib): New function.
1876 (avr_devicespecs_file): Use it to remove -nodevicelib from the
1877 options for cores only.
1878 * config/avr/avr-arch.h (avr_get_parch): New prototype.
1879 * config/avr/avr-devices.cc (avr_get_parch): New function.
1881 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1883 PR target/113247
1884 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
1885 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
1886 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
1888 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1890 PR target/113281
1891 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
1892 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
1893 * config/riscv/riscv-vector-costs.h: New function.
1895 2024-01-15 Richard Biener <rguenther@suse.de>
1897 PR tree-optimization/113385
1898 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1899 First redirect, then split the exit edge.
1901 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1903 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
1904 Remove m_num_vector_iterations.
1905 * config/riscv/riscv-vector-costs.h: Ditto.
1907 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
1909 PR target/113156
1910 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
1911 (-mbranch-cost): Set "Optimization" flag.
1913 2024-01-15 Jakub Jelinek <jakub@redhat.com>
1915 PR tree-optimization/113370
1916 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
1917 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
1918 set it to just prec % limb_prec.
1920 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1922 PR target/113393
1923 * config/riscv/vector.md: Fix ternary attributes.
1925 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
1927 PR target/112944
1928 * configure.ac [target=avr]: Check availability of emulations
1929 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
1930 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
1931 * configure: Regenerate.
1932 * config.in: Regenerate.
1933 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
1934 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
1935 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
1936 * config/avr/avr-arch.h (enum avr_device_specific_features):
1937 Add AVR_ISA_FLMAP.
1938 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
1939 AVR_ISA_FLMAP.
1940 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
1941 (avr_set_core_architecture): Set avr_arch_index.
1942 (have_avrxmega2_flmap, have_avrxmega4_flmap)
1943 (have_avrxmega3_rodata_in_flash): Set new static const bool according
1944 to configure results.
1945 (avr_rodata_in_flash_p): New function using them.
1946 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
1947 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
1948 (avr_asm_named_section): Track avr_has_rodata_p.
1949 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
1950 and not avr_rodata_in_flash_p ().
1951 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
1952 (LINK_SPEC): Add %(link_rodata_in_ram).
1953 (LINK_ARCH_SPEC): Remove.
1954 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
1955 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
1956 const bool according to configure results.
1957 (diagnose_mrodata_in_ram): New function.
1958 (print_mcu): Generate specs with the following changes:
1959 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
1960 need to extend avr/specs.h each time we add a new bell or whistle.
1961 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
1962 -m[no-]rodata-in-ram.
1963 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
1964 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
1965 <*cpp>: Add %(cpp_rodata_in_ram).
1966 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
1967 requested.
1968 <*self_spec>: Add -mflmap or %<mflmap as needed.
1970 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
1972 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
1973 not the GPR iterator. Adjust pattern name and mode attribute
1974 accordingly.
1976 2024-01-13 Jakub Jelinek <jakub@redhat.com>
1978 PR tree-optimization/113361
1979 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
1980 Fix up determination of the type for > limb_prec constants.
1982 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
1984 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
1985 Add web-link to the avr-gcc wiki.
1987 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
1989 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
1990 documentation for a version without argument, which is not supported.
1992 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
1994 * config/arm/arm_neon.h
1995 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
1996 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
1997 (vld1_f16_x4, vld1_f32_x4): New.
1998 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
1999 (vld1_bf16_x4): New.
2000 (vld1q_types_x4): Updated to use vld1q_x4
2001 from arm_neon_builtins.def
2002 * config/arm/arm_neon_builtins.def
2003 (vld1_x4): Updated entries.
2004 (vld1q_x4): New entries, but comes from the old vld1_x4
2005 * config/arm/neon.md
2006 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
2008 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2010 * config/arm/arm_neon.h
2011 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
2012 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
2013 (vld1_f16_x3, vld1_f32_x3): New.
2014 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
2015 (vld1_bf16_x3): New.
2016 (vld1q_types_x3): Updated to use vld1q_x3 from
2017 arm_neon_builtins.def
2018 * config/arm/arm_neon_builtins.def
2019 (vld1_x3): Updated entries.
2020 (vld1q_x3): New entries, but comes from the old vld1_x2
2021 * config/arm/neon.md
2022 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
2024 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2026 * config/arm/arm_neon.h
2027 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
2028 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
2029 (vld1_f16_x2, vld1_f32_x2): New.
2030 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
2031 (vld1_bf16_x2): New.
2032 (vld1q_types_x2): Updated to use vld1q_x2 from
2033 arm_neon_builtins.def
2034 * config/arm/arm_neon_builtins.def
2035 (vld1_x2): Updated entries.
2036 (vld1q_x2): New entries, but comes from the old vld1_x2
2037 * config/arm/neon.md
2038 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
2039 neon_vld1_x2<mode>.
2041 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2043 * config/arm/arm_neon.h
2044 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
2045 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
2046 (vst1q_f16_x4, vst1q_f32_x4): New.
2047 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
2048 (vst1q_bf16_x4): New.
2049 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
2050 * config/arm/neon.md
2051 (neon_vst1q_x4<mode>): New.
2052 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
2053 * config/arm/unspecs.md
2054 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
2056 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2058 * config/arm/arm_neon.h
2059 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
2060 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
2061 (vst1q_f16_x3, vst1q_f32_x3): New.
2062 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
2063 (vst1q_bf16_x3): New.
2064 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
2065 * config/arm/neon.md
2066 (neon_vst1q_x3<mode>): New.
2067 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
2068 * config/arm/unspecs.md
2069 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
2071 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2073 * config/arm/arm_neon.h
2074 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
2075 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
2076 (vst1q_f16_x2, vst1q_f32_x2): New.
2077 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
2078 (vst1q_bf16_x2): New.
2079 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
2080 * config/arm/neon.md
2081 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
2082 neon_vst1_x2<mode>.
2083 * config/arm/iterators.md
2084 (VMEMX2): New mode iterator.
2085 (VMEMX2_q): New mode attribute.
2087 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2089 * config/arm/arm_neon.h
2090 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
2091 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
2092 (vst1_f16_x4, vst1_f32_x4): New.
2093 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
2094 (vst1_bf16_x4): New.
2095 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
2096 * config/arm/neon.md (vst1_x4<mode>): New.
2098 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2100 * config/arm/arm_neon.h
2101 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
2102 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
2103 (vst1_f16_x3, vst1_f32_x3): New.
2104 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
2105 (vst1_bf16_x3): New.
2106 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
2107 * config/arm/neon.md (vst1_x3<mode>): New.
2109 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2111 * config/arm/arm_neon.h
2112 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
2113 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
2114 (vst1_f16_x2, vst1_f32_x2): New.
2115 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
2116 (vst1_bf16_x2): New.
2117 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
2118 * config/arm/neon.md (vst1_x2<mode>): New.
2120 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2122 * config/arm/arm_neon.h
2123 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
2124 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
2125 (vld1q_f16_x4, vld1q_f32_x4): New.
2126 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
2127 (vld1q_bf16_x4): New.
2128 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
2129 * config/arm/neon.md
2130 (neon_vld1_x4<mode>): New.
2131 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
2132 * config/arm/unspecs.md
2133 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
2135 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2137 * config/arm/arm_neon.h
2138 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
2139 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
2140 (vld1q_f16_x3, vld1q_f32_x3): New.
2141 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
2142 (vld1q_bf16_x3): New.
2143 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
2144 * config/arm/neon.md
2145 (neon_vld1_x3<mode>): New.
2146 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
2147 * config/arm/unspecs.md
2148 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
2150 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2152 * config/arm/arm_neon.h
2153 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
2154 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
2155 (vld1q_f16_x2, vld1q_f32_x2): New.
2156 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
2157 (vld1q_bf16_x2): New.
2158 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
2159 * config/arm/neon.md (vld1_x2<mode>): New.
2161 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2163 PR tree-optimization/113287
2164 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
2166 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2168 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
2169 * tree-vect-loop.cc (vect_transform_loop): Likewise.
2171 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2173 PR tree-optimization/113178
2174 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
2175 alternate exits.
2177 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2179 PR tree-optimization/113237
2180 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
2181 existing LCSSA variable for exit when all exits are early break.
2183 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2185 PR tree-optimization/113137
2186 PR tree-optimization/113136
2187 PR tree-optimization/113172
2188 PR tree-optimization/113178
2189 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2190 Maintain PHIs on inverted loops.
2191 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
2192 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
2193 latch.
2194 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
2196 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2198 PR tree-optimization/113135
2199 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
2200 dependency analysis.
2202 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
2204 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
2205 diagnostics class member name for abort of error.
2207 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
2209 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
2210 format string to %s argument.
2212 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
2213 Jakub Jelinek <jakub@redhat.com>
2215 PR middle-end/113182
2216 * varasm.cc (process_pending_assemble_externals,
2217 assemble_external_libcall): Use targetm.strip_name_encoding
2218 before calling get_identifier.
2220 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2222 PR target/113196
2223 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
2224 New member variable.
2225 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
2226 Declare.
2227 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
2228 * config/aarch64/aarch64-simd.md
2229 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
2230 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
2231 zip2 for zero-extends to...
2232 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
2233 instruction. Fix big-endian handling.
2234 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
2235 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
2236 zip1 for zero-extends to...
2237 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
2238 Fix big-endian handling.
2239 (*aarch64_zip1_uxtl): New pattern.
2240 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
2241 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
2242 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
2243 (aarch64_gen_shareable_zero): Use it.
2244 (aarch64_split_simd_shift_p): New function.
2246 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2248 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
2249 (function_beg_insn): New macro.
2250 * function.cc (expand_function_start): Initialize function_beg_insn.
2252 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2254 PR target/112989
2255 * config/aarch64/aarch64-sve-builtins.h
2256 (function_builder::m_overload_names): Replace with...
2257 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
2258 new global.
2259 (add_overloaded_function): Update accordingly, using get_identifier
2260 to get a GGC-friendly record of the name.
2262 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2264 PR target/112989
2265 * config/aarch64/aarch64-sve-builtins.def: Don't include
2266 aarch64-sve-builtins-sme.def.
2267 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
2268 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
2269 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
2270 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
2271 requires AARCH64_FL_SME2.
2272 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
2273 AARCH64_FL_SME adjustment here.
2274 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
2275 include SME intrinsics.
2276 (sme_function_groups): New array.
2277 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
2278 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
2280 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2282 PR target/113281
2283 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
2284 (struct cpu_vector_cost): Add regmove struct.
2285 (get_vector_costs): Export as global.
2286 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
2287 (costs::add_stmt_cost): Ditto.
2288 * config/riscv/riscv.cc (get_common_costs): Export global function.
2290 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2292 PR tree-optimization/113334
2293 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
2294 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
2295 to determine if number should be extended by all ones rather than zero
2296 extended.
2298 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2300 PR tree-optimization/113330
2301 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
2302 too large size.
2304 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2306 PR tree-optimization/113323
2307 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
2308 check for lhs being large/huge _BitInt not in m_names.
2310 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2312 PR tree-optimization/113316
2313 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
2314 uninitialized large/huge _BitInt arguments to calls.
2316 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2318 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
2319 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
2320 CEIL (TYPE_PRECISION (t), limb_prec).
2321 (bitint_large_huge::handle_cast): Likewise.
2323 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
2325 PR sanitizer/113284
2326 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
2327 Use assemble_function_label_final () for Power ELF V1 ABI.
2328 * output.h (assemble_function_label_final): New function.
2329 * varasm.cc (assemble_function_label_raw): Use
2330 assemble_function_label_final ().
2331 (assemble_function_label_final): New function.
2333 2024-01-12 Richard Biener <rguenther@suse.de>
2335 PR middle-end/113344
2336 * match.pd ((double)float CMP (double)float -> float CMP float):
2337 Perform result type check only for vectors.
2338 * fold-const.cc (fold_binary_loc): Likewise.
2340 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
2342 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
2343 (usdot_prod<mode>): Ditto.
2344 (sdot_prod<mode>): Ditto.
2345 (udot_prod<mode>): Ditto.
2347 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
2349 PR target/113288
2350 * config/i386/i386-c.cc (ix86_target_macros_internal):
2351 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
2353 2024-01-12 Richard Biener <rguenther@suse.de>
2355 PR target/112280
2356 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
2357 Do not generate code when d.testing_p.
2359 2024-01-12 liuhongt <hongtao.liu@intel.com>
2361 PR target/113039
2362 * doc/invoke.texi (fcf-protection=): Update documents.
2364 2024-01-12 Pan Li <pan2.li@intel.com>
2366 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
2367 comments of predicate func riscv_v_ext_mode_p.
2369 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
2371 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
2372 Modify ABI-name length of vfloat16m8_t
2374 2024-01-12 Li Wei <liwei@loongson.cn>
2376 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
2377 Adjust.
2379 2024-01-12 Li Wei <liwei@loongson.cn>
2381 * config/loongarch/loongarch.md (add<mode>3): Removed.
2382 (*addsi3): New.
2383 (addsi3): Ditto.
2384 (adddi3): Ditto.
2385 (*addsi3_extended): Removed.
2386 (addsi3_extended): New.
2388 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
2390 * config/riscv/thead.md: Add limits for splits.
2392 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
2394 PR middle-end/113322
2395 * expr.cc (do_store_flag): Don't try single bit tests with
2396 comparison on vector types.
2398 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
2400 PR tree-optimization/113301
2401 * match.pd (`1/x`): Delay signed case until late.
2403 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
2405 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
2406 and -msp8 to...
2407 (AVR Internal Options): ...this new @subsubsection.
2409 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
2411 PR rtl-optimization/112918
2412 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
2413 (in_class_p): Restrict condition for narrowing class in case of
2414 allow_all_reload_class_changes_p.
2415 (process_alt_operands): Try to match operand without and with
2416 narrowing reg class. Discourage narrowing the class. Finish insn
2417 matching only if there is no class narrowing.
2418 (curr_insn_transform): Pass true to in_class_p for reg operand win.
2420 2024-01-11 Richard Biener <rguenther@suse.de>
2422 PR tree-optimization/112505
2423 * tree-vect-loop.cc (vectorizable_induction): Reject
2424 bit-precision induction.
2426 2024-01-11 Richard Biener <rguenther@suse.de>
2428 PR tree-optimization/113126
2429 * match.pd ((double)float CMP (double)float -> float CMP float):
2430 Make sure the boolean type is the same.
2431 * fold-const.cc (fold_binary_loc): Likewise.
2433 2024-01-11 Richard Biener <rguenther@suse.de>
2435 PR tree-optimization/112636
2436 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
2437 estimate_numbers_of_iterations before querying
2438 get_max_loop_iterations_int.
2439 (pass_ch::execute): Initialize SCEV and loops appropriately.
2441 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
2443 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
2444 Reduced Tiny.
2445 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
2446 * doc/extend.texi (AVR Variable Attributes): Improve documentation
2447 of io, io_low and address attributes.
2448 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
2449 * doc/avr-mmcu.texi: Rebuild.
2451 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
2453 PR target/113233
2454 * config/loongarch/genopts/loongarch.opt.in: Mark options with
2455 the "Save" property.
2456 * config/loongarch/loongarch.opt: Same.
2457 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
2458 according to la_target.
2459 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
2460 RESTORE} for the la_target structure; Rename option conditions
2461 to have the same "la_" prefix.
2462 * config/loongarch/loongarch.h: Same.
2464 2024-01-11 Pan Li <pan2.li@intel.com>
2466 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
2467 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
2469 2024-01-11 Alex Coplan <alex.coplan@arm.com>
2471 PR target/113077
2472 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
2473 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
2474 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
2475 synthesize these if needed. Update caller ...
2476 (ldp_bb_info::fuse_pair): ... here.
2477 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
2478 and either insn is frame-related.
2479 (find_trailing_add): Punt on frame-related insns.
2480 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
2481 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
2483 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
2485 * config/mips/mips.cc (mips_start_function_definition):
2486 Add ATTRIBUTE_UNUSED.
2488 2024-01-11 Richard Biener <rguenther@suse.de>
2490 PR middle-end/112740
2491 * expr.cc (store_constructor): Check the integer vector
2492 mask has a single bit per element before using sign-extension
2493 to expand an uniform vector.
2495 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2497 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
2498 preempt VLS on unknown NITERS loop.
2500 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
2502 * doc/invoke.texi: Add -mevex512.
2504 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
2506 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
2507 (*nor<mode>3): Likewise.
2508 (nor<mode>3): Likewise.
2509 (*negsi2_extended): New template.
2510 (*<optab>si3_internal): Likewise.
2511 (*one_cmplsi2_internal): Likewise.
2512 (*norsi3_internal): Likewise.
2513 (*<optab>nsi_internal): Likewise.
2514 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
2515 modified bit operation to make the optimization work.
2517 2024-01-11 liuhongt <hongtao.liu@intel.com>
2519 PR target/104401
2520 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
2522 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2524 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
2525 (get_vector_costs): Ditto.
2526 (riscv_builtin_vectorization_cost): Ditto.
2528 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2530 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
2532 2024-01-10 Antoni Boucher <bouanto@zoho.com>
2534 PR jit/111396
2535 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
2536 ipa_free_size_summary.
2537 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
2538 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
2539 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
2540 * ipa-prop.h (ipa_prop_cc_finalize): New function.
2541 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
2542 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
2543 ipa_sra_cc_finalize): New functions.
2544 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
2545 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
2546 ipa_sra_cc_finalize
2547 Include ipa-utils.h.
2549 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
2551 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
2552 (th_int_get_save_adjustment): Likewise.
2553 (th_int_adjust_cfi_prologue): Likewise.
2554 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
2555 (TH_INT_INTERRUPT): New macro.
2556 (riscv_expand_prologue): Add the processing of XTheadInt.
2557 (riscv_expand_epilogue): Likewise.
2558 * config/riscv/riscv.h (BITSET_P): Moved to here.
2559 * config/riscv/riscv.md: New unspec.
2560 * config/riscv/thead.cc (th_int_get_mask): New function.
2561 (th_int_get_save_adjustment): Likewise.
2562 (th_int_adjust_cfi_prologue): Likewise.
2563 * config/riscv/thead.md (th_int_push): New pattern.
2564 (th_int_pop): new pattern.
2566 2024-01-10 Tamar Christina <tamar.christina@arm.com>
2568 PR tree-optimization/112468
2569 * doc/sourcebuild.texi: Document ifn_copysign.
2570 * match.pd: Only apply transformation if target supports the IFN.
2572 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
2574 PR tree-optimization/112581
2575 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
2576 mark_ssa_maybe_undefs.
2577 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
2578 variables can not be reassociated.
2579 (init_range_entry): Check for uninitialized variables too.
2580 (init_reassoc): Call mark_ssa_maybe_undefs.
2582 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
2584 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
2585 Also handle sign extension.
2587 2024-01-10 Alex Coplan <alex.coplan@arm.com>
2589 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
2590 to 0.
2591 (-mlate-ldp-fusion): Likewise.
2593 2024-01-10 Tamar Christina <tamar.christina@arm.com>
2595 PR tree-optimization/113287
2596 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
2597 instead of using BRANCH_EDGE to determine true edge.
2599 2024-01-10 Richard Biener <rguenther@suse.de>
2601 PR tree-optimization/113078
2602 * tree-vect-loop.cc (check_reduction_path): Canonicalize
2603 .COND_SUB to .COND_ADD.
2605 2024-01-10 David Malcolm <dmalcolm@redhat.com>
2607 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
2608 Handle prefix mappings before calling find_opt.
2609 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
2610 "-fno-"-prefixed command-line option.
2611 * opts-common.cc (get_option_prefix_remapping): New.
2612 * opts.h (get_option_prefix_remapping): New decl.
2614 2024-01-10 David Malcolm <dmalcolm@redhat.com>
2616 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
2617 m_urlifier to pp_output_formatted_text.
2618 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
2619 (obstack_append_string): New overload, taking a length.
2620 (urlify_quoted_string): Pass in an obstack ptr, rather than using
2621 that of the pp's buffer. Generalize to handle trailing text in
2622 the buffer beyond the run of quoted text.
2623 (class quoting_info): New.
2624 (on_begin_quote): New.
2625 (on_end_quote): New.
2626 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
2627 it to calls to on_begin_quote and on_end_quote.
2628 (struct auto_obstack): New.
2629 (quoting_info::handle_phase_3): New.
2630 (pp_output_formatted_text): Add urlifier param. Use it if there
2631 is deferred urlification. Delete m_quotes.
2632 (selftest::pp_printf_with_urlifier): Pass urlifier to
2633 pp_output_formatted_text.
2634 (selftest::test_urlification): Update results for the existing
2635 case of quoted text stradding chunks; add more such test cases.
2636 * pretty-print.h (class quoting_info): New forward decl.
2637 (chunk_info::m_quotes): New field.
2638 (pp_output_formatted_text): Add optional urlifier param.
2640 2024-01-10 David Malcolm <dmalcolm@redhat.com>
2642 * pretty-print.cc (selftest::test_pp_format): Add selftest
2643 coverage for numbered args.
2645 2024-01-10 Tamar Christina <tamar.christina@arm.com>
2647 PR tree-optimization/113144
2648 PR tree-optimization/113145
2649 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2650 Update all BB that the original exits dominated.
2652 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
2654 * dwarf2out.cc (modified_type_die): Extend the support of reverse
2655 storage order to enumeration types if -gstrict-dwarf is not passed.
2656 (gen_enumeration_type_die): Add REVERSE parameter and generate the
2657 DIE immediately after the existing one if it is true.
2658 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
2659 call to gen_enumeration_type_die.
2660 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
2661 first recursive call as well as the call to gen_tagged_type_die.
2662 (gen_type_die): Add REVERSE parameter and pass it in the call to
2663 gen_type_die_with_usage.
2665 2024-01-10 Jakub Jelinek <jakub@redhat.com>
2667 PR tree-optimization/113120
2668 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
2669 with root->size TYPE_PRECISION don't build anything new.
2670 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
2671 rather than build_nonstandard_integer_type.
2673 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
2675 * config/i386/i386.opt: Adjust document.
2676 * doc/invoke.texi: Add description for
2677 -mapx-inline-asm-use-gpr32.
2679 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2681 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
2682 (avg<v_double_trunc>3_floor): New pattern.
2683 (<u>avg<v_double_trunc>3_ceil): Remove.
2684 (avg<v_double_trunc>3_ceil): New pattern.
2685 (uavg<mode>3_floor): Ditto.
2686 (uavg<mode>3_ceil): Ditto.
2687 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
2688 (enum insn_type): Ditto.
2689 * config/riscv/riscv-v.cc: Ditto.
2690 * config/riscv/vector-iterators.md (ashiftrt): Remove.
2691 (ASHIFTRT): Ditto.
2692 * config/riscv/vector.md: Add VLS modes.
2694 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
2696 PR target/111480
2697 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
2698 (vczlsbb_char): New int attribute.
2699 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
2700 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
2701 (*vctzlsbb_zext_<mode>): Rename to ...
2702 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
2703 cover vclzlsbb.
2705 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
2707 PR target/112606
2708 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
2709 of the last argument from altivec_register_operand to any_operand. If
2710 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
2711 otherwise if it doesn't satisfy altivec_register_operand, force it to
2712 REG using copy_to_mode_reg.
2714 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
2716 PR middle-end/113100
2717 * builtins.cc (expand_builtin_stack_address): Guard stack point
2718 adjustment with SPARC_STACK_BOUNDARY_HACK.
2720 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2722 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
2723 argument string definitions.
2724 * config/loongarch/loongarch-str.h: Same.
2725 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
2726 as aliases to -mexplicit-relocs={always,none}
2727 * config/loongarch/loongarch.opt: Regenerate.
2728 * config/loongarch/loongarch.cc: Same.
2730 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2732 * config/loongarch/loongarch-def.h: Define constants with
2733 enums instead of Macros.
2735 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2737 * config/loongarch/genopts/loongarch-strings: Rename.
2738 * config/loongarch/genopts/loongarch.opt.in: Same.
2739 * config/loongarch/loongarch-cpu.cc: Same.
2740 * config/loongarch/loongarch-def.cc: Same.
2741 * config/loongarch/loongarch-def.h: Same.
2742 * config/loongarch/loongarch-opts.cc: Same.
2743 * config/loongarch/loongarch-opts.h: Same.
2744 * config/loongarch/loongarch-str.h: Same.
2745 * config/loongarch/loongarch.opt: Same.
2747 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2749 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
2750 variable with the common la_ prefix.
2751 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
2752 flags as saved using TargetVariable.
2753 * config/loongarch/loongarch.opt: Same.
2754 * config/loongarch/loongarch-def.h: Define evolution_set to
2755 mark changes to the -march default.
2756 * config/loongarch/loongarch-driver.cc: Same.
2757 * config/loongarch/loongarch-opts.cc: Same.
2758 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
2759 conditions around the la_target structure.
2760 * config/loongarch/loongarch.cc: Same.
2761 * config/loongarch/loongarch.md: Same.
2762 * config/loongarch/loongarch-builtins.cc: Same.
2763 * config/loongarch/loongarch-c.cc: Same.
2764 * config/loongarch/lasx.md: Same.
2765 * config/loongarch/lsx.md: Same.
2766 * config/loongarch/sync.md: Same.
2768 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
2770 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
2771 no less.
2773 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
2775 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
2777 2024-01-09 Tamar Christina <tamar.christina@arm.com>
2779 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
2780 restart_loop.
2781 (vectorizable_live_operation): Likewise.
2783 2024-01-09 Tamar Christina <tamar.christina@arm.com>
2785 PR tree-optimization/113199
2786 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
2787 BIT_FIELD_REF.
2789 2024-01-09 Jakub Jelinek <jakub@redhat.com>
2791 PR target/113270
2792 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
2793 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
2794 GTY(()) declaration before the definition, drop GTY(()) drom the
2795 definition.
2797 2024-01-09 Richard Biener <rguenther@suse.de>
2799 PR tree-optimization/113026
2800 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
2801 redundant and wrong niter bound setting. Move niter
2802 bound adjustment down.
2804 2024-01-09 Tamar Christina <tamar.christina@arm.com>
2806 PR middle-end/113163
2807 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
2808 Reject non-linear inductions that aren't supported.
2810 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
2812 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
2813 left shift implementation strategies.
2814 (arc_shift_info): Type for each entry of the shift strategy table.
2815 (arc_shift_context_idx): Return a integer value for each code
2816 generation context, used as an index
2817 (arc_ashl_alg): Table indexed by context and shifted bit count.
2818 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
2819 left shift implementation.
2820 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
2821 provide accurate costs, when optimizing for speed or size.
2823 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2825 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
2827 2024-01-09 Julian Brown <julian@codesourcery.com>
2829 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
2830 processed out before gimplification.
2831 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
2832 * tree.def (OMP_ARRAY_SECTION): New tree code.
2834 2024-01-09 Jakub Jelinek <jakub@redhat.com>
2836 PR tree-optimization/113210
2837 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
2838 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
2839 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
2840 minus 1.
2842 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
2844 PR rtl-optimization/113140
2845 * reorg.cc (fill_slots_from_thread): If we are to branch after the
2846 last instruction of the function, create an end label.
2848 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
2849 Hongtao Liu <hongtao.liu@intel.com>
2851 PR target/112992
2852 * config/i386/i386-expand.cc
2853 (ix86_convert_const_wide_int_to_broadcast): Allow call to
2854 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
2855 (ix86_broadcast_from_constant): Revert recent change; Return a
2856 suitable MEMREF independently of mode/target combinations.
2857 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
2858 to decide whether expansion is possible/preferrable. Only try
2859 forcing DImode constants to memory (and trying again) if calling
2860 ix86_expand_vector_init_duplicate fails with an DImode immediate
2861 constant.
2862 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
2863 V4SImode for suitable immediate constants.
2864 <case E_V4DImode>: Try using V8SImode for suitable constants.
2865 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
2866 <case E_V2HImode>: Likewise.
2867 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
2868 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
2869 <label widen>: Handle CONT_INTs via simplify_binary_operation.
2870 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
2871 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
2872 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
2873 (ix86_expand_vector_init): Move try using a broadcast for all_same
2874 with ix86_expand_vector_init_duplicate before using constant pool.
2876 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
2878 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
2880 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
2882 * config/arm/arm-cpus.in (cortex-m52): New cpu.
2883 * config/arm/arm-tables.opt: Regenerate.
2884 * config/arm/arm-tune.md: Regenerate.
2886 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
2888 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
2889 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
2890 (@vec_concatz<mode>): New insn pattern.
2891 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
2892 Handle VALS containing two vectors.
2894 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2896 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
2897 (vundefined): Ditto.
2899 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
2901 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2902 Add new function_base for crypto vector.
2903 (class bitmanip): Ditto.
2904 (class b_reverse):Ditto.
2905 (class vwsll): Ditto.
2906 (class clmul): Ditto.
2907 (class vg_nhab): Ditto.
2908 (class crypto_vv):Ditto.
2909 (class crypto_vi):Ditto.
2910 (class vaeskf2_vsm3c):Ditto.
2911 (class vsm3me): Ditto.
2912 (BASE): Add BASE declaration for crypto vector.
2913 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2914 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2915 Add crypto vector intrinsic definition.
2916 (vbrev): Ditto.
2917 (vclz): Ditto.
2918 (vctz): Ditto.
2919 (vwsll): Ditto.
2920 (vandn): Ditto.
2921 (vbrev8): Ditto.
2922 (vrev8): Ditto.
2923 (vrol): Ditto.
2924 (vror): Ditto.
2925 (vclmul): Ditto.
2926 (vclmulh): Ditto.
2927 (vghsh): Ditto.
2928 (vgmul): Ditto.
2929 (vaesef): Ditto.
2930 (vaesem): Ditto.
2931 (vaesdf): Ditto.
2932 (vaesdm): Ditto.
2933 (vaesz): Ditto.
2934 (vaeskf1): Ditto.
2935 (vaeskf2): Ditto.
2936 (vsha2ms): Ditto.
2937 (vsha2ch): Ditto.
2938 (vsha2cl): Ditto.
2939 (vsm4k): Ditto.
2940 (vsm4r): Ditto.
2941 (vsm3me): Ditto.
2942 (vsm3c): Ditto.
2943 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2944 Add new function_shape for crypto vector.
2945 (struct crypto_vi_def): Ditto.
2946 (struct crypto_vv_no_op_type_def): Ditto.
2947 (SHAPE): Add SHAPE declaration of crypto vector.
2948 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2949 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2950 Add new data type for crypto vector.
2951 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2952 (vuint32mf2_t): Ditto.
2953 (vuint32m1_t): Ditto.
2954 (vuint32m2_t): Ditto.
2955 (vuint32m4_t): Ditto.
2956 (vuint32m8_t): Ditto.
2957 (vuint64m1_t): Ditto.
2958 (vuint64m2_t): Ditto.
2959 (vuint64m4_t): Ditto.
2960 (vuint64m8_t): Ditto.
2961 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2962 Add new data struct for crypto vector.
2963 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2964 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2965 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2967 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
2969 PR sanitizer/113251
2970 * varasm.cc (assemble_function_label_raw): Do not call
2971 asan_function_start () without the current function.
2973 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
2975 PR target/113225
2976 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
2977 extern and kernel_helper attributed function decls.
2979 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
2981 * btfout.cc (output_btf_strs): Changed.
2983 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
2985 * config/gcn/mkoffload.cc (main): Handle gfx1100
2986 when setting the default XNACK.
2988 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
2990 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
2991 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
2992 (ASM_SPEC): Handle gfx1100.
2993 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
2994 (enum gcn_isa): Add ISA_RDNA3.
2995 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
2996 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
2997 * config/gcn/gcn.cc (gcn_option_override,
2998 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
2999 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
3000 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
3001 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
3002 with gfx1100.
3003 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
3004 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
3005 __gfx1100__.
3006 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
3007 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
3008 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
3009 (isa_has_combined_avgprs, main): Handle gfx1100.
3010 * config/gcn/t-omp-device (isa): Add gfx1100.
3012 2024-01-08 Richard Biener <rguenther@suse.de>
3014 * doc/invoke.texi (-mmovbe): Clarify.
3016 2024-01-08 Richard Biener <rguenther@suse.de>
3018 PR tree-optimization/113026
3019 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
3020 Avoid an epilog in more cases.
3021 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
3022 epilogues niter upper bounds and estimates.
3024 2024-01-08 Jakub Jelinek <jakub@redhat.com>
3026 PR tree-optimization/113228
3027 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
3029 2024-01-08 Jakub Jelinek <jakub@redhat.com>
3031 PR tree-optimization/113120
3032 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
3033 large _BitInt zero INTEGER_CST PHI argument.
3035 2024-01-08 Jakub Jelinek <jakub@redhat.com>
3037 PR tree-optimization/113119
3038 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
3039 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
3040 is before REALPART_EXPR.
3042 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
3044 PR target/112952
3045 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
3046 range when diagnosing attribute "io" and "io_low" are out of range.
3047 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
3048 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
3049 in contexts other than static storage.
3050 (avr_asm_output_aligned_decl_common): Move output of decls with
3051 attribute "address", "io", and "io_low" to...
3052 (avr_output_addr_attrib): ...this new function.
3053 (avr_asm_asm_output_aligned_bss): Remove output for decls with
3054 attribute "address", "io", and "io_low".
3055 (avr_encode_section_info): Rectify handling of decls with attribute
3056 "address", "io", and "io_low".
3058 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
3060 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
3061 (elf_flags): Remove XNACK from the default value.
3062 (main): Set a default XNACK according to the arch.
3064 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
3066 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
3067 (process_asm): Don't count avgprs.
3069 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
3071 * config/i386/i386.opt: Add supported sub-features.
3072 * doc/extend.texi: Add description for target attribute.
3074 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
3076 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
3078 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
3079 Uros Bizjak <ubizjak@gmail.com>
3081 PR target/113231
3082 * config/i386/i386-features.cc (compute_convert_gain): Include
3083 the overhead of explicit load and store (movd) instructions when
3084 converting non-store scalar operations with memory destinations.
3085 Various indentation whitespace fixes.
3087 2024-01-07 Tamar Christina <tamar.christina@arm.com>
3089 * config/arm/neon.md (cbranch<mode>4): New.
3091 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3093 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
3095 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
3097 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
3099 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3101 PR target/113248
3102 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
3103 Update the MAX_SEW.
3105 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3107 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
3108 (variable_vectorized_p): Teach loop invariant.
3109 (has_unexpected_spills_p): Ditto.
3111 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3113 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
3114 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
3115 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
3117 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
3119 PR target/113104
3120 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
3121 (aarch64-vect-compare-costs): ...this.
3122 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
3123 Replace with...
3124 (-param=aarch64-vect-compare-costs=): ...this new param.
3125 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
3126 Don't disable it when vectorizing for Advanced SIMD only.
3127 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
3128 whenever aarch64_vect_compare_costs is true.
3130 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
3132 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
3133 Modify the method of determining the memory offset of [x]vld/[x]vst.
3134 (lasx_mxst_<lasxfmt_f>): Likewise.
3135 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
3136 (loongarch_address_insns): Likewise.
3137 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
3138 (lsx_st_<lsxfmt_f>): Likewise.
3139 * config/loongarch/predicates.md (aq10b_operand): Likewise.
3140 (aq10h_operand): Likewise.
3141 (aq10w_operand): Likewise.
3142 (aq10d_operand): Likewise.
3144 2024-01-05 Alex Coplan <alex.coplan@arm.com>
3146 PR target/113217
3147 * config/aarch64/aarch64-ldp-fusion.cc
3148 (ldp_bb_info::try_fuse_pair): If the second access can throw,
3149 narrow the move range to exactly that insn.
3151 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
3153 * asan.cc (asan_function_start): Drop switch_to_section ().
3154 (asan_emit_stack_protection): Set .LASANPC alignment.
3155 * config/i386/i386.cc: Use assemble_function_label_raw ()
3156 instead of ASM_OUTPUT_LABEL ().
3157 * config/s390/s390.cc (s390_asm_output_function_label):
3158 Likewise.
3159 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
3160 * final.cc (final_start_function_1): Drop
3161 asan_function_start ().
3162 * output.h (assemble_function_label_raw): New function.
3163 * varasm.cc (assemble_function_label_raw): Likewise.
3165 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
3167 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
3168 Use ASM_OUTPUT_FUNCTION_LABEL ().
3169 * config/alpha/alpha.cc (alpha_start_function): Likewise.
3170 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3171 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
3172 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3173 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3174 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
3175 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3176 * config/ia64/ia64.cc (ia64_start_function): Likewise.
3177 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
3178 Likewise.
3179 * config/microblaze/microblaze.cc (microblaze_function_prologue):
3180 Likewise.
3181 * config/mips/mips.cc (mips_start_unique_function): Return the
3182 tree.
3183 (mips_start_function_definition): Use
3184 ASM_OUTPUT_FUNCTION_LABEL ().
3185 (mips_finish_stub): Pass the tree to
3186 mips_start_function_definition ().
3187 (mips16_build_function_stub): Likewise.
3188 (mips16_build_call_stub): Likewise.
3189 (mips_output_function_prologue): Likewise.
3190 * config/pa/pa.cc (pa_output_function_label): Use
3191 ASM_OUTPUT_FUNCTION_LABEL ().
3192 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
3193 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
3194 Likewise.
3195 (rs6000_xcoff_declare_function_name): Likewise.
3197 2024-01-05 Jakub Jelinek <jakub@redhat.com>
3199 PR tree-optimization/113201
3200 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
3201 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
3203 2024-01-05 Jakub Jelinek <jakub@redhat.com>
3205 PR tree-optimization/90693
3206 * tree-ssa-math-opts.cc (match_single_bit_test): If
3207 tree_expr_nonzero_p (arg), remember it in the second argument to
3208 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
3209 arg ^ (arg - 1) > arg - 1.
3210 * internal-fn.cc (expand_POPCOUNT): If second argument to
3211 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
3212 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
3214 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
3216 * config/riscv/riscv-v.cc (expand_load_store):
3217 Remove `value`.
3218 (expand_cond_len_op): Ditto.
3219 (expand_gather_scatter): Ditto.
3220 (expand_lanes_load_store): Ditto.
3221 (expand_fold_extract_last): Ditto.
3223 2024-01-05 Pan Li <pan2.li@intel.com>
3225 Revert:
3226 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
3228 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
3229 Add new function_base for crypto vector.
3230 (class bitmanip): Ditto.
3231 (class b_reverse):Ditto.
3232 (class vwsll): Ditto.
3233 (class clmul): Ditto.
3234 (class vg_nhab): Ditto.
3235 (class crypto_vv):Ditto.
3236 (class crypto_vi):Ditto.
3237 (class vaeskf2_vsm3c):Ditto.
3238 (class vsm3me): Ditto.
3239 (BASE): Add BASE declaration for crypto vector.
3240 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
3241 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
3242 Add crypto vector intrinsic definition.
3243 (vbrev): Ditto.
3244 (vclz): Ditto.
3245 (vctz): Ditto.
3246 (vwsll): Ditto.
3247 (vandn): Ditto.
3248 (vbrev8): Ditto.
3249 (vrev8): Ditto.
3250 (vrol): Ditto.
3251 (vror): Ditto.
3252 (vclmul): Ditto.
3253 (vclmulh): Ditto.
3254 (vghsh): Ditto.
3255 (vgmul): Ditto.
3256 (vaesef): Ditto.
3257 (vaesem): Ditto.
3258 (vaesdf): Ditto.
3259 (vaesdm): Ditto.
3260 (vaesz): Ditto.
3261 (vaeskf1): Ditto.
3262 (vaeskf2): Ditto.
3263 (vsha2ms): Ditto.
3264 (vsha2ch): Ditto.
3265 (vsha2cl): Ditto.
3266 (vsm4k): Ditto.
3267 (vsm4r): Ditto.
3268 (vsm3me): Ditto.
3269 (vsm3c): Ditto.
3270 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
3271 Add new function_shape for crypto vector.
3272 (struct crypto_vi_def): Ditto.
3273 (struct crypto_vv_no_op_type_def): Ditto.
3274 (SHAPE): Add SHAPE declaration of crypto vector.
3275 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
3276 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
3277 Add new data type for crypto vector.
3278 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3279 (vuint32mf2_t): Ditto.
3280 (vuint32m1_t): Ditto.
3281 (vuint32m2_t): Ditto.
3282 (vuint32m4_t): Ditto.
3283 (vuint32m8_t): Ditto.
3284 (vuint64m1_t): Ditto.
3285 (vuint64m2_t): Ditto.
3286 (vuint64m4_t): Ditto.
3287 (vuint64m8_t): Ditto.
3288 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
3289 Add new data struct for crypto vector.
3290 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3291 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
3292 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
3294 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
3296 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
3297 Add new function_base for crypto vector.
3298 (class bitmanip): Ditto.
3299 (class b_reverse):Ditto.
3300 (class vwsll): Ditto.
3301 (class clmul): Ditto.
3302 (class vg_nhab): Ditto.
3303 (class crypto_vv):Ditto.
3304 (class crypto_vi):Ditto.
3305 (class vaeskf2_vsm3c):Ditto.
3306 (class vsm3me): Ditto.
3307 (BASE): Add BASE declaration for crypto vector.
3308 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
3309 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
3310 Add crypto vector intrinsic definition.
3311 (vbrev): Ditto.
3312 (vclz): Ditto.
3313 (vctz): Ditto.
3314 (vwsll): Ditto.
3315 (vandn): Ditto.
3316 (vbrev8): Ditto.
3317 (vrev8): Ditto.
3318 (vrol): Ditto.
3319 (vror): Ditto.
3320 (vclmul): Ditto.
3321 (vclmulh): Ditto.
3322 (vghsh): Ditto.
3323 (vgmul): Ditto.
3324 (vaesef): Ditto.
3325 (vaesem): Ditto.
3326 (vaesdf): Ditto.
3327 (vaesdm): Ditto.
3328 (vaesz): Ditto.
3329 (vaeskf1): Ditto.
3330 (vaeskf2): Ditto.
3331 (vsha2ms): Ditto.
3332 (vsha2ch): Ditto.
3333 (vsha2cl): Ditto.
3334 (vsm4k): Ditto.
3335 (vsm4r): Ditto.
3336 (vsm3me): Ditto.
3337 (vsm3c): Ditto.
3338 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
3339 Add new function_shape for crypto vector.
3340 (struct crypto_vi_def): Ditto.
3341 (struct crypto_vv_no_op_type_def): Ditto.
3342 (SHAPE): Add SHAPE declaration of crypto vector.
3343 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
3344 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
3345 Add new data type for crypto vector.
3346 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3347 (vuint32mf2_t): Ditto.
3348 (vuint32m1_t): Ditto.
3349 (vuint32m2_t): Ditto.
3350 (vuint32m4_t): Ditto.
3351 (vuint32m8_t): Ditto.
3352 (vuint64m1_t): Ditto.
3353 (vuint64m2_t): Ditto.
3354 (vuint64m4_t): Ditto.
3355 (vuint64m8_t): Ditto.
3356 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
3357 Add new data struct for crypto vector.
3358 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3359 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
3360 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
3362 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3364 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
3366 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
3368 PR tree-optimization/113186
3369 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
3370 Match `^` with the `==` for 1bit integral types.
3371 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
3372 integral types.
3374 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3376 * toplev.cc (general_init): Pass lang_mask to urlifier.
3378 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3380 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
3381 param.
3382 (diagnostic_context::make_option_url): Update for lang_mask param.
3383 * gcc-urlifier.cc: Include "opts.h" and "options.h".
3384 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
3385 (gcc_urlifier::m_lang_mask): New field.
3386 (doc_urls): Make static.
3387 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
3388 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
3389 Look for an option by name before trying a binary search in
3390 doc_urls.
3391 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
3392 (gcc_urlifier::get_url_suffix_for_option): New.
3393 (make_gcc_urlifier): Add lang_mask param.
3394 (selftest::gcc_urlifier_cc_tests): Update for above changes.
3395 Verify that a URL is found for "-fpack-struct".
3396 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
3397 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
3398 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
3399 to make_gcc_urlifier.
3400 * opts-diagnostic.h (get_option_url): Add lang_mask param.
3401 * opts.cc (get_option_html_page): Remove special-casing for
3402 analyzer and LTO.
3403 (get_option_url_suffix): New.
3404 (get_option_url): Reimplement.
3405 (selftest::test_get_option_html_page): Rename to...
3406 (selftest::test_get_option_url_suffix): ...this and update for
3407 above changes.
3408 (selftest::opts_cc_tests): Update for renaming.
3409 * opts.h: Include "rich-location.h".
3410 (get_option_url_suffix): New decl.
3412 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3414 * Makefile.in (ALL_OPT_URL_FILES): New.
3415 (GCC_OBJS): Add options-urls.o.
3416 (OBJS): Likewise.
3417 (OBJS-libcommon): Likewise.
3418 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
3419 inputs to opt-gather.awk.
3420 (options-urls.cc): New Makefile target.
3421 * opt-functions.awk (url_suffix): New function.
3422 (lang_url_suffix): New function.
3423 * options-urls-cc-gen.awk: New file.
3424 * opts.h (get_opt_url_suffix): New decl.
3426 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3428 * params.opt.urls: New file, autogenerated by
3429 regenerate-opt-urls.py.
3431 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3433 * common.opt.urls: New file, autogenerated by
3434 regenerate-opt-urls.py.
3435 * config/aarch64/aarch64.opt.urls: Likewise.
3436 * config/alpha/alpha.opt.urls: Likewise.
3437 * config/alpha/elf.opt.urls: Likewise.
3438 * config/arc/arc-tables.opt.urls: Likewise.
3439 * config/arc/arc.opt.urls: Likewise.
3440 * config/arm/arm-tables.opt.urls: Likewise.
3441 * config/arm/arm.opt.urls: Likewise.
3442 * config/arm/vxworks.opt.urls: Likewise.
3443 * config/avr/avr.opt.urls: Likewise.
3444 * config/bpf/bpf.opt.urls: Likewise.
3445 * config/c6x/c6x-tables.opt.urls: Likewise.
3446 * config/c6x/c6x.opt.urls: Likewise.
3447 * config/cris/cris.opt.urls: Likewise.
3448 * config/cris/elf.opt.urls: Likewise.
3449 * config/csky/csky.opt.urls: Likewise.
3450 * config/csky/csky_tables.opt.urls: Likewise.
3451 * config/darwin.opt.urls: Likewise.
3452 * config/dragonfly.opt.urls: Likewise.
3453 * config/epiphany/epiphany.opt.urls: Likewise.
3454 * config/fr30/fr30.opt.urls: Likewise.
3455 * config/freebsd.opt.urls: Likewise.
3456 * config/frv/frv.opt.urls: Likewise.
3457 * config/ft32/ft32.opt.urls: Likewise.
3458 * config/fused-madd.opt.urls: Likewise.
3459 * config/g.opt.urls: Likewise.
3460 * config/gcn/gcn.opt.urls: Likewise.
3461 * config/gnu-user.opt.urls: Likewise.
3462 * config/h8300/h8300.opt.urls: Likewise.
3463 * config/hpux11.opt.urls: Likewise.
3464 * config/i386/cygming.opt.urls: Likewise.
3465 * config/i386/cygwin.opt.urls: Likewise.
3466 * config/i386/djgpp.opt.urls: Likewise.
3467 * config/i386/i386.opt.urls: Likewise.
3468 * config/i386/mingw-w64.opt.urls: Likewise.
3469 * config/i386/mingw.opt.urls: Likewise.
3470 * config/i386/nto.opt.urls: Likewise.
3471 * config/ia64/ia64.opt.urls: Likewise.
3472 * config/ia64/ilp32.opt.urls: Likewise.
3473 * config/ia64/vms.opt.urls: Likewise.
3474 * config/iq2000/iq2000.opt.urls: Likewise.
3475 * config/linux-android.opt.urls: Likewise.
3476 * config/linux.opt.urls: Likewise.
3477 * config/lm32/lm32.opt.urls: Likewise.
3478 * config/loongarch/loongarch.opt.urls: Likewise.
3479 * config/lynx.opt.urls: Likewise.
3480 * config/m32c/m32c.opt.urls: Likewise.
3481 * config/m32r/m32r.opt.urls: Likewise.
3482 * config/m68k/ieee.opt.urls: Likewise.
3483 * config/m68k/m68k-tables.opt.urls: Likewise.
3484 * config/m68k/m68k.opt.urls: Likewise.
3485 * config/m68k/uclinux.opt.urls: Likewise.
3486 * config/mcore/mcore.opt.urls: Likewise.
3487 * config/microblaze/microblaze.opt.urls: Likewise.
3488 * config/mips/mips-tables.opt.urls: Likewise.
3489 * config/mips/mips.opt.urls: Likewise.
3490 * config/mips/sde.opt.urls: Likewise.
3491 * config/mmix/mmix.opt.urls: Likewise.
3492 * config/mn10300/mn10300.opt.urls: Likewise.
3493 * config/moxie/moxie.opt.urls: Likewise.
3494 * config/msp430/msp430.opt.urls: Likewise.
3495 * config/nds32/nds32-elf.opt.urls: Likewise.
3496 * config/nds32/nds32-linux.opt.urls: Likewise.
3497 * config/nds32/nds32.opt.urls: Likewise.
3498 * config/netbsd-elf.opt.urls: Likewise.
3499 * config/netbsd.opt.urls: Likewise.
3500 * config/nios2/elf.opt.urls: Likewise.
3501 * config/nios2/nios2.opt.urls: Likewise.
3502 * config/nvptx/nvptx-gen.opt.urls: Likewise.
3503 * config/nvptx/nvptx.opt.urls: Likewise.
3504 * config/openbsd.opt.urls: Likewise.
3505 * config/or1k/elf.opt.urls: Likewise.
3506 * config/or1k/or1k.opt.urls: Likewise.
3507 * config/pa/pa-hpux.opt.urls: Likewise.
3508 * config/pa/pa-hpux1010.opt.urls: Likewise.
3509 * config/pa/pa-hpux1111.opt.urls: Likewise.
3510 * config/pa/pa-hpux1131.opt.urls: Likewise.
3511 * config/pa/pa.opt.urls: Likewise.
3512 * config/pa/pa64-hpux.opt.urls: Likewise.
3513 * config/pdp11/pdp11.opt.urls: Likewise.
3514 * config/pru/pru.opt.urls: Likewise.
3515 * config/riscv/riscv.opt.urls: Likewise.
3516 * config/rl78/rl78.opt.urls: Likewise.
3517 * config/rpath.opt.urls: Likewise.
3518 * config/rs6000/476.opt.urls: Likewise.
3519 * config/rs6000/aix64.opt.urls: Likewise.
3520 * config/rs6000/darwin.opt.urls: Likewise.
3521 * config/rs6000/linux64.opt.urls: Likewise.
3522 * config/rs6000/rs6000-tables.opt.urls: Likewise.
3523 * config/rs6000/rs6000.opt.urls: Likewise.
3524 * config/rs6000/sysv4.opt.urls: Likewise.
3525 * config/rtems.opt.urls: Likewise.
3526 * config/rx/elf.opt.urls: Likewise.
3527 * config/rx/rx.opt.urls: Likewise.
3528 * config/s390/s390.opt.urls: Likewise.
3529 * config/s390/tpf.opt.urls: Likewise.
3530 * config/sh/sh.opt.urls: Likewise.
3531 * config/sh/superh.opt.urls: Likewise.
3532 * config/sol2.opt.urls: Likewise.
3533 * config/sparc/long-double-switch.opt.urls: Likewise.
3534 * config/sparc/sparc.opt.urls: Likewise.
3535 * config/stormy16/stormy16.opt.urls: Likewise.
3536 * config/v850/v850.opt.urls: Likewise.
3537 * config/vax/elf.opt.urls: Likewise.
3538 * config/vax/vax.opt.urls: Likewise.
3539 * config/visium/visium.opt.urls: Likewise.
3540 * config/vms/vms.opt.urls: Likewise.
3541 * config/vxworks-smp.opt.urls: Likewise.
3542 * config/vxworks.opt.urls: Likewise.
3543 * config/xtensa/elf.opt.urls: Likewise.
3544 * config/xtensa/uclinux.opt.urls: Likewise.
3545 * config/xtensa/xtensa.opt.urls: Likewise.
3546 * config/bfin/bfin.opt.urls: New file.
3548 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3550 * Makefile.in (OPT_URLS_HTML_DEPS): New.
3551 (regenerate-opt-urls): New target.
3552 (regenerate-opt-urls-unit-test): New target.
3553 * doc/options.texi (Option properties): Add UrlSuffix and
3554 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
3555 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
3556 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
3557 and Makefile.in's OPT_URLS_HTML_DEPS.
3558 (Anatomy of a Target Back End): Add
3559 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
3560 * regenerate-opt-urls.py: New file.
3562 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3564 * diagnostic-format-sarif.cc
3565 (sarif_builder::make_logical_location_object): Convert to...
3566 (make_sarif_logical_location_object): ...this.
3567 (sarif_builder::set_any_logical_locs_arr): Update for above
3568 change.
3569 (sarif_builder::make_thread_flow_location_object): Call
3570 maybe_add_sarif_properties on each diagnostic_event.
3571 * diagnostic-format-sarif.h (class logical_location): New forward
3572 decl.
3573 (make_sarif_logical_location_object): New decl.
3574 * diagnostic-path.h (class sarif_object): New forward decl.
3575 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
3577 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
3578 Patrick Lin <patrick@andestech.com>
3579 Rufus Chen <rufus@andestech.com>
3580 Monk Chiang <monk.chiang@sifive.com>
3582 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
3583 with Nan-boxing value.
3584 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
3586 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
3587 Jeff Law <jlaw@ventanamicro.com>
3589 PR rtl-optimization/104914
3590 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
3591 a sign or zero extension is only required if the modified field
3592 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
3593 targets, don't refer to the temporarily incorrectly extended value
3594 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
3596 2024-01-04 Pan Li <pan2.li@intel.com>
3598 Revert:
3599 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3601 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
3603 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3605 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
3607 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
3609 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
3610 offset of fcsr.
3612 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3614 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
3615 (compute_nregs_for_mode): Refine LMUL.
3616 (max_number_of_live_regs): Ditto.
3617 (compute_estimated_lmul): Ditto.
3618 (has_unexpected_spills_p): Ditto.
3620 2024-01-04 Li Wei <liwei@loongson.cn>
3622 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
3623 Remove useless forward declaration.
3624 (loongarch_is_even_extraction): Remove useless forward declaration.
3625 (loongarch_try_expand_lsx_vshuf_const): Removed.
3626 (loongarch_expand_vec_perm_const_1): Merged.
3627 (loongarch_is_double_duplicate): Removed.
3628 (loongarch_is_center_extraction): Ditto.
3629 (loongarch_is_reversing_permutation): Ditto.
3630 (loongarch_is_di_misalign_extract): Ditto.
3631 (loongarch_is_si_misalign_extract): Ditto.
3632 (loongarch_is_lasx_lowpart_extract): Ditto.
3633 (loongarch_is_op_reverse_perm): Ditto.
3634 (loongarch_is_single_op_perm): Ditto.
3635 (loongarch_is_divisible_perm): Ditto.
3636 (loongarch_is_triple_stride_extract): Ditto.
3637 (loongarch_expand_vec_perm_const_2): Merged.
3638 (loongarch_expand_vec_perm_const): New.
3639 (loongarch_vectorize_vec_perm_const): Adjust.
3641 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
3643 * omp-general.cc: Fix comment typos and misplaced/confusing
3644 comments. Delete redundant include of omp-general.h.
3646 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
3648 PR rtl-optimization/104914
3649 * config/mips/mips.md (insqisi_extended): New patterns.
3650 (inshisi_extended): Ditto.
3652 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
3654 * config/mips/mips.cc (mips_insn_cost): New function.
3656 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
3658 * config/mips/mips.md (perf_ratio): New attribute.
3660 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3662 PR target/113206
3663 PR target/113209
3664 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
3665 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
3666 blocks belong to infinite loop.
3667 (pre_vsetvl::emit_vsetvl): Remove fake edges.
3668 * config/riscv/t-riscv: Add a new include file.
3670 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3672 * config/riscv/vector.md: Fix indent.
3674 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3676 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
3677 OMP_CLAUSE__SIMDUID_.
3678 * tree.cc (omp_clause_num_ops): Update position of entry for
3679 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
3680 (omp_clause_code_name): Likewise.
3682 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3684 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
3685 printing of FUNC_MAP/IND_FUNC_MAP labels.
3687 2024-01-03 Jakub Jelinek <jakub@redhat.com>
3689 * gcc.cc (process_command): Update copyright notice dates.
3690 * gcov-dump.cc (print_version): Ditto.
3691 * gcov.cc (print_version): Ditto.
3692 * gcov-tool.cc (print_version): Ditto.
3693 * gengtype.cc (create_file): Ditto.
3694 * doc/cpp.texi: Bump @copying's copyright year.
3695 * doc/cppinternals.texi: Ditto.
3696 * doc/gcc.texi: Ditto.
3697 * doc/gccint.texi: Ditto.
3698 * doc/gcov.texi: Ditto.
3699 * doc/install.texi: Ditto.
3700 * doc/invoke.texi: Ditto.
3702 2024-01-03 Xi Ruoyao <xry111@xry111.site>
3704 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
3705 (fmin<mode>3): Likewise.
3706 (reduc_fmax_scal_<mode>3): New define_expand.
3707 (reduc_fmin_scal_<mode>3): Likewise.
3709 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3711 PR target/113112
3712 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
3713 (max_number_of_live_regs): Ditto.
3714 (has_unexpected_spills_p): Ditto.
3716 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3717 Jin Ma <jinma@linux.alibaba.com>
3718 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3719 Christoph Müllner <christoph.muellner@vrull.eu>
3721 * config/riscv/vector.md:
3722 Use vector_length_operand for vsetvl patterns.
3724 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3726 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
3727 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
3729 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
3731 * config/aarch64/aarch64-tuning-flags.def
3732 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
3733 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
3734 * config/aarch64/aarch64.cc
3735 (aarch64_override_options_internal): Set
3736 param_fully_pipelined_fma according to tuning option.
3737 * config/aarch64/tuning_models/ampere1.h: Add
3738 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
3739 * config/aarch64/tuning_models/ampere1a.h: Likewise.
3740 * config/aarch64/tuning_models/ampere1b.h: Likewise.
3742 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
3744 * config/riscv/vector-crypto.md: Modify copyright year.
3746 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3748 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
3750 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
3752 * config.in: Regenerate.
3753 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
3754 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
3755 Added TLS Le Relax support.
3756 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
3757 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
3758 * configure: Regenerate.
3759 * configure.ac: Check if binutils supports TLS le relax.
3761 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
3763 * config/riscv/iterators.md: Add rotate insn name.
3764 * config/riscv/riscv.md: Add new insns name for crypto vector.
3765 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
3766 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
3767 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
3769 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3771 PR target/113112
3772 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
3773 pointer type liveness count.
3774 \f
3775 Copyright (C) 2024 Free Software Foundation, Inc.
3777 Copying and distribution of this file, with or without modification,
3778 are permitted in any medium without royalty provided the copyright
3779 notice and this notice are preserved.