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1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Configuration triples for ARM ports work as follows:
25 arm-*-*: little endian
26 armel-*-*: little endian
27 armeb-*-*: big endian
28 If a non-embedded environment (ie: "real" OS) is specified, `arm'
29 should default to that used by the OS.
30 */
55 #ifdef AOF_ASSEMBLER
57 #endif
59 #define TARGET_CPU_arm2 0x0000
60 #define TARGET_CPU_arm250 0x0000
61 #define TARGET_CPU_arm3 0x0000
62 #define TARGET_CPU_arm6 0x0001
63 #define TARGET_CPU_arm600 0x0001
64 #define TARGET_CPU_arm610 0x0002
65 #define TARGET_CPU_arm7 0x0001
66 #define TARGET_CPU_arm7m 0x0004
67 #define TARGET_CPU_arm7dm 0x0004
68 #define TARGET_CPU_arm7dmi 0x0004
69 #define TARGET_CPU_arm700 0x0001
70 #define TARGET_CPU_arm710 0x0002
71 #define TARGET_CPU_arm7100 0x0002
72 #define TARGET_CPU_arm7500 0x0002
73 #define TARGET_CPU_arm7500fe 0x1001
74 #define TARGET_CPU_arm7tdmi 0x0008
75 #define TARGET_CPU_arm8 0x0010
76 #define TARGET_CPU_arm810 0x0020
77 #define TARGET_CPU_strongarm 0x0040
78 #define TARGET_CPU_strongarm110 0x0040
79 /* Configure didn't specify */
80 #define TARGET_CPU_generic 0x8000
82 enum arm_cond_code
83 {
86 };
90 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
92 /* This is needed by the tail-calling peepholes */
95 \f
96 /* Just in case configure has failed to define anything. */
97 #ifndef TARGET_CPU_DEFAULT
98 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
99 #endif
101 /* If the configuration file doesn't specify the cpu, the subtarget may
102 override it. If it doesn't, then default to an ARM6. */
103 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
104 #undef TARGET_CPU_DEFAULT
105 #ifdef SUBTARGET_CPU_DEFAULT
106 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
107 #else
108 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
109 #endif
110 #endif
112 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
114 #else
115 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFUALT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
117 #else
118 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
120 #else
121 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi
123 #else
124 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
126 #else
127 Unrecognized value in TARGET_CPU_DEFAULT.
128 #endif
129 #endif
130 #endif
131 #endif
132 #endif
134 #ifndef CPP_PREDEFINES
136 #endif
141 %{m2:-D__arm2__ -D__ARM_ARCH_2__} \
142 %{m3:-D__arm2__ -D__ARM_ARCH_2__} \
143 %{m6:-D__arm6__ -D__ARM_ARCH_3__} \
144 %{mcpu=arm2:-D__ARM_ARCH_2__} \
145 %{mcpu=arm250:-D__ARM_ARCH_2__} \
146 %{mcpu=arm3:-D__ARM_ARCH_2__} \
147 %{mcpu=arm6:-D__ARM_ARCH_3__} \
148 %{mcpu=arm600:-D__ARM_ARCH_3__} \
149 %{mcpu=arm610:-D__ARM_ARCH_3__} \
150 %{mcpu=arm7:-D__ARM_ARCH_3__} \
151 %{mcpu=arm700:-D__ARM_ARCH_3__} \
152 %{mcpu=arm710:-D__ARM_ARCH_3__} \
153 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
154 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
155 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
156 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
157 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
158 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
159 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
160 %{mcpu=arm8:-D__ARM_ARCH_4__} \
161 %{mcpu=arm810:-D__ARM_ARCH_4__} \
162 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
163 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
164 %{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}} \
165 "
167 /* Define __APCS_26__ if the PC also contains the PSR */
168 /* This also examines deprecated -m[236] if neither of -mapcs-{26,32} is set,
169 ??? Delete this for 2.9. */
171 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
172 -D__APCS_32__} \
173 %{mapcs-26:-D__APCS_26__} \
174 %{!mapcs-32: %{!mapcs-26:%{m6:-D__APCS_32__} %{m2:-D__APCS_26__} \
175 %{m3:-D__APCS_26__} %{!m6:%{!m3:%{!m2:%(cpp_apcs_pc_default)}}}}} \
176 "
181 %{msoft-float:\
182 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
183 -D__SOFTFP__} \
184 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
185 "
187 /* Default is hard float, which doesn't define anything */
191 %{mbig-endian: \
192 %{mlittle-endian: \
193 %e-mbig-endian and -mlittle-endian may not be used together} \
194 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} \
195 %{mle: \
196 %e-mbig-endian and -mle may not be used together} \
197 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
198 %{mbe: \
199 %{mlittle-endian: \
200 %e-mbe and -mlittle-endian may not be used together} \
201 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} \
202 %{mle: \
203 %e-mbe and -mle may not be used together} \
204 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
205 %{!mlittle-endian:%{!mbig-endian:%{!mbe:%{!mle:%(cpp_endian_default)}}}} \
206 "
208 /* Default is little endian, which doesn't define anything. */
211 /* Translate (for now) the old -m[236] option into the appropriate -mcpu=...
212 and -mapcs-xx equivalents.
213 ??? Remove support for this style in 2.9.
214 Also handle -mbe and -mle by expanding them into big-endian and
215 little-endian. */
217 %{m2:-mcpu=arm2 -mapcs-26} \
218 %{m3:-mcpu=arm3 -mapcs-26} \
219 %{m6:-mcpu=arm6 -mapcs-32} \
220 %{mbe:-mbig-endian} \
221 %{mle:-mlittle-endian} \
222 "
224 /* This macro defines names of additional specifications to put in the specs
225 that can be used in various specifications like CC1_SPEC. Its definition
226 is an initializer with a subgrouping for each command option.
228 Each subgrouping contains a string constant, that defines the
229 specification name, and a string constant that used by the GNU CC driver
230 program.
232 Do not define this macro if it does not need to do anything. */
233 #define EXTRA_SPECS \
242 SUBTARGET_EXTRA_SPECS
244 #define SUBTARGET_EXTRA_SPECS
246 \f
247 /* Run-time Target Specification. */
248 #ifndef TARGET_VERSION
249 #define TARGET_VERSION \
251 #endif
253 /* Run-time compilation parameters selecting different hardware subsets. */
256 /* These two are used by TARGET_OPTIONS, they are parsed in OVERRIDE_OPTIONS */
259 /* Nonzero if the function prologue (and epilogue) should obey
260 the ARM Procedure Call Standard. */
261 #define ARM_FLAG_APCS_FRAME (0x0001)
263 /* Nonzero if the function prologue should output the function name to enable
264 the post mortem debugger to print a backtrace (very useful on RISCOS,
265 unused on RISCiX). Specifying this flag also enables
266 -fno-omit-frame-pointer.
267 XXX Must still be implemented in the prologue. */
268 #define ARM_FLAG_POKE (0x0002)
270 /* Nonzero if floating point instructions are emulated by the FPE, in which
271 case instruction scheduling becomes very uninteresting. */
272 #define ARM_FLAG_FPE (0x0004)
274 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
275 of condition flags when returning from a branch & link (ie. a function) */
276 /* ********* DEPRECATED ******** */
277 #define ARM_FLAG_ARM6 (0x0008)
279 /* ********* DEPRECATED ******** */
280 #define ARM_FLAG_ARM3 (0x0010)
282 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
283 that assume restoration of the condition flags when returning from a
284 branch and link (ie a function). */
285 #define ARM_FLAG_APCS_32 (0x0020)
287 /* Nonzero if stack checking should be performed on entry to each function
288 which allocates temporary variables on the stack. */
289 #define ARM_FLAG_APCS_STACK (0x0040)
291 /* Nonzero if floating point parameters should be passed to functions in
292 floating point registers. */
293 #define ARM_FLAG_APCS_FLOAT (0x0080)
295 /* Nonzero if re-entrant, position independent code should be generated.
296 This is equivalent to -fpic. */
297 #define ARM_FLAG_APCS_REENT (0x0100)
299 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
300 loaded byte-at-a-time. */
301 #define ARM_FLAG_SHORT_BYTE (0x0200)
303 /* Nonzero if all floating point instructions are missing (and there is no
304 emulator either). Generate function calls for all ops in this case. */
305 #define ARM_FLAG_SOFT_FLOAT (0x0400)
307 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
308 #define ARM_FLAG_BIG_END (0x0800)
310 /* Nonzero if we should compile for Thumb interworking. */
311 #define ARM_FLAG_THUMB (0x1000)
313 /* Nonzero if we should have little-endian words even when compiling for
314 big-endian (for backwards compatibility with older versions of GCC). */
315 #define ARM_FLAG_LITTLE_WORDS (0x2000)
317 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
318 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
319 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
320 #define TARGET_6 (target_flags & ARM_FLAG_ARM6)
321 #define TARGET_3 (target_flags & ARM_FLAG_ARM3)
322 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
323 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
324 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
325 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
326 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
327 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
328 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
329 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
330 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
331 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
333 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
334 Bit 31 is reserved. See riscix.h. */
335 #ifndef SUBTARGET_SWITCHES
336 #define SUBTARGET_SWITCHES
337 #endif
339 #define TARGET_SWITCHES \
340 { \
368 SUBTARGET_SWITCHES \
370 }
372 #define TARGET_OPTIONS \
373 { \
377 }
379 /* arm_select[0] is reserved for the default cpu. */
380 struct arm_cpu_select
381 {
386 };
390 #ifndef PROCESSOR_DEFAULT
391 #define PROCESSOR_DEFAULT PROCESSOR_ARM2
392 #endif
394 #ifndef TARGET_CPU_DEFAULT
395 #define TARGET_CPU_DEFAULT ((char *) 0)
396 #endif
398 /* Which processor we are running on. */
399 enum processor_type
400 {
401 PROCESSOR_ARM2,
402 PROCESSOR_ARM3,
403 PROCESSOR_ARM6,
404 PROCESSOR_ARM7,
405 PROCESSOR_ARM8,
406 PROCESSOR_STARM
407 };
409 /* Recast the cpu class to be the cpu attribute. */
411 /* Recast the cpu class to be the cpu attribute. */
412 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
416 enum prog_mode_type
417 {
418 prog_mode26,
419 prog_mode32
420 };
422 /* Recast the program mode class to be the prog_mode attribute */
423 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
427 /* What sort of floating point unit do we have? Hardware or software.
428 If software, is it issue 2 or issue 3? */
429 enum floating_point_type
430 {
431 FP_HARD,
432 FP_SOFT2,
433 FP_SOFT3
434 };
436 /* Recast the floating point class to be the floating point attribute. */
437 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
441 /* Nonzero if the processor has a fast multiply insn, and one that does
442 a 64-bit multiply of two 32-bit values. */
445 /* Nonzero if this chip support the ARM Architecture 4 extensions */
448 #ifndef TARGET_DEFAULT
449 #define TARGET_DEFAULT 0
450 #endif
452 /* A particular target can define this to a particular cpu name, eg "arm710dmi"
453 and the code generated should then be appropriate for that processor. */
454 #ifndef ARM_CPU_NAME
455 #define ARM_CPU_NAME NULL
456 #endif
458 /* The frame pointer register used in gcc has nothing to do with debugging;
459 that is controlled by the APCS-FRAME option. */
460 /* Not fully implemented yet */
461 /* #define CAN_DEBUG_WITHOUT_FP 1 */
463 #define TARGET_MEM_FUNCTIONS 1
465 #define OVERRIDE_OPTIONS arm_override_options ()
466 \f
467 /* Target machine storage Layout. */
470 /* Define this macro if it is advisable to hold scalars in registers
471 in a wider mode than that declared by the program. In such cases,
472 the value is constrained to be within the bounds of the declared
473 type, but kept valid in the wider mode. The signedness of the
474 extension may differ from that of the type. */
476 /* It is far faster to zero extend chars than to sign extend them */
478 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
479 if (GET_MODE_CLASS (MODE) == MODE_INT \
480 && GET_MODE_SIZE (MODE) < 4) \
481 { \
482 if (MODE == QImode) \
483 UNSIGNEDP = 1; \
484 else if (MODE == HImode) \
485 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
486 (MODE) = SImode; \
487 }
489 /* Define for XFmode extended real floating point support.
490 This will automatically cause REAL_ARITHMETIC to be defined. */
491 /* For the ARM:
492 I think I have added all the code to make this work. Unfortunately,
493 early releases of the floating point emulation code on RISCiX used a
494 different format for extended precision numbers. On my RISCiX box there
495 is a bug somewhere which causes the machine to lock up when running enquire
496 with long doubles. There is the additional aspect that Norcroft C
497 treats long doubles as doubles and we ought to remain compatible.
498 Perhaps someone with an FPA coprocessor and not running RISCiX would like
499 to try this someday. */
500 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
502 /* Disable XFmode patterns in md file */
503 #define ENABLE_XF_PATTERNS 0
505 /* Define if you don't want extended real, but do want to use the
506 software floating point emulator for REAL_ARITHMETIC and
507 decimal <-> binary conversion. */
508 /* See comment above */
509 #define REAL_ARITHMETIC
511 /* Define this if most significant bit is lowest numbered
512 in instructions that operate on numbered bit-fields. */
513 #define BITS_BIG_ENDIAN 0
515 /* Define this if most significant byte of a word is the lowest numbered.
516 Most ARM processors are run in little endian mode, so that is the default.
517 If you want to have it run-time selectable, change the definition in a
518 cover file to be TARGET_BIG_ENDIAN. */
519 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
521 /* Define this if most significant word of a multiword number is the lowest
522 numbered.
523 This is always false, even when in big-endian mode. */
524 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
526 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
527 on processor pre-defineds when compiling libgcc2.c. */
528 #if defined(__ARMEB__) && !defined(__ARMWEL__)
529 #define LIBGCC2_WORDS_BIG_ENDIAN 1
530 #else
531 #define LIBGCC2_WORDS_BIG_ENDIAN 0
532 #endif
534 /* Define this if most significant word of doubles is the lowest numbered.
535 This is always true, even when in little-endian mode. */
536 #define FLOAT_WORDS_BIG_ENDIAN 1
538 /* Number of bits in an addressable storage unit */
539 #define BITS_PER_UNIT 8
541 #define BITS_PER_WORD 32
543 #define UNITS_PER_WORD 4
545 #define POINTER_SIZE 32
547 #define PARM_BOUNDARY 32
549 #define STACK_BOUNDARY 32
551 #define FUNCTION_BOUNDARY 32
553 #define EMPTY_FIELD_BOUNDARY 32
555 #define BIGGEST_ALIGNMENT 32
557 /* Make strings word-aligned so strcpy from constants will be faster. */
558 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
559 (TREE_CODE (EXP) == STRING_CST \
560 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
562 /* Every structures size must be a multiple of 32 bits. */
563 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
564 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
565 boundaries". */
566 #define STRUCTURE_SIZE_BOUNDARY 32
568 /* Non-zero if move instructions will actually fail to work
569 when given unaligned data. */
570 #define STRICT_ALIGNMENT 1
572 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
574 \f
575 /* Standard register usage. */
577 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
578 (S - saved over call).
580 r0 * argument word/integer result
581 r1-r3 argument word
583 r4-r8 S register variable
584 r9 S (rfp) register variable (real frame pointer)
586 r10 F S (sl) stack limit (not currently used)
587 r11 F S (fp) argument pointer
588 r12 (ip) temp workspace
589 r13 F S (sp) lower end of current stack frame
590 r14 (lr) link address/workspace
591 r15 F (pc) program counter
593 f0 floating point result
594 f1-f3 floating point scratch
596 f4-f7 S floating point variable
598 cc This is NOT a real register, but is used internally
599 to represent things that use or set the condition
600 codes.
601 sfp This isn't either. It is used during rtl generation
602 since the offset between the frame pointer and the
603 auto's isn't known until after register allocation.
604 afp Nor this, we only need this because of non-local
605 goto. Without it fp appears to be used and the
606 elimination code won't get rid of sfp. It tracks
607 fp exactly at all times.
609 *: See CONDITIONAL_REGISTER_USAGE */
611 /* The stack backtrace structure is as follows:
612 fp points to here: | save code pointer | [fp]
613 | return link value | [fp, #-4]
614 | return sp value | [fp, #-8]
615 | return fp value | [fp, #-12]
616 [| saved r10 value |]
617 [| saved r9 value |]
618 [| saved r8 value |]
619 [| saved r7 value |]
620 [| saved r6 value |]
621 [| saved r5 value |]
622 [| saved r4 value |]
623 [| saved r3 value |]
624 [| saved r2 value |]
625 [| saved r1 value |]
626 [| saved r0 value |]
627 [| saved f7 value |] three words
628 [| saved f6 value |] three words
629 [| saved f5 value |] three words
630 [| saved f4 value |] three words
631 r0-r3 are not normally saved in a C function. */
633 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
634 #define FIRST_PSEUDO_REGISTER 27
636 /* 1 for registers that have pervasive standard uses
637 and are not available for the register allocator. */
638 #define FIXED_REGISTERS \
639 { \
640 0,0,0,0,0,0,0,0, \
641 0,0,1,1,0,1,0,1, \
642 0,0,0,0,0,0,0,0, \
643 1,1,1 \
644 }
646 /* 1 for registers not available across function calls.
647 These must include the FIXED_REGISTERS and also any
648 registers that can be used without being saved.
649 The latter must include the registers where values are returned
650 and the register where structure-value addresses are passed.
651 Aside from that, you can include as many other registers as you like.
652 The CC is not preserved over function calls on the ARM 6, so it is
653 easier to assume this for all. SFP is preserved, since FP is. */
654 #define CALL_USED_REGISTERS \
655 { \
656 1,1,1,1,0,0,0,0, \
657 0,0,1,1,1,1,1,1, \
658 1,1,1,1,0,0,0,0, \
659 1,1,1 \
660 }
662 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
663 trampled. This effectively reduces the number of available registers by 1.
664 XXX It is a hack, I know.
665 XXX Is this still needed? */
666 #define CONDITIONAL_REGISTER_USAGE \
667 { \
668 if (obey_regdecls) \
669 fixed_regs[0] = 1; \
670 if (TARGET_SOFT_FLOAT) \
671 { \
672 int regno; \
673 for (regno = 16; regno < 24; ++regno) \
674 fixed_regs[regno] = call_used_regs[regno] = 1; \
675 } \
676 if (flag_pic) \
677 { \
678 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
679 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
680 } \
681 }
683 /* Return number of consecutive hard regs needed starting at reg REGNO
684 to hold something of mode MODE.
685 This is ordinarily the length in words of a value of mode MODE
686 but can be less for certain modes in special long registers.
688 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
689 mode. */
690 #define HARD_REGNO_NREGS(REGNO, MODE) \
691 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
692 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
693 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
695 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
696 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
697 regs holding FP. */
698 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
699 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
700 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
701 || REGNO == ARG_POINTER_REGNUM \
702 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
704 /* Value is 1 if it is a good idea to tie two pseudo registers
705 when one has mode MODE1 and one has mode MODE2.
706 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
707 for any hard reg, then this must be 0 for correct output. */
708 #define MODES_TIEABLE_P(MODE1, MODE2) \
709 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
711 /* Specify the registers used for certain standard purposes.
712 The values of these macros are register numbers. */
714 /* Define this if the program counter is overloaded on a register. */
715 #define PC_REGNUM 15
717 /* Register to use for pushing function arguments. */
718 #define STACK_POINTER_REGNUM 13
720 /* Base register for access to local variables of the function. */
721 #define FRAME_POINTER_REGNUM 25
723 /* Define this to be where the real frame pointer is if it is not possible to
724 work out the offset between the frame pointer and the automatic variables
725 until after register allocation has taken place. FRAME_POINTER_REGNUM
726 should point to a special register that we will make sure is eliminated. */
727 #define HARD_FRAME_POINTER_REGNUM 11
729 /* Value should be nonzero if functions must have frame pointers.
730 Zero means the frame pointer need not be set up (and parms may be accessed
731 via the stack pointer) in functions that seem suitable.
732 If we have to have a frame pointer we might as well make use of it.
733 APCS says that the frame pointer does not need to be pushed in leaf
734 functions. */
735 #define FRAME_POINTER_REQUIRED \
736 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
738 /* Base register for access to arguments of the function. */
739 #define ARG_POINTER_REGNUM 26
741 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
742 as an invisible last argument (possible since varargs don't exist in
743 Pascal), so the following is not true. */
744 #define STATIC_CHAIN_REGNUM 8
746 /* Register in which address to store a structure value
747 is passed to a function. */
748 #define STRUCT_VALUE_REGNUM 0
750 /* Internal, so that we don't need to refer to a raw number */
751 #define CC_REGNUM 24
753 /* The order in which register should be allocated. It is good to use ip
754 since no saving is required (though calls clobber it) and it never contains
755 function parameters. It is quite good to use lr since other calls may
756 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
757 least likely to contain a function parameter; in addition results are
758 returned in r0.
759 */
760 #define REG_ALLOC_ORDER \
761 { \
762 3, 2, 1, 0, 12, 14, 4, 5, \
763 6, 7, 8, 10, 9, 11, 13, 15, \
764 16, 17, 18, 19, 20, 21, 22, 23, \
765 24, 25 \
766 }
767 \f
768 /* Register and constant classes. */
770 /* Register classes: all ARM regs or all FPU regs---simple! */
771 enum reg_class
772 {
773 NO_REGS,
774 FPU_REGS,
775 GENERAL_REGS,
776 ALL_REGS,
777 LIM_REG_CLASSES
778 };
780 #define N_REG_CLASSES (int) LIM_REG_CLASSES
782 /* Give names of register classes as strings for dump file. */
783 #define REG_CLASS_NAMES \
784 { \
789 }
791 /* Define which registers fit in which classes.
792 This is an initializer for a vector of HARD_REG_SET
793 of length N_REG_CLASSES. */
794 #define REG_CLASS_CONTENTS \
795 { \
800 }
802 /* The same information, inverted:
803 Return the class number of the smallest class containing
804 reg number REGNO. This could be a conditional expression
805 or could index an array. */
806 #define REGNO_REG_CLASS(REGNO) \
807 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
808 || REGNO == ARG_POINTER_REGNUM) \
809 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
810 ? NO_REGS : FPU_REGS)
812 /* The class value for index registers, and the one for base regs. */
813 #define INDEX_REG_CLASS GENERAL_REGS
814 #define BASE_REG_CLASS GENERAL_REGS
816 /* Get reg_class from a letter such as appears in the machine description.
817 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
818 #define REG_CLASS_FROM_LETTER(C) \
821 /* The letters I, J, K, L and M in a register constraint string
822 can be used to stand for particular ranges of immediate operands.
823 This macro defines what the ranges are.
824 C is the letter, and VALUE is a constant value.
825 Return 1 if VALUE is in the range specified by C.
826 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
827 J: valid indexing constants.
828 K: ~value ok in rhs argument of data operand.
829 L: -value ok in rhs argument of data operand.
830 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
831 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
837 || (((VALUE) & ((VALUE) - 1)) == 0)) \
838 : 0)
840 /* For the ARM, `Q' means that this is a memory operand that is just
841 an offset from a register.
842 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
843 address. This means that the symbol is in the text segment and can be
844 accessed without using a load. */
846 #define EXTRA_CONSTRAINT(OP, C) \
849 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
850 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
852 : 0)
854 /* Constant letter 'G' for the FPU immediate constants.
855 'H' means the same constant negated. */
856 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
860 /* Given an rtx X being reloaded into a reg required to be
861 in class CLASS, return the class of reg to actually use.
862 In general this is just CLASS; but on some machines
863 in some cases it is preferable to use a more restrictive class. */
864 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
866 /* Return the register class of a scratch register needed to copy IN into
867 or out of a register in CLASS in MODE. If it can be done directly,
868 NO_REGS is returned. */
869 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
870 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
871 ? GENERAL_REGS : NO_REGS)
873 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
874 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
875 (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \
876 ? GENERAL_REGS : NO_REGS)
878 /* Return the maximum number of consecutive registers
879 needed to represent mode MODE in a register of class CLASS.
880 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
881 #define CLASS_MAX_NREGS(CLASS, MODE) \
882 ((CLASS) == FPU_REGS ? 1 \
883 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
885 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
886 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
887 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
888 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
889 ? 20 : 2)
890 \f
891 /* Stack layout; function entry, exit and calling. */
893 /* Define this if pushing a word on the stack
894 makes the stack pointer a smaller address. */
895 #define STACK_GROWS_DOWNWARD 1
897 /* Define this if the nominal address of the stack frame
898 is at the high-address end of the local variables;
899 that is, each additional local variable allocated
900 goes at a more negative offset in the frame. */
901 #define FRAME_GROWS_DOWNWARD 1
903 /* Offset within stack frame to start allocating local variables at.
904 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
905 first local allocated. Otherwise, it is the offset to the BEGINNING
906 of the first local allocated. */
907 #define STARTING_FRAME_OFFSET 0
909 /* If we generate an insn to push BYTES bytes,
910 this says how many the stack pointer really advances by. */
911 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
913 /* Offset of first parameter from the argument pointer register value. */
914 #define FIRST_PARM_OFFSET(FNDECL) 4
916 /* Value is the number of byte of arguments automatically
917 popped when returning from a subroutine call.
918 FUNDECL is the declaration node of the function (as a tree),
919 FUNTYPE is the data type of the function (as a tree),
920 or for a library call it is an identifier node for the subroutine name.
921 SIZE is the number of bytes of arguments passed on the stack.
923 On the ARM, the caller does not pop any of its arguments that were passed
924 on the stack. */
925 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
927 /* Define how to find the value returned by a function.
928 VALTYPE is the data type of the value (as a tree).
929 If the precise function being called is known, FUNC is its FUNCTION_DECL;
930 otherwise, FUNC is 0. */
931 #define FUNCTION_VALUE(VALTYPE, FUNC) \
932 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
933 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
934 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
936 /* Define how to find the value returned by a library function
937 assuming the value has mode MODE. */
938 #define LIBCALL_VALUE(MODE) \
939 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
940 ? gen_rtx (REG, MODE, 16) \
941 : gen_rtx (REG, MODE, 0))
943 /* 1 if N is a possible register number for a function value.
944 On the ARM, only r0 and f0 can return results. */
945 #define FUNCTION_VALUE_REGNO_P(REGNO) \
946 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
948 /* How large values are returned */
949 /* A C expression which can inhibit the returning of certain function values
950 in registers, based on the type of value. */
951 #define RETURN_IN_MEMORY(TYPE) \
952 (TYPE_MODE ((TYPE)) == BLKmode || \
953 (AGGREGATE_TYPE_P ((TYPE)) && arm_return_in_memory ((TYPE))))
955 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
956 values must be in memory. On the ARM, they need only do so if larger
957 than a word, or if they contain elements offset from zero in the struct. */
958 #define DEFAULT_PCC_STRUCT_RETURN 0
960 /* Define where to put the arguments to a function.
961 Value is zero to push the argument on the stack,
962 or a hard register in which to store the argument.
964 MODE is the argument's machine mode.
965 TYPE is the data type of the argument (as a tree).
966 This is null for libcalls where that information may
967 not be available.
968 CUM is a variable of type CUMULATIVE_ARGS which gives info about
969 the preceding args and about the function being called.
970 NAMED is nonzero if this argument is a named parameter
971 (otherwise it is an extra parameter matching an ellipsis).
973 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
974 other arguments are passed on the stack. If (NAMED == 0) (which happens
975 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
976 passed in the stack (function_prologue will indeed make it pass in the
977 stack if necessary). */
978 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
979 ((NAMED) \
980 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
981 : 0)
983 /* For an arg passed partly in registers and partly in memory,
984 this is the number of registers used.
985 For args passed entirely in registers or entirely in memory, zero. */
986 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
987 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
988 ? GET_MODE_SIZE (MODE) \
989 : int_size_in_bytes (TYPE)) \
990 ? 4 - (CUM) / 4 : 0)
992 /* A C type for declaring a variable that is used as the first argument of
993 `FUNCTION_ARG' and other related values. For some target machines, the
994 type `int' suffices and can hold the number of bytes of argument so far.
996 On the ARM, this is the number of bytes of arguments scanned so far. */
997 #define CUMULATIVE_ARGS int
999 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1000 for a call to a function whose data type is FNTYPE.
1001 For a library call, FNTYPE is 0.
1002 On the ARM, the offset starts at 0. */
1003 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1004 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1006 /* Update the data in CUM to advance over an argument
1007 of mode MODE and data type TYPE.
1008 (TYPE is null for libcalls where that information may not be available.) */
1009 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1010 (CUM) += ((MODE) != BLKmode \
1011 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1012 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1014 /* 1 if N is a possible register number for function argument passing.
1015 On the ARM, r0-r3 are used to pass args. */
1016 #define FUNCTION_ARG_REGNO_P(REGNO) \
1017 ((REGNO) >= 0 && (REGNO) <= 3)
1019 /* Perform any actions needed for a function that is receiving a variable
1020 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1021 of the current parameter. PRETEND_SIZE is a variable that should be set to
1022 the amount of stack that must be pushed by the prolog to pretend that our
1023 caller pushed it.
1025 Normally, this macro will push all remaining incoming registers on the
1026 stack and set PRETEND_SIZE to the length of the registers pushed.
1028 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1029 named arg and all anonymous args onto the stack.
1030 XXX I know the prologue shouldn't be pushing registers, but it is faster
1031 that way. */
1032 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1033 { \
1034 extern int current_function_anonymous_args; \
1035 current_function_anonymous_args = 1; \
1036 if ((CUM) < 16) \
1037 (PRETEND_SIZE) = 16 - (CUM); \
1038 }
1040 /* Generate assembly output for the start of a function. */
1041 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1042 output_func_prologue ((STREAM), (SIZE))
1044 /* Call the function profiler with a given profile label. The Acorn compiler
1045 puts this BEFORE the prolog but gcc puts it afterwards. The ``mov ip,lr''
1046 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
1047 to mind about this! */
1048 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1049 { \
1053 }
1055 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1056 the stack pointer does not matter. The value is tested only in
1057 functions that have frame pointers.
1058 No definition is equivalent to always zero.
1060 On the ARM, the function epilogue recovers the stack pointer from the
1061 frame. */
1062 #define EXIT_IGNORE_STACK 1
1064 /* Generate the assembly code for function exit. */
1065 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1066 output_func_epilogue ((STREAM), (SIZE))
1068 /* Determine if the epilogue should be output as RTL.
1069 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1070 #define USE_RETURN_INSN use_return_insn ()
1072 /* Definitions for register eliminations.
1074 This is an array of structures. Each structure initializes one pair
1075 of eliminable registers. The "from" register number is given first,
1076 followed by "to". Eliminations of the same "from" register are listed
1077 in order of preference.
1079 We have two registers that can be eliminated on the ARM. First, the
1080 arg pointer register can often be eliminated in favor of the stack
1081 pointer register. Secondly, the pseudo frame pointer register can always
1082 be eliminated; it is replaced with either the stack or the real frame
1083 pointer. */
1085 #define ELIMINABLE_REGS \
1086 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1087 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1088 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1089 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1091 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1092 Frame pointer elimination is automatically handled.
1094 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1095 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1096 pointer, we must eliminate FRAME_POINTER_REGNUM into
1097 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1098 #define CAN_ELIMINATE(FROM, TO) \
1099 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1101 /* Define the offset between two registers, one to be eliminated, and the other
1102 its replacement, at the start of a routine. */
1103 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1104 { \
1105 int volatile_func = arm_volatile_func (); \
1106 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1107 (OFFSET) = 0; \
1108 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
1109 (OFFSET) = (get_frame_size () + 3 & ~3); \
1110 else \
1111 { \
1112 int regno; \
1113 int offset = 12; \
1114 int saved_hard_reg = 0; \
1115 \
1116 if (! volatile_func) \
1117 { \
1118 for (regno = 0; regno <= 10; regno++) \
1119 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1120 saved_hard_reg = 1, offset += 4; \
1121 for (regno = 16; regno <=23; regno++) \
1122 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1123 offset += 12; \
1124 } \
1125 if ((FROM) == FRAME_POINTER_REGNUM) \
1126 (OFFSET) = -offset; \
1127 else \
1128 { \
1129 if (! frame_pointer_needed) \
1130 offset -= 16; \
1131 if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \
1132 offset += 4; \
1133 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
1134 } \
1135 } \
1136 }
1138 /* Output assembler code for a block containing the constant parts
1139 of a trampoline, leaving space for the variable parts.
1141 On the ARM, (if r8 is the static chain regnum, and remembering that
1142 referencing pc adds an offset of 8) the trampoline looks like:
1143 ldr r8, [pc, #0]
1144 ldr pc, [pc]
1145 .word static chain value
1146 .word function's address
1147 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1148 #define TRAMPOLINE_TEMPLATE(FILE) \
1149 { \
1151 REGISTER_PREFIX, REGISTER_PREFIX); \
1153 REGISTER_PREFIX, REGISTER_PREFIX); \
1156 }
1158 /* Length in units of the trampoline for entering a nested function. */
1159 #define TRAMPOLINE_SIZE 16
1161 /* Alignment required for a trampoline in units. */
1162 #define TRAMPOLINE_ALIGN 4
1164 /* Emit RTL insns to initialize the variable parts of a trampoline.
1165 FNADDR is an RTX for the address of the function's pure code.
1166 CXT is an RTX for the static chain value for the function. */
1167 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1168 { \
1169 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
1170 (CXT)); \
1171 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
1172 (FNADDR)); \
1173 }
1175 \f
1176 /* Addressing modes, and classification of registers for them. */
1178 #define HAVE_POST_INCREMENT 1
1179 #define HAVE_PRE_INCREMENT 1
1180 #define HAVE_POST_DECREMENT 1
1181 #define HAVE_PRE_DECREMENT 1
1183 /* Macros to check register numbers against specific register classes. */
1185 /* These assume that REGNO is a hard or pseudo reg number.
1186 They give nonzero only if REGNO is a hard reg of the suitable class
1187 or a pseudo reg currently allocated to a suitable hard reg.
1188 Since they use reg_renumber, they are safe only once reg_renumber
1189 has been allocated, which happens in local-alloc.c.
1191 On the ARM, don't allow the pc to be used. */
1192 #define REGNO_OK_FOR_BASE_P(REGNO) \
1193 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1194 || (REGNO) == ARG_POINTER_REGNUM \
1195 || (unsigned) reg_renumber[(REGNO)] < 15 \
1196 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1197 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1198 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1199 REGNO_OK_FOR_BASE_P(REGNO)
1201 /* Maximum number of registers that can appear in a valid memory address.
1202 Shifts in addresses can't be by a register. */
1204 #define MAX_REGS_PER_ADDRESS 2
1206 /* Recognize any constant value that is a valid address. */
1207 /* XXX We can address any constant, eventually... */
1209 #ifdef AOF_ASSEMBLER
1211 #define CONSTANT_ADDRESS_P(X) \
1212 (GET_CODE (X) == SYMBOL_REF \
1213 && CONSTANT_POOL_ADDRESS_P (X))
1215 #else
1217 #define CONSTANT_ADDRESS_P(X) \
1218 (GET_CODE (X) == SYMBOL_REF \
1219 && (CONSTANT_POOL_ADDRESS_P (X) \
1220 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1224 /* Nonzero if the constant value X is a legitimate general operand.
1225 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1227 On the ARM, allow any integer (invalid ones are removed later by insn
1228 patterns), nice doubles and symbol_refs which refer to the function's
1229 constant pool XXX. */
1230 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1232 /* Symbols in the text segment can be accessed without indirecting via the
1233 constant pool; it may take an extra binary operation, but this is still
1234 faster than indirecting via memory. Don't do this when not optimizing,
1235 since we won't be calculating al of the offsets necessary to do this
1236 simplification. */
1237 /* This doesn't work with AOF syntax, since the string table may be in
1238 a different AREA. */
1239 #ifndef AOF_ASSEMBLER
1240 #define ENCODE_SECTION_INFO(decl) \
1241 { \
1242 if (optimize > 0 && TREE_CONSTANT (decl) \
1243 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1244 { \
1246 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1247 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1248 } \
1249 }
1250 #endif
1252 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1253 and check its validity for a certain class.
1254 We have two alternate definitions for each of them.
1255 The usual definition accepts all pseudo regs; the other rejects
1256 them unless they have been allocated suitable hard regs.
1257 The symbol REG_OK_STRICT causes the latter definition to be used. */
1258 #ifndef REG_OK_STRICT
1260 /* Nonzero if X is a hard reg that can be used as a base reg
1261 or if it is a pseudo reg. */
1262 #define REG_OK_FOR_BASE_P(X) \
1263 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1264 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1266 /* Nonzero if X is a hard reg that can be used as an index
1267 or if it is a pseudo reg. */
1268 #define REG_OK_FOR_INDEX_P(X) \
1269 REG_OK_FOR_BASE_P(X)
1271 #define REG_OK_FOR_PRE_POST_P(X) \
1272 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1273 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1275 #else
1277 /* Nonzero if X is a hard reg that can be used as a base reg. */
1278 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1280 /* Nonzero if X is a hard reg that can be used as an index. */
1281 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1283 #define REG_OK_FOR_PRE_POST_P(X) \
1284 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1285 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1286 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1287 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1289 #endif
1290 \f
1291 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1292 that is a valid memory address for an instruction.
1293 The MODE argument is the machine mode for the MEM expression
1294 that wants to use this address.
1296 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1297 #define BASE_REGISTER_RTX_P(X) \
1298 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1300 #define INDEX_REGISTER_RTX_P(X) \
1301 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1303 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1304 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1305 only be small constants. */
1306 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1307 do \
1308 { \
1309 HOST_WIDE_INT range; \
1310 enum rtx_code code = GET_CODE (INDEX); \
1311 \
1312 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1313 { \
1314 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1315 && INTVAL (INDEX) > -1024 \
1316 && (INTVAL (INDEX) & 3) == 0) \
1317 goto LABEL; \
1318 } \
1319 else \
1320 { \
1321 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1322 goto LABEL; \
1323 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1324 && (! arm_arch4 || (MODE) != HImode)) \
1325 { \
1326 rtx xiop0 = XEXP (INDEX, 0); \
1327 rtx xiop1 = XEXP (INDEX, 1); \
1328 if (INDEX_REGISTER_RTX_P (xiop0) \
1329 && power_of_two_operand (xiop1, SImode)) \
1330 goto LABEL; \
1331 if (INDEX_REGISTER_RTX_P (xiop1) \
1332 && power_of_two_operand (xiop0, SImode)) \
1333 goto LABEL; \
1334 } \
1335 if (GET_MODE_SIZE (MODE) <= 4 \
1336 && (code == LSHIFTRT || code == ASHIFTRT \
1337 || code == ASHIFT || code == ROTATERT) \
1338 && (! arm_arch4 || (MODE) != HImode)) \
1339 { \
1340 rtx op = XEXP (INDEX, 1); \
1341 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1342 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1343 && INTVAL (op) <= 31) \
1344 goto LABEL; \
1345 } \
1346 range = (MODE) == HImode ? (arm_arch4 ? 256 : 4095) : 4096; \
1347 if (code == CONST_INT && INTVAL (INDEX) < range \
1348 && INTVAL (INDEX) > -range) \
1349 goto LABEL; \
1350 } \
1351 } while (0)
1353 /* Jump to LABEL if X is a valid address RTX. This must also take
1354 REG_OK_STRICT into account when deciding about valid registers, but it uses
1355 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1356 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1357 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1358 refs must be forced though a static cell to ensure addressability. */
1359 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1360 { \
1361 if (BASE_REGISTER_RTX_P (X)) \
1362 goto LABEL; \
1363 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1364 && GET_CODE (XEXP (X, 0)) == REG \
1365 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1366 goto LABEL; \
1367 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1368 && (GET_CODE (X) == LABEL_REF \
1369 || (GET_CODE (X) == CONST \
1370 && GET_CODE (XEXP ((X), 0)) == PLUS \
1371 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1372 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1373 goto LABEL; \
1374 else if ((MODE) == TImode) \
1375 ; \
1376 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1377 { \
1378 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1379 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1380 { \
1381 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1382 if (val == 4 || val == -4 || val == -8) \
1383 goto LABEL; \
1384 } \
1385 } \
1386 else if (GET_CODE (X) == PLUS) \
1387 { \
1388 rtx xop0 = XEXP(X,0); \
1389 rtx xop1 = XEXP(X,1); \
1390 \
1391 if (BASE_REGISTER_RTX_P (xop0)) \
1392 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1393 else if (BASE_REGISTER_RTX_P (xop1)) \
1394 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1395 } \
1396 else if (GET_CODE (X) == MINUS) \
1397 { \
1398 rtx xop0 = XEXP (X,0); \
1399 rtx xop1 = XEXP (X,1); \
1400 \
1401 if (BASE_REGISTER_RTX_P (xop0)) \
1402 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1403 } \
1404 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1405 && GET_CODE (X) == SYMBOL_REF \
1406 && CONSTANT_POOL_ADDRESS_P (X)) \
1407 goto LABEL; \
1408 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1409 && (GET_MODE_SIZE (MODE) <= 4) \
1410 && GET_CODE (XEXP (X, 0)) == REG \
1411 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1412 goto LABEL; \
1413 }
1414 \f
1415 /* Try machine-dependent ways of modifying an illegitimate address
1416 to be legitimate. If we find one, return the new, valid address.
1417 This macro is used in only one place: `memory_address' in explow.c.
1419 OLDX is the address as it was before break_out_memory_refs was called.
1420 In some cases it is useful to look at this to decide what needs to be done.
1422 MODE and WIN are passed so that this macro can use
1423 GO_IF_LEGITIMATE_ADDRESS.
1425 It is always safe for this macro to do nothing. It exists to recognize
1426 opportunities to optimize the output.
1428 On the ARM, try to convert [REG, #BIGCONST]
1429 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1430 where VALIDCONST == 0 in case of TImode. */
1432 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1433 { \
1434 if (GET_CODE (X) == PLUS) \
1435 { \
1436 rtx xop0 = XEXP (X, 0); \
1437 rtx xop1 = XEXP (X, 1); \
1438 \
1439 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1440 xop0 = force_reg (SImode, xop0); \
1441 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1442 xop1 = force_reg (SImode, xop1); \
1443 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1444 { \
1445 HOST_WIDE_INT n, low_n; \
1446 rtx base_reg, val; \
1447 n = INTVAL (xop1); \
1448 \
1449 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1450 { \
1451 low_n = n & 0x0f; \
1452 n &= ~0x0f; \
1453 if (low_n > 4) \
1454 { \
1455 n += 16; \
1456 low_n -= 16; \
1457 } \
1458 } \
1459 else \
1460 { \
1461 low_n = ((MODE) == TImode ? 0 \
1462 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1463 n -= low_n; \
1464 } \
1465 base_reg = gen_reg_rtx (SImode); \
1466 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1467 GEN_INT (n)), NULL_RTX); \
1468 emit_move_insn (base_reg, val); \
1469 (X) = (low_n == 0 ? base_reg \
1470 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1471 } \
1472 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1473 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1474 } \
1475 else if (GET_CODE (X) == MINUS) \
1476 { \
1477 rtx xop0 = XEXP (X, 0); \
1478 rtx xop1 = XEXP (X, 1); \
1479 \
1480 if (CONSTANT_P (xop0)) \
1481 xop0 = force_reg (SImode, xop0); \
1482 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1483 xop1 = force_reg (SImode, xop1); \
1484 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1485 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1486 } \
1487 if (flag_pic) \
1488 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1489 if (memory_address_p (MODE, X)) \
1490 goto WIN; \
1491 }
1493 /* Go to LABEL if ADDR (a legitimate address expression)
1494 has an effect that depends on the machine mode it is used for. */
1495 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1496 { \
1497 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1498 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1499 goto LABEL; \
1500 }
1501 \f
1502 /* Specify the machine mode that this machine uses
1503 for the index in the tablejump instruction. */
1504 #define CASE_VECTOR_MODE SImode
1506 /* Define this if the tablejump instruction expects the table
1507 to contain offsets from the address of the table.
1508 Do not define this if the table should contain absolute addresses. */
1509 /* #define CASE_VECTOR_PC_RELATIVE */
1511 /* Specify the tree operation to be used to convert reals to integers. */
1512 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1514 /* This is the kind of divide that is easiest to do in the general case. */
1515 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1517 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1518 unsigned is probably best, but may break some code. */
1519 #ifndef DEFAULT_SIGNED_CHAR
1520 #define DEFAULT_SIGNED_CHAR 0
1521 #endif
1523 /* Don't cse the address of the function being compiled. */
1524 #define NO_RECURSIVE_FUNCTION_CSE 1
1526 /* Max number of bytes we can move from memory to memory
1527 in one reasonably fast instruction. */
1528 #define MOVE_MAX 4
1530 /* Define if operations between registers always perform the operation
1531 on the full register even if a narrower mode is specified. */
1532 #define WORD_REGISTER_OPERATIONS
1534 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1535 will either zero-extend or sign-extend. The value of this macro should
1536 be the code that says which one of the two operations is implicitly
1537 done, NIL if none. */
1538 #define LOAD_EXTEND_OP(MODE) \
1539 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1540 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1542 /* Define this if zero-extension is slow (more than one real instruction).
1543 On the ARM, it is more than one instruction only if not fetching from
1544 memory. */
1545 /* #define SLOW_ZERO_EXTEND */
1547 /* Nonzero if access to memory by bytes is slow and undesirable. */
1548 #define SLOW_BYTE_ACCESS 0
1550 /* Immediate shift counts are truncated by the output routines (or was it
1551 the assembler?). Shift counts in a register are truncated by ARM. Note
1552 that the native compiler puts too large (> 32) immediate shift counts
1553 into a register and shifts by the register, letting the ARM decide what
1554 to do instead of doing that itself. */
1555 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1556 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1557 On the arm, Y in a register is used modulo 256 for the shift. Only for
1558 rotates is modulo 32 used. */
1559 /* #define SHIFT_COUNT_TRUNCATED 1 */
1561 /* All integers have the same format so truncation is easy. */
1562 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1564 /* Calling from registers is a massive pain. */
1565 #define NO_FUNCTION_CSE 1
1567 /* Chars and shorts should be passed as ints. */
1568 #define PROMOTE_PROTOTYPES 1
1570 /* The machine modes of pointers and functions */
1571 #define Pmode SImode
1572 #define FUNCTION_MODE Pmode
1574 /* The structure type of the machine dependent info field of insns
1575 No uses for this yet. */
1576 /* #define INSN_MACHINE_INFO struct machine_info */
1578 /* The relative costs of various types of constants. Note that cse.c defines
1579 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1580 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1581 case CONST_INT: \
1582 if (const_ok_for_arm (INTVAL (RTX))) \
1583 return (OUTER_CODE) == SET ? 2 : -1; \
1584 else if (OUTER_CODE == AND \
1585 && const_ok_for_arm (~INTVAL (RTX))) \
1586 return -1; \
1587 else if ((OUTER_CODE == COMPARE \
1588 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1589 && const_ok_for_arm (-INTVAL (RTX))) \
1590 return -1; \
1591 else \
1592 return 5; \
1593 case CONST: \
1594 case LABEL_REF: \
1595 case SYMBOL_REF: \
1596 return 6; \
1597 case CONST_DOUBLE: \
1598 if (const_double_rtx_ok_for_fpu (RTX)) \
1599 return (OUTER_CODE) == SET ? 2 : -1; \
1600 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1601 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1602 return -1; \
1603 return(7);
1605 #define ARM_FRAME_RTX(X) \
1606 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1607 || (X) == arg_pointer_rtx)
1609 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1610 default: \
1611 return arm_rtx_costs (X, CODE, OUTER_CODE);
1613 /* Moves to and from memory are quite expensive */
1614 #define MEMORY_MOVE_COST(MODE) 10
1616 /* All address computations that can be done are free, but rtx cost returns
1617 the same for practically all of them. So we weight the different types
1618 of address here in the order (most pref first):
1619 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1620 #define ADDRESS_COST(X) \
1621 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1622 || GET_CODE (X) == SYMBOL_REF) \
1623 ? 0 \
1624 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1625 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1626 ? 10 \
1627 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1628 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1633 ? 1 : 0)) \
1634 : 4)))))
1638 /* Try to generate sequences that don't involve branches, we can then use
1639 conditional instructions */
1640 #define BRANCH_COST 4
1642 /* A C statement to update the variable COST based on the relationship
1643 between INSN that is dependent on DEP through dependence LINK. */
1644 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1645 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1646 \f
1647 /* Position Independent Code. */
1648 /* We decide which register to use based on the compilation options and
1649 the assembler in use; this is more general than the APCS restriction of
1650 using sb (r9) all the time. */
1653 /* The register number of the register used to address a table of static
1654 data addresses in memory. */
1655 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1657 #define FINALIZE_PIC arm_finalize_pic ()
1659 #define LEGITIMATE_PIC_OPERAND_P(X) (! symbol_mentioned_p (X))
1662 \f
1663 /* Condition code information. */
1664 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1665 return the mode to be used for the comparison.
1666 CCFPEmode should be used with floating inequalities,
1667 CCFPmode should be used with floating equalities.
1668 CC_NOOVmode should be used with SImode integer equalities.
1669 CC_Zmode should be used if only the Z flag is set correctly
1670 CCmode should be used otherwise. */
1672 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1673 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1674 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1675 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1682 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1684 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1687 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1688 do \
1689 { \
1690 if (GET_CODE (OP1) == CONST_INT \
1691 && ! (const_ok_for_arm (INTVAL (OP1)) \
1692 || (const_ok_for_arm (- INTVAL (OP1))))) \
1693 { \
1694 rtx const_op = OP1; \
1695 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1696 } \
1697 } while (0)
1699 #define STORE_FLAG_VALUE 1
1701 /* Define the information needed to generate branch insns. This is
1702 stored from the compare operation. Note that we can't use "rtx" here
1703 since it hasn't been defined! */
1708 /* Define the codes that are matched by predicates in arm.c */
1709 #define PREDICATE_CODES \
1734 \f
1736 /* Gcc puts the pool in the wrong place for ARM, since we can only
1737 load addresses a limited distance around the pc. We do some
1738 special munging to move the constant pool values to the correct
1739 point in the code. */
1740 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1742 /* The pool is empty, since we have moved everything into the code. */
1743 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1744 goto JUMPTO
1746 /* Output an internal label definition. */
1747 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1748 do \
1749 { \
1750 char *s = (char *) alloca (40 + strlen (PREFIX)); \
1751 extern int arm_target_label, arm_ccfsm_state; \
1752 extern rtx arm_target_insn; \
1753 \
1754 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1756 { \
1757 arm_ccfsm_state = 0; \
1758 arm_target_insn = NULL; \
1759 } \
1760 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1761 arm_asm_output_label (STREAM, s); \
1762 } while (0)
1764 /* Output a label definition. */
1765 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1766 arm_asm_output_label ((STREAM), (NAME))
1768 /* Output a push or a pop instruction (only used when profiling). */
1769 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1771 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
1773 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1775 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
1777 /* Target characters. */
1778 #define TARGET_BELL 007
1779 #define TARGET_BS 010
1780 #define TARGET_TAB 011
1781 #define TARGET_NEWLINE 012
1782 #define TARGET_VT 013
1783 #define TARGET_FF 014
1784 #define TARGET_CR 015
1785 \f
1786 /* Only perform branch elimination (by making instructions conditional) if
1787 we're optimising. Otherwise it's of no use anyway. */
1788 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1789 if (optimize) \
1790 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1792 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1794 /* Output an operand of an instruction. */
1795 #define PRINT_OPERAND(STREAM, X, CODE) \
1796 arm_print_operand (STREAM, X, CODE)
1798 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1799 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1800 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1801 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1802 ? ((~ (HOST_WIDE_INT) 0) \
1803 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1804 : 0))))
1806 /* Output the address of an operand. */
1807 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1808 { \
1809 int is_minus = GET_CODE (X) == MINUS; \
1810 \
1811 if (GET_CODE (X) == REG) \
1813 reg_names[REGNO (X)]); \
1814 else if (GET_CODE (X) == PLUS || is_minus) \
1815 { \
1816 rtx base = XEXP (X, 0); \
1817 rtx index = XEXP (X, 1); \
1818 char *base_reg_name; \
1819 HOST_WIDE_INT offset = 0; \
1820 if (GET_CODE (base) != REG) \
1821 { \
1823 rtx temp = base; \
1824 base = index; \
1825 index = temp; \
1826 } \
1827 base_reg_name = reg_names[REGNO (base)]; \
1828 switch (GET_CODE (index)) \
1829 { \
1830 case CONST_INT: \
1831 offset = INTVAL (index); \
1832 if (is_minus) \
1833 offset = -offset; \
1835 base_reg_name, offset); \
1836 break; \
1837 \
1838 case REG: \
1841 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1842 break; \
1843 \
1844 case MULT: \
1845 case ASHIFTRT: \
1846 case LSHIFTRT: \
1847 case ASHIFT: \
1848 case ROTATERT: \
1849 { \
1852 reg_names[REGNO (XEXP (index, 0))]); \
1855 break; \
1856 } \
1857 \
1858 default: \
1859 abort(); \
1860 } \
1861 } \
1862 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1863 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1864 { \
1865 extern int output_memory_reference_mode; \
1866 \
1867 if (GET_CODE (XEXP (X, 0)) != REG) \
1868 abort (); \
1869 \
1870 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1872 reg_names[REGNO (XEXP (X, 0))], \
1874 GET_MODE_SIZE (output_memory_reference_mode)); \
1875 else \
1877 reg_names[REGNO (XEXP (X, 0))], \
1879 GET_MODE_SIZE (output_memory_reference_mode)); \
1880 } \
1881 else output_addr_const(STREAM, X); \
1882 }
1884 /* Handles PIC addr specially */
1885 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
1886 { \
1887 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
1888 { \
1889 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
1891 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
1893 } \
1894 else output_addr_const(STREAM, X); \
1895 }
1897 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1898 Used for C++ multiple inheritance. */
1899 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1900 do { \
1901 int mi_delta = (DELTA); \
1903 int shift = 0; \
1904 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
1905 ? 1 : 0); \
1906 if (mi_delta < 0) mi_delta = -mi_delta; \
1907 while (mi_delta != 0) \
1908 { \
1909 if (mi_delta & (3 << shift) == 0) \
1910 shift += 2; \
1911 else \
1912 { \
1914 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
1915 REGISTER_PREFIX, reg_names[this_regno], \
1916 mi_delta & (0xff << shift)); \
1917 mi_delta &= ~(0xff << shift); \
1918 shift += 8; \
1919 } \
1920 } \
1922 REGISTER_PREFIX); \
1923 ASM_OUTPUT_INT (FILE, XEXP (DECL_RTL (FUNCTION), 0)); \
1924 } while (0)
1926 /* A C expression whose value is RTL representing the value of the return
1927 address for the frame COUNT steps up from the current frame. */
1929 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1930 ((COUNT == 0) \
1931 ? gen_rtx (MEM, Pmode, plus_constant (FRAME, -4)) \
1932 : (rtx) 0)
1934 /* Used to mask out junk bits from the return address, such as
1935 processor state, interrupt status, condition codes and the like. */
1936 #define MASK_RETURN_ADDR \
1937 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
1938 in 26 bit mode, the condition codes must be masked out of the \
1939 return address. This does not apply to ARM6 and later processors \
1941 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))