| blob | b49da7bc489b870909450613aff926e5f29d8739 |
1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
5 ;; of Utah.
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; any later version.
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; This gcc Version 2 machine description is inspired by sparc.md and
24 ;; mips.md.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Uses of UNSPEC in this file:
30 (define_constants
31 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
32 (UNSPEC_GOTO 1) ; indirect_goto
33 (UNSPEC_DLTIND14R 2) ;
34 (UNSPEC_TP 3)
35 (UNSPEC_TLSGD 4)
36 (UNSPEC_TLSLDM 5)
37 (UNSPEC_TLSLDO 6)
38 (UNSPEC_TLSLDBASE 7)
39 (UNSPEC_TLSIE 8)
40 (UNSPEC_TLSLE 9)
41 (UNSPEC_TLSGD_PIC 10)
42 (UNSPEC_TLSLDM_PIC 11)
43 (UNSPEC_TLSIE_PIC 12)
44 ])
46 ;; UNSPEC_VOLATILE:
48 (define_constants
49 [(UNSPECV_BLOCKAGE 0) ; blockage
50 (UNSPECV_DCACHE 1) ; dcacheflush
51 (UNSPECV_ICACHE 2) ; icacheflush
52 (UNSPECV_OPC 3) ; outline_prologue_call
53 (UNSPECV_OEC 4) ; outline_epilogue_call
54 (UNSPECV_LONGJMP 5) ; builtin_longjmp
55 ])
57 ;; Maximum pc-relative branch offsets.
59 ;; These numbers are a bit smaller than the maximum allowable offsets
60 ;; so that a few instructions may be inserted before the actual branch.
62 (define_constants
63 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
64 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
65 ])
67 ;; Insn type. Used to default other attribute values.
69 ;; type "unary" insns have one input operand (1) and one output operand (0)
70 ;; type "binary" insns have two input operands (1,2) and one output (0)
72 (define_attr "type"
73 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
74 (const_string "binary"))
76 (define_attr "pa_combine_type"
77 "fmpy,faddsub,uncond_branch,addmove,none"
78 (const_string "none"))
80 ;; Processor type (for scheduling, not code generation) -- this attribute
81 ;; must exactly match the processor_type enumeration in pa.h.
82 ;;
83 ;; FIXME: Add 800 scheduling for completeness?
85 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
87 ;; Length (in # of bytes).
88 (define_attr "length" ""
89 (cond [(eq_attr "type" "load,fpload")
90 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
91 (const_int 8) (const_int 4))
93 (eq_attr "type" "store,fpstore")
94 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
95 (const_int 8) (const_int 4))
97 (eq_attr "type" "binary,shift,nullshift")
98 (if_then_else (match_operand 2 "arith_operand" "")
99 (const_int 4) (const_int 12))
101 (eq_attr "type" "move,unary,shift,nullshift")
102 (if_then_else (match_operand 1 "arith_operand" "")
103 (const_int 4) (const_int 8))]
105 (const_int 4)))
107 (define_asm_attributes
108 [(set_attr "length" "4")
109 (set_attr "type" "multi")])
111 ;; Attributes for instruction and branch scheduling
113 ;; For conditional branches.
114 (define_attr "in_branch_delay" "false,true"
115 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
116 (eq_attr "length" "4"))
117 (const_string "true")
118 (const_string "false")))
120 ;; Disallow instructions which use the FPU since they will tie up the FPU
121 ;; even if the instruction is nullified.
122 (define_attr "in_nullified_branch_delay" "false,true"
123 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
124 (eq_attr "length" "4"))
125 (const_string "true")
126 (const_string "false")))
128 ;; For calls and millicode calls. Allow unconditional branches in the
129 ;; delay slot.
130 (define_attr "in_call_delay" "false,true"
131 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
132 (eq_attr "length" "4"))
133 (const_string "true")
134 (eq_attr "type" "uncond_branch")
135 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
136 (const_int 0))
137 (const_string "true")
138 (const_string "false"))]
139 (const_string "false")))
142 ;; Call delay slot description.
143 (define_delay (eq_attr "type" "call")
144 [(eq_attr "in_call_delay" "true") (nil) (nil)])
146 ;; Millicode call delay slot description.
147 (define_delay (eq_attr "type" "milli")
148 [(eq_attr "in_call_delay" "true") (nil) (nil)])
150 ;; Return and other similar instructions.
151 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
152 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
154 ;; Floating point conditional branch delay slot description.
155 (define_delay (eq_attr "type" "fbranch")
156 [(eq_attr "in_branch_delay" "true")
157 (eq_attr "in_nullified_branch_delay" "true")
158 (nil)])
160 ;; Integer conditional branch delay slot description.
161 ;; Nullification of conditional branches on the PA is dependent on the
162 ;; direction of the branch. Forward branches nullify true and
163 ;; backward branches nullify false. If the direction is unknown
164 ;; then nullification is not allowed.
165 (define_delay (eq_attr "type" "cbranch")
166 [(eq_attr "in_branch_delay" "true")
167 (and (eq_attr "in_nullified_branch_delay" "true")
168 (attr_flag "forward"))
169 (and (eq_attr "in_nullified_branch_delay" "true")
170 (attr_flag "backward"))])
172 (define_delay (and (eq_attr "type" "uncond_branch")
173 (eq (symbol_ref "following_call (insn)")
174 (const_int 0)))
175 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
177 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
178 ;; load: 2, fpload: 3
179 ;; store, fpstore: 3, no D-cache operations should be scheduled.
181 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
182 ;; Timings:
183 ;; Instruction Time Unit Minimum Distance (unit contention)
184 ;; fcpy 3 ALU 2
185 ;; fabs 3 ALU 2
186 ;; fadd 3 ALU 2
187 ;; fsub 3 ALU 2
188 ;; fcmp 3 ALU 2
189 ;; fcnv 3 ALU 2
190 ;; fmpyadd 3 ALU,MPY 2
191 ;; fmpysub 3 ALU,MPY 2
192 ;; fmpycfxt 3 ALU,MPY 2
193 ;; fmpy 3 MPY 2
194 ;; fmpyi 3 MPY 2
195 ;; fdiv,sgl 10 MPY 10
196 ;; fdiv,dbl 12 MPY 12
197 ;; fsqrt,sgl 14 MPY 14
198 ;; fsqrt,dbl 18 MPY 18
199 ;;
200 ;; We don't model fmpyadd/fmpysub properly as those instructions
201 ;; keep both the FP ALU and MPY units busy. Given that these
202 ;; processors are obsolete, I'm not going to spend the time to
203 ;; model those instructions correctly.
205 (define_automaton "pa700")
206 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
208 (define_insn_reservation "W0" 4
209 (and (eq_attr "type" "fpcc")
210 (eq_attr "cpu" "700"))
211 "fpalu_700*2")
213 (define_insn_reservation "W1" 3
214 (and (eq_attr "type" "fpalu")
215 (eq_attr "cpu" "700"))
216 "fpalu_700*2")
218 (define_insn_reservation "W2" 3
219 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
220 (eq_attr "cpu" "700"))
221 "fpmpy_700*2")
223 (define_insn_reservation "W3" 10
224 (and (eq_attr "type" "fpdivsgl")
225 (eq_attr "cpu" "700"))
226 "fpmpy_700*10")
228 (define_insn_reservation "W4" 12
229 (and (eq_attr "type" "fpdivdbl")
230 (eq_attr "cpu" "700"))
231 "fpmpy_700*12")
233 (define_insn_reservation "W5" 14
234 (and (eq_attr "type" "fpsqrtsgl")
235 (eq_attr "cpu" "700"))
236 "fpmpy_700*14")
238 (define_insn_reservation "W6" 18
239 (and (eq_attr "type" "fpsqrtdbl")
240 (eq_attr "cpu" "700"))
241 "fpmpy_700*18")
243 (define_insn_reservation "W7" 2
244 (and (eq_attr "type" "load")
245 (eq_attr "cpu" "700"))
246 "mem_700")
248 (define_insn_reservation "W8" 2
249 (and (eq_attr "type" "fpload")
250 (eq_attr "cpu" "700"))
251 "mem_700")
253 (define_insn_reservation "W9" 3
254 (and (eq_attr "type" "store")
255 (eq_attr "cpu" "700"))
256 "mem_700*3")
258 (define_insn_reservation "W10" 3
259 (and (eq_attr "type" "fpstore")
260 (eq_attr "cpu" "700"))
261 "mem_700*3")
263 (define_insn_reservation "W11" 5
264 (and (eq_attr "type" "fpstore_load")
265 (eq_attr "cpu" "700"))
266 "mem_700*5")
268 (define_insn_reservation "W12" 6
269 (and (eq_attr "type" "store_fpload")
270 (eq_attr "cpu" "700"))
271 "mem_700*6")
273 (define_insn_reservation "W13" 1
274 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
275 (eq_attr "cpu" "700"))
276 "dummy_700")
278 ;; We have a bypass for all computations in the FP unit which feed an
279 ;; FP store as long as the sizes are the same.
280 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
281 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
282 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
283 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
284 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
286 ;; We have an "anti-bypass" for FP loads which feed an FP store.
287 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
289 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
290 ;; floating point computations with non-floating point computations (fp loads
291 ;; and stores are not fp computations).
292 ;;
293 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
294 ;; take two cycles, during which no Dcache operations should be scheduled.
295 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
296 ;; all have the same memory characteristics if one disregards cache misses.
297 ;;
298 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
299 ;; There's no value in modeling the ALU and MUL separately though
300 ;; since there can never be a functional unit conflict given the
301 ;; latency and issue rates for those units.
302 ;;
303 ;; Timings:
304 ;; Instruction Time Unit Minimum Distance (unit contention)
305 ;; fcpy 2 ALU 1
306 ;; fabs 2 ALU 1
307 ;; fadd 2 ALU 1
308 ;; fsub 2 ALU 1
309 ;; fcmp 2 ALU 1
310 ;; fcnv 2 ALU 1
311 ;; fmpyadd 2 ALU,MPY 1
312 ;; fmpysub 2 ALU,MPY 1
313 ;; fmpycfxt 2 ALU,MPY 1
314 ;; fmpy 2 MPY 1
315 ;; fmpyi 2 MPY 1
316 ;; fdiv,sgl 8 DIV 8
317 ;; fdiv,dbl 15 DIV 15
318 ;; fsqrt,sgl 8 DIV 8
319 ;; fsqrt,dbl 15 DIV 15
321 (define_automaton "pa7100")
322 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
324 (define_insn_reservation "X0" 2
325 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
326 (eq_attr "cpu" "7100"))
327 "f_7100,fpmac_7100")
329 (define_insn_reservation "X1" 8
330 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
331 (eq_attr "cpu" "7100"))
332 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
334 (define_insn_reservation "X2" 15
335 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
336 (eq_attr "cpu" "7100"))
337 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
339 (define_insn_reservation "X3" 2
340 (and (eq_attr "type" "load")
341 (eq_attr "cpu" "7100"))
342 "i_7100+mem_7100")
344 (define_insn_reservation "X4" 2
345 (and (eq_attr "type" "fpload")
346 (eq_attr "cpu" "7100"))
347 "i_7100+mem_7100")
349 (define_insn_reservation "X5" 2
350 (and (eq_attr "type" "store")
351 (eq_attr "cpu" "7100"))
352 "i_7100+mem_7100,mem_7100")
354 (define_insn_reservation "X6" 2
355 (and (eq_attr "type" "fpstore")
356 (eq_attr "cpu" "7100"))
357 "i_7100+mem_7100,mem_7100")
359 (define_insn_reservation "X7" 4
360 (and (eq_attr "type" "fpstore_load")
361 (eq_attr "cpu" "7100"))
362 "i_7100+mem_7100,mem_7100*3")
364 (define_insn_reservation "X8" 4
365 (and (eq_attr "type" "store_fpload")
366 (eq_attr "cpu" "7100"))
367 "i_7100+mem_7100,mem_7100*3")
369 (define_insn_reservation "X9" 1
370 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
371 (eq_attr "cpu" "7100"))
372 "i_7100")
374 ;; We have a bypass for all computations in the FP unit which feed an
375 ;; FP store as long as the sizes are the same.
376 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
377 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
378 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
380 ;; We have an "anti-bypass" for FP loads which feed an FP store.
381 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
383 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
384 ;; There's no value in modeling the ALU and MUL separately though
385 ;; since there can never be a functional unit conflict that
386 ;; can be avoided given the latency, issue rates and mandatory
387 ;; one cycle cpu-wide lock for a double precision fp multiply.
388 ;;
389 ;; Timings:
390 ;; Instruction Time Unit Minimum Distance (unit contention)
391 ;; fcpy 2 ALU 1
392 ;; fabs 2 ALU 1
393 ;; fadd 2 ALU 1
394 ;; fsub 2 ALU 1
395 ;; fcmp 2 ALU 1
396 ;; fcnv 2 ALU 1
397 ;; fmpyadd,sgl 2 ALU,MPY 1
398 ;; fmpyadd,dbl 3 ALU,MPY 2
399 ;; fmpysub,sgl 2 ALU,MPY 1
400 ;; fmpysub,dbl 3 ALU,MPY 2
401 ;; fmpycfxt,sgl 2 ALU,MPY 1
402 ;; fmpycfxt,dbl 3 ALU,MPY 2
403 ;; fmpy,sgl 2 MPY 1
404 ;; fmpy,dbl 3 MPY 2
405 ;; fmpyi 3 MPY 2
406 ;; fdiv,sgl 8 DIV 8
407 ;; fdiv,dbl 15 DIV 15
408 ;; fsqrt,sgl 8 DIV 8
409 ;; fsqrt,dbl 15 DIV 15
410 ;;
411 ;; The PA7200 is just like the PA7100LC except that there is
412 ;; no store-store penalty.
413 ;;
414 ;; The PA7300 is just like the PA7200 except that there is
415 ;; no store-load penalty.
416 ;;
417 ;; Note there are some aspects of the 7100LC we are not modeling
418 ;; at the moment. I'll be reviewing the 7100LC scheduling info
419 ;; shortly and updating this description.
420 ;;
421 ;; load-load pairs
422 ;; store-store pairs
423 ;; other issue modeling
425 (define_automaton "pa7100lc")
426 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
427 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
428 (define_cpu_unit "mem_7100lc" "pa7100lc")
430 ;; Double precision multiplies lock the entire CPU for one
431 ;; cycle. There is no way to avoid this lock and trying to
432 ;; schedule around the lock is pointless and thus there is no
433 ;; value in trying to model this lock.
434 ;;
435 ;; Not modeling the lock allows us to treat fp multiplies just
436 ;; like any other FP alu instruction. It allows for a smaller
437 ;; DFA and may reduce register pressure.
438 (define_insn_reservation "Y0" 2
439 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
440 (eq_attr "cpu" "7100LC,7200,7300"))
441 "f_7100lc,fpmac_7100lc")
443 ;; fp division and sqrt instructions lock the entire CPU for
444 ;; 7 cycles (single precision) or 14 cycles (double precision).
445 ;; There is no way to avoid this lock and trying to schedule
446 ;; around the lock is pointless and thus there is no value in
447 ;; trying to model this lock. Not modeling the lock allows
448 ;; for a smaller DFA and may reduce register pressure.
449 (define_insn_reservation "Y1" 1
450 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
451 (eq_attr "cpu" "7100LC,7200,7300"))
452 "f_7100lc")
454 (define_insn_reservation "Y2" 2
455 (and (eq_attr "type" "load")
456 (eq_attr "cpu" "7100LC,7200,7300"))
457 "i1_7100lc+mem_7100lc")
459 (define_insn_reservation "Y3" 2
460 (and (eq_attr "type" "fpload")
461 (eq_attr "cpu" "7100LC,7200,7300"))
462 "i1_7100lc+mem_7100lc")
464 (define_insn_reservation "Y4" 2
465 (and (eq_attr "type" "store")
466 (eq_attr "cpu" "7100LC"))
467 "i1_7100lc+mem_7100lc,mem_7100lc")
469 (define_insn_reservation "Y5" 2
470 (and (eq_attr "type" "fpstore")
471 (eq_attr "cpu" "7100LC"))
472 "i1_7100lc+mem_7100lc,mem_7100lc")
474 (define_insn_reservation "Y6" 4
475 (and (eq_attr "type" "fpstore_load")
476 (eq_attr "cpu" "7100LC"))
477 "i1_7100lc+mem_7100lc,mem_7100lc*3")
479 (define_insn_reservation "Y7" 4
480 (and (eq_attr "type" "store_fpload")
481 (eq_attr "cpu" "7100LC"))
482 "i1_7100lc+mem_7100lc,mem_7100lc*3")
484 (define_insn_reservation "Y8" 1
485 (and (eq_attr "type" "shift,nullshift")
486 (eq_attr "cpu" "7100LC,7200,7300"))
487 "i1_7100lc")
489 (define_insn_reservation "Y9" 1
490 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
491 (eq_attr "cpu" "7100LC,7200,7300"))
492 "(i0_7100lc|i1_7100lc)")
494 ;; The 7200 has a store-load penalty
495 (define_insn_reservation "Y10" 2
496 (and (eq_attr "type" "store")
497 (eq_attr "cpu" "7200"))
498 "i1_7100lc,mem_7100lc")
500 (define_insn_reservation "Y11" 2
501 (and (eq_attr "type" "fpstore")
502 (eq_attr "cpu" "7200"))
503 "i1_7100lc,mem_7100lc")
505 (define_insn_reservation "Y12" 4
506 (and (eq_attr "type" "fpstore_load")
507 (eq_attr "cpu" "7200"))
508 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
510 (define_insn_reservation "Y13" 4
511 (and (eq_attr "type" "store_fpload")
512 (eq_attr "cpu" "7200"))
513 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
515 ;; The 7300 has no penalty for store-store or store-load
516 (define_insn_reservation "Y14" 2
517 (and (eq_attr "type" "store")
518 (eq_attr "cpu" "7300"))
519 "i1_7100lc")
521 (define_insn_reservation "Y15" 2
522 (and (eq_attr "type" "fpstore")
523 (eq_attr "cpu" "7300"))
524 "i1_7100lc")
526 (define_insn_reservation "Y16" 4
527 (and (eq_attr "type" "fpstore_load")
528 (eq_attr "cpu" "7300"))
529 "i1_7100lc,i1_7100lc+mem_7100lc")
531 (define_insn_reservation "Y17" 4
532 (and (eq_attr "type" "store_fpload")
533 (eq_attr "cpu" "7300"))
534 "i1_7100lc,i1_7100lc+mem_7100lc")
536 ;; We have an "anti-bypass" for FP loads which feed an FP store.
537 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
539 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
540 ;; traditional architecture.
541 ;;
542 ;; The PA8000 has a large (56) entry reorder buffer that is split between
543 ;; memory and non-memory operations.
544 ;;
545 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
546 ;; the function units, with the exception of branches and multi-output
547 ;; instructions. The PA8000 can retire two non-memory operations per cycle
548 ;; and two memory operations per cycle, only one of which may be a store.
549 ;;
550 ;; Given the large reorder buffer, the processor can hide most latencies.
551 ;; According to HP, they've got the best results by scheduling for retirement
552 ;; bandwidth with limited latency scheduling for floating point operations.
553 ;; Latency for integer operations and memory references is ignored.
554 ;;
555 ;;
556 ;; We claim floating point operations have a 2 cycle latency and are
557 ;; fully pipelined, except for div and sqrt which are not pipelined and
558 ;; take from 17 to 31 cycles to complete.
559 ;;
560 ;; It's worth noting that there is no way to saturate all the functional
561 ;; units on the PA8000 as there is not enough issue bandwidth.
563 (define_automaton "pa8000")
564 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
565 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
566 (define_cpu_unit "store_8000" "pa8000")
567 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
568 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
569 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
570 (define_reservation "im_8000" "im0_8000 | im1_8000")
571 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
572 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
573 (define_reservation "f_8000" "f0_8000 | f1_8000")
574 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
576 ;; We can issue any two memops per cycle, but we can only retire
577 ;; one memory store per cycle. We assume that the reorder buffer
578 ;; will hide any memory latencies per HP's recommendation.
579 (define_insn_reservation "Z0" 0
580 (and
581 (eq_attr "type" "load,fpload")
582 (eq_attr "cpu" "8000"))
583 "im_8000,rm_8000")
585 (define_insn_reservation "Z1" 0
586 (and
587 (eq_attr "type" "store,fpstore")
588 (eq_attr "cpu" "8000"))
589 "im_8000,rm_8000+store_8000")
591 (define_insn_reservation "Z2" 0
592 (and (eq_attr "type" "fpstore_load,store_fpload")
593 (eq_attr "cpu" "8000"))
594 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
596 ;; We can issue and retire two non-memory operations per cycle with
597 ;; a few exceptions (branches). This group catches those we want
598 ;; to assume have zero latency.
599 (define_insn_reservation "Z3" 0
600 (and
601 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
602 (eq_attr "cpu" "8000"))
603 "inm_8000,rnm_8000")
605 ;; Branches use both slots in the non-memory issue and
606 ;; retirement unit.
607 (define_insn_reservation "Z4" 0
608 (and
609 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
610 (eq_attr "cpu" "8000"))
611 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
613 ;; We partial latency schedule the floating point units.
614 ;; They can issue/retire two at a time in the non-memory
615 ;; units. We fix their latency at 2 cycles and they
616 ;; are fully pipelined.
617 (define_insn_reservation "Z5" 1
618 (and
619 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
620 (eq_attr "cpu" "8000"))
621 "inm_8000,f_8000,rnm_8000")
623 ;; The fdivsqrt units are not pipelined and have a very long latency.
624 ;; To keep the DFA from exploding, we do not show all the
625 ;; reservations for the divsqrt unit.
626 (define_insn_reservation "Z6" 17
627 (and
628 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
629 (eq_attr "cpu" "8000"))
630 "inm_8000,fdivsqrt_8000*6,rnm_8000")
632 (define_insn_reservation "Z7" 31
633 (and
634 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
635 (eq_attr "cpu" "8000"))
636 "inm_8000,fdivsqrt_8000*6,rnm_8000")
638 ;; Operand and operator predicates and constraints
640 (include "predicates.md")
641 (include "constraints.md")
642 \f
643 ;; Compare instructions.
644 ;; This controls RTL generation and register allocation.
646 ;; We generate RTL for comparisons and branches by having the cmpxx
647 ;; patterns store away the operands. Then, the scc and bcc patterns
648 ;; emit RTL for both the compare and the branch.
649 ;;
651 (define_expand "cmpdi"
652 [(set (reg:CC 0)
653 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
654 (match_operand:DI 1 "register_operand" "")))]
655 "TARGET_64BIT"
657 "
658 {
659 hppa_compare_op0 = operands[0];
660 hppa_compare_op1 = operands[1];
661 hppa_branch_type = CMP_SI;
662 DONE;
663 }")
665 (define_expand "cmpsi"
666 [(set (reg:CC 0)
667 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
668 (match_operand:SI 1 "arith5_operand" "")))]
669 ""
670 "
671 {
672 hppa_compare_op0 = operands[0];
673 hppa_compare_op1 = operands[1];
674 hppa_branch_type = CMP_SI;
675 DONE;
676 }")
678 (define_expand "cmpsf"
679 [(set (reg:CCFP 0)
680 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
681 (match_operand:SF 1 "reg_or_0_operand" "")))]
682 "! TARGET_SOFT_FLOAT"
683 "
684 {
685 hppa_compare_op0 = operands[0];
686 hppa_compare_op1 = operands[1];
687 hppa_branch_type = CMP_SF;
688 DONE;
689 }")
691 (define_expand "cmpdf"
692 [(set (reg:CCFP 0)
693 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
694 (match_operand:DF 1 "reg_or_0_operand" "")))]
695 "! TARGET_SOFT_FLOAT"
696 "
697 {
698 hppa_compare_op0 = operands[0];
699 hppa_compare_op1 = operands[1];
700 hppa_branch_type = CMP_DF;
701 DONE;
702 }")
704 (define_insn ""
705 [(set (reg:CCFP 0)
706 (match_operator:CCFP 2 "comparison_operator"
707 [(match_operand:SF 0 "reg_or_0_operand" "fG")
708 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
709 "! TARGET_SOFT_FLOAT"
710 "fcmp,sgl,%Y2 %f0,%f1"
711 [(set_attr "length" "4")
712 (set_attr "type" "fpcc")])
714 (define_insn ""
715 [(set (reg:CCFP 0)
716 (match_operator:CCFP 2 "comparison_operator"
717 [(match_operand:DF 0 "reg_or_0_operand" "fG")
718 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
719 "! TARGET_SOFT_FLOAT"
720 "fcmp,dbl,%Y2 %f0,%f1"
721 [(set_attr "length" "4")
722 (set_attr "type" "fpcc")])
724 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
725 ;; placeholders. This is necessary in rare situations when a
726 ;; placeholder is re-emitted (see PR 8705).
728 (define_expand "movccfp"
729 [(set (reg:CCFP 0)
730 (match_operand 0 "const_int_operand" ""))]
731 "! TARGET_SOFT_FLOAT"
732 "
733 {
734 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
735 FAIL;
736 }")
738 ;; The following patterns are optimization placeholders. In almost
739 ;; all cases, the user of the condition code will be simplified and the
740 ;; original condition code setting insn should be eliminated.
742 (define_insn "*movccfp0"
743 [(set (reg:CCFP 0)
744 (const_int 0))]
745 "! TARGET_SOFT_FLOAT"
746 "fcmp,dbl,= %%fr0,%%fr0"
747 [(set_attr "length" "4")
748 (set_attr "type" "fpcc")])
750 (define_insn "*movccfp1"
751 [(set (reg:CCFP 0)
752 (const_int 1))]
753 "! TARGET_SOFT_FLOAT"
754 "fcmp,dbl,!= %%fr0,%%fr0"
755 [(set_attr "length" "4")
756 (set_attr "type" "fpcc")])
758 ;; scc insns.
760 (define_expand "seq"
761 [(set (match_operand:SI 0 "register_operand" "")
762 (eq:SI (match_dup 1)
763 (match_dup 2)))]
764 "!TARGET_64BIT"
765 "
766 {
767 /* fp scc patterns rarely match, and are not a win on the PA. */
768 if (hppa_branch_type != CMP_SI)
769 FAIL;
770 /* set up operands from compare. */
771 operands[1] = hppa_compare_op0;
772 operands[2] = hppa_compare_op1;
773 /* fall through and generate default code */
774 }")
776 (define_expand "sne"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (ne:SI (match_dup 1)
779 (match_dup 2)))]
780 "!TARGET_64BIT"
781 "
782 {
783 /* fp scc patterns rarely match, and are not a win on the PA. */
784 if (hppa_branch_type != CMP_SI)
785 FAIL;
786 operands[1] = hppa_compare_op0;
787 operands[2] = hppa_compare_op1;
788 }")
790 (define_expand "slt"
791 [(set (match_operand:SI 0 "register_operand" "")
792 (lt:SI (match_dup 1)
793 (match_dup 2)))]
794 "!TARGET_64BIT"
795 "
796 {
797 /* fp scc patterns rarely match, and are not a win on the PA. */
798 if (hppa_branch_type != CMP_SI)
799 FAIL;
800 operands[1] = hppa_compare_op0;
801 operands[2] = hppa_compare_op1;
802 }")
804 (define_expand "sgt"
805 [(set (match_operand:SI 0 "register_operand" "")
806 (gt:SI (match_dup 1)
807 (match_dup 2)))]
808 "!TARGET_64BIT"
809 "
810 {
811 /* fp scc patterns rarely match, and are not a win on the PA. */
812 if (hppa_branch_type != CMP_SI)
813 FAIL;
814 operands[1] = hppa_compare_op0;
815 operands[2] = hppa_compare_op1;
816 }")
818 (define_expand "sle"
819 [(set (match_operand:SI 0 "register_operand" "")
820 (le:SI (match_dup 1)
821 (match_dup 2)))]
822 "!TARGET_64BIT"
823 "
824 {
825 /* fp scc patterns rarely match, and are not a win on the PA. */
826 if (hppa_branch_type != CMP_SI)
827 FAIL;
828 operands[1] = hppa_compare_op0;
829 operands[2] = hppa_compare_op1;
830 }")
832 (define_expand "sge"
833 [(set (match_operand:SI 0 "register_operand" "")
834 (ge:SI (match_dup 1)
835 (match_dup 2)))]
836 "!TARGET_64BIT"
837 "
838 {
839 /* fp scc patterns rarely match, and are not a win on the PA. */
840 if (hppa_branch_type != CMP_SI)
841 FAIL;
842 operands[1] = hppa_compare_op0;
843 operands[2] = hppa_compare_op1;
844 }")
846 (define_expand "sltu"
847 [(set (match_operand:SI 0 "register_operand" "")
848 (ltu:SI (match_dup 1)
849 (match_dup 2)))]
850 "!TARGET_64BIT"
851 "
852 {
853 if (hppa_branch_type != CMP_SI)
854 FAIL;
855 operands[1] = hppa_compare_op0;
856 operands[2] = hppa_compare_op1;
857 }")
859 (define_expand "sgtu"
860 [(set (match_operand:SI 0 "register_operand" "")
861 (gtu:SI (match_dup 1)
862 (match_dup 2)))]
863 "!TARGET_64BIT"
864 "
865 {
866 if (hppa_branch_type != CMP_SI)
867 FAIL;
868 operands[1] = hppa_compare_op0;
869 operands[2] = hppa_compare_op1;
870 }")
872 (define_expand "sleu"
873 [(set (match_operand:SI 0 "register_operand" "")
874 (leu:SI (match_dup 1)
875 (match_dup 2)))]
876 "!TARGET_64BIT"
877 "
878 {
879 if (hppa_branch_type != CMP_SI)
880 FAIL;
881 operands[1] = hppa_compare_op0;
882 operands[2] = hppa_compare_op1;
883 }")
885 (define_expand "sgeu"
886 [(set (match_operand:SI 0 "register_operand" "")
887 (geu:SI (match_dup 1)
888 (match_dup 2)))]
889 "!TARGET_64BIT"
890 "
891 {
892 if (hppa_branch_type != CMP_SI)
893 FAIL;
894 operands[1] = hppa_compare_op0;
895 operands[2] = hppa_compare_op1;
896 }")
898 ;; Instruction canonicalization puts immediate operands second, which
899 ;; is the reverse of what we want.
901 (define_insn "scc"
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (match_operator:SI 3 "comparison_operator"
904 [(match_operand:SI 1 "register_operand" "r")
905 (match_operand:SI 2 "arith11_operand" "rI")]))]
906 ""
907 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
911 (define_insn ""
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (match_operator:DI 3 "comparison_operator"
914 [(match_operand:DI 1 "register_operand" "r")
915 (match_operand:DI 2 "arith11_operand" "rI")]))]
916 "TARGET_64BIT"
917 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 (define_insn "iorscc"
922 [(set (match_operand:SI 0 "register_operand" "=r")
923 (ior:SI (match_operator:SI 3 "comparison_operator"
924 [(match_operand:SI 1 "register_operand" "r")
925 (match_operand:SI 2 "arith11_operand" "rI")])
926 (match_operator:SI 6 "comparison_operator"
927 [(match_operand:SI 4 "register_operand" "r")
928 (match_operand:SI 5 "arith11_operand" "rI")])))]
929 ""
930 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "12")])
934 (define_insn ""
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (ior:DI (match_operator:DI 3 "comparison_operator"
937 [(match_operand:DI 1 "register_operand" "r")
938 (match_operand:DI 2 "arith11_operand" "rI")])
939 (match_operator:DI 6 "comparison_operator"
940 [(match_operand:DI 4 "register_operand" "r")
941 (match_operand:DI 5 "arith11_operand" "rI")])))]
942 "TARGET_64BIT"
943 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
944 [(set_attr "type" "binary")
945 (set_attr "length" "12")])
947 ;; Combiner patterns for common operations performed with the output
948 ;; from an scc insn (negscc and incscc).
949 (define_insn "negscc"
950 [(set (match_operand:SI 0 "register_operand" "=r")
951 (neg:SI (match_operator:SI 3 "comparison_operator"
952 [(match_operand:SI 1 "register_operand" "r")
953 (match_operand:SI 2 "arith11_operand" "rI")])))]
954 ""
955 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
956 [(set_attr "type" "binary")
957 (set_attr "length" "8")])
959 (define_insn ""
960 [(set (match_operand:DI 0 "register_operand" "=r")
961 (neg:DI (match_operator:DI 3 "comparison_operator"
962 [(match_operand:DI 1 "register_operand" "r")
963 (match_operand:DI 2 "arith11_operand" "rI")])))]
964 "TARGET_64BIT"
965 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
966 [(set_attr "type" "binary")
967 (set_attr "length" "8")])
969 ;; Patterns for adding/subtracting the result of a boolean expression from
970 ;; a register. First we have special patterns that make use of the carry
971 ;; bit, and output only two instructions. For the cases we can't in
972 ;; general do in two instructions, the incscc pattern at the end outputs
973 ;; two or three instructions.
975 (define_insn ""
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
978 (match_operand:SI 3 "arith11_operand" "rI"))
979 (match_operand:SI 1 "register_operand" "r")))]
980 ""
981 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
982 [(set_attr "type" "binary")
983 (set_attr "length" "8")])
985 (define_insn ""
986 [(set (match_operand:DI 0 "register_operand" "=r")
987 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
988 (match_operand:DI 3 "arith11_operand" "rI"))
989 (match_operand:DI 1 "register_operand" "r")))]
990 "TARGET_64BIT"
991 "sub%I3,* %3,%2,%%r0\;add,dc %%r0,%1,%0"
992 [(set_attr "type" "binary")
993 (set_attr "length" "8")])
995 ; This need only accept registers for op3, since canonicalization
996 ; replaces geu with gtu when op3 is an integer.
997 (define_insn ""
998 [(set (match_operand:SI 0 "register_operand" "=r")
999 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
1000 (match_operand:SI 3 "register_operand" "r"))
1001 (match_operand:SI 1 "register_operand" "r")))]
1002 ""
1003 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
1004 [(set_attr "type" "binary")
1005 (set_attr "length" "8")])
1007 (define_insn ""
1008 [(set (match_operand:DI 0 "register_operand" "=r")
1009 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
1010 (match_operand:DI 3 "register_operand" "r"))
1011 (match_operand:DI 1 "register_operand" "r")))]
1012 "TARGET_64BIT"
1013 "sub,* %2,%3,%%r0\;add,dc %%r0,%1,%0"
1014 [(set_attr "type" "binary")
1015 (set_attr "length" "8")])
1017 ; Match only integers for op3 here. This is used as canonical form of the
1018 ; geu pattern when op3 is an integer. Don't match registers since we can't
1019 ; make better code than the general incscc pattern.
1020 (define_insn ""
1021 [(set (match_operand:SI 0 "register_operand" "=r")
1022 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
1023 (match_operand:SI 3 "int11_operand" "I"))
1024 (match_operand:SI 1 "register_operand" "r")))]
1025 ""
1026 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
1027 [(set_attr "type" "binary")
1028 (set_attr "length" "8")])
1030 (define_insn ""
1031 [(set (match_operand:DI 0 "register_operand" "=r")
1032 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
1033 (match_operand:DI 3 "int11_operand" "I"))
1034 (match_operand:DI 1 "register_operand" "r")))]
1035 "TARGET_64BIT"
1036 "addi,* %k3,%2,%%r0\;add,dc %%r0,%1,%0"
1037 [(set_attr "type" "binary")
1038 (set_attr "length" "8")])
1040 (define_insn "incscc"
1041 [(set (match_operand:SI 0 "register_operand" "=r,r")
1042 (plus:SI (match_operator:SI 4 "comparison_operator"
1043 [(match_operand:SI 2 "register_operand" "r,r")
1044 (match_operand:SI 3 "arith11_operand" "rI,rI")])
1045 (match_operand:SI 1 "register_operand" "0,?r")))]
1046 ""
1047 "@
1048 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
1049 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1050 [(set_attr "type" "binary,binary")
1051 (set_attr "length" "8,12")])
1053 (define_insn ""
1054 [(set (match_operand:DI 0 "register_operand" "=r,r")
1055 (plus:DI (match_operator:DI 4 "comparison_operator"
1056 [(match_operand:DI 2 "register_operand" "r,r")
1057 (match_operand:DI 3 "arith11_operand" "rI,rI")])
1058 (match_operand:DI 1 "register_operand" "0,?r")))]
1059 "TARGET_64BIT"
1060 "@
1061 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1062 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1063 [(set_attr "type" "binary,binary")
1064 (set_attr "length" "8,12")])
1066 (define_insn ""
1067 [(set (match_operand:SI 0 "register_operand" "=r")
1068 (minus:SI (match_operand:SI 1 "register_operand" "r")
1069 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1070 (match_operand:SI 3 "arith11_operand" "rI"))))]
1071 ""
1072 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1073 [(set_attr "type" "binary")
1074 (set_attr "length" "8")])
1076 (define_insn ""
1077 [(set (match_operand:DI 0 "register_operand" "=r")
1078 (minus:DI (match_operand:DI 1 "register_operand" "r")
1079 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1080 (match_operand:DI 3 "arith11_operand" "rI"))))]
1081 "TARGET_64BIT"
1082 "sub%I3,* %3,%2,%%r0\;sub,db %1,%%r0,%0"
1083 [(set_attr "type" "binary")
1084 (set_attr "length" "8")])
1086 (define_insn ""
1087 [(set (match_operand:SI 0 "register_operand" "=r")
1088 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1089 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1090 (match_operand:SI 3 "arith11_operand" "rI")))
1091 (match_operand:SI 4 "register_operand" "r")))]
1092 ""
1093 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1094 [(set_attr "type" "binary")
1095 (set_attr "length" "8")])
1097 (define_insn ""
1098 [(set (match_operand:DI 0 "register_operand" "=r")
1099 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1100 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1101 (match_operand:DI 3 "arith11_operand" "rI")))
1102 (match_operand:DI 4 "register_operand" "r")))]
1103 "TARGET_64BIT"
1104 "sub%I3,* %3,%2,%%r0\;sub,db %1,%4,%0"
1105 [(set_attr "type" "binary")
1106 (set_attr "length" "8")])
1108 ; This need only accept registers for op3, since canonicalization
1109 ; replaces ltu with leu when op3 is an integer.
1110 (define_insn ""
1111 [(set (match_operand:SI 0 "register_operand" "=r")
1112 (minus:SI (match_operand:SI 1 "register_operand" "r")
1113 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1114 (match_operand:SI 3 "register_operand" "r"))))]
1115 ""
1116 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1117 [(set_attr "type" "binary")
1118 (set_attr "length" "8")])
1120 (define_insn ""
1121 [(set (match_operand:DI 0 "register_operand" "=r")
1122 (minus:DI (match_operand:DI 1 "register_operand" "r")
1123 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1124 (match_operand:DI 3 "register_operand" "r"))))]
1125 "TARGET_64BIT"
1126 "sub,* %2,%3,%%r0\;sub,db %1,%%r0,%0"
1127 [(set_attr "type" "binary")
1128 (set_attr "length" "8")])
1130 (define_insn ""
1131 [(set (match_operand:SI 0 "register_operand" "=r")
1132 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1133 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1134 (match_operand:SI 3 "register_operand" "r")))
1135 (match_operand:SI 4 "register_operand" "r")))]
1136 ""
1137 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1138 [(set_attr "type" "binary")
1139 (set_attr "length" "8")])
1141 (define_insn ""
1142 [(set (match_operand:DI 0 "register_operand" "=r")
1143 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1144 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1145 (match_operand:DI 3 "register_operand" "r")))
1146 (match_operand:DI 4 "register_operand" "r")))]
1147 "TARGET_64BIT"
1148 "sub,* %2,%3,%%r0\;sub,db %1,%4,%0"
1149 [(set_attr "type" "binary")
1150 (set_attr "length" "8")])
1152 ; Match only integers for op3 here. This is used as canonical form of the
1153 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1154 ; make better code than the general incscc pattern.
1155 (define_insn ""
1156 [(set (match_operand:SI 0 "register_operand" "=r")
1157 (minus:SI (match_operand:SI 1 "register_operand" "r")
1158 (leu:SI (match_operand:SI 2 "register_operand" "r")
1159 (match_operand:SI 3 "int11_operand" "I"))))]
1160 ""
1161 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1162 [(set_attr "type" "binary")
1163 (set_attr "length" "8")])
1165 (define_insn ""
1166 [(set (match_operand:DI 0 "register_operand" "=r")
1167 (minus:DI (match_operand:DI 1 "register_operand" "r")
1168 (leu:DI (match_operand:DI 2 "register_operand" "r")
1169 (match_operand:DI 3 "int11_operand" "I"))))]
1170 "TARGET_64BIT"
1171 "addi,* %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1172 [(set_attr "type" "binary")
1173 (set_attr "length" "8")])
1175 (define_insn ""
1176 [(set (match_operand:SI 0 "register_operand" "=r")
1177 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1178 (leu:SI (match_operand:SI 2 "register_operand" "r")
1179 (match_operand:SI 3 "int11_operand" "I")))
1180 (match_operand:SI 4 "register_operand" "r")))]
1181 ""
1182 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1183 [(set_attr "type" "binary")
1184 (set_attr "length" "8")])
1186 (define_insn ""
1187 [(set (match_operand:DI 0 "register_operand" "=r")
1188 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1189 (leu:DI (match_operand:DI 2 "register_operand" "r")
1190 (match_operand:DI 3 "int11_operand" "I")))
1191 (match_operand:DI 4 "register_operand" "r")))]
1192 "TARGET_64BIT"
1193 "addi,* %k3,%2,%%r0\;sub,db %1,%4,%0"
1194 [(set_attr "type" "binary")
1195 (set_attr "length" "8")])
1197 (define_insn "decscc"
1198 [(set (match_operand:SI 0 "register_operand" "=r,r")
1199 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1200 (match_operator:SI 4 "comparison_operator"
1201 [(match_operand:SI 2 "register_operand" "r,r")
1202 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1203 ""
1204 "@
1205 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1206 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1207 [(set_attr "type" "binary,binary")
1208 (set_attr "length" "8,12")])
1210 (define_insn ""
1211 [(set (match_operand:DI 0 "register_operand" "=r,r")
1212 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1213 (match_operator:DI 4 "comparison_operator"
1214 [(match_operand:DI 2 "register_operand" "r,r")
1215 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1216 "TARGET_64BIT"
1217 "@
1218 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1219 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1220 [(set_attr "type" "binary,binary")
1221 (set_attr "length" "8,12")])
1223 ; Patterns for max and min. (There is no need for an earlyclobber in the
1224 ; last alternative since the middle alternative will match if op0 == op1.)
1226 (define_insn "sminsi3"
1227 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1228 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1229 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1230 ""
1231 "@
1232 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1233 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1234 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1235 [(set_attr "type" "multi,multi,multi")
1236 (set_attr "length" "8,8,8")])
1238 (define_insn "smindi3"
1239 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1240 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1241 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1242 "TARGET_64BIT"
1243 "@
1244 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1245 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1246 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1247 [(set_attr "type" "multi,multi,multi")
1248 (set_attr "length" "8,8,8")])
1250 (define_insn "uminsi3"
1251 [(set (match_operand:SI 0 "register_operand" "=r,r")
1252 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1253 (match_operand:SI 2 "arith11_operand" "r,I")))]
1254 ""
1255 "@
1256 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1257 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1258 [(set_attr "type" "multi,multi")
1259 (set_attr "length" "8,8")])
1261 (define_insn "umindi3"
1262 [(set (match_operand:DI 0 "register_operand" "=r,r")
1263 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1264 (match_operand:DI 2 "arith11_operand" "r,I")))]
1265 "TARGET_64BIT"
1266 "@
1267 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1268 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1269 [(set_attr "type" "multi,multi")
1270 (set_attr "length" "8,8")])
1272 (define_insn "smaxsi3"
1273 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1274 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1275 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1276 ""
1277 "@
1278 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1279 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1280 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1281 [(set_attr "type" "multi,multi,multi")
1282 (set_attr "length" "8,8,8")])
1284 (define_insn "smaxdi3"
1285 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1286 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1287 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1288 "TARGET_64BIT"
1289 "@
1290 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1291 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1292 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1293 [(set_attr "type" "multi,multi,multi")
1294 (set_attr "length" "8,8,8")])
1296 (define_insn "umaxsi3"
1297 [(set (match_operand:SI 0 "register_operand" "=r,r")
1298 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1299 (match_operand:SI 2 "arith11_operand" "r,I")))]
1300 ""
1301 "@
1302 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1303 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1304 [(set_attr "type" "multi,multi")
1305 (set_attr "length" "8,8")])
1307 (define_insn "umaxdi3"
1308 [(set (match_operand:DI 0 "register_operand" "=r,r")
1309 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1310 (match_operand:DI 2 "arith11_operand" "r,I")))]
1311 "TARGET_64BIT"
1312 "@
1313 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1314 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1315 [(set_attr "type" "multi,multi")
1316 (set_attr "length" "8,8")])
1318 (define_insn "abssi2"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1320 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1321 ""
1322 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1323 [(set_attr "type" "multi")
1324 (set_attr "length" "8")])
1326 (define_insn "absdi2"
1327 [(set (match_operand:DI 0 "register_operand" "=r")
1328 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1329 "TARGET_64BIT"
1330 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1331 [(set_attr "type" "multi")
1332 (set_attr "length" "8")])
1334 ;;; Experimental conditional move patterns
1336 (define_expand "movsicc"
1337 [(set (match_operand:SI 0 "register_operand" "")
1338 (if_then_else:SI
1339 (match_operator 1 "comparison_operator"
1340 [(match_dup 4)
1341 (match_dup 5)])
1342 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1343 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1344 ""
1345 "
1346 {
1347 enum rtx_code code = GET_CODE (operands[1]);
1349 if (hppa_branch_type != CMP_SI)
1350 FAIL;
1352 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1353 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1354 FAIL;
1356 /* operands[1] is currently the result of compare_from_rtx. We want to
1357 emit a compare of the original operands. */
1358 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1359 operands[4] = hppa_compare_op0;
1360 operands[5] = hppa_compare_op1;
1361 }")
1363 ;; We used to accept any register for op1.
1364 ;;
1365 ;; However, it loses sometimes because the compiler will end up using
1366 ;; different registers for op0 and op1 in some critical cases. local-alloc
1367 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1368 ;;
1369 ;; If/when global register allocation supports tying we should allow any
1370 ;; register for op1 again.
1371 (define_insn ""
1372 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1373 (if_then_else:SI
1374 (match_operator 2 "comparison_operator"
1375 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1376 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1377 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1378 (const_int 0)))]
1379 ""
1380 "@
1381 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1382 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1383 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1384 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1385 [(set_attr "type" "multi,multi,multi,nullshift")
1386 (set_attr "length" "8,8,8,8")])
1388 (define_insn ""
1389 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1390 (if_then_else:SI
1391 (match_operator 5 "comparison_operator"
1392 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1393 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1394 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1395 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1396 ""
1397 "@
1398 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1399 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1400 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1401 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1402 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1403 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1404 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1405 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1406 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1407 (set_attr "length" "8,8,8,8,8,8,8,8")])
1409 (define_expand "movdicc"
1410 [(set (match_operand:DI 0 "register_operand" "")
1411 (if_then_else:DI
1412 (match_operator 1 "comparison_operator"
1413 [(match_dup 4)
1414 (match_dup 5)])
1415 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1416 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1417 "TARGET_64BIT"
1418 "
1419 {
1420 enum rtx_code code = GET_CODE (operands[1]);
1422 if (hppa_branch_type != CMP_SI)
1423 FAIL;
1425 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1426 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1427 FAIL;
1429 /* operands[1] is currently the result of compare_from_rtx. We want to
1430 emit a compare of the original operands. */
1431 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1432 operands[4] = hppa_compare_op0;
1433 operands[5] = hppa_compare_op1;
1434 }")
1436 ; We need the first constraint alternative in order to avoid
1437 ; earlyclobbers on all other alternatives.
1438 (define_insn ""
1439 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1440 (if_then_else:DI
1441 (match_operator 2 "comparison_operator"
1442 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1443 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1444 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1445 (const_int 0)))]
1446 "TARGET_64BIT"
1447 "@
1448 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1449 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1450 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1451 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1452 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1453 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1454 (set_attr "length" "8,8,8,8,8")])
1456 (define_insn ""
1457 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1458 (if_then_else:DI
1459 (match_operator 5 "comparison_operator"
1460 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1461 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1462 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1463 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1464 "TARGET_64BIT"
1465 "@
1466 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1467 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1468 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1469 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1470 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1471 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1472 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1473 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1474 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1475 (set_attr "length" "8,8,8,8,8,8,8,8")])
1477 ;; Conditional Branches
1479 (define_expand "beq"
1480 [(set (pc)
1481 (if_then_else (eq (match_dup 1) (match_dup 2))
1482 (label_ref (match_operand 0 "" ""))
1483 (pc)))]
1484 ""
1485 "
1486 {
1487 if (hppa_branch_type != CMP_SI)
1488 {
1489 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1490 emit_bcond_fp (NE, operands[0]);
1491 DONE;
1492 }
1493 /* set up operands from compare. */
1494 operands[1] = hppa_compare_op0;
1495 operands[2] = hppa_compare_op1;
1496 /* fall through and generate default code */
1497 }")
1499 (define_expand "bne"
1500 [(set (pc)
1501 (if_then_else (ne (match_dup 1) (match_dup 2))
1502 (label_ref (match_operand 0 "" ""))
1503 (pc)))]
1504 ""
1505 "
1506 {
1507 if (hppa_branch_type != CMP_SI)
1508 {
1509 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1510 emit_bcond_fp (NE, operands[0]);
1511 DONE;
1512 }
1513 operands[1] = hppa_compare_op0;
1514 operands[2] = hppa_compare_op1;
1515 }")
1517 (define_expand "bgt"
1518 [(set (pc)
1519 (if_then_else (gt (match_dup 1) (match_dup 2))
1520 (label_ref (match_operand 0 "" ""))
1521 (pc)))]
1522 ""
1523 "
1524 {
1525 if (hppa_branch_type != CMP_SI)
1526 {
1527 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1528 emit_bcond_fp (NE, operands[0]);
1529 DONE;
1530 }
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1533 }")
1535 (define_expand "blt"
1536 [(set (pc)
1537 (if_then_else (lt (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1539 (pc)))]
1540 ""
1541 "
1542 {
1543 if (hppa_branch_type != CMP_SI)
1544 {
1545 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1546 emit_bcond_fp (NE, operands[0]);
1547 DONE;
1548 }
1549 operands[1] = hppa_compare_op0;
1550 operands[2] = hppa_compare_op1;
1551 }")
1553 (define_expand "bge"
1554 [(set (pc)
1555 (if_then_else (ge (match_dup 1) (match_dup 2))
1556 (label_ref (match_operand 0 "" ""))
1557 (pc)))]
1558 ""
1559 "
1560 {
1561 if (hppa_branch_type != CMP_SI)
1562 {
1563 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1564 emit_bcond_fp (NE, operands[0]);
1565 DONE;
1566 }
1567 operands[1] = hppa_compare_op0;
1568 operands[2] = hppa_compare_op1;
1569 }")
1571 (define_expand "ble"
1572 [(set (pc)
1573 (if_then_else (le (match_dup 1) (match_dup 2))
1574 (label_ref (match_operand 0 "" ""))
1575 (pc)))]
1576 ""
1577 "
1578 {
1579 if (hppa_branch_type != CMP_SI)
1580 {
1581 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1582 emit_bcond_fp (NE, operands[0]);
1583 DONE;
1584 }
1585 operands[1] = hppa_compare_op0;
1586 operands[2] = hppa_compare_op1;
1587 }")
1589 (define_expand "bgtu"
1590 [(set (pc)
1591 (if_then_else (gtu (match_dup 1) (match_dup 2))
1592 (label_ref (match_operand 0 "" ""))
1593 (pc)))]
1594 ""
1595 "
1596 {
1597 if (hppa_branch_type != CMP_SI)
1598 FAIL;
1599 operands[1] = hppa_compare_op0;
1600 operands[2] = hppa_compare_op1;
1601 }")
1603 (define_expand "bltu"
1604 [(set (pc)
1605 (if_then_else (ltu (match_dup 1) (match_dup 2))
1606 (label_ref (match_operand 0 "" ""))
1607 (pc)))]
1608 ""
1609 "
1610 {
1611 if (hppa_branch_type != CMP_SI)
1612 FAIL;
1613 operands[1] = hppa_compare_op0;
1614 operands[2] = hppa_compare_op1;
1615 }")
1617 (define_expand "bgeu"
1618 [(set (pc)
1619 (if_then_else (geu (match_dup 1) (match_dup 2))
1620 (label_ref (match_operand 0 "" ""))
1621 (pc)))]
1622 ""
1623 "
1624 {
1625 if (hppa_branch_type != CMP_SI)
1626 FAIL;
1627 operands[1] = hppa_compare_op0;
1628 operands[2] = hppa_compare_op1;
1629 }")
1631 (define_expand "bleu"
1632 [(set (pc)
1633 (if_then_else (leu (match_dup 1) (match_dup 2))
1634 (label_ref (match_operand 0 "" ""))
1635 (pc)))]
1636 ""
1637 "
1638 {
1639 if (hppa_branch_type != CMP_SI)
1640 FAIL;
1641 operands[1] = hppa_compare_op0;
1642 operands[2] = hppa_compare_op1;
1643 }")
1645 (define_expand "bltgt"
1646 [(set (pc)
1647 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1648 (label_ref (match_operand 0 "" ""))
1649 (pc)))]
1650 ""
1651 "
1652 {
1653 if (hppa_branch_type == CMP_SI)
1654 FAIL;
1655 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1656 emit_bcond_fp (NE, operands[0]);
1657 DONE;
1658 }")
1660 (define_expand "bunle"
1661 [(set (pc)
1662 (if_then_else (unle (match_dup 1) (match_dup 2))
1663 (label_ref (match_operand 0 "" ""))
1664 (pc)))]
1665 ""
1666 "
1667 {
1668 if (hppa_branch_type == CMP_SI)
1669 FAIL;
1670 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1671 emit_bcond_fp (NE, operands[0]);
1672 DONE;
1673 }")
1675 (define_expand "bunlt"
1676 [(set (pc)
1677 (if_then_else (unlt (match_dup 1) (match_dup 2))
1678 (label_ref (match_operand 0 "" ""))
1679 (pc)))]
1680 ""
1681 "
1682 {
1683 if (hppa_branch_type == CMP_SI)
1684 FAIL;
1685 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1686 emit_bcond_fp (NE, operands[0]);
1687 DONE;
1688 }")
1690 (define_expand "bunge"
1691 [(set (pc)
1692 (if_then_else (unge (match_dup 1) (match_dup 2))
1693 (label_ref (match_operand 0 "" ""))
1694 (pc)))]
1695 ""
1696 "
1697 {
1698 if (hppa_branch_type == CMP_SI)
1699 FAIL;
1700 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1701 emit_bcond_fp (NE, operands[0]);
1702 DONE;
1703 }")
1705 (define_expand "bungt"
1706 [(set (pc)
1707 (if_then_else (ungt (match_dup 1) (match_dup 2))
1708 (label_ref (match_operand 0 "" ""))
1709 (pc)))]
1710 ""
1711 "
1712 {
1713 if (hppa_branch_type == CMP_SI)
1714 FAIL;
1715 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1716 emit_bcond_fp (NE, operands[0]);
1717 DONE;
1718 }")
1720 (define_expand "buneq"
1721 [(set (pc)
1722 (if_then_else (uneq (match_dup 1) (match_dup 2))
1723 (label_ref (match_operand 0 "" ""))
1724 (pc)))]
1725 ""
1726 "
1727 {
1728 if (hppa_branch_type == CMP_SI)
1729 FAIL;
1730 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1731 emit_bcond_fp (NE, operands[0]);
1732 DONE;
1733 }")
1735 (define_expand "bunordered"
1736 [(set (pc)
1737 (if_then_else (unordered (match_dup 1) (match_dup 2))
1738 (label_ref (match_operand 0 "" ""))
1739 (pc)))]
1740 ""
1741 "
1742 {
1743 if (hppa_branch_type == CMP_SI)
1744 FAIL;
1745 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1746 emit_bcond_fp (NE, operands[0]);
1747 DONE;
1748 }")
1750 (define_expand "bordered"
1751 [(set (pc)
1752 (if_then_else (ordered (match_dup 1) (match_dup 2))
1753 (label_ref (match_operand 0 "" ""))
1754 (pc)))]
1755 ""
1756 "
1757 {
1758 if (hppa_branch_type == CMP_SI)
1759 FAIL;
1760 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1761 emit_bcond_fp (NE, operands[0]);
1762 DONE;
1763 }")
1765 ;; Match the branch patterns.
1768 ;; Note a long backward conditional branch with an annulled delay slot
1769 ;; has a length of 12.
1770 (define_insn ""
1771 [(set (pc)
1772 (if_then_else
1773 (match_operator 3 "comparison_operator"
1774 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1775 (match_operand:SI 2 "arith5_operand" "rL")])
1776 (label_ref (match_operand 0 "" ""))
1777 (pc)))]
1778 ""
1779 "*
1780 {
1781 return output_cbranch (operands, 0, insn);
1782 }"
1783 [(set_attr "type" "cbranch")
1784 (set (attr "length")
1785 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1786 (const_int MAX_12BIT_OFFSET))
1787 (const_int 4)
1788 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1789 (const_int MAX_17BIT_OFFSET))
1790 (const_int 8)
1791 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1792 (const_int 24)
1793 (eq (symbol_ref "flag_pic") (const_int 0))
1794 (const_int 20)]
1795 (const_int 28)))])
1797 ;; Match the negated branch.
1799 (define_insn ""
1800 [(set (pc)
1801 (if_then_else
1802 (match_operator 3 "comparison_operator"
1803 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1804 (match_operand:SI 2 "arith5_operand" "rL")])
1805 (pc)
1806 (label_ref (match_operand 0 "" ""))))]
1807 ""
1808 "*
1809 {
1810 return output_cbranch (operands, 1, insn);
1811 }"
1812 [(set_attr "type" "cbranch")
1813 (set (attr "length")
1814 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1815 (const_int MAX_12BIT_OFFSET))
1816 (const_int 4)
1817 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1818 (const_int MAX_17BIT_OFFSET))
1819 (const_int 8)
1820 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1821 (const_int 24)
1822 (eq (symbol_ref "flag_pic") (const_int 0))
1823 (const_int 20)]
1824 (const_int 28)))])
1826 (define_insn ""
1827 [(set (pc)
1828 (if_then_else
1829 (match_operator 3 "comparison_operator"
1830 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1831 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1832 (label_ref (match_operand 0 "" ""))
1833 (pc)))]
1834 "TARGET_64BIT"
1835 "*
1836 {
1837 return output_cbranch (operands, 0, insn);
1838 }"
1839 [(set_attr "type" "cbranch")
1840 (set (attr "length")
1841 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1842 (const_int MAX_12BIT_OFFSET))
1843 (const_int 4)
1844 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1845 (const_int MAX_17BIT_OFFSET))
1846 (const_int 8)
1847 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1848 (const_int 24)
1849 (eq (symbol_ref "flag_pic") (const_int 0))
1850 (const_int 20)]
1851 (const_int 28)))])
1853 ;; Match the negated branch.
1855 (define_insn ""
1856 [(set (pc)
1857 (if_then_else
1858 (match_operator 3 "comparison_operator"
1859 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1860 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1861 (pc)
1862 (label_ref (match_operand 0 "" ""))))]
1863 "TARGET_64BIT"
1864 "*
1865 {
1866 return output_cbranch (operands, 1, insn);
1867 }"
1868 [(set_attr "type" "cbranch")
1869 (set (attr "length")
1870 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1871 (const_int MAX_12BIT_OFFSET))
1872 (const_int 4)
1873 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1874 (const_int MAX_17BIT_OFFSET))
1875 (const_int 8)
1876 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1877 (const_int 24)
1878 (eq (symbol_ref "flag_pic") (const_int 0))
1879 (const_int 20)]
1880 (const_int 28)))])
1881 (define_insn ""
1882 [(set (pc)
1883 (if_then_else
1884 (match_operator 3 "cmpib_comparison_operator"
1885 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1886 (match_operand:DI 2 "arith5_operand" "rL")])
1887 (label_ref (match_operand 0 "" ""))
1888 (pc)))]
1889 "TARGET_64BIT"
1890 "*
1891 {
1892 return output_cbranch (operands, 0, insn);
1893 }"
1894 [(set_attr "type" "cbranch")
1895 (set (attr "length")
1896 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1897 (const_int MAX_12BIT_OFFSET))
1898 (const_int 4)
1899 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1900 (const_int MAX_17BIT_OFFSET))
1901 (const_int 8)
1902 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1903 (const_int 24)
1904 (eq (symbol_ref "flag_pic") (const_int 0))
1905 (const_int 20)]
1906 (const_int 28)))])
1908 ;; Match the negated branch.
1910 (define_insn ""
1911 [(set (pc)
1912 (if_then_else
1913 (match_operator 3 "cmpib_comparison_operator"
1914 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1915 (match_operand:DI 2 "arith5_operand" "rL")])
1916 (pc)
1917 (label_ref (match_operand 0 "" ""))))]
1918 "TARGET_64BIT"
1919 "*
1920 {
1921 return output_cbranch (operands, 1, insn);
1922 }"
1923 [(set_attr "type" "cbranch")
1924 (set (attr "length")
1925 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1926 (const_int MAX_12BIT_OFFSET))
1927 (const_int 4)
1928 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1929 (const_int MAX_17BIT_OFFSET))
1930 (const_int 8)
1931 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1932 (const_int 24)
1933 (eq (symbol_ref "flag_pic") (const_int 0))
1934 (const_int 20)]
1935 (const_int 28)))])
1937 ;; Branch on Bit patterns.
1938 (define_insn ""
1939 [(set (pc)
1940 (if_then_else
1941 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1942 (const_int 1)
1943 (match_operand:SI 1 "uint5_operand" ""))
1944 (const_int 0))
1945 (label_ref (match_operand 2 "" ""))
1946 (pc)))]
1947 ""
1948 "*
1949 {
1950 return output_bb (operands, 0, insn, 0);
1951 }"
1952 [(set_attr "type" "cbranch")
1953 (set (attr "length")
1954 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1955 (const_int MAX_12BIT_OFFSET))
1956 (const_int 4)
1957 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1958 (const_int MAX_17BIT_OFFSET))
1959 (const_int 8)
1960 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1961 (const_int 24)
1962 (eq (symbol_ref "flag_pic") (const_int 0))
1963 (const_int 20)]
1964 (const_int 28)))])
1966 (define_insn ""
1967 [(set (pc)
1968 (if_then_else
1969 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1970 (const_int 1)
1971 (match_operand:DI 1 "uint32_operand" ""))
1972 (const_int 0))
1973 (label_ref (match_operand 2 "" ""))
1974 (pc)))]
1975 "TARGET_64BIT"
1976 "*
1977 {
1978 return output_bb (operands, 0, insn, 0);
1979 }"
1980 [(set_attr "type" "cbranch")
1981 (set (attr "length")
1982 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1983 (const_int MAX_12BIT_OFFSET))
1984 (const_int 4)
1985 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1986 (const_int MAX_17BIT_OFFSET))
1987 (const_int 8)
1988 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1989 (const_int 24)
1990 (eq (symbol_ref "flag_pic") (const_int 0))
1991 (const_int 20)]
1992 (const_int 28)))])
1994 (define_insn ""
1995 [(set (pc)
1996 (if_then_else
1997 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1998 (const_int 1)
1999 (match_operand:SI 1 "uint5_operand" ""))
2000 (const_int 0))
2001 (pc)
2002 (label_ref (match_operand 2 "" ""))))]
2003 ""
2004 "*
2005 {
2006 return output_bb (operands, 1, insn, 0);
2007 }"
2008 [(set_attr "type" "cbranch")
2009 (set (attr "length")
2010 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2011 (const_int MAX_12BIT_OFFSET))
2012 (const_int 4)
2013 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2014 (const_int MAX_17BIT_OFFSET))
2015 (const_int 8)
2016 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2017 (const_int 24)
2018 (eq (symbol_ref "flag_pic") (const_int 0))
2019 (const_int 20)]
2020 (const_int 28)))])
2022 (define_insn ""
2023 [(set (pc)
2024 (if_then_else
2025 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2026 (const_int 1)
2027 (match_operand:DI 1 "uint32_operand" ""))
2028 (const_int 0))
2029 (pc)
2030 (label_ref (match_operand 2 "" ""))))]
2031 "TARGET_64BIT"
2032 "*
2033 {
2034 return output_bb (operands, 1, insn, 0);
2035 }"
2036 [(set_attr "type" "cbranch")
2037 (set (attr "length")
2038 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2039 (const_int MAX_12BIT_OFFSET))
2040 (const_int 4)
2041 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2042 (const_int MAX_17BIT_OFFSET))
2043 (const_int 8)
2044 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2045 (const_int 24)
2046 (eq (symbol_ref "flag_pic") (const_int 0))
2047 (const_int 20)]
2048 (const_int 28)))])
2050 (define_insn ""
2051 [(set (pc)
2052 (if_then_else
2053 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2054 (const_int 1)
2055 (match_operand:SI 1 "uint5_operand" ""))
2056 (const_int 0))
2057 (label_ref (match_operand 2 "" ""))
2058 (pc)))]
2059 ""
2060 "*
2061 {
2062 return output_bb (operands, 0, insn, 1);
2063 }"
2064 [(set_attr "type" "cbranch")
2065 (set (attr "length")
2066 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2067 (const_int MAX_12BIT_OFFSET))
2068 (const_int 4)
2069 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2070 (const_int MAX_17BIT_OFFSET))
2071 (const_int 8)
2072 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2073 (const_int 24)
2074 (eq (symbol_ref "flag_pic") (const_int 0))
2075 (const_int 20)]
2076 (const_int 28)))])
2078 (define_insn ""
2079 [(set (pc)
2080 (if_then_else
2081 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2082 (const_int 1)
2083 (match_operand:DI 1 "uint32_operand" ""))
2084 (const_int 0))
2085 (label_ref (match_operand 2 "" ""))
2086 (pc)))]
2087 "TARGET_64BIT"
2088 "*
2089 {
2090 return output_bb (operands, 0, insn, 1);
2091 }"
2092 [(set_attr "type" "cbranch")
2093 (set (attr "length")
2094 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2095 (const_int MAX_12BIT_OFFSET))
2096 (const_int 4)
2097 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2098 (const_int MAX_17BIT_OFFSET))
2099 (const_int 8)
2100 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2101 (const_int 24)
2102 (eq (symbol_ref "flag_pic") (const_int 0))
2103 (const_int 20)]
2104 (const_int 28)))])
2106 (define_insn ""
2107 [(set (pc)
2108 (if_then_else
2109 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2110 (const_int 1)
2111 (match_operand:SI 1 "uint5_operand" ""))
2112 (const_int 0))
2113 (pc)
2114 (label_ref (match_operand 2 "" ""))))]
2115 ""
2116 "*
2117 {
2118 return output_bb (operands, 1, insn, 1);
2119 }"
2120 [(set_attr "type" "cbranch")
2121 (set (attr "length")
2122 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (const_int MAX_12BIT_OFFSET))
2124 (const_int 4)
2125 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (const_int MAX_17BIT_OFFSET))
2127 (const_int 8)
2128 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2129 (const_int 24)
2130 (eq (symbol_ref "flag_pic") (const_int 0))
2131 (const_int 20)]
2132 (const_int 28)))])
2134 (define_insn ""
2135 [(set (pc)
2136 (if_then_else
2137 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2138 (const_int 1)
2139 (match_operand:DI 1 "uint32_operand" ""))
2140 (const_int 0))
2141 (pc)
2142 (label_ref (match_operand 2 "" ""))))]
2143 "TARGET_64BIT"
2144 "*
2145 {
2146 return output_bb (operands, 1, insn, 1);
2147 }"
2148 [(set_attr "type" "cbranch")
2149 (set (attr "length")
2150 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2151 (const_int MAX_12BIT_OFFSET))
2152 (const_int 4)
2153 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2154 (const_int MAX_17BIT_OFFSET))
2155 (const_int 8)
2156 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2157 (const_int 24)
2158 (eq (symbol_ref "flag_pic") (const_int 0))
2159 (const_int 20)]
2160 (const_int 28)))])
2162 ;; Branch on Variable Bit patterns.
2163 (define_insn ""
2164 [(set (pc)
2165 (if_then_else
2166 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2167 (const_int 1)
2168 (match_operand:SI 1 "register_operand" "q"))
2169 (const_int 0))
2170 (label_ref (match_operand 2 "" ""))
2171 (pc)))]
2172 ""
2173 "*
2174 {
2175 return output_bvb (operands, 0, insn, 0);
2176 }"
2177 [(set_attr "type" "cbranch")
2178 (set (attr "length")
2179 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2180 (const_int MAX_12BIT_OFFSET))
2181 (const_int 4)
2182 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2183 (const_int MAX_17BIT_OFFSET))
2184 (const_int 8)
2185 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2186 (const_int 24)
2187 (eq (symbol_ref "flag_pic") (const_int 0))
2188 (const_int 20)]
2189 (const_int 28)))])
2191 (define_insn ""
2192 [(set (pc)
2193 (if_then_else
2194 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2195 (const_int 1)
2196 (match_operand:DI 1 "register_operand" "q"))
2197 (const_int 0))
2198 (label_ref (match_operand 2 "" ""))
2199 (pc)))]
2200 "TARGET_64BIT"
2201 "*
2202 {
2203 return output_bvb (operands, 0, insn, 0);
2204 }"
2205 [(set_attr "type" "cbranch")
2206 (set (attr "length")
2207 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2208 (const_int MAX_12BIT_OFFSET))
2209 (const_int 4)
2210 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2211 (const_int MAX_17BIT_OFFSET))
2212 (const_int 8)
2213 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2214 (const_int 24)
2215 (eq (symbol_ref "flag_pic") (const_int 0))
2216 (const_int 20)]
2217 (const_int 28)))])
2219 (define_insn ""
2220 [(set (pc)
2221 (if_then_else
2222 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2223 (const_int 1)
2224 (match_operand:SI 1 "register_operand" "q"))
2225 (const_int 0))
2226 (pc)
2227 (label_ref (match_operand 2 "" ""))))]
2228 ""
2229 "*
2230 {
2231 return output_bvb (operands, 1, insn, 0);
2232 }"
2233 [(set_attr "type" "cbranch")
2234 (set (attr "length")
2235 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2236 (const_int MAX_12BIT_OFFSET))
2237 (const_int 4)
2238 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2239 (const_int MAX_17BIT_OFFSET))
2240 (const_int 8)
2241 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2242 (const_int 24)
2243 (eq (symbol_ref "flag_pic") (const_int 0))
2244 (const_int 20)]
2245 (const_int 28)))])
2247 (define_insn ""
2248 [(set (pc)
2249 (if_then_else
2250 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2251 (const_int 1)
2252 (match_operand:DI 1 "register_operand" "q"))
2253 (const_int 0))
2254 (pc)
2255 (label_ref (match_operand 2 "" ""))))]
2256 "TARGET_64BIT"
2257 "*
2258 {
2259 return output_bvb (operands, 1, insn, 0);
2260 }"
2261 [(set_attr "type" "cbranch")
2262 (set (attr "length")
2263 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2264 (const_int MAX_12BIT_OFFSET))
2265 (const_int 4)
2266 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2267 (const_int MAX_17BIT_OFFSET))
2268 (const_int 8)
2269 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2270 (const_int 24)
2271 (eq (symbol_ref "flag_pic") (const_int 0))
2272 (const_int 20)]
2273 (const_int 28)))])
2275 (define_insn ""
2276 [(set (pc)
2277 (if_then_else
2278 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2279 (const_int 1)
2280 (match_operand:SI 1 "register_operand" "q"))
2281 (const_int 0))
2282 (label_ref (match_operand 2 "" ""))
2283 (pc)))]
2284 ""
2285 "*
2286 {
2287 return output_bvb (operands, 0, insn, 1);
2288 }"
2289 [(set_attr "type" "cbranch")
2290 (set (attr "length")
2291 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2292 (const_int MAX_12BIT_OFFSET))
2293 (const_int 4)
2294 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2295 (const_int MAX_17BIT_OFFSET))
2296 (const_int 8)
2297 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2298 (const_int 24)
2299 (eq (symbol_ref "flag_pic") (const_int 0))
2300 (const_int 20)]
2301 (const_int 28)))])
2303 (define_insn ""
2304 [(set (pc)
2305 (if_then_else
2306 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2307 (const_int 1)
2308 (match_operand:DI 1 "register_operand" "q"))
2309 (const_int 0))
2310 (label_ref (match_operand 2 "" ""))
2311 (pc)))]
2312 "TARGET_64BIT"
2313 "*
2314 {
2315 return output_bvb (operands, 0, insn, 1);
2316 }"
2317 [(set_attr "type" "cbranch")
2318 (set (attr "length")
2319 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2320 (const_int MAX_12BIT_OFFSET))
2321 (const_int 4)
2322 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2323 (const_int MAX_17BIT_OFFSET))
2324 (const_int 8)
2325 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2326 (const_int 24)
2327 (eq (symbol_ref "flag_pic") (const_int 0))
2328 (const_int 20)]
2329 (const_int 28)))])
2331 (define_insn ""
2332 [(set (pc)
2333 (if_then_else
2334 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2335 (const_int 1)
2336 (match_operand:SI 1 "register_operand" "q"))
2337 (const_int 0))
2338 (pc)
2339 (label_ref (match_operand 2 "" ""))))]
2340 ""
2341 "*
2342 {
2343 return output_bvb (operands, 1, insn, 1);
2344 }"
2345 [(set_attr "type" "cbranch")
2346 (set (attr "length")
2347 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2348 (const_int MAX_12BIT_OFFSET))
2349 (const_int 4)
2350 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2351 (const_int MAX_17BIT_OFFSET))
2352 (const_int 8)
2353 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2354 (const_int 24)
2355 (eq (symbol_ref "flag_pic") (const_int 0))
2356 (const_int 20)]
2357 (const_int 28)))])
2359 (define_insn ""
2360 [(set (pc)
2361 (if_then_else
2362 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2363 (const_int 1)
2364 (match_operand:DI 1 "register_operand" "q"))
2365 (const_int 0))
2366 (pc)
2367 (label_ref (match_operand 2 "" ""))))]
2368 "TARGET_64BIT"
2369 "*
2370 {
2371 return output_bvb (operands, 1, insn, 1);
2372 }"
2373 [(set_attr "type" "cbranch")
2374 (set (attr "length")
2375 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2376 (const_int MAX_12BIT_OFFSET))
2377 (const_int 4)
2378 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2379 (const_int MAX_17BIT_OFFSET))
2380 (const_int 8)
2381 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2382 (const_int 24)
2383 (eq (symbol_ref "flag_pic") (const_int 0))
2384 (const_int 20)]
2385 (const_int 28)))])
2387 ;; Floating point branches
2389 ;; ??? Nullification is handled differently from other branches.
2390 ;; If nullification is specified, the delay slot is nullified on any
2391 ;; taken branch regardless of branch direction.
2392 (define_insn ""
2393 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2394 (label_ref (match_operand 0 "" ""))
2395 (pc)))]
2396 "!TARGET_SOFT_FLOAT"
2397 "*
2398 {
2399 int length = get_attr_length (insn);
2400 rtx xoperands[1];
2401 int nullify, xdelay;
2403 if (length < 16)
2404 return \"ftest\;b%* %l0\";
2406 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2407 {
2408 nullify = 1;
2409 xdelay = 0;
2410 xoperands[0] = GEN_INT (length - 8);
2411 }
2412 else
2413 {
2414 nullify = 0;
2415 xdelay = 1;
2416 xoperands[0] = GEN_INT (length - 4);
2417 }
2419 if (nullify)
2420 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2421 else
2422 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2423 return output_lbranch (operands[0], insn, xdelay);
2424 }"
2425 [(set_attr "type" "fbranch")
2426 (set (attr "length")
2427 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2428 (const_int MAX_17BIT_OFFSET))
2429 (const_int 8)
2430 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2431 (const_int 32)
2432 (eq (symbol_ref "flag_pic") (const_int 0))
2433 (const_int 28)]
2434 (const_int 36)))])
2436 (define_insn ""
2437 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2438 (pc)
2439 (label_ref (match_operand 0 "" ""))))]
2440 "!TARGET_SOFT_FLOAT"
2441 "*
2442 {
2443 int length = get_attr_length (insn);
2444 rtx xoperands[1];
2445 int nullify, xdelay;
2447 if (length < 16)
2448 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2450 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2451 {
2452 nullify = 1;
2453 xdelay = 0;
2454 xoperands[0] = GEN_INT (length - 4);
2455 }
2456 else
2457 {
2458 nullify = 0;
2459 xdelay = 1;
2460 xoperands[0] = GEN_INT (length);
2461 }
2463 if (nullify)
2464 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2465 else
2466 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2467 return output_lbranch (operands[0], insn, xdelay);
2468 }"
2469 [(set_attr "type" "fbranch")
2470 (set (attr "length")
2471 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2472 (const_int MAX_17BIT_OFFSET))
2473 (const_int 12)
2474 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2475 (const_int 28)
2476 (eq (symbol_ref "flag_pic") (const_int 0))
2477 (const_int 24)]
2478 (const_int 32)))])
2480 ;; Move instructions
2482 (define_expand "movsi"
2483 [(set (match_operand:SI 0 "general_operand" "")
2484 (match_operand:SI 1 "general_operand" ""))]
2485 ""
2486 "
2487 {
2488 if (emit_move_sequence (operands, SImode, 0))
2489 DONE;
2490 }")
2492 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2493 (define_expand "reload_insi_r1"
2494 [(set (match_operand:SI 0 "register_operand" "=Z")
2495 (match_operand:SI 1 "non_hard_reg_operand" ""))
2496 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2497 ""
2498 "
2499 {
2500 if (emit_move_sequence (operands, SImode, operands[2]))
2501 DONE;
2503 /* We don't want the clobber emitted, so handle this ourselves. */
2504 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2505 DONE;
2506 }")
2508 ;; Handle SImode input reloads requiring a general register as a
2509 ;; scratch register.
2510 (define_expand "reload_insi"
2511 [(set (match_operand:SI 0 "register_operand" "=Z")
2512 (match_operand:SI 1 "non_hard_reg_operand" ""))
2513 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2514 ""
2515 "
2516 {
2517 if (emit_move_sequence (operands, SImode, operands[2]))
2518 DONE;
2520 /* We don't want the clobber emitted, so handle this ourselves. */
2521 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2522 DONE;
2523 }")
2525 ;; Handle SImode output reloads requiring a general register as a
2526 ;; scratch register.
2527 (define_expand "reload_outsi"
2528 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2529 (match_operand:SI 1 "register_operand" "Z"))
2530 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2531 ""
2532 "
2533 {
2534 if (emit_move_sequence (operands, SImode, operands[2]))
2535 DONE;
2537 /* We don't want the clobber emitted, so handle this ourselves. */
2538 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2539 DONE;
2540 }")
2542 (define_insn ""
2543 [(set (match_operand:SI 0 "move_dest_operand"
2544 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2545 (match_operand:SI 1 "move_src_operand"
2546 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2547 "(register_operand (operands[0], SImode)
2548 || reg_or_0_operand (operands[1], SImode))
2549 && !TARGET_SOFT_FLOAT
2550 && !TARGET_64BIT"
2551 "@
2552 ldw RT'%A1,%0
2553 copy %1,%0
2554 ldi %1,%0
2555 ldil L'%1,%0
2556 {zdepi|depwi,z} %Z1,%0
2557 ldw%M1 %1,%0
2558 stw%M0 %r1,%0
2559 mtsar %r1
2560 {mfctl|mfctl,w} %%sar,%0
2561 fcpy,sgl %f1,%0
2562 fldw%F1 %1,%0
2563 fstw%F0 %1,%0
2564 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2565 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2566 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2567 (set_attr "pa_combine_type" "addmove")
2568 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2570 (define_insn ""
2571 [(set (match_operand:SI 0 "move_dest_operand"
2572 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2573 (match_operand:SI 1 "move_src_operand"
2574 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2575 "(register_operand (operands[0], SImode)
2576 || reg_or_0_operand (operands[1], SImode))
2577 && !TARGET_SOFT_FLOAT
2578 && TARGET_64BIT"
2579 "@
2580 ldw RT'%A1,%0
2581 copy %1,%0
2582 ldi %1,%0
2583 ldil L'%1,%0
2584 {zdepi|depwi,z} %Z1,%0
2585 ldw%M1 %1,%0
2586 stw%M0 %r1,%0
2587 mtsar %r1
2588 {mfctl|mfctl,w} %%sar,%0
2589 fcpy,sgl %f1,%0
2590 fldw%F1 %1,%0
2591 fstw%F0 %1,%0"
2592 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2593 (set_attr "pa_combine_type" "addmove")
2594 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2596 (define_insn ""
2597 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2598 (match_operand:SI 1 "register_operand" "f"))]
2599 "!TARGET_SOFT_FLOAT
2600 && !TARGET_DISABLE_INDEXING
2601 && reload_completed"
2602 "fstw%F0 %1,%0"
2603 [(set_attr "type" "fpstore")
2604 (set_attr "pa_combine_type" "addmove")
2605 (set_attr "length" "4")])
2607 ; Rewrite RTL using an indexed store. This will allow the insn that
2608 ; computes the address to be deleted if the register it sets is dead.
2609 (define_peephole2
2610 [(set (match_operand:SI 0 "register_operand" "")
2611 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2612 (const_int 4))
2613 (match_operand:SI 2 "register_operand" "")))
2614 (set (mem:SI (match_dup 0))
2615 (match_operand:SI 3 "register_operand" ""))]
2616 "!TARGET_SOFT_FLOAT
2617 && !TARGET_DISABLE_INDEXING
2618 && REG_OK_FOR_BASE_P (operands[2])
2619 && FP_REGNO_P (REGNO (operands[3]))"
2620 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2621 (match_dup 3))
2622 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2623 (match_dup 2)))]
2624 "")
2626 (define_peephole2
2627 [(set (match_operand:SI 0 "register_operand" "")
2628 (plus:SI (match_operand:SI 2 "register_operand" "")
2629 (mult:SI (match_operand:SI 1 "register_operand" "")
2630 (const_int 4))))
2631 (set (mem:SI (match_dup 0))
2632 (match_operand:SI 3 "register_operand" ""))]
2633 "!TARGET_SOFT_FLOAT
2634 && !TARGET_DISABLE_INDEXING
2635 && REG_OK_FOR_BASE_P (operands[2])
2636 && FP_REGNO_P (REGNO (operands[3]))"
2637 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2638 (match_dup 3))
2639 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2640 (match_dup 2)))]
2641 "")
2643 (define_peephole2
2644 [(set (match_operand:DI 0 "register_operand" "")
2645 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2646 (const_int 4))
2647 (match_operand:DI 2 "register_operand" "")))
2648 (set (mem:SI (match_dup 0))
2649 (match_operand:SI 3 "register_operand" ""))]
2650 "!TARGET_SOFT_FLOAT
2651 && !TARGET_DISABLE_INDEXING
2652 && TARGET_64BIT
2653 && REG_OK_FOR_BASE_P (operands[2])
2654 && FP_REGNO_P (REGNO (operands[3]))"
2655 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2656 (match_dup 3))
2657 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2658 (match_dup 2)))]
2659 "")
2661 (define_peephole2
2662 [(set (match_operand:DI 0 "register_operand" "")
2663 (plus:DI (match_operand:DI 2 "register_operand" "")
2664 (mult:DI (match_operand:DI 1 "register_operand" "")
2665 (const_int 4))))
2666 (set (mem:SI (match_dup 0))
2667 (match_operand:SI 3 "register_operand" ""))]
2668 "!TARGET_SOFT_FLOAT
2669 && !TARGET_DISABLE_INDEXING
2670 && TARGET_64BIT
2671 && REG_OK_FOR_BASE_P (operands[2])
2672 && FP_REGNO_P (REGNO (operands[3]))"
2673 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2674 (match_dup 3))
2675 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2676 (match_dup 2)))]
2677 "")
2679 (define_peephole2
2680 [(set (match_operand:SI 0 "register_operand" "")
2681 (plus:SI (match_operand:SI 1 "register_operand" "")
2682 (match_operand:SI 2 "register_operand" "")))
2683 (set (mem:SI (match_dup 0))
2684 (match_operand:SI 3 "register_operand" ""))]
2685 "!TARGET_SOFT_FLOAT
2686 && !TARGET_DISABLE_INDEXING
2687 && TARGET_NO_SPACE_REGS
2688 && REG_OK_FOR_INDEX_P (operands[1])
2689 && REG_OK_FOR_BASE_P (operands[2])
2690 && FP_REGNO_P (REGNO (operands[3]))"
2691 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2692 (match_dup 3))
2693 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2694 "")
2696 (define_peephole2
2697 [(set (match_operand:SI 0 "register_operand" "")
2698 (plus:SI (match_operand:SI 1 "register_operand" "")
2699 (match_operand:SI 2 "register_operand" "")))
2700 (set (mem:SI (match_dup 0))
2701 (match_operand:SI 3 "register_operand" ""))]
2702 "!TARGET_SOFT_FLOAT
2703 && !TARGET_DISABLE_INDEXING
2704 && TARGET_NO_SPACE_REGS
2705 && REG_OK_FOR_BASE_P (operands[1])
2706 && REG_OK_FOR_INDEX_P (operands[2])
2707 && FP_REGNO_P (REGNO (operands[3]))"
2708 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2709 (match_dup 3))
2710 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2711 "")
2713 (define_peephole2
2714 [(set (match_operand:DI 0 "register_operand" "")
2715 (plus:DI (match_operand:DI 1 "register_operand" "")
2716 (match_operand:DI 2 "register_operand" "")))
2717 (set (mem:SI (match_dup 0))
2718 (match_operand:SI 3 "register_operand" ""))]
2719 "!TARGET_SOFT_FLOAT
2720 && !TARGET_DISABLE_INDEXING
2721 && TARGET_64BIT
2722 && TARGET_NO_SPACE_REGS
2723 && REG_OK_FOR_INDEX_P (operands[1])
2724 && REG_OK_FOR_BASE_P (operands[2])
2725 && FP_REGNO_P (REGNO (operands[3]))"
2726 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2727 (match_dup 3))
2728 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2729 "")
2731 (define_peephole2
2732 [(set (match_operand:DI 0 "register_operand" "")
2733 (plus:DI (match_operand:DI 1 "register_operand" "")
2734 (match_operand:DI 2 "register_operand" "")))
2735 (set (mem:SI (match_dup 0))
2736 (match_operand:SI 3 "register_operand" ""))]
2737 "!TARGET_SOFT_FLOAT
2738 && !TARGET_DISABLE_INDEXING
2739 && TARGET_64BIT
2740 && TARGET_NO_SPACE_REGS
2741 && REG_OK_FOR_BASE_P (operands[1])
2742 && REG_OK_FOR_INDEX_P (operands[2])
2743 && FP_REGNO_P (REGNO (operands[3]))"
2744 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2745 (match_dup 3))
2746 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2747 "")
2749 (define_insn ""
2750 [(set (match_operand:SI 0 "move_dest_operand"
2751 "=r,r,r,r,r,r,Q,!*q,!r")
2752 (match_operand:SI 1 "move_src_operand"
2753 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2754 "(register_operand (operands[0], SImode)
2755 || reg_or_0_operand (operands[1], SImode))
2756 && TARGET_SOFT_FLOAT"
2757 "@
2758 ldw RT'%A1,%0
2759 copy %1,%0
2760 ldi %1,%0
2761 ldil L'%1,%0
2762 {zdepi|depwi,z} %Z1,%0
2763 ldw%M1 %1,%0
2764 stw%M0 %r1,%0
2765 mtsar %r1
2766 {mfctl|mfctl,w} %%sar,%0"
2767 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2768 (set_attr "pa_combine_type" "addmove")
2769 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2771 ;; Load or store with base-register modification.
2772 (define_insn ""
2773 [(set (match_operand:SI 0 "register_operand" "=r")
2774 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2775 (match_operand:DI 2 "int5_operand" "L"))))
2776 (set (match_dup 1)
2777 (plus:DI (match_dup 1) (match_dup 2)))]
2778 "TARGET_64BIT"
2779 "ldw,mb %2(%1),%0"
2780 [(set_attr "type" "load")
2781 (set_attr "length" "4")])
2783 ; And a zero extended variant.
2784 (define_insn ""
2785 [(set (match_operand:DI 0 "register_operand" "=r")
2786 (zero_extend:DI (mem:SI
2787 (plus:DI
2788 (match_operand:DI 1 "register_operand" "+r")
2789 (match_operand:DI 2 "int5_operand" "L")))))
2790 (set (match_dup 1)
2791 (plus:DI (match_dup 1) (match_dup 2)))]
2792 "TARGET_64BIT"
2793 "ldw,mb %2(%1),%0"
2794 [(set_attr "type" "load")
2795 (set_attr "length" "4")])
2797 (define_expand "pre_load"
2798 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2799 (mem (plus (match_operand 1 "register_operand" "")
2800 (match_operand 2 "pre_cint_operand" ""))))
2801 (set (match_dup 1)
2802 (plus (match_dup 1) (match_dup 2)))])]
2803 ""
2804 "
2805 {
2806 if (TARGET_64BIT)
2807 {
2808 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2809 DONE;
2810 }
2811 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2812 DONE;
2813 }")
2815 (define_insn "pre_ldw"
2816 [(set (match_operand:SI 0 "register_operand" "=r")
2817 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2818 (match_operand:SI 2 "pre_cint_operand" ""))))
2819 (set (match_dup 1)
2820 (plus:SI (match_dup 1) (match_dup 2)))]
2821 ""
2822 "*
2823 {
2824 if (INTVAL (operands[2]) < 0)
2825 return \"{ldwm|ldw,mb} %2(%1),%0\";
2826 return \"{ldws|ldw},mb %2(%1),%0\";
2827 }"
2828 [(set_attr "type" "load")
2829 (set_attr "length" "4")])
2831 (define_insn "pre_ldd"
2832 [(set (match_operand:DI 0 "register_operand" "=r")
2833 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2834 (match_operand:DI 2 "pre_cint_operand" ""))))
2835 (set (match_dup 1)
2836 (plus:DI (match_dup 1) (match_dup 2)))]
2837 "TARGET_64BIT"
2838 "ldd,mb %2(%1),%0"
2839 [(set_attr "type" "load")
2840 (set_attr "length" "4")])
2842 (define_insn ""
2843 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2844 (match_operand:SI 1 "pre_cint_operand" "")))
2845 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2846 (set (match_dup 0)
2847 (plus:SI (match_dup 0) (match_dup 1)))]
2848 ""
2849 "*
2850 {
2851 if (INTVAL (operands[1]) < 0)
2852 return \"{stwm|stw,mb} %r2,%1(%0)\";
2853 return \"{stws|stw},mb %r2,%1(%0)\";
2854 }"
2855 [(set_attr "type" "store")
2856 (set_attr "length" "4")])
2858 (define_insn ""
2859 [(set (match_operand:SI 0 "register_operand" "=r")
2860 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2861 (set (match_dup 1)
2862 (plus:SI (match_dup 1)
2863 (match_operand:SI 2 "post_cint_operand" "")))]
2864 ""
2865 "*
2866 {
2867 if (INTVAL (operands[2]) > 0)
2868 return \"{ldwm|ldw,ma} %2(%1),%0\";
2869 return \"{ldws|ldw},ma %2(%1),%0\";
2870 }"
2871 [(set_attr "type" "load")
2872 (set_attr "length" "4")])
2874 (define_expand "post_store"
2875 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2876 (match_operand 1 "reg_or_0_operand" ""))
2877 (set (match_dup 0)
2878 (plus (match_dup 0)
2879 (match_operand 2 "post_cint_operand" "")))])]
2880 ""
2881 "
2882 {
2883 if (TARGET_64BIT)
2884 {
2885 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2886 DONE;
2887 }
2888 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2889 DONE;
2890 }")
2892 (define_insn "post_stw"
2893 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2894 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2895 (set (match_dup 0)
2896 (plus:SI (match_dup 0)
2897 (match_operand:SI 2 "post_cint_operand" "")))]
2898 ""
2899 "*
2900 {
2901 if (INTVAL (operands[2]) > 0)
2902 return \"{stwm|stw,ma} %r1,%2(%0)\";
2903 return \"{stws|stw},ma %r1,%2(%0)\";
2904 }"
2905 [(set_attr "type" "store")
2906 (set_attr "length" "4")])
2908 (define_insn "post_std"
2909 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2910 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2911 (set (match_dup 0)
2912 (plus:DI (match_dup 0)
2913 (match_operand:DI 2 "post_cint_operand" "")))]
2914 "TARGET_64BIT"
2915 "std,ma %r1,%2(%0)"
2916 [(set_attr "type" "store")
2917 (set_attr "length" "4")])
2919 ;; For loading the address of a label while generating PIC code.
2920 ;; Note since this pattern can be created at reload time (via movsi), all
2921 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2922 (define_insn ""
2923 [(set (match_operand 0 "pmode_register_operand" "=a")
2924 (match_operand 1 "pic_label_operand" ""))]
2925 "TARGET_PA_20"
2926 "*
2927 {
2928 rtx xoperands[3];
2930 xoperands[0] = operands[0];
2931 xoperands[1] = operands[1];
2932 xoperands[2] = gen_label_rtx ();
2934 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2935 CODE_LABEL_NUMBER (xoperands[2]));
2936 output_asm_insn (\"mfia %0\", xoperands);
2938 /* If we're trying to load the address of a label that happens to be
2939 close, then we can use a shorter sequence. */
2940 if (GET_CODE (operands[1]) == LABEL_REF
2941 && !LABEL_REF_NONLOCAL_P (operands[1])
2942 && INSN_ADDRESSES_SET_P ()
2943 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2944 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2945 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2946 else
2947 {
2948 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2949 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2950 }
2951 return \"\";
2952 }"
2953 [(set_attr "type" "multi")
2954 (set_attr "length" "12")]) ; 8 or 12
2956 (define_insn ""
2957 [(set (match_operand 0 "pmode_register_operand" "=a")
2958 (match_operand 1 "pic_label_operand" ""))]
2959 "!TARGET_PA_20"
2960 "*
2961 {
2962 rtx xoperands[3];
2964 xoperands[0] = operands[0];
2965 xoperands[1] = operands[1];
2966 xoperands[2] = gen_label_rtx ();
2968 output_asm_insn (\"bl .+8,%0\", xoperands);
2969 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2970 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2971 CODE_LABEL_NUMBER (xoperands[2]));
2973 /* If we're trying to load the address of a label that happens to be
2974 close, then we can use a shorter sequence. */
2975 if (GET_CODE (operands[1]) == LABEL_REF
2976 && !LABEL_REF_NONLOCAL_P (operands[1])
2977 && INSN_ADDRESSES_SET_P ()
2978 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2979 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2980 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2981 else
2982 {
2983 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2984 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2985 }
2986 return \"\";
2987 }"
2988 [(set_attr "type" "multi")
2989 (set_attr "length" "16")]) ; 12 or 16
2991 (define_insn ""
2992 [(set (match_operand:SI 0 "register_operand" "=a")
2993 (plus:SI (match_operand:SI 1 "register_operand" "r")
2994 (high:SI (match_operand 2 "" ""))))]
2995 "symbolic_operand (operands[2], Pmode)
2996 && ! function_label_operand (operands[2], Pmode)
2997 && flag_pic"
2998 "addil LT'%G2,%1"
2999 [(set_attr "type" "binary")
3000 (set_attr "length" "4")])
3002 (define_insn ""
3003 [(set (match_operand:DI 0 "register_operand" "=a")
3004 (plus:DI (match_operand:DI 1 "register_operand" "r")
3005 (high:DI (match_operand 2 "" ""))))]
3006 "symbolic_operand (operands[2], Pmode)
3007 && ! function_label_operand (operands[2], Pmode)
3008 && TARGET_64BIT
3009 && flag_pic"
3010 "addil LT'%G2,%1"
3011 [(set_attr "type" "binary")
3012 (set_attr "length" "4")])
3014 ;; Always use addil rather than ldil;add sequences. This allows the
3015 ;; HP linker to eliminate the dp relocation if the symbolic operand
3016 ;; lives in the TEXT space.
3017 (define_insn ""
3018 [(set (match_operand:SI 0 "register_operand" "=a")
3019 (high:SI (match_operand 1 "" "")))]
3020 "symbolic_operand (operands[1], Pmode)
3021 && ! function_label_operand (operands[1], Pmode)
3022 && ! read_only_operand (operands[1], Pmode)
3023 && ! flag_pic"
3024 "*
3025 {
3026 if (TARGET_LONG_LOAD_STORE)
3027 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
3028 else
3029 return \"addil LR'%H1,%%r27\";
3030 }"
3031 [(set_attr "type" "binary")
3032 (set (attr "length")
3033 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
3034 (const_int 4)
3035 (const_int 8)))])
3038 ;; This is for use in the prologue/epilogue code. We need it
3039 ;; to add large constants to a stack pointer or frame pointer.
3040 ;; Because of the additional %r1 pressure, we probably do not
3041 ;; want to use this in general code, so make it available
3042 ;; only after reload.
3043 (define_insn ""
3044 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
3045 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
3046 (high:SI (match_operand 2 "const_int_operand" ""))))]
3047 "reload_completed"
3048 "@
3049 addil L'%G2,%1
3050 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3051 [(set_attr "type" "binary,binary")
3052 (set_attr "length" "4,8")])
3054 (define_insn ""
3055 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
3056 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
3057 (high:DI (match_operand 2 "const_int_operand" ""))))]
3058 "reload_completed && TARGET_64BIT"
3059 "@
3060 addil L'%G2,%1
3061 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3062 [(set_attr "type" "binary,binary")
3063 (set_attr "length" "4,8")])
3065 (define_insn ""
3066 [(set (match_operand:SI 0 "register_operand" "=r")
3067 (high:SI (match_operand 1 "" "")))]
3068 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3069 && !is_function_label_plus_const (operands[1])"
3070 "*
3071 {
3072 if (symbolic_operand (operands[1], Pmode))
3073 return \"ldil LR'%H1,%0\";
3074 else
3075 return \"ldil L'%G1,%0\";
3076 }"
3077 [(set_attr "type" "move")
3078 (set_attr "length" "4")])
3080 (define_insn ""
3081 [(set (match_operand:DI 0 "register_operand" "=r")
3082 (high:DI (match_operand 1 "const_int_operand" "")))]
3083 "TARGET_64BIT"
3084 "ldil L'%G1,%0";
3085 [(set_attr "type" "move")
3086 (set_attr "length" "4")])
3088 (define_insn ""
3089 [(set (match_operand:DI 0 "register_operand" "=r")
3090 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3091 (match_operand:DI 2 "const_int_operand" "i")))]
3092 "TARGET_64BIT"
3093 "ldo R'%G2(%1),%0";
3094 [(set_attr "type" "move")
3095 (set_attr "length" "4")])
3097 (define_insn ""
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3100 (match_operand:SI 2 "immediate_operand" "i")))]
3101 "!is_function_label_plus_const (operands[2])"
3102 "*
3103 {
3104 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3106 if (symbolic_operand (operands[2], Pmode))
3107 return \"ldo RR'%G2(%1),%0\";
3108 else
3109 return \"ldo R'%G2(%1),%0\";
3110 }"
3111 [(set_attr "type" "move")
3112 (set_attr "length" "4")])
3114 ;; Now that a symbolic_address plus a constant is broken up early
3115 ;; in the compilation phase (for better CSE) we need a special
3116 ;; combiner pattern to load the symbolic address plus the constant
3117 ;; in only 2 instructions. (For cases where the symbolic address
3118 ;; was not a common subexpression.)
3119 (define_split
3120 [(set (match_operand:SI 0 "register_operand" "")
3121 (match_operand:SI 1 "symbolic_operand" ""))
3122 (clobber (match_operand:SI 2 "register_operand" ""))]
3123 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3124 [(set (match_dup 2) (high:SI (match_dup 1)))
3125 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3126 "")
3128 ;; hppa_legitimize_address goes to a great deal of trouble to
3129 ;; create addresses which use indexing. In some cases, this
3130 ;; is a lose because there isn't any store instructions which
3131 ;; allow indexed addresses (with integer register source).
3132 ;;
3133 ;; These define_splits try to turn a 3 insn store into
3134 ;; a 2 insn store with some creative RTL rewriting.
3135 (define_split
3136 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3137 (match_operand:SI 1 "shadd_operand" ""))
3138 (plus:SI (match_operand:SI 2 "register_operand" "")
3139 (match_operand:SI 3 "const_int_operand" ""))))
3140 (match_operand:SI 4 "register_operand" ""))
3141 (clobber (match_operand:SI 5 "register_operand" ""))]
3142 ""
3143 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3144 (match_dup 2)))
3145 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3146 "")
3148 (define_split
3149 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3150 (match_operand:SI 1 "shadd_operand" ""))
3151 (plus:SI (match_operand:SI 2 "register_operand" "")
3152 (match_operand:SI 3 "const_int_operand" ""))))
3153 (match_operand:HI 4 "register_operand" ""))
3154 (clobber (match_operand:SI 5 "register_operand" ""))]
3155 ""
3156 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3157 (match_dup 2)))
3158 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3159 "")
3161 (define_split
3162 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3163 (match_operand:SI 1 "shadd_operand" ""))
3164 (plus:SI (match_operand:SI 2 "register_operand" "")
3165 (match_operand:SI 3 "const_int_operand" ""))))
3166 (match_operand:QI 4 "register_operand" ""))
3167 (clobber (match_operand:SI 5 "register_operand" ""))]
3168 ""
3169 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3170 (match_dup 2)))
3171 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3172 "")
3174 (define_expand "movhi"
3175 [(set (match_operand:HI 0 "general_operand" "")
3176 (match_operand:HI 1 "general_operand" ""))]
3177 ""
3178 "
3179 {
3180 if (emit_move_sequence (operands, HImode, 0))
3181 DONE;
3182 }")
3184 ;; Handle HImode input reloads requiring a general register as a
3185 ;; scratch register.
3186 (define_expand "reload_inhi"
3187 [(set (match_operand:HI 0 "register_operand" "=Z")
3188 (match_operand:HI 1 "non_hard_reg_operand" ""))
3189 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
3190 ""
3191 "
3192 {
3193 if (emit_move_sequence (operands, HImode, operands[2]))
3194 DONE;
3196 /* We don't want the clobber emitted, so handle this ourselves. */
3197 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3198 DONE;
3199 }")
3201 ;; Handle HImode output reloads requiring a general register as a
3202 ;; scratch register.
3203 (define_expand "reload_outhi"
3204 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
3205 (match_operand:HI 1 "register_operand" "Z"))
3206 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
3207 ""
3208 "
3209 {
3210 if (emit_move_sequence (operands, HImode, operands[2]))
3211 DONE;
3213 /* We don't want the clobber emitted, so handle this ourselves. */
3214 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3215 DONE;
3216 }")
3218 (define_insn ""
3219 [(set (match_operand:HI 0 "move_dest_operand"
3220 "=r,r,r,r,r,Q,!*q,!r")
3221 (match_operand:HI 1 "move_src_operand"
3222 "r,J,N,K,RQ,rM,!rM,!*q"))]
3223 "(register_operand (operands[0], HImode)
3224 || reg_or_0_operand (operands[1], HImode))"
3225 "@
3226 copy %1,%0
3227 ldi %1,%0
3228 ldil L'%1,%0
3229 {zdepi|depwi,z} %Z1,%0
3230 ldh%M1 %1,%0
3231 sth%M0 %r1,%0
3232 mtsar %r1
3233 {mfctl|mfctl,w} %sar,%0"
3234 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3235 (set_attr "pa_combine_type" "addmove")
3236 (set_attr "length" "4,4,4,4,4,4,4,4")])
3238 (define_insn ""
3239 [(set (match_operand:HI 0 "register_operand" "=r")
3240 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3241 (match_operand:SI 2 "int5_operand" "L"))))
3242 (set (match_dup 1)
3243 (plus:SI (match_dup 1) (match_dup 2)))]
3244 ""
3245 "{ldhs|ldh},mb %2(%1),%0"
3246 [(set_attr "type" "load")
3247 (set_attr "length" "4")])
3249 (define_insn ""
3250 [(set (match_operand:HI 0 "register_operand" "=r")
3251 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3252 (match_operand:DI 2 "int5_operand" "L"))))
3253 (set (match_dup 1)
3254 (plus:DI (match_dup 1) (match_dup 2)))]
3255 "TARGET_64BIT"
3256 "ldh,mb %2(%1),%0"
3257 [(set_attr "type" "load")
3258 (set_attr "length" "4")])
3260 ; And a zero extended variant.
3261 (define_insn ""
3262 [(set (match_operand:DI 0 "register_operand" "=r")
3263 (zero_extend:DI (mem:HI
3264 (plus:DI
3265 (match_operand:DI 1 "register_operand" "+r")
3266 (match_operand:DI 2 "int5_operand" "L")))))
3267 (set (match_dup 1)
3268 (plus:DI (match_dup 1) (match_dup 2)))]
3269 "TARGET_64BIT"
3270 "ldh,mb %2(%1),%0"
3271 [(set_attr "type" "load")
3272 (set_attr "length" "4")])
3274 (define_insn ""
3275 [(set (match_operand:SI 0 "register_operand" "=r")
3276 (zero_extend:SI (mem:HI
3277 (plus:SI
3278 (match_operand:SI 1 "register_operand" "+r")
3279 (match_operand:SI 2 "int5_operand" "L")))))
3280 (set (match_dup 1)
3281 (plus:SI (match_dup 1) (match_dup 2)))]
3282 ""
3283 "{ldhs|ldh},mb %2(%1),%0"
3284 [(set_attr "type" "load")
3285 (set_attr "length" "4")])
3287 (define_insn ""
3288 [(set (match_operand:SI 0 "register_operand" "=r")
3289 (zero_extend:SI (mem:HI
3290 (plus:DI
3291 (match_operand:DI 1 "register_operand" "+r")
3292 (match_operand:DI 2 "int5_operand" "L")))))
3293 (set (match_dup 1)
3294 (plus:DI (match_dup 1) (match_dup 2)))]
3295 "TARGET_64BIT"
3296 "ldh,mb %2(%1),%0"
3297 [(set_attr "type" "load")
3298 (set_attr "length" "4")])
3300 (define_insn ""
3301 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3302 (match_operand:SI 1 "int5_operand" "L")))
3303 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3304 (set (match_dup 0)
3305 (plus:SI (match_dup 0) (match_dup 1)))]
3306 ""
3307 "{sths|sth},mb %r2,%1(%0)"
3308 [(set_attr "type" "store")
3309 (set_attr "length" "4")])
3311 (define_insn ""
3312 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3313 (match_operand:DI 1 "int5_operand" "L")))
3314 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3315 (set (match_dup 0)
3316 (plus:DI (match_dup 0) (match_dup 1)))]
3317 "TARGET_64BIT"
3318 "sth,mb %r2,%1(%0)"
3319 [(set_attr "type" "store")
3320 (set_attr "length" "4")])
3322 (define_insn ""
3323 [(set (match_operand:HI 0 "register_operand" "=r")
3324 (plus:HI (match_operand:HI 1 "register_operand" "r")
3325 (match_operand 2 "const_int_operand" "J")))]
3326 ""
3327 "ldo %2(%1),%0"
3328 [(set_attr "type" "binary")
3329 (set_attr "pa_combine_type" "addmove")
3330 (set_attr "length" "4")])
3332 (define_expand "movqi"
3333 [(set (match_operand:QI 0 "general_operand" "")
3334 (match_operand:QI 1 "general_operand" ""))]
3335 ""
3336 "
3337 {
3338 if (emit_move_sequence (operands, QImode, 0))
3339 DONE;
3340 }")
3342 ;; Handle QImode input reloads requiring a general register as a
3343 ;; scratch register.
3344 (define_expand "reload_inqi"
3345 [(set (match_operand:QI 0 "register_operand" "=Z")
3346 (match_operand:QI 1 "non_hard_reg_operand" ""))
3347 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3348 ""
3349 "
3350 {
3351 if (emit_move_sequence (operands, QImode, operands[2]))
3352 DONE;
3354 /* We don't want the clobber emitted, so handle this ourselves. */
3355 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3356 DONE;
3357 }")
3359 ;; Handle QImode output reloads requiring a general register as a
3360 ;; scratch register.
3361 (define_expand "reload_outqi"
3362 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
3363 (match_operand:QI 1 "register_operand" "Z"))
3364 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3365 ""
3366 "
3367 {
3368 if (emit_move_sequence (operands, QImode, operands[2]))
3369 DONE;
3371 /* We don't want the clobber emitted, so handle this ourselves. */
3372 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3373 DONE;
3374 }")
3376 (define_insn ""
3377 [(set (match_operand:QI 0 "move_dest_operand"
3378 "=r,r,r,r,r,Q,!*q,!r")
3379 (match_operand:QI 1 "move_src_operand"
3380 "r,J,N,K,RQ,rM,!rM,!*q"))]
3381 "(register_operand (operands[0], QImode)
3382 || reg_or_0_operand (operands[1], QImode))"
3383 "@
3384 copy %1,%0
3385 ldi %1,%0
3386 ldil L'%1,%0
3387 {zdepi|depwi,z} %Z1,%0
3388 ldb%M1 %1,%0
3389 stb%M0 %r1,%0
3390 mtsar %r1
3391 {mfctl|mfctl,w} %%sar,%0"
3392 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3393 (set_attr "pa_combine_type" "addmove")
3394 (set_attr "length" "4,4,4,4,4,4,4,4")])
3396 (define_insn ""
3397 [(set (match_operand:QI 0 "register_operand" "=r")
3398 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3399 (match_operand:SI 2 "int5_operand" "L"))))
3400 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3401 ""
3402 "{ldbs|ldb},mb %2(%1),%0"
3403 [(set_attr "type" "load")
3404 (set_attr "length" "4")])
3406 (define_insn ""
3407 [(set (match_operand:QI 0 "register_operand" "=r")
3408 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3409 (match_operand:DI 2 "int5_operand" "L"))))
3410 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3411 "TARGET_64BIT"
3412 "ldb,mb %2(%1),%0"
3413 [(set_attr "type" "load")
3414 (set_attr "length" "4")])
3416 ; Now the same thing with zero extensions.
3417 (define_insn ""
3418 [(set (match_operand:DI 0 "register_operand" "=r")
3419 (zero_extend:DI (mem:QI (plus:DI
3420 (match_operand:DI 1 "register_operand" "+r")
3421 (match_operand:DI 2 "int5_operand" "L")))))
3422 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3423 "TARGET_64BIT"
3424 "ldb,mb %2(%1),%0"
3425 [(set_attr "type" "load")
3426 (set_attr "length" "4")])
3428 (define_insn ""
3429 [(set (match_operand:SI 0 "register_operand" "=r")
3430 (zero_extend:SI (mem:QI (plus:SI
3431 (match_operand:SI 1 "register_operand" "+r")
3432 (match_operand:SI 2 "int5_operand" "L")))))
3433 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3434 ""
3435 "{ldbs|ldb},mb %2(%1),%0"
3436 [(set_attr "type" "load")
3437 (set_attr "length" "4")])
3439 (define_insn ""
3440 [(set (match_operand:SI 0 "register_operand" "=r")
3441 (zero_extend:SI (mem:QI (plus:DI
3442 (match_operand:DI 1 "register_operand" "+r")
3443 (match_operand:DI 2 "int5_operand" "L")))))
3444 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3445 "TARGET_64BIT"
3446 "ldb,mb %2(%1),%0"
3447 [(set_attr "type" "load")
3448 (set_attr "length" "4")])
3450 (define_insn ""
3451 [(set (match_operand:HI 0 "register_operand" "=r")
3452 (zero_extend:HI (mem:QI (plus:SI
3453 (match_operand:SI 1 "register_operand" "+r")
3454 (match_operand:SI 2 "int5_operand" "L")))))
3455 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3456 ""
3457 "{ldbs|ldb},mb %2(%1),%0"
3458 [(set_attr "type" "load")
3459 (set_attr "length" "4")])
3461 (define_insn ""
3462 [(set (match_operand:HI 0 "register_operand" "=r")
3463 (zero_extend:HI (mem:QI (plus:DI
3464 (match_operand:DI 1 "register_operand" "+r")
3465 (match_operand:DI 2 "int5_operand" "L")))))
3466 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3467 "TARGET_64BIT"
3468 "ldb,mb %2(%1),%0"
3469 [(set_attr "type" "load")
3470 (set_attr "length" "4")])
3472 (define_insn ""
3473 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3474 (match_operand:SI 1 "int5_operand" "L")))
3475 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3476 (set (match_dup 0)
3477 (plus:SI (match_dup 0) (match_dup 1)))]
3478 ""
3479 "{stbs|stb},mb %r2,%1(%0)"
3480 [(set_attr "type" "store")
3481 (set_attr "length" "4")])
3483 (define_insn ""
3484 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3485 (match_operand:DI 1 "int5_operand" "L")))
3486 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3487 (set (match_dup 0)
3488 (plus:DI (match_dup 0) (match_dup 1)))]
3489 "TARGET_64BIT"
3490 "stb,mb %r2,%1(%0)"
3491 [(set_attr "type" "store")
3492 (set_attr "length" "4")])
3494 ;; The definition of this insn does not really explain what it does,
3495 ;; but it should suffice that anything generated as this insn will be
3496 ;; recognized as a movmemsi operation, and that it will not successfully
3497 ;; combine with anything.
3498 (define_expand "movmemsi"
3499 [(parallel [(set (match_operand:BLK 0 "" "")
3500 (match_operand:BLK 1 "" ""))
3501 (clobber (match_dup 4))
3502 (clobber (match_dup 5))
3503 (clobber (match_dup 6))
3504 (clobber (match_dup 7))
3505 (clobber (match_dup 8))
3506 (use (match_operand:SI 2 "arith_operand" ""))
3507 (use (match_operand:SI 3 "const_int_operand" ""))])]
3508 "!TARGET_64BIT && optimize > 0"
3509 "
3510 {
3511 int size, align;
3513 /* HP provides very fast block move library routine for the PA;
3514 this routine includes:
3516 4x4 byte at a time block moves,
3517 1x4 byte at a time with alignment checked at runtime with
3518 attempts to align the source and destination as needed
3519 1x1 byte loop
3521 With that in mind, here's the heuristics to try and guess when
3522 the inlined block move will be better than the library block
3523 move:
3525 If the size isn't constant, then always use the library routines.
3527 If the size is large in respect to the known alignment, then use
3528 the library routines.
3530 If the size is small in respect to the known alignment, then open
3531 code the copy (since that will lead to better scheduling).
3533 Else use the block move pattern. */
3535 /* Undetermined size, use the library routine. */
3536 if (GET_CODE (operands[2]) != CONST_INT)
3537 FAIL;
3539 size = INTVAL (operands[2]);
3540 align = INTVAL (operands[3]);
3541 align = align > 4 ? 4 : (align ? align : 1);
3543 /* If size/alignment is large, then use the library routines. */
3544 if (size / align > 16)
3545 FAIL;
3547 /* This does happen, but not often enough to worry much about. */
3548 if (size / align < MOVE_RATIO)
3549 FAIL;
3551 /* Fall through means we're going to use our block move pattern. */
3552 operands[0]
3553 = replace_equiv_address (operands[0],
3554 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3555 operands[1]
3556 = replace_equiv_address (operands[1],
3557 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3558 operands[4] = gen_reg_rtx (SImode);
3559 operands[5] = gen_reg_rtx (SImode);
3560 operands[6] = gen_reg_rtx (SImode);
3561 operands[7] = gen_reg_rtx (SImode);
3562 operands[8] = gen_reg_rtx (SImode);
3563 }")
3565 ;; The operand constraints are written like this to support both compile-time
3566 ;; and run-time determined byte counts. The expander and output_block_move
3567 ;; only support compile-time determined counts at this time.
3568 ;;
3569 ;; If the count is run-time determined, the register with the byte count
3570 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3571 ;;
3572 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3573 ;; broke this semantic for pseudo registers. We can't use match_scratch
3574 ;; as this requires two registers in the class R1_REGS when the MEMs for
3575 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3576 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3577 ;; respectively. We then split or peephole optimize after reload.
3578 (define_insn "movmemsi_prereload"
3579 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3580 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3581 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3582 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3583 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3584 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3585 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3586 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3587 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3588 "!TARGET_64BIT"
3589 "#"
3590 [(set_attr "type" "multi,multi")])
3592 (define_split
3593 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3594 (match_operand:BLK 1 "memory_operand" ""))
3595 (clobber (match_operand:SI 2 "register_operand" ""))
3596 (clobber (match_operand:SI 3 "register_operand" ""))
3597 (clobber (match_operand:SI 6 "register_operand" ""))
3598 (clobber (match_operand:SI 7 "register_operand" ""))
3599 (clobber (match_operand:SI 8 "register_operand" ""))
3600 (use (match_operand:SI 4 "arith_operand" ""))
3601 (use (match_operand:SI 5 "const_int_operand" ""))])]
3602 "!TARGET_64BIT && reload_completed && !flag_peephole2
3603 && GET_CODE (operands[0]) == MEM
3604 && register_operand (XEXP (operands[0], 0), SImode)
3605 && GET_CODE (operands[1]) == MEM
3606 && register_operand (XEXP (operands[1], 0), SImode)"
3607 [(set (match_dup 7) (match_dup 9))
3608 (set (match_dup 8) (match_dup 10))
3609 (parallel [(set (match_dup 0) (match_dup 1))
3610 (clobber (match_dup 2))
3611 (clobber (match_dup 3))
3612 (clobber (match_dup 6))
3613 (clobber (match_dup 7))
3614 (clobber (match_dup 8))
3615 (use (match_dup 4))
3616 (use (match_dup 5))
3617 (const_int 0)])]
3618 "
3619 {
3620 operands[9] = XEXP (operands[0], 0);
3621 operands[10] = XEXP (operands[1], 0);
3622 operands[0] = replace_equiv_address (operands[0], operands[7]);
3623 operands[1] = replace_equiv_address (operands[1], operands[8]);
3624 }")
3626 (define_peephole2
3627 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3628 (match_operand:BLK 1 "memory_operand" ""))
3629 (clobber (match_operand:SI 2 "register_operand" ""))
3630 (clobber (match_operand:SI 3 "register_operand" ""))
3631 (clobber (match_operand:SI 6 "register_operand" ""))
3632 (clobber (match_operand:SI 7 "register_operand" ""))
3633 (clobber (match_operand:SI 8 "register_operand" ""))
3634 (use (match_operand:SI 4 "arith_operand" ""))
3635 (use (match_operand:SI 5 "const_int_operand" ""))])]
3636 "!TARGET_64BIT
3637 && GET_CODE (operands[0]) == MEM
3638 && register_operand (XEXP (operands[0], 0), SImode)
3639 && GET_CODE (operands[1]) == MEM
3640 && register_operand (XEXP (operands[1], 0), SImode)"
3641 [(parallel [(set (match_dup 0) (match_dup 1))
3642 (clobber (match_dup 2))
3643 (clobber (match_dup 3))
3644 (clobber (match_dup 6))
3645 (clobber (match_dup 7))
3646 (clobber (match_dup 8))
3647 (use (match_dup 4))
3648 (use (match_dup 5))
3649 (const_int 0)])]
3650 "
3651 {
3652 rtx addr = XEXP (operands[0], 0);
3653 if (dead_or_set_p (curr_insn, addr))
3654 operands[7] = addr;
3655 else
3656 {
3657 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3658 operands[0] = replace_equiv_address (operands[0], operands[7]);
3659 }
3661 addr = XEXP (operands[1], 0);
3662 if (dead_or_set_p (curr_insn, addr))
3663 operands[8] = addr;
3664 else
3665 {
3666 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3667 operands[1] = replace_equiv_address (operands[1], operands[8]);
3668 }
3669 }")
3671 (define_insn "movmemsi_postreload"
3672 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3673 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3674 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3675 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3676 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3677 (clobber (match_dup 0))
3678 (clobber (match_dup 1))
3679 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3680 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3681 (const_int 0)]
3682 "!TARGET_64BIT && reload_completed"
3683 "* return output_block_move (operands, !which_alternative);"
3684 [(set_attr "type" "multi,multi")])
3686 (define_expand "movmemdi"
3687 [(parallel [(set (match_operand:BLK 0 "" "")
3688 (match_operand:BLK 1 "" ""))
3689 (clobber (match_dup 4))
3690 (clobber (match_dup 5))
3691 (clobber (match_dup 6))
3692 (clobber (match_dup 7))
3693 (clobber (match_dup 8))
3694 (use (match_operand:DI 2 "arith_operand" ""))
3695 (use (match_operand:DI 3 "const_int_operand" ""))])]
3696 "TARGET_64BIT && optimize > 0"
3697 "
3698 {
3699 int size, align;
3701 /* HP provides very fast block move library routine for the PA;
3702 this routine includes:
3704 4x4 byte at a time block moves,
3705 1x4 byte at a time with alignment checked at runtime with
3706 attempts to align the source and destination as needed
3707 1x1 byte loop
3709 With that in mind, here's the heuristics to try and guess when
3710 the inlined block move will be better than the library block
3711 move:
3713 If the size isn't constant, then always use the library routines.
3715 If the size is large in respect to the known alignment, then use
3716 the library routines.
3718 If the size is small in respect to the known alignment, then open
3719 code the copy (since that will lead to better scheduling).
3721 Else use the block move pattern. */
3723 /* Undetermined size, use the library routine. */
3724 if (GET_CODE (operands[2]) != CONST_INT)
3725 FAIL;
3727 size = INTVAL (operands[2]);
3728 align = INTVAL (operands[3]);
3729 align = align > 8 ? 8 : (align ? align : 1);
3731 /* If size/alignment is large, then use the library routines. */
3732 if (size / align > 16)
3733 FAIL;
3735 /* This does happen, but not often enough to worry much about. */
3736 if (size / align < MOVE_RATIO)
3737 FAIL;
3739 /* Fall through means we're going to use our block move pattern. */
3740 operands[0]
3741 = replace_equiv_address (operands[0],
3742 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3743 operands[1]
3744 = replace_equiv_address (operands[1],
3745 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3746 operands[4] = gen_reg_rtx (DImode);
3747 operands[5] = gen_reg_rtx (DImode);
3748 operands[6] = gen_reg_rtx (DImode);
3749 operands[7] = gen_reg_rtx (DImode);
3750 operands[8] = gen_reg_rtx (DImode);
3751 }")
3753 ;; The operand constraints are written like this to support both compile-time
3754 ;; and run-time determined byte counts. The expander and output_block_move
3755 ;; only support compile-time determined counts at this time.
3756 ;;
3757 ;; If the count is run-time determined, the register with the byte count
3758 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3759 ;;
3760 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3761 ;; broke this semantic for pseudo registers. We can't use match_scratch
3762 ;; as this requires two registers in the class R1_REGS when the MEMs for
3763 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3764 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3765 ;; respectively. We then split or peephole optimize after reload.
3766 (define_insn "movmemdi_prereload"
3767 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3768 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3769 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3770 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3771 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3772 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3773 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3774 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3775 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3776 "TARGET_64BIT"
3777 "#"
3778 [(set_attr "type" "multi,multi")])
3780 (define_split
3781 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3782 (match_operand:BLK 1 "memory_operand" ""))
3783 (clobber (match_operand:DI 2 "register_operand" ""))
3784 (clobber (match_operand:DI 3 "register_operand" ""))
3785 (clobber (match_operand:DI 6 "register_operand" ""))
3786 (clobber (match_operand:DI 7 "register_operand" ""))
3787 (clobber (match_operand:DI 8 "register_operand" ""))
3788 (use (match_operand:DI 4 "arith_operand" ""))
3789 (use (match_operand:DI 5 "const_int_operand" ""))])]
3790 "TARGET_64BIT && reload_completed && !flag_peephole2
3791 && GET_CODE (operands[0]) == MEM
3792 && register_operand (XEXP (operands[0], 0), DImode)
3793 && GET_CODE (operands[1]) == MEM
3794 && register_operand (XEXP (operands[1], 0), DImode)"
3795 [(set (match_dup 7) (match_dup 9))
3796 (set (match_dup 8) (match_dup 10))
3797 (parallel [(set (match_dup 0) (match_dup 1))
3798 (clobber (match_dup 2))
3799 (clobber (match_dup 3))
3800 (clobber (match_dup 6))
3801 (clobber (match_dup 7))
3802 (clobber (match_dup 8))
3803 (use (match_dup 4))
3804 (use (match_dup 5))
3805 (const_int 0)])]
3806 "
3807 {
3808 operands[9] = XEXP (operands[0], 0);
3809 operands[10] = XEXP (operands[1], 0);
3810 operands[0] = replace_equiv_address (operands[0], operands[7]);
3811 operands[1] = replace_equiv_address (operands[1], operands[8]);
3812 }")
3814 (define_peephole2
3815 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3816 (match_operand:BLK 1 "memory_operand" ""))
3817 (clobber (match_operand:DI 2 "register_operand" ""))
3818 (clobber (match_operand:DI 3 "register_operand" ""))
3819 (clobber (match_operand:DI 6 "register_operand" ""))
3820 (clobber (match_operand:DI 7 "register_operand" ""))
3821 (clobber (match_operand:DI 8 "register_operand" ""))
3822 (use (match_operand:DI 4 "arith_operand" ""))
3823 (use (match_operand:DI 5 "const_int_operand" ""))])]
3824 "TARGET_64BIT
3825 && GET_CODE (operands[0]) == MEM
3826 && register_operand (XEXP (operands[0], 0), DImode)
3827 && GET_CODE (operands[1]) == MEM
3828 && register_operand (XEXP (operands[1], 0), DImode)"
3829 [(parallel [(set (match_dup 0) (match_dup 1))
3830 (clobber (match_dup 2))
3831 (clobber (match_dup 3))
3832 (clobber (match_dup 6))
3833 (clobber (match_dup 7))
3834 (clobber (match_dup 8))
3835 (use (match_dup 4))
3836 (use (match_dup 5))
3837 (const_int 0)])]
3838 "
3839 {
3840 rtx addr = XEXP (operands[0], 0);
3841 if (dead_or_set_p (curr_insn, addr))
3842 operands[7] = addr;
3843 else
3844 {
3845 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3846 operands[0] = replace_equiv_address (operands[0], operands[7]);
3847 }
3849 addr = XEXP (operands[1], 0);
3850 if (dead_or_set_p (curr_insn, addr))
3851 operands[8] = addr;
3852 else
3853 {
3854 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3855 operands[1] = replace_equiv_address (operands[1], operands[8]);
3856 }
3857 }")
3859 (define_insn "movmemdi_postreload"
3860 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3861 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3862 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3863 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3864 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3865 (clobber (match_dup 0))
3866 (clobber (match_dup 1))
3867 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3868 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3869 (const_int 0)]
3870 "TARGET_64BIT && reload_completed"
3871 "* return output_block_move (operands, !which_alternative);"
3872 [(set_attr "type" "multi,multi")])
3874 (define_expand "setmemsi"
3875 [(parallel [(set (match_operand:BLK 0 "" "")
3876 (match_operand 2 "const_int_operand" ""))
3877 (clobber (match_dup 4))
3878 (clobber (match_dup 5))
3879 (use (match_operand:SI 1 "arith_operand" ""))
3880 (use (match_operand:SI 3 "const_int_operand" ""))])]
3881 "!TARGET_64BIT && optimize > 0"
3882 "
3883 {
3884 int size, align;
3886 /* If value to set is not zero, use the library routine. */
3887 if (operands[2] != const0_rtx)
3888 FAIL;
3890 /* Undetermined size, use the library routine. */
3891 if (GET_CODE (operands[1]) != CONST_INT)
3892 FAIL;
3894 size = INTVAL (operands[1]);
3895 align = INTVAL (operands[3]);
3896 align = align > 4 ? 4 : align;
3898 /* If size/alignment is large, then use the library routines. */
3899 if (size / align > 16)
3900 FAIL;
3902 /* This does happen, but not often enough to worry much about. */
3903 if (size / align < MOVE_RATIO)
3904 FAIL;
3906 /* Fall through means we're going to use our block clear pattern. */
3907 operands[0]
3908 = replace_equiv_address (operands[0],
3909 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3910 operands[4] = gen_reg_rtx (SImode);
3911 operands[5] = gen_reg_rtx (SImode);
3912 }")
3914 (define_insn "clrmemsi_prereload"
3915 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3916 (const_int 0))
3917 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3918 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3919 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3920 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3921 "!TARGET_64BIT"
3922 "#"
3923 [(set_attr "type" "multi,multi")])
3925 (define_split
3926 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3927 (const_int 0))
3928 (clobber (match_operand:SI 1 "register_operand" ""))
3929 (clobber (match_operand:SI 4 "register_operand" ""))
3930 (use (match_operand:SI 2 "arith_operand" ""))
3931 (use (match_operand:SI 3 "const_int_operand" ""))])]
3932 "!TARGET_64BIT && reload_completed && !flag_peephole2
3933 && GET_CODE (operands[0]) == MEM
3934 && register_operand (XEXP (operands[0], 0), SImode)"
3935 [(set (match_dup 4) (match_dup 5))
3936 (parallel [(set (match_dup 0) (const_int 0))
3937 (clobber (match_dup 1))
3938 (clobber (match_dup 4))
3939 (use (match_dup 2))
3940 (use (match_dup 3))
3941 (const_int 0)])]
3942 "
3943 {
3944 operands[5] = XEXP (operands[0], 0);
3945 operands[0] = replace_equiv_address (operands[0], operands[4]);
3946 }")
3948 (define_peephole2
3949 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3950 (const_int 0))
3951 (clobber (match_operand:SI 1 "register_operand" ""))
3952 (clobber (match_operand:SI 4 "register_operand" ""))
3953 (use (match_operand:SI 2 "arith_operand" ""))
3954 (use (match_operand:SI 3 "const_int_operand" ""))])]
3955 "!TARGET_64BIT
3956 && GET_CODE (operands[0]) == MEM
3957 && register_operand (XEXP (operands[0], 0), SImode)"
3958 [(parallel [(set (match_dup 0) (const_int 0))
3959 (clobber (match_dup 1))
3960 (clobber (match_dup 4))
3961 (use (match_dup 2))
3962 (use (match_dup 3))
3963 (const_int 0)])]
3964 "
3965 {
3966 rtx addr = XEXP (operands[0], 0);
3967 if (dead_or_set_p (curr_insn, addr))
3968 operands[4] = addr;
3969 else
3970 {
3971 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3972 operands[0] = replace_equiv_address (operands[0], operands[4]);
3973 }
3974 }")
3976 (define_insn "clrmemsi_postreload"
3977 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3978 (const_int 0))
3979 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3980 (clobber (match_dup 0))
3981 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3982 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3983 (const_int 0)]
3984 "!TARGET_64BIT && reload_completed"
3985 "* return output_block_clear (operands, !which_alternative);"
3986 [(set_attr "type" "multi,multi")])
3988 (define_expand "setmemdi"
3989 [(parallel [(set (match_operand:BLK 0 "" "")
3990 (match_operand 2 "const_int_operand" ""))
3991 (clobber (match_dup 4))
3992 (clobber (match_dup 5))
3993 (use (match_operand:DI 1 "arith_operand" ""))
3994 (use (match_operand:DI 3 "const_int_operand" ""))])]
3995 "TARGET_64BIT && optimize > 0"
3996 "
3997 {
3998 int size, align;
4000 /* If value to set is not zero, use the library routine. */
4001 if (operands[2] != const0_rtx)
4002 FAIL;
4004 /* Undetermined size, use the library routine. */
4005 if (GET_CODE (operands[1]) != CONST_INT)
4006 FAIL;
4008 size = INTVAL (operands[1]);
4009 align = INTVAL (operands[3]);
4010 align = align > 8 ? 8 : align;
4012 /* If size/alignment is large, then use the library routines. */
4013 if (size / align > 16)
4014 FAIL;
4016 /* This does happen, but not often enough to worry much about. */
4017 if (size / align < MOVE_RATIO)
4018 FAIL;
4020 /* Fall through means we're going to use our block clear pattern. */
4021 operands[0]
4022 = replace_equiv_address (operands[0],
4023 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
4024 operands[4] = gen_reg_rtx (DImode);
4025 operands[5] = gen_reg_rtx (DImode);
4026 }")
4028 (define_insn "clrmemdi_prereload"
4029 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
4030 (const_int 0))
4031 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4032 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
4033 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4034 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
4035 "TARGET_64BIT"
4036 "#"
4037 [(set_attr "type" "multi,multi")])
4039 (define_split
4040 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4041 (const_int 0))
4042 (clobber (match_operand:DI 1 "register_operand" ""))
4043 (clobber (match_operand:DI 4 "register_operand" ""))
4044 (use (match_operand:DI 2 "arith_operand" ""))
4045 (use (match_operand:DI 3 "const_int_operand" ""))])]
4046 "TARGET_64BIT && reload_completed && !flag_peephole2
4047 && GET_CODE (operands[0]) == MEM
4048 && register_operand (XEXP (operands[0], 0), DImode)"
4049 [(set (match_dup 4) (match_dup 5))
4050 (parallel [(set (match_dup 0) (const_int 0))
4051 (clobber (match_dup 1))
4052 (clobber (match_dup 4))
4053 (use (match_dup 2))
4054 (use (match_dup 3))
4055 (const_int 0)])]
4056 "
4057 {
4058 operands[5] = XEXP (operands[0], 0);
4059 operands[0] = replace_equiv_address (operands[0], operands[4]);
4060 }")
4062 (define_peephole2
4063 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4064 (const_int 0))
4065 (clobber (match_operand:DI 1 "register_operand" ""))
4066 (clobber (match_operand:DI 4 "register_operand" ""))
4067 (use (match_operand:DI 2 "arith_operand" ""))
4068 (use (match_operand:DI 3 "const_int_operand" ""))])]
4069 "TARGET_64BIT
4070 && GET_CODE (operands[0]) == MEM
4071 && register_operand (XEXP (operands[0], 0), DImode)"
4072 [(parallel [(set (match_dup 0) (const_int 0))
4073 (clobber (match_dup 1))
4074 (clobber (match_dup 4))
4075 (use (match_dup 2))
4076 (use (match_dup 3))
4077 (const_int 0)])]
4078 "
4079 {
4080 rtx addr = XEXP (operands[0], 0);
4081 if (dead_or_set_p (curr_insn, addr))
4082 operands[4] = addr;
4083 else
4084 {
4085 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4086 operands[0] = replace_equiv_address (operands[0], operands[4]);
4087 }
4088 }")
4090 (define_insn "clrmemdi_postreload"
4091 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4092 (const_int 0))
4093 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4094 (clobber (match_dup 0))
4095 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4096 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4097 (const_int 0)]
4098 "TARGET_64BIT && reload_completed"
4099 "* return output_block_clear (operands, !which_alternative);"
4100 [(set_attr "type" "multi,multi")])
4101 \f
4102 ;; Floating point move insns
4104 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4105 ;; to be reloaded by putting the constant into memory when
4106 ;; reg is a floating point register.
4107 ;;
4108 ;; For integer registers we use ldil;ldo to set the appropriate
4109 ;; value.
4110 ;;
4111 ;; This must come before the movdf pattern, and it must be present
4112 ;; to handle obscure reloading cases.
4113 (define_insn ""
4114 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4115 (match_operand:DF 1 "" "?F,m"))]
4116 "GET_CODE (operands[1]) == CONST_DOUBLE
4117 && operands[1] != CONST0_RTX (DFmode)
4118 && !TARGET_64BIT
4119 && !TARGET_SOFT_FLOAT"
4120 "* return (which_alternative == 0 ? output_move_double (operands)
4121 : \"fldd%F1 %1,%0\");"
4122 [(set_attr "type" "move,fpload")
4123 (set_attr "length" "16,4")])
4125 (define_expand "movdf"
4126 [(set (match_operand:DF 0 "general_operand" "")
4127 (match_operand:DF 1 "general_operand" ""))]
4128 ""
4129 "
4130 {
4131 if (GET_CODE (operands[1]) == CONST_DOUBLE
4132 && operands[1] != CONST0_RTX (DFmode))
4133 {
4134 /* Reject CONST_DOUBLE loads to all hard registers when
4135 generating 64-bit code and to floating point registers
4136 when generating 32-bit code. */
4137 if (REG_P (operands[0])
4138 && HARD_REGISTER_P (operands[0])
4139 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
4140 FAIL;
4142 if (TARGET_64BIT)
4143 operands[1] = force_const_mem (DFmode, operands[1]);
4144 }
4146 if (emit_move_sequence (operands, DFmode, 0))
4147 DONE;
4148 }")
4150 ;; Handle DFmode input reloads requiring a general register as a
4151 ;; scratch register.
4152 (define_expand "reload_indf"
4153 [(set (match_operand:DF 0 "register_operand" "=Z")
4154 (match_operand:DF 1 "non_hard_reg_operand" ""))
4155 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4156 ""
4157 "
4158 {
4159 if (emit_move_sequence (operands, DFmode, operands[2]))
4160 DONE;
4162 /* We don't want the clobber emitted, so handle this ourselves. */
4163 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4164 DONE;
4165 }")
4167 ;; Handle DFmode output reloads requiring a general register as a
4168 ;; scratch register.
4169 (define_expand "reload_outdf"
4170 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4171 (match_operand:DF 1 "register_operand" "Z"))
4172 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4173 ""
4174 "
4175 {
4176 if (emit_move_sequence (operands, DFmode, operands[2]))
4177 DONE;
4179 /* We don't want the clobber emitted, so handle this ourselves. */
4180 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4181 DONE;
4182 }")
4184 (define_insn ""
4185 [(set (match_operand:DF 0 "move_dest_operand"
4186 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
4187 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4188 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
4189 "(register_operand (operands[0], DFmode)
4190 || reg_or_0_operand (operands[1], DFmode))
4191 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4192 && GET_CODE (operands[0]) == MEM)
4193 && !TARGET_64BIT
4194 && !TARGET_SOFT_FLOAT"
4195 "*
4196 {
4197 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4198 || operands[1] == CONST0_RTX (DFmode))
4199 && !(REG_P (operands[0]) && REG_P (operands[1])
4200 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4201 return output_fp_move_double (operands);
4202 return output_move_double (operands);
4203 }"
4204 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
4205 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4207 (define_insn ""
4208 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4209 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4210 "!TARGET_SOFT_FLOAT
4211 && !TARGET_DISABLE_INDEXING
4212 && reload_completed"
4213 "fstd%F0 %1,%0"
4214 [(set_attr "type" "fpstore")
4215 (set_attr "pa_combine_type" "addmove")
4216 (set_attr "length" "4")])
4218 (define_peephole2
4219 [(set (match_operand:SI 0 "register_operand" "")
4220 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4221 (const_int 8))
4222 (match_operand:SI 2 "register_operand" "")))
4223 (set (mem:DF (match_dup 0))
4224 (match_operand:DF 3 "register_operand" ""))]
4225 "!TARGET_SOFT_FLOAT
4226 && !TARGET_DISABLE_INDEXING
4227 && REG_OK_FOR_BASE_P (operands[2])
4228 && FP_REGNO_P (REGNO (operands[3]))"
4229 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4230 (match_dup 3))
4231 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4232 (match_dup 2)))]
4233 "")
4235 (define_peephole2
4236 [(set (match_operand:SI 0 "register_operand" "")
4237 (plus:SI (match_operand:SI 2 "register_operand" "")
4238 (mult:SI (match_operand:SI 1 "register_operand" "")
4239 (const_int 8))))
4240 (set (mem:DF (match_dup 0))
4241 (match_operand:DF 3 "register_operand" ""))]
4242 "!TARGET_SOFT_FLOAT
4243 && !TARGET_DISABLE_INDEXING
4244 && REG_OK_FOR_BASE_P (operands[2])
4245 && FP_REGNO_P (REGNO (operands[3]))"
4246 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4247 (match_dup 3))
4248 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4249 (match_dup 2)))]
4250 "")
4252 (define_peephole2
4253 [(set (match_operand:DI 0 "register_operand" "")
4254 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4255 (const_int 8))
4256 (match_operand:DI 2 "register_operand" "")))
4257 (set (mem:DF (match_dup 0))
4258 (match_operand:DF 3 "register_operand" ""))]
4259 "!TARGET_SOFT_FLOAT
4260 && !TARGET_DISABLE_INDEXING
4261 && TARGET_64BIT
4262 && REG_OK_FOR_BASE_P (operands[2])
4263 && FP_REGNO_P (REGNO (operands[3]))"
4264 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4265 (match_dup 3))
4266 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4267 (match_dup 2)))]
4268 "")
4270 (define_peephole2
4271 [(set (match_operand:DI 0 "register_operand" "")
4272 (plus:DI (match_operand:DI 2 "register_operand" "")
4273 (mult:DI (match_operand:DI 1 "register_operand" "")
4274 (const_int 8))))
4275 (set (mem:DF (match_dup 0))
4276 (match_operand:DF 3 "register_operand" ""))]
4277 "!TARGET_SOFT_FLOAT
4278 && !TARGET_DISABLE_INDEXING
4279 && TARGET_64BIT
4280 && REG_OK_FOR_BASE_P (operands[2])
4281 && FP_REGNO_P (REGNO (operands[3]))"
4282 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4283 (match_dup 3))
4284 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4285 (match_dup 2)))]
4286 "")
4288 (define_peephole2
4289 [(set (match_operand:SI 0 "register_operand" "")
4290 (plus:SI (match_operand:SI 1 "register_operand" "")
4291 (match_operand:SI 2 "register_operand" "")))
4292 (set (mem:DF (match_dup 0))
4293 (match_operand:DF 3 "register_operand" ""))]
4294 "!TARGET_SOFT_FLOAT
4295 && !TARGET_DISABLE_INDEXING
4296 && TARGET_NO_SPACE_REGS
4297 && REG_OK_FOR_INDEX_P (operands[1])
4298 && REG_OK_FOR_BASE_P (operands[2])
4299 && FP_REGNO_P (REGNO (operands[3]))"
4300 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4301 (match_dup 3))
4302 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4303 "")
4305 (define_peephole2
4306 [(set (match_operand:SI 0 "register_operand" "")
4307 (plus:SI (match_operand:SI 1 "register_operand" "")
4308 (match_operand:SI 2 "register_operand" "")))
4309 (set (mem:DF (match_dup 0))
4310 (match_operand:DF 3 "register_operand" ""))]
4311 "!TARGET_SOFT_FLOAT
4312 && !TARGET_DISABLE_INDEXING
4313 && TARGET_NO_SPACE_REGS
4314 && REG_OK_FOR_BASE_P (operands[1])
4315 && REG_OK_FOR_INDEX_P (operands[2])
4316 && FP_REGNO_P (REGNO (operands[3]))"
4317 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4318 (match_dup 3))
4319 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4320 "")
4322 (define_peephole2
4323 [(set (match_operand:DI 0 "register_operand" "")
4324 (plus:DI (match_operand:DI 1 "register_operand" "")
4325 (match_operand:DI 2 "register_operand" "")))
4326 (set (mem:DF (match_dup 0))
4327 (match_operand:DF 3 "register_operand" ""))]
4328 "!TARGET_SOFT_FLOAT
4329 && !TARGET_DISABLE_INDEXING
4330 && TARGET_64BIT
4331 && TARGET_NO_SPACE_REGS
4332 && REG_OK_FOR_INDEX_P (operands[1])
4333 && REG_OK_FOR_BASE_P (operands[2])
4334 && FP_REGNO_P (REGNO (operands[3]))"
4335 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4336 (match_dup 3))
4337 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4338 "")
4340 (define_peephole2
4341 [(set (match_operand:DI 0 "register_operand" "")
4342 (plus:DI (match_operand:DI 1 "register_operand" "")
4343 (match_operand:DI 2 "register_operand" "")))
4344 (set (mem:DF (match_dup 0))
4345 (match_operand:DF 3 "register_operand" ""))]
4346 "!TARGET_SOFT_FLOAT
4347 && !TARGET_DISABLE_INDEXING
4348 && TARGET_64BIT
4349 && TARGET_NO_SPACE_REGS
4350 && REG_OK_FOR_BASE_P (operands[1])
4351 && REG_OK_FOR_INDEX_P (operands[2])
4352 && FP_REGNO_P (REGNO (operands[3]))"
4353 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4354 (match_dup 3))
4355 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4356 "")
4358 (define_insn ""
4359 [(set (match_operand:DF 0 "move_dest_operand"
4360 "=r,?o,?Q,r,r")
4361 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4362 "rG,r,r,o,RQ"))]
4363 "(register_operand (operands[0], DFmode)
4364 || reg_or_0_operand (operands[1], DFmode))
4365 && !TARGET_64BIT
4366 && TARGET_SOFT_FLOAT"
4367 "*
4368 {
4369 return output_move_double (operands);
4370 }"
4371 [(set_attr "type" "move,store,store,load,load")
4372 (set_attr "length" "8,8,16,8,16")])
4374 (define_insn ""
4375 [(set (match_operand:DF 0 "move_dest_operand"
4376 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4377 (match_operand:DF 1 "move_src_operand"
4378 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4379 "(register_operand (operands[0], DFmode)
4380 || reg_or_0_operand (operands[1], DFmode))
4381 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4382 "@
4383 copy %1,%0
4384 ldi %1,%0
4385 ldil L'%1,%0
4386 depdi,z %z1,%0
4387 ldd%M1 %1,%0
4388 std%M0 %r1,%0
4389 fcpy,dbl %f1,%0
4390 fldd%F1 %1,%0
4391 fstd%F0 %1,%0"
4392 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4393 (set_attr "pa_combine_type" "addmove")
4394 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4396 \f
4397 (define_expand "movdi"
4398 [(set (match_operand:DI 0 "general_operand" "")
4399 (match_operand:DI 1 "general_operand" ""))]
4400 ""
4401 "
4402 {
4403 /* Except for zero, we don't support loading a CONST_INT directly
4404 to a hard floating-point register since a scratch register is
4405 needed for the operation. While the operation could be handled
4406 before register allocation, the simplest solution is to fail. */
4407 if (TARGET_64BIT
4408 && GET_CODE (operands[1]) == CONST_INT
4409 && operands[1] != CONST0_RTX (DImode)
4410 && REG_P (operands[0])
4411 && HARD_REGISTER_P (operands[0])
4412 && REGNO (operands[0]) >= 32)
4413 FAIL;
4415 if (emit_move_sequence (operands, DImode, 0))
4416 DONE;
4417 }")
4419 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4420 (define_expand "reload_indi_r1"
4421 [(set (match_operand:DI 0 "register_operand" "=Z")
4422 (match_operand:DI 1 "non_hard_reg_operand" ""))
4423 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4424 ""
4425 "
4426 {
4427 if (emit_move_sequence (operands, DImode, operands[2]))
4428 DONE;
4430 /* We don't want the clobber emitted, so handle this ourselves. */
4431 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4432 DONE;
4433 }")
4435 ;; Handle DImode input reloads requiring a general register as a
4436 ;; scratch register.
4437 (define_expand "reload_indi"
4438 [(set (match_operand:DI 0 "register_operand" "=Z")
4439 (match_operand:DI 1 "non_hard_reg_operand" ""))
4440 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4441 ""
4442 "
4443 {
4444 if (emit_move_sequence (operands, DImode, operands[2]))
4445 DONE;
4447 /* We don't want the clobber emitted, so handle this ourselves. */
4448 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4449 DONE;
4450 }")
4452 ;; Handle DImode output reloads requiring a general register as a
4453 ;; scratch register.
4454 (define_expand "reload_outdi"
4455 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4456 (match_operand:DI 1 "register_operand" "Z"))
4457 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4458 ""
4459 "
4460 {
4461 if (emit_move_sequence (operands, DImode, operands[2]))
4462 DONE;
4464 /* We don't want the clobber emitted, so handle this ourselves. */
4465 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4466 DONE;
4467 }")
4469 (define_insn ""
4470 [(set (match_operand:DI 0 "register_operand" "=r")
4471 (high:DI (match_operand 1 "" "")))]
4472 "!TARGET_64BIT"
4473 "*
4474 {
4475 rtx op0 = operands[0];
4476 rtx op1 = operands[1];
4478 switch (GET_CODE (op1))
4479 {
4480 case CONST_INT:
4481 #if HOST_BITS_PER_WIDE_INT <= 32
4482 operands[0] = operand_subword (op0, 1, 0, DImode);
4483 output_asm_insn (\"ldil L'%1,%0\", operands);
4485 operands[0] = operand_subword (op0, 0, 0, DImode);
4486 if (INTVAL (op1) < 0)
4487 output_asm_insn (\"ldi -1,%0\", operands);
4488 else
4489 output_asm_insn (\"ldi 0,%0\", operands);
4490 #else
4491 operands[0] = operand_subword (op0, 1, 0, DImode);
4492 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4493 output_asm_insn (\"ldil L'%1,%0\", operands);
4495 operands[0] = operand_subword (op0, 0, 0, DImode);
4496 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4497 output_asm_insn (singlemove_string (operands), operands);
4498 #endif
4499 break;
4501 case CONST_DOUBLE:
4502 operands[0] = operand_subword (op0, 1, 0, DImode);
4503 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4504 output_asm_insn (\"ldil L'%1,%0\", operands);
4506 operands[0] = operand_subword (op0, 0, 0, DImode);
4507 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4508 output_asm_insn (singlemove_string (operands), operands);
4509 break;
4511 default:
4512 gcc_unreachable ();
4513 }
4514 return \"\";
4515 }"
4516 [(set_attr "type" "move")
4517 (set_attr "length" "12")])
4519 (define_insn ""
4520 [(set (match_operand:DI 0 "move_dest_operand"
4521 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4522 (match_operand:DI 1 "general_operand"
4523 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4524 "(register_operand (operands[0], DImode)
4525 || reg_or_0_operand (operands[1], DImode))
4526 && !TARGET_64BIT
4527 && !TARGET_SOFT_FLOAT"
4528 "*
4529 {
4530 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4531 || operands[1] == CONST0_RTX (DFmode))
4532 && !(REG_P (operands[0]) && REG_P (operands[1])
4533 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4534 return output_fp_move_double (operands);
4535 return output_move_double (operands);
4536 }"
4537 [(set_attr "type"
4538 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4539 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4541 (define_insn ""
4542 [(set (match_operand:DI 0 "move_dest_operand"
4543 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4544 (match_operand:DI 1 "move_src_operand"
4545 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4546 "(register_operand (operands[0], DImode)
4547 || reg_or_0_operand (operands[1], DImode))
4548 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4549 "@
4550 ldd RT'%A1,%0
4551 copy %1,%0
4552 ldi %1,%0
4553 ldil L'%1,%0
4554 depdi,z %z1,%0
4555 ldd%M1 %1,%0
4556 std%M0 %r1,%0
4557 mtsar %r1
4558 {mfctl|mfctl,w} %%sar,%0
4559 fcpy,dbl %f1,%0
4560 fldd%F1 %1,%0
4561 fstd%F0 %1,%0"
4562 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4563 (set_attr "pa_combine_type" "addmove")
4564 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4566 (define_insn ""
4567 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4568 (match_operand:DI 1 "register_operand" "f"))]
4569 "!TARGET_SOFT_FLOAT
4570 && TARGET_64BIT
4571 && !TARGET_DISABLE_INDEXING
4572 && reload_completed"
4573 "fstd%F0 %1,%0"
4574 [(set_attr "type" "fpstore")
4575 (set_attr "pa_combine_type" "addmove")
4576 (set_attr "length" "4")])
4578 (define_peephole2
4579 [(set (match_operand:DI 0 "register_operand" "")
4580 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4581 (const_int 8))
4582 (match_operand:DI 2 "register_operand" "")))
4583 (set (mem:DI (match_dup 0))
4584 (match_operand:DI 3 "register_operand" ""))]
4585 "!TARGET_SOFT_FLOAT
4586 && !TARGET_DISABLE_INDEXING
4587 && TARGET_64BIT
4588 && REG_OK_FOR_BASE_P (operands[2])
4589 && FP_REGNO_P (REGNO (operands[3]))"
4590 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4591 (match_dup 3))
4592 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4593 (match_dup 2)))]
4594 "")
4596 (define_peephole2
4597 [(set (match_operand:DI 0 "register_operand" "")
4598 (plus:DI (match_operand:DI 2 "register_operand" "")
4599 (mult:DI (match_operand:DI 1 "register_operand" "")
4600 (const_int 8))))
4601 (set (mem:DI (match_dup 0))
4602 (match_operand:DI 3 "register_operand" ""))]
4603 "!TARGET_SOFT_FLOAT
4604 && !TARGET_DISABLE_INDEXING
4605 && TARGET_64BIT
4606 && REG_OK_FOR_BASE_P (operands[2])
4607 && FP_REGNO_P (REGNO (operands[3]))"
4608 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4609 (match_dup 3))
4610 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4611 (match_dup 2)))]
4612 "")
4614 (define_peephole2
4615 [(set (match_operand:DI 0 "register_operand" "")
4616 (plus:DI (match_operand:DI 1 "register_operand" "")
4617 (match_operand:DI 2 "register_operand" "")))
4618 (set (mem:DI (match_dup 0))
4619 (match_operand:DI 3 "register_operand" ""))]
4620 "!TARGET_SOFT_FLOAT
4621 && !TARGET_DISABLE_INDEXING
4622 && TARGET_64BIT
4623 && TARGET_NO_SPACE_REGS
4624 && REG_OK_FOR_INDEX_P (operands[1])
4625 && REG_OK_FOR_BASE_P (operands[2])
4626 && FP_REGNO_P (REGNO (operands[3]))"
4627 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4628 (match_dup 3))
4629 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4630 "")
4632 (define_peephole2
4633 [(set (match_operand:DI 0 "register_operand" "")
4634 (plus:DI (match_operand:DI 1 "register_operand" "")
4635 (match_operand:DI 2 "register_operand" "")))
4636 (set (mem:DI (match_dup 0))
4637 (match_operand:DI 3 "register_operand" ""))]
4638 "!TARGET_SOFT_FLOAT
4639 && !TARGET_DISABLE_INDEXING
4640 && TARGET_64BIT
4641 && TARGET_NO_SPACE_REGS
4642 && REG_OK_FOR_BASE_P (operands[1])
4643 && REG_OK_FOR_INDEX_P (operands[2])
4644 && FP_REGNO_P (REGNO (operands[3]))"
4645 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4646 (match_dup 3))
4647 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4648 "")
4650 (define_insn ""
4651 [(set (match_operand:DI 0 "move_dest_operand"
4652 "=r,o,Q,r,r,r")
4653 (match_operand:DI 1 "general_operand"
4654 "rM,r,r,o,Q,i"))]
4655 "(register_operand (operands[0], DImode)
4656 || reg_or_0_operand (operands[1], DImode))
4657 && !TARGET_64BIT
4658 && TARGET_SOFT_FLOAT"
4659 "*
4660 {
4661 return output_move_double (operands);
4662 }"
4663 [(set_attr "type" "move,store,store,load,load,multi")
4664 (set_attr "length" "8,8,16,8,16,16")])
4666 (define_insn ""
4667 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4668 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4669 (match_operand:DI 2 "immediate_operand" "i,i")))]
4670 "!TARGET_64BIT"
4671 "*
4672 {
4673 /* Don't output a 64-bit constant, since we can't trust the assembler to
4674 handle it correctly. */
4675 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4676 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4677 else if (HOST_BITS_PER_WIDE_INT > 32
4678 && GET_CODE (operands[2]) == CONST_INT)
4679 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4680 if (which_alternative == 1)
4681 output_asm_insn (\"copy %1,%0\", operands);
4682 return \"ldo R'%G2(%R1),%R0\";
4683 }"
4684 [(set_attr "type" "move,move")
4685 (set_attr "length" "4,8")])
4687 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4688 ;; to be reloaded by putting the constant into memory when
4689 ;; reg is a floating point register.
4690 ;;
4691 ;; For integer registers we use ldil;ldo to set the appropriate
4692 ;; value.
4693 ;;
4694 ;; This must come before the movsf pattern, and it must be present
4695 ;; to handle obscure reloading cases.
4696 (define_insn ""
4697 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4698 (match_operand:SF 1 "" "?F,m"))]
4699 "GET_CODE (operands[1]) == CONST_DOUBLE
4700 && operands[1] != CONST0_RTX (SFmode)
4701 && ! TARGET_SOFT_FLOAT"
4702 "* return (which_alternative == 0 ? singlemove_string (operands)
4703 : \" fldw%F1 %1,%0\");"
4704 [(set_attr "type" "move,fpload")
4705 (set_attr "length" "8,4")])
4707 (define_expand "movsf"
4708 [(set (match_operand:SF 0 "general_operand" "")
4709 (match_operand:SF 1 "general_operand" ""))]
4710 ""
4711 "
4712 {
4713 /* Reject CONST_DOUBLE loads to floating point registers. */
4714 if (GET_CODE (operands[1]) == CONST_DOUBLE
4715 && operands[1] != CONST0_RTX (SFmode)
4716 && REG_P (operands[0])
4717 && HARD_REGISTER_P (operands[0])
4718 && REGNO (operands[0]) >= 32)
4719 FAIL;
4721 if (emit_move_sequence (operands, SFmode, 0))
4722 DONE;
4723 }")
4725 ;; Handle SFmode input reloads requiring a general register as a
4726 ;; scratch register.
4727 (define_expand "reload_insf"
4728 [(set (match_operand:SF 0 "register_operand" "=Z")
4729 (match_operand:SF 1 "non_hard_reg_operand" ""))
4730 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4731 ""
4732 "
4733 {
4734 if (emit_move_sequence (operands, SFmode, operands[2]))
4735 DONE;
4737 /* We don't want the clobber emitted, so handle this ourselves. */
4738 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4739 DONE;
4740 }")
4742 ;; Handle SFmode output reloads requiring a general register as a
4743 ;; scratch register.
4744 (define_expand "reload_outsf"
4745 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4746 (match_operand:SF 1 "register_operand" "Z"))
4747 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4748 ""
4749 "
4750 {
4751 if (emit_move_sequence (operands, SFmode, operands[2]))
4752 DONE;
4754 /* We don't want the clobber emitted, so handle this ourselves. */
4755 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4756 DONE;
4757 }")
4759 (define_insn ""
4760 [(set (match_operand:SF 0 "move_dest_operand"
4761 "=f,!*r,f,*r,Q,Q,?*r,?f")
4762 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4763 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4764 "(register_operand (operands[0], SFmode)
4765 || reg_or_0_operand (operands[1], SFmode))
4766 && !TARGET_SOFT_FLOAT
4767 && !TARGET_64BIT"
4768 "@
4769 fcpy,sgl %f1,%0
4770 copy %r1,%0
4771 fldw%F1 %1,%0
4772 ldw%M1 %1,%0
4773 fstw%F0 %1,%0
4774 stw%M0 %r1,%0
4775 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4776 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4777 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4778 (set_attr "pa_combine_type" "addmove")
4779 (set_attr "length" "4,4,4,4,4,4,8,8")])
4781 (define_insn ""
4782 [(set (match_operand:SF 0 "move_dest_operand"
4783 "=f,!*r,f,*r,Q,Q")
4784 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4785 "fG,!*rG,RQ,RQ,f,*rG"))]
4786 "(register_operand (operands[0], SFmode)
4787 || reg_or_0_operand (operands[1], SFmode))
4788 && !TARGET_SOFT_FLOAT
4789 && TARGET_64BIT"
4790 "@
4791 fcpy,sgl %f1,%0
4792 copy %r1,%0
4793 fldw%F1 %1,%0
4794 ldw%M1 %1,%0
4795 fstw%F0 %1,%0
4796 stw%M0 %r1,%0"
4797 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4798 (set_attr "pa_combine_type" "addmove")
4799 (set_attr "length" "4,4,4,4,4,4")])
4801 (define_insn ""
4802 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4803 (match_operand:SF 1 "register_operand" "f"))]
4804 "!TARGET_SOFT_FLOAT
4805 && !TARGET_DISABLE_INDEXING
4806 && reload_completed"
4807 "fstw%F0 %1,%0"
4808 [(set_attr "type" "fpstore")
4809 (set_attr "pa_combine_type" "addmove")
4810 (set_attr "length" "4")])
4812 (define_peephole2
4813 [(set (match_operand:SI 0 "register_operand" "")
4814 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4815 (const_int 4))
4816 (match_operand:SI 2 "register_operand" "")))
4817 (set (mem:SF (match_dup 0))
4818 (match_operand:SF 3 "register_operand" ""))]
4819 "!TARGET_SOFT_FLOAT
4820 && !TARGET_DISABLE_INDEXING
4821 && REG_OK_FOR_BASE_P (operands[2])
4822 && FP_REGNO_P (REGNO (operands[3]))"
4823 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4824 (match_dup 3))
4825 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4826 (match_dup 2)))]
4827 "")
4829 (define_peephole2
4830 [(set (match_operand:SI 0 "register_operand" "")
4831 (plus:SI (match_operand:SI 2 "register_operand" "")
4832 (mult:SI (match_operand:SI 1 "register_operand" "")
4833 (const_int 4))))
4834 (set (mem:SF (match_dup 0))
4835 (match_operand:SF 3 "register_operand" ""))]
4836 "!TARGET_SOFT_FLOAT
4837 && !TARGET_DISABLE_INDEXING
4838 && REG_OK_FOR_BASE_P (operands[2])
4839 && FP_REGNO_P (REGNO (operands[3]))"
4840 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4841 (match_dup 3))
4842 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4843 (match_dup 2)))]
4844 "")
4846 (define_peephole2
4847 [(set (match_operand:DI 0 "register_operand" "")
4848 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4849 (const_int 4))
4850 (match_operand:DI 2 "register_operand" "")))
4851 (set (mem:SF (match_dup 0))
4852 (match_operand:SF 3 "register_operand" ""))]
4853 "!TARGET_SOFT_FLOAT
4854 && !TARGET_DISABLE_INDEXING
4855 && TARGET_64BIT
4856 && REG_OK_FOR_BASE_P (operands[2])
4857 && FP_REGNO_P (REGNO (operands[3]))"
4858 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4859 (match_dup 3))
4860 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4861 (match_dup 2)))]
4862 "")
4864 (define_peephole2
4865 [(set (match_operand:DI 0 "register_operand" "")
4866 (plus:DI (match_operand:DI 2 "register_operand" "")
4867 (mult:DI (match_operand:DI 1 "register_operand" "")
4868 (const_int 4))))
4869 (set (mem:SF (match_dup 0))
4870 (match_operand:SF 3 "register_operand" ""))]
4871 "!TARGET_SOFT_FLOAT
4872 && !TARGET_DISABLE_INDEXING
4873 && TARGET_64BIT
4874 && REG_OK_FOR_BASE_P (operands[2])
4875 && FP_REGNO_P (REGNO (operands[3]))"
4876 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4877 (match_dup 3))
4878 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4879 (match_dup 2)))]
4880 "")
4882 (define_peephole2
4883 [(set (match_operand:SI 0 "register_operand" "")
4884 (plus:SI (match_operand:SI 1 "register_operand" "")
4885 (match_operand:SI 2 "register_operand" "")))
4886 (set (mem:SF (match_dup 0))
4887 (match_operand:SF 3 "register_operand" ""))]
4888 "!TARGET_SOFT_FLOAT
4889 && !TARGET_DISABLE_INDEXING
4890 && TARGET_NO_SPACE_REGS
4891 && REG_OK_FOR_INDEX_P (operands[1])
4892 && REG_OK_FOR_BASE_P (operands[2])
4893 && FP_REGNO_P (REGNO (operands[3]))"
4894 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4895 (match_dup 3))
4896 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4897 "")
4899 (define_peephole2
4900 [(set (match_operand:SI 0 "register_operand" "")
4901 (plus:SI (match_operand:SI 1 "register_operand" "")
4902 (match_operand:SI 2 "register_operand" "")))
4903 (set (mem:SF (match_dup 0))
4904 (match_operand:SF 3 "register_operand" ""))]
4905 "!TARGET_SOFT_FLOAT
4906 && !TARGET_DISABLE_INDEXING
4907 && TARGET_NO_SPACE_REGS
4908 && REG_OK_FOR_BASE_P (operands[1])
4909 && REG_OK_FOR_INDEX_P (operands[2])
4910 && FP_REGNO_P (REGNO (operands[3]))"
4911 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4912 (match_dup 3))
4913 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4914 "")
4916 (define_peephole2
4917 [(set (match_operand:DI 0 "register_operand" "")
4918 (plus:DI (match_operand:DI 1 "register_operand" "")
4919 (match_operand:DI 2 "register_operand" "")))
4920 (set (mem:SF (match_dup 0))
4921 (match_operand:SF 3 "register_operand" ""))]
4922 "!TARGET_SOFT_FLOAT
4923 && !TARGET_DISABLE_INDEXING
4924 && TARGET_64BIT
4925 && TARGET_NO_SPACE_REGS
4926 && REG_OK_FOR_INDEX_P (operands[1])
4927 && REG_OK_FOR_BASE_P (operands[2])
4928 && FP_REGNO_P (REGNO (operands[3]))"
4929 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4930 (match_dup 3))
4931 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4932 "")
4934 (define_peephole2
4935 [(set (match_operand:DI 0 "register_operand" "")
4936 (plus:DI (match_operand:DI 1 "register_operand" "")
4937 (match_operand:DI 2 "register_operand" "")))
4938 (set (mem:SF (match_dup 0))
4939 (match_operand:SF 3 "register_operand" ""))]
4940 "!TARGET_SOFT_FLOAT
4941 && !TARGET_DISABLE_INDEXING
4942 && TARGET_64BIT
4943 && TARGET_NO_SPACE_REGS
4944 && REG_OK_FOR_BASE_P (operands[1])
4945 && REG_OK_FOR_INDEX_P (operands[2])
4946 && FP_REGNO_P (REGNO (operands[3]))"
4947 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4948 (match_dup 3))
4949 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4950 "")
4952 (define_insn ""
4953 [(set (match_operand:SF 0 "move_dest_operand"
4954 "=r,r,Q")
4955 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4956 "rG,RQ,rG"))]
4957 "(register_operand (operands[0], SFmode)
4958 || reg_or_0_operand (operands[1], SFmode))
4959 && TARGET_SOFT_FLOAT"
4960 "@
4961 copy %r1,%0
4962 ldw%M1 %1,%0
4963 stw%M0 %r1,%0"
4964 [(set_attr "type" "move,load,store")
4965 (set_attr "pa_combine_type" "addmove")
4966 (set_attr "length" "4,4,4")])
4968 \f
4970 ;;- zero extension instructions
4971 ;; We have define_expand for zero extension patterns to make sure the
4972 ;; operands get loaded into registers. The define_insns accept
4973 ;; memory operands. This gives us better overall code than just
4974 ;; having a pattern that does or does not accept memory operands.
4976 (define_expand "zero_extendqihi2"
4977 [(set (match_operand:HI 0 "register_operand" "")
4978 (zero_extend:HI
4979 (match_operand:QI 1 "register_operand" "")))]
4980 ""
4981 "")
4983 (define_insn ""
4984 [(set (match_operand:HI 0 "register_operand" "=r,r")
4985 (zero_extend:HI
4986 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4987 "GET_CODE (operands[1]) != CONST_INT"
4988 "@
4989 {extru|extrw,u} %1,31,8,%0
4990 ldb%M1 %1,%0"
4991 [(set_attr "type" "shift,load")
4992 (set_attr "length" "4,4")])
4994 (define_expand "zero_extendqisi2"
4995 [(set (match_operand:SI 0 "register_operand" "")
4996 (zero_extend:SI
4997 (match_operand:QI 1 "register_operand" "")))]
4998 ""
4999 "")
5001 (define_insn ""
5002 [(set (match_operand:SI 0 "register_operand" "=r,r")
5003 (zero_extend:SI
5004 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5005 "GET_CODE (operands[1]) != CONST_INT"
5006 "@
5007 {extru|extrw,u} %1,31,8,%0
5008 ldb%M1 %1,%0"
5009 [(set_attr "type" "shift,load")
5010 (set_attr "length" "4,4")])
5012 (define_expand "zero_extendhisi2"
5013 [(set (match_operand:SI 0 "register_operand" "")
5014 (zero_extend:SI
5015 (match_operand:HI 1 "register_operand" "")))]
5016 ""
5017 "")
5019 (define_insn ""
5020 [(set (match_operand:SI 0 "register_operand" "=r,r")
5021 (zero_extend:SI
5022 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5023 "GET_CODE (operands[1]) != CONST_INT"
5024 "@
5025 {extru|extrw,u} %1,31,16,%0
5026 ldh%M1 %1,%0"
5027 [(set_attr "type" "shift,load")
5028 (set_attr "length" "4,4")])
5030 (define_expand "zero_extendqidi2"
5031 [(set (match_operand:DI 0 "register_operand" "")
5032 (zero_extend:DI
5033 (match_operand:QI 1 "register_operand" "")))]
5034 "TARGET_64BIT"
5035 "")
5037 (define_insn ""
5038 [(set (match_operand:DI 0 "register_operand" "=r,r")
5039 (zero_extend:DI
5040 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5041 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5042 "@
5043 extrd,u %1,63,8,%0
5044 ldb%M1 %1,%0"
5045 [(set_attr "type" "shift,load")
5046 (set_attr "length" "4,4")])
5048 (define_expand "zero_extendhidi2"
5049 [(set (match_operand:DI 0 "register_operand" "")
5050 (zero_extend:DI
5051 (match_operand:HI 1 "register_operand" "")))]
5052 "TARGET_64BIT"
5053 "")
5055 (define_insn ""
5056 [(set (match_operand:DI 0 "register_operand" "=r,r")
5057 (zero_extend:DI
5058 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5059 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5060 "@
5061 extrd,u %1,63,16,%0
5062 ldh%M1 %1,%0"
5063 [(set_attr "type" "shift,load")
5064 (set_attr "length" "4,4")])
5066 (define_expand "zero_extendsidi2"
5067 [(set (match_operand:DI 0 "register_operand" "")
5068 (zero_extend:DI
5069 (match_operand:SI 1 "register_operand" "")))]
5070 "TARGET_64BIT"
5071 "")
5073 (define_insn ""
5074 [(set (match_operand:DI 0 "register_operand" "=r,r")
5075 (zero_extend:DI
5076 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5077 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5078 "@
5079 extrd,u %1,63,32,%0
5080 ldw%M1 %1,%0"
5081 [(set_attr "type" "shift,load")
5082 (set_attr "length" "4,4")])
5084 ;;- sign extension instructions
5086 (define_insn "extendhisi2"
5087 [(set (match_operand:SI 0 "register_operand" "=r")
5088 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5089 ""
5090 "{extrs|extrw,s} %1,31,16,%0"
5091 [(set_attr "type" "shift")
5092 (set_attr "length" "4")])
5094 (define_insn "extendqihi2"
5095 [(set (match_operand:HI 0 "register_operand" "=r")
5096 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5097 ""
5098 "{extrs|extrw,s} %1,31,8,%0"
5099 [(set_attr "type" "shift")
5100 (set_attr "length" "4")])
5102 (define_insn "extendqisi2"
5103 [(set (match_operand:SI 0 "register_operand" "=r")
5104 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5105 ""
5106 "{extrs|extrw,s} %1,31,8,%0"
5107 [(set_attr "type" "shift")
5108 (set_attr "length" "4")])
5110 (define_insn "extendqidi2"
5111 [(set (match_operand:DI 0 "register_operand" "=r")
5112 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5113 "TARGET_64BIT"
5114 "extrd,s %1,63,8,%0"
5115 [(set_attr "type" "shift")
5116 (set_attr "length" "4")])
5118 (define_insn "extendhidi2"
5119 [(set (match_operand:DI 0 "register_operand" "=r")
5120 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5121 "TARGET_64BIT"
5122 "extrd,s %1,63,16,%0"
5123 [(set_attr "type" "shift")
5124 (set_attr "length" "4")])
5126 (define_insn "extendsidi2"
5127 [(set (match_operand:DI 0 "register_operand" "=r")
5128 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5129 "TARGET_64BIT"
5130 "extrd,s %1,63,32,%0"
5131 [(set_attr "type" "shift")
5132 (set_attr "length" "4")])
5134 \f
5135 ;; Conversions between float and double.
5137 (define_insn "extendsfdf2"
5138 [(set (match_operand:DF 0 "register_operand" "=f")
5139 (float_extend:DF
5140 (match_operand:SF 1 "register_operand" "f")))]
5141 "! TARGET_SOFT_FLOAT"
5142 "{fcnvff|fcnv},sgl,dbl %1,%0"
5143 [(set_attr "type" "fpalu")
5144 (set_attr "length" "4")])
5146 (define_insn "truncdfsf2"
5147 [(set (match_operand:SF 0 "register_operand" "=f")
5148 (float_truncate:SF
5149 (match_operand:DF 1 "register_operand" "f")))]
5150 "! TARGET_SOFT_FLOAT"
5151 "{fcnvff|fcnv},dbl,sgl %1,%0"
5152 [(set_attr "type" "fpalu")
5153 (set_attr "length" "4")])
5155 ;; Conversion between fixed point and floating point.
5156 ;; Note that among the fix-to-float insns
5157 ;; the ones that start with SImode come first.
5158 ;; That is so that an operand that is a CONST_INT
5159 ;; (and therefore lacks a specific machine mode).
5160 ;; will be recognized as SImode (which is always valid)
5161 ;; rather than as QImode or HImode.
5163 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5164 ;; to be reloaded by putting the constant into memory.
5165 ;; It must come before the more general floatsisf2 pattern.
5166 (define_insn ""
5167 [(set (match_operand:SF 0 "register_operand" "=f")
5168 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5169 "! TARGET_SOFT_FLOAT"
5170 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5171 [(set_attr "type" "fpalu")
5172 (set_attr "length" "8")])
5174 (define_insn "floatsisf2"
5175 [(set (match_operand:SF 0 "register_operand" "=f")
5176 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5177 "! TARGET_SOFT_FLOAT"
5178 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5179 [(set_attr "type" "fpalu")
5180 (set_attr "length" "4")])
5182 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5183 ;; to be reloaded by putting the constant into memory.
5184 ;; It must come before the more general floatsidf2 pattern.
5185 (define_insn ""
5186 [(set (match_operand:DF 0 "register_operand" "=f")
5187 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5188 "! TARGET_SOFT_FLOAT"
5189 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5190 [(set_attr "type" "fpalu")
5191 (set_attr "length" "8")])
5193 (define_insn "floatsidf2"
5194 [(set (match_operand:DF 0 "register_operand" "=f")
5195 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5196 "! TARGET_SOFT_FLOAT"
5197 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5198 [(set_attr "type" "fpalu")
5199 (set_attr "length" "4")])
5201 (define_expand "floatunssisf2"
5202 [(set (subreg:SI (match_dup 2) 4)
5203 (match_operand:SI 1 "register_operand" ""))
5204 (set (subreg:SI (match_dup 2) 0)
5205 (const_int 0))
5206 (set (match_operand:SF 0 "register_operand" "")
5207 (float:SF (match_dup 2)))]
5208 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5209 "
5210 {
5211 if (TARGET_PA_20)
5212 {
5213 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5214 DONE;
5215 }
5216 operands[2] = gen_reg_rtx (DImode);
5217 }")
5219 (define_expand "floatunssidf2"
5220 [(set (subreg:SI (match_dup 2) 4)
5221 (match_operand:SI 1 "register_operand" ""))
5222 (set (subreg:SI (match_dup 2) 0)
5223 (const_int 0))
5224 (set (match_operand:DF 0 "register_operand" "")
5225 (float:DF (match_dup 2)))]
5226 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5227 "
5228 {
5229 if (TARGET_PA_20)
5230 {
5231 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5232 DONE;
5233 }
5234 operands[2] = gen_reg_rtx (DImode);
5235 }")
5237 (define_insn "floatdisf2"
5238 [(set (match_operand:SF 0 "register_operand" "=f")
5239 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5240 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5241 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5242 [(set_attr "type" "fpalu")
5243 (set_attr "length" "4")])
5245 (define_insn "floatdidf2"
5246 [(set (match_operand:DF 0 "register_operand" "=f")
5247 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5248 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5249 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5250 [(set_attr "type" "fpalu")
5251 (set_attr "length" "4")])
5253 ;; Convert a float to an actual integer.
5254 ;; Truncation is performed as part of the conversion.
5256 (define_insn "fix_truncsfsi2"
5257 [(set (match_operand:SI 0 "register_operand" "=f")
5258 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5259 "! TARGET_SOFT_FLOAT"
5260 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5261 [(set_attr "type" "fpalu")
5262 (set_attr "length" "4")])
5264 (define_insn "fix_truncdfsi2"
5265 [(set (match_operand:SI 0 "register_operand" "=f")
5266 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5267 "! TARGET_SOFT_FLOAT"
5268 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5269 [(set_attr "type" "fpalu")
5270 (set_attr "length" "4")])
5272 (define_insn "fix_truncsfdi2"
5273 [(set (match_operand:DI 0 "register_operand" "=f")
5274 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5275 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5276 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5277 [(set_attr "type" "fpalu")
5278 (set_attr "length" "4")])
5280 (define_insn "fix_truncdfdi2"
5281 [(set (match_operand:DI 0 "register_operand" "=f")
5282 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5283 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5284 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5285 [(set_attr "type" "fpalu")
5286 (set_attr "length" "4")])
5288 (define_insn "floatunssidf2_pa20"
5289 [(set (match_operand:DF 0 "register_operand" "=f")
5290 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5291 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5292 "fcnv,uw,dbl %1,%0"
5293 [(set_attr "type" "fpalu")
5294 (set_attr "length" "4")])
5296 (define_insn "floatunssisf2_pa20"
5297 [(set (match_operand:SF 0 "register_operand" "=f")
5298 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5299 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5300 "fcnv,uw,sgl %1,%0"
5301 [(set_attr "type" "fpalu")
5302 (set_attr "length" "4")])
5304 (define_insn "floatunsdisf2"
5305 [(set (match_operand:SF 0 "register_operand" "=f")
5306 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5307 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5308 "fcnv,udw,sgl %1,%0"
5309 [(set_attr "type" "fpalu")
5310 (set_attr "length" "4")])
5312 (define_insn "floatunsdidf2"
5313 [(set (match_operand:DF 0 "register_operand" "=f")
5314 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5315 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5316 "fcnv,udw,dbl %1,%0"
5317 [(set_attr "type" "fpalu")
5318 (set_attr "length" "4")])
5320 (define_insn "fixuns_truncsfsi2"
5321 [(set (match_operand:SI 0 "register_operand" "=f")
5322 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5323 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5324 "fcnv,t,sgl,uw %1,%0"
5325 [(set_attr "type" "fpalu")
5326 (set_attr "length" "4")])
5328 (define_insn "fixuns_truncdfsi2"
5329 [(set (match_operand:SI 0 "register_operand" "=f")
5330 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5331 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5332 "fcnv,t,dbl,uw %1,%0"
5333 [(set_attr "type" "fpalu")
5334 (set_attr "length" "4")])
5336 (define_insn "fixuns_truncsfdi2"
5337 [(set (match_operand:DI 0 "register_operand" "=f")
5338 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5339 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5340 "fcnv,t,sgl,udw %1,%0"
5341 [(set_attr "type" "fpalu")
5342 (set_attr "length" "4")])
5344 (define_insn "fixuns_truncdfdi2"
5345 [(set (match_operand:DI 0 "register_operand" "=f")
5346 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5347 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5348 "fcnv,t,dbl,udw %1,%0"
5349 [(set_attr "type" "fpalu")
5350 (set_attr "length" "4")])
5351 \f
5352 ;;- arithmetic instructions
5354 (define_expand "adddi3"
5355 [(set (match_operand:DI 0 "register_operand" "")
5356 (plus:DI (match_operand:DI 1 "register_operand" "")
5357 (match_operand:DI 2 "adddi3_operand" "")))]
5358 ""
5359 "")
5361 (define_insn ""
5362 [(set (match_operand:DI 0 "register_operand" "=r")
5363 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5364 (match_operand:DI 2 "arith11_operand" "rI")))]
5365 "!TARGET_64BIT"
5366 "*
5367 {
5368 if (GET_CODE (operands[2]) == CONST_INT)
5369 {
5370 if (INTVAL (operands[2]) >= 0)
5371 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5372 else
5373 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5374 }
5375 else
5376 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5377 }"
5378 [(set_attr "type" "binary")
5379 (set_attr "length" "8")])
5381 (define_insn ""
5382 [(set (match_operand:DI 0 "register_operand" "=r,r")
5383 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5384 (match_operand:DI 2 "arith_operand" "r,J")))]
5385 "TARGET_64BIT"
5386 "@
5387 add,l %1,%2,%0
5388 ldo %2(%1),%0"
5389 [(set_attr "type" "binary,binary")
5390 (set_attr "pa_combine_type" "addmove")
5391 (set_attr "length" "4,4")])
5393 (define_insn ""
5394 [(set (match_operand:DI 0 "register_operand" "=r")
5395 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5396 (match_operand:DI 2 "register_operand" "r")))]
5397 "TARGET_64BIT"
5398 "uaddcm %2,%1,%0"
5399 [(set_attr "type" "binary")
5400 (set_attr "length" "4")])
5402 (define_insn ""
5403 [(set (match_operand:SI 0 "register_operand" "=r")
5404 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5405 (match_operand:SI 2 "register_operand" "r")))]
5406 ""
5407 "uaddcm %2,%1,%0"
5408 [(set_attr "type" "binary")
5409 (set_attr "length" "4")])
5411 (define_expand "addvdi3"
5412 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5413 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5414 (match_operand:DI 2 "arith11_operand" "")))
5415 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5416 (sign_extend:TI (match_dup 2)))
5417 (sign_extend:TI (plus:DI (match_dup 1)
5418 (match_dup 2))))
5419 (const_int 0))])]
5420 ""
5421 "")
5423 (define_insn ""
5424 [(set (match_operand:DI 0 "register_operand" "=r,r")
5425 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5426 (match_operand:DI 2 "arith11_operand" "r,I")))
5427 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5428 (sign_extend:TI (match_dup 2)))
5429 (sign_extend:TI (plus:DI (match_dup 1)
5430 (match_dup 2))))
5431 (const_int 0))]
5432 "TARGET_64BIT"
5433 "@
5434 add,tsv,* %2,%1,%0
5435 addi,tsv,* %2,%1,%0"
5436 [(set_attr "type" "binary,binary")
5437 (set_attr "length" "4,4")])
5439 (define_insn ""
5440 [(set (match_operand:DI 0 "register_operand" "=r")
5441 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5442 (match_operand:DI 2 "arith11_operand" "rI")))
5443 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5444 (sign_extend:TI (match_dup 2)))
5445 (sign_extend:TI (plus:DI (match_dup 1)
5446 (match_dup 2))))
5447 (const_int 0))]
5448 "!TARGET_64BIT"
5449 "*
5450 {
5451 if (GET_CODE (operands[2]) == CONST_INT)
5452 {
5453 if (INTVAL (operands[2]) >= 0)
5454 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5455 else
5456 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5457 }
5458 else
5459 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5460 }"
5461 [(set_attr "type" "binary")
5462 (set_attr "length" "8")])
5464 ;; define_splits to optimize cases of adding a constant integer
5465 ;; to a register when the constant does not fit in 14 bits. */
5466 (define_split
5467 [(set (match_operand:SI 0 "register_operand" "")
5468 (plus:SI (match_operand:SI 1 "register_operand" "")
5469 (match_operand:SI 2 "const_int_operand" "")))
5470 (clobber (match_operand:SI 4 "register_operand" ""))]
5471 "! cint_ok_for_move (INTVAL (operands[2]))
5472 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5473 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5474 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5475 "
5476 {
5477 int val = INTVAL (operands[2]);
5478 int low = (val < 0) ? -0x2000 : 0x1fff;
5479 int rest = val - low;
5481 operands[2] = GEN_INT (rest);
5482 operands[3] = GEN_INT (low);
5483 }")
5485 (define_split
5486 [(set (match_operand:SI 0 "register_operand" "")
5487 (plus:SI (match_operand:SI 1 "register_operand" "")
5488 (match_operand:SI 2 "const_int_operand" "")))
5489 (clobber (match_operand:SI 4 "register_operand" ""))]
5490 "! cint_ok_for_move (INTVAL (operands[2]))"
5491 [(set (match_dup 4) (match_dup 2))
5492 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5493 (match_dup 1)))]
5494 "
5495 {
5496 HOST_WIDE_INT intval = INTVAL (operands[2]);
5498 /* Try dividing the constant by 2, then 4, and finally 8 to see
5499 if we can get a constant which can be loaded into a register
5500 in a single instruction (cint_ok_for_move).
5502 If that fails, try to negate the constant and subtract it
5503 from our input operand. */
5504 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5505 {
5506 operands[2] = GEN_INT (intval / 2);
5507 operands[3] = const2_rtx;
5508 }
5509 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5510 {
5511 operands[2] = GEN_INT (intval / 4);
5512 operands[3] = GEN_INT (4);
5513 }
5514 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5515 {
5516 operands[2] = GEN_INT (intval / 8);
5517 operands[3] = GEN_INT (8);
5518 }
5519 else if (cint_ok_for_move (-intval))
5520 {
5521 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5522 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5523 DONE;
5524 }
5525 else
5526 FAIL;
5527 }")
5529 (define_insn "addsi3"
5530 [(set (match_operand:SI 0 "register_operand" "=r,r")
5531 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5532 (match_operand:SI 2 "arith_operand" "r,J")))]
5533 ""
5534 "@
5535 {addl|add,l} %1,%2,%0
5536 ldo %2(%1),%0"
5537 [(set_attr "type" "binary,binary")
5538 (set_attr "pa_combine_type" "addmove")
5539 (set_attr "length" "4,4")])
5541 (define_insn "addvsi3"
5542 [(set (match_operand:SI 0 "register_operand" "=r,r")
5543 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5544 (match_operand:SI 2 "arith11_operand" "r,I")))
5545 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5546 (sign_extend:DI (match_dup 2)))
5547 (sign_extend:DI (plus:SI (match_dup 1)
5548 (match_dup 2))))
5549 (const_int 0))]
5550 ""
5551 "@
5552 {addo|add,tsv} %2,%1,%0
5553 {addio|addi,tsv} %2,%1,%0"
5554 [(set_attr "type" "binary,binary")
5555 (set_attr "length" "4,4")])
5557 (define_expand "subdi3"
5558 [(set (match_operand:DI 0 "register_operand" "")
5559 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5560 (match_operand:DI 2 "reg_or_0_operand" "")))]
5561 ""
5562 "")
5564 (define_insn ""
5565 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5566 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5567 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5568 "TARGET_64BIT"
5569 "@
5570 sub %1,%2,%0
5571 subi %1,%2,%0
5572 mtsarcm %2"
5573 [(set_attr "type" "binary,binary,move")
5574 (set_attr "length" "4,4,4")])
5576 (define_insn ""
5577 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5578 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5579 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5580 "!TARGET_64BIT"
5581 "*
5582 {
5583 if (GET_CODE (operands[1]) == CONST_INT)
5584 {
5585 if (INTVAL (operands[1]) >= 0)
5586 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5587 else
5588 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5589 }
5590 else
5591 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5592 }"
5593 [(set_attr "type" "binary")
5594 (set (attr "length")
5595 (if_then_else (eq_attr "alternative" "0")
5596 (const_int 8)
5597 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5598 (const_int 0))
5599 (const_int 8)
5600 (const_int 12))))])
5602 (define_expand "subvdi3"
5603 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5604 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5605 (match_operand:DI 2 "reg_or_0_operand" "")))
5606 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5607 (sign_extend:TI (match_dup 2)))
5608 (sign_extend:TI (minus:DI (match_dup 1)
5609 (match_dup 2))))
5610 (const_int 0))])]
5611 ""
5612 "")
5614 (define_insn ""
5615 [(set (match_operand:DI 0 "register_operand" "=r,r")
5616 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5617 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5618 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5619 (sign_extend:TI (match_dup 2)))
5620 (sign_extend:TI (minus:DI (match_dup 1)
5621 (match_dup 2))))
5622 (const_int 0))]
5623 "TARGET_64BIT"
5624 "@
5625 {subo|sub,tsv} %1,%2,%0
5626 {subio|subi,tsv} %1,%2,%0"
5627 [(set_attr "type" "binary,binary")
5628 (set_attr "length" "4,4")])
5630 (define_insn ""
5631 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5632 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5633 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5634 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5635 (sign_extend:TI (match_dup 2)))
5636 (sign_extend:TI (minus:DI (match_dup 1)
5637 (match_dup 2))))
5638 (const_int 0))]
5639 "!TARGET_64BIT"
5640 "*
5641 {
5642 if (GET_CODE (operands[1]) == CONST_INT)
5643 {
5644 if (INTVAL (operands[1]) >= 0)
5645 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5646 else
5647 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5648 }
5649 else
5650 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5651 }"
5652 [(set_attr "type" "binary,binary")
5653 (set (attr "length")
5654 (if_then_else (eq_attr "alternative" "0")
5655 (const_int 8)
5656 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5657 (const_int 0))
5658 (const_int 8)
5659 (const_int 12))))])
5661 (define_expand "subsi3"
5662 [(set (match_operand:SI 0 "register_operand" "")
5663 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5664 (match_operand:SI 2 "register_operand" "")))]
5665 ""
5666 "")
5668 (define_insn ""
5669 [(set (match_operand:SI 0 "register_operand" "=r,r")
5670 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5671 (match_operand:SI 2 "register_operand" "r,r")))]
5672 "!TARGET_PA_20"
5673 "@
5674 sub %1,%2,%0
5675 subi %1,%2,%0"
5676 [(set_attr "type" "binary,binary")
5677 (set_attr "length" "4,4")])
5679 (define_insn ""
5680 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5681 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5682 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5683 "TARGET_PA_20"
5684 "@
5685 sub %1,%2,%0
5686 subi %1,%2,%0
5687 mtsarcm %2"
5688 [(set_attr "type" "binary,binary,move")
5689 (set_attr "length" "4,4,4")])
5691 (define_insn "subvsi3"
5692 [(set (match_operand:SI 0 "register_operand" "=r,r")
5693 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5694 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5695 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5696 (sign_extend:DI (match_dup 2)))
5697 (sign_extend:DI (minus:SI (match_dup 1)
5698 (match_dup 2))))
5699 (const_int 0))]
5700 ""
5701 "@
5702 {subo|sub,tsv} %1,%2,%0
5703 {subio|subi,tsv} %1,%2,%0"
5704 [(set_attr "type" "binary,binary")
5705 (set_attr "length" "4,4")])
5707 ;; Clobbering a "register_operand" instead of a match_scratch
5708 ;; in operand3 of millicode calls avoids spilling %r1 and
5709 ;; produces better code.
5711 ;; The mulsi3 insns set up registers for the millicode call.
5712 (define_expand "mulsi3"
5713 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5714 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5715 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5716 (clobber (match_dup 3))
5717 (clobber (reg:SI 26))
5718 (clobber (reg:SI 25))
5719 (clobber (match_dup 4))])
5720 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5721 ""
5722 "
5723 {
5724 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5725 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5726 {
5727 rtx scratch = gen_reg_rtx (DImode);
5728 operands[1] = force_reg (SImode, operands[1]);
5729 operands[2] = force_reg (SImode, operands[2]);
5730 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5731 emit_insn (gen_movsi (operands[0],
5732 gen_rtx_SUBREG (SImode, scratch,
5733 GET_MODE_SIZE (SImode))));
5734 DONE;
5735 }
5736 operands[3] = gen_reg_rtx (SImode);
5737 }")
5739 (define_insn "umulsidi3"
5740 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5741 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5742 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5743 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5744 "xmpyu %1,%2,%0"
5745 [(set_attr "type" "fpmuldbl")
5746 (set_attr "length" "4")])
5748 (define_insn ""
5749 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5750 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5751 (match_operand:DI 2 "uint32_operand" "f")))]
5752 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5753 "xmpyu %1,%R2,%0"
5754 [(set_attr "type" "fpmuldbl")
5755 (set_attr "length" "4")])
5757 (define_insn ""
5758 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5759 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5760 (match_operand:DI 2 "uint32_operand" "f")))]
5761 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5762 "xmpyu %1,%2R,%0"
5763 [(set_attr "type" "fpmuldbl")
5764 (set_attr "length" "4")])
5766 (define_insn ""
5767 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5768 (clobber (match_operand:SI 0 "register_operand" "=a"))
5769 (clobber (reg:SI 26))
5770 (clobber (reg:SI 25))
5771 (clobber (reg:SI 31))]
5772 "!TARGET_64BIT"
5773 "* return output_mul_insn (0, insn);"
5774 [(set_attr "type" "milli")
5775 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5777 (define_insn ""
5778 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5779 (clobber (match_operand:SI 0 "register_operand" "=a"))
5780 (clobber (reg:SI 26))
5781 (clobber (reg:SI 25))
5782 (clobber (reg:SI 2))]
5783 "TARGET_64BIT"
5784 "* return output_mul_insn (0, insn);"
5785 [(set_attr "type" "milli")
5786 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5788 (define_expand "muldi3"
5789 [(set (match_operand:DI 0 "register_operand" "")
5790 (mult:DI (match_operand:DI 1 "register_operand" "")
5791 (match_operand:DI 2 "register_operand" "")))]
5792 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5793 "
5794 {
5795 rtx low_product = gen_reg_rtx (DImode);
5796 rtx cross_product1 = gen_reg_rtx (DImode);
5797 rtx cross_product2 = gen_reg_rtx (DImode);
5798 rtx cross_scratch = gen_reg_rtx (DImode);
5799 rtx cross_product = gen_reg_rtx (DImode);
5800 rtx op1l, op1r, op2l, op2r;
5801 rtx op1shifted, op2shifted;
5803 op1shifted = gen_reg_rtx (DImode);
5804 op2shifted = gen_reg_rtx (DImode);
5805 op1l = gen_reg_rtx (SImode);
5806 op1r = gen_reg_rtx (SImode);
5807 op2l = gen_reg_rtx (SImode);
5808 op2r = gen_reg_rtx (SImode);
5810 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5811 GEN_INT (32)));
5812 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5813 GEN_INT (32)));
5814 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5815 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5816 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5817 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5819 /* Emit multiplies for the cross products. */
5820 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5821 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5823 /* Emit a multiply for the low sub-word. */
5824 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5826 /* Sum the cross products and shift them into proper position. */
5827 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5828 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5830 /* Add the cross product to the low product and store the result
5831 into the output operand . */
5832 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5833 DONE;
5834 }")
5836 ;;; Division and mod.
5837 (define_expand "divsi3"
5838 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5839 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5840 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5841 (clobber (match_dup 3))
5842 (clobber (match_dup 4))
5843 (clobber (reg:SI 26))
5844 (clobber (reg:SI 25))
5845 (clobber (match_dup 5))])
5846 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5847 ""
5848 "
5849 {
5850 operands[3] = gen_reg_rtx (SImode);
5851 if (TARGET_64BIT)
5852 {
5853 operands[5] = gen_rtx_REG (SImode, 2);
5854 operands[4] = operands[5];
5855 }
5856 else
5857 {
5858 operands[5] = gen_rtx_REG (SImode, 31);
5859 operands[4] = gen_reg_rtx (SImode);
5860 }
5861 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5862 DONE;
5863 }")
5865 (define_insn ""
5866 [(set (reg:SI 29)
5867 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5868 (clobber (match_operand:SI 1 "register_operand" "=a"))
5869 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5870 (clobber (reg:SI 26))
5871 (clobber (reg:SI 25))
5872 (clobber (reg:SI 31))]
5873 "!TARGET_64BIT"
5874 "*
5875 return output_div_insn (operands, 0, insn);"
5876 [(set_attr "type" "milli")
5877 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5879 (define_insn ""
5880 [(set (reg:SI 29)
5881 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5882 (clobber (match_operand:SI 1 "register_operand" "=a"))
5883 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5884 (clobber (reg:SI 26))
5885 (clobber (reg:SI 25))
5886 (clobber (reg:SI 2))]
5887 "TARGET_64BIT"
5888 "*
5889 return output_div_insn (operands, 0, insn);"
5890 [(set_attr "type" "milli")
5891 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5893 (define_expand "udivsi3"
5894 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5895 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5896 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5897 (clobber (match_dup 3))
5898 (clobber (match_dup 4))
5899 (clobber (reg:SI 26))
5900 (clobber (reg:SI 25))
5901 (clobber (match_dup 5))])
5902 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5903 ""
5904 "
5905 {
5906 operands[3] = gen_reg_rtx (SImode);
5908 if (TARGET_64BIT)
5909 {
5910 operands[5] = gen_rtx_REG (SImode, 2);
5911 operands[4] = operands[5];
5912 }
5913 else
5914 {
5915 operands[5] = gen_rtx_REG (SImode, 31);
5916 operands[4] = gen_reg_rtx (SImode);
5917 }
5918 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5919 DONE;
5920 }")
5922 (define_insn ""
5923 [(set (reg:SI 29)
5924 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5925 (clobber (match_operand:SI 1 "register_operand" "=a"))
5926 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5927 (clobber (reg:SI 26))
5928 (clobber (reg:SI 25))
5929 (clobber (reg:SI 31))]
5930 "!TARGET_64BIT"
5931 "*
5932 return output_div_insn (operands, 1, insn);"
5933 [(set_attr "type" "milli")
5934 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5936 (define_insn ""
5937 [(set (reg:SI 29)
5938 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5939 (clobber (match_operand:SI 1 "register_operand" "=a"))
5940 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5941 (clobber (reg:SI 26))
5942 (clobber (reg:SI 25))
5943 (clobber (reg:SI 2))]
5944 "TARGET_64BIT"
5945 "*
5946 return output_div_insn (operands, 1, insn);"
5947 [(set_attr "type" "milli")
5948 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5950 (define_expand "modsi3"
5951 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5952 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5953 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5954 (clobber (match_dup 3))
5955 (clobber (match_dup 4))
5956 (clobber (reg:SI 26))
5957 (clobber (reg:SI 25))
5958 (clobber (match_dup 5))])
5959 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5960 ""
5961 "
5962 {
5963 if (TARGET_64BIT)
5964 {
5965 operands[5] = gen_rtx_REG (SImode, 2);
5966 operands[4] = operands[5];
5967 }
5968 else
5969 {
5970 operands[5] = gen_rtx_REG (SImode, 31);
5971 operands[4] = gen_reg_rtx (SImode);
5972 }
5973 operands[3] = gen_reg_rtx (SImode);
5974 }")
5976 (define_insn ""
5977 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5978 (clobber (match_operand:SI 0 "register_operand" "=a"))
5979 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5980 (clobber (reg:SI 26))
5981 (clobber (reg:SI 25))
5982 (clobber (reg:SI 31))]
5983 "!TARGET_64BIT"
5984 "*
5985 return output_mod_insn (0, insn);"
5986 [(set_attr "type" "milli")
5987 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5989 (define_insn ""
5990 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5991 (clobber (match_operand:SI 0 "register_operand" "=a"))
5992 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5993 (clobber (reg:SI 26))
5994 (clobber (reg:SI 25))
5995 (clobber (reg:SI 2))]
5996 "TARGET_64BIT"
5997 "*
5998 return output_mod_insn (0, insn);"
5999 [(set_attr "type" "milli")
6000 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6002 (define_expand "umodsi3"
6003 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
6004 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
6005 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6006 (clobber (match_dup 3))
6007 (clobber (match_dup 4))
6008 (clobber (reg:SI 26))
6009 (clobber (reg:SI 25))
6010 (clobber (match_dup 5))])
6011 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
6012 ""
6013 "
6014 {
6015 if (TARGET_64BIT)
6016 {
6017 operands[5] = gen_rtx_REG (SImode, 2);
6018 operands[4] = operands[5];
6019 }
6020 else
6021 {
6022 operands[5] = gen_rtx_REG (SImode, 31);
6023 operands[4] = gen_reg_rtx (SImode);
6024 }
6025 operands[3] = gen_reg_rtx (SImode);
6026 }")
6028 (define_insn ""
6029 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6030 (clobber (match_operand:SI 0 "register_operand" "=a"))
6031 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6032 (clobber (reg:SI 26))
6033 (clobber (reg:SI 25))
6034 (clobber (reg:SI 31))]
6035 "!TARGET_64BIT"
6036 "*
6037 return output_mod_insn (1, insn);"
6038 [(set_attr "type" "milli")
6039 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6041 (define_insn ""
6042 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6043 (clobber (match_operand:SI 0 "register_operand" "=a"))
6044 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6045 (clobber (reg:SI 26))
6046 (clobber (reg:SI 25))
6047 (clobber (reg:SI 2))]
6048 "TARGET_64BIT"
6049 "*
6050 return output_mod_insn (1, insn);"
6051 [(set_attr "type" "milli")
6052 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6054 ;;- and instructions
6055 ;; We define DImode `and` so with DImode `not` we can get
6056 ;; DImode `andn`. Other combinations are possible.
6058 (define_expand "anddi3"
6059 [(set (match_operand:DI 0 "register_operand" "")
6060 (and:DI (match_operand:DI 1 "register_operand" "")
6061 (match_operand:DI 2 "and_operand" "")))]
6062 ""
6063 "
6064 {
6065 /* Both operands must be register operands. */
6066 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6067 FAIL;
6068 }")
6070 (define_insn ""
6071 [(set (match_operand:DI 0 "register_operand" "=r")
6072 (and:DI (match_operand:DI 1 "register_operand" "%r")
6073 (match_operand:DI 2 "register_operand" "r")))]
6074 "!TARGET_64BIT"
6075 "and %1,%2,%0\;and %R1,%R2,%R0"
6076 [(set_attr "type" "binary")
6077 (set_attr "length" "8")])
6079 (define_insn ""
6080 [(set (match_operand:DI 0 "register_operand" "=r,r")
6081 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
6082 (match_operand:DI 2 "and_operand" "rO,P")))]
6083 "TARGET_64BIT"
6084 "* return output_64bit_and (operands); "
6085 [(set_attr "type" "binary")
6086 (set_attr "length" "4")])
6088 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
6089 ; constant with ldil;ldo.
6090 (define_insn "andsi3"
6091 [(set (match_operand:SI 0 "register_operand" "=r,r")
6092 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
6093 (match_operand:SI 2 "and_operand" "rO,P")))]
6094 ""
6095 "* return output_and (operands); "
6096 [(set_attr "type" "binary,shift")
6097 (set_attr "length" "4,4")])
6099 (define_insn ""
6100 [(set (match_operand:DI 0 "register_operand" "=r")
6101 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6102 (match_operand:DI 2 "register_operand" "r")))]
6103 "!TARGET_64BIT"
6104 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
6105 [(set_attr "type" "binary")
6106 (set_attr "length" "8")])
6108 (define_insn ""
6109 [(set (match_operand:DI 0 "register_operand" "=r")
6110 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6111 (match_operand:DI 2 "register_operand" "r")))]
6112 "TARGET_64BIT"
6113 "andcm %2,%1,%0"
6114 [(set_attr "type" "binary")
6115 (set_attr "length" "4")])
6117 (define_insn ""
6118 [(set (match_operand:SI 0 "register_operand" "=r")
6119 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
6120 (match_operand:SI 2 "register_operand" "r")))]
6121 ""
6122 "andcm %2,%1,%0"
6123 [(set_attr "type" "binary")
6124 (set_attr "length" "4")])
6126 (define_expand "iordi3"
6127 [(set (match_operand:DI 0 "register_operand" "")
6128 (ior:DI (match_operand:DI 1 "register_operand" "")
6129 (match_operand:DI 2 "ior_operand" "")))]
6130 ""
6131 "
6132 {
6133 /* Both operands must be register operands. */
6134 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6135 FAIL;
6136 }")
6138 (define_insn ""
6139 [(set (match_operand:DI 0 "register_operand" "=r")
6140 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6141 (match_operand:DI 2 "register_operand" "r")))]
6142 "!TARGET_64BIT"
6143 "or %1,%2,%0\;or %R1,%R2,%R0"
6144 [(set_attr "type" "binary")
6145 (set_attr "length" "8")])
6147 (define_insn ""
6148 [(set (match_operand:DI 0 "register_operand" "=r,r")
6149 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
6150 (match_operand:DI 2 "ior_operand" "M,i")))]
6151 "TARGET_64BIT"
6152 "* return output_64bit_ior (operands); "
6153 [(set_attr "type" "binary,shift")
6154 (set_attr "length" "4,4")])
6156 (define_insn ""
6157 [(set (match_operand:DI 0 "register_operand" "=r")
6158 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6159 (match_operand:DI 2 "register_operand" "r")))]
6160 "TARGET_64BIT"
6161 "or %1,%2,%0"
6162 [(set_attr "type" "binary")
6163 (set_attr "length" "4")])
6165 ;; Need a define_expand because we've run out of CONST_OK... characters.
6166 (define_expand "iorsi3"
6167 [(set (match_operand:SI 0 "register_operand" "")
6168 (ior:SI (match_operand:SI 1 "register_operand" "")
6169 (match_operand:SI 2 "arith32_operand" "")))]
6170 ""
6171 "
6172 {
6173 if (! (ior_operand (operands[2], SImode)
6174 || register_operand (operands[2], SImode)))
6175 operands[2] = force_reg (SImode, operands[2]);
6176 }")
6178 (define_insn ""
6179 [(set (match_operand:SI 0 "register_operand" "=r,r")
6180 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
6181 (match_operand:SI 2 "ior_operand" "M,i")))]
6182 ""
6183 "* return output_ior (operands); "
6184 [(set_attr "type" "binary,shift")
6185 (set_attr "length" "4,4")])
6187 (define_insn ""
6188 [(set (match_operand:SI 0 "register_operand" "=r")
6189 (ior:SI (match_operand:SI 1 "register_operand" "%r")
6190 (match_operand:SI 2 "register_operand" "r")))]
6191 ""
6192 "or %1,%2,%0"
6193 [(set_attr "type" "binary")
6194 (set_attr "length" "4")])
6196 (define_expand "xordi3"
6197 [(set (match_operand:DI 0 "register_operand" "")
6198 (xor:DI (match_operand:DI 1 "register_operand" "")
6199 (match_operand:DI 2 "register_operand" "")))]
6200 ""
6201 "
6202 {
6203 }")
6205 (define_insn ""
6206 [(set (match_operand:DI 0 "register_operand" "=r")
6207 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6208 (match_operand:DI 2 "register_operand" "r")))]
6209 "!TARGET_64BIT"
6210 "xor %1,%2,%0\;xor %R1,%R2,%R0"
6211 [(set_attr "type" "binary")
6212 (set_attr "length" "8")])
6214 (define_insn ""
6215 [(set (match_operand:DI 0 "register_operand" "=r")
6216 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6217 (match_operand:DI 2 "register_operand" "r")))]
6218 "TARGET_64BIT"
6219 "xor %1,%2,%0"
6220 [(set_attr "type" "binary")
6221 (set_attr "length" "4")])
6223 (define_insn "xorsi3"
6224 [(set (match_operand:SI 0 "register_operand" "=r")
6225 (xor:SI (match_operand:SI 1 "register_operand" "%r")
6226 (match_operand:SI 2 "register_operand" "r")))]
6227 ""
6228 "xor %1,%2,%0"
6229 [(set_attr "type" "binary")
6230 (set_attr "length" "4")])
6232 (define_expand "negdi2"
6233 [(set (match_operand:DI 0 "register_operand" "")
6234 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6235 ""
6236 "")
6238 (define_insn ""
6239 [(set (match_operand:DI 0 "register_operand" "=r")
6240 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6241 "!TARGET_64BIT"
6242 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6243 [(set_attr "type" "unary")
6244 (set_attr "length" "8")])
6246 (define_insn ""
6247 [(set (match_operand:DI 0 "register_operand" "=r")
6248 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6249 "TARGET_64BIT"
6250 "sub %%r0,%1,%0"
6251 [(set_attr "type" "unary")
6252 (set_attr "length" "4")])
6254 (define_expand "negvdi2"
6255 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6256 (neg:DI (match_operand:DI 1 "register_operand" "")))
6257 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6258 (sign_extend:TI (neg:DI (match_dup 1))))
6259 (const_int 0))])]
6260 ""
6261 "")
6263 (define_insn ""
6264 [(set (match_operand:DI 0 "register_operand" "=r")
6265 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6266 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6267 (sign_extend:TI (neg:DI (match_dup 1))))
6268 (const_int 0))]
6269 "!TARGET_64BIT"
6270 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
6271 [(set_attr "type" "unary")
6272 (set_attr "length" "8")])
6274 (define_insn ""
6275 [(set (match_operand:DI 0 "register_operand" "=r")
6276 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6277 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6278 (sign_extend:TI (neg:DI (match_dup 1))))
6279 (const_int 0))]
6280 "TARGET_64BIT"
6281 "sub,tsv %%r0,%1,%0"
6282 [(set_attr "type" "unary")
6283 (set_attr "length" "4")])
6285 (define_insn "negsi2"
6286 [(set (match_operand:SI 0 "register_operand" "=r")
6287 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6288 ""
6289 "sub %%r0,%1,%0"
6290 [(set_attr "type" "unary")
6291 (set_attr "length" "4")])
6293 (define_insn "negvsi2"
6294 [(set (match_operand:SI 0 "register_operand" "=r")
6295 (neg:SI (match_operand:SI 1 "register_operand" "r")))
6296 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
6297 (sign_extend:DI (neg:SI (match_dup 1))))
6298 (const_int 0))]
6299 ""
6300 "{subo|sub,tsv} %%r0,%1,%0"
6301 [(set_attr "type" "unary")
6302 (set_attr "length" "4")])
6304 (define_expand "one_cmpldi2"
6305 [(set (match_operand:DI 0 "register_operand" "")
6306 (not:DI (match_operand:DI 1 "register_operand" "")))]
6307 ""
6308 "
6309 {
6310 }")
6312 (define_insn ""
6313 [(set (match_operand:DI 0 "register_operand" "=r")
6314 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6315 "!TARGET_64BIT"
6316 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6317 [(set_attr "type" "unary")
6318 (set_attr "length" "8")])
6320 (define_insn ""
6321 [(set (match_operand:DI 0 "register_operand" "=r")
6322 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6323 "TARGET_64BIT"
6324 "uaddcm %%r0,%1,%0"
6325 [(set_attr "type" "unary")
6326 (set_attr "length" "4")])
6328 (define_insn "one_cmplsi2"
6329 [(set (match_operand:SI 0 "register_operand" "=r")
6330 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6331 ""
6332 "uaddcm %%r0,%1,%0"
6333 [(set_attr "type" "unary")
6334 (set_attr "length" "4")])
6335 \f
6336 ;; Floating point arithmetic instructions.
6338 (define_insn "adddf3"
6339 [(set (match_operand:DF 0 "register_operand" "=f")
6340 (plus:DF (match_operand:DF 1 "register_operand" "f")
6341 (match_operand:DF 2 "register_operand" "f")))]
6342 "! TARGET_SOFT_FLOAT"
6343 "fadd,dbl %1,%2,%0"
6344 [(set_attr "type" "fpalu")
6345 (set_attr "pa_combine_type" "faddsub")
6346 (set_attr "length" "4")])
6348 (define_insn "addsf3"
6349 [(set (match_operand:SF 0 "register_operand" "=f")
6350 (plus:SF (match_operand:SF 1 "register_operand" "f")
6351 (match_operand:SF 2 "register_operand" "f")))]
6352 "! TARGET_SOFT_FLOAT"
6353 "fadd,sgl %1,%2,%0"
6354 [(set_attr "type" "fpalu")
6355 (set_attr "pa_combine_type" "faddsub")
6356 (set_attr "length" "4")])
6358 (define_insn "subdf3"
6359 [(set (match_operand:DF 0 "register_operand" "=f")
6360 (minus:DF (match_operand:DF 1 "register_operand" "f")
6361 (match_operand:DF 2 "register_operand" "f")))]
6362 "! TARGET_SOFT_FLOAT"
6363 "fsub,dbl %1,%2,%0"
6364 [(set_attr "type" "fpalu")
6365 (set_attr "pa_combine_type" "faddsub")
6366 (set_attr "length" "4")])
6368 (define_insn "subsf3"
6369 [(set (match_operand:SF 0 "register_operand" "=f")
6370 (minus:SF (match_operand:SF 1 "register_operand" "f")
6371 (match_operand:SF 2 "register_operand" "f")))]
6372 "! TARGET_SOFT_FLOAT"
6373 "fsub,sgl %1,%2,%0"
6374 [(set_attr "type" "fpalu")
6375 (set_attr "pa_combine_type" "faddsub")
6376 (set_attr "length" "4")])
6378 (define_insn "muldf3"
6379 [(set (match_operand:DF 0 "register_operand" "=f")
6380 (mult:DF (match_operand:DF 1 "register_operand" "f")
6381 (match_operand:DF 2 "register_operand" "f")))]
6382 "! TARGET_SOFT_FLOAT"
6383 "fmpy,dbl %1,%2,%0"
6384 [(set_attr "type" "fpmuldbl")
6385 (set_attr "pa_combine_type" "fmpy")
6386 (set_attr "length" "4")])
6388 (define_insn "mulsf3"
6389 [(set (match_operand:SF 0 "register_operand" "=f")
6390 (mult:SF (match_operand:SF 1 "register_operand" "f")
6391 (match_operand:SF 2 "register_operand" "f")))]
6392 "! TARGET_SOFT_FLOAT"
6393 "fmpy,sgl %1,%2,%0"
6394 [(set_attr "type" "fpmulsgl")
6395 (set_attr "pa_combine_type" "fmpy")
6396 (set_attr "length" "4")])
6398 (define_insn "divdf3"
6399 [(set (match_operand:DF 0 "register_operand" "=f")
6400 (div:DF (match_operand:DF 1 "register_operand" "f")
6401 (match_operand:DF 2 "register_operand" "f")))]
6402 "! TARGET_SOFT_FLOAT"
6403 "fdiv,dbl %1,%2,%0"
6404 [(set_attr "type" "fpdivdbl")
6405 (set_attr "length" "4")])
6407 (define_insn "divsf3"
6408 [(set (match_operand:SF 0 "register_operand" "=f")
6409 (div:SF (match_operand:SF 1 "register_operand" "f")
6410 (match_operand:SF 2 "register_operand" "f")))]
6411 "! TARGET_SOFT_FLOAT"
6412 "fdiv,sgl %1,%2,%0"
6413 [(set_attr "type" "fpdivsgl")
6414 (set_attr "length" "4")])
6416 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6417 ;; negation can be done by subtracting from plus zero. However, this
6418 ;; violates the IEEE standard when negating plus and minus zero.
6419 (define_expand "negdf2"
6420 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6421 (neg:DF (match_operand:DF 1 "register_operand" "")))
6422 (use (match_dup 2))])]
6423 "! TARGET_SOFT_FLOAT"
6424 {
6425 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6426 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6427 else
6428 {
6429 operands[2] = force_reg (DFmode,
6430 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6431 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6432 }
6433 DONE;
6434 })
6436 (define_insn "negdf2_fast"
6437 [(set (match_operand:DF 0 "register_operand" "=f")
6438 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6439 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6440 "*
6441 {
6442 if (TARGET_PA_20)
6443 return \"fneg,dbl %1,%0\";
6444 else
6445 return \"fsub,dbl %%fr0,%1,%0\";
6446 }"
6447 [(set_attr "type" "fpalu")
6448 (set_attr "length" "4")])
6450 (define_expand "negsf2"
6451 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6452 (neg:SF (match_operand:SF 1 "register_operand" "")))
6453 (use (match_dup 2))])]
6454 "! TARGET_SOFT_FLOAT"
6455 {
6456 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6457 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6458 else
6459 {
6460 operands[2] = force_reg (SFmode,
6461 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6462 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6463 }
6464 DONE;
6465 })
6467 (define_insn "negsf2_fast"
6468 [(set (match_operand:SF 0 "register_operand" "=f")
6469 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6470 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6471 "*
6472 {
6473 if (TARGET_PA_20)
6474 return \"fneg,sgl %1,%0\";
6475 else
6476 return \"fsub,sgl %%fr0,%1,%0\";
6477 }"
6478 [(set_attr "type" "fpalu")
6479 (set_attr "length" "4")])
6481 (define_insn "absdf2"
6482 [(set (match_operand:DF 0 "register_operand" "=f")
6483 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6484 "! TARGET_SOFT_FLOAT"
6485 "fabs,dbl %1,%0"
6486 [(set_attr "type" "fpalu")
6487 (set_attr "length" "4")])
6489 (define_insn "abssf2"
6490 [(set (match_operand:SF 0 "register_operand" "=f")
6491 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6492 "! TARGET_SOFT_FLOAT"
6493 "fabs,sgl %1,%0"
6494 [(set_attr "type" "fpalu")
6495 (set_attr "length" "4")])
6497 (define_insn "sqrtdf2"
6498 [(set (match_operand:DF 0 "register_operand" "=f")
6499 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6500 "! TARGET_SOFT_FLOAT"
6501 "fsqrt,dbl %1,%0"
6502 [(set_attr "type" "fpsqrtdbl")
6503 (set_attr "length" "4")])
6505 (define_insn "sqrtsf2"
6506 [(set (match_operand:SF 0 "register_operand" "=f")
6507 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6508 "! TARGET_SOFT_FLOAT"
6509 "fsqrt,sgl %1,%0"
6510 [(set_attr "type" "fpsqrtsgl")
6511 (set_attr "length" "4")])
6513 ;; PA 2.0 floating point instructions
6515 ; fmpyfadd patterns
6516 (define_insn ""
6517 [(set (match_operand:DF 0 "register_operand" "=f")
6518 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6519 (match_operand:DF 2 "register_operand" "f"))
6520 (match_operand:DF 3 "register_operand" "f")))]
6521 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6522 "fmpyfadd,dbl %1,%2,%3,%0"
6523 [(set_attr "type" "fpmuldbl")
6524 (set_attr "length" "4")])
6526 (define_insn ""
6527 [(set (match_operand:DF 0 "register_operand" "=f")
6528 (plus:DF (match_operand:DF 1 "register_operand" "f")
6529 (mult:DF (match_operand:DF 2 "register_operand" "f")
6530 (match_operand:DF 3 "register_operand" "f"))))]
6531 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6532 "fmpyfadd,dbl %2,%3,%1,%0"
6533 [(set_attr "type" "fpmuldbl")
6534 (set_attr "length" "4")])
6536 (define_insn ""
6537 [(set (match_operand:SF 0 "register_operand" "=f")
6538 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6539 (match_operand:SF 2 "register_operand" "f"))
6540 (match_operand:SF 3 "register_operand" "f")))]
6541 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6542 "fmpyfadd,sgl %1,%2,%3,%0"
6543 [(set_attr "type" "fpmulsgl")
6544 (set_attr "length" "4")])
6546 (define_insn ""
6547 [(set (match_operand:SF 0 "register_operand" "=f")
6548 (plus:SF (match_operand:SF 1 "register_operand" "f")
6549 (mult:SF (match_operand:SF 2 "register_operand" "f")
6550 (match_operand:SF 3 "register_operand" "f"))))]
6551 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6552 "fmpyfadd,sgl %2,%3,%1,%0"
6553 [(set_attr "type" "fpmulsgl")
6554 (set_attr "length" "4")])
6556 ; fmpynfadd patterns
6557 (define_insn ""
6558 [(set (match_operand:DF 0 "register_operand" "=f")
6559 (minus:DF (match_operand:DF 1 "register_operand" "f")
6560 (mult:DF (match_operand:DF 2 "register_operand" "f")
6561 (match_operand:DF 3 "register_operand" "f"))))]
6562 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6563 "fmpynfadd,dbl %2,%3,%1,%0"
6564 [(set_attr "type" "fpmuldbl")
6565 (set_attr "length" "4")])
6567 (define_insn ""
6568 [(set (match_operand:SF 0 "register_operand" "=f")
6569 (minus:SF (match_operand:SF 1 "register_operand" "f")
6570 (mult:SF (match_operand:SF 2 "register_operand" "f")
6571 (match_operand:SF 3 "register_operand" "f"))))]
6572 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6573 "fmpynfadd,sgl %2,%3,%1,%0"
6574 [(set_attr "type" "fpmulsgl")
6575 (set_attr "length" "4")])
6577 ; fnegabs patterns
6578 (define_insn ""
6579 [(set (match_operand:DF 0 "register_operand" "=f")
6580 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6581 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6582 "fnegabs,dbl %1,%0"
6583 [(set_attr "type" "fpalu")
6584 (set_attr "length" "4")])
6586 (define_insn ""
6587 [(set (match_operand:SF 0 "register_operand" "=f")
6588 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6589 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6590 "fnegabs,sgl %1,%0"
6591 [(set_attr "type" "fpalu")
6592 (set_attr "length" "4")])
6594 ;; Generating a fused multiply sequence is a win for this case as it will
6595 ;; reduce the latency for the fused case without impacting the plain
6596 ;; multiply case.
6597 ;;
6598 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6599 ;; perform two operations with the result of the first feeding the second.
6600 (define_insn ""
6601 [(set (match_operand:DF 0 "register_operand" "=f")
6602 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6603 (match_operand:DF 2 "register_operand" "f"))
6604 (match_operand:DF 3 "register_operand" "f")))
6605 (set (match_operand:DF 4 "register_operand" "=&f")
6606 (mult:DF (match_dup 1) (match_dup 2)))]
6607 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6608 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6609 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6610 "#"
6611 [(set_attr "type" "fpmuldbl")
6612 (set_attr "length" "8")])
6614 ;; We want to split this up during scheduling since we want both insns
6615 ;; to schedule independently.
6616 (define_split
6617 [(set (match_operand:DF 0 "register_operand" "")
6618 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6619 (match_operand:DF 2 "register_operand" ""))
6620 (match_operand:DF 3 "register_operand" "")))
6621 (set (match_operand:DF 4 "register_operand" "")
6622 (mult:DF (match_dup 1) (match_dup 2)))]
6623 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6624 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6625 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6626 (match_dup 3)))]
6627 "")
6629 (define_insn ""
6630 [(set (match_operand:SF 0 "register_operand" "=f")
6631 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6632 (match_operand:SF 2 "register_operand" "f"))
6633 (match_operand:SF 3 "register_operand" "f")))
6634 (set (match_operand:SF 4 "register_operand" "=&f")
6635 (mult:SF (match_dup 1) (match_dup 2)))]
6636 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6637 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6638 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6639 "#"
6640 [(set_attr "type" "fpmuldbl")
6641 (set_attr "length" "8")])
6643 ;; We want to split this up during scheduling since we want both insns
6644 ;; to schedule independently.
6645 (define_split
6646 [(set (match_operand:SF 0 "register_operand" "")
6647 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6648 (match_operand:SF 2 "register_operand" ""))
6649 (match_operand:SF 3 "register_operand" "")))
6650 (set (match_operand:SF 4 "register_operand" "")
6651 (mult:SF (match_dup 1) (match_dup 2)))]
6652 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6653 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6654 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6655 (match_dup 3)))]
6656 "")
6658 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6659 ;; instruction.
6660 (define_insn ""
6661 [(set (match_operand:DF 0 "register_operand" "=f")
6662 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6663 (match_operand:DF 2 "register_operand" "f"))))]
6664 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6665 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6666 [(set_attr "type" "fpmuldbl")
6667 (set_attr "length" "4")])
6669 (define_insn ""
6670 [(set (match_operand:SF 0 "register_operand" "=f")
6671 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6672 (match_operand:SF 2 "register_operand" "f"))))]
6673 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6674 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6675 [(set_attr "type" "fpmuldbl")
6676 (set_attr "length" "4")])
6678 (define_insn ""
6679 [(set (match_operand:DF 0 "register_operand" "=f")
6680 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6681 (match_operand:DF 2 "register_operand" "f"))))
6682 (set (match_operand:DF 3 "register_operand" "=&f")
6683 (mult:DF (match_dup 1) (match_dup 2)))]
6684 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6685 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6686 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6687 "#"
6688 [(set_attr "type" "fpmuldbl")
6689 (set_attr "length" "8")])
6691 (define_split
6692 [(set (match_operand:DF 0 "register_operand" "")
6693 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6694 (match_operand:DF 2 "register_operand" ""))))
6695 (set (match_operand:DF 3 "register_operand" "")
6696 (mult:DF (match_dup 1) (match_dup 2)))]
6697 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6698 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6699 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6700 "")
6702 (define_insn ""
6703 [(set (match_operand:SF 0 "register_operand" "=f")
6704 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6705 (match_operand:SF 2 "register_operand" "f"))))
6706 (set (match_operand:SF 3 "register_operand" "=&f")
6707 (mult:SF (match_dup 1) (match_dup 2)))]
6708 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6709 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6710 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6711 "#"
6712 [(set_attr "type" "fpmuldbl")
6713 (set_attr "length" "8")])
6715 (define_split
6716 [(set (match_operand:SF 0 "register_operand" "")
6717 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6718 (match_operand:SF 2 "register_operand" ""))))
6719 (set (match_operand:SF 3 "register_operand" "")
6720 (mult:SF (match_dup 1) (match_dup 2)))]
6721 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6722 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6723 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6724 "")
6726 ;; Now fused multiplies with the result of the multiply negated.
6727 (define_insn ""
6728 [(set (match_operand:DF 0 "register_operand" "=f")
6729 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6730 (match_operand:DF 2 "register_operand" "f")))
6731 (match_operand:DF 3 "register_operand" "f")))]
6732 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6733 "fmpynfadd,dbl %1,%2,%3,%0"
6734 [(set_attr "type" "fpmuldbl")
6735 (set_attr "length" "4")])
6737 (define_insn ""
6738 [(set (match_operand:SF 0 "register_operand" "=f")
6739 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6740 (match_operand:SF 2 "register_operand" "f")))
6741 (match_operand:SF 3 "register_operand" "f")))]
6742 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6743 "fmpynfadd,sgl %1,%2,%3,%0"
6744 [(set_attr "type" "fpmuldbl")
6745 (set_attr "length" "4")])
6747 (define_insn ""
6748 [(set (match_operand:DF 0 "register_operand" "=f")
6749 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6750 (match_operand:DF 2 "register_operand" "f")))
6751 (match_operand:DF 3 "register_operand" "f")))
6752 (set (match_operand:DF 4 "register_operand" "=&f")
6753 (mult:DF (match_dup 1) (match_dup 2)))]
6754 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6755 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6756 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6757 "#"
6758 [(set_attr "type" "fpmuldbl")
6759 (set_attr "length" "8")])
6761 (define_split
6762 [(set (match_operand:DF 0 "register_operand" "")
6763 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6764 (match_operand:DF 2 "register_operand" "")))
6765 (match_operand:DF 3 "register_operand" "")))
6766 (set (match_operand:DF 4 "register_operand" "")
6767 (mult:DF (match_dup 1) (match_dup 2)))]
6768 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6769 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6770 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6771 (match_dup 3)))]
6772 "")
6774 (define_insn ""
6775 [(set (match_operand:SF 0 "register_operand" "=f")
6776 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6777 (match_operand:SF 2 "register_operand" "f")))
6778 (match_operand:SF 3 "register_operand" "f")))
6779 (set (match_operand:SF 4 "register_operand" "=&f")
6780 (mult:SF (match_dup 1) (match_dup 2)))]
6781 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6782 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6783 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6784 "#"
6785 [(set_attr "type" "fpmuldbl")
6786 (set_attr "length" "8")])
6788 (define_split
6789 [(set (match_operand:SF 0 "register_operand" "")
6790 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6791 (match_operand:SF 2 "register_operand" "")))
6792 (match_operand:SF 3 "register_operand" "")))
6793 (set (match_operand:SF 4 "register_operand" "")
6794 (mult:SF (match_dup 1) (match_dup 2)))]
6795 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6796 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6797 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6798 (match_dup 3)))]
6799 "")
6801 (define_insn ""
6802 [(set (match_operand:DF 0 "register_operand" "=f")
6803 (minus:DF (match_operand:DF 3 "register_operand" "f")
6804 (mult:DF (match_operand:DF 1 "register_operand" "f")
6805 (match_operand:DF 2 "register_operand" "f"))))
6806 (set (match_operand:DF 4 "register_operand" "=&f")
6807 (mult:DF (match_dup 1) (match_dup 2)))]
6808 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6809 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6810 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6811 "#"
6812 [(set_attr "type" "fpmuldbl")
6813 (set_attr "length" "8")])
6815 (define_split
6816 [(set (match_operand:DF 0 "register_operand" "")
6817 (minus:DF (match_operand:DF 3 "register_operand" "")
6818 (mult:DF (match_operand:DF 1 "register_operand" "")
6819 (match_operand:DF 2 "register_operand" ""))))
6820 (set (match_operand:DF 4 "register_operand" "")
6821 (mult:DF (match_dup 1) (match_dup 2)))]
6822 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6823 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6824 (set (match_dup 0) (minus:DF (match_dup 3)
6825 (mult:DF (match_dup 1) (match_dup 2))))]
6826 "")
6828 (define_insn ""
6829 [(set (match_operand:SF 0 "register_operand" "=f")
6830 (minus:SF (match_operand:SF 3 "register_operand" "f")
6831 (mult:SF (match_operand:SF 1 "register_operand" "f")
6832 (match_operand:SF 2 "register_operand" "f"))))
6833 (set (match_operand:SF 4 "register_operand" "=&f")
6834 (mult:SF (match_dup 1) (match_dup 2)))]
6835 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6836 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6837 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6838 "#"
6839 [(set_attr "type" "fpmuldbl")
6840 (set_attr "length" "8")])
6842 (define_split
6843 [(set (match_operand:SF 0 "register_operand" "")
6844 (minus:SF (match_operand:SF 3 "register_operand" "")
6845 (mult:SF (match_operand:SF 1 "register_operand" "")
6846 (match_operand:SF 2 "register_operand" ""))))
6847 (set (match_operand:SF 4 "register_operand" "")
6848 (mult:SF (match_dup 1) (match_dup 2)))]
6849 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6850 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6851 (set (match_dup 0) (minus:SF (match_dup 3)
6852 (mult:SF (match_dup 1) (match_dup 2))))]
6853 "")
6855 (define_insn ""
6856 [(set (match_operand:DF 0 "register_operand" "=f")
6857 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6858 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6859 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6860 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6861 "#"
6862 [(set_attr "type" "fpalu")
6863 (set_attr "length" "8")])
6865 (define_split
6866 [(set (match_operand:DF 0 "register_operand" "")
6867 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6868 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6869 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6870 [(set (match_dup 2) (abs:DF (match_dup 1)))
6871 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6872 "")
6874 (define_insn ""
6875 [(set (match_operand:SF 0 "register_operand" "=f")
6876 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6877 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6878 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6879 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6880 "#"
6881 [(set_attr "type" "fpalu")
6882 (set_attr "length" "8")])
6884 (define_split
6885 [(set (match_operand:SF 0 "register_operand" "")
6886 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6887 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6888 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6889 [(set (match_dup 2) (abs:SF (match_dup 1)))
6890 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6891 "")
6892 \f
6893 ;;- Shift instructions
6895 ;; Optimized special case of shifting.
6897 (define_insn ""
6898 [(set (match_operand:SI 0 "register_operand" "=r")
6899 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6900 (const_int 24)))]
6901 ""
6902 "ldb%M1 %1,%0"
6903 [(set_attr "type" "load")
6904 (set_attr "length" "4")])
6906 (define_insn ""
6907 [(set (match_operand:SI 0 "register_operand" "=r")
6908 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6909 (const_int 16)))]
6910 ""
6911 "ldh%M1 %1,%0"
6912 [(set_attr "type" "load")
6913 (set_attr "length" "4")])
6915 (define_insn ""
6916 [(set (match_operand:SI 0 "register_operand" "=r")
6917 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6918 (match_operand:SI 3 "shadd_operand" ""))
6919 (match_operand:SI 1 "register_operand" "r")))]
6920 ""
6921 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6922 [(set_attr "type" "binary")
6923 (set_attr "length" "4")])
6925 (define_insn ""
6926 [(set (match_operand:DI 0 "register_operand" "=r")
6927 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6928 (match_operand:DI 3 "shadd_operand" ""))
6929 (match_operand:DI 1 "register_operand" "r")))]
6930 "TARGET_64BIT"
6931 "shladd,l %2,%O3,%1,%0"
6932 [(set_attr "type" "binary")
6933 (set_attr "length" "4")])
6935 (define_expand "ashlsi3"
6936 [(set (match_operand:SI 0 "register_operand" "")
6937 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6938 (match_operand:SI 2 "arith32_operand" "")))]
6939 ""
6940 "
6941 {
6942 if (GET_CODE (operands[2]) != CONST_INT)
6943 {
6944 rtx temp = gen_reg_rtx (SImode);
6945 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6946 if (GET_CODE (operands[1]) == CONST_INT)
6947 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6948 else
6949 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6950 DONE;
6951 }
6952 /* Make sure both inputs are not constants,
6953 there are no patterns for that. */
6954 operands[1] = force_reg (SImode, operands[1]);
6955 }")
6957 (define_insn ""
6958 [(set (match_operand:SI 0 "register_operand" "=r")
6959 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6960 (match_operand:SI 2 "const_int_operand" "n")))]
6961 ""
6962 "{zdep|depw,z} %1,%P2,%L2,%0"
6963 [(set_attr "type" "shift")
6964 (set_attr "length" "4")])
6966 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6967 ; Doing it like this makes slightly better code since reload can
6968 ; replace a register with a known value in range -16..15 with a
6969 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6970 ; but since we have no more CONST_OK... characters, that is not
6971 ; possible.
6972 (define_insn "zvdep32"
6973 [(set (match_operand:SI 0 "register_operand" "=r,r")
6974 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6975 (minus:SI (const_int 31)
6976 (match_operand:SI 2 "register_operand" "q,q"))))]
6977 ""
6978 "@
6979 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6980 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6981 [(set_attr "type" "shift,shift")
6982 (set_attr "length" "4,4")])
6984 (define_insn "zvdep_imm32"
6985 [(set (match_operand:SI 0 "register_operand" "=r")
6986 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6987 (minus:SI (const_int 31)
6988 (match_operand:SI 2 "register_operand" "q"))))]
6989 ""
6990 "*
6991 {
6992 int x = INTVAL (operands[1]);
6993 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6994 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6995 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6996 }"
6997 [(set_attr "type" "shift")
6998 (set_attr "length" "4")])
7000 (define_insn "vdepi_ior"
7001 [(set (match_operand:SI 0 "register_operand" "=r")
7002 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
7003 (minus:SI (const_int 31)
7004 (match_operand:SI 2 "register_operand" "q")))
7005 (match_operand:SI 3 "register_operand" "0")))]
7006 ; accept ...0001...1, can this be generalized?
7007 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
7008 "*
7009 {
7010 int x = INTVAL (operands[1]);
7011 operands[2] = GEN_INT (exact_log2 (x + 1));
7012 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
7013 }"
7014 [(set_attr "type" "shift")
7015 (set_attr "length" "4")])
7017 (define_insn "vdepi_and"
7018 [(set (match_operand:SI 0 "register_operand" "=r")
7019 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
7020 (minus:SI (const_int 31)
7021 (match_operand:SI 2 "register_operand" "q")))
7022 (match_operand:SI 3 "register_operand" "0")))]
7023 ; this can be generalized...!
7024 "INTVAL (operands[1]) == -2"
7025 "*
7026 {
7027 int x = INTVAL (operands[1]);
7028 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7029 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
7030 }"
7031 [(set_attr "type" "shift")
7032 (set_attr "length" "4")])
7034 (define_expand "ashldi3"
7035 [(set (match_operand:DI 0 "register_operand" "")
7036 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
7037 (match_operand:DI 2 "arith32_operand" "")))]
7038 "TARGET_64BIT"
7039 "
7040 {
7041 if (GET_CODE (operands[2]) != CONST_INT)
7042 {
7043 rtx temp = gen_reg_rtx (DImode);
7044 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7045 if (GET_CODE (operands[1]) == CONST_INT)
7046 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
7047 else
7048 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
7049 DONE;
7050 }
7051 /* Make sure both inputs are not constants,
7052 there are no patterns for that. */
7053 operands[1] = force_reg (DImode, operands[1]);
7054 }")
7056 (define_insn ""
7057 [(set (match_operand:DI 0 "register_operand" "=r")
7058 (ashift:DI (match_operand:DI 1 "register_operand" "r")
7059 (match_operand:DI 2 "const_int_operand" "n")))]
7060 "TARGET_64BIT"
7061 "depd,z %1,%p2,%Q2,%0"
7062 [(set_attr "type" "shift")
7063 (set_attr "length" "4")])
7065 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
7066 ; Doing it like this makes slightly better code since reload can
7067 ; replace a register with a known value in range -16..15 with a
7068 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
7069 ; but since we have no more CONST_OK... characters, that is not
7070 ; possible.
7071 (define_insn "zvdep64"
7072 [(set (match_operand:DI 0 "register_operand" "=r,r")
7073 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
7074 (minus:DI (const_int 63)
7075 (match_operand:DI 2 "register_operand" "q,q"))))]
7076 "TARGET_64BIT"
7077 "@
7078 depd,z %1,%%sar,64,%0
7079 depdi,z %1,%%sar,64,%0"
7080 [(set_attr "type" "shift,shift")
7081 (set_attr "length" "4,4")])
7083 (define_insn "zvdep_imm64"
7084 [(set (match_operand:DI 0 "register_operand" "=r")
7085 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
7086 (minus:DI (const_int 63)
7087 (match_operand:DI 2 "register_operand" "q"))))]
7088 "TARGET_64BIT"
7089 "*
7090 {
7091 int x = INTVAL (operands[1]);
7092 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7093 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
7094 return \"depdi,z %1,%%sar,%2,%0\";
7095 }"
7096 [(set_attr "type" "shift")
7097 (set_attr "length" "4")])
7099 (define_insn ""
7100 [(set (match_operand:DI 0 "register_operand" "=r")
7101 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
7102 (minus:DI (const_int 63)
7103 (match_operand:DI 2 "register_operand" "q")))
7104 (match_operand:DI 3 "register_operand" "0")))]
7105 ; accept ...0001...1, can this be generalized?
7106 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
7107 "*
7108 {
7109 int x = INTVAL (operands[1]);
7110 operands[2] = GEN_INT (exact_log2 (x + 1));
7111 return \"depdi -1,%%sar,%2,%0\";
7112 }"
7113 [(set_attr "type" "shift")
7114 (set_attr "length" "4")])
7116 (define_insn ""
7117 [(set (match_operand:DI 0 "register_operand" "=r")
7118 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
7119 (minus:DI (const_int 63)
7120 (match_operand:DI 2 "register_operand" "q")))
7121 (match_operand:DI 3 "register_operand" "0")))]
7122 ; this can be generalized...!
7123 "TARGET_64BIT && INTVAL (operands[1]) == -2"
7124 "*
7125 {
7126 int x = INTVAL (operands[1]);
7127 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7128 return \"depdi 0,%%sar,%2,%0\";
7129 }"
7130 [(set_attr "type" "shift")
7131 (set_attr "length" "4")])
7133 (define_expand "ashrsi3"
7134 [(set (match_operand:SI 0 "register_operand" "")
7135 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7136 (match_operand:SI 2 "arith32_operand" "")))]
7137 ""
7138 "
7139 {
7140 if (GET_CODE (operands[2]) != CONST_INT)
7141 {
7142 rtx temp = gen_reg_rtx (SImode);
7143 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
7144 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
7145 DONE;
7146 }
7147 }")
7149 (define_insn ""
7150 [(set (match_operand:SI 0 "register_operand" "=r")
7151 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7152 (match_operand:SI 2 "const_int_operand" "n")))]
7153 ""
7154 "{extrs|extrw,s} %1,%P2,%L2,%0"
7155 [(set_attr "type" "shift")
7156 (set_attr "length" "4")])
7158 (define_insn "vextrs32"
7159 [(set (match_operand:SI 0 "register_operand" "=r")
7160 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7161 (minus:SI (const_int 31)
7162 (match_operand:SI 2 "register_operand" "q"))))]
7163 ""
7164 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
7165 [(set_attr "type" "shift")
7166 (set_attr "length" "4")])
7168 (define_expand "ashrdi3"
7169 [(set (match_operand:DI 0 "register_operand" "")
7170 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7171 (match_operand:DI 2 "arith32_operand" "")))]
7172 "TARGET_64BIT"
7173 "
7174 {
7175 if (GET_CODE (operands[2]) != CONST_INT)
7176 {
7177 rtx temp = gen_reg_rtx (DImode);
7178 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7179 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
7180 DONE;
7181 }
7182 }")
7184 (define_insn ""
7185 [(set (match_operand:DI 0 "register_operand" "=r")
7186 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7187 (match_operand:DI 2 "const_int_operand" "n")))]
7188 "TARGET_64BIT"
7189 "extrd,s %1,%p2,%Q2,%0"
7190 [(set_attr "type" "shift")
7191 (set_attr "length" "4")])
7193 (define_insn "vextrs64"
7194 [(set (match_operand:DI 0 "register_operand" "=r")
7195 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7196 (minus:DI (const_int 63)
7197 (match_operand:DI 2 "register_operand" "q"))))]
7198 "TARGET_64BIT"
7199 "extrd,s %1,%%sar,64,%0"
7200 [(set_attr "type" "shift")
7201 (set_attr "length" "4")])
7203 (define_insn "lshrsi3"
7204 [(set (match_operand:SI 0 "register_operand" "=r,r")
7205 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7206 (match_operand:SI 2 "arith32_operand" "q,n")))]
7207 ""
7208 "@
7209 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
7210 {extru|extrw,u} %1,%P2,%L2,%0"
7211 [(set_attr "type" "shift")
7212 (set_attr "length" "4")])
7214 (define_insn "lshrdi3"
7215 [(set (match_operand:DI 0 "register_operand" "=r,r")
7216 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
7217 (match_operand:DI 2 "arith32_operand" "q,n")))]
7218 "TARGET_64BIT"
7219 "@
7220 shrpd %%r0,%1,%%sar,%0
7221 extrd,u %1,%p2,%Q2,%0"
7222 [(set_attr "type" "shift")
7223 (set_attr "length" "4")])
7225 (define_insn "rotrsi3"
7226 [(set (match_operand:SI 0 "register_operand" "=r,r")
7227 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
7228 (match_operand:SI 2 "arith32_operand" "q,n")))]
7229 ""
7230 "*
7231 {
7232 if (GET_CODE (operands[2]) == CONST_INT)
7233 {
7234 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
7235 return \"{shd|shrpw} %1,%1,%2,%0\";
7236 }
7237 else
7238 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
7239 }"
7240 [(set_attr "type" "shift")
7241 (set_attr "length" "4")])
7243 (define_expand "rotlsi3"
7244 [(set (match_operand:SI 0 "register_operand" "")
7245 (rotate:SI (match_operand:SI 1 "register_operand" "")
7246 (match_operand:SI 2 "arith32_operand" "")))]
7247 ""
7248 "
7249 {
7250 if (GET_CODE (operands[2]) != CONST_INT)
7251 {
7252 rtx temp = gen_reg_rtx (SImode);
7253 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
7254 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
7255 DONE;
7256 }
7257 /* Else expand normally. */
7258 }")
7260 (define_insn ""
7261 [(set (match_operand:SI 0 "register_operand" "=r")
7262 (rotate:SI (match_operand:SI 1 "register_operand" "r")
7263 (match_operand:SI 2 "const_int_operand" "n")))]
7264 ""
7265 "*
7266 {
7267 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
7268 return \"{shd|shrpw} %1,%1,%2,%0\";
7269 }"
7270 [(set_attr "type" "shift")
7271 (set_attr "length" "4")])
7273 (define_insn ""
7274 [(set (match_operand:SI 0 "register_operand" "=r")
7275 (match_operator:SI 5 "plus_xor_ior_operator"
7276 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7277 (match_operand:SI 3 "const_int_operand" "n"))
7278 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7279 (match_operand:SI 4 "const_int_operand" "n"))]))]
7280 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7281 "{shd|shrpw} %1,%2,%4,%0"
7282 [(set_attr "type" "shift")
7283 (set_attr "length" "4")])
7285 (define_insn ""
7286 [(set (match_operand:SI 0 "register_operand" "=r")
7287 (match_operator:SI 5 "plus_xor_ior_operator"
7288 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7289 (match_operand:SI 4 "const_int_operand" "n"))
7290 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7291 (match_operand:SI 3 "const_int_operand" "n"))]))]
7292 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7293 "{shd|shrpw} %1,%2,%4,%0"
7294 [(set_attr "type" "shift")
7295 (set_attr "length" "4")])
7297 (define_insn ""
7298 [(set (match_operand:SI 0 "register_operand" "=r")
7299 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7300 (match_operand:SI 2 "const_int_operand" ""))
7301 (match_operand:SI 3 "const_int_operand" "")))]
7302 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
7303 "*
7304 {
7305 int cnt = INTVAL (operands[2]) & 31;
7306 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7307 operands[2] = GEN_INT (31 - cnt);
7308 return \"{zdep|depw,z} %1,%2,%3,%0\";
7309 }"
7310 [(set_attr "type" "shift")
7311 (set_attr "length" "4")])
7312 \f
7313 ;; Unconditional and other jump instructions.
7315 ;; This is used for most returns.
7316 (define_insn "return_internal"
7317 [(return)
7318 (use (reg:SI 2))]
7319 ""
7320 "*
7321 {
7322 if (TARGET_PA_20)
7323 return \"bve%* (%%r2)\";
7324 return \"bv%* %%r0(%%r2)\";
7325 }"
7326 [(set_attr "type" "branch")
7327 (set_attr "length" "4")])
7329 ;; This is used for eh returns which bypass the return stub.
7330 (define_insn "return_external_pic"
7331 [(return)
7332 (clobber (reg:SI 1))
7333 (use (reg:SI 2))]
7334 "!TARGET_NO_SPACE_REGS
7335 && !TARGET_PA_20
7336 && flag_pic && current_function_calls_eh_return"
7337 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7338 [(set_attr "type" "branch")
7339 (set_attr "length" "12")])
7341 (define_expand "prologue"
7342 [(const_int 0)]
7343 ""
7344 "hppa_expand_prologue ();DONE;")
7346 (define_expand "sibcall_epilogue"
7347 [(return)]
7348 ""
7349 "
7350 {
7351 hppa_expand_epilogue ();
7352 DONE;
7353 }")
7355 (define_expand "epilogue"
7356 [(return)]
7357 ""
7358 "
7359 {
7360 rtx x;
7362 /* Try to use the trivial return first. Else use the full epilogue. */
7363 if (reload_completed
7364 && !frame_pointer_needed
7365 && !df_regs_ever_live_p (2)
7366 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
7367 x = gen_return_internal ();
7368 else
7369 {
7370 hppa_expand_epilogue ();
7372 /* EH returns bypass the normal return stub. Thus, we must do an
7373 interspace branch to return from functions that call eh_return.
7374 This is only a problem for returns from shared code on ports
7375 using space registers. */
7376 if (!TARGET_NO_SPACE_REGS
7377 && !TARGET_PA_20
7378 && flag_pic && current_function_calls_eh_return)
7379 x = gen_return_external_pic ();
7380 else
7381 x = gen_return_internal ();
7382 }
7383 emit_jump_insn (x);
7384 DONE;
7385 }")
7387 ; Used by hppa_profile_hook to load the starting address of the current
7388 ; function; operand 1 contains the address of the label in operand 3
7389 (define_insn "load_offset_label_address"
7390 [(set (match_operand:SI 0 "register_operand" "=r")
7391 (plus:SI (match_operand:SI 1 "register_operand" "r")
7392 (minus:SI (match_operand:SI 2 "" "")
7393 (label_ref:SI (match_operand 3 "" "")))))]
7394 ""
7395 "ldo %2-%l3(%1),%0"
7396 [(set_attr "type" "multi")
7397 (set_attr "length" "4")])
7399 ; Output a code label and load its address.
7400 (define_insn "lcla1"
7401 [(set (match_operand:SI 0 "register_operand" "=r")
7402 (label_ref:SI (match_operand 1 "" "")))
7403 (const_int 0)]
7404 "!TARGET_PA_20"
7405 "*
7406 {
7407 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7408 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7409 CODE_LABEL_NUMBER (operands[1]));
7410 return \"\";
7411 }"
7412 [(set_attr "type" "multi")
7413 (set_attr "length" "8")])
7415 (define_insn "lcla2"
7416 [(set (match_operand:SI 0 "register_operand" "=r")
7417 (label_ref:SI (match_operand 1 "" "")))
7418 (const_int 0)]
7419 "TARGET_PA_20"
7420 "*
7421 {
7422 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7423 CODE_LABEL_NUMBER (operands[1]));
7424 return \"mfia %0\";
7425 }"
7426 [(set_attr "type" "move")
7427 (set_attr "length" "4")])
7429 (define_insn "blockage"
7430 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7431 ""
7432 ""
7433 [(set_attr "length" "0")])
7435 (define_insn "jump"
7436 [(set (pc) (label_ref (match_operand 0 "" "")))]
7437 ""
7438 "*
7439 {
7440 /* An unconditional branch which can reach its target. */
7441 if (get_attr_length (insn) < 16)
7442 return \"b%* %l0\";
7444 return output_lbranch (operands[0], insn, 1);
7445 }"
7446 [(set_attr "type" "uncond_branch")
7447 (set_attr "pa_combine_type" "uncond_branch")
7448 (set (attr "length")
7449 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7450 (if_then_else (lt (abs (minus (match_dup 0)
7451 (plus (pc) (const_int 8))))
7452 (const_int MAX_12BIT_OFFSET))
7453 (const_int 4)
7454 (const_int 8))
7455 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7456 (const_int MAX_17BIT_OFFSET))
7457 (const_int 4)
7458 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7459 (const_int 20)
7460 (eq (symbol_ref "flag_pic") (const_int 0))
7461 (const_int 16)]
7462 (const_int 24)))])
7464 ;;; Hope this is only within a function...
7465 (define_insn "indirect_jump"
7466 [(set (pc) (match_operand 0 "register_operand" "r"))]
7467 "GET_MODE (operands[0]) == word_mode"
7468 "bv%* %%r0(%0)"
7469 [(set_attr "type" "branch")
7470 (set_attr "length" "4")])
7472 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7473 ;;; SOM target doesn't allow branching to a label inside a function.
7474 ;;; We also don't correctly compute branch distances for labels
7475 ;;; outside the current function. Thus, we use an indirect jump can't
7476 ;;; be optimized to a direct jump for all targets. We assume that
7477 ;;; the branch target is in the same space (i.e., nested function
7478 ;;; jumping to a label in an outer function in the same translation
7479 ;;; unit).
7480 (define_expand "nonlocal_goto"
7481 [(use (match_operand 0 "general_operand" ""))
7482 (use (match_operand 1 "general_operand" ""))
7483 (use (match_operand 2 "general_operand" ""))
7484 (use (match_operand 3 "general_operand" ""))]
7485 ""
7486 {
7487 rtx lab = operands[1];
7488 rtx stack = operands[2];
7489 rtx fp = operands[3];
7491 lab = copy_to_reg (lab);
7493 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7494 gen_rtx_MEM (BLKmode,
7495 gen_rtx_SCRATCH (VOIDmode))));
7496 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7497 gen_rtx_MEM (BLKmode,
7498 hard_frame_pointer_rtx)));
7500 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7501 instead of the hard_frame_pointer_rtx in the save area. As a
7502 result, an extra instruction is needed to adjust for the offset
7503 of the virtual stack variables and the frame pointer. */
7504 if (GET_CODE (fp) != REG)
7505 fp = force_reg (Pmode, fp);
7506 emit_move_insn (virtual_stack_vars_rtx, fp);
7508 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7510 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7511 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7513 /* Nonlocal goto jumps are only used between functions in the same
7514 translation unit. Thus, we can avoid the extra overhead of an
7515 interspace jump. */
7516 emit_jump_insn (gen_indirect_goto (lab));
7517 emit_barrier ();
7518 DONE;
7519 })
7521 (define_insn "indirect_goto"
7522 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7523 "GET_MODE (operands[0]) == word_mode"
7524 "bv%* %%r0(%0)"
7525 [(set_attr "type" "branch")
7526 (set_attr "length" "4")])
7528 ;;; This jump is used in branch tables where the insn length is fixed.
7529 ;;; The length of this insn is adjusted if the delay slot is not filled.
7530 (define_insn "short_jump"
7531 [(set (pc) (label_ref (match_operand 0 "" "")))
7532 (const_int 0)]
7533 ""
7534 "b%* %l0%#"
7535 [(set_attr "type" "btable_branch")
7536 (set_attr "length" "4")])
7538 ;; Subroutines of "casesi".
7539 ;; operand 0 is index
7540 ;; operand 1 is the minimum bound
7541 ;; operand 2 is the maximum bound - minimum bound + 1
7542 ;; operand 3 is CODE_LABEL for the table;
7543 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7545 (define_expand "casesi"
7546 [(match_operand:SI 0 "general_operand" "")
7547 (match_operand:SI 1 "const_int_operand" "")
7548 (match_operand:SI 2 "const_int_operand" "")
7549 (match_operand 3 "" "")
7550 (match_operand 4 "" "")]
7551 ""
7552 "
7553 {
7554 if (GET_CODE (operands[0]) != REG)
7555 operands[0] = force_reg (SImode, operands[0]);
7557 if (operands[1] != const0_rtx)
7558 {
7559 rtx index = gen_reg_rtx (SImode);
7561 operands[1] = GEN_INT (-INTVAL (operands[1]));
7562 if (!INT_14_BITS (operands[1]))
7563 operands[1] = force_reg (SImode, operands[1]);
7564 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7565 operands[0] = index;
7566 }
7568 if (!INT_5_BITS (operands[2]))
7569 operands[2] = force_reg (SImode, operands[2]);
7571 /* This branch prevents us finding an insn for the delay slot of the
7572 following vectored branch. It might be possible to use the delay
7573 slot if an index value of -1 was used to transfer to the out-of-range
7574 label. In order to do this, we would have to output the -1 vector
7575 element after the delay insn. The casesi output code would have to
7576 check if the casesi insn is in a delay branch sequence and output
7577 the delay insn if one is found. If this was done, then it might
7578 then be worthwhile to split the casesi patterns to improve scheduling.
7579 However, it's not clear that all this extra complexity is worth
7580 the effort. */
7581 emit_insn (gen_cmpsi (operands[0], operands[2]));
7582 emit_jump_insn (gen_bgtu (operands[4]));
7584 /* In 64bit mode we must make sure to wipe the upper bits of the register
7585 just in case the addition overflowed or we had random bits in the
7586 high part of the register. */
7587 if (TARGET_64BIT)
7588 {
7589 rtx index = gen_reg_rtx (DImode);
7591 emit_insn (gen_extendsidi2 (index, operands[0]));
7592 operands[0] = index;
7593 }
7595 if (TARGET_BIG_SWITCH)
7596 {
7597 if (TARGET_64BIT)
7598 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7599 else if (flag_pic)
7600 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7601 else
7602 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7603 }
7604 else
7605 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7606 DONE;
7607 }")
7609 ;;; The rtl for this pattern doesn't accurately describe what the insn
7610 ;;; actually does, particularly when case-vector elements are exploded
7611 ;;; in pa_reorg. However, the initial SET in these patterns must show
7612 ;;; the connection of the insn to the following jump table.
7613 (define_insn "casesi0"
7614 [(set (pc) (mem:SI (plus:SI
7615 (mult:SI (match_operand:SI 0 "register_operand" "r")
7616 (const_int 4))
7617 (label_ref (match_operand 1 "" "")))))]
7618 ""
7619 "blr,n %0,%%r0\;nop"
7620 [(set_attr "type" "multi")
7621 (set_attr "length" "8")])
7623 ;;; 32-bit code, absolute branch table.
7624 (define_insn "casesi32"
7625 [(set (pc) (mem:SI (plus:SI
7626 (mult:SI (match_operand:SI 0 "register_operand" "r")
7627 (const_int 4))
7628 (label_ref (match_operand 1 "" "")))))
7629 (clobber (match_scratch:SI 2 "=&r"))]
7630 "!flag_pic"
7631 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7632 [(set_attr "type" "multi")
7633 (set_attr "length" "16")])
7635 ;;; 32-bit code, relative branch table.
7636 (define_insn "casesi32p"
7637 [(set (pc) (mem:SI (plus:SI
7638 (mult:SI (match_operand:SI 0 "register_operand" "r")
7639 (const_int 4))
7640 (label_ref (match_operand 1 "" "")))))
7641 (clobber (match_scratch:SI 2 "=&r"))
7642 (clobber (match_scratch:SI 3 "=&r"))]
7643 "flag_pic"
7644 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7645 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7646 [(set_attr "type" "multi")
7647 (set (attr "length")
7648 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7649 (const_int 20)
7650 (const_int 24)))])
7652 ;;; 64-bit code, 32-bit relative branch table.
7653 (define_insn "casesi64p"
7654 [(set (pc) (mem:DI (plus:DI
7655 (mult:DI (match_operand:DI 0 "register_operand" "r")
7656 (const_int 8))
7657 (label_ref (match_operand 1 "" "")))))
7658 (clobber (match_scratch:DI 2 "=&r"))
7659 (clobber (match_scratch:DI 3 "=&r"))]
7660 ""
7661 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7662 add,l %2,%3,%3\;bv,n %%r0(%3)"
7663 [(set_attr "type" "multi")
7664 (set_attr "length" "24")])
7667 ;; Call patterns.
7668 ;;- jump to subroutine
7670 (define_expand "call"
7671 [(parallel [(call (match_operand:SI 0 "" "")
7672 (match_operand 1 "" ""))
7673 (clobber (reg:SI 2))])]
7674 ""
7675 "
7676 {
7677 rtx op, call_insn;
7678 rtx nb = operands[1];
7680 if (TARGET_PORTABLE_RUNTIME)
7681 op = force_reg (SImode, XEXP (operands[0], 0));
7682 else
7683 op = XEXP (operands[0], 0);
7685 if (TARGET_64BIT)
7686 {
7687 if (!virtuals_instantiated)
7688 emit_move_insn (arg_pointer_rtx,
7689 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7690 GEN_INT (64)));
7691 else
7692 {
7693 /* The loop pass can generate new libcalls after the virtual
7694 registers are instantiated when fpregs are disabled because
7695 the only method that we have for doing DImode multiplication
7696 is with a libcall. This could be trouble if we haven't
7697 allocated enough space for the outgoing arguments. */
7698 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7700 emit_move_insn (arg_pointer_rtx,
7701 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7702 GEN_INT (STACK_POINTER_OFFSET + 64)));
7703 }
7704 }
7706 /* Use two different patterns for calls to explicitly named functions
7707 and calls through function pointers. This is necessary as these two
7708 types of calls use different calling conventions, and CSE might try
7709 to change the named call into an indirect call in some cases (using
7710 two patterns keeps CSE from performing this optimization).
7712 We now use even more call patterns as there was a subtle bug in
7713 attempting to restore the pic register after a call using a simple
7714 move insn. During reload, a instruction involving a pseudo register
7715 with no explicit dependence on the PIC register can be converted
7716 to an equivalent load from memory using the PIC register. If we
7717 emit a simple move to restore the PIC register in the initial rtl
7718 generation, then it can potentially be repositioned during scheduling.
7719 and an instruction that eventually uses the PIC register may end up
7720 between the call and the PIC register restore.
7722 This only worked because there is a post call group of instructions
7723 that are scheduled with the call. These instructions are included
7724 in the same basic block as the call. However, calls can throw in
7725 C++ code and a basic block has to terminate at the call if the call
7726 can throw. This results in the PIC register restore being scheduled
7727 independently from the call. So, we now hide the save and restore
7728 of the PIC register in the call pattern until after reload. Then,
7729 we split the moves out. A small side benefit is that we now don't
7730 need to have a use of the PIC register in the return pattern and
7731 the final save/restore operation is not needed.
7733 I elected to just clobber %r4 in the PIC patterns and use it instead
7734 of trying to force hppa_pic_save_rtx () to a callee saved register.
7735 This might have required a new register class and constraint. It
7736 was also simpler to just handle the restore from a register than a
7737 generic pseudo. */
7738 if (TARGET_64BIT)
7739 {
7740 if (GET_CODE (op) == SYMBOL_REF)
7741 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7742 else
7743 {
7744 op = force_reg (word_mode, op);
7745 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7746 }
7747 }
7748 else
7749 {
7750 if (GET_CODE (op) == SYMBOL_REF)
7751 {
7752 if (flag_pic)
7753 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7754 else
7755 call_insn = emit_call_insn (gen_call_symref (op, nb));
7756 }
7757 else
7758 {
7759 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7761 emit_move_insn (tmpreg, force_reg (word_mode, op));
7762 if (flag_pic)
7763 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7764 else
7765 call_insn = emit_call_insn (gen_call_reg (nb));
7766 }
7767 }
7769 DONE;
7770 }")
7772 ;; We use function calls to set the attribute length of calls and millicode
7773 ;; calls. This is necessary because of the large variety of call sequences.
7774 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7775 ;; we need the same calculation in several places, maintenance becomes a
7776 ;; nightmare.
7777 ;;
7778 ;; However, this has a subtle impact on branch shortening. When the
7779 ;; expression used to set the length attribute of an instruction depends
7780 ;; on a relative address (e.g., pc or a branch address), genattrtab
7781 ;; notes that the insn's length is variable, and attempts to determine a
7782 ;; worst-case default length and code to compute an insn's current length.
7784 ;; The use of a function call hides the variable dependence of our calls
7785 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7786 ;; as variable and it only generates code for the default case using our
7787 ;; function call. Because of this, calls and millicode calls have a fixed
7788 ;; length in the branch shortening pass, and some branches will use a longer
7789 ;; code sequence than necessary. However, the length of any given call
7790 ;; will still reflect its final code location and it may be shorter than
7791 ;; the initial length estimate.
7793 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7794 ;; in the set. However, when genattrtab hits a function call in its attempt
7795 ;; to compute the default length, it marks the result as unknown and sets
7796 ;; the default result to MAX_INT ;-( One possible fix that would allow
7797 ;; calls to participate in branch shortening would be to make the call to
7798 ;; insn_default_length a target option. Then, we could massage unknown
7799 ;; results. Another fix might be to change genattrtab so that it just does
7800 ;; the call in the variable case as it already does for the fixed case.
7802 (define_insn "call_symref"
7803 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7804 (match_operand 1 "" "i"))
7805 (clobber (reg:SI 1))
7806 (clobber (reg:SI 2))
7807 (use (const_int 0))]
7808 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7809 "*
7810 {
7811 output_arg_descriptor (insn);
7812 return output_call (insn, operands[0], 0);
7813 }"
7814 [(set_attr "type" "call")
7815 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7817 (define_insn "call_symref_pic"
7818 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7819 (match_operand 1 "" "i"))
7820 (clobber (reg:SI 1))
7821 (clobber (reg:SI 2))
7822 (clobber (reg:SI 4))
7823 (use (reg:SI 19))
7824 (use (const_int 0))]
7825 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7826 "*
7827 {
7828 output_arg_descriptor (insn);
7829 return output_call (insn, operands[0], 0);
7830 }"
7831 [(set_attr "type" "call")
7832 (set (attr "length")
7833 (plus (symbol_ref "attr_length_call (insn, 0)")
7834 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7836 ;; Split out the PIC register save and restore after reload. This is
7837 ;; done only if the function returns. As the split is done after reload,
7838 ;; there are some situations in which we unnecessarily save and restore
7839 ;; %r4. This happens when there is a single call and the PIC register
7840 ;; is "dead" after the call. This isn't easy to fix as the usage of
7841 ;; the PIC register isn't completely determined until the reload pass.
7842 (define_split
7843 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7844 (match_operand 1 "" ""))
7845 (clobber (reg:SI 1))
7846 (clobber (reg:SI 2))
7847 (clobber (reg:SI 4))
7848 (use (reg:SI 19))
7849 (use (const_int 0))])]
7850 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7851 && reload_completed
7852 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7853 [(set (reg:SI 4) (reg:SI 19))
7854 (parallel [(call (mem:SI (match_dup 0))
7855 (match_dup 1))
7856 (clobber (reg:SI 1))
7857 (clobber (reg:SI 2))
7858 (use (reg:SI 19))
7859 (use (const_int 0))])
7860 (set (reg:SI 19) (reg:SI 4))]
7861 "")
7863 ;; Remove the clobber of register 4 when optimizing. This has to be
7864 ;; done with a peephole optimization rather than a split because the
7865 ;; split sequence for a call must be longer than one instruction.
7866 (define_peephole2
7867 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7868 (match_operand 1 "" ""))
7869 (clobber (reg:SI 1))
7870 (clobber (reg:SI 2))
7871 (clobber (reg:SI 4))
7872 (use (reg:SI 19))
7873 (use (const_int 0))])]
7874 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7875 [(parallel [(call (mem:SI (match_dup 0))
7876 (match_dup 1))
7877 (clobber (reg:SI 1))
7878 (clobber (reg:SI 2))
7879 (use (reg:SI 19))
7880 (use (const_int 0))])]
7881 "")
7883 (define_insn "*call_symref_pic_post_reload"
7884 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7885 (match_operand 1 "" "i"))
7886 (clobber (reg:SI 1))
7887 (clobber (reg:SI 2))
7888 (use (reg:SI 19))
7889 (use (const_int 0))]
7890 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7891 "*
7892 {
7893 output_arg_descriptor (insn);
7894 return output_call (insn, operands[0], 0);
7895 }"
7896 [(set_attr "type" "call")
7897 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7899 ;; This pattern is split if it is necessary to save and restore the
7900 ;; PIC register.
7901 (define_insn "call_symref_64bit"
7902 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7903 (match_operand 1 "" "i"))
7904 (clobber (reg:DI 1))
7905 (clobber (reg:DI 2))
7906 (clobber (reg:DI 4))
7907 (use (reg:DI 27))
7908 (use (reg:DI 29))
7909 (use (const_int 0))]
7910 "TARGET_64BIT"
7911 "*
7912 {
7913 output_arg_descriptor (insn);
7914 return output_call (insn, operands[0], 0);
7915 }"
7916 [(set_attr "type" "call")
7917 (set (attr "length")
7918 (plus (symbol_ref "attr_length_call (insn, 0)")
7919 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7921 ;; Split out the PIC register save and restore after reload. This is
7922 ;; done only if the function returns. As the split is done after reload,
7923 ;; there are some situations in which we unnecessarily save and restore
7924 ;; %r4. This happens when there is a single call and the PIC register
7925 ;; is "dead" after the call. This isn't easy to fix as the usage of
7926 ;; the PIC register isn't completely determined until the reload pass.
7927 (define_split
7928 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7929 (match_operand 1 "" ""))
7930 (clobber (reg:DI 1))
7931 (clobber (reg:DI 2))
7932 (clobber (reg:DI 4))
7933 (use (reg:DI 27))
7934 (use (reg:DI 29))
7935 (use (const_int 0))])]
7936 "TARGET_64BIT
7937 && reload_completed
7938 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7939 [(set (reg:DI 4) (reg:DI 27))
7940 (parallel [(call (mem:SI (match_dup 0))
7941 (match_dup 1))
7942 (clobber (reg:DI 1))
7943 (clobber (reg:DI 2))
7944 (use (reg:DI 27))
7945 (use (reg:DI 29))
7946 (use (const_int 0))])
7947 (set (reg:DI 27) (reg:DI 4))]
7948 "")
7950 ;; Remove the clobber of register 4 when optimizing. This has to be
7951 ;; done with a peephole optimization rather than a split because the
7952 ;; split sequence for a call must be longer than one instruction.
7953 (define_peephole2
7954 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7955 (match_operand 1 "" ""))
7956 (clobber (reg:DI 1))
7957 (clobber (reg:DI 2))
7958 (clobber (reg:DI 4))
7959 (use (reg:DI 27))
7960 (use (reg:DI 29))
7961 (use (const_int 0))])]
7962 "TARGET_64BIT && reload_completed"
7963 [(parallel [(call (mem:SI (match_dup 0))
7964 (match_dup 1))
7965 (clobber (reg:DI 1))
7966 (clobber (reg:DI 2))
7967 (use (reg:DI 27))
7968 (use (reg:DI 29))
7969 (use (const_int 0))])]
7970 "")
7972 (define_insn "*call_symref_64bit_post_reload"
7973 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7974 (match_operand 1 "" "i"))
7975 (clobber (reg:DI 1))
7976 (clobber (reg:DI 2))
7977 (use (reg:DI 27))
7978 (use (reg:DI 29))
7979 (use (const_int 0))]
7980 "TARGET_64BIT"
7981 "*
7982 {
7983 output_arg_descriptor (insn);
7984 return output_call (insn, operands[0], 0);
7985 }"
7986 [(set_attr "type" "call")
7987 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7989 (define_insn "call_reg"
7990 [(call (mem:SI (reg:SI 22))
7991 (match_operand 0 "" "i"))
7992 (clobber (reg:SI 1))
7993 (clobber (reg:SI 2))
7994 (use (const_int 1))]
7995 "!TARGET_64BIT"
7996 "*
7997 {
7998 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7999 }"
8000 [(set_attr "type" "dyncall")
8001 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8003 ;; This pattern is split if it is necessary to save and restore the
8004 ;; PIC register.
8005 (define_insn "call_reg_pic"
8006 [(call (mem:SI (reg:SI 22))
8007 (match_operand 0 "" "i"))
8008 (clobber (reg:SI 1))
8009 (clobber (reg:SI 2))
8010 (clobber (reg:SI 4))
8011 (use (reg:SI 19))
8012 (use (const_int 1))]
8013 "!TARGET_64BIT"
8014 "*
8015 {
8016 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8017 }"
8018 [(set_attr "type" "dyncall")
8019 (set (attr "length")
8020 (plus (symbol_ref "attr_length_indirect_call (insn)")
8021 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8023 ;; Split out the PIC register save and restore after reload. This is
8024 ;; done only if the function returns. As the split is done after reload,
8025 ;; there are some situations in which we unnecessarily save and restore
8026 ;; %r4. This happens when there is a single call and the PIC register
8027 ;; is "dead" after the call. This isn't easy to fix as the usage of
8028 ;; the PIC register isn't completely determined until the reload pass.
8029 (define_split
8030 [(parallel [(call (mem:SI (reg:SI 22))
8031 (match_operand 0 "" ""))
8032 (clobber (reg:SI 1))
8033 (clobber (reg:SI 2))
8034 (clobber (reg:SI 4))
8035 (use (reg:SI 19))
8036 (use (const_int 1))])]
8037 "!TARGET_64BIT
8038 && reload_completed
8039 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8040 [(set (reg:SI 4) (reg:SI 19))
8041 (parallel [(call (mem:SI (reg:SI 22))
8042 (match_dup 0))
8043 (clobber (reg:SI 1))
8044 (clobber (reg:SI 2))
8045 (use (reg:SI 19))
8046 (use (const_int 1))])
8047 (set (reg:SI 19) (reg:SI 4))]
8048 "")
8050 ;; Remove the clobber of register 4 when optimizing. This has to be
8051 ;; done with a peephole optimization rather than a split because the
8052 ;; split sequence for a call must be longer than one instruction.
8053 (define_peephole2
8054 [(parallel [(call (mem:SI (reg:SI 22))
8055 (match_operand 0 "" ""))
8056 (clobber (reg:SI 1))
8057 (clobber (reg:SI 2))
8058 (clobber (reg:SI 4))
8059 (use (reg:SI 19))
8060 (use (const_int 1))])]
8061 "!TARGET_64BIT && reload_completed"
8062 [(parallel [(call (mem:SI (reg:SI 22))
8063 (match_dup 0))
8064 (clobber (reg:SI 1))
8065 (clobber (reg:SI 2))
8066 (use (reg:SI 19))
8067 (use (const_int 1))])]
8068 "")
8070 (define_insn "*call_reg_pic_post_reload"
8071 [(call (mem:SI (reg:SI 22))
8072 (match_operand 0 "" "i"))
8073 (clobber (reg:SI 1))
8074 (clobber (reg:SI 2))
8075 (use (reg:SI 19))
8076 (use (const_int 1))]
8077 "!TARGET_64BIT"
8078 "*
8079 {
8080 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8081 }"
8082 [(set_attr "type" "dyncall")
8083 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8085 ;; This pattern is split if it is necessary to save and restore the
8086 ;; PIC register.
8087 (define_insn "call_reg_64bit"
8088 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8089 (match_operand 1 "" "i"))
8090 (clobber (reg:DI 2))
8091 (clobber (reg:DI 4))
8092 (use (reg:DI 27))
8093 (use (reg:DI 29))
8094 (use (const_int 1))]
8095 "TARGET_64BIT"
8096 "*
8097 {
8098 return output_indirect_call (insn, operands[0]);
8099 }"
8100 [(set_attr "type" "dyncall")
8101 (set (attr "length")
8102 (plus (symbol_ref "attr_length_indirect_call (insn)")
8103 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8105 ;; Split out the PIC register save and restore after reload. This is
8106 ;; done only if the function returns. As the split is done after reload,
8107 ;; there are some situations in which we unnecessarily save and restore
8108 ;; %r4. This happens when there is a single call and the PIC register
8109 ;; is "dead" after the call. This isn't easy to fix as the usage of
8110 ;; the PIC register isn't completely determined until the reload pass.
8111 (define_split
8112 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8113 (match_operand 1 "" ""))
8114 (clobber (reg:DI 2))
8115 (clobber (reg:DI 4))
8116 (use (reg:DI 27))
8117 (use (reg:DI 29))
8118 (use (const_int 1))])]
8119 "TARGET_64BIT
8120 && reload_completed
8121 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8122 [(set (reg:DI 4) (reg:DI 27))
8123 (parallel [(call (mem:SI (match_dup 0))
8124 (match_dup 1))
8125 (clobber (reg:DI 2))
8126 (use (reg:DI 27))
8127 (use (reg:DI 29))
8128 (use (const_int 1))])
8129 (set (reg:DI 27) (reg:DI 4))]
8130 "")
8132 ;; Remove the clobber of register 4 when optimizing. This has to be
8133 ;; done with a peephole optimization rather than a split because the
8134 ;; split sequence for a call must be longer than one instruction.
8135 (define_peephole2
8136 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8137 (match_operand 1 "" ""))
8138 (clobber (reg:DI 2))
8139 (clobber (reg:DI 4))
8140 (use (reg:DI 27))
8141 (use (reg:DI 29))
8142 (use (const_int 1))])]
8143 "TARGET_64BIT && reload_completed"
8144 [(parallel [(call (mem:SI (match_dup 0))
8145 (match_dup 1))
8146 (clobber (reg:DI 2))
8147 (use (reg:DI 27))
8148 (use (reg:DI 29))
8149 (use (const_int 1))])]
8150 "")
8152 (define_insn "*call_reg_64bit_post_reload"
8153 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8154 (match_operand 1 "" "i"))
8155 (clobber (reg:DI 2))
8156 (use (reg:DI 27))
8157 (use (reg:DI 29))
8158 (use (const_int 1))]
8159 "TARGET_64BIT"
8160 "*
8161 {
8162 return output_indirect_call (insn, operands[0]);
8163 }"
8164 [(set_attr "type" "dyncall")
8165 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8167 (define_expand "call_value"
8168 [(parallel [(set (match_operand 0 "" "")
8169 (call (match_operand:SI 1 "" "")
8170 (match_operand 2 "" "")))
8171 (clobber (reg:SI 2))])]
8172 ""
8173 "
8174 {
8175 rtx op, call_insn;
8176 rtx dst = operands[0];
8177 rtx nb = operands[2];
8179 if (TARGET_PORTABLE_RUNTIME)
8180 op = force_reg (SImode, XEXP (operands[1], 0));
8181 else
8182 op = XEXP (operands[1], 0);
8184 if (TARGET_64BIT)
8185 {
8186 if (!virtuals_instantiated)
8187 emit_move_insn (arg_pointer_rtx,
8188 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8189 GEN_INT (64)));
8190 else
8191 {
8192 /* The loop pass can generate new libcalls after the virtual
8193 registers are instantiated when fpregs are disabled because
8194 the only method that we have for doing DImode multiplication
8195 is with a libcall. This could be trouble if we haven't
8196 allocated enough space for the outgoing arguments. */
8197 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8199 emit_move_insn (arg_pointer_rtx,
8200 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8201 GEN_INT (STACK_POINTER_OFFSET + 64)));
8202 }
8203 }
8205 /* Use two different patterns for calls to explicitly named functions
8206 and calls through function pointers. This is necessary as these two
8207 types of calls use different calling conventions, and CSE might try
8208 to change the named call into an indirect call in some cases (using
8209 two patterns keeps CSE from performing this optimization).
8211 We now use even more call patterns as there was a subtle bug in
8212 attempting to restore the pic register after a call using a simple
8213 move insn. During reload, a instruction involving a pseudo register
8214 with no explicit dependence on the PIC register can be converted
8215 to an equivalent load from memory using the PIC register. If we
8216 emit a simple move to restore the PIC register in the initial rtl
8217 generation, then it can potentially be repositioned during scheduling.
8218 and an instruction that eventually uses the PIC register may end up
8219 between the call and the PIC register restore.
8221 This only worked because there is a post call group of instructions
8222 that are scheduled with the call. These instructions are included
8223 in the same basic block as the call. However, calls can throw in
8224 C++ code and a basic block has to terminate at the call if the call
8225 can throw. This results in the PIC register restore being scheduled
8226 independently from the call. So, we now hide the save and restore
8227 of the PIC register in the call pattern until after reload. Then,
8228 we split the moves out. A small side benefit is that we now don't
8229 need to have a use of the PIC register in the return pattern and
8230 the final save/restore operation is not needed.
8232 I elected to just clobber %r4 in the PIC patterns and use it instead
8233 of trying to force hppa_pic_save_rtx () to a callee saved register.
8234 This might have required a new register class and constraint. It
8235 was also simpler to just handle the restore from a register than a
8236 generic pseudo. */
8237 if (TARGET_64BIT)
8238 {
8239 if (GET_CODE (op) == SYMBOL_REF)
8240 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8241 else
8242 {
8243 op = force_reg (word_mode, op);
8244 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8245 }
8246 }
8247 else
8248 {
8249 if (GET_CODE (op) == SYMBOL_REF)
8250 {
8251 if (flag_pic)
8252 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8253 else
8254 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8255 }
8256 else
8257 {
8258 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8260 emit_move_insn (tmpreg, force_reg (word_mode, op));
8261 if (flag_pic)
8262 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8263 else
8264 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8265 }
8266 }
8268 DONE;
8269 }")
8271 (define_insn "call_val_symref"
8272 [(set (match_operand 0 "" "")
8273 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8274 (match_operand 2 "" "i")))
8275 (clobber (reg:SI 1))
8276 (clobber (reg:SI 2))
8277 (use (const_int 0))]
8278 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8279 "*
8280 {
8281 output_arg_descriptor (insn);
8282 return output_call (insn, operands[1], 0);
8283 }"
8284 [(set_attr "type" "call")
8285 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8287 (define_insn "call_val_symref_pic"
8288 [(set (match_operand 0 "" "")
8289 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8290 (match_operand 2 "" "i")))
8291 (clobber (reg:SI 1))
8292 (clobber (reg:SI 2))
8293 (clobber (reg:SI 4))
8294 (use (reg:SI 19))
8295 (use (const_int 0))]
8296 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8297 "*
8298 {
8299 output_arg_descriptor (insn);
8300 return output_call (insn, operands[1], 0);
8301 }"
8302 [(set_attr "type" "call")
8303 (set (attr "length")
8304 (plus (symbol_ref "attr_length_call (insn, 0)")
8305 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8307 ;; Split out the PIC register save and restore after reload. This is
8308 ;; done only if the function returns. As the split is done after reload,
8309 ;; there are some situations in which we unnecessarily save and restore
8310 ;; %r4. This happens when there is a single call and the PIC register
8311 ;; is "dead" after the call. This isn't easy to fix as the usage of
8312 ;; the PIC register isn't completely determined until the reload pass.
8313 (define_split
8314 [(parallel [(set (match_operand 0 "" "")
8315 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8316 (match_operand 2 "" "")))
8317 (clobber (reg:SI 1))
8318 (clobber (reg:SI 2))
8319 (clobber (reg:SI 4))
8320 (use (reg:SI 19))
8321 (use (const_int 0))])]
8322 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8323 && reload_completed
8324 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8325 [(set (reg:SI 4) (reg:SI 19))
8326 (parallel [(set (match_dup 0)
8327 (call (mem:SI (match_dup 1))
8328 (match_dup 2)))
8329 (clobber (reg:SI 1))
8330 (clobber (reg:SI 2))
8331 (use (reg:SI 19))
8332 (use (const_int 0))])
8333 (set (reg:SI 19) (reg:SI 4))]
8334 "")
8336 ;; Remove the clobber of register 4 when optimizing. This has to be
8337 ;; done with a peephole optimization rather than a split because the
8338 ;; split sequence for a call must be longer than one instruction.
8339 (define_peephole2
8340 [(parallel [(set (match_operand 0 "" "")
8341 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8342 (match_operand 2 "" "")))
8343 (clobber (reg:SI 1))
8344 (clobber (reg:SI 2))
8345 (clobber (reg:SI 4))
8346 (use (reg:SI 19))
8347 (use (const_int 0))])]
8348 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8349 [(parallel [(set (match_dup 0)
8350 (call (mem:SI (match_dup 1))
8351 (match_dup 2)))
8352 (clobber (reg:SI 1))
8353 (clobber (reg:SI 2))
8354 (use (reg:SI 19))
8355 (use (const_int 0))])]
8356 "")
8358 (define_insn "*call_val_symref_pic_post_reload"
8359 [(set (match_operand 0 "" "")
8360 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8361 (match_operand 2 "" "i")))
8362 (clobber (reg:SI 1))
8363 (clobber (reg:SI 2))
8364 (use (reg:SI 19))
8365 (use (const_int 0))]
8366 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8367 "*
8368 {
8369 output_arg_descriptor (insn);
8370 return output_call (insn, operands[1], 0);
8371 }"
8372 [(set_attr "type" "call")
8373 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8375 ;; This pattern is split if it is necessary to save and restore the
8376 ;; PIC register.
8377 (define_insn "call_val_symref_64bit"
8378 [(set (match_operand 0 "" "")
8379 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8380 (match_operand 2 "" "i")))
8381 (clobber (reg:DI 1))
8382 (clobber (reg:DI 2))
8383 (clobber (reg:DI 4))
8384 (use (reg:DI 27))
8385 (use (reg:DI 29))
8386 (use (const_int 0))]
8387 "TARGET_64BIT"
8388 "*
8389 {
8390 output_arg_descriptor (insn);
8391 return output_call (insn, operands[1], 0);
8392 }"
8393 [(set_attr "type" "call")
8394 (set (attr "length")
8395 (plus (symbol_ref "attr_length_call (insn, 0)")
8396 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8398 ;; Split out the PIC register save and restore after reload. This is
8399 ;; done only if the function returns. As the split is done after reload,
8400 ;; there are some situations in which we unnecessarily save and restore
8401 ;; %r4. This happens when there is a single call and the PIC register
8402 ;; is "dead" after the call. This isn't easy to fix as the usage of
8403 ;; the PIC register isn't completely determined until the reload pass.
8404 (define_split
8405 [(parallel [(set (match_operand 0 "" "")
8406 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8407 (match_operand 2 "" "")))
8408 (clobber (reg:DI 1))
8409 (clobber (reg:DI 2))
8410 (clobber (reg:DI 4))
8411 (use (reg:DI 27))
8412 (use (reg:DI 29))
8413 (use (const_int 0))])]
8414 "TARGET_64BIT
8415 && reload_completed
8416 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8417 [(set (reg:DI 4) (reg:DI 27))
8418 (parallel [(set (match_dup 0)
8419 (call (mem:SI (match_dup 1))
8420 (match_dup 2)))
8421 (clobber (reg:DI 1))
8422 (clobber (reg:DI 2))
8423 (use (reg:DI 27))
8424 (use (reg:DI 29))
8425 (use (const_int 0))])
8426 (set (reg:DI 27) (reg:DI 4))]
8427 "")
8429 ;; Remove the clobber of register 4 when optimizing. This has to be
8430 ;; done with a peephole optimization rather than a split because the
8431 ;; split sequence for a call must be longer than one instruction.
8432 (define_peephole2
8433 [(parallel [(set (match_operand 0 "" "")
8434 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8435 (match_operand 2 "" "")))
8436 (clobber (reg:DI 1))
8437 (clobber (reg:DI 2))
8438 (clobber (reg:DI 4))
8439 (use (reg:DI 27))
8440 (use (reg:DI 29))
8441 (use (const_int 0))])]
8442 "TARGET_64BIT && reload_completed"
8443 [(parallel [(set (match_dup 0)
8444 (call (mem:SI (match_dup 1))
8445 (match_dup 2)))
8446 (clobber (reg:DI 1))
8447 (clobber (reg:DI 2))
8448 (use (reg:DI 27))
8449 (use (reg:DI 29))
8450 (use (const_int 0))])]
8451 "")
8453 (define_insn "*call_val_symref_64bit_post_reload"
8454 [(set (match_operand 0 "" "")
8455 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8456 (match_operand 2 "" "i")))
8457 (clobber (reg:DI 1))
8458 (clobber (reg:DI 2))
8459 (use (reg:DI 27))
8460 (use (reg:DI 29))
8461 (use (const_int 0))]
8462 "TARGET_64BIT"
8463 "*
8464 {
8465 output_arg_descriptor (insn);
8466 return output_call (insn, operands[1], 0);
8467 }"
8468 [(set_attr "type" "call")
8469 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8471 (define_insn "call_val_reg"
8472 [(set (match_operand 0 "" "")
8473 (call (mem:SI (reg:SI 22))
8474 (match_operand 1 "" "i")))
8475 (clobber (reg:SI 1))
8476 (clobber (reg:SI 2))
8477 (use (const_int 1))]
8478 "!TARGET_64BIT"
8479 "*
8480 {
8481 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8482 }"
8483 [(set_attr "type" "dyncall")
8484 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8486 ;; This pattern is split if it is necessary to save and restore the
8487 ;; PIC register.
8488 (define_insn "call_val_reg_pic"
8489 [(set (match_operand 0 "" "")
8490 (call (mem:SI (reg:SI 22))
8491 (match_operand 1 "" "i")))
8492 (clobber (reg:SI 1))
8493 (clobber (reg:SI 2))
8494 (clobber (reg:SI 4))
8495 (use (reg:SI 19))
8496 (use (const_int 1))]
8497 "!TARGET_64BIT"
8498 "*
8499 {
8500 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8501 }"
8502 [(set_attr "type" "dyncall")
8503 (set (attr "length")
8504 (plus (symbol_ref "attr_length_indirect_call (insn)")
8505 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8507 ;; Split out the PIC register save and restore after reload. This is
8508 ;; done only if the function returns. As the split is done after reload,
8509 ;; there are some situations in which we unnecessarily save and restore
8510 ;; %r4. This happens when there is a single call and the PIC register
8511 ;; is "dead" after the call. This isn't easy to fix as the usage of
8512 ;; the PIC register isn't completely determined until the reload pass.
8513 (define_split
8514 [(parallel [(set (match_operand 0 "" "")
8515 (call (mem:SI (reg:SI 22))
8516 (match_operand 1 "" "")))
8517 (clobber (reg:SI 1))
8518 (clobber (reg:SI 2))
8519 (clobber (reg:SI 4))
8520 (use (reg:SI 19))
8521 (use (const_int 1))])]
8522 "!TARGET_64BIT
8523 && reload_completed
8524 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8525 [(set (reg:SI 4) (reg:SI 19))
8526 (parallel [(set (match_dup 0)
8527 (call (mem:SI (reg:SI 22))
8528 (match_dup 1)))
8529 (clobber (reg:SI 1))
8530 (clobber (reg:SI 2))
8531 (use (reg:SI 19))
8532 (use (const_int 1))])
8533 (set (reg:SI 19) (reg:SI 4))]
8534 "")
8536 ;; Remove the clobber of register 4 when optimizing. This has to be
8537 ;; done with a peephole optimization rather than a split because the
8538 ;; split sequence for a call must be longer than one instruction.
8539 (define_peephole2
8540 [(parallel [(set (match_operand 0 "" "")
8541 (call (mem:SI (reg:SI 22))
8542 (match_operand 1 "" "")))
8543 (clobber (reg:SI 1))
8544 (clobber (reg:SI 2))
8545 (clobber (reg:SI 4))
8546 (use (reg:SI 19))
8547 (use (const_int 1))])]
8548 "!TARGET_64BIT && reload_completed"
8549 [(parallel [(set (match_dup 0)
8550 (call (mem:SI (reg:SI 22))
8551 (match_dup 1)))
8552 (clobber (reg:SI 1))
8553 (clobber (reg:SI 2))
8554 (use (reg:SI 19))
8555 (use (const_int 1))])]
8556 "")
8558 (define_insn "*call_val_reg_pic_post_reload"
8559 [(set (match_operand 0 "" "")
8560 (call (mem:SI (reg:SI 22))
8561 (match_operand 1 "" "i")))
8562 (clobber (reg:SI 1))
8563 (clobber (reg:SI 2))
8564 (use (reg:SI 19))
8565 (use (const_int 1))]
8566 "!TARGET_64BIT"
8567 "*
8568 {
8569 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8570 }"
8571 [(set_attr "type" "dyncall")
8572 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8574 ;; This pattern is split if it is necessary to save and restore the
8575 ;; PIC register.
8576 (define_insn "call_val_reg_64bit"
8577 [(set (match_operand 0 "" "")
8578 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8579 (match_operand 2 "" "i")))
8580 (clobber (reg:DI 2))
8581 (clobber (reg:DI 4))
8582 (use (reg:DI 27))
8583 (use (reg:DI 29))
8584 (use (const_int 1))]
8585 "TARGET_64BIT"
8586 "*
8587 {
8588 return output_indirect_call (insn, operands[1]);
8589 }"
8590 [(set_attr "type" "dyncall")
8591 (set (attr "length")
8592 (plus (symbol_ref "attr_length_indirect_call (insn)")
8593 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8595 ;; Split out the PIC register save and restore after reload. This is
8596 ;; done only if the function returns. As the split is done after reload,
8597 ;; there are some situations in which we unnecessarily save and restore
8598 ;; %r4. This happens when there is a single call and the PIC register
8599 ;; is "dead" after the call. This isn't easy to fix as the usage of
8600 ;; the PIC register isn't completely determined until the reload pass.
8601 (define_split
8602 [(parallel [(set (match_operand 0 "" "")
8603 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8604 (match_operand 2 "" "")))
8605 (clobber (reg:DI 2))
8606 (clobber (reg:DI 4))
8607 (use (reg:DI 27))
8608 (use (reg:DI 29))
8609 (use (const_int 1))])]
8610 "TARGET_64BIT
8611 && reload_completed
8612 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8613 [(set (reg:DI 4) (reg:DI 27))
8614 (parallel [(set (match_dup 0)
8615 (call (mem:SI (match_dup 1))
8616 (match_dup 2)))
8617 (clobber (reg:DI 2))
8618 (use (reg:DI 27))
8619 (use (reg:DI 29))
8620 (use (const_int 1))])
8621 (set (reg:DI 27) (reg:DI 4))]
8622 "")
8624 ;; Remove the clobber of register 4 when optimizing. This has to be
8625 ;; done with a peephole optimization rather than a split because the
8626 ;; split sequence for a call must be longer than one instruction.
8627 (define_peephole2
8628 [(parallel [(set (match_operand 0 "" "")
8629 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8630 (match_operand 2 "" "")))
8631 (clobber (reg:DI 2))
8632 (clobber (reg:DI 4))
8633 (use (reg:DI 27))
8634 (use (reg:DI 29))
8635 (use (const_int 1))])]
8636 "TARGET_64BIT && reload_completed"
8637 [(parallel [(set (match_dup 0)
8638 (call (mem:SI (match_dup 1))
8639 (match_dup 2)))
8640 (clobber (reg:DI 2))
8641 (use (reg:DI 27))
8642 (use (reg:DI 29))
8643 (use (const_int 1))])]
8644 "")
8646 (define_insn "*call_val_reg_64bit_post_reload"
8647 [(set (match_operand 0 "" "")
8648 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8649 (match_operand 2 "" "i")))
8650 (clobber (reg:DI 2))
8651 (use (reg:DI 27))
8652 (use (reg:DI 29))
8653 (use (const_int 1))]
8654 "TARGET_64BIT"
8655 "*
8656 {
8657 return output_indirect_call (insn, operands[1]);
8658 }"
8659 [(set_attr "type" "dyncall")
8660 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8662 ;; Call subroutine returning any type.
8664 (define_expand "untyped_call"
8665 [(parallel [(call (match_operand 0 "" "")
8666 (const_int 0))
8667 (match_operand 1 "" "")
8668 (match_operand 2 "" "")])]
8669 ""
8670 "
8671 {
8672 int i;
8674 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8676 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8677 {
8678 rtx set = XVECEXP (operands[2], 0, i);
8679 emit_move_insn (SET_DEST (set), SET_SRC (set));
8680 }
8682 /* The optimizer does not know that the call sets the function value
8683 registers we stored in the result block. We avoid problems by
8684 claiming that all hard registers are used and clobbered at this
8685 point. */
8686 emit_insn (gen_blockage ());
8688 DONE;
8689 }")
8691 (define_expand "sibcall"
8692 [(call (match_operand:SI 0 "" "")
8693 (match_operand 1 "" ""))]
8694 "!TARGET_PORTABLE_RUNTIME"
8695 "
8696 {
8697 rtx op, call_insn;
8698 rtx nb = operands[1];
8700 op = XEXP (operands[0], 0);
8702 if (TARGET_64BIT)
8703 {
8704 if (!virtuals_instantiated)
8705 emit_move_insn (arg_pointer_rtx,
8706 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8707 GEN_INT (64)));
8708 else
8709 {
8710 /* The loop pass can generate new libcalls after the virtual
8711 registers are instantiated when fpregs are disabled because
8712 the only method that we have for doing DImode multiplication
8713 is with a libcall. This could be trouble if we haven't
8714 allocated enough space for the outgoing arguments. */
8715 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8717 emit_move_insn (arg_pointer_rtx,
8718 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8719 GEN_INT (STACK_POINTER_OFFSET + 64)));
8720 }
8721 }
8723 /* Indirect sibling calls are not allowed. */
8724 if (TARGET_64BIT)
8725 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8726 else
8727 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8729 call_insn = emit_call_insn (call_insn);
8731 if (TARGET_64BIT)
8732 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8734 /* We don't have to restore the PIC register. */
8735 if (flag_pic)
8736 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8738 DONE;
8739 }")
8741 (define_insn "sibcall_internal_symref"
8742 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8743 (match_operand 1 "" "i"))
8744 (clobber (reg:SI 1))
8745 (use (reg:SI 2))
8746 (use (const_int 0))]
8747 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8748 "*
8749 {
8750 output_arg_descriptor (insn);
8751 return output_call (insn, operands[0], 1);
8752 }"
8753 [(set_attr "type" "call")
8754 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8756 (define_insn "sibcall_internal_symref_64bit"
8757 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8758 (match_operand 1 "" "i"))
8759 (clobber (reg:DI 1))
8760 (use (reg:DI 2))
8761 (use (const_int 0))]
8762 "TARGET_64BIT"
8763 "*
8764 {
8765 output_arg_descriptor (insn);
8766 return output_call (insn, operands[0], 1);
8767 }"
8768 [(set_attr "type" "call")
8769 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8771 (define_expand "sibcall_value"
8772 [(set (match_operand 0 "" "")
8773 (call (match_operand:SI 1 "" "")
8774 (match_operand 2 "" "")))]
8775 "!TARGET_PORTABLE_RUNTIME"
8776 "
8777 {
8778 rtx op, call_insn;
8779 rtx nb = operands[1];
8781 op = XEXP (operands[1], 0);
8783 if (TARGET_64BIT)
8784 {
8785 if (!virtuals_instantiated)
8786 emit_move_insn (arg_pointer_rtx,
8787 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8788 GEN_INT (64)));
8789 else
8790 {
8791 /* The loop pass can generate new libcalls after the virtual
8792 registers are instantiated when fpregs are disabled because
8793 the only method that we have for doing DImode multiplication
8794 is with a libcall. This could be trouble if we haven't
8795 allocated enough space for the outgoing arguments. */
8796 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8798 emit_move_insn (arg_pointer_rtx,
8799 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8800 GEN_INT (STACK_POINTER_OFFSET + 64)));
8801 }
8802 }
8804 /* Indirect sibling calls are not allowed. */
8805 if (TARGET_64BIT)
8806 call_insn
8807 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8808 else
8809 call_insn
8810 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8812 call_insn = emit_call_insn (call_insn);
8814 if (TARGET_64BIT)
8815 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8817 /* We don't have to restore the PIC register. */
8818 if (flag_pic)
8819 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8821 DONE;
8822 }")
8824 (define_insn "sibcall_value_internal_symref"
8825 [(set (match_operand 0 "" "")
8826 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8827 (match_operand 2 "" "i")))
8828 (clobber (reg:SI 1))
8829 (use (reg:SI 2))
8830 (use (const_int 0))]
8831 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8832 "*
8833 {
8834 output_arg_descriptor (insn);
8835 return output_call (insn, operands[1], 1);
8836 }"
8837 [(set_attr "type" "call")
8838 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8840 (define_insn "sibcall_value_internal_symref_64bit"
8841 [(set (match_operand 0 "" "")
8842 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8843 (match_operand 2 "" "i")))
8844 (clobber (reg:DI 1))
8845 (use (reg:DI 2))
8846 (use (const_int 0))]
8847 "TARGET_64BIT"
8848 "*
8849 {
8850 output_arg_descriptor (insn);
8851 return output_call (insn, operands[1], 1);
8852 }"
8853 [(set_attr "type" "call")
8854 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8856 (define_insn "nop"
8857 [(const_int 0)]
8858 ""
8859 "nop"
8860 [(set_attr "type" "move")
8861 (set_attr "length" "4")])
8863 ;; These are just placeholders so we know where branch tables
8864 ;; begin and end.
8865 (define_insn "begin_brtab"
8866 [(const_int 1)]
8867 ""
8868 "*
8869 {
8870 /* Only GAS actually supports this pseudo-op. */
8871 if (TARGET_GAS)
8872 return \".begin_brtab\";
8873 else
8874 return \"\";
8875 }"
8876 [(set_attr "type" "move")
8877 (set_attr "length" "0")])
8879 (define_insn "end_brtab"
8880 [(const_int 2)]
8881 ""
8882 "*
8883 {
8884 /* Only GAS actually supports this pseudo-op. */
8885 if (TARGET_GAS)
8886 return \".end_brtab\";
8887 else
8888 return \"\";
8889 }"
8890 [(set_attr "type" "move")
8891 (set_attr "length" "0")])
8893 ;;; EH does longjmp's from and within the data section. Thus,
8894 ;;; an interspace branch is required for the longjmp implementation.
8895 ;;; Registers r1 and r2 are used as scratch registers for the jump
8896 ;;; when necessary.
8897 (define_expand "interspace_jump"
8898 [(parallel
8899 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8900 (clobber (match_dup 1))])]
8901 ""
8902 "
8903 {
8904 operands[1] = gen_rtx_REG (word_mode, 2);
8905 }")
8907 (define_insn ""
8908 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8909 (clobber (reg:SI 2))]
8910 "TARGET_PA_20 && !TARGET_64BIT"
8911 "bve%* (%0)"
8912 [(set_attr "type" "branch")
8913 (set_attr "length" "4")])
8915 (define_insn ""
8916 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8917 (clobber (reg:SI 2))]
8918 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8919 "be%* 0(%%sr4,%0)"
8920 [(set_attr "type" "branch")
8921 (set_attr "length" "4")])
8923 (define_insn ""
8924 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8925 (clobber (reg:SI 2))]
8926 "!TARGET_64BIT"
8927 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8928 [(set_attr "type" "branch")
8929 (set_attr "length" "12")])
8931 (define_insn ""
8932 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8933 (clobber (reg:DI 2))]
8934 "TARGET_64BIT"
8935 "bve%* (%0)"
8936 [(set_attr "type" "branch")
8937 (set_attr "length" "4")])
8939 (define_expand "builtin_longjmp"
8940 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8941 ""
8942 "
8943 {
8944 /* The elements of the buffer are, in order: */
8945 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8946 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8947 POINTER_SIZE / BITS_PER_UNIT));
8948 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8949 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8950 rtx pv = gen_rtx_REG (Pmode, 1);
8952 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8953 gen_rtx_MEM (BLKmode,
8954 gen_rtx_SCRATCH (VOIDmode))));
8955 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8956 gen_rtx_MEM (BLKmode,
8957 hard_frame_pointer_rtx)));
8959 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8960 instead of the hard_frame_pointer_rtx in the save area. We need
8961 to adjust for the offset between these two values when we have
8962 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8963 pattern, the receiver performs the adjustment. */
8964 #ifdef HAVE_nonlocal_goto
8965 if (HAVE_nonlocal_goto)
8966 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8967 else
8968 #endif
8969 emit_move_insn (hard_frame_pointer_rtx, fp);
8971 /* This bit is the same as expand_builtin_longjmp. */
8972 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8973 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8974 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8976 /* Load the label we are jumping through into r1 so that we know
8977 where to look for it when we get back to setjmp's function for
8978 restoring the gp. */
8979 emit_move_insn (pv, lab);
8981 /* Prevent the insns above from being scheduled into the delay slot
8982 of the interspace jump because the space register could change. */
8983 emit_insn (gen_blockage ());
8985 emit_jump_insn (gen_interspace_jump (pv));
8986 emit_barrier ();
8987 DONE;
8988 }")
8990 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8991 (define_expand "extzv"
8992 [(set (match_operand 0 "register_operand" "")
8993 (zero_extract (match_operand 1 "register_operand" "")
8994 (match_operand 2 "uint32_operand" "")
8995 (match_operand 3 "uint32_operand" "")))]
8996 ""
8997 "
8998 {
8999 HOST_WIDE_INT len = INTVAL (operands[2]);
9000 HOST_WIDE_INT pos = INTVAL (operands[3]);
9002 /* PA extraction insns don't support zero length bitfields or fields
9003 extending beyond the left or right-most bits. Also, we reject lengths
9004 equal to a word as they are better handled by the move patterns. */
9005 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9006 FAIL;
9008 /* From mips.md: extract_bit_field doesn't verify that our source
9009 matches the predicate, so check it again here. */
9010 if (!register_operand (operands[1], VOIDmode))
9011 FAIL;
9013 if (TARGET_64BIT)
9014 emit_insn (gen_extzv_64 (operands[0], operands[1],
9015 operands[2], operands[3]));
9016 else
9017 emit_insn (gen_extzv_32 (operands[0], operands[1],
9018 operands[2], operands[3]));
9019 DONE;
9020 }")
9022 (define_insn "extzv_32"
9023 [(set (match_operand:SI 0 "register_operand" "=r")
9024 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9025 (match_operand:SI 2 "uint5_operand" "")
9026 (match_operand:SI 3 "uint5_operand" "")))]
9027 ""
9028 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
9029 [(set_attr "type" "shift")
9030 (set_attr "length" "4")])
9032 (define_insn ""
9033 [(set (match_operand:SI 0 "register_operand" "=r")
9034 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9035 (const_int 1)
9036 (match_operand:SI 2 "register_operand" "q")))]
9037 ""
9038 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
9039 [(set_attr "type" "shift")
9040 (set_attr "length" "4")])
9042 (define_insn "extzv_64"
9043 [(set (match_operand:DI 0 "register_operand" "=r")
9044 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9045 (match_operand:DI 2 "uint32_operand" "")
9046 (match_operand:DI 3 "uint32_operand" "")))]
9047 "TARGET_64BIT"
9048 "extrd,u %1,%3+%2-1,%2,%0"
9049 [(set_attr "type" "shift")
9050 (set_attr "length" "4")])
9052 (define_insn ""
9053 [(set (match_operand:DI 0 "register_operand" "=r")
9054 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9055 (const_int 1)
9056 (match_operand:DI 2 "register_operand" "q")))]
9057 "TARGET_64BIT"
9058 "extrd,u %1,%%sar,1,%0"
9059 [(set_attr "type" "shift")
9060 (set_attr "length" "4")])
9062 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
9063 (define_expand "extv"
9064 [(set (match_operand 0 "register_operand" "")
9065 (sign_extract (match_operand 1 "register_operand" "")
9066 (match_operand 2 "uint32_operand" "")
9067 (match_operand 3 "uint32_operand" "")))]
9068 ""
9069 "
9070 {
9071 HOST_WIDE_INT len = INTVAL (operands[2]);
9072 HOST_WIDE_INT pos = INTVAL (operands[3]);
9074 /* PA extraction insns don't support zero length bitfields or fields
9075 extending beyond the left or right-most bits. Also, we reject lengths
9076 equal to a word as they are better handled by the move patterns. */
9077 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9078 FAIL;
9080 /* From mips.md: extract_bit_field doesn't verify that our source
9081 matches the predicate, so check it again here. */
9082 if (!register_operand (operands[1], VOIDmode))
9083 FAIL;
9085 if (TARGET_64BIT)
9086 emit_insn (gen_extv_64 (operands[0], operands[1],
9087 operands[2], operands[3]));
9088 else
9089 emit_insn (gen_extv_32 (operands[0], operands[1],
9090 operands[2], operands[3]));
9091 DONE;
9092 }")
9094 (define_insn "extv_32"
9095 [(set (match_operand:SI 0 "register_operand" "=r")
9096 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9097 (match_operand:SI 2 "uint5_operand" "")
9098 (match_operand:SI 3 "uint5_operand" "")))]
9099 ""
9100 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
9101 [(set_attr "type" "shift")
9102 (set_attr "length" "4")])
9104 (define_insn ""
9105 [(set (match_operand:SI 0 "register_operand" "=r")
9106 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9107 (const_int 1)
9108 (match_operand:SI 2 "register_operand" "q")))]
9109 "!TARGET_64BIT"
9110 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9111 [(set_attr "type" "shift")
9112 (set_attr "length" "4")])
9114 (define_insn "extv_64"
9115 [(set (match_operand:DI 0 "register_operand" "=r")
9116 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9117 (match_operand:DI 2 "uint32_operand" "")
9118 (match_operand:DI 3 "uint32_operand" "")))]
9119 "TARGET_64BIT"
9120 "extrd,s %1,%3+%2-1,%2,%0"
9121 [(set_attr "type" "shift")
9122 (set_attr "length" "4")])
9124 (define_insn ""
9125 [(set (match_operand:DI 0 "register_operand" "=r")
9126 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9127 (const_int 1)
9128 (match_operand:DI 2 "register_operand" "q")))]
9129 "TARGET_64BIT"
9130 "extrd,s %1,%%sar,1,%0"
9131 [(set_attr "type" "shift")
9132 (set_attr "length" "4")])
9134 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9135 (define_expand "insv"
9136 [(set (zero_extract (match_operand 0 "register_operand" "")
9137 (match_operand 1 "uint32_operand" "")
9138 (match_operand 2 "uint32_operand" ""))
9139 (match_operand 3 "arith5_operand" ""))]
9140 ""
9141 "
9142 {
9143 HOST_WIDE_INT len = INTVAL (operands[1]);
9144 HOST_WIDE_INT pos = INTVAL (operands[2]);
9146 /* PA insertion insns don't support zero length bitfields or fields
9147 extending beyond the left or right-most bits. Also, we reject lengths
9148 equal to a word as they are better handled by the move patterns. */
9149 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9150 FAIL;
9152 /* From mips.md: insert_bit_field doesn't verify that our destination
9153 matches the predicate, so check it again here. */
9154 if (!register_operand (operands[0], VOIDmode))
9155 FAIL;
9157 if (TARGET_64BIT)
9158 emit_insn (gen_insv_64 (operands[0], operands[1],
9159 operands[2], operands[3]));
9160 else
9161 emit_insn (gen_insv_32 (operands[0], operands[1],
9162 operands[2], operands[3]));
9163 DONE;
9164 }")
9166 (define_insn "insv_32"
9167 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9168 (match_operand:SI 1 "uint5_operand" "")
9169 (match_operand:SI 2 "uint5_operand" ""))
9170 (match_operand:SI 3 "arith5_operand" "r,L"))]
9171 ""
9172 "@
9173 {dep|depw} %3,%2+%1-1,%1,%0
9174 {depi|depwi} %3,%2+%1-1,%1,%0"
9175 [(set_attr "type" "shift,shift")
9176 (set_attr "length" "4,4")])
9178 ;; Optimize insertion of const_int values of type 1...1xxxx.
9179 (define_insn ""
9180 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9181 (match_operand:SI 1 "uint5_operand" "")
9182 (match_operand:SI 2 "uint5_operand" ""))
9183 (match_operand:SI 3 "const_int_operand" ""))]
9184 "(INTVAL (operands[3]) & 0x10) != 0 &&
9185 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9186 "*
9187 {
9188 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9189 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9190 }"
9191 [(set_attr "type" "shift")
9192 (set_attr "length" "4")])
9194 (define_insn "insv_64"
9195 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9196 (match_operand:DI 1 "uint32_operand" "")
9197 (match_operand:DI 2 "uint32_operand" ""))
9198 (match_operand:DI 3 "arith32_operand" "r,L"))]
9199 "TARGET_64BIT"
9200 "@
9201 depd %3,%2+%1-1,%1,%0
9202 depdi %3,%2+%1-1,%1,%0"
9203 [(set_attr "type" "shift,shift")
9204 (set_attr "length" "4,4")])
9206 ;; Optimize insertion of const_int values of type 1...1xxxx.
9207 (define_insn ""
9208 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9209 (match_operand:DI 1 "uint32_operand" "")
9210 (match_operand:DI 2 "uint32_operand" ""))
9211 (match_operand:DI 3 "const_int_operand" ""))]
9212 "(INTVAL (operands[3]) & 0x10) != 0
9213 && TARGET_64BIT
9214 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9215 "*
9216 {
9217 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9218 return \"depdi %3,%2+%1-1,%1,%0\";
9219 }"
9220 [(set_attr "type" "shift")
9221 (set_attr "length" "4")])
9223 (define_insn ""
9224 [(set (match_operand:DI 0 "register_operand" "=r")
9225 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9226 (const_int 32)))]
9227 "TARGET_64BIT"
9228 "depd,z %1,31,32,%0"
9229 [(set_attr "type" "shift")
9230 (set_attr "length" "4")])
9232 ;; This insn is used for some loop tests, typically loops reversed when
9233 ;; strength reduction is used. It is actually created when the instruction
9234 ;; combination phase combines the special loop test. Since this insn
9235 ;; is both a jump insn and has an output, it must deal with its own
9236 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
9237 ;; to not choose the register alternatives in the event a reload is needed.
9238 (define_insn "decrement_and_branch_until_zero"
9239 [(set (pc)
9240 (if_then_else
9241 (match_operator 2 "comparison_operator"
9242 [(plus:SI
9243 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9244 (match_operand:SI 1 "int5_operand" "L,L,L"))
9245 (const_int 0)])
9246 (label_ref (match_operand 3 "" ""))
9247 (pc)))
9248 (set (match_dup 0)
9249 (plus:SI (match_dup 0) (match_dup 1)))
9250 (clobber (match_scratch:SI 4 "=X,r,r"))]
9251 ""
9252 "* return output_dbra (operands, insn, which_alternative); "
9253 ;; Do not expect to understand this the first time through.
9254 [(set_attr "type" "cbranch,multi,multi")
9255 (set (attr "length")
9256 (if_then_else (eq_attr "alternative" "0")
9257 ;; Loop counter in register case
9258 ;; Short branch has length of 4
9259 ;; Long branch has length of 8, 20, 24 or 28
9260 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9261 (const_int MAX_12BIT_OFFSET))
9262 (const_int 4)
9263 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9264 (const_int MAX_17BIT_OFFSET))
9265 (const_int 8)
9266 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9267 (const_int 24)
9268 (eq (symbol_ref "flag_pic") (const_int 0))
9269 (const_int 20)]
9270 (const_int 28))
9272 ;; Loop counter in FP reg case.
9273 ;; Extra goo to deal with additional reload insns.
9274 (if_then_else (eq_attr "alternative" "1")
9275 (if_then_else (lt (match_dup 3) (pc))
9276 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9277 (const_int MAX_12BIT_OFFSET))
9278 (const_int 24)
9279 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9280 (const_int MAX_17BIT_OFFSET))
9281 (const_int 28)
9282 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9283 (const_int 44)
9284 (eq (symbol_ref "flag_pic") (const_int 0))
9285 (const_int 40)]
9286 (const_int 48))
9287 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9288 (const_int MAX_12BIT_OFFSET))
9289 (const_int 24)
9290 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9291 (const_int MAX_17BIT_OFFSET))
9292 (const_int 28)
9293 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9294 (const_int 44)
9295 (eq (symbol_ref "flag_pic") (const_int 0))
9296 (const_int 40)]
9297 (const_int 48)))
9299 ;; Loop counter in memory case.
9300 ;; Extra goo to deal with additional reload insns.
9301 (if_then_else (lt (match_dup 3) (pc))
9302 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9303 (const_int MAX_12BIT_OFFSET))
9304 (const_int 12)
9305 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9306 (const_int MAX_17BIT_OFFSET))
9307 (const_int 16)
9308 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9309 (const_int 32)
9310 (eq (symbol_ref "flag_pic") (const_int 0))
9311 (const_int 28)]
9312 (const_int 36))
9313 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9314 (const_int MAX_12BIT_OFFSET))
9315 (const_int 12)
9316 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9317 (const_int MAX_17BIT_OFFSET))
9318 (const_int 16)
9319 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9320 (const_int 32)
9321 (eq (symbol_ref "flag_pic") (const_int 0))
9322 (const_int 28)]
9323 (const_int 36))))))])
9325 (define_insn ""
9326 [(set (pc)
9327 (if_then_else
9328 (match_operator 2 "movb_comparison_operator"
9329 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9330 (label_ref (match_operand 3 "" ""))
9331 (pc)))
9332 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9333 (match_dup 1))]
9334 ""
9335 "* return output_movb (operands, insn, which_alternative, 0); "
9336 ;; Do not expect to understand this the first time through.
9337 [(set_attr "type" "cbranch,multi,multi,multi")
9338 (set (attr "length")
9339 (if_then_else (eq_attr "alternative" "0")
9340 ;; Loop counter in register case
9341 ;; Short branch has length of 4
9342 ;; Long branch has length of 8, 20, 24 or 28
9343 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9344 (const_int MAX_12BIT_OFFSET))
9345 (const_int 4)
9346 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9347 (const_int MAX_17BIT_OFFSET))
9348 (const_int 8)
9349 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9350 (const_int 24)
9351 (eq (symbol_ref "flag_pic") (const_int 0))
9352 (const_int 20)]
9353 (const_int 28))
9355 ;; Loop counter in FP reg case.
9356 ;; Extra goo to deal with additional reload insns.
9357 (if_then_else (eq_attr "alternative" "1")
9358 (if_then_else (lt (match_dup 3) (pc))
9359 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9360 (const_int MAX_12BIT_OFFSET))
9361 (const_int 12)
9362 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9363 (const_int MAX_17BIT_OFFSET))
9364 (const_int 16)
9365 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9366 (const_int 32)
9367 (eq (symbol_ref "flag_pic") (const_int 0))
9368 (const_int 28)]
9369 (const_int 36))
9370 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9371 (const_int MAX_12BIT_OFFSET))
9372 (const_int 12)
9373 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9374 (const_int MAX_17BIT_OFFSET))
9375 (const_int 16)
9376 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9377 (const_int 32)
9378 (eq (symbol_ref "flag_pic") (const_int 0))
9379 (const_int 28)]
9380 (const_int 36)))
9382 ;; Loop counter in memory or sar case.
9383 ;; Extra goo to deal with additional reload insns.
9384 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9385 (const_int MAX_12BIT_OFFSET))
9386 (const_int 8)
9387 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9388 (const_int MAX_17BIT_OFFSET))
9389 (const_int 12)
9390 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9391 (const_int 28)
9392 (eq (symbol_ref "flag_pic") (const_int 0))
9393 (const_int 24)]
9394 (const_int 32)))))])
9396 ;; Handle negated branch.
9397 (define_insn ""
9398 [(set (pc)
9399 (if_then_else
9400 (match_operator 2 "movb_comparison_operator"
9401 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9402 (pc)
9403 (label_ref (match_operand 3 "" ""))))
9404 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9405 (match_dup 1))]
9406 ""
9407 "* return output_movb (operands, insn, which_alternative, 1); "
9408 ;; Do not expect to understand this the first time through.
9409 [(set_attr "type" "cbranch,multi,multi,multi")
9410 (set (attr "length")
9411 (if_then_else (eq_attr "alternative" "0")
9412 ;; Loop counter in register case
9413 ;; Short branch has length of 4
9414 ;; Long branch has length of 8
9415 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9416 (const_int MAX_12BIT_OFFSET))
9417 (const_int 4)
9418 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9419 (const_int MAX_17BIT_OFFSET))
9420 (const_int 8)
9421 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9422 (const_int 24)
9423 (eq (symbol_ref "flag_pic") (const_int 0))
9424 (const_int 20)]
9425 (const_int 28))
9427 ;; Loop counter in FP reg case.
9428 ;; Extra goo to deal with additional reload insns.
9429 (if_then_else (eq_attr "alternative" "1")
9430 (if_then_else (lt (match_dup 3) (pc))
9431 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9432 (const_int MAX_12BIT_OFFSET))
9433 (const_int 12)
9434 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9435 (const_int MAX_17BIT_OFFSET))
9436 (const_int 16)
9437 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9438 (const_int 32)
9439 (eq (symbol_ref "flag_pic") (const_int 0))
9440 (const_int 28)]
9441 (const_int 36))
9442 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9443 (const_int MAX_12BIT_OFFSET))
9444 (const_int 12)
9445 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9446 (const_int MAX_17BIT_OFFSET))
9447 (const_int 16)
9448 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9449 (const_int 32)
9450 (eq (symbol_ref "flag_pic") (const_int 0))
9451 (const_int 28)]
9452 (const_int 36)))
9454 ;; Loop counter in memory or SAR case.
9455 ;; Extra goo to deal with additional reload insns.
9456 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9457 (const_int MAX_12BIT_OFFSET))
9458 (const_int 8)
9459 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9460 (const_int MAX_17BIT_OFFSET))
9461 (const_int 12)
9462 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9463 (const_int 28)
9464 (eq (symbol_ref "flag_pic") (const_int 0))
9465 (const_int 24)]
9466 (const_int 32)))))])
9468 (define_insn ""
9469 [(set (pc) (label_ref (match_operand 3 "" "" )))
9470 (set (match_operand:SI 0 "ireg_operand" "=r")
9471 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9472 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9473 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9474 "*
9475 {
9476 return output_parallel_addb (operands, insn);
9477 }"
9478 [(set_attr "type" "parallel_branch")
9479 (set (attr "length")
9480 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9481 (const_int MAX_12BIT_OFFSET))
9482 (const_int 4)
9483 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9484 (const_int MAX_17BIT_OFFSET))
9485 (const_int 8)
9486 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9487 (const_int 24)
9488 (eq (symbol_ref "flag_pic") (const_int 0))
9489 (const_int 20)]
9490 (const_int 28)))])
9492 (define_insn ""
9493 [(set (pc) (label_ref (match_operand 2 "" "" )))
9494 (set (match_operand:SF 0 "ireg_operand" "=r")
9495 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9496 "reload_completed"
9497 "*
9498 {
9499 return output_parallel_movb (operands, insn);
9500 }"
9501 [(set_attr "type" "parallel_branch")
9502 (set (attr "length")
9503 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9504 (const_int MAX_12BIT_OFFSET))
9505 (const_int 4)
9506 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9507 (const_int MAX_17BIT_OFFSET))
9508 (const_int 8)
9509 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9510 (const_int 24)
9511 (eq (symbol_ref "flag_pic") (const_int 0))
9512 (const_int 20)]
9513 (const_int 28)))])
9515 (define_insn ""
9516 [(set (pc) (label_ref (match_operand 2 "" "" )))
9517 (set (match_operand:SI 0 "ireg_operand" "=r")
9518 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9519 "reload_completed"
9520 "*
9521 {
9522 return output_parallel_movb (operands, insn);
9523 }"
9524 [(set_attr "type" "parallel_branch")
9525 (set (attr "length")
9526 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9527 (const_int MAX_12BIT_OFFSET))
9528 (const_int 4)
9529 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9530 (const_int MAX_17BIT_OFFSET))
9531 (const_int 8)
9532 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9533 (const_int 24)
9534 (eq (symbol_ref "flag_pic") (const_int 0))
9535 (const_int 20)]
9536 (const_int 28)))])
9538 (define_insn ""
9539 [(set (pc) (label_ref (match_operand 2 "" "" )))
9540 (set (match_operand:HI 0 "ireg_operand" "=r")
9541 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9542 "reload_completed"
9543 "*
9544 {
9545 return output_parallel_movb (operands, insn);
9546 }"
9547 [(set_attr "type" "parallel_branch")
9548 (set (attr "length")
9549 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9550 (const_int MAX_12BIT_OFFSET))
9551 (const_int 4)
9552 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9553 (const_int MAX_17BIT_OFFSET))
9554 (const_int 8)
9555 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9556 (const_int 24)
9557 (eq (symbol_ref "flag_pic") (const_int 0))
9558 (const_int 20)]
9559 (const_int 28)))])
9561 (define_insn ""
9562 [(set (pc) (label_ref (match_operand 2 "" "" )))
9563 (set (match_operand:QI 0 "ireg_operand" "=r")
9564 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9565 "reload_completed"
9566 "*
9567 {
9568 return output_parallel_movb (operands, insn);
9569 }"
9570 [(set_attr "type" "parallel_branch")
9571 (set (attr "length")
9572 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9573 (const_int MAX_12BIT_OFFSET))
9574 (const_int 4)
9575 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9576 (const_int MAX_17BIT_OFFSET))
9577 (const_int 8)
9578 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9579 (const_int 24)
9580 (eq (symbol_ref "flag_pic") (const_int 0))
9581 (const_int 20)]
9582 (const_int 28)))])
9584 (define_insn ""
9585 [(set (match_operand 0 "register_operand" "=f")
9586 (mult (match_operand 1 "register_operand" "f")
9587 (match_operand 2 "register_operand" "f")))
9588 (set (match_operand 3 "register_operand" "+f")
9589 (plus (match_operand 4 "register_operand" "f")
9590 (match_operand 5 "register_operand" "f")))]
9591 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9592 && reload_completed && fmpyaddoperands (operands)"
9593 "*
9594 {
9595 if (GET_MODE (operands[0]) == DFmode)
9596 {
9597 if (rtx_equal_p (operands[3], operands[5]))
9598 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9599 else
9600 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9601 }
9602 else
9603 {
9604 if (rtx_equal_p (operands[3], operands[5]))
9605 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9606 else
9607 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9608 }
9609 }"
9610 [(set_attr "type" "fpalu")
9611 (set_attr "length" "4")])
9613 (define_insn ""
9614 [(set (match_operand 3 "register_operand" "+f")
9615 (plus (match_operand 4 "register_operand" "f")
9616 (match_operand 5 "register_operand" "f")))
9617 (set (match_operand 0 "register_operand" "=f")
9618 (mult (match_operand 1 "register_operand" "f")
9619 (match_operand 2 "register_operand" "f")))]
9620 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9621 && reload_completed && fmpyaddoperands (operands)"
9622 "*
9623 {
9624 if (GET_MODE (operands[0]) == DFmode)
9625 {
9626 if (rtx_equal_p (operands[3], operands[5]))
9627 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9628 else
9629 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9630 }
9631 else
9632 {
9633 if (rtx_equal_p (operands[3], operands[5]))
9634 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9635 else
9636 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9637 }
9638 }"
9639 [(set_attr "type" "fpalu")
9640 (set_attr "length" "4")])
9642 (define_insn ""
9643 [(set (match_operand 0 "register_operand" "=f")
9644 (mult (match_operand 1 "register_operand" "f")
9645 (match_operand 2 "register_operand" "f")))
9646 (set (match_operand 3 "register_operand" "+f")
9647 (minus (match_operand 4 "register_operand" "f")
9648 (match_operand 5 "register_operand" "f")))]
9649 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9650 && reload_completed && fmpysuboperands (operands)"
9651 "*
9652 {
9653 if (GET_MODE (operands[0]) == DFmode)
9654 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9655 else
9656 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9657 }"
9658 [(set_attr "type" "fpalu")
9659 (set_attr "length" "4")])
9661 (define_insn ""
9662 [(set (match_operand 3 "register_operand" "+f")
9663 (minus (match_operand 4 "register_operand" "f")
9664 (match_operand 5 "register_operand" "f")))
9665 (set (match_operand 0 "register_operand" "=f")
9666 (mult (match_operand 1 "register_operand" "f")
9667 (match_operand 2 "register_operand" "f")))]
9668 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9669 && reload_completed && fmpysuboperands (operands)"
9670 "*
9671 {
9672 if (GET_MODE (operands[0]) == DFmode)
9673 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9674 else
9675 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9676 }"
9677 [(set_attr "type" "fpalu")
9678 (set_attr "length" "4")])
9680 ;; Flush the I and D cache lines from the start address (operand0)
9681 ;; to the end address (operand1). No lines are flushed if the end
9682 ;; address is less than the start address (unsigned).
9683 ;;
9684 ;; Because the range of memory flushed is variable and the size of
9685 ;; a MEM can only be a CONST_INT, the patterns specify that they
9686 ;; perform an unspecified volatile operation on all memory.
9687 ;;
9688 ;; The address range for an icache flush must lie within a single
9689 ;; space on targets with non-equivalent space registers.
9690 ;;
9691 ;; This is used by the trampoline code for nested functions.
9692 ;;
9693 ;; Operand 0 contains the start address.
9694 ;; Operand 1 contains the end address.
9695 ;; Operand 2 contains the line length to use.
9696 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
9697 (define_insn "dcacheflush"
9698 [(const_int 1)
9699 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9700 (use (match_operand 0 "pmode_register_operand" "r"))
9701 (use (match_operand 1 "pmode_register_operand" "r"))
9702 (use (match_operand 2 "pmode_register_operand" "r"))
9703 (clobber (match_scratch 3 "=&0"))]
9704 ""
9705 "*
9706 {
9707 if (TARGET_64BIT)
9708 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9709 else
9710 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9711 }"
9712 [(set_attr "type" "multi")
9713 (set_attr "length" "12")])
9715 (define_insn "icacheflush"
9716 [(const_int 2)
9717 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9718 (use (match_operand 0 "pmode_register_operand" "r"))
9719 (use (match_operand 1 "pmode_register_operand" "r"))
9720 (use (match_operand 2 "pmode_register_operand" "r"))
9721 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9722 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9723 (clobber (match_scratch 5 "=&0"))]
9724 ""
9725 "*
9726 {
9727 if (TARGET_64BIT)
9728 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9729 else
9730 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9731 }"
9732 [(set_attr "type" "multi")
9733 (set_attr "length" "52")])
9735 ;; An out-of-line prologue.
9736 (define_insn "outline_prologue_call"
9737 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9738 (clobber (reg:SI 31))
9739 (clobber (reg:SI 22))
9740 (clobber (reg:SI 21))
9741 (clobber (reg:SI 20))
9742 (clobber (reg:SI 19))
9743 (clobber (reg:SI 1))]
9744 ""
9745 "*
9746 {
9747 extern int frame_pointer_needed;
9749 /* We need two different versions depending on whether or not we
9750 need a frame pointer. Also note that we return to the instruction
9751 immediately after the branch rather than two instructions after the
9752 break as normally is the case. */
9753 if (frame_pointer_needed)
9754 {
9755 /* Must import the magic millicode routine(s). */
9756 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9758 if (TARGET_PORTABLE_RUNTIME)
9759 {
9760 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9761 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9762 NULL);
9763 }
9764 else
9765 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9766 }
9767 else
9768 {
9769 /* Must import the magic millicode routine(s). */
9770 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9772 if (TARGET_PORTABLE_RUNTIME)
9773 {
9774 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9775 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9776 }
9777 else
9778 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9779 }
9780 return \"\";
9781 }"
9782 [(set_attr "type" "multi")
9783 (set_attr "length" "8")])
9785 ;; An out-of-line epilogue.
9786 (define_insn "outline_epilogue_call"
9787 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9788 (use (reg:SI 29))
9789 (use (reg:SI 28))
9790 (clobber (reg:SI 31))
9791 (clobber (reg:SI 22))
9792 (clobber (reg:SI 21))
9793 (clobber (reg:SI 20))
9794 (clobber (reg:SI 19))
9795 (clobber (reg:SI 2))
9796 (clobber (reg:SI 1))]
9797 ""
9798 "*
9799 {
9800 extern int frame_pointer_needed;
9802 /* We need two different versions depending on whether or not we
9803 need a frame pointer. Also note that we return to the instruction
9804 immediately after the branch rather than two instructions after the
9805 break as normally is the case. */
9806 if (frame_pointer_needed)
9807 {
9808 /* Must import the magic millicode routine. */
9809 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9811 /* The out-of-line prologue will make sure we return to the right
9812 instruction. */
9813 if (TARGET_PORTABLE_RUNTIME)
9814 {
9815 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9816 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9817 NULL);
9818 }
9819 else
9820 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9821 }
9822 else
9823 {
9824 /* Must import the magic millicode routine. */
9825 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9827 /* The out-of-line prologue will make sure we return to the right
9828 instruction. */
9829 if (TARGET_PORTABLE_RUNTIME)
9830 {
9831 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9832 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9833 }
9834 else
9835 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9836 }
9837 return \"\";
9838 }"
9839 [(set_attr "type" "multi")
9840 (set_attr "length" "8")])
9842 ;; Given a function pointer, canonicalize it so it can be
9843 ;; reliably compared to another function pointer. */
9844 (define_expand "canonicalize_funcptr_for_compare"
9845 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9846 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9847 (clobber (match_dup 2))
9848 (clobber (reg:SI 26))
9849 (clobber (reg:SI 22))
9850 (clobber (reg:SI 31))])
9851 (set (match_operand:SI 0 "register_operand" "")
9852 (reg:SI 29))]
9853 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9854 "
9855 {
9856 if (TARGET_ELF32)
9857 {
9858 rtx canonicalize_funcptr_for_compare_libfunc
9859 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9861 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9862 operands[0], LCT_NORMAL, Pmode,
9863 1, operands[1], Pmode);
9864 DONE;
9865 }
9867 operands[2] = gen_reg_rtx (SImode);
9868 if (GET_CODE (operands[1]) != REG)
9869 {
9870 rtx tmp = gen_reg_rtx (Pmode);
9871 emit_move_insn (tmp, operands[1]);
9872 operands[1] = tmp;
9873 }
9874 }")
9876 (define_insn "*$$sh_func_adrs"
9877 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9878 (clobber (match_operand:SI 0 "register_operand" "=a"))
9879 (clobber (reg:SI 26))
9880 (clobber (reg:SI 22))
9881 (clobber (reg:SI 31))]
9882 "!TARGET_64BIT"
9883 "*
9884 {
9885 int length = get_attr_length (insn);
9886 rtx xoperands[2];
9888 xoperands[0] = GEN_INT (length - 8);
9889 xoperands[1] = GEN_INT (length - 16);
9891 /* Must import the magic millicode routine. */
9892 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9894 /* This is absolutely amazing.
9896 First, copy our input parameter into %r29 just in case we don't
9897 need to call $$sh_func_adrs. */
9898 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9899 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9901 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9902 we use %r26 unchanged. */
9903 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9904 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9906 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9907 4096, then again we use %r26 unchanged. */
9908 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9910 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9911 return output_millicode_call (insn,
9912 gen_rtx_SYMBOL_REF (SImode,
9913 \"$$sh_func_adrs\"));
9914 }"
9915 [(set_attr "type" "multi")
9916 (set (attr "length")
9917 (plus (symbol_ref "attr_length_millicode_call (insn)")
9918 (const_int 20)))])
9920 ;; On the PA, the PIC register is call clobbered, so it must
9921 ;; be saved & restored around calls by the caller. If the call
9922 ;; doesn't return normally (nonlocal goto, or an exception is
9923 ;; thrown), then the code at the exception handler label must
9924 ;; restore the PIC register.
9925 (define_expand "exception_receiver"
9926 [(const_int 4)]
9927 "flag_pic"
9928 "
9929 {
9930 /* On the 64-bit port, we need a blockage because there is
9931 confusion regarding the dependence of the restore on the
9932 frame pointer. As a result, the frame pointer and pic
9933 register restores sometimes are interchanged erroneously. */
9934 if (TARGET_64BIT)
9935 emit_insn (gen_blockage ());
9936 /* Restore the PIC register using hppa_pic_save_rtx (). The
9937 PIC register is not saved in the frame in 64-bit ABI. */
9938 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9939 emit_insn (gen_blockage ());
9940 DONE;
9941 }")
9943 (define_expand "builtin_setjmp_receiver"
9944 [(label_ref (match_operand 0 "" ""))]
9945 "flag_pic"
9946 "
9947 {
9948 if (TARGET_64BIT)
9949 emit_insn (gen_blockage ());
9950 /* Restore the PIC register. Hopefully, this will always be from
9951 a stack slot. The only registers that are valid after a
9952 builtin_longjmp are the stack and frame pointers. */
9953 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9954 emit_insn (gen_blockage ());
9955 DONE;
9956 }")
9958 ;; Allocate new stack space and update the saved stack pointer in the
9959 ;; frame marker. The HP C compilers also copy additional words in the
9960 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9961 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9962 ;; currently don't copy these values.
9963 ;;
9964 ;; Since the copy of the frame marker can't be done atomically, I
9965 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9966 ;; The HP compilers appear to raise the stack and copy the frame
9967 ;; marker in a strict instruction sequence. This suggests that the
9968 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9969 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9970 ;; as GAS doesn't support it, or try to keep the instructions emitted
9971 ;; here in strict sequence.
9972 (define_expand "allocate_stack"
9973 [(match_operand 0 "" "")
9974 (match_operand 1 "" "")]
9975 ""
9976 "
9977 {
9978 rtx addr;
9980 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9981 in operand 0 before adjusting the stack. */
9982 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9983 anti_adjust_stack (operands[1]);
9984 if (TARGET_HPUX_UNWIND_LIBRARY)
9985 {
9986 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9987 GEN_INT (TARGET_64BIT ? -8 : -4));
9988 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9989 }
9990 if (!TARGET_64BIT && flag_pic)
9991 {
9992 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9993 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9994 }
9995 DONE;
9996 }")
9998 (define_expand "prefetch"
9999 [(match_operand 0 "address_operand" "")
10000 (match_operand 1 "const_int_operand" "")
10001 (match_operand 2 "const_int_operand" "")]
10002 "TARGET_PA_20"
10003 {
10004 operands[0] = copy_addr_to_reg (operands[0]);
10005 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
10006 DONE;
10007 })
10009 (define_insn "prefetch_20"
10010 [(prefetch (match_operand 0 "pmode_register_operand" "r")
10011 (match_operand:SI 1 "const_int_operand" "n")
10012 (match_operand:SI 2 "const_int_operand" "n"))]
10013 "TARGET_PA_20"
10014 {
10015 /* The SL cache-control completer indicates good spatial locality but
10016 poor temporal locality. The ldw instruction with a target of general
10017 register 0 prefetches a cache line for a read. The ldd instruction
10018 prefetches a cache line for a write. */
10019 static const char * const instr[2][2] = {
10020 {
10021 "ldw,sl 0(%0),%%r0",
10022 "ldd,sl 0(%0),%%r0"
10023 },
10024 {
10025 "ldw 0(%0),%%r0",
10026 "ldd 0(%0),%%r0"
10027 }
10028 };
10029 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
10030 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
10032 return instr [locality][read_or_write];
10033 }
10034 [(set_attr "type" "load")
10035 (set_attr "length" "4")])
10037 ;; TLS Support
10038 (define_insn "tgd_load"
10039 [(set (match_operand:SI 0 "register_operand" "=r")
10040 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
10041 (clobber (reg:SI 1))
10042 (use (reg:SI 27))]
10043 ""
10044 "*
10045 {
10046 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
10047 }"
10048 [(set_attr "type" "multi")
10049 (set_attr "length" "8")])
10051 (define_insn "tgd_load_pic"
10052 [(set (match_operand:SI 0 "register_operand" "=r")
10053 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
10054 (clobber (reg:SI 1))
10055 (use (reg:SI 19))]
10056 ""
10057 "*
10058 {
10059 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
10060 }"
10061 [(set_attr "type" "multi")
10062 (set_attr "length" "8")])
10064 (define_insn "tld_load"
10065 [(set (match_operand:SI 0 "register_operand" "=r")
10066 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10067 (clobber (reg:SI 1))
10068 (use (reg:SI 27))]
10069 ""
10070 "*
10071 {
10072 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10073 }"
10074 [(set_attr "type" "multi")
10075 (set_attr "length" "8")])
10077 (define_insn "tld_load_pic"
10078 [(set (match_operand:SI 0 "register_operand" "=r")
10079 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
10080 (clobber (reg:SI 1))
10081 (use (reg:SI 19))]
10082 ""
10083 "*
10084 {
10085 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10086 }"
10087 [(set_attr "type" "multi")
10088 (set_attr "length" "8")])
10090 (define_insn "tld_offset_load"
10091 [(set (match_operand:SI 0 "register_operand" "=r")
10092 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10093 UNSPEC_TLSLDO)
10094 (match_operand:SI 2 "register_operand" "r")))
10095 (clobber (reg:SI 1))]
10096 ""
10097 "*
10098 {
10099 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10100 }"
10101 [(set_attr "type" "multi")
10102 (set_attr "length" "8")])
10104 (define_insn "tp_load"
10105 [(set (match_operand:SI 0 "register_operand" "=r")
10106 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10107 ""
10108 "mfctl %%cr27,%0"
10109 [(set_attr "type" "multi")
10110 (set_attr "length" "4")])
10112 (define_insn "tie_load"
10113 [(set (match_operand:SI 0 "register_operand" "=r")
10114 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10115 (clobber (reg:SI 1))
10116 (use (reg:SI 27))]
10117 ""
10118 "*
10119 {
10120 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10121 }"
10122 [(set_attr "type" "multi")
10123 (set_attr "length" "8")])
10125 (define_insn "tie_load_pic"
10126 [(set (match_operand:SI 0 "register_operand" "=r")
10127 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
10128 (clobber (reg:SI 1))
10129 (use (reg:SI 19))]
10130 ""
10131 "*
10132 {
10133 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10134 }"
10135 [(set_attr "type" "multi")
10136 (set_attr "length" "8")])
10138 (define_insn "tle_load"
10139 [(set (match_operand:SI 0 "register_operand" "=r")
10140 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10141 UNSPEC_TLSLE)
10142 (match_operand:SI 2 "register_operand" "r")))
10143 (clobber (reg:SI 1))]
10144 ""
10145 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10146 [(set_attr "type" "multi")
10147 (set_attr "length" "8")])