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Move body of HARD_REGNO_MODE_OK into a function: arm_hard_regno_mode_ok
[official-gcc.git] / gcc / config / arm / arm.h
blob6f055699f010cd1eaed9df79bac024b3dae937c9
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
55
56 typedef enum arm_cond_code
57 {
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 }
61 arm_cc;
62
63 extern arm_cc arm_current_cc;
64
65 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
66
67 extern int arm_target_label;
68 extern int arm_ccfsm_state;
69 extern struct rtx_def * arm_target_insn;
70 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags;
72 /* The floating point instruction architecture, can be 2 or 3 */
73 extern const char * target_fp_name;
74 /* Define the information needed to generate branch insns. This is
75 stored from the compare operation. Note that we can't use "rtx" here
76 since it hasn't been defined! */
77 extern struct rtx_def * arm_compare_op0;
78 extern struct rtx_def * arm_compare_op1;
79 /* The label of the current constant pool. */
80 extern struct rtx_def * pool_vector_label;
81 /* Set to 1 when a return insn is output, this means that the epilogue
82 is not needed. */
83 extern int return_used_this_function;
84 /* Nonzero if the prologue must setup `fp'. */
85 extern int current_function_anonymous_args;
86 \f
87 /* Just in case configure has failed to define anything. */
88 #ifndef TARGET_CPU_DEFAULT
89 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
90 #endif
91
92 /* If the configuration file doesn't specify the cpu, the subtarget may
93 override it. If it doesn't, then default to an ARM6. */
94 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
95 #undef TARGET_CPU_DEFAULT
96
97 #ifdef SUBTARGET_CPU_DEFAULT
98 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
99 #else
100 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
101 #endif
102 #endif
103
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
106 #else
107 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
108 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
109 #else
110 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
111 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
112 #else
113 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
114 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
115 #else
116 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
117 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
118 #else
119 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
120 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
121 #else
122 Unrecognized value in TARGET_CPU_DEFAULT.
123 #endif
124 #endif
125 #endif
126 #endif
127 #endif
128 #endif
129
130 #undef CPP_SPEC
131 #define CPP_SPEC "\
132 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
133 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
134
135 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
136
137 /* Set the architecture define -- if -march= is set, then it overrides
138 the -mcpu= setting. */
139 #define CPP_CPU_ARCH_SPEC "\
140 -Acpu=arm -Amachine=arm \
141 %{march=arm2:-D__ARM_ARCH_2__} \
142 %{march=arm250:-D__ARM_ARCH_2__} \
143 %{march=arm3:-D__ARM_ARCH_2__} \
144 %{march=arm6:-D__ARM_ARCH_3__} \
145 %{march=arm600:-D__ARM_ARCH_3__} \
146 %{march=arm610:-D__ARM_ARCH_3__} \
147 %{march=arm7:-D__ARM_ARCH_3__} \
148 %{march=arm700:-D__ARM_ARCH_3__} \
149 %{march=arm710:-D__ARM_ARCH_3__} \
150 %{march=arm720:-D__ARM_ARCH_3__} \
151 %{march=arm7100:-D__ARM_ARCH_3__} \
152 %{march=arm7500:-D__ARM_ARCH_3__} \
153 %{march=arm7500fe:-D__ARM_ARCH_3__} \
154 %{march=arm7m:-D__ARM_ARCH_3M__} \
155 %{march=arm7dm:-D__ARM_ARCH_3M__} \
156 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
157 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
158 %{march=arm8:-D__ARM_ARCH_4__} \
159 %{march=arm810:-D__ARM_ARCH_4__} \
160 %{march=arm9:-D__ARM_ARCH_4T__} \
161 %{march=arm920:-D__ARM_ARCH_4__} \
162 %{march=arm920t:-D__ARM_ARCH_4T__} \
163 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
164 %{march=strongarm:-D__ARM_ARCH_4__} \
165 %{march=strongarm110:-D__ARM_ARCH_4__} \
166 %{march=strongarm1100:-D__ARM_ARCH_4__} \
167 %{march=xscale:-D__ARM_ARCH_5TE__} \
168 %{march=xscale:-D__XSCALE__} \
169 %{march=armv2:-D__ARM_ARCH_2__} \
170 %{march=armv2a:-D__ARM_ARCH_2__} \
171 %{march=armv3:-D__ARM_ARCH_3__} \
172 %{march=armv3m:-D__ARM_ARCH_3M__} \
173 %{march=armv4:-D__ARM_ARCH_4__} \
174 %{march=armv4t:-D__ARM_ARCH_4T__} \
175 %{march=armv5:-D__ARM_ARCH_5__} \
176 %{march=armv5t:-D__ARM_ARCH_5T__} \
177 %{march=armv5e:-D__ARM_ARCH_5E__} \
178 %{march=armv5te:-D__ARM_ARCH_5TE__} \
179 %{!march=*: \
180 %{mcpu=arm2:-D__ARM_ARCH_2__} \
181 %{mcpu=arm250:-D__ARM_ARCH_2__} \
182 %{mcpu=arm3:-D__ARM_ARCH_2__} \
183 %{mcpu=arm6:-D__ARM_ARCH_3__} \
184 %{mcpu=arm600:-D__ARM_ARCH_3__} \
185 %{mcpu=arm610:-D__ARM_ARCH_3__} \
186 %{mcpu=arm7:-D__ARM_ARCH_3__} \
187 %{mcpu=arm700:-D__ARM_ARCH_3__} \
188 %{mcpu=arm710:-D__ARM_ARCH_3__} \
189 %{mcpu=arm720:-D__ARM_ARCH_3__} \
190 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
191 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
192 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
193 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
194 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
195 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
196 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
197 %{mcpu=arm8:-D__ARM_ARCH_4__} \
198 %{mcpu=arm810:-D__ARM_ARCH_4__} \
199 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm920:-D__ARM_ARCH_4__} \
201 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
202 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
203 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
204 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
205 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
206 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
207 %{mcpu=xscale:-D__XSCALE__} \
208 %{!mcpu*:%(cpp_cpu_arch_default)}} \
209 "
210
211 /* Define __APCS_26__ if the PC also contains the PSR */
212 #define CPP_APCS_PC_SPEC "\
213 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
214 -D__APCS_32__} \
215 %{mapcs-26:-D__APCS_26__} \
216 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
217 "
218
219 #ifndef CPP_APCS_PC_DEFAULT_SPEC
220 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
221 #endif
222
223 #define CPP_FLOAT_SPEC "\
224 %{msoft-float:\
225 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
226 -D__SOFTFP__} \
227 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
228 "
229
230 /* Default is hard float, which doesn't define anything */
231 #define CPP_FLOAT_DEFAULT_SPEC ""
232
233 #define CPP_ENDIAN_SPEC "\
234 %{mbig-endian: \
235 %{mlittle-endian: \
236 %e-mbig-endian and -mlittle-endian may not be used together} \
237 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
238 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
239 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
240 "
241
242 /* Default is little endian. */
243 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
244
245 /* Add a define for interworking. Needed when building libgcc.a.
246 This must define __THUMB_INTERWORK__ to the pre-processor if
247 interworking is enabled by default. */
248 #ifndef CPP_INTERWORK_DEFAULT_SPEC
249 #define CPP_INTERWORK_DEFAULT_SPEC ""
250 #endif
251
252 #define CPP_INTERWORK_SPEC " \
253 %{mthumb-interwork: \
254 %{mno-thumb-interwork: %eincompatible interworking options} \
255 -D__THUMB_INTERWORK__} \
256 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
257 "
258
259 #ifndef CPP_PREDEFINES
260 #define CPP_PREDEFINES ""
261 #endif
262
263 #ifndef CC1_SPEC
264 #define CC1_SPEC ""
265 #endif
266
267 /* This macro defines names of additional specifications to put in the specs
268 that can be used in various specifications like CC1_SPEC. Its definition
269 is an initializer with a subgrouping for each command option.
270
271 Each subgrouping contains a string constant, that defines the
272 specification name, and a string constant that used by the GNU CC driver
273 program.
274
275 Do not define this macro if it does not need to do anything. */
276 #define EXTRA_SPECS \
277 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
278 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
279 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
280 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
281 { "cpp_float", CPP_FLOAT_SPEC }, \
282 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
283 { "cpp_endian", CPP_ENDIAN_SPEC }, \
284 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
285 { "cpp_isa", CPP_ISA_SPEC }, \
286 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
287 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
288 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
289 SUBTARGET_EXTRA_SPECS
290
291 #ifndef SUBTARGET_EXTRA_SPECS
292 #define SUBTARGET_EXTRA_SPECS
293 #endif
294
295 #ifndef SUBTARGET_CPP_SPEC
296 #define SUBTARGET_CPP_SPEC ""
297 #endif
298 \f
299 /* Run-time Target Specification. */
300 #ifndef TARGET_VERSION
301 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
302 #endif
303
304 /* Nonzero if the function prologue (and epilogue) should obey
305 the ARM Procedure Call Standard. */
306 #define ARM_FLAG_APCS_FRAME (1 << 0)
307
308 /* Nonzero if the function prologue should output the function name to enable
309 the post mortem debugger to print a backtrace (very useful on RISCOS,
310 unused on RISCiX). Specifying this flag also enables
311 -fno-omit-frame-pointer.
312 XXX Must still be implemented in the prologue. */
313 #define ARM_FLAG_POKE (1 << 1)
314
315 /* Nonzero if floating point instructions are emulated by the FPE, in which
316 case instruction scheduling becomes very uninteresting. */
317 #define ARM_FLAG_FPE (1 << 2)
318
319 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
320 that assume restoration of the condition flags when returning from a
321 branch and link (ie a function). */
322 #define ARM_FLAG_APCS_32 (1 << 3)
323
324 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
325
326 /* Nonzero if stack checking should be performed on entry to each function
327 which allocates temporary variables on the stack. */
328 #define ARM_FLAG_APCS_STACK (1 << 4)
329
330 /* Nonzero if floating point parameters should be passed to functions in
331 floating point registers. */
332 #define ARM_FLAG_APCS_FLOAT (1 << 5)
333
334 /* Nonzero if re-entrant, position independent code should be generated.
335 This is equivalent to -fpic. */
336 #define ARM_FLAG_APCS_REENT (1 << 6)
337
338 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
339 be loaded using either LDRH or LDRB instructions. */
340 #define ARM_FLAG_MMU_TRAPS (1 << 7)
341
342 /* Nonzero if all floating point instructions are missing (and there is no
343 emulator either). Generate function calls for all ops in this case. */
344 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
345
346 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
347 #define ARM_FLAG_BIG_END (1 << 9)
348
349 /* Nonzero if we should compile for Thumb interworking. */
350 #define ARM_FLAG_INTERWORK (1 << 10)
351
352 /* Nonzero if we should have little-endian words even when compiling for
353 big-endian (for backwards compatibility with older versions of GCC). */
354 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
355
356 /* Nonzero if we need to protect the prolog from scheduling */
357 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
358
359 /* Nonzero if a call to abort should be generated if a noreturn
360 function tries to return. */
361 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
362
363 /* Nonzero if function prologues should not load the PIC register. */
364 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
365
366 /* Nonzero if all call instructions should be indirect. */
367 #define ARM_FLAG_LONG_CALLS (1 << 15)
368
369 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
370 #define ARM_FLAG_THUMB (1 << 16)
371
372 /* Set if a TPCS style stack frame should be generated, for non-leaf
373 functions, even if they do not need one. */
374 #define THUMB_FLAG_BACKTRACE (1 << 17)
375
376 /* Set if a TPCS style stack frame should be generated, for leaf
377 functions, even if they do not need one. */
378 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
379
380 /* Set if externally visible functions should assume that they
381 might be called in ARM mode, from a non-thumb aware code. */
382 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
383
384 /* Set if calls via function pointers should assume that their
385 destination is non-Thumb aware. */
386 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
387
388 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
389 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
390 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
391 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
392 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
393 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
394 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
395 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
396 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
397 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
398 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
399 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
400 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
401 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
402 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
403 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
404 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
405 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
406 #define TARGET_ARM (! TARGET_THUMB)
407 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
408 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
409 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
410 #define TARGET_BACKTRACE (leaf_function_p () \
411 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
412 : (target_flags & THUMB_FLAG_BACKTRACE))
413
414 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
415 Bit 31 is reserved. See riscix.h. */
416 #ifndef SUBTARGET_SWITCHES
417 #define SUBTARGET_SWITCHES
418 #endif
419
420 #define TARGET_SWITCHES \
421 { \
422 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
423 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
424 N_("Generate APCS conformant stack frames") }, \
425 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
426 {"poke-function-name", ARM_FLAG_POKE, \
427 N_("Store function names in object code") }, \
428 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
429 {"fpe", ARM_FLAG_FPE, "" }, \
430 {"apcs-32", ARM_FLAG_APCS_32, \
431 N_("Use the 32-bit version of the APCS") }, \
432 {"apcs-26", -ARM_FLAG_APCS_32, \
433 N_("Use the 26-bit version of the APCS") }, \
434 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
435 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
436 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
437 N_("Pass FP arguments in FP registers") }, \
438 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
439 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
440 N_("Generate re-entrant, PIC code") }, \
441 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
442 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
443 N_("The MMU will trap on unaligned accesses") }, \
444 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
446 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
447 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
448 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
449 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
450 N_("Use library calls to perform FP operations") }, \
451 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
452 N_("Use hardware floating point instructions") }, \
453 {"big-endian", ARM_FLAG_BIG_END, \
454 N_("Assume target CPU is configured as big endian") }, \
455 {"little-endian", -ARM_FLAG_BIG_END, \
456 N_("Assume target CPU is configured as little endian") }, \
457 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
458 N_("Assume big endian bytes, little endian words") }, \
459 {"thumb-interwork", ARM_FLAG_INTERWORK, \
460 N_("Support calls between Thumb and ARM instruction sets") }, \
461 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
462 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
463 N_("Generate a call to abort if a noreturn function returns")}, \
464 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
465 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
466 N_("Do not move instructions into a function's prologue") }, \
467 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
468 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
469 N_("Do not load the PIC register in function prologues") }, \
470 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
471 {"long-calls", ARM_FLAG_LONG_CALLS, \
472 N_("Generate call insns as indirect calls, if necessary") }, \
473 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
474 {"thumb", ARM_FLAG_THUMB, \
475 N_("Compile for the Thumb not the ARM") }, \
476 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
477 {"arm", -ARM_FLAG_THUMB, "" }, \
478 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
479 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
480 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
481 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
482 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
483 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
484 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
485 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
486 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
487 "" }, \
488 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
489 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
490 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
491 "" }, \
492 SUBTARGET_SWITCHES \
493 {"", TARGET_DEFAULT, "" } \
494 }
495
496 #define TARGET_OPTIONS \
497 { \
498 {"cpu=", & arm_select[0].string, \
499 N_("Specify the name of the target CPU") }, \
500 {"arch=", & arm_select[1].string, \
501 N_("Specify the name of the target architecture") }, \
502 {"tune=", & arm_select[2].string, "" }, \
503 {"fpe=", & target_fp_name, "" }, \
504 {"fp=", & target_fp_name, \
505 N_("Specify the version of the floating point emulator") }, \
506 {"structure-size-boundary=", & structure_size_string, \
507 N_("Specify the minimum bit alignment of structures") }, \
508 {"pic-register=", & arm_pic_register_string, \
509 N_("Specify the register to be used for PIC addressing") } \
510 }
511
512 struct arm_cpu_select
513 {
514 const char * string;
515 const char * name;
516 const struct processors * processors;
517 };
518
519 /* This is a magic array. If the user specifies a command line switch
520 which matches one of the entries in TARGET_OPTIONS then the corresponding
521 string pointer will be set to the value specified by the user. */
522 extern struct arm_cpu_select arm_select[];
523
524 enum prog_mode_type
525 {
526 prog_mode26,
527 prog_mode32
528 };
529
530 /* Recast the program mode class to be the prog_mode attribute */
531 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
532
533 extern enum prog_mode_type arm_prgmode;
534
535 /* What sort of floating point unit do we have? Hardware or software.
536 If software, is it issue 2 or issue 3? */
537 enum floating_point_type
538 {
539 FP_HARD,
540 FP_SOFT2,
541 FP_SOFT3
542 };
543
544 /* Recast the floating point class to be the floating point attribute. */
545 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
546
547 /* What type of floating point to tune for */
548 extern enum floating_point_type arm_fpu;
549
550 /* What type of floating point instructions are available */
551 extern enum floating_point_type arm_fpu_arch;
552
553 /* Default floating point architecture. Override in sub-target if
554 necessary. */
555 #ifndef FP_DEFAULT
556 #define FP_DEFAULT FP_SOFT2
557 #endif
558
559 /* Nonzero if the processor has a fast multiply insn, and one that does
560 a 64-bit multiply of two 32-bit values. */
561 extern int arm_fast_multiply;
562
563 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
564 extern int arm_arch4;
565
566 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
567 extern int arm_arch5;
568
569 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
570 extern int arm_arch5e;
571
572 /* Nonzero if this chip can benefit from load scheduling. */
573 extern int arm_ld_sched;
574
575 /* Nonzero if generating thumb code. */
576 extern int thumb_code;
577
578 /* Nonzero if this chip is a StrongARM. */
579 extern int arm_is_strong;
580
581 /* Nonzero if this chip is an XScale. */
582 extern int arm_is_xscale;
583
584 /* Nonzero if this chip is an ARM6 or an ARM7. */
585 extern int arm_is_6_or_7;
586
587 #ifndef TARGET_DEFAULT
588 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
589 #endif
590
591 /* The frame pointer register used in gcc has nothing to do with debugging;
592 that is controlled by the APCS-FRAME option. */
593 #define CAN_DEBUG_WITHOUT_FP
594
595 #undef TARGET_MEM_FUNCTIONS
596 #define TARGET_MEM_FUNCTIONS 1
597
598 #define OVERRIDE_OPTIONS arm_override_options ()
599
600 /* Nonzero if PIC code requires explicit qualifiers to generate
601 PLT and GOT relocs rather than the assembler doing so implicitly.
602 Subtargets can override these if required. */
603 #ifndef NEED_GOT_RELOC
604 #define NEED_GOT_RELOC 0
605 #endif
606 #ifndef NEED_PLT_RELOC
607 #define NEED_PLT_RELOC 0
608 #endif
609
610 /* Nonzero if we need to refer to the GOT with a PC-relative
611 offset. In other words, generate
612
613 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
614
615 rather than
616
617 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
618
619 The default is true, which matches NetBSD. Subtargets can
620 override this if required. */
621 #ifndef GOT_PCREL
622 #define GOT_PCREL 1
623 #endif
624 \f
625 /* Target machine storage Layout. */
626
627
628 /* Define this macro if it is advisable to hold scalars in registers
629 in a wider mode than that declared by the program. In such cases,
630 the value is constrained to be within the bounds of the declared
631 type, but kept valid in the wider mode. The signedness of the
632 extension may differ from that of the type. */
633
634 /* It is far faster to zero extend chars than to sign extend them */
635
636 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
637 if (GET_MODE_CLASS (MODE) == MODE_INT \
638 && GET_MODE_SIZE (MODE) < 4) \
639 { \
640 if (MODE == QImode) \
641 UNSIGNEDP = 1; \
642 else if (MODE == HImode) \
643 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
644 (MODE) = SImode; \
645 }
646
647 /* Define this macro if the promotion described by `PROMOTE_MODE'
648 should also be done for outgoing function arguments. */
649 /* This is required to ensure that push insns always push a word. */
650 #define PROMOTE_FUNCTION_ARGS
651
652 /* Define for XFmode extended real floating point support.
653 This will automatically cause REAL_ARITHMETIC to be defined. */
654 /* For the ARM:
655 I think I have added all the code to make this work. Unfortunately,
656 early releases of the floating point emulation code on RISCiX used a
657 different format for extended precision numbers. On my RISCiX box there
658 is a bug somewhere which causes the machine to lock up when running enquire
659 with long doubles. There is the additional aspect that Norcroft C
660 treats long doubles as doubles and we ought to remain compatible.
661 Perhaps someone with an FPA coprocessor and not running RISCiX would like
662 to try this someday. */
663 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
664
665 /* Disable XFmode patterns in md file */
666 #define ENABLE_XF_PATTERNS 0
667
668 /* Define if you don't want extended real, but do want to use the
669 software floating point emulator for REAL_ARITHMETIC and
670 decimal <-> binary conversion. */
671 /* See comment above */
672 #define REAL_ARITHMETIC
673
674 /* Define this if most significant bit is lowest numbered
675 in instructions that operate on numbered bit-fields. */
676 #define BITS_BIG_ENDIAN 0
677
678 /* Define this if most significant byte of a word is the lowest numbered.
679 Most ARM processors are run in little endian mode, so that is the default.
680 If you want to have it run-time selectable, change the definition in a
681 cover file to be TARGET_BIG_ENDIAN. */
682 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
683
684 /* Define this if most significant word of a multiword number is the lowest
685 numbered.
686 This is always false, even when in big-endian mode. */
687 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
688
689 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
690 on processor pre-defineds when compiling libgcc2.c. */
691 #if defined(__ARMEB__) && !defined(__ARMWEL__)
692 #define LIBGCC2_WORDS_BIG_ENDIAN 1
693 #else
694 #define LIBGCC2_WORDS_BIG_ENDIAN 0
695 #endif
696
697 /* Define this if most significant word of doubles is the lowest numbered.
698 This is always true, even when in little-endian mode. */
699 #define FLOAT_WORDS_BIG_ENDIAN 1
700
701 /* Number of bits in an addressable storage unit */
702 #define BITS_PER_UNIT 8
703
704 #define BITS_PER_WORD 32
705
706 #define UNITS_PER_WORD 4
707
708 #define POINTER_SIZE 32
709
710 #define PARM_BOUNDARY 32
711
712 #define STACK_BOUNDARY 32
713
714 #define FUNCTION_BOUNDARY 32
715
716 /* The lowest bit is used to indicate Thumb-mode functions, so the
717 vbit must go into the delta field of pointers to member
718 functions. */
719 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
720
721 #define EMPTY_FIELD_BOUNDARY 32
722
723 #define BIGGEST_ALIGNMENT 32
724
725 /* Make strings word-aligned so strcpy from constants will be faster. */
726 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
727
728 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
729 ((TREE_CODE (EXP) == STRING_CST \
730 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
731 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
732
733 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
734 value set in previous versions of this toolchain was 8, which produces more
735 compact structures. The command line option -mstructure_size_boundary=<n>
736 can be used to change this value. For compatibility with the ARM SDK
737 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
738 0020D) page 2-20 says "Structures are aligned on word boundaries". */
739 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
740 extern int arm_structure_size_boundary;
741
742 /* This is the value used to initialise arm_structure_size_boundary. If a
743 particular arm target wants to change the default value it should change
744 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
745 for an example of this. */
746 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
747 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
748 #endif
749
750 /* Used when parsing command line option -mstructure_size_boundary. */
751 extern const char * structure_size_string;
752
753 /* Non-zero if move instructions will actually fail to work
754 when given unaligned data. */
755 #define STRICT_ALIGNMENT 1
756
757 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
758
759 \f
760 /* Standard register usage. */
761
762 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
763 (S - saved over call).
764
765 r0 * argument word/integer result
766 r1-r3 argument word
767
768 r4-r8 S register variable
769 r9 S (rfp) register variable (real frame pointer)
770
771 r10 F S (sl) stack limit (used by -mapcs-stack-check)
772 r11 F S (fp) argument pointer
773 r12 (ip) temp workspace
774 r13 F S (sp) lower end of current stack frame
775 r14 (lr) link address/workspace
776 r15 F (pc) program counter
777
778 f0 floating point result
779 f1-f3 floating point scratch
780
781 f4-f7 S floating point variable
782
783 cc This is NOT a real register, but is used internally
784 to represent things that use or set the condition
785 codes.
786 sfp This isn't either. It is used during rtl generation
787 since the offset between the frame pointer and the
788 auto's isn't known until after register allocation.
789 afp Nor this, we only need this because of non-local
790 goto. Without it fp appears to be used and the
791 elimination code won't get rid of sfp. It tracks
792 fp exactly at all times.
793
794 *: See CONDITIONAL_REGISTER_USAGE */
795
796 /* The stack backtrace structure is as follows:
797 fp points to here: | save code pointer | [fp]
798 | return link value | [fp, #-4]
799 | return sp value | [fp, #-8]
800 | return fp value | [fp, #-12]
801 [| saved r10 value |]
802 [| saved r9 value |]
803 [| saved r8 value |]
804 [| saved r7 value |]
805 [| saved r6 value |]
806 [| saved r5 value |]
807 [| saved r4 value |]
808 [| saved r3 value |]
809 [| saved r2 value |]
810 [| saved r1 value |]
811 [| saved r0 value |]
812 [| saved f7 value |] three words
813 [| saved f6 value |] three words
814 [| saved f5 value |] three words
815 [| saved f4 value |] three words
816 r0-r3 are not normally saved in a C function. */
817
818 /* 1 for registers that have pervasive standard uses
819 and are not available for the register allocator. */
820 #define FIXED_REGISTERS \
821 { \
822 0,0,0,0,0,0,0,0, \
823 0,0,0,0,0,1,0,1, \
824 0,0,0,0,0,0,0,0, \
825 1,1,1 \
826 }
827
828 /* 1 for registers not available across function calls.
829 These must include the FIXED_REGISTERS and also any
830 registers that can be used without being saved.
831 The latter must include the registers where values are returned
832 and the register where structure-value addresses are passed.
833 Aside from that, you can include as many other registers as you like.
834 The CC is not preserved over function calls on the ARM 6, so it is
835 easier to assume this for all. SFP is preserved, since FP is. */
836 #define CALL_USED_REGISTERS \
837 { \
838 1,1,1,1,0,0,0,0, \
839 0,0,0,0,1,1,1,1, \
840 1,1,1,1,0,0,0,0, \
841 1,1,1 \
842 }
843
844 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
845 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
846 #endif
847
848 #define CONDITIONAL_REGISTER_USAGE \
849 { \
850 int regno; \
851 \
852 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
853 { \
854 for (regno = FIRST_ARM_FP_REGNUM; \
855 regno <= LAST_ARM_FP_REGNUM; ++regno) \
856 fixed_regs[regno] = call_used_regs[regno] = 1; \
857 } \
858 if (flag_pic) \
859 { \
860 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
861 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
862 } \
863 else if (TARGET_APCS_STACK) \
864 { \
865 fixed_regs[10] = 1; \
866 call_used_regs[10] = 1; \
867 } \
868 if (TARGET_APCS_FRAME) \
869 { \
870 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
871 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
872 } \
873 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
874 }
875
876 /* These are a couple of extensions to the formats accecpted
877 by asm_fprintf:
878 %@ prints out ASM_COMMENT_START
879 %r prints out REGISTER_PREFIX reg_names[arg] */
880 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
881 case '@': \
882 fputs (ASM_COMMENT_START, FILE); \
883 break; \
884 \
885 case 'r': \
886 fputs (REGISTER_PREFIX, FILE); \
887 fputs (reg_names [va_arg (ARGS, int)], FILE); \
888 break;
889
890 /* Round X up to the nearest word. */
891 #define ROUND_UP(X) (((X) + 3) & ~3)
892
893 /* Convert fron bytes to ints. */
894 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
895
896 /* The number of (integer) registers required to hold a quantity of type MODE. */
897 #define NUM_REGS(MODE) \
898 NUM_INTS (GET_MODE_SIZE (MODE))
899
900 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
901 #define NUM_REGS2(MODE, TYPE) \
902 NUM_INTS ((MODE) == BLKmode ? \
903 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
904
905 /* The number of (integer) argument register available. */
906 #define NUM_ARG_REGS 4
907
908 /* Return the regiser number of the N'th (integer) argument. */
909 #define ARG_REGISTER(N) (N - 1)
910
911 #if 0 /* FIXME: The ARM backend has special code to handle structure
912 returns, and will reserve its own hidden first argument. So
913 if this macro is enabled a *second* hidden argument will be
914 reserved, which will break binary compatibility with old
915 toolchains and also thunk handling. One day this should be
916 fixed. */
917 /* RTX for structure returns. NULL means use a hidden first argument. */
918 #define STRUCT_VALUE 0
919 #else
920 /* Register in which address to store a structure value
921 is passed to a function. */
922 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
923 #endif
924
925 /* Specify the registers used for certain standard purposes.
926 The values of these macros are register numbers. */
927
928 /* The number of the last argument register. */
929 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
930
931 /* The number of the last "lo" register (thumb). */
932 #define LAST_LO_REGNUM 7
933
934 /* The register that holds the return address in exception handlers. */
935 #define EXCEPTION_LR_REGNUM 2
936
937 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
938 as an invisible last argument (possible since varargs don't exist in
939 Pascal), so the following is not true. */
940 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
941
942 /* Define this to be where the real frame pointer is if it is not possible to
943 work out the offset between the frame pointer and the automatic variables
944 until after register allocation has taken place. FRAME_POINTER_REGNUM
945 should point to a special register that we will make sure is eliminated.
946
947 For the Thumb we have another problem. The TPCS defines the frame pointer
948 as r11, and GCC belives that it is always possible to use the frame pointer
949 as base register for addressing purposes. (See comments in
950 find_reloads_address()). But - the Thumb does not allow high registers,
951 including r11, to be used as base address registers. Hence our problem.
952
953 The solution used here, and in the old thumb port is to use r7 instead of
954 r11 as the hard frame pointer and to have special code to generate
955 backtrace structures on the stack (if required to do so via a command line
956 option) using r11. This is the only 'user visable' use of r11 as a frame
957 pointer. */
958 #define ARM_HARD_FRAME_POINTER_REGNUM 11
959 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
960
961 #define HARD_FRAME_POINTER_REGNUM \
962 (TARGET_ARM \
963 ? ARM_HARD_FRAME_POINTER_REGNUM \
964 : THUMB_HARD_FRAME_POINTER_REGNUM)
965
966 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
967
968 /* Register to use for pushing function arguments. */
969 #define STACK_POINTER_REGNUM SP_REGNUM
970
971 /* ARM floating pointer registers. */
972 #define FIRST_ARM_FP_REGNUM 16
973 #define LAST_ARM_FP_REGNUM 23
974
975 /* Base register for access to local variables of the function. */
976 #define FRAME_POINTER_REGNUM 25
977
978 /* Base register for access to arguments of the function. */
979 #define ARG_POINTER_REGNUM 26
980
981 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
982 #define FIRST_PSEUDO_REGISTER 27
983
984 /* Value should be nonzero if functions must have frame pointers.
985 Zero means the frame pointer need not be set up (and parms may be accessed
986 via the stack pointer) in functions that seem suitable.
987 If we have to have a frame pointer we might as well make use of it.
988 APCS says that the frame pointer does not need to be pushed in leaf
989 functions, or simple tail call functions. */
990 #define FRAME_POINTER_REQUIRED \
991 (current_function_has_nonlocal_label \
992 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
993
994 /* Return number of consecutive hard regs needed starting at reg REGNO
995 to hold something of mode MODE.
996 This is ordinarily the length in words of a value of mode MODE
997 but can be less for certain modes in special long registers.
998
999 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
1000 mode. */
1001 #define HARD_REGNO_NREGS(REGNO, MODE) \
1002 ((TARGET_ARM \
1003 && REGNO >= FIRST_ARM_FP_REGNUM \
1004 && REGNO != FRAME_POINTER_REGNUM \
1005 && REGNO != ARG_POINTER_REGNUM) \
1006 ? 1 : NUM_REGS (MODE))
1007
1008 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1009 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1010 arm_hard_regno_mode_ok ((REGNO), (MODE))
1011
1012 /* Value is 1 if it is a good idea to tie two pseudo registers
1013 when one has mode MODE1 and one has mode MODE2.
1014 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1015 for any hard reg, then this must be 0 for correct output. */
1016 #define MODES_TIEABLE_P(MODE1, MODE2) \
1017 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1018
1019 /* The order in which register should be allocated. It is good to use ip
1020 since no saving is required (though calls clobber it) and it never contains
1021 function parameters. It is quite good to use lr since other calls may
1022 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1023 least likely to contain a function parameter; in addition results are
1024 returned in r0. */
1025 #define REG_ALLOC_ORDER \
1026 { \
1027 3, 2, 1, 0, 12, 14, 4, 5, \
1028 6, 7, 8, 10, 9, 11, 13, 15, \
1029 16, 17, 18, 19, 20, 21, 22, 23, \
1030 24, 25, 26 \
1031 }
1032 \f
1033 /* Register and constant classes. */
1034
1035 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1036 Now that the Thumb is involved it has become more complicated. */
1037 enum reg_class
1038 {
1039 NO_REGS,
1040 FPU_REGS,
1041 LO_REGS,
1042 STACK_REG,
1043 BASE_REGS,
1044 HI_REGS,
1045 CC_REG,
1046 GENERAL_REGS,
1047 ALL_REGS,
1048 LIM_REG_CLASSES
1049 };
1050
1051 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1052
1053 /* Give names of register classes as strings for dump file. */
1054 #define REG_CLASS_NAMES \
1055 { \
1056 "NO_REGS", \
1057 "FPU_REGS", \
1058 "LO_REGS", \
1059 "STACK_REG", \
1060 "BASE_REGS", \
1061 "HI_REGS", \
1062 "CC_REG", \
1063 "GENERAL_REGS", \
1064 "ALL_REGS", \
1065 }
1066
1067 /* Define which registers fit in which classes.
1068 This is an initializer for a vector of HARD_REG_SET
1069 of length N_REG_CLASSES. */
1070 #define REG_CLASS_CONTENTS \
1071 { \
1072 { 0x0000000 }, /* NO_REGS */ \
1073 { 0x0FF0000 }, /* FPU_REGS */ \
1074 { 0x00000FF }, /* LO_REGS */ \
1075 { 0x0002000 }, /* STACK_REG */ \
1076 { 0x00020FF }, /* BASE_REGS */ \
1077 { 0x000FF00 }, /* HI_REGS */ \
1078 { 0x1000000 }, /* CC_REG */ \
1079 { 0x200FFFF }, /* GENERAL_REGS */ \
1080 { 0x2FFFFFF } /* ALL_REGS */ \
1081 }
1082
1083 /* The same information, inverted:
1084 Return the class number of the smallest class containing
1085 reg number REGNO. This could be a conditional expression
1086 or could index an array. */
1087 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1088
1089 /* The class value for index registers, and the one for base regs. */
1090 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1091 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1092
1093 /* For the Thumb the high registers cannot be used as base
1094 registers when addressing quanitities in QI or HI mode. */
1095 #define MODE_BASE_REG_CLASS(MODE) \
1096 (TARGET_ARM ? BASE_REGS : \
1097 (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \
1098 ? LO_REGS : BASE_REGS))
1099
1100 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1101 registers explicitly used in the rtl to be used as spill registers
1102 but prevents the compiler from extending the lifetime of these
1103 registers. */
1104 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1105
1106 /* Get reg_class from a letter such as appears in the machine description.
1107 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1108 ARM, but several more letters for the Thumb. */
1109 #define REG_CLASS_FROM_LETTER(C) \
1110 ( (C) == 'f' ? FPU_REGS \
1111 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1112 : TARGET_ARM ? NO_REGS \
1113 : (C) == 'h' ? HI_REGS \
1114 : (C) == 'b' ? BASE_REGS \
1115 : (C) == 'k' ? STACK_REG \
1116 : (C) == 'c' ? CC_REG \
1117 : NO_REGS)
1118
1119 /* The letters I, J, K, L and M in a register constraint string
1120 can be used to stand for particular ranges of immediate operands.
1121 This macro defines what the ranges are.
1122 C is the letter, and VALUE is a constant value.
1123 Return 1 if VALUE is in the range specified by C.
1124 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1125 J: valid indexing constants.
1126 K: ~value ok in rhs argument of data operand.
1127 L: -value ok in rhs argument of data operand.
1128 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1129 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1130 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1131 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1132 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1133 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1134 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1135 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1136 : 0)
1137
1138 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1139 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1140 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1141 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1142 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1143 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1144 && ((VAL) & 3) == 0) : \
1145 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1146 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1147 : 0)
1148
1149 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1150 (TARGET_ARM ? \
1151 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1152
1153 /* Constant letter 'G' for the FPU immediate constants.
1154 'H' means the same constant negated. */
1155 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1156 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1157 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1158
1159 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1160 (TARGET_ARM ? \
1161 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1162
1163 /* For the ARM, `Q' means that this is a memory operand that is just
1164 an offset from a register.
1165 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1166 address. This means that the symbol is in the text segment and can be
1167 accessed without using a load. */
1168
1169 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1170 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1171 (C) == 'R' ? (GET_CODE (OP) == MEM \
1172 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1173 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1174 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1175 : 0)
1176
1177 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1178 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1179 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1180
1181 #define EXTRA_CONSTRAINT(X, C) \
1182 (TARGET_ARM ? \
1183 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1184
1185 /* Given an rtx X being reloaded into a reg required to be
1186 in class CLASS, return the class of reg to actually use.
1187 In general this is just CLASS, but for the Thumb we prefer
1188 a LO_REGS class or a subset. */
1189 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1190 (TARGET_ARM ? (CLASS) : \
1191 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1192
1193 /* Must leave BASE_REGS reloads alone */
1194 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1195 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1196 ? ((true_regnum (X) == -1 ? LO_REGS \
1197 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1198 : NO_REGS)) \
1199 : NO_REGS)
1200
1201 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1202 ((CLASS) != LO_REGS \
1203 ? ((true_regnum (X) == -1 ? LO_REGS \
1204 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1205 : NO_REGS)) \
1206 : NO_REGS)
1207
1208 /* Return the register class of a scratch register needed to copy IN into
1209 or out of a register in CLASS in MODE. If it can be done directly,
1210 NO_REGS is returned. */
1211 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1212 (TARGET_ARM ? \
1213 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1214 ? GENERAL_REGS : NO_REGS) \
1215 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1216
1217 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1218 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1219 (TARGET_ARM ? \
1220 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1221 && (GET_CODE (X) == MEM \
1222 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1223 && true_regnum (X) == -1))) \
1224 ? GENERAL_REGS : NO_REGS) \
1225 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1226
1227 /* Try a machine-dependent way of reloading an illegitimate address
1228 operand. If we find one, push the reload and jump to WIN. This
1229 macro is used in only one place: `find_reloads_address' in reload.c.
1230
1231 For the ARM, we wish to handle large displacements off a base
1232 register by splitting the addend across a MOV and the mem insn.
1233 This can cut the number of reloads needed. */
1234 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1235 do \
1236 { \
1237 if (GET_CODE (X) == PLUS \
1238 && GET_CODE (XEXP (X, 0)) == REG \
1239 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1240 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1241 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1242 { \
1243 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1244 HOST_WIDE_INT low, high; \
1245 \
1246 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1247 low = ((val & 0xf) ^ 0x8) - 0x8; \
1248 else if (MODE == SImode \
1249 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1250 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1251 /* Need to be careful, -4096 is not a valid offset. */ \
1252 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1253 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1254 /* Need to be careful, -256 is not a valid offset. */ \
1255 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1256 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1257 && TARGET_HARD_FLOAT) \
1258 /* Need to be careful, -1024 is not a valid offset. */ \
1259 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1260 else \
1261 break; \
1262 \
1263 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1264 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1265 - (unsigned HOST_WIDE_INT) 0x80000000); \
1266 /* Check for overflow or zero */ \
1267 if (low == 0 || high == 0 || (high + low != val)) \
1268 break; \
1269 \
1270 /* Reload the high part into a base reg; leave the low part \
1271 in the mem. */ \
1272 X = gen_rtx_PLUS (GET_MODE (X), \
1273 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1274 GEN_INT (high)), \
1275 GEN_INT (low)); \
1276 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1277 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1278 VOIDmode, 0, 0, OPNUM, TYPE); \
1279 goto WIN; \
1280 } \
1281 } \
1282 while (0)
1283
1284 /* ??? If an HImode FP+large_offset address is converted to an HImode
1285 SP+large_offset address, then reload won't know how to fix it. It sees
1286 only that SP isn't valid for HImode, and so reloads the SP into an index
1287 register, but the resulting address is still invalid because the offset
1288 is too big. We fix it here instead by reloading the entire address. */
1289 /* We could probably achieve better results by defining PROMOTE_MODE to help
1290 cope with the variances between the Thumb's signed and unsigned byte and
1291 halfword load instructions. */
1292 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1293 { \
1294 if (GET_CODE (X) == PLUS \
1295 && GET_MODE_SIZE (MODE) < 4 \
1296 && GET_CODE (XEXP (X, 0)) == REG \
1297 && XEXP (X, 0) == stack_pointer_rtx \
1298 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1299 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1300 { \
1301 rtx orig_X = X; \
1302 X = copy_rtx (X); \
1303 push_reload (orig_X, NULL_RTX, &X, NULL, \
1304 MODE_BASE_REG_CLASS (MODE), \
1305 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1306 goto WIN; \
1307 } \
1308 }
1309
1310 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1311 if (TARGET_ARM) \
1312 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1313 else \
1314 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1315
1316 /* Return the maximum number of consecutive registers
1317 needed to represent mode MODE in a register of class CLASS.
1318 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1319 #define CLASS_MAX_NREGS(CLASS, MODE) \
1320 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1321
1322 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1323 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1324 (TARGET_ARM ? \
1325 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1326 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1327 : \
1328 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1329 \f
1330 /* Stack layout; function entry, exit and calling. */
1331
1332 /* Define this if pushing a word on the stack
1333 makes the stack pointer a smaller address. */
1334 #define STACK_GROWS_DOWNWARD 1
1335
1336 /* Define this if the nominal address of the stack frame
1337 is at the high-address end of the local variables;
1338 that is, each additional local variable allocated
1339 goes at a more negative offset in the frame. */
1340 #define FRAME_GROWS_DOWNWARD 1
1341
1342 /* Offset within stack frame to start allocating local variables at.
1343 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1344 first local allocated. Otherwise, it is the offset to the BEGINNING
1345 of the first local allocated. */
1346 #define STARTING_FRAME_OFFSET 0
1347
1348 /* If we generate an insn to push BYTES bytes,
1349 this says how many the stack pointer really advances by. */
1350 /* The push insns do not do this rounding implicitly.
1351 So don't define this. */
1352 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1353
1354 /* Define this if the maximum size of all the outgoing args is to be
1355 accumulated and pushed during the prologue. The amount can be
1356 found in the variable current_function_outgoing_args_size. */
1357 #define ACCUMULATE_OUTGOING_ARGS 1
1358
1359 /* Offset of first parameter from the argument pointer register value. */
1360 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1361
1362 /* Value is the number of byte of arguments automatically
1363 popped when returning from a subroutine call.
1364 FUNDECL is the declaration node of the function (as a tree),
1365 FUNTYPE is the data type of the function (as a tree),
1366 or for a library call it is an identifier node for the subroutine name.
1367 SIZE is the number of bytes of arguments passed on the stack.
1368
1369 On the ARM, the caller does not pop any of its arguments that were passed
1370 on the stack. */
1371 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1372
1373 /* Define how to find the value returned by a library function
1374 assuming the value has mode MODE. */
1375 #define LIBCALL_VALUE(MODE) \
1376 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1377 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1378 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1379
1380 /* Define how to find the value returned by a function.
1381 VALTYPE is the data type of the value (as a tree).
1382 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1383 otherwise, FUNC is 0. */
1384 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1385 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1386
1387 /* 1 if N is a possible register number for a function value.
1388 On the ARM, only r0 and f0 can return results. */
1389 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1390 ((REGNO) == ARG_REGISTER (1) \
1391 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1392
1393 /* How large values are returned */
1394 /* A C expression which can inhibit the returning of certain function values
1395 in registers, based on the type of value. */
1396 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1397
1398 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1399 values must be in memory. On the ARM, they need only do so if larger
1400 than a word, or if they contain elements offset from zero in the struct. */
1401 #define DEFAULT_PCC_STRUCT_RETURN 0
1402
1403 /* Flags for the call/call_value rtl operations set up by function_arg. */
1404 #define CALL_NORMAL 0x00000000 /* No special processing. */
1405 #define CALL_LONG 0x00000001 /* Always call indirect. */
1406 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1407
1408 /* These bits describe the different types of function supported
1409 by the ARM backend. They are exclusive. ie a function cannot be both a
1410 normal function and an interworked function, for example. Knowing the
1411 type of a function is important for determining its prologue and
1412 epilogue sequences.
1413 Note value 7 is currently unassigned. Also note that the interrupt
1414 function types all have bit 2 set, so that they can be tested for easily.
1415 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1416 machine_function structure is initialised (to zero) func_type will
1417 default to unknown. This will force the first use of arm_current_func_type
1418 to call arm_compute_func_type. */
1419 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1420 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1421 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1422 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1423 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1424 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1425 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1426
1427 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1428
1429 /* In addition functions can have several type modifiers,
1430 outlined by these bit masks: */
1431 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1432 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1433 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1434 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1435
1436 /* Some macros to test these flags. */
1437 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1438 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1439 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1440 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1441 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1442
1443 /* A C structure for machine-specific, per-function data.
1444 This is added to the cfun structure. */
1445 typedef struct machine_function
1446 {
1447 /* Additionsl stack adjustment in __builtin_eh_throw. */
1448 struct rtx_def *eh_epilogue_sp_ofs;
1449 /* Records if LR has to be saved for far jumps. */
1450 int far_jump_used;
1451 /* Records if ARG_POINTER was ever live. */
1452 int arg_pointer_live;
1453 /* Records if the save of LR has been eliminated. */
1454 int lr_save_eliminated;
1455 /* Records the type of the current function. */
1456 unsigned long func_type;
1457 }
1458 machine_function;
1459
1460 /* A C type for declaring a variable that is used as the first argument of
1461 `FUNCTION_ARG' and other related values. For some target machines, the
1462 type `int' suffices and can hold the number of bytes of argument so far. */
1463 typedef struct
1464 {
1465 /* This is the number of registers of arguments scanned so far. */
1466 int nregs;
1467 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1468 int call_cookie;
1469 } CUMULATIVE_ARGS;
1470
1471 /* Define where to put the arguments to a function.
1472 Value is zero to push the argument on the stack,
1473 or a hard register in which to store the argument.
1474
1475 MODE is the argument's machine mode.
1476 TYPE is the data type of the argument (as a tree).
1477 This is null for libcalls where that information may
1478 not be available.
1479 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1480 the preceding args and about the function being called.
1481 NAMED is nonzero if this argument is a named parameter
1482 (otherwise it is an extra parameter matching an ellipsis).
1483
1484 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1485 other arguments are passed on the stack. If (NAMED == 0) (which happens
1486 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1487 passed in the stack (function_prologue will indeed make it pass in the
1488 stack if necessary). */
1489 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1490 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1491
1492 /* For an arg passed partly in registers and partly in memory,
1493 this is the number of registers used.
1494 For args passed entirely in registers or entirely in memory, zero. */
1495 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1496 ( NUM_ARG_REGS > (CUM).nregs \
1497 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1498 ? NUM_ARG_REGS - (CUM).nregs : 0)
1499
1500 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1501 for a call to a function whose data type is FNTYPE.
1502 For a library call, FNTYPE is 0.
1503 On the ARM, the offset starts at 0. */
1504 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1505 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1506
1507 /* Update the data in CUM to advance over an argument
1508 of mode MODE and data type TYPE.
1509 (TYPE is null for libcalls where that information may not be available.) */
1510 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1511 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1512
1513 /* 1 if N is a possible register number for function argument passing.
1514 On the ARM, r0-r3 are used to pass args. */
1515 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1516
1517 \f
1518 /* Tail calling. */
1519
1520 /* A C expression that evaluates to true if it is ok to perform a sibling
1521 call to DECL. */
1522 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1523
1524 /* Perform any actions needed for a function that is receiving a variable
1525 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1526 of the current parameter. PRETEND_SIZE is a variable that should be set to
1527 the amount of stack that must be pushed by the prolog to pretend that our
1528 caller pushed it.
1529
1530 Normally, this macro will push all remaining incoming registers on the
1531 stack and set PRETEND_SIZE to the length of the registers pushed.
1532
1533 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1534 named arg and all anonymous args onto the stack.
1535 XXX I know the prologue shouldn't be pushing registers, but it is faster
1536 that way. */
1537 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1538 { \
1539 extern int current_function_anonymous_args; \
1540 current_function_anonymous_args = 1; \
1541 if ((CUM).nregs < NUM_ARG_REGS) \
1542 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1543 }
1544
1545 /* If your target environment doesn't prefix user functions with an
1546 underscore, you may wish to re-define this to prevent any conflicts.
1547 e.g. AOF may prefix mcount with an underscore. */
1548 #ifndef ARM_MCOUNT_NAME
1549 #define ARM_MCOUNT_NAME "*mcount"
1550 #endif
1551
1552 /* Call the function profiler with a given profile label. The Acorn
1553 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1554 On the ARM the full profile code will look like:
1555 .data
1556 LP1
1557 .word 0
1558 .text
1559 mov ip, lr
1560 bl mcount
1561 .word LP1
1562
1563 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1564 will output the .text section.
1565
1566 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1567 ``prof'' doesn't seem to mind about this! */
1568 #ifndef ARM_FUNCTION_PROFILER
1569 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1570 { \
1571 char temp[20]; \
1572 rtx sym; \
1573 \
1574 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1575 IP_REGNUM, LR_REGNUM); \
1576 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1577 fputc ('\n', STREAM); \
1578 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1579 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1580 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1581 }
1582 #endif
1583
1584 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1585 { \
1586 fprintf (STREAM, "\tmov\tip, lr\n"); \
1587 fprintf (STREAM, "\tbl\tmcount\n"); \
1588 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1589 }
1590
1591 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1592 if (TARGET_ARM) \
1593 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1594 else \
1595 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1596
1597 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1598 the stack pointer does not matter. The value is tested only in
1599 functions that have frame pointers.
1600 No definition is equivalent to always zero.
1601
1602 On the ARM, the function epilogue recovers the stack pointer from the
1603 frame. */
1604 #define EXIT_IGNORE_STACK 1
1605
1606 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1607
1608 /* Determine if the epilogue should be output as RTL.
1609 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1610 #define USE_RETURN_INSN(ISCOND) \
1611 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1612
1613 /* Definitions for register eliminations.
1614
1615 This is an array of structures. Each structure initializes one pair
1616 of eliminable registers. The "from" register number is given first,
1617 followed by "to". Eliminations of the same "from" register are listed
1618 in order of preference.
1619
1620 We have two registers that can be eliminated on the ARM. First, the
1621 arg pointer register can often be eliminated in favor of the stack
1622 pointer register. Secondly, the pseudo frame pointer register can always
1623 be eliminated; it is replaced with either the stack or the real frame
1624 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1625 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1626
1627 #define ELIMINABLE_REGS \
1628 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1629 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1630 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1631 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1632 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1633 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1634 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1635
1636 /* Given FROM and TO register numbers, say whether this elimination is
1637 allowed. Frame pointer elimination is automatically handled.
1638
1639 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1640 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1641 pointer, we must eliminate FRAME_POINTER_REGNUM into
1642 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1643 ARG_POINTER_REGNUM. */
1644 #define CAN_ELIMINATE(FROM, TO) \
1645 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1646 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1647 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1648 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1649 1)
1650
1651 /* Define the offset between two registers, one to be eliminated, and the
1652 other its replacement, at the start of a routine. */
1653 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1654 do \
1655 { \
1656 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1657 } \
1658 while (0)
1659
1660 /* Note: This macro must match the code in thumb_function_prologue(). */
1661 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1662 { \
1663 (OFFSET) = 0; \
1664 if ((FROM) == ARG_POINTER_REGNUM) \
1665 { \
1666 int count_regs = 0; \
1667 int regno; \
1668 for (regno = 8; regno < 13; regno ++) \
1669 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1670 count_regs ++; \
1671 if (count_regs) \
1672 (OFFSET) += 4 * count_regs; \
1673 count_regs = 0; \
1674 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1675 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1676 count_regs ++; \
1677 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1678 (OFFSET) += 4 * (count_regs + 1); \
1679 if (TARGET_BACKTRACE) \
1680 { \
1681 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1682 (OFFSET) += 20; \
1683 else \
1684 (OFFSET) += 16; \
1685 } \
1686 } \
1687 if ((TO) == STACK_POINTER_REGNUM) \
1688 { \
1689 (OFFSET) += current_function_outgoing_args_size; \
1690 (OFFSET) += ROUND_UP (get_frame_size ()); \
1691 } \
1692 }
1693
1694 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1695 if (TARGET_ARM) \
1696 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1697 else \
1698 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1699
1700 /* Special case handling of the location of arguments passed on the stack. */
1701 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1702
1703 /* Initialize data used by insn expanders. This is called from insn_emit,
1704 once for every function before code is generated. */
1705 #define INIT_EXPANDERS arm_init_expanders ()
1706
1707 /* Output assembler code for a block containing the constant parts
1708 of a trampoline, leaving space for the variable parts.
1709
1710 On the ARM, (if r8 is the static chain regnum, and remembering that
1711 referencing pc adds an offset of 8) the trampoline looks like:
1712 ldr r8, [pc, #0]
1713 ldr pc, [pc]
1714 .word static chain value
1715 .word function's address
1716 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1717 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1718 { \
1719 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1720 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1721 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1722 PC_REGNUM, PC_REGNUM); \
1723 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1724 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1725 }
1726
1727 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1728 Why - because it is easier. This code will always be branched to via
1729 a BX instruction and since the compiler magically generates the address
1730 of the function the linker has no opportunity to ensure that the
1731 bottom bit is set. Thus the processor will be in ARM mode when it
1732 reaches this code. So we duplicate the ARM trampoline code and add
1733 a switch into Thumb mode as well. */
1734 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1735 { \
1736 fprintf (FILE, "\t.code 32\n"); \
1737 fprintf (FILE, ".Ltrampoline_start:\n"); \
1738 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1739 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1740 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1741 IP_REGNUM, PC_REGNUM); \
1742 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1743 IP_REGNUM, IP_REGNUM); \
1744 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1745 fprintf (FILE, "\t.word\t0\n"); \
1746 fprintf (FILE, "\t.word\t0\n"); \
1747 fprintf (FILE, "\t.code 16\n"); \
1748 }
1749
1750 #define TRAMPOLINE_TEMPLATE(FILE) \
1751 if (TARGET_ARM) \
1752 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1753 else \
1754 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1755
1756 /* Length in units of the trampoline for entering a nested function. */
1757 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1758
1759 /* Alignment required for a trampoline in bits. */
1760 #define TRAMPOLINE_ALIGNMENT 32
1761
1762 /* Emit RTL insns to initialize the variable parts of a trampoline.
1763 FNADDR is an RTX for the address of the function's pure code.
1764 CXT is an RTX for the static chain value for the function. */
1765 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1766 { \
1767 emit_move_insn \
1768 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1769 emit_move_insn \
1770 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1771 }
1772
1773 \f
1774 /* Addressing modes, and classification of registers for them. */
1775 #define HAVE_POST_INCREMENT 1
1776 #define HAVE_PRE_INCREMENT TARGET_ARM
1777 #define HAVE_POST_DECREMENT TARGET_ARM
1778 #define HAVE_PRE_DECREMENT TARGET_ARM
1779
1780 /* Macros to check register numbers against specific register classes. */
1781
1782 /* These assume that REGNO is a hard or pseudo reg number.
1783 They give nonzero only if REGNO is a hard reg of the suitable class
1784 or a pseudo reg currently allocated to a suitable hard reg.
1785 Since they use reg_renumber, they are safe only once reg_renumber
1786 has been allocated, which happens in local-alloc.c. */
1787 #define TEST_REGNO(R, TEST, VALUE) \
1788 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1789
1790 /* On the ARM, don't allow the pc to be used. */
1791 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1792 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1793 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1794 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1795
1796 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1797 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1798 || (GET_MODE_SIZE (MODE) >= 4 \
1799 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1800
1801 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1802 (TARGET_THUMB \
1803 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1804 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1805
1806 /* For ARM code, we don't care about the mode, but for Thumb, the index
1807 must be suitable for use in a QImode load. */
1808 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1809 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1810
1811 /* Maximum number of registers that can appear in a valid memory address.
1812 Shifts in addresses can't be by a register. */
1813 #define MAX_REGS_PER_ADDRESS 2
1814
1815 /* Recognize any constant value that is a valid address. */
1816 /* XXX We can address any constant, eventually... */
1817
1818 #ifdef AOF_ASSEMBLER
1819
1820 #define CONSTANT_ADDRESS_P(X) \
1821 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1822
1823 #else
1824
1825 #define CONSTANT_ADDRESS_P(X) \
1826 (GET_CODE (X) == SYMBOL_REF \
1827 && (CONSTANT_POOL_ADDRESS_P (X) \
1828 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1829
1830 #endif /* AOF_ASSEMBLER */
1831
1832 /* Nonzero if the constant value X is a legitimate general operand.
1833 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1834
1835 On the ARM, allow any integer (invalid ones are removed later by insn
1836 patterns), nice doubles and symbol_refs which refer to the function's
1837 constant pool XXX.
1838
1839 When generating pic allow anything. */
1840 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1841
1842 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1843 ( GET_CODE (X) == CONST_INT \
1844 || GET_CODE (X) == CONST_DOUBLE \
1845 || CONSTANT_ADDRESS_P (X))
1846
1847 #define LEGITIMATE_CONSTANT_P(X) \
1848 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1849
1850 /* Special characters prefixed to function names
1851 in order to encode attribute like information.
1852 Note, '@' and '*' have already been taken. */
1853 #define SHORT_CALL_FLAG_CHAR '^'
1854 #define LONG_CALL_FLAG_CHAR '#'
1855
1856 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1857 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1858
1859 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1860 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1861
1862 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1863 #define SUBTARGET_NAME_ENCODING_LENGTHS
1864 #endif
1865
1866 /* This is a C fragement for the inside of a switch statement.
1867 Each case label should return the number of characters to
1868 be stripped from the start of a function's name, if that
1869 name starts with the indicated character. */
1870 #define ARM_NAME_ENCODING_LENGTHS \
1871 case SHORT_CALL_FLAG_CHAR: return 1; \
1872 case LONG_CALL_FLAG_CHAR: return 1; \
1873 case '*': return 1; \
1874 SUBTARGET_NAME_ENCODING_LENGTHS
1875
1876 /* This has to be handled by a function because more than part of the
1877 ARM backend uses function name prefixes to encode attributes. */
1878 #undef STRIP_NAME_ENCODING
1879 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1880 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1881
1882 /* This is how to output a reference to a user-level label named NAME.
1883 `assemble_name' uses this. */
1884 #undef ASM_OUTPUT_LABELREF
1885 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1886 asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME))
1887
1888 /* If we are referencing a function that is weak then encode a long call
1889 flag in the function name, otherwise if the function is static or
1890 or known to be defined in this file then encode a short call flag.
1891 This macro is used inside the ENCODE_SECTION macro. */
1892 #define ARM_ENCODE_CALL_TYPE(decl) \
1893 if (TREE_CODE (decl) == FUNCTION_DECL) \
1894 { \
1895 if (DECL_WEAK (decl)) \
1896 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1897 else if (! TREE_PUBLIC (decl)) \
1898 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1899 }
1900
1901 /* Symbols in the text segment can be accessed without indirecting via the
1902 constant pool; it may take an extra binary operation, but this is still
1903 faster than indirecting via memory. Don't do this when not optimizing,
1904 since we won't be calculating al of the offsets necessary to do this
1905 simplification. */
1906 /* This doesn't work with AOF syntax, since the string table may be in
1907 a different AREA. */
1908 #ifndef AOF_ASSEMBLER
1909 #define ENCODE_SECTION_INFO(decl) \
1910 { \
1911 if (optimize > 0 && TREE_CONSTANT (decl) \
1912 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1913 { \
1914 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1915 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1916 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1917 } \
1918 ARM_ENCODE_CALL_TYPE (decl) \
1919 }
1920 #else
1921 #define ENCODE_SECTION_INFO(decl) \
1922 { \
1923 ARM_ENCODE_CALL_TYPE (decl) \
1924 }
1925 #endif
1926
1927 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1928 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1929
1930 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1931 and check its validity for a certain class.
1932 We have two alternate definitions for each of them.
1933 The usual definition accepts all pseudo regs; the other rejects
1934 them unless they have been allocated suitable hard regs.
1935 The symbol REG_OK_STRICT causes the latter definition to be used. */
1936 #ifndef REG_OK_STRICT
1937
1938 #define ARM_REG_OK_FOR_BASE_P(X) \
1939 (REGNO (X) <= LAST_ARM_REGNUM \
1940 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1941 || REGNO (X) == FRAME_POINTER_REGNUM \
1942 || REGNO (X) == ARG_POINTER_REGNUM)
1943
1944 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1945 (REGNO (X) <= LAST_LO_REGNUM \
1946 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1947 || (GET_MODE_SIZE (MODE) >= 4 \
1948 && (REGNO (X) == STACK_POINTER_REGNUM \
1949 || (X) == hard_frame_pointer_rtx \
1950 || (X) == arg_pointer_rtx)))
1951
1952 #else /* REG_OK_STRICT */
1953
1954 #define ARM_REG_OK_FOR_BASE_P(X) \
1955 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1956
1957 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1958 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1959
1960 #endif /* REG_OK_STRICT */
1961
1962 /* Now define some helpers in terms of the above. */
1963
1964 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1965 (TARGET_THUMB \
1966 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1967 : ARM_REG_OK_FOR_BASE_P (X))
1968
1969 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1970
1971 /* For Thumb, a valid index register is anything that can be used in
1972 a byte load instruction. */
1973 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1974
1975 /* Nonzero if X is a hard reg that can be used as an index
1976 or if it is a pseudo reg. On the Thumb, the stack pointer
1977 is not suitable. */
1978 #define REG_OK_FOR_INDEX_P(X) \
1979 (TARGET_THUMB \
1980 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1981 : ARM_REG_OK_FOR_INDEX_P (X))
1982
1983 \f
1984 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1985 that is a valid memory address for an instruction.
1986 The MODE argument is the machine mode for the MEM expression
1987 that wants to use this address.
1988
1989 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1990
1991 /* --------------------------------arm version----------------------------- */
1992 #define ARM_BASE_REGISTER_RTX_P(X) \
1993 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1994
1995 #define ARM_INDEX_REGISTER_RTX_P(X) \
1996 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1997
1998 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1999 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2000 only be small constants. */
2001 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2002 do \
2003 { \
2004 HOST_WIDE_INT range; \
2005 enum rtx_code code = GET_CODE (INDEX); \
2006 \
2007 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2008 { \
2009 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2010 && INTVAL (INDEX) > -1024 \
2011 && (INTVAL (INDEX) & 3) == 0) \
2012 goto LABEL; \
2013 } \
2014 else \
2015 { \
2016 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2017 && GET_MODE_SIZE (MODE) <= 4) \
2018 goto LABEL; \
2019 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2020 && (! arm_arch4 || (MODE) != HImode)) \
2021 { \
2022 rtx xiop0 = XEXP (INDEX, 0); \
2023 rtx xiop1 = XEXP (INDEX, 1); \
2024 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2025 && power_of_two_operand (xiop1, SImode)) \
2026 goto LABEL; \
2027 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2028 && power_of_two_operand (xiop0, SImode)) \
2029 goto LABEL; \
2030 } \
2031 if (GET_MODE_SIZE (MODE) <= 4 \
2032 && (code == LSHIFTRT || code == ASHIFTRT \
2033 || code == ASHIFT || code == ROTATERT) \
2034 && (! arm_arch4 || (MODE) != HImode)) \
2035 { \
2036 rtx op = XEXP (INDEX, 1); \
2037 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2038 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2039 && INTVAL (op) <= 31) \
2040 goto LABEL; \
2041 } \
2042 /* NASTY: Since this limits the addressing of unsigned \
2043 byte loads. */ \
2044 range = ((MODE) == HImode || (MODE) == QImode) \
2045 ? (arm_arch4 ? 256 : 4095) : 4096; \
2046 if (code == CONST_INT && INTVAL (INDEX) < range \
2047 && INTVAL (INDEX) > -range) \
2048 goto LABEL; \
2049 } \
2050 } \
2051 while (0)
2052
2053 /* Jump to LABEL if X is a valid address RTX. This must take
2054 REG_OK_STRICT into account when deciding about valid registers.
2055
2056 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2057 floating SYMBOL_REF to the constant pool. Allow REG-only and
2058 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2059 forced though a static cell to ensure addressability. */
2060 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2061 { \
2062 if (ARM_BASE_REGISTER_RTX_P (X)) \
2063 goto LABEL; \
2064 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2065 && GET_CODE (XEXP (X, 0)) == REG \
2066 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2067 goto LABEL; \
2068 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2069 && (GET_CODE (X) == LABEL_REF \
2070 || (GET_CODE (X) == CONST \
2071 && GET_CODE (XEXP ((X), 0)) == PLUS \
2072 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2073 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2074 goto LABEL; \
2075 else if ((MODE) == TImode) \
2076 ; \
2077 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2078 { \
2079 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2080 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2081 { \
2082 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2083 if (val == 4 || val == -4 || val == -8) \
2084 goto LABEL; \
2085 } \
2086 } \
2087 else if (GET_CODE (X) == PLUS) \
2088 { \
2089 rtx xop0 = XEXP (X, 0); \
2090 rtx xop1 = XEXP (X, 1); \
2091 \
2092 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2093 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2094 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2095 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2096 } \
2097 /* Reload currently can't handle MINUS, so disable this for now */ \
2098 /* else if (GET_CODE (X) == MINUS) \
2099 { \
2100 rtx xop0 = XEXP (X,0); \
2101 rtx xop1 = XEXP (X,1); \
2102 \
2103 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2104 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2105 } */ \
2106 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2107 && GET_CODE (X) == SYMBOL_REF \
2108 && CONSTANT_POOL_ADDRESS_P (X) \
2109 && ! (flag_pic \
2110 && symbol_mentioned_p (get_pool_constant (X)))) \
2111 goto LABEL; \
2112 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2113 && (GET_MODE_SIZE (MODE) <= 4) \
2114 && GET_CODE (XEXP (X, 0)) == REG \
2115 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2116 goto LABEL; \
2117 }
2118
2119 /* ---------------------thumb version----------------------------------*/
2120 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2121 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2122 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2123 && ((VAL) & 1) == 0) \
2124 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2125 && ((VAL) & 3) == 0))
2126
2127 /* The AP may be eliminated to either the SP or the FP, so we use the
2128 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2129
2130 /* ??? Verify whether the above is the right approach. */
2131
2132 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2133 needs special handling also. */
2134
2135 /* ??? Look at how the mips16 port solves this problem. It probably uses
2136 better ways to solve some of these problems. */
2137
2138 /* Although it is not incorrect, we don't accept QImode and HImode
2139 addresses based on the frame pointer or arg pointer until the
2140 reload pass starts. This is so that eliminating such addresses
2141 into stack based ones won't produce impossible code. */
2142 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2143 { \
2144 /* ??? Not clear if this is right. Experiment. */ \
2145 if (GET_MODE_SIZE (MODE) < 4 \
2146 && ! (reload_in_progress || reload_completed) \
2147 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2148 || reg_mentioned_p (arg_pointer_rtx, X) \
2149 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2150 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2151 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2152 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2153 ; \
2154 /* Accept any base register. SP only in SImode or larger. */ \
2155 else if (GET_CODE (X) == REG \
2156 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2157 goto WIN; \
2158 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2159 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2160 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2161 goto WIN; \
2162 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2163 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2164 && (GET_CODE (X) == LABEL_REF \
2165 || (GET_CODE (X) == CONST \
2166 && GET_CODE (XEXP (X, 0)) == PLUS \
2167 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2168 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2169 goto WIN; \
2170 /* Post-inc indexing only supported for SImode and larger. */ \
2171 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2172 && GET_CODE (XEXP (X, 0)) == REG \
2173 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2174 goto WIN; \
2175 else if (GET_CODE (X) == PLUS) \
2176 { \
2177 /* REG+REG address can be any two index registers. */ \
2178 /* We disallow FRAME+REG addressing since we know that FRAME \
2179 will be replaced with STACK, and SP relative addressing only \
2180 permits SP+OFFSET. */ \
2181 if (GET_MODE_SIZE (MODE) <= 4 \
2182 && GET_CODE (XEXP (X, 0)) == REG \
2183 && GET_CODE (XEXP (X, 1)) == REG \
2184 && XEXP (X, 0) != frame_pointer_rtx \
2185 && XEXP (X, 1) != frame_pointer_rtx \
2186 && XEXP (X, 0) != virtual_stack_vars_rtx \
2187 && XEXP (X, 1) != virtual_stack_vars_rtx \
2188 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2189 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2190 goto WIN; \
2191 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2192 else if (GET_CODE (XEXP (X, 0)) == REG \
2193 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2194 || XEXP (X, 0) == arg_pointer_rtx) \
2195 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2196 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2197 goto WIN; \
2198 /* REG+const has 10 bit offset for SP, but only SImode and \
2199 larger is supported. */ \
2200 /* ??? Should probably check for DI/DFmode overflow here \
2201 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2202 else if (GET_CODE (XEXP (X, 0)) == REG \
2203 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2204 && GET_MODE_SIZE (MODE) >= 4 \
2205 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2206 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2207 + GET_MODE_SIZE (MODE)) <= 1024 \
2208 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2209 goto WIN; \
2210 else if (GET_CODE (XEXP (X, 0)) == REG \
2211 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2212 && GET_MODE_SIZE (MODE) >= 4 \
2213 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2214 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2215 goto WIN; \
2216 } \
2217 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2218 && GET_CODE (X) == SYMBOL_REF \
2219 && CONSTANT_POOL_ADDRESS_P (X) \
2220 && ! (flag_pic \
2221 && symbol_mentioned_p (get_pool_constant (X)))) \
2222 goto WIN; \
2223 }
2224
2225 /* ------------------------------------------------------------------- */
2226 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2227 if (TARGET_ARM) \
2228 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2229 else /* if (TARGET_THUMB) */ \
2230 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2231 /* ------------------------------------------------------------------- */
2232 \f
2233 /* Try machine-dependent ways of modifying an illegitimate address
2234 to be legitimate. If we find one, return the new, valid address.
2235 This macro is used in only one place: `memory_address' in explow.c.
2236
2237 OLDX is the address as it was before break_out_memory_refs was called.
2238 In some cases it is useful to look at this to decide what needs to be done.
2239
2240 MODE and WIN are passed so that this macro can use
2241 GO_IF_LEGITIMATE_ADDRESS.
2242
2243 It is always safe for this macro to do nothing. It exists to recognize
2244 opportunities to optimize the output.
2245
2246 On the ARM, try to convert [REG, #BIGCONST]
2247 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2248 where VALIDCONST == 0 in case of TImode. */
2249 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2250 { \
2251 if (GET_CODE (X) == PLUS) \
2252 { \
2253 rtx xop0 = XEXP (X, 0); \
2254 rtx xop1 = XEXP (X, 1); \
2255 \
2256 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2257 xop0 = force_reg (SImode, xop0); \
2258 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2259 xop1 = force_reg (SImode, xop1); \
2260 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2261 && GET_CODE (xop1) == CONST_INT) \
2262 { \
2263 HOST_WIDE_INT n, low_n; \
2264 rtx base_reg, val; \
2265 n = INTVAL (xop1); \
2266 \
2267 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2268 { \
2269 low_n = n & 0x0f; \
2270 n &= ~0x0f; \
2271 if (low_n > 4) \
2272 { \
2273 n += 16; \
2274 low_n -= 16; \
2275 } \
2276 } \
2277 else \
2278 { \
2279 low_n = ((MODE) == TImode ? 0 \
2280 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2281 n -= low_n; \
2282 } \
2283 base_reg = gen_reg_rtx (SImode); \
2284 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2285 GEN_INT (n)), NULL_RTX); \
2286 emit_move_insn (base_reg, val); \
2287 (X) = (low_n == 0 ? base_reg \
2288 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2289 } \
2290 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2291 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2292 } \
2293 else if (GET_CODE (X) == MINUS) \
2294 { \
2295 rtx xop0 = XEXP (X, 0); \
2296 rtx xop1 = XEXP (X, 1); \
2297 \
2298 if (CONSTANT_P (xop0)) \
2299 xop0 = force_reg (SImode, xop0); \
2300 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2301 xop1 = force_reg (SImode, xop1); \
2302 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2303 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2304 } \
2305 if (flag_pic) \
2306 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2307 if (memory_address_p (MODE, X)) \
2308 goto WIN; \
2309 }
2310
2311 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2312 if (flag_pic) \
2313 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2314
2315 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2316 if (TARGET_ARM) \
2317 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2318 else \
2319 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2320
2321 /* Go to LABEL if ADDR (a legitimate address expression)
2322 has an effect that depends on the machine mode it is used for. */
2323 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2324 { \
2325 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2326 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2327 goto LABEL; \
2328 }
2329
2330 /* Nothing helpful to do for the Thumb */
2331 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2332 if (TARGET_ARM) \
2333 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2334 \f
2335
2336 /* Specify the machine mode that this machine uses
2337 for the index in the tablejump instruction. */
2338 #define CASE_VECTOR_MODE Pmode
2339
2340 /* Define as C expression which evaluates to nonzero if the tablejump
2341 instruction expects the table to contain offsets from the address of the
2342 table.
2343 Do not define this if the table should contain absolute addresses. */
2344 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2345
2346 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2347 unsigned is probably best, but may break some code. */
2348 #ifndef DEFAULT_SIGNED_CHAR
2349 #define DEFAULT_SIGNED_CHAR 0
2350 #endif
2351
2352 /* Don't cse the address of the function being compiled. */
2353 #define NO_RECURSIVE_FUNCTION_CSE 1
2354
2355 /* Max number of bytes we can move from memory to memory
2356 in one reasonably fast instruction. */
2357 #define MOVE_MAX 4
2358
2359 #undef MOVE_RATIO
2360 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2361
2362 /* Define if operations between registers always perform the operation
2363 on the full register even if a narrower mode is specified. */
2364 #define WORD_REGISTER_OPERATIONS
2365
2366 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2367 will either zero-extend or sign-extend. The value of this macro should
2368 be the code that says which one of the two operations is implicitly
2369 done, NIL if none. */
2370 #define LOAD_EXTEND_OP(MODE) \
2371 (TARGET_THUMB ? ZERO_EXTEND : \
2372 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2373 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2374
2375 /* Nonzero if access to memory by bytes is slow and undesirable. */
2376 #define SLOW_BYTE_ACCESS 0
2377
2378 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2379
2380 /* Immediate shift counts are truncated by the output routines (or was it
2381 the assembler?). Shift counts in a register are truncated by ARM. Note
2382 that the native compiler puts too large (> 32) immediate shift counts
2383 into a register and shifts by the register, letting the ARM decide what
2384 to do instead of doing that itself. */
2385 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2386 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2387 On the arm, Y in a register is used modulo 256 for the shift. Only for
2388 rotates is modulo 32 used. */
2389 /* #define SHIFT_COUNT_TRUNCATED 1 */
2390
2391 /* All integers have the same format so truncation is easy. */
2392 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2393
2394 /* Calling from registers is a massive pain. */
2395 #define NO_FUNCTION_CSE 1
2396
2397 /* Chars and shorts should be passed as ints. */
2398 #define PROMOTE_PROTOTYPES 1
2399
2400 /* The machine modes of pointers and functions */
2401 #define Pmode SImode
2402 #define FUNCTION_MODE Pmode
2403
2404 #define ARM_FRAME_RTX(X) \
2405 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2406 || (X) == arg_pointer_rtx)
2407
2408 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2409 return arm_rtx_costs (X, CODE, OUTER_CODE);
2410
2411 /* Moves to and from memory are quite expensive */
2412 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2413 (TARGET_ARM ? 10 : \
2414 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2415 * (CLASS == LO_REGS ? 1 : 2)))
2416
2417 /* All address computations that can be done are free, but rtx cost returns
2418 the same for practically all of them. So we weight the different types
2419 of address here in the order (most pref first):
2420 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2421 #define ARM_ADDRESS_COST(X) \
2422 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2423 || GET_CODE (X) == SYMBOL_REF) \
2424 ? 0 \
2425 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2426 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2427 ? 10 \
2428 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2429 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2430 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2431 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2432 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2433 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2434 ? 1 : 0)) \
2435 : 4)))))
2436
2437 #define THUMB_ADDRESS_COST(X) \
2438 ((GET_CODE (X) == REG \
2439 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2440 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2441 ? 1 : 2)
2442
2443 #define ADDRESS_COST(X) \
2444 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2445
2446 /* Try to generate sequences that don't involve branches, we can then use
2447 conditional instructions */
2448 #define BRANCH_COST \
2449 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2450 \f
2451 /* Position Independent Code. */
2452 /* We decide which register to use based on the compilation options and
2453 the assembler in use; this is more general than the APCS restriction of
2454 using sb (r9) all the time. */
2455 extern int arm_pic_register;
2456
2457 /* Used when parsing command line option -mpic-register=. */
2458 extern const char * arm_pic_register_string;
2459
2460 /* The register number of the register used to address a table of static
2461 data addresses in memory. */
2462 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2463
2464 #define FINALIZE_PIC arm_finalize_pic (1)
2465
2466 /* We can't directly access anything that contains a symbol,
2467 nor can we indirect via the constant pool. */
2468 #define LEGITIMATE_PIC_OPERAND_P(X) \
2469 ( ! symbol_mentioned_p (X) \
2470 && ! label_mentioned_p (X) \
2471 && (! CONSTANT_POOL_ADDRESS_P (X) \
2472 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2473 && ! label_mentioned_p (get_pool_constant (X)))))
2474
2475 /* We need to know when we are making a constant pool; this determines
2476 whether data needs to be in the GOT or can be referenced via a GOT
2477 offset. */
2478 extern int making_const_table;
2479 \f
2480 /* Handle pragmas for compatibility with Intel's compilers. */
2481 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2482 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2483 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2484 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2485 } while (0)
2486
2487 /* Condition code information. */
2488 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2489 return the mode to be used for the comparison.
2490 CCFPEmode should be used with floating inequalities,
2491 CCFPmode should be used with floating equalities.
2492 CC_NOOVmode should be used with SImode integer equalities.
2493 CC_Zmode should be used if only the Z flag is set correctly
2494 CCmode should be used otherwise. */
2495
2496 #define EXTRA_CC_MODES \
2497 CC(CC_NOOVmode, "CC_NOOV") \
2498 CC(CC_Zmode, "CC_Z") \
2499 CC(CC_SWPmode, "CC_SWP") \
2500 CC(CCFPmode, "CCFP") \
2501 CC(CCFPEmode, "CCFPE") \
2502 CC(CC_DNEmode, "CC_DNE") \
2503 CC(CC_DEQmode, "CC_DEQ") \
2504 CC(CC_DLEmode, "CC_DLE") \
2505 CC(CC_DLTmode, "CC_DLT") \
2506 CC(CC_DGEmode, "CC_DGE") \
2507 CC(CC_DGTmode, "CC_DGT") \
2508 CC(CC_DLEUmode, "CC_DLEU") \
2509 CC(CC_DLTUmode, "CC_DLTU") \
2510 CC(CC_DGEUmode, "CC_DGEU") \
2511 CC(CC_DGTUmode, "CC_DGTU") \
2512 CC(CC_Cmode, "CC_C")
2513
2514 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2515
2516 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2517
2518 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2519 do \
2520 { \
2521 if (GET_CODE (OP1) == CONST_INT \
2522 && ! (const_ok_for_arm (INTVAL (OP1)) \
2523 || (const_ok_for_arm (- INTVAL (OP1))))) \
2524 { \
2525 rtx const_op = OP1; \
2526 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2527 OP1 = const_op; \
2528 } \
2529 } \
2530 while (0)
2531
2532 #define STORE_FLAG_VALUE 1
2533
2534 \f
2535
2536 /* Gcc puts the pool in the wrong place for ARM, since we can only
2537 load addresses a limited distance around the pc. We do some
2538 special munging to move the constant pool values to the correct
2539 point in the code. */
2540 #define MACHINE_DEPENDENT_REORG(INSN) \
2541 arm_reorg (INSN); \
2542
2543 #undef ASM_APP_OFF
2544 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2545
2546 /* Output an internal label definition. */
2547 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2548 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2549 do \
2550 { \
2551 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2552 \
2553 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2554 && !strcmp (PREFIX, "L")) \
2555 { \
2556 arm_ccfsm_state = 0; \
2557 arm_target_insn = NULL; \
2558 } \
2559 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2560 ASM_OUTPUT_LABEL (STREAM, s); \
2561 } \
2562 while (0)
2563 #endif
2564
2565 /* Output a push or a pop instruction (only used when profiling). */
2566 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2567 if (TARGET_ARM) \
2568 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2569 STACK_POINTER_REGNUM, REGNO); \
2570 else \
2571 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2572
2573
2574 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2575 if (TARGET_ARM) \
2576 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2577 STACK_POINTER_REGNUM, REGNO); \
2578 else \
2579 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2580
2581 /* This is how to output a label which precedes a jumptable. Since
2582 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2583 #undef ASM_OUTPUT_CASE_LABEL
2584 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2585 do \
2586 { \
2587 if (TARGET_THUMB) \
2588 ASM_OUTPUT_ALIGN (FILE, 2); \
2589 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2590 } \
2591 while (0)
2592
2593 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2594 do \
2595 { \
2596 if (TARGET_THUMB) \
2597 { \
2598 if (is_called_in_ARM_mode (DECL)) \
2599 fprintf (STREAM, "\t.code 32\n") ; \
2600 else \
2601 fprintf (STREAM, "\t.thumb_func\n") ; \
2602 } \
2603 if (TARGET_POKE_FUNCTION_NAME) \
2604 arm_poke_function_name (STREAM, (char *) NAME); \
2605 } \
2606 while (0)
2607
2608 /* For aliases of functions we use .thumb_set instead. */
2609 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2610 do \
2611 { \
2612 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2613 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2614 \
2615 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2616 { \
2617 fprintf (FILE, "\t.thumb_set "); \
2618 assemble_name (FILE, LABEL1); \
2619 fprintf (FILE, ","); \
2620 assemble_name (FILE, LABEL2); \
2621 fprintf (FILE, "\n"); \
2622 } \
2623 else \
2624 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2625 } \
2626 while (0)
2627
2628 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2629 /* To support -falign-* switches we need to use .p2align so
2630 that alignment directives in code sections will be padded
2631 with no-op instructions, rather than zeroes. */
2632 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2633 if ((LOG) != 0) \
2634 { \
2635 if ((MAX_SKIP) == 0) \
2636 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2637 else \
2638 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2639 (LOG), (MAX_SKIP)); \
2640 }
2641 #endif
2642 \f
2643 /* Only perform branch elimination (by making instructions conditional) if
2644 we're optimising. Otherwise it's of no use anyway. */
2645 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2646 if (TARGET_ARM && optimize) \
2647 arm_final_prescan_insn (INSN); \
2648 else if (TARGET_THUMB) \
2649 thumb_final_prescan_insn (INSN)
2650
2651 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2652 (CODE == '@' || CODE == '|' \
2653 || (TARGET_ARM && (CODE == '?')) \
2654 || (TARGET_THUMB && (CODE == '_')))
2655
2656 /* Output an operand of an instruction. */
2657 #define PRINT_OPERAND(STREAM, X, CODE) \
2658 arm_print_operand (STREAM, X, CODE)
2659
2660 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2661 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2662 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2663 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2664 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2665 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2666 : 0))))
2667
2668 /* Output the address of an operand. */
2669 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2670 { \
2671 int is_minus = GET_CODE (X) == MINUS; \
2672 \
2673 if (GET_CODE (X) == REG) \
2674 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2675 else if (GET_CODE (X) == PLUS || is_minus) \
2676 { \
2677 rtx base = XEXP (X, 0); \
2678 rtx index = XEXP (X, 1); \
2679 HOST_WIDE_INT offset = 0; \
2680 if (GET_CODE (base) != REG) \
2681 { \
2682 /* Ensure that BASE is a register */ \
2683 /* (one of them must be). */ \
2684 rtx temp = base; \
2685 base = index; \
2686 index = temp; \
2687 } \
2688 switch (GET_CODE (index)) \
2689 { \
2690 case CONST_INT: \
2691 offset = INTVAL (index); \
2692 if (is_minus) \
2693 offset = -offset; \
2694 asm_fprintf (STREAM, "[%r, #%d]", \
2695 REGNO (base), offset); \
2696 break; \
2697 \
2698 case REG: \
2699 asm_fprintf (STREAM, "[%r, %s%r]", \
2700 REGNO (base), is_minus ? "-" : "", \
2701 REGNO (index)); \
2702 break; \
2703 \
2704 case MULT: \
2705 case ASHIFTRT: \
2706 case LSHIFTRT: \
2707 case ASHIFT: \
2708 case ROTATERT: \
2709 { \
2710 asm_fprintf (STREAM, "[%r, %s%r", \
2711 REGNO (base), is_minus ? "-" : "", \
2712 REGNO (XEXP (index, 0))); \
2713 arm_print_operand (STREAM, index, 'S'); \
2714 fputs ("]", STREAM); \
2715 break; \
2716 } \
2717 \
2718 default: \
2719 abort(); \
2720 } \
2721 } \
2722 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2723 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2724 { \
2725 extern int output_memory_reference_mode; \
2726 \
2727 if (GET_CODE (XEXP (X, 0)) != REG) \
2728 abort (); \
2729 \
2730 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2731 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2732 REGNO (XEXP (X, 0)), \
2733 GET_CODE (X) == PRE_DEC ? "-" : "", \
2734 GET_MODE_SIZE (output_memory_reference_mode));\
2735 else \
2736 asm_fprintf (STREAM, "[%r], #%s%d", \
2737 REGNO (XEXP (X, 0)), \
2738 GET_CODE (X) == POST_DEC ? "-" : "", \
2739 GET_MODE_SIZE (output_memory_reference_mode));\
2740 } \
2741 else output_addr_const (STREAM, X); \
2742 }
2743
2744 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2745 { \
2746 if (GET_CODE (X) == REG) \
2747 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2748 else if (GET_CODE (X) == POST_INC) \
2749 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2750 else if (GET_CODE (X) == PLUS) \
2751 { \
2752 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2753 asm_fprintf (STREAM, "[%r, #%d]", \
2754 REGNO (XEXP (X, 0)), \
2755 (int) INTVAL (XEXP (X, 1))); \
2756 else \
2757 asm_fprintf (STREAM, "[%r, %r]", \
2758 REGNO (XEXP (X, 0)), \
2759 REGNO (XEXP (X, 1))); \
2760 } \
2761 else \
2762 output_addr_const (STREAM, X); \
2763 }
2764
2765 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2766 if (TARGET_ARM) \
2767 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2768 else \
2769 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2770
2771 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2772 Used for C++ multiple inheritance. */
2773 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2774 do \
2775 { \
2776 int mi_delta = (DELTA); \
2777 const char *const mi_op = mi_delta < 0 ? "sub" : "add"; \
2778 int shift = 0; \
2779 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2780 ? 1 : 0); \
2781 if (mi_delta < 0) \
2782 mi_delta = - mi_delta; \
2783 while (mi_delta != 0) \
2784 { \
2785 if ((mi_delta & (3 << shift)) == 0) \
2786 shift += 2; \
2787 else \
2788 { \
2789 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2790 mi_op, this_regno, this_regno, \
2791 mi_delta & (0xff << shift)); \
2792 mi_delta &= ~(0xff << shift); \
2793 shift += 8; \
2794 } \
2795 } \
2796 fputs ("\tb\t", FILE); \
2797 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2798 if (NEED_PLT_RELOC) \
2799 fputs ("(PLT)", FILE); \
2800 fputc ('\n', FILE); \
2801 } \
2802 while (0)
2803
2804 /* A C expression whose value is RTL representing the value of the return
2805 address for the frame COUNT steps up from the current frame. */
2806
2807 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2808 arm_return_addr (COUNT, FRAME)
2809
2810 /* Mask of the bits in the PC that contain the real return address
2811 when running in 26-bit mode. */
2812 #define RETURN_ADDR_MASK26 (0x03fffffc)
2813
2814 /* Pick up the return address upon entry to a procedure. Used for
2815 dwarf2 unwind information. This also enables the table driven
2816 mechanism. */
2817 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2818 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2819
2820 /* Used to mask out junk bits from the return address, such as
2821 processor state, interrupt status, condition codes and the like. */
2822 #define MASK_RETURN_ADDR \
2823 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2824 in 26 bit mode, the condition codes must be masked out of the \
2825 return address. This does not apply to ARM6 and later processors \
2826 when running in 32 bit mode. */ \
2827 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2828 : (GEN_INT ((unsigned long)0xffffffff)))
2829
2830 \f
2831 /* Define the codes that are matched by predicates in arm.c */
2832 #define PREDICATE_CODES \
2833 {"s_register_operand", {SUBREG, REG}}, \
2834 {"arm_hard_register_operand", {REG}}, \
2835 {"f_register_operand", {SUBREG, REG}}, \
2836 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2837 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2838 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2839 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2840 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2841 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2842 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2843 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2844 {"offsettable_memory_operand", {MEM}}, \
2845 {"bad_signed_byte_operand", {MEM}}, \
2846 {"alignable_memory_operand", {MEM}}, \
2847 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2848 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2849 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2850 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2851 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2852 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2853 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2854 {"load_multiple_operation", {PARALLEL}}, \
2855 {"store_multiple_operation", {PARALLEL}}, \
2856 {"equality_operator", {EQ, NE}}, \
2857 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2858 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2859 UNGE, UNGT}}, \
2860 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2861 {"const_shift_operand", {CONST_INT}}, \
2862 {"multi_register_push", {PARALLEL}}, \
2863 {"cc_register", {REG}}, \
2864 {"logical_binary_operator", {AND, IOR, XOR}}, \
2865 {"dominant_cc_register", {REG}},
2866
2867 /* Define this if you have special predicates that know special things
2868 about modes. Genrecog will warn about certain forms of
2869 match_operand without a mode; if the operand predicate is listed in
2870 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2871 #define SPECIAL_MODE_PREDICATES \
2872 "cc_register", "dominant_cc_register",
2873
2874 enum arm_builtins
2875 {
2876 ARM_BUILTIN_CLZ,
2877 ARM_BUILTIN_MAX
2878 };
2879 #endif /* ! GCC_ARM_H */
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