| blob | 3a4acd798468f6480a5038bfcc36d9b58d9a59a3 |
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
47 /* Forward definitions of types. */
51 /* In order to improve the layout of the prototypes below
52 some short type abbreviations are defined here. */
53 #define Hint HOST_WIDE_INT
54 #define Mmode enum machine_mode
55 #define Ulong unsigned long
57 /* Forward function declarations. */
98 \f
99 #undef Hint
100 #undef Mmode
101 #undef Ulong
103 /* The maximum number of insns skipped which will be conditionalised if
104 possible. */
109 /* True if we are currently building a constant table. */
112 /* Define the information needed to generate branch insns. This is
113 stored from the compare operation. */
116 /* What type of floating point are we tuning for? */
119 /* What type of floating point instructions are available? */
122 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
125 /* Set by the -mfp=... option. */
128 /* Used to parse -mstructure_size_boundary command line option. */
132 /* Bit values used to identify processor capabilities. */
143 /* The bits in this mask specify which instructions we are
144 allowed to generate. */
147 /* The bits in this mask specify which instruction scheduling options should
148 be used. Note - there is an overlap with the FL_FAST_MULT. For some
149 hardware we want to be able to generate the multiply instructions, but to
150 tune as if they were not present in the architecture. */
153 /* The following are used in the arm.md file as equivalents to bits
154 in the above two flag variables. */
156 /* Nonzero if this is an "M" variant of the processor. */
159 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
162 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
165 /* Nonzero if this chip can benefit from load scheduling. */
168 /* Nonzero if this chip is a StrongARM. */
171 /* Nonzero if this chip is a an ARM6 or an ARM7. */
174 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
175 must report the mode of the memory reference from PRINT_OPERAND to
176 PRINT_OPERAND_ADDRESS. */
179 /* Nonzero if the prologue must setup `fp'. */
182 /* The register number to be used for the PIC offset register. */
186 /* Set to one if we think that lr is only saved because of subroutine calls,
187 but all of these can be `put after' return insns. */
190 /* Set to 1 when a return insn is output, this means that the epilogue
191 is not needed. */
194 /* Set to 1 after arm_reorg has started. Reset to start at the start of
195 the next function. */
198 /* The maximum number of insns to be used when loading a constant. */
201 /* For an explanation of these variables, see final_prescan_insn below. */
204 rtx arm_target_insn;
207 /* The condition codes of the ARM, and the inverse function. */
209 {
212 };
214 #define streq(string1, string2) (strcmp (string1, string2) == 0)
215 \f
216 /* Initialization code. */
218 struct processors
219 {
222 };
224 /* Not all of these give usefully different compilation alternatives,
225 but there is no simple way of generalizing them. */
227 {
228 /* ARM Cores */
239 /* arm7m doesn't exist on its own, but only with D, (and I), but
240 those don't alter the code, so arm7m is sometimes used. */
254 /* Doesn't have an external co-proc, but does have embedded fpu. */
268 };
271 {
272 /* ARM Architectures */
279 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
280 implementations that support it, so we will leave it out for now. */
284 };
286 /* This is a magic stucture. The 'string' field is magically filled in
287 with a pointer to the value specified by the user on the command line
288 assuming that the user has specified such a value. */
291 {
292 /* string name processors */
296 };
298 /* Return the number of bits set in value' */
299 static unsigned long
302 {
306 {
309 }
312 }
314 /* Fix up any incompatible options that the user has specified.
315 This has now turned into a maze. */
316 void
318 {
321 /* Set up the flags based on the cpu/architecture selected by the user. */
323 {
327 {
332 {
335 else
336 {
337 /* If we have been given an architecture and a processor
338 make sure that they are compatible. We only generate
339 a warning though, and we prefer the CPU over the
340 architecture. */
346 }
349 }
353 }
354 }
356 /* If the user did not specify a processor, choose one for them. */
358 {
361 static struct cpu_default
362 {
365 }
366 cpu_defaults[] =
367 {
381 };
384 /* Find the default. */
389 /* Make sure we found the default CPU. */
393 /* Find the default CPU's flags. */
403 /* Now check to see if the user has specified some command line
404 switch that require certain abilities from the cpu. */
408 {
411 /* Force apcs-32 to be used for interworking. */
414 /* There are no ARM processors that support both APCS-26 and
415 interworking. Therefore we force FL_MODE26 to be removed
416 from insn_flags here (if it was set), so that the search
417 below will always be able to find a compatible processor. */
419 }
424 {
425 /* Try to locate a CPU type that supports all of the abilities
426 of the default CPU, plus the extra abilities requested by
427 the user. */
433 {
437 /* Ideally we would like to issue an error message here
438 saying that it was not possible to find a CPU compatible
439 with the default CPU, but which also supports the command
440 line options specified by the programmer, and so they
441 ought to use the -mcpu=<name> command line option to
442 override the default CPU type.
444 Unfortunately this does not work with multilibing. We
445 need to be able to support multilibs for -mapcs-26 and for
446 -mthumb-interwork and there is no CPU that can support both
447 options. Instead if we cannot find a cpu that has both the
448 characteristics of the default cpu and the given command line
449 options we scan the array again looking for a best match. */
452 {
458 {
461 }
462 }
466 else
468 }
471 }
472 }
474 /* If tuning has not been specified, tune for whichever processor or
475 architecture has been selected. */
479 /* Make sure that the processor choice does not conflict with any of the
480 other command line choices. */
482 {
483 /* If APCS-32 was not the default then it must have been set by the
484 user, so issue a warning message. If the user has specified
485 "-mapcs-32 -mcpu=arm2" then we loose here. */
489 }
491 {
494 }
497 {
500 }
503 {
506 }
509 {
510 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
512 }
514 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
515 from here where no function is being compiled currently. */
521 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
524 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
526 /* If interworking is enabled then APCS-32 must be selected as well. */
528 {
532 }
535 {
538 }
549 /* If this target is normally configured to use APCS frames, warn if they
550 are turned off and debugging is turned on. */
553 && ! TARGET_APCS_FRAME
557 /* If stack checking is disabled, we can use r10 as the PIC register,
558 which keeps r9 available. */
565 /* Initialise boolean versions of the flags, for use in the arm.md file. */
575 /* Default value for floating point code... if no co-processor
576 bus, then schedule for emulated floating point. Otherwise,
577 assume the user has an FPA.
578 Note: this does not prevent use of floating point instructions,
579 -msoft-float does that. */
583 {
588 else
590 target_fp_name);
591 }
592 else
598 /* For arm2/3 there is no need to do any scheduling if there is only
599 a floating point emulator, or we are doing software floating-point. */
607 {
612 else
614 }
617 {
625 /* Prevent the user from choosing an obviously stupid PIC register. */
631 else
633 }
636 {
637 /* Don't warn since it's on by default in -O2. */
639 }
641 /* If optimizing for space, don't synthesize constants.
642 For processors with load scheduling, it never costs more than 2 cycles
643 to load a constant, and the load scheduler may well reduce that to 1. */
647 /* If optimizing for size, bump the number of instructions that we
648 are prepared to conditionally execute (even on a StrongARM).
649 Otherwise for the StrongARM, which has early execution of branches,
650 a sequence that is worth skipping is shorter. */
656 /* Register global variables with the garbage collector. */
658 }
660 static void
662 {
666 /* XXX: What about the minipool tables? */
667 }
668 \f
669 /* Return 1 if it is possible to return using a single instruction. */
670 int
673 {
676 /* Never use a return instruction before reload has run. */
678 /* Or if the function is variadic. */
679 || current_function_pretend_args_size
680 || current_function_anonymous_args
681 /* Of if the function calls __builtin_eh_return () */
683 /* Or if there is no frame pointer and there is a stack adjustment. */
688 /* Can't be done if interworking with Thumb, and any registers have been
689 stacked. Similarly, on StrongARM, conditional returns are expensive
690 if they aren't taken and registers have been stacked. */
696 {
703 }
705 /* Can't be done if any of the FPU regs are pushed, since this also
706 requires an insn. */
712 /* If a function is naked, don't use the "return" insn. */
717 }
719 /* Return TRUE if int I is a valid immediate ARM constant. */
721 int
723 HOST_WIDE_INT i;
724 {
727 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
728 be all zero, or all one. */
735 /* Fast return for 0 and powers of 2 */
739 do
740 {
743 mask =
749 }
751 /* Return true if I is a valid constant for the operation CODE. */
752 static int
754 HOST_WIDE_INT i;
756 {
761 {
775 }
776 }
778 /* Emit a sequence of insns to handle a large constant.
779 CODE is the code of the operation required, it can be any of SET, PLUS,
780 IOR, AND, XOR, MINUS;
781 MODE is the mode in which the operation is being performed;
782 VAL is the integer to operate on;
783 SOURCE is the other operand (a register, or a null-pointer for SET);
784 SUBTARGETS means it is safe to create scratch registers if that will
785 either produce a simpler sequence, or we will want to cse the values.
786 Return value is the number of insns emitted. */
788 int
792 HOST_WIDE_INT val;
793 rtx target;
794 rtx source;
796 {
800 {
801 /* After arm_reorg has been called, we can't fix up expensive
802 constants by pushing them into memory so we must synthesise
803 them in-line, regardless of the cost. This is only likely to
804 be more costly on chips that have load delay slots and we are
805 compiling without running the scheduler (so no splitting
806 occurred before the final instruction emission).
808 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
809 */
813 {
815 {
816 /* Currently SET is the only monadic value for CODE, all
817 the rest are diadic. */
820 }
821 else
822 {
826 /* For MINUS, the value is subtracted from, since we never
827 have subtraction of a constant. */
831 else
835 }
836 }
837 }
840 }
842 /* As above, but extra parameter GENERATE which, if clear, suppresses
843 RTL generation. */
844 static int
848 HOST_WIDE_INT val;
849 rtx target;
850 rtx source;
853 {
868 /* Find out which operations are safe for a given CODE. Also do a quick
869 check for degenerate cases; these can occur when DImode operations
870 are split. */
872 {
886 {
891 }
893 {
899 }
904 {
908 }
910 {
916 }
922 {
928 }
930 {
935 }
937 /* We don't know how to handle this yet below. */
941 /* We treat MINUS as (val - source), since (source - val) is always
942 passed as (source + (-val)). */
944 {
949 }
951 {
955 source)));
957 }
964 }
966 /* If we can do it in one insn get out quickly. */
970 {
977 }
979 /* Calculate a few attributes that may be useful for specific
980 optimizations. */
982 {
984 clear_sign_bit_copies++;
985 else
987 }
990 {
992 set_sign_bit_copies++;
993 else
995 }
998 {
1000 clear_zero_bit_copies++;
1001 else
1003 }
1006 {
1008 set_zero_bit_copies++;
1009 else
1011 }
1014 {
1016 /* See if we can do this by sign_extending a constant that is known
1017 to be negative. This is a good, way of doing it, since the shift
1018 may well merge into a subsequent insn. */
1020 {
1024 {
1026 {
1032 }
1034 }
1035 /* For an inverted constant, we will need to set the low bits,
1036 these will be shifted out of harm's way. */
1039 {
1041 {
1047 }
1049 }
1050 }
1052 /* See if we can generate this by setting the bottom (or the top)
1053 16 bits, and then shifting these into the other half of the
1054 word. We only look for the simplest cases, to do more would cost
1055 too much. Be careful, however, not to generate this when the
1056 alternative would take fewer insns. */
1058 {
1062 /* Overlaps outside this range are best done using other methods. */
1064 {
1068 {
1069 rtx new_src = (subtargets
1081 source)));
1083 }
1084 }
1086 /* Don't duplicate cases already considered. */
1088 {
1091 {
1092 rtx new_src = (subtargets
1099 emit_insn
1101 gen_rtx_IOR
1105 source)));
1107 }
1108 }
1109 }
1114 /* If we have IOR or XOR, and the constant can be loaded in a
1115 single instruction, and we can find a temporary to put it in,
1116 then this can be done in two instructions instead of 3-4. */
1118 /* TARGET can't be NULL if SUBTARGETS is 0 */
1120 {
1122 {
1124 {
1130 }
1132 }
1133 }
1140 {
1142 {
1149 source,
1150 shift))));
1154 shift))));
1155 }
1157 }
1161 {
1163 {
1170 source,
1171 shift))));
1175 shift))));
1176 }
1178 }
1181 {
1183 {
1195 }
1197 }
1201 /* See if two shifts will do 2 or more insn's worth of work. */
1203 {
1209 {
1211 {
1216 }
1217 else
1218 {
1222 }
1223 }
1226 {
1232 }
1235 }
1238 {
1242 {
1244 {
1250 }
1251 else
1252 {
1257 }
1258 }
1261 {
1267 }
1270 }
1276 }
1280 num_bits_set++;
1286 else
1287 {
1290 }
1292 /* Now try and find a way of doing the job in either two or three
1293 instructions.
1294 We start by looking for the largest block of zeros that are aligned on
1295 a 2-bit boundary, we then fill up the temps, wrapping around to the
1296 top of the word when we drop off the bottom.
1297 In the worst case this code should produce no more than four insns. */
1298 {
1303 {
1307 {
1309 {
1312 }
1314 {
1317 }
1319 }
1320 }
1322 /* Now start emitting the insns, starting with the one with the highest
1323 bit set: we do this so that the smallest number will be emitted last;
1324 this is more likely to be combinable with addressing insns. */
1326 do
1327 {
1333 {
1342 {
1343 rtx new_src;
1347 new_src = (subtargets
1354 new_src = (subtargets
1358 source)));
1359 else
1361 new_src = (remainder
1362 ? (subtargets
1368 : (can_negate
1369 ? -temp1
1372 }
1375 {
1378 }
1382 insns++;
1384 }
1387 }
1389 }
1391 /* Canonicalize a comparison so that we are more likely to recognize it.
1392 This can be done for a few constant compares, where we can make the
1393 immediate value easier to load. */
1394 enum rtx_code
1398 {
1402 {
1412 {
1415 }
1422 {
1425 }
1432 {
1435 }
1442 {
1445 }
1450 }
1453 }
1455 /* Decide whether a type should be returned in memory (true)
1456 or in a register (false). This is called by the macro
1457 RETURN_IN_MEMORY. */
1458 int
1460 tree type;
1461 {
1463 /* All simple types are returned in registers. */
1466 /* For the arm-wince targets we choose to be compitable with Microsoft's
1467 ARM and Thumb compilers, which always return aggregates in memory. */
1468 #ifndef ARM_WINCE
1471 /* All structures/unions bigger than one word are returned in memory. */
1475 {
1476 tree field;
1478 /* For a struct the APCS says that we only return in a register
1479 if the type is 'integer like' and every addressable element
1480 has an offset of zero. For practical purposes this means
1481 that the structure can have at most one non bit-field element
1482 and that this element must be the first one in the structure. */
1484 /* Find the first field, ignoring non FIELD_DECL things which will
1485 have been created by C++. */
1494 /* Check that the first field is valid for returning in a register. */
1496 /* ... Floats are not allowed */
1500 /* ... Aggregates that are not themselves valid for returning in
1501 a register are not allowed. */
1505 /* Now check the remaining fields, if any. Only bitfields are allowed,
1506 since they are not addressable. */
1508 field;
1510 {
1516 }
1519 }
1522 {
1523 tree field;
1525 /* Unions can be returned in registers if every element is
1526 integral, or can be returned in an integer register. */
1528 field;
1530 {
1539 }
1542 }
1545 /* Return all other types in memory. */
1547 }
1549 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1550 for a call to a function whose data type is FNTYPE.
1551 For a library call, FNTYPE is NULL. */
1552 void
1555 tree fntype;
1556 rtx libname ATTRIBUTE_UNUSED;
1558 {
1559 /* On the ARM, the offset starts at 0. */
1567 /* Check for long call/short call attributes. The attributes
1568 override any command line option. */
1570 {
1575 }
1576 }
1578 /* Determine where to put an argument to a function.
1579 Value is zero to push the argument on the stack,
1580 or a hard register in which to store the argument.
1582 MODE is the argument's machine mode.
1583 TYPE is the data type of the argument (as a tree).
1584 This is null for libcalls where that information may
1585 not be available.
1586 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1587 the preceding args and about the function being called.
1588 NAMED is nonzero if this argument is a named parameter
1589 (otherwise it is an extra parameter matching an ellipsis). */
1590 rtx
1594 tree type ATTRIBUTE_UNUSED;
1596 {
1598 /* Compute operand 2 of the call insn. */
1605 }
1606 \f
1607 /* Encode the current state of the #pragma [no_]long_calls. */
1609 {
1612 SHORT /* #pragma no_long_calls is in effect. */
1617 /* Handle pragmas for compatibility with Intel's compilers.
1618 FIXME: This is incomplete, since it does not handle all
1619 the pragmas that the Intel compilers understand. */
1620 int
1625 {
1626 /* Should be pragma 'far' or equivalent for callx/balx here. */
1633 else
1637 }
1638 \f
1639 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1640 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1641 assigned to TYPE. */
1642 int
1644 tree type;
1645 tree attributes ATTRIBUTE_UNUSED;
1646 tree identifier;
1647 tree args;
1648 {
1655 /* Function calls made to this symbol must be done indirectly, because
1656 it may lie outside of the 26 bit addressing range of a normal function
1657 call. */
1661 /* Whereas these functions are always known to reside within the 26 bit
1662 addressing range. */
1667 }
1669 /* Return 0 if the attributes for two types are incompatible, 1 if they
1670 are compatible, and 2 if they are nearly compatible (which causes a
1671 warning to be generated). */
1672 int
1674 tree type1;
1675 tree type2;
1676 {
1679 /* Check for mismatch of non-default calling convention. */
1683 /* Check for mismatched call attributes. */
1689 /* Only bother to check if an attribute is defined. */
1691 {
1692 /* If one type has an attribute, the other must have the same attribute. */
1696 /* Disallow mixed attributes. */
1699 }
1702 }
1704 /* Encode long_call or short_call attribute by prefixing
1705 symbol name in DECL with a special character FLAG. */
1706 void
1708 tree decl;
1710 {
1718 /* Do not allow weak functions to be treated as short call. */
1724 else
1730 }
1732 /* Assigns default attributes to newly defined type. This is used to
1733 set short_call/long_call attributes for function types of
1734 functions defined inside corresponding #pragma scopes. */
1735 void
1737 tree type;
1738 {
1739 /* Add __attribute__ ((long_call)) to all functions, when
1740 inside #pragma long_calls or __attribute__ ((short_call)),
1741 when inside #pragma no_long_calls. */
1743 {
1751 else
1756 }
1757 }
1758 \f
1759 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1760 defined within the current compilation unit. If this caanot be
1761 determined, then 0 is returned. */
1762 static int
1764 rtx sym_ref;
1765 {
1766 /* This is a bit of a fib. A function will have a short call flag
1767 applied to its name if it has the short call attribute, or it has
1768 already been defined within the current compilation unit. */
1772 /* The current funciton is always defined within the current compilation
1773 unit. if it s a weak defintion however, then this may not be the real
1774 defintion of the function, and so we have to say no. */
1779 /* We cannot make the determination - default to returning 0. */
1781 }
1783 /* Return non-zero if a 32 bit "long_call" should be generated for
1784 this call. We generate a long_call if the function:
1786 a. has an __attribute__((long call))
1787 or b. is within the scope of a #pragma long_calls
1788 or c. the -mlong-calls command line switch has been specified
1790 However we do not generate a long call if the function:
1792 d. has an __attribute__ ((short_call))
1793 or e. is inside the scope of a #pragma no_long_calls
1794 or f. has an __attribute__ ((section))
1795 or g. is defined within the current compilation unit.
1797 This function will be called by C fragments contained in the machine
1798 description file. CALL_REF and CALL_COOKIE correspond to the matched
1799 rtl operands. CALL_SYMBOL is used to distinguish between
1800 two different callers of the function. It is set to 1 in the
1801 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1802 and "call_value" patterns. This is because of the difference in the
1803 SYM_REFs passed by these patterns. */
1804 int
1806 rtx sym_ref;
1809 {
1811 {
1816 }
1833 }
1834 \f
1835 int
1837 rtx x;
1838 {
1840 && flag_pic
1848 }
1850 rtx
1852 rtx orig;
1854 rtx reg;
1855 {
1857 {
1859 rtx insn;
1863 {
1866 else
1870 }
1872 #ifdef AOF_ASSEMBLER
1873 /* The AOF assembler can generate relocations for these directly, and
1874 understands that the PIC register has to be added into the offset. */
1876 #else
1879 else
1886 address));
1889 #endif
1891 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1892 by loop. */
1896 }
1898 {
1906 {
1909 else
1911 }
1914 {
1918 }
1919 else
1923 {
1924 /* The base register doesn't really matter, we only want to
1925 test the index for the appropriate mode. */
1930 else
1933 win:
1936 }
1941 {
1944 }
1947 }
1949 {
1953 {
1961 }
1962 }
1965 }
1969 int
1971 rtx x;
1972 {
1976 }
1978 void
1980 {
1981 #ifndef AOF_ASSEMBLER
1983 rtx global_offset_table;
1995 /* On the ARM the PC register contains 'dot + 8' at the time of the
1996 addition, on the Thumb it is 'dot + 4'. */
2001 else
2009 else
2016 /* Need to emit this whether or not we obey regdecls,
2017 since setjmp/longjmp can cause life info to screw up. */
2020 }
2022 #define REG_OR_SUBREG_REG(X) \
2023 (GET_CODE (X) == REG \
2024 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2026 #define REG_OR_SUBREG_RTX(X) \
2027 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2029 #ifndef COSTS_N_INSNS
2030 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2031 #endif
2033 int
2035 rtx x;
2038 {
2044 {
2046 {
2060 {
2065 {
2067 cycles ++;
2068 }
2070 }
2080 {
2086 }
2116 /* XXX guess. */
2121 /* XXX another guess. */
2122 /* Memory costs quite a lot for the first word, but subsequent words
2123 load at the equivalent of a single insn each. */
2128 /* XXX a guess. */
2134 /* XXX still guessing. */
2136 {
2150 }
2154 #if 0
2159 /* XXX guess */
2163 #endif
2164 }
2165 }
2168 {
2170 /* Memory costs quite a lot for the first word, but subsequent words
2171 load at the equivalent of a single insn each. */
2182 /* Fall through */
2186 /* Fall through */
2237 /* Fall through */
2247 /* Fall through */
2251 /* Normally the frame registers will be spilt into reg+const during
2252 reload, so it is a bad idea to combine them with other instructions,
2253 since then they might not be moved outside of loops. As a compromise
2254 we allow integration with ops that have a constant as their second
2255 operand. */
2294 /* There is no point basing this on the tuning, since it is always the
2295 fast variant if it exists at all. */
2307 {
2313 /* Tune as appropriate. */
2317 {
2320 }
2323 }
2343 /* Fall through */
2365 /* Fall through */
2368 {
2382 }
2395 else
2413 }
2414 }
2416 int
2418 rtx insn;
2419 rtx link;
2420 rtx dep;
2422 {
2425 /* XXX This is not strictly true for the FPA. */
2430 /* Call insns don't incur a stall, even if they follow a load. */
2439 {
2440 /* This is a load after a store, there is no conflict if the load reads
2441 from a cached area. Assume that loads from the stack, and from the
2442 constant pool are cached, and that others will miss. This is a
2443 hack. */
2451 }
2454 }
2456 /* This code has been fixed for cross compilation. */
2461 {
2464 };
2468 static void
2470 {
2472 REAL_VALUE_TYPE r;
2475 {
2478 }
2481 }
2483 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2485 int
2487 rtx x;
2488 {
2489 REAL_VALUE_TYPE r;
2504 }
2506 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2508 int
2510 rtx x;
2511 {
2512 REAL_VALUE_TYPE r;
2528 }
2529 \f
2530 /* Predicates for `match_operand' and `match_operator'. */
2532 /* s_register_operand is the same as register_operand, but it doesn't accept
2533 (SUBREG (MEM)...).
2535 This function exists because at the time it was put in it led to better
2536 code. SUBREG(MEM) always needs a reload in the places where
2537 s_register_operand is used, and this seemed to lead to excessive
2538 reloading. */
2540 int
2544 {
2551 /* We don't consider registers whose class is NO_REGS
2552 to be a register operand. */
2553 /* XXX might have to check for lo regs only for thumb ??? */
2557 }
2559 /* Only accept reg, subreg(reg), const_int. */
2561 int
2565 {
2575 /* We don't consider registers whose class is NO_REGS
2576 to be a register operand. */
2580 }
2582 /* Return 1 if OP is an item in memory, given that we are in reload. */
2584 int
2586 rtx op;
2588 {
2595 }
2597 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2598 memory access (architecture V4).
2599 MODE is QImode if called when computing contraints, or VOIDmode when
2600 emitting patterns. In this latter case we cannot use memory_operand()
2601 because it will fail on badly formed MEMs, which is precisly what we are
2602 trying to catch. */
2603 int
2605 rtx op;
2607 {
2608 #if 0
2611 #endif
2617 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2624 /* Big constants are also bad. */
2630 /* Everything else is good, or can will automatically be made so. */
2632 }
2634 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2636 int
2638 rtx op;
2640 {
2643 }
2645 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2646 */
2648 int
2650 rtx op;
2652 {
2656 }
2658 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2659 constant that is valid when negated. */
2661 int
2663 rtx op;
2665 {
2673 }
2675 int
2677 rtx op;
2679 {
2684 }
2686 /* Return TRUE if the operand is a memory reference which contains an
2687 offsettable address. */
2688 int
2692 {
2700 }
2702 /* Return TRUE if the operand is a memory reference which is, or can be
2703 made word aligned by adjusting the offset. */
2704 int
2708 {
2709 rtx reg;
2728 }
2730 /* Similar to s_register_operand, but does not allow hard integer
2731 registers. */
2732 int
2736 {
2743 /* We don't consider registers whose class is NO_REGS
2744 to be a register operand. */
2748 }
2750 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2752 int
2754 rtx op;
2756 {
2767 }
2769 int
2771 rtx op;
2773 {
2785 }
2787 /* Return nonzero if OP is a constant power of two. */
2789 int
2791 rtx op;
2793 {
2795 {
2798 }
2800 }
2802 /* Return TRUE for a valid operand of a DImode operation.
2803 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2804 Note that this disallows MEM(REG+REG), but allows
2805 MEM(PRE/POST_INC/DEC(REG)). */
2807 int
2809 rtx op;
2811 {
2822 {
2832 }
2833 }
2835 /* Like di_operand, but don't accept constants. */
2836 int
2838 rtx op;
2840 {
2854 }
2856 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2857 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2858 Note that this disallows MEM(REG+REG), but allows
2859 MEM(PRE/POST_INC/DEC(REG)). */
2861 int
2863 rtx op;
2865 {
2879 {
2888 }
2889 }
2891 /* Like soft_df_operand, but don't accept constants. */
2892 int
2894 rtx op;
2896 {
2909 }
2911 /* Return TRUE for valid index operands. */
2912 int
2914 rtx op;
2916 {
2921 }
2923 /* Return TRUE for valid shifts by a constant. This also accepts any
2924 power of two on the (somewhat overly relaxed) assumption that the
2925 shift operator in this case was a mult. */
2927 int
2929 rtx op;
2931 {
2936 }
2938 /* Return TRUE for arithmetic operators which can be combined with a multiply
2939 (shift). */
2941 int
2943 rtx x;
2945 {
2948 else
2949 {
2954 }
2955 }
2957 /* Return TRUE for binary logical operators. */
2959 int
2961 rtx x;
2963 {
2966 else
2967 {
2971 }
2972 }
2974 /* Return TRUE for shift operators. */
2976 int
2978 rtx x;
2980 {
2983 else
2984 {
2992 }
2993 }
2995 /* Return TRUE if x is EQ or NE. */
2996 int
2998 rtx x;
3000 {
3002 }
3004 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3005 int
3007 rtx x;
3009 {
3016 }
3018 /* Return TRUE if this is the condition code register, if we aren't given
3019 a mode, accept any class CCmode register. */
3020 int
3022 rtx x;
3024 {
3026 {
3031 }
3039 }
3041 /* Return TRUE if this is the condition code register, if we aren't given
3042 a mode, accept any class CCmode register which indicates a dominance
3043 expression. */
3044 int
3046 rtx x;
3048 {
3050 {
3055 }
3065 }
3067 /* Return TRUE if X references a SYMBOL_REF. */
3068 int
3070 rtx x;
3071 {
3081 {
3083 {
3089 }
3092 }
3095 }
3097 /* Return TRUE if X references a LABEL_REF. */
3098 int
3100 rtx x;
3101 {
3110 {
3112 {
3118 }
3121 }
3124 }
3126 enum rtx_code
3128 rtx x;
3129 {
3142 }
3144 /* Return 1 if memory locations are adjacent. */
3145 int
3148 {
3158 {
3160 {
3163 }
3164 else
3167 {
3170 }
3171 else
3174 }
3176 }
3178 /* Return 1 if OP is a load multiple operation. It is known to be
3179 parallel and the first section will be tested. */
3180 int
3182 rtx op;
3184 {
3187 rtx src_addr;
3189 rtx elt;
3195 /* Check to see if this might be a write-back. */
3197 {
3198 i++;
3201 /* Now check it more carefully. */
3213 count--;
3214 }
3216 /* Perform a quick check so we don't blow up below. */
3227 {
3241 }
3244 }
3246 /* Return 1 if OP is a store multiple operation. It is known to be
3247 parallel and the first section will be tested. */
3248 int
3250 rtx op;
3252 {
3255 rtx dest_addr;
3257 rtx elt;
3263 /* Check to see if this might be a write-back. */
3265 {
3266 i++;
3269 /* Now check it more carefully. */
3281 count--;
3282 }
3284 /* Perform a quick check so we don't blow up below. */
3295 {
3309 }
3312 }
3314 int
3321 {
3328 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3329 extended if required. */
3333 /* Loop over the operands and check that the memory references are
3334 suitable (ie immediate offsets from the same base register). At
3335 the same time, extract the target register, and the memory
3336 offsets. */
3338 {
3339 rtx reg;
3340 rtx offset;
3342 /* Convert a subreg of a mem into the mem itself. */
3349 /* Don't reorder volatile memory references; it doesn't seem worth
3350 looking for the case where the order is ok anyway. */
3366 {
3368 {
3374 }
3375 else
3376 {
3378 /* Not addressed from the same base register. */
3386 }
3388 /* If it isn't an integer register, or if it overwrites the
3389 base register but isn't the last insn in the list, then
3390 we can't do this. */
3396 }
3397 else
3398 /* Not a suitable memory address. */
3400 }
3402 /* All the useful information has now been extracted from the
3403 operands into unsorted_regs and unsorted_offsets; additionally,
3404 order[0] has been set to the lowest numbered register in the
3405 list. Sort the registers into order, and check that the memory
3406 offsets are ascending and adjacent. */
3409 {
3419 /* Have we found a suitable register? if not, one must be used more
3420 than once. */
3424 /* Is the memory address adjacent and ascending? */
3427 }
3430 {
3437 }
3451 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3452 if the offset isn't small enough. The reason 2 ldrs are faster
3453 is because these ARMs are able to do more than one cache access
3454 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3455 whilst the ARM8 has a double bandwidth cache. This means that
3456 these cores can do both an instruction fetch and a data fetch in
3457 a single cycle, so the trick of calculating the address into a
3458 scratch register (one of the result regs) and then doing a load
3459 multiple actually becomes slower (and no smaller in code size).
3460 That is the transformation
3462 ldr rd1, [rbase + offset]
3463 ldr rd2, [rbase + offset + 4]
3465 to
3467 add rd1, rbase, offset
3468 ldmia rd1, {rd1, rd2}
3470 produces worse code -- '3 cycles + any stalls on rd2' instead of
3471 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3472 access per cycle, the first sequence could never complete in less
3473 than 6 cycles, whereas the ldm sequence would only take 5 and
3474 would make better use of sequential accesses if not hitting the
3475 cache.
3477 We cheat here and test 'arm_ld_sched' which we currently know to
3478 only be true for the ARM8, ARM9 and StrongARM. If this ever
3479 changes, then the test below needs to be reworked. */
3483 /* Can't do it without setting up the offset, only do this if it takes
3484 no more than one insn. */
3487 }
3493 {
3496 HOST_WIDE_INT offset;
3501 {
3523 else
3534 }
3547 }
3549 int
3556 {
3563 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3564 extended if required. */
3568 /* Loop over the operands and check that the memory references are
3569 suitable (ie immediate offsets from the same base register). At
3570 the same time, extract the target register, and the memory
3571 offsets. */
3573 {
3574 rtx reg;
3575 rtx offset;
3577 /* Convert a subreg of a mem into the mem itself. */
3584 /* Don't reorder volatile memory references; it doesn't seem worth
3585 looking for the case where the order is ok anyway. */
3601 {
3603 {
3609 }
3610 else
3611 {
3613 /* Not addressed from the same base register. */
3621 }
3623 /* If it isn't an integer register, then we can't do this. */
3628 }
3629 else
3630 /* Not a suitable memory address. */
3632 }
3634 /* All the useful information has now been extracted from the
3635 operands into unsorted_regs and unsorted_offsets; additionally,
3636 order[0] has been set to the lowest numbered register in the
3637 list. Sort the registers into order, and check that the memory
3638 offsets are ascending and adjacent. */
3641 {
3651 /* Have we found a suitable register? if not, one must be used more
3652 than once. */
3656 /* Is the memory address adjacent and ascending? */
3659 }
3662 {
3669 }
3684 }
3690 {
3693 HOST_WIDE_INT offset;
3698 {
3717 }
3730 }
3732 int
3734 rtx op;
3736 {
3744 }
3745 \f
3746 /* Routines for use with attributes. */
3748 /* Return nonzero if ATTR is a valid attribute for DECL.
3749 ATTRIBUTES are any existing attributes and ARGS are
3750 the arguments supplied with ATTR.
3752 Supported attributes:
3754 naked:
3755 don't output any prologue or epilogue code, the user is assumed
3756 to do the right thing.
3758 interfacearm:
3759 Always assume that this function will be entered in ARM mode,
3760 not Thumb mode, and that the caller wishes to be returned to in
3761 ARM mode. */
3762 int
3764 tree decl;
3765 tree attr;
3766 tree args;
3767 {
3774 #ifdef ARM_PE
3780 }
3782 /* Return non-zero if FUNC is a naked function. */
3783 static int
3785 tree func;
3786 {
3787 tree a;
3794 }
3795 \f
3796 /* Routines for use in generating RTL. */
3797 rtx
3802 rtx from;
3808 {
3810 rtx result;
3812 rtx mem;
3817 {
3822 count++;
3823 }
3826 {
3833 }
3839 }
3841 rtx
3846 rtx to;
3852 {
3854 rtx result;
3856 rtx mem;
3861 {
3866 count++;
3867 }
3870 {
3878 }
3884 }
3886 int
3889 {
3895 rtx mem;
3926 {
3929 src_unchanging_p,
3930 src_in_struct_p,
3931 src_scalar_p));
3932 else
3938 {
3941 dst_unchanging_p,
3942 dst_in_struct_p,
3943 dst_scalar_p));
3949 dst_unchanging_p,
3950 dst_in_struct_p,
3951 dst_scalar_p));
3952 else
3953 {
3961 }
3962 }
3966 }
3968 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3970 {
3971 rtx sreg;
3986 in_words_to_go--;
3990 }
3993 {
4002 }
4008 {
4011 /* The bytes we want are in the top end of the word. */
4017 {
4025 {
4029 }
4030 }
4032 }
4033 else
4034 {
4036 {
4044 {
4050 }
4051 }
4054 {
4060 }
4061 }
4064 }
4066 /* Generate a memory reference for a half word, such that it will be loaded
4067 into the top 16 bits of the word. We can assume that the address is
4068 known to be alignable and of the form reg, or plus (reg, const). */
4069 rtx
4071 rtx memref;
4072 {
4077 {
4080 }
4082 /* If we aren't allowed to generate unaligned addresses, then fail. */
4093 }
4095 static enum machine_mode
4097 rtx x;
4098 rtx y;
4099 HOST_WIDE_INT cond_or;
4100 {
4104 /* Currently we will probably get the wrong result if the individual
4105 comparisons are not simple. This also ensures that it is safe to
4106 reverse a comparison if necessary. */
4116 /* If the comparisons are not equal, and one doesn't dominate the other,
4117 then we can't do this. */
4124 {
4128 }
4131 {
4137 {
4143 }
4183 /* The remaining cases only occur when both comparisons are the
4184 same. */
4202 }
4205 }
4207 enum machine_mode
4210 rtx x;
4211 rtx y;
4212 {
4213 /* All floating point compares return CCFP if it is an equality
4214 comparison, and CCFPE otherwise. */
4218 /* A compare with a shifted operand. Because of canonicalization, the
4219 comparison will have to be swapped when we emit the assembler. */
4226 /* This is a special case that is used by combine to allow a
4227 comparison of a shifted byte load to be split into a zero-extend
4228 followed by a comparison of the shifted integer (only valid for
4229 equalities and unsigned inequalities). */
4241 /* An operation that sets the condition codes as a side-effect, the
4242 V flag is not set correctly, so we can only use comparisons where
4243 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4244 instead. */
4257 /* A construct for a conditional compare, if the false arm contains
4258 0, then both conditions must be true, otherwise either condition
4259 must be true. Not all conditions are possible, so CCmode is
4260 returned if it can't be done. */
4278 }
4280 /* X and Y are two things to compare using CODE. Emit the compare insn and
4281 return the rtx for register 0 in the proper mode. FP means this is a
4282 floating point compare: I don't think that it is needed on the arm. */
4284 rtx
4288 {
4296 }
4298 void
4301 {
4307 {
4314 }
4317 {
4318 /* We have a pseudo which has been spilt onto the stack; there
4319 are two cases here: the first where there is a simple
4320 stack-slot replacement and a second where the stack-slot is
4321 out of range, or is used as a subreg. */
4323 {
4326 }
4327 else
4328 /* The slot is out of range, or was dressed up in a SUBREG. */
4330 }
4331 else
4334 /* Handle the case where the address is too complex to be offset by 1. */
4337 {
4342 }
4344 {
4345 /* The addend must be CONST_INT, or we would have dealt with it above. */
4351 /* Rework the address into a legal sequence of insns. */
4352 /* Valid range for lo is -4095 -> 4095 */
4357 /* Corner case, if lo is the max offset then we would be out of range
4358 once we have added the additional 1 below, so bump the msb into the
4359 pre-loading insn(s). */
4371 {
4374 /* Get the base address; addsi3 knows how to handle constants
4375 that require more than one insn. */
4379 }
4380 }
4386 offset))));
4394 gen_rtx_ASHIFT
4398 scratch)));
4399 else
4406 }
4408 /* Handle storing a half-word to memory during reload by synthesising as two
4409 byte stores. Take care not to clobber the input values until after we
4410 have moved them somewhere safe. This code assumes that if the DImode
4411 scratch in operands[2] overlaps either the input value or output address
4412 in some way, then that value must die in this insn (we absolutely need
4413 two scratch registers for some corner cases). */
4414 void
4417 {
4424 {
4431 }
4435 {
4436 /* We have a pseudo which has been spilt onto the stack; there
4437 are two cases here: the first where there is a simple
4438 stack-slot replacement and a second where the stack-slot is
4439 out of range, or is used as a subreg. */
4441 {
4444 }
4445 else
4446 /* The slot is out of range, or was dressed up in a SUBREG. */
4448 }
4449 else
4454 /* Handle the case where the address is too complex to be offset by 1. */
4457 {
4460 /* Be careful not to destroy OUTVAL. */
4462 {
4463 /* Updating base_plus might destroy outval, see if we can
4464 swap the scratch and base_plus. */
4466 {
4470 }
4471 else
4472 {
4475 /* Be conservative and copy OUTVAL into the scratch now,
4476 this should only be necessary if outval is a subreg
4477 of something larger than a word. */
4478 /* XXX Might this clobber base? I can't see how it can,
4479 since scratch is known to overlap with OUTVAL, and
4480 must be wider than a word. */
4483 }
4484 }
4488 }
4490 {
4491 /* The addend must be CONST_INT, or we would have dealt with it above. */
4497 /* Rework the address into a legal sequence of insns. */
4498 /* Valid range for lo is -4095 -> 4095 */
4503 /* Corner case, if lo is the max offset then we would be out of range
4504 once we have added the additional 1 below, so bump the msb into the
4505 pre-loading insn(s). */
4517 {
4520 /* Be careful not to destroy OUTVAL. */
4522 {
4523 /* Updating base_plus might destroy outval, see if we
4524 can swap the scratch and base_plus. */
4526 {
4530 }
4531 else
4532 {
4535 /* Be conservative and copy outval into scratch now,
4536 this should only be necessary if outval is a
4537 subreg of something larger than a word. */
4538 /* XXX Might this clobber base? I can't see how it
4539 can, since scratch is known to overlap with
4540 outval. */
4543 }
4544 }
4546 /* Get the base address; addsi3 knows how to handle constants
4547 that require more than one insn. */
4551 }
4552 }
4555 {
4564 }
4565 else
4566 {
4575 }
4576 }
4577 \f
4578 /* Print a symbolic form of X to the debug file, F. */
4579 static void
4582 rtx x;
4583 {
4585 {
4623 }
4624 }
4625 \f
4626 /* Routines for manipulation of the constant pool. */
4628 /* Arm instructions cannot load a large constant directly into a
4629 register; they have to come from a pc relative load. The constant
4630 must therefore be placed in the addressable range of the pc
4631 relative load. Depending on the precise pc relative load
4632 instruction the range is somewhere between 256 bytes and 4k. This
4633 means that we often have to dump a constant inside a function, and
4634 generate code to branch around it.
4636 It is important to minimize this, since the branches will slow
4637 things down and make the code larger.
4639 Normally we can hide the table after an existing unconditional
4640 branch so that there is no interruption of the flow, but in the
4641 worst case the code looks like this:
4643 ldr rn, L1
4644 ...
4645 b L2
4646 align
4647 L1: .long value
4648 L2:
4649 ...
4651 ldr rn, L3
4652 ...
4653 b L4
4654 align
4655 L3: .long value
4656 L4:
4657 ...
4659 We fix this by performing a scan after scheduling, which notices
4660 which instructions need to have their operands fetched from the
4661 constant table and builds the table.
4663 The algorithm starts by building a table of all the constants that
4664 need fixing up and all the natural barriers in the function (places
4665 where a constant table can be dropped without breaking the flow).
4666 For each fixup we note how far the pc-relative replacement will be
4667 able to reach and the offset of the instruction into the function.
4669 Having built the table we then group the fixes together to form
4670 tables that are as large as possible (subject to addressing
4671 constraints) and emit each table of constants after the last
4672 barrier that is within range of all the instructions in the group.
4673 If a group does not contain a barrier, then we forcibly create one
4674 by inserting a jump instruction into the flow. Once the table has
4675 been inserted, the insns are then modified to reference the
4676 relevant entry in the pool.
4678 Possible enhancements to the algorithm (not implemented) are:
4680 1) For some processors and object formats, there may be benefit in
4681 aligning the pools to the start of cache lines; this alignment
4682 would need to be taken into account when calculating addressability
4683 of a pool. */
4685 /* These typedefs are located at the start of this file, so that
4686 they can be used in the prototypes there. This comment is to
4687 remind readers of that fact so that the following structures
4688 can be understood more easily.
4690 typedef struct minipool_node Mnode;
4691 typedef struct minipool_fixup Mfix; */
4693 struct minipool_node
4694 {
4695 /* Doubly linked chain of entries. */
4698 /* The maximum offset into the code that this entry can be placed. While
4699 pushing fixes for forward references, all entries are sorted in order
4700 of increasing max_address. */
4701 HOST_WIDE_INT max_address;
4702 /* Similarly for a entry inserted for a backwards ref. */
4703 HOST_WIDE_INT min_address;
4704 /* The number of fixes referencing this entry. This can become zero
4705 if we "unpush" an entry. In this case we ignore the entry when we
4706 come to emit the code. */
4708 /* The offset from the start of the minipool. */
4709 HOST_WIDE_INT offset;
4710 /* The value in table. */
4711 rtx value;
4712 /* The mode of value. */
4715 };
4717 struct minipool_fixup
4718 {
4720 rtx insn;
4721 HOST_WIDE_INT address;
4725 rtx value;
4727 HOST_WIDE_INT forwards;
4728 HOST_WIDE_INT backwards;
4729 };
4731 /* Fixes less than a word need padding out to a word boundary. */
4732 #define MINIPOOL_FIX_SIZE(mode) \
4733 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
4739 /* The linked list of all minipool fixes required for this function. */
4742 /* The fix entry for the current minipool, once it has been placed. */
4745 /* Determines if INSN is the start of a jump table. Returns the end
4746 of the TABLE or NULL_RTX. */
4747 static rtx
4749 rtx insn;
4750 {
4751 rtx table;
4764 }
4766 static HOST_WIDE_INT
4768 rtx insn;
4769 {
4774 }
4776 /* Move a minipool fix MP from its current location to before MAX_MP.
4777 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
4778 contrains may need updating. */
4783 HOST_WIDE_INT max_address;
4784 {
4785 /* This should never be true and the code below assumes these are
4786 different. */
4791 {
4794 }
4795 else
4796 {
4799 else
4802 /* Unlink MP from its current position. Since max_mp is non-null,
4803 mp->prev must be non-null. */
4807 else
4810 /* Re-insert it before MAX_MP. */
4817 else
4819 }
4821 /* Save the new entry. */
4824 /* Scan over the preceeding entries and adjust their addresses as
4825 required. */
4828 {
4831 }
4834 }
4836 /* Add a constant to the minipool for a forward reference. Returns the
4837 node added or NULL if the constant will not fit in this pool. */
4841 {
4842 /* If set, max_mp is the first pool_entry that has a lower
4843 constraint than the one we are trying to add. */
4848 /* If this fix's address is greater than the address of the first
4849 entry, then we can't put the fix in this pool. We subtract the
4850 size of the current fix to ensure that if the table is fully
4851 packed we still have enough room to insert this value by suffling
4852 the other fixes forwards. */
4857 /* Scan the pool to see if a constant with the same value has
4858 already been added. While we are doing this, also note the
4859 location where we must insert the constant if it doesn't already
4860 exist. */
4862 {
4869 {
4870 /* More than one fix references this entry. */
4873 }
4875 /* Note the insertion point if necessary. */
4879 }
4881 /* The value is not currently in the minipool, so we need to create
4882 a new entry for it. If MAX_MP is NULL, the entry will be put on
4883 the end of the list since the placement is less constrained than
4884 any existing entry. Otherwise, we insert the new fix before
4885 MAX_MP and, if neceesary, adjust the constraints on the other
4886 entries. */
4892 /* Not yet required for a backwards ref. */
4896 {
4902 {
4905 }
4906 else
4910 }
4911 else
4912 {
4915 else
4923 else
4925 }
4927 /* Save the new entry. */
4930 /* Scan over the preceeding entries and adjust their addresses as
4931 required. */
4934 {
4937 }
4940 }
4946 HOST_WIDE_INT min_address;
4947 {
4948 HOST_WIDE_INT offset;
4950 /* This should never be true, and the code below assumes these are
4951 different. */
4956 {
4959 }
4960 else
4961 {
4962 /* We will adjust this below if it is too loose. */
4965 /* Unlink MP from its current position. Since min_mp is non-null,
4966 mp->next must be non-null. */
4970 else
4973 /* Reinsert it after MIN_MP. */
4979 else
4981 }
4987 {
4994 }
4997 }
4999 /* Add a constant to the minipool for a backward reference. Returns the
5000 node added or NULL if the constant will not fit in this pool.
5002 Note that the code for insertion for a backwards reference can be
5003 somewhat confusing because the calculated offsets for each fix do
5004 not take into account the size of the pool (which is still under
5005 construction. */
5009 {
5010 /* If set, min_mp is the last pool_entry that has a lower constraint
5011 than the one we are trying to add. */
5013 /* This can be negative, since it is only a constraint. */
5017 /* If we can't reach the current pool from this insn, or if we can't
5018 insert this entry at the end of the pool without pushing other
5019 fixes out of range, then we don't try. This ensures that we
5020 can't fail later on. */
5026 /* Scan the pool to see if a constant with the same value has
5027 already been added. While we are doing this, also note the
5028 location where we must insert the constant if it doesn't already
5029 exist. */
5031 {
5038 /* Check that there is enough slack to move this entry to the
5039 end of the table (this is conservative). */
5044 {
5047 }
5051 else
5052 {
5053 /* Note the insertion point if necessary. */
5058 {
5059 /* Inserting before this entry would push the fix beyond
5060 its maximum address (which can happen if we have
5061 re-located a forwards fix); force the new fix to come
5062 after it. */
5065 }
5066 }
5067 }
5069 /* We need to create a new entry. */
5080 {
5085 {
5088 }
5089 else
5093 }
5094 else
5095 {
5102 else
5104 }
5106 /* Save the new entry. */
5111 else
5114 /* Scan over the following entries and adjust their offsets. */
5116 {
5122 else
5126 }
5129 }
5131 static void
5134 {
5141 {
5146 }
5147 }
5149 /* Output the literal table */
5150 static void
5152 rtx scan;
5153 {
5167 {
5169 {
5171 {
5178 }
5181 {
5182 #ifdef HAVE_consttable_1
5187 #endif
5188 #ifdef HAVE_consttable_2
5193 #endif
5194 #ifdef HAVE_consttable_4
5199 #endif
5200 #ifdef HAVE_consttable_8
5205 #endif
5209 }
5210 }
5214 }
5219 }
5221 /* Return the cost of forcibly inserting a barrier after INSN. */
5222 static int
5224 rtx insn;
5225 {
5226 /* Basing the location of the pool on the loop depth is preferable,
5227 but at the moment, the basic block information seems to be
5228 corrupt by this stage of the compilation. */
5236 {
5238 /* It will always be better to place the table before the label, rather
5239 than after it. */
5251 }
5252 }
5254 /* Find the best place in the insn stream in the range
5255 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5256 Create the barrier by inserting a jump and add a new fix entry for
5257 it. */
5261 HOST_WIDE_INT max_address;
5262 {
5264 rtx barrier;
5268 HOST_WIDE_INT selected_address;
5277 {
5278 rtx tmp;
5281 /* This code shouldn't have been called if there was a natural barrier
5282 within range. */
5286 /* Count the length of this insn. */
5289 /* If there is a jump table, add its length. */
5292 {
5295 /* Jump tables aren't in a basic block, so base the cost on
5296 the dispatch insn. If we select this location, we will
5297 still put the pool after the table. */
5301 {
5305 }
5307 /* Continue after the dispatch table. */
5310 }
5315 {
5319 }
5322 }
5324 /* Create a new JUMP_INSN that branches around a barrier. */
5330 /* Create a minipool barrier entry for the new barrier. */
5338 }
5340 /* Record that there is a natural barrier in the insn stream at
5341 ADDRESS. */
5342 static void
5344 rtx insn;
5345 HOST_WIDE_INT address;
5346 {
5355 else
5359 }
5361 /* Record INSN, which will need fixing up to load a value from the
5362 minipool. ADDRESS is the offset of the insn since the start of the
5363 function; LOC is a pointer to the part of the insn which requires
5364 fixing; VALUE is the constant that must be loaded, which is of type
5365 MODE. */
5366 static void
5368 rtx insn;
5369 HOST_WIDE_INT address;
5372 rtx value;
5373 {
5376 #ifdef AOF_ASSEMBLER
5377 /* PIC symbol refereneces need to be converted into offsets into the
5378 based area. */
5379 /* XXX This shouldn't be done here. */
5394 /* If an insn doesn't have a range defined for it, then it isn't
5395 expecting to be reworked by this code. Better to abort now than
5396 to generate duff assembly code. */
5401 {
5409 }
5411 /* Add it to the chain of fixes. */
5416 else
5420 }
5422 /* Scan INSN and note any of its operands that need fixing. */
5423 static void
5425 rtx insn;
5426 HOST_WIDE_INT address;
5427 {
5435 /* Fill in recog_op_alt with information about the constraints of this
5436 insn. */
5440 {
5441 /* Things we need to fix can only occur in inputs. */
5445 /* If this alternative is a memory reference, then any mention
5446 of constants in this alternative is really to fool reload
5447 into allowing us to accept one there. We need to fix them up
5448 now so that we output the right code. */
5450 {
5456 #if 0
5457 /* RWE: Now we look correctly at the operands for the insn,
5458 this shouldn't be needed any more. */
5459 #ifndef AOF_ASSEMBLER
5460 /* XXX Is this still needed? */
5465 #endif
5466 #endif
5473 }
5474 }
5475 }
5477 void
5479 rtx first;
5480 {
5481 rtx insn;
5487 /* The first insn must always be a note, or the code below won't
5488 scan it properly. */
5492 /* Scan all the insns and record the operands that will need fixing. */
5494 {
5500 {
5501 rtx table;
5506 /* If the insn is a vector jump, add the size of the table
5507 and skip the table. */
5509 {
5512 }
5513 }
5514 }
5518 /* Now scan the fixups and perform the required changes. */
5520 {
5527 /* Skip any further barriers before the next fix. */
5531 /* No more fixes. */
5538 {
5540 {
5545 }
5550 }
5552 /* If we found a barrier, drop back to that; any fixes that we
5553 could have reached but come after the barrier will now go in
5554 the next mini-pool. */
5556 {
5557 /* Reduce the refcount for those fixes that won't go into this
5558 pool after all. */
5562 {
5565 }
5568 }
5569 else
5570 {
5571 /* ftmp is first fix that we can't fit into this pool and
5572 there no natural barriers that we could use. Insert a
5573 new barrier in the code somewhere between the previous
5574 fix and this one, and arrange to jump around it. */
5575 HOST_WIDE_INT max_address;
5577 /* The last item on the list of fixes must be a barrier, so
5578 we can never run off the end of the list of fixes without
5579 last_barrier being set. */
5584 /* Check that there isn't another fix that is in range that
5585 we couldn't fit into this pool because the pool was
5586 already too large: we need to put the pool before such an
5587 instruction. */
5592 }
5597 {
5604 }
5606 /* Scan over the fixes we have identified for this pool, fixing them
5607 up and adding the constants to the pool itself. */
5611 {
5612 rtx addr
5614 minipool_vector_label),
5617 }
5621 }
5623 /* From now on we must synthesize any constants that we can't handle
5624 directly. This can happen if the RTL gets split during final
5625 instruction generation. */
5627 }
5628 \f
5629 /* Routines to output assembly language. */
5631 /* If the rtx is the correct value then return the string of the number.
5632 In this way we can ensure that valid double constants are generated even
5633 when cross compiling. */
5636 rtx x;
5637 {
5638 REAL_VALUE_TYPE r;
5650 }
5652 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
5656 {
5667 }
5669 /* Output the operands of a LDM/STM instruction to STREAM.
5670 MASK is the ARM register set mask of which only bits 0-15 are important.
5671 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
5672 must follow the register list. */
5674 static void
5681 {
5691 {
5697 }
5700 }
5702 /* Output a 'call' insn. */
5707 {
5708 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
5711 {
5714 }
5720 else
5724 }
5726 static int
5729 {
5737 {
5740 {
5743 }
5746 /* Scan through the sub-elements and change any references there. */
5757 }
5758 }
5760 /* Output a 'call' insn that is a reference in memory. */
5765 {
5767 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
5772 {
5776 }
5777 else
5778 {
5781 }
5784 }
5787 /* Output a move from arm registers to an fpu registers.
5788 OPERANDS[0] is an fpu register.
5789 OPERANDS[1] is the first registers of an arm register pair. */
5794 {
5809 }
5811 /* Output a move from an fpu register to arm registers.
5812 OPERANDS[0] is the first registers of an arm register pair.
5813 OPERANDS[1] is an fpu register. */
5818 {
5832 }
5834 /* Output a move from arm registers to arm registers of a long double
5835 OPERANDS[0] is the destination.
5836 OPERANDS[1] is the source. */
5840 {
5841 /* We have to be careful here because the two might overlap. */
5848 {
5850 {
5854 }
5855 }
5856 else
5857 {
5859 {
5863 }
5864 }
5867 }
5870 /* Output a move from arm registers to an fpu registers.
5871 OPERANDS[0] is an fpu register.
5872 OPERANDS[1] is the first registers of an arm register pair. */
5877 {
5889 }
5891 /* Output a move from an fpu register to arm registers.
5892 OPERANDS[0] is the first registers of an arm register pair.
5893 OPERANDS[1] is an fpu register. */
5898 {
5910 }
5912 /* Output a move between double words.
5913 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
5914 or MEM<-REG and all MEMs must be offsettable addresses. */
5919 {
5925 {
5931 {
5936 /* Ensure the second source is not overwritten. */
5939 else
5941 }
5943 {
5945 {
5954 }
5958 {
5962 }
5963 else
5964 {
5968 }
5972 }
5974 {
5975 #if HOST_BITS_PER_WIDE_INT > 32
5976 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5977 what the upper word is. */
5979 {
5982 }
5983 else
5984 {
5987 }
5988 #else
5989 /* Sign extend the intval into the high-order word. */
5991 {
5995 }
5996 else
5998 #endif
6001 }
6003 {
6005 {
6035 {
6040 {
6042 {
6044 {
6054 }
6057 else
6059 }
6060 else
6062 }
6063 else
6067 }
6068 else
6069 {
6071 /* Take care of overlapping base/data reg. */
6073 {
6076 }
6077 else
6078 {
6081 }
6082 }
6083 }
6084 }
6085 else
6087 }
6089 {
6094 {
6117 {
6119 {
6131 }
6132 }
6133 /* Fall through */
6140 }
6141 }
6142 else
6146 }
6149 /* Output an arbitrary MOV reg, #n.
6150 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6155 {
6160 /* Try to use one MOV */
6162 {
6165 }
6167 /* Try to use one MVN */
6169 {
6173 }
6175 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6179 n_ones++;
6184 else
6188 }
6191 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6192 adding zero to one register, output nothing. */
6197 {
6201 {
6206 else
6209 n);
6210 }
6213 }
6215 /* Output a multiple immediate operation.
6216 OPERANDS is the vector of operands referred to in the output patterns.
6217 INSTR1 is the output pattern to use for the first constant.
6218 INSTR2 is the output pattern to use for subsequent constants.
6219 IMMED_OP is the index of the constant slot in OPERANDS.
6220 N is the constant value. */
6227 HOST_WIDE_INT n;
6228 {
6229 #if HOST_BITS_PER_WIDE_INT > 32
6231 #endif
6234 {
6237 }
6238 else
6239 {
6243 /* Note that n is never zero here (which would give no output). */
6245 {
6247 {
6252 }
6253 }
6254 }
6256 }
6259 /* Return the appropriate ARM instruction for the operation code.
6260 The returned result should not be overwritten. OP is the rtx of the
6261 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6262 was shifted. */
6266 rtx op;
6268 {
6270 {
6288 }
6289 }
6292 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6293 for the operation code. The returned result should not be overwritten.
6294 OP is the rtx code of the shift.
6295 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6296 shift. */
6300 rtx op;
6302 {
6310 else
6314 {
6332 /* We never have to worry about the amount being other than a
6333 power of 2, since this case can never be reloaded from a reg. */
6336 else
6342 }
6345 {
6346 /* This is not 100% correct, but follows from the desire to merge
6347 multiplication by a power of 2 with the recognizer for a
6348 shift. >=32 is not a valid shift for "asl", so we must try and
6349 output a shift that produces the correct arithmetical result.
6350 Using lsr #32 is identical except for the fact that the carry bit
6351 is not set correctly if we set the flags; but we never use the
6352 carry bit from such an operation, so we can ignore that. */
6356 {
6360 }
6362 /* Shifts of 0 are no-ops. */
6365 }
6368 }
6371 /* Obtain the shift from the POWER of two. */
6372 static HOST_WIDE_INT
6374 HOST_WIDE_INT power;
6375 {
6379 {
6382 shift++;
6383 }
6386 }
6388 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6389 /bin/as is horribly restrictive. */
6390 #define MAX_ASCII_LEN 51
6392 void
6397 {
6404 {
6408 {
6411 }
6414 {
6440 /* This is a good place for a line break. */
6442 else
6449 len_so_far ++;
6450 /* drop through. */
6454 {
6456 len_so_far ++;
6457 }
6458 else
6459 {
6462 }
6464 }
6465 }
6468 }
6469 \f
6471 /* Try to determine whether a pattern really clobbers the link register.
6472 This information is useful when peepholing, so that lr need not be pushed
6473 if we combine a call followed by a return.
6474 NOTE: This code does not check for side-effect expressions in a SET_SRC:
6475 such a check should not be needed because these only update an existing
6476 value within a register; the register must still be set elsewhere within
6477 the function. */
6478 static int
6480 rtx x;
6481 {
6485 {
6488 {
6502 }
6512 {
6523 }
6530 }
6531 }
6533 static int
6535 rtx first;
6536 {
6540 {
6542 {
6555 /* Don't yet know how to handle those calls that are not to a
6556 SYMBOL_REF. */
6561 {
6577 }
6579 /* A call can be made (by peepholing) not to clobber lr iff it is
6580 followed by a return. There may, however, be a use insn iff
6581 we are returning the result of the call.
6582 If we run off the end of the insn chain, then that means the
6583 call was at the end of the function. Unfortunately we don't
6584 have a return insn for the peephole to recognize, so we
6585 must reject this. (Can this be fixed by adding our own insn?) */
6589 /* No need to worry about lr if the call never returns. */
6609 }
6610 }
6612 /* We have reached the end of the chain so lr was _not_ clobbered. */
6614 }
6618 rtx operand;
6621 {
6626 /* If a function is naked, don't use the "return" insn. */
6633 {
6634 /* If this function was declared non-returning, and we have found a tail
6635 call, then we have to trust that the called function won't return. */
6637 {
6640 /* Otherwise, trap an attempted return by aborting. */
6646 }
6649 }
6656 live_regs++;
6659 && ! frame_pointer_needed
6662 live_regs++;
6666 live_regs++;
6669 live_regs++;
6674 /* On some ARM architectures it is faster to use LDR rather than LDM to
6675 load a single register. On other architectures, the cost is the same. */
6678 && ! lr_save_eliminated
6679 /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
6680 really_return is true, and only the PC needs restoring. */
6686 && ! lr_save_eliminated
6691 {
6693 live_regs++;
6698 else
6707 {
6712 }
6715 {
6725 }
6726 else
6727 {
6731 {
6735 }
6741 else
6743 }
6749 {
6756 }
6757 }
6759 {
6762 else
6767 }
6770 }
6772 /* Return nonzero if optimizing and the current function is volatile.
6773 Such functions never return, and many memory cycles can be saved
6774 by not storing register values that will never be needed again.
6775 This optimization was added to speed up context switching in a
6776 kernel application. */
6777 int
6779 {
6781 && current_function_nothrow
6783 }
6785 /* Write the function name into the code section, directly preceding
6786 the function prologue.
6788 Code will be output similar to this:
6789 t0
6790 .ascii "arm_poke_function_name", 0
6791 .align
6792 t1
6793 .word 0xff000000 + (t1 - t0)
6794 arm_poke_function_name
6795 mov ip, sp
6796 stmfd sp!, {fp, ip, lr, pc}
6797 sub fp, ip, #4
6799 When performing a stack backtrace, code can inspect the value
6800 of 'pc' stored at 'fp' + 0. If the trace function then looks
6801 at location pc - 12 and the top 8 bits are set, then we know
6802 that there is a function name embedded immediately preceding this
6803 location and has length ((pc[-3]) & 0xff000000).
6805 We assume that pc is declared as a pointer to an unsigned long.
6807 It is of no benefit to output the function name if we are assembling
6808 a leaf function. These function types will not contain a stack
6809 backtrace structure, therefore it is not possible to determine the
6810 function name. */
6812 void
6816 {
6819 rtx x;
6828 }
6830 /* The amount of stack adjustment that happens here, in output_return and in
6831 output_epilogue must be exactly the same as was calculated during reload,
6832 or things will point to the wrong place. The only time we can safely
6833 ignore this constraint is when a function has no arguments on the stack,
6834 no stack frame requirement and no live registers execpt for `lr'. If we
6835 can guarantee that by making all function calls into tail calls and that
6836 lr is not clobbered in any other way, then there is no need to push lr
6837 onto the stack. */
6838 void
6842 {
6846 /* Nonzero if we must stuff some register arguments onto the stack as if
6847 they were passed there. */
6860 current_function_args_size,
6863 frame_pointer_needed,
6864 current_function_anonymous_args);
6877 && ! frame_pointer_needed
6889 {
6893 else
6895 }
6898 {
6899 /* If a di mode load/store multiple is used, and the base register
6900 is r3, then r4 can become an ever live register without lr
6901 doing so, in this case we need to push lr as well, or we
6902 will fail to get a proper return. */
6906 }
6911 #ifdef AOF_ASSEMBLER
6914 #endif
6915 }
6919 {
6922 /* If we need this, then it will always be at least this much. */
6935 /* Naked functions don't have epilogues. */
6939 /* If we are throwing an exception, the address we want to jump to is in
6940 R1; otherwise, it's in LR. */
6943 /* A volatile function should never return. Call abort. */
6945 {
6946 rtx op;
6951 }
6955 {
6958 }
6960 /* Handle the frame pointer as a special case. */
6962 && ! frame_pointer_needed
6965 {
6968 }
6970 /* If we aren't loading the PIC register, don't stack it even though it may
6971 be live. */
6974 {
6977 }
6980 {
6982 {
6985 {
6989 }
6990 }
6991 else
6992 {
6996 {
6998 {
7001 /* We can't unstack more than four registers at once. */
7003 {
7007 }
7008 }
7009 else
7010 {
7016 }
7017 }
7019 /* Just in case the last register checked also needs unstacking. */
7024 }
7027 {
7034 }
7036 {
7041 /* Even in 26-bit mode we do a mov (rather than a movs) because
7042 we don't have the PSR bits set in the address. */
7044 }
7045 else
7046 {
7050 }
7051 }
7052 else
7053 {
7054 /* Restore stack pointer if necessary. */
7056 {
7061 }
7064 {
7069 }
7070 else
7071 {
7075 {
7077 {
7079 {
7083 }
7084 }
7085 else
7086 {
7090 SP_REGNUM);
7093 }
7094 }
7096 /* Just in case the last register checked also needs unstacking. */
7100 }
7103 {
7105 {
7109 /* Handle LR on its own. */
7111 {
7114 SP_REGNUM);
7115 else
7117 SP_REGNUM);
7118 }
7121 FALSE);
7128 }
7134 {
7137 else
7143 /* Jump to the target; even in 26-bit mode. */
7145 }
7148 else
7152 }
7153 else
7154 {
7156 {
7157 /* Restore the integer regs, and the return address into lr. */
7162 {
7165 SP_REGNUM);
7166 else
7168 SP_REGNUM);
7169 }
7172 FALSE);
7173 }
7176 {
7177 /* Unwind the pre-pushed regs. */
7181 }
7187 /* And finally, go home. */
7192 else
7194 }
7195 }
7198 }
7200 void
7203 {
7205 {
7206 /* ??? Probably not safe to set this here, since it assumes that a
7207 function will be emitted as assembly immediately after we generate
7208 RTL for it. This does not happen for inline functions. */
7210 }
7211 else
7212 {
7214 && return_used_this_function
7219 /* Reset the ARM-specific per-function variables. */
7222 }
7223 }
7225 /* Generate and emit an insn that we will recognize as a push_multi.
7226 Unfortunately, since this insn does not reflect very well the actual
7227 semantics of the operation, we need to annotate the insn for the benefit
7228 of DWARF2 frame unwind information. */
7229 static rtx
7232 {
7235 rtx par;
7236 rtx dwarf;
7241 num_regs ++;
7251 {
7253 {
7260 stack_pointer_rtx)),
7268 stack_pointer_rtx)),
7269 reg);
7274 }
7275 }
7278 {
7280 {
7288 stack_pointer_rtx)),
7289 reg);
7293 j++;
7294 }
7295 }
7301 }
7303 static rtx
7307 {
7308 rtx par;
7309 rtx dwarf;
7326 tmp
7330 reg);
7335 {
7342 stack_pointer_rtx)),
7343 reg);
7346 }
7352 }
7354 void
7356 {
7362 /* If this function doesn't return, then there is no need to push
7363 the call-saved regs. */
7365 rtx insn;
7367 /* Naked functions don't have prologues. */
7375 {
7381 && ! frame_pointer_needed
7391 }
7394 {
7397 stack_pointer_rtx));
7399 }
7402 {
7404 insn = emit_multi_reg_push
7406 else
7407 insn = emit_insn
7411 }
7414 {
7415 /* If we have to push any regs, then we must push lr as well, or
7416 we won't get a proper return. */
7420 }
7422 /* For now the integer regs are still pushed in output_arm_epilogue (). */
7425 {
7427 {
7430 {
7436 }
7437 }
7438 else
7439 {
7443 {
7445 {
7447 {
7451 }
7452 }
7453 else
7454 {
7456 {
7459 }
7461 }
7462 }
7465 {
7468 }
7469 }
7470 }
7473 {
7477 insn));
7479 }
7482 {
7484 amount));
7488 }
7490 /* If we are profiling, make sure no instructions are scheduled before
7491 the call to mcount. Similarly if the user has requested no
7492 scheduling in the prolog. */
7495 }
7497 \f
7498 /* If CODE is 'd', then the X is a condition operand and the instruction
7499 should only be executed if the condition is true.
7500 if CODE is 'D', then the X is a condition operand and the instruction
7501 should only be executed if the condition is false: however, if the mode
7502 of the comparison is CCFPEmode, then always execute the instruction -- we
7503 do this because in these circumstances !GE does not necessarily imply LT;
7504 in these cases the instruction pattern will take care to make sure that
7505 an instruction containing %d will follow, thereby undoing the effects of
7506 doing this instruction unconditionally.
7507 If CODE is 'N' then X is a floating point operand that must be negated
7508 before output.
7509 If CODE is 'B' then output a bitwise inverted value of X (a const int).
7510 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
7512 void
7515 rtx x;
7517 {
7519 {
7538 {
7539 REAL_VALUE_TYPE r;
7543 }
7548 {
7549 HOST_WIDE_INT val;
7552 }
7553 else
7554 {
7557 }
7569 {
7570 HOST_WIDE_INT val;
7574 {
7578 else
7579 {
7582 }
7583 }
7584 }
7587 /* An explanation of the 'Q', 'R' and 'H' register operands:
7589 In a pair of registers containing a DI or DF value the 'Q'
7590 operand returns the register number of the register containing
7591 the least signficant part of the value. The 'R' operand returns
7592 the register number of the register containing the most
7593 significant part of the value.
7595 The 'H' operand returns the higher of the two register numbers.
7596 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
7597 same as the 'Q' operand, since the most signficant part of the
7598 value is held in the lower number register. The reverse is true
7599 on systems where WORDS_BIG_ENDIAN is false.
7601 The purpose of these operands is to distinguish between cases
7602 where the endian-ness of the values is important (for example
7603 when they are added together), and cases where the endian-ness
7604 is irrelevant, but the order of register operations is important.
7605 For example when loading a value from memory into a register
7606 pair, the endian-ness does not matter. Provided that the value
7607 from the lower memory address is put into the lower numbered
7608 register, and the value from the higher address is put into the
7609 higher numbered register, the load will work regardless of whether
7610 the value being loaded is big-wordian or little-wordian. The
7611 order of the two register loads can matter however, if the address
7612 of the memory location is actually held in one of the registers
7613 being overwritten by the load. */
7650 stream);
7651 else
7662 stream);
7663 else
7674 {
7677 }
7682 else
7683 {
7686 }
7687 }
7688 }
7689 \f
7690 /* A finite state machine takes care of noticing whether or not instructions
7691 can be conditionally executed, and thus decrease execution time and code
7692 size by deleting branch instructions. The fsm is controlled by
7693 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
7695 /* The state of the fsm controlling condition codes are:
7696 0: normal, do nothing special
7697 1: make ASM_OUTPUT_OPCODE not output this instruction
7698 2: make ASM_OUTPUT_OPCODE not output this instruction
7699 3: make instructions conditional
7700 4: make instructions conditional
7702 State transitions (state->state by whom under condition):
7703 0 -> 1 final_prescan_insn if the `target' is a label
7704 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
7705 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
7706 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
7707 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
7708 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
7709 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
7710 (the target insn is arm_target_insn).
7712 If the jump clobbers the conditions then we use states 2 and 4.
7714 A similar thing can be done with conditional return insns.
7716 XXX In case the `target' is an unconditional branch, this conditionalising
7717 of the instructions always reduces code size, but not always execution
7718 time. But then, I want to reduce the code size to somewhere near what
7719 /bin/cc produces. */
7721 /* Returns the index of the ARM condition code string in
7722 `arm_condition_codes'. COMPARISON should be an rtx like
7723 `(eq (...) (...))'. */
7725 static enum arm_cond_code
7727 rtx comparison;
7728 {
7738 {
7750 dominance:
7760 {
7766 }
7771 {
7775 }
7779 {
7785 }
7789 {
7801 }
7805 {
7809 }
7813 {
7825 }
7828 }
7831 }
7834 void
7836 rtx insn;
7837 {
7838 /* BODY will hold the body of INSN. */
7841 /* This will be 1 if trying to repeat the trick, and things need to be
7842 reversed if it appears to fail. */
7845 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
7846 taken are clobbered, even if the rtl suggests otherwise. It also
7847 means that we have to grub around within the jump expression to find
7848 out what the conditions are when the jump isn't taken. */
7851 /* If we start with a return insn, we only succeed if we find another one. */
7854 /* START_INSN will hold the insn from where we start looking. This is the
7855 first insn after the following code_label if REVERSE is true. */
7858 /* If in state 4, check if the target branch is reached, in order to
7859 change back to state 0. */
7861 {
7863 {
7866 }
7868 }
7870 /* If in state 3, it is possible to repeat the trick, if this insn is an
7871 unconditional branch to a label, and immediately following this branch
7872 is the previous target label which is only used once, and the label this
7873 branch jumps to is not too far off. */
7875 {
7877 {
7880 {
7881 /* XXX Isn't this always a barrier? */
7883 }
7888 else
7890 }
7892 {
7899 {
7902 }
7903 else
7905 }
7906 else
7908 }
7915 /* This jump might be paralleled with a clobber of the condition codes
7916 the jump should always come first */
7920 #if 0
7921 /* If this is a conditional return then we don't want to know */
7927 #endif
7932 {
7935 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
7940 {
7941 /* The code below is wrong for these, and I haven't time to
7942 fix it now. So we just do the safe thing and return. This
7943 whole function needs re-writing anyway. */
7946 }
7948 /* Register the insn jumped to. */
7950 {
7953 }
7957 {
7960 }
7964 {
7967 }
7968 else
7971 /* See how many insns this branch skips, and what kind of insns. If all
7972 insns are okay, and the label or unconditional branch to the same
7973 label is not too far away, succeed. */
7976 {
7977 rtx scanbody;
7984 {
7986 /* Succeed if it is the target label, otherwise fail since
7987 control falls in from somewhere else. */
7989 {
7991 {
7994 }
7995 else
7998 }
7999 else
8004 /* Succeed if the following insn is the target label.
8005 Otherwise fail.
8006 If return insns are used then the last insn in a function
8007 will be a barrier. */
8010 {
8012 {
8015 }
8016 else
8019 }
8020 else
8025 /* If using 32-bit addresses the cc is not preserved over
8026 calls. */
8028 {
8029 /* Succeed if the following insn is the target label,
8030 or if the following two insns are a barrier and
8031 the target label. */
8038 {
8040 {
8043 }
8044 else
8047 }
8048 else
8050 }
8054 /* If this is an unconditional branch to the same label, succeed.
8055 If it is to another label, do nothing. If it is conditional,
8056 fail. */
8057 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8062 {
8065 {
8068 }
8071 }
8072 /* Fail if a conditional return is undesirable (eg on a
8073 StrongARM), but still allow this if optimizing for size. */
8080 {
8083 }
8085 {
8087 {
8093 }
8094 }
8098 /* Instructions using or affecting the condition codes make it
8099 fail. */
8109 }
8110 }
8112 {
8116 {
8118 {
8123 }
8125 {
8126 /* Oh, dear! we ran off the end.. give up */
8131 }
8133 }
8134 else
8137 {
8140 arm_current_cc =
8147 }
8148 else
8149 {
8150 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8151 what it was. */
8155 }
8159 }
8161 /* Restore recog_data (getting the attributes of other insns can
8162 destroy this array, but final.c assumes that it remains intact
8163 across this call; since the insn has been recognized already we
8164 call recog direct). */
8166 }
8167 }
8169 int
8172 {
8174 {
8182 }
8193 }
8195 /* Handle a special case when computing the offset
8196 of an argument from the frame pointer. */
8197 int
8200 rtx addr;
8201 {
8202 rtx insn;
8204 /* We are only interested if dbxout_parms() failed to compute the offset. */
8208 /* We can only cope with the case where the address is held in a register. */
8212 /* If we are using the frame pointer to point at the argument, then
8213 an offset of 0 is correct. */
8217 /* If we are using the stack pointer to point at the
8218 argument, then an offset of 0 is correct. */
8223 /* Oh dear. The argument is pointed to by a register rather
8224 than being held in a register, or being stored at a known
8225 offset from the frame pointer. Since GDB only understands
8226 those two kinds of argument we must translate the address
8227 held in the register into an offset from the frame pointer.
8228 We do this by searching through the insns for the function
8229 looking to see where this register gets its value. If the
8230 register is initialised from the frame pointer plus an offset
8231 then we are in luck and we can continue, otherwise we give up.
8233 This code is exercised by producing debugging information
8234 for a function with arguments like this:
8236 double func (double a, double b, int c, double d) {return d;}
8238 Without this code the stab for parameter 'd' will be set to
8239 an offset of 0 from the frame pointer, rather than 8. */
8241 /* The if() statement says:
8243 If the insn is a normal instruction
8244 and if the insn is setting the value in a register
8245 and if the register being set is the register holding the address of the argument
8246 and if the address is computing by an addition
8247 that involves adding to a register
8248 which is the frame pointer
8249 a constant integer
8251 then... */
8254 {
8262 )
8263 {
8267 }
8268 }
8271 {
8275 }
8278 }
8280 \f
8281 /* Recursively search through all of the blocks in a function
8282 checking to see if any of the variables created in that
8283 function match the RTX called 'orig'. If they do then
8284 replace them with the RTX called 'new'. */
8286 static void
8288 tree block;
8289 rtx orig;
8291 {
8293 {
8294 tree sym;
8300 {
8306 )
8310 }
8313 }
8314 }
8316 /* Return the number (counting from 0) of the least significant set
8317 bit in MASK. */
8318 #ifdef __GNUC__
8319 inline
8320 #endif
8321 static int
8324 {
8333 }
8335 /* Generate code to return from a thumb function.
8336 If 'reg_containing_return_addr' is -1, then the return address is
8337 actually on the stack, at the stack pointer. */
8338 static void
8342 rtx eh_ofs;
8343 {
8353 /* Compute the registers we need to pop. */
8357 /* There is an assumption here, that if eh_ofs is not NULL, the
8358 normal return address will have been pushed. */
8360 {
8361 /* When we are generating a return for __builtin_eh_return,
8362 reg_containing_return_addr must specify the return regno. */
8368 }
8371 {
8372 /* Restore the (ARM) frame pointer and stack pointer. */
8375 }
8377 /* If there is nothing to pop then just emit the BX instruction and
8378 return. */
8380 {
8386 }
8387 /* Otherwise if we are not supporting interworking and we have not created
8388 a backtrace structure and the function was not entered in ARM mode then
8389 just pop the return address straight into the PC. */
8391 && ! TARGET_BACKTRACE
8393 {
8395 {
8399 }
8400 else
8404 }
8406 /* Find out how many of the (return) argument registers we can corrupt. */
8409 /* If returning via __builtin_eh_return, the bottom three registers
8410 all contain information needed for the return. */
8413 else
8414 {
8415 #ifdef RTX_CODE
8416 /* If we can deduce the registers used from the function's
8417 return value. This is more reliable that examining
8418 regs_ever_live[] because that will be set if the register is
8419 ever used in the function, not just if the register is used
8420 to hold a return value. */
8424 else
8425 #endif
8431 {
8432 /* In a void function we can use any argument register.
8433 In a function that returns a structure on the stack
8434 we can use the second and third argument registers. */
8436 regs_available_for_popping =
8440 else
8441 regs_available_for_popping =
8444 }
8446 regs_available_for_popping =
8450 regs_available_for_popping =
8452 }
8454 /* Match registers to be popped with registers into which we pop them. */
8462 /* If we have any popping registers left over, remove them. */
8466 /* Otherwise if we need another popping register we can use
8467 the fourth argument register. */
8469 {
8470 /* If we have not found any free argument registers and
8471 reg a4 contains the return address, we must move it. */
8474 {
8477 }
8479 {
8480 /* Register a4 is being used to hold part of the return value,
8481 but we have dire need of a free, low register. */
8485 }
8488 {
8489 /* The fourth argument register is available. */
8493 }
8494 }
8496 /* Pop as many registers as we can. */
8499 /* Process the registers we popped. */
8501 {
8502 /* The return address was popped into the lowest numbered register. */
8505 reg_containing_return_addr =
8508 /* Remove this register for the mask of available registers, so that
8509 the return address will not be corrupted by futher pops. */
8511 }
8513 /* If we popped other registers then handle them here. */
8515 {
8518 /* Work out which register currently contains the frame pointer. */
8521 /* Move it into the correct place. */
8525 /* (Temporarily) remove it from the mask of popped registers. */
8530 {
8533 /* We popped the stack pointer as well,
8534 find the register that contains it. */
8537 /* Move it into the stack register. */
8540 /* At this point we have popped all necessary registers, so
8541 do not worry about restoring regs_available_for_popping
8542 to its correct value:
8544 assert (pops_needed == 0)
8545 assert (regs_available_for_popping == (1 << frame_pointer))
8546 assert (regs_to_pop == (1 << STACK_POINTER)) */
8547 }
8548 else
8549 {
8550 /* Since we have just move the popped value into the frame
8551 pointer, the popping register is available for reuse, and
8552 we know that we still have the stack pointer left to pop. */
8554 }
8555 }
8557 /* If we still have registers left on the stack, but we no longer have
8558 any registers into which we can pop them, then we must move the return
8559 address into the link register and make available the register that
8560 contained it. */
8562 {
8566 reg_containing_return_addr);
8569 }
8571 /* If we have registers left on the stack then pop some more.
8572 We know that at most we will want to pop FP and SP. */
8574 {
8580 /* We have popped either FP or SP.
8581 Move whichever one it is into the correct register. */
8590 }
8592 /* If we still have not popped everything then we must have only
8593 had one register available to us and we are now popping the SP. */
8595 {
8603 /*
8604 assert (regs_to_pop == (1 << STACK_POINTER))
8605 assert (pops_needed == 1)
8606 */
8607 }
8609 /* If necessary restore the a4 register. */
8611 {
8613 {
8616 }
8619 }
8624 /* Return to caller. */
8626 }
8628 /* Emit code to push or pop registers to or from the stack. */
8629 static void
8634 {
8639 {
8640 /* Special case. Do not generate a POP PC statement here, do it in
8641 thumb_exit() */
8644 }
8648 /* Look at the low registers first. */
8650 {
8652 {
8657 }
8658 }
8661 {
8662 /* Catch pushing the LR. */
8667 }
8669 {
8670 /* Catch popping the PC. */
8672 {
8673 /* The PC is never poped directly, instead
8674 it is popped into r3 and then BX is used. */
8680 }
8681 else
8682 {
8687 }
8688 }
8691 }
8692 \f
8693 void
8695 rtx insn;
8696 {
8701 }
8703 int
8706 {
8718 }
8720 /* Returns non-zero if the current function contains,
8721 or might contain a far jump. */
8722 int
8724 {
8725 rtx insn;
8727 /* This test is only important for leaf functions. */
8728 /* assert (! leaf_function_p ()); */
8730 /* If we have already decided that far jumps may be used,
8731 do not bother checking again, and always return true even if
8732 it turns out that they are not being used. Once we have made
8733 the decision that far jumps are present (and that hence the link
8734 register will be pushed onto the stack) we cannot go back on it. */
8738 /* If this function is not being called from the prologue/epilogue
8739 generation code then it must be being called from the
8740 INITIAL_ELIMINATION_OFFSET macro. */
8742 {
8743 /* In this case we know that we are being asked about the elimination
8744 of the arg pointer register. If that register is not being used,
8745 then there are no arguments on the stack, and we do not have to
8746 worry that a far jump might force the prologue to push the link
8747 register, changing the stack offsets. In this case we can just
8748 return false, since the presence of far jumps in the function will
8749 not affect stack offsets.
8751 If the arg pointer is live (or if it was live, but has now been
8752 eliminated and so set to dead) then we do have to test to see if
8753 the function might contain a far jump. This test can lead to some
8754 false negatives, since before reload is completed, then length of
8755 branch instructions is not known, so gcc defaults to returning their
8756 longest length, which in turn sets the far jump attribute to true.
8758 A false negative will not result in bad code being generated, but it
8759 will result in a needless push and pop of the link register. We
8760 hope that this does not occur too often. */
8765 }
8767 /* Check to see if the function contains a branch
8768 insn with the far jump attribute set. */
8770 {
8772 /* Ignore tablejump patterns. */
8776 )
8777 {
8778 /* Record the fact that we have decied that
8779 the function does use far jumps. */
8782 }
8783 }
8786 }
8788 /* Return non-zero if FUNC must be entered in ARM mode. */
8789 int
8791 tree func;
8792 {
8796 /* Ignore the problem about functions whoes address is taken. */
8800 #ifdef ARM_PE
8802 #else
8804 #endif
8805 }
8807 /* The bits which aren't usefully expanded as rtl. */
8810 {
8827 {
8830 high_regs_pushed ++;
8831 }
8833 /* The prolog may have pushed some high registers to use as
8834 work registers. eg the testuite file:
8835 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
8836 compiles to produce:
8837 push {r4, r5, r6, r7, lr}
8838 mov r7, r9
8839 mov r6, r8
8840 push {r6, r7}
8841 as part of the prolog. We have to undo that pushing here. */
8844 {
8850 #ifdef RTX_CODE
8851 /* If we can deduce the registers used from the function's return value.
8852 This is more reliable that examining regs_ever_live[] because that
8853 will be set if the register is ever used in the function, not just if
8854 the register is used to hold a return value. */
8858 else
8859 #endif
8864 /* Unless we are returning a type of size > 12 register r3 is
8865 available. */
8870 /* Oh dear! We have no low registers into which we can pop
8871 high registers! */
8880 {
8881 /* Find lo register(s) into which the high register(s) can
8882 be popped. */
8884 {
8886 high_regs_pushed--;
8889 }
8893 /* Pop the values into the low register(s). */
8896 /* Move the value(s) into the high registers. */
8898 {
8900 {
8902 regno);
8907 && ! (TARGET_SINGLE_PIC_BASE
8910 }
8911 }
8912 }
8913 }
8921 {
8922 /* The stack backtrace structure creation code had to
8923 push R7 in order to get a work register, so we pop
8924 it now. */
8926 }
8929 {
8935 /* Either no argument registers were pushed or a backtrace
8936 structure was created which includes an adjusted stack
8937 pointer, so just pop everything. */
8943 /* We have either just popped the return address into the
8944 PC or it is was kept in LR for the entire function or
8945 it is still on the stack because we do not want to
8946 return by doing a pop {pc}. */
8949 (had_to_push_lr
8952 }
8953 else
8954 {
8955 /* Pop everything but the return address. */
8962 /* Get the return address into a temporary register. */
8965 /* Remove the argument registers that were pushed onto the stack. */
8968 current_function_pretend_args_size);
8972 else
8975 }
8978 }
8980 /* Functions to save and restore machine-specific function data. */
8982 static void
8985 {
8990 }
8992 static void
8995 {
8998 }
9000 /* Return an RTX indicating where the return address to the
9001 calling function can be found. */
9002 rtx
9005 rtx frame ATTRIBUTE_UNUSED;
9006 {
9007 rtx reg;
9015 {
9016 rtx init;
9018 /* No rtx yet. Invent one, and initialize it for r14 (lr) in
9019 the prologue. */
9026 else
9031 /* Emit the insn to the prologue with the other argument copies. */
9035 }
9038 }
9040 /* Do anything needed before RTL is emitted for each function. */
9041 void
9043 {
9044 /* Arrange to initialize and mark the machine per-function status. */
9047 }
9049 /* Generate the rest of a function's prologue. */
9050 void
9052 {
9056 /* Naked functions don't have prologues. */
9064 {
9070 else
9071 {
9073 rtx reg;
9075 /* The stack decrement is too big for an immediate value in a single
9076 insn. In theory we could issue multiple subtracts, but after
9077 three of them it becomes more space efficient to place the full
9078 value in the constant pool and load into a register. (Also the
9079 ARM debugger really likes to see only one stack decrement per
9080 function). So instead we look for a scratch register into which
9081 we can load the decrement, and then we subtract this from the
9082 stack pointer. Unfortunately on the thumb the only available
9083 scratch registers are the argument registers, and we cannot use
9084 these as they may hold arguments to the function. Instead we
9085 attempt to locate a call preserved register which is used by this
9086 function. If we can find one, then we know that it will have
9087 been pushed at the start of the prologue and so we can corrupt
9088 it now. */
9093 && ! (frame_pointer_needed
9098 {
9101 /* Choose an arbitary, non-argument low register. */
9104 /* Save it by copying it into a high, scratch register. */
9107 /* Decrement the stack. */
9110 reg));
9112 /* Restore the low register's original value. */
9115 /* Emit a USE of the restored scratch register, so that flow
9116 analysis will not consider the restore redundant. The
9117 register won't be used again in this function and isn't
9118 restored by the epilogue. */
9120 }
9121 else
9122 {
9127 reg));
9128 }
9129 }
9130 }
9134 }
9136 void
9138 {
9142 /* Naked functions don't have epilogues. */
9149 {
9155 else
9156 {
9157 /* r3 is always free in the epilogue. */
9162 }
9163 }
9165 /* Emit a USE (stack_pointer_rtx), so that
9166 the stack adjustment will not be deleted. */
9171 }
9173 void
9176 {
9186 {
9195 /* Generate code sequence to switch us into Thumb mode. */
9196 /* The .code 32 directive has already been emitted by
9197 ASM_DECLARE_FUNCITON_NAME */
9201 /* Generate a label, so that the debugger will notice the
9202 change in instruction sets. This label is also used by
9203 the assembler to bypass the ARM code when this function
9204 is called from a Thumb encoded function elsewhere in the
9205 same file. Hence the definition of STUB_NAME here must
9206 agree with the definition in gas/config/tc-arm.c */
9211 #ifdef ARM_PE
9214 #endif
9218 }
9224 {
9226 {
9235 regno ++)
9240 }
9241 else
9244 current_function_pretend_args_size);
9245 }
9256 {
9261 /* We have been asked to create a stack backtrace structure.
9262 The code looks like this:
9264 0 .align 2
9265 0 func:
9266 0 sub SP, #16 Reserve space for 4 registers.
9267 2 push {R7} Get a work register.
9268 4 add R7, SP, #20 Get the stack pointer before the push.
9269 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
9270 8 mov R7, PC Get hold of the start of this code plus 12.
9271 10 str R7, [SP, #16] Store it.
9272 12 mov R7, FP Get hold of the current frame pointer.
9273 14 str R7, [SP, #4] Store it.
9274 16 mov R7, LR Get hold of the current return address.
9275 18 str R7, [SP, #12] Store it.
9276 20 add R7, SP, #16 Point at the start of the backtrace structure.
9277 22 mov FP, R7 Put this value into the frame pointer. */
9280 {
9281 /* See if the a4 register is free. */
9287 }
9290 {
9291 /* Select a register from the list that will be pushed to
9292 use as our work register. */
9296 }
9298 asm_fprintf
9315 /* Make sure that the instruction fetching the PC is in the right place
9316 to calculate "start of backtrace creation code + 12". */
9318 {
9323 ARM_HARD_FRAME_POINTER_REGNUM);
9325 offset);
9326 }
9327 else
9328 {
9330 ARM_HARD_FRAME_POINTER_REGNUM);
9332 offset);
9336 }
9345 }
9350 {
9353 high_regs_pushed ++;
9354 }
9357 {
9363 {
9365 && ! (TARGET_SINGLE_PIC_BASE
9368 }
9373 {
9374 /* Desperation time -- this probably will never happen. */
9379 }
9382 {
9384 {
9386 {
9389 high_regs_pushed --;
9393 next_hi_reg--)
9394 {
9397 && ! (TARGET_SINGLE_PIC_BASE
9400 }
9401 else
9402 {
9405 }
9406 }
9407 }
9410 }
9416 }
9417 }
9419 /* Handle the case of a double word load into a low register from
9420 a computed memory address. The computed address may involve a
9421 register which is overwritten by the load. */
9426 {
9427 rtx addr;
9428 rtx base;
9429 rtx offset;
9430 rtx arg1;
9431 rtx arg2;
9437 {
9440 }
9442 /* Get the memory address. */
9445 /* Work out how the memory address is computed. */
9447 {
9453 {
9456 }
9457 else
9458 {
9461 }
9465 /* Compute <address> + 4 for the high order load. */
9479 else
9485 /* Catch the case of <address> = <reg> + <reg> */
9487 {
9492 /* Add the base and offset registers together into the
9493 higher destination register. */
9497 /* Load the lower destination register from the address in
9498 the higher destination register. */
9502 /* Load the higher destination register from its own address
9503 plus 4. */
9506 }
9507 else
9508 {
9509 /* Compute <address> + 4 for the high order load. */
9513 /* If the computed address is held in the low order register
9514 then load the high order register first, otherwise always
9515 load the low order register first. */
9517 {
9520 }
9521 else
9522 {
9525 }
9526 }
9530 /* With no registers to worry about we can just load the value
9531 directly. */
9543 }
9546 }
9553 {
9554 rtx tmp;
9557 {
9560 {
9564 }
9571 {
9575 }
9577 {
9581 }
9583 {
9587 }
9595 }
9598 }
9600 /* Routines for generating rtl */
9602 void
9605 {
9612 {
9615 }
9618 {
9621 }
9624 {
9630 }
9633 {
9638 reg));
9641 }
9644 {
9649 reg));
9650 }
9651 }
9653 int
9655 rtx op;
9657 {
9661 }
9665 rtx x;
9667 {
9669 {
9672 };
9676 {
9689 }
9692 }
9694 /* Handle storing a half-word to memory during reload. */
9695 void
9698 {
9700 }
9702 /* Handle storing a half-word to memory during reload. */
9703 void
9706 {
9708 }
9710 /* Return the length of a function name prefix
9711 that starts with the character 'c'. */
9712 static int
9714 {
9716 {
9717 ARM_NAME_ENCODING_LENGTHS
9719 }
9720 }
9722 /* Return a pointer to a function's name with any
9723 and all prefix encodings stripped from it. */
9726 {
9733 }
9735 #ifdef AOF_ASSEMBLER
9736 /* Special functions only needed when producing AOF syntax assembler. */
9739 struct pic_chain
9740 {
9743 };
9747 rtx
9749 rtx x;
9750 {
9755 {
9756 /* We mark this here and not in arm_add_gc_roots() to avoid
9757 polluting even more code with ifdefs, and because it never
9758 contains anything useful until we assign to it here. */
9760 /* This needs to persist throughout the compilation. */
9764 }
9775 }
9777 void
9780 {
9787 PIC_OFFSET_TABLE_REGNUM,
9788 PIC_OFFSET_TABLE_REGNUM);
9792 {
9796 }
9797 }
9803 {
9806 arm_text_section_count++);
9810 }
9816 {
9820 }
9822 /* The AOF assembler is religiously strict about declarations of
9823 imported and exported symbols, so that it is impossible to declare
9824 a function as imported near the beginning of the file, and then to
9825 export it later on. It is, however, possible to delay the decision
9826 until all the functions in the file have been compiled. To get
9827 around this, we maintain a list of the imports and exports, and
9828 delete from it any that are subsequently defined. At the end of
9829 compilation we spit the remainder of the list out before the END
9830 directive. */
9832 struct import
9833 {
9836 };
9840 void
9843 {
9854 }
9856 void
9859 {
9863 {
9865 {
9868 }
9869 }
9870 }
9874 void
9877 {
9878 /* The AOF assembler needs this to cause the startup code to be extracted
9879 from the library. Brining in __main causes the whole thing to work
9880 automagically. */
9882 {
9886 }
9888 /* Now dump the remaining imports. */
9890 {
9895 }
9896 }