| blob | 2e4df11579a01b526bbaa6ea4176bf919aa7b886 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_MOVSI_GOT
73 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
74 UNSPEC_FCTIWZ
75 UNSPEC_FRIM
76 UNSPEC_FRIN
77 UNSPEC_FRIP
78 UNSPEC_FRIZ
79 UNSPEC_LD_MPIC ; load_macho_picbase
80 UNSPEC_RELD_MPIC ; re-load_macho_picbase
81 UNSPEC_MPIC_CORRECT ; macho_correct_pic
82 UNSPEC_TLSGD
83 UNSPEC_TLSLD
84 UNSPEC_MOVESI_FROM_CR
85 UNSPEC_MOVESI_TO_CR
86 UNSPEC_TLSDTPREL
87 UNSPEC_TLSDTPRELHA
88 UNSPEC_TLSDTPRELLO
89 UNSPEC_TLSGOTDTPREL
90 UNSPEC_TLSTPREL
91 UNSPEC_TLSTPRELHA
92 UNSPEC_TLSTPRELLO
93 UNSPEC_TLSGOTTPREL
94 UNSPEC_TLSTLS
95 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
96 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
97 UNSPEC_STFIWX
98 UNSPEC_POPCNTB
99 UNSPEC_FRES
100 UNSPEC_SP_SET
101 UNSPEC_SP_TEST
102 UNSPEC_SYNC
103 UNSPEC_LWSYNC
104 UNSPEC_SYNC_OP
105 UNSPEC_ATOMIC
106 UNSPEC_CMPXCHG
107 UNSPEC_XCHG
108 UNSPEC_AND
109 UNSPEC_DLMZB
110 UNSPEC_DLMZB_CR
111 UNSPEC_DLMZB_STRLEN
112 UNSPEC_RSQRT
113 UNSPEC_TOCREL
114 UNSPEC_MACHOPIC_OFFSET
115 UNSPEC_BPERM
116 UNSPEC_COPYSIGN
117 UNSPEC_PARITY
118 UNSPEC_FCTIW
119 UNSPEC_FCTID
120 UNSPEC_LFIWAX
121 UNSPEC_LFIWZX
122 UNSPEC_FCTIWUZ
123 UNSPEC_GRP_END_NOP
124 UNSPEC_P8V_FMRGOW
125 UNSPEC_P8V_MTVSRWZ
126 UNSPEC_P8V_RELOAD_FROM_GPR
127 UNSPEC_P8V_MTVSRD
128 UNSPEC_P8V_XXPERMDI
129 UNSPEC_P8V_RELOAD_FROM_VSX
130 UNSPEC_ADDG6S
131 UNSPEC_CDTBCD
132 UNSPEC_CBCDTD
133 UNSPEC_DIVE
134 UNSPEC_DIVEO
135 UNSPEC_DIVEU
136 UNSPEC_DIVEUO
137 UNSPEC_UNPACK_128BIT
138 UNSPEC_PACK_128BIT
139 UNSPEC_LSQ
140 ])
142 ;;
143 ;; UNSPEC_VOLATILE usage
144 ;;
146 (define_c_enum "unspecv"
147 [UNSPECV_BLOCK
148 UNSPECV_LL ; load-locked
149 UNSPECV_SC ; store-conditional
150 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
151 UNSPECV_EH_RR ; eh_reg_restore
152 UNSPECV_ISYNC ; isync instruction
153 UNSPECV_MFTB ; move from time base
154 UNSPECV_NLGR ; non-local goto receiver
155 UNSPECV_MFFS ; Move from FPSCR
156 UNSPECV_MTFSF ; Move to FPSCR Fields
157 ])
159 \f
160 ;; Define an insn type attribute. This is used in function unit delay
161 ;; computations.
162 (define_attr "type"
163 "integer,two,three,
164 add,logical,shift,insert,
165 mul,halfmul,div,
166 exts,cntlz,popcnt,isel,
167 load,store,fpload,fpstore,vecload,vecstore,
168 cmp,
169 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
170 compare,
171 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
172 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
173 brinc,
174 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
175 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
176 htm"
177 (const_string "integer"))
179 ;; What data size does this instruction work on?
180 ;; This is used for insert, mul.
181 (define_attr "size" "8,16,32,64" (const_string "32"))
183 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
184 ;; This is used for add, logical, shift, mul.
185 (define_attr "dot" "no,yes" (const_string "no"))
187 ;; Does this instruction sign-extend its result?
188 ;; This is used for load insns.
189 (define_attr "sign_extend" "no,yes" (const_string "no"))
191 ;; Does this instruction use indexed (that is, reg+reg) addressing?
192 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
193 ;; it is automatically set based on that. If a load or store instruction
194 ;; has fewer than two operands it needs to set this attribute manually
195 ;; or the compiler will crash.
196 (define_attr "indexed" "no,yes"
197 (if_then_else (ior (match_operand 0 "indexed_address_mem")
198 (match_operand 1 "indexed_address_mem"))
199 (const_string "yes")
200 (const_string "no")))
202 ;; Does this instruction use update addressing?
203 ;; This is used for load and store insns. See the comments for "indexed".
204 (define_attr "update" "no,yes"
205 (if_then_else (ior (match_operand 0 "update_address_mem")
206 (match_operand 1 "update_address_mem"))
207 (const_string "yes")
208 (const_string "no")))
210 ;; Is this instruction using operands[2] as shift amount, and can that be a
211 ;; register?
212 ;; This is used for shift insns.
213 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
215 ;; Is this instruction using a shift amount from a register?
216 ;; This is used for shift insns.
217 (define_attr "var_shift" "no,yes"
218 (if_then_else (and (eq_attr "type" "shift")
219 (eq_attr "maybe_var_shift" "yes"))
220 (if_then_else (match_operand 2 "gpc_reg_operand")
221 (const_string "yes")
222 (const_string "no"))
223 (const_string "no")))
225 ;; Define floating point instruction sub-types for use with Xfpu.md
226 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
228 ;; Length (in bytes).
229 ; '(pc)' in the following doesn't include the instruction itself; it is
230 ; calculated as if the instruction had zero size.
231 (define_attr "length" ""
232 (if_then_else (eq_attr "type" "branch")
233 (if_then_else (and (ge (minus (match_dup 0) (pc))
234 (const_int -32768))
235 (lt (minus (match_dup 0) (pc))
236 (const_int 32764)))
237 (const_int 4)
238 (const_int 8))
239 (const_int 4)))
241 ;; Processor type -- this attribute must exactly match the processor_type
242 ;; enumeration in rs6000-opts.h.
243 (define_attr "cpu"
244 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
245 ppc750,ppc7400,ppc7450,
246 ppc403,ppc405,ppc440,ppc476,
247 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
248 power4,power5,power6,power7,power8,
249 rs64a,mpccore,cell,ppca2,titan"
250 (const (symbol_ref "rs6000_cpu_attr")))
253 ;; If this instruction is microcoded on the CELL processor
254 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
255 (define_attr "cell_micro" "not,conditional,always"
256 (if_then_else (ior (eq_attr "type" "compare")
257 (and (eq_attr "type" "shift,mul")
258 (eq_attr "dot" "yes"))
259 (and (eq_attr "type" "load")
260 (eq_attr "sign_extend" "yes"))
261 (and (eq_attr "type" "shift")
262 (eq_attr "var_shift" "yes")))
263 (const_string "always")
264 (const_string "not")))
266 (automata_option "ndfa")
268 (include "rs64.md")
269 (include "mpc.md")
270 (include "40x.md")
271 (include "440.md")
272 (include "476.md")
273 (include "601.md")
274 (include "603.md")
275 (include "6xx.md")
276 (include "7xx.md")
277 (include "7450.md")
278 (include "8540.md")
279 (include "e300c2c3.md")
280 (include "e500mc.md")
281 (include "e500mc64.md")
282 (include "e5500.md")
283 (include "e6500.md")
284 (include "power4.md")
285 (include "power5.md")
286 (include "power6.md")
287 (include "power7.md")
288 (include "power8.md")
289 (include "cell.md")
290 (include "xfpu.md")
291 (include "a2.md")
292 (include "titan.md")
294 (include "predicates.md")
295 (include "constraints.md")
297 (include "darwin.md")
299 \f
300 ;; Mode iterators
302 ; This mode iterator allows :GPR to be used to indicate the allowable size
303 ; of whole values in GPRs.
304 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
306 ; Any supported integer mode.
307 (define_mode_iterator INT [QI HI SI DI TI PTI])
309 ; Any supported integer mode that fits in one register.
310 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
312 ; extend modes for DImode
313 (define_mode_iterator QHSI [QI HI SI])
315 ; QImode or HImode for small atomic ops
316 (define_mode_iterator QHI [QI HI])
318 ; HImode or SImode for sign extended fusion ops
319 (define_mode_iterator HSI [HI SI])
321 ; SImode or DImode, even if DImode doesn't fit in GPRs.
322 (define_mode_iterator SDI [SI DI])
324 ; The size of a pointer. Also, the size of the value that a record-condition
325 ; (one with a '.') will compare; and the size used for arithmetic carries.
326 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
328 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
329 ; PTImode is GPR only)
330 (define_mode_iterator TI2 [TI PTI])
332 ; Any hardware-supported floating-point mode
333 (define_mode_iterator FP [
334 (SF "TARGET_HARD_FLOAT
335 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
336 (DF "TARGET_HARD_FLOAT
337 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
338 (TF "!TARGET_IEEEQUAD
339 && TARGET_HARD_FLOAT
340 && (TARGET_FPRS || TARGET_E500_DOUBLE)
341 && TARGET_LONG_DOUBLE_128")
342 (DD "TARGET_DFP")
343 (TD "TARGET_DFP")])
345 ; Any fma capable floating-point mode.
346 (define_mode_iterator FMA_F [
347 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
348 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
349 || VECTOR_UNIT_VSX_P (DFmode)")
350 (V2SF "TARGET_PAIRED_FLOAT")
351 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
352 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
353 ])
355 ; Floating point move iterators to combine binary and decimal moves
356 (define_mode_iterator FMOVE32 [SF SD])
357 (define_mode_iterator FMOVE64 [DF DD])
358 (define_mode_iterator FMOVE64X [DI DF DD])
359 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
360 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
362 ; Iterators for 128 bit types for direct move
363 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
364 (V16QI "")
365 (V8HI "")
366 (V4SI "")
367 (V4SF "")
368 (V2DI "")
369 (V2DF "")
370 (V1TI "")])
372 ; Whether a floating point move is ok, don't allow SD without hardware FP
373 (define_mode_attr fmove_ok [(SF "")
374 (DF "")
375 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
376 (DD "")])
378 ; Convert REAL_VALUE to the appropriate bits
379 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
380 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
381 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
382 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
384 ; Definitions for load to 32-bit fpr register
385 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
386 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
387 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
388 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
390 ; Definitions for store from 32-bit fpr register
391 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
392 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
393 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
394 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
396 ; Definitions for 32-bit fpr direct move
397 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
399 ; These modes do not fit in integer registers in 32-bit mode.
400 ; but on e500v2, the gpr are 64 bit registers
401 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
403 ; Iterator for reciprocal estimate instructions
404 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
406 ; Iterator for just SF/DF
407 (define_mode_iterator SFDF [SF DF])
409 ; SF/DF suffix for traditional floating instructions
410 (define_mode_attr Ftrad [(SF "s") (DF "")])
412 ; SF/DF suffix for VSX instructions
413 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
415 ; SF/DF constraint for arithmetic on traditional floating point registers
416 (define_mode_attr Ff [(SF "f") (DF "d")])
418 ; SF/DF constraint for arithmetic on VSX registers
419 (define_mode_attr Fv [(SF "wy") (DF "ws")])
421 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
422 (define_mode_attr Fs [(SF "s") (DF "d")])
424 ; FRE/FRES support
425 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
426 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
428 ; Conditional returns.
429 (define_code_iterator any_return [return simple_return])
430 (define_code_attr return_pred [(return "direct_return ()")
431 (simple_return "1")])
432 (define_code_attr return_str [(return "") (simple_return "simple_")])
434 ; Various instructions that come in SI and DI forms.
435 ; A generic w/d attribute, for things like cmpw/cmpd.
436 (define_mode_attr wd [(QI "b")
437 (HI "h")
438 (SI "w")
439 (DI "d")
440 (V16QI "b")
441 (V8HI "h")
442 (V4SI "w")
443 (V2DI "d")])
445 ;; How many bits in this mode?
446 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
448 ; DImode bits
449 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
451 ;; ISEL/ISEL64 target selection
452 (define_mode_attr sel [(SI "") (DI "64")])
454 ;; Bitmask for shift instructions
455 (define_mode_attr hH [(SI "h") (DI "H")])
457 ;; Suffix for reload patterns
458 (define_mode_attr ptrsize [(SI "32bit")
459 (DI "64bit")])
461 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
462 (DI "TARGET_64BIT")])
464 (define_mode_attr mptrsize [(SI "si")
465 (DI "di")])
467 (define_mode_attr ptrload [(SI "lwz")
468 (DI "ld")])
470 (define_mode_attr ptrm [(SI "m")
471 (DI "Y")])
473 (define_mode_attr rreg [(SF "f")
474 (DF "ws")
475 (TF "f")
476 (TD "f")
477 (V4SF "wf")
478 (V2DF "wd")])
480 (define_mode_attr rreg2 [(SF "f")
481 (DF "d")])
483 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
484 (DF "TARGET_FCFID")])
486 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
487 (DF "TARGET_E500_DOUBLE")])
489 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
490 (DF "TARGET_DOUBLE_FLOAT")])
492 ;; Mode iterator for logical operations on 128-bit types
493 (define_mode_iterator BOOL_128 [TI
494 PTI
495 (V16QI "TARGET_ALTIVEC")
496 (V8HI "TARGET_ALTIVEC")
497 (V4SI "TARGET_ALTIVEC")
498 (V4SF "TARGET_ALTIVEC")
499 (V2DI "TARGET_ALTIVEC")
500 (V2DF "TARGET_ALTIVEC")
501 (V1TI "TARGET_ALTIVEC")])
503 ;; For the GPRs we use 3 constraints for register outputs, two that are the
504 ;; same as the output register, and a third where the output register is an
505 ;; early clobber, so we don't have to deal with register overlaps. For the
506 ;; vector types, we prefer to use the vector registers. For TI mode, allow
507 ;; either.
509 ;; Mode attribute for boolean operation register constraints for output
510 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
511 (PTI "&r,r,r")
512 (V16QI "wa,v,&?r,?r,?r")
513 (V8HI "wa,v,&?r,?r,?r")
514 (V4SI "wa,v,&?r,?r,?r")
515 (V4SF "wa,v,&?r,?r,?r")
516 (V2DI "wa,v,&?r,?r,?r")
517 (V2DF "wa,v,&?r,?r,?r")
518 (V1TI "wa,v,&?r,?r,?r")])
520 ;; Mode attribute for boolean operation register constraints for operand1
521 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
522 (PTI "r,0,r")
523 (V16QI "wa,v,r,0,r")
524 (V8HI "wa,v,r,0,r")
525 (V4SI "wa,v,r,0,r")
526 (V4SF "wa,v,r,0,r")
527 (V2DI "wa,v,r,0,r")
528 (V2DF "wa,v,r,0,r")
529 (V1TI "wa,v,r,0,r")])
531 ;; Mode attribute for boolean operation register constraints for operand2
532 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
533 (PTI "r,r,0")
534 (V16QI "wa,v,r,r,0")
535 (V8HI "wa,v,r,r,0")
536 (V4SI "wa,v,r,r,0")
537 (V4SF "wa,v,r,r,0")
538 (V2DI "wa,v,r,r,0")
539 (V2DF "wa,v,r,r,0")
540 (V1TI "wa,v,r,r,0")])
542 ;; Mode attribute for boolean operation register constraints for operand1
543 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
544 ;; is used for operand1 or operand2
545 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
546 (PTI "r,0,0")
547 (V16QI "wa,v,r,0,0")
548 (V8HI "wa,v,r,0,0")
549 (V4SI "wa,v,r,0,0")
550 (V4SF "wa,v,r,0,0")
551 (V2DI "wa,v,r,0,0")
552 (V2DF "wa,v,r,0,0")
553 (V1TI "wa,v,r,0,0")])
555 ;; Mode attribute for the clobber of CC0 for AND expansion.
556 ;; For the 128-bit types, we never do AND immediate, but we need to
557 ;; get the correct number of X's for the number of operands.
558 (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
559 (PTI "X,X,X")
560 (V16QI "X,X,X,X,X")
561 (V8HI "X,X,X,X,X")
562 (V4SI "X,X,X,X,X")
563 (V4SF "X,X,X,X,X")
564 (V2DI "X,X,X,X,X")
565 (V2DF "X,X,X,X,X")
566 (V1TI "X,X,X,X,X")])
567 \f
568 ;; Start with fixed-point load and store insns. Here we put only the more
569 ;; complex forms. Basic data transfer is done later.
571 (define_expand "zero_extend<mode>di2"
572 [(set (match_operand:DI 0 "gpc_reg_operand" "")
573 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
574 "TARGET_POWERPC64"
575 "")
577 (define_insn "*zero_extend<mode>di2_internal1"
578 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
579 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
580 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
581 "@
582 l<wd>z%U1%X1 %0,%1
583 rldicl %0,%1,0,<dbits>"
584 [(set_attr "type" "load,shift")])
586 (define_insn "*zero_extend<mode>di2_internal2"
587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
588 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
589 (const_int 0)))
590 (clobber (match_scratch:DI 2 "=r,r"))]
591 "TARGET_64BIT"
592 "@
593 rldicl. %2,%1,0,<dbits>
594 #"
595 [(set_attr "type" "shift")
596 (set_attr "dot" "yes")
597 (set_attr "length" "4,8")])
599 (define_split
600 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
601 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
602 (const_int 0)))
603 (clobber (match_scratch:DI 2 ""))]
604 "TARGET_POWERPC64 && reload_completed"
605 [(set (match_dup 2)
606 (zero_extend:DI (match_dup 1)))
607 (set (match_dup 0)
608 (compare:CC (match_dup 2)
609 (const_int 0)))]
610 "")
612 (define_insn "*zero_extend<mode>di2_internal3"
613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
615 (const_int 0)))
616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
617 (zero_extend:DI (match_dup 1)))]
618 "TARGET_64BIT"
619 "@
620 rldicl. %0,%1,0,<dbits>
621 #"
622 [(set_attr "type" "shift")
623 (set_attr "dot" "yes")
624 (set_attr "length" "4,8")])
626 (define_split
627 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
628 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
629 (const_int 0)))
630 (set (match_operand:DI 0 "gpc_reg_operand" "")
631 (zero_extend:DI (match_dup 1)))]
632 "TARGET_POWERPC64 && reload_completed"
633 [(set (match_dup 0)
634 (zero_extend:DI (match_dup 1)))
635 (set (match_dup 2)
636 (compare:CC (match_dup 0)
637 (const_int 0)))]
638 "")
640 (define_insn "*zero_extendsidi2_lfiwzx"
641 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
642 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
643 "TARGET_POWERPC64 && TARGET_LFIWZX"
644 "@
645 lwz%U1%X1 %0,%1
646 rldicl %0,%1,0,32
647 mtvsrwz %x0,%1
648 lfiwzx %0,%y1
649 lxsiwzx %x0,%y1"
650 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
652 (define_insn "extendqidi2"
653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
654 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
655 "TARGET_POWERPC64"
656 "extsb %0,%1"
657 [(set_attr "type" "exts")])
659 (define_insn ""
660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
661 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
662 (const_int 0)))
663 (clobber (match_scratch:DI 2 "=r,r"))]
664 "TARGET_64BIT"
665 "@
666 extsb. %2,%1
667 #"
668 [(set_attr "type" "compare")
669 (set_attr "length" "4,8")])
671 (define_split
672 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
673 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
674 (const_int 0)))
675 (clobber (match_scratch:DI 2 ""))]
676 "TARGET_POWERPC64 && reload_completed"
677 [(set (match_dup 2)
678 (sign_extend:DI (match_dup 1)))
679 (set (match_dup 0)
680 (compare:CC (match_dup 2)
681 (const_int 0)))]
682 "")
684 (define_insn ""
685 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
686 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
687 (const_int 0)))
688 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
689 (sign_extend:DI (match_dup 1)))]
690 "TARGET_64BIT"
691 "@
692 extsb. %0,%1
693 #"
694 [(set_attr "type" "compare")
695 (set_attr "length" "4,8")])
697 (define_split
698 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
699 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
700 (const_int 0)))
701 (set (match_operand:DI 0 "gpc_reg_operand" "")
702 (sign_extend:DI (match_dup 1)))]
703 "TARGET_POWERPC64 && reload_completed"
704 [(set (match_dup 0)
705 (sign_extend:DI (match_dup 1)))
706 (set (match_dup 2)
707 (compare:CC (match_dup 0)
708 (const_int 0)))]
709 "")
711 (define_expand "extendhidi2"
712 [(set (match_operand:DI 0 "gpc_reg_operand" "")
713 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
714 "TARGET_POWERPC64"
715 "")
717 (define_insn ""
718 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
719 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
720 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
721 "@
722 lha%U1%X1 %0,%1
723 extsh %0,%1"
724 [(set_attr "type" "load,exts")
725 (set_attr "sign_extend" "yes")])
727 (define_insn ""
728 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
729 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
730 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
731 "extsh %0,%1"
732 [(set_attr "type" "exts")])
734 (define_insn ""
735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
736 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
737 (const_int 0)))
738 (clobber (match_scratch:DI 2 "=r,r"))]
739 "TARGET_64BIT"
740 "@
741 extsh. %2,%1
742 #"
743 [(set_attr "type" "compare")
744 (set_attr "length" "4,8")])
746 (define_split
747 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
748 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
749 (const_int 0)))
750 (clobber (match_scratch:DI 2 ""))]
751 "TARGET_POWERPC64 && reload_completed"
752 [(set (match_dup 2)
753 (sign_extend:DI (match_dup 1)))
754 (set (match_dup 0)
755 (compare:CC (match_dup 2)
756 (const_int 0)))]
757 "")
759 (define_insn ""
760 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
761 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
762 (const_int 0)))
763 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
764 (sign_extend:DI (match_dup 1)))]
765 "TARGET_64BIT"
766 "@
767 extsh. %0,%1
768 #"
769 [(set_attr "type" "compare")
770 (set_attr "length" "4,8")])
772 (define_split
773 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
774 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
775 (const_int 0)))
776 (set (match_operand:DI 0 "gpc_reg_operand" "")
777 (sign_extend:DI (match_dup 1)))]
778 "TARGET_POWERPC64 && reload_completed"
779 [(set (match_dup 0)
780 (sign_extend:DI (match_dup 1)))
781 (set (match_dup 2)
782 (compare:CC (match_dup 0)
783 (const_int 0)))]
784 "")
786 (define_expand "extendsidi2"
787 [(set (match_operand:DI 0 "gpc_reg_operand" "")
788 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
789 "TARGET_POWERPC64"
790 "")
792 (define_insn "*extendsidi2_lfiwax"
793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
794 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
795 "TARGET_POWERPC64 && TARGET_LFIWAX"
796 "@
797 lwa%U1%X1 %0,%1
798 extsw %0,%1
799 mtvsrwa %x0,%1
800 lfiwax %0,%y1
801 lxsiwax %x0,%y1"
802 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
803 (set_attr "sign_extend" "yes")])
805 (define_insn "*extendsidi2_nocell"
806 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
807 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))]
808 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
809 "@
810 lwa%U1%X1 %0,%1
811 extsw %0,%1"
812 [(set_attr "type" "load,exts")
813 (set_attr "sign_extend" "yes")])
815 (define_insn "*extendsidi2_nocell"
816 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
817 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
818 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
819 "extsw %0,%1"
820 [(set_attr "type" "exts")])
822 (define_insn ""
823 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
824 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
825 (const_int 0)))
826 (clobber (match_scratch:DI 2 "=r,r"))]
827 "TARGET_64BIT"
828 "@
829 extsw. %2,%1
830 #"
831 [(set_attr "type" "compare")
832 (set_attr "length" "4,8")])
834 (define_split
835 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
836 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
837 (const_int 0)))
838 (clobber (match_scratch:DI 2 ""))]
839 "TARGET_POWERPC64 && reload_completed"
840 [(set (match_dup 2)
841 (sign_extend:DI (match_dup 1)))
842 (set (match_dup 0)
843 (compare:CC (match_dup 2)
844 (const_int 0)))]
845 "")
847 (define_insn ""
848 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
849 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
850 (const_int 0)))
851 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
852 (sign_extend:DI (match_dup 1)))]
853 "TARGET_64BIT"
854 "@
855 extsw. %0,%1
856 #"
857 [(set_attr "type" "compare")
858 (set_attr "length" "4,8")])
860 (define_split
861 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
862 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
863 (const_int 0)))
864 (set (match_operand:DI 0 "gpc_reg_operand" "")
865 (sign_extend:DI (match_dup 1)))]
866 "TARGET_POWERPC64 && reload_completed"
867 [(set (match_dup 0)
868 (sign_extend:DI (match_dup 1)))
869 (set (match_dup 2)
870 (compare:CC (match_dup 0)
871 (const_int 0)))]
872 "")
874 (define_expand "zero_extendqisi2"
875 [(set (match_operand:SI 0 "gpc_reg_operand" "")
876 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
877 ""
878 "")
880 (define_insn ""
881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
882 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
883 ""
884 "@
885 lbz%U1%X1 %0,%1
886 rlwinm %0,%1,0,0xff"
887 [(set_attr "type" "load,shift")])
889 (define_insn ""
890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
891 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
892 (const_int 0)))
893 (clobber (match_scratch:SI 2 "=r,r"))]
894 ""
895 "@
896 andi. %2,%1,0xff
897 #"
898 [(set_attr "type" "logical,compare")
899 (set_attr "dot" "yes")
900 (set_attr "length" "4,8")])
902 (define_split
903 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
904 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
905 (const_int 0)))
906 (clobber (match_scratch:SI 2 ""))]
907 "reload_completed"
908 [(set (match_dup 2)
909 (zero_extend:SI (match_dup 1)))
910 (set (match_dup 0)
911 (compare:CC (match_dup 2)
912 (const_int 0)))]
913 "")
915 (define_insn ""
916 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
917 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
918 (const_int 0)))
919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
920 (zero_extend:SI (match_dup 1)))]
921 ""
922 "@
923 andi. %0,%1,0xff
924 #"
925 [(set_attr "type" "logical,compare")
926 (set_attr "dot" "yes")
927 (set_attr "length" "4,8")])
929 (define_split
930 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
931 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
932 (const_int 0)))
933 (set (match_operand:SI 0 "gpc_reg_operand" "")
934 (zero_extend:SI (match_dup 1)))]
935 "reload_completed"
936 [(set (match_dup 0)
937 (zero_extend:SI (match_dup 1)))
938 (set (match_dup 2)
939 (compare:CC (match_dup 0)
940 (const_int 0)))]
941 "")
943 (define_insn "extendqisi2"
944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
945 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
946 ""
947 "extsb %0,%1"
948 [(set_attr "type" "exts")])
950 (define_insn ""
951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
952 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
953 (const_int 0)))
954 (clobber (match_scratch:SI 2 "=r,r"))]
955 ""
956 "@
957 extsb. %2,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
962 (define_split
963 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
965 (const_int 0)))
966 (clobber (match_scratch:SI 2 ""))]
967 "reload_completed"
968 [(set (match_dup 2)
969 (sign_extend:SI (match_dup 1)))
970 (set (match_dup 0)
971 (compare:CC (match_dup 2)
972 (const_int 0)))]
973 "")
975 (define_insn ""
976 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
977 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
978 (const_int 0)))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
980 (sign_extend:SI (match_dup 1)))]
981 ""
982 "@
983 extsb. %0,%1
984 #"
985 [(set_attr "type" "compare")
986 (set_attr "length" "4,8")])
988 (define_split
989 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
990 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
991 (const_int 0)))
992 (set (match_operand:SI 0 "gpc_reg_operand" "")
993 (sign_extend:SI (match_dup 1)))]
994 "reload_completed"
995 [(set (match_dup 0)
996 (sign_extend:SI (match_dup 1)))
997 (set (match_dup 2)
998 (compare:CC (match_dup 0)
999 (const_int 0)))]
1000 "")
1002 (define_insn ""
1003 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1004 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1005 ""
1006 "@
1007 lbz%U1%X1 %0,%1
1008 rlwinm %0,%1,0,0xff"
1009 [(set_attr "type" "load,shift")])
1011 (define_insn ""
1012 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1013 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1014 (const_int 0)))
1015 (clobber (match_scratch:HI 2 "=r,r"))]
1016 ""
1017 "@
1018 andi. %2,%1,0xff
1019 #"
1020 [(set_attr "type" "logical,compare")
1021 (set_attr "dot" "yes")
1022 (set_attr "length" "4,8")])
1024 (define_split
1025 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1026 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1027 (const_int 0)))
1028 (clobber (match_scratch:HI 2 ""))]
1029 "reload_completed"
1030 [(set (match_dup 2)
1031 (zero_extend:HI (match_dup 1)))
1032 (set (match_dup 0)
1033 (compare:CC (match_dup 2)
1034 (const_int 0)))]
1035 "")
1037 (define_insn ""
1038 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1039 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1040 (const_int 0)))
1041 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1042 (zero_extend:HI (match_dup 1)))]
1043 ""
1044 "@
1045 andi. %0,%1,0xff
1046 #"
1047 [(set_attr "type" "logical,compare")
1048 (set_attr "dot" "yes")
1049 (set_attr "length" "4,8")])
1051 (define_split
1052 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1053 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1054 (const_int 0)))
1055 (set (match_operand:HI 0 "gpc_reg_operand" "")
1056 (zero_extend:HI (match_dup 1)))]
1057 "reload_completed"
1058 [(set (match_dup 0)
1059 (zero_extend:HI (match_dup 1)))
1060 (set (match_dup 2)
1061 (compare:CC (match_dup 0)
1062 (const_int 0)))]
1063 "")
1065 (define_insn "extendqihi2"
1066 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1067 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1068 ""
1069 "extsb %0,%1"
1070 [(set_attr "type" "exts")])
1072 (define_insn ""
1073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1074 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1075 (const_int 0)))
1076 (clobber (match_scratch:HI 2 "=r,r"))]
1077 ""
1078 "@
1079 extsb. %2,%1
1080 #"
1081 [(set_attr "type" "compare")
1082 (set_attr "length" "4,8")])
1084 (define_split
1085 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1086 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1087 (const_int 0)))
1088 (clobber (match_scratch:HI 2 ""))]
1089 "reload_completed"
1090 [(set (match_dup 2)
1091 (sign_extend:HI (match_dup 1)))
1092 (set (match_dup 0)
1093 (compare:CC (match_dup 2)
1094 (const_int 0)))]
1095 "")
1097 (define_insn ""
1098 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1099 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1100 (const_int 0)))
1101 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1102 (sign_extend:HI (match_dup 1)))]
1103 ""
1104 "@
1105 extsb. %0,%1
1106 #"
1107 [(set_attr "type" "compare")
1108 (set_attr "length" "4,8")])
1110 (define_split
1111 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1112 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1113 (const_int 0)))
1114 (set (match_operand:HI 0 "gpc_reg_operand" "")
1115 (sign_extend:HI (match_dup 1)))]
1116 "reload_completed"
1117 [(set (match_dup 0)
1118 (sign_extend:HI (match_dup 1)))
1119 (set (match_dup 2)
1120 (compare:CC (match_dup 0)
1121 (const_int 0)))]
1122 "")
1124 (define_expand "zero_extendhisi2"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1126 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1127 ""
1128 "")
1130 (define_insn ""
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1132 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1133 ""
1134 "@
1135 lhz%U1%X1 %0,%1
1136 rlwinm %0,%1,0,0xffff"
1137 [(set_attr "type" "load,shift")])
1139 (define_insn ""
1140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1141 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1142 (const_int 0)))
1143 (clobber (match_scratch:SI 2 "=r,r"))]
1144 ""
1145 "@
1146 andi. %2,%1,0xffff
1147 #"
1148 [(set_attr "type" "logical,compare")
1149 (set_attr "dot" "yes")
1150 (set_attr "length" "4,8")])
1152 (define_split
1153 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1154 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1155 (const_int 0)))
1156 (clobber (match_scratch:SI 2 ""))]
1157 "reload_completed"
1158 [(set (match_dup 2)
1159 (zero_extend:SI (match_dup 1)))
1160 (set (match_dup 0)
1161 (compare:CC (match_dup 2)
1162 (const_int 0)))]
1163 "")
1165 (define_insn ""
1166 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1167 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1168 (const_int 0)))
1169 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1170 (zero_extend:SI (match_dup 1)))]
1171 ""
1172 "@
1173 andi. %0,%1,0xffff
1174 #"
1175 [(set_attr "type" "logical,compare")
1176 (set_attr "dot" "yes")
1177 (set_attr "length" "4,8")])
1179 (define_split
1180 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1181 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1182 (const_int 0)))
1183 (set (match_operand:SI 0 "gpc_reg_operand" "")
1184 (zero_extend:SI (match_dup 1)))]
1185 "reload_completed"
1186 [(set (match_dup 0)
1187 (zero_extend:SI (match_dup 1)))
1188 (set (match_dup 2)
1189 (compare:CC (match_dup 0)
1190 (const_int 0)))]
1191 "")
1193 (define_expand "extendhisi2"
1194 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1195 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1196 ""
1197 "")
1199 (define_insn ""
1200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1201 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1202 "rs6000_gen_cell_microcode"
1203 "@
1204 lha%U1%X1 %0,%1
1205 extsh %0,%1"
1206 [(set_attr "type" "load,exts")
1207 (set_attr "sign_extend" "yes")])
1209 (define_insn ""
1210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1211 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1212 "!rs6000_gen_cell_microcode"
1213 "extsh %0,%1"
1214 [(set_attr "type" "exts")])
1216 (define_insn ""
1217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1218 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1219 (const_int 0)))
1220 (clobber (match_scratch:SI 2 "=r,r"))]
1221 ""
1222 "@
1223 extsh. %2,%1
1224 #"
1225 [(set_attr "type" "compare")
1226 (set_attr "length" "4,8")])
1228 (define_split
1229 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1230 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1231 (const_int 0)))
1232 (clobber (match_scratch:SI 2 ""))]
1233 "reload_completed"
1234 [(set (match_dup 2)
1235 (sign_extend:SI (match_dup 1)))
1236 (set (match_dup 0)
1237 (compare:CC (match_dup 2)
1238 (const_int 0)))]
1239 "")
1241 (define_insn ""
1242 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1243 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1244 (const_int 0)))
1245 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1246 (sign_extend:SI (match_dup 1)))]
1247 ""
1248 "@
1249 extsh. %0,%1
1250 #"
1251 [(set_attr "type" "compare")
1252 (set_attr "length" "4,8")])
1254 (define_split
1255 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1256 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1257 (const_int 0)))
1258 (set (match_operand:SI 0 "gpc_reg_operand" "")
1259 (sign_extend:SI (match_dup 1)))]
1260 "reload_completed"
1261 [(set (match_dup 0)
1262 (sign_extend:SI (match_dup 1)))
1263 (set (match_dup 2)
1264 (compare:CC (match_dup 0)
1265 (const_int 0)))]
1266 "")
1267 \f
1268 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1270 (define_insn "*macchwc"
1271 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1272 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1273 (match_operand:SI 2 "gpc_reg_operand" "r")
1274 (const_int 16))
1275 (sign_extend:SI
1276 (match_operand:HI 1 "gpc_reg_operand" "r")))
1277 (match_operand:SI 4 "gpc_reg_operand" "0"))
1278 (const_int 0)))
1279 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (plus:SI (mult:SI (ashiftrt:SI
1281 (match_dup 2)
1282 (const_int 16))
1283 (sign_extend:SI
1284 (match_dup 1)))
1285 (match_dup 4)))]
1286 "TARGET_MULHW"
1287 "macchw. %0,%1,%2"
1288 [(set_attr "type" "halfmul")])
1290 (define_insn "*macchw"
1291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1292 (plus:SI (mult:SI (ashiftrt:SI
1293 (match_operand:SI 2 "gpc_reg_operand" "r")
1294 (const_int 16))
1295 (sign_extend:SI
1296 (match_operand:HI 1 "gpc_reg_operand" "r")))
1297 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1298 "TARGET_MULHW"
1299 "macchw %0,%1,%2"
1300 [(set_attr "type" "halfmul")])
1302 (define_insn "*macchwuc"
1303 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1304 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1305 (match_operand:SI 2 "gpc_reg_operand" "r")
1306 (const_int 16))
1307 (zero_extend:SI
1308 (match_operand:HI 1 "gpc_reg_operand" "r")))
1309 (match_operand:SI 4 "gpc_reg_operand" "0"))
1310 (const_int 0)))
1311 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1312 (plus:SI (mult:SI (lshiftrt:SI
1313 (match_dup 2)
1314 (const_int 16))
1315 (zero_extend:SI
1316 (match_dup 1)))
1317 (match_dup 4)))]
1318 "TARGET_MULHW"
1319 "macchwu. %0,%1,%2"
1320 [(set_attr "type" "halfmul")])
1322 (define_insn "*macchwu"
1323 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1324 (plus:SI (mult:SI (lshiftrt:SI
1325 (match_operand:SI 2 "gpc_reg_operand" "r")
1326 (const_int 16))
1327 (zero_extend:SI
1328 (match_operand:HI 1 "gpc_reg_operand" "r")))
1329 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1330 "TARGET_MULHW"
1331 "macchwu %0,%1,%2"
1332 [(set_attr "type" "halfmul")])
1334 (define_insn "*machhwc"
1335 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1336 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1337 (match_operand:SI 1 "gpc_reg_operand" "%r")
1338 (const_int 16))
1339 (ashiftrt:SI
1340 (match_operand:SI 2 "gpc_reg_operand" "r")
1341 (const_int 16)))
1342 (match_operand:SI 4 "gpc_reg_operand" "0"))
1343 (const_int 0)))
1344 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1345 (plus:SI (mult:SI (ashiftrt:SI
1346 (match_dup 1)
1347 (const_int 16))
1348 (ashiftrt:SI
1349 (match_dup 2)
1350 (const_int 16)))
1351 (match_dup 4)))]
1352 "TARGET_MULHW"
1353 "machhw. %0,%1,%2"
1354 [(set_attr "type" "halfmul")])
1356 (define_insn "*machhw"
1357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1358 (plus:SI (mult:SI (ashiftrt:SI
1359 (match_operand:SI 1 "gpc_reg_operand" "%r")
1360 (const_int 16))
1361 (ashiftrt:SI
1362 (match_operand:SI 2 "gpc_reg_operand" "r")
1363 (const_int 16)))
1364 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1365 "TARGET_MULHW"
1366 "machhw %0,%1,%2"
1367 [(set_attr "type" "halfmul")])
1369 (define_insn "*machhwuc"
1370 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1371 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1372 (match_operand:SI 1 "gpc_reg_operand" "%r")
1373 (const_int 16))
1374 (lshiftrt:SI
1375 (match_operand:SI 2 "gpc_reg_operand" "r")
1376 (const_int 16)))
1377 (match_operand:SI 4 "gpc_reg_operand" "0"))
1378 (const_int 0)))
1379 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1380 (plus:SI (mult:SI (lshiftrt:SI
1381 (match_dup 1)
1382 (const_int 16))
1383 (lshiftrt:SI
1384 (match_dup 2)
1385 (const_int 16)))
1386 (match_dup 4)))]
1387 "TARGET_MULHW"
1388 "machhwu. %0,%1,%2"
1389 [(set_attr "type" "halfmul")])
1391 (define_insn "*machhwu"
1392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1393 (plus:SI (mult:SI (lshiftrt:SI
1394 (match_operand:SI 1 "gpc_reg_operand" "%r")
1395 (const_int 16))
1396 (lshiftrt:SI
1397 (match_operand:SI 2 "gpc_reg_operand" "r")
1398 (const_int 16)))
1399 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1400 "TARGET_MULHW"
1401 "machhwu %0,%1,%2"
1402 [(set_attr "type" "halfmul")])
1404 (define_insn "*maclhwc"
1405 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1406 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (sign_extend:SI
1409 (match_operand:HI 2 "gpc_reg_operand" "r")))
1410 (match_operand:SI 4 "gpc_reg_operand" "0"))
1411 (const_int 0)))
1412 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1413 (plus:SI (mult:SI (sign_extend:SI
1414 (match_dup 1))
1415 (sign_extend:SI
1416 (match_dup 2)))
1417 (match_dup 4)))]
1418 "TARGET_MULHW"
1419 "maclhw. %0,%1,%2"
1420 [(set_attr "type" "halfmul")])
1422 (define_insn "*maclhw"
1423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1424 (plus:SI (mult:SI (sign_extend:SI
1425 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1426 (sign_extend:SI
1427 (match_operand:HI 2 "gpc_reg_operand" "r")))
1428 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1429 "TARGET_MULHW"
1430 "maclhw %0,%1,%2"
1431 [(set_attr "type" "halfmul")])
1433 (define_insn "*maclhwuc"
1434 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1435 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1436 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1437 (zero_extend:SI
1438 (match_operand:HI 2 "gpc_reg_operand" "r")))
1439 (match_operand:SI 4 "gpc_reg_operand" "0"))
1440 (const_int 0)))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1442 (plus:SI (mult:SI (zero_extend:SI
1443 (match_dup 1))
1444 (zero_extend:SI
1445 (match_dup 2)))
1446 (match_dup 4)))]
1447 "TARGET_MULHW"
1448 "maclhwu. %0,%1,%2"
1449 [(set_attr "type" "halfmul")])
1451 (define_insn "*maclhwu"
1452 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1453 (plus:SI (mult:SI (zero_extend:SI
1454 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1455 (zero_extend:SI
1456 (match_operand:HI 2 "gpc_reg_operand" "r")))
1457 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1458 "TARGET_MULHW"
1459 "maclhwu %0,%1,%2"
1460 [(set_attr "type" "halfmul")])
1462 (define_insn "*nmacchwc"
1463 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1464 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1465 (mult:SI (ashiftrt:SI
1466 (match_operand:SI 2 "gpc_reg_operand" "r")
1467 (const_int 16))
1468 (sign_extend:SI
1469 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1470 (const_int 0)))
1471 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1472 (minus:SI (match_dup 4)
1473 (mult:SI (ashiftrt:SI
1474 (match_dup 2)
1475 (const_int 16))
1476 (sign_extend:SI
1477 (match_dup 1)))))]
1478 "TARGET_MULHW"
1479 "nmacchw. %0,%1,%2"
1480 [(set_attr "type" "halfmul")])
1482 (define_insn "*nmacchw"
1483 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1484 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1485 (mult:SI (ashiftrt:SI
1486 (match_operand:SI 2 "gpc_reg_operand" "r")
1487 (const_int 16))
1488 (sign_extend:SI
1489 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1490 "TARGET_MULHW"
1491 "nmacchw %0,%1,%2"
1492 [(set_attr "type" "halfmul")])
1494 (define_insn "*nmachhwc"
1495 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1496 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1497 (mult:SI (ashiftrt:SI
1498 (match_operand:SI 1 "gpc_reg_operand" "%r")
1499 (const_int 16))
1500 (ashiftrt:SI
1501 (match_operand:SI 2 "gpc_reg_operand" "r")
1502 (const_int 16))))
1503 (const_int 0)))
1504 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1505 (minus:SI (match_dup 4)
1506 (mult:SI (ashiftrt:SI
1507 (match_dup 1)
1508 (const_int 16))
1509 (ashiftrt:SI
1510 (match_dup 2)
1511 (const_int 16)))))]
1512 "TARGET_MULHW"
1513 "nmachhw. %0,%1,%2"
1514 [(set_attr "type" "halfmul")])
1516 (define_insn "*nmachhw"
1517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1518 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1519 (mult:SI (ashiftrt:SI
1520 (match_operand:SI 1 "gpc_reg_operand" "%r")
1521 (const_int 16))
1522 (ashiftrt:SI
1523 (match_operand:SI 2 "gpc_reg_operand" "r")
1524 (const_int 16)))))]
1525 "TARGET_MULHW"
1526 "nmachhw %0,%1,%2"
1527 [(set_attr "type" "halfmul")])
1529 (define_insn "*nmaclhwc"
1530 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1531 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1532 (mult:SI (sign_extend:SI
1533 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1534 (sign_extend:SI
1535 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1536 (const_int 0)))
1537 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1538 (minus:SI (match_dup 4)
1539 (mult:SI (sign_extend:SI
1540 (match_dup 1))
1541 (sign_extend:SI
1542 (match_dup 2)))))]
1543 "TARGET_MULHW"
1544 "nmaclhw. %0,%1,%2"
1545 [(set_attr "type" "halfmul")])
1547 (define_insn "*nmaclhw"
1548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1549 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1550 (mult:SI (sign_extend:SI
1551 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1552 (sign_extend:SI
1553 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1554 "TARGET_MULHW"
1555 "nmaclhw %0,%1,%2"
1556 [(set_attr "type" "halfmul")])
1558 (define_insn "*mulchwc"
1559 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1560 (compare:CC (mult:SI (ashiftrt:SI
1561 (match_operand:SI 2 "gpc_reg_operand" "r")
1562 (const_int 16))
1563 (sign_extend:SI
1564 (match_operand:HI 1 "gpc_reg_operand" "r")))
1565 (const_int 0)))
1566 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1567 (mult:SI (ashiftrt:SI
1568 (match_dup 2)
1569 (const_int 16))
1570 (sign_extend:SI
1571 (match_dup 1))))]
1572 "TARGET_MULHW"
1573 "mulchw. %0,%1,%2"
1574 [(set_attr "type" "halfmul")])
1576 (define_insn "*mulchw"
1577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1578 (mult:SI (ashiftrt:SI
1579 (match_operand:SI 2 "gpc_reg_operand" "r")
1580 (const_int 16))
1581 (sign_extend:SI
1582 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1583 "TARGET_MULHW"
1584 "mulchw %0,%1,%2"
1585 [(set_attr "type" "halfmul")])
1587 (define_insn "*mulchwuc"
1588 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1589 (compare:CC (mult:SI (lshiftrt:SI
1590 (match_operand:SI 2 "gpc_reg_operand" "r")
1591 (const_int 16))
1592 (zero_extend:SI
1593 (match_operand:HI 1 "gpc_reg_operand" "r")))
1594 (const_int 0)))
1595 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1596 (mult:SI (lshiftrt:SI
1597 (match_dup 2)
1598 (const_int 16))
1599 (zero_extend:SI
1600 (match_dup 1))))]
1601 "TARGET_MULHW"
1602 "mulchwu. %0,%1,%2"
1603 [(set_attr "type" "halfmul")])
1605 (define_insn "*mulchwu"
1606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1607 (mult:SI (lshiftrt:SI
1608 (match_operand:SI 2 "gpc_reg_operand" "r")
1609 (const_int 16))
1610 (zero_extend:SI
1611 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1612 "TARGET_MULHW"
1613 "mulchwu %0,%1,%2"
1614 [(set_attr "type" "halfmul")])
1616 (define_insn "*mulhhwc"
1617 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1618 (compare:CC (mult:SI (ashiftrt:SI
1619 (match_operand:SI 1 "gpc_reg_operand" "%r")
1620 (const_int 16))
1621 (ashiftrt:SI
1622 (match_operand:SI 2 "gpc_reg_operand" "r")
1623 (const_int 16)))
1624 (const_int 0)))
1625 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1626 (mult:SI (ashiftrt:SI
1627 (match_dup 1)
1628 (const_int 16))
1629 (ashiftrt:SI
1630 (match_dup 2)
1631 (const_int 16))))]
1632 "TARGET_MULHW"
1633 "mulhhw. %0,%1,%2"
1634 [(set_attr "type" "halfmul")])
1636 (define_insn "*mulhhw"
1637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1638 (mult:SI (ashiftrt:SI
1639 (match_operand:SI 1 "gpc_reg_operand" "%r")
1640 (const_int 16))
1641 (ashiftrt:SI
1642 (match_operand:SI 2 "gpc_reg_operand" "r")
1643 (const_int 16))))]
1644 "TARGET_MULHW"
1645 "mulhhw %0,%1,%2"
1646 [(set_attr "type" "halfmul")])
1648 (define_insn "*mulhhwuc"
1649 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1650 (compare:CC (mult:SI (lshiftrt:SI
1651 (match_operand:SI 1 "gpc_reg_operand" "%r")
1652 (const_int 16))
1653 (lshiftrt:SI
1654 (match_operand:SI 2 "gpc_reg_operand" "r")
1655 (const_int 16)))
1656 (const_int 0)))
1657 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1658 (mult:SI (lshiftrt:SI
1659 (match_dup 1)
1660 (const_int 16))
1661 (lshiftrt:SI
1662 (match_dup 2)
1663 (const_int 16))))]
1664 "TARGET_MULHW"
1665 "mulhhwu. %0,%1,%2"
1666 [(set_attr "type" "halfmul")])
1668 (define_insn "*mulhhwu"
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1670 (mult:SI (lshiftrt:SI
1671 (match_operand:SI 1 "gpc_reg_operand" "%r")
1672 (const_int 16))
1673 (lshiftrt:SI
1674 (match_operand:SI 2 "gpc_reg_operand" "r")
1675 (const_int 16))))]
1676 "TARGET_MULHW"
1677 "mulhhwu %0,%1,%2"
1678 [(set_attr "type" "halfmul")])
1680 (define_insn "*mullhwc"
1681 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1682 (compare:CC (mult:SI (sign_extend:SI
1683 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1684 (sign_extend:SI
1685 (match_operand:HI 2 "gpc_reg_operand" "r")))
1686 (const_int 0)))
1687 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1688 (mult:SI (sign_extend:SI
1689 (match_dup 1))
1690 (sign_extend:SI
1691 (match_dup 2))))]
1692 "TARGET_MULHW"
1693 "mullhw. %0,%1,%2"
1694 [(set_attr "type" "halfmul")])
1696 (define_insn "*mullhw"
1697 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1698 (mult:SI (sign_extend:SI
1699 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1700 (sign_extend:SI
1701 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1702 "TARGET_MULHW"
1703 "mullhw %0,%1,%2"
1704 [(set_attr "type" "halfmul")])
1706 (define_insn "*mullhwuc"
1707 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1708 (compare:CC (mult:SI (zero_extend:SI
1709 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1710 (zero_extend:SI
1711 (match_operand:HI 2 "gpc_reg_operand" "r")))
1712 (const_int 0)))
1713 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1714 (mult:SI (zero_extend:SI
1715 (match_dup 1))
1716 (zero_extend:SI
1717 (match_dup 2))))]
1718 "TARGET_MULHW"
1719 "mullhwu. %0,%1,%2"
1720 [(set_attr "type" "halfmul")])
1722 (define_insn "*mullhwu"
1723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1724 (mult:SI (zero_extend:SI
1725 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1726 (zero_extend:SI
1727 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1728 "TARGET_MULHW"
1729 "mullhwu %0,%1,%2"
1730 [(set_attr "type" "halfmul")])
1731 \f
1732 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1733 (define_insn "dlmzb"
1734 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1735 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1736 (match_operand:SI 2 "gpc_reg_operand" "r")]
1737 UNSPEC_DLMZB_CR))
1738 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1739 (unspec:SI [(match_dup 1)
1740 (match_dup 2)]
1741 UNSPEC_DLMZB))]
1742 "TARGET_DLMZB"
1743 "dlmzb. %0,%1,%2")
1745 (define_expand "strlensi"
1746 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1747 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1748 (match_operand:QI 2 "const_int_operand" "")
1749 (match_operand 3 "const_int_operand" "")]
1750 UNSPEC_DLMZB_STRLEN))
1751 (clobber (match_scratch:CC 4 "=x"))]
1752 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1753 {
1754 rtx result = operands[0];
1755 rtx src = operands[1];
1756 rtx search_char = operands[2];
1757 rtx align = operands[3];
1758 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1759 rtx loop_label, end_label, mem, cr0, cond;
1760 if (search_char != const0_rtx
1761 || GET_CODE (align) != CONST_INT
1762 || INTVAL (align) < 8)
1763 FAIL;
1764 word1 = gen_reg_rtx (SImode);
1765 word2 = gen_reg_rtx (SImode);
1766 scratch_dlmzb = gen_reg_rtx (SImode);
1767 scratch_string = gen_reg_rtx (Pmode);
1768 loop_label = gen_label_rtx ();
1769 end_label = gen_label_rtx ();
1770 addr = force_reg (Pmode, XEXP (src, 0));
1771 emit_move_insn (scratch_string, addr);
1772 emit_label (loop_label);
1773 mem = change_address (src, SImode, scratch_string);
1774 emit_move_insn (word1, mem);
1775 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1776 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1777 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1778 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1779 emit_jump_insn (gen_rtx_SET (VOIDmode,
1780 pc_rtx,
1781 gen_rtx_IF_THEN_ELSE (VOIDmode,
1782 cond,
1783 gen_rtx_LABEL_REF
1784 (VOIDmode,
1785 end_label),
1786 pc_rtx)));
1787 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1788 emit_jump_insn (gen_rtx_SET (VOIDmode,
1789 pc_rtx,
1790 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1791 emit_barrier ();
1792 emit_label (end_label);
1793 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1794 emit_insn (gen_subsi3 (result, scratch_string, addr));
1795 emit_insn (gen_subsi3 (result, result, const1_rtx));
1796 DONE;
1797 })
1798 \f
1799 ;; Fixed-point arithmetic insns.
1801 (define_expand "add<mode>3"
1802 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1803 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1804 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1805 ""
1806 {
1807 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1808 {
1809 if (non_short_cint_operand (operands[2], DImode))
1810 FAIL;
1811 }
1812 else if (GET_CODE (operands[2]) == CONST_INT
1813 && ! add_operand (operands[2], <MODE>mode))
1814 {
1815 rtx tmp = ((!can_create_pseudo_p ()
1816 || rtx_equal_p (operands[0], operands[1]))
1817 ? operands[0] : gen_reg_rtx (<MODE>mode));
1819 HOST_WIDE_INT val = INTVAL (operands[2]);
1820 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1821 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1823 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1824 FAIL;
1826 /* The ordering here is important for the prolog expander.
1827 When space is allocated from the stack, adding 'low' first may
1828 produce a temporary deallocation (which would be bad). */
1829 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1830 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1831 DONE;
1832 }
1833 })
1835 ;; Discourage ai/addic because of carry but provide it in an alternative
1836 ;; allowing register zero as source.
1837 (define_insn "*add<mode>3_internal1"
1838 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1839 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1840 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1841 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1842 "@
1843 add %0,%1,%2
1844 addi %0,%1,%2
1845 addic %0,%1,%2
1846 addis %0,%1,%v2"
1847 [(set_attr "type" "add")])
1849 (define_insn "addsi3_high"
1850 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1851 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1852 (high:SI (match_operand 2 "" ""))))]
1853 "TARGET_MACHO && !TARGET_64BIT"
1854 "addis %0,%1,ha16(%2)"
1855 [(set_attr "type" "add")])
1857 (define_insn "*add<mode>3_internal2"
1858 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1859 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1860 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1861 (const_int 0)))
1862 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1863 ""
1864 "@
1865 add. %3,%1,%2
1866 addic. %3,%1,%2
1867 #
1868 #"
1869 [(set_attr "type" "add,compare,compare,compare")
1870 (set_attr "dot" "yes")
1871 (set_attr "length" "4,4,8,8")])
1873 (define_split
1874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1875 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1876 (match_operand:GPR 2 "reg_or_short_operand" ""))
1877 (const_int 0)))
1878 (clobber (match_scratch:GPR 3 ""))]
1879 "reload_completed"
1880 [(set (match_dup 3)
1881 (plus:GPR (match_dup 1)
1882 (match_dup 2)))
1883 (set (match_dup 0)
1884 (compare:CC (match_dup 3)
1885 (const_int 0)))]
1886 "")
1888 (define_insn "*add<mode>3_internal3"
1889 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1890 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1891 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1892 (const_int 0)))
1893 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1894 (plus:P (match_dup 1)
1895 (match_dup 2)))]
1896 ""
1897 "@
1898 add. %0,%1,%2
1899 addic. %0,%1,%2
1900 #
1901 #"
1902 [(set_attr "type" "add,compare,compare,compare")
1903 (set_attr "dot" "yes")
1904 (set_attr "length" "4,4,8,8")])
1906 (define_split
1907 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1908 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1909 (match_operand:P 2 "reg_or_short_operand" ""))
1910 (const_int 0)))
1911 (set (match_operand:P 0 "gpc_reg_operand" "")
1912 (plus:P (match_dup 1) (match_dup 2)))]
1913 "reload_completed"
1914 [(set (match_dup 0)
1915 (plus:P (match_dup 1)
1916 (match_dup 2)))
1917 (set (match_dup 3)
1918 (compare:CC (match_dup 0)
1919 (const_int 0)))]
1920 "")
1922 ;; Split an add that we can't do in one insn into two insns, each of which
1923 ;; does one 16-bit part. This is used by combine. Note that the low-order
1924 ;; add should be last in case the result gets used in an address.
1926 (define_split
1927 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1928 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1929 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1930 ""
1931 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1932 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1933 {
1934 HOST_WIDE_INT val = INTVAL (operands[2]);
1935 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1936 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1938 operands[4] = GEN_INT (low);
1939 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1940 operands[3] = GEN_INT (rest);
1941 else if (can_create_pseudo_p ())
1942 {
1943 operands[3] = gen_reg_rtx (DImode);
1944 emit_move_insn (operands[3], operands[2]);
1945 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1946 DONE;
1947 }
1948 else
1949 FAIL;
1950 })
1952 (define_expand "one_cmpl<mode>2"
1953 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1954 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1955 ""
1956 {
1957 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1958 {
1959 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
1960 DONE;
1961 }
1962 })
1964 (define_insn "*one_cmpl<mode>2"
1965 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1966 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1967 ""
1968 "nor %0,%1,%1")
1970 (define_insn ""
1971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1972 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1973 (const_int 0)))
1974 (clobber (match_scratch:P 2 "=r,r"))]
1975 ""
1976 "@
1977 nor. %2,%1,%1
1978 #"
1979 [(set_attr "type" "logical,compare")
1980 (set_attr "dot" "yes")
1981 (set_attr "length" "4,8")])
1983 (define_split
1984 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1985 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1986 (const_int 0)))
1987 (clobber (match_scratch:P 2 ""))]
1988 "reload_completed"
1989 [(set (match_dup 2)
1990 (not:P (match_dup 1)))
1991 (set (match_dup 0)
1992 (compare:CC (match_dup 2)
1993 (const_int 0)))]
1994 "")
1996 (define_insn ""
1997 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1998 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1999 (const_int 0)))
2000 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2001 (not:P (match_dup 1)))]
2002 ""
2003 "@
2004 nor. %0,%1,%1
2005 #"
2006 [(set_attr "type" "logical,compare")
2007 (set_attr "dot" "yes")
2008 (set_attr "length" "4,8")])
2010 (define_split
2011 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
2012 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
2013 (const_int 0)))
2014 (set (match_operand:P 0 "gpc_reg_operand" "")
2015 (not:P (match_dup 1)))]
2016 "reload_completed"
2017 [(set (match_dup 0)
2018 (not:P (match_dup 1)))
2019 (set (match_dup 2)
2020 (compare:CC (match_dup 0)
2021 (const_int 0)))]
2022 "")
2024 (define_insn ""
2025 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2026 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
2027 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
2028 ""
2029 "@
2030 subf %0,%2,%1
2031 subfic %0,%2,%1"
2032 [(set_attr "type" "add")])
2034 (define_insn ""
2035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2036 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2037 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2038 (const_int 0)))
2039 (clobber (match_scratch:P 3 "=r,r"))]
2040 ""
2041 "@
2042 subf. %3,%2,%1
2043 #"
2044 [(set_attr "type" "add")
2045 (set_attr "dot" "yes")
2046 (set_attr "length" "4,8")])
2048 (define_split
2049 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2050 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2051 (match_operand:P 2 "gpc_reg_operand" ""))
2052 (const_int 0)))
2053 (clobber (match_scratch:P 3 ""))]
2054 "reload_completed"
2055 [(set (match_dup 3)
2056 (minus:P (match_dup 1)
2057 (match_dup 2)))
2058 (set (match_dup 0)
2059 (compare:CC (match_dup 3)
2060 (const_int 0)))]
2061 "")
2063 (define_insn ""
2064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2065 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2066 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2067 (const_int 0)))
2068 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2069 (minus:P (match_dup 1)
2070 (match_dup 2)))]
2071 ""
2072 "@
2073 subf. %0,%2,%1
2074 #"
2075 [(set_attr "type" "add")
2076 (set_attr "dot" "yes")
2077 (set_attr "length" "4,8")])
2079 (define_split
2080 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2081 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2082 (match_operand:P 2 "gpc_reg_operand" ""))
2083 (const_int 0)))
2084 (set (match_operand:P 0 "gpc_reg_operand" "")
2085 (minus:P (match_dup 1)
2086 (match_dup 2)))]
2087 "reload_completed"
2088 [(set (match_dup 0)
2089 (minus:P (match_dup 1)
2090 (match_dup 2)))
2091 (set (match_dup 3)
2092 (compare:CC (match_dup 0)
2093 (const_int 0)))]
2094 "")
2096 (define_expand "sub<mode>3"
2097 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2098 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
2099 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
2100 ""
2101 "
2102 {
2103 if (GET_CODE (operands[2]) == CONST_INT)
2104 {
2105 emit_insn (gen_add<mode>3 (operands[0], operands[1],
2106 negate_rtx (<MODE>mode, operands[2])));
2107 DONE;
2108 }
2109 }")
2111 (define_expand "neg<mode>2"
2112 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2113 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2114 ""
2115 "")
2117 (define_insn "*neg<mode>2_internal"
2118 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2119 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2120 ""
2121 "neg %0,%1"
2122 [(set_attr "type" "add")])
2124 (define_insn ""
2125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2126 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2127 (const_int 0)))
2128 (clobber (match_scratch:P 2 "=r,r"))]
2129 ""
2130 "@
2131 neg. %2,%1
2132 #"
2133 [(set_attr "type" "add")
2134 (set_attr "dot" "yes")
2135 (set_attr "length" "4,8")])
2137 (define_split
2138 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2139 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2140 (const_int 0)))
2141 (clobber (match_scratch:P 2 ""))]
2142 "reload_completed"
2143 [(set (match_dup 2)
2144 (neg:P (match_dup 1)))
2145 (set (match_dup 0)
2146 (compare:CC (match_dup 2)
2147 (const_int 0)))]
2148 "")
2150 (define_insn ""
2151 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2152 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2153 (const_int 0)))
2154 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2155 (neg:P (match_dup 1)))]
2156 ""
2157 "@
2158 neg. %0,%1
2159 #"
2160 [(set_attr "type" "add")
2161 (set_attr "dot" "yes")
2162 (set_attr "length" "4,8")])
2164 (define_split
2165 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2166 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2167 (const_int 0)))
2168 (set (match_operand:P 0 "gpc_reg_operand" "")
2169 (neg:P (match_dup 1)))]
2170 "reload_completed"
2171 [(set (match_dup 0)
2172 (neg:P (match_dup 1)))
2173 (set (match_dup 2)
2174 (compare:CC (match_dup 0)
2175 (const_int 0)))]
2176 "")
2178 (define_insn "clz<mode>2"
2179 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2180 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2181 ""
2182 "cntlz<wd> %0,%1"
2183 [(set_attr "type" "cntlz")])
2185 (define_expand "ctz<mode>2"
2186 [(set (match_dup 2)
2187 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2188 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2189 (match_dup 2)))
2190 (clobber (scratch:CC))])
2191 (set (match_dup 4) (clz:GPR (match_dup 3)))
2192 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2193 (minus:GPR (match_dup 5) (match_dup 4)))]
2194 ""
2195 {
2196 operands[2] = gen_reg_rtx (<MODE>mode);
2197 operands[3] = gen_reg_rtx (<MODE>mode);
2198 operands[4] = gen_reg_rtx (<MODE>mode);
2199 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2200 })
2202 (define_expand "ffs<mode>2"
2203 [(set (match_dup 2)
2204 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2205 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2206 (match_dup 2)))
2207 (clobber (scratch:CC))])
2208 (set (match_dup 4) (clz:GPR (match_dup 3)))
2209 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2210 (minus:GPR (match_dup 5) (match_dup 4)))]
2211 ""
2212 {
2213 operands[2] = gen_reg_rtx (<MODE>mode);
2214 operands[3] = gen_reg_rtx (<MODE>mode);
2215 operands[4] = gen_reg_rtx (<MODE>mode);
2216 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2217 })
2219 (define_insn "popcntb<mode>2"
2220 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2221 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2222 UNSPEC_POPCNTB))]
2223 "TARGET_POPCNTB"
2224 "popcntb %0,%1"
2225 [(set_attr "length" "4")
2226 (set_attr "type" "popcnt")])
2228 (define_insn "popcntd<mode>2"
2229 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2230 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2231 "TARGET_POPCNTD"
2232 "popcnt<wd> %0,%1"
2233 [(set_attr "length" "4")
2234 (set_attr "type" "popcnt")])
2236 (define_expand "popcount<mode>2"
2237 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2238 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2239 "TARGET_POPCNTB || TARGET_POPCNTD"
2240 {
2241 rs6000_emit_popcount (operands[0], operands[1]);
2242 DONE;
2243 })
2245 (define_insn "parity<mode>2_cmpb"
2246 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2247 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2248 "TARGET_CMPB && TARGET_POPCNTB"
2249 "prty<wd> %0,%1"
2250 [(set_attr "length" "4")
2251 (set_attr "type" "popcnt")])
2253 (define_expand "parity<mode>2"
2254 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2255 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2256 "TARGET_POPCNTB"
2257 {
2258 rs6000_emit_parity (operands[0], operands[1]);
2259 DONE;
2260 })
2262 ;; Since the hardware zeros the upper part of the register, save generating the
2263 ;; AND immediate if we are converting to unsigned
2264 (define_insn "*bswaphi2_extenddi"
2265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2266 (zero_extend:DI
2267 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2268 "TARGET_POWERPC64"
2269 "lhbrx %0,%y1"
2270 [(set_attr "length" "4")
2271 (set_attr "type" "load")])
2273 (define_insn "*bswaphi2_extendsi"
2274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2275 (zero_extend:SI
2276 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2277 ""
2278 "lhbrx %0,%y1"
2279 [(set_attr "length" "4")
2280 (set_attr "type" "load")])
2282 (define_expand "bswaphi2"
2283 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2284 (bswap:HI
2285 (match_operand:HI 1 "reg_or_mem_operand" "")))
2286 (clobber (match_scratch:SI 2 ""))])]
2287 ""
2288 {
2289 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2290 operands[1] = force_reg (HImode, operands[1]);
2291 })
2293 (define_insn "bswaphi2_internal"
2294 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2295 (bswap:HI
2296 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2297 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2298 ""
2299 "@
2300 lhbrx %0,%y1
2301 sthbrx %1,%y0
2302 #"
2303 [(set_attr "length" "4,4,12")
2304 (set_attr "type" "load,store,*")])
2306 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2307 ;; correct for -mlittle as well as -mbig.
2308 (define_split
2309 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2310 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2311 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2312 "reload_completed"
2313 [(set (match_dup 3)
2314 (zero_extract:SI (match_dup 4)
2315 (const_int 8)
2316 (const_int 16)))
2317 (set (match_dup 2)
2318 (and:SI (ashift:SI (match_dup 4)
2319 (const_int 8))
2320 (const_int 65280))) ;; 0xff00
2321 (set (match_dup 3)
2322 (ior:SI (match_dup 3)
2323 (match_dup 2)))]
2324 "
2325 {
2326 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2327 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2328 }")
2330 (define_insn "*bswapsi2_extenddi"
2331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2332 (zero_extend:DI
2333 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2334 "TARGET_POWERPC64"
2335 "lwbrx %0,%y1"
2336 [(set_attr "length" "4")
2337 (set_attr "type" "load")])
2339 (define_expand "bswapsi2"
2340 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2341 (bswap:SI
2342 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2343 ""
2344 {
2345 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2346 operands[1] = force_reg (SImode, operands[1]);
2347 })
2349 (define_insn "*bswapsi2_internal"
2350 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2351 (bswap:SI
2352 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2353 ""
2354 "@
2355 lwbrx %0,%y1
2356 stwbrx %1,%y0
2357 #"
2358 [(set_attr "length" "4,4,12")
2359 (set_attr "type" "load,store,*")])
2361 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2362 ;; zero_extract insns do not change for -mlittle.
2363 (define_split
2364 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2365 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2366 "reload_completed"
2367 [(set (match_dup 0)
2368 (rotate:SI (match_dup 1) (const_int 8)))
2369 (set (zero_extract:SI (match_dup 0)
2370 (const_int 8)
2371 (const_int 0))
2372 (match_dup 1))
2373 (set (zero_extract:SI (match_dup 0)
2374 (const_int 8)
2375 (const_int 16))
2376 (rotate:SI (match_dup 1)
2377 (const_int 16)))]
2378 "")
2380 (define_expand "bswapdi2"
2381 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2382 (bswap:DI
2383 (match_operand:DI 1 "reg_or_mem_operand" "")))
2384 (clobber (match_scratch:DI 2 ""))
2385 (clobber (match_scratch:DI 3 ""))
2386 (clobber (match_scratch:DI 4 ""))])]
2387 ""
2388 {
2389 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2390 operands[1] = force_reg (DImode, operands[1]);
2392 if (!TARGET_POWERPC64)
2393 {
2394 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2395 that uses 64-bit registers needs the same scratch registers as 64-bit
2396 mode. */
2397 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2398 DONE;
2399 }
2400 })
2402 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2403 (define_insn "*bswapdi2_ldbrx"
2404 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2405 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2406 (clobber (match_scratch:DI 2 "=X,X,&r"))
2407 (clobber (match_scratch:DI 3 "=X,X,&r"))
2408 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2409 "TARGET_POWERPC64 && TARGET_LDBRX
2410 && (REG_P (operands[0]) || REG_P (operands[1]))"
2411 "@
2412 ldbrx %0,%y1
2413 stdbrx %1,%y0
2414 #"
2415 [(set_attr "length" "4,4,36")
2416 (set_attr "type" "load,store,*")])
2418 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2419 (define_insn "*bswapdi2_64bit"
2420 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2421 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2422 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2423 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2424 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2425 "TARGET_POWERPC64 && !TARGET_LDBRX
2426 && (REG_P (operands[0]) || REG_P (operands[1]))
2427 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2428 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2429 "#"
2430 [(set_attr "length" "16,12,36")])
2432 (define_split
2433 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2434 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2435 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2436 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2437 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2438 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2439 [(const_int 0)]
2440 "
2441 {
2442 rtx dest = operands[0];
2443 rtx src = operands[1];
2444 rtx op2 = operands[2];
2445 rtx op3 = operands[3];
2446 rtx op4 = operands[4];
2447 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2448 BYTES_BIG_ENDIAN ? 4 : 0);
2449 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2450 BYTES_BIG_ENDIAN ? 4 : 0);
2451 rtx addr1;
2452 rtx addr2;
2453 rtx word_high;
2454 rtx word_low;
2456 addr1 = XEXP (src, 0);
2457 if (GET_CODE (addr1) == PLUS)
2458 {
2459 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2460 if (TARGET_AVOID_XFORM)
2461 {
2462 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2463 addr2 = op2;
2464 }
2465 else
2466 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2467 }
2468 else if (TARGET_AVOID_XFORM)
2469 {
2470 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2471 addr2 = op2;
2472 }
2473 else
2474 {
2475 emit_move_insn (op2, GEN_INT (4));
2476 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2477 }
2479 if (BYTES_BIG_ENDIAN)
2480 {
2481 word_high = change_address (src, SImode, addr1);
2482 word_low = change_address (src, SImode, addr2);
2483 }
2484 else
2485 {
2486 word_high = change_address (src, SImode, addr2);
2487 word_low = change_address (src, SImode, addr1);
2488 }
2490 emit_insn (gen_bswapsi2 (op3_32, word_low));
2491 emit_insn (gen_bswapsi2 (op4_32, word_high));
2492 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2493 emit_insn (gen_iordi3 (dest, dest, op4));
2494 DONE;
2495 }")
2497 (define_split
2498 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2499 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2500 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2501 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2502 (clobber (match_operand:DI 4 "" ""))]
2503 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2504 [(const_int 0)]
2505 "
2506 {
2507 rtx dest = operands[0];
2508 rtx src = operands[1];
2509 rtx op2 = operands[2];
2510 rtx op3 = operands[3];
2511 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2512 BYTES_BIG_ENDIAN ? 4 : 0);
2513 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2514 BYTES_BIG_ENDIAN ? 4 : 0);
2515 rtx addr1;
2516 rtx addr2;
2517 rtx word_high;
2518 rtx word_low;
2520 addr1 = XEXP (dest, 0);
2521 if (GET_CODE (addr1) == PLUS)
2522 {
2523 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2524 if (TARGET_AVOID_XFORM)
2525 {
2526 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2527 addr2 = op2;
2528 }
2529 else
2530 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2531 }
2532 else if (TARGET_AVOID_XFORM)
2533 {
2534 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2535 addr2 = op2;
2536 }
2537 else
2538 {
2539 emit_move_insn (op2, GEN_INT (4));
2540 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2541 }
2543 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2544 if (BYTES_BIG_ENDIAN)
2545 {
2546 word_high = change_address (dest, SImode, addr1);
2547 word_low = change_address (dest, SImode, addr2);
2548 }
2549 else
2550 {
2551 word_high = change_address (dest, SImode, addr2);
2552 word_low = change_address (dest, SImode, addr1);
2553 }
2554 emit_insn (gen_bswapsi2 (word_high, src_si));
2555 emit_insn (gen_bswapsi2 (word_low, op3_si));
2556 DONE;
2557 }")
2559 (define_split
2560 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2561 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2562 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2563 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2564 (clobber (match_operand:DI 4 "" ""))]
2565 "TARGET_POWERPC64 && reload_completed"
2566 [(const_int 0)]
2567 "
2568 {
2569 rtx dest = operands[0];
2570 rtx src = operands[1];
2571 rtx op2 = operands[2];
2572 rtx op3 = operands[3];
2573 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2574 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2575 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2576 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2577 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2579 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2580 emit_insn (gen_bswapsi2 (dest_si, src_si));
2581 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2582 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2583 emit_insn (gen_iordi3 (dest, dest, op3));
2584 DONE;
2585 }")
2587 (define_insn "bswapdi2_32bit"
2588 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2589 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2590 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2591 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2592 "#"
2593 [(set_attr "length" "16,12,36")])
2595 (define_split
2596 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2597 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2598 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2599 "!TARGET_POWERPC64 && reload_completed"
2600 [(const_int 0)]
2601 "
2602 {
2603 rtx dest = operands[0];
2604 rtx src = operands[1];
2605 rtx op2 = operands[2];
2606 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2607 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2608 rtx addr1;
2609 rtx addr2;
2610 rtx word1;
2611 rtx word2;
2613 addr1 = XEXP (src, 0);
2614 if (GET_CODE (addr1) == PLUS)
2615 {
2616 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2617 if (TARGET_AVOID_XFORM)
2618 {
2619 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2620 addr2 = op2;
2621 }
2622 else
2623 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2624 }
2625 else if (TARGET_AVOID_XFORM)
2626 {
2627 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2628 addr2 = op2;
2629 }
2630 else
2631 {
2632 emit_move_insn (op2, GEN_INT (4));
2633 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2634 }
2636 word1 = change_address (src, SImode, addr1);
2637 word2 = change_address (src, SImode, addr2);
2639 emit_insn (gen_bswapsi2 (dest2, word1));
2640 emit_insn (gen_bswapsi2 (dest1, word2));
2641 DONE;
2642 }")
2644 (define_split
2645 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2646 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2647 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2648 "!TARGET_POWERPC64 && reload_completed"
2649 [(const_int 0)]
2650 "
2651 {
2652 rtx dest = operands[0];
2653 rtx src = operands[1];
2654 rtx op2 = operands[2];
2655 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2656 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2657 rtx addr1;
2658 rtx addr2;
2659 rtx word1;
2660 rtx word2;
2662 addr1 = XEXP (dest, 0);
2663 if (GET_CODE (addr1) == PLUS)
2664 {
2665 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2666 if (TARGET_AVOID_XFORM)
2667 {
2668 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2669 addr2 = op2;
2670 }
2671 else
2672 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2673 }
2674 else if (TARGET_AVOID_XFORM)
2675 {
2676 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2677 addr2 = op2;
2678 }
2679 else
2680 {
2681 emit_move_insn (op2, GEN_INT (4));
2682 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2683 }
2685 word1 = change_address (dest, SImode, addr1);
2686 word2 = change_address (dest, SImode, addr2);
2688 emit_insn (gen_bswapsi2 (word2, src1));
2689 emit_insn (gen_bswapsi2 (word1, src2));
2690 DONE;
2691 }")
2693 (define_split
2694 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2695 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2696 (clobber (match_operand:SI 2 "" ""))]
2697 "!TARGET_POWERPC64 && reload_completed"
2698 [(const_int 0)]
2699 "
2700 {
2701 rtx dest = operands[0];
2702 rtx src = operands[1];
2703 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2704 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2705 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2706 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2708 emit_insn (gen_bswapsi2 (dest1, src2));
2709 emit_insn (gen_bswapsi2 (dest2, src1));
2710 DONE;
2711 }")
2713 (define_insn "mulsi3"
2714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2715 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2716 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2717 ""
2718 "@
2719 mullw %0,%1,%2
2720 mulli %0,%1,%2"
2721 [(set_attr "type" "mul")
2722 (set (attr "size")
2723 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2724 (const_string "8")
2725 (match_operand:SI 2 "short_cint_operand" "")
2726 (const_string "16")]
2727 (const_string "32")))])
2729 (define_insn "*mulsi3_internal1"
2730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2732 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2733 (const_int 0)))
2734 (clobber (match_scratch:SI 3 "=r,r"))]
2735 "TARGET_32BIT"
2736 "@
2737 mullw. %3,%1,%2
2738 #"
2739 [(set_attr "type" "mul")
2740 (set_attr "dot" "yes")
2741 (set_attr "length" "4,8")])
2743 (define_split
2744 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2745 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2746 (match_operand:SI 2 "gpc_reg_operand" ""))
2747 (const_int 0)))
2748 (clobber (match_scratch:SI 3 ""))]
2749 "TARGET_32BIT && reload_completed"
2750 [(set (match_dup 3)
2751 (mult:SI (match_dup 1) (match_dup 2)))
2752 (set (match_dup 0)
2753 (compare:CC (match_dup 3)
2754 (const_int 0)))]
2755 "")
2757 (define_insn "*mulsi3_internal2"
2758 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2759 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2760 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2761 (const_int 0)))
2762 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2763 (mult:SI (match_dup 1) (match_dup 2)))]
2764 "TARGET_32BIT"
2765 "@
2766 mullw. %0,%1,%2
2767 #"
2768 [(set_attr "type" "mul")
2769 (set_attr "dot" "yes")
2770 (set_attr "length" "4,8")])
2772 (define_split
2773 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2774 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2775 (match_operand:SI 2 "gpc_reg_operand" ""))
2776 (const_int 0)))
2777 (set (match_operand:SI 0 "gpc_reg_operand" "")
2778 (mult:SI (match_dup 1) (match_dup 2)))]
2779 "TARGET_32BIT && reload_completed"
2780 [(set (match_dup 0)
2781 (mult:SI (match_dup 1) (match_dup 2)))
2782 (set (match_dup 3)
2783 (compare:CC (match_dup 0)
2784 (const_int 0)))]
2785 "")
2788 (define_insn "udiv<mode>3"
2789 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2790 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2791 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2792 ""
2793 "div<wd>u %0,%1,%2"
2794 [(set_attr "type" "div")
2795 (set_attr "size" "<bits>")])
2798 ;; For powers of two we can do srai/aze for divide and then adjust for
2799 ;; modulus. If it isn't a power of two, force operands into register and do
2800 ;; a normal divide.
2801 (define_expand "div<mode>3"
2802 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2803 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2804 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2805 ""
2806 {
2807 if (GET_CODE (operands[2]) != CONST_INT
2808 || INTVAL (operands[2]) <= 0
2809 || exact_log2 (INTVAL (operands[2])) < 0)
2810 operands[2] = force_reg (<MODE>mode, operands[2]);
2811 })
2813 (define_insn "*div<mode>3"
2814 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2815 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2816 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2817 ""
2818 "div<wd> %0,%1,%2"
2819 [(set_attr "type" "div")
2820 (set_attr "size" "<bits>")])
2822 (define_expand "mod<mode>3"
2823 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2824 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2825 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2826 ""
2827 "
2828 {
2829 int i;
2830 rtx temp1;
2831 rtx temp2;
2833 if (GET_CODE (operands[2]) != CONST_INT
2834 || INTVAL (operands[2]) <= 0
2835 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2836 FAIL;
2838 temp1 = gen_reg_rtx (<MODE>mode);
2839 temp2 = gen_reg_rtx (<MODE>mode);
2841 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2842 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2843 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2844 DONE;
2845 }")
2847 (define_insn ""
2848 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2849 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2850 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2851 ""
2852 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2853 [(set_attr "type" "two")
2854 (set_attr "length" "8")])
2856 (define_insn ""
2857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2858 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2859 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2860 (const_int 0)))
2861 (clobber (match_scratch:P 3 "=r,r"))]
2862 ""
2863 "@
2864 sra<wd>i %3,%1,%p2\;addze. %3,%3
2865 #"
2866 [(set_attr "type" "compare")
2867 (set_attr "length" "8,12")
2868 (set_attr "cell_micro" "not")])
2870 (define_split
2871 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2872 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2873 (match_operand:GPR 2 "exact_log2_cint_operand"
2874 ""))
2875 (const_int 0)))
2876 (clobber (match_scratch:GPR 3 ""))]
2877 "reload_completed"
2878 [(set (match_dup 3)
2879 (div:<MODE> (match_dup 1) (match_dup 2)))
2880 (set (match_dup 0)
2881 (compare:CC (match_dup 3)
2882 (const_int 0)))]
2883 "")
2885 (define_insn ""
2886 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2887 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2888 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2889 (const_int 0)))
2890 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2891 (div:P (match_dup 1) (match_dup 2)))]
2892 ""
2893 "@
2894 sra<wd>i %0,%1,%p2\;addze. %0,%0
2895 #"
2896 [(set_attr "type" "compare")
2897 (set_attr "length" "8,12")
2898 (set_attr "cell_micro" "not")])
2900 (define_split
2901 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2902 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2903 (match_operand:GPR 2 "exact_log2_cint_operand"
2904 ""))
2905 (const_int 0)))
2906 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2907 (div:GPR (match_dup 1) (match_dup 2)))]
2908 "reload_completed"
2909 [(set (match_dup 0)
2910 (div:<MODE> (match_dup 1) (match_dup 2)))
2911 (set (match_dup 3)
2912 (compare:CC (match_dup 0)
2913 (const_int 0)))]
2914 "")
2915 \f
2916 ;; Logical instructions
2917 ;; The logical instructions are mostly combined by using match_operator,
2918 ;; but the plain AND insns are somewhat different because there is no
2919 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2920 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2922 (define_expand "andsi3"
2923 [(parallel
2924 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2925 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2926 (match_operand:SI 2 "and_operand" "")))
2927 (clobber (match_scratch:CC 3 ""))])]
2928 ""
2929 "")
2931 (define_insn "andsi3_mc"
2932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2933 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2934 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2935 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2936 "rs6000_gen_cell_microcode"
2937 "@
2938 and %0,%1,%2
2939 rlwinm %0,%1,0,%m2,%M2
2940 andi. %0,%1,%b2
2941 andis. %0,%1,%u2"
2942 [(set_attr "type" "*,shift,logical,logical")
2943 (set_attr "dot" "no,no,yes,yes")])
2945 (define_insn "andsi3_nomc"
2946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2947 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2948 (match_operand:SI 2 "and_operand" "?r,T")))
2949 (clobber (match_scratch:CC 3 "=X,X"))]
2950 "!rs6000_gen_cell_microcode"
2951 "@
2952 and %0,%1,%2
2953 rlwinm %0,%1,0,%m2,%M2"
2954 [(set_attr "type" "logical,shift")])
2956 (define_insn "andsi3_internal0_nomc"
2957 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2958 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2959 (match_operand:SI 2 "and_operand" "?r,T")))]
2960 "!rs6000_gen_cell_microcode"
2961 "@
2962 and %0,%1,%2
2963 rlwinm %0,%1,0,%m2,%M2"
2964 [(set_attr "type" "logical,shift")])
2967 ;; Note to set cr's other than cr0 we do the and immediate and then
2968 ;; the test again -- this avoids a mfcr which on the higher end
2969 ;; machines causes an execution serialization
2971 (define_insn "*andsi3_internal2_mc"
2972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2973 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2974 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2975 (const_int 0)))
2976 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2977 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2978 "TARGET_32BIT && rs6000_gen_cell_microcode"
2979 "@
2980 and. %3,%1,%2
2981 andi. %3,%1,%b2
2982 andis. %3,%1,%u2
2983 rlwinm. %3,%1,0,%m2,%M2
2984 #
2985 #
2986 #
2987 #"
2988 [(set_attr "type" "logical,logical,logical,shift,\
2989 compare,compare,compare,compare")
2990 (set_attr "dot" "yes")
2991 (set_attr "length" "4,4,4,4,8,8,8,8")])
2993 (define_insn "*andsi3_internal3_mc"
2994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2995 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2996 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2997 (const_int 0)))
2998 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2999 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3000 "TARGET_64BIT && rs6000_gen_cell_microcode"
3001 "@
3002 #
3003 andi. %3,%1,%b2
3004 andis. %3,%1,%u2
3005 rlwinm. %3,%1,0,%m2,%M2
3006 #
3007 #
3008 #
3009 #"
3010 [(set_attr "type" "compare,logical,logical,shift,compare,\
3011 compare,compare,compare")
3012 (set_attr "dot" "yes")
3013 (set_attr "length" "8,4,4,4,8,8,8,8")])
3015 (define_split
3016 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3017 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3018 (match_operand:GPR 2 "and_operand" ""))
3019 (const_int 0)))
3020 (clobber (match_scratch:GPR 3 ""))
3021 (clobber (match_scratch:CC 4 ""))]
3022 "reload_completed"
3023 [(parallel [(set (match_dup 3)
3024 (and:<MODE> (match_dup 1)
3025 (match_dup 2)))
3026 (clobber (match_dup 4))])
3027 (set (match_dup 0)
3028 (compare:CC (match_dup 3)
3029 (const_int 0)))]
3030 "")
3032 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3033 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3035 (define_split
3036 [(set (match_operand:CC 0 "cc_reg_operand" "")
3037 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3038 (match_operand:SI 2 "gpc_reg_operand" ""))
3039 (const_int 0)))
3040 (clobber (match_scratch:SI 3 ""))
3041 (clobber (match_scratch:CC 4 ""))]
3042 "TARGET_POWERPC64 && reload_completed"
3043 [(parallel [(set (match_dup 3)
3044 (and:SI (match_dup 1)
3045 (match_dup 2)))
3046 (clobber (match_dup 4))])
3047 (set (match_dup 0)
3048 (compare:CC (match_dup 3)
3049 (const_int 0)))]
3050 "")
3052 (define_insn "*andsi3_internal4"
3053 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3054 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3055 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3056 (const_int 0)))
3057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3058 (and:SI (match_dup 1)
3059 (match_dup 2)))
3060 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3061 "TARGET_32BIT && rs6000_gen_cell_microcode"
3062 "@
3063 and. %0,%1,%2
3064 andi. %0,%1,%b2
3065 andis. %0,%1,%u2
3066 rlwinm. %0,%1,0,%m2,%M2
3067 #
3068 #
3069 #
3070 #"
3071 [(set_attr "type" "logical,logical,logical,shift,\
3072 compare,compare,compare,compare")
3073 (set_attr "dot" "yes")
3074 (set_attr "length" "4,4,4,4,8,8,8,8")])
3076 (define_insn "*andsi3_internal5_mc"
3077 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3078 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3079 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3080 (const_int 0)))
3081 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3082 (and:SI (match_dup 1)
3083 (match_dup 2)))
3084 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3085 "TARGET_64BIT && rs6000_gen_cell_microcode"
3086 "@
3087 #
3088 andi. %0,%1,%b2
3089 andis. %0,%1,%u2
3090 rlwinm. %0,%1,0,%m2,%M2
3091 #
3092 #
3093 #
3094 #"
3095 [(set_attr "type" "compare,logical,logical,shift,compare,\
3096 compare,compare,compare")
3097 (set_attr "dot" "yes")
3098 (set_attr "length" "8,4,4,4,8,8,8,8")])
3100 (define_split
3101 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3102 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3103 (match_operand:SI 2 "and_operand" ""))
3104 (const_int 0)))
3105 (set (match_operand:SI 0 "gpc_reg_operand" "")
3106 (and:SI (match_dup 1)
3107 (match_dup 2)))
3108 (clobber (match_scratch:CC 4 ""))]
3109 "reload_completed"
3110 [(parallel [(set (match_dup 0)
3111 (and:SI (match_dup 1)
3112 (match_dup 2)))
3113 (clobber (match_dup 4))])
3114 (set (match_dup 3)
3115 (compare:CC (match_dup 0)
3116 (const_int 0)))]
3117 "")
3119 (define_split
3120 [(set (match_operand:CC 3 "cc_reg_operand" "")
3121 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3122 (match_operand:SI 2 "gpc_reg_operand" ""))
3123 (const_int 0)))
3124 (set (match_operand:SI 0 "gpc_reg_operand" "")
3125 (and:SI (match_dup 1)
3126 (match_dup 2)))
3127 (clobber (match_scratch:CC 4 ""))]
3128 "TARGET_POWERPC64 && reload_completed"
3129 [(parallel [(set (match_dup 0)
3130 (and:SI (match_dup 1)
3131 (match_dup 2)))
3132 (clobber (match_dup 4))])
3133 (set (match_dup 3)
3134 (compare:CC (match_dup 0)
3135 (const_int 0)))]
3136 "")
3138 ;; Handle the PowerPC64 rlwinm corner case
3140 (define_insn_and_split "*andsi3_internal6"
3141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3142 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3143 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3144 "TARGET_POWERPC64"
3145 "#"
3146 "TARGET_POWERPC64"
3147 [(set (match_dup 0)
3148 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3149 (match_dup 4)))
3150 (set (match_dup 0)
3151 (rotate:SI (match_dup 0) (match_dup 5)))]
3152 "
3153 {
3154 int mb = extract_MB (operands[2]);
3155 int me = extract_ME (operands[2]);
3156 operands[3] = GEN_INT (me + 1);
3157 operands[5] = GEN_INT (32 - (me + 1));
3158 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3159 }"
3160 [(set_attr "length" "8")])
3163 (define_expand "ior<mode>3"
3164 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
3165 (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
3166 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
3167 ""
3168 {
3169 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3170 {
3171 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
3172 DONE;
3173 }
3175 if (non_logical_cint_operand (operands[2], <MODE>mode))
3176 {
3177 rtx tmp = ((!can_create_pseudo_p ()
3178 || rtx_equal_p (operands[0], operands[1]))
3179 ? operands[0] : gen_reg_rtx (<MODE>mode));
3180 HOST_WIDE_INT value = INTVAL (operands[2]);
3182 emit_insn (gen_ior<mode>3 (tmp, operands[1],
3183 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3185 emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3186 DONE;
3187 }
3189 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
3190 operands[2] = force_reg (<MODE>mode, operands[2]);
3191 })
3193 (define_expand "xor<mode>3"
3194 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
3195 (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
3196 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
3197 ""
3198 {
3199 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3200 {
3201 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
3202 DONE;
3203 }
3205 if (non_logical_cint_operand (operands[2], <MODE>mode))
3206 {
3207 rtx tmp = ((!can_create_pseudo_p ()
3208 || rtx_equal_p (operands[0], operands[1]))
3209 ? operands[0] : gen_reg_rtx (<MODE>mode));
3210 HOST_WIDE_INT value = INTVAL (operands[2]);
3212 emit_insn (gen_xor<mode>3 (tmp, operands[1],
3213 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3215 emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3216 DONE;
3217 }
3219 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
3220 operands[2] = force_reg (<MODE>mode, operands[2]);
3221 })
3223 (define_insn "*bool<mode>3"
3224 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3225 (match_operator:GPR 3 "boolean_or_operator"
3226 [(match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3227 (match_operand:GPR 2 "logical_operand" "r,n")]))]
3228 ""
3229 "@
3230 %q3 %0,%1,%2
3231 %q3i%e2 %0,%1,%u2"
3232 [(set_attr "type" "logical")])
3234 (define_insn_and_split "*bool<mode>3_dot"
3235 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3236 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
3237 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3238 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3239 (const_int 0)))
3240 (clobber (match_scratch:GPR 0 "=r,r"))]
3241 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3242 "@
3243 %q3. %0,%1,%2
3244 #"
3245 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3246 [(set (match_dup 0)
3247 (match_dup 3))
3248 (set (match_dup 4)
3249 (compare:CC (match_dup 0)
3250 (const_int 0)))]
3251 ""
3252 [(set_attr "type" "logical")
3253 (set_attr "dot" "yes")
3254 (set_attr "length" "4,8")])
3256 (define_insn_and_split "*bool<mode>3_dot2"
3257 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3258 (compare:CC (match_operator:GPR 3 "boolean_or_operator"
3259 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3260 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3261 (const_int 0)))
3262 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3263 (match_dup 3))]
3264 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3265 "@
3266 %q3. %0,%1,%2
3267 #"
3268 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3269 [(set (match_dup 0)
3270 (match_dup 3))
3271 (set (match_dup 4)
3272 (compare:CC (match_dup 0)
3273 (const_int 0)))]
3274 ""
3275 [(set_attr "type" "logical")
3276 (set_attr "dot" "yes")
3277 (set_attr "length" "4,8")])
3279 ;; Split a logical operation that we can't do in one insn into two insns,
3280 ;; each of which does one 16-bit part. This is used by combine.
3282 (define_split
3283 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3284 (match_operator:GPR 3 "boolean_or_operator"
3285 [(match_operand:GPR 1 "gpc_reg_operand" "")
3286 (match_operand:GPR 2 "non_logical_cint_operand" "")]))]
3287 ""
3288 [(set (match_dup 0) (match_dup 4))
3289 (set (match_dup 0) (match_dup 5))]
3290 {
3291 rtx i;
3292 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3293 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3294 operands[1], i);
3295 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3296 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
3297 operands[0], i);
3298 })
3301 (define_insn "*boolcsi3_internal1"
3302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3303 (match_operator:SI 3 "boolean_operator"
3304 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3305 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3306 ""
3307 "%q3 %0,%2,%1")
3309 (define_insn "*boolcsi3_internal2"
3310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3311 (compare:CC (match_operator:SI 4 "boolean_operator"
3312 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3313 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3314 (const_int 0)))
3315 (clobber (match_scratch:SI 3 "=r,r"))]
3316 "TARGET_32BIT"
3317 "@
3318 %q4. %3,%2,%1
3319 #"
3320 [(set_attr "type" "compare")
3321 (set_attr "length" "4,8")])
3323 (define_split
3324 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3325 (compare:CC (match_operator:SI 4 "boolean_operator"
3326 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3327 (match_operand:SI 2 "gpc_reg_operand" "")])
3328 (const_int 0)))
3329 (clobber (match_scratch:SI 3 ""))]
3330 "TARGET_32BIT && reload_completed"
3331 [(set (match_dup 3) (match_dup 4))
3332 (set (match_dup 0)
3333 (compare:CC (match_dup 3)
3334 (const_int 0)))]
3335 "")
3337 (define_insn "*boolcsi3_internal3"
3338 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3339 (compare:CC (match_operator:SI 4 "boolean_operator"
3340 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3341 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3342 (const_int 0)))
3343 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3344 (match_dup 4))]
3345 "TARGET_32BIT"
3346 "@
3347 %q4. %0,%2,%1
3348 #"
3349 [(set_attr "type" "compare")
3350 (set_attr "length" "4,8")])
3352 (define_split
3353 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3354 (compare:CC (match_operator:SI 4 "boolean_operator"
3355 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3356 (match_operand:SI 2 "gpc_reg_operand" "")])
3357 (const_int 0)))
3358 (set (match_operand:SI 0 "gpc_reg_operand" "")
3359 (match_dup 4))]
3360 "TARGET_32BIT && reload_completed"
3361 [(set (match_dup 0) (match_dup 4))
3362 (set (match_dup 3)
3363 (compare:CC (match_dup 0)
3364 (const_int 0)))]
3365 "")
3367 (define_insn "*boolccsi3_internal1"
3368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3369 (match_operator:SI 3 "boolean_operator"
3370 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3371 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3372 ""
3373 "%q3 %0,%1,%2")
3375 (define_insn "*boolccsi3_internal2"
3376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3377 (compare:CC (match_operator:SI 4 "boolean_operator"
3378 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3379 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3380 (const_int 0)))
3381 (clobber (match_scratch:SI 3 "=r,r"))]
3382 "TARGET_32BIT"
3383 "@
3384 %q4. %3,%1,%2
3385 #"
3386 [(set_attr "type" "logical,compare")
3387 (set_attr "dot" "yes")
3388 (set_attr "length" "4,8")])
3390 (define_split
3391 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3392 (compare:CC (match_operator:SI 4 "boolean_operator"
3393 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3394 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3395 (const_int 0)))
3396 (clobber (match_scratch:SI 3 ""))]
3397 "TARGET_32BIT && reload_completed"
3398 [(set (match_dup 3) (match_dup 4))
3399 (set (match_dup 0)
3400 (compare:CC (match_dup 3)
3401 (const_int 0)))]
3402 "")
3404 (define_insn "*boolccsi3_internal3"
3405 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3406 (compare:CC (match_operator:SI 4 "boolean_operator"
3407 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3408 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3409 (const_int 0)))
3410 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3411 (match_dup 4))]
3412 "TARGET_32BIT"
3413 "@
3414 %q4. %0,%1,%2
3415 #"
3416 [(set_attr "type" "logical,compare")
3417 (set_attr "dot" "yes")
3418 (set_attr "length" "4,8")])
3420 (define_split
3421 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3422 (compare:CC (match_operator:SI 4 "boolean_operator"
3423 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3424 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3425 (const_int 0)))
3426 (set (match_operand:SI 0 "gpc_reg_operand" "")
3427 (match_dup 4))]
3428 "TARGET_32BIT && reload_completed"
3429 [(set (match_dup 0) (match_dup 4))
3430 (set (match_dup 3)
3431 (compare:CC (match_dup 0)
3432 (const_int 0)))]
3433 "")
3434 \f
3435 ;; Rotate and shift insns, in all their variants. These support shifts,
3436 ;; field inserts and extracts, and various combinations thereof.
3437 (define_expand "insv"
3438 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3439 (match_operand:SI 1 "const_int_operand" "")
3440 (match_operand:SI 2 "const_int_operand" ""))
3441 (match_operand 3 "gpc_reg_operand" ""))]
3442 ""
3443 "
3444 {
3445 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3446 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3447 compiler if the address of the structure is taken later. Likewise, do
3448 not handle invalid E500 subregs. */
3449 if (GET_CODE (operands[0]) == SUBREG
3450 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3451 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3452 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3453 FAIL;
3455 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3456 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3457 operands[3]));
3458 else
3459 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3460 operands[3]));
3461 DONE;
3462 }")
3464 (define_insn "insvsi_internal"
3465 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3466 (match_operand:SI 1 "const_int_operand" "i")
3467 (match_operand:SI 2 "const_int_operand" "i"))
3468 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3469 ""
3470 "*
3471 {
3472 int start = INTVAL (operands[2]) & 31;
3473 int size = INTVAL (operands[1]) & 31;
3475 operands[4] = GEN_INT (32 - start - size);
3476 operands[1] = GEN_INT (start + size - 1);
3477 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3478 }"
3479 [(set_attr "type" "insert")])
3481 (define_insn "*insvsi_internal1"
3482 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3483 (match_operand:SI 1 "const_int_operand" "i")
3484 (match_operand:SI 2 "const_int_operand" "i"))
3485 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3486 (match_operand:SI 4 "const_int_operand" "i")))]
3487 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3488 "*
3489 {
3490 int shift = INTVAL (operands[4]) & 31;
3491 int start = INTVAL (operands[2]) & 31;
3492 int size = INTVAL (operands[1]) & 31;
3494 operands[4] = GEN_INT (shift - start - size);
3495 operands[1] = GEN_INT (start + size - 1);
3496 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3497 }"
3498 [(set_attr "type" "insert")])
3500 (define_insn "*insvsi_internal2"
3501 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3502 (match_operand:SI 1 "const_int_operand" "i")
3503 (match_operand:SI 2 "const_int_operand" "i"))
3504 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3505 (match_operand:SI 4 "const_int_operand" "i")))]
3506 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3507 "*
3508 {
3509 int shift = INTVAL (operands[4]) & 31;
3510 int start = INTVAL (operands[2]) & 31;
3511 int size = INTVAL (operands[1]) & 31;
3513 operands[4] = GEN_INT (32 - shift - start - size);
3514 operands[1] = GEN_INT (start + size - 1);
3515 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3516 }"
3517 [(set_attr "type" "insert")])
3519 (define_insn "*insvsi_internal3"
3520 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3521 (match_operand:SI 1 "const_int_operand" "i")
3522 (match_operand:SI 2 "const_int_operand" "i"))
3523 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3524 (match_operand:SI 4 "const_int_operand" "i")))]
3525 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3526 "*
3527 {
3528 int shift = INTVAL (operands[4]) & 31;
3529 int start = INTVAL (operands[2]) & 31;
3530 int size = INTVAL (operands[1]) & 31;
3532 operands[4] = GEN_INT (32 - shift - start - size);
3533 operands[1] = GEN_INT (start + size - 1);
3534 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3535 }"
3536 [(set_attr "type" "insert")])
3538 (define_insn "*insvsi_internal4"
3539 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3540 (match_operand:SI 1 "const_int_operand" "i")
3541 (match_operand:SI 2 "const_int_operand" "i"))
3542 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3543 (match_operand:SI 4 "const_int_operand" "i")
3544 (match_operand:SI 5 "const_int_operand" "i")))]
3545 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3546 "*
3547 {
3548 int extract_start = INTVAL (operands[5]) & 31;
3549 int extract_size = INTVAL (operands[4]) & 31;
3550 int insert_start = INTVAL (operands[2]) & 31;
3551 int insert_size = INTVAL (operands[1]) & 31;
3553 /* Align extract field with insert field */
3554 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3555 operands[1] = GEN_INT (insert_start + insert_size - 1);
3556 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3557 }"
3558 [(set_attr "type" "insert")])
3560 ;; combine patterns for rlwimi
3561 (define_insn "*insvsi_internal5"
3562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3563 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3564 (match_operand:SI 1 "mask_operand" "i"))
3565 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3566 (match_operand:SI 2 "const_int_operand" "i"))
3567 (match_operand:SI 5 "mask_operand" "i"))))]
3568 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3569 "*
3570 {
3571 int me = extract_ME(operands[5]);
3572 int mb = extract_MB(operands[5]);
3573 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3574 operands[2] = GEN_INT(mb);
3575 operands[1] = GEN_INT(me);
3576 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3577 }"
3578 [(set_attr "type" "insert")])
3580 (define_insn "*insvsi_internal6"
3581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3582 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3583 (match_operand:SI 2 "const_int_operand" "i"))
3584 (match_operand:SI 5 "mask_operand" "i"))
3585 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3586 (match_operand:SI 1 "mask_operand" "i"))))]
3587 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3588 "*
3589 {
3590 int me = extract_ME(operands[5]);
3591 int mb = extract_MB(operands[5]);
3592 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3593 operands[2] = GEN_INT(mb);
3594 operands[1] = GEN_INT(me);
3595 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3596 }"
3597 [(set_attr "type" "insert")])
3599 (define_insn "insvdi_internal"
3600 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3601 (match_operand:SI 1 "const_int_operand" "i")
3602 (match_operand:SI 2 "const_int_operand" "i"))
3603 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3604 "TARGET_POWERPC64"
3605 "*
3606 {
3607 int start = INTVAL (operands[2]) & 63;
3608 int size = INTVAL (operands[1]) & 63;
3610 operands[1] = GEN_INT (64 - start - size);
3611 return \"rldimi %0,%3,%H1,%H2\";
3612 }"
3613 [(set_attr "type" "insert")
3614 (set_attr "size" "64")])
3616 (define_insn "*insvdi_internal2"
3617 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3618 (match_operand:SI 1 "const_int_operand" "i")
3619 (match_operand:SI 2 "const_int_operand" "i"))
3620 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3621 (match_operand:SI 4 "const_int_operand" "i")))]
3622 "TARGET_POWERPC64
3623 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3624 "*
3625 {
3626 int shift = INTVAL (operands[4]) & 63;
3627 int start = (INTVAL (operands[2]) & 63) - 32;
3628 int size = INTVAL (operands[1]) & 63;
3630 operands[4] = GEN_INT (64 - shift - start - size);
3631 operands[2] = GEN_INT (start);
3632 operands[1] = GEN_INT (start + size - 1);
3633 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3634 }")
3636 (define_insn "*insvdi_internal3"
3637 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3638 (match_operand:SI 1 "const_int_operand" "i")
3639 (match_operand:SI 2 "const_int_operand" "i"))
3640 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3641 (match_operand:SI 4 "const_int_operand" "i")))]
3642 "TARGET_POWERPC64
3643 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3644 "*
3645 {
3646 int shift = INTVAL (operands[4]) & 63;
3647 int start = (INTVAL (operands[2]) & 63) - 32;
3648 int size = INTVAL (operands[1]) & 63;
3650 operands[4] = GEN_INT (64 - shift - start - size);
3651 operands[2] = GEN_INT (start);
3652 operands[1] = GEN_INT (start + size - 1);
3653 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3654 }")
3656 (define_expand "extzv"
3657 [(set (match_operand 0 "gpc_reg_operand" "")
3658 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3659 (match_operand:SI 2 "const_int_operand" "")
3660 (match_operand:SI 3 "const_int_operand" "")))]
3661 ""
3662 "
3663 {
3664 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3665 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3666 compiler if the address of the structure is taken later. */
3667 if (GET_CODE (operands[0]) == SUBREG
3668 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3669 FAIL;
3671 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3672 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3673 operands[3]));
3674 else
3675 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3676 operands[3]));
3677 DONE;
3678 }")
3680 (define_insn "extzvsi_internal"
3681 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3682 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3683 (match_operand:SI 2 "const_int_operand" "i")
3684 (match_operand:SI 3 "const_int_operand" "i")))]
3685 ""
3686 "*
3687 {
3688 int start = INTVAL (operands[3]) & 31;
3689 int size = INTVAL (operands[2]) & 31;
3691 if (start + size >= 32)
3692 operands[3] = const0_rtx;
3693 else
3694 operands[3] = GEN_INT (start + size);
3695 return \"rlwinm %0,%1,%3,%s2,31\";
3696 }"
3697 [(set_attr "type" "shift")])
3699 (define_insn "*extzvsi_internal1"
3700 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3701 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3702 (match_operand:SI 2 "const_int_operand" "i,i")
3703 (match_operand:SI 3 "const_int_operand" "i,i"))
3704 (const_int 0)))
3705 (clobber (match_scratch:SI 4 "=r,r"))]
3706 ""
3707 "*
3708 {
3709 int start = INTVAL (operands[3]) & 31;
3710 int size = INTVAL (operands[2]) & 31;
3712 /* Force split for non-cc0 compare. */
3713 if (which_alternative == 1)
3714 return \"#\";
3716 /* If the bit-field being tested fits in the upper or lower half of a
3717 word, it is possible to use andiu. or andil. to test it. This is
3718 useful because the condition register set-use delay is smaller for
3719 andi[ul]. than for rlinm. This doesn't work when the starting bit
3720 position is 0 because the LT and GT bits may be set wrong. */
3722 if ((start > 0 && start + size <= 16) || start >= 16)
3723 {
3724 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3725 - (1 << (16 - (start & 15) - size))));
3726 if (start < 16)
3727 return \"andis. %4,%1,%3\";
3728 else
3729 return \"andi. %4,%1,%3\";
3730 }
3732 if (start + size >= 32)
3733 operands[3] = const0_rtx;
3734 else
3735 operands[3] = GEN_INT (start + size);
3736 return \"rlwinm. %4,%1,%3,%s2,31\";
3737 }"
3738 [(set_attr "type" "shift")
3739 (set_attr "dot" "yes")
3740 (set_attr "length" "4,8")])
3742 (define_split
3743 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3744 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3745 (match_operand:SI 2 "const_int_operand" "")
3746 (match_operand:SI 3 "const_int_operand" ""))
3747 (const_int 0)))
3748 (clobber (match_scratch:SI 4 ""))]
3749 "reload_completed"
3750 [(set (match_dup 4)
3751 (zero_extract:SI (match_dup 1) (match_dup 2)
3752 (match_dup 3)))
3753 (set (match_dup 0)
3754 (compare:CC (match_dup 4)
3755 (const_int 0)))]
3756 "")
3758 (define_insn "*extzvsi_internal2"
3759 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3760 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3761 (match_operand:SI 2 "const_int_operand" "i,i")
3762 (match_operand:SI 3 "const_int_operand" "i,i"))
3763 (const_int 0)))
3764 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3765 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3766 ""
3767 "*
3768 {
3769 int start = INTVAL (operands[3]) & 31;
3770 int size = INTVAL (operands[2]) & 31;
3772 /* Force split for non-cc0 compare. */
3773 if (which_alternative == 1)
3774 return \"#\";
3776 /* Since we are using the output value, we can't ignore any need for
3777 a shift. The bit-field must end at the LSB. */
3778 if (start >= 16 && start + size == 32)
3779 {
3780 operands[3] = GEN_INT ((1 << size) - 1);
3781 return \"andi. %0,%1,%3\";
3782 }
3784 if (start + size >= 32)
3785 operands[3] = const0_rtx;
3786 else
3787 operands[3] = GEN_INT (start + size);
3788 return \"rlwinm. %0,%1,%3,%s2,31\";
3789 }"
3790 [(set_attr "type" "shift")
3791 (set_attr "dot" "yes")
3792 (set_attr "length" "4,8")])
3794 (define_split
3795 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3796 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3797 (match_operand:SI 2 "const_int_operand" "")
3798 (match_operand:SI 3 "const_int_operand" ""))
3799 (const_int 0)))
3800 (set (match_operand:SI 0 "gpc_reg_operand" "")
3801 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3802 "reload_completed"
3803 [(set (match_dup 0)
3804 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3805 (set (match_dup 4)
3806 (compare:CC (match_dup 0)
3807 (const_int 0)))]
3808 "")
3810 (define_insn "extzvdi_internal"
3811 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3812 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3813 (match_operand:SI 2 "const_int_operand" "i")
3814 (match_operand:SI 3 "const_int_operand" "i")))]
3815 "TARGET_POWERPC64"
3816 "*
3817 {
3818 int start = INTVAL (operands[3]) & 63;
3819 int size = INTVAL (operands[2]) & 63;
3821 if (start + size >= 64)
3822 operands[3] = const0_rtx;
3823 else
3824 operands[3] = GEN_INT (start + size);
3825 operands[2] = GEN_INT (64 - size);
3826 return \"rldicl %0,%1,%3,%2\";
3827 }"
3828 [(set_attr "type" "shift")])
3830 (define_insn "*extzvdi_internal1"
3831 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3832 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3833 (match_operand:SI 2 "const_int_operand" "i")
3834 (match_operand:SI 3 "const_int_operand" "i"))
3835 (const_int 0)))
3836 (clobber (match_scratch:DI 4 "=r"))]
3837 "TARGET_64BIT && rs6000_gen_cell_microcode"
3838 "*
3839 {
3840 int start = INTVAL (operands[3]) & 63;
3841 int size = INTVAL (operands[2]) & 63;
3843 if (start + size >= 64)
3844 operands[3] = const0_rtx;
3845 else
3846 operands[3] = GEN_INT (start + size);
3847 operands[2] = GEN_INT (64 - size);
3848 return \"rldicl. %4,%1,%3,%2\";
3849 }"
3850 [(set_attr "type" "shift")
3851 (set_attr "dot" "yes")])
3853 (define_insn "*extzvdi_internal2"
3854 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3855 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3856 (match_operand:SI 2 "const_int_operand" "i")
3857 (match_operand:SI 3 "const_int_operand" "i"))
3858 (const_int 0)))
3859 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3860 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3861 "TARGET_64BIT && rs6000_gen_cell_microcode"
3862 "*
3863 {
3864 int start = INTVAL (operands[3]) & 63;
3865 int size = INTVAL (operands[2]) & 63;
3867 if (start + size >= 64)
3868 operands[3] = const0_rtx;
3869 else
3870 operands[3] = GEN_INT (start + size);
3871 operands[2] = GEN_INT (64 - size);
3872 return \"rldicl. %0,%1,%3,%2\";
3873 }"
3874 [(set_attr "type" "shift")
3875 (set_attr "dot" "yes")])
3878 (define_insn "rotl<mode>3"
3879 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3880 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3882 ""
3883 "rotl<wd>%I2 %0,%1,%<hH>2"
3884 [(set_attr "type" "shift")
3885 (set_attr "maybe_var_shift" "yes")])
3887 (define_insn "*rotlsi3_64"
3888 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3889 (zero_extend:DI
3890 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3891 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3892 "TARGET_POWERPC64"
3893 "rotlw%I2 %0,%1,%h2"
3894 [(set_attr "type" "shift")
3895 (set_attr "maybe_var_shift" "yes")])
3897 (define_insn_and_split "*rotl<mode>3_dot"
3898 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3899 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3900 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3901 (const_int 0)))
3902 (clobber (match_scratch:GPR 0 "=r,r"))]
3903 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3904 "@
3905 rotl<wd>%I2. %0,%1,%<hH>2
3906 #"
3907 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3908 [(set (match_dup 0)
3909 (rotate:GPR (match_dup 1)
3910 (match_dup 2)))
3911 (set (match_dup 3)
3912 (compare:CC (match_dup 0)
3913 (const_int 0)))]
3914 ""
3915 [(set_attr "type" "shift")
3916 (set_attr "maybe_var_shift" "yes")
3917 (set_attr "dot" "yes")
3918 (set_attr "length" "4,8")])
3920 (define_insn_and_split "*rotl<mode>3_dot2"
3921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3922 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3923 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3924 (const_int 0)))
3925 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3926 (rotate:GPR (match_dup 1)
3927 (match_dup 2)))]
3928 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3929 "@
3930 rotl<wd>%I2. %0,%1,%<hH>2
3931 #"
3932 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3933 [(set (match_dup 0)
3934 (rotate:GPR (match_dup 1)
3935 (match_dup 2)))
3936 (set (match_dup 3)
3937 (compare:CC (match_dup 0)
3938 (const_int 0)))]
3939 ""
3940 [(set_attr "type" "shift")
3941 (set_attr "maybe_var_shift" "yes")
3942 (set_attr "dot" "yes")
3943 (set_attr "length" "4,8")])
3946 (define_insn "*rotlsi3_internal4"
3947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3948 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3949 (match_operand:SI 2 "reg_or_cint_operand" "rn"))
3950 (match_operand:SI 3 "mask_operand" "n")))]
3951 ""
3952 "rlw%I2nm %0,%1,%h2,%m3,%M3"
3953 [(set_attr "type" "shift")
3954 (set_attr "maybe_var_shift" "yes")])
3956 (define_insn "*rotlsi3_internal5"
3957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3958 (compare:CC (and:SI
3959 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3960 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3961 (match_operand:SI 3 "mask_operand" "n,n"))
3962 (const_int 0)))
3963 (clobber (match_scratch:SI 4 "=r,r"))]
3964 ""
3965 "@
3966 rlw%I2nm. %4,%1,%h2,%m3,%M3
3967 #"
3968 [(set_attr "type" "shift")
3969 (set_attr "maybe_var_shift" "yes")
3970 (set_attr "dot" "yes")
3971 (set_attr "length" "4,8")])
3973 (define_split
3974 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3975 (compare:CC (and:SI
3976 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3977 (match_operand:SI 2 "reg_or_cint_operand" ""))
3978 (match_operand:SI 3 "mask_operand" ""))
3979 (const_int 0)))
3980 (clobber (match_scratch:SI 4 ""))]
3981 "reload_completed"
3982 [(set (match_dup 4)
3983 (and:SI (rotate:SI (match_dup 1)
3984 (match_dup 2))
3985 (match_dup 3)))
3986 (set (match_dup 0)
3987 (compare:CC (match_dup 4)
3988 (const_int 0)))]
3989 "")
3991 (define_insn "*rotlsi3_internal6"
3992 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3993 (compare:CC (and:SI
3994 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3995 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3996 (match_operand:SI 3 "mask_operand" "n,n"))
3997 (const_int 0)))
3998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3999 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4000 ""
4001 "@
4002 rlw%I2nm. %0,%1,%h2,%m3,%M3
4003 #"
4004 [(set_attr "type" "shift")
4005 (set_attr "maybe_var_shift" "yes")
4006 (set_attr "dot" "yes")
4007 (set_attr "length" "4,8")])
4009 (define_split
4010 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4011 (compare:CC (and:SI
4012 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4013 (match_operand:SI 2 "reg_or_cint_operand" ""))
4014 (match_operand:SI 3 "mask_operand" ""))
4015 (const_int 0)))
4016 (set (match_operand:SI 0 "gpc_reg_operand" "")
4017 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4018 "reload_completed"
4019 [(set (match_dup 0)
4020 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4021 (set (match_dup 4)
4022 (compare:CC (match_dup 0)
4023 (const_int 0)))]
4024 "")
4026 (define_insn "*rotlsi3_internal7le"
4027 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4028 (zero_extend:SI
4029 (subreg:QI
4030 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4031 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4032 "!BYTES_BIG_ENDIAN"
4033 "rlw%I2nm %0,%1,%h2,0xff"
4034 [(set (attr "cell_micro")
4035 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4036 (const_string "not")
4037 (const_string "always")))
4038 (set_attr "type" "shift")])
4040 (define_insn "*rotlsi3_internal7be"
4041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4042 (zero_extend:SI
4043 (subreg:QI
4044 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4045 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
4046 "BYTES_BIG_ENDIAN"
4047 "rlw%I2nm %0,%1,%h2,0xff"
4048 [(set (attr "cell_micro")
4049 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4050 (const_string "not")
4051 (const_string "always")))
4052 (set_attr "type" "shift")])
4054 (define_insn "*rotlsi3_internal8le"
4055 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4056 (compare:CC (zero_extend:SI
4057 (subreg:QI
4058 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4059 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4060 (const_int 0)))
4061 (clobber (match_scratch:SI 3 "=r,r"))]
4062 "!BYTES_BIG_ENDIAN"
4063 "@
4064 rlw%I2nm. %3,%1,%h2,0xff
4065 #"
4066 [(set_attr "type" "shift")
4067 (set_attr "maybe_var_shift" "yes")
4068 (set_attr "dot" "yes")
4069 (set_attr "length" "4,8")])
4071 (define_insn "*rotlsi3_internal8be"
4072 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4073 (compare:CC (zero_extend:SI
4074 (subreg:QI
4075 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4076 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
4077 (const_int 0)))
4078 (clobber (match_scratch:SI 3 "=r,r"))]
4079 "BYTES_BIG_ENDIAN"
4080 "@
4081 rlw%I2nm. %3,%1,%h2,0xff
4082 #"
4083 [(set_attr "type" "shift")
4084 (set_attr "maybe_var_shift" "yes")
4085 (set_attr "dot" "yes")
4086 (set_attr "length" "4,8")])
4088 (define_split
4089 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4090 (compare:CC (zero_extend:SI
4091 (subreg:QI
4092 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4093 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4094 (const_int 0)))
4095 (clobber (match_scratch:SI 3 ""))]
4096 "!BYTES_BIG_ENDIAN && reload_completed"
4097 [(set (match_dup 3)
4098 (zero_extend:SI (subreg:QI
4099 (rotate:SI (match_dup 1)
4100 (match_dup 2)) 0)))
4101 (set (match_dup 0)
4102 (compare:CC (match_dup 3)
4103 (const_int 0)))]
4104 "")
4106 (define_split
4107 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4108 (compare:CC (zero_extend:SI
4109 (subreg:QI
4110 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4111 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4112 (const_int 0)))
4113 (clobber (match_scratch:SI 3 ""))]
4114 "BYTES_BIG_ENDIAN && reload_completed"
4115 [(set (match_dup 3)
4116 (zero_extend:SI (subreg:QI
4117 (rotate:SI (match_dup 1)
4118 (match_dup 2)) 3)))
4119 (set (match_dup 0)
4120 (compare:CC (match_dup 3)
4121 (const_int 0)))]
4122 "")
4124 (define_insn "*rotlsi3_internal9le"
4125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4126 (compare:CC (zero_extend:SI
4127 (subreg:QI
4128 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4129 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4130 (const_int 0)))
4131 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4132 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4133 "!BYTES_BIG_ENDIAN"
4134 "@
4135 rlw%I2nm. %0,%1,%h2,0xff
4136 #"
4137 [(set_attr "type" "shift")
4138 (set_attr "maybe_var_shift" "yes")
4139 (set_attr "dot" "yes")
4140 (set_attr "length" "4,8")])
4142 (define_insn "*rotlsi3_internal9be"
4143 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4144 (compare:CC (zero_extend:SI
4145 (subreg:QI
4146 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 3))
4148 (const_int 0)))
4149 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4150 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4151 "BYTES_BIG_ENDIAN"
4152 "@
4153 rlw%I2nm. %0,%1,%h2,0xff
4154 #"
4155 [(set_attr "type" "shift")
4156 (set_attr "maybe_var_shift" "yes")
4157 (set_attr "dot" "yes")
4158 (set_attr "length" "4,8")])
4160 (define_split
4161 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4162 (compare:CC (zero_extend:SI
4163 (subreg:QI
4164 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4165 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4166 (const_int 0)))
4167 (set (match_operand:SI 0 "gpc_reg_operand" "")
4168 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4169 "!BYTES_BIG_ENDIAN && reload_completed"
4170 [(set (match_dup 0)
4171 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4172 (set (match_dup 3)
4173 (compare:CC (match_dup 0)
4174 (const_int 0)))]
4175 "")
4177 (define_split
4178 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4179 (compare:CC (zero_extend:SI
4180 (subreg:QI
4181 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4182 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4183 (const_int 0)))
4184 (set (match_operand:SI 0 "gpc_reg_operand" "")
4185 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4186 "BYTES_BIG_ENDIAN && reload_completed"
4187 [(set (match_dup 0)
4188 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4189 (set (match_dup 3)
4190 (compare:CC (match_dup 0)
4191 (const_int 0)))]
4192 "")
4194 (define_insn "*rotlsi3_internal10le"
4195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4196 (zero_extend:SI
4197 (subreg:HI
4198 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4199 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
4200 "!BYTES_BIG_ENDIAN"
4201 "rlw%I2nm %0,%1,%h2,0xffff"
4202 [(set_attr "type" "shift")
4203 (set_attr "maybe_var_shift" "yes")])
4205 (define_insn "*rotlsi3_internal10be"
4206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4207 (zero_extend:SI
4208 (subreg:HI
4209 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4210 (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
4211 "BYTES_BIG_ENDIAN"
4212 "rlw%I2nm %0,%1,%h2,0xffff"
4213 [(set_attr "type" "shift")
4214 (set_attr "maybe_var_shift" "yes")])
4216 (define_insn "*rotlsi3_internal11le"
4217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4218 (compare:CC (zero_extend:SI
4219 (subreg:HI
4220 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4221 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4222 (const_int 0)))
4223 (clobber (match_scratch:SI 3 "=r,r"))]
4224 "!BYTES_BIG_ENDIAN"
4225 "@
4226 rlw%I2nm. %3,%1,%h2,0xffff
4227 #"
4228 [(set_attr "type" "shift")
4229 (set_attr "maybe_var_shift" "yes")
4230 (set_attr "dot" "yes")
4231 (set_attr "length" "4,8")])
4233 (define_insn "*rotlsi3_internal11be"
4234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4235 (compare:CC (zero_extend:SI
4236 (subreg:HI
4237 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4238 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4239 (const_int 0)))
4240 (clobber (match_scratch:SI 3 "=r,r"))]
4241 "BYTES_BIG_ENDIAN"
4242 "@
4243 rlw%I2nm. %3,%1,%h2,0xffff
4244 #"
4245 [(set_attr "type" "shift")
4246 (set_attr "maybe_var_shift" "yes")
4247 (set_attr "dot" "yes")
4248 (set_attr "length" "4,8")])
4250 (define_split
4251 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4252 (compare:CC (zero_extend:SI
4253 (subreg:HI
4254 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4255 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4256 (const_int 0)))
4257 (clobber (match_scratch:SI 3 ""))]
4258 "!BYTES_BIG_ENDIAN && reload_completed"
4259 [(set (match_dup 3)
4260 (zero_extend:SI (subreg:HI
4261 (rotate:SI (match_dup 1)
4262 (match_dup 2)) 0)))
4263 (set (match_dup 0)
4264 (compare:CC (match_dup 3)
4265 (const_int 0)))]
4266 "")
4268 (define_split
4269 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4270 (compare:CC (zero_extend:SI
4271 (subreg:HI
4272 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4273 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4274 (const_int 0)))
4275 (clobber (match_scratch:SI 3 ""))]
4276 "BYTES_BIG_ENDIAN && reload_completed"
4277 [(set (match_dup 3)
4278 (zero_extend:SI (subreg:HI
4279 (rotate:SI (match_dup 1)
4280 (match_dup 2)) 2)))
4281 (set (match_dup 0)
4282 (compare:CC (match_dup 3)
4283 (const_int 0)))]
4284 "")
4286 (define_insn "*rotlsi3_internal12le"
4287 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4288 (compare:CC (zero_extend:SI
4289 (subreg:HI
4290 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4291 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 0))
4292 (const_int 0)))
4293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4294 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4295 "!BYTES_BIG_ENDIAN"
4296 "@
4297 rlw%I2nm. %0,%1,%h2,0xffff
4298 #"
4299 [(set_attr "type" "shift")
4300 (set_attr "maybe_var_shift" "yes")
4301 (set_attr "dot" "yes")
4302 (set_attr "length" "4,8")])
4304 (define_insn "*rotlsi3_internal12be"
4305 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4306 (compare:CC (zero_extend:SI
4307 (subreg:HI
4308 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4309 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")) 2))
4310 (const_int 0)))
4311 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4312 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4313 "BYTES_BIG_ENDIAN"
4314 "@
4315 rlw%I2nm. %0,%1,%h2,0xffff
4316 #"
4317 [(set_attr "type" "shift")
4318 (set_attr "maybe_var_shift" "yes")
4319 (set_attr "dot" "yes")
4320 (set_attr "length" "4,8")])
4322 (define_split
4323 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4324 (compare:CC (zero_extend:SI
4325 (subreg:HI
4326 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4327 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4328 (const_int 0)))
4329 (set (match_operand:SI 0 "gpc_reg_operand" "")
4330 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4331 "!BYTES_BIG_ENDIAN && reload_completed"
4332 [(set (match_dup 0)
4333 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4334 (set (match_dup 3)
4335 (compare:CC (match_dup 0)
4336 (const_int 0)))]
4337 "")
4339 (define_split
4340 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4341 (compare:CC (zero_extend:SI
4342 (subreg:HI
4343 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4344 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4345 (const_int 0)))
4346 (set (match_operand:SI 0 "gpc_reg_operand" "")
4347 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4348 "BYTES_BIG_ENDIAN && reload_completed"
4349 [(set (match_dup 0)
4350 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4351 (set (match_dup 3)
4352 (compare:CC (match_dup 0)
4353 (const_int 0)))]
4354 "")
4357 (define_insn "ashl<mode>3"
4358 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4359 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4360 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4361 ""
4362 "sl<wd>%I2 %0,%1,%<hH>2"
4363 [(set_attr "type" "shift")
4364 (set_attr "maybe_var_shift" "yes")])
4366 (define_insn "*ashlsi3_64"
4367 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4368 (zero_extend:DI
4369 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4370 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4371 "TARGET_POWERPC64"
4372 "slw%I2 %0,%1,%h2"
4373 [(set_attr "type" "shift")
4374 (set_attr "maybe_var_shift" "yes")])
4376 (define_insn_and_split "*ashl<mode>3_dot"
4377 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4378 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4379 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4380 (const_int 0)))
4381 (clobber (match_scratch:GPR 0 "=r,r"))]
4382 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4383 "@
4384 sl<wd>%I2. %0,%1,%<hH>2
4385 #"
4386 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4387 [(set (match_dup 0)
4388 (ashift:GPR (match_dup 1)
4389 (match_dup 2)))
4390 (set (match_dup 3)
4391 (compare:CC (match_dup 0)
4392 (const_int 0)))]
4393 ""
4394 [(set_attr "type" "shift")
4395 (set_attr "maybe_var_shift" "yes")
4396 (set_attr "dot" "yes")
4397 (set_attr "length" "4,8")])
4399 (define_insn_and_split "*ashl<mode>3_dot2"
4400 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4401 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4402 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4403 (const_int 0)))
4404 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4405 (ashift:GPR (match_dup 1)
4406 (match_dup 2)))]
4407 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4408 "@
4409 sl<wd>%I2. %0,%1,%<hH>2
4410 #"
4411 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4412 [(set (match_dup 0)
4413 (ashift:GPR (match_dup 1)
4414 (match_dup 2)))
4415 (set (match_dup 3)
4416 (compare:CC (match_dup 0)
4417 (const_int 0)))]
4418 ""
4419 [(set_attr "type" "shift")
4420 (set_attr "maybe_var_shift" "yes")
4421 (set_attr "dot" "yes")
4422 (set_attr "length" "4,8")])
4425 (define_insn "rlwinm"
4426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4427 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4428 (match_operand:SI 2 "const_int_operand" "i"))
4429 (match_operand:SI 3 "mask_operand" "n")))]
4430 "includes_lshift_p (operands[2], operands[3])"
4431 "rlwinm %0,%1,%h2,%m3,%M3"
4432 [(set_attr "type" "shift")])
4434 (define_insn ""
4435 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4436 (compare:CC
4437 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4438 (match_operand:SI 2 "const_int_operand" "i,i"))
4439 (match_operand:SI 3 "mask_operand" "n,n"))
4440 (const_int 0)))
4441 (clobber (match_scratch:SI 4 "=r,r"))]
4442 "includes_lshift_p (operands[2], operands[3])"
4443 "@
4444 rlwinm. %4,%1,%h2,%m3,%M3
4445 #"
4446 [(set_attr "type" "shift")
4447 (set_attr "dot" "yes")
4448 (set_attr "length" "4,8")])
4450 (define_split
4451 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4452 (compare:CC
4453 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4454 (match_operand:SI 2 "const_int_operand" ""))
4455 (match_operand:SI 3 "mask_operand" ""))
4456 (const_int 0)))
4457 (clobber (match_scratch:SI 4 ""))]
4458 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4459 [(set (match_dup 4)
4460 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4461 (match_dup 3)))
4462 (set (match_dup 0)
4463 (compare:CC (match_dup 4)
4464 (const_int 0)))]
4465 "")
4467 (define_insn ""
4468 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4469 (compare:CC
4470 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4471 (match_operand:SI 2 "const_int_operand" "i,i"))
4472 (match_operand:SI 3 "mask_operand" "n,n"))
4473 (const_int 0)))
4474 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4475 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4476 "includes_lshift_p (operands[2], operands[3])"
4477 "@
4478 rlwinm. %0,%1,%h2,%m3,%M3
4479 #"
4480 [(set_attr "type" "shift")
4481 (set_attr "dot" "yes")
4482 (set_attr "length" "4,8")])
4484 (define_split
4485 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4486 (compare:CC
4487 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4488 (match_operand:SI 2 "const_int_operand" ""))
4489 (match_operand:SI 3 "mask_operand" ""))
4490 (const_int 0)))
4491 (set (match_operand:SI 0 "gpc_reg_operand" "")
4492 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4493 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4494 [(set (match_dup 0)
4495 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4496 (set (match_dup 4)
4497 (compare:CC (match_dup 0)
4498 (const_int 0)))]
4499 "")
4502 (define_insn "lshr<mode>3"
4503 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4504 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4505 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4506 ""
4507 "sr<wd>%I2 %0,%1,%<hH>2"
4508 [(set_attr "type" "shift")
4509 (set_attr "maybe_var_shift" "yes")])
4511 (define_insn "*lshrsi3_64"
4512 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4513 (zero_extend:DI
4514 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4515 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4516 "TARGET_POWERPC64"
4517 "srw%I2 %0,%1,%h2"
4518 [(set_attr "type" "shift")
4519 (set_attr "maybe_var_shift" "yes")])
4521 (define_insn_and_split "*lshr<mode>3_dot"
4522 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4523 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4524 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4525 (const_int 0)))
4526 (clobber (match_scratch:GPR 0 "=r,r"))]
4527 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4528 "@
4529 sr<wd>%I2. %0,%1,%<hH>2
4530 #"
4531 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4532 [(set (match_dup 0)
4533 (lshiftrt:GPR (match_dup 1)
4534 (match_dup 2)))
4535 (set (match_dup 3)
4536 (compare:CC (match_dup 0)
4537 (const_int 0)))]
4538 ""
4539 [(set_attr "type" "shift")
4540 (set_attr "maybe_var_shift" "yes")
4541 (set_attr "dot" "yes")
4542 (set_attr "length" "4,8")])
4544 (define_insn_and_split "*lshr<mode>3_dot2"
4545 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4546 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4547 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4548 (const_int 0)))
4549 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4550 (lshiftrt:GPR (match_dup 1)
4551 (match_dup 2)))]
4552 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4553 "@
4554 sr<wd>%I2. %0,%1,%<hH>2
4555 #"
4556 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4557 [(set (match_dup 0)
4558 (lshiftrt:GPR (match_dup 1)
4559 (match_dup 2)))
4560 (set (match_dup 3)
4561 (compare:CC (match_dup 0)
4562 (const_int 0)))]
4563 ""
4564 [(set_attr "type" "shift")
4565 (set_attr "maybe_var_shift" "yes")
4566 (set_attr "dot" "yes")
4567 (set_attr "length" "4,8")])
4570 (define_insn ""
4571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4572 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4573 (match_operand:SI 2 "const_int_operand" "i"))
4574 (match_operand:SI 3 "mask_operand" "n")))]
4575 "includes_rshift_p (operands[2], operands[3])"
4576 "rlwinm %0,%1,%s2,%m3,%M3"
4577 [(set_attr "type" "shift")])
4579 (define_insn ""
4580 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4581 (compare:CC
4582 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4583 (match_operand:SI 2 "const_int_operand" "i,i"))
4584 (match_operand:SI 3 "mask_operand" "n,n"))
4585 (const_int 0)))
4586 (clobber (match_scratch:SI 4 "=r,r"))]
4587 "includes_rshift_p (operands[2], operands[3])"
4588 "@
4589 rlwinm. %4,%1,%s2,%m3,%M3
4590 #"
4591 [(set_attr "type" "shift")
4592 (set_attr "dot" "yes")
4593 (set_attr "length" "4,8")])
4595 (define_split
4596 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4597 (compare:CC
4598 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4599 (match_operand:SI 2 "const_int_operand" ""))
4600 (match_operand:SI 3 "mask_operand" ""))
4601 (const_int 0)))
4602 (clobber (match_scratch:SI 4 ""))]
4603 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4604 [(set (match_dup 4)
4605 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4606 (match_dup 3)))
4607 (set (match_dup 0)
4608 (compare:CC (match_dup 4)
4609 (const_int 0)))]
4610 "")
4612 (define_insn ""
4613 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4614 (compare:CC
4615 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4616 (match_operand:SI 2 "const_int_operand" "i,i"))
4617 (match_operand:SI 3 "mask_operand" "n,n"))
4618 (const_int 0)))
4619 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4620 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4621 "includes_rshift_p (operands[2], operands[3])"
4622 "@
4623 rlwinm. %0,%1,%s2,%m3,%M3
4624 #"
4625 [(set_attr "type" "shift")
4626 (set_attr "dot" "yes")
4627 (set_attr "length" "4,8")])
4629 (define_split
4630 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4631 (compare:CC
4632 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4633 (match_operand:SI 2 "const_int_operand" ""))
4634 (match_operand:SI 3 "mask_operand" ""))
4635 (const_int 0)))
4636 (set (match_operand:SI 0 "gpc_reg_operand" "")
4637 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4638 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4639 [(set (match_dup 0)
4640 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4641 (set (match_dup 4)
4642 (compare:CC (match_dup 0)
4643 (const_int 0)))]
4644 "")
4646 (define_insn "*lshiftrt_internal1le"
4647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4648 (zero_extend:SI
4649 (subreg:QI
4650 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4651 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4652 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4653 "rlwinm %0,%1,%s2,0xff"
4654 [(set_attr "type" "shift")])
4656 (define_insn "*lshiftrt_internal1be"
4657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4658 (zero_extend:SI
4659 (subreg:QI
4660 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4661 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4662 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4663 "rlwinm %0,%1,%s2,0xff"
4664 [(set_attr "type" "shift")])
4666 (define_insn "*lshiftrt_internal2le"
4667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4668 (compare:CC
4669 (zero_extend:SI
4670 (subreg:QI
4671 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4672 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4673 (const_int 0)))
4674 (clobber (match_scratch:SI 3 "=r,r"))]
4675 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4676 "@
4677 rlwinm. %3,%1,%s2,0xff
4678 #"
4679 [(set_attr "type" "shift")
4680 (set_attr "dot" "yes")
4681 (set_attr "length" "4,8")])
4683 (define_insn "*lshiftrt_internal2be"
4684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4685 (compare:CC
4686 (zero_extend:SI
4687 (subreg:QI
4688 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4689 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4690 (const_int 0)))
4691 (clobber (match_scratch:SI 3 "=r,r"))]
4692 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4693 "@
4694 rlwinm. %3,%1,%s2,0xff
4695 #"
4696 [(set_attr "type" "shift")
4697 (set_attr "dot" "yes")
4698 (set_attr "length" "4,8")])
4700 (define_split
4701 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4702 (compare:CC
4703 (zero_extend:SI
4704 (subreg:QI
4705 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4706 (match_operand:SI 2 "const_int_operand" "")) 0))
4707 (const_int 0)))
4708 (clobber (match_scratch:SI 3 ""))]
4709 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4710 [(set (match_dup 3)
4711 (zero_extend:SI (subreg:QI
4712 (lshiftrt:SI (match_dup 1)
4713 (match_dup 2)) 0)))
4714 (set (match_dup 0)
4715 (compare:CC (match_dup 3)
4716 (const_int 0)))]
4717 "")
4719 (define_split
4720 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4721 (compare:CC
4722 (zero_extend:SI
4723 (subreg:QI
4724 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4725 (match_operand:SI 2 "const_int_operand" "")) 3))
4726 (const_int 0)))
4727 (clobber (match_scratch:SI 3 ""))]
4728 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4729 [(set (match_dup 3)
4730 (zero_extend:SI (subreg:QI
4731 (lshiftrt:SI (match_dup 1)
4732 (match_dup 2)) 3)))
4733 (set (match_dup 0)
4734 (compare:CC (match_dup 3)
4735 (const_int 0)))]
4736 "")
4738 (define_insn "*lshiftrt_internal3le"
4739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4740 (compare:CC
4741 (zero_extend:SI
4742 (subreg:QI
4743 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4744 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4745 (const_int 0)))
4746 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4747 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4748 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4749 "@
4750 rlwinm. %0,%1,%s2,0xff
4751 #"
4752 [(set_attr "type" "shift")
4753 (set_attr "dot" "yes")
4754 (set_attr "length" "4,8")])
4756 (define_insn "*lshiftrt_internal3be"
4757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4758 (compare:CC
4759 (zero_extend:SI
4760 (subreg:QI
4761 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4762 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4763 (const_int 0)))
4764 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4765 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4766 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4767 "@
4768 rlwinm. %0,%1,%s2,0xff
4769 #"
4770 [(set_attr "type" "shift")
4771 (set_attr "dot" "yes")
4772 (set_attr "length" "4,8")])
4774 (define_split
4775 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4776 (compare:CC
4777 (zero_extend:SI
4778 (subreg:QI
4779 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4780 (match_operand:SI 2 "const_int_operand" "")) 0))
4781 (const_int 0)))
4782 (set (match_operand:SI 0 "gpc_reg_operand" "")
4783 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4784 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4785 [(set (match_dup 0)
4786 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4787 (set (match_dup 3)
4788 (compare:CC (match_dup 0)
4789 (const_int 0)))]
4790 "")
4792 (define_split
4793 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4794 (compare:CC
4795 (zero_extend:SI
4796 (subreg:QI
4797 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4798 (match_operand:SI 2 "const_int_operand" "")) 3))
4799 (const_int 0)))
4800 (set (match_operand:SI 0 "gpc_reg_operand" "")
4801 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4802 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4803 [(set (match_dup 0)
4804 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4805 (set (match_dup 3)
4806 (compare:CC (match_dup 0)
4807 (const_int 0)))]
4808 "")
4810 (define_insn "*lshiftrt_internal4le"
4811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4812 (zero_extend:SI
4813 (subreg:HI
4814 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4815 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4816 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4817 "rlwinm %0,%1,%s2,0xffff"
4818 [(set_attr "type" "shift")])
4820 (define_insn "*lshiftrt_internal4be"
4821 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4822 (zero_extend:SI
4823 (subreg:HI
4824 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4825 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4826 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4827 "rlwinm %0,%1,%s2,0xffff"
4828 [(set_attr "type" "shift")])
4830 (define_insn "*lshiftrt_internal5le"
4831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4832 (compare:CC
4833 (zero_extend:SI
4834 (subreg:HI
4835 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4836 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4837 (const_int 0)))
4838 (clobber (match_scratch:SI 3 "=r,r"))]
4839 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4840 "@
4841 rlwinm. %3,%1,%s2,0xffff
4842 #"
4843 [(set_attr "type" "shift")
4844 (set_attr "dot" "yes")
4845 (set_attr "length" "4,8")])
4847 (define_insn "*lshiftrt_internal5be"
4848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4849 (compare:CC
4850 (zero_extend:SI
4851 (subreg:HI
4852 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4853 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4854 (const_int 0)))
4855 (clobber (match_scratch:SI 3 "=r,r"))]
4856 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4857 "@
4858 rlwinm. %3,%1,%s2,0xffff
4859 #"
4860 [(set_attr "type" "shift")
4861 (set_attr "dot" "yes")
4862 (set_attr "length" "4,8")])
4864 (define_split
4865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4866 (compare:CC
4867 (zero_extend:SI
4868 (subreg:HI
4869 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4870 (match_operand:SI 2 "const_int_operand" "")) 0))
4871 (const_int 0)))
4872 (clobber (match_scratch:SI 3 ""))]
4873 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4874 [(set (match_dup 3)
4875 (zero_extend:SI (subreg:HI
4876 (lshiftrt:SI (match_dup 1)
4877 (match_dup 2)) 0)))
4878 (set (match_dup 0)
4879 (compare:CC (match_dup 3)
4880 (const_int 0)))]
4881 "")
4883 (define_split
4884 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4885 (compare:CC
4886 (zero_extend:SI
4887 (subreg:HI
4888 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4889 (match_operand:SI 2 "const_int_operand" "")) 2))
4890 (const_int 0)))
4891 (clobber (match_scratch:SI 3 ""))]
4892 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4893 [(set (match_dup 3)
4894 (zero_extend:SI (subreg:HI
4895 (lshiftrt:SI (match_dup 1)
4896 (match_dup 2)) 2)))
4897 (set (match_dup 0)
4898 (compare:CC (match_dup 3)
4899 (const_int 0)))]
4900 "")
4902 (define_insn "*lshiftrt_internal5le"
4903 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4904 (compare:CC
4905 (zero_extend:SI
4906 (subreg:HI
4907 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4908 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4909 (const_int 0)))
4910 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4911 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4912 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4913 "@
4914 rlwinm. %0,%1,%s2,0xffff
4915 #"
4916 [(set_attr "type" "shift")
4917 (set_attr "dot" "yes")
4918 (set_attr "length" "4,8")])
4920 (define_insn "*lshiftrt_internal5be"
4921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4922 (compare:CC
4923 (zero_extend:SI
4924 (subreg:HI
4925 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4926 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4927 (const_int 0)))
4928 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4929 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4930 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4931 "@
4932 rlwinm. %0,%1,%s2,0xffff
4933 #"
4934 [(set_attr "type" "shift")
4935 (set_attr "dot" "yes")
4936 (set_attr "length" "4,8")])
4938 (define_split
4939 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4940 (compare:CC
4941 (zero_extend:SI
4942 (subreg:HI
4943 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4944 (match_operand:SI 2 "const_int_operand" "")) 0))
4945 (const_int 0)))
4946 (set (match_operand:SI 0 "gpc_reg_operand" "")
4947 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4948 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4949 [(set (match_dup 0)
4950 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4951 (set (match_dup 3)
4952 (compare:CC (match_dup 0)
4953 (const_int 0)))]
4954 "")
4956 (define_split
4957 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4958 (compare:CC
4959 (zero_extend:SI
4960 (subreg:HI
4961 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4962 (match_operand:SI 2 "const_int_operand" "")) 2))
4963 (const_int 0)))
4964 (set (match_operand:SI 0 "gpc_reg_operand" "")
4965 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4966 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4967 [(set (match_dup 0)
4968 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4969 (set (match_dup 3)
4970 (compare:CC (match_dup 0)
4971 (const_int 0)))]
4972 "")
4975 (define_expand "ashr<mode>3"
4976 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4977 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
4978 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4979 ""
4980 {
4981 /* The generic code does not generate optimal code for the low word
4982 (it should be a rlwimi and a rot). Until we have target code to
4983 solve this generically, keep this expander. */
4985 if (<MODE>mode == DImode && !TARGET_POWERPC64)
4986 {
4987 if (CONST_INT_P (operands[2]))
4988 {
4989 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
4990 DONE;
4991 }
4992 else
4993 FAIL;
4994 }
4995 })
4997 (define_insn "*ashr<mode>3"
4998 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4999 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
5000 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
5001 ""
5002 "sra<wd>%I2 %0,%1,%<hH>2"
5003 [(set_attr "type" "shift")
5004 (set_attr "maybe_var_shift" "yes")])
5006 (define_insn "*ashrsi3_64"
5007 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5008 (sign_extend:DI
5009 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5010 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
5011 "TARGET_POWERPC64"
5012 "sraw%I2 %0,%1,%h2"
5013 [(set_attr "type" "shift")
5014 (set_attr "maybe_var_shift" "yes")])
5016 (define_insn_and_split "*ashr<mode>3_dot"
5017 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5018 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
5019 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
5020 (const_int 0)))
5021 (clobber (match_scratch:GPR 0 "=r,r"))]
5022 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
5023 "@
5024 sra<wd>%I2. %0,%1,%<hH>2
5025 #"
5026 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
5027 [(set (match_dup 0)
5028 (ashiftrt:GPR (match_dup 1)
5029 (match_dup 2)))
5030 (set (match_dup 3)
5031 (compare:CC (match_dup 0)
5032 (const_int 0)))]
5033 ""
5034 [(set_attr "type" "shift")
5035 (set_attr "maybe_var_shift" "yes")
5036 (set_attr "dot" "yes")
5037 (set_attr "length" "4,8")])
5039 (define_insn_and_split "*ashr<mode>3_dot2"
5040 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5041 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
5042 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
5043 (const_int 0)))
5044 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5045 (ashiftrt:GPR (match_dup 1)
5046 (match_dup 2)))]
5047 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
5048 "@
5049 sra<wd>%I2. %0,%1,%<hH>2
5050 #"
5051 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
5052 [(set (match_dup 0)
5053 (ashiftrt:GPR (match_dup 1)
5054 (match_dup 2)))
5055 (set (match_dup 3)
5056 (compare:CC (match_dup 0)
5057 (const_int 0)))]
5058 ""
5059 [(set_attr "type" "shift")
5060 (set_attr "maybe_var_shift" "yes")
5061 (set_attr "dot" "yes")
5062 (set_attr "length" "4,8")])
5063 \f
5064 ;; Builtins to replace a division to generate FRE reciprocal estimate
5065 ;; instructions and the necessary fixup instructions
5066 (define_expand "recip<mode>3"
5067 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5068 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5069 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5070 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5071 {
5072 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5073 DONE;
5074 })
5076 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5077 ;; hardware division. This is only done before register allocation and with
5078 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5079 (define_split
5080 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5081 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5082 (match_operand 2 "gpc_reg_operand" "")))]
5083 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5084 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5085 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5086 [(const_int 0)]
5087 {
5088 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5089 DONE;
5090 })
5092 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5093 ;; appropriate fixup.
5094 (define_expand "rsqrt<mode>2"
5095 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5096 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5097 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5098 {
5099 rs6000_emit_swrsqrt (operands[0], operands[1]);
5100 DONE;
5101 })
5102 \f
5103 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
5104 ;; modes here, and also add in conditional vsx/power8-vector support to access
5105 ;; values in the traditional Altivec registers if the appropriate
5106 ;; -mupper-regs-{df,sf} option is enabled.
5108 (define_expand "abs<mode>2"
5109 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5110 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5111 "TARGET_<MODE>_INSN"
5112 "")
5114 (define_insn "*abs<mode>2_fpr"
5115 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5116 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5117 "TARGET_<MODE>_FPR"
5118 "@
5119 fabs %0,%1
5120 xsabsdp %x0,%x1"
5121 [(set_attr "type" "fp")
5122 (set_attr "fp_type" "fp_addsub_<Fs>")])
5124 (define_insn "*nabs<mode>2_fpr"
5125 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5126 (neg:SFDF
5127 (abs:SFDF
5128 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
5129 "TARGET_<MODE>_FPR"
5130 "@
5131 fnabs %0,%1
5132 xsnabsdp %x0,%x1"
5133 [(set_attr "type" "fp")
5134 (set_attr "fp_type" "fp_addsub_<Fs>")])
5136 (define_expand "neg<mode>2"
5137 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5138 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5139 "TARGET_<MODE>_INSN"
5140 "")
5142 (define_insn "*neg<mode>2_fpr"
5143 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5144 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5145 "TARGET_<MODE>_FPR"
5146 "@
5147 fneg %0,%1
5148 xsnegdp %x0,%x1"
5149 [(set_attr "type" "fp")
5150 (set_attr "fp_type" "fp_addsub_<Fs>")])
5152 (define_expand "add<mode>3"
5153 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5154 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5155 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5156 "TARGET_<MODE>_INSN"
5157 "")
5159 (define_insn "*add<mode>3_fpr"
5160 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5161 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5162 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5163 "TARGET_<MODE>_FPR"
5164 "@
5165 fadd<Ftrad> %0,%1,%2
5166 xsadd<Fvsx> %x0,%x1,%x2"
5167 [(set_attr "type" "fp")
5168 (set_attr "fp_type" "fp_addsub_<Fs>")])
5170 (define_expand "sub<mode>3"
5171 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5172 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5173 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5174 "TARGET_<MODE>_INSN"
5175 "")
5177 (define_insn "*sub<mode>3_fpr"
5178 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5179 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5180 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5181 "TARGET_<MODE>_FPR"
5182 "@
5183 fsub<Ftrad> %0,%1,%2
5184 xssub<Fvsx> %x0,%x1,%x2"
5185 [(set_attr "type" "fp")
5186 (set_attr "fp_type" "fp_addsub_<Fs>")])
5188 (define_expand "mul<mode>3"
5189 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5190 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5191 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5192 "TARGET_<MODE>_INSN"
5193 "")
5195 (define_insn "*mul<mode>3_fpr"
5196 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5197 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5198 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5199 "TARGET_<MODE>_FPR"
5200 "@
5201 fmul<Ftrad> %0,%1,%2
5202 xsmul<Fvsx> %x0,%x1,%x2"
5203 [(set_attr "type" "dmul")
5204 (set_attr "fp_type" "fp_mul_<Fs>")])
5206 (define_expand "div<mode>3"
5207 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5208 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5209 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5210 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
5211 "")
5213 (define_insn "*div<mode>3_fpr"
5214 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5215 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5216 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5217 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
5218 "@
5219 fdiv<Ftrad> %0,%1,%2
5220 xsdiv<Fvsx> %x0,%x1,%x2"
5221 [(set_attr "type" "<Fs>div")
5222 (set_attr "fp_type" "fp_div_<Fs>")])
5224 (define_insn "sqrt<mode>2"
5225 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5226 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5227 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
5228 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
5229 "@
5230 fsqrt<Ftrad> %0,%1
5231 xssqrt<Fvsx> %x0,%x1"
5232 [(set_attr "type" "<Fs>sqrt")
5233 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5235 ;; Floating point reciprocal approximation
5236 (define_insn "fre<Fs>"
5237 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5238 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5239 UNSPEC_FRES))]
5240 "TARGET_<FFRE>"
5241 "@
5242 fre<Ftrad> %0,%1
5243 xsre<Fvsx> %x0,%x1"
5244 [(set_attr "type" "fp")])
5246 (define_insn "*rsqrt<mode>2"
5247 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5248 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5249 UNSPEC_RSQRT))]
5250 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5251 "@
5252 frsqrte<Ftrad> %0,%1
5253 xsrsqrte<Fvsx> %x0,%x1"
5254 [(set_attr "type" "fp")])
5256 ;; Floating point comparisons
5257 (define_insn "*cmp<mode>_fpr"
5258 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5259 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5260 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5261 "TARGET_<MODE>_FPR"
5262 "@
5263 fcmpu %0,%1,%2
5264 xscmpudp %0,%x1,%x2"
5265 [(set_attr "type" "fpcompare")])
5267 ;; Floating point conversions
5268 (define_expand "extendsfdf2"
5269 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5270 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5271 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5272 "")
5274 (define_insn_and_split "*extendsfdf2_fpr"
5275 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5276 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5277 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5278 "@
5279 #
5280 fmr %0,%1
5281 lfs%U1%X1 %0,%1
5282 #
5283 xxlor %x0,%x1,%x1
5284 lxsspx %x0,%y1"
5285 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5286 [(const_int 0)]
5287 {
5288 emit_note (NOTE_INSN_DELETED);
5289 DONE;
5290 }
5291 [(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
5293 (define_expand "truncdfsf2"
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5295 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5296 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5297 "")
5299 (define_insn "*truncdfsf2_fpr"
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5302 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5303 "frsp %0,%1"
5304 [(set_attr "type" "fp")])
5306 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5307 ;; builtins.c and optabs.c that are not correct for IBM long double
5308 ;; when little-endian.
5309 (define_expand "signbittf2"
5310 [(set (match_dup 2)
5311 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5312 (set (match_dup 3)
5313 (subreg:DI (match_dup 2) 0))
5314 (set (match_dup 4)
5315 (match_dup 5))
5316 (set (match_operand:SI 0 "gpc_reg_operand" "")
5317 (match_dup 6))]
5318 "!TARGET_IEEEQUAD
5319 && TARGET_HARD_FLOAT
5320 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5321 && TARGET_LONG_DOUBLE_128"
5322 {
5323 operands[2] = gen_reg_rtx (DFmode);
5324 operands[3] = gen_reg_rtx (DImode);
5325 if (TARGET_POWERPC64)
5326 {
5327 operands[4] = gen_reg_rtx (DImode);
5328 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5329 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5330 WORDS_BIG_ENDIAN ? 4 : 0);
5331 }
5332 else
5333 {
5334 operands[4] = gen_reg_rtx (SImode);
5335 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5336 WORDS_BIG_ENDIAN ? 0 : 4);
5337 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5338 }
5339 })
5341 (define_expand "copysign<mode>3"
5342 [(set (match_dup 3)
5343 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5344 (set (match_dup 4)
5345 (neg:SFDF (abs:SFDF (match_dup 1))))
5346 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5347 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5348 (match_dup 5))
5349 (match_dup 3)
5350 (match_dup 4)))]
5351 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5352 && ((TARGET_PPC_GFXOPT
5353 && !HONOR_NANS (<MODE>mode)
5354 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5355 || TARGET_CMPB
5356 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5357 {
5358 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5359 {
5360 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5361 operands[2]));
5362 DONE;
5363 }
5365 operands[3] = gen_reg_rtx (<MODE>mode);
5366 operands[4] = gen_reg_rtx (<MODE>mode);
5367 operands[5] = CONST0_RTX (<MODE>mode);
5368 })
5370 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5371 ;; compiler from optimizing -0.0
5372 (define_insn "copysign<mode>3_fcpsgn"
5373 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5374 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5375 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5376 UNSPEC_COPYSIGN))]
5377 "TARGET_<MODE>_FPR && TARGET_CMPB"
5378 "@
5379 fcpsgn %0,%2,%1
5380 xscpsgn<Fvsx> %x0,%x2,%x1"
5381 [(set_attr "type" "fp")])
5383 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5384 ;; fsel instruction and some auxiliary computations. Then we just have a
5385 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5386 ;; combine.
5387 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5388 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5389 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5390 ;; define_splits to make them if made by combine. On VSX machines we have the
5391 ;; min/max instructions.
5392 ;;
5393 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5394 ;; to allow either DF/SF to use only traditional registers.
5396 (define_expand "smax<mode>3"
5397 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5398 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5399 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5400 (match_dup 1)
5401 (match_dup 2)))]
5402 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5403 {
5404 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5405 DONE;
5406 })
5408 (define_insn "*smax<mode>3_vsx"
5409 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5410 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5411 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5412 "TARGET_<MODE>_FPR && TARGET_VSX"
5413 "xsmaxdp %x0,%x1,%x2"
5414 [(set_attr "type" "fp")])
5416 (define_expand "smin<mode>3"
5417 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5418 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5419 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5420 (match_dup 2)
5421 (match_dup 1)))]
5422 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5423 {
5424 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5425 DONE;
5426 })
5428 (define_insn "*smin<mode>3_vsx"
5429 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5430 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5431 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5432 "TARGET_<MODE>_FPR && TARGET_VSX"
5433 "xsmindp %x0,%x1,%x2"
5434 [(set_attr "type" "fp")])
5436 (define_split
5437 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5438 (match_operator:SFDF 3 "min_max_operator"
5439 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5440 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5441 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5442 && !TARGET_VSX"
5443 [(const_int 0)]
5444 {
5445 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5446 operands[2]);
5447 DONE;
5448 })
5450 (define_split
5451 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5452 (match_operator:SF 3 "min_max_operator"
5453 [(match_operand:SF 1 "gpc_reg_operand" "")
5454 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5455 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5456 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5457 [(const_int 0)]
5458 "
5459 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5460 operands[1], operands[2]);
5461 DONE;
5462 }")
5464 (define_expand "mov<mode>cc"
5465 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5466 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5467 (match_operand:GPR 2 "gpc_reg_operand" "")
5468 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5469 "TARGET_ISEL<sel>"
5470 "
5471 {
5472 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5473 DONE;
5474 else
5475 FAIL;
5476 }")
5478 ;; We use the BASE_REGS for the isel input operands because, if rA is
5479 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5480 ;; because we may switch the operands and rB may end up being rA.
5481 ;;
5482 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5483 ;; leave out the mode in operand 4 and use one pattern, but reload can
5484 ;; change the mode underneath our feet and then gets confused trying
5485 ;; to reload the value.
5486 (define_insn "isel_signed_<mode>"
5487 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5488 (if_then_else:GPR
5489 (match_operator 1 "scc_comparison_operator"
5490 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5491 (const_int 0)])
5492 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5493 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5494 "TARGET_ISEL<sel>"
5495 "*
5496 { return output_isel (operands); }"
5497 [(set_attr "type" "isel")
5498 (set_attr "length" "4")])
5500 (define_insn "isel_unsigned_<mode>"
5501 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5502 (if_then_else:GPR
5503 (match_operator 1 "scc_comparison_operator"
5504 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5505 (const_int 0)])
5506 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5507 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5508 "TARGET_ISEL<sel>"
5509 "*
5510 { return output_isel (operands); }"
5511 [(set_attr "type" "isel")
5512 (set_attr "length" "4")])
5514 ;; These patterns can be useful for combine; they let combine know that
5515 ;; isel can handle reversed comparisons so long as the operands are
5516 ;; registers.
5518 (define_insn "*isel_reversed_signed_<mode>"
5519 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5520 (if_then_else:GPR
5521 (match_operator 1 "scc_rev_comparison_operator"
5522 [(match_operand:CC 4 "cc_reg_operand" "y")
5523 (const_int 0)])
5524 (match_operand:GPR 2 "gpc_reg_operand" "b")
5525 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5526 "TARGET_ISEL<sel>"
5527 "*
5528 { return output_isel (operands); }"
5529 [(set_attr "type" "isel")
5530 (set_attr "length" "4")])
5532 (define_insn "*isel_reversed_unsigned_<mode>"
5533 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5534 (if_then_else:GPR
5535 (match_operator 1 "scc_rev_comparison_operator"
5536 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5537 (const_int 0)])
5538 (match_operand:GPR 2 "gpc_reg_operand" "b")
5539 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5540 "TARGET_ISEL<sel>"
5541 "*
5542 { return output_isel (operands); }"
5543 [(set_attr "type" "isel")
5544 (set_attr "length" "4")])
5546 (define_expand "movsfcc"
5547 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5548 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5549 (match_operand:SF 2 "gpc_reg_operand" "")
5550 (match_operand:SF 3 "gpc_reg_operand" "")))]
5551 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5552 "
5553 {
5554 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5555 DONE;
5556 else
5557 FAIL;
5558 }")
5560 (define_insn "*fselsfsf4"
5561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5562 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5563 (match_operand:SF 4 "zero_fp_constant" "F"))
5564 (match_operand:SF 2 "gpc_reg_operand" "f")
5565 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5566 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5567 "fsel %0,%1,%2,%3"
5568 [(set_attr "type" "fp")])
5570 (define_insn "*fseldfsf4"
5571 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5572 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5573 (match_operand:DF 4 "zero_fp_constant" "F"))
5574 (match_operand:SF 2 "gpc_reg_operand" "f")
5575 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5576 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5577 "fsel %0,%1,%2,%3"
5578 [(set_attr "type" "fp")])
5580 ;; The conditional move instructions allow us to perform max and min
5581 ;; operations even when
5583 (define_split
5584 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5585 (match_operator:DF 3 "min_max_operator"
5586 [(match_operand:DF 1 "gpc_reg_operand" "")
5587 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5588 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5589 && !flag_trapping_math"
5590 [(const_int 0)]
5591 "
5592 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5593 operands[1], operands[2]);
5594 DONE;
5595 }")
5597 (define_expand "movdfcc"
5598 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5599 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5600 (match_operand:DF 2 "gpc_reg_operand" "")
5601 (match_operand:DF 3 "gpc_reg_operand" "")))]
5602 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5603 "
5604 {
5605 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5606 DONE;
5607 else
5608 FAIL;
5609 }")
5611 (define_insn "*fseldfdf4"
5612 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5613 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5614 (match_operand:DF 4 "zero_fp_constant" "F"))
5615 (match_operand:DF 2 "gpc_reg_operand" "d")
5616 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5617 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5618 "fsel %0,%1,%2,%3"
5619 [(set_attr "type" "fp")])
5621 (define_insn "*fselsfdf4"
5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5623 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5624 (match_operand:SF 4 "zero_fp_constant" "F"))
5625 (match_operand:DF 2 "gpc_reg_operand" "d")
5626 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5627 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5628 "fsel %0,%1,%2,%3"
5629 [(set_attr "type" "fp")])
5630 \f
5631 ;; Conversions to and from floating-point.
5633 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5634 ; don't want to support putting SImode in FPR registers.
5635 (define_insn "lfiwax"
5636 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
5637 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5638 UNSPEC_LFIWAX))]
5639 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5640 "@
5641 lfiwax %0,%y1
5642 lxsiwax %x0,%y1
5643 mtvsrwa %x0,%1"
5644 [(set_attr "type" "fpload,fpload,mffgpr")])
5646 ; This split must be run before register allocation because it allocates the
5647 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5648 ; it earlier to allow for the combiner to merge insns together where it might
5649 ; not be needed and also in case the insns are deleted as dead code.
5651 (define_insn_and_split "floatsi<mode>2_lfiwax"
5652 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5653 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5654 (clobber (match_scratch:DI 2 "=d"))]
5655 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5656 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5657 "#"
5658 ""
5659 [(pc)]
5660 "
5661 {
5662 rtx dest = operands[0];
5663 rtx src = operands[1];
5664 rtx tmp;
5666 if (!MEM_P (src) && TARGET_POWERPC64
5667 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5668 tmp = convert_to_mode (DImode, src, false);
5669 else
5670 {
5671 tmp = operands[2];
5672 if (GET_CODE (tmp) == SCRATCH)
5673 tmp = gen_reg_rtx (DImode);
5674 if (MEM_P (src))
5675 {
5676 src = rs6000_address_for_fpconvert (src);
5677 emit_insn (gen_lfiwax (tmp, src));
5678 }
5679 else
5680 {
5681 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5682 emit_move_insn (stack, src);
5683 emit_insn (gen_lfiwax (tmp, stack));
5684 }
5685 }
5686 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5687 DONE;
5688 }"
5689 [(set_attr "length" "12")
5690 (set_attr "type" "fpload")])
5692 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5693 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5694 (float:SFDF
5695 (sign_extend:DI
5696 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5697 (clobber (match_scratch:DI 2 "=0,d"))]
5698 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5699 && <SI_CONVERT_FP>"
5700 "#"
5701 ""
5702 [(pc)]
5703 "
5704 {
5705 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5706 if (GET_CODE (operands[2]) == SCRATCH)
5707 operands[2] = gen_reg_rtx (DImode);
5708 emit_insn (gen_lfiwax (operands[2], operands[1]));
5709 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5710 DONE;
5711 }"
5712 [(set_attr "length" "8")
5713 (set_attr "type" "fpload")])
5715 (define_insn "lfiwzx"
5716 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
5717 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5718 UNSPEC_LFIWZX))]
5719 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5720 "@
5721 lfiwzx %0,%y1
5722 lxsiwzx %x0,%y1
5723 mtvsrwz %x0,%1"
5724 [(set_attr "type" "fpload,fpload,mftgpr")])
5726 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5727 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5728 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5729 (clobber (match_scratch:DI 2 "=d"))]
5730 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5731 && <SI_CONVERT_FP>"
5732 "#"
5733 ""
5734 [(pc)]
5735 "
5736 {
5737 rtx dest = operands[0];
5738 rtx src = operands[1];
5739 rtx tmp;
5741 if (!MEM_P (src) && TARGET_POWERPC64
5742 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5743 tmp = convert_to_mode (DImode, src, true);
5744 else
5745 {
5746 tmp = operands[2];
5747 if (GET_CODE (tmp) == SCRATCH)
5748 tmp = gen_reg_rtx (DImode);
5749 if (MEM_P (src))
5750 {
5751 src = rs6000_address_for_fpconvert (src);
5752 emit_insn (gen_lfiwzx (tmp, src));
5753 }
5754 else
5755 {
5756 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5757 emit_move_insn (stack, src);
5758 emit_insn (gen_lfiwzx (tmp, stack));
5759 }
5760 }
5761 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5762 DONE;
5763 }"
5764 [(set_attr "length" "12")
5765 (set_attr "type" "fpload")])
5767 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5768 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5769 (unsigned_float:SFDF
5770 (zero_extend:DI
5771 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5772 (clobber (match_scratch:DI 2 "=0,d"))]
5773 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5774 && <SI_CONVERT_FP>"
5775 "#"
5776 ""
5777 [(pc)]
5778 "
5779 {
5780 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5781 if (GET_CODE (operands[2]) == SCRATCH)
5782 operands[2] = gen_reg_rtx (DImode);
5783 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5784 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5785 DONE;
5786 }"
5787 [(set_attr "length" "8")
5788 (set_attr "type" "fpload")])
5790 ; For each of these conversions, there is a define_expand, a define_insn
5791 ; with a '#' template, and a define_split (with C code). The idea is
5792 ; to allow constant folding with the template of the define_insn,
5793 ; then to have the insns split later (between sched1 and final).
5795 (define_expand "floatsidf2"
5796 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5797 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5798 (use (match_dup 2))
5799 (use (match_dup 3))
5800 (clobber (match_dup 4))
5801 (clobber (match_dup 5))
5802 (clobber (match_dup 6))])]
5803 "TARGET_HARD_FLOAT
5804 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5805 "
5806 {
5807 if (TARGET_E500_DOUBLE)
5808 {
5809 if (!REG_P (operands[1]))
5810 operands[1] = force_reg (SImode, operands[1]);
5811 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5812 DONE;
5813 }
5814 else if (TARGET_LFIWAX && TARGET_FCFID)
5815 {
5816 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5817 DONE;
5818 }
5819 else if (TARGET_FCFID)
5820 {
5821 rtx dreg = operands[1];
5822 if (!REG_P (dreg))
5823 dreg = force_reg (SImode, dreg);
5824 dreg = convert_to_mode (DImode, dreg, false);
5825 emit_insn (gen_floatdidf2 (operands[0], dreg));
5826 DONE;
5827 }
5829 if (!REG_P (operands[1]))
5830 operands[1] = force_reg (SImode, operands[1]);
5831 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5832 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5833 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5834 operands[5] = gen_reg_rtx (DFmode);
5835 operands[6] = gen_reg_rtx (SImode);
5836 }")
5838 (define_insn_and_split "*floatsidf2_internal"
5839 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5840 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5841 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5842 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5843 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5844 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5845 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5846 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5847 "#"
5848 ""
5849 [(pc)]
5850 "
5851 {
5852 rtx lowword, highword;
5853 gcc_assert (MEM_P (operands[4]));
5854 highword = adjust_address (operands[4], SImode, 0);
5855 lowword = adjust_address (operands[4], SImode, 4);
5856 if (! WORDS_BIG_ENDIAN)
5857 {
5858 rtx tmp;
5859 tmp = highword; highword = lowword; lowword = tmp;
5860 }
5862 emit_insn (gen_xorsi3 (operands[6], operands[1],
5863 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5864 emit_move_insn (lowword, operands[6]);
5865 emit_move_insn (highword, operands[2]);
5866 emit_move_insn (operands[5], operands[4]);
5867 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5868 DONE;
5869 }"
5870 [(set_attr "length" "24")
5871 (set_attr "type" "fp")])
5873 ;; If we don't have a direct conversion to single precision, don't enable this
5874 ;; conversion for 32-bit without fast math, because we don't have the insn to
5875 ;; generate the fixup swizzle to avoid double rounding problems.
5876 (define_expand "floatunssisf2"
5877 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5878 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5879 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5880 && (!TARGET_FPRS
5881 || (TARGET_FPRS
5882 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5883 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5884 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5885 "
5886 {
5887 if (!TARGET_FPRS)
5888 {
5889 if (!REG_P (operands[1]))
5890 operands[1] = force_reg (SImode, operands[1]);
5891 }
5892 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5893 {
5894 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5895 DONE;
5896 }
5897 else
5898 {
5899 rtx dreg = operands[1];
5900 if (!REG_P (dreg))
5901 dreg = force_reg (SImode, dreg);
5902 dreg = convert_to_mode (DImode, dreg, true);
5903 emit_insn (gen_floatdisf2 (operands[0], dreg));
5904 DONE;
5905 }
5906 }")
5908 (define_expand "floatunssidf2"
5909 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5910 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5911 (use (match_dup 2))
5912 (use (match_dup 3))
5913 (clobber (match_dup 4))
5914 (clobber (match_dup 5))])]
5915 "TARGET_HARD_FLOAT
5916 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5917 "
5918 {
5919 if (TARGET_E500_DOUBLE)
5920 {
5921 if (!REG_P (operands[1]))
5922 operands[1] = force_reg (SImode, operands[1]);
5923 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5924 DONE;
5925 }
5926 else if (TARGET_LFIWZX && TARGET_FCFID)
5927 {
5928 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5929 DONE;
5930 }
5931 else if (TARGET_FCFID)
5932 {
5933 rtx dreg = operands[1];
5934 if (!REG_P (dreg))
5935 dreg = force_reg (SImode, dreg);
5936 dreg = convert_to_mode (DImode, dreg, true);
5937 emit_insn (gen_floatdidf2 (operands[0], dreg));
5938 DONE;
5939 }
5941 if (!REG_P (operands[1]))
5942 operands[1] = force_reg (SImode, operands[1]);
5943 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5944 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5945 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5946 operands[5] = gen_reg_rtx (DFmode);
5947 }")
5949 (define_insn_and_split "*floatunssidf2_internal"
5950 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5951 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5952 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5953 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5954 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5955 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5956 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5957 && !(TARGET_FCFID && TARGET_POWERPC64)"
5958 "#"
5959 ""
5960 [(pc)]
5961 "
5962 {
5963 rtx lowword, highword;
5964 gcc_assert (MEM_P (operands[4]));
5965 highword = adjust_address (operands[4], SImode, 0);
5966 lowword = adjust_address (operands[4], SImode, 4);
5967 if (! WORDS_BIG_ENDIAN)
5968 {
5969 rtx tmp;
5970 tmp = highword; highword = lowword; lowword = tmp;
5971 }
5973 emit_move_insn (lowword, operands[1]);
5974 emit_move_insn (highword, operands[2]);
5975 emit_move_insn (operands[5], operands[4]);
5976 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5977 DONE;
5978 }"
5979 [(set_attr "length" "20")
5980 (set_attr "type" "fp")])
5982 (define_expand "fix_trunc<mode>si2"
5983 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5984 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5985 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5986 "
5987 {
5988 if (!<E500_CONVERT>)
5989 {
5990 rtx tmp, stack;
5992 if (TARGET_STFIWX)
5993 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5994 else
5995 {
5996 tmp = gen_reg_rtx (DImode);
5997 stack = rs6000_allocate_stack_temp (DImode, true, false);
5998 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5999 tmp, stack));
6000 }
6001 DONE;
6002 }
6003 }")
6005 ; Like the convert to float patterns, this insn must be split before
6006 ; register allocation so that it can allocate the memory slot if it
6007 ; needed
6008 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6009 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6010 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6011 (clobber (match_scratch:DI 2 "=d"))]
6012 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6013 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6014 && TARGET_STFIWX && can_create_pseudo_p ()"
6015 "#"
6016 ""
6017 [(pc)]
6018 {
6019 rtx dest = operands[0];
6020 rtx src = operands[1];
6021 rtx tmp = operands[2];
6023 if (GET_CODE (tmp) == SCRATCH)
6024 tmp = gen_reg_rtx (DImode);
6026 emit_insn (gen_fctiwz_<mode> (tmp, src));
6027 if (MEM_P (dest))
6028 {
6029 dest = rs6000_address_for_fpconvert (dest);
6030 emit_insn (gen_stfiwx (dest, tmp));
6031 DONE;
6032 }
6033 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6034 {
6035 dest = gen_lowpart (DImode, dest);
6036 emit_move_insn (dest, tmp);
6037 DONE;
6038 }
6039 else
6040 {
6041 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6042 emit_insn (gen_stfiwx (stack, tmp));
6043 emit_move_insn (dest, stack);
6044 DONE;
6045 }
6046 }
6047 [(set_attr "length" "12")
6048 (set_attr "type" "fp")])
6050 (define_insn_and_split "fix_trunc<mode>si2_internal"
6051 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6052 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6053 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6054 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6055 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6056 "#"
6057 ""
6058 [(pc)]
6059 "
6060 {
6061 rtx lowword;
6062 gcc_assert (MEM_P (operands[3]));
6063 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6065 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6066 emit_move_insn (operands[3], operands[2]);
6067 emit_move_insn (operands[0], lowword);
6068 DONE;
6069 }"
6070 [(set_attr "length" "16")
6071 (set_attr "type" "fp")])
6073 (define_expand "fix_trunc<mode>di2"
6074 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6075 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6076 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6077 && TARGET_FCFID"
6078 "")
6080 (define_insn "*fix_trunc<mode>di2_fctidz"
6081 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6082 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6083 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6084 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6085 "fctidz %0,%1"
6086 [(set_attr "type" "fp")])
6088 (define_expand "fixuns_trunc<mode>si2"
6089 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6090 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6091 "TARGET_HARD_FLOAT
6092 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6093 || <E500_CONVERT>)"
6094 "
6095 {
6096 if (!<E500_CONVERT>)
6097 {
6098 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6099 DONE;
6100 }
6101 }")
6103 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6104 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6105 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6106 (clobber (match_scratch:DI 2 "=d"))]
6107 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6108 && TARGET_STFIWX && can_create_pseudo_p ()"
6109 "#"
6110 ""
6111 [(pc)]
6112 {
6113 rtx dest = operands[0];
6114 rtx src = operands[1];
6115 rtx tmp = operands[2];
6117 if (GET_CODE (tmp) == SCRATCH)
6118 tmp = gen_reg_rtx (DImode);
6120 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6121 if (MEM_P (dest))
6122 {
6123 dest = rs6000_address_for_fpconvert (dest);
6124 emit_insn (gen_stfiwx (dest, tmp));
6125 DONE;
6126 }
6127 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6128 {
6129 dest = gen_lowpart (DImode, dest);
6130 emit_move_insn (dest, tmp);
6131 DONE;
6132 }
6133 else
6134 {
6135 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6136 emit_insn (gen_stfiwx (stack, tmp));
6137 emit_move_insn (dest, stack);
6138 DONE;
6139 }
6140 }
6141 [(set_attr "length" "12")
6142 (set_attr "type" "fp")])
6144 (define_expand "fixuns_trunc<mode>di2"
6145 [(set (match_operand:DI 0 "register_operand" "")
6146 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6147 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6148 "")
6150 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6151 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6152 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6153 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6154 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6155 "fctiduz %0,%1"
6156 [(set_attr "type" "fp")])
6158 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6159 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6160 ; because the first makes it clear that operand 0 is not live
6161 ; before the instruction.
6162 (define_insn "fctiwz_<mode>"
6163 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6164 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6165 UNSPEC_FCTIWZ))]
6166 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6167 "fctiwz %0,%1"
6168 [(set_attr "type" "fp")])
6170 (define_insn "fctiwuz_<mode>"
6171 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6172 (unspec:DI [(unsigned_fix:SI
6173 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6174 UNSPEC_FCTIWUZ))]
6175 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6176 "fctiwuz %0,%1"
6177 [(set_attr "type" "fp")])
6179 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6180 ;; since the friz instruction does not truncate the value if the floating
6181 ;; point value is < LONG_MIN or > LONG_MAX.
6182 (define_insn "*friz"
6183 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6184 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6185 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6186 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6187 && !flag_trapping_math && TARGET_FRIZ"
6188 "friz %0,%1"
6189 [(set_attr "type" "fp")])
6191 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6192 ;; load to properly sign extend the value, but at least doing a store, load
6193 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6194 ;; if we have 32-bit memory ops
6195 (define_insn_and_split "*round32<mode>2_fprs"
6196 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6197 (float:SFDF
6198 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6199 (clobber (match_scratch:DI 2 "=d"))
6200 (clobber (match_scratch:DI 3 "=d"))]
6201 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6202 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6203 && can_create_pseudo_p ()"
6204 "#"
6205 ""
6206 [(pc)]
6207 {
6208 rtx dest = operands[0];
6209 rtx src = operands[1];
6210 rtx tmp1 = operands[2];
6211 rtx tmp2 = operands[3];
6212 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6214 if (GET_CODE (tmp1) == SCRATCH)
6215 tmp1 = gen_reg_rtx (DImode);
6216 if (GET_CODE (tmp2) == SCRATCH)
6217 tmp2 = gen_reg_rtx (DImode);
6219 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6220 emit_insn (gen_stfiwx (stack, tmp1));
6221 emit_insn (gen_lfiwax (tmp2, stack));
6222 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6223 DONE;
6224 }
6225 [(set_attr "type" "fpload")
6226 (set_attr "length" "16")])
6228 (define_insn_and_split "*roundu32<mode>2_fprs"
6229 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6230 (unsigned_float:SFDF
6231 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6232 (clobber (match_scratch:DI 2 "=d"))
6233 (clobber (match_scratch:DI 3 "=d"))]
6234 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6235 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6236 && can_create_pseudo_p ()"
6237 "#"
6238 ""
6239 [(pc)]
6240 {
6241 rtx dest = operands[0];
6242 rtx src = operands[1];
6243 rtx tmp1 = operands[2];
6244 rtx tmp2 = operands[3];
6245 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6247 if (GET_CODE (tmp1) == SCRATCH)
6248 tmp1 = gen_reg_rtx (DImode);
6249 if (GET_CODE (tmp2) == SCRATCH)
6250 tmp2 = gen_reg_rtx (DImode);
6252 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6253 emit_insn (gen_stfiwx (stack, tmp1));
6254 emit_insn (gen_lfiwzx (tmp2, stack));
6255 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6256 DONE;
6257 }
6258 [(set_attr "type" "fpload")
6259 (set_attr "length" "16")])
6261 ;; No VSX equivalent to fctid
6262 (define_insn "lrint<mode>di2"
6263 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6264 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6265 UNSPEC_FCTID))]
6266 "TARGET_<MODE>_FPR && TARGET_FPRND"
6267 "fctid %0,%1"
6268 [(set_attr "type" "fp")])
6270 (define_insn "btrunc<mode>2"
6271 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6272 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6273 UNSPEC_FRIZ))]
6274 "TARGET_<MODE>_FPR && TARGET_FPRND"
6275 "@
6276 friz %0,%1
6277 xsrdpiz %x0,%x1"
6278 [(set_attr "type" "fp")
6279 (set_attr "fp_type" "fp_addsub_<Fs>")])
6281 (define_insn "ceil<mode>2"
6282 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6283 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6284 UNSPEC_FRIP))]
6285 "TARGET_<MODE>_FPR && TARGET_FPRND"
6286 "@
6287 frip %0,%1
6288 xsrdpip %x0,%x1"
6289 [(set_attr "type" "fp")
6290 (set_attr "fp_type" "fp_addsub_<Fs>")])
6292 (define_insn "floor<mode>2"
6293 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6294 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6295 UNSPEC_FRIM))]
6296 "TARGET_<MODE>_FPR && TARGET_FPRND"
6297 "@
6298 frim %0,%1
6299 xsrdpim %x0,%x1"
6300 [(set_attr "type" "fp")
6301 (set_attr "fp_type" "fp_addsub_<Fs>")])
6303 ;; No VSX equivalent to frin
6304 (define_insn "round<mode>2"
6305 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6306 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6307 UNSPEC_FRIN))]
6308 "TARGET_<MODE>_FPR && TARGET_FPRND"
6309 "frin %0,%1"
6310 [(set_attr "type" "fp")
6311 (set_attr "fp_type" "fp_addsub_<Fs>")])
6313 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6314 (define_insn "stfiwx"
6315 [(set (match_operand:SI 0 "memory_operand" "=Z")
6316 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6317 UNSPEC_STFIWX))]
6318 "TARGET_PPC_GFXOPT"
6319 "stfiwx %1,%y0"
6320 [(set_attr "type" "fpstore")])
6322 ;; If we don't have a direct conversion to single precision, don't enable this
6323 ;; conversion for 32-bit without fast math, because we don't have the insn to
6324 ;; generate the fixup swizzle to avoid double rounding problems.
6325 (define_expand "floatsisf2"
6326 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6327 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6328 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6329 && (!TARGET_FPRS
6330 || (TARGET_FPRS
6331 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6332 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6333 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6334 "
6335 {
6336 if (!TARGET_FPRS)
6337 {
6338 if (!REG_P (operands[1]))
6339 operands[1] = force_reg (SImode, operands[1]);
6340 }
6341 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6342 {
6343 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6344 DONE;
6345 }
6346 else if (TARGET_FCFID && TARGET_LFIWAX)
6347 {
6348 rtx dfreg = gen_reg_rtx (DFmode);
6349 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6350 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6351 DONE;
6352 }
6353 else
6354 {
6355 rtx dreg = operands[1];
6356 if (!REG_P (dreg))
6357 dreg = force_reg (SImode, dreg);
6358 dreg = convert_to_mode (DImode, dreg, false);
6359 emit_insn (gen_floatdisf2 (operands[0], dreg));
6360 DONE;
6361 }
6362 }")
6364 (define_expand "floatdidf2"
6365 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6366 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6367 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6368 "")
6370 (define_insn "*floatdidf2_fpr"
6371 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6372 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6373 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6374 && !VECTOR_UNIT_VSX_P (DFmode)"
6375 "fcfid %0,%1"
6376 [(set_attr "type" "fp")])
6378 ; Allow the combiner to merge source memory operands to the conversion so that
6379 ; the optimizer/register allocator doesn't try to load the value too early in a
6380 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6381 ; hit. We will split after reload to avoid the trip through the GPRs
6383 (define_insn_and_split "*floatdidf2_mem"
6384 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6385 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6386 (clobber (match_scratch:DI 2 "=d"))]
6387 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6388 "#"
6389 "&& reload_completed"
6390 [(set (match_dup 2) (match_dup 1))
6391 (set (match_dup 0) (float:DF (match_dup 2)))]
6392 ""
6393 [(set_attr "length" "8")
6394 (set_attr "type" "fpload")])
6396 (define_expand "floatunsdidf2"
6397 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6398 (unsigned_float:DF
6399 (match_operand:DI 1 "gpc_reg_operand" "")))]
6400 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6401 "")
6403 (define_insn "*floatunsdidf2_fcfidu"
6404 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6405 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6406 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6407 "fcfidu %0,%1"
6408 [(set_attr "type" "fp")
6409 (set_attr "length" "4")])
6411 (define_insn_and_split "*floatunsdidf2_mem"
6412 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6413 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6414 (clobber (match_scratch:DI 2 "=d"))]
6415 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6416 "#"
6417 "&& reload_completed"
6418 [(set (match_dup 2) (match_dup 1))
6419 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6420 ""
6421 [(set_attr "length" "8")
6422 (set_attr "type" "fpload")])
6424 (define_expand "floatdisf2"
6425 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6426 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6427 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6428 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6429 "
6430 {
6431 if (!TARGET_FCFIDS)
6432 {
6433 rtx val = operands[1];
6434 if (!flag_unsafe_math_optimizations)
6435 {
6436 rtx label = gen_label_rtx ();
6437 val = gen_reg_rtx (DImode);
6438 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6439 emit_label (label);
6440 }
6441 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6442 DONE;
6443 }
6444 }")
6446 (define_insn "floatdisf2_fcfids"
6447 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6448 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6449 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6450 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6451 "fcfids %0,%1"
6452 [(set_attr "type" "fp")])
6454 (define_insn_and_split "*floatdisf2_mem"
6455 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6456 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6457 (clobber (match_scratch:DI 2 "=f"))]
6458 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6459 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6460 "#"
6461 "&& reload_completed"
6462 [(pc)]
6463 "
6464 {
6465 emit_move_insn (operands[2], operands[1]);
6466 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6467 DONE;
6468 }"
6469 [(set_attr "length" "8")])
6471 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6472 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6473 ;; from double rounding.
6474 ;; Instead of creating a new cpu type for two FP operations, just use fp
6475 (define_insn_and_split "floatdisf2_internal1"
6476 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6477 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6478 (clobber (match_scratch:DF 2 "=d"))]
6479 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6480 "#"
6481 "&& reload_completed"
6482 [(set (match_dup 2)
6483 (float:DF (match_dup 1)))
6484 (set (match_dup 0)
6485 (float_truncate:SF (match_dup 2)))]
6486 ""
6487 [(set_attr "length" "8")
6488 (set_attr "type" "fp")])
6490 ;; Twiddles bits to avoid double rounding.
6491 ;; Bits that might be truncated when converting to DFmode are replaced
6492 ;; by a bit that won't be lost at that stage, but is below the SFmode
6493 ;; rounding position.
6494 (define_expand "floatdisf2_internal2"
6495 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6496 (const_int 53)))
6497 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6498 (const_int 2047)))
6499 (clobber (scratch:CC))])
6500 (set (match_dup 3) (plus:DI (match_dup 3)
6501 (const_int 1)))
6502 (set (match_dup 0) (plus:DI (match_dup 0)
6503 (const_int 2047)))
6504 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6505 (const_int 2)))
6506 (set (match_dup 0) (ior:DI (match_dup 0)
6507 (match_dup 1)))
6508 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6509 (const_int -2048)))
6510 (clobber (scratch:CC))])
6511 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6512 (label_ref (match_operand:DI 2 "" ""))
6513 (pc)))
6514 (set (match_dup 0) (match_dup 1))]
6515 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6516 "
6517 {
6518 operands[3] = gen_reg_rtx (DImode);
6519 operands[4] = gen_reg_rtx (CCUNSmode);
6520 }")
6522 (define_expand "floatunsdisf2"
6523 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6524 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6526 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6527 "")
6529 (define_insn "floatunsdisf2_fcfidus"
6530 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6531 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6532 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6533 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6534 "fcfidus %0,%1"
6535 [(set_attr "type" "fp")])
6537 (define_insn_and_split "*floatunsdisf2_mem"
6538 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6539 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6540 (clobber (match_scratch:DI 2 "=f"))]
6541 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6542 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6543 "#"
6544 "&& reload_completed"
6545 [(pc)]
6546 "
6547 {
6548 emit_move_insn (operands[2], operands[1]);
6549 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6550 DONE;
6551 }"
6552 [(set_attr "length" "8")
6553 (set_attr "type" "fpload")])
6554 \f
6555 ;; Define the TImode operations that can be done in a small number
6556 ;; of instructions. The & constraints are to prevent the register
6557 ;; allocator from allocating registers that overlap with the inputs
6558 ;; (for example, having an input in 7,8 and an output in 6,7). We
6559 ;; also allow for the output being the same as one of the inputs.
6561 (define_insn "addti3"
6562 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r")
6563 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0")
6564 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))]
6565 "TARGET_64BIT"
6566 {
6567 if (WORDS_BIG_ENDIAN)
6568 return (GET_CODE (operands[2])) != CONST_INT
6569 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6570 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6571 else
6572 return (GET_CODE (operands[2])) != CONST_INT
6573 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6574 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6575 }
6576 [(set_attr "type" "two")
6577 (set_attr "length" "8")])
6579 (define_insn "subti3"
6580 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6581 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I")
6582 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6583 "TARGET_64BIT"
6584 {
6585 if (WORDS_BIG_ENDIAN)
6586 return (GET_CODE (operands[1]) != CONST_INT)
6587 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6588 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6589 else
6590 return (GET_CODE (operands[1]) != CONST_INT)
6591 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6592 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6593 }
6594 [(set_attr "type" "two")
6595 (set_attr "length" "8")])
6598 ;; Define the DImode operations that can be done in a small number
6599 ;; of instructions. The & constraints are to prevent the register
6600 ;; allocator from allocating registers that overlap with the inputs
6601 ;; (for example, having an input in 7,8 and an output in 6,7). We
6602 ;; also allow for the output being the same as one of the inputs.
6604 (define_insn "*adddi3_noppc64"
6605 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6606 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6607 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6608 "! TARGET_POWERPC64"
6609 "*
6610 {
6611 if (WORDS_BIG_ENDIAN)
6612 return (GET_CODE (operands[2])) != CONST_INT
6613 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6614 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6615 else
6616 return (GET_CODE (operands[2])) != CONST_INT
6617 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6618 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6619 }"
6620 [(set_attr "type" "two")
6621 (set_attr "length" "8")])
6623 (define_insn "*subdi3_noppc64"
6624 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6625 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6626 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6627 "! TARGET_POWERPC64"
6628 "*
6629 {
6630 if (WORDS_BIG_ENDIAN)
6631 return (GET_CODE (operands[1]) != CONST_INT)
6632 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6633 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6634 else
6635 return (GET_CODE (operands[1]) != CONST_INT)
6636 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6637 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6638 }"
6639 [(set_attr "type" "two")
6640 (set_attr "length" "8")])
6642 (define_insn "*negdi2_noppc64"
6643 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6644 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6645 "! TARGET_POWERPC64"
6646 "*
6647 {
6648 return (WORDS_BIG_ENDIAN)
6649 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6650 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6651 }"
6652 [(set_attr "type" "two")
6653 (set_attr "length" "8")])
6655 (define_insn "mulsidi3"
6656 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6657 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6658 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6659 "! TARGET_POWERPC64"
6660 {
6661 return (WORDS_BIG_ENDIAN)
6662 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6663 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6664 }
6665 [(set_attr "type" "mul")
6666 (set_attr "length" "8")])
6668 (define_split
6669 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6670 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6671 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6672 "! TARGET_POWERPC64 && reload_completed"
6673 [(set (match_dup 3)
6674 (truncate:SI
6675 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6676 (sign_extend:DI (match_dup 2)))
6677 (const_int 32))))
6678 (set (match_dup 4)
6679 (mult:SI (match_dup 1)
6680 (match_dup 2)))]
6681 "
6682 {
6683 int endian = (WORDS_BIG_ENDIAN == 0);
6684 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6685 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6686 }")
6688 (define_insn "umulsidi3"
6689 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6690 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6691 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6692 "! TARGET_POWERPC64"
6693 "*
6694 {
6695 return (WORDS_BIG_ENDIAN)
6696 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6697 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6698 }"
6699 [(set_attr "type" "mul")
6700 (set_attr "length" "8")])
6702 (define_split
6703 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6704 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6705 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6706 "! TARGET_POWERPC64 && reload_completed"
6707 [(set (match_dup 3)
6708 (truncate:SI
6709 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6710 (zero_extend:DI (match_dup 2)))
6711 (const_int 32))))
6712 (set (match_dup 4)
6713 (mult:SI (match_dup 1)
6714 (match_dup 2)))]
6715 "
6716 {
6717 int endian = (WORDS_BIG_ENDIAN == 0);
6718 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6719 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6720 }")
6722 (define_insn "smulsi3_highpart"
6723 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6724 (truncate:SI
6725 (lshiftrt:DI (mult:DI (sign_extend:DI
6726 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6727 (sign_extend:DI
6728 (match_operand:SI 2 "gpc_reg_operand" "r")))
6729 (const_int 32))))]
6730 ""
6731 "mulhw %0,%1,%2"
6732 [(set_attr "type" "mul")])
6734 (define_insn "umulsi3_highpart"
6735 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6736 (truncate:SI
6737 (lshiftrt:DI (mult:DI (zero_extend:DI
6738 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6739 (zero_extend:DI
6740 (match_operand:SI 2 "gpc_reg_operand" "r")))
6741 (const_int 32))))]
6742 ""
6743 "mulhwu %0,%1,%2"
6744 [(set_attr "type" "mul")])
6746 ;; Shift by a variable amount is too complex to be worth open-coding. We
6747 ;; just handle shifts by constants.
6748 (define_insn "ashrdi3_no_power"
6749 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6750 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6751 (match_operand:SI 2 "const_int_operand" "M,i")))]
6752 "!TARGET_POWERPC64"
6753 "*
6754 {
6755 switch (which_alternative)
6756 {
6757 default:
6758 gcc_unreachable ();
6759 case 0:
6760 if (WORDS_BIG_ENDIAN)
6761 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6762 else
6763 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6764 case 1:
6765 if (WORDS_BIG_ENDIAN)
6766 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6767 else
6768 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6769 }
6770 }"
6771 [(set_attr "type" "two,three")
6772 (set_attr "length" "8,12")])
6774 (define_insn "*ashrdisi3_noppc64be"
6775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6776 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6777 (const_int 32)) 4))]
6778 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6779 "*
6780 {
6781 if (REGNO (operands[0]) == REGNO (operands[1]))
6782 return \"\";
6783 else
6784 return \"mr %0,%1\";
6785 }"
6786 [(set_attr "length" "4")])
6788 \f
6789 ;; PowerPC64 DImode operations.
6791 (define_insn "muldi3"
6792 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6793 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6794 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6795 "TARGET_POWERPC64"
6796 "@
6797 mulld %0,%1,%2
6798 mulli %0,%1,%2"
6799 [(set_attr "type" "mul")
6800 (set (attr "size")
6801 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6802 (const_string "8")
6803 (match_operand:SI 2 "short_cint_operand" "")
6804 (const_string "16")]
6805 (const_string "64")))])
6807 (define_insn "*muldi3_internal1"
6808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6809 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6810 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6811 (const_int 0)))
6812 (clobber (match_scratch:DI 3 "=r,r"))]
6813 "TARGET_POWERPC64"
6814 "@
6815 mulld. %3,%1,%2
6816 #"
6817 [(set_attr "type" "mul")
6818 (set_attr "size" "64")
6819 (set_attr "dot" "yes")
6820 (set_attr "length" "4,8")])
6822 (define_split
6823 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6824 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6825 (match_operand:DI 2 "gpc_reg_operand" ""))
6826 (const_int 0)))
6827 (clobber (match_scratch:DI 3 ""))]
6828 "TARGET_POWERPC64 && reload_completed"
6829 [(set (match_dup 3)
6830 (mult:DI (match_dup 1) (match_dup 2)))
6831 (set (match_dup 0)
6832 (compare:CC (match_dup 3)
6833 (const_int 0)))]
6834 "")
6836 (define_insn "*muldi3_internal2"
6837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6838 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6839 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6840 (const_int 0)))
6841 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6842 (mult:DI (match_dup 1) (match_dup 2)))]
6843 "TARGET_POWERPC64"
6844 "@
6845 mulld. %0,%1,%2
6846 #"
6847 [(set_attr "type" "mul")
6848 (set_attr "size" "64")
6849 (set_attr "dot" "yes")
6850 (set_attr "length" "4,8")])
6852 (define_split
6853 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6854 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6855 (match_operand:DI 2 "gpc_reg_operand" ""))
6856 (const_int 0)))
6857 (set (match_operand:DI 0 "gpc_reg_operand" "")
6858 (mult:DI (match_dup 1) (match_dup 2)))]
6859 "TARGET_POWERPC64 && reload_completed"
6860 [(set (match_dup 0)
6861 (mult:DI (match_dup 1) (match_dup 2)))
6862 (set (match_dup 3)
6863 (compare:CC (match_dup 0)
6864 (const_int 0)))]
6865 "")
6867 (define_insn "smuldi3_highpart"
6868 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6869 (truncate:DI
6870 (lshiftrt:TI (mult:TI (sign_extend:TI
6871 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6872 (sign_extend:TI
6873 (match_operand:DI 2 "gpc_reg_operand" "r")))
6874 (const_int 64))))]
6875 "TARGET_POWERPC64"
6876 "mulhd %0,%1,%2"
6877 [(set_attr "type" "mul")
6878 (set_attr "size" "64")])
6880 (define_insn "umuldi3_highpart"
6881 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6882 (truncate:DI
6883 (lshiftrt:TI (mult:TI (zero_extend:TI
6884 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6885 (zero_extend:TI
6886 (match_operand:DI 2 "gpc_reg_operand" "r")))
6887 (const_int 64))))]
6888 "TARGET_POWERPC64"
6889 "mulhdu %0,%1,%2"
6890 [(set_attr "type" "mul")
6891 (set_attr "size" "64")])
6893 (define_expand "mulditi3"
6894 [(set (match_operand:TI 0 "gpc_reg_operand")
6895 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6896 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6897 "TARGET_POWERPC64"
6898 {
6899 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6900 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6901 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6902 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6903 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6904 DONE;
6905 })
6907 (define_expand "umulditi3"
6908 [(set (match_operand:TI 0 "gpc_reg_operand")
6909 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6910 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6911 "TARGET_POWERPC64"
6912 {
6913 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6914 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6915 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6916 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6917 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6918 DONE;
6919 })
6921 (define_insn "*rotldi3_internal4"
6922 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6923 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6924 (match_operand:DI 2 "reg_or_cint_operand" "rn"))
6925 (match_operand:DI 3 "mask64_operand" "n")))]
6926 "TARGET_POWERPC64"
6927 "rld%I2c%B3 %0,%1,%H2,%S3"
6928 [(set_attr "type" "shift")
6929 (set_attr "maybe_var_shift" "yes")])
6931 (define_insn "*rotldi3_internal5"
6932 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6933 (compare:CC (and:DI
6934 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6935 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6936 (match_operand:DI 3 "mask64_operand" "n,n"))
6937 (const_int 0)))
6938 (clobber (match_scratch:DI 4 "=r,r"))]
6939 "TARGET_64BIT"
6940 "@
6941 rld%I2c%B3. %4,%1,%H2,%S3
6942 #"
6943 [(set_attr "type" "shift")
6944 (set_attr "maybe_var_shift" "yes")
6945 (set_attr "dot" "yes")
6946 (set_attr "length" "4,8")])
6948 (define_split
6949 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6950 (compare:CC (and:DI
6951 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6952 (match_operand:DI 2 "reg_or_cint_operand" ""))
6953 (match_operand:DI 3 "mask64_operand" ""))
6954 (const_int 0)))
6955 (clobber (match_scratch:DI 4 ""))]
6956 "TARGET_POWERPC64 && reload_completed"
6957 [(set (match_dup 4)
6958 (and:DI (rotate:DI (match_dup 1)
6959 (match_dup 2))
6960 (match_dup 3)))
6961 (set (match_dup 0)
6962 (compare:CC (match_dup 4)
6963 (const_int 0)))]
6964 "")
6966 (define_insn "*rotldi3_internal6"
6967 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6968 (compare:CC (and:DI
6969 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6970 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn"))
6971 (match_operand:DI 3 "mask64_operand" "n,n"))
6972 (const_int 0)))
6973 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6974 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6975 "TARGET_64BIT"
6976 "@
6977 rld%I2c%B3. %0,%1,%H2,%S3
6978 #"
6979 [(set_attr "type" "shift")
6980 (set_attr "maybe_var_shift" "yes")
6981 (set_attr "dot" "yes")
6982 (set_attr "length" "4,8")])
6984 (define_split
6985 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6986 (compare:CC (and:DI
6987 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6988 (match_operand:DI 2 "reg_or_cint_operand" ""))
6989 (match_operand:DI 3 "mask64_operand" ""))
6990 (const_int 0)))
6991 (set (match_operand:DI 0 "gpc_reg_operand" "")
6992 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6993 "TARGET_POWERPC64 && reload_completed"
6994 [(set (match_dup 0)
6995 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6996 (set (match_dup 4)
6997 (compare:CC (match_dup 0)
6998 (const_int 0)))]
6999 "")
7001 (define_insn "*rotldi3_internal7le"
7002 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7003 (zero_extend:DI
7004 (subreg:QI
7005 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7006 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7007 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7008 "rld%I2cl %0,%1,%H2,56"
7009 [(set_attr "type" "shift")
7010 (set_attr "maybe_var_shift" "yes")])
7012 (define_insn "*rotldi3_internal7be"
7013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7014 (zero_extend:DI
7015 (subreg:QI
7016 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7017 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
7018 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7019 "rld%I2cl %0,%1,%H2,56"
7020 [(set_attr "type" "shift")
7021 (set_attr "maybe_var_shift" "yes")])
7023 (define_insn "*rotldi3_internal8le"
7024 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7025 (compare:CC (zero_extend:DI
7026 (subreg:QI
7027 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7028 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7029 (const_int 0)))
7030 (clobber (match_scratch:DI 3 "=r,r"))]
7031 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7032 "@
7033 rld%I2cl. %3,%1,%H2,56
7034 #"
7035 [(set_attr "type" "shift")
7036 (set_attr "maybe_var_shift" "yes")
7037 (set_attr "dot" "yes")
7038 (set_attr "length" "4,8")])
7040 (define_insn "*rotldi3_internal8be"
7041 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7042 (compare:CC (zero_extend:DI
7043 (subreg:QI
7044 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7045 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
7046 (const_int 0)))
7047 (clobber (match_scratch:DI 3 "=r,r"))]
7048 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7049 "@
7050 rld%I2cl. %3,%1,%H2,56
7051 #"
7052 [(set_attr "type" "shift")
7053 (set_attr "maybe_var_shift" "yes")
7054 (set_attr "dot" "yes")
7055 (set_attr "length" "4,8")])
7057 (define_split
7058 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7059 (compare:CC (zero_extend:DI
7060 (subreg:QI
7061 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7062 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7063 (const_int 0)))
7064 (clobber (match_scratch:DI 3 ""))]
7065 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7066 [(set (match_dup 3)
7067 (zero_extend:DI (subreg:QI
7068 (rotate:DI (match_dup 1)
7069 (match_dup 2)) 0)))
7070 (set (match_dup 0)
7071 (compare:CC (match_dup 3)
7072 (const_int 0)))]
7073 "")
7075 (define_split
7076 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7077 (compare:CC (zero_extend:DI
7078 (subreg:QI
7079 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7080 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7081 (const_int 0)))
7082 (clobber (match_scratch:DI 3 ""))]
7083 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7084 [(set (match_dup 3)
7085 (zero_extend:DI (subreg:QI
7086 (rotate:DI (match_dup 1)
7087 (match_dup 2)) 7)))
7088 (set (match_dup 0)
7089 (compare:CC (match_dup 3)
7090 (const_int 0)))]
7091 "")
7093 (define_insn "*rotldi3_internal9le"
7094 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7095 (compare:CC (zero_extend:DI
7096 (subreg:QI
7097 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7098 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7099 (const_int 0)))
7100 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7101 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7102 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7103 "@
7104 rld%I2cl. %0,%1,%H2,56
7105 #"
7106 [(set_attr "type" "shift")
7107 (set_attr "maybe_var_shift" "yes")
7108 (set_attr "dot" "yes")
7109 (set_attr "length" "4,8")])
7111 (define_insn "*rotldi3_internal9be"
7112 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7113 (compare:CC (zero_extend:DI
7114 (subreg:QI
7115 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7116 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 7))
7117 (const_int 0)))
7118 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7119 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7120 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7121 "@
7122 rld%I2cl. %0,%1,%H2,56
7123 #"
7124 [(set_attr "type" "shift")
7125 (set_attr "maybe_var_shift" "yes")
7126 (set_attr "dot" "yes")
7127 (set_attr "length" "4,8")])
7129 (define_split
7130 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7131 (compare:CC (zero_extend:DI
7132 (subreg:QI
7133 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7134 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7135 (const_int 0)))
7136 (set (match_operand:DI 0 "gpc_reg_operand" "")
7137 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7138 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7139 [(set (match_dup 0)
7140 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7141 (set (match_dup 3)
7142 (compare:CC (match_dup 0)
7143 (const_int 0)))]
7144 "")
7146 (define_split
7147 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7148 (compare:CC (zero_extend:DI
7149 (subreg:QI
7150 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7151 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7152 (const_int 0)))
7153 (set (match_operand:DI 0 "gpc_reg_operand" "")
7154 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7155 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7156 [(set (match_dup 0)
7157 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7158 (set (match_dup 3)
7159 (compare:CC (match_dup 0)
7160 (const_int 0)))]
7161 "")
7163 (define_insn "*rotldi3_internal10le"
7164 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7165 (zero_extend:DI
7166 (subreg:HI
7167 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7168 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7169 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7170 "rld%I2cl %0,%1,%H2,48"
7171 [(set_attr "type" "shift")
7172 (set_attr "maybe_var_shift" "yes")])
7174 (define_insn "*rotldi3_internal10be"
7175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7176 (zero_extend:DI
7177 (subreg:HI
7178 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7179 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
7180 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7181 "rld%I2cl %0,%1,%H2,48"
7182 [(set_attr "type" "shift")
7183 (set_attr "maybe_var_shift" "yes")])
7185 (define_insn "*rotldi3_internal11le"
7186 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7187 (compare:CC (zero_extend:DI
7188 (subreg:HI
7189 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7190 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7191 (const_int 0)))
7192 (clobber (match_scratch:DI 3 "=r,r"))]
7193 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7194 "@
7195 rld%I2cl. %3,%1,%H2,48
7196 #"
7197 [(set_attr "type" "shift")
7198 (set_attr "maybe_var_shift" "yes")
7199 (set_attr "dot" "yes")
7200 (set_attr "length" "4,8")])
7202 (define_insn "*rotldi3_internal11be"
7203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7204 (compare:CC (zero_extend:DI
7205 (subreg:HI
7206 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7207 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
7208 (const_int 0)))
7209 (clobber (match_scratch:DI 3 "=r,r"))]
7210 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7211 "@
7212 rld%I2cl. %3,%1,%H2,48
7213 #"
7214 [(set_attr "type" "shift")
7215 (set_attr "maybe_var_shift" "yes")
7216 (set_attr "dot" "yes")
7217 (set_attr "length" "4,8")])
7219 (define_split
7220 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7221 (compare:CC (zero_extend:DI
7222 (subreg:HI
7223 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7224 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7225 (const_int 0)))
7226 (clobber (match_scratch:DI 3 ""))]
7227 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7228 [(set (match_dup 3)
7229 (zero_extend:DI (subreg:HI
7230 (rotate:DI (match_dup 1)
7231 (match_dup 2)) 0)))
7232 (set (match_dup 0)
7233 (compare:CC (match_dup 3)
7234 (const_int 0)))]
7235 "")
7237 (define_split
7238 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7239 (compare:CC (zero_extend:DI
7240 (subreg:HI
7241 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7243 (const_int 0)))
7244 (clobber (match_scratch:DI 3 ""))]
7245 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7246 [(set (match_dup 3)
7247 (zero_extend:DI (subreg:HI
7248 (rotate:DI (match_dup 1)
7249 (match_dup 2)) 6)))
7250 (set (match_dup 0)
7251 (compare:CC (match_dup 3)
7252 (const_int 0)))]
7253 "")
7255 (define_insn "*rotldi3_internal12le"
7256 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7257 (compare:CC (zero_extend:DI
7258 (subreg:HI
7259 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7260 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7261 (const_int 0)))
7262 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7263 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7264 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7265 "@
7266 rld%I2cl. %0,%1,%H2,48
7267 #"
7268 [(set_attr "type" "shift")
7269 (set_attr "maybe_var_shift" "yes")
7270 (set_attr "dot" "yes")
7271 (set_attr "length" "4,8")])
7273 (define_insn "*rotldi3_internal12be"
7274 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7275 (compare:CC (zero_extend:DI
7276 (subreg:HI
7277 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7278 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 6))
7279 (const_int 0)))
7280 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7281 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7282 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7283 "@
7284 rld%I2cl. %0,%1,%H2,48
7285 #"
7286 [(set_attr "type" "shift")
7287 (set_attr "maybe_var_shift" "yes")
7288 (set_attr "dot" "yes")
7289 (set_attr "length" "4,8")])
7291 (define_split
7292 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7293 (compare:CC (zero_extend:DI
7294 (subreg:HI
7295 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7296 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7297 (const_int 0)))
7298 (set (match_operand:DI 0 "gpc_reg_operand" "")
7299 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7300 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7301 [(set (match_dup 0)
7302 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7303 (set (match_dup 3)
7304 (compare:CC (match_dup 0)
7305 (const_int 0)))]
7306 "")
7308 (define_split
7309 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7310 (compare:CC (zero_extend:DI
7311 (subreg:HI
7312 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7313 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7314 (const_int 0)))
7315 (set (match_operand:DI 0 "gpc_reg_operand" "")
7316 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7317 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7318 [(set (match_dup 0)
7319 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7320 (set (match_dup 3)
7321 (compare:CC (match_dup 0)
7322 (const_int 0)))]
7323 "")
7325 (define_insn "*rotldi3_internal13le"
7326 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7327 (zero_extend:DI
7328 (subreg:SI
7329 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7330 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
7331 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7332 "rld%I2cl %0,%1,%H2,32"
7333 [(set_attr "type" "shift")
7334 (set_attr "maybe_var_shift" "yes")])
7336 (define_insn "*rotldi3_internal13be"
7337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7338 (zero_extend:DI
7339 (subreg:SI
7340 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7341 (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
7342 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7343 "rld%I2cl %0,%1,%H2,32"
7344 [(set_attr "type" "shift")
7345 (set_attr "maybe_var_shift" "yes")])
7347 (define_insn "*rotldi3_internal14le"
7348 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7349 (compare:CC (zero_extend:DI
7350 (subreg:SI
7351 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7352 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7353 (const_int 0)))
7354 (clobber (match_scratch:DI 3 "=r,r"))]
7355 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7356 "@
7357 rld%I2cl. %3,%1,%H2,32
7358 #"
7359 [(set_attr "type" "shift")
7360 (set_attr "maybe_var_shift" "yes")
7361 (set_attr "dot" "yes")
7362 (set_attr "length" "4,8")])
7364 (define_insn "*rotldi3_internal14be"
7365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7366 (compare:CC (zero_extend:DI
7367 (subreg:SI
7368 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7369 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
7370 (const_int 0)))
7371 (clobber (match_scratch:DI 3 "=r,r"))]
7372 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7373 "@
7374 rld%I2cl. %3,%1,%H2,32
7375 #"
7376 [(set_attr "type" "shift")
7377 (set_attr "maybe_var_shift" "yes")
7378 (set_attr "dot" "yes")
7379 (set_attr "length" "4,8")])
7381 (define_split
7382 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7383 (compare:CC (zero_extend:DI
7384 (subreg:SI
7385 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7386 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7387 (const_int 0)))
7388 (clobber (match_scratch:DI 3 ""))]
7389 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7390 [(set (match_dup 3)
7391 (zero_extend:DI (subreg:SI
7392 (rotate:DI (match_dup 1)
7393 (match_dup 2)) 0)))
7394 (set (match_dup 0)
7395 (compare:CC (match_dup 3)
7396 (const_int 0)))]
7397 "")
7399 (define_split
7400 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7401 (compare:CC (zero_extend:DI
7402 (subreg:SI
7403 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7404 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7405 (const_int 0)))
7406 (clobber (match_scratch:DI 3 ""))]
7407 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7408 [(set (match_dup 3)
7409 (zero_extend:DI (subreg:SI
7410 (rotate:DI (match_dup 1)
7411 (match_dup 2)) 4)))
7412 (set (match_dup 0)
7413 (compare:CC (match_dup 3)
7414 (const_int 0)))]
7415 "")
7417 (define_insn "*rotldi3_internal15le"
7418 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7419 (compare:CC (zero_extend:DI
7420 (subreg:SI
7421 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7422 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 0))
7423 (const_int 0)))
7424 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7425 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7426 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7427 "@
7428 rld%I2cl. %0,%1,%H2,32
7429 #"
7430 [(set_attr "type" "shift")
7431 (set_attr "maybe_var_shift" "yes")
7432 (set_attr "dot" "yes")
7433 (set_attr "length" "4,8")])
7435 (define_insn "*rotldi3_internal15be"
7436 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7437 (compare:CC (zero_extend:DI
7438 (subreg:SI
7439 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7440 (match_operand:DI 2 "reg_or_cint_operand" "rn,rn")) 4))
7441 (const_int 0)))
7442 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7443 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7444 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7445 "@
7446 rld%I2cl. %0,%1,%H2,32
7447 #"
7448 [(set_attr "type" "shift")
7449 (set_attr "maybe_var_shift" "yes")
7450 (set_attr "dot" "yes")
7451 (set_attr "length" "4,8")])
7453 (define_split
7454 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7455 (compare:CC (zero_extend:DI
7456 (subreg:SI
7457 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7458 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7459 (const_int 0)))
7460 (set (match_operand:DI 0 "gpc_reg_operand" "")
7461 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7462 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7463 [(set (match_dup 0)
7464 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7465 (set (match_dup 3)
7466 (compare:CC (match_dup 0)
7467 (const_int 0)))]
7468 "")
7470 (define_split
7471 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7472 (compare:CC (zero_extend:DI
7473 (subreg:SI
7474 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7475 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7476 (const_int 0)))
7477 (set (match_operand:DI 0 "gpc_reg_operand" "")
7478 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7479 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7480 [(set (match_dup 0)
7481 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7482 (set (match_dup 3)
7483 (compare:CC (match_dup 0)
7484 (const_int 0)))]
7485 "")
7487 (define_insn "*ashldi3_internal4"
7488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7489 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7490 (match_operand:SI 2 "const_int_operand" "i"))
7491 (match_operand:DI 3 "const_int_operand" "n")))]
7492 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7493 "rldic %0,%1,%H2,%W3"
7494 [(set_attr "type" "shift")])
7496 (define_insn "ashldi3_internal5"
7497 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7498 (compare:CC
7499 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7500 (match_operand:SI 2 "const_int_operand" "i,i"))
7501 (match_operand:DI 3 "const_int_operand" "n,n"))
7502 (const_int 0)))
7503 (clobber (match_scratch:DI 4 "=r,r"))]
7504 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7505 "@
7506 rldic. %4,%1,%H2,%W3
7507 #"
7508 [(set_attr "type" "shift")
7509 (set_attr "dot" "yes")
7510 (set_attr "length" "4,8")])
7512 (define_split
7513 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7514 (compare:CC
7515 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7516 (match_operand:SI 2 "const_int_operand" ""))
7517 (match_operand:DI 3 "const_int_operand" ""))
7518 (const_int 0)))
7519 (clobber (match_scratch:DI 4 ""))]
7520 "TARGET_POWERPC64 && reload_completed
7521 && includes_rldic_lshift_p (operands[2], operands[3])"
7522 [(set (match_dup 4)
7523 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7524 (match_dup 3)))
7525 (set (match_dup 0)
7526 (compare:CC (match_dup 4)
7527 (const_int 0)))]
7528 "")
7530 (define_insn "*ashldi3_internal6"
7531 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7532 (compare:CC
7533 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7534 (match_operand:SI 2 "const_int_operand" "i,i"))
7535 (match_operand:DI 3 "const_int_operand" "n,n"))
7536 (const_int 0)))
7537 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7538 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7539 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7540 "@
7541 rldic. %0,%1,%H2,%W3
7542 #"
7543 [(set_attr "type" "shift")
7544 (set_attr "dot" "yes")
7545 (set_attr "length" "4,8")])
7547 (define_split
7548 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7549 (compare:CC
7550 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7551 (match_operand:SI 2 "const_int_operand" ""))
7552 (match_operand:DI 3 "const_int_operand" ""))
7553 (const_int 0)))
7554 (set (match_operand:DI 0 "gpc_reg_operand" "")
7555 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7556 "TARGET_POWERPC64 && reload_completed
7557 && includes_rldic_lshift_p (operands[2], operands[3])"
7558 [(set (match_dup 0)
7559 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7560 (match_dup 3)))
7561 (set (match_dup 4)
7562 (compare:CC (match_dup 0)
7563 (const_int 0)))]
7564 "")
7566 (define_insn "*ashldi3_internal7"
7567 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7568 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7569 (match_operand:SI 2 "const_int_operand" "i"))
7570 (match_operand:DI 3 "mask64_operand" "n")))]
7571 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7572 "rldicr %0,%1,%H2,%S3"
7573 [(set_attr "type" "shift")])
7575 (define_insn "ashldi3_internal8"
7576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7577 (compare:CC
7578 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7579 (match_operand:SI 2 "const_int_operand" "i,i"))
7580 (match_operand:DI 3 "mask64_operand" "n,n"))
7581 (const_int 0)))
7582 (clobber (match_scratch:DI 4 "=r,r"))]
7583 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7584 "@
7585 rldicr. %4,%1,%H2,%S3
7586 #"
7587 [(set_attr "type" "shift")
7588 (set_attr "dot" "yes")
7589 (set_attr "length" "4,8")])
7591 (define_split
7592 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7593 (compare:CC
7594 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7595 (match_operand:SI 2 "const_int_operand" ""))
7596 (match_operand:DI 3 "mask64_operand" ""))
7597 (const_int 0)))
7598 (clobber (match_scratch:DI 4 ""))]
7599 "TARGET_POWERPC64 && reload_completed
7600 && includes_rldicr_lshift_p (operands[2], operands[3])"
7601 [(set (match_dup 4)
7602 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7603 (match_dup 3)))
7604 (set (match_dup 0)
7605 (compare:CC (match_dup 4)
7606 (const_int 0)))]
7607 "")
7609 (define_insn "*ashldi3_internal9"
7610 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7611 (compare:CC
7612 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7613 (match_operand:SI 2 "const_int_operand" "i,i"))
7614 (match_operand:DI 3 "mask64_operand" "n,n"))
7615 (const_int 0)))
7616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7617 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7618 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7619 "@
7620 rldicr. %0,%1,%H2,%S3
7621 #"
7622 [(set_attr "type" "shift")
7623 (set_attr "dot" "yes")
7624 (set_attr "length" "4,8")])
7626 (define_split
7627 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7628 (compare:CC
7629 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7630 (match_operand:SI 2 "const_int_operand" ""))
7631 (match_operand:DI 3 "mask64_operand" ""))
7632 (const_int 0)))
7633 (set (match_operand:DI 0 "gpc_reg_operand" "")
7634 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7635 "TARGET_POWERPC64 && reload_completed
7636 && includes_rldicr_lshift_p (operands[2], operands[3])"
7637 [(set (match_dup 0)
7638 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7639 (match_dup 3)))
7640 (set (match_dup 4)
7641 (compare:CC (match_dup 0)
7642 (const_int 0)))]
7643 "")
7645 (define_expand "anddi3"
7646 [(parallel
7647 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7648 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7649 (match_operand:DI 2 "reg_or_cint_operand" "")))
7650 (clobber (match_scratch:CC 3 ""))])]
7651 ""
7652 {
7653 if (!TARGET_POWERPC64)
7654 {
7655 rtx cc = gen_rtx_SCRATCH (CCmode);
7656 rs6000_split_logical (operands, AND, false, false, false, cc);
7657 DONE;
7658 }
7659 else if (!and64_2_operand (operands[2], DImode))
7660 operands[2] = force_reg (DImode, operands[2]);
7661 })
7663 (define_insn "anddi3_mc"
7664 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7665 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7666 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7667 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7668 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7669 "@
7670 and %0,%1,%2
7671 rldic%B2 %0,%1,0,%S2
7672 rlwinm %0,%1,0,%m2,%M2
7673 andi. %0,%1,%b2
7674 andis. %0,%1,%u2
7675 #"
7676 [(set_attr "type" "*,shift,shift,logical,logical,*")
7677 (set_attr "dot" "no,no,no,yes,yes,no")
7678 (set_attr "length" "4,4,4,4,4,8")])
7680 (define_insn "anddi3_nomc"
7681 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7682 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7683 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7684 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7685 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7686 "@
7687 and %0,%1,%2
7688 rldic%B2 %0,%1,0,%S2
7689 rlwinm %0,%1,0,%m2,%M2
7690 #"
7691 [(set_attr "type" "*,shift,shift,*")
7692 (set_attr "length" "4,4,4,8")])
7694 (define_split
7695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7696 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7697 (match_operand:DI 2 "mask64_2_operand" "")))
7698 (clobber (match_scratch:CC 3 ""))]
7699 "TARGET_POWERPC64
7700 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7701 && !mask_operand (operands[2], DImode)
7702 && !mask64_operand (operands[2], DImode)"
7703 [(set (match_dup 0)
7704 (and:DI (rotate:DI (match_dup 1)
7705 (match_dup 4))
7706 (match_dup 5)))
7707 (set (match_dup 0)
7708 (and:DI (rotate:DI (match_dup 0)
7709 (match_dup 6))
7710 (match_dup 7)))]
7711 {
7712 build_mask64_2_operands (operands[2], &operands[4]);
7713 })
7715 (define_insn "*anddi3_internal2_mc"
7716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7717 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7718 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7719 (const_int 0)))
7720 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7721 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7722 "TARGET_64BIT && rs6000_gen_cell_microcode"
7723 "@
7724 and. %3,%1,%2
7725 rldic%B2. %3,%1,0,%S2
7726 rlwinm. %3,%1,0,%m2,%M2
7727 andi. %3,%1,%b2
7728 andis. %3,%1,%u2
7729 #
7730 #
7731 #
7732 #
7733 #
7734 #
7735 #"
7736 [(set_attr "type" "logical,shift,shift,logical,\
7737 logical,compare,compare,compare,compare,compare,\
7738 compare,compare")
7739 (set_attr "dot" "yes")
7740 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7742 (define_split
7743 [(set (match_operand:CC 0 "cc_reg_operand" "")
7744 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7745 (match_operand:DI 2 "mask64_2_operand" ""))
7746 (const_int 0)))
7747 (clobber (match_scratch:DI 3 ""))
7748 (clobber (match_scratch:CC 4 ""))]
7749 "TARGET_64BIT && reload_completed
7750 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7751 && !mask_operand (operands[2], DImode)
7752 && !mask64_operand (operands[2], DImode)"
7753 [(set (match_dup 3)
7754 (and:DI (rotate:DI (match_dup 1)
7755 (match_dup 5))
7756 (match_dup 6)))
7757 (parallel [(set (match_dup 0)
7758 (compare:CC (and:DI (rotate:DI (match_dup 3)
7759 (match_dup 7))
7760 (match_dup 8))
7761 (const_int 0)))
7762 (clobber (match_dup 3))])]
7763 "
7764 {
7765 build_mask64_2_operands (operands[2], &operands[5]);
7766 }")
7768 (define_insn "*anddi3_internal3_mc"
7769 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7770 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7771 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7772 (const_int 0)))
7773 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7774 (and:DI (match_dup 1) (match_dup 2)))
7775 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7776 "TARGET_64BIT && rs6000_gen_cell_microcode"
7777 "@
7778 and. %0,%1,%2
7779 rldic%B2. %0,%1,0,%S2
7780 rlwinm. %0,%1,0,%m2,%M2
7781 andi. %0,%1,%b2
7782 andis. %0,%1,%u2
7783 #
7784 #
7785 #
7786 #
7787 #
7788 #
7789 #"
7790 [(set_attr "type" "logical,shift,shift,logical,\
7791 logical,compare,compare,compare,compare,compare,\
7792 compare,compare")
7793 (set_attr "dot" "yes")
7794 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7796 (define_split
7797 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7798 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7799 (match_operand:DI 2 "and64_2_operand" ""))
7800 (const_int 0)))
7801 (set (match_operand:DI 0 "gpc_reg_operand" "")
7802 (and:DI (match_dup 1) (match_dup 2)))
7803 (clobber (match_scratch:CC 4 ""))]
7804 "TARGET_64BIT && reload_completed"
7805 [(parallel [(set (match_dup 0)
7806 (and:DI (match_dup 1) (match_dup 2)))
7807 (clobber (match_dup 4))])
7808 (set (match_dup 3)
7809 (compare:CC (match_dup 0)
7810 (const_int 0)))]
7811 "")
7813 (define_split
7814 [(set (match_operand:CC 3 "cc_reg_operand" "")
7815 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7816 (match_operand:DI 2 "mask64_2_operand" ""))
7817 (const_int 0)))
7818 (set (match_operand:DI 0 "gpc_reg_operand" "")
7819 (and:DI (match_dup 1) (match_dup 2)))
7820 (clobber (match_scratch:CC 4 ""))]
7821 "TARGET_64BIT && reload_completed
7822 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7823 && !mask_operand (operands[2], DImode)
7824 && !mask64_operand (operands[2], DImode)"
7825 [(set (match_dup 0)
7826 (and:DI (rotate:DI (match_dup 1)
7827 (match_dup 5))
7828 (match_dup 6)))
7829 (parallel [(set (match_dup 3)
7830 (compare:CC (and:DI (rotate:DI (match_dup 0)
7831 (match_dup 7))
7832 (match_dup 8))
7833 (const_int 0)))
7834 (set (match_dup 0)
7835 (and:DI (rotate:DI (match_dup 0)
7836 (match_dup 7))
7837 (match_dup 8)))])]
7838 "
7839 {
7840 build_mask64_2_operands (operands[2], &operands[5]);
7841 }")
7843 (define_insn "*boolcdi3_internal1"
7844 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7845 (match_operator:DI 3 "boolean_operator"
7846 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7847 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7848 "TARGET_POWERPC64"
7849 "%q3 %0,%2,%1")
7851 (define_insn "*boolcdi3_internal2"
7852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7853 (compare:CC (match_operator:DI 4 "boolean_operator"
7854 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7855 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7856 (const_int 0)))
7857 (clobber (match_scratch:DI 3 "=r,r"))]
7858 "TARGET_64BIT"
7859 "@
7860 %q4. %3,%2,%1
7861 #"
7862 [(set_attr "type" "logical,compare")
7863 (set_attr "dot" "yes")
7864 (set_attr "length" "4,8")])
7866 (define_split
7867 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7868 (compare:CC (match_operator:DI 4 "boolean_operator"
7869 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7870 (match_operand:DI 2 "gpc_reg_operand" "")])
7871 (const_int 0)))
7872 (clobber (match_scratch:DI 3 ""))]
7873 "TARGET_POWERPC64 && reload_completed"
7874 [(set (match_dup 3) (match_dup 4))
7875 (set (match_dup 0)
7876 (compare:CC (match_dup 3)
7877 (const_int 0)))]
7878 "")
7880 (define_insn "*boolcdi3_internal3"
7881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7882 (compare:CC (match_operator:DI 4 "boolean_operator"
7883 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7884 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7885 (const_int 0)))
7886 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7887 (match_dup 4))]
7888 "TARGET_64BIT"
7889 "@
7890 %q4. %0,%2,%1
7891 #"
7892 [(set_attr "type" "logical,compare")
7893 (set_attr "dot" "yes")
7894 (set_attr "length" "4,8")])
7896 (define_split
7897 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7898 (compare:CC (match_operator:DI 4 "boolean_operator"
7899 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7900 (match_operand:DI 2 "gpc_reg_operand" "")])
7901 (const_int 0)))
7902 (set (match_operand:DI 0 "gpc_reg_operand" "")
7903 (match_dup 4))]
7904 "TARGET_POWERPC64 && reload_completed"
7905 [(set (match_dup 0) (match_dup 4))
7906 (set (match_dup 3)
7907 (compare:CC (match_dup 0)
7908 (const_int 0)))]
7909 "")
7911 (define_insn "*boolccdi3_internal1"
7912 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7913 (match_operator:DI 3 "boolean_operator"
7914 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7915 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7916 "TARGET_POWERPC64"
7917 "%q3 %0,%1,%2")
7919 (define_insn "*boolccdi3_internal2"
7920 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7921 (compare:CC (match_operator:DI 4 "boolean_operator"
7922 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7923 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7924 (const_int 0)))
7925 (clobber (match_scratch:DI 3 "=r,r"))]
7926 "TARGET_64BIT"
7927 "@
7928 %q4. %3,%1,%2
7929 #"
7930 [(set_attr "type" "logical,compare")
7931 (set_attr "dot" "yes")
7932 (set_attr "length" "4,8")])
7934 (define_split
7935 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7936 (compare:CC (match_operator:DI 4 "boolean_operator"
7937 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7938 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7939 (const_int 0)))
7940 (clobber (match_scratch:DI 3 ""))]
7941 "TARGET_POWERPC64 && reload_completed"
7942 [(set (match_dup 3) (match_dup 4))
7943 (set (match_dup 0)
7944 (compare:CC (match_dup 3)
7945 (const_int 0)))]
7946 "")
7948 (define_insn "*boolccdi3_internal3"
7949 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7950 (compare:CC (match_operator:DI 4 "boolean_operator"
7951 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7952 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7953 (const_int 0)))
7954 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7955 (match_dup 4))]
7956 "TARGET_64BIT"
7957 "@
7958 %q4. %0,%1,%2
7959 #"
7960 [(set_attr "type" "logical,compare")
7961 (set_attr "dot" "yes")
7962 (set_attr "length" "4,8")])
7964 (define_split
7965 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7966 (compare:CC (match_operator:DI 4 "boolean_operator"
7967 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7968 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7969 (const_int 0)))
7970 (set (match_operand:DI 0 "gpc_reg_operand" "")
7971 (match_dup 4))]
7972 "TARGET_POWERPC64 && reload_completed"
7973 [(set (match_dup 0) (match_dup 4))
7974 (set (match_dup 3)
7975 (compare:CC (match_dup 0)
7976 (const_int 0)))]
7977 "")
7979 ;; Eqv operation.
7980 (define_insn "*eqv<mode>3"
7981 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
7982 (not:GPR
7983 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
7984 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
7985 ""
7986 "eqv %0,%1,%2"
7987 [(set_attr "type" "integer")
7988 (set_attr "length" "4")])
7990 \f
7991 ;; 128-bit logical operations expanders
7993 (define_expand "and<mode>3"
7994 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
7995 (and:BOOL_128
7996 (match_operand:BOOL_128 1 "vlogical_operand" "")
7997 (match_operand:BOOL_128 2 "vlogical_operand" "")))
7998 (clobber (match_scratch:CC 3 ""))])]
7999 ""
8000 "")
8002 (define_expand "ior<mode>3"
8003 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8004 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8005 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8006 ""
8007 "")
8009 (define_expand "xor<mode>3"
8010 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8011 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8012 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8013 ""
8014 "")
8016 (define_expand "one_cmpl<mode>2"
8017 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8018 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8019 ""
8020 "")
8022 (define_expand "nor<mode>3"
8023 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8024 (and:BOOL_128
8025 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8026 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8027 ""
8028 "")
8030 (define_expand "andc<mode>3"
8031 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8032 (and:BOOL_128
8033 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8034 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8035 ""
8036 "")
8038 ;; Power8 vector logical instructions.
8039 (define_expand "eqv<mode>3"
8040 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8041 (not:BOOL_128
8042 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8043 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8044 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8045 "")
8047 ;; Rewrite nand into canonical form
8048 (define_expand "nand<mode>3"
8049 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8050 (ior:BOOL_128
8051 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8052 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8053 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8054 "")
8056 ;; The canonical form is to have the negated element first, so we need to
8057 ;; reverse arguments.
8058 (define_expand "orc<mode>3"
8059 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8060 (ior:BOOL_128
8061 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8062 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8063 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8064 "")
8066 ;; 128-bit logical operations insns and split operations
8067 (define_insn_and_split "*and<mode>3_internal"
8068 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8069 (and:BOOL_128
8070 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8071 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
8072 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
8073 ""
8074 {
8075 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8076 return "xxland %x0,%x1,%x2";
8078 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8079 return "vand %0,%1,%2";
8081 return "#";
8082 }
8083 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8084 [(const_int 0)]
8085 {
8086 rs6000_split_logical (operands, AND, false, false, false, operands[3]);
8087 DONE;
8088 }
8089 [(set (attr "type")
8090 (if_then_else
8091 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8092 (const_string "vecsimple")
8093 (const_string "integer")))
8094 (set (attr "length")
8095 (if_then_else
8096 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8097 (const_string "4")
8098 (if_then_else
8099 (match_test "TARGET_POWERPC64")
8100 (const_string "8")
8101 (const_string "16"))))])
8103 ;; 128-bit IOR/XOR
8104 (define_insn_and_split "*bool<mode>3_internal"
8105 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8106 (match_operator:BOOL_128 3 "boolean_or_operator"
8107 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8108 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8109 ""
8110 {
8111 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8112 return "xxl%q3 %x0,%x1,%x2";
8114 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8115 return "v%q3 %0,%1,%2";
8117 return "#";
8118 }
8119 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8120 [(const_int 0)]
8121 {
8122 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
8123 NULL_RTX);
8124 DONE;
8125 }
8126 [(set (attr "type")
8127 (if_then_else
8128 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8129 (const_string "vecsimple")
8130 (const_string "integer")))
8131 (set (attr "length")
8132 (if_then_else
8133 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8134 (const_string "4")
8135 (if_then_else
8136 (match_test "TARGET_POWERPC64")
8137 (const_string "8")
8138 (const_string "16"))))])
8140 ;; 128-bit ANDC/ORC
8141 (define_insn_and_split "*boolc<mode>3_internal1"
8142 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8143 (match_operator:BOOL_128 3 "boolean_operator"
8144 [(not:BOOL_128
8145 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
8146 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8147 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8148 {
8149 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8150 return "xxl%q3 %x0,%x1,%x2";
8152 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8153 return "v%q3 %0,%1,%2";
8155 return "#";
8156 }
8157 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8158 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8159 [(const_int 0)]
8160 {
8161 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8162 NULL_RTX);
8163 DONE;
8164 }
8165 [(set (attr "type")
8166 (if_then_else
8167 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8168 (const_string "vecsimple")
8169 (const_string "integer")))
8170 (set (attr "length")
8171 (if_then_else
8172 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8173 (const_string "4")
8174 (if_then_else
8175 (match_test "TARGET_POWERPC64")
8176 (const_string "8")
8177 (const_string "16"))))])
8179 (define_insn_and_split "*boolc<mode>3_internal2"
8180 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8181 (match_operator:TI2 3 "boolean_operator"
8182 [(not:TI2
8183 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8184 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
8185 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8186 "#"
8187 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8188 [(const_int 0)]
8189 {
8190 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8191 NULL_RTX);
8192 DONE;
8193 }
8194 [(set_attr "type" "integer")
8195 (set (attr "length")
8196 (if_then_else
8197 (match_test "TARGET_POWERPC64")
8198 (const_string "8")
8199 (const_string "16")))])
8201 ;; 128-bit NAND/NOR
8202 (define_insn_and_split "*boolcc<mode>3_internal1"
8203 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8204 (match_operator:BOOL_128 3 "boolean_operator"
8205 [(not:BOOL_128
8206 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
8207 (not:BOOL_128
8208 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
8209 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8210 {
8211 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8212 return "xxl%q3 %x0,%x1,%x2";
8214 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8215 return "v%q3 %0,%1,%2";
8217 return "#";
8218 }
8219 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8220 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8221 [(const_int 0)]
8222 {
8223 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8224 NULL_RTX);
8225 DONE;
8226 }
8227 [(set (attr "type")
8228 (if_then_else
8229 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8230 (const_string "vecsimple")
8231 (const_string "integer")))
8232 (set (attr "length")
8233 (if_then_else
8234 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8235 (const_string "4")
8236 (if_then_else
8237 (match_test "TARGET_POWERPC64")
8238 (const_string "8")
8239 (const_string "16"))))])
8241 (define_insn_and_split "*boolcc<mode>3_internal2"
8242 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8243 (match_operator:TI2 3 "boolean_operator"
8244 [(not:TI2
8245 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8246 (not:TI2
8247 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
8248 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8249 "#"
8250 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8251 [(const_int 0)]
8252 {
8253 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8254 NULL_RTX);
8255 DONE;
8256 }
8257 [(set_attr "type" "integer")
8258 (set (attr "length")
8259 (if_then_else
8260 (match_test "TARGET_POWERPC64")
8261 (const_string "8")
8262 (const_string "16")))])
8265 ;; 128-bit EQV
8266 (define_insn_and_split "*eqv<mode>3_internal1"
8267 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8268 (not:BOOL_128
8269 (xor:BOOL_128
8270 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
8271 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
8272 "TARGET_P8_VECTOR"
8273 {
8274 if (vsx_register_operand (operands[0], <MODE>mode))
8275 return "xxleqv %x0,%x1,%x2";
8277 return "#";
8278 }
8279 "TARGET_P8_VECTOR && reload_completed
8280 && int_reg_operand (operands[0], <MODE>mode)"
8281 [(const_int 0)]
8282 {
8283 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8284 DONE;
8285 }
8286 [(set (attr "type")
8287 (if_then_else
8288 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8289 (const_string "vecsimple")
8290 (const_string "integer")))
8291 (set (attr "length")
8292 (if_then_else
8293 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8294 (const_string "4")
8295 (if_then_else
8296 (match_test "TARGET_POWERPC64")
8297 (const_string "8")
8298 (const_string "16"))))])
8300 (define_insn_and_split "*eqv<mode>3_internal2"
8301 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8302 (not:TI2
8303 (xor:TI2
8304 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
8305 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
8306 "!TARGET_P8_VECTOR"
8307 "#"
8308 "reload_completed && !TARGET_P8_VECTOR"
8309 [(const_int 0)]
8310 {
8311 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8312 DONE;
8313 }
8314 [(set_attr "type" "integer")
8315 (set (attr "length")
8316 (if_then_else
8317 (match_test "TARGET_POWERPC64")
8318 (const_string "8")
8319 (const_string "16")))])
8321 ;; 128-bit one's complement
8322 (define_insn_and_split "*one_cmpl<mode>3_internal"
8323 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8324 (not:BOOL_128
8325 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
8326 ""
8327 {
8328 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8329 return "xxlnor %x0,%x1,%x1";
8331 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8332 return "vnor %0,%1,%1";
8334 return "#";
8335 }
8336 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8337 [(const_int 0)]
8338 {
8339 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
8340 DONE;
8341 }
8342 [(set (attr "type")
8343 (if_then_else
8344 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8345 (const_string "vecsimple")
8346 (const_string "integer")))
8347 (set (attr "length")
8348 (if_then_else
8349 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8350 (const_string "4")
8351 (if_then_else
8352 (match_test "TARGET_POWERPC64")
8353 (const_string "8")
8354 (const_string "16"))))])
8356 \f
8357 ;; Now define ways of moving data around.
8359 ;; Set up a register with a value from the GOT table
8361 (define_expand "movsi_got"
8362 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8363 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8364 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8365 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8366 "
8367 {
8368 if (GET_CODE (operands[1]) == CONST)
8369 {
8370 rtx offset = const0_rtx;
8371 HOST_WIDE_INT value;
8373 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8374 value = INTVAL (offset);
8375 if (value != 0)
8376 {
8377 rtx tmp = (!can_create_pseudo_p ()
8378 ? operands[0]
8379 : gen_reg_rtx (Pmode));
8380 emit_insn (gen_movsi_got (tmp, operands[1]));
8381 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8382 DONE;
8383 }
8384 }
8386 operands[2] = rs6000_got_register (operands[1]);
8387 }")
8389 (define_insn "*movsi_got_internal"
8390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8391 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8392 (match_operand:SI 2 "gpc_reg_operand" "b")]
8393 UNSPEC_MOVSI_GOT))]
8394 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8395 "lwz %0,%a1@got(%2)"
8396 [(set_attr "type" "load")])
8398 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8399 ;; didn't get allocated to a hard register.
8400 (define_split
8401 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8402 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8403 (match_operand:SI 2 "memory_operand" "")]
8404 UNSPEC_MOVSI_GOT))]
8405 "DEFAULT_ABI == ABI_V4
8406 && flag_pic == 1
8407 && (reload_in_progress || reload_completed)"
8408 [(set (match_dup 0) (match_dup 2))
8409 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8410 UNSPEC_MOVSI_GOT))]
8411 "")
8413 ;; For SI, we special-case integers that can't be loaded in one insn. We
8414 ;; do the load 16-bits at a time. We could do this by loading from memory,
8415 ;; and this is even supposed to be faster, but it is simpler not to get
8416 ;; integers in the TOC.
8417 (define_insn "movsi_low"
8418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8419 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8420 (match_operand 2 "" ""))))]
8421 "TARGET_MACHO && ! TARGET_64BIT"
8422 "lwz %0,lo16(%2)(%1)"
8423 [(set_attr "type" "load")
8424 (set_attr "length" "4")])
8426 (define_insn "*movsi_internal1"
8427 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8428 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8429 "!TARGET_SINGLE_FPU &&
8430 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8431 "@
8432 mr %0,%1
8433 la %0,%a1
8434 lwz%U1%X1 %0,%1
8435 stw%U0%X0 %1,%0
8436 li %0,%1
8437 lis %0,%v1
8438 #
8439 mf%1 %0
8440 mt%0 %1
8441 mt%0 %1
8442 nop"
8443 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
8444 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8446 (define_insn "*movsi_internal1_single"
8447 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8448 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8449 "TARGET_SINGLE_FPU &&
8450 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8451 "@
8452 mr %0,%1
8453 la %0,%a1
8454 lwz%U1%X1 %0,%1
8455 stw%U0%X0 %1,%0
8456 li %0,%1
8457 lis %0,%v1
8458 #
8459 mf%1 %0
8460 mt%0 %1
8461 mt%0 %1
8462 nop
8463 stfs%U0%X0 %1,%0
8464 lfs%U1%X1 %0,%1"
8465 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
8466 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8468 ;; Split a load of a large constant into the appropriate two-insn
8469 ;; sequence.
8471 (define_split
8472 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8473 (match_operand:SI 1 "const_int_operand" ""))]
8474 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8475 && (INTVAL (operands[1]) & 0xffff) != 0"
8476 [(set (match_dup 0)
8477 (match_dup 2))
8478 (set (match_dup 0)
8479 (ior:SI (match_dup 0)
8480 (match_dup 3)))]
8481 "
8482 {
8483 if (rs6000_emit_set_const (operands[0], operands[1]))
8484 DONE;
8485 else
8486 FAIL;
8487 }")
8489 (define_insn "*mov<mode>_internal2"
8490 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8491 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8492 (const_int 0)))
8493 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8494 ""
8495 "@
8496 cmp<wd>i %2,%0,0
8497 mr. %0,%1
8498 #"
8499 [(set_attr "type" "cmp,logical,cmp")
8500 (set_attr "dot" "yes")
8501 (set_attr "length" "4,4,8")])
8503 (define_split
8504 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8505 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8506 (const_int 0)))
8507 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8508 "reload_completed"
8509 [(set (match_dup 0) (match_dup 1))
8510 (set (match_dup 2)
8511 (compare:CC (match_dup 0)
8512 (const_int 0)))]
8513 "")
8514 \f
8515 (define_insn "*movhi_internal"
8516 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8517 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8518 "gpc_reg_operand (operands[0], HImode)
8519 || gpc_reg_operand (operands[1], HImode)"
8520 "@
8521 mr %0,%1
8522 lhz%U1%X1 %0,%1
8523 sth%U0%X0 %1,%0
8524 li %0,%w1
8525 mf%1 %0
8526 mt%0 %1
8527 nop"
8528 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
8530 (define_expand "mov<mode>"
8531 [(set (match_operand:INT 0 "general_operand" "")
8532 (match_operand:INT 1 "any_operand" ""))]
8533 ""
8534 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8536 (define_insn "*movqi_internal"
8537 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8538 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8539 "gpc_reg_operand (operands[0], QImode)
8540 || gpc_reg_operand (operands[1], QImode)"
8541 "@
8542 mr %0,%1
8543 lbz%U1%X1 %0,%1
8544 stb%U0%X0 %1,%0
8545 li %0,%1
8546 mf%1 %0
8547 mt%0 %1
8548 nop"
8549 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
8550 \f
8551 ;; Here is how to move condition codes around. When we store CC data in
8552 ;; an integer register or memory, we store just the high-order 4 bits.
8553 ;; This lets us not shift in the most common case of CR0.
8554 (define_expand "movcc"
8555 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8556 (match_operand:CC 1 "nonimmediate_operand" ""))]
8557 ""
8558 "")
8560 (define_insn "*movcc_internal1"
8561 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
8562 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
8563 "register_operand (operands[0], CCmode)
8564 || register_operand (operands[1], CCmode)"
8565 "@
8566 mcrf %0,%1
8567 mtcrf 128,%1
8568 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
8569 crxor %0,%0,%0
8570 mfcr %0%Q1
8571 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
8572 mr %0,%1
8573 li %0,%1
8574 mf%1 %0
8575 mt%0 %1
8576 lwz%U1%X1 %0,%1
8577 stw%U0%X0 %1,%0"
8578 [(set (attr "type")
8579 (cond [(eq_attr "alternative" "0,3")
8580 (const_string "cr_logical")
8581 (eq_attr "alternative" "1,2")
8582 (const_string "mtcr")
8583 (eq_attr "alternative" "6,7")
8584 (const_string "integer")
8585 (eq_attr "alternative" "8")
8586 (const_string "mfjmpr")
8587 (eq_attr "alternative" "9")
8588 (const_string "mtjmpr")
8589 (eq_attr "alternative" "10")
8590 (const_string "load")
8591 (eq_attr "alternative" "11")
8592 (const_string "store")
8593 (match_test "TARGET_MFCRF")
8594 (const_string "mfcrf")
8595 ]
8596 (const_string "mfcr")))
8597 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
8598 \f
8599 ;; For floating-point, we normally deal with the floating-point registers
8600 ;; unless -msoft-float is used. The sole exception is that parameter passing
8601 ;; can produce floating-point values in fixed-point registers. Unless the
8602 ;; value is a simple constant or already in memory, we deal with this by
8603 ;; allocating memory and copying the value explicitly via that memory location.
8605 ;; Move 32-bit binary/decimal floating point
8606 (define_expand "mov<mode>"
8607 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
8608 (match_operand:FMOVE32 1 "any_operand" ""))]
8609 "<fmove_ok>"
8610 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8612 (define_split
8613 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
8614 (match_operand:FMOVE32 1 "const_double_operand" ""))]
8615 "reload_completed
8616 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8617 || (GET_CODE (operands[0]) == SUBREG
8618 && GET_CODE (SUBREG_REG (operands[0])) == REG
8619 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8620 [(set (match_dup 2) (match_dup 3))]
8621 "
8622 {
8623 long l;
8624 REAL_VALUE_TYPE rv;
8626 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8627 <real_value_to_target> (rv, l);
8629 if (! TARGET_POWERPC64)
8630 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
8631 else
8632 operands[2] = gen_lowpart (SImode, operands[0]);
8634 operands[3] = gen_int_mode (l, SImode);
8635 }")
8637 (define_insn "mov<mode>_hardfloat"
8638 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
8639 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
8640 "(gpc_reg_operand (operands[0], <MODE>mode)
8641 || gpc_reg_operand (operands[1], <MODE>mode))
8642 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8643 "@
8644 mr %0,%1
8645 lwz%U1%X1 %0,%1
8646 stw%U0%X0 %1,%0
8647 fmr %0,%1
8648 xxlor %x0,%x1,%x1
8649 xxlxor %x0,%x0,%x0
8650 <f32_li>
8651 <f32_si>
8652 <f32_lv>
8653 <f32_sv>
8654 mtvsrwz %x0,%1
8655 mfvsrwz %0,%x1
8656 mt%0 %1
8657 mf%1 %0
8658 nop
8659 #
8660 #"
8661 [(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
8662 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
8664 (define_insn "*mov<mode>_softfloat"
8665 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
8666 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
8667 "(gpc_reg_operand (operands[0], <MODE>mode)
8668 || gpc_reg_operand (operands[1], <MODE>mode))
8669 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8670 "@
8671 mr %0,%1
8672 mt%0 %1
8673 mf%1 %0
8674 lwz%U1%X1 %0,%1
8675 stw%U0%X0 %1,%0
8676 li %0,%1
8677 lis %0,%v1
8678 #
8679 #
8680 nop"
8681 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
8682 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
8684 \f
8685 ;; Move 64-bit binary/decimal floating point
8686 (define_expand "mov<mode>"
8687 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
8688 (match_operand:FMOVE64 1 "any_operand" ""))]
8689 ""
8690 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8692 (define_split
8693 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8694 (match_operand:FMOVE64 1 "const_int_operand" ""))]
8695 "! TARGET_POWERPC64 && reload_completed
8696 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8697 || (GET_CODE (operands[0]) == SUBREG
8698 && GET_CODE (SUBREG_REG (operands[0])) == REG
8699 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8700 [(set (match_dup 2) (match_dup 4))
8701 (set (match_dup 3) (match_dup 1))]
8702 "
8703 {
8704 int endian = (WORDS_BIG_ENDIAN == 0);
8705 HOST_WIDE_INT value = INTVAL (operands[1]);
8707 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8708 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8709 operands[4] = GEN_INT (value >> 32);
8710 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8711 }")
8713 (define_split
8714 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8715 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8716 "! TARGET_POWERPC64 && reload_completed
8717 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8718 || (GET_CODE (operands[0]) == SUBREG
8719 && GET_CODE (SUBREG_REG (operands[0])) == REG
8720 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8721 [(set (match_dup 2) (match_dup 4))
8722 (set (match_dup 3) (match_dup 5))]
8723 "
8724 {
8725 int endian = (WORDS_BIG_ENDIAN == 0);
8726 long l[2];
8727 REAL_VALUE_TYPE rv;
8729 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8730 <real_value_to_target> (rv, l);
8732 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
8733 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
8734 operands[4] = gen_int_mode (l[endian], SImode);
8735 operands[5] = gen_int_mode (l[1 - endian], SImode);
8736 }")
8738 (define_split
8739 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
8740 (match_operand:FMOVE64 1 "const_double_operand" ""))]
8741 "TARGET_POWERPC64 && reload_completed
8742 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8743 || (GET_CODE (operands[0]) == SUBREG
8744 && GET_CODE (SUBREG_REG (operands[0])) == REG
8745 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8746 [(set (match_dup 2) (match_dup 3))]
8747 "
8748 {
8749 int endian = (WORDS_BIG_ENDIAN == 0);
8750 long l[2];
8751 REAL_VALUE_TYPE rv;
8752 HOST_WIDE_INT val;
8754 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8755 <real_value_to_target> (rv, l);
8757 operands[2] = gen_lowpart (DImode, operands[0]);
8758 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8759 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8760 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8762 operands[3] = gen_int_mode (val, DImode);
8763 }")
8765 ;; Don't have reload use general registers to load a constant. It is
8766 ;; less efficient than loading the constant into an FP register, since
8767 ;; it will probably be used there.
8769 ;; The move constraints are ordered to prefer floating point registers before
8770 ;; general purpose registers to avoid doing a store and a load to get the value
8771 ;; into a floating point register when it is needed for a floating point
8772 ;; operation. Prefer traditional floating point registers over VSX registers,
8773 ;; since the D-form version of the memory instructions does not need a GPR for
8774 ;; reloading.
8776 (define_insn "*mov<mode>_hardfloat32"
8777 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
8778 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
8779 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8780 && (gpc_reg_operand (operands[0], <MODE>mode)
8781 || gpc_reg_operand (operands[1], <MODE>mode))"
8782 "@
8783 stfd%U0%X0 %1,%0
8784 lfd%U1%X1 %0,%1
8785 fmr %0,%1
8786 lxsd%U1x %x0,%y1
8787 stxsd%U0x %x1,%y0
8788 xxlor %x0,%x1,%x1
8789 xxlxor %x0,%x0,%x0
8790 #
8791 #
8792 #
8793 #
8794 #
8795 #"
8796 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
8797 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
8799 (define_insn "*mov<mode>_softfloat32"
8800 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8801 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
8802 "! TARGET_POWERPC64
8803 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8804 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
8805 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
8806 && (gpc_reg_operand (operands[0], <MODE>mode)
8807 || gpc_reg_operand (operands[1], <MODE>mode))"
8808 "#"
8809 [(set_attr "type" "store,load,two,*,*,*")
8810 (set_attr "length" "8,8,8,8,12,16")])
8812 ; ld/std require word-aligned displacements -> 'Y' constraint.
8813 ; List Y->r and r->Y before r->r for reload.
8814 (define_insn "*mov<mode>_hardfloat64"
8815 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
8816 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
8817 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8818 && (gpc_reg_operand (operands[0], <MODE>mode)
8819 || gpc_reg_operand (operands[1], <MODE>mode))"
8820 "@
8821 stfd%U0%X0 %1,%0
8822 lfd%U1%X1 %0,%1
8823 fmr %0,%1
8824 lxsd%U1x %x0,%y1
8825 stxsd%U0x %x1,%y0
8826 xxlor %x0,%x1,%x1
8827 xxlxor %x0,%x0,%x0
8828 std%U0%X0 %1,%0
8829 ld%U1%X1 %0,%1
8830 mr %0,%1
8831 mt%0 %1
8832 mf%1 %0
8833 nop
8834 #
8835 #
8836 #
8837 mftgpr %0,%1
8838 mffgpr %0,%1
8839 mfvsrd %0,%x1
8840 mtvsrd %x0,%1"
8841 [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
8842 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
8844 (define_insn "*mov<mode>_softfloat64"
8845 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8846 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8847 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8848 && (gpc_reg_operand (operands[0], <MODE>mode)
8849 || gpc_reg_operand (operands[1], <MODE>mode))"
8850 "@
8851 std%U0%X0 %1,%0
8852 ld%U1%X1 %0,%1
8853 mr %0,%1
8854 mt%0 %1
8855 mf%1 %0
8856 #
8857 #
8858 #
8859 nop"
8860 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8861 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8862 \f
8863 (define_expand "mov<mode>"
8864 [(set (match_operand:FMOVE128 0 "general_operand" "")
8865 (match_operand:FMOVE128 1 "any_operand" ""))]
8866 ""
8867 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8869 ;; It's important to list Y->r and r->Y before r->r because otherwise
8870 ;; reload, given m->r, will try to pick r->r and reload it, which
8871 ;; doesn't make progress.
8873 ;; We can't split little endian direct moves of TDmode, because the words are
8874 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8875 ;; problematical. Don't allow direct move for this case.
8877 (define_insn_and_split "*mov<mode>_64bit_dm"
8878 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
8879 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
8880 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8881 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8882 && (gpc_reg_operand (operands[0], <MODE>mode)
8883 || gpc_reg_operand (operands[1], <MODE>mode))"
8884 "#"
8885 "&& reload_completed"
8886 [(pc)]
8887 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8888 [(set_attr "length" "8,8,8,12,12,8,8,8")])
8890 (define_insn_and_split "*movtd_64bit_nodm"
8891 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8892 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
8893 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8894 && (gpc_reg_operand (operands[0], TDmode)
8895 || gpc_reg_operand (operands[1], TDmode))"
8896 "#"
8897 "&& reload_completed"
8898 [(pc)]
8899 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8900 [(set_attr "length" "8,8,8,12,12,8")])
8902 (define_insn_and_split "*mov<mode>_32bit"
8903 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8904 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
8905 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
8906 && (gpc_reg_operand (operands[0], <MODE>mode)
8907 || gpc_reg_operand (operands[1], <MODE>mode))"
8908 "#"
8909 "&& reload_completed"
8910 [(pc)]
8911 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8912 [(set_attr "length" "8,8,8,20,20,16")])
8914 (define_insn_and_split "*mov<mode>_softfloat"
8915 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8916 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
8917 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
8918 && (gpc_reg_operand (operands[0], <MODE>mode)
8919 || gpc_reg_operand (operands[1], <MODE>mode))"
8920 "#"
8921 "&& reload_completed"
8922 [(pc)]
8923 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8924 [(set_attr "length" "20,20,16")])
8926 (define_expand "extenddftf2"
8927 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8928 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8929 "!TARGET_IEEEQUAD
8930 && TARGET_HARD_FLOAT
8931 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8932 && TARGET_LONG_DOUBLE_128"
8933 {
8934 if (TARGET_E500_DOUBLE)
8935 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8936 else
8937 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8938 DONE;
8939 })
8941 (define_expand "extenddftf2_fprs"
8942 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8943 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8944 (use (match_dup 2))])]
8945 "!TARGET_IEEEQUAD
8946 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8947 && TARGET_LONG_DOUBLE_128"
8948 {
8949 operands[2] = CONST0_RTX (DFmode);
8950 /* Generate GOT reference early for SVR4 PIC. */
8951 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8952 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8953 })
8955 (define_insn_and_split "*extenddftf2_internal"
8956 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8957 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8958 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8959 "!TARGET_IEEEQUAD
8960 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8961 && TARGET_LONG_DOUBLE_128"
8962 "#"
8963 "&& reload_completed"
8964 [(pc)]
8965 {
8966 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
8967 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
8968 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8969 operands[1]);
8970 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8971 operands[2]);
8972 DONE;
8973 })
8975 (define_expand "extendsftf2"
8976 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8977 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8978 "!TARGET_IEEEQUAD
8979 && TARGET_HARD_FLOAT
8980 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8981 && TARGET_LONG_DOUBLE_128"
8982 {
8983 rtx tmp = gen_reg_rtx (DFmode);
8984 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8985 emit_insn (gen_extenddftf2 (operands[0], tmp));
8986 DONE;
8987 })
8989 (define_expand "trunctfdf2"
8990 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8991 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8992 "!TARGET_IEEEQUAD
8993 && TARGET_HARD_FLOAT
8994 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8995 && TARGET_LONG_DOUBLE_128"
8996 "")
8998 (define_insn_and_split "trunctfdf2_internal1"
8999 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9000 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9001 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9002 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9003 "@
9004 #
9005 fmr %0,%1"
9006 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9007 [(const_int 0)]
9008 {
9009 emit_note (NOTE_INSN_DELETED);
9010 DONE;
9011 }
9012 [(set_attr "type" "fp")])
9014 (define_insn "trunctfdf2_internal2"
9015 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9016 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9017 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9018 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9019 && TARGET_LONG_DOUBLE_128"
9020 "fadd %0,%1,%L1"
9021 [(set_attr "type" "fp")
9022 (set_attr "fp_type" "fp_addsub_d")])
9024 (define_expand "trunctfsf2"
9025 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9026 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9027 "!TARGET_IEEEQUAD
9028 && TARGET_HARD_FLOAT
9029 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9030 && TARGET_LONG_DOUBLE_128"
9031 {
9032 if (TARGET_E500_DOUBLE)
9033 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9034 else
9035 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9036 DONE;
9037 })
9039 (define_insn_and_split "trunctfsf2_fprs"
9040 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9041 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9042 (clobber (match_scratch:DF 2 "=d"))]
9043 "!TARGET_IEEEQUAD
9044 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9045 && TARGET_LONG_DOUBLE_128"
9046 "#"
9047 "&& reload_completed"
9048 [(set (match_dup 2)
9049 (float_truncate:DF (match_dup 1)))
9050 (set (match_dup 0)
9051 (float_truncate:SF (match_dup 2)))]
9052 "")
9054 (define_expand "floatsitf2"
9055 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9056 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9057 "!TARGET_IEEEQUAD
9058 && TARGET_HARD_FLOAT
9059 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9060 && TARGET_LONG_DOUBLE_128"
9061 {
9062 rtx tmp = gen_reg_rtx (DFmode);
9063 expand_float (tmp, operands[1], false);
9064 emit_insn (gen_extenddftf2 (operands[0], tmp));
9065 DONE;
9066 })
9068 ; fadd, but rounding towards zero.
9069 ; This is probably not the optimal code sequence.
9070 (define_insn "fix_trunc_helper"
9071 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9072 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9073 UNSPEC_FIX_TRUNC_TF))
9074 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9075 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9076 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9077 [(set_attr "type" "fp")
9078 (set_attr "length" "20")])
9080 (define_expand "fix_trunctfsi2"
9081 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9082 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9083 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9084 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9085 {
9086 if (TARGET_E500_DOUBLE)
9087 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9088 else
9089 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9090 DONE;
9091 })
9093 (define_expand "fix_trunctfsi2_fprs"
9094 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9095 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9096 (clobber (match_dup 2))
9097 (clobber (match_dup 3))
9098 (clobber (match_dup 4))
9099 (clobber (match_dup 5))])]
9100 "!TARGET_IEEEQUAD
9101 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9102 {
9103 operands[2] = gen_reg_rtx (DFmode);
9104 operands[3] = gen_reg_rtx (DFmode);
9105 operands[4] = gen_reg_rtx (DImode);
9106 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9107 })
9109 (define_insn_and_split "*fix_trunctfsi2_internal"
9110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9111 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9112 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9113 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9114 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9115 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9116 "!TARGET_IEEEQUAD
9117 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9118 "#"
9119 ""
9120 [(pc)]
9121 {
9122 rtx lowword;
9123 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9125 gcc_assert (MEM_P (operands[5]));
9126 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9128 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9129 emit_move_insn (operands[5], operands[4]);
9130 emit_move_insn (operands[0], lowword);
9131 DONE;
9132 })
9134 (define_expand "negtf2"
9135 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9136 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9137 "!TARGET_IEEEQUAD
9138 && TARGET_HARD_FLOAT
9139 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9140 && TARGET_LONG_DOUBLE_128"
9141 "")
9143 (define_insn "negtf2_internal"
9144 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9145 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9146 "!TARGET_IEEEQUAD
9147 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9148 "*
9149 {
9150 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9151 return \"fneg %L0,%L1\;fneg %0,%1\";
9152 else
9153 return \"fneg %0,%1\;fneg %L0,%L1\";
9154 }"
9155 [(set_attr "type" "fp")
9156 (set_attr "length" "8")])
9158 (define_expand "abstf2"
9159 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9160 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9161 "!TARGET_IEEEQUAD
9162 && TARGET_HARD_FLOAT
9163 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9164 && TARGET_LONG_DOUBLE_128"
9165 "
9166 {
9167 rtx label = gen_label_rtx ();
9168 if (TARGET_E500_DOUBLE)
9169 {
9170 if (flag_finite_math_only && !flag_trapping_math)
9171 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9172 else
9173 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9174 }
9175 else
9176 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9177 emit_label (label);
9178 DONE;
9179 }")
9181 (define_expand "abstf2_internal"
9182 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9183 (match_operand:TF 1 "gpc_reg_operand" ""))
9184 (set (match_dup 3) (match_dup 5))
9185 (set (match_dup 5) (abs:DF (match_dup 5)))
9186 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9187 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9188 (label_ref (match_operand 2 "" ""))
9189 (pc)))
9190 (set (match_dup 6) (neg:DF (match_dup 6)))]
9191 "!TARGET_IEEEQUAD
9192 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9193 && TARGET_LONG_DOUBLE_128"
9194 "
9195 {
9196 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9197 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9198 operands[3] = gen_reg_rtx (DFmode);
9199 operands[4] = gen_reg_rtx (CCFPmode);
9200 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9201 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9202 }")
9203 \f
9204 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9205 ;; must have 3 arguments, and scratch register constraint must be a single
9206 ;; constraint.
9208 ;; Reload patterns to support gpr load/store with misaligned mem.
9209 ;; and multiple gpr load/store at offset >= 0xfffc
9210 (define_expand "reload_<mode>_store"
9211 [(parallel [(match_operand 0 "memory_operand" "=m")
9212 (match_operand 1 "gpc_reg_operand" "r")
9213 (match_operand:GPR 2 "register_operand" "=&b")])]
9214 ""
9215 {
9216 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9217 DONE;
9218 })
9220 (define_expand "reload_<mode>_load"
9221 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9222 (match_operand 1 "memory_operand" "m")
9223 (match_operand:GPR 2 "register_operand" "=b")])]
9224 ""
9225 {
9226 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9227 DONE;
9228 })
9230 \f
9231 ;; Power8 merge instructions to allow direct move to/from floating point
9232 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
9233 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
9234 ;; value, since it is allocated in reload and not all of the flow information
9235 ;; is setup for it. We have two patterns to do the two moves between gprs and
9236 ;; fprs. There isn't a dependancy between the two, but we could potentially
9237 ;; schedule other instructions between the two instructions. TFmode is
9238 ;; currently limited to traditional FPR registers. If/when this is changed, we
9239 ;; will need to revist %L to make sure it works with VSX registers, or add an
9240 ;; %x version of %L.
9242 (define_insn "p8_fmrgow_<mode>"
9243 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
9244 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
9245 UNSPEC_P8V_FMRGOW))]
9246 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9247 "fmrgow %0,%1,%L1"
9248 [(set_attr "type" "vecperm")])
9250 (define_insn "p8_mtvsrwz_1"
9251 [(set (match_operand:TF 0 "register_operand" "=d")
9252 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
9253 UNSPEC_P8V_MTVSRWZ))]
9254 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9255 "mtvsrwz %x0,%1"
9256 [(set_attr "type" "mftgpr")])
9258 (define_insn "p8_mtvsrwz_2"
9259 [(set (match_operand:TF 0 "register_operand" "+d")
9260 (unspec:TF [(match_dup 0)
9261 (match_operand:SI 1 "register_operand" "r")]
9262 UNSPEC_P8V_MTVSRWZ))]
9263 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9264 "mtvsrwz %L0,%1"
9265 [(set_attr "type" "mftgpr")])
9267 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9268 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
9269 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
9270 UNSPEC_P8V_RELOAD_FROM_GPR))
9271 (clobber (match_operand:TF 2 "register_operand" "=d"))]
9272 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9273 "#"
9274 "&& reload_completed"
9275 [(const_int 0)]
9276 {
9277 rtx dest = operands[0];
9278 rtx src = operands[1];
9279 rtx tmp = operands[2];
9280 rtx gpr_hi_reg = gen_highpart (SImode, src);
9281 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9283 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
9284 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
9285 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
9286 DONE;
9287 }
9288 [(set_attr "length" "12")
9289 (set_attr "type" "three")])
9291 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
9292 (define_insn "p8_mtvsrd_1"
9293 [(set (match_operand:TF 0 "register_operand" "=ws")
9294 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
9295 UNSPEC_P8V_MTVSRD))]
9296 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9297 "mtvsrd %0,%1"
9298 [(set_attr "type" "mftgpr")])
9300 (define_insn "p8_mtvsrd_2"
9301 [(set (match_operand:TF 0 "register_operand" "+ws")
9302 (unspec:TF [(match_dup 0)
9303 (match_operand:DI 1 "register_operand" "r")]
9304 UNSPEC_P8V_MTVSRD))]
9305 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9306 "mtvsrd %L0,%1"
9307 [(set_attr "type" "mftgpr")])
9309 (define_insn "p8_xxpermdi_<mode>"
9310 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9311 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
9312 UNSPEC_P8V_XXPERMDI))]
9313 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9314 "xxpermdi %x0,%1,%L1,0"
9315 [(set_attr "type" "vecperm")])
9317 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9318 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9319 (unspec:FMOVE128_GPR
9320 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
9321 UNSPEC_P8V_RELOAD_FROM_GPR))
9322 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
9323 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9324 "#"
9325 "&& reload_completed"
9326 [(const_int 0)]
9327 {
9328 rtx dest = operands[0];
9329 rtx src = operands[1];
9330 rtx tmp = operands[2];
9331 rtx gpr_hi_reg = gen_highpart (DImode, src);
9332 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9334 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
9335 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
9336 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
9337 }
9338 [(set_attr "length" "12")
9339 (set_attr "type" "three")])
9341 (define_split
9342 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
9343 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
9344 "reload_completed
9345 && (int_reg_operand (operands[0], <MODE>mode)
9346 || int_reg_operand (operands[1], <MODE>mode))"
9347 [(pc)]
9348 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9350 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9351 ;; type is stored internally as double precision in the VSX registers, we have
9352 ;; to convert it from the vector format.
9354 (define_insn_and_split "reload_vsx_from_gprsf"
9355 [(set (match_operand:SF 0 "register_operand" "=wa")
9356 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
9357 UNSPEC_P8V_RELOAD_FROM_GPR))
9358 (clobber (match_operand:DI 2 "register_operand" "=r"))]
9359 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9360 "#"
9361 "&& reload_completed"
9362 [(const_int 0)]
9363 {
9364 rtx op0 = operands[0];
9365 rtx op1 = operands[1];
9366 rtx op2 = operands[2];
9367 /* Also use the destination register to hold the unconverted DImode value.
9368 This is conceptually a separate value from OP0, so we use gen_rtx_REG
9369 rather than simplify_gen_subreg. */
9370 rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
9371 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
9373 /* Move SF value to upper 32-bits for xscvspdpn. */
9374 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
9375 emit_move_insn (op0_di, op2);
9376 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
9377 DONE;
9378 }
9379 [(set_attr "length" "8")
9380 (set_attr "type" "two")])
9382 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
9383 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
9384 ;; and then doing a move of that.
9385 (define_insn "p8_mfvsrd_3_<mode>"
9386 [(set (match_operand:DF 0 "register_operand" "=r")
9387 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9388 UNSPEC_P8V_RELOAD_FROM_VSX))]
9389 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9390 "mfvsrd %0,%x1"
9391 [(set_attr "type" "mftgpr")])
9393 (define_insn_and_split "reload_gpr_from_vsx<mode>"
9394 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
9395 (unspec:FMOVE128_GPR
9396 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
9397 UNSPEC_P8V_RELOAD_FROM_VSX))
9398 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
9399 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9400 "#"
9401 "&& reload_completed"
9402 [(const_int 0)]
9403 {
9404 rtx dest = operands[0];
9405 rtx src = operands[1];
9406 rtx tmp = operands[2];
9407 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
9408 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
9410 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
9411 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
9412 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
9413 }
9414 [(set_attr "length" "12")
9415 (set_attr "type" "three")])
9417 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
9418 ;; type is stored internally as double precision, we have to convert it to the
9419 ;; vector format.
9421 (define_insn_and_split "reload_gpr_from_vsxsf"
9422 [(set (match_operand:SF 0 "register_operand" "=r")
9423 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
9424 UNSPEC_P8V_RELOAD_FROM_VSX))
9425 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
9426 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9427 "#"
9428 "&& reload_completed"
9429 [(const_int 0)]
9430 {
9431 rtx op0 = operands[0];
9432 rtx op1 = operands[1];
9433 rtx op2 = operands[2];
9434 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
9436 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
9437 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
9438 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
9439 DONE;
9440 }
9441 [(set_attr "length" "12")
9442 (set_attr "type" "three")])
9444 (define_insn "p8_mfvsrd_4_disf"
9445 [(set (match_operand:DI 0 "register_operand" "=r")
9446 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
9447 UNSPEC_P8V_RELOAD_FROM_VSX))]
9448 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9449 "mfvsrd %0,%x1"
9450 [(set_attr "type" "mftgpr")])
9452 \f
9453 ;; Next come the multi-word integer load and store and the load and store
9454 ;; multiple insns.
9456 ;; List r->r after r->Y, otherwise reload will try to reload a
9457 ;; non-offsettable address by using r->r which won't make progress.
9458 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9459 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9460 (define_insn "*movdi_internal32"
9461 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
9462 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
9463 "! TARGET_POWERPC64
9464 && (gpc_reg_operand (operands[0], DImode)
9465 || gpc_reg_operand (operands[1], DImode))"
9466 "@
9467 #
9468 #
9469 #
9470 stfd%U0%X0 %1,%0
9471 lfd%U1%X1 %0,%1
9472 fmr %0,%1
9473 #"
9474 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*")])
9476 (define_split
9477 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9478 (match_operand:DI 1 "const_int_operand" ""))]
9479 "! TARGET_POWERPC64 && reload_completed
9480 && gpr_or_gpr_p (operands[0], operands[1])
9481 && !direct_move_p (operands[0], operands[1])"
9482 [(set (match_dup 2) (match_dup 4))
9483 (set (match_dup 3) (match_dup 1))]
9484 "
9485 {
9486 HOST_WIDE_INT value = INTVAL (operands[1]);
9487 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9488 DImode);
9489 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9490 DImode);
9491 operands[4] = GEN_INT (value >> 32);
9492 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9493 }")
9495 (define_split
9496 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9497 (match_operand:DIFD 1 "input_operand" ""))]
9498 "reload_completed && !TARGET_POWERPC64
9499 && gpr_or_gpr_p (operands[0], operands[1])
9500 && !direct_move_p (operands[0], operands[1])"
9501 [(pc)]
9502 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9504 (define_insn "*movdi_internal64"
9505 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
9506 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
9507 "TARGET_POWERPC64
9508 && (gpc_reg_operand (operands[0], DImode)
9509 || gpc_reg_operand (operands[1], DImode))"
9510 "@
9511 std%U0%X0 %1,%0
9512 ld%U1%X1 %0,%1
9513 mr %0,%1
9514 li %0,%1
9515 lis %0,%v1
9516 #
9517 stfd%U0%X0 %1,%0
9518 lfd%U1%X1 %0,%1
9519 fmr %0,%1
9520 mf%1 %0
9521 mt%0 %1
9522 nop
9523 mftgpr %0,%1
9524 mffgpr %0,%1
9525 mfvsrd %0,%x1
9526 mtvsrd %x0,%1
9527 xxlxor %x0,%x0,%x0"
9528 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr,vecsimple")
9529 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
9531 ;; Generate all one-bits and clear left or right.
9532 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9533 (define_split
9534 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9535 (match_operand:DI 1 "mask64_operand" ""))]
9536 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9537 [(set (match_dup 0) (const_int -1))
9538 (set (match_dup 0)
9539 (and:DI (rotate:DI (match_dup 0)
9540 (const_int 0))
9541 (match_dup 1)))]
9542 "")
9544 ;; Split a load of a large constant into the appropriate five-instruction
9545 ;; sequence. Handle anything in a constant number of insns.
9546 ;; When non-easy constants can go in the TOC, this should use
9547 ;; easy_fp_constant predicate.
9548 (define_split
9549 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9550 (match_operand:DI 1 "const_int_operand" ""))]
9551 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9552 [(set (match_dup 0) (match_dup 2))
9553 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9554 "
9555 {
9556 if (rs6000_emit_set_const (operands[0], operands[1]))
9557 DONE;
9558 else
9559 FAIL;
9560 }")
9562 (define_split
9563 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9564 (match_operand:DI 1 "const_scalar_int_operand" ""))]
9565 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9566 [(set (match_dup 0) (match_dup 2))
9567 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9568 "
9569 {
9570 if (rs6000_emit_set_const (operands[0], operands[1]))
9571 DONE;
9572 else
9573 FAIL;
9574 }")
9575 \f
9576 ;; TImode/PTImode is similar, except that we usually want to compute the
9577 ;; address into a register and use lsi/stsi (the exception is during reload).
9579 (define_insn "*mov<mode>_string"
9580 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9581 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
9582 "! TARGET_POWERPC64
9583 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
9584 && (gpc_reg_operand (operands[0], <MODE>mode)
9585 || gpc_reg_operand (operands[1], <MODE>mode))"
9586 "*
9587 {
9588 switch (which_alternative)
9589 {
9590 default:
9591 gcc_unreachable ();
9592 case 0:
9593 if (TARGET_STRING)
9594 return \"stswi %1,%P0,16\";
9595 case 1:
9596 return \"#\";
9597 case 2:
9598 /* If the address is not used in the output, we can use lsi. Otherwise,
9599 fall through to generating four loads. */
9600 if (TARGET_STRING
9601 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9602 return \"lswi %0,%P1,16\";
9603 /* ... fall through ... */
9604 case 3:
9605 case 4:
9606 case 5:
9607 return \"#\";
9608 }
9609 }"
9610 [(set_attr "type" "store,store,load,load,*,*")
9611 (set_attr "update" "yes")
9612 (set_attr "indexed" "yes")
9613 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9614 (const_string "always")
9615 (const_string "conditional")))])
9617 (define_insn "*mov<mode>_ppc64"
9618 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
9619 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
9620 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
9621 && (gpc_reg_operand (operands[0], <MODE>mode)
9622 || gpc_reg_operand (operands[1], <MODE>mode)))"
9623 {
9624 return rs6000_output_move_128bit (operands);
9625 }
9626 [(set_attr "type" "store,store,load,load,*,*")
9627 (set_attr "length" "8")])
9629 (define_split
9630 [(set (match_operand:TI2 0 "int_reg_operand" "")
9631 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
9632 "TARGET_POWERPC64
9633 && (VECTOR_MEM_NONE_P (<MODE>mode)
9634 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
9635 [(set (match_dup 2) (match_dup 4))
9636 (set (match_dup 3) (match_dup 5))]
9637 "
9638 {
9639 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9640 <MODE>mode);
9641 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9642 <MODE>mode);
9643 if (CONST_WIDE_INT_P (operands[1]))
9644 {
9645 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
9646 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
9647 }
9648 else if (CONST_INT_P (operands[1]))
9649 {
9650 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9651 operands[5] = operands[1];
9652 }
9653 else
9654 FAIL;
9655 }")
9657 (define_split
9658 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
9659 (match_operand:TI2 1 "input_operand" ""))]
9660 "reload_completed
9661 && gpr_or_gpr_p (operands[0], operands[1])
9662 && !direct_move_p (operands[0], operands[1])
9663 && !quad_load_store_p (operands[0], operands[1])"
9664 [(pc)]
9665 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9666 \f
9667 (define_expand "load_multiple"
9668 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9669 (match_operand:SI 1 "" ""))
9670 (use (match_operand:SI 2 "" ""))])]
9671 "TARGET_STRING && !TARGET_POWERPC64"
9672 "
9673 {
9674 int regno;
9675 int count;
9676 rtx op1;
9677 int i;
9679 /* Support only loading a constant number of fixed-point registers from
9680 memory and only bother with this if more than two; the machine
9681 doesn't support more than eight. */
9682 if (GET_CODE (operands[2]) != CONST_INT
9683 || INTVAL (operands[2]) <= 2
9684 || INTVAL (operands[2]) > 8
9685 || GET_CODE (operands[1]) != MEM
9686 || GET_CODE (operands[0]) != REG
9687 || REGNO (operands[0]) >= 32)
9688 FAIL;
9690 count = INTVAL (operands[2]);
9691 regno = REGNO (operands[0]);
9693 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9694 op1 = replace_equiv_address (operands[1],
9695 force_reg (SImode, XEXP (operands[1], 0)));
9697 for (i = 0; i < count; i++)
9698 XVECEXP (operands[3], 0, i)
9699 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9700 adjust_address_nv (op1, SImode, i * 4));
9701 }")
9703 (define_insn "*ldmsi8"
9704 [(match_parallel 0 "load_multiple_operation"
9705 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9706 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9707 (set (match_operand:SI 3 "gpc_reg_operand" "")
9708 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9709 (set (match_operand:SI 4 "gpc_reg_operand" "")
9710 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9711 (set (match_operand:SI 5 "gpc_reg_operand" "")
9712 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9713 (set (match_operand:SI 6 "gpc_reg_operand" "")
9714 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9715 (set (match_operand:SI 7 "gpc_reg_operand" "")
9716 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9717 (set (match_operand:SI 8 "gpc_reg_operand" "")
9718 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9719 (set (match_operand:SI 9 "gpc_reg_operand" "")
9720 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9721 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9722 "*
9723 { return rs6000_output_load_multiple (operands); }"
9724 [(set_attr "type" "load")
9725 (set_attr "update" "yes")
9726 (set_attr "indexed" "yes")
9727 (set_attr "length" "32")])
9729 (define_insn "*ldmsi7"
9730 [(match_parallel 0 "load_multiple_operation"
9731 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9732 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9733 (set (match_operand:SI 3 "gpc_reg_operand" "")
9734 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9735 (set (match_operand:SI 4 "gpc_reg_operand" "")
9736 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9737 (set (match_operand:SI 5 "gpc_reg_operand" "")
9738 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9739 (set (match_operand:SI 6 "gpc_reg_operand" "")
9740 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9741 (set (match_operand:SI 7 "gpc_reg_operand" "")
9742 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9743 (set (match_operand:SI 8 "gpc_reg_operand" "")
9744 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9745 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9746 "*
9747 { return rs6000_output_load_multiple (operands); }"
9748 [(set_attr "type" "load")
9749 (set_attr "update" "yes")
9750 (set_attr "indexed" "yes")
9751 (set_attr "length" "32")])
9753 (define_insn "*ldmsi6"
9754 [(match_parallel 0 "load_multiple_operation"
9755 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9756 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9757 (set (match_operand:SI 3 "gpc_reg_operand" "")
9758 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9759 (set (match_operand:SI 4 "gpc_reg_operand" "")
9760 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9761 (set (match_operand:SI 5 "gpc_reg_operand" "")
9762 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9763 (set (match_operand:SI 6 "gpc_reg_operand" "")
9764 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9765 (set (match_operand:SI 7 "gpc_reg_operand" "")
9766 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9767 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9768 "*
9769 { return rs6000_output_load_multiple (operands); }"
9770 [(set_attr "type" "load")
9771 (set_attr "update" "yes")
9772 (set_attr "indexed" "yes")
9773 (set_attr "length" "32")])
9775 (define_insn "*ldmsi5"
9776 [(match_parallel 0 "load_multiple_operation"
9777 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9778 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9779 (set (match_operand:SI 3 "gpc_reg_operand" "")
9780 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9781 (set (match_operand:SI 4 "gpc_reg_operand" "")
9782 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9783 (set (match_operand:SI 5 "gpc_reg_operand" "")
9784 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9785 (set (match_operand:SI 6 "gpc_reg_operand" "")
9786 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9787 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9788 "*
9789 { return rs6000_output_load_multiple (operands); }"
9790 [(set_attr "type" "load")
9791 (set_attr "update" "yes")
9792 (set_attr "indexed" "yes")
9793 (set_attr "length" "32")])
9795 (define_insn "*ldmsi4"
9796 [(match_parallel 0 "load_multiple_operation"
9797 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9798 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9799 (set (match_operand:SI 3 "gpc_reg_operand" "")
9800 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9801 (set (match_operand:SI 4 "gpc_reg_operand" "")
9802 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9803 (set (match_operand:SI 5 "gpc_reg_operand" "")
9804 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9805 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9806 "*
9807 { return rs6000_output_load_multiple (operands); }"
9808 [(set_attr "type" "load")
9809 (set_attr "update" "yes")
9810 (set_attr "indexed" "yes")
9811 (set_attr "length" "32")])
9813 (define_insn "*ldmsi3"
9814 [(match_parallel 0 "load_multiple_operation"
9815 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9816 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9817 (set (match_operand:SI 3 "gpc_reg_operand" "")
9818 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9819 (set (match_operand:SI 4 "gpc_reg_operand" "")
9820 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9821 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9822 "*
9823 { return rs6000_output_load_multiple (operands); }"
9824 [(set_attr "type" "load")
9825 (set_attr "update" "yes")
9826 (set_attr "indexed" "yes")
9827 (set_attr "length" "32")])
9829 (define_expand "store_multiple"
9830 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9831 (match_operand:SI 1 "" ""))
9832 (clobber (scratch:SI))
9833 (use (match_operand:SI 2 "" ""))])]
9834 "TARGET_STRING && !TARGET_POWERPC64"
9835 "
9836 {
9837 int regno;
9838 int count;
9839 rtx to;
9840 rtx op0;
9841 int i;
9843 /* Support only storing a constant number of fixed-point registers to
9844 memory and only bother with this if more than two; the machine
9845 doesn't support more than eight. */
9846 if (GET_CODE (operands[2]) != CONST_INT
9847 || INTVAL (operands[2]) <= 2
9848 || INTVAL (operands[2]) > 8
9849 || GET_CODE (operands[0]) != MEM
9850 || GET_CODE (operands[1]) != REG
9851 || REGNO (operands[1]) >= 32)
9852 FAIL;
9854 count = INTVAL (operands[2]);
9855 regno = REGNO (operands[1]);
9857 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9858 to = force_reg (SImode, XEXP (operands[0], 0));
9859 op0 = replace_equiv_address (operands[0], to);
9861 XVECEXP (operands[3], 0, 0)
9862 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9863 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9864 gen_rtx_SCRATCH (SImode));
9866 for (i = 1; i < count; i++)
9867 XVECEXP (operands[3], 0, i + 1)
9868 = gen_rtx_SET (VOIDmode,
9869 adjust_address_nv (op0, SImode, i * 4),
9870 gen_rtx_REG (SImode, regno + i));
9871 }")
9873 (define_insn "*stmsi8"
9874 [(match_parallel 0 "store_multiple_operation"
9875 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9876 (match_operand:SI 2 "gpc_reg_operand" "r"))
9877 (clobber (match_scratch:SI 3 "=X"))
9878 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9879 (match_operand:SI 4 "gpc_reg_operand" "r"))
9880 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9881 (match_operand:SI 5 "gpc_reg_operand" "r"))
9882 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9883 (match_operand:SI 6 "gpc_reg_operand" "r"))
9884 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9885 (match_operand:SI 7 "gpc_reg_operand" "r"))
9886 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9887 (match_operand:SI 8 "gpc_reg_operand" "r"))
9888 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9889 (match_operand:SI 9 "gpc_reg_operand" "r"))
9890 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9891 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9892 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9893 "stswi %2,%1,%O0"
9894 [(set_attr "type" "store")
9895 (set_attr "update" "yes")
9896 (set_attr "indexed" "yes")
9897 (set_attr "cell_micro" "always")])
9899 (define_insn "*stmsi7"
9900 [(match_parallel 0 "store_multiple_operation"
9901 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9902 (match_operand:SI 2 "gpc_reg_operand" "r"))
9903 (clobber (match_scratch:SI 3 "=X"))
9904 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9905 (match_operand:SI 4 "gpc_reg_operand" "r"))
9906 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9907 (match_operand:SI 5 "gpc_reg_operand" "r"))
9908 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9909 (match_operand:SI 6 "gpc_reg_operand" "r"))
9910 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9911 (match_operand:SI 7 "gpc_reg_operand" "r"))
9912 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9913 (match_operand:SI 8 "gpc_reg_operand" "r"))
9914 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9915 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9916 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9917 "stswi %2,%1,%O0"
9918 [(set_attr "type" "store")
9919 (set_attr "update" "yes")
9920 (set_attr "indexed" "yes")
9921 (set_attr "cell_micro" "always")])
9923 (define_insn "*stmsi6"
9924 [(match_parallel 0 "store_multiple_operation"
9925 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9926 (match_operand:SI 2 "gpc_reg_operand" "r"))
9927 (clobber (match_scratch:SI 3 "=X"))
9928 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9929 (match_operand:SI 4 "gpc_reg_operand" "r"))
9930 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9931 (match_operand:SI 5 "gpc_reg_operand" "r"))
9932 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9933 (match_operand:SI 6 "gpc_reg_operand" "r"))
9934 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9935 (match_operand:SI 7 "gpc_reg_operand" "r"))
9936 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9937 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9938 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9939 "stswi %2,%1,%O0"
9940 [(set_attr "type" "store")
9941 (set_attr "update" "yes")
9942 (set_attr "indexed" "yes")
9943 (set_attr "cell_micro" "always")])
9945 (define_insn "*stmsi5"
9946 [(match_parallel 0 "store_multiple_operation"
9947 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9948 (match_operand:SI 2 "gpc_reg_operand" "r"))
9949 (clobber (match_scratch:SI 3 "=X"))
9950 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9951 (match_operand:SI 4 "gpc_reg_operand" "r"))
9952 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9953 (match_operand:SI 5 "gpc_reg_operand" "r"))
9954 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9955 (match_operand:SI 6 "gpc_reg_operand" "r"))
9956 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9957 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9958 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9959 "stswi %2,%1,%O0"
9960 [(set_attr "type" "store")
9961 (set_attr "update" "yes")
9962 (set_attr "indexed" "yes")
9963 (set_attr "cell_micro" "always")])
9965 (define_insn "*stmsi4"
9966 [(match_parallel 0 "store_multiple_operation"
9967 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9968 (match_operand:SI 2 "gpc_reg_operand" "r"))
9969 (clobber (match_scratch:SI 3 "=X"))
9970 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9971 (match_operand:SI 4 "gpc_reg_operand" "r"))
9972 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9973 (match_operand:SI 5 "gpc_reg_operand" "r"))
9974 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9975 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9976 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9977 "stswi %2,%1,%O0"
9978 [(set_attr "type" "store")
9979 (set_attr "update" "yes")
9980 (set_attr "indexed" "yes")
9981 (set_attr "cell_micro" "always")])
9983 (define_insn "*stmsi3"
9984 [(match_parallel 0 "store_multiple_operation"
9985 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9986 (match_operand:SI 2 "gpc_reg_operand" "r"))
9987 (clobber (match_scratch:SI 3 "=X"))
9988 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9989 (match_operand:SI 4 "gpc_reg_operand" "r"))
9990 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9991 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9992 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9993 "stswi %2,%1,%O0"
9994 [(set_attr "type" "store")
9995 (set_attr "update" "yes")
9996 (set_attr "indexed" "yes")
9997 (set_attr "cell_micro" "always")])
9998 \f
9999 (define_expand "setmemsi"
10000 [(parallel [(set (match_operand:BLK 0 "" "")
10001 (match_operand 2 "const_int_operand" ""))
10002 (use (match_operand:SI 1 "" ""))
10003 (use (match_operand:SI 3 "" ""))])]
10004 ""
10005 "
10006 {
10007 /* If value to set is not zero, use the library routine. */
10008 if (operands[2] != const0_rtx)
10009 FAIL;
10011 if (expand_block_clear (operands))
10012 DONE;
10013 else
10014 FAIL;
10015 }")
10017 ;; String/block move insn.
10018 ;; Argument 0 is the destination
10019 ;; Argument 1 is the source
10020 ;; Argument 2 is the length
10021 ;; Argument 3 is the alignment
10023 (define_expand "movmemsi"
10024 [(parallel [(set (match_operand:BLK 0 "" "")
10025 (match_operand:BLK 1 "" ""))
10026 (use (match_operand:SI 2 "" ""))
10027 (use (match_operand:SI 3 "" ""))])]
10028 ""
10029 "
10030 {
10031 if (expand_block_move (operands))
10032 DONE;
10033 else
10034 FAIL;
10035 }")
10037 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10038 ;; register allocator doesn't have a clue about allocating 8 word registers.
10039 ;; rD/rS = r5 is preferred, efficient form.
10040 (define_expand "movmemsi_8reg"
10041 [(parallel [(set (match_operand 0 "" "")
10042 (match_operand 1 "" ""))
10043 (use (match_operand 2 "" ""))
10044 (use (match_operand 3 "" ""))
10045 (clobber (reg:SI 5))
10046 (clobber (reg:SI 6))
10047 (clobber (reg:SI 7))
10048 (clobber (reg:SI 8))
10049 (clobber (reg:SI 9))
10050 (clobber (reg:SI 10))
10051 (clobber (reg:SI 11))
10052 (clobber (reg:SI 12))
10053 (clobber (match_scratch:SI 4 ""))])]
10054 "TARGET_STRING"
10055 "")
10057 (define_insn ""
10058 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10059 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10060 (use (match_operand:SI 2 "immediate_operand" "i"))
10061 (use (match_operand:SI 3 "immediate_operand" "i"))
10062 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10063 (clobber (reg:SI 6))
10064 (clobber (reg:SI 7))
10065 (clobber (reg:SI 8))
10066 (clobber (reg:SI 9))
10067 (clobber (reg:SI 10))
10068 (clobber (reg:SI 11))
10069 (clobber (reg:SI 12))
10070 (clobber (match_scratch:SI 5 "=X"))]
10071 "TARGET_STRING
10072 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10073 || INTVAL (operands[2]) == 0)
10074 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10075 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10076 && REGNO (operands[4]) == 5"
10077 "lswi %4,%1,%2\;stswi %4,%0,%2"
10078 [(set_attr "type" "store")
10079 (set_attr "update" "yes")
10080 (set_attr "indexed" "yes")
10081 (set_attr "cell_micro" "always")
10082 (set_attr "length" "8")])
10084 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10085 ;; register allocator doesn't have a clue about allocating 6 word registers.
10086 ;; rD/rS = r5 is preferred, efficient form.
10087 (define_expand "movmemsi_6reg"
10088 [(parallel [(set (match_operand 0 "" "")
10089 (match_operand 1 "" ""))
10090 (use (match_operand 2 "" ""))
10091 (use (match_operand 3 "" ""))
10092 (clobber (reg:SI 5))
10093 (clobber (reg:SI 6))
10094 (clobber (reg:SI 7))
10095 (clobber (reg:SI 8))
10096 (clobber (reg:SI 9))
10097 (clobber (reg:SI 10))
10098 (clobber (match_scratch:SI 4 ""))])]
10099 "TARGET_STRING"
10100 "")
10102 (define_insn ""
10103 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10104 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10105 (use (match_operand:SI 2 "immediate_operand" "i"))
10106 (use (match_operand:SI 3 "immediate_operand" "i"))
10107 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10108 (clobber (reg:SI 6))
10109 (clobber (reg:SI 7))
10110 (clobber (reg:SI 8))
10111 (clobber (reg:SI 9))
10112 (clobber (reg:SI 10))
10113 (clobber (match_scratch:SI 5 "=X"))]
10114 "TARGET_STRING
10115 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10116 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10117 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10118 && REGNO (operands[4]) == 5"
10119 "lswi %4,%1,%2\;stswi %4,%0,%2"
10120 [(set_attr "type" "store")
10121 (set_attr "update" "yes")
10122 (set_attr "indexed" "yes")
10123 (set_attr "cell_micro" "always")
10124 (set_attr "length" "8")])
10126 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10127 ;; problems with TImode.
10128 ;; rD/rS = r5 is preferred, efficient form.
10129 (define_expand "movmemsi_4reg"
10130 [(parallel [(set (match_operand 0 "" "")
10131 (match_operand 1 "" ""))
10132 (use (match_operand 2 "" ""))
10133 (use (match_operand 3 "" ""))
10134 (clobber (reg:SI 5))
10135 (clobber (reg:SI 6))
10136 (clobber (reg:SI 7))
10137 (clobber (reg:SI 8))
10138 (clobber (match_scratch:SI 4 ""))])]
10139 "TARGET_STRING"
10140 "")
10142 (define_insn ""
10143 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10144 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10145 (use (match_operand:SI 2 "immediate_operand" "i"))
10146 (use (match_operand:SI 3 "immediate_operand" "i"))
10147 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10148 (clobber (reg:SI 6))
10149 (clobber (reg:SI 7))
10150 (clobber (reg:SI 8))
10151 (clobber (match_scratch:SI 5 "=X"))]
10152 "TARGET_STRING
10153 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10154 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10155 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10156 && REGNO (operands[4]) == 5"
10157 "lswi %4,%1,%2\;stswi %4,%0,%2"
10158 [(set_attr "type" "store")
10159 (set_attr "update" "yes")
10160 (set_attr "indexed" "yes")
10161 (set_attr "cell_micro" "always")
10162 (set_attr "length" "8")])
10164 ;; Move up to 8 bytes at a time.
10165 (define_expand "movmemsi_2reg"
10166 [(parallel [(set (match_operand 0 "" "")
10167 (match_operand 1 "" ""))
10168 (use (match_operand 2 "" ""))
10169 (use (match_operand 3 "" ""))
10170 (clobber (match_scratch:DI 4 ""))
10171 (clobber (match_scratch:SI 5 ""))])]
10172 "TARGET_STRING && ! TARGET_POWERPC64"
10173 "")
10175 (define_insn ""
10176 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10177 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10178 (use (match_operand:SI 2 "immediate_operand" "i"))
10179 (use (match_operand:SI 3 "immediate_operand" "i"))
10180 (clobber (match_scratch:DI 4 "=&r"))
10181 (clobber (match_scratch:SI 5 "=X"))]
10182 "TARGET_STRING && ! TARGET_POWERPC64
10183 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10184 "lswi %4,%1,%2\;stswi %4,%0,%2"
10185 [(set_attr "type" "store")
10186 (set_attr "update" "yes")
10187 (set_attr "indexed" "yes")
10188 (set_attr "cell_micro" "always")
10189 (set_attr "length" "8")])
10191 ;; Move up to 4 bytes at a time.
10192 (define_expand "movmemsi_1reg"
10193 [(parallel [(set (match_operand 0 "" "")
10194 (match_operand 1 "" ""))
10195 (use (match_operand 2 "" ""))
10196 (use (match_operand 3 "" ""))
10197 (clobber (match_scratch:SI 4 ""))
10198 (clobber (match_scratch:SI 5 ""))])]
10199 "TARGET_STRING"
10200 "")
10202 (define_insn ""
10203 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10204 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10205 (use (match_operand:SI 2 "immediate_operand" "i"))
10206 (use (match_operand:SI 3 "immediate_operand" "i"))
10207 (clobber (match_scratch:SI 4 "=&r"))
10208 (clobber (match_scratch:SI 5 "=X"))]
10209 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10210 "lswi %4,%1,%2\;stswi %4,%0,%2"
10211 [(set_attr "type" "store")
10212 (set_attr "update" "yes")
10213 (set_attr "indexed" "yes")
10214 (set_attr "cell_micro" "always")
10215 (set_attr "length" "8")])
10216 \f
10217 ;; Define insns that do load or store with update. Some of these we can
10218 ;; get by using pre-decrement or pre-increment, but the hardware can also
10219 ;; do cases where the increment is not the size of the object.
10220 ;;
10221 ;; In all these cases, we use operands 0 and 1 for the register being
10222 ;; incremented because those are the operands that local-alloc will
10223 ;; tie and these are the pair most likely to be tieable (and the ones
10224 ;; that will benefit the most).
10226 (define_insn "*movdi_update1"
10227 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10228 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10229 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10230 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10231 (plus:DI (match_dup 1) (match_dup 2)))]
10232 "TARGET_POWERPC64 && TARGET_UPDATE
10233 && (!avoiding_indexed_address_p (DImode)
10234 || !gpc_reg_operand (operands[2], DImode))"
10235 "@
10236 ldux %3,%0,%2
10237 ldu %3,%2(%0)"
10238 [(set_attr "type" "load")
10239 (set_attr "update" "yes")
10240 (set_attr "indexed" "yes,no")])
10242 (define_insn "movdi_<mode>_update"
10243 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10244 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10245 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10246 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10247 (plus:P (match_dup 1) (match_dup 2)))]
10248 "TARGET_POWERPC64 && TARGET_UPDATE
10249 && (!avoiding_indexed_address_p (Pmode)
10250 || !gpc_reg_operand (operands[2], Pmode)
10251 || (REG_P (operands[0])
10252 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10253 "@
10254 stdux %3,%0,%2
10255 stdu %3,%2(%0)"
10256 [(set_attr "type" "store")
10257 (set_attr "update" "yes")
10258 (set_attr "indexed" "yes,no")])
10260 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10261 ;; needed for stack allocation, even if the user passes -mno-update.
10262 (define_insn "movdi_<mode>_update_stack"
10263 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10264 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10265 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10266 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10267 (plus:P (match_dup 1) (match_dup 2)))]
10268 "TARGET_POWERPC64"
10269 "@
10270 stdux %3,%0,%2
10271 stdu %3,%2(%0)"
10272 [(set_attr "type" "store")
10273 (set_attr "update" "yes")
10274 (set_attr "indexed" "yes,no")])
10276 (define_insn "*movsi_update1"
10277 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10278 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10279 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10280 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10281 (plus:SI (match_dup 1) (match_dup 2)))]
10282 "TARGET_UPDATE
10283 && (!avoiding_indexed_address_p (SImode)
10284 || !gpc_reg_operand (operands[2], SImode))"
10285 "@
10286 lwzux %3,%0,%2
10287 lwzu %3,%2(%0)"
10288 [(set_attr "type" "load")
10289 (set_attr "update" "yes")
10290 (set_attr "indexed" "yes,no")])
10292 (define_insn "*movsi_update2"
10293 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10294 (sign_extend:DI
10295 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10296 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10297 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10298 (plus:DI (match_dup 1) (match_dup 2)))]
10299 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10300 && !avoiding_indexed_address_p (DImode)"
10301 "lwaux %3,%0,%2"
10302 [(set_attr "type" "load")
10303 (set_attr "sign_extend" "yes")
10304 (set_attr "update" "yes")
10305 (set_attr "indexed" "yes")])
10307 (define_insn "movsi_update"
10308 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10309 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10310 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10311 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10312 (plus:SI (match_dup 1) (match_dup 2)))]
10313 "TARGET_UPDATE
10314 && (!avoiding_indexed_address_p (SImode)
10315 || !gpc_reg_operand (operands[2], SImode)
10316 || (REG_P (operands[0])
10317 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10318 "@
10319 stwux %3,%0,%2
10320 stwu %3,%2(%0)"
10321 [(set_attr "type" "store")
10322 (set_attr "update" "yes")
10323 (set_attr "indexed" "yes,no")])
10325 ;; This is an unconditional pattern; needed for stack allocation, even
10326 ;; if the user passes -mno-update.
10327 (define_insn "movsi_update_stack"
10328 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10329 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10330 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10331 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10332 (plus:SI (match_dup 1) (match_dup 2)))]
10333 ""
10334 "@
10335 stwux %3,%0,%2
10336 stwu %3,%2(%0)"
10337 [(set_attr "type" "store")
10338 (set_attr "update" "yes")
10339 (set_attr "indexed" "yes,no")])
10341 (define_insn "*movhi_update1"
10342 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10343 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10344 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10345 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10346 (plus:SI (match_dup 1) (match_dup 2)))]
10347 "TARGET_UPDATE
10348 && (!avoiding_indexed_address_p (SImode)
10349 || !gpc_reg_operand (operands[2], SImode))"
10350 "@
10351 lhzux %3,%0,%2
10352 lhzu %3,%2(%0)"
10353 [(set_attr "type" "load")
10354 (set_attr "update" "yes")
10355 (set_attr "indexed" "yes,no")])
10357 (define_insn "*movhi_update2"
10358 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10359 (zero_extend:SI
10360 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10361 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10362 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10363 (plus:SI (match_dup 1) (match_dup 2)))]
10364 "TARGET_UPDATE
10365 && (!avoiding_indexed_address_p (SImode)
10366 || !gpc_reg_operand (operands[2], SImode))"
10367 "@
10368 lhzux %3,%0,%2
10369 lhzu %3,%2(%0)"
10370 [(set_attr "type" "load")
10371 (set_attr "update" "yes")
10372 (set_attr "indexed" "yes,no")])
10374 (define_insn "*movhi_update3"
10375 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10376 (sign_extend:SI
10377 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10378 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10379 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10380 (plus:SI (match_dup 1) (match_dup 2)))]
10381 "TARGET_UPDATE && rs6000_gen_cell_microcode
10382 && (!avoiding_indexed_address_p (SImode)
10383 || !gpc_reg_operand (operands[2], SImode))"
10384 "@
10385 lhaux %3,%0,%2
10386 lhau %3,%2(%0)"
10387 [(set_attr "type" "load")
10388 (set_attr "sign_extend" "yes")
10389 (set_attr "update" "yes")
10390 (set_attr "indexed" "yes,no")])
10392 (define_insn "*movhi_update4"
10393 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10394 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10395 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10396 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10397 (plus:SI (match_dup 1) (match_dup 2)))]
10398 "TARGET_UPDATE
10399 && (!avoiding_indexed_address_p (SImode)
10400 || !gpc_reg_operand (operands[2], SImode))"
10401 "@
10402 sthux %3,%0,%2
10403 sthu %3,%2(%0)"
10404 [(set_attr "type" "store")
10405 (set_attr "update" "yes")
10406 (set_attr "indexed" "yes,no")])
10408 (define_insn "*movqi_update1"
10409 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10410 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10411 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10412 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10413 (plus:SI (match_dup 1) (match_dup 2)))]
10414 "TARGET_UPDATE
10415 && (!avoiding_indexed_address_p (SImode)
10416 || !gpc_reg_operand (operands[2], SImode))"
10417 "@
10418 lbzux %3,%0,%2
10419 lbzu %3,%2(%0)"
10420 [(set_attr "type" "load")
10421 (set_attr "update" "yes")
10422 (set_attr "indexed" "yes,no")])
10424 (define_insn "*movqi_update2"
10425 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10426 (zero_extend:SI
10427 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10428 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10429 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10430 (plus:SI (match_dup 1) (match_dup 2)))]
10431 "TARGET_UPDATE
10432 && (!avoiding_indexed_address_p (SImode)
10433 || !gpc_reg_operand (operands[2], SImode))"
10434 "@
10435 lbzux %3,%0,%2
10436 lbzu %3,%2(%0)"
10437 [(set_attr "type" "load")
10438 (set_attr "update" "yes")
10439 (set_attr "indexed" "yes,no")])
10441 (define_insn "*movqi_update3"
10442 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10443 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10444 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10445 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10446 (plus:SI (match_dup 1) (match_dup 2)))]
10447 "TARGET_UPDATE
10448 && (!avoiding_indexed_address_p (SImode)
10449 || !gpc_reg_operand (operands[2], SImode))"
10450 "@
10451 stbux %3,%0,%2
10452 stbu %3,%2(%0)"
10453 [(set_attr "type" "store")
10454 (set_attr "update" "yes")
10455 (set_attr "indexed" "yes,no")])
10457 (define_insn "*movsf_update1"
10458 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10459 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10460 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10461 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10462 (plus:SI (match_dup 1) (match_dup 2)))]
10463 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10464 && (!avoiding_indexed_address_p (SImode)
10465 || !gpc_reg_operand (operands[2], SImode))"
10466 "@
10467 lfsux %3,%0,%2
10468 lfsu %3,%2(%0)"
10469 [(set_attr "type" "fpload")
10470 (set_attr "update" "yes")
10471 (set_attr "indexed" "yes,no")])
10473 (define_insn "*movsf_update2"
10474 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10475 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10476 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10477 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10478 (plus:SI (match_dup 1) (match_dup 2)))]
10479 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10480 && (!avoiding_indexed_address_p (SImode)
10481 || !gpc_reg_operand (operands[2], SImode))"
10482 "@
10483 stfsux %3,%0,%2
10484 stfsu %3,%2(%0)"
10485 [(set_attr "type" "fpstore")
10486 (set_attr "update" "yes")
10487 (set_attr "indexed" "yes,no")])
10489 (define_insn "*movsf_update3"
10490 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10491 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10492 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10493 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10494 (plus:SI (match_dup 1) (match_dup 2)))]
10495 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10496 && (!avoiding_indexed_address_p (SImode)
10497 || !gpc_reg_operand (operands[2], SImode))"
10498 "@
10499 lwzux %3,%0,%2
10500 lwzu %3,%2(%0)"
10501 [(set_attr "type" "load")
10502 (set_attr "update" "yes")
10503 (set_attr "indexed" "yes,no")])
10505 (define_insn "*movsf_update4"
10506 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10507 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10508 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10509 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10510 (plus:SI (match_dup 1) (match_dup 2)))]
10511 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10512 && (!avoiding_indexed_address_p (SImode)
10513 || !gpc_reg_operand (operands[2], SImode))"
10514 "@
10515 stwux %3,%0,%2
10516 stwu %3,%2(%0)"
10517 [(set_attr "type" "store")
10518 (set_attr "update" "yes")
10519 (set_attr "indexed" "yes,no")])
10521 (define_insn "*movdf_update1"
10522 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10523 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10524 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10525 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10526 (plus:SI (match_dup 1) (match_dup 2)))]
10527 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10528 && (!avoiding_indexed_address_p (SImode)
10529 || !gpc_reg_operand (operands[2], SImode))"
10530 "@
10531 lfdux %3,%0,%2
10532 lfdu %3,%2(%0)"
10533 [(set_attr "type" "fpload")
10534 (set_attr "update" "yes")
10535 (set_attr "indexed" "yes,no")])
10537 (define_insn "*movdf_update2"
10538 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10539 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10540 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10541 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10542 (plus:SI (match_dup 1) (match_dup 2)))]
10543 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10544 && (!avoiding_indexed_address_p (SImode)
10545 || !gpc_reg_operand (operands[2], SImode))"
10546 "@
10547 stfdux %3,%0,%2
10548 stfdu %3,%2(%0)"
10549 [(set_attr "type" "fpstore")
10550 (set_attr "update" "yes")
10551 (set_attr "indexed" "yes,no")])
10554 ;; After inserting conditional returns we can sometimes have
10555 ;; unnecessary register moves. Unfortunately we cannot have a
10556 ;; modeless peephole here, because some single SImode sets have early
10557 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10558 ;; sequences, using get_attr_length here will smash the operands
10559 ;; array. Neither is there an early_cobbler_p predicate.
10560 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10561 (define_peephole2
10562 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10563 (match_operand:DF 1 "any_operand" ""))
10564 (set (match_operand:DF 2 "gpc_reg_operand" "")
10565 (match_dup 0))]
10566 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10567 && peep2_reg_dead_p (2, operands[0])"
10568 [(set (match_dup 2) (match_dup 1))])
10570 (define_peephole2
10571 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10572 (match_operand:SF 1 "any_operand" ""))
10573 (set (match_operand:SF 2 "gpc_reg_operand" "")
10574 (match_dup 0))]
10575 "peep2_reg_dead_p (2, operands[0])"
10576 [(set (match_dup 2) (match_dup 1))])
10578 \f
10579 ;; TLS support.
10581 ;; Mode attributes for different ABIs.
10582 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10583 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10584 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10585 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10587 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10588 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10589 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10590 (match_operand 4 "" "g")))
10591 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10592 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10593 UNSPEC_TLSGD)
10594 (clobber (reg:SI LR_REGNO))]
10595 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10596 {
10597 if (TARGET_CMODEL != CMODEL_SMALL)
10598 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
10599 "bl %z3\;nop";
10600 else
10601 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
10602 }
10603 "&& TARGET_TLS_MARKERS"
10604 [(set (match_dup 0)
10605 (unspec:TLSmode [(match_dup 1)
10606 (match_dup 2)]
10607 UNSPEC_TLSGD))
10608 (parallel [(set (match_dup 0)
10609 (call (mem:TLSmode (match_dup 3))
10610 (match_dup 4)))
10611 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10612 (clobber (reg:SI LR_REGNO))])]
10613 ""
10614 [(set_attr "type" "two")
10615 (set (attr "length")
10616 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10617 (const_int 16)
10618 (const_int 12)))])
10620 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10621 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10622 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10623 (match_operand 4 "" "g")))
10624 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10625 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10626 UNSPEC_TLSGD)
10627 (clobber (reg:SI LR_REGNO))]
10628 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10629 {
10630 if (flag_pic)
10631 {
10632 if (TARGET_SECURE_PLT && flag_pic == 2)
10633 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10634 else
10635 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10636 }
10637 else
10638 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10639 }
10640 "&& TARGET_TLS_MARKERS"
10641 [(set (match_dup 0)
10642 (unspec:TLSmode [(match_dup 1)
10643 (match_dup 2)]
10644 UNSPEC_TLSGD))
10645 (parallel [(set (match_dup 0)
10646 (call (mem:TLSmode (match_dup 3))
10647 (match_dup 4)))
10648 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10649 (clobber (reg:SI LR_REGNO))])]
10650 ""
10651 [(set_attr "type" "two")
10652 (set_attr "length" "8")])
10654 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10655 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10656 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10657 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10658 UNSPEC_TLSGD))]
10659 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10660 "addi %0,%1,%2@got@tlsgd"
10661 "&& TARGET_CMODEL != CMODEL_SMALL"
10662 [(set (match_dup 3)
10663 (high:TLSmode
10664 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10665 (set (match_dup 0)
10666 (lo_sum:TLSmode (match_dup 3)
10667 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
10668 "
10669 {
10670 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10671 }"
10672 [(set (attr "length")
10673 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10674 (const_int 8)
10675 (const_int 4)))])
10677 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10678 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10679 (high:TLSmode
10680 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10681 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10682 UNSPEC_TLSGD)))]
10683 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10684 "addis %0,%1,%2@got@tlsgd@ha"
10685 [(set_attr "length" "4")])
10687 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10688 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10689 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10690 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10691 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10692 UNSPEC_TLSGD)))]
10693 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10694 "addi %0,%1,%2@got@tlsgd@l"
10695 [(set_attr "length" "4")])
10697 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10698 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10699 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10700 (match_operand 2 "" "g")))
10701 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10702 UNSPEC_TLSGD)
10703 (clobber (reg:SI LR_REGNO))]
10704 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10705 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10706 "bl %z1(%3@tlsgd)\;nop"
10707 [(set_attr "type" "branch")
10708 (set_attr "length" "8")])
10710 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10711 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10712 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10713 (match_operand 2 "" "g")))
10714 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10715 UNSPEC_TLSGD)
10716 (clobber (reg:SI LR_REGNO))]
10717 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10718 {
10719 if (flag_pic)
10720 {
10721 if (TARGET_SECURE_PLT && flag_pic == 2)
10722 return "bl %z1+32768(%3@tlsgd)@plt";
10723 return "bl %z1(%3@tlsgd)@plt";
10724 }
10725 return "bl %z1(%3@tlsgd)";
10726 }
10727 [(set_attr "type" "branch")
10728 (set_attr "length" "4")])
10730 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10731 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10732 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10733 (match_operand 3 "" "g")))
10734 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10735 UNSPEC_TLSLD)
10736 (clobber (reg:SI LR_REGNO))]
10737 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10738 {
10739 if (TARGET_CMODEL != CMODEL_SMALL)
10740 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
10741 "bl %z2\;nop";
10742 else
10743 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
10744 }
10745 "&& TARGET_TLS_MARKERS"
10746 [(set (match_dup 0)
10747 (unspec:TLSmode [(match_dup 1)]
10748 UNSPEC_TLSLD))
10749 (parallel [(set (match_dup 0)
10750 (call (mem:TLSmode (match_dup 2))
10751 (match_dup 3)))
10752 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10753 (clobber (reg:SI LR_REGNO))])]
10754 ""
10755 [(set_attr "type" "two")
10756 (set (attr "length")
10757 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10758 (const_int 16)
10759 (const_int 12)))])
10761 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10762 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10763 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10764 (match_operand 3 "" "g")))
10765 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10766 UNSPEC_TLSLD)
10767 (clobber (reg:SI LR_REGNO))]
10768 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10769 {
10770 if (flag_pic)
10771 {
10772 if (TARGET_SECURE_PLT && flag_pic == 2)
10773 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10774 else
10775 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10776 }
10777 else
10778 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10779 }
10780 "&& TARGET_TLS_MARKERS"
10781 [(set (match_dup 0)
10782 (unspec:TLSmode [(match_dup 1)]
10783 UNSPEC_TLSLD))
10784 (parallel [(set (match_dup 0)
10785 (call (mem:TLSmode (match_dup 2))
10786 (match_dup 3)))
10787 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10788 (clobber (reg:SI LR_REGNO))])]
10789 ""
10790 [(set_attr "length" "8")])
10792 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10793 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10794 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10795 UNSPEC_TLSLD))]
10796 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10797 "addi %0,%1,%&@got@tlsld"
10798 "&& TARGET_CMODEL != CMODEL_SMALL"
10799 [(set (match_dup 2)
10800 (high:TLSmode
10801 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10802 (set (match_dup 0)
10803 (lo_sum:TLSmode (match_dup 2)
10804 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
10805 "
10806 {
10807 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10808 }"
10809 [(set (attr "length")
10810 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10811 (const_int 8)
10812 (const_int 4)))])
10814 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10815 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10816 (high:TLSmode
10817 (unspec:TLSmode [(const_int 0)
10818 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10819 UNSPEC_TLSLD)))]
10820 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10821 "addis %0,%1,%&@got@tlsld@ha"
10822 [(set_attr "length" "4")])
10824 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10825 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10826 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10827 (unspec:TLSmode [(const_int 0)
10828 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
10829 UNSPEC_TLSLD)))]
10830 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10831 "addi %0,%1,%&@got@tlsld@l"
10832 [(set_attr "length" "4")])
10834 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10835 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10836 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10837 (match_operand 2 "" "g")))
10838 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10839 (clobber (reg:SI LR_REGNO))]
10840 "HAVE_AS_TLS && TARGET_TLS_MARKERS
10841 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
10842 "bl %z1(%&@tlsld)\;nop"
10843 [(set_attr "type" "branch")
10844 (set_attr "length" "8")])
10846 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10847 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10848 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10849 (match_operand 2 "" "g")))
10850 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10851 (clobber (reg:SI LR_REGNO))]
10852 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10853 {
10854 if (flag_pic)
10855 {
10856 if (TARGET_SECURE_PLT && flag_pic == 2)
10857 return "bl %z1+32768(%&@tlsld)@plt";
10858 return "bl %z1(%&@tlsld)@plt";
10859 }
10860 return "bl %z1(%&@tlsld)";
10861 }
10862 [(set_attr "type" "branch")
10863 (set_attr "length" "4")])
10865 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10866 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10867 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10868 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10869 UNSPEC_TLSDTPREL))]
10870 "HAVE_AS_TLS"
10871 "addi %0,%1,%2@dtprel")
10873 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10874 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10875 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10876 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10877 UNSPEC_TLSDTPRELHA))]
10878 "HAVE_AS_TLS"
10879 "addis %0,%1,%2@dtprel@ha")
10881 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10882 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10883 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10884 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10885 UNSPEC_TLSDTPRELLO))]
10886 "HAVE_AS_TLS"
10887 "addi %0,%1,%2@dtprel@l")
10889 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10890 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10891 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10892 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10893 UNSPEC_TLSGOTDTPREL))]
10894 "HAVE_AS_TLS"
10895 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10896 "&& TARGET_CMODEL != CMODEL_SMALL"
10897 [(set (match_dup 3)
10898 (high:TLSmode
10899 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10900 (set (match_dup 0)
10901 (lo_sum:TLSmode (match_dup 3)
10902 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10903 "
10904 {
10905 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10906 }"
10907 [(set (attr "length")
10908 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10909 (const_int 8)
10910 (const_int 4)))])
10912 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10913 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10914 (high:TLSmode
10915 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10916 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10917 UNSPEC_TLSGOTDTPREL)))]
10918 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10919 "addis %0,%1,%2@got@dtprel@ha"
10920 [(set_attr "length" "4")])
10922 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10923 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10924 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10925 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10926 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10927 UNSPEC_TLSGOTDTPREL)))]
10928 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10929 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10930 [(set_attr "length" "4")])
10932 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10933 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10934 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10935 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10936 UNSPEC_TLSTPREL))]
10937 "HAVE_AS_TLS"
10938 "addi %0,%1,%2@tprel")
10940 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10941 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10942 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10943 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10944 UNSPEC_TLSTPRELHA))]
10945 "HAVE_AS_TLS"
10946 "addis %0,%1,%2@tprel@ha")
10948 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10949 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10950 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10951 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10952 UNSPEC_TLSTPRELLO))]
10953 "HAVE_AS_TLS"
10954 "addi %0,%1,%2@tprel@l")
10956 ;; "b" output constraint here and on tls_tls input to support linker tls
10957 ;; optimization. The linker may edit the instructions emitted by a
10958 ;; tls_got_tprel/tls_tls pair to addis,addi.
10959 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10960 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10961 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10962 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10963 UNSPEC_TLSGOTTPREL))]
10964 "HAVE_AS_TLS"
10965 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10966 "&& TARGET_CMODEL != CMODEL_SMALL"
10967 [(set (match_dup 3)
10968 (high:TLSmode
10969 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10970 (set (match_dup 0)
10971 (lo_sum:TLSmode (match_dup 3)
10972 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10973 "
10974 {
10975 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10976 }"
10977 [(set (attr "length")
10978 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10979 (const_int 8)
10980 (const_int 4)))])
10982 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10983 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10984 (high:TLSmode
10985 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10986 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10987 UNSPEC_TLSGOTTPREL)))]
10988 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10989 "addis %0,%1,%2@got@tprel@ha"
10990 [(set_attr "length" "4")])
10992 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10993 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10994 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10995 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
10996 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10997 UNSPEC_TLSGOTTPREL)))]
10998 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10999 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11000 [(set_attr "length" "4")])
11002 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11003 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11004 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11005 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11006 UNSPEC_TLSTLS))]
11007 "TARGET_ELF && HAVE_AS_TLS"
11008 "add %0,%1,%2@tls")
11010 (define_expand "tls_get_tpointer"
11011 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11012 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11013 "TARGET_XCOFF && HAVE_AS_TLS"
11014 "
11015 {
11016 emit_insn (gen_tls_get_tpointer_internal ());
11017 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11018 DONE;
11019 }")
11021 (define_insn "tls_get_tpointer_internal"
11022 [(set (reg:SI 3)
11023 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11024 (clobber (reg:SI LR_REGNO))]
11025 "TARGET_XCOFF && HAVE_AS_TLS"
11026 "bla __get_tpointer")
11028 (define_expand "tls_get_addr<mode>"
11029 [(set (match_operand:P 0 "gpc_reg_operand" "")
11030 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11031 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11032 "TARGET_XCOFF && HAVE_AS_TLS"
11033 "
11034 {
11035 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11036 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11037 emit_insn (gen_tls_get_addr_internal<mode> ());
11038 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11039 DONE;
11040 }")
11042 (define_insn "tls_get_addr_internal<mode>"
11043 [(set (reg:P 3)
11044 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11045 (clobber (reg:P 0))
11046 (clobber (reg:P 4))
11047 (clobber (reg:P 5))
11048 (clobber (reg:P 11))
11049 (clobber (reg:CC CR0_REGNO))
11050 (clobber (reg:P LR_REGNO))]
11051 "TARGET_XCOFF && HAVE_AS_TLS"
11052 "bla __tls_get_addr")
11053 \f
11054 ;; Next come insns related to the calling sequence.
11055 ;;
11056 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11057 ;; We move the back-chain and decrement the stack pointer.
11059 (define_expand "allocate_stack"
11060 [(set (match_operand 0 "gpc_reg_operand" "")
11061 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11062 (set (reg 1)
11063 (minus (reg 1) (match_dup 1)))]
11064 ""
11065 "
11066 { rtx chain = gen_reg_rtx (Pmode);
11067 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11068 rtx neg_op0;
11069 rtx insn, par, set, mem;
11071 emit_move_insn (chain, stack_bot);
11073 /* Check stack bounds if necessary. */
11074 if (crtl->limit_stack)
11075 {
11076 rtx available;
11077 available = expand_binop (Pmode, sub_optab,
11078 stack_pointer_rtx, stack_limit_rtx,
11079 NULL_RTX, 1, OPTAB_WIDEN);
11080 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11081 }
11083 if (GET_CODE (operands[1]) != CONST_INT
11084 || INTVAL (operands[1]) < -32767
11085 || INTVAL (operands[1]) > 32768)
11086 {
11087 neg_op0 = gen_reg_rtx (Pmode);
11088 if (TARGET_32BIT)
11089 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11090 else
11091 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11092 }
11093 else
11094 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11096 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11097 : gen_movdi_di_update_stack))
11098 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11099 chain));
11100 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11101 it now and set the alias set/attributes. The above gen_*_update
11102 calls will generate a PARALLEL with the MEM set being the first
11103 operation. */
11104 par = PATTERN (insn);
11105 gcc_assert (GET_CODE (par) == PARALLEL);
11106 set = XVECEXP (par, 0, 0);
11107 gcc_assert (GET_CODE (set) == SET);
11108 mem = SET_DEST (set);
11109 gcc_assert (MEM_P (mem));
11110 MEM_NOTRAP_P (mem) = 1;
11111 set_mem_alias_set (mem, get_frame_alias_set ());
11113 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11114 DONE;
11115 }")
11117 ;; These patterns say how to save and restore the stack pointer. We need not
11118 ;; save the stack pointer at function level since we are careful to
11119 ;; preserve the backchain. At block level, we have to restore the backchain
11120 ;; when we restore the stack pointer.
11121 ;;
11122 ;; For nonlocal gotos, we must save both the stack pointer and its
11123 ;; backchain and restore both. Note that in the nonlocal case, the
11124 ;; save area is a memory location.
11126 (define_expand "save_stack_function"
11127 [(match_operand 0 "any_operand" "")
11128 (match_operand 1 "any_operand" "")]
11129 ""
11130 "DONE;")
11132 (define_expand "restore_stack_function"
11133 [(match_operand 0 "any_operand" "")
11134 (match_operand 1 "any_operand" "")]
11135 ""
11136 "DONE;")
11138 ;; Adjust stack pointer (op0) to a new value (op1).
11139 ;; First copy old stack backchain to new location, and ensure that the
11140 ;; scheduler won't reorder the sp assignment before the backchain write.
11141 (define_expand "restore_stack_block"
11142 [(set (match_dup 2) (match_dup 3))
11143 (set (match_dup 4) (match_dup 2))
11144 (match_dup 5)
11145 (set (match_operand 0 "register_operand" "")
11146 (match_operand 1 "register_operand" ""))]
11147 ""
11148 "
11149 {
11150 rtvec p;
11152 operands[1] = force_reg (Pmode, operands[1]);
11153 operands[2] = gen_reg_rtx (Pmode);
11154 operands[3] = gen_frame_mem (Pmode, operands[0]);
11155 operands[4] = gen_frame_mem (Pmode, operands[1]);
11156 p = rtvec_alloc (1);
11157 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11158 gen_frame_mem (BLKmode, operands[0]),
11159 const0_rtx);
11160 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11161 }")
11163 (define_expand "save_stack_nonlocal"
11164 [(set (match_dup 3) (match_dup 4))
11165 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11166 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11167 ""
11168 "
11169 {
11170 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11172 /* Copy the backchain to the first word, sp to the second. */
11173 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11174 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11175 operands[3] = gen_reg_rtx (Pmode);
11176 operands[4] = gen_frame_mem (Pmode, operands[1]);
11177 }")
11179 (define_expand "restore_stack_nonlocal"
11180 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11181 (set (match_dup 3) (match_dup 4))
11182 (set (match_dup 5) (match_dup 2))
11183 (match_dup 6)
11184 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11185 ""
11186 "
11187 {
11188 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11189 rtvec p;
11191 /* Restore the backchain from the first word, sp from the second. */
11192 operands[2] = gen_reg_rtx (Pmode);
11193 operands[3] = gen_reg_rtx (Pmode);
11194 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11195 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11196 operands[5] = gen_frame_mem (Pmode, operands[3]);
11197 p = rtvec_alloc (1);
11198 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11199 gen_frame_mem (BLKmode, operands[0]),
11200 const0_rtx);
11201 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11202 }")
11203 \f
11204 ;; TOC register handling.
11206 ;; Code to initialize the TOC register...
11208 (define_insn "load_toc_aix_si"
11209 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11210 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11211 (use (reg:SI 2))])]
11212 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
11213 "*
11214 {
11215 char buf[30];
11216 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11217 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11218 operands[2] = gen_rtx_REG (Pmode, 2);
11219 return \"lwz %0,%1(%2)\";
11220 }"
11221 [(set_attr "type" "load")
11222 (set_attr "update" "no")
11223 (set_attr "indexed" "no")])
11225 (define_insn "load_toc_aix_di"
11226 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11227 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11228 (use (reg:DI 2))])]
11229 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
11230 "*
11231 {
11232 char buf[30];
11233 #ifdef TARGET_RELOCATABLE
11234 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11235 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11236 #else
11237 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11238 #endif
11239 if (TARGET_ELF)
11240 strcat (buf, \"@toc\");
11241 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11242 operands[2] = gen_rtx_REG (Pmode, 2);
11243 return \"ld %0,%1(%2)\";
11244 }"
11245 [(set_attr "type" "load")
11246 (set_attr "update" "no")
11247 (set_attr "indexed" "no")])
11249 (define_insn "load_toc_v4_pic_si"
11250 [(set (reg:SI LR_REGNO)
11251 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11252 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11253 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11254 [(set_attr "type" "branch")
11255 (set_attr "length" "4")])
11257 (define_expand "load_toc_v4_PIC_1"
11258 [(parallel [(set (reg:SI LR_REGNO)
11259 (match_operand:SI 0 "immediate_operand" "s"))
11260 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11261 "TARGET_ELF && DEFAULT_ABI == ABI_V4
11262 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11263 "")
11265 (define_insn "load_toc_v4_PIC_1_normal"
11266 [(set (reg:SI LR_REGNO)
11267 (match_operand:SI 0 "immediate_operand" "s"))
11268 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11269 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11270 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11271 "bcl 20,31,%0\\n%0:"
11272 [(set_attr "type" "branch")
11273 (set_attr "length" "4")])
11275 (define_insn "load_toc_v4_PIC_1_476"
11276 [(set (reg:SI LR_REGNO)
11277 (match_operand:SI 0 "immediate_operand" "s"))
11278 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11279 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11280 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11281 "*
11282 {
11283 char name[32];
11284 static char templ[32];
11286 get_ppc476_thunk_name (name);
11287 sprintf (templ, \"bl %s\\n%%0:\", name);
11288 return templ;
11289 }"
11290 [(set_attr "type" "branch")
11291 (set_attr "length" "4")])
11293 (define_expand "load_toc_v4_PIC_1b"
11294 [(parallel [(set (reg:SI LR_REGNO)
11295 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11296 (label_ref (match_operand 1 "" ""))]
11297 UNSPEC_TOCPTR))
11298 (match_dup 1)])]
11299 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11300 "")
11302 (define_insn "load_toc_v4_PIC_1b_normal"
11303 [(set (reg:SI LR_REGNO)
11304 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11305 (label_ref (match_operand 1 "" ""))]
11306 UNSPEC_TOCPTR))
11307 (match_dup 1)]
11308 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11309 "bcl 20,31,$+8\;.long %0-$"
11310 [(set_attr "type" "branch")
11311 (set_attr "length" "8")])
11313 (define_insn "load_toc_v4_PIC_1b_476"
11314 [(set (reg:SI LR_REGNO)
11315 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11316 (label_ref (match_operand 1 "" ""))]
11317 UNSPEC_TOCPTR))
11318 (match_dup 1)]
11319 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11320 "*
11321 {
11322 char name[32];
11323 static char templ[32];
11325 get_ppc476_thunk_name (name);
11326 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11327 return templ;
11328 }"
11329 [(set_attr "type" "branch")
11330 (set_attr "length" "16")])
11332 (define_insn "load_toc_v4_PIC_2"
11333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11334 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11335 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11336 (match_operand:SI 3 "immediate_operand" "s")))))]
11337 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11338 "lwz %0,%2-%3(%1)"
11339 [(set_attr "type" "load")])
11341 (define_insn "load_toc_v4_PIC_3b"
11342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11343 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11344 (high:SI
11345 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11346 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11347 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11348 "addis %0,%1,%2-%3@ha")
11350 (define_insn "load_toc_v4_PIC_3c"
11351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11352 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11353 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11354 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11355 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11356 "addi %0,%1,%2-%3@l")
11358 ;; If the TOC is shared over a translation unit, as happens with all
11359 ;; the kinds of PIC that we support, we need to restore the TOC
11360 ;; pointer only when jumping over units of translation.
11361 ;; On Darwin, we need to reload the picbase.
11363 (define_expand "builtin_setjmp_receiver"
11364 [(use (label_ref (match_operand 0 "" "")))]
11365 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11366 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11367 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11368 "
11369 {
11370 #if TARGET_MACHO
11371 if (DEFAULT_ABI == ABI_DARWIN)
11372 {
11373 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11374 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11375 rtx tmplabrtx;
11376 char tmplab[20];
11378 crtl->uses_pic_offset_table = 1;
11379 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11380 CODE_LABEL_NUMBER (operands[0]));
11381 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11383 emit_insn (gen_load_macho_picbase (tmplabrtx));
11384 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11385 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11386 }
11387 else
11388 #endif
11389 rs6000_emit_load_toc_table (FALSE);
11390 DONE;
11391 }")
11393 ;; Largetoc support
11394 (define_insn "*largetoc_high"
11395 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11396 (high:DI
11397 (unspec [(match_operand:DI 1 "" "")
11398 (match_operand:DI 2 "gpc_reg_operand" "b")]
11399 UNSPEC_TOCREL)))]
11400 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11401 "addis %0,%2,%1@toc@ha")
11403 (define_insn "*largetoc_high_aix<mode>"
11404 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11405 (high:P
11406 (unspec [(match_operand:P 1 "" "")
11407 (match_operand:P 2 "gpc_reg_operand" "b")]
11408 UNSPEC_TOCREL)))]
11409 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11410 "addis %0,%1@u(%2)")
11412 (define_insn "*largetoc_high_plus"
11413 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
11414 (high:DI
11415 (plus:DI
11416 (unspec [(match_operand:DI 1 "" "")
11417 (match_operand:DI 2 "gpc_reg_operand" "b")]
11418 UNSPEC_TOCREL)
11419 (match_operand:DI 3 "add_cint_operand" "n"))))]
11420 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11421 "addis %0,%2,%1+%3@toc@ha")
11423 (define_insn "*largetoc_high_plus_aix<mode>"
11424 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11425 (high:P
11426 (plus:P
11427 (unspec [(match_operand:P 1 "" "")
11428 (match_operand:P 2 "gpc_reg_operand" "b")]
11429 UNSPEC_TOCREL)
11430 (match_operand:P 3 "add_cint_operand" "n"))))]
11431 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11432 "addis %0,%1+%3@u(%2)")
11434 (define_insn "*largetoc_low"
11435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11436 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
11437 (match_operand:DI 2 "" "")))]
11438 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11439 "@
11440 addi %0,%1,%2@l
11441 addic %0,%1,%2@l")
11443 (define_insn "*largetoc_low_aix<mode>"
11444 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11445 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
11446 (match_operand:P 2 "" "")))]
11447 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11448 "la %0,%2@l(%1)")
11450 (define_insn_and_split "*tocref<mode>"
11451 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
11452 (match_operand:P 1 "small_toc_ref" "R"))]
11453 "TARGET_TOC"
11454 "la %0,%a1"
11455 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11456 [(set (match_dup 0) (high:P (match_dup 1)))
11457 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
11459 ;; Elf specific ways of loading addresses for non-PIC code.
11460 ;; The output of this could be r0, but we make a very strong
11461 ;; preference for a base register because it will usually
11462 ;; be needed there.
11463 (define_insn "elf_high"
11464 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11465 (high:SI (match_operand 1 "" "")))]
11466 "TARGET_ELF && ! TARGET_64BIT"
11467 "lis %0,%1@ha")
11469 (define_insn "elf_low"
11470 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11471 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11472 (match_operand 2 "" "")))]
11473 "TARGET_ELF && ! TARGET_64BIT"
11474 "@
11475 la %0,%2@l(%1)
11476 addic %0,%1,%K2")
11477 \f
11478 ;; Call and call_value insns
11479 (define_expand "call"
11480 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11481 (match_operand 1 "" ""))
11482 (use (match_operand 2 "" ""))
11483 (clobber (reg:SI LR_REGNO))])]
11484 ""
11485 "
11486 {
11487 #if TARGET_MACHO
11488 if (MACHOPIC_INDIRECT)
11489 operands[0] = machopic_indirect_call_target (operands[0]);
11490 #endif
11492 gcc_assert (GET_CODE (operands[0]) == MEM);
11493 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11495 operands[0] = XEXP (operands[0], 0);
11497 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11498 {
11499 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11500 DONE;
11501 }
11503 if (GET_CODE (operands[0]) != SYMBOL_REF
11504 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11505 {
11506 if (INTVAL (operands[2]) & CALL_LONG)
11507 operands[0] = rs6000_longcall_ref (operands[0]);
11509 switch (DEFAULT_ABI)
11510 {
11511 case ABI_V4:
11512 case ABI_DARWIN:
11513 operands[0] = force_reg (Pmode, operands[0]);
11514 break;
11516 default:
11517 gcc_unreachable ();
11518 }
11519 }
11520 }")
11522 (define_expand "call_value"
11523 [(parallel [(set (match_operand 0 "" "")
11524 (call (mem:SI (match_operand 1 "address_operand" ""))
11525 (match_operand 2 "" "")))
11526 (use (match_operand 3 "" ""))
11527 (clobber (reg:SI LR_REGNO))])]
11528 ""
11529 "
11530 {
11531 #if TARGET_MACHO
11532 if (MACHOPIC_INDIRECT)
11533 operands[1] = machopic_indirect_call_target (operands[1]);
11534 #endif
11536 gcc_assert (GET_CODE (operands[1]) == MEM);
11537 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11539 operands[1] = XEXP (operands[1], 0);
11541 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11542 {
11543 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
11544 DONE;
11545 }
11547 if (GET_CODE (operands[1]) != SYMBOL_REF
11548 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11549 {
11550 if (INTVAL (operands[3]) & CALL_LONG)
11551 operands[1] = rs6000_longcall_ref (operands[1]);
11553 switch (DEFAULT_ABI)
11554 {
11555 case ABI_V4:
11556 case ABI_DARWIN:
11557 operands[1] = force_reg (Pmode, operands[1]);
11558 break;
11560 default:
11561 gcc_unreachable ();
11562 }
11563 }
11564 }")
11566 ;; Call to function in current module. No TOC pointer reload needed.
11567 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11568 ;; either the function was not prototyped, or it was prototyped as a
11569 ;; variable argument function. It is > 0 if FP registers were passed
11570 ;; and < 0 if they were not.
11572 (define_insn "*call_local32"
11573 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11574 (match_operand 1 "" "g,g"))
11575 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11576 (clobber (reg:SI LR_REGNO))]
11577 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11578 "*
11579 {
11580 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11581 output_asm_insn (\"crxor 6,6,6\", operands);
11583 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11584 output_asm_insn (\"creqv 6,6,6\", operands);
11586 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11587 }"
11588 [(set_attr "type" "branch")
11589 (set_attr "length" "4,8")])
11591 (define_insn "*call_local64"
11592 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11593 (match_operand 1 "" "g,g"))
11594 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11595 (clobber (reg:SI LR_REGNO))]
11596 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11597 "*
11598 {
11599 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11600 output_asm_insn (\"crxor 6,6,6\", operands);
11602 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11603 output_asm_insn (\"creqv 6,6,6\", operands);
11605 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11606 }"
11607 [(set_attr "type" "branch")
11608 (set_attr "length" "4,8")])
11610 (define_insn "*call_value_local32"
11611 [(set (match_operand 0 "" "")
11612 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11613 (match_operand 2 "" "g,g")))
11614 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11615 (clobber (reg:SI LR_REGNO))]
11616 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11617 "*
11618 {
11619 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11620 output_asm_insn (\"crxor 6,6,6\", operands);
11622 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11623 output_asm_insn (\"creqv 6,6,6\", operands);
11625 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11626 }"
11627 [(set_attr "type" "branch")
11628 (set_attr "length" "4,8")])
11631 (define_insn "*call_value_local64"
11632 [(set (match_operand 0 "" "")
11633 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11634 (match_operand 2 "" "g,g")))
11635 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11636 (clobber (reg:SI LR_REGNO))]
11637 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11638 "*
11639 {
11640 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11641 output_asm_insn (\"crxor 6,6,6\", operands);
11643 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11644 output_asm_insn (\"creqv 6,6,6\", operands);
11646 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11647 }"
11648 [(set_attr "type" "branch")
11649 (set_attr "length" "4,8")])
11652 ;; A function pointer under System V is just a normal pointer
11653 ;; operands[0] is the function pointer
11654 ;; operands[1] is the stack size to clean up
11655 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11656 ;; which indicates how to set cr1
11658 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11659 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11660 (match_operand 1 "" "g,g,g,g"))
11661 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11662 (clobber (reg:SI LR_REGNO))]
11663 "DEFAULT_ABI == ABI_V4
11664 || DEFAULT_ABI == ABI_DARWIN"
11665 {
11666 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11667 output_asm_insn ("crxor 6,6,6", operands);
11669 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11670 output_asm_insn ("creqv 6,6,6", operands);
11672 return "b%T0l";
11673 }
11674 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11675 (set_attr "length" "4,4,8,8")])
11677 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11678 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11679 (match_operand 1 "" "g,g"))
11680 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11681 (clobber (reg:SI LR_REGNO))]
11682 "(DEFAULT_ABI == ABI_DARWIN
11683 || (DEFAULT_ABI == ABI_V4
11684 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11685 {
11686 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11687 output_asm_insn ("crxor 6,6,6", operands);
11689 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11690 output_asm_insn ("creqv 6,6,6", operands);
11692 #if TARGET_MACHO
11693 return output_call(insn, operands, 0, 2);
11694 #else
11695 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11696 {
11697 gcc_assert (!TARGET_SECURE_PLT);
11698 return "bl %z0@plt";
11699 }
11700 else
11701 return "bl %z0";
11702 #endif
11703 }
11704 "DEFAULT_ABI == ABI_V4
11705 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11706 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11707 [(parallel [(call (mem:SI (match_dup 0))
11708 (match_dup 1))
11709 (use (match_dup 2))
11710 (use (match_dup 3))
11711 (clobber (reg:SI LR_REGNO))])]
11712 {
11713 operands[3] = pic_offset_table_rtx;
11714 }
11715 [(set_attr "type" "branch,branch")
11716 (set_attr "length" "4,8")])
11718 (define_insn "*call_nonlocal_sysv_secure<mode>"
11719 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11720 (match_operand 1 "" "g,g"))
11721 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11722 (use (match_operand:SI 3 "register_operand" "r,r"))
11723 (clobber (reg:SI LR_REGNO))]
11724 "(DEFAULT_ABI == ABI_V4
11725 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11726 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11727 {
11728 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11729 output_asm_insn ("crxor 6,6,6", operands);
11731 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11732 output_asm_insn ("creqv 6,6,6", operands);
11734 if (flag_pic == 2)
11735 /* The magic 32768 offset here and in the other sysv call insns
11736 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11737 See sysv4.h:toc_section. */
11738 return "bl %z0+32768@plt";
11739 else
11740 return "bl %z0@plt";
11741 }
11742 [(set_attr "type" "branch,branch")
11743 (set_attr "length" "4,8")])
11745 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11746 [(set (match_operand 0 "" "")
11747 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11748 (match_operand 2 "" "g,g,g,g")))
11749 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11750 (clobber (reg:SI LR_REGNO))]
11751 "DEFAULT_ABI == ABI_V4
11752 || DEFAULT_ABI == ABI_DARWIN"
11753 {
11754 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11755 output_asm_insn ("crxor 6,6,6", operands);
11757 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11758 output_asm_insn ("creqv 6,6,6", operands);
11760 return "b%T1l";
11761 }
11762 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11763 (set_attr "length" "4,4,8,8")])
11765 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11766 [(set (match_operand 0 "" "")
11767 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11768 (match_operand 2 "" "g,g")))
11769 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11770 (clobber (reg:SI LR_REGNO))]
11771 "(DEFAULT_ABI == ABI_DARWIN
11772 || (DEFAULT_ABI == ABI_V4
11773 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11774 {
11775 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11776 output_asm_insn ("crxor 6,6,6", operands);
11778 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11779 output_asm_insn ("creqv 6,6,6", operands);
11781 #if TARGET_MACHO
11782 return output_call(insn, operands, 1, 3);
11783 #else
11784 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11785 {
11786 gcc_assert (!TARGET_SECURE_PLT);
11787 return "bl %z1@plt";
11788 }
11789 else
11790 return "bl %z1";
11791 #endif
11792 }
11793 "DEFAULT_ABI == ABI_V4
11794 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11795 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11796 [(parallel [(set (match_dup 0)
11797 (call (mem:SI (match_dup 1))
11798 (match_dup 2)))
11799 (use (match_dup 3))
11800 (use (match_dup 4))
11801 (clobber (reg:SI LR_REGNO))])]
11802 {
11803 operands[4] = pic_offset_table_rtx;
11804 }
11805 [(set_attr "type" "branch,branch")
11806 (set_attr "length" "4,8")])
11808 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11809 [(set (match_operand 0 "" "")
11810 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11811 (match_operand 2 "" "g,g")))
11812 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11813 (use (match_operand:SI 4 "register_operand" "r,r"))
11814 (clobber (reg:SI LR_REGNO))]
11815 "(DEFAULT_ABI == ABI_V4
11816 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11817 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11818 {
11819 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11820 output_asm_insn ("crxor 6,6,6", operands);
11822 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11823 output_asm_insn ("creqv 6,6,6", operands);
11825 if (flag_pic == 2)
11826 return "bl %z1+32768@plt";
11827 else
11828 return "bl %z1@plt";
11829 }
11830 [(set_attr "type" "branch,branch")
11831 (set_attr "length" "4,8")])
11834 ;; Call to AIX abi function in the same module.
11836 (define_insn "*call_local_aix<mode>"
11837 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
11838 (match_operand 1 "" "g"))
11839 (clobber (reg:P LR_REGNO))]
11840 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11841 "bl %z0"
11842 [(set_attr "type" "branch")
11843 (set_attr "length" "4")])
11845 (define_insn "*call_value_local_aix<mode>"
11846 [(set (match_operand 0 "" "")
11847 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
11848 (match_operand 2 "" "g")))
11849 (clobber (reg:P LR_REGNO))]
11850 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11851 "bl %z1"
11852 [(set_attr "type" "branch")
11853 (set_attr "length" "4")])
11855 ;; Call to AIX abi function which may be in another module.
11856 ;; Restore the TOC pointer (r2) after the call.
11858 (define_insn "*call_nonlocal_aix<mode>"
11859 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
11860 (match_operand 1 "" "g"))
11861 (clobber (reg:P LR_REGNO))]
11862 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11863 "bl %z0\;nop"
11864 [(set_attr "type" "branch")
11865 (set_attr "length" "8")])
11867 (define_insn "*call_value_nonlocal_aix<mode>"
11868 [(set (match_operand 0 "" "")
11869 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
11870 (match_operand 2 "" "g")))
11871 (clobber (reg:P LR_REGNO))]
11872 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
11873 "bl %z1\;nop"
11874 [(set_attr "type" "branch")
11875 (set_attr "length" "8")])
11877 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11878 ;; Operand0 is the addresss of the function to call
11879 ;; Operand2 is the location in the function descriptor to load r2 from
11880 ;; Operand3 is the stack location to hold the current TOC pointer
11882 (define_insn "*call_indirect_aix<mode>"
11883 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11884 (match_operand 1 "" "g,g"))
11885 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11886 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11887 (clobber (reg:P LR_REGNO))]
11888 "DEFAULT_ABI == ABI_AIX"
11889 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11890 [(set_attr "type" "jmpreg")
11891 (set_attr "length" "12")])
11893 (define_insn "*call_value_indirect_aix<mode>"
11894 [(set (match_operand 0 "" "")
11895 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11896 (match_operand 2 "" "g,g")))
11897 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11898 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
11899 (clobber (reg:P LR_REGNO))]
11900 "DEFAULT_ABI == ABI_AIX"
11901 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11902 [(set_attr "type" "jmpreg")
11903 (set_attr "length" "12")])
11905 ;; Call to indirect functions with the ELFv2 ABI.
11906 ;; Operand0 is the addresss of the function to call
11907 ;; Operand2 is the stack location to hold the current TOC pointer
11909 (define_insn "*call_indirect_elfv2<mode>"
11910 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11911 (match_operand 1 "" "g,g"))
11912 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
11913 (clobber (reg:P LR_REGNO))]
11914 "DEFAULT_ABI == ABI_ELFv2"
11915 "b%T0l\;<ptrload> 2,%2"
11916 [(set_attr "type" "jmpreg")
11917 (set_attr "length" "8")])
11919 (define_insn "*call_value_indirect_elfv2<mode>"
11920 [(set (match_operand 0 "" "")
11921 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11922 (match_operand 2 "" "g,g")))
11923 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
11924 (clobber (reg:P LR_REGNO))]
11925 "DEFAULT_ABI == ABI_ELFv2"
11926 "b%T1l\;<ptrload> 2,%3"
11927 [(set_attr "type" "jmpreg")
11928 (set_attr "length" "8")])
11931 ;; Call subroutine returning any type.
11932 (define_expand "untyped_call"
11933 [(parallel [(call (match_operand 0 "" "")
11934 (const_int 0))
11935 (match_operand 1 "" "")
11936 (match_operand 2 "" "")])]
11937 ""
11938 "
11939 {
11940 int i;
11942 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11944 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11945 {
11946 rtx set = XVECEXP (operands[2], 0, i);
11947 emit_move_insn (SET_DEST (set), SET_SRC (set));
11948 }
11950 /* The optimizer does not know that the call sets the function value
11951 registers we stored in the result block. We avoid problems by
11952 claiming that all hard registers are used and clobbered at this
11953 point. */
11954 emit_insn (gen_blockage ());
11956 DONE;
11957 }")
11959 ;; sibling call patterns
11960 (define_expand "sibcall"
11961 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11962 (match_operand 1 "" ""))
11963 (use (match_operand 2 "" ""))
11964 (use (reg:SI LR_REGNO))
11965 (simple_return)])]
11966 ""
11967 "
11968 {
11969 #if TARGET_MACHO
11970 if (MACHOPIC_INDIRECT)
11971 operands[0] = machopic_indirect_call_target (operands[0]);
11972 #endif
11974 gcc_assert (GET_CODE (operands[0]) == MEM);
11975 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11977 operands[0] = XEXP (operands[0], 0);
11979 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11980 {
11981 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
11982 DONE;
11983 }
11984 }")
11986 (define_expand "sibcall_value"
11987 [(parallel [(set (match_operand 0 "register_operand" "")
11988 (call (mem:SI (match_operand 1 "address_operand" ""))
11989 (match_operand 2 "" "")))
11990 (use (match_operand 3 "" ""))
11991 (use (reg:SI LR_REGNO))
11992 (simple_return)])]
11993 ""
11994 "
11995 {
11996 #if TARGET_MACHO
11997 if (MACHOPIC_INDIRECT)
11998 operands[1] = machopic_indirect_call_target (operands[1]);
11999 #endif
12001 gcc_assert (GET_CODE (operands[1]) == MEM);
12002 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12004 operands[1] = XEXP (operands[1], 0);
12006 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12007 {
12008 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
12009 DONE;
12010 }
12011 }")
12013 ;; this and similar patterns must be marked as using LR, otherwise
12014 ;; dataflow will try to delete the store into it. This is true
12015 ;; even when the actual reg to jump to is in CTR, when LR was
12016 ;; saved and restored around the PIC-setting BCL.
12017 (define_insn "*sibcall_local32"
12018 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12019 (match_operand 1 "" "g,g"))
12020 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12021 (use (reg:SI LR_REGNO))
12022 (simple_return)]
12023 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12024 "*
12025 {
12026 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12027 output_asm_insn (\"crxor 6,6,6\", operands);
12029 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12030 output_asm_insn (\"creqv 6,6,6\", operands);
12032 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12033 }"
12034 [(set_attr "type" "branch")
12035 (set_attr "length" "4,8")])
12037 (define_insn "*sibcall_local64"
12038 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12039 (match_operand 1 "" "g,g"))
12040 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12041 (use (reg:SI LR_REGNO))
12042 (simple_return)]
12043 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12044 "*
12045 {
12046 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12047 output_asm_insn (\"crxor 6,6,6\", operands);
12049 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12050 output_asm_insn (\"creqv 6,6,6\", operands);
12052 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12053 }"
12054 [(set_attr "type" "branch")
12055 (set_attr "length" "4,8")])
12057 (define_insn "*sibcall_value_local32"
12058 [(set (match_operand 0 "" "")
12059 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12060 (match_operand 2 "" "g,g")))
12061 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12062 (use (reg:SI LR_REGNO))
12063 (simple_return)]
12064 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12065 "*
12066 {
12067 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12068 output_asm_insn (\"crxor 6,6,6\", operands);
12070 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12071 output_asm_insn (\"creqv 6,6,6\", operands);
12073 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12074 }"
12075 [(set_attr "type" "branch")
12076 (set_attr "length" "4,8")])
12078 (define_insn "*sibcall_value_local64"
12079 [(set (match_operand 0 "" "")
12080 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12081 (match_operand 2 "" "g,g")))
12082 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12083 (use (reg:SI LR_REGNO))
12084 (simple_return)]
12085 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12086 "*
12087 {
12088 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12089 output_asm_insn (\"crxor 6,6,6\", operands);
12091 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12092 output_asm_insn (\"creqv 6,6,6\", operands);
12094 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12095 }"
12096 [(set_attr "type" "branch")
12097 (set_attr "length" "4,8")])
12099 (define_insn "*sibcall_nonlocal_sysv<mode>"
12100 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12101 (match_operand 1 "" ""))
12102 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12103 (use (reg:SI LR_REGNO))
12104 (simple_return)]
12105 "(DEFAULT_ABI == ABI_DARWIN
12106 || DEFAULT_ABI == ABI_V4)
12107 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12108 "*
12109 {
12110 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12111 output_asm_insn (\"crxor 6,6,6\", operands);
12113 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12114 output_asm_insn (\"creqv 6,6,6\", operands);
12116 if (which_alternative >= 2)
12117 return \"b%T0\";
12118 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12119 {
12120 gcc_assert (!TARGET_SECURE_PLT);
12121 return \"b %z0@plt\";
12122 }
12123 else
12124 return \"b %z0\";
12125 }"
12126 [(set_attr "type" "branch")
12127 (set_attr "length" "4,8,4,8")])
12129 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12130 [(set (match_operand 0 "" "")
12131 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12132 (match_operand 2 "" "")))
12133 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12134 (use (reg:SI LR_REGNO))
12135 (simple_return)]
12136 "(DEFAULT_ABI == ABI_DARWIN
12137 || DEFAULT_ABI == ABI_V4)
12138 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12139 "*
12140 {
12141 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12142 output_asm_insn (\"crxor 6,6,6\", operands);
12144 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12145 output_asm_insn (\"creqv 6,6,6\", operands);
12147 if (which_alternative >= 2)
12148 return \"b%T1\";
12149 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12150 {
12151 gcc_assert (!TARGET_SECURE_PLT);
12152 return \"b %z1@plt\";
12153 }
12154 else
12155 return \"b %z1\";
12156 }"
12157 [(set_attr "type" "branch")
12158 (set_attr "length" "4,8,4,8")])
12160 ;; AIX ABI sibling call patterns.
12162 (define_insn "*sibcall_aix<mode>"
12163 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12164 (match_operand 1 "" "g,g"))
12165 (simple_return)]
12166 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12167 "@
12168 b %z0
12169 b%T0"
12170 [(set_attr "type" "branch")
12171 (set_attr "length" "4")])
12173 (define_insn "*sibcall_value_aix<mode>"
12174 [(set (match_operand 0 "" "")
12175 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12176 (match_operand 2 "" "g,g")))
12177 (simple_return)]
12178 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12179 "@
12180 b %z1
12181 b%T1"
12182 [(set_attr "type" "branch")
12183 (set_attr "length" "4")])
12185 (define_expand "sibcall_epilogue"
12186 [(use (const_int 0))]
12187 ""
12188 {
12189 if (!TARGET_SCHED_PROLOG)
12190 emit_insn (gen_blockage ());
12191 rs6000_emit_epilogue (TRUE);
12192 DONE;
12193 })
12195 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12196 ;; all of memory. This blocks insns from being moved across this point.
12198 (define_insn "blockage"
12199 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12200 ""
12201 "")
12203 (define_expand "probe_stack"
12204 [(set (match_operand 0 "memory_operand" "=m")
12205 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12206 ""
12207 {
12208 if (TARGET_64BIT)
12209 emit_insn (gen_probe_stack_di (operands[0]));
12210 else
12211 emit_insn (gen_probe_stack_si (operands[0]));
12212 DONE;
12213 })
12215 (define_insn "probe_stack_<mode>"
12216 [(set (match_operand:P 0 "memory_operand" "=m")
12217 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12218 ""
12219 {
12220 operands[1] = gen_rtx_REG (Pmode, 0);
12221 return "st<wd>%U0%X0 %1,%0";
12222 }
12223 [(set_attr "type" "store")
12224 (set (attr "update")
12225 (if_then_else (match_operand 0 "update_address_mem")
12226 (const_string "yes")
12227 (const_string "no")))
12228 (set (attr "indexed")
12229 (if_then_else (match_operand 0 "indexed_address_mem")
12230 (const_string "yes")
12231 (const_string "no")))
12232 (set_attr "length" "4")])
12234 (define_insn "probe_stack_range<P:mode>"
12235 [(set (match_operand:P 0 "register_operand" "=r")
12236 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12237 (match_operand:P 2 "register_operand" "r")]
12238 UNSPECV_PROBE_STACK_RANGE))]
12239 ""
12240 "* return output_probe_stack_range (operands[0], operands[2]);"
12241 [(set_attr "type" "three")])
12242 \f
12243 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12244 ;; signed & unsigned, and one type of branch.
12245 ;;
12246 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12247 ;; insns, and branches.
12249 (define_expand "cbranch<mode>4"
12250 [(use (match_operator 0 "rs6000_cbranch_operator"
12251 [(match_operand:GPR 1 "gpc_reg_operand" "")
12252 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12253 (use (match_operand 3 ""))]
12254 ""
12255 "
12256 {
12257 /* Take care of the possibility that operands[2] might be negative but
12258 this might be a logical operation. That insn doesn't exist. */
12259 if (GET_CODE (operands[2]) == CONST_INT
12260 && INTVAL (operands[2]) < 0)
12261 {
12262 operands[2] = force_reg (<MODE>mode, operands[2]);
12263 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12264 GET_MODE (operands[0]),
12265 operands[1], operands[2]);
12266 }
12268 rs6000_emit_cbranch (<MODE>mode, operands);
12269 DONE;
12270 }")
12272 (define_expand "cbranch<mode>4"
12273 [(use (match_operator 0 "rs6000_cbranch_operator"
12274 [(match_operand:FP 1 "gpc_reg_operand" "")
12275 (match_operand:FP 2 "gpc_reg_operand" "")]))
12276 (use (match_operand 3 ""))]
12277 ""
12278 "
12279 {
12280 rs6000_emit_cbranch (<MODE>mode, operands);
12281 DONE;
12282 }")
12284 (define_expand "cstore<mode>4"
12285 [(use (match_operator 1 "rs6000_cbranch_operator"
12286 [(match_operand:GPR 2 "gpc_reg_operand" "")
12287 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12288 (clobber (match_operand:SI 0 "register_operand"))]
12289 ""
12290 "
12291 {
12292 /* Take care of the possibility that operands[3] might be negative but
12293 this might be a logical operation. That insn doesn't exist. */
12294 if (GET_CODE (operands[3]) == CONST_INT
12295 && INTVAL (operands[3]) < 0)
12296 {
12297 operands[3] = force_reg (<MODE>mode, operands[3]);
12298 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12299 GET_MODE (operands[1]),
12300 operands[2], operands[3]);
12301 }
12303 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12304 For SEQ, likewise, except that comparisons with zero should be done
12305 with an scc insns. However, due to the order that combine see the
12306 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12307 the cases we don't want to handle or are best handled by portable
12308 code. */
12309 if (GET_CODE (operands[1]) == NE)
12310 FAIL;
12311 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12312 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12313 && operands[3] == const0_rtx)
12314 FAIL;
12315 rs6000_emit_sCOND (<MODE>mode, operands);
12316 DONE;
12317 }")
12319 (define_expand "cstore<mode>4"
12320 [(use (match_operator 1 "rs6000_cbranch_operator"
12321 [(match_operand:FP 2 "gpc_reg_operand" "")
12322 (match_operand:FP 3 "gpc_reg_operand" "")]))
12323 (clobber (match_operand:SI 0 "register_operand"))]
12324 ""
12325 "
12326 {
12327 rs6000_emit_sCOND (<MODE>mode, operands);
12328 DONE;
12329 }")
12332 (define_expand "stack_protect_set"
12333 [(match_operand 0 "memory_operand" "")
12334 (match_operand 1 "memory_operand" "")]
12335 ""
12336 {
12337 #ifdef TARGET_THREAD_SSP_OFFSET
12338 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12339 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12340 operands[1] = gen_rtx_MEM (Pmode, addr);
12341 #endif
12342 if (TARGET_64BIT)
12343 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12344 else
12345 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12346 DONE;
12347 })
12349 (define_insn "stack_protect_setsi"
12350 [(set (match_operand:SI 0 "memory_operand" "=m")
12351 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12352 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12353 "TARGET_32BIT"
12354 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12355 [(set_attr "type" "three")
12356 (set_attr "length" "12")])
12358 (define_insn "stack_protect_setdi"
12359 [(set (match_operand:DI 0 "memory_operand" "=Y")
12360 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12361 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12362 "TARGET_64BIT"
12363 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12364 [(set_attr "type" "three")
12365 (set_attr "length" "12")])
12367 (define_expand "stack_protect_test"
12368 [(match_operand 0 "memory_operand" "")
12369 (match_operand 1 "memory_operand" "")
12370 (match_operand 2 "" "")]
12371 ""
12372 {
12373 rtx test, op0, op1;
12374 #ifdef TARGET_THREAD_SSP_OFFSET
12375 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12376 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12377 operands[1] = gen_rtx_MEM (Pmode, addr);
12378 #endif
12379 op0 = operands[0];
12380 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12381 test = gen_rtx_EQ (VOIDmode, op0, op1);
12382 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12383 DONE;
12384 })
12386 (define_insn "stack_protect_testsi"
12387 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12388 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12389 (match_operand:SI 2 "memory_operand" "m,m")]
12390 UNSPEC_SP_TEST))
12391 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12392 (clobber (match_scratch:SI 3 "=&r,&r"))]
12393 "TARGET_32BIT"
12394 "@
12395 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12396 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
12397 [(set_attr "length" "16,20")])
12399 (define_insn "stack_protect_testdi"
12400 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12401 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
12402 (match_operand:DI 2 "memory_operand" "Y,Y")]
12403 UNSPEC_SP_TEST))
12404 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12405 (clobber (match_scratch:DI 3 "=&r,&r"))]
12406 "TARGET_64BIT"
12407 "@
12408 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
12409 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
12410 [(set_attr "length" "16,20")])
12412 \f
12413 ;; Here are the actual compare insns.
12414 (define_insn "*cmp<mode>_internal1"
12415 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12416 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12417 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12418 ""
12419 "cmp<wd>%I2 %0,%1,%2"
12420 [(set_attr "type" "cmp")])
12422 ;; If we are comparing a register for equality with a large constant,
12423 ;; we can do this with an XOR followed by a compare. But this is profitable
12424 ;; only if the large constant is only used for the comparison (and in this
12425 ;; case we already have a register to reuse as scratch).
12426 ;;
12427 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12428 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12430 (define_peephole2
12431 [(set (match_operand:SI 0 "register_operand")
12432 (match_operand:SI 1 "logical_const_operand" ""))
12433 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12434 [(match_dup 0)
12435 (match_operand:SI 2 "logical_const_operand" "")]))
12436 (set (match_operand:CC 4 "cc_reg_operand" "")
12437 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12438 (match_dup 0)))
12439 (set (pc)
12440 (if_then_else (match_operator 6 "equality_operator"
12441 [(match_dup 4) (const_int 0)])
12442 (match_operand 7 "" "")
12443 (match_operand 8 "" "")))]
12444 "peep2_reg_dead_p (3, operands[0])
12445 && peep2_reg_dead_p (4, operands[4])"
12446 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12447 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12448 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12450 {
12451 /* Get the constant we are comparing against, and see what it looks like
12452 when sign-extended from 16 to 32 bits. Then see what constant we could
12453 XOR with SEXTC to get the sign-extended value. */
12454 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12455 SImode,
12456 operands[1], operands[2]);
12457 HOST_WIDE_INT c = INTVAL (cnst);
12458 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12459 HOST_WIDE_INT xorv = c ^ sextc;
12461 operands[9] = GEN_INT (xorv);
12462 operands[10] = GEN_INT (sextc);
12463 })
12465 (define_insn "*cmpsi_internal2"
12466 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12467 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12468 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12469 ""
12470 "cmplw%I2 %0,%1,%b2"
12471 [(set_attr "type" "cmp")])
12473 (define_insn "*cmpdi_internal2"
12474 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12475 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12476 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12477 ""
12478 "cmpld%I2 %0,%1,%b2"
12479 [(set_attr "type" "cmp")])
12481 ;; The following two insns don't exist as single insns, but if we provide
12482 ;; them, we can swap an add and compare, which will enable us to overlap more
12483 ;; of the required delay between a compare and branch. We generate code for
12484 ;; them by splitting.
12486 (define_insn ""
12487 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12488 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12489 (match_operand:SI 2 "short_cint_operand" "i")))
12490 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12491 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12492 ""
12493 "#"
12494 [(set_attr "length" "8")])
12496 (define_insn ""
12497 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12498 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12499 (match_operand:SI 2 "u_short_cint_operand" "i")))
12500 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12501 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12502 ""
12503 "#"
12504 [(set_attr "length" "8")])
12506 (define_split
12507 [(set (match_operand:CC 3 "cc_reg_operand" "")
12508 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12509 (match_operand:SI 2 "short_cint_operand" "")))
12510 (set (match_operand:SI 0 "gpc_reg_operand" "")
12511 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12512 ""
12513 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12514 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12516 (define_split
12517 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12518 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12519 (match_operand:SI 2 "u_short_cint_operand" "")))
12520 (set (match_operand:SI 0 "gpc_reg_operand" "")
12521 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12522 ""
12523 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12524 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12526 ;; Only need to compare second words if first words equal
12527 (define_insn "*cmptf_internal1"
12528 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12529 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12530 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12531 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12532 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12533 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12534 [(set_attr "type" "fpcompare")
12535 (set_attr "length" "12")])
12537 (define_insn_and_split "*cmptf_internal2"
12538 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12539 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12540 (match_operand:TF 2 "gpc_reg_operand" "d")))
12541 (clobber (match_scratch:DF 3 "=d"))
12542 (clobber (match_scratch:DF 4 "=d"))
12543 (clobber (match_scratch:DF 5 "=d"))
12544 (clobber (match_scratch:DF 6 "=d"))
12545 (clobber (match_scratch:DF 7 "=d"))
12546 (clobber (match_scratch:DF 8 "=d"))
12547 (clobber (match_scratch:DF 9 "=d"))
12548 (clobber (match_scratch:DF 10 "=d"))
12549 (clobber (match_scratch:GPR 11 "=b"))]
12550 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12551 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12552 "#"
12553 "&& reload_completed"
12554 [(set (match_dup 3) (match_dup 14))
12555 (set (match_dup 4) (match_dup 15))
12556 (set (match_dup 9) (abs:DF (match_dup 5)))
12557 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12558 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12559 (label_ref (match_dup 12))
12560 (pc)))
12561 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12562 (set (pc) (label_ref (match_dup 13)))
12563 (match_dup 12)
12564 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12565 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12566 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12567 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12568 (match_dup 13)]
12569 {
12570 REAL_VALUE_TYPE rv;
12571 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
12572 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
12574 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12575 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12576 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12577 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12578 operands[12] = gen_label_rtx ();
12579 operands[13] = gen_label_rtx ();
12580 real_inf (&rv);
12581 operands[14] = force_const_mem (DFmode,
12582 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12583 operands[15] = force_const_mem (DFmode,
12584 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12585 DFmode));
12586 if (TARGET_TOC)
12587 {
12588 rtx tocref;
12589 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12590 operands[14] = gen_const_mem (DFmode, tocref);
12591 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12592 operands[15] = gen_const_mem (DFmode, tocref);
12593 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12594 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12595 }
12596 })
12597 \f
12598 ;; Now we have the scc insns. We can do some combinations because of the
12599 ;; way the machine works.
12600 ;;
12601 ;; Note that this is probably faster if we can put an insn between the
12602 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12603 ;; cases the insns below which don't use an intermediate CR field will
12604 ;; be used instead.
12605 (define_insn ""
12606 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12607 (match_operator:SI 1 "scc_comparison_operator"
12608 [(match_operand 2 "cc_reg_operand" "y")
12609 (const_int 0)]))]
12610 ""
12611 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12612 [(set (attr "type")
12613 (cond [(match_test "TARGET_MFCRF")
12614 (const_string "mfcrf")
12615 ]
12616 (const_string "mfcr")))
12617 (set_attr "length" "8")])
12619 ;; Same as above, but get the GT bit.
12620 (define_insn "move_from_CR_gt_bit"
12621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12622 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12623 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12624 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
12625 [(set_attr "type" "mfcr")
12626 (set_attr "length" "8")])
12628 ;; Same as above, but get the OV/ORDERED bit.
12629 (define_insn "move_from_CR_ov_bit"
12630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12631 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
12632 UNSPEC_MV_CR_OV))]
12633 "TARGET_ISEL"
12634 "mfcr %0\;rlwinm %0,%0,%t1,1"
12635 [(set_attr "type" "mfcr")
12636 (set_attr "length" "8")])
12638 (define_insn ""
12639 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12640 (match_operator:DI 1 "scc_comparison_operator"
12641 [(match_operand 2 "cc_reg_operand" "y")
12642 (const_int 0)]))]
12643 "TARGET_POWERPC64"
12644 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
12645 [(set (attr "type")
12646 (cond [(match_test "TARGET_MFCRF")
12647 (const_string "mfcrf")
12648 ]
12649 (const_string "mfcr")))
12650 (set_attr "length" "8")])
12652 (define_insn ""
12653 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12654 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12655 [(match_operand 2 "cc_reg_operand" "y,y")
12656 (const_int 0)])
12657 (const_int 0)))
12658 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12659 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12660 "TARGET_32BIT"
12661 "@
12662 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
12663 #"
12664 [(set_attr "type" "shift")
12665 (set_attr "dot" "yes")
12666 (set_attr "length" "8,16")])
12668 (define_split
12669 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12670 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12671 [(match_operand 2 "cc_reg_operand" "")
12672 (const_int 0)])
12673 (const_int 0)))
12674 (set (match_operand:SI 3 "gpc_reg_operand" "")
12675 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12676 "TARGET_32BIT && reload_completed"
12677 [(set (match_dup 3)
12678 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12679 (set (match_dup 0)
12680 (compare:CC (match_dup 3)
12681 (const_int 0)))]
12682 "")
12684 (define_insn ""
12685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12686 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12687 [(match_operand 2 "cc_reg_operand" "y")
12688 (const_int 0)])
12689 (match_operand:SI 3 "const_int_operand" "n")))]
12690 ""
12691 "*
12692 {
12693 int is_bit = ccr_bit (operands[1], 1);
12694 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12695 int count;
12697 if (is_bit >= put_bit)
12698 count = is_bit - put_bit;
12699 else
12700 count = 32 - (put_bit - is_bit);
12702 operands[4] = GEN_INT (count);
12703 operands[5] = GEN_INT (put_bit);
12705 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
12706 }"
12707 [(set (attr "type")
12708 (cond [(match_test "TARGET_MFCRF")
12709 (const_string "mfcrf")
12710 ]
12711 (const_string "mfcr")))
12712 (set_attr "length" "8")])
12714 (define_insn ""
12715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12716 (compare:CC
12717 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12718 [(match_operand 2 "cc_reg_operand" "y,y")
12719 (const_int 0)])
12720 (match_operand:SI 3 "const_int_operand" "n,n"))
12721 (const_int 0)))
12722 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12723 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12724 (match_dup 3)))]
12725 ""
12726 "*
12727 {
12728 int is_bit = ccr_bit (operands[1], 1);
12729 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12730 int count;
12732 /* Force split for non-cc0 compare. */
12733 if (which_alternative == 1)
12734 return \"#\";
12736 if (is_bit >= put_bit)
12737 count = is_bit - put_bit;
12738 else
12739 count = 32 - (put_bit - is_bit);
12741 operands[5] = GEN_INT (count);
12742 operands[6] = GEN_INT (put_bit);
12744 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
12745 }"
12746 [(set_attr "type" "shift")
12747 (set_attr "dot" "yes")
12748 (set_attr "length" "8,16")])
12750 (define_split
12751 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12752 (compare:CC
12753 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12754 [(match_operand 2 "cc_reg_operand" "")
12755 (const_int 0)])
12756 (match_operand:SI 3 "const_int_operand" ""))
12757 (const_int 0)))
12758 (set (match_operand:SI 4 "gpc_reg_operand" "")
12759 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12760 (match_dup 3)))]
12761 "reload_completed"
12762 [(set (match_dup 4)
12763 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12764 (match_dup 3)))
12765 (set (match_dup 0)
12766 (compare:CC (match_dup 4)
12767 (const_int 0)))]
12768 "")
12770 ;; There is a 3 cycle delay between consecutive mfcr instructions
12771 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12773 (define_peephole
12774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12775 (match_operator:SI 1 "scc_comparison_operator"
12776 [(match_operand 2 "cc_reg_operand" "y")
12777 (const_int 0)]))
12778 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12779 (match_operator:SI 4 "scc_comparison_operator"
12780 [(match_operand 5 "cc_reg_operand" "y")
12781 (const_int 0)]))]
12782 "REGNO (operands[2]) != REGNO (operands[5])"
12783 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12784 [(set_attr "type" "mfcr")
12785 (set_attr "length" "12")])
12787 (define_peephole
12788 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12789 (match_operator:DI 1 "scc_comparison_operator"
12790 [(match_operand 2 "cc_reg_operand" "y")
12791 (const_int 0)]))
12792 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12793 (match_operator:DI 4 "scc_comparison_operator"
12794 [(match_operand 5 "cc_reg_operand" "y")
12795 (const_int 0)]))]
12796 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12797 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
12798 [(set_attr "type" "mfcr")
12799 (set_attr "length" "12")])
12801 ;; There are some scc insns that can be done directly, without a compare.
12802 ;; These are faster because they don't involve the communications between
12803 ;; the FXU and branch units. In fact, we will be replacing all of the
12804 ;; integer scc insns here or in the portable methods in emit_store_flag.
12805 ;;
12806 ;; Also support (neg (scc ..)) since that construct is used to replace
12807 ;; branches, (plus (scc ..) ..) since that construct is common and
12808 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12809 ;; cases where it is no more expensive than (neg (scc ..)).
12811 ;; Have reload force a constant into a register for the simple insns that
12812 ;; otherwise won't accept constants. We do this because it is faster than
12813 ;; the cmp/mfcr sequence we would otherwise generate.
12815 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12816 (DI "rKJI")])
12818 (define_insn_and_split "*eq<mode>"
12819 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12820 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12821 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12822 ""
12823 "#"
12824 ""
12825 [(set (match_dup 0)
12826 (clz:GPR (match_dup 3)))
12827 (set (match_dup 0)
12828 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12829 {
12830 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12831 {
12832 /* Use output operand as intermediate. */
12833 operands[3] = operands[0];
12835 if (logical_operand (operands[2], <MODE>mode))
12836 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12837 gen_rtx_XOR (<MODE>mode,
12838 operands[1], operands[2])));
12839 else
12840 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12841 gen_rtx_PLUS (<MODE>mode, operands[1],
12842 negate_rtx (<MODE>mode,
12843 operands[2]))));
12844 }
12845 else
12846 operands[3] = operands[1];
12848 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12849 })
12851 (define_insn_and_split "*eq<mode>_compare"
12852 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12853 (compare:CC
12854 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12855 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12856 (const_int 0)))
12857 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12858 (eq:P (match_dup 1) (match_dup 2)))]
12859 "optimize_size"
12860 "#"
12861 "optimize_size"
12862 [(set (match_dup 0)
12863 (clz:P (match_dup 4)))
12864 (parallel [(set (match_dup 3)
12865 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12866 (const_int 0)))
12867 (set (match_dup 0)
12868 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12869 {
12870 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12871 {
12872 /* Use output operand as intermediate. */
12873 operands[4] = operands[0];
12875 if (logical_operand (operands[2], <MODE>mode))
12876 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12877 gen_rtx_XOR (<MODE>mode,
12878 operands[1], operands[2])));
12879 else
12880 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12881 gen_rtx_PLUS (<MODE>mode, operands[1],
12882 negate_rtx (<MODE>mode,
12883 operands[2]))));
12884 }
12885 else
12886 operands[4] = operands[1];
12888 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12889 })
12891 ;; We have insns of the form shown by the first define_insn below. If
12892 ;; there is something inside the comparison operation, we must split it.
12893 (define_split
12894 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12895 (plus:SI (match_operator 1 "comparison_operator"
12896 [(match_operand:SI 2 "" "")
12897 (match_operand:SI 3
12898 "reg_or_cint_operand" "")])
12899 (match_operand:SI 4 "gpc_reg_operand" "")))
12900 (clobber (match_operand:SI 5 "register_operand" ""))]
12901 "! gpc_reg_operand (operands[2], SImode)"
12902 [(set (match_dup 5) (match_dup 2))
12903 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
12904 (match_dup 4)))])
12906 (define_insn "*plus_eqsi"
12907 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12908 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12909 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12910 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12911 "TARGET_32BIT"
12912 "@
12913 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
12914 subfic %0,%1,0\;addze %0,%3
12915 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
12916 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
12917 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
12918 [(set_attr "type" "three,two,three,three,three")
12919 (set_attr "length" "12,8,12,12,12")])
12921 (define_insn "*compare_plus_eqsi"
12922 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12923 (compare:CC
12924 (plus:SI
12925 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12926 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12927 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12928 (const_int 0)))
12929 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12930 "TARGET_32BIT && optimize_size"
12931 "@
12932 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12933 subfic %4,%1,0\;addze. %4,%3
12934 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
12935 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
12936 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
12937 #
12938 #
12939 #
12940 #
12941 #"
12942 [(set_attr "type" "compare")
12943 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12945 (define_split
12946 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12947 (compare:CC
12948 (plus:SI
12949 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12950 (match_operand:SI 2 "scc_eq_operand" ""))
12951 (match_operand:SI 3 "gpc_reg_operand" ""))
12952 (const_int 0)))
12953 (clobber (match_scratch:SI 4 ""))]
12954 "TARGET_32BIT && optimize_size && reload_completed"
12955 [(set (match_dup 4)
12956 (plus:SI (eq:SI (match_dup 1)
12957 (match_dup 2))
12958 (match_dup 3)))
12959 (set (match_dup 0)
12960 (compare:CC (match_dup 4)
12961 (const_int 0)))]
12962 "")
12964 (define_insn "*plus_eqsi_compare"
12965 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12966 (compare:CC
12967 (plus:SI
12968 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12969 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12970 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12971 (const_int 0)))
12972 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12973 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12974 "TARGET_32BIT && optimize_size"
12975 "@
12976 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12977 subfic %0,%1,0\;addze. %0,%3
12978 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
12979 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
12980 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
12981 #
12982 #
12983 #
12984 #
12985 #"
12986 [(set_attr "type" "compare")
12987 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12989 (define_split
12990 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12991 (compare:CC
12992 (plus:SI
12993 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12994 (match_operand:SI 2 "scc_eq_operand" ""))
12995 (match_operand:SI 3 "gpc_reg_operand" ""))
12996 (const_int 0)))
12997 (set (match_operand:SI 0 "gpc_reg_operand" "")
12998 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12999 "TARGET_32BIT && optimize_size && reload_completed"
13000 [(set (match_dup 0)
13001 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13002 (set (match_dup 4)
13003 (compare:CC (match_dup 0)
13004 (const_int 0)))]
13005 "")
13007 (define_insn "*neg_eq0<mode>"
13008 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13009 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13010 (const_int 0))))]
13011 ""
13012 "addic %0,%1,-1\;subfe %0,%0,%0"
13013 [(set_attr "type" "two")
13014 (set_attr "length" "8")])
13016 (define_insn_and_split "*neg_eq<mode>"
13017 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13018 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13019 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13020 ""
13021 "#"
13022 ""
13023 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13024 {
13025 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13026 {
13027 /* Use output operand as intermediate. */
13028 operands[3] = operands[0];
13030 if (logical_operand (operands[2], <MODE>mode))
13031 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13032 gen_rtx_XOR (<MODE>mode,
13033 operands[1], operands[2])));
13034 else
13035 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13036 gen_rtx_PLUS (<MODE>mode, operands[1],
13037 negate_rtx (<MODE>mode,
13038 operands[2]))));
13039 }
13040 else
13041 operands[3] = operands[1];
13042 })
13044 (define_insn "*ne0_<mode>"
13045 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13046 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13047 (const_int 0)))
13048 (clobber (match_scratch:P 2 "=&r"))]
13049 "!(TARGET_32BIT && TARGET_ISEL)"
13050 "addic %2,%1,-1\;subfe %0,%2,%1"
13051 [(set_attr "type" "two")
13052 (set_attr "length" "8")])
13054 (define_insn "*plus_ne0_<mode>"
13055 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13056 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13057 (const_int 0))
13058 (match_operand:P 2 "gpc_reg_operand" "r")))
13059 (clobber (match_scratch:P 3 "=&r"))]
13060 ""
13061 "addic %3,%1,-1\;addze %0,%2"
13062 [(set_attr "type" "two")
13063 (set_attr "length" "8")])
13065 (define_insn "*compare_plus_ne0_<mode>"
13066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13067 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13068 (const_int 0))
13069 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13070 (const_int 0)))
13071 (clobber (match_scratch:P 3 "=&r,&r"))
13072 (clobber (match_scratch:P 4 "=X,&r"))]
13073 ""
13074 "@
13075 addic %3,%1,-1\;addze. %3,%2
13076 #"
13077 [(set_attr "type" "compare")
13078 (set_attr "length" "8,12")])
13080 (define_split
13081 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13082 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13083 (const_int 0))
13084 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13085 (clobber (match_scratch:P 3 ""))
13086 (clobber (match_scratch:P 4 ""))]
13087 "reload_completed"
13088 [(parallel [(set (match_dup 3)
13089 (plus:P (ne:P (match_dup 1)
13090 (const_int 0))
13091 (match_dup 2)))
13092 (clobber (match_dup 4))])
13093 (set (match_dup 0)
13094 (compare:CC (match_dup 3)
13095 (const_int 0)))]
13096 "")
13098 ; For combine.
13099 (define_insn "*compare_plus_ne0_<mode>_1"
13100 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13101 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13102 (const_int 0))
13103 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13104 (clobber (match_scratch:P 3 "=&r,&r"))
13105 (clobber (match_scratch:P 4 "=X,&r"))]
13106 ""
13107 "@
13108 addic %3,%1,-1\;addze. %3,%2
13109 #"
13110 [(set_attr "type" "compare")
13111 (set_attr "length" "8,12")])
13113 (define_split
13114 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13115 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13116 (const_int 0))
13117 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13118 (clobber (match_scratch:P 3 ""))
13119 (clobber (match_scratch:P 4 ""))]
13120 "reload_completed"
13121 [(parallel [(set (match_dup 3)
13122 (plus:P (ne:P (match_dup 1)
13123 (const_int 0))
13124 (match_dup 2)))
13125 (clobber (match_dup 4))])
13126 (set (match_dup 0)
13127 (compare:CC (match_dup 3)
13128 (const_int 0)))]
13129 "")
13131 (define_insn "*plus_ne0_<mode>_compare"
13132 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13133 (compare:CC
13134 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13135 (const_int 0))
13136 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13137 (const_int 0)))
13138 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13139 (plus:P (ne:P (match_dup 1)
13140 (const_int 0))
13141 (match_dup 2)))
13142 (clobber (match_scratch:P 3 "=&r,&r"))]
13143 ""
13144 "@
13145 addic %3,%1,-1\;addze. %0,%2
13146 #"
13147 [(set_attr "type" "compare")
13148 (set_attr "length" "8,12")])
13150 (define_split
13151 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13152 (compare:CC
13153 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13154 (const_int 0))
13155 (match_operand:P 2 "gpc_reg_operand" ""))
13156 (const_int 0)))
13157 (set (match_operand:P 0 "gpc_reg_operand" "")
13158 (plus:P (ne:P (match_dup 1)
13159 (const_int 0))
13160 (match_dup 2)))
13161 (clobber (match_scratch:P 3 ""))]
13162 "reload_completed"
13163 [(parallel [(set (match_dup 0)
13164 (plus:P (ne:P (match_dup 1)
13165 (const_int 0))
13166 (match_dup 2)))
13167 (clobber (match_dup 3))])
13168 (set (match_dup 4)
13169 (compare:CC (match_dup 0)
13170 (const_int 0)))]
13171 "")
13173 (define_insn "*leu<mode>"
13174 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13175 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13176 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13177 ""
13178 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13179 [(set_attr "type" "three")
13180 (set_attr "length" "12")])
13182 (define_insn "*leu<mode>_compare"
13183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13184 (compare:CC
13185 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13186 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13187 (const_int 0)))
13188 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13189 (leu:P (match_dup 1) (match_dup 2)))]
13190 ""
13191 "@
13192 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13193 #"
13194 [(set_attr "type" "compare")
13195 (set_attr "length" "12,16")])
13197 (define_split
13198 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13199 (compare:CC
13200 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13201 (match_operand:P 2 "reg_or_short_operand" ""))
13202 (const_int 0)))
13203 (set (match_operand:P 0 "gpc_reg_operand" "")
13204 (leu:P (match_dup 1) (match_dup 2)))]
13205 "reload_completed"
13206 [(set (match_dup 0)
13207 (leu:P (match_dup 1) (match_dup 2)))
13208 (set (match_dup 3)
13209 (compare:CC (match_dup 0)
13210 (const_int 0)))]
13211 "")
13213 (define_insn "*plus_leu<mode>"
13214 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13215 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13216 (match_operand:P 2 "reg_or_short_operand" "rI"))
13217 (match_operand:P 3 "gpc_reg_operand" "r")))]
13218 ""
13219 "subf%I2c %0,%1,%2\;addze %0,%3"
13220 [(set_attr "type" "two")
13221 (set_attr "length" "8")])
13223 (define_insn ""
13224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13225 (compare:CC
13226 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13227 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13228 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13229 (const_int 0)))
13230 (clobber (match_scratch:SI 4 "=&r,&r"))]
13231 "TARGET_32BIT"
13232 "@
13233 subf%I2c %4,%1,%2\;addze. %4,%3
13234 #"
13235 [(set_attr "type" "compare")
13236 (set_attr "length" "8,12")])
13238 (define_split
13239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13240 (compare:CC
13241 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13242 (match_operand:SI 2 "reg_or_short_operand" ""))
13243 (match_operand:SI 3 "gpc_reg_operand" ""))
13244 (const_int 0)))
13245 (clobber (match_scratch:SI 4 ""))]
13246 "TARGET_32BIT && reload_completed"
13247 [(set (match_dup 4)
13248 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13249 (match_dup 3)))
13250 (set (match_dup 0)
13251 (compare:CC (match_dup 4)
13252 (const_int 0)))]
13253 "")
13255 (define_insn ""
13256 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13257 (compare:CC
13258 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13259 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13260 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13261 (const_int 0)))
13262 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13263 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13264 "TARGET_32BIT"
13265 "@
13266 subf%I2c %0,%1,%2\;addze. %0,%3
13267 #"
13268 [(set_attr "type" "compare")
13269 (set_attr "length" "8,12")])
13271 (define_split
13272 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13273 (compare:CC
13274 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13275 (match_operand:SI 2 "reg_or_short_operand" ""))
13276 (match_operand:SI 3 "gpc_reg_operand" ""))
13277 (const_int 0)))
13278 (set (match_operand:SI 0 "gpc_reg_operand" "")
13279 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13280 "TARGET_32BIT && reload_completed"
13281 [(set (match_dup 0)
13282 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13283 (set (match_dup 4)
13284 (compare:CC (match_dup 0)
13285 (const_int 0)))]
13286 "")
13288 (define_insn "*neg_leu<mode>"
13289 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13290 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13291 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13292 ""
13293 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13294 [(set_attr "type" "three")
13295 (set_attr "length" "12")])
13297 (define_insn "*and_neg_leu<mode>"
13298 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13299 (and:P (neg:P
13300 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13301 (match_operand:P 2 "reg_or_short_operand" "rI")))
13302 (match_operand:P 3 "gpc_reg_operand" "r")))]
13303 ""
13304 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13305 [(set_attr "type" "three")
13306 (set_attr "length" "12")])
13308 (define_insn ""
13309 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13310 (compare:CC
13311 (and:SI (neg:SI
13312 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13313 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13314 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13315 (const_int 0)))
13316 (clobber (match_scratch:SI 4 "=&r,&r"))]
13317 "TARGET_32BIT"
13318 "@
13319 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13320 #"
13321 [(set_attr "type" "compare")
13322 (set_attr "length" "12,16")])
13324 (define_split
13325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13326 (compare:CC
13327 (and:SI (neg:SI
13328 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13329 (match_operand:SI 2 "reg_or_short_operand" "")))
13330 (match_operand:SI 3 "gpc_reg_operand" ""))
13331 (const_int 0)))
13332 (clobber (match_scratch:SI 4 ""))]
13333 "TARGET_32BIT && reload_completed"
13334 [(set (match_dup 4)
13335 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13336 (match_dup 3)))
13337 (set (match_dup 0)
13338 (compare:CC (match_dup 4)
13339 (const_int 0)))]
13340 "")
13342 (define_insn ""
13343 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13344 (compare:CC
13345 (and:SI (neg:SI
13346 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13347 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13348 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13349 (const_int 0)))
13350 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13351 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13352 "TARGET_32BIT"
13353 "@
13354 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13355 #"
13356 [(set_attr "type" "compare")
13357 (set_attr "length" "12,16")])
13359 (define_split
13360 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13361 (compare:CC
13362 (and:SI (neg:SI
13363 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13364 (match_operand:SI 2 "reg_or_short_operand" "")))
13365 (match_operand:SI 3 "gpc_reg_operand" ""))
13366 (const_int 0)))
13367 (set (match_operand:SI 0 "gpc_reg_operand" "")
13368 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13369 "TARGET_32BIT && reload_completed"
13370 [(set (match_dup 0)
13371 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13372 (match_dup 3)))
13373 (set (match_dup 4)
13374 (compare:CC (match_dup 0)
13375 (const_int 0)))]
13376 "")
13378 (define_insn_and_split "*ltu<mode>"
13379 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13380 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13381 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13382 ""
13383 "#"
13384 ""
13385 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13386 (set (match_dup 0) (neg:P (match_dup 0)))]
13387 "")
13389 (define_insn_and_split "*ltu<mode>_compare"
13390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13391 (compare:CC
13392 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13393 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13394 (const_int 0)))
13395 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13396 (ltu:P (match_dup 1) (match_dup 2)))]
13397 ""
13398 "#"
13399 ""
13400 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13401 (parallel [(set (match_dup 3)
13402 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13403 (set (match_dup 0) (neg:P (match_dup 0)))])]
13404 "")
13406 (define_insn_and_split "*plus_ltu<mode>"
13407 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13408 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13409 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13410 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13411 ""
13412 "#"
13413 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13414 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13415 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13416 "")
13418 (define_insn_and_split "*plus_ltu<mode>_compare"
13419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13420 (compare:CC
13421 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13422 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13423 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13424 (const_int 0)))
13425 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13426 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13427 ""
13428 "#"
13429 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13430 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13431 (parallel [(set (match_dup 4)
13432 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13433 (const_int 0)))
13434 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13435 "")
13437 (define_insn "*neg_ltu<mode>"
13438 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13439 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13440 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13441 ""
13442 "@
13443 subfc %0,%2,%1\;subfe %0,%0,%0
13444 addic %0,%1,%n2\;subfe %0,%0,%0"
13445 [(set_attr "type" "two")
13446 (set_attr "length" "8")])
13448 (define_insn "*geu<mode>"
13449 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13450 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13451 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13452 ""
13453 "@
13454 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13455 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13456 [(set_attr "type" "three")
13457 (set_attr "length" "12")])
13459 (define_insn "*geu<mode>_compare"
13460 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13461 (compare:CC
13462 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13463 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13464 (const_int 0)))
13465 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13466 (geu:P (match_dup 1) (match_dup 2)))]
13467 ""
13468 "@
13469 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13470 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13471 #
13472 #"
13473 [(set_attr "type" "compare")
13474 (set_attr "length" "12,12,16,16")])
13476 (define_split
13477 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13478 (compare:CC
13479 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13480 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13481 (const_int 0)))
13482 (set (match_operand:P 0 "gpc_reg_operand" "")
13483 (geu:P (match_dup 1) (match_dup 2)))]
13484 "reload_completed"
13485 [(set (match_dup 0)
13486 (geu:P (match_dup 1) (match_dup 2)))
13487 (set (match_dup 3)
13488 (compare:CC (match_dup 0)
13489 (const_int 0)))]
13490 "")
13492 (define_insn "*plus_geu<mode>"
13493 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13494 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13495 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13496 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13497 ""
13498 "@
13499 subfc %0,%2,%1\;addze %0,%3
13500 addic %0,%1,%n2\;addze %0,%3"
13501 [(set_attr "type" "two")
13502 (set_attr "length" "8")])
13504 (define_insn ""
13505 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13506 (compare:CC
13507 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13508 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13509 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13510 (const_int 0)))
13511 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13512 "TARGET_32BIT"
13513 "@
13514 subfc %4,%2,%1\;addze. %4,%3
13515 addic %4,%1,%n2\;addze. %4,%3
13516 #
13517 #"
13518 [(set_attr "type" "compare")
13519 (set_attr "length" "8,8,12,12")])
13521 (define_split
13522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13523 (compare:CC
13524 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13525 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13526 (match_operand:SI 3 "gpc_reg_operand" ""))
13527 (const_int 0)))
13528 (clobber (match_scratch:SI 4 ""))]
13529 "TARGET_32BIT && reload_completed"
13530 [(set (match_dup 4)
13531 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13532 (match_dup 3)))
13533 (set (match_dup 0)
13534 (compare:CC (match_dup 4)
13535 (const_int 0)))]
13536 "")
13538 (define_insn ""
13539 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13540 (compare:CC
13541 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13542 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13543 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13544 (const_int 0)))
13545 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13546 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13547 "TARGET_32BIT"
13548 "@
13549 subfc %0,%2,%1\;addze. %0,%3
13550 addic %0,%1,%n2\;addze. %0,%3
13551 #
13552 #"
13553 [(set_attr "type" "compare")
13554 (set_attr "length" "8,8,12,12")])
13556 (define_split
13557 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13558 (compare:CC
13559 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13560 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13561 (match_operand:SI 3 "gpc_reg_operand" ""))
13562 (const_int 0)))
13563 (set (match_operand:SI 0 "gpc_reg_operand" "")
13564 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13565 "TARGET_32BIT && reload_completed"
13566 [(set (match_dup 0)
13567 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13568 (set (match_dup 4)
13569 (compare:CC (match_dup 0)
13570 (const_int 0)))]
13571 "")
13573 (define_insn "*neg_geu<mode>"
13574 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13575 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13576 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13577 ""
13578 "@
13579 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
13580 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
13581 [(set_attr "type" "three")
13582 (set_attr "length" "12")])
13584 (define_insn "*and_neg_geu<mode>"
13585 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13586 (and:P (neg:P
13587 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13588 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13589 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13590 ""
13591 "@
13592 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
13593 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
13594 [(set_attr "type" "three")
13595 (set_attr "length" "12")])
13597 (define_insn ""
13598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13599 (compare:CC
13600 (and:SI (neg:SI
13601 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13602 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13603 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13604 (const_int 0)))
13605 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13606 "TARGET_32BIT"
13607 "@
13608 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
13609 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
13610 #
13611 #"
13612 [(set_attr "type" "compare")
13613 (set_attr "length" "12,12,16,16")])
13615 (define_split
13616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13617 (compare:CC
13618 (and:SI (neg:SI
13619 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13620 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13621 (match_operand:SI 3 "gpc_reg_operand" ""))
13622 (const_int 0)))
13623 (clobber (match_scratch:SI 4 ""))]
13624 "TARGET_32BIT && reload_completed"
13625 [(set (match_dup 4)
13626 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13627 (match_dup 3)))
13628 (set (match_dup 0)
13629 (compare:CC (match_dup 4)
13630 (const_int 0)))]
13631 "")
13633 (define_insn ""
13634 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13635 (compare:CC
13636 (and:SI (neg:SI
13637 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13638 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13639 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13640 (const_int 0)))
13641 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13642 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13643 "TARGET_32BIT"
13644 "@
13645 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
13646 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
13647 #
13648 #"
13649 [(set_attr "type" "compare")
13650 (set_attr "length" "12,12,16,16")])
13652 (define_split
13653 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13654 (compare:CC
13655 (and:SI (neg:SI
13656 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13657 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13658 (match_operand:SI 3 "gpc_reg_operand" ""))
13659 (const_int 0)))
13660 (set (match_operand:SI 0 "gpc_reg_operand" "")
13661 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13662 "TARGET_32BIT && reload_completed"
13663 [(set (match_dup 0)
13664 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13665 (set (match_dup 4)
13666 (compare:CC (match_dup 0)
13667 (const_int 0)))]
13668 "")
13670 (define_insn "*plus_gt0<mode>"
13671 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13672 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13673 (const_int 0))
13674 (match_operand:P 2 "gpc_reg_operand" "r")))]
13675 ""
13676 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13677 [(set_attr "type" "three")
13678 (set_attr "length" "12")])
13680 (define_insn ""
13681 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13682 (compare:CC
13683 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13684 (const_int 0))
13685 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13686 (const_int 0)))
13687 (clobber (match_scratch:SI 3 "=&r,&r"))]
13688 "TARGET_32BIT"
13689 "@
13690 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13691 #"
13692 [(set_attr "type" "compare")
13693 (set_attr "length" "12,16")])
13695 (define_split
13696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13697 (compare:CC
13698 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13699 (const_int 0))
13700 (match_operand:SI 2 "gpc_reg_operand" ""))
13701 (const_int 0)))
13702 (clobber (match_scratch:SI 3 ""))]
13703 "TARGET_32BIT && reload_completed"
13704 [(set (match_dup 3)
13705 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13706 (match_dup 2)))
13707 (set (match_dup 0)
13708 (compare:CC (match_dup 3)
13709 (const_int 0)))]
13710 "")
13712 (define_insn ""
13713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13714 (compare:CC
13715 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13716 (const_int 0))
13717 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13718 (const_int 0)))
13719 (clobber (match_scratch:DI 3 "=&r,&r"))]
13720 "TARGET_64BIT"
13721 "@
13722 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13723 #"
13724 [(set_attr "type" "compare")
13725 (set_attr "length" "12,16")])
13727 (define_split
13728 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13729 (compare:CC
13730 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13731 (const_int 0))
13732 (match_operand:DI 2 "gpc_reg_operand" ""))
13733 (const_int 0)))
13734 (clobber (match_scratch:DI 3 ""))]
13735 "TARGET_64BIT && reload_completed"
13736 [(set (match_dup 3)
13737 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13738 (match_dup 2)))
13739 (set (match_dup 0)
13740 (compare:CC (match_dup 3)
13741 (const_int 0)))]
13742 "")
13744 (define_insn ""
13745 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13746 (compare:CC
13747 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13748 (const_int 0))
13749 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13750 (const_int 0)))
13751 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13752 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13753 "TARGET_32BIT"
13754 "@
13755 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13756 #"
13757 [(set_attr "type" "compare")
13758 (set_attr "length" "12,16")])
13760 (define_split
13761 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13762 (compare:CC
13763 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13764 (const_int 0))
13765 (match_operand:SI 2 "gpc_reg_operand" ""))
13766 (const_int 0)))
13767 (set (match_operand:SI 0 "gpc_reg_operand" "")
13768 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13769 "TARGET_32BIT && reload_completed"
13770 [(set (match_dup 0)
13771 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13772 (set (match_dup 3)
13773 (compare:CC (match_dup 0)
13774 (const_int 0)))]
13775 "")
13777 (define_insn ""
13778 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13779 (compare:CC
13780 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13781 (const_int 0))
13782 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13783 (const_int 0)))
13784 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13785 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13786 "TARGET_64BIT"
13787 "@
13788 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13789 #"
13790 [(set_attr "type" "compare")
13791 (set_attr "length" "12,16")])
13793 (define_split
13794 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13795 (compare:CC
13796 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13797 (const_int 0))
13798 (match_operand:DI 2 "gpc_reg_operand" ""))
13799 (const_int 0)))
13800 (set (match_operand:DI 0 "gpc_reg_operand" "")
13801 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13802 "TARGET_64BIT && reload_completed"
13803 [(set (match_dup 0)
13804 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13805 (set (match_dup 3)
13806 (compare:CC (match_dup 0)
13807 (const_int 0)))]
13808 "")
13810 (define_insn_and_split "*gtu<mode>"
13811 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13812 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13813 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13814 ""
13815 "#"
13816 ""
13817 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13818 (set (match_dup 0) (neg:P (match_dup 0)))]
13819 "")
13821 (define_insn_and_split "*gtu<mode>_compare"
13822 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13823 (compare:CC
13824 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13825 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13826 (const_int 0)))
13827 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13828 (gtu:P (match_dup 1) (match_dup 2)))]
13829 ""
13830 "#"
13831 ""
13832 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13833 (parallel [(set (match_dup 3)
13834 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13835 (set (match_dup 0) (neg:P (match_dup 0)))])]
13836 "")
13838 (define_insn_and_split "*plus_gtu<mode>"
13839 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13840 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13841 (match_operand:P 2 "reg_or_short_operand" "rI"))
13842 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13843 ""
13844 "#"
13845 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13846 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13847 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13848 "")
13850 (define_insn_and_split "*plus_gtu<mode>_compare"
13851 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13852 (compare:CC
13853 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13854 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13855 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13856 (const_int 0)))
13857 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13858 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13859 ""
13860 "#"
13861 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13862 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13863 (parallel [(set (match_dup 4)
13864 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13865 (const_int 0)))
13866 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13867 "")
13869 (define_insn "*neg_gtu<mode>"
13870 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13871 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13872 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13873 ""
13874 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13875 [(set_attr "type" "two")
13876 (set_attr "length" "8")])
13878 \f
13879 ;; Define both directions of branch and return. If we need a reload
13880 ;; register, we'd rather use CR0 since it is much easier to copy a
13881 ;; register CC value to there.
13883 (define_insn ""
13884 [(set (pc)
13885 (if_then_else (match_operator 1 "branch_comparison_operator"
13886 [(match_operand 2
13887 "cc_reg_operand" "y")
13888 (const_int 0)])
13889 (label_ref (match_operand 0 "" ""))
13890 (pc)))]
13891 ""
13892 "*
13893 {
13894 return output_cbranch (operands[1], \"%l0\", 0, insn);
13895 }"
13896 [(set_attr "type" "branch")])
13898 (define_insn ""
13899 [(set (pc)
13900 (if_then_else (match_operator 0 "branch_comparison_operator"
13901 [(match_operand 1
13902 "cc_reg_operand" "y")
13903 (const_int 0)])
13904 (any_return)
13905 (pc)))]
13906 "<return_pred>"
13907 "*
13908 {
13909 return output_cbranch (operands[0], NULL, 0, insn);
13910 }"
13911 [(set_attr "type" "jmpreg")
13912 (set_attr "length" "4")])
13914 (define_insn ""
13915 [(set (pc)
13916 (if_then_else (match_operator 1 "branch_comparison_operator"
13917 [(match_operand 2
13918 "cc_reg_operand" "y")
13919 (const_int 0)])
13920 (pc)
13921 (label_ref (match_operand 0 "" ""))))]
13922 ""
13923 "*
13924 {
13925 return output_cbranch (operands[1], \"%l0\", 1, insn);
13926 }"
13927 [(set_attr "type" "branch")])
13929 (define_insn ""
13930 [(set (pc)
13931 (if_then_else (match_operator 0 "branch_comparison_operator"
13932 [(match_operand 1
13933 "cc_reg_operand" "y")
13934 (const_int 0)])
13935 (pc)
13936 (any_return)))]
13937 "<return_pred>"
13938 "*
13939 {
13940 return output_cbranch (operands[0], NULL, 1, insn);
13941 }"
13942 [(set_attr "type" "jmpreg")
13943 (set_attr "length" "4")])
13945 ;; Logic on condition register values.
13947 ; This pattern matches things like
13948 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13949 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13950 ; (const_int 1)))
13951 ; which are generated by the branch logic.
13952 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13954 (define_insn "*cceq_ior_compare"
13955 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13956 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13957 [(match_operator:SI 2
13958 "branch_positive_comparison_operator"
13959 [(match_operand 3
13960 "cc_reg_operand" "y,y")
13961 (const_int 0)])
13962 (match_operator:SI 4
13963 "branch_positive_comparison_operator"
13964 [(match_operand 5
13965 "cc_reg_operand" "0,y")
13966 (const_int 0)])])
13967 (const_int 1)))]
13968 ""
13969 "cr%q1 %E0,%j2,%j4"
13970 [(set_attr "type" "cr_logical,delayed_cr")])
13972 ; Why is the constant -1 here, but 1 in the previous pattern?
13973 ; Because ~1 has all but the low bit set.
13974 (define_insn ""
13975 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13976 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13977 [(not:SI (match_operator:SI 2
13978 "branch_positive_comparison_operator"
13979 [(match_operand 3
13980 "cc_reg_operand" "y,y")
13981 (const_int 0)]))
13982 (match_operator:SI 4
13983 "branch_positive_comparison_operator"
13984 [(match_operand 5
13985 "cc_reg_operand" "0,y")
13986 (const_int 0)])])
13987 (const_int -1)))]
13988 ""
13989 "cr%q1 %E0,%j2,%j4"
13990 [(set_attr "type" "cr_logical,delayed_cr")])
13992 (define_insn "*cceq_rev_compare"
13993 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13994 (compare:CCEQ (match_operator:SI 1
13995 "branch_positive_comparison_operator"
13996 [(match_operand 2
13997 "cc_reg_operand" "0,y")
13998 (const_int 0)])
13999 (const_int 0)))]
14000 ""
14001 "crnot %E0,%j1"
14002 [(set_attr "type" "cr_logical,delayed_cr")])
14004 ;; If we are comparing the result of two comparisons, this can be done
14005 ;; using creqv or crxor.
14007 (define_insn_and_split ""
14008 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14009 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14010 [(match_operand 2 "cc_reg_operand" "y")
14011 (const_int 0)])
14012 (match_operator 3 "branch_comparison_operator"
14013 [(match_operand 4 "cc_reg_operand" "y")
14014 (const_int 0)])))]
14015 ""
14016 "#"
14017 ""
14018 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14019 (match_dup 5)))]
14020 "
14021 {
14022 int positive_1, positive_2;
14024 positive_1 = branch_positive_comparison_operator (operands[1],
14025 GET_MODE (operands[1]));
14026 positive_2 = branch_positive_comparison_operator (operands[3],
14027 GET_MODE (operands[3]));
14029 if (! positive_1)
14030 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14031 GET_CODE (operands[1])),
14032 SImode,
14033 operands[2], const0_rtx);
14034 else if (GET_MODE (operands[1]) != SImode)
14035 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14036 operands[2], const0_rtx);
14038 if (! positive_2)
14039 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14040 GET_CODE (operands[3])),
14041 SImode,
14042 operands[4], const0_rtx);
14043 else if (GET_MODE (operands[3]) != SImode)
14044 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14045 operands[4], const0_rtx);
14047 if (positive_1 == positive_2)
14048 {
14049 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14050 operands[5] = constm1_rtx;
14051 }
14052 else
14053 {
14054 operands[5] = const1_rtx;
14055 }
14056 }")
14058 ;; Unconditional branch and return.
14060 (define_insn "jump"
14061 [(set (pc)
14062 (label_ref (match_operand 0 "" "")))]
14063 ""
14064 "b %l0"
14065 [(set_attr "type" "branch")])
14067 (define_insn "<return_str>return"
14068 [(any_return)]
14069 "<return_pred>"
14070 "blr"
14071 [(set_attr "type" "jmpreg")])
14073 (define_expand "indirect_jump"
14074 [(set (pc) (match_operand 0 "register_operand" ""))])
14076 (define_insn "*indirect_jump<mode>"
14077 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14078 ""
14079 "@
14080 bctr
14081 blr"
14082 [(set_attr "type" "jmpreg")])
14084 ;; Table jump for switch statements:
14085 (define_expand "tablejump"
14086 [(use (match_operand 0 "" ""))
14087 (use (label_ref (match_operand 1 "" "")))]
14088 ""
14089 "
14090 {
14091 if (TARGET_32BIT)
14092 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14093 else
14094 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14095 DONE;
14096 }")
14098 (define_expand "tablejumpsi"
14099 [(set (match_dup 3)
14100 (plus:SI (match_operand:SI 0 "" "")
14101 (match_dup 2)))
14102 (parallel [(set (pc) (match_dup 3))
14103 (use (label_ref (match_operand 1 "" "")))])]
14104 "TARGET_32BIT"
14105 "
14106 { operands[0] = force_reg (SImode, operands[0]);
14107 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14108 operands[3] = gen_reg_rtx (SImode);
14109 }")
14111 (define_expand "tablejumpdi"
14112 [(set (match_dup 4)
14113 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14114 (set (match_dup 3)
14115 (plus:DI (match_dup 4)
14116 (match_dup 2)))
14117 (parallel [(set (pc) (match_dup 3))
14118 (use (label_ref (match_operand 1 "" "")))])]
14119 "TARGET_64BIT"
14120 "
14121 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14122 operands[3] = gen_reg_rtx (DImode);
14123 operands[4] = gen_reg_rtx (DImode);
14124 }")
14126 (define_insn "*tablejump<mode>_internal1"
14127 [(set (pc)
14128 (match_operand:P 0 "register_operand" "c,*l"))
14129 (use (label_ref (match_operand 1 "" "")))]
14130 ""
14131 "@
14132 bctr
14133 blr"
14134 [(set_attr "type" "jmpreg")])
14136 (define_insn "nop"
14137 [(const_int 0)]
14138 ""
14139 "nop")
14141 (define_insn "group_ending_nop"
14142 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14143 ""
14144 "*
14145 {
14146 if (rs6000_cpu_attr == CPU_POWER6)
14147 return \"ori 1,1,0\";
14148 return \"ori 2,2,0\";
14149 }")
14150 \f
14151 ;; Define the subtract-one-and-jump insns, starting with the template
14152 ;; so loop.c knows what to generate.
14154 (define_expand "doloop_end"
14155 [(use (match_operand 0 "" "")) ; loop pseudo
14156 (use (match_operand 1 "" ""))] ; label
14157 ""
14158 "
14159 {
14160 if (TARGET_64BIT)
14161 {
14162 if (GET_MODE (operands[0]) != DImode)
14163 FAIL;
14164 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
14165 }
14166 else
14167 {
14168 if (GET_MODE (operands[0]) != SImode)
14169 FAIL;
14170 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
14171 }
14172 DONE;
14173 }")
14175 (define_expand "ctr<mode>"
14176 [(parallel [(set (pc)
14177 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14178 (const_int 1))
14179 (label_ref (match_operand 1 "" ""))
14180 (pc)))
14181 (set (match_dup 0)
14182 (plus:P (match_dup 0)
14183 (const_int -1)))
14184 (clobber (match_scratch:CC 2 ""))
14185 (clobber (match_scratch:P 3 ""))])]
14186 ""
14187 "")
14189 ;; We need to be able to do this for any operand, including MEM, or we
14190 ;; will cause reload to blow up since we don't allow output reloads on
14191 ;; JUMP_INSNs.
14192 ;; For the length attribute to be calculated correctly, the
14193 ;; label MUST be operand 0.
14195 (define_insn "*ctr<mode>_internal1"
14196 [(set (pc)
14197 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14198 (const_int 1))
14199 (label_ref (match_operand 0 "" ""))
14200 (pc)))
14201 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14202 (plus:P (match_dup 1)
14203 (const_int -1)))
14204 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14205 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14206 ""
14207 "*
14208 {
14209 if (which_alternative != 0)
14210 return \"#\";
14211 else if (get_attr_length (insn) == 4)
14212 return \"bdnz %l0\";
14213 else
14214 return \"bdz $+8\;b %l0\";
14215 }"
14216 [(set_attr "type" "branch")
14217 (set_attr "length" "*,12,16,16")])
14219 (define_insn "*ctr<mode>_internal2"
14220 [(set (pc)
14221 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14222 (const_int 1))
14223 (pc)
14224 (label_ref (match_operand 0 "" ""))))
14225 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14226 (plus:P (match_dup 1)
14227 (const_int -1)))
14228 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14229 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14230 ""
14231 "*
14232 {
14233 if (which_alternative != 0)
14234 return \"#\";
14235 else if (get_attr_length (insn) == 4)
14236 return \"bdz %l0\";
14237 else
14238 return \"bdnz $+8\;b %l0\";
14239 }"
14240 [(set_attr "type" "branch")
14241 (set_attr "length" "*,12,16,16")])
14243 ;; Similar but use EQ
14245 (define_insn "*ctr<mode>_internal5"
14246 [(set (pc)
14247 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14248 (const_int 1))
14249 (label_ref (match_operand 0 "" ""))
14250 (pc)))
14251 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14252 (plus:P (match_dup 1)
14253 (const_int -1)))
14254 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14255 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14256 ""
14257 "*
14258 {
14259 if (which_alternative != 0)
14260 return \"#\";
14261 else if (get_attr_length (insn) == 4)
14262 return \"bdz %l0\";
14263 else
14264 return \"bdnz $+8\;b %l0\";
14265 }"
14266 [(set_attr "type" "branch")
14267 (set_attr "length" "*,12,16,16")])
14269 (define_insn "*ctr<mode>_internal6"
14270 [(set (pc)
14271 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14272 (const_int 1))
14273 (pc)
14274 (label_ref (match_operand 0 "" ""))))
14275 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14276 (plus:P (match_dup 1)
14277 (const_int -1)))
14278 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14279 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14280 ""
14281 "*
14282 {
14283 if (which_alternative != 0)
14284 return \"#\";
14285 else if (get_attr_length (insn) == 4)
14286 return \"bdnz %l0\";
14287 else
14288 return \"bdz $+8\;b %l0\";
14289 }"
14290 [(set_attr "type" "branch")
14291 (set_attr "length" "*,12,16,16")])
14293 ;; Now the splitters if we could not allocate the CTR register
14295 (define_split
14296 [(set (pc)
14297 (if_then_else (match_operator 2 "comparison_operator"
14298 [(match_operand:P 1 "gpc_reg_operand" "")
14299 (const_int 1)])
14300 (match_operand 5 "" "")
14301 (match_operand 6 "" "")))
14302 (set (match_operand:P 0 "gpc_reg_operand" "")
14303 (plus:P (match_dup 1) (const_int -1)))
14304 (clobber (match_scratch:CC 3 ""))
14305 (clobber (match_scratch:P 4 ""))]
14306 "reload_completed"
14307 [(parallel [(set (match_dup 3)
14308 (compare:CC (plus:P (match_dup 1)
14309 (const_int -1))
14310 (const_int 0)))
14311 (set (match_dup 0)
14312 (plus:P (match_dup 1)
14313 (const_int -1)))])
14314 (set (pc) (if_then_else (match_dup 7)
14315 (match_dup 5)
14316 (match_dup 6)))]
14317 "
14318 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14319 operands[3], const0_rtx); }")
14321 (define_split
14322 [(set (pc)
14323 (if_then_else (match_operator 2 "comparison_operator"
14324 [(match_operand:P 1 "gpc_reg_operand" "")
14325 (const_int 1)])
14326 (match_operand 5 "" "")
14327 (match_operand 6 "" "")))
14328 (set (match_operand:P 0 "nonimmediate_operand" "")
14329 (plus:P (match_dup 1) (const_int -1)))
14330 (clobber (match_scratch:CC 3 ""))
14331 (clobber (match_scratch:P 4 ""))]
14332 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14333 [(parallel [(set (match_dup 3)
14334 (compare:CC (plus:P (match_dup 1)
14335 (const_int -1))
14336 (const_int 0)))
14337 (set (match_dup 4)
14338 (plus:P (match_dup 1)
14339 (const_int -1)))])
14340 (set (match_dup 0)
14341 (match_dup 4))
14342 (set (pc) (if_then_else (match_dup 7)
14343 (match_dup 5)
14344 (match_dup 6)))]
14345 "
14346 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14347 operands[3], const0_rtx); }")
14348 \f
14349 (define_insn "trap"
14350 [(trap_if (const_int 1) (const_int 0))]
14351 ""
14352 "trap"
14353 [(set_attr "type" "trap")])
14355 (define_expand "ctrap<mode>4"
14356 [(trap_if (match_operator 0 "ordered_comparison_operator"
14357 [(match_operand:GPR 1 "register_operand")
14358 (match_operand:GPR 2 "reg_or_short_operand")])
14359 (match_operand 3 "zero_constant" ""))]
14360 ""
14361 "")
14363 (define_insn ""
14364 [(trap_if (match_operator 0 "ordered_comparison_operator"
14365 [(match_operand:GPR 1 "register_operand" "r")
14366 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14367 (const_int 0))]
14368 ""
14369 "t<wd>%V0%I2 %1,%2"
14370 [(set_attr "type" "trap")])
14371 \f
14372 ;; Insns related to generating the function prologue and epilogue.
14374 (define_expand "prologue"
14375 [(use (const_int 0))]
14376 ""
14377 {
14378 rs6000_emit_prologue ();
14379 if (!TARGET_SCHED_PROLOG)
14380 emit_insn (gen_blockage ());
14381 DONE;
14382 })
14384 (define_insn "*movesi_from_cr_one"
14385 [(match_parallel 0 "mfcr_operation"
14386 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14387 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14388 (match_operand 3 "immediate_operand" "n")]
14389 UNSPEC_MOVESI_FROM_CR))])]
14390 "TARGET_MFCRF"
14391 "*
14392 {
14393 int mask = 0;
14394 int i;
14395 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14396 {
14397 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14398 operands[4] = GEN_INT (mask);
14399 output_asm_insn (\"mfcr %1,%4\", operands);
14400 }
14401 return \"\";
14402 }"
14403 [(set_attr "type" "mfcrf")])
14405 (define_insn "movesi_from_cr"
14406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14407 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14408 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14409 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14410 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14411 UNSPEC_MOVESI_FROM_CR))]
14412 ""
14413 "mfcr %0"
14414 [(set_attr "type" "mfcr")])
14416 (define_insn "*crsave"
14417 [(match_parallel 0 "crsave_operation"
14418 [(set (match_operand:SI 1 "memory_operand" "=m")
14419 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14420 ""
14421 "stw %2,%1"
14422 [(set_attr "type" "store")])
14424 (define_insn "*stmw"
14425 [(match_parallel 0 "stmw_operation"
14426 [(set (match_operand:SI 1 "memory_operand" "=m")
14427 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14428 "TARGET_MULTIPLE"
14429 "stmw %2,%1"
14430 [(set_attr "type" "store")
14431 (set_attr "update" "yes")
14432 (set_attr "indexed" "yes")])
14434 ; The following comment applies to:
14435 ; save_gpregs_*
14436 ; save_fpregs_*
14437 ; restore_gpregs*
14438 ; return_and_restore_gpregs*
14439 ; return_and_restore_fpregs*
14440 ; return_and_restore_fpregs_aix*
14441 ;
14442 ; The out-of-line save / restore functions expects one input argument.
14443 ; Since those are not standard call_insn's, we must avoid using
14444 ; MATCH_OPERAND for that argument. That way the register rename
14445 ; optimization will not try to rename this register.
14446 ; Each pattern is repeated for each possible register number used in
14447 ; various ABIs (r11, r1, and for some functions r12)
14449 (define_insn "*save_gpregs_<mode>_r11"
14450 [(match_parallel 0 "any_parallel_operand"
14451 [(clobber (reg:P 65))
14452 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14453 (use (reg:P 11))
14454 (set (match_operand:P 2 "memory_operand" "=m")
14455 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14456 ""
14457 "bl %1"
14458 [(set_attr "type" "branch")
14459 (set_attr "length" "4")])
14461 (define_insn "*save_gpregs_<mode>_r12"
14462 [(match_parallel 0 "any_parallel_operand"
14463 [(clobber (reg:P 65))
14464 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14465 (use (reg:P 12))
14466 (set (match_operand:P 2 "memory_operand" "=m")
14467 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14468 ""
14469 "bl %1"
14470 [(set_attr "type" "branch")
14471 (set_attr "length" "4")])
14473 (define_insn "*save_gpregs_<mode>_r1"
14474 [(match_parallel 0 "any_parallel_operand"
14475 [(clobber (reg:P 65))
14476 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14477 (use (reg:P 1))
14478 (set (match_operand:P 2 "memory_operand" "=m")
14479 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14480 ""
14481 "bl %1"
14482 [(set_attr "type" "branch")
14483 (set_attr "length" "4")])
14485 (define_insn "*save_fpregs_<mode>_r11"
14486 [(match_parallel 0 "any_parallel_operand"
14487 [(clobber (reg:P 65))
14488 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14489 (use (reg:P 11))
14490 (set (match_operand:DF 2 "memory_operand" "=m")
14491 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14492 ""
14493 "bl %1"
14494 [(set_attr "type" "branch")
14495 (set_attr "length" "4")])
14497 (define_insn "*save_fpregs_<mode>_r12"
14498 [(match_parallel 0 "any_parallel_operand"
14499 [(clobber (reg:P 65))
14500 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14501 (use (reg:P 12))
14502 (set (match_operand:DF 2 "memory_operand" "=m")
14503 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14504 ""
14505 "bl %1"
14506 [(set_attr "type" "branch")
14507 (set_attr "length" "4")])
14509 (define_insn "*save_fpregs_<mode>_r1"
14510 [(match_parallel 0 "any_parallel_operand"
14511 [(clobber (reg:P 65))
14512 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14513 (use (reg:P 1))
14514 (set (match_operand:DF 2 "memory_operand" "=m")
14515 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14516 ""
14517 "bl %1"
14518 [(set_attr "type" "branch")
14519 (set_attr "length" "4")])
14521 ; This is to explain that changes to the stack pointer should
14522 ; not be moved over loads from or stores to stack memory.
14523 (define_insn "stack_tie"
14524 [(match_parallel 0 "tie_operand"
14525 [(set (mem:BLK (reg 1)) (const_int 0))])]
14526 ""
14527 ""
14528 [(set_attr "length" "0")])
14530 (define_expand "epilogue"
14531 [(use (const_int 0))]
14532 ""
14533 {
14534 if (!TARGET_SCHED_PROLOG)
14535 emit_insn (gen_blockage ());
14536 rs6000_emit_epilogue (FALSE);
14537 DONE;
14538 })
14540 ; On some processors, doing the mtcrf one CC register at a time is
14541 ; faster (like on the 604e). On others, doing them all at once is
14542 ; faster; for instance, on the 601 and 750.
14544 (define_expand "movsi_to_cr_one"
14545 [(set (match_operand:CC 0 "cc_reg_operand" "")
14546 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14547 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14548 ""
14549 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14551 (define_insn "*movsi_to_cr"
14552 [(match_parallel 0 "mtcrf_operation"
14553 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14554 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14555 (match_operand 3 "immediate_operand" "n")]
14556 UNSPEC_MOVESI_TO_CR))])]
14557 ""
14558 "*
14559 {
14560 int mask = 0;
14561 int i;
14562 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14563 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14564 operands[4] = GEN_INT (mask);
14565 return \"mtcrf %4,%2\";
14566 }"
14567 [(set_attr "type" "mtcr")])
14569 (define_insn "*mtcrfsi"
14570 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14571 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14572 (match_operand 2 "immediate_operand" "n")]
14573 UNSPEC_MOVESI_TO_CR))]
14574 "GET_CODE (operands[0]) == REG
14575 && CR_REGNO_P (REGNO (operands[0]))
14576 && GET_CODE (operands[2]) == CONST_INT
14577 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14578 "mtcrf %R0,%1"
14579 [(set_attr "type" "mtcr")])
14581 ; The load-multiple instructions have similar properties.
14582 ; Note that "load_multiple" is a name known to the machine-independent
14583 ; code that actually corresponds to the PowerPC load-string.
14585 (define_insn "*lmw"
14586 [(match_parallel 0 "lmw_operation"
14587 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14588 (match_operand:SI 2 "memory_operand" "m"))])]
14589 "TARGET_MULTIPLE"
14590 "lmw %1,%2"
14591 [(set_attr "type" "load")
14592 (set_attr "update" "yes")
14593 (set_attr "indexed" "yes")
14594 (set_attr "cell_micro" "always")])
14596 (define_insn "*return_internal_<mode>"
14597 [(simple_return)
14598 (use (match_operand:P 0 "register_operand" "lc"))]
14599 ""
14600 "b%T0"
14601 [(set_attr "type" "jmpreg")])
14603 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14604 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14606 ; The following comment applies to:
14607 ; save_gpregs_*
14608 ; save_fpregs_*
14609 ; restore_gpregs*
14610 ; return_and_restore_gpregs*
14611 ; return_and_restore_fpregs*
14612 ; return_and_restore_fpregs_aix*
14613 ;
14614 ; The out-of-line save / restore functions expects one input argument.
14615 ; Since those are not standard call_insn's, we must avoid using
14616 ; MATCH_OPERAND for that argument. That way the register rename
14617 ; optimization will not try to rename this register.
14618 ; Each pattern is repeated for each possible register number used in
14619 ; various ABIs (r11, r1, and for some functions r12)
14621 (define_insn "*restore_gpregs_<mode>_r11"
14622 [(match_parallel 0 "any_parallel_operand"
14623 [(clobber (match_operand:P 1 "register_operand" "=l"))
14624 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14625 (use (reg:P 11))
14626 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14627 (match_operand:P 4 "memory_operand" "m"))])]
14628 ""
14629 "bl %2"
14630 [(set_attr "type" "branch")
14631 (set_attr "length" "4")])
14633 (define_insn "*restore_gpregs_<mode>_r12"
14634 [(match_parallel 0 "any_parallel_operand"
14635 [(clobber (match_operand:P 1 "register_operand" "=l"))
14636 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14637 (use (reg:P 12))
14638 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14639 (match_operand:P 4 "memory_operand" "m"))])]
14640 ""
14641 "bl %2"
14642 [(set_attr "type" "branch")
14643 (set_attr "length" "4")])
14645 (define_insn "*restore_gpregs_<mode>_r1"
14646 [(match_parallel 0 "any_parallel_operand"
14647 [(clobber (match_operand:P 1 "register_operand" "=l"))
14648 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14649 (use (reg:P 1))
14650 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14651 (match_operand:P 4 "memory_operand" "m"))])]
14652 ""
14653 "bl %2"
14654 [(set_attr "type" "branch")
14655 (set_attr "length" "4")])
14657 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14658 [(match_parallel 0 "any_parallel_operand"
14659 [(return)
14660 (clobber (match_operand:P 1 "register_operand" "=l"))
14661 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14662 (use (reg:P 11))
14663 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14664 (match_operand:P 4 "memory_operand" "m"))])]
14665 ""
14666 "b %2"
14667 [(set_attr "type" "branch")
14668 (set_attr "length" "4")])
14670 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14671 [(match_parallel 0 "any_parallel_operand"
14672 [(return)
14673 (clobber (match_operand:P 1 "register_operand" "=l"))
14674 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14675 (use (reg:P 12))
14676 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14677 (match_operand:P 4 "memory_operand" "m"))])]
14678 ""
14679 "b %2"
14680 [(set_attr "type" "branch")
14681 (set_attr "length" "4")])
14683 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14684 [(match_parallel 0 "any_parallel_operand"
14685 [(return)
14686 (clobber (match_operand:P 1 "register_operand" "=l"))
14687 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14688 (use (reg:P 1))
14689 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14690 (match_operand:P 4 "memory_operand" "m"))])]
14691 ""
14692 "b %2"
14693 [(set_attr "type" "branch")
14694 (set_attr "length" "4")])
14696 (define_insn "*return_and_restore_fpregs_<mode>_r11"
14697 [(match_parallel 0 "any_parallel_operand"
14698 [(return)
14699 (clobber (match_operand:P 1 "register_operand" "=l"))
14700 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14701 (use (reg:P 11))
14702 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14703 (match_operand:DF 4 "memory_operand" "m"))])]
14704 ""
14705 "b %2"
14706 [(set_attr "type" "branch")
14707 (set_attr "length" "4")])
14709 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14710 [(match_parallel 0 "any_parallel_operand"
14711 [(return)
14712 (clobber (match_operand:P 1 "register_operand" "=l"))
14713 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14714 (use (reg:P 12))
14715 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14716 (match_operand:DF 4 "memory_operand" "m"))])]
14717 ""
14718 "b %2"
14719 [(set_attr "type" "branch")
14720 (set_attr "length" "4")])
14722 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14723 [(match_parallel 0 "any_parallel_operand"
14724 [(return)
14725 (clobber (match_operand:P 1 "register_operand" "=l"))
14726 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14727 (use (reg:P 1))
14728 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14729 (match_operand:DF 4 "memory_operand" "m"))])]
14730 ""
14731 "b %2"
14732 [(set_attr "type" "branch")
14733 (set_attr "length" "4")])
14735 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14736 [(match_parallel 0 "any_parallel_operand"
14737 [(return)
14738 (use (match_operand:P 1 "register_operand" "l"))
14739 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14740 (use (reg:P 11))
14741 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14742 (match_operand:DF 4 "memory_operand" "m"))])]
14743 ""
14744 "b %2"
14745 [(set_attr "type" "branch")
14746 (set_attr "length" "4")])
14748 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14749 [(match_parallel 0 "any_parallel_operand"
14750 [(return)
14751 (use (match_operand:P 1 "register_operand" "l"))
14752 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14753 (use (reg:P 1))
14754 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14755 (match_operand:DF 4 "memory_operand" "m"))])]
14756 ""
14757 "b %2"
14758 [(set_attr "type" "branch")
14759 (set_attr "length" "4")])
14761 ; This is used in compiling the unwind routines.
14762 (define_expand "eh_return"
14763 [(use (match_operand 0 "general_operand" ""))]
14764 ""
14765 "
14766 {
14767 if (TARGET_32BIT)
14768 emit_insn (gen_eh_set_lr_si (operands[0]));
14769 else
14770 emit_insn (gen_eh_set_lr_di (operands[0]));
14771 DONE;
14772 }")
14774 ; We can't expand this before we know where the link register is stored.
14775 (define_insn "eh_set_lr_<mode>"
14776 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14777 UNSPECV_EH_RR)
14778 (clobber (match_scratch:P 1 "=&b"))]
14779 ""
14780 "#")
14782 (define_split
14783 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14784 (clobber (match_scratch 1 ""))]
14785 "reload_completed"
14786 [(const_int 0)]
14787 "
14788 {
14789 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14790 DONE;
14791 }")
14793 (define_insn "prefetch"
14794 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14795 (match_operand:SI 1 "const_int_operand" "n")
14796 (match_operand:SI 2 "const_int_operand" "n"))]
14797 ""
14798 "*
14799 {
14800 if (GET_CODE (operands[0]) == REG)
14801 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14802 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14803 }"
14804 [(set_attr "type" "load")])
14805 \f
14806 (define_insn "bpermd_<mode>"
14807 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14808 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14809 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14810 "TARGET_POPCNTD"
14811 "bpermd %0,%1,%2"
14812 [(set_attr "type" "popcnt")])
14814 \f
14815 ;; Builtin fma support. Handle
14816 ;; Note that the conditions for expansion are in the FMA_F iterator.
14818 (define_expand "fma<mode>4"
14819 [(set (match_operand:FMA_F 0 "register_operand" "")
14820 (fma:FMA_F
14821 (match_operand:FMA_F 1 "register_operand" "")
14822 (match_operand:FMA_F 2 "register_operand" "")
14823 (match_operand:FMA_F 3 "register_operand" "")))]
14824 ""
14825 "")
14827 (define_insn "*fma<mode>4_fpr"
14828 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14829 (fma:SFDF
14830 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
14831 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14832 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
14833 "TARGET_<MODE>_FPR"
14834 "@
14835 fmadd<Ftrad> %0,%1,%2,%3
14836 xsmadda<Fvsx> %x0,%x1,%x2
14837 xsmaddm<Fvsx> %x0,%x1,%x3"
14838 [(set_attr "type" "fp")
14839 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14841 ; Altivec only has fma and nfms.
14842 (define_expand "fms<mode>4"
14843 [(set (match_operand:FMA_F 0 "register_operand" "")
14844 (fma:FMA_F
14845 (match_operand:FMA_F 1 "register_operand" "")
14846 (match_operand:FMA_F 2 "register_operand" "")
14847 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14848 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14849 "")
14851 (define_insn "*fms<mode>4_fpr"
14852 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14853 (fma:SFDF
14854 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14855 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14856 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14857 "TARGET_<MODE>_FPR"
14858 "@
14859 fmsub<Ftrad> %0,%1,%2,%3
14860 xsmsuba<Fvsx> %x0,%x1,%x2
14861 xsmsubm<Fvsx> %x0,%x1,%x3"
14862 [(set_attr "type" "fp")
14863 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14865 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14866 (define_expand "fnma<mode>4"
14867 [(set (match_operand:FMA_F 0 "register_operand" "")
14868 (neg:FMA_F
14869 (fma:FMA_F
14870 (match_operand:FMA_F 1 "register_operand" "")
14871 (match_operand:FMA_F 2 "register_operand" "")
14872 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14873 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14874 "")
14876 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14877 (define_expand "fnms<mode>4"
14878 [(set (match_operand:FMA_F 0 "register_operand" "")
14879 (neg:FMA_F
14880 (fma:FMA_F
14881 (match_operand:FMA_F 1 "register_operand" "")
14882 (match_operand:FMA_F 2 "register_operand" "")
14883 (match_operand:FMA_F 3 "register_operand" ""))))]
14884 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14885 "")
14887 ; Not an official optab name, but used from builtins.
14888 (define_expand "nfma<mode>4"
14889 [(set (match_operand:FMA_F 0 "register_operand" "")
14890 (neg:FMA_F
14891 (fma:FMA_F
14892 (match_operand:FMA_F 1 "register_operand" "")
14893 (match_operand:FMA_F 2 "register_operand" "")
14894 (match_operand:FMA_F 3 "register_operand" ""))))]
14895 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14896 "")
14898 (define_insn "*nfma<mode>4_fpr"
14899 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14900 (neg:SFDF
14901 (fma:SFDF
14902 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14903 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14904 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
14905 "TARGET_<MODE>_FPR"
14906 "@
14907 fnmadd<Ftrad> %0,%1,%2,%3
14908 xsnmadda<Fvsx> %x0,%x1,%x2
14909 xsnmaddm<Fvsx> %x0,%x1,%x3"
14910 [(set_attr "type" "fp")
14911 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14913 ; Not an official optab name, but used from builtins.
14914 (define_expand "nfms<mode>4"
14915 [(set (match_operand:FMA_F 0 "register_operand" "")
14916 (neg:FMA_F
14917 (fma:FMA_F
14918 (match_operand:FMA_F 1 "register_operand" "")
14919 (match_operand:FMA_F 2 "register_operand" "")
14920 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14921 ""
14922 "")
14924 (define_insn "*nfmssf4_fpr"
14925 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
14926 (neg:SFDF
14927 (fma:SFDF
14928 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
14929 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
14930 (neg:SFDF
14931 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
14932 "TARGET_<MODE>_FPR"
14933 "@
14934 fnmsub<Ftrad> %0,%1,%2,%3
14935 xsnmsuba<Fvsx> %x0,%x1,%x2
14936 xsnmsubm<Fvsx> %x0,%x1,%x3"
14937 [(set_attr "type" "fp")
14938 (set_attr "fp_type" "fp_maddsub_<Fs>")])
14940 \f
14941 (define_expand "rs6000_get_timebase"
14942 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
14943 ""
14944 {
14945 if (TARGET_POWERPC64)
14946 emit_insn (gen_rs6000_mftb_di (operands[0]));
14947 else
14948 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
14949 DONE;
14950 })
14952 (define_insn "rs6000_get_timebase_ppc32"
14953 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
14954 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
14955 (clobber (match_scratch:SI 1 "=r"))
14956 (clobber (match_scratch:CC 2 "=y"))]
14957 "!TARGET_POWERPC64"
14958 {
14959 if (WORDS_BIG_ENDIAN)
14960 if (TARGET_MFCRF)
14961 {
14962 return "mfspr %0,269\;"
14963 "mfspr %L0,268\;"
14964 "mfspr %1,269\;"
14965 "cmpw %2,%0,%1\;"
14966 "bne- %2,$-16";
14967 }
14968 else
14969 {
14970 return "mftbu %0\;"
14971 "mftb %L0\;"
14972 "mftbu %1\;"
14973 "cmpw %2,%0,%1\;"
14974 "bne- %2,$-16";
14975 }
14976 else
14977 if (TARGET_MFCRF)
14978 {
14979 return "mfspr %L0,269\;"
14980 "mfspr %0,268\;"
14981 "mfspr %1,269\;"
14982 "cmpw %2,%L0,%1\;"
14983 "bne- %2,$-16";
14984 }
14985 else
14986 {
14987 return "mftbu %L0\;"
14988 "mftb %0\;"
14989 "mftbu %1\;"
14990 "cmpw %2,%L0,%1\;"
14991 "bne- %2,$-16";
14992 }
14993 }
14994 [(set_attr "length" "20")])
14996 (define_insn "rs6000_mftb_<mode>"
14997 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14998 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
14999 ""
15000 {
15001 if (TARGET_MFCRF)
15002 return "mfspr %0,268";
15003 else
15004 return "mftb %0";
15005 })
15007 \f
15008 (define_insn "rs6000_mffs"
15009 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
15010 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
15011 "TARGET_HARD_FLOAT && TARGET_FPRS"
15012 "mffs %0")
15014 (define_insn "rs6000_mtfsf"
15015 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
15016 (match_operand:DF 1 "gpc_reg_operand" "d")]
15017 UNSPECV_MTFSF)]
15018 "TARGET_HARD_FLOAT && TARGET_FPRS"
15019 "mtfsf %0,%1")
15021 \f
15022 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
15023 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
15024 ;; register that is being loaded. The fused ops must be physically adjacent.
15026 ;; We use define_peephole for the actual addis/load, and the register used to
15027 ;; hold the addis value must be the same as the register being loaded. We use
15028 ;; define_peephole2 to change the register used for addis to be the register
15029 ;; being loaded, since we can look at whether it is dead after the load insn.
15031 (define_peephole
15032 [(set (match_operand:P 0 "base_reg_operand" "")
15033 (match_operand:P 1 "fusion_gpr_addis" ""))
15034 (set (match_operand:INT1 2 "base_reg_operand" "")
15035 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15036 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
15037 {
15038 return emit_fusion_gpr_load (operands);
15039 }
15040 [(set_attr "type" "load")
15041 (set_attr "length" "8")])
15043 (define_peephole2
15044 [(set (match_operand:P 0 "base_reg_operand" "")
15045 (match_operand:P 1 "fusion_gpr_addis" ""))
15046 (set (match_operand:INT1 2 "base_reg_operand" "")
15047 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15048 "TARGET_P8_FUSION
15049 && (REGNO (operands[0]) != REGNO (operands[2])
15050 || GET_CODE (operands[3]) == SIGN_EXTEND)
15051 && fusion_gpr_load_p (operands, true)"
15052 [(const_int 0)]
15053 {
15054 expand_fusion_gpr_load (operands);
15055 DONE;
15056 })
15058 \f
15059 ;; Miscellaneous ISA 2.06 (power7) instructions
15060 (define_insn "addg6s"
15061 [(set (match_operand:SI 0 "register_operand" "=r")
15062 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
15063 (match_operand:SI 2 "register_operand" "r")]
15064 UNSPEC_ADDG6S))]
15065 "TARGET_POPCNTD"
15066 "addg6s %0,%1,%2"
15067 [(set_attr "type" "integer")
15068 (set_attr "length" "4")])
15070 (define_insn "cdtbcd"
15071 [(set (match_operand:SI 0 "register_operand" "=r")
15072 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
15073 UNSPEC_CDTBCD))]
15074 "TARGET_POPCNTD"
15075 "cdtbcd %0,%1"
15076 [(set_attr "type" "integer")
15077 (set_attr "length" "4")])
15079 (define_insn "cbcdtd"
15080 [(set (match_operand:SI 0 "register_operand" "=r")
15081 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
15082 UNSPEC_CBCDTD))]
15083 "TARGET_POPCNTD"
15084 "cbcdtd %0,%1"
15085 [(set_attr "type" "integer")
15086 (set_attr "length" "4")])
15088 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
15089 UNSPEC_DIVEO
15090 UNSPEC_DIVEU
15091 UNSPEC_DIVEUO])
15093 (define_int_attr div_extend [(UNSPEC_DIVE "e")
15094 (UNSPEC_DIVEO "eo")
15095 (UNSPEC_DIVEU "eu")
15096 (UNSPEC_DIVEUO "euo")])
15098 (define_insn "div<div_extend>_<mode>"
15099 [(set (match_operand:GPR 0 "register_operand" "=r")
15100 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
15101 (match_operand:GPR 2 "register_operand" "r")]
15102 UNSPEC_DIV_EXTEND))]
15103 "TARGET_POPCNTD"
15104 "div<wd><div_extend> %0,%1,%2"
15105 [(set_attr "type" "div")
15106 (set_attr "size" "<bits>")])
15108 \f
15109 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
15111 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
15112 (define_mode_attr FP128_64 [(TF "DF") (TD "DI")])
15114 (define_expand "unpack<mode>"
15115 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
15116 (unspec:<FP128_64>
15117 [(match_operand:FMOVE128 1 "register_operand" "")
15118 (match_operand:QI 2 "const_0_to_1_operand" "")]
15119 UNSPEC_UNPACK_128BIT))]
15120 ""
15121 "")
15123 (define_insn_and_split "unpack<mode>_dm"
15124 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
15125 (unspec:<FP128_64>
15126 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
15127 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
15128 UNSPEC_UNPACK_128BIT))]
15129 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
15130 "#"
15131 "&& reload_completed"
15132 [(set (match_dup 0) (match_dup 3))]
15133 {
15134 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
15136 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
15137 {
15138 emit_note (NOTE_INSN_DELETED);
15139 DONE;
15140 }
15142 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
15143 }
15144 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
15145 (set_attr "length" "4")])
15147 (define_insn_and_split "unpack<mode>_nodm"
15148 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
15149 (unspec:<FP128_64>
15150 [(match_operand:FMOVE128 1 "register_operand" "d,d")
15151 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
15152 UNSPEC_UNPACK_128BIT))]
15153 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE"
15154 "#"
15155 "&& reload_completed"
15156 [(set (match_dup 0) (match_dup 3))]
15157 {
15158 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
15160 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
15161 {
15162 emit_note (NOTE_INSN_DELETED);
15163 DONE;
15164 }
15166 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
15167 }
15168 [(set_attr "type" "fp,fpstore")
15169 (set_attr "length" "4")])
15171 (define_insn_and_split "pack<mode>"
15172 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
15173 (unspec:FMOVE128
15174 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
15175 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
15176 UNSPEC_PACK_128BIT))]
15177 ""
15178 "@
15179 fmr %L0,%2
15180 #"
15181 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
15182 [(set (match_dup 3) (match_dup 1))
15183 (set (match_dup 4) (match_dup 2))]
15184 {
15185 unsigned dest_hi = REGNO (operands[0]);
15186 unsigned dest_lo = dest_hi + 1;
15188 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
15189 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
15191 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
15192 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
15193 }
15194 [(set_attr "type" "fp,fp")
15195 (set_attr "length" "4,8")])
15197 (define_insn "unpackv1ti"
15198 [(set (match_operand:DI 0 "register_operand" "=d,d")
15199 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa")
15200 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
15201 UNSPEC_UNPACK_128BIT))]
15202 "TARGET_VSX"
15203 {
15204 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
15205 return ASM_COMMENT_START " xxpermdi to same register";
15207 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
15208 return "xxpermdi %x0,%x1,%x1,%3";
15209 }
15210 [(set_attr "type" "vecperm")
15211 (set_attr "length" "4")])
15213 (define_insn "packv1ti"
15214 [(set (match_operand:V1TI 0 "register_operand" "=wa")
15215 (unspec:V1TI
15216 [(match_operand:DI 1 "register_operand" "d")
15217 (match_operand:DI 2 "register_operand" "d")]
15218 UNSPEC_PACK_128BIT))]
15219 "TARGET_VSX"
15220 "xxpermdi %x0,%x1,%x2,0"
15221 [(set_attr "type" "vecperm")
15222 (set_attr "length" "4")])
15224 \f
15226 (include "sync.md")
15227 (include "vector.md")
15228 (include "vsx.md")
15229 (include "altivec.md")
15230 (include "spe.md")
15231 (include "dfp.md")
15232 (include "paired.md")
15233 (include "crypto.md")
15234 (include "htm.md")