| blob | ad6c330b75e5bd1987c0ffbaa4f4d223b6755cac |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
80 /* This file should be included last. */
83 /* Defined for convenience. */
84 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
86 /* Classifies an address.
88 ADDRESS_REG_IMM
89 A simple base register plus immediate offset.
91 ADDRESS_REG_WB
92 A base register indexed by immediate offset with writeback.
94 ADDRESS_REG_REG
95 A base register indexed by (optionally scaled) register.
97 ADDRESS_REG_UXTW
98 A base register indexed by (optionally scaled) zero-extended register.
100 ADDRESS_REG_SXTW
101 A base register indexed by (optionally scaled) sign-extended register.
103 ADDRESS_LO_SUM
104 A LO_SUM rtx with a base register and "LO12" symbol relocation.
106 ADDRESS_SYMBOLIC:
107 A constant symbolic address, in pc-relative literal pool. */
110 ADDRESS_REG_IMM,
111 ADDRESS_REG_WB,
112 ADDRESS_REG_REG,
113 ADDRESS_REG_UXTW,
114 ADDRESS_REG_SXTW,
115 ADDRESS_LO_SUM,
116 ADDRESS_SYMBOLIC
117 };
121 rtx base;
122 rtx offset;
125 };
127 struct simd_immediate_info
128 {
129 rtx value;
134 };
136 /* The current code model. */
139 #ifdef HAVE_AS_TLS
140 #undef TARGET_HAVE_TLS
141 #define TARGET_HAVE_TLS 1
142 #endif
146 const_tree,
158 /* Major revision number of the ARM Architecture implemented by the target. */
161 /* The processor for which instructions should be scheduled. */
164 /* Mask to specify which instruction scheduling options should be used. */
167 /* Support for command line parsing of boolean flags in the tuning
168 structures. */
169 struct aarch64_flag_desc
170 {
173 };
175 #define AARCH64_FUSION_PAIR(name, internal_name, y) \
176 { name, AARCH64_FUSE_##internal_name },
178 {
183 };
184 #undef AARCH64_FUION_PAIR
186 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name, y) \
187 { name, AARCH64_EXTRA_TUNE_##internal_name },
189 {
194 };
195 #undef AARCH64_EXTRA_TUNING_OPTION
197 /* Tuning parameters. */
200 {
201 {
206 },
212 };
215 {
216 {
221 },
227 };
230 {
231 {
236 },
242 };
245 {
247 /* Avoid the use of slow int<->fp moves for spilling by setting
248 their cost higher than memmov_cost. */
252 };
255 {
257 /* Avoid the use of slow int<->fp moves for spilling by setting
258 their cost higher than memmov_cost. */
262 };
265 {
267 /* Avoid the use of slow int<->fp moves for spilling by setting
268 their cost higher than memmov_cost. */
272 };
275 {
280 };
283 {
285 /* Avoid the use of slow int<->fp moves for spilling by setting
286 their cost higher than memmov_cost. */
290 };
292 /* Generic costs for vector insn classes. */
294 {
307 };
309 /* Generic costs for vector insn classes. */
311 {
324 };
326 /* Generic costs for vector insn classes. */
328 {
341 };
343 /* Generic costs for branch instructions. */
345 {
348 };
351 {
369 };
372 {
391 };
394 {
413 };
416 {
435 };
438 {
456 };
459 {
477 };
479 /* Support for fine-grained override of the tuning structures. */
480 struct aarch64_tuning_override_function
481 {
484 };
489 static const struct aarch64_tuning_override_function
490 aarch64_tuning_override_functions[] =
491 {
495 };
497 /* A processor implementing AArch64. */
498 struct processor
499 {
507 };
509 /* Architectures implementing AArch64. */
511 {
512 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
513 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
515 #undef AARCH64_ARCH
517 };
519 /* Processor cores implementing AArch64. */
521 {
522 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
523 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
524 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
525 FLAGS, &COSTS##_tunings},
527 #undef AARCH64_CORE
531 };
534 /* Target specification. These are populated by the -march, -mtune, -mcpu
535 handling code or by target attributes. */
540 /* The current tuning set. */
543 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
545 /* An ISA extension in the co-processor and main instruction set space. */
546 struct aarch64_option_extension
547 {
551 };
553 /* ISA extensions in AArch64. */
555 {
556 #define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
557 {NAME, FLAGS_ON, FLAGS_OFF},
559 #undef AARCH64_OPT_EXTENSION
561 };
563 /* Used to track the size of an address when generating a pre/post
564 increment address. */
567 /* A table of valid AArch64 "bitmask immediate" values for
568 logical instructions. */
570 #define AARCH64_NUM_BITMASKS 5334
574 {
578 }
579 aarch64_cc;
581 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
583 /* The condition codes of the processor, and the inverse function. */
585 {
588 };
590 void
592 {
596 else
598 }
600 static unsigned int
602 {
606 }
608 static int
611 {
619 }
621 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
622 unsigned
624 {
632 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
633 equivalent DWARF register. */
635 }
637 /* Return TRUE if MODE is any of the large INT modes. */
638 static bool
640 {
642 }
644 /* Return TRUE if MODE is any of the vector modes. */
645 static bool
647 {
650 }
652 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
653 static bool
656 {
663 }
665 /* Implement HARD_REGNO_NREGS. */
667 int
669 {
671 {
677 }
679 }
681 /* Implement HARD_REGNO_MODE_OK. */
683 int
685 {
690 /* The purpose of comparing with ptr_mode is to support the
691 global register variable associated with the stack pointer
692 register via the syntax of asm ("wsp") in ILP32. */
702 {
704 return
706 else
708 }
711 }
713 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
714 machine_mode
716 machine_mode mode)
717 {
718 /* Handle modes that fit within single registers. */
720 {
723 else
725 }
726 /* Fall back to generic for multi-reg and very large modes. */
727 else
729 }
731 /* Return true if calls to DECL should be treated as
732 long-calls (ie called via a register). */
733 static bool
735 {
737 }
739 /* Return true if calls to symbol-ref SYM should be treated as
740 long-calls (ie called via a register). */
741 bool
743 {
745 }
747 /* Return true if the offsets to a zero/sign-extract operation
748 represent an expression that matches an extend operation. The
749 operands represent the paramters from
751 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
752 bool
754 rtx extract_imm)
755 {
772 }
774 /* Emit an insn that's a simple single-set. Both the operands must be
775 known to be valid. */
778 {
780 }
782 /* X and Y are two things to compare using CODE. Emit the compare insn and
783 return the rtx for register 0 in the proper mode. */
784 rtx
786 {
792 }
794 /* Build the SYMBOL_REF for __tls_get_addr. */
798 rtx
800 {
804 }
806 /* Return the TLS model to use for ADDR. */
808 static enum tls_model
810 {
815 {
819 }
824 }
826 /* We'll allow lo_sum's in addresses in our legitimate addresses
827 so that combine would take care of combining addresses where
828 necessary, but for generation purposes, we'll generate the address
829 as :
830 RTL Absolute
831 tmp = hi (symbol_ref); adrp x1, foo
832 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
833 nop
835 PIC TLS
836 adrp x1, :got:foo adrp tmp, :tlsgd:foo
837 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
838 bl __tls_get_addr
839 nop
841 Load TLS symbol, depending on TLS mechanism and TLS access model.
843 Global Dynamic - Traditional TLS:
844 adrp tmp, :tlsgd:imm
845 add dest, tmp, #:tlsgd_lo12:imm
846 bl __tls_get_addr
848 Global Dynamic - TLS Descriptors:
849 adrp dest, :tlsdesc:imm
850 ldr tmp, [dest, #:tlsdesc_lo12:imm]
851 add dest, dest, #:tlsdesc_lo12:imm
852 blr tmp
853 mrs tp, tpidr_el0
854 add dest, dest, tp
856 Initial Exec:
857 mrs tp, tpidr_el0
858 adrp tmp, :gottprel:imm
859 ldr dest, [tmp, #:gottprel_lo12:imm]
860 add dest, dest, tp
862 Local Exec:
863 mrs tp, tpidr_el0
864 add t0, tp, #:tprel_hi12:imm, lsl #12
865 add t0, t0, #:tprel_lo12_nc:imm
866 */
868 static void
871 {
873 {
875 {
876 /* In ILP32, the mode of dest can be either SImode or DImode. */
888 }
895 {
898 rtx insn;
899 rtx mem;
901 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
902 here before rtl expand. Tree IVOPT will generate rtl pattern to
903 decide rtx costs, in which case pic_offset_table_rtx is not
904 initialized. For that case no need to generate the first adrp
905 instruction as the final cost for global variable access is
906 one instruction. */
908 {
909 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
910 using the page base as GOT base, the first page may be wasted,
911 in the worst scenario, there is only 28K space for GOT).
913 The generate instruction sequence for accessing global variable
914 is:
916 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
918 Only one instruction needed. But we must initialize
919 pic_offset_table_rtx properly. We generate initialize insn for
920 every global access, and allow CSE to remove all redundant.
922 The final instruction sequences will look like the following
923 for multiply global variables access.
925 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
927 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
928 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
929 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
930 ... */
938 }
941 {
944 else
948 }
949 else
950 {
955 }
957 /* The operand is expected to be MEM. Whenever the related insn
958 pattern changed, above code which calculate mem should be
959 updated. */
965 }
968 {
969 /* In ILP32, the mode of dest can be either SImode or DImode,
970 while the got entry is always of SImode size. The mode of
971 dest depends on how dest is used: if dest is assigned to a
972 pointer (e.g. in the memory), it has SImode; it may have
973 DImode if dest is dereferenced to access the memeory.
974 This is why we have to handle three different ldr_got_small
975 patterns here (two patterns for ILP32). */
977 rtx insn;
978 rtx mem;
987 {
990 else
994 }
995 else
996 {
1001 }
1008 }
1011 {
1023 }
1026 {
1029 rtx tp;
1033 /* In ILP32, the got entry is always of SImode size. Unlike
1034 small GOT, the dest is fixed at reg 0. */
1037 else
1047 }
1050 {
1051 /* In ILP32, the mode of dest can be either SImode or DImode,
1052 while the got entry is always of SImode size. The mode of
1053 dest depends on how dest is used: if dest is assigned to a
1054 pointer (e.g. in the memory), it has SImode; it may have
1055 DImode if dest is dereferenced to access the memeory.
1056 This is why we have to handle three different tlsie_small
1057 patterns here (two patterns for ILP32). */
1063 {
1066 else
1067 {
1070 }
1071 }
1072 else
1073 {
1076 }
1081 }
1084 {
1093 }
1101 }
1102 }
1104 /* Emit a move from SRC to DEST. Assume that the move expanders can
1105 handle all moves if !can_create_pseudo_p (). The distinction is
1106 important because, unlike emit_move_insn, the move expanders know
1107 how to force Pmode objects into the constant pool even when the
1108 constant pool address is not itself legitimate. */
1109 static rtx
1111 {
1115 }
1117 /* Split a 128-bit move operation into two 64-bit move operations,
1118 taking care to handle partial overlap of register to register
1119 copies. Special cases are needed when moving between GP regs and
1120 FP regs. SRC can be a register, constant or memory; DST a register
1121 or memory. If either operand is memory it must not have any side
1122 effects. */
1123 void
1125 {
1136 {
1140 /* Handle FP <-> GP regs. */
1142 {
1147 {
1150 }
1151 else
1152 {
1155 }
1157 }
1159 {
1164 {
1167 }
1168 else
1169 {
1172 }
1174 }
1175 }
1182 /* At most one pairing may overlap. */
1184 {
1187 }
1188 else
1189 {
1192 }
1193 }
1195 bool
1197 {
1200 }
1202 /* Split a complex SIMD combine. */
1204 void
1206 {
1213 {
1217 {
1238 }
1242 }
1243 }
1245 /* Split a complex SIMD move. */
1247 void
1249 {
1256 {
1262 {
1283 }
1287 }
1288 }
1290 static rtx
1292 {
1295 else
1296 {
1299 }
1300 }
1303 static rtx
1305 {
1307 {
1308 rtx high;
1309 /* Load the full offset into a register. This
1310 might be improvable in the future. */
1316 }
1318 }
1320 static int
1322 machine_mode mode)
1323 {
1329 rtx subtarget;
1334 {
1337 num_insns++;
1339 }
1342 {
1343 /* We know we can't do this in 1 insn, and we must be able to do it
1344 in two; so don't mess around looking for sequences that don't buy
1345 us anything. */
1347 {
1351 }
1354 }
1356 /* Remaining cases are all for DImode. */
1367 {
1369 one_match++;
1370 else
1371 {
1375 zero_match++;
1376 }
1377 }
1380 {
1381 /* Set one of the quarters and then insert back into result. */
1384 {
1389 }
1392 }
1399 {
1403 {
1405 {
1410 }
1413 }
1415 {
1417 {
1423 }
1426 }
1428 {
1430 {
1436 }
1439 }
1441 {
1443 {
1448 }
1451 }
1452 }
1454 /* See if we can do it by arithmetically combining two
1455 immediates. */
1457 {
1463 {
1465 {
1471 }
1474 }
1477 {
1479 {
1481 {
1486 }
1489 }
1490 }
1491 }
1493 /* See if we can do it by logically combining two immediates. */
1495 {
1497 {
1502 {
1504 {
1510 }
1513 }
1514 }
1516 {
1521 {
1523 {
1529 }
1532 }
1533 }
1534 }
1537 {
1538 /* Set either first three quarters or all but the third. */
1543 num_insns ++;
1545 /* Now insert other two quarters. */
1548 {
1550 {
1554 num_insns ++;
1555 }
1556 }
1558 }
1560 simple_sequence:
1564 {
1566 {
1568 {
1571 num_insns ++;
1573 }
1574 else
1575 {
1579 num_insns ++;
1580 }
1581 }
1582 }
1585 }
1588 void
1590 {
1595 /* Check on what type of symbol it is. */
1599 {
1603 /* If we have (const (plus symbol offset)), separate out the offset
1604 before we start classifying the symbol. */
1609 {
1613 {
1619 }
1634 {
1640 }
1641 /* FALLTHRU */
1651 }
1652 }
1655 {
1658 else
1659 {
1663 }
1666 }
1669 }
1671 static bool
1673 tree exp ATTRIBUTE_UNUSED)
1674 {
1675 /* Currently, always true. */
1677 }
1679 /* Implement TARGET_PASS_BY_REFERENCE. */
1681 static bool
1683 machine_mode mode,
1684 const_tree type,
1686 {
1687 HOST_WIDE_INT size;
1688 machine_mode dummymode;
1691 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1695 /* Aggregates are passed by reference based on their size. */
1697 {
1699 }
1701 /* Variable sized arguments are always returned by reference. */
1705 /* Can this be a candidate to be passed in fp/simd register(s)? */
1708 NULL))
1711 /* Arguments which are variable sized or larger than 2 registers are
1712 passed by reference unless they are a homogenous floating point
1713 aggregate. */
1715 }
1717 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1718 static bool
1720 {
1721 machine_mode dummy_mode;
1724 /* Never happens in little-endian mode. */
1728 /* Only composite types smaller than or equal to 16 bytes can
1729 be potentially returned in registers. */
1735 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1736 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1737 is always passed/returned in the least significant bits of fp/simd
1738 register(s). */
1744 }
1746 /* Implement TARGET_FUNCTION_VALUE.
1747 Define how to find the value returned by a function. */
1749 static rtx
1752 {
1753 machine_mode mode;
1756 machine_mode ag_mode;
1763 {
1767 {
1770 }
1771 }
1775 {
1777 {
1780 }
1781 else
1782 {
1784 rtx par;
1788 {
1793 }
1795 }
1796 }
1797 else
1799 }
1801 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1802 Return true if REGNO is the number of a hard register in which the values
1803 of called function may come back. */
1805 static bool
1807 {
1808 /* Maximum of 16 bytes can be returned in the general registers. Examples
1809 of 16-byte return values are: 128-bit integers and 16-byte small
1810 structures (excluding homogeneous floating-point aggregates). */
1814 /* Up to four fp/simd registers can return a function value, e.g. a
1815 homogeneous floating-point aggregate having four members. */
1820 }
1822 /* Implement TARGET_RETURN_IN_MEMORY.
1824 If the type T of the result of a function is such that
1825 void func (T arg)
1826 would require that arg be passed as a value in a register (or set of
1827 registers) according to the parameter passing rules, then the result
1828 is returned in the same registers as would be used for such an
1829 argument. */
1831 static bool
1833 {
1834 HOST_WIDE_INT size;
1835 machine_mode ag_mode;
1841 /* Simple scalar types always returned in registers. */
1845 type,
1848 NULL))
1851 /* Types larger than 2 registers returned in memory. */
1854 }
1856 static bool
1859 {
1862 type,
1864 nregs,
1865 NULL);
1866 }
1868 /* Given MODE and TYPE of a function argument, return the alignment in
1869 bits. The idea is to suppress any stronger alignment requested by
1870 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1871 This is a helper function for local use only. */
1873 static unsigned int
1875 {
1879 {
1881 {
1884 else
1886 }
1887 else
1889 }
1890 else
1894 }
1896 /* Layout a function argument according to the AAPCS64 rules. The rule
1897 numbers refer to the rule numbers in the AAPCS64. */
1899 static void
1901 const_tree type,
1903 {
1907 HOST_WIDE_INT size;
1909 /* We need to do this once per argument. */
1915 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
1916 size
1918 UNITS_PER_WORD);
1922 mode,
1923 type,
1926 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
1927 The following code thus handles passing by SIMD/FP registers first. */
1931 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
1932 and homogenous short-vector aggregates (HVA). */
1934 {
1939 {
1942 {
1945 }
1946 else
1947 {
1948 rtx par;
1952 {
1955 tmp = gen_rtx_EXPR_LIST
1959 }
1961 }
1963 }
1964 else
1965 {
1966 /* C.3 NSRN is set to 8. */
1969 }
1970 }
1975 /* C6 - C9. though the sign and zero extension semantics are
1976 handled elsewhere. This is the case where the argument fits
1977 entirely general registers. */
1979 {
1984 /* C.8 if the argument has an alignment of 16 then the NGRN is
1985 rounded up to the next even number. */
1987 {
1990 }
1991 /* NREGS can be 0 when e.g. an empty structure is to be passed.
1992 A reg is still generated for it, but the caller should be smart
1993 enough not to use it. */
1995 {
1997 }
1998 else
1999 {
2000 rtx par;
2005 {
2010 }
2012 }
2016 }
2018 /* C.11 */
2021 /* The argument is passed on stack; record the needed number of words for
2022 this argument and align the total size if necessary. */
2023 on_stack:
2029 }
2031 /* Implement TARGET_FUNCTION_ARG. */
2033 static rtx
2036 {
2045 }
2047 void
2049 const_tree fntype ATTRIBUTE_UNUSED,
2050 rtx libname ATTRIBUTE_UNUSED,
2051 const_tree fndecl ATTRIBUTE_UNUSED,
2053 {
2067 {
2074 }
2076 }
2078 static void
2080 machine_mode mode,
2081 const_tree type,
2083 {
2086 {
2096 }
2097 }
2099 bool
2101 {
2104 }
2106 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2107 PARM_BOUNDARY bits of alignment, but will be given anything up
2108 to STACK_BOUNDARY bits if the type requires it. This makes sure
2109 that both before and after the layout of each argument, the Next
2110 Stacked Argument Address (NSAA) will have a minimum alignment of
2111 8 bytes. */
2113 static unsigned int
2115 {
2123 }
2125 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2127 Return true if an argument passed on the stack should be padded upwards,
2128 i.e. if the least-significant byte of the stack slot has useful data.
2130 Small aggregate types are placed in the lowest memory address.
2132 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2134 bool
2136 {
2137 /* On little-endian targets, the least significant byte of every stack
2138 argument is passed at the lowest byte address of the stack slot. */
2142 /* Otherwise, integral, floating-point and pointer types are padded downward:
2143 the least significant byte of a stack argument is passed at the highest
2144 byte address of the stack slot. */
2151 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2153 }
2155 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2157 It specifies padding for the last (may also be the only)
2158 element of a block move between registers and memory. If
2159 assuming the block is in the memory, padding upward means that
2160 the last element is padded after its highest significant byte,
2161 while in downward padding, the last element is padded at the
2162 its least significant byte side.
2164 Small aggregates and small complex types are always padded
2165 upwards.
2167 We don't need to worry about homogeneous floating-point or
2168 short-vector aggregates; their move is not affected by the
2169 padding direction determined here. Regardless of endianness,
2170 each element of such an aggregate is put in the least
2171 significant bits of a fp/simd register.
2173 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2174 register has useful data, and return the opposite if the most
2175 significant byte does. */
2177 bool
2180 {
2182 /* Small composite types are always padded upward. */
2184 {
2189 }
2191 /* Otherwise, use the default padding. */
2193 }
2195 static machine_mode
2197 {
2199 }
2201 static bool
2203 {
2204 /* In aarch64_override_options_after_change
2205 flag_omit_leaf_frame_pointer turns off the frame pointer by
2206 default. Turn it back on now if we've not got a leaf
2207 function. */
2213 }
2215 /* Mark the registers that need to be saved by the callee and calculate
2216 the size of the callee-saved registers area and frame record (both FP
2217 and LR may be omitted). */
2218 static void
2220 {
2227 #define SLOT_NOT_REQUIRED (-2)
2228 #define SLOT_REQUIRED (-1)
2233 /* First mark all the registers that really need to be saved... */
2240 /* ... that includes the eh data registers (if needed)... */
2246 /* ... and any callee saved register that dataflow says is live. */
2259 {
2260 /* FP and LR are placed in the linkage record. */
2267 }
2269 /* Now assign stack slots for them. */
2272 {
2279 }
2283 {
2291 }
2311 }
2313 static bool
2315 {
2317 }
2319 static unsigned
2321 {
2323 regno ++;
2325 }
2327 static void
2329 HOST_WIDE_INT adjustment)
2330 {
2341 }
2343 static rtx
2345 HOST_WIDE_INT adjustment)
2346 {
2348 {
2359 }
2360 }
2362 static void
2365 {
2375 }
2377 static rtx
2379 HOST_WIDE_INT adjustment)
2380 {
2382 {
2391 }
2392 }
2394 static rtx
2396 rtx reg2)
2397 {
2399 {
2408 }
2409 }
2411 static rtx
2413 rtx mem2)
2414 {
2416 {
2425 }
2426 }
2429 static void
2432 {
2442 {
2444 HOST_WIDE_INT offset;
2454 offset));
2462 {
2464 rtx mem2;
2468 offset));
2470 reg2));
2472 /* The first part of a frame-related parallel insn is
2473 always assumed to be relevant to the frame
2474 calculations; subsequent parts, are only
2475 frame-related if explicitly marked. */
2478 }
2479 else
2483 }
2484 }
2486 static void
2490 {
2496 HOST_WIDE_INT offset;
2501 {
2518 {
2520 rtx mem2;
2528 }
2529 else
2532 }
2533 }
2535 /* AArch64 stack frames generated by this compiler look like:
2537 +-------------------------------+
2538 | |
2539 | incoming stack arguments |
2540 | |
2541 +-------------------------------+
2542 | | <-- incoming stack pointer (aligned)
2543 | callee-allocated save area |
2544 | for register varargs |
2545 | |
2546 +-------------------------------+
2547 | local variables | <-- frame_pointer_rtx
2548 | |
2549 +-------------------------------+
2550 | padding0 | \
2551 +-------------------------------+ |
2552 | callee-saved registers | | frame.saved_regs_size
2553 +-------------------------------+ |
2554 | LR' | |
2555 +-------------------------------+ |
2556 | FP' | / <- hard_frame_pointer_rtx (aligned)
2557 +-------------------------------+
2558 | dynamic allocation |
2559 +-------------------------------+
2560 | padding |
2561 +-------------------------------+
2562 | outgoing stack arguments | <-- arg_pointer
2563 | |
2564 +-------------------------------+
2565 | | <-- stack_pointer_rtx (aligned)
2567 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2568 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2569 unchanged. */
2571 /* Generate the prologue instructions for entry into a function.
2572 Establish the stack frame by decreasing the stack pointer with a
2573 properly calculated size and, if necessary, create a frame record
2574 filled with the values of LR and previous frame pointer. The
2575 current FP is also set up if it is in use. */
2577 void
2579 {
2580 /* sub sp, sp, #<frame_size>
2581 stp {fp, lr}, [sp, #<frame_size> - 16]
2582 add fp, sp, #<frame_size> - hardfp_offset
2583 stp {cs_reg}, [fp, #-16] etc.
2585 sub sp, sp, <final_adjustment_if_any>
2586 */
2589 HOST_WIDE_INT hard_fp_offset;
2601 /* Store pairs and load pairs have a range only -512 to 504. */
2603 {
2604 /* When the frame has a large size, an initial decrease is done on
2605 the stack pointer to jump over the callee-allocated save area for
2606 register varargs, the local variable area and/or the callee-saved
2607 register area. This will allow the pre-index write-back
2608 store pair instructions to be used for setting up the stack frame
2609 efficiently. */
2618 {
2628 }
2630 {
2635 {
2639 }
2641 {
2645 }
2646 }
2647 }
2648 else
2652 {
2656 {
2660 {
2667 }
2668 else
2671 /* Set up frame pointer to point to the location of the
2672 previous frame pointer on the stack. */
2674 stack_pointer_rtx,
2678 }
2679 else
2680 {
2688 {
2692 }
2693 else
2694 {
2701 else
2703 }
2704 }
2707 skip_wb);
2709 skip_wb);
2710 }
2712 /* when offset >= 512,
2713 sub sp, sp, #<outgoing_args_size> */
2715 {
2717 {
2722 }
2723 }
2724 }
2726 /* Return TRUE if we can use a simple_return insn.
2728 This function checks whether the callee saved stack is empty, which
2729 means no restore actions are need. The pro_and_epilogue will use
2730 this to check whether shrink-wrapping opt is feasible. */
2732 bool
2734 {
2744 }
2746 /* Generate the epilogue instructions for returning from a function. */
2747 void
2749 {
2751 HOST_WIDE_INT fp_offset;
2752 HOST_WIDE_INT hard_fp_offset;
2754 /* We need to add memory barrier to prevent read from deallocated stack. */
2764 /* Store pairs and load pairs have a range only -512 to 504. */
2766 {
2774 {
2779 }
2780 }
2781 else
2784 /* If there were outgoing arguments or we've done dynamic stack
2785 allocation, then restore the stack pointer from the frame
2786 pointer. This is at most one insn and more efficient than using
2787 GCC's internal mechanism. */
2790 {
2795 hard_frame_pointer_rtx,
2798 }
2801 {
2824 {
2830 {
2835 }
2836 else
2837 {
2844 }
2845 }
2846 else
2847 {
2850 }
2852 /* Reset the CFA to be SP + FRAME_SIZE. */
2859 }
2862 {
2867 {
2871 }
2872 else
2873 {
2878 {
2883 }
2886 }
2888 /* Reset the CFA to be SP + 0. */
2891 }
2893 /* Stack adjustment for exception handler. */
2895 {
2896 /* We need to unwind the stack by the offset computed by
2897 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
2898 to be SP; letting the CFA move during this adjustment
2899 is just as correct as retaining the CFA from the body
2900 of the function. Therefore, do nothing special. */
2902 }
2907 }
2909 /* Return the place to copy the exception unwinding return address to.
2910 This will probably be a stack slot, but could (in theory be the
2911 return register). */
2912 rtx
2914 {
2915 HOST_WIDE_INT fp_offset;
2925 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
2926 result in a store to save LR introduced by builtin_eh_return () being
2927 incorrectly deleted because the alias is not detected.
2928 So in the calculation of the address to copy the exception unwinding
2929 return address to, we note 2 cases.
2930 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
2931 we return a SP-relative location since all the addresses are SP-relative
2932 in this case. This prevents the store from being optimized away.
2933 If the fp_offset is not 0, then the addresses will be FP-relative and
2934 therefore we return a FP-relative location. */
2937 {
2941 else
2944 }
2946 /* If FP is not needed, we calculate the location of LR, which would be
2947 at the top of the saved registers block. */
2951 stack_pointer_rtx,
2952 fp_offset
2955 }
2957 /* Possibly output code to build up a constant in a register. For
2958 the benefit of the costs infrastructure, returns the number of
2959 instructions which would be emitted. GENERATE inhibits or
2960 enables code generation. */
2962 static int
2964 {
2968 {
2972 }
2973 else
2974 {
2979 HOST_WIDE_INT valm;
2980 HOST_WIDE_INT tval;
2983 {
2993 }
2995 /* zcount contains the number of additional MOVK instructions
2996 required if the constant is built up with an initial MOVZ instruction,
2997 while ncount is the number of MOVK instructions required if starting
2998 with a MOVN instruction. Choose the sequence that yields the fewest
2999 number of instructions, preferring MOVZ instructions when they are both
3000 the same. */
3002 {
3007 insns++;
3008 }
3009 else
3010 {
3015 insns++;
3016 }
3021 {
3023 {
3028 insns++;
3029 }
3031 }
3032 }
3034 }
3036 static void
3038 {
3047 {
3050 }
3052 {
3054 {
3060 else
3063 }
3065 {
3069 }
3070 }
3071 }
3073 /* Output code to add DELTA to the first argument, and then jump
3074 to FUNCTION. Used for C++ multiple inheritance. */
3075 static void
3077 HOST_WIDE_INT delta,
3078 HOST_WIDE_INT vcall_offset,
3079 tree function)
3080 {
3081 /* The this pointer is always in x0. Note that this differs from
3082 Arm where the this pointer maybe bumped to r1 if r0 is required
3083 to return a pointer to an aggregate. On AArch64 a result value
3084 pointer will be in x8. */
3094 else
3095 {
3104 {
3108 else
3110 }
3114 else
3121 else
3122 {
3125 }
3129 else
3135 }
3137 /* Generate a tail call to the target function. */
3139 {
3142 }
3154 /* Stop pretending to be a post-reload pass. */
3156 }
3158 static bool
3160 {
3165 {
3169 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3170 TLS offsets, not real symbol references. */
3173 }
3175 }
3178 static int
3180 {
3189 }
3192 static void
3194 {
3200 {
3204 else
3207 {
3209 {
3210 /* set s consecutive bits to 1 (s < 64) */
3212 /* rotate right by r */
3215 /* replicate the constant depending on SIMD size */
3226 }
3229 }
3230 }
3231 }
3235 aarch64_bitmasks_cmp);
3236 }
3239 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3240 a left shift of 0 or 12 bits. */
3241 bool
3243 {
3246 );
3247 }
3250 /* Return true if val is an immediate that can be loaded into a
3251 register by a MOVZ instruction. */
3252 static bool
3254 {
3256 {
3260 }
3261 else
3262 {
3263 /* Ignore sign extension. */
3265 }
3268 }
3271 /* Return true if val is a valid bitmask immediate. */
3272 bool
3274 {
3276 {
3277 /* Replicate bit pattern. */
3280 }
3283 }
3286 /* Return true if val is an immediate that can be loaded into a
3287 register in a single instruction. */
3288 bool
3290 {
3294 }
3296 static bool
3298 {
3306 {
3310 else
3311 /* Avoid generating a 64-bit relocation in ILP32; leave
3312 to aarch64_expand_mov_immediate to handle it properly. */
3314 }
3317 }
3319 /* Return true if register REGNO is a valid index register.
3320 STRICT_P is true if REG_OK_STRICT is in effect. */
3322 bool
3324 {
3326 {
3334 }
3336 }
3338 /* Return true if register REGNO is a valid base register for mode MODE.
3339 STRICT_P is true if REG_OK_STRICT is in effect. */
3341 bool
3343 {
3345 {
3353 }
3355 /* The fake registers will be eliminated to either the stack or
3356 hard frame pointer, both of which are usually valid base registers.
3357 Reload deals with the cases where the eliminated form isn't valid. */
3362 }
3364 /* Return true if X is a valid base register for mode MODE.
3365 STRICT_P is true if REG_OK_STRICT is in effect. */
3367 static bool
3369 {
3374 }
3376 /* Return true if address offset is a valid index. If it is, fill in INFO
3377 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3379 static bool
3382 {
3384 rtx index;
3387 /* (reg:P) */
3390 {
3394 }
3395 /* (sign_extend:DI (reg:SI)) */
3400 {
3405 }
3406 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3413 {
3418 }
3419 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3426 {
3431 }
3432 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3439 {
3447 }
3448 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3449 (const_int 0xffffffff<<shift)) */
3456 {
3462 }
3463 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3470 {
3478 }
3479 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3480 (const_int 0xffffffff<<shift)) */
3487 {
3493 }
3494 /* (mult:P (reg:P) (const_int scale)) */
3499 {
3503 }
3504 /* (ashift:P (reg:P) (const_int shift)) */
3509 {
3513 }
3514 else
3525 {
3530 }
3533 }
3535 bool
3537 {
3541 }
3545 HOST_WIDE_INT offset)
3546 {
3548 }
3552 {
3556 }
3558 /* Return true if X is a valid address for machine mode MODE. If it is,
3559 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3560 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3562 static bool
3566 {
3570 /* On BE, we use load/store pair for all large int mode load/stores. */
3572 || (BYTES_BIG_ENDIAN
3576 !load_store_pair_p
3580 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3581 REG addressing. */
3587 {
3605 {
3611 }
3616 {
3623 /* TImode and TFmode values are allowed in both pairs of X
3624 registers and individual Q registers. The available
3625 address modes are:
3626 X,X: 7-bit signed scaled offset
3627 Q: 9-bit signed offset
3628 We conservatively require an offset representable in either mode.
3629 */
3634 /* A 7bit offset check because OImode will emit a ldp/stp
3635 instruction (only big endian will get here).
3636 For ldp/stp instructions, the offset is scaled for the size of a
3637 single element of the pair. */
3641 /* Three 9/12 bit offsets checks because CImode will emit three
3642 ldr/str instructions (only big endian will get here). */
3649 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3650 instructions (only big endian will get here). */
3659 else
3662 }
3665 {
3666 /* Look for base + (scaled/extended) index register. */
3669 {
3672 }
3675 {
3678 }
3679 }
3700 {
3701 HOST_WIDE_INT offset;
3705 /* TImode and TFmode values are allowed in both pairs of X
3706 registers and individual Q registers. The available
3707 address modes are:
3708 X,X: 7-bit signed scaled offset
3709 Q: 9-bit signed offset
3710 We conservatively require an offset representable in either mode.
3711 */
3719 else
3721 }
3727 /* load literal: pc-relative constant pool entry. Only supported
3728 for SI mode or larger. */
3732 {
3739 }
3748 {
3754 {
3755 /* The symbol and offset must be aligned to the access size. */
3762 {
3766 }
3772 else
3781 }
3782 }
3787 }
3788 }
3790 bool
3792 {
3793 rtx offset;
3797 }
3799 /* Classify the base of symbolic expression X, given that X appears in
3800 context CONTEXT. */
3802 enum aarch64_symbol_type
3805 {
3806 rtx offset;
3810 }
3813 /* Return TRUE if X is a legitimate address for accessing memory in
3814 mode MODE. */
3815 static bool
3817 {
3821 }
3823 /* Return TRUE if X is a legitimate address for accessing memory in
3824 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
3825 pair operation. */
3826 bool
3829 {
3833 }
3835 /* Return TRUE if rtx X is immediate constant 0.0 */
3836 bool
3838 {
3839 REAL_VALUE_TYPE r;
3848 }
3850 /* Return the fixed registers used for condition codes. */
3852 static bool
3854 {
3858 }
3860 /* Emit call insn with PAT and do aarch64-specific handling. */
3862 void
3864 {
3870 }
3872 machine_mode
3874 {
3875 /* All floating point compares return CCFP if it is an equality
3876 comparison, and CCFPE otherwise. */
3878 {
3880 {
3901 }
3902 }
3911 /* A compare with a shifted operand. Because of canonicalization,
3912 the comparison will have to be swapped when we emit the assembly
3913 code. */
3921 /* Similarly for a negated operand, but we can only do this for
3922 equalities. */
3929 /* A compare of a mode narrower than SI mode against zero can be done
3930 by extending the value in the comparison. */
3933 /* Only use sign-extension if we really need it. */
3937 /* For everything else, return CCmode. */
3939 }
3941 static int
3944 int
3946 {
3953 }
3955 static int
3957 {
3960 {
3964 {
3978 }
4033 {
4045 }
4052 {
4064 }
4069 {
4075 }
4080 {
4084 }
4090 }
4099 }
4101 bool
4103 HOST_WIDE_INT minval,
4104 HOST_WIDE_INT maxval)
4105 {
4106 HOST_WIDE_INT firstval;
4123 }
4125 bool
4127 {
4129 }
4131 static unsigned
4133 {
4137 {
4138 count++;
4140 }
4143 }
4145 /* N Z C V. */
4146 #define AARCH64_CC_V 1
4147 #define AARCH64_CC_C (1 << 1)
4148 #define AARCH64_CC_Z (1 << 2)
4149 #define AARCH64_CC_N (1 << 3)
4151 /* N Z C V flags for ccmp. The first code is for AND op and the other
4152 is for IOR op. Indexed by AARCH64_COND_CODE. */
4154 {
4171 };
4173 int
4175 {
4177 {
4210 }
4211 }
4214 void
4216 {
4218 {
4219 /* An integer or symbol address without a preceding # sign. */
4222 {
4234 {
4237 }
4238 /* Fall through. */
4242 }
4246 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4247 {
4252 {
4255 }
4258 {
4271 }
4272 }
4276 {
4279 /* Print N such that 2^N == X. */
4281 {
4284 }
4287 }
4291 /* Print the number of non-zero bits in X (a const_int). */
4293 {
4296 }
4302 /* Print the higher numbered register of a pair (TImode) of regs. */
4304 {
4307 }
4313 {
4315 /* Print a condition (eq, ne, etc). */
4317 /* CONST_TRUE_RTX means always -- that's the default. */
4322 {
4325 }
4330 }
4334 {
4336 /* Print the inverse of a condition (eq <-> ne, etc). */
4338 /* CONST_TRUE_RTX means never -- that's the default. */
4340 {
4343 }
4346 {
4349 }
4354 }
4362 /* Print a scalar FP/SIMD register name. */
4364 {
4365 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4367 }
4375 /* Print the first FP/SIMD register name in a list. */
4377 {
4378 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4380 }
4385 /* Print a scalar FP/SIMD register name + 1. */
4387 {
4388 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4390 }
4395 /* Print bottom 16 bits of integer constant in hex. */
4397 {
4400 }
4406 /* Print a general register name or the zero register (32-bit or
4407 64-bit). */
4410 {
4413 }
4416 {
4419 }
4422 {
4425 }
4427 /* Fall through */
4430 /* Print a normal operand, if it's a general register, then we
4431 assume DImode. */
4433 {
4436 }
4439 {
4460 {
4463 HOST_WIDE_INT_MIN,
4464 HOST_WIDE_INT_MAX));
4466 }
4468 {
4470 }
4471 else
4476 /* CONST_DOUBLE can represent a double-width integer.
4477 In this case, the mode of x is VOIDmode. */
4481 {
4484 }
4486 {
4487 #define buf_size 20
4489 REAL_VALUE_TYPE r;
4496 #undef buf_size
4497 }
4503 }
4511 {
4538 }
4544 {
4571 }
4578 {
4584 }
4589 {
4591 /* Print nzcv. */
4594 {
4597 }
4602 }
4606 {
4608 /* Print nzcv. */
4611 {
4614 }
4619 }
4625 }
4626 }
4628 void
4630 {
4636 {
4640 else
4649 else
4658 else
4667 else
4674 {
4701 }
4712 }
4715 }
4717 bool
4719 {
4726 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4727 referencing instruction, but they are constant offsets, not
4728 symbols. */
4734 {
4736 {
4742 }
4745 }
4748 }
4750 /* Implement REGNO_REG_CLASS. */
4752 enum reg_class
4754 {
4769 }
4771 static rtx
4773 {
4774 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
4775 where mask is selected by alignment and size of the offset.
4776 We try to pick as large a range for the offset as possible to
4777 maximize the chance of a CSE. However, for aligned addresses
4778 we limit the range to 4k so that structures with different sized
4779 elements are likely to use the same base. */
4782 {
4784 HOST_WIDE_INT base_offset;
4786 /* Does it look like we'll need a load/store-pair operation? */
4791 /* For offsets aren't a multiple of the access size, the limit is
4792 -256...255. */
4795 else
4804 NULL_RTX);
4807 }
4810 }
4812 /* Try a machine-dependent way of reloading an illegitimate address
4813 operand. If we find one, push the reload and return the new rtx. */
4815 rtx
4817 machine_mode mode,
4820 {
4823 /* Do not allow mem (plus (reg, const)) if vector struct mode. */
4828 {
4835 }
4837 /* We must recognize output that we have already generated ourselves. */
4843 {
4848 }
4850 /* We wish to handle large displacements off a base register by splitting
4851 the addend across an add and the mem insn. This can cut the number of
4852 extra insns needed from 3 to 1. It is only useful for load/store of a
4853 single register with 12 bit offset field. */
4861 {
4865 HOST_WIDE_INT offs;
4866 rtx cst;
4869 /* In ILP32, xmode can be either DImode or SImode. */
4872 /* Reload non-zero BLKmode offsets. This is because we cannot ascertain
4873 BLKmode alignment. */
4879 /* Align misaligned offset by adjusting high part to compensate. */
4881 {
4883 {
4884 /* Align down. */
4887 }
4888 else
4889 {
4890 /* Align up. */
4895 }
4896 }
4898 /* Check for overflow. */
4906 /* Reload high part into base reg, leaving the low part
4907 in the mem instruction.
4908 Note that replacing this gen_rtx_PLUS with plus_constant is
4909 wrong in this case because we rely on the
4910 (plus (plus reg c1) c2) structure being preserved so that
4911 XEXP (*p, 0) in push_reload below uses the correct term. */
4920 }
4923 }
4926 static reg_class_t
4928 reg_class_t rclass,
4929 machine_mode mode,
4931 {
4932 /* Without the TARGET_SIMD instructions we cannot move a Q register
4933 to a Q register directly. We need a scratch. */
4937 {
4943 }
4945 /* A TFmode or TImode memory access should be handled via an FP_REGS
4946 because AArch64 has richer addressing modes for LDR/STR instructions
4947 than LDP/STP instructions. */
4956 }
4958 static bool
4960 {
4961 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
4962 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
4965 {
4977 }
4978 else
4979 {
4980 /* If we decided that we didn't need a leaf frame pointer but then used
4981 LR in the function, then we'll want a frame pointer after all, so
4982 prevent this elimination to ensure a frame pointer is used. */
4984 && flag_omit_leaf_frame_pointer
4987 }
4990 }
4992 HOST_WIDE_INT
4994 {
4998 {
5005 }
5008 {
5012 }
5015 }
5017 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5018 previous frame. */
5020 rtx
5022 {
5026 }
5029 static void
5031 {
5033 {
5036 }
5037 else
5038 {
5041 }
5046 }
5048 static void
5050 {
5054 /* Don't need to copy the trailing D-words, we fill those in below. */
5066 /* XXX We should really define a "clear_cache" pattern and use
5067 gen_clear_cache(). */
5072 ptr_mode);
5073 }
5075 static unsigned char
5077 {
5079 {
5086 return
5098 }
5100 }
5102 static reg_class_t
5104 {
5109 {
5115 }
5117 /* If it's an integer immediate that MOVI can't handle, then
5118 FP_REGS is not an option, so we return NO_REGS instead. */
5123 /* Register eliminiation can result in a request for
5124 SP+constant->FP_REGS. We cannot support such operations which
5125 use SP as source and an FP_REG as destination, so reject out
5126 right now. */
5128 {
5131 /* Look through a possible SUBREG introduced by ILP32. */
5137 POINTER_REGS));
5139 }
5142 }
5144 void
5146 {
5148 }
5150 static void
5152 {
5155 else
5156 {
5164 }
5165 }
5167 static void
5169 {
5172 else
5173 {
5181 }
5182 }
5186 {
5192 {
5193 {
5196 },
5197 {
5200 },
5201 {
5204 },
5205 /* We assume that DImode is only generated when not optimizing and
5206 that we don't really need 64-bit address offsets. That would
5207 imply an object file with 8GB of code in a single function! */
5208 {
5211 }
5212 };
5220 /* Need to implement table size reduction, by chaning the code below. */
5230 }
5233 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5234 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5235 operator. */
5237 int
5239 {
5241 {
5244 {
5248 }
5249 }
5251 }
5253 static bool
5255 const_rtx x ATTRIBUTE_UNUSED)
5256 {
5257 /* We can't use blocks for constants when we're using a per-function
5258 constant pool. */
5260 }
5264 rtx x ATTRIBUTE_UNUSED,
5266 {
5267 /* Force all constant pool entries into the current function section. */
5269 }
5272 /* Costs. */
5274 /* Helper function for rtx cost calculation. Strip a shift expression
5275 from X. Returns the inner operand if successful, or the original
5276 expression on failure. */
5277 static rtx
5279 {
5282 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5283 we can convert both to ROR during final output. */
5298 }
5300 /* Helper function for rtx cost calculation. Strip an extend
5301 expression from X. Returns the inner operand if successful, or the
5302 original expression on failure. We deal with a number of possible
5303 canonicalization variations here. */
5304 static rtx
5306 {
5309 /* Zero and sign extraction of a widened value. */
5317 /* It can also be represented (for zero-extend) as an AND with an
5318 immediate. */
5327 /* Now handle extended register, as this may also have an optional
5328 left shift by 1..4. */
5342 }
5344 /* Return true iff CODE is a shift supported in combination
5345 with arithmetic instructions. */
5347 static bool
5349 {
5351 }
5353 /* Helper function for rtx cost calculation. Calculate the cost of
5354 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5355 Return the calculated cost of the expression, recursing manually in to
5356 operands where needed. */
5358 static int
5360 {
5376 /* Integer multiply/fma. */
5378 {
5379 /* The multiply will be canonicalized as a shift, cost it as such. */
5383 {
5387 {
5389 {
5391 /* ARITH + shift-by-register. */
5394 /* ARITH + extended register. We don't have a cost field
5395 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5397 else
5398 /* ARITH + shift-by-immediate. */
5400 }
5401 else
5402 /* LSL (immediate). */
5405 }
5406 /* Strip extends as we will have costed them in the case above. */
5413 }
5415 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5416 compound and let the below cases handle it. After all, MNEG is a
5417 special-case alias of MSUB. */
5419 {
5422 }
5424 /* Integer multiplies or FMAs have zero/sign extending variants. */
5429 {
5434 {
5436 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5438 else
5439 /* MUL/SMULL/UMULL. */
5441 }
5444 }
5446 /* This is either an integer multiply or a MADD. In both cases
5447 we want to recurse and cost the operands. */
5452 {
5454 /* MADD/MSUB. */
5456 else
5457 /* MUL. */
5459 }
5462 }
5463 else
5464 {
5466 {
5467 /* Floating-point FMA/FMUL can also support negations of the
5468 operands. */
5475 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5477 else
5478 /* FMUL/FNMUL. */
5480 }
5485 }
5486 }
5488 static int
5490 machine_mode mode,
5491 addr_space_t as ATTRIBUTE_UNUSED,
5493 {
5501 {
5503 {
5504 /* This is a CONST or SYMBOL ref which will be split
5505 in a different way depending on the code model in use.
5506 Cost it through the generic infrastructure. */
5508 /* Divide through by the cost of one instruction to
5509 bring it to the same units as the address costs. */
5511 /* The cost is then the cost of preparing the address,
5512 followed by an immediate (possibly 0) offset. */
5514 }
5515 else
5516 {
5517 /* This is most likely a jump table from a case
5518 statement. */
5520 }
5521 }
5524 {
5536 else
5552 }
5556 {
5557 /* For the sake of calculating the cost of the shifted register
5558 component, we can treat same sized modes in the same way. */
5560 {
5573 /* We can't tell, or this is a 128-bit vector. */
5577 }
5578 }
5581 }
5583 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5584 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5585 to be taken. */
5587 int
5589 {
5590 /* When optimizing for speed, use the cost of unpredictable branches. */
5596 else
5598 }
5600 /* Return true if the RTX X in mode MODE is a zero or sign extract
5601 usable in an ADD or SUB (extended register) instruction. */
5602 static bool
5604 {
5605 /* Catch add with a sign extract.
5606 This is add_<optab><mode>_multp2. */
5609 {
5620 op1))
5621 {
5623 }
5624 }
5625 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
5626 No shift. */
5632 }
5634 static bool
5636 {
5638 {
5650 }
5651 }
5653 /* Return true iff X is an rtx that will match an extr instruction
5654 i.e. as described in the *extr<mode>5_insn family of patterns.
5655 OP0 and OP1 will be set to the operands of the shifts involved
5656 on success and will be NULL_RTX otherwise. */
5658 static bool
5660 {
5675 {
5676 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5688 {
5692 }
5693 }
5696 }
5698 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5699 storing it in *COST. Result is true if the total cost of the operation
5700 has now been calculated. */
5701 static bool
5703 {
5704 rtx inner;
5705 rtx comparator;
5709 {
5713 }
5714 else
5715 {
5719 }
5722 {
5723 /* Conditional branch. */
5726 else
5727 {
5729 {
5731 {
5732 /* TBZ/TBNZ/CBZ/CBNZ. */
5734 /* TBZ/TBNZ. */
5737 else
5738 /* CBZ/CBNZ. */
5742 }
5743 }
5745 {
5746 /* TBZ/TBNZ. */
5749 }
5750 }
5751 }
5753 {
5754 /* It's a conditional operation based on the status flags,
5755 so it must be some flavor of CSEL. */
5757 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
5766 }
5768 /* We don't know what this is, cost all operands. */
5770 }
5772 /* Calculate the cost of calculating X, storing it in *COST. Result
5773 is true if the total cost of the operation has now been calculated. */
5774 static bool
5777 {
5783 /* By default, assume that everything has equivalent cost to the
5784 cheapest instruction. Any additional costs are applied as a delta
5785 above this default. */
5789 {
5791 /* The cost depends entirely on the operands to SET. */
5797 {
5800 {
5814 }
5823 /* Fall through. */
5825 /* The cost is one per vector-register copied. */
5827 {
5831 }
5832 /* const0_rtx is in general free, but we will use an
5833 instruction to set a register to 0. */
5835 {
5836 /* The cost is 1 per register copied. */
5840 }
5841 else
5842 /* Cost is just the cost of the RHS of the set. */
5848 /* Bit-field insertion. Strip any redundant widening of
5849 the RHS to meet the width of the target. */
5860 {
5861 /* MOV immediate is assumed to always be cheap. */
5863 }
5864 else
5865 {
5866 /* BFM. */
5870 }
5875 /* We can't make sense of this, assume default cost. */
5878 }
5882 /* If an instruction can incorporate a constant within the
5883 instruction, the instruction's expression avoids calling
5884 rtx_cost() on the constant. If rtx_cost() is called on a
5885 constant, then it is usually because the constant must be
5886 moved into a register by one or more instructions.
5888 The exception is constant 0, which can be expressed
5889 as XZR/WZR and is therefore free. The exception to this is
5890 if we have (set (reg) (const0_rtx)) in which case we must cost
5891 the move. However, we can catch that when we cost the SET, so
5892 we don't need to consider that here. */
5895 else
5896 {
5897 /* To an approximation, building any other constant is
5898 proportionally expensive to the number of instructions
5899 required to build that constant. This is true whether we
5900 are compiling for SPEED or otherwise. */
5903 }
5908 {
5909 /* mov[df,sf]_aarch64. */
5911 /* FMOV (scalar immediate). */
5914 {
5915 /* This will be a load from memory. */
5918 else
5920 }
5921 else
5922 /* Otherwise this is +0.0. We get this using MOVI d0, #0
5923 or MOV v0.s[0], wzr - neither of which are modeled by the
5924 cost tables. Just use the default cost. */
5925 {
5926 }
5927 }
5933 {
5934 /* For loads we want the base cost of a load, plus an
5935 approximation for the additional cost of the addressing
5936 mode. */
5950 }
5958 {
5960 {
5961 /* FNEG. */
5963 }
5965 }
5968 {
5971 {
5972 /* CSETM. */
5975 }
5977 /* Cost this as SUB wzr, X. */
5981 }
5984 {
5985 /* Support (neg(fma...)) as a single instruction only if
5986 sign of zeros is unimportant. This matches the decision
5987 making in aarch64.md. */
5989 {
5990 /* FNMADD. */
5993 }
5995 /* FNEG. */
5998 }
6005 {
6008 else
6010 }
6020 {
6024 }
6027 {
6028 /* TODO: A write to the CC flags possibly costs extra, this
6029 needs encoding in the cost tables. */
6031 /* CC_ZESWPmode supports zero extend for free. */
6036 /* ANDS. */
6038 {
6041 }
6044 {
6045 /* ADDS (and CMN alias). */
6048 }
6051 {
6052 /* SUBS. */
6055 }
6058 {
6059 /* CMN. */
6066 }
6068 /* CMP.
6070 Compare can freely swap the order of operands, and
6071 canonicalization puts the more complex operation first.
6072 But the integer MINUS logic expects the shift/extend
6073 operation in op1. */
6076 {
6079 }
6081 }
6084 {
6085 /* FCMP. */
6090 {
6092 /* FCMP supports constant 0.0 for no extra cost. */
6094 }
6096 }
6099 {
6100 /* Vector compare. */
6105 {
6106 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6107 cost. */
6109 }
6111 }
6115 {
6119 cost_minus:
6122 /* Detect valid immediates. */
6128 {
6130 /* SUB(S) (immediate). */
6133 }
6135 /* Look for SUB (extended register). */
6137 {
6145 }
6149 /* Cost this as an FMA-alike operation. */
6153 {
6156 speed);
6158 }
6163 {
6165 {
6166 /* Vector SUB. */
6168 }
6170 {
6171 /* SUB(S). */
6173 }
6175 {
6176 /* FSUB. */
6178 }
6179 }
6181 }
6184 {
6185 rtx new_op0;
6190 cost_plus:
6193 {
6194 /* CSINC. */
6198 }
6203 {
6207 /* ADD (immediate). */
6210 }
6214 /* Look for ADD (extended register). */
6216 {
6224 }
6226 /* Strip any extend, leave shifts behind as we will
6227 cost them through mult_cost. */
6232 {
6234 speed);
6236 }
6241 {
6243 {
6244 /* Vector ADD. */
6246 }
6248 {
6249 /* ADD. */
6251 }
6253 {
6254 /* FADD. */
6256 }
6257 }
6259 }
6265 {
6268 else
6270 }
6275 {
6279 {
6282 else
6284 }
6286 }
6289 {
6296 }
6297 /* Fall through. */
6300 cost_logic:
6305 {
6309 }
6317 {
6318 /* This is a UBFM/SBFM. */
6323 }
6326 {
6327 /* We possibly get the immediate for free, this is not
6328 modelled. */
6331 {
6338 }
6339 else
6340 {
6343 /* Handle ORN, EON, or BIC. */
6349 /* If we had a shift on op0 then this is a logical-shift-
6350 by-register/immediate operation. Otherwise, this is just
6351 a logical operation. */
6353 {
6355 {
6356 /* Shift by immediate. */
6359 else
6361 }
6362 else
6364 }
6366 /* In both cases we want to cost both operands. */
6371 }
6372 }
6380 {
6381 /* Vector NOT. */
6384 }
6386 /* MVN-shifted-reg. */
6388 {
6395 }
6396 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6397 Handle the second form here taking care that 'a' in the above can
6398 be a shift. */
6400 {
6409 {
6412 else
6414 }
6417 }
6418 /* MVN. */
6427 /* If a value is written in SI mode, then zero extended to DI
6428 mode, the operation will in general be free as a write to
6429 a 'w' register implicitly zeroes the upper bits of an 'x'
6430 register. However, if this is
6432 (set (reg) (zero_extend (reg)))
6434 we must cost the explicit register move. */
6438 {
6442 /* MOV. */
6444 else
6445 /* Free, the cost is that of the SI mode operation. */
6449 }
6451 {
6452 /* All loads can zero extend to any size for free. */
6455 }
6458 {
6460 {
6461 /* UMOV. */
6463 }
6464 else
6465 {
6466 /* UXTB/UXTH. */
6468 }
6469 }
6474 {
6475 /* LDRSH. */
6477 {
6484 }
6486 }
6489 {
6492 else
6494 }
6502 {
6504 {
6506 {
6507 /* Vector shift (immediate). */
6509 }
6510 else
6511 {
6512 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6513 aliases. */
6515 }
6516 }
6518 /* We can incorporate zero/sign extend for free. */
6525 }
6526 else
6527 {
6529 {
6531 {
6532 /* Vector shift (register). */
6534 }
6535 else
6536 {
6537 /* LSLV. */
6539 }
6540 }
6542 }
6552 {
6553 /* ASR (immediate) and friends. */
6555 {
6558 else
6560 }
6564 }
6565 else
6566 {
6568 /* ASR (register) and friends. */
6570 {
6573 else
6575 }
6577 }
6583 {
6584 /* LDR. */
6587 }
6590 {
6591 /* ADRP, followed by ADD. */
6595 }
6598 {
6599 /* ADR. */
6602 }
6605 {
6606 /* One extra load instruction, after accessing the GOT. */
6610 }
6615 /* ADRP/ADD (immediate). */
6622 /* UBFX/SBFX. */
6624 {
6627 else
6629 }
6631 /* We can trust that the immediates used will be correct (there
6632 are no by-register forms), so we need only cost op0. */
6638 /* aarch64_rtx_mult_cost always handles recursion to its
6639 operands. */
6645 {
6657 }
6664 {
6668 /* There is no integer SQRT, so only DIV and UDIV can get
6669 here. */
6671 else
6673 }
6699 {
6702 else
6704 }
6706 /* FMSUB, FNMADD, and FNMSUB are free. */
6713 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
6714 and the by-element operand as operand 0. */
6718 /* Catch vector-by-element operations. The by-element operand can
6719 either be (vec_duplicate (vec_select (x))) or just
6720 (vec_select (x)), depending on whether we are multiplying by
6721 a vector or a scalar.
6723 Canonicalization is not very good in these cases, FMA4 will put the
6724 by-element operand as operand 0, FNMA4 will have it as operand 1. */
6735 /* If the remaining parameters are not registers,
6736 get the cost to put them into registers. */
6750 {
6752 {
6753 /*Vector truncate. */
6755 }
6756 else
6758 }
6763 {
6765 {
6766 /*Vector conversion. */
6768 }
6769 else
6771 }
6777 /* Strip the rounding part. They will all be implemented
6778 by the fcvt* family of instructions anyway. */
6780 {
6789 }
6792 {
6795 else
6797 }
6803 {
6804 /* ABS (vector). */
6807 }
6809 {
6812 /* FABD, which is analogous to FADD. */
6814 {
6821 }
6822 /* Simple FABS is analogous to FNEG. */
6825 }
6826 else
6827 {
6828 /* Integer ABS will either be split to
6829 two arithmetic instructions, or will be an ABS
6830 (scalar), which we don't model. */
6834 }
6840 {
6843 else
6844 {
6845 /* FMAXNM/FMINNM/FMAX/FMIN.
6846 TODO: This may not be accurate for all implementations, but
6847 we do not model this in the cost tables. */
6849 }
6850 }
6854 /* The floating point round to integer frint* instructions. */
6856 {
6861 }
6864 {
6869 }
6874 /* Decompose <su>muldi3_highpart. */
6876 mode == DImode
6877 /* (lshiftrt:TI */
6880 /* (mult:TI */
6882 /* (ANY_EXTEND:TI (reg:DI))
6883 (ANY_EXTEND:TI (reg:DI))) */
6890 /* (const_int 64) */
6893 {
6894 /* UMULH/SMULH. */
6902 }
6904 /* Fall through. */
6907 }
6914 }
6916 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
6917 calculated for X. This cost is stored in *COST. Returns true
6918 if the total cost of X was calculated. */
6919 static bool
6922 {
6926 {
6931 }
6934 }
6936 static int
6939 {
6945 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
6952 /* Moving between GPR and stack cost is the same as GP2GP. */
6957 /* To/From the stack register, we move via the gprs. */
6963 {
6964 /* 128-bit operations on general registers require 2 instructions. */
6972 /* When AdvSIMD instructions are disabled it is not possible to move
6973 a 128-bit value directly between Q registers. This is handled in
6974 secondary reload. A general register is used as a scratch to move
6975 the upper DI value and the lower DI value is moved directly,
6976 hence the cost is the sum of three moves. */
6981 }
6991 }
6993 static int
6995 reg_class_t rclass ATTRIBUTE_UNUSED,
6997 {
6999 }
7001 /* Return the number of instructions that can be issued per cycle. */
7002 static int
7004 {
7006 }
7008 static int
7010 {
7014 }
7016 /* Vectorizer cost model target hooks. */
7018 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7019 static int
7021 tree vectype,
7023 {
7027 {
7074 }
7075 }
7077 /* Implement targetm.vectorize.add_stmt_cost. */
7078 static unsigned
7082 {
7087 {
7092 /* Statements in an inner loop relative to the loop being
7093 vectorized are weighted more heavily. The value here is
7094 a function (linear for now) of the loop nest level. */
7096 {
7102 }
7106 }
7109 }
7113 /* Enum describing the various ways that the
7114 aarch64_parse_{arch,tune,cpu,extension} functions can fail.
7115 This way their callers can choose what kind of error to give. */
7117 enum aarch64_parse_opt_result
7118 {
7122 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */
7123 };
7125 /* Parse the architecture extension string STR and update ISA_FLAGS
7126 with the architecture features turned on or off. Return a
7127 aarch64_parse_opt_result describing the result. */
7129 static enum aarch64_parse_opt_result
7131 {
7132 /* The extension string is parsed left to right. */
7135 /* Flag to say whether we are adding or removing an extension. */
7139 {
7143 str++;
7148 else
7152 {
7156 }
7164 /* Scan over the extensions table trying to find an exact match. */
7166 {
7168 {
7169 /* Add or remove the extension. */
7172 else
7175 }
7176 }
7179 {
7180 /* Extension not found in list. */
7182 }
7185 };
7188 }
7190 /* Parse the TO_PARSE string and put the architecture struct that it
7191 selects into RES and the architectural features into ISA_FLAGS.
7192 Return an aarch64_parse_opt_result describing the parse result.
7193 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7195 static enum aarch64_parse_opt_result
7198 {
7210 else
7217 /* Loop through the list of supported ARCHes to find a match. */
7219 {
7221 {
7225 {
7226 /* TO_PARSE string contains at least one extension. */
7227 enum aarch64_parse_opt_result ext_res
7232 }
7233 /* Extension parsing was successful. Confirm the result
7234 arch and ISA flags. */
7238 }
7239 }
7241 /* ARCH name not found in list. */
7243 }
7245 /* Parse the TO_PARSE string and put the result tuning in RES and the
7246 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7247 describing the parse result. If there is an error parsing, RES and
7248 ISA_FLAGS are left unchanged. */
7250 static enum aarch64_parse_opt_result
7253 {
7265 else
7272 /* Loop through the list of supported CPUs to find a match. */
7274 {
7276 {
7281 {
7282 /* TO_PARSE string contains at least one extension. */
7283 enum aarch64_parse_opt_result ext_res
7288 }
7289 /* Extension parsing was successfull. Confirm the result
7290 cpu and ISA flags. */
7294 }
7295 }
7297 /* CPU name not found in list. */
7299 }
7301 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7302 Return an aarch64_parse_opt_result describing the parse result.
7303 If the parsing fails the RES does not change. */
7305 static enum aarch64_parse_opt_result
7307 {
7313 /* Loop through the list of supported CPUs to find a match. */
7315 {
7317 {
7320 }
7321 }
7323 /* CPU name not found in list. */
7325 }
7327 /* Parse TOKEN, which has length LENGTH to see if it is an option
7328 described in FLAG. If it is, return the index bit for that fusion type.
7329 If not, error (printing OPTION_NAME) and return zero. */
7331 static unsigned int
7336 {
7338 {
7342 }
7346 }
7348 /* Parse OPTION which is a comma-separated list of flags to enable.
7349 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7350 default state we inherit from the CPU tuning structures. OPTION_NAME
7351 gives the top-level option we are parsing in the -moverride string,
7352 for use in error messages. */
7354 static unsigned int
7359 {
7366 {
7369 token_length,
7370 flags,
7371 option_name);
7372 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7373 in the token stream, reset the supported operations. So:
7375 adrp+add.cmp+branch.none.adrp+add
7377 would have the result of turning on only adrp+add fusion. */
7383 }
7385 /* We ended with a comma, print something. */
7387 {
7390 }
7392 /* We still have one more token to parse. */
7395 token_length,
7396 flags,
7397 option_name);
7403 }
7405 /* Support for overriding instruction fusion. */
7407 static void
7410 {
7412 aarch64_fusible_pairs,
7415 }
7417 /* Support for overriding other tuning flags. */
7419 static void
7422 {
7423 tune->extra_tuning_flags
7425 aarch64_tuning_flags,
7428 }
7430 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
7431 we understand. If it is, extract the option string and handoff to
7432 the appropriate function. */
7434 void
7438 {
7444 {
7447 }
7449 /* Get the length of the option name. */
7451 /* Skip the '=' to get to the option string. */
7452 option_part++;
7455 {
7457 {
7460 }
7461 }
7465 }
7467 /* Parse STRING looking for options in the format:
7468 string :: option:string
7469 option :: name=substring
7470 name :: {a-z}
7471 substring :: defined by option. */
7473 static void
7476 {
7487 {
7489 /* Make this substring look like a string. */
7493 }
7495 /* One last option to parse. */
7498 }
7501 static void
7503 {
7509 /* If not opzimizing for size, set the default
7510 alignment to what the target wants. */
7512 {
7519 }
7520 }
7522 /* 'Unpack' up the internal tuning structs and update the options
7523 in OPTS. The caller must have set up selected_tune and selected_arch
7524 as all the other target-specific codegen decisions are
7525 derived from them. */
7527 void
7529 {
7532 /* Make a copy of the tuning parameters attached to the core, which
7533 we may later overwrite. */
7541 /* This target defaults to strict volatile bitfields. */
7545 /* -mgeneral-regs-only sets a mask in target_flags, make sure that
7546 aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags
7547 in case some code tries reading aarch64_isa_flags directly to check if
7548 FP is available. Reuse the aarch64_parse_extension machinery since it
7549 knows how to disable any other flags that fp implies. */
7551 {
7552 /* aarch64_parse_extension takes char* rather than const char* because
7553 it is usually called from within other parsing functions. */
7556 }
7561 }
7563 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
7564 specified in STR and throw errors if appropriate. Put the results if
7565 they are valid in RES and ISA_FLAGS. Return whether the option is
7566 valid. */
7568 static bool
7571 {
7572 enum aarch64_parse_opt_result parse_res
7579 {
7591 }
7594 }
7596 /* Validate a command-line -march option. Parse the arch and extensions
7597 (if any) specified in STR and throw errors if appropriate. Put the
7598 results, if they are valid, in RES and ISA_FLAGS. Return whether the
7599 option is valid. */
7601 static bool
7604 {
7605 enum aarch64_parse_opt_result parse_res
7612 {
7624 }
7627 }
7629 /* Validate a command-line -mtune option. Parse the cpu
7630 specified in STR and throw errors if appropriate. Put the
7631 result, if it is valid, in RES. Return whether the option is
7632 valid. */
7634 static bool
7636 {
7637 enum aarch64_parse_opt_result parse_res
7644 {
7653 }
7655 }
7657 /* Return the CPU corresponding to the enum CPU.
7658 If it doesn't specify a cpu, return the default. */
7662 {
7666 /* The & 0x3f is to extract the bottom 6 bits that encode the
7667 default cpu as selected by the --with-cpu GCC configure option
7668 in config.gcc.
7669 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
7670 flags mechanism should be reworked to make it more sane. */
7672 }
7674 /* Return the architecture corresponding to the enum ARCH.
7675 If it doesn't specify a valid architecture, return the default. */
7679 {
7686 }
7688 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
7689 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
7690 tuning structs. In particular it must set selected_tune and
7691 aarch64_isa_flags that define the available ISA features and tuning
7692 decisions. It must also set selected_arch as this will be used to
7693 output the .arch asm tags for each function. */
7695 static void
7697 {
7710 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
7711 If either of -march or -mtune is given, they override their
7712 respective component of -mcpu. */
7724 /* If the user did not specify a processor, choose the default
7725 one for them. This will be the CPU set during configuration using
7726 --with-cpu, otherwise it is "generic". */
7728 {
7730 {
7734 }
7735 else
7736 {
7737 /* Get default configure-time CPU. */
7740 }
7744 }
7745 /* If both -mcpu and -march are specified check that they are architecturally
7746 compatible, warn if they're not and prefer the -march ISA flags. */
7748 {
7750 {
7754 }
7759 }
7760 else
7761 {
7762 /* -mcpu but no -march. */
7769 }
7771 /* Set the arch as well as we will need it when outputing
7772 the .arch directive in assembly. */
7774 {
7777 }
7782 #ifndef HAVE_AS_MABI_OPTION
7783 /* The compiler may have been configured with 2.23.* binutils, which does
7784 not have support for ILP32. */
7787 #endif
7789 /* Make sure we properly set up the explicit options. */
7802 /* Save these options as the default ones in case we push and pop them later
7803 while processing functions with potential target attributes. */
7804 target_option_default_node = target_option_current_node
7809 }
7811 /* Implement targetm.override_options_after_change. */
7813 static void
7815 {
7817 }
7821 {
7825 }
7827 void
7829 {
7831 }
7833 /* A checking mechanism for the implementation of the various code models. */
7834 static void
7836 {
7838 {
7840 {
7845 #ifdef HAVE_AS_SMALL_PIC_RELOCS
7847 ? AARCH64_CMODEL_SMALL_PIC
7849 #else
7851 #endif
7858 }
7859 }
7860 else
7862 }
7864 /* Print to F the architecture features specified by ISA_FLAGS. */
7866 static void
7868 {
7876 }
7878 /* Implement TARGET_OPTION_SAVE. */
7880 static void
7882 {
7884 }
7886 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
7887 using the information saved in PTR. */
7889 static void
7891 {
7899 }
7901 /* Implement TARGET_OPTION_PRINT. */
7903 static void
7905 {
7914 }
7918 void
7920 {
7922 }
7924 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
7925 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
7926 of the function, if such exists. This function may be called multiple
7927 times on a single function so use aarch64_previous_fndecl to avoid
7928 setting up identical state. */
7930 static void
7932 {
7933 tree old_tree = (aarch64_previous_fndecl
7937 tree new_tree = (fndecl
7943 {
7946 ;
7949 {
7954 else
7957 }
7960 {
7968 else
7971 }
7972 }
7973 }
7975 /* Enum describing the various ways we can handle attributes.
7976 In many cases we can reuse the generic option handling machinery. */
7978 enum aarch64_attr_opt_type
7979 {
7983 aarch64_attr_custom /* Attribute requires a custom handling function. */
7984 };
7986 /* All the information needed to handle a target attribute.
7987 NAME is the name of the attribute.
7988 ATTR_TYPE specifies the type of behaviour of the attribute as described
7989 in the definition of enum aarch64_attr_opt_type.
7990 ALLOW_NEG is true if the attribute supports a "no-" form.
7991 HANDLER is the function that takes the attribute string and whether
7992 it is a pragma or attribute and handles the option. It is needed only
7993 when the ATTR_TYPE is aarch64_attr_custom.
7994 OPT_NUM is the enum specifying the option that the attribute modifies.
7995 This is needed for attributes that mirror the behaviour of a command-line
7996 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
7997 aarch64_attr_enum. */
7999 struct aarch64_attribute_info
8000 {
8006 };
8008 /* Handle the ARCH_STR argument to the arch= target attribute.
8009 PRAGMA_OR_ATTR is used in potential error messages. */
8011 static bool
8013 {
8015 enum aarch64_parse_opt_result parse_res
8019 {
8024 }
8027 {
8040 }
8043 }
8045 /* Handle the argument CPU_STR to the cpu= target attribute.
8046 PRAGMA_OR_ATTR is used in potential error messages. */
8048 static bool
8050 {
8052 enum aarch64_parse_opt_result parse_res
8056 {
8064 }
8067 {
8080 }
8083 }
8085 /* Handle the argument STR to the tune= target attribute.
8086 PRAGMA_OR_ATTR is used in potential error messages. */
8088 static bool
8090 {
8092 enum aarch64_parse_opt_result parse_res
8096 {
8101 }
8104 {
8110 }
8113 }
8115 /* Parse an architecture extensions target attribute string specified in STR.
8116 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8117 if successful. Update aarch64_isa_flags to reflect the ISA features
8118 modified.
8119 PRAGMA_OR_ATTR is used in potential error messages. */
8121 static bool
8123 {
8127 /* We allow "+nothing" in the beginning to clear out all architectural
8128 features if the user wants to handpick specific features. */
8130 {
8133 }
8138 {
8141 }
8144 {
8157 }
8160 }
8162 /* The target attributes that we support. On top of these we also support just
8163 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8164 handled explicitly in aarch64_process_one_target_attr. */
8167 {
8169 OPT_mgeneral_regs_only },
8171 OPT_mfix_cortex_a53_835769 },
8175 OPT_momit_leaf_frame_pointer },
8178 OPT_march_ },
8181 OPT_mtune_ },
8183 };
8185 /* Parse ARG_STR which contains the definition of one target attribute.
8186 Show appropriate errors if any or return true if the attribute is valid.
8187 PRAGMA_OR_ATTR holds the string to use in error messages about whether
8188 we're processing a target attribute or pragma. */
8190 static bool
8192 {
8198 {
8201 }
8206 /* Skip leading whitespace. */
8208 str_to_check++;
8210 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
8211 It is easier to detect and handle it explicitly here rather than going
8212 through the machinery for the rest of the target attributes in this
8213 function. */
8218 {
8221 }
8224 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
8225 and point ARG to "foo". */
8227 {
8229 arg++;
8230 }
8233 {
8234 /* If the names don't match up, or the user has given an argument
8235 to an attribute that doesn't accept one, or didn't give an argument
8236 to an attribute that expects one, fail to match. */
8244 {
8248 }
8250 /* If the name matches but the attribute does not allow "no-" versions
8251 then we can't match. */
8253 {
8257 }
8260 {
8261 /* Has a custom handler registered.
8262 For example, cpu=, arch=, tune=. */
8269 /* Either set or unset a boolean option. */
8271 {
8279 }
8280 /* Set or unset a bit in the target_flags. aarch64_handle_option
8281 should know what mask to apply given the option number. */
8283 {
8285 /* We only need to specify the option number.
8286 aarch64_handle_option will know which mask to apply. */
8292 }
8293 /* Use the option setting machinery to set an option to an enum. */
8295 {
8302 {
8305 global_dc);
8306 }
8307 else
8308 {
8311 }
8313 }
8316 }
8317 }
8320 }
8322 /* Count how many times the character C appears in
8323 NULL-terminated string STR. */
8325 static unsigned int
8327 {
8330 {
8332 res++;
8334 str++;
8335 }
8338 }
8340 /* Parse the tree in ARGS that contains the target attribute information
8341 and update the global target options space. PRAGMA_OR_ATTR is a string
8342 to be used in error messages, specifying whether this is processing
8343 a target attribute or a target pragma. */
8345 bool
8347 {
8349 {
8350 do
8351 {
8354 {
8357 }
8362 }
8363 /* We expect to find a string to parse. */
8371 {
8374 }
8376 /* Used to catch empty spaces between commas i.e.
8377 attribute ((target ("attr1,,attr2"))). */
8380 /* Handle multiple target attributes separated by ','. */
8385 {
8386 num_attrs++;
8388 {
8391 }
8394 }
8397 {
8401 }
8404 }
8406 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
8407 process attribute ((target ("..."))). */
8409 static bool
8411 {
8414 tree old_optimize;
8418 /* If what we're processing is the current pragma string then the
8419 target option node is already stored in target_option_current_node
8420 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
8421 having to re-parse the string. This is especially useful to keep
8422 arm_neon.h compile times down since that header contains a lot
8423 of intrinsics enclosed in pragmas. */
8425 {
8428 }
8434 /* If the function changed the optimization levels as well as setting
8435 target options, start with the optimizations specified. */
8440 /* Save the current target options to restore at the end. */
8443 /* If fndecl already has some target attributes applied to it, unpack
8444 them so that we add this attribute on top of them, rather than
8445 overwriting them. */
8447 {
8453 }
8454 else
8461 /* Set up any additional state. */
8463 {
8465 /* Initialize SIMD builtins if we haven't already.
8466 Set current_target_pragma to NULL for the duration so that
8467 the builtin initialization code doesn't try to tag the functions
8468 being built with the attributes specified by any current pragma, thus
8469 going into an infinite recursion. */
8471 {
8476 }
8478 }
8479 else
8485 {
8490 }
8498 }
8500 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
8501 tri-bool options (yes, no, don't care) and the default value is
8502 DEF, determine whether to reject inlining. */
8504 static bool
8507 {
8508 /* If the callee doesn't care, always allow inlining. */
8512 /* If the caller doesn't care, always allow inlining. */
8516 /* Otherwise, allow inlining if either the callee and caller values
8517 agree, or if the callee is using the default value. */
8519 }
8521 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
8522 to inline CALLEE into CALLER based on target-specific info.
8523 Make sure that the caller and callee have compatible architectural
8524 features. Then go through the other possible target attributes
8525 and see if they can block inlining. Try not to reject always_inline
8526 callees unless they are incompatible architecturally. */
8528 static bool
8530 {
8534 /* If callee has no option attributes, then it is ok to inline. */
8545 /* Callee's ISA flags should be a subset of the caller's. */
8550 /* Allow non-strict aligned functions inlining into strict
8551 aligned ones. */
8561 /* If the architectural features match up and the callee is always_inline
8562 then the other attributes don't matter. */
8574 /* Honour explicit requests to workaround errata. */
8581 /* If the user explicitly specified -momit-leaf-frame-pointer for the
8582 caller and calle and they don't match up, reject inlining. */
8589 /* If the callee has specific tuning overrides, respect them. */
8594 /* If the user specified tuning override strings for the
8595 caller and callee and they don't match up, reject inlining.
8596 We just do a string compare here, we don't analyze the meaning
8597 of the string, as it would be too costly for little gain. */
8605 }
8607 /* Return true if SYMBOL_REF X binds locally. */
8609 static bool
8611 {
8615 }
8617 /* Return true if SYMBOL_REF X is thread local */
8618 static bool
8620 {
8628 }
8630 /* Classify a TLS symbol into one of the TLS kinds. */
8631 enum aarch64_symbol_type
8633 {
8637 {
8654 }
8655 }
8657 /* Return the method that should be used to access SYMBOL_REF or
8658 LABEL_REF X in context CONTEXT. */
8660 enum aarch64_symbol_type
8663 {
8665 {
8667 {
8682 }
8683 }
8686 {
8694 {
8696 /* When we retreive symbol + offset address, we have to make sure
8697 the offset does not cause overflow of the final address. But
8698 we have no way of knowing the address of symbol at compile time
8699 so we can't accurately say if the distance between the PC and
8700 symbol + offset is outside the addressible range of +/-1M in the
8701 TINY code model. So we rely on images not being greater than
8702 1M and cap the offset at 1M and anything beyond 1M will have to
8703 be loaded using an alternative mechanism. */
8710 /* Same reasoning as the tiny code model, but the offset cap here is
8711 4G. */
8732 }
8733 }
8735 /* By default push everything into the constant pool. */
8737 }
8739 bool
8741 {
8743 }
8745 bool
8747 {
8755 }
8757 /* Return true if X holds either a quarter-precision or
8758 floating-point +0.0 constant. */
8759 static bool
8761 {
8768 /* We only handle moving 0.0 to a TFmode register. */
8773 }
8775 static bool
8777 {
8778 /* Do not allow vector struct mode constants. We could support
8779 0 and -1 easily, but they need support in aarch64-simd.md. */
8783 /* This could probably go away because
8784 we now decompose CONST_INTs according to expand_mov_immediate. */
8795 }
8797 rtx
8799 {
8805 /* Can return in any reg. */
8808 }
8810 /* On AAPCS systems, this is the "struct __va_list". */
8813 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
8814 Return the type to use as __builtin_va_list.
8816 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
8818 struct __va_list
8819 {
8820 void *__stack;
8821 void *__gr_top;
8822 void *__vr_top;
8823 int __gr_offs;
8824 int __vr_offs;
8825 }; */
8827 static tree
8829 {
8830 tree va_list_name;
8833 /* Create the type. */
8835 /* Give it the required name. */
8837 TYPE_DECL,
8839 va_list_type);
8844 /* Create the fields. */
8847 ptr_type_node);
8850 ptr_type_node);
8853 ptr_type_node);
8856 integer_type_node);
8859 integer_type_node);
8879 /* Compute its layout. */
8883 }
8885 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
8886 static void
8888 {
8892 tree t;
8898 gr_save_area_size
8900 vr_save_area_size
8904 {
8907 }
8916 NULL_TREE);
8918 NULL_TREE);
8920 NULL_TREE);
8922 NULL_TREE);
8924 NULL_TREE);
8926 /* Emit code to initialize STACK, which points to the next varargs stack
8927 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
8928 by named arguments. STACK is 8-byte aligned. */
8935 /* Emit code to initialize GRTOP, the top of the GR save area.
8936 virtual_incoming_args_rtx should have been 16 byte aligned. */
8941 /* Emit code to initialize VRTOP, the top of the VR save area.
8942 This address is gr_save_area_bytes below GRTOP, rounded
8943 down to the next 16-byte boundary. */
8953 /* Emit code to initialize GROFF, the offset from GRTOP of the
8954 next GPR argument. */
8959 /* Likewise emit code to initialize VROFF, the offset from FTOP
8960 of the next VR argument. */
8964 }
8966 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
8968 static tree
8971 {
8972 tree addr;
8978 machine_mode mode;
9005 type,
9009 {
9010 /* TYPE passed in fp/simd registers. */
9022 {
9025 }
9028 {
9030 }
9031 }
9032 else
9033 {
9034 /* TYPE passed in general registers. */
9047 {
9049 }
9050 }
9052 /* Get a local temporary for the field value. */
9055 /* Emit code to branch if off >= 0. */
9061 {
9062 /* Emit: offs = (offs + 15) & -16. */
9068 }
9069 else
9072 /* Update ap.__[g|v]r_offs */
9077 /* String up. */
9081 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9086 /* String up: make sure the assignment happens before the use. */
9090 /* Prepare the trees handling the argument that is passed on the stack;
9091 the top level node will store in ON_STACK. */
9094 {
9095 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9103 }
9104 else
9106 /* Advance ap.__stack */
9114 /* String up roundup and advance. */
9117 /* String up with arg */
9119 /* Big-endianness related address adjustment. */
9122 {
9126 }
9131 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
9141 {
9142 /* type ha; // treat as "struct {ftype field[n];}"
9143 ... [computing offs]
9144 for (i = 0; i <nregs; ++i, offs += 16)
9145 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
9146 return ha; */
9150 /* Declare a local variable. */
9154 /* Establish the base type. */
9156 {
9169 /* The half precision and quad precision are not fully supported yet. Enable
9170 the following code after the support is complete. Need to find the correct
9171 type node for __fp16 *. */
9172 #if 0
9177 #endif
9180 {
9184 }
9188 }
9190 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
9198 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
9200 {
9210 }
9214 }
9224 }
9226 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
9228 static void
9232 {
9234 CUMULATIVE_ARGS local_cum;
9237 /* The caller has advanced CUM up to, but not beyond, the last named
9238 argument. Advance a local copy of CUM past the last "real" named
9239 argument, to find out how many registers are left over. */
9243 /* Found out how many registers we need to save. */
9248 {
9251 }
9254 {
9256 {
9259 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
9267 }
9269 {
9270 /* We can't use move_block_from_reg, because it will use
9271 the wrong mode, storing D regs only. */
9275 /* Set OFF to the offset from virtual_incoming_args_rtx of
9276 the first vector register. The VR save area lies below
9277 the GR one, and is aligned to 16 bytes. */
9283 {
9291 }
9292 }
9293 }
9295 /* We don't save the size into *PRETEND_SIZE because we want to avoid
9296 any complication of having crtl->args.pretend_args_size changed. */
9301 }
9303 static void
9305 {
9308 {
9310 {
9313 }
9314 }
9315 }
9317 /* Walk down the type tree of TYPE counting consecutive base elements.
9318 If *MODEP is VOIDmode, then set it to the first valid floating point
9319 type. If a non-floating point type is found, or if a floating point
9320 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
9321 otherwise return the count in the sub-tree. */
9322 static int
9324 {
9325 machine_mode mode;
9326 HOST_WIDE_INT size;
9329 {
9357 /* Use V2SImode and V4SImode as representatives of all 64-bit
9358 and 128-bit vector types. */
9361 {
9370 }
9375 /* Vector modes are considered to be opaque: two vectors are
9376 equivalent for the purposes of being homogeneous aggregates
9377 if they are the same size. */
9384 {
9388 /* Can't handle incomplete types nor sizes that are not
9389 fixed. */
9396 || !index
9407 /* There must be no padding. */
9412 }
9415 {
9418 tree field;
9420 /* Can't handle incomplete types nor sizes that are not
9421 fixed. */
9427 {
9435 }
9437 /* There must be no padding. */
9442 }
9446 {
9447 /* These aren't very interesting except in a degenerate case. */
9450 tree field;
9452 /* Can't handle incomplete types nor sizes that are not
9453 fixed. */
9459 {
9467 }
9469 /* There must be no padding. */
9474 }
9478 }
9481 }
9483 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
9484 type as described in AAPCS64 \S 4.1.2.
9486 See the comment above aarch64_composite_type_p for the notes on MODE. */
9488 static bool
9490 machine_mode mode)
9491 {
9501 }
9503 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
9504 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
9505 array types. The C99 floating-point complex types are also considered
9506 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
9507 types, which are GCC extensions and out of the scope of AAPCS64, are
9508 treated as composite types here as well.
9510 Note that MODE itself is not sufficient in determining whether a type
9511 is such a composite type or not. This is because
9512 stor-layout.c:compute_record_mode may have already changed the MODE
9513 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
9514 structure with only one field may have its MODE set to the mode of the
9515 field. Also an integer mode whose size matches the size of the
9516 RECORD_TYPE type may be used to substitute the original mode
9517 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
9518 solely relied on. */
9520 static bool
9522 machine_mode mode)
9523 {
9536 }
9538 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
9539 shall be passed or returned in simd/fp register(s) (providing these
9540 parameter passing registers are available).
9542 Upon successful return, *COUNT returns the number of needed registers,
9543 *BASE_MODE returns the mode of the individual register and when IS_HAF
9544 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
9545 floating-point aggregate or a homogeneous short-vector aggregate. */
9547 static bool
9549 const_tree type,
9553 {
9561 {
9564 }
9566 {
9570 }
9572 {
9576 {
9579 }
9580 else
9582 }
9583 else
9588 }
9590 /* Implement TARGET_STRUCT_VALUE_RTX. */
9592 static rtx
9595 {
9597 }
9599 /* Implements target hook vector_mode_supported_p. */
9600 static bool
9602 {
9613 }
9615 /* Return appropriate SIMD container
9616 for MODE within a vector of WIDTH bits. */
9617 static machine_mode
9619 {
9622 {
9625 {
9640 }
9641 else
9643 {
9654 }
9655 }
9657 }
9659 /* Return 128-bit container as the preferred SIMD mode for MODE. */
9660 static machine_mode
9662 {
9664 }
9666 /* Return the bitmask of possible vector sizes for the vectorizer
9667 to iterate over. */
9668 static unsigned int
9670 {
9672 }
9674 /* Implement TARGET_MANGLE_TYPE. */
9678 {
9679 /* The AArch64 ABI documents say that "__va_list" has to be
9680 managled as if it is in the "std" namespace. */
9684 /* Half-precision float. */
9688 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
9689 builtin types. */
9693 /* Use the default mangling. */
9695 }
9698 /* Return true if the rtx_insn contains a MEM RTX somewhere
9699 in it. */
9701 static bool
9703 {
9710 }
9712 /* Find the first rtx_insn before insn that will generate an assembly
9713 instruction. */
9717 {
9721 do
9722 {
9724 }
9728 }
9730 static bool
9732 {
9734 /* A number of these may be AArch32 only. */
9739 };
9742 {
9745 }
9748 }
9750 /* Check if there is a register dependency between a load and the insn
9751 for which we hold recog_data. */
9753 static bool
9755 {
9756 rtx load_reg;
9766 {
9772 }
9774 }
9777 /* When working around the Cortex-A53 erratum 835769,
9778 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
9779 instruction and has a preceding memory instruction such that a NOP
9780 should be inserted between them. */
9782 bool
9784 {
9787 rtx body;
9800 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
9801 Restore recog state to INSN to avoid state corruption. */
9809 /* If the previous insn is a memory op and there is no dependency between
9810 it and the DImode madd, emit a NOP between them. If body is NULL then we
9811 have a complex memory operation, probably a load/store pair.
9812 Be conservative for now and emit a NOP. */
9819 }
9822 /* Implement FINAL_PRESCAN_INSN. */
9824 void
9826 {
9829 }
9832 /* Return the equivalent letter for size. */
9833 static char
9835 {
9837 {
9843 }
9844 }
9846 /* Return true iff x is a uniform vector of floating-point
9847 constants, and the constant can be represented in
9848 quarter-precision form. Note, as aarch64_float_const_representable
9849 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
9850 static bool
9852 {
9867 {
9875 }
9878 }
9880 /* Return true for valid and false for invalid. */
9881 bool
9884 {
9885 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
9886 matches = 1; \
9887 for (i = 0; i < idx; i += (STRIDE)) \
9888 if (!(TEST)) \
9889 matches = 0; \
9890 if (matches) \
9891 { \
9892 immtype = (CLASS); \
9893 elsize = (ELSIZE); \
9894 eshift = (SHIFT); \
9895 emvn = (NEG); \
9896 break; \
9897 }
9907 {
9913 {
9918 }
9921 }
9923 /* Splat vector constant out into a byte vector. */
9925 {
9926 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
9927 it must be laid out in the vector register in reverse order. */
9933 {
9936 }
9938 {
9941 }
9942 else
9946 {
9949 {
9952 }
9955 }
9956 }
9958 /* Sanity check. */
9961 do
9962 {
10011 }
10018 {
10028 /* Un-invert bytes of recognized vector, if necessary. */
10034 {
10035 /* FIXME: Broken on 32-bit H_W_I hosts. */
10044 }
10045 else
10046 {
10050 /* Construct 'abcdefgh' because the assembler cannot handle
10051 generic constants. */
10056 }
10057 }
10060 #undef CHECK
10061 }
10063 /* Check of immediate shift constants are within range. */
10064 bool
10066 {
10070 else
10072 }
10074 /* Return true if X is a uniform vector where all elements
10075 are either the floating-point constant 0.0 or the
10076 integer constant 0. */
10077 bool
10079 {
10081 }
10083 bool
10085 {
10090 {
10095 }
10098 }
10100 bool
10103 machine_mode mode)
10104 {
10117 }
10119 /* Return a const_int vector of VAL. */
10120 rtx
10122 {
10131 }
10133 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10135 bool
10137 {
10138 machine_mode vmode;
10144 }
10146 /* Construct and return a PARALLEL RTX vector with elements numbering the
10147 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10148 the vector - from the perspective of the architecture. This does not
10149 line up with GCC's perspective on lane numbers, so we end up with
10150 different masks depending on our target endian-ness. The diagram
10151 below may help. We must draw the distinction when building masks
10152 which select one half of the vector. An instruction selecting
10153 architectural low-lanes for a big-endian target, must be described using
10154 a mask selecting GCC high-lanes.
10156 Big-Endian Little-Endian
10158 GCC 0 1 2 3 3 2 1 0
10159 | x | x | x | x | | x | x | x | x |
10160 Architecture 3 2 1 0 3 2 1 0
10162 Low Mask: { 2, 3 } { 0, 1 }
10163 High Mask: { 0, 1 } { 2, 3 }
10164 */
10166 rtx
10168 {
10174 rtx t1;
10179 else
10187 }
10189 /* Check OP for validity as a PARALLEL RTX vector with elements
10190 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
10191 from the perspective of the architecture. See the diagram above
10192 aarch64_simd_vect_par_cnst_half for more details. */
10194 bool
10197 {
10210 {
10217 }
10219 }
10221 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
10222 HIGH (exclusive). */
10223 void
10225 const_tree exp)
10226 {
10227 HOST_WIDE_INT lane;
10232 {
10235 else
10237 }
10238 }
10240 /* Return TRUE if OP is a valid vector addressing mode. */
10241 bool
10243 {
10246 }
10248 /* Emit a register copy from operand to operand, taking care not to
10249 early-clobber source registers in the process.
10251 COUNT is the number of components into which the copy needs to be
10252 decomposed. */
10253 void
10256 {
10266 else
10270 }
10272 /* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
10273 one of VSTRUCT modes: OI, CI or XI. */
10274 int
10276 {
10277 machine_mode mode;
10282 {
10285 {
10294 }
10295 }
10297 }
10299 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
10300 one of VSTRUCT modes: OI, CI, EI, or XI. */
10301 int
10303 {
10305 }
10307 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
10308 alignment of a vector to 128 bits. */
10309 static HOST_WIDE_INT
10311 {
10314 }
10316 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
10317 static bool
10319 {
10323 /* We guarantee alignment for vectors up to 128-bits. */
10328 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
10330 }
10332 /* If VALS is a vector constant that can be loaded into a register
10333 using DUP, generate instructions to do so and return an RTX to
10334 assign to the register. Otherwise return NULL_RTX. */
10335 static rtx
10337 {
10342 rtx x;
10349 {
10353 }
10358 /* We can load this constant by using DUP and a constant in a
10359 single ARM register. This will be cheaper than a vector
10360 load. */
10363 }
10366 /* Generate code to load VALS, which is a PARALLEL containing only
10367 constants (for vec_init) or CONST_VECTOR, efficiently into a
10368 register. Returns an RTX to copy into the register, or NULL_RTX
10369 for a PARALLEL that can not be converted into a CONST_VECTOR. */
10370 static rtx
10372 {
10374 rtx const_dup;
10383 {
10384 /* A CONST_VECTOR must contain only CONST_INTs and
10385 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
10386 Only store valid constants in a CONST_VECTOR. */
10388 {
10391 n_const++;
10392 }
10395 }
10396 else
10401 /* Load using MOVI/MVNI. */
10404 /* Loaded using DUP. */
10407 /* Load from constant pool. We can not take advantage of single-cycle
10408 LD1 because we need a PC-relative addressing mode. */
10410 else
10411 /* A PARALLEL containing something not valid inside CONST_VECTOR.
10412 We can not construct an initializer. */
10414 }
10416 void
10418 {
10427 {
10431 else
10436 }
10439 {
10442 {
10445 }
10446 }
10448 /* Splat a single non-constant element if we can. */
10450 {
10454 }
10456 /* Half the fields (or less) are non-constant. Load constant then overwrite
10457 varying fields. Hope that this is more efficient than using the stack. */
10459 {
10462 /* Load constant part of vector. We really don't care what goes into the
10463 parts we will overwrite, but we're more likely to be able to load the
10464 constant efficiently if it has fewer, larger, repeating parts
10465 (see aarch64_simd_valid_immediate). */
10467 {
10473 {
10474 /* Look in the copied vector, as more elements are const. */
10477 {
10480 }
10481 }
10483 }
10486 /* Insert variables. */
10491 {
10497 }
10499 }
10501 /* Construct the vector in memory one field at a time
10502 and load the whole vector. */
10510 }
10512 static unsigned HOST_WIDE_INT
10514 {
10515 return
10518 }
10520 #ifndef TLS_SECTION_ASM_FLAG
10522 #endif
10524 void
10526 tree decl ATTRIBUTE_UNUSED)
10527 {
10530 /* If we have already declared this section, we can use an
10531 abbreviated form to switch back to it -- unless this section is
10532 part of a COMDAT groups, in which case GAS requires the full
10533 declaration every time. */
10536 {
10539 }
10562 {
10568 else
10571 #ifdef TYPE_OPERAND_FMT
10573 #else
10575 #endif
10582 {
10585 else
10588 }
10589 }
10592 }
10594 /* Select a format to encode pointers in exception handling data. */
10595 int
10597 {
10600 {
10606 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
10607 for everything. */
10611 /* No assumptions here. 8-byte relocs required. */
10614 }
10616 }
10618 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
10619 by the function fndecl. */
10621 void
10623 tree fndecl)
10624 {
10630 else
10640 /* Print the cpu name we're tuning for in the comments, might be
10641 useful to readers of the generated asm. */
10649 /* Don't forget the type directive for ELF. */
10652 }
10654 /* Emit load exclusive. */
10656 static void
10659 {
10663 {
10670 }
10673 }
10675 /* Emit store exclusive. */
10677 static void
10680 {
10684 {
10691 }
10694 }
10696 /* Mark the previous jump instruction as unlikely. */
10698 static void
10700 {
10705 }
10707 /* Expand a compare and swap pattern. */
10709 void
10711 {
10727 /* Normally the succ memory model must be stronger than fail, but in the
10728 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
10729 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
10736 {
10739 /* For short modes, we're going to perform the comparison in SImode,
10740 so do the zero-extension now. */
10744 /* Fall through. */
10748 /* Force the value into a register if needed. */
10755 }
10758 {
10765 }
10775 }
10777 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
10778 sequence implementing an atomic operation. */
10780 static void
10782 {
10789 {
10791 }
10792 }
10794 /* Split a compare and swap pattern. */
10796 void
10798 {
10800 machine_mode mode;
10805 rtx model_rtx;
10819 {
10822 }
10825 /* The initial load can be relaxed for a __sync operation since a final
10826 barrier will be emitted to stop code hoisting. */
10830 else
10842 {
10847 }
10848 else
10849 {
10853 }
10857 /* Emit any final barrier needed for a __sync operation. */
10860 }
10862 /* Split an atomic operation. */
10864 void
10867 {
10873 rtx x;
10882 else
10886 /* The initial load can be relaxed for a __sync operation since a final
10887 barrier will be emitted to stop code hoisting. */
10891 else
10895 {
10909 {
10912 }
10913 /* Fall through. */
10919 }
10929 /* Emit any final barrier needed for a __sync operation. */
10932 }
10934 static void
10936 {
10937 /* Half-precision float operations. The compiler handles all operations
10938 with NULL libfuncs by converting to SFmode. */
10940 /* Conversions. */
10944 /* Arithmetic. */
10951 /* Comparisons. */
10959 }
10961 /* Target hook for c_mode_for_suffix. */
10962 static machine_mode
10964 {
10969 }
10971 /* We can only represent floating point constants which will fit in
10972 "quarter-precision" values. These values are characterised by
10973 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
10974 by:
10976 (-1)^s * (n/16) * 2^r
10978 Where:
10979 's' is the sign bit.
10980 'n' is an integer in the range 16 <= n <= 31.
10981 'r' is an integer in the range -3 <= r <= 4. */
10983 /* Return true iff X can be represented by a quarter-precision
10984 floating point immediate operand X. Note, we cannot represent 0.0. */
10985 bool
10987 {
10988 /* This represents our current view of how many bits
10989 make up the mantissa. */
10999 /* We don't support HFmode constants yet. */
11005 /* We cannot represent infinities, NaNs or +/-zero. We won't
11006 know if we have +zero until we analyse the mantissa, but we
11007 can reject the other invalid values. */
11012 /* Extract exponent. */
11016 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
11017 highest (sign) bit, with a fixed binary point at bit point_pos.
11018 m1 holds the low part of the mantissa, m2 the high part.
11019 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
11020 bits for the mantissa, this can fail (low bits will be lost). */
11024 /* If the low part of the mantissa has bits set we cannot represent
11025 the value. */
11028 /* We have rejected the lower HOST_WIDE_INT, so update our
11029 understanding of how many bits lie in the mantissa and
11030 look only at the high HOST_WIDE_INT. */
11034 /* We can only represent values with a mantissa of the form 1.xxxx. */
11039 /* Having filtered unrepresentable values, we may now remove all
11040 but the highest 5 bits. */
11043 /* We cannot represent the value 0.0, so reject it. This is handled
11044 elsewhere. */
11048 /* Then, as bit 4 is always set, we can mask it off, leaving
11049 the mantissa in the range [0, 15]. */
11053 /* GCC internally does not use IEEE754-like encoding (where normalized
11054 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
11055 Our mantissa values are shifted 4 places to the left relative to
11056 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
11057 by 5 places to correct for GCC's representation. */
11061 }
11065 machine_mode mode,
11067 {
11077 /* This will return true to show const_vector is legal for use as either
11078 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
11079 also update INFO to show how the immediate should be generated. */
11088 {
11092 else
11093 {
11094 #define buf_size 20
11095 REAL_VALUE_TYPE r;
11099 #undef buf_size
11103 else
11107 }
11108 }
11120 else
11124 }
11128 machine_mode mode)
11129 {
11130 machine_mode vmode;
11136 }
11138 /* Split operands into moves from op[1] + op[2] into op[0]. */
11140 void
11142 {
11153 {
11154 /* No-op move. Can't split to nothing; emit something. */
11157 }
11159 /* Preserve register attributes for variable tracking. */
11164 /* Special case of reversed high/low parts. */
11167 {
11171 }
11173 {
11174 /* Try to avoid unnecessary moves if part of the result
11175 is in the right place already. */
11180 }
11181 else
11182 {
11187 }
11188 }
11190 /* vec_perm support. */
11192 #define MAX_VECT_LEN 16
11194 struct expand_vec_perm_d
11195 {
11198 machine_mode vmode;
11202 };
11204 /* Generate a variable permutation. */
11206 static void
11208 {
11219 {
11221 {
11222 /* Expand the argument to a V16QI mode by duplicating it. */
11226 }
11227 else
11228 {
11230 }
11231 }
11232 else
11233 {
11234 rtx pair;
11237 {
11241 }
11242 else
11243 {
11247 }
11248 }
11249 }
11251 void
11253 {
11257 rtx mask;
11259 /* The TBL instruction does not use a modulo index, so we must take care
11260 of that ourselves. */
11265 /* For big-endian, we also need to reverse the index within the vector
11266 (but not which vector). */
11268 {
11269 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
11274 }
11276 }
11278 /* Recognize patterns suitable for the TRN instructions. */
11279 static bool
11281 {
11290 /* Note that these are little-endian tests.
11291 We correct for big-endian later. */
11296 else
11301 {
11306 }
11308 /* Success! */
11315 {
11318 }
11322 {
11324 {
11337 }
11338 }
11339 else
11340 {
11342 {
11355 }
11356 }
11360 }
11362 /* Recognize patterns suitable for the UZP instructions. */
11363 static bool
11365 {
11374 /* Note that these are little-endian tests.
11375 We correct for big-endian later. */
11380 else
11385 {
11389 }
11391 /* Success! */
11398 {
11401 }
11405 {
11407 {
11420 }
11421 }
11422 else
11423 {
11425 {
11438 }
11439 }
11443 }
11445 /* Recognize patterns suitable for the ZIP instructions. */
11446 static bool
11448 {
11457 /* Note that these are little-endian tests.
11458 We correct for big-endian later. */
11461 /* Do Nothing. */
11462 ;
11465 else
11470 {
11477 }
11479 /* Success! */
11486 {
11489 }
11493 {
11495 {
11508 }
11509 }
11510 else
11511 {
11513 {
11526 }
11527 }
11531 }
11533 /* Recognize patterns for the EXT insn. */
11535 static bool
11537 {
11540 rtx offset;
11544 /* Check if the extracted indices are increasing by one. */
11546 {
11549 {
11550 /* We'll pass the same vector in twice, so allow indices to wrap. */
11552 }
11555 }
11558 {
11571 }
11573 /* Success! */
11577 /* The case where (location == 0) is a no-op for both big- and little-endian,
11578 and is removed by the mid-end at optimization levels -O1 and higher. */
11581 {
11582 /* After setup, we want the high elements of the first vector (stored
11583 at the LSB end of the register), and the low elements of the second
11584 vector (stored at the MSB end of the register). So swap. */
11586 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
11588 }
11593 }
11595 /* Recognize patterns for the REV insns. */
11597 static bool
11599 {
11608 {
11611 {
11616 }
11620 {
11627 }
11631 {
11642 }
11646 }
11650 {
11651 /* This is guaranteed to be true as the value of diff
11652 is 7, 3, 1 and we should have enough elements in the
11653 queue to generate this. Getting a vector mask with a
11654 value of diff other than these values implies that
11655 something is wrong by the time we get here. */
11659 }
11661 /* Success! */
11667 }
11669 static bool
11671 {
11674 rtx in0;
11677 rtx lane;
11681 {
11684 }
11686 /* The generic preparation in aarch64_expand_vec_perm_const_1
11687 swaps the operand order and the permute indices if it finds
11688 d->perm[0] to be in the second operand. Thus, we can always
11689 use d->op0 and need not do any extra arithmetic to get the
11690 correct lane number. */
11695 {
11708 }
11712 }
11714 static bool
11716 {
11724 /* Generic code will try constant permutation twice. Once with the
11725 original mode and again with the elements lowered to QImode.
11726 So wait and don't do the selector expansion ourselves. */
11731 {
11734 /* If big-endian and two vectors we end up with a weird mixed-endian
11735 mode on NEON. Reverse the index within each word but not the word
11736 itself. */
11739 }
11745 }
11747 static bool
11749 {
11750 /* The pattern matching functions above are written to look for a small
11751 number to begin the sequence (0, 1, N/2). If we begin with an index
11752 from the second operand, we can swap the operands. */
11754 {
11762 }
11765 {
11779 }
11781 }
11783 /* Expand a vec_perm_const pattern. */
11785 bool
11787 {
11801 {
11806 }
11809 {
11818 /* The elements of PERM do not suggest that only the first operand
11819 is used, but both operands are identical. Allow easier matching
11820 of the permutation by folding the permutation into the single
11821 input vector. */
11822 /* Fall Through. */
11834 }
11837 }
11839 static bool
11842 {
11852 /* Calculate whether all elements are in one vector. */
11854 {
11858 }
11860 /* If all elements are from the second vector, reindex as if from the
11861 first vector. */
11866 /* Check whether the mask can be applied to a single vector. */
11879 }
11881 rtx
11883 {
11884 /* We have to reverse each vector because we dont have
11885 a permuted load that can reverse-load according to ABI rules. */
11886 rtx mask;
11900 }
11902 /* Implement MODES_TIEABLE_P. */
11904 bool
11906 {
11910 /* We specifically want to allow elements of "structure" modes to
11911 be tieable to the structure. This more general condition allows
11912 other rarer situations too. */
11919 }
11921 /* Return a new RTX holding the result of moving POINTER forward by
11922 AMOUNT bytes. */
11924 static rtx
11926 {
11931 }
11933 /* Return a new RTX holding the result of moving POINTER forward by the
11934 size of the mode it points to. */
11936 static rtx
11938 {
11942 }
11944 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
11945 MODE bytes. */
11947 static void
11949 machine_mode mode)
11950 {
11953 /* "Cast" the pointers to the correct mode. */
11956 /* Emit the memcpy. */
11959 /* Move the pointers forward. */
11962 }
11964 /* Expand movmem, as if from a __builtin_memcpy. Return true if
11965 we succeed, otherwise return false. */
11967 bool
11969 {
11973 rtx base;
11976 /* When optimizing for size, give a better estimate of the length of a
11977 memcpy call, but use the default otherwise. */
11980 /* We can't do anything smart if the amount to copy is not constant. */
11986 /* Try to keep the number of instructions low. For cases below 16 bytes we
11987 need to make at most two moves. For cases above 16 bytes it will be one
11988 move for each 16 byte chunk, then at most two additional moves. */
11998 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
11999 1-byte chunk. */
12001 {
12003 {
12006 }
12012 }
12014 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
12015 4-byte chunk, partially overlapping with the previously copied chunk. */
12017 {
12021 {
12027 }
12029 }
12031 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
12032 them, then (if applicable) an 8-byte chunk. */
12034 {
12036 {
12039 }
12040 else
12041 {
12044 }
12045 }
12047 /* Finish the final bytes of the copy. We can always do this in one
12048 instruction. We either copy the exact amount we need, or partially
12049 overlap with the previous chunk we copied and copy 8-bytes. */
12058 else
12059 {
12061 {
12065 }
12066 else
12067 {
12073 }
12074 }
12077 }
12079 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
12081 static unsigned HOST_WIDE_INT
12083 {
12085 }
12087 static bool
12092 {
12093 /* STORE_BY_PIECES can be used when copying a constant string, but
12094 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
12095 For now we always fail this and let the move_by_pieces code copy
12096 the string from read-only memory. */
12101 }
12103 static enum machine_mode
12105 {
12107 {
12140 }
12141 }
12143 static rtx
12146 {
12165 {
12181 }
12186 {
12189 }
12203 {
12206 }
12211 }
12213 static rtx
12216 {
12235 {
12253 }
12258 {
12261 }
12278 {
12281 }
12287 }
12289 #undef TARGET_GEN_CCMP_FIRST
12290 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
12292 #undef TARGET_GEN_CCMP_NEXT
12293 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
12295 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
12296 instruction fusion of some sort. */
12298 static bool
12300 {
12302 }
12305 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
12306 should be kept together during scheduling. */
12308 static bool
12310 {
12311 rtx set_dest;
12314 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
12322 {
12323 /* We are trying to match:
12324 prev (mov) == (set (reg r0) (const_int imm16))
12325 curr (movk) == (set (zero_extract (reg r0)
12326 (const_int 16)
12327 (const_int 16))
12328 (const_int imm16_1)) */
12340 {
12342 }
12343 }
12347 {
12349 /* We're trying to match:
12350 prev (adrp) == (set (reg r1)
12351 (high (symbol_ref ("SYM"))))
12352 curr (add) == (set (reg r0)
12353 (lo_sum (reg r1)
12354 (symbol_ref ("SYM"))))
12355 Note that r0 need not necessarily be the same as r1, especially
12356 during pre-regalloc scheduling. */
12360 {
12368 }
12369 }
12373 {
12375 /* We're trying to match:
12376 prev (movk) == (set (zero_extract (reg r0)
12377 (const_int 16)
12378 (const_int 32))
12379 (const_int imm16_1))
12380 curr (movk) == (set (zero_extract (reg r0)
12381 (const_int 16)
12382 (const_int 48))
12383 (const_int imm16_2)) */
12399 }
12402 {
12403 /* We're trying to match:
12404 prev (adrp) == (set (reg r0)
12405 (high (symbol_ref ("SYM"))))
12406 curr (ldr) == (set (reg r1)
12407 (mem (lo_sum (reg r0)
12408 (symbol_ref ("SYM")))))
12409 or
12410 curr (ldr) == (set (reg r1)
12411 (zero_extend (mem
12412 (lo_sum (reg r0)
12413 (symbol_ref ("SYM")))))) */
12416 {
12429 }
12430 }
12434 {
12437 /* FIXME: this misses some which is considered simple arthematic
12438 instructions for ThunderX. Simple shifts are missed here. */
12444 }
12447 }
12449 /* If MEM is in the form of [base+offset], extract the two parts
12450 of address and set to BASE and OFFSET, otherwise return false
12451 after clearing BASE and OFFSET. */
12453 bool
12455 {
12456 rtx addr;
12463 {
12467 }
12471 {
12475 }
12481 }
12483 /* Types for scheduling fusion. */
12484 enum sched_fusion_type
12485 {
12487 SCHED_FUSION_LD_SIGN_EXTEND,
12488 SCHED_FUSION_LD_ZERO_EXTEND,
12489 SCHED_FUSION_LD,
12490 SCHED_FUSION_ST,
12491 SCHED_FUSION_NUM
12492 };
12494 /* If INSN is a load or store of address in the form of [base+offset],
12495 extract the two parts and set to BASE and OFFSET. Return scheduling
12496 fusion type this INSN is. */
12498 static enum sched_fusion_type
12500 {
12517 {
12522 }
12524 {
12529 }
12534 {
12537 }
12538 else
12545 }
12547 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
12549 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
12550 and PRI are only calculated for these instructions. For other instruction,
12551 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
12552 type instruction fusion can be added by returning different priorities.
12554 It's important that irrelevant instructions get the largest FUSION_PRI. */
12556 static void
12559 {
12569 {
12573 }
12575 /* Set FUSION_PRI according to fusion type and base register. */
12578 /* Calculate PRI. */
12581 /* INSN with smaller offset goes first. */
12585 else
12590 }
12592 /* Given OPERANDS of consecutive load/store, check if we can merge
12593 them into ldp/stp. LOAD is true if they are load instructions.
12594 MODE is the mode of memory operands. */
12596 bool
12599 {
12605 {
12613 }
12614 else
12615 {
12620 }
12622 /* The mems cannot be volatile. */
12626 /* Check if the addresses are in the form of [base+offset]. */
12634 /* Check if the bases are same. */
12641 /* Check if the offsets are consecutive. */
12645 /* Check if the addresses are clobbered by load. */
12647 {
12651 /* In increasing order, the last load can clobber the address. */
12654 }
12658 else
12663 else
12666 /* Check if the registers are of same class. */
12671 }
12673 /* Given OPERANDS of consecutive load/store, check if we can merge
12674 them into ldp/stp by adjusting the offset. LOAD is true if they
12675 are load instructions. MODE is the mode of memory operands.
12677 Given below consecutive stores:
12679 str w1, [xb, 0x100]
12680 str w1, [xb, 0x104]
12681 str w1, [xb, 0x108]
12682 str w1, [xb, 0x10c]
12684 Though the offsets are out of the range supported by stp, we can
12685 still pair them after adjusting the offset, like:
12687 add scratch, xb, 0x100
12688 stp w1, w1, [scratch]
12689 stp w1, w1, [scratch, 0x8]
12691 The peephole patterns detecting this opportunity should guarantee
12692 the scratch register is avaliable. */
12694 bool
12697 {
12704 {
12717 }
12718 else
12719 {
12728 }
12729 /* Skip if memory operand is by itslef valid for ldp/stp. */
12733 /* The mems cannot be volatile. */
12738 /* Check if the addresses are in the form of [base+offset]. */
12752 /* Check if the bases are same. */
12763 /* Check if the offsets are consecutive. */
12772 /* Check if the addresses are clobbered by load. */
12774 {
12780 /* In increasing order, the last load can clobber the address. */
12783 }
12787 else
12792 else
12797 else
12802 else
12805 /* Check if the registers are of same class. */
12810 }
12812 /* Given OPERANDS of consecutive load/store, this function pairs them
12813 into ldp/stp after adjusting the offset. It depends on the fact
12814 that addresses of load/store instructions are in increasing order.
12815 MODE is the mode of memory operands. CODE is the rtl operator
12816 which should be applied to all memory operands, it's SIGN_EXTEND,
12817 ZERO_EXTEND or UNKNOWN. */
12819 bool
12822 {
12828 {
12833 }
12834 else
12835 {
12841 }
12846 /* Adjust offset thus it can fit in ldp/stp instruction. */
12854 /* Further adjust to make sure all offsets are OK. */
12856 {
12859 }
12861 /* Make sure the adjustment can be done with ADD/SUB instructions. */
12866 {
12869 }
12871 /* Create new memory references. */
12875 /* Check if the adjusted address is OK for ldp/stp. */
12894 {
12899 }
12901 {
12906 }
12909 {
12914 }
12915 else
12916 {
12921 }
12923 /* Emit adjusting instruction. */
12925 /* Emit ldp/stp instructions. */
12933 }
12935 /* Return 1 if pseudo register should be created and used to hold
12936 GOT address for PIC code. */
12938 bool
12940 {
12942 }
12944 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
12946 static int
12948 {
12950 {
12957 }
12960 }
12962 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
12963 static tree
12965 {
12969 }
12970 #undef TARGET_ADDRESS_COST
12971 #define TARGET_ADDRESS_COST aarch64_address_cost
12973 /* This hook will determines whether unnamed bitfields affect the alignment
12974 of the containing structure. The hook returns true if the structure
12975 should inherit the alignment requirements of an unnamed bitfield's
12976 type. */
12977 #undef TARGET_ALIGN_ANON_BITFIELD
12978 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
12980 #undef TARGET_ASM_ALIGNED_DI_OP
12983 #undef TARGET_ASM_ALIGNED_HI_OP
12986 #undef TARGET_ASM_ALIGNED_SI_OP
12989 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12990 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
12991 hook_bool_const_tree_hwi_hwi_const_tree_true
12993 #undef TARGET_ASM_OUTPUT_MI_THUNK
12994 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
12996 #undef TARGET_ASM_SELECT_RTX_SECTION
12997 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
12999 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
13000 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
13002 #undef TARGET_BUILD_BUILTIN_VA_LIST
13003 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
13005 #undef TARGET_CALLEE_COPIES
13006 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
13008 #undef TARGET_CAN_ELIMINATE
13009 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
13011 #undef TARGET_CAN_INLINE_P
13012 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
13014 #undef TARGET_CANNOT_FORCE_CONST_MEM
13015 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
13017 #undef TARGET_CONDITIONAL_REGISTER_USAGE
13018 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
13020 /* Only the least significant bit is used for initialization guard
13021 variables. */
13022 #undef TARGET_CXX_GUARD_MASK_BIT
13023 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
13025 #undef TARGET_C_MODE_FOR_SUFFIX
13026 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
13028 #ifdef TARGET_BIG_ENDIAN_DEFAULT
13029 #undef TARGET_DEFAULT_TARGET_FLAGS
13030 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
13031 #endif
13033 #undef TARGET_CLASS_MAX_NREGS
13034 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
13036 #undef TARGET_BUILTIN_DECL
13037 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
13039 #undef TARGET_EXPAND_BUILTIN
13040 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
13042 #undef TARGET_EXPAND_BUILTIN_VA_START
13043 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
13045 #undef TARGET_FOLD_BUILTIN
13046 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
13048 #undef TARGET_FUNCTION_ARG
13049 #define TARGET_FUNCTION_ARG aarch64_function_arg
13051 #undef TARGET_FUNCTION_ARG_ADVANCE
13052 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
13054 #undef TARGET_FUNCTION_ARG_BOUNDARY
13055 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
13057 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13058 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
13060 #undef TARGET_FUNCTION_VALUE
13061 #define TARGET_FUNCTION_VALUE aarch64_function_value
13063 #undef TARGET_FUNCTION_VALUE_REGNO_P
13064 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
13066 #undef TARGET_FRAME_POINTER_REQUIRED
13067 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
13069 #undef TARGET_GIMPLE_FOLD_BUILTIN
13070 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
13072 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
13073 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
13075 #undef TARGET_INIT_BUILTINS
13076 #define TARGET_INIT_BUILTINS aarch64_init_builtins
13078 #undef TARGET_LEGITIMATE_ADDRESS_P
13079 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
13081 #undef TARGET_LEGITIMATE_CONSTANT_P
13082 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
13084 #undef TARGET_LIBGCC_CMP_RETURN_MODE
13085 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
13087 #undef TARGET_LRA_P
13088 #define TARGET_LRA_P hook_bool_void_true
13090 #undef TARGET_MANGLE_TYPE
13091 #define TARGET_MANGLE_TYPE aarch64_mangle_type
13093 #undef TARGET_MEMORY_MOVE_COST
13094 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
13096 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
13097 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
13099 #undef TARGET_MUST_PASS_IN_STACK
13100 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
13102 /* This target hook should return true if accesses to volatile bitfields
13103 should use the narrowest mode possible. It should return false if these
13104 accesses should use the bitfield container type. */
13105 #undef TARGET_NARROW_VOLATILE_BITFIELD
13106 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
13108 #undef TARGET_OPTION_OVERRIDE
13109 #define TARGET_OPTION_OVERRIDE aarch64_override_options
13111 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
13112 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
13113 aarch64_override_options_after_change
13115 #undef TARGET_OPTION_SAVE
13116 #define TARGET_OPTION_SAVE aarch64_option_save
13118 #undef TARGET_OPTION_RESTORE
13119 #define TARGET_OPTION_RESTORE aarch64_option_restore
13121 #undef TARGET_OPTION_PRINT
13122 #define TARGET_OPTION_PRINT aarch64_option_print
13124 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
13125 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
13127 #undef TARGET_SET_CURRENT_FUNCTION
13128 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
13130 #undef TARGET_PASS_BY_REFERENCE
13131 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
13133 #undef TARGET_PREFERRED_RELOAD_CLASS
13134 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
13136 #undef TARGET_SCHED_REASSOCIATION_WIDTH
13137 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
13139 #undef TARGET_PROMOTED_TYPE
13140 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
13142 #undef TARGET_SECONDARY_RELOAD
13143 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
13145 #undef TARGET_SHIFT_TRUNCATION_MASK
13146 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
13148 #undef TARGET_SETUP_INCOMING_VARARGS
13149 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
13151 #undef TARGET_STRUCT_VALUE_RTX
13152 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
13154 #undef TARGET_REGISTER_MOVE_COST
13155 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
13157 #undef TARGET_RETURN_IN_MEMORY
13158 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
13160 #undef TARGET_RETURN_IN_MSB
13161 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
13163 #undef TARGET_RTX_COSTS
13164 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
13166 #undef TARGET_SCHED_ISSUE_RATE
13167 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
13169 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
13170 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
13171 aarch64_sched_first_cycle_multipass_dfa_lookahead
13173 #undef TARGET_TRAMPOLINE_INIT
13174 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
13176 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
13177 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
13179 #undef TARGET_VECTOR_MODE_SUPPORTED_P
13180 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
13182 #undef TARGET_ARRAY_MODE_SUPPORTED_P
13183 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
13185 #undef TARGET_VECTORIZE_ADD_STMT_COST
13186 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
13188 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
13189 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
13190 aarch64_builtin_vectorization_cost
13192 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
13193 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
13195 #undef TARGET_VECTORIZE_BUILTINS
13196 #define TARGET_VECTORIZE_BUILTINS
13198 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
13199 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
13200 aarch64_builtin_vectorized_function
13202 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
13203 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
13204 aarch64_autovectorize_vector_sizes
13206 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
13207 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
13208 aarch64_atomic_assign_expand_fenv
13210 /* Section anchor support. */
13212 #undef TARGET_MIN_ANCHOR_OFFSET
13213 #define TARGET_MIN_ANCHOR_OFFSET -256
13215 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
13216 byte offset; we can do much more for larger data types, but have no way
13217 to determine the size of the access. We assume accesses are aligned. */
13218 #undef TARGET_MAX_ANCHOR_OFFSET
13219 #define TARGET_MAX_ANCHOR_OFFSET 4095
13221 #undef TARGET_VECTOR_ALIGNMENT
13222 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
13224 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
13225 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
13226 aarch64_simd_vector_alignment_reachable
13228 /* vec_perm support. */
13230 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
13231 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
13232 aarch64_vectorize_vec_perm_const_ok
13234 #undef TARGET_INIT_LIBFUNCS
13235 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
13237 #undef TARGET_FIXED_CONDITION_CODE_REGS
13238 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
13240 #undef TARGET_FLAGS_REGNUM
13241 #define TARGET_FLAGS_REGNUM CC_REGNUM
13243 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
13244 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
13246 #undef TARGET_ASAN_SHADOW_OFFSET
13247 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
13249 #undef TARGET_LEGITIMIZE_ADDRESS
13250 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
13252 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
13253 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
13254 aarch64_use_by_pieces_infrastructure_p
13256 #undef TARGET_CAN_USE_DOLOOP_P
13257 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
13259 #undef TARGET_SCHED_MACRO_FUSION_P
13260 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
13262 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
13263 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
13265 #undef TARGET_SCHED_FUSION_PRIORITY
13266 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
13268 #undef TARGET_UNSPEC_MAY_TRAP_P
13269 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
13271 #undef TARGET_USE_PSEUDO_PIC_REG
13272 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg