| blob | 65fea7e13e0dc5331f410d1c83d5e3401661d25d |
1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; any later version.
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 ;; Boston, MA 02110-1301, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; adds/subs.
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
48 ;; CONSTANTS
49 ;; ----------------------------------------------------------------------
51 (define_constants
52 [(UNSPEC_INCDEC 0)
53 (UNSPEC_MONITOR 1)])
55 (define_constants
56 [(UNSPEC_MOVMD 100)
57 (UNSPEC_STPCPY 101)])
59 (define_constants
60 [(R0_REG 0)
61 (SC_REG 3)
62 (COUNTER_REG 4)
63 (SOURCE_REG 5)
64 (DESTINATION_REG 6)
65 (HFP_REG 6)
66 (SP_REG 7)
67 (MAC_REG 8)
68 (AP_REG 9)
69 (RAP_REG 10)
70 (FP_REG 11)])
72 ;; ----------------------------------------------------------------------
73 ;; ATTRIBUTES
74 ;; ----------------------------------------------------------------------
76 (define_attr "cpu" "h8300,h8300h"
77 (const (symbol_ref "cpu_type")))
79 (define_attr "type" "branch,arith,bitbranch,call"
80 (const_string "arith"))
82 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
83 (const_string "none"))
85 ;; The size of instructions in bytes.
87 (define_attr "length" ""
88 (cond [(eq_attr "type" "branch")
89 ;; In a forward delayed branch, (pc) represents the end of the
90 ;; delay sequence, not the end of the branch itself.
91 (if_then_else (and (ge (minus (match_dup 0) (pc))
92 (const_int -126))
93 (le (plus (minus (match_dup 0) (pc))
94 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
95 (const_int 126)))
96 (const_int 2)
97 (if_then_else (and (eq_attr "cpu" "h8300h")
98 (and (ge (minus (pc) (match_dup 0))
99 (const_int -32000))
100 (le (minus (pc) (match_dup 0))
101 (const_int 32000))))
102 (const_int 4)
103 (const_int 6)))
104 (eq_attr "type" "bitbranch")
105 (if_then_else
106 (and (ge (minus (match_dup 0) (pc))
107 (const_int -126))
108 (le (minus (match_dup 0) (pc))
109 (const_int 126)))
110 (plus
111 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
112 (const_int 2))
113 (if_then_else
114 (and (eq_attr "cpu" "h8300h")
115 (and (ge (minus (pc) (match_dup 0))
116 (const_int -32000))
117 (le (minus (pc) (match_dup 0))
118 (const_int 32000))))
119 (plus
120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
121 (const_int 4))
122 (plus
123 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
124 (const_int 6))))
125 (eq_attr "length_table" "!none")
126 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
127 (const_int 200)))
129 ;; Condition code settings.
130 ;;
131 ;; none - insn does not affect cc
132 ;; none_0hit - insn does not affect cc but it does modify operand 0
133 ;; This attribute is used to keep track of when operand 0 changes.
134 ;; See the description of NOTICE_UPDATE_CC for more info.
135 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
136 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
137 ;; compare - compare instruction
138 ;; clobber - value of cc is unknown
140 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
141 (const_string "clobber"))
143 ;; Type of delay slot. NONE means the instruction has no delay slot.
144 ;; JUMP means it is an unconditional jump that (if short enough)
145 ;; could be implemented using bra/s.
146 (define_attr "delay_slot" "none,jump"
147 (const_string "none"))
149 ;; "yes" if the instruction can be put into a delay slot. It's not
150 ;; entirely clear that jsr is not valid in delay slots, but it
151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call")
155 (const_string "no")
156 (ne (symbol_ref "get_attr_length (insn)") (const_int 2))
157 (const_string "no")]
158 (const_string "yes")))
160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimization: we don't know
162 ;; for certain whether they will be or not.
163 (define_delay (and (eq_attr "delay_slot" "jump")
164 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
165 [(eq_attr "can_delay" "yes")
166 (nil)
167 (nil)])
169 ;; Provide the maximum length of an assembly instruction in an asm
170 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
172 (define_asm_attributes
173 [(set (attr "length")
174 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
175 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
176 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
177 (const_int 14)))])
179 (include "predicates.md")
180 \f
181 ;; ----------------------------------------------------------------------
182 ;; MOVE INSTRUCTIONS
183 ;; ----------------------------------------------------------------------
185 ;; movqi
187 (define_insn "*movqi_h8300"
188 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
189 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
190 "TARGET_H8300
191 && (register_operand (operands[0], QImode)
192 || register_operand (operands[1], QImode))"
193 "@
194 sub.b %X0,%X0
195 mov.b %R1,%X0
196 mov.b %X1,%R0
197 mov.b %R1,%X0
198 mov.b %R1,%X0
199 mov.b %X1,%R0"
200 [(set_attr "length" "2,2,2,2,4,4")
201 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
203 (define_insn "*movqi_h8300hs"
204 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
205 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
206 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
207 && (register_operand (operands[0], QImode)
208 || register_operand (operands[1], QImode))"
209 "@
210 sub.b %X0,%X0
211 mov.b %R1,%X0
212 mov.b %X1,%R0
213 mov.b %R1,%X0
214 mov.b %R1,%X0
215 mov.b %X1,%R0"
216 [(set (attr "length")
217 (symbol_ref "compute_mov_length (operands)"))
218 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
220 (define_insn "*movqi_h8sx"
221 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
222 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
223 "TARGET_H8300SX"
224 "@
225 mov.b %X1,%X0
226 mov.b %X1,%X0"
227 [(set_attr "length_table" "mov_imm4,movb")
228 (set_attr "cc" "set_znv")])
230 (define_expand "movqi"
231 [(set (match_operand:QI 0 "general_operand_dst" "")
232 (match_operand:QI 1 "general_operand_src" ""))]
233 ""
234 "
235 {
236 /* One of the ops has to be in a register. */
237 if (!TARGET_H8300SX
238 && !register_operand (operand0, QImode)
239 && !register_operand (operand1, QImode))
240 {
241 operands[1] = copy_to_mode_reg (QImode, operand1);
242 }
243 }")
245 (define_insn "movstrictqi"
246 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
247 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
248 ""
249 "@
250 sub.b %X0,%X0
251 mov.b %X1,%X0"
252 [(set_attr "length" "2,*")
253 (set_attr "length_table" "*,movb")
254 (set_attr "cc" "set_zn,set_znv")])
256 ;; movhi
258 (define_insn "*movhi_h8300"
259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
261 "TARGET_H8300
262 && (register_operand (operands[0], HImode)
263 || register_operand (operands[1], HImode))
264 && !(GET_CODE (operands[0]) == MEM
265 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
266 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
267 && GET_CODE (operands[1]) == REG
268 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
269 "@
270 sub.w %T0,%T0
271 mov.w %T1,%T0
272 mov.w %T1,%T0
273 mov.w %T1,%T0
274 mov.w %T1,%T0
275 mov.w %T1,%T0"
276 [(set (attr "length")
277 (symbol_ref "compute_mov_length (operands)"))
278 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
280 (define_insn "*movhi_h8300hs"
281 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
282 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
283 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
284 && (register_operand (operands[0], HImode)
285 || register_operand (operands[1], HImode))"
286 "@
287 sub.w %T0,%T0
288 mov.w %T1,%T0
289 mov.w %T1,%T0
290 mov.w %T1,%T0
291 mov.w %T1,%T0
292 mov.w %T1,%T0"
293 [(set (attr "length")
294 (symbol_ref "compute_mov_length (operands)"))
295 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
297 (define_insn "*movhi_h8sx"
298 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
299 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
300 "TARGET_H8300SX"
301 "@
302 sub.w %T0,%T0
303 mov.w %T1,%T0
304 mov.w %T1,%T0
305 mov.w %T1,%T0
306 mov.w %T1,%T0"
307 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
308 (set_attr "length" "2,2,*,*,*")
309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
311 (define_expand "movhi"
312 [(set (match_operand:HI 0 "general_operand_dst" "")
313 (match_operand:HI 1 "general_operand_src" ""))]
314 ""
315 "
316 {
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, HImode)
319 && !register_operand (operand0, HImode))
320 {
321 operands[1] = copy_to_mode_reg (HImode, operand1);
322 }
323 }")
325 (define_insn "movstricthi"
326 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
327 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
328 ""
329 "@
330 sub.w %T0,%T0
331 mov.w %T1,%T0
332 mov.w %T1,%T0"
333 [(set_attr "length" "2,2,*")
334 (set_attr "length_table" "*,*,movw")
335 (set_attr "cc" "set_zn,set_znv,set_znv")])
337 ;; movsi
339 (define_expand "movsi"
340 [(set (match_operand:SI 0 "general_operand_dst" "")
341 (match_operand:SI 1 "general_operand_src" ""))]
342 ""
343 "
344 {
345 if (TARGET_H8300)
346 {
347 if (h8300_expand_movsi (operands))
348 DONE;
349 }
350 else if (!TARGET_H8300SX)
351 {
352 /* One of the ops has to be in a register. */
353 if (!register_operand (operand1, SImode)
354 && !register_operand (operand0, SImode))
355 {
356 operands[1] = copy_to_mode_reg (SImode, operand1);
357 }
358 }
359 }")
361 (define_insn "*movsi_h8300"
362 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
363 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
364 "TARGET_H8300
365 && (register_operand (operands[0], SImode)
366 || register_operand (operands[1], SImode))"
367 "*
368 {
369 unsigned int rn = -1;
370 switch (which_alternative)
371 {
372 case 0:
373 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
374 case 1:
375 if (REGNO (operands[0]) < REGNO (operands[1]))
376 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
377 else
378 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
379 case 2:
380 /* Make sure we don't trample the register we index with. */
381 if (GET_CODE (operands[1]) == MEM)
382 {
383 rtx inside = XEXP (operands[1], 0);
384 if (REG_P (inside))
385 {
386 rn = REGNO (inside);
387 }
388 else if (GET_CODE (inside) == PLUS)
389 {
390 rtx lhs = XEXP (inside, 0);
391 rtx rhs = XEXP (inside, 1);
392 if (REG_P (lhs)) rn = REGNO (lhs);
393 if (REG_P (rhs)) rn = REGNO (rhs);
394 }
395 }
396 if (rn == REGNO (operands[0]))
397 {
398 /* Move the second word first. */
399 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
400 }
401 else
402 {
403 if (GET_CODE (operands[1]) == CONST_INT)
404 {
405 /* If either half is zero, use sub.w to clear that
406 half. */
407 if ((INTVAL (operands[1]) & 0xffff) == 0)
408 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
409 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
410 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
411 /* If the upper half and the lower half are the same,
412 copy one half to the other. */
413 if ((INTVAL (operands[1]) & 0xffff)
414 == ((INTVAL (operands[1]) >> 16) & 0xffff))
415 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
416 }
417 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
418 }
419 case 3:
420 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
421 case 4:
422 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
423 case 5:
424 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
425 default:
426 gcc_unreachable ();
427 }
428 }"
429 [(set (attr "length")
430 (symbol_ref "compute_mov_length (operands)"))])
432 (define_insn "*movsi_h8300hs"
433 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
434 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
435 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
436 && (register_operand (operands[0], SImode)
437 || register_operand (operands[1], SImode))
438 && !(GET_CODE (operands[0]) == MEM
439 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
440 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
441 && GET_CODE (operands[1]) == REG
442 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
443 "*
444 {
445 switch (which_alternative)
446 {
447 case 0:
448 return \"sub.l %S0,%S0\";
449 case 7:
450 return \"clrmac\";
451 case 8:
452 return \"clrmac\;ldmac %1,macl\";
453 case 9:
454 return \"stmac macl,%0\";
455 default:
456 if (GET_CODE (operands[1]) == CONST_INT)
457 {
458 int val = INTVAL (operands[1]);
460 /* Look for constants which can be made by adding an 8-bit
461 number to zero in one of the two low bytes. */
462 if (val == (val & 0xff))
463 {
464 operands[1] = GEN_INT ((char) val & 0xff);
465 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
466 }
468 if (val == (val & 0xff00))
469 {
470 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
471 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
472 }
474 /* Look for constants that can be obtained by subs, inc, and
475 dec to 0. */
476 switch (val & 0xffffffff)
477 {
478 case 0xffffffff:
479 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
480 case 0xfffffffe:
481 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
482 case 0xfffffffc:
483 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
485 case 0x0000ffff:
486 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
487 case 0x0000fffe:
488 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
490 case 0xffff0000:
491 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
492 case 0xfffe0000:
493 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
495 case 0x00010000:
496 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
497 case 0x00020000:
498 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
499 }
500 }
501 }
502 return \"mov.l %S1,%S0\";
503 }"
504 [(set (attr "length")
505 (symbol_ref "compute_mov_length (operands)"))
506 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
508 (define_insn "*movsi_h8sx"
509 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
510 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
511 "TARGET_H8300SX"
512 "@
513 sub.l %S0,%S0
514 mov.l %S1,%S0
515 mov.l %S1,%S0
516 mov.l %S1,%S0
517 clrmac
518 clrmac\;ldmac %1,macl
519 stmac macl,%0"
520 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
521 (set_attr "length" "2,2,*,*,2,6,4")
522 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
524 (define_insn "*movsf_h8sx"
525 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
526 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
527 "TARGET_H8300SX"
528 "@
529 sub.l %S0,%S0
530 mov.l %S1,%S0"
531 [(set_attr "length" "2,*")
532 (set_attr "length_table" "*,movl")
533 (set_attr "cc" "set_zn,set_znv")])
535 ;; Implement block moves using movmd. Defining movmemsi allows the full
536 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
537 ;; See h8sx_emit_movmd for details.
538 (define_expand "movmemsi"
539 [(use (match_operand:BLK 0 "memory_operand" ""))
540 (use (match_operand:BLK 1 "memory_operand" ""))
541 (use (match_operand:SI 2 "" ""))
542 (use (match_operand:SI 3 "const_int_operand" ""))]
543 "TARGET_H8300SX"
544 {
545 if (h8sx_emit_movmd (operands[0], operands[1], operands[2],
546 INTVAL (operands[3])))
547 DONE;
548 else
549 FAIL;
550 })
552 ;; Expander for generating movmd insns. Operand 0 is the destination
553 ;; memory region, operand 1 is the source, operand 2 is the counter
554 ;; register and operand 3 is the chunk size (1, 2 or 4).
555 (define_expand "movmd"
556 [(parallel
557 [(set (match_operand:BLK 0 "memory_operand" "")
558 (match_operand:BLK 1 "memory_operand" ""))
559 (unspec [(match_operand:HI 2 "register_operand" "")
560 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
561 (clobber (match_dup 4))
562 (clobber (match_dup 5))
563 (set (match_dup 2)
564 (const_int 0))])]
565 "TARGET_H8300SX"
566 {
567 operands[4] = copy_rtx (XEXP (operands[0], 0));
568 operands[5] = copy_rtx (XEXP (operands[1], 0));
569 })
572 ;; This is a difficult instruction to reload since operand 0 must be the
573 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
574 (define_insn "movmd_internal_normal"
575 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
576 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
577 (unspec [(match_operand:HI 5 "register_operand" "2,2")
578 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
579 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
580 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
581 (set (match_operand:HI 2 "register_operand" "=c,c")
582 (const_int 0))]
583 "TARGET_H8300SX && TARGET_NORMAL_MODE"
584 "@
585 movmd%m6
586 #"
587 [(set_attr "length" "2,14")
588 (set_attr "can_delay" "no")
589 (set_attr "cc" "none,clobber")])
591 (define_insn "movmd_internal"
592 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
593 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
594 (unspec [(match_operand:HI 5 "register_operand" "2,2")
595 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
596 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
597 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
598 (set (match_operand:HI 2 "register_operand" "=c,c")
599 (const_int 0))]
600 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
601 "@
602 movmd%m6
603 #"
604 [(set_attr "length" "2,14")
605 (set_attr "can_delay" "no")
606 (set_attr "cc" "none,clobber")])
608 ;; Split the above instruction if the destination register isn't er6.
609 ;; We need a sequence like:
610 ;;
611 ;; mov.l er6,@-er7
612 ;; mov.l <dest>,er6
613 ;; movmd.sz
614 ;; mov.l er6,<dest>
615 ;; mov.l @er7+,er6
616 ;;
617 ;; where <dest> is the current destination register (operand 4).
618 ;; The fourth instruction will be deleted if <dest> dies here.
619 (define_split
620 [(set (match_operand:BLK 0 "memory_operand" "")
621 (match_operand:BLK 1 "memory_operand" ""))
622 (unspec [(match_operand:HI 2 "register_operand" "")
623 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
624 (clobber (match_operand:HI 4 "register_operand" ""))
625 (clobber (match_operand:HI 5 "register_operand" ""))
626 (set (match_dup 2)
627 (const_int 0))]
628 "TARGET_H8300SX && TARGET_NORMAL_MODE
629 && reload_completed
630 && REGNO (operands[4]) != DESTINATION_REG"
631 [(const_int 0)]
632 {
633 rtx dest;
635 h8300_swap_into_er6 (XEXP (operands[0], 0));
636 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
637 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
638 h8300_swap_out_of_er6 (operands[4]);
639 DONE;
640 })
642 (define_split
643 [(set (match_operand:BLK 0 "memory_operand" "")
644 (match_operand:BLK 1 "memory_operand" ""))
645 (unspec [(match_operand:HI 2 "register_operand" "")
646 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
647 (clobber (match_operand:SI 4 "register_operand" ""))
648 (clobber (match_operand:SI 5 "register_operand" ""))
649 (set (match_dup 2)
650 (const_int 0))]
651 "TARGET_H8300SX && !TARGET_NORMAL_MODE
652 && reload_completed
653 && REGNO (operands[4]) != DESTINATION_REG"
654 [(const_int 0)]
655 {
656 rtx dest;
658 h8300_swap_into_er6 (XEXP (operands[0], 0));
659 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
660 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
661 h8300_swap_out_of_er6 (operands[4]);
662 DONE;
663 })
665 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
666 ;; the final character, but movsd leaves it pointing to the character
667 ;; after that.
668 (define_expand "movstr"
669 [(use (match_operand 0 "register_operand" ""))
670 (use (match_operand:BLK 1 "memory_operand" ""))
671 (use (match_operand:BLK 2 "memory_operand" ""))]
672 "TARGET_H8300SX"
673 {
674 operands[1] = replace_equiv_address
675 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
676 operands[2] = replace_equiv_address
677 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
678 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
679 emit_insn (gen_add3_insn (operands[0],
680 XEXP (operands[1], 0),
681 constm1_rtx));
682 DONE;
683 })
685 ;; Expander for generating a movsd instruction. Operand 0 is the
686 ;; destination string, operand 1 is the source string and operand 2
687 ;; is a scratch register.
688 (define_expand "movsd"
689 [(parallel
690 [(set (match_operand:BLK 0 "memory_operand" "")
691 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
692 UNSPEC_STPCPY))
693 (clobber (match_dup 3))
694 (clobber (match_dup 4))
695 (clobber (match_operand 2 "register_operand" ""))])]
696 "TARGET_H8300SX"
697 {
698 operands[3] = copy_rtx (XEXP (operands[0], 0));
699 operands[4] = copy_rtx (XEXP (operands[1], 0));
700 })
702 ;; See comments above memcpy_internal().
703 (define_insn "stpcpy_internal_normal"
704 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
705 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
706 UNSPEC_STPCPY))
707 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
708 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
709 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
710 "TARGET_H8300SX && TARGET_NORMAL_MODE"
711 "@
712 \n1:\tmovsd\t2f\;bra\t1b\n2:
713 #"
714 [(set_attr "length" "6,18")
715 (set_attr "cc" "none,clobber")])
717 (define_insn "stpcpy_internal"
718 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
719 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
720 UNSPEC_STPCPY))
721 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
722 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
723 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
724 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
725 "@
726 \n1:\tmovsd\t2f\;bra\t1b\n2:
727 #"
728 [(set_attr "length" "6,18")
729 (set_attr "cc" "none,clobber")])
731 ;; Split the above instruction if the destination isn't er6. This works
732 ;; in the same way as the movmd splitter.
733 (define_split
734 [(set (match_operand:BLK 0 "memory_operand" "")
735 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
736 (clobber (match_operand:HI 2 "register_operand" ""))
737 (clobber (match_operand:HI 3 "register_operand" ""))
738 (clobber (match_operand:HI 4 "register_operand" ""))]
739 "TARGET_H8300SX && TARGET_NORMAL_MODE
740 && reload_completed
741 && REGNO (operands[2]) != DESTINATION_REG"
742 [(const_int 0)]
743 {
744 rtx dest;
746 h8300_swap_into_er6 (XEXP (operands[0], 0));
747 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
748 emit_insn (gen_movsd (dest, operands[1], operands[4]));
749 h8300_swap_out_of_er6 (operands[2]);
750 DONE;
751 })
753 (define_split
754 [(set (match_operand:BLK 0 "memory_operand" "")
755 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
756 (clobber (match_operand:SI 2 "register_operand" ""))
757 (clobber (match_operand:SI 3 "register_operand" ""))
758 (clobber (match_operand:SI 4 "register_operand" ""))]
759 "TARGET_H8300SX && !TARGET_NORMAL_MODE
760 && reload_completed
761 && REGNO (operands[2]) != DESTINATION_REG"
762 [(const_int 0)]
763 {
764 rtx dest;
766 h8300_swap_into_er6 (XEXP (operands[0], 0));
767 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
768 emit_insn (gen_movsd (dest, operands[1], operands[4]));
769 h8300_swap_out_of_er6 (operands[2]);
770 DONE;
771 })
773 (include "mova.md")
775 (define_expand "movsf"
776 [(set (match_operand:SF 0 "general_operand_dst" "")
777 (match_operand:SF 1 "general_operand_src" ""))]
778 ""
779 "
780 {
781 if (TARGET_H8300)
782 {
783 if (h8300_expand_movsi (operands))
784 DONE;
785 }
786 else if (!TARGET_H8300SX)
787 {
788 /* One of the ops has to be in a register. */
789 if (!register_operand (operand1, SFmode)
790 && !register_operand (operand0, SFmode))
791 {
792 operands[1] = copy_to_mode_reg (SFmode, operand1);
793 }
794 }
795 }")
797 (define_insn "*movsf_h8300"
798 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
799 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
800 "TARGET_H8300
801 && (register_operand (operands[0], SFmode)
802 || register_operand (operands[1], SFmode))"
803 "*
804 {
805 /* Copy of the movsi stuff. */
806 unsigned int rn = -1;
807 switch (which_alternative)
808 {
809 case 0:
810 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
811 case 1:
812 if (REGNO (operands[0]) < REGNO (operands[1]))
813 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
814 else
815 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
816 case 2:
817 /* Make sure we don't trample the register we index with. */
818 if (GET_CODE (operands[1]) == MEM)
819 {
820 rtx inside = XEXP (operands[1], 0);
821 if (REG_P (inside))
822 {
823 rn = REGNO (inside);
824 }
825 else if (GET_CODE (inside) == PLUS)
826 {
827 rtx lhs = XEXP (inside, 0);
828 rtx rhs = XEXP (inside, 1);
829 if (REG_P (lhs)) rn = REGNO (lhs);
830 if (REG_P (rhs)) rn = REGNO (rhs);
831 }
832 }
833 if (rn == REGNO (operands[0]))
834 /* Move the second word first. */
835 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
836 else
837 /* Move the first word first. */
838 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
840 case 3:
841 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
842 case 4:
843 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
844 case 5:
845 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
846 default:
847 gcc_unreachable ();
848 }
849 }"
850 [(set (attr "length")
851 (symbol_ref "compute_mov_length (operands)"))])
853 (define_insn "*movsf_h8300hs"
854 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
855 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
856 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
857 && (register_operand (operands[0], SFmode)
858 || register_operand (operands[1], SFmode))"
859 "@
860 sub.l %S0,%S0
861 mov.l %S1,%S0
862 mov.l %S1,%S0
863 mov.l %S1,%S0
864 mov.l %S1,%S0
865 mov.l %S1,%S0"
866 [(set (attr "length")
867 (symbol_ref "compute_mov_length (operands)"))
868 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
869 \f
870 ;; ----------------------------------------------------------------------
871 ;; PUSH INSTRUCTIONS
872 ;; ----------------------------------------------------------------------
874 (define_insn "pushqi1_h8300"
875 [(set (reg:HI SP_REG)
876 (plus:HI (reg:HI SP_REG) (const_int -2)))
877 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
878 (match_operand:QI 0 "register_operand" "r"))]
879 "TARGET_H8300
880 && operands[0] != stack_pointer_rtx"
881 "mov.w\\t%T0,@-r7"
882 [(set_attr "length" "2")])
884 (define_insn "pushqi1_h8300hs_advanced"
885 [(set (reg:SI SP_REG)
886 (plus:SI (reg:SI SP_REG) (const_int -4)))
887 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
888 (match_operand:QI 0 "register_operand" "r"))]
889 "(TARGET_H8300H || TARGET_H8300S)
890 && operands[0] != stack_pointer_rtx"
891 "mov.l\\t%S0,@-er7"
892 [(set_attr "length" "4")])
894 (define_insn "pushqi1_h8300hs_normal"
895 [(set (reg:HI SP_REG)
896 (plus:HI (reg:HI SP_REG) (const_int -4)))
897 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
898 (match_operand:QI 0 "register_operand" "r"))]
899 "(TARGET_H8300H || TARGET_H8300S)
900 && operands[0] != stack_pointer_rtx"
901 "mov.l\\t%S0,@-er7"
902 [(set_attr "length" "4")])
904 (define_expand "pushqi1"
905 [(match_operand:QI 0 "register_operand" "")]
906 ""
907 "
908 {
909 if (TARGET_H8300)
910 emit_insn (gen_pushqi1_h8300 (operands[0]));
911 else if (!TARGET_NORMAL_MODE)
912 emit_insn (gen_pushqi1_h8300hs_advanced (operands[0]));
913 else
914 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
915 DONE;
916 }")
918 (define_expand "pushhi1_h8300"
919 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
920 (match_operand:HI 0 "register_operand" ""))]
921 "TARGET_H8300
922 && operands[0] != stack_pointer_rtx"
923 "")
925 (define_insn "pushhi1_h8300hs_advanced"
926 [(set (reg:SI SP_REG)
927 (plus:SI (reg:SI SP_REG) (const_int -4)))
928 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
929 (match_operand:HI 0 "register_operand" "r"))]
930 "(TARGET_H8300H || TARGET_H8300S)
931 && operands[0] != stack_pointer_rtx"
932 "mov.l\\t%S0,@-er7"
933 [(set_attr "length" "4")])
935 (define_insn "pushhi1_h8300hs_normal"
936 [(set (reg:HI SP_REG)
937 (plus:HI (reg:HI SP_REG) (const_int -4)))
938 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
939 (match_operand:HI 0 "register_operand" "r"))]
940 "(TARGET_H8300H || TARGET_H8300S)
941 && operands[0] != stack_pointer_rtx"
942 "mov.l\\t%S0,@-er7"
943 [(set_attr "length" "4")])
945 (define_expand "pushhi1"
946 [(match_operand:HI 0 "register_operand" "")]
947 ""
948 "
949 {
950 if (TARGET_H8300)
951 emit_insn (gen_pushhi1_h8300 (operands[0]));
952 else if (!TARGET_NORMAL_MODE)
953 emit_insn (gen_pushhi1_h8300hs_advanced (operands[0]));
954 else
955 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
956 DONE;
957 }")
958 \f
959 ;; ----------------------------------------------------------------------
960 ;; TEST INSTRUCTIONS
961 ;; ----------------------------------------------------------------------
963 (define_insn ""
964 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
965 (const_int 1)
966 (match_operand 1 "const_int_operand" "n,n")))]
967 "TARGET_H8300"
968 "btst %Z1,%Y0"
969 [(set_attr "length" "2,4")
970 (set_attr "cc" "set_zn,set_zn")])
972 (define_insn ""
973 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
974 (const_int 1)
975 (match_operand 1 "const_int_operand" "n")))]
976 "TARGET_H8300"
977 "btst %Z1,%Y0"
978 [(set_attr "length" "2")
979 (set_attr "cc" "set_zn")])
981 (define_insn_and_split "*tst_extzv_1_n"
982 [(set (cc0)
983 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
984 (const_int 1)
985 (match_operand 1 "const_int_operand" "n,n,n")))
986 (clobber (match_scratch:QI 2 "=X,X,&r"))]
987 "(TARGET_H8300H || TARGET_H8300S)"
988 "@
989 btst\\t%Z1,%Y0
990 btst\\t%Z1,%Y0
991 #"
992 "&& reload_completed
993 && !OK_FOR_U (operands[0])"
994 [(set (match_dup 2)
995 (match_dup 0))
996 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
997 (const_int 1)
998 (match_dup 1)))
999 (clobber (scratch:QI))])]
1000 ""
1001 [(set_attr "length" "2,8,10")
1002 (set_attr "cc" "set_zn,set_zn,set_zn")])
1004 (define_insn ""
1005 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1006 (const_int 1)
1007 (match_operand 1 "const_int_operand" "n")))]
1008 "(TARGET_H8300H || TARGET_H8300S)
1009 && INTVAL (operands[1]) <= 15"
1010 "btst %Z1,%Y0"
1011 [(set_attr "length" "2")
1012 (set_attr "cc" "set_zn")])
1014 (define_insn_and_split "*tstsi_upper_bit"
1015 [(set (cc0)
1016 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1017 (const_int 1)
1018 (match_operand 1 "const_int_operand" "n")))
1019 (clobber (match_scratch:SI 2 "=&r"))]
1020 "(TARGET_H8300H || TARGET_H8300S)
1021 && INTVAL (operands[1]) >= 16"
1022 "#"
1023 "&& reload_completed"
1024 [(set (match_dup 2)
1025 (ior:SI (and:SI (match_dup 2)
1026 (const_int -65536))
1027 (lshiftrt:SI (match_dup 0)
1028 (const_int 16))))
1029 (set (cc0)
1030 (zero_extract:SI (match_dup 2)
1031 (const_int 1)
1032 (match_dup 3)))]
1033 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
1035 (define_insn "*tstsi_variable_bit"
1036 [(set (cc0)
1037 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1038 (const_int 1)
1039 (and:SI (match_operand:SI 1 "register_operand" "r")
1040 (const_int 7))))]
1041 "TARGET_H8300H || TARGET_H8300S"
1042 "btst %w1,%w0"
1043 [(set_attr "length" "2")
1044 (set_attr "cc" "set_zn")])
1046 (define_insn_and_split "*tstsi_variable_bit_qi"
1047 [(set (cc0)
1048 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
1049 (const_int 1)
1050 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
1051 (const_int 7))))
1052 (clobber (match_scratch:QI 2 "=X,X,&r"))]
1053 "(TARGET_H8300H || TARGET_H8300S)"
1054 "@
1055 btst\\t%w1,%X0
1056 btst\\t%w1,%X0
1057 #"
1058 "&& reload_completed
1059 && !OK_FOR_U (operands[0])"
1060 [(set (match_dup 2)
1061 (match_dup 0))
1062 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
1063 (const_int 1)
1064 (and:SI (match_dup 1)
1065 (const_int 7))))
1066 (clobber (scratch:QI))])]
1067 ""
1068 [(set_attr "length" "2,8,10")
1069 (set_attr "cc" "set_zn,set_zn,set_zn")])
1071 (define_insn "tstqi"
1072 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
1073 ""
1074 "mov.b %X0,%X0"
1075 [(set_attr "length" "2")
1076 (set_attr "cc" "set_znv")])
1078 (define_insn "tsthi"
1079 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
1080 ""
1081 "mov.w %T0,%T0"
1082 [(set_attr "length" "2")
1083 (set_attr "cc" "set_znv")])
1085 (define_insn "*tsthi_upper"
1086 [(set (cc0)
1087 (and:HI (match_operand:HI 0 "register_operand" "r")
1088 (const_int -256)))]
1089 ""
1090 "mov.b %t0,%t0"
1091 [(set_attr "length" "2")
1092 (set_attr "cc" "set_znv")])
1094 (define_insn "tstsi"
1095 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
1096 "TARGET_H8300H || TARGET_H8300S"
1097 "mov.l %S0,%S0"
1098 [(set_attr "length" "2")
1099 (set_attr "cc" "set_znv")])
1101 (define_insn "*tstsi_upper"
1102 [(set (cc0)
1103 (and:SI (match_operand:SI 0 "register_operand" "r")
1104 (const_int -65536)))]
1105 ""
1106 "mov.w %e0,%e0"
1107 [(set_attr "length" "2")
1108 (set_attr "cc" "set_znv")])
1110 (define_insn "cmpqi"
1111 [(set (cc0)
1112 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1113 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1114 ""
1115 "cmp.b %X1,%X0"
1116 [(set_attr "length_table" "addb")
1117 (set_attr "cc" "compare")])
1119 (define_expand "cmphi"
1120 [(set (cc0)
1121 (compare (match_operand:HI 0 "h8300_dst_operand" "")
1122 (match_operand:HI 1 "h8300_src_operand" "")))]
1123 ""
1124 "
1125 {
1126 /* Force operand1 into a register if we're compiling
1127 for the H8/300. */
1128 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
1129 operands[1] = force_reg (HImode, operands[1]);
1130 }")
1132 (define_insn "*cmphi_h8300_znvc"
1133 [(set (cc0)
1134 (compare (match_operand:HI 0 "register_operand" "r")
1135 (match_operand:HI 1 "register_operand" "r")))]
1136 "TARGET_H8300"
1137 "cmp.w %T1,%T0"
1138 [(set_attr "length" "2")
1139 (set_attr "cc" "compare")])
1141 (define_insn "*cmphi_h8300hs_znvc"
1142 [(set (cc0)
1143 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1144 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1145 "TARGET_H8300H || TARGET_H8300S"
1146 "cmp.w %T1,%T0"
1147 [(set_attr "length_table" "short_immediate,addw")
1148 (set_attr "cc" "compare,compare")])
1150 (define_insn "cmpsi"
1151 [(set (cc0)
1152 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1153 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1154 "TARGET_H8300H || TARGET_H8300S"
1155 "cmp.l %S1,%S0"
1156 [(set_attr "length" "2,*")
1157 (set_attr "length_table" "*,addl")
1158 (set_attr "cc" "compare,compare")])
1159 \f
1160 ;; ----------------------------------------------------------------------
1161 ;; ADD INSTRUCTIONS
1162 ;; ----------------------------------------------------------------------
1164 (define_expand "addqi3"
1165 [(set (match_operand:QI 0 "register_operand" "")
1166 (plus:QI (match_operand:QI 1 "register_operand" "")
1167 (match_operand:QI 2 "h8300_src_operand" "")))]
1168 ""
1169 "")
1171 (define_insn "*addqi3"
1172 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1173 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1174 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1175 "h8300_operands_match_p (operands)"
1176 "add.b %X2,%X0"
1177 [(set_attr "length_table" "addb")
1178 (set_attr "cc" "set_zn")])
1180 (define_expand "addhi3"
1181 [(set (match_operand:HI 0 "register_operand" "")
1182 (plus:HI (match_operand:HI 1 "register_operand" "")
1183 (match_operand:HI 2 "h8300_src_operand" "")))]
1184 ""
1185 "")
1187 (define_insn "*addhi3_h8300"
1188 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1189 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1190 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1191 "TARGET_H8300"
1192 "@
1193 adds %2,%T0
1194 subs %G2,%T0
1195 add.b %t2,%t0
1196 add.b %s2,%s0\;addx %t2,%t0
1197 add.w %T2,%T0"
1198 [(set_attr "length" "2,2,2,4,2")
1199 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1201 ;; This splitter is very important to make the stack adjustment
1202 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1203 ;;
1204 ;; We apply this split after the peephole2 pass so that we won't end
1205 ;; up creating too many adds/subs when a scratch register is
1206 ;; available, which is actually a common case because stack unrolling
1207 ;; tends to happen immediately after a function call.
1209 (define_split
1210 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1211 (plus:HI (match_dup 0)
1212 (match_operand 1 "const_int_gt_2_operand" "")))]
1213 "TARGET_H8300 && flow2_completed"
1214 [(const_int 0)]
1215 "split_adds_subs (HImode, operands); DONE;")
1217 (define_peephole2
1218 [(match_scratch:HI 2 "r")
1219 (set (match_operand:HI 0 "stack_pointer_operand" "")
1220 (plus:HI (match_dup 0)
1221 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1222 "TARGET_H8300"
1223 [(set (match_dup 2)
1224 (match_dup 1))
1225 (set (match_dup 0)
1226 (plus:HI (match_dup 0)
1227 (match_dup 2)))]
1228 "")
1230 (define_insn "*addhi3_h8300hs"
1231 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1232 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1233 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1234 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1235 "@
1236 adds %2,%S0
1237 subs %G2,%S0
1238 add.b %t2,%t0
1239 add.w %T2,%T0
1240 add.w %T2,%T0"
1241 [(set_attr "length" "2,2,2,4,2")
1242 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1244 (define_insn "*addhi3_incdec"
1245 [(set (match_operand:HI 0 "register_operand" "=r,r")
1246 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1247 (match_operand:HI 2 "incdec_operand" "M,O")]
1248 UNSPEC_INCDEC))]
1249 "TARGET_H8300H || TARGET_H8300S"
1250 "@
1251 inc.w %2,%T0
1252 dec.w %G2,%T0"
1253 [(set_attr "length" "2,2")
1254 (set_attr "cc" "set_zn,set_zn")])
1256 (define_insn "*addhi3_h8sx"
1257 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1258 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1259 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1260 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1261 "@
1262 add.w %T2,%T0
1263 sub.w %G2,%T0
1264 add.b %t2,%t0
1265 add.w %T2,%T0"
1266 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1267 (set_attr "length" "*,*,2,*")
1268 (set_attr "cc" "set_zn")])
1270 (define_split
1271 [(set (match_operand:HI 0 "register_operand" "")
1272 (plus:HI (match_dup 0)
1273 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1274 ""
1275 [(const_int 0)]
1276 "split_adds_subs (HImode, operands); DONE;")
1278 (define_expand "addsi3"
1279 [(set (match_operand:SI 0 "register_operand" "")
1280 (plus:SI (match_operand:SI 1 "register_operand" "")
1281 (match_operand:SI 2 "h8300_src_operand" "")))]
1282 ""
1283 "")
1285 (define_insn "*addsi_h8300"
1286 [(set (match_operand:SI 0 "register_operand" "=r,r")
1287 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1288 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1289 "TARGET_H8300"
1290 "* return output_plussi (operands);"
1291 [(set (attr "length")
1292 (symbol_ref "compute_plussi_length (operands)"))
1293 (set (attr "cc")
1294 (symbol_ref "compute_plussi_cc (operands)"))])
1296 (define_insn "*addsi_h8300hs"
1297 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1298 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1299 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1300 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1301 "* return output_plussi (operands);"
1302 [(set (attr "length")
1303 (symbol_ref "compute_plussi_length (operands)"))
1304 (set (attr "cc")
1305 (symbol_ref "compute_plussi_cc (operands)"))])
1307 (define_insn "*addsi3_incdec"
1308 [(set (match_operand:SI 0 "register_operand" "=r,r")
1309 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1310 (match_operand:SI 2 "incdec_operand" "M,O")]
1311 UNSPEC_INCDEC))]
1312 "TARGET_H8300H || TARGET_H8300S"
1313 "@
1314 inc.l %2,%S0
1315 dec.l %G2,%S0"
1316 [(set_attr "length" "2,2")
1317 (set_attr "cc" "set_zn,set_zn")])
1319 (define_split
1320 [(set (match_operand:SI 0 "register_operand" "")
1321 (plus:SI (match_dup 0)
1322 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1323 "TARGET_H8300H || TARGET_H8300S"
1324 [(const_int 0)]
1325 "split_adds_subs (SImode, operands); DONE;")
1327 ;; ----------------------------------------------------------------------
1328 ;; SUBTRACT INSTRUCTIONS
1329 ;; ----------------------------------------------------------------------
1331 (define_expand "subqi3"
1332 [(set (match_operand:QI 0 "register_operand" "")
1333 (minus:QI (match_operand:QI 1 "register_operand" "")
1334 (match_operand:QI 2 "h8300_src_operand" "")))]
1335 ""
1336 "")
1338 (define_insn "*subqi3"
1339 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1340 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1341 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1342 "h8300_operands_match_p (operands)"
1343 "sub.b %X2,%X0"
1344 [(set_attr "length_table" "addb")
1345 (set_attr "cc" "set_zn")])
1347 (define_expand "subhi3"
1348 [(set (match_operand:HI 0 "register_operand" "")
1349 (minus:HI (match_operand:HI 1 "register_operand" "")
1350 (match_operand:HI 2 "h8300_src_operand" "")))]
1351 ""
1352 "")
1354 (define_insn "*subhi3_h8300"
1355 [(set (match_operand:HI 0 "register_operand" "=r,r")
1356 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1357 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1358 "TARGET_H8300"
1359 "@
1360 sub.w %T2,%T0
1361 add.b %E2,%s0\;addx %F2,%t0"
1362 [(set_attr "length" "2,4")
1363 (set_attr "cc" "set_zn,clobber")])
1365 (define_insn "*subhi3_h8300hs"
1366 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1367 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1368 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1369 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1370 "@
1371 sub.w %T2,%T0
1372 sub.w %T2,%T0"
1373 [(set_attr "length_table" "addw")
1374 (set_attr "cc" "set_zn")])
1376 (define_expand "subsi3"
1377 [(set (match_operand:SI 0 "register_operand" "")
1378 (minus:SI (match_operand:SI 1 "register_operand" "")
1379 (match_operand:SI 2 "h8300_src_operand" "")))]
1380 ""
1381 {
1382 if (TARGET_H8300)
1383 operands[2] = force_reg (SImode, operands[2]);
1384 })
1386 (define_insn "*subsi3_h8300"
1387 [(set (match_operand:SI 0 "register_operand" "=r")
1388 (minus:SI (match_operand:SI 1 "register_operand" "0")
1389 (match_operand:SI 2 "register_operand" "r")))]
1390 "TARGET_H8300"
1391 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1392 [(set_attr "length" "6")])
1394 (define_insn "*subsi3_h8300hs"
1395 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1396 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1397 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1398 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1399 "@
1400 sub.l %S2,%S0
1401 sub.l %S2,%S0"
1402 [(set_attr "length_table" "addl")
1403 (set_attr "cc" "set_zn")])
1404 \f
1405 ;; ----------------------------------------------------------------------
1406 ;; MULTIPLY INSTRUCTIONS
1407 ;; ----------------------------------------------------------------------
1409 ;; Note that the H8/300 can only handle umulqihi3.
1411 (define_expand "mulqihi3"
1412 [(set (match_operand:HI 0 "register_operand" "")
1413 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1414 ;; intentionally-mismatched modes
1415 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1416 "TARGET_H8300H || TARGET_H8300S"
1417 "
1418 {
1419 if (GET_MODE (operands[2]) != VOIDmode)
1420 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1421 }")
1423 (define_insn "*mulqihi3_const"
1424 [(set (match_operand:HI 0 "register_operand" "=r")
1425 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1426 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1427 "TARGET_H8300SX"
1428 "mulxs.b %X2,%T0"
1429 [(set_attr "length" "4")
1430 (set_attr "cc" "set_zn")])
1432 (define_insn "*mulqihi3"
1433 [(set (match_operand:HI 0 "register_operand" "=r")
1434 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1435 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1436 "TARGET_H8300H || TARGET_H8300S"
1437 "mulxs.b %X2,%T0"
1438 [(set_attr "length" "4")
1439 (set_attr "cc" "set_zn")])
1441 (define_expand "mulhisi3"
1442 [(set (match_operand:SI 0 "register_operand" "")
1443 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1444 ;; intentionally-mismatched modes
1445 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1446 "TARGET_H8300H || TARGET_H8300S"
1447 "
1448 {
1449 if (GET_MODE (operands[2]) != VOIDmode)
1450 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1451 }")
1453 (define_insn "*mulhisi3_const"
1454 [(set (match_operand:SI 0 "register_operand" "=r")
1455 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1456 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1457 "TARGET_H8300SX"
1458 "mulxs.w %T2,%S0"
1459 [(set_attr "length" "4")
1460 (set_attr "cc" "set_zn")])
1462 (define_insn "*mulhisi3"
1463 [(set (match_operand:SI 0 "register_operand" "=r")
1464 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1465 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1466 "TARGET_H8300H || TARGET_H8300S"
1467 "mulxs.w %T2,%S0"
1468 [(set_attr "length" "4")
1469 (set_attr "cc" "set_zn")])
1471 (define_expand "umulqihi3"
1472 [(set (match_operand:HI 0 "register_operand" "")
1473 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1474 ;; intentionally-mismatched modes
1475 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1476 "TARGET_H8300H || TARGET_H8300S"
1477 "
1478 {
1479 if (GET_MODE (operands[2]) != VOIDmode)
1480 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1481 }")
1483 (define_insn "*umulqihi3_const"
1484 [(set (match_operand:HI 0 "register_operand" "=r")
1485 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1486 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1487 "TARGET_H8300SX"
1488 "mulxu.b %X2,%T0"
1489 [(set_attr "length" "4")
1490 (set_attr "cc" "set_zn")])
1492 (define_insn "*umulqihi3"
1493 [(set (match_operand:HI 0 "register_operand" "=r")
1494 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1495 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1496 ""
1497 "mulxu.b %X2,%T0"
1498 [(set_attr "length" "2")
1499 (set_attr "cc" "none_0hit")])
1501 (define_expand "umulhisi3"
1502 [(set (match_operand:SI 0 "register_operand" "")
1503 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1504 ;; intentionally-mismatched modes
1505 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1506 "TARGET_H8300H || TARGET_H8300S"
1507 "
1508 {
1509 if (GET_MODE (operands[2]) != VOIDmode)
1510 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1511 }")
1513 (define_insn "*umulhisi3_const"
1514 [(set (match_operand:SI 0 "register_operand" "=r")
1515 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1516 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1517 "TARGET_H8300SX"
1518 "mulxu.w %T2,%S0"
1519 [(set_attr "length" "4")
1520 (set_attr "cc" "set_zn")])
1522 (define_insn "*umulhisi3"
1523 [(set (match_operand:SI 0 "register_operand" "=r")
1524 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1525 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1526 "TARGET_H8300H || TARGET_H8300S"
1527 "mulxu.w %T2,%S0"
1528 [(set_attr "length" "2")
1529 (set_attr "cc" "none_0hit")])
1531 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1532 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1533 ;; on all H8SX variants.
1534 (define_insn "mulhi3"
1535 [(set (match_operand:HI 0 "register_operand" "=r")
1536 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1537 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1538 "TARGET_H8300SX"
1539 "muls.w\\t%T2,%T0"
1540 [(set_attr "length" "2")
1541 (set_attr "cc" "set_zn")])
1543 (define_insn "mulsi3"
1544 [(set (match_operand:SI 0 "register_operand" "=r")
1545 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1546 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1547 "TARGET_H8300SX"
1548 "muls.l\\t%S2,%S0"
1549 [(set_attr "length" "2")
1550 (set_attr "cc" "set_zn")])
1552 (define_insn "smulsi3_highpart"
1553 [(set (match_operand:SI 0 "register_operand" "=r")
1554 (truncate:SI
1555 (lshiftrt:DI
1556 (mult:DI
1557 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1558 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1559 (const_int 32))))]
1560 "TARGET_H8300SXMUL"
1561 "muls/u.l\\t%S2,%S0"
1562 [(set_attr "length" "2")
1563 (set_attr "cc" "set_zn")])
1565 (define_insn "umulsi3_highpart"
1566 [(set (match_operand:SI 0 "register_operand" "=r")
1567 (truncate:SI
1568 (ashiftrt:DI
1569 (mult:DI
1570 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1571 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1572 (const_int 32))))]
1573 "TARGET_H8300SX"
1574 "mulu/u.l\\t%S2,%S0"
1575 [(set_attr "length" "2")
1576 (set_attr "cc" "none_0hit")])
1578 ;; This is a "bridge" instruction. Combine can't cram enough insns
1579 ;; together to crate a MAC instruction directly, but it can create
1580 ;; this instruction, which then allows combine to create the real
1581 ;; MAC insn.
1582 ;;
1583 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1584 ;; insn must generate reasonably correct code. Egad.
1585 (define_insn ""
1586 [(set (match_operand:SI 0 "register_operand" "=a")
1587 (mult:SI
1588 (sign_extend:SI
1589 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1590 (sign_extend:SI
1591 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1592 "TARGET_MAC"
1593 "clrmac\;mac @%2+,@%1+"
1594 [(set_attr "length" "6")
1595 (set_attr "cc" "none_0hit")])
1597 (define_insn ""
1598 [(set (match_operand:SI 0 "register_operand" "=a")
1599 (plus:SI (mult:SI
1600 (sign_extend:SI (mem:HI
1601 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1602 (sign_extend:SI (mem:HI
1603 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1604 (match_operand:SI 3 "register_operand" "0")))]
1605 "TARGET_MAC"
1606 "mac @%2+,@%1+"
1607 [(set_attr "length" "4")
1608 (set_attr "cc" "none_0hit")])
1610 ;; ----------------------------------------------------------------------
1611 ;; DIVIDE/MOD INSTRUCTIONS
1612 ;; ----------------------------------------------------------------------
1614 (define_insn "udivhi3"
1615 [(set (match_operand:HI 0 "register_operand" "=r")
1616 (udiv:HI
1617 (match_operand:HI 1 "register_operand" "0")
1618 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1619 "TARGET_H8300SX"
1620 "divu.w\\t%T2,%T0"
1621 [(set_attr "length" "2")])
1623 (define_insn "divhi3"
1624 [(set (match_operand:HI 0 "register_operand" "=r")
1625 (div:HI
1626 (match_operand:HI 1 "register_operand" "0")
1627 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1628 "TARGET_H8300SX"
1629 "divs.w\\t%T2,%T0"
1630 [(set_attr "length" "2")])
1632 (define_insn "udivsi3"
1633 [(set (match_operand:SI 0 "register_operand" "=r")
1634 (udiv:SI
1635 (match_operand:SI 1 "register_operand" "0")
1636 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1637 "TARGET_H8300SX"
1638 "divu.l\\t%S2,%S0"
1639 [(set_attr "length" "2")])
1641 (define_insn "divsi3"
1642 [(set (match_operand:SI 0 "register_operand" "=r")
1643 (div:SI
1644 (match_operand:SI 1 "register_operand" "0")
1645 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1646 "TARGET_H8300SX"
1647 "divs.l\\t%S2,%S0"
1648 [(set_attr "length" "2")])
1650 (define_insn "udivmodqi4"
1651 [(set (match_operand:QI 0 "register_operand" "=r")
1652 (truncate:QI
1653 (udiv:HI
1654 (match_operand:HI 1 "register_operand" "0")
1655 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1656 (set (match_operand:QI 3 "register_operand" "=r")
1657 (truncate:QI
1658 (umod:HI
1659 (match_dup 1)
1660 (zero_extend:HI (match_dup 2)))))]
1661 ""
1662 "*
1663 {
1664 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1665 return \"divxu.b\\t%X2,%T0\";
1666 else
1667 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1668 }"
1669 [(set_attr "length" "4")])
1671 (define_insn "divmodqi4"
1672 [(set (match_operand:QI 0 "register_operand" "=r")
1673 (truncate:QI
1674 (div:HI
1675 (match_operand:HI 1 "register_operand" "0")
1676 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1677 (set (match_operand:QI 3 "register_operand" "=r")
1678 (truncate:QI
1679 (mod:HI
1680 (match_dup 1)
1681 (sign_extend:HI (match_dup 2)))))]
1682 "TARGET_H8300H || TARGET_H8300S"
1683 "*
1684 {
1685 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1686 return \"divxs.b\\t%X2,%T0\";
1687 else
1688 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1689 }"
1690 [(set_attr "length" "6")])
1692 (define_insn "udivmodhi4"
1693 [(set (match_operand:HI 0 "register_operand" "=r")
1694 (truncate:HI
1695 (udiv:SI
1696 (match_operand:SI 1 "register_operand" "0")
1697 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1698 (set (match_operand:HI 3 "register_operand" "=r")
1699 (truncate:HI
1700 (umod:SI
1701 (match_dup 1)
1702 (zero_extend:SI (match_dup 2)))))]
1703 "TARGET_H8300H || TARGET_H8300S"
1704 "*
1705 {
1706 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1707 return \"divxu.w\\t%T2,%S0\";
1708 else
1709 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1710 }"
1711 [(set_attr "length" "4")])
1713 (define_insn "divmodhi4"
1714 [(set (match_operand:HI 0 "register_operand" "=r")
1715 (truncate:HI
1716 (div:SI
1717 (match_operand:SI 1 "register_operand" "0")
1718 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1719 (set (match_operand:HI 3 "register_operand" "=r")
1720 (truncate:HI
1721 (mod:SI
1722 (match_dup 1)
1723 (sign_extend:SI (match_dup 2)))))]
1724 "TARGET_H8300H || TARGET_H8300S"
1725 "*
1726 {
1727 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1728 return \"divxs.w\\t%T2,%S0\";
1729 else
1730 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1731 }"
1732 [(set_attr "length" "6")])
1733 \f
1734 ;; ----------------------------------------------------------------------
1735 ;; AND INSTRUCTIONS
1736 ;; ----------------------------------------------------------------------
1738 (define_insn "*andqi3_2"
1739 [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
1740 (and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
1741 (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
1742 "TARGET_H8300SX"
1743 "@
1744 and %X2,%X0
1745 bfld %2,%1,%R0"
1746 [(set_attr "length" "*,8")
1747 (set_attr "length_table" "logicb,*")
1748 (set_attr "cc" "set_znv,none_0hit")])
1750 (define_insn "andqi3_1"
1751 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1752 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1753 (match_operand:QI 2 "h8300_src_operand" "rn,n")))]
1754 "register_operand (operands[0], QImode)
1755 || single_zero_operand (operands[2], QImode)"
1756 "@
1757 and %X2,%X0
1758 bclr %W2,%R0"
1759 [(set_attr "length" "2,8")
1760 (set_attr "cc" "set_znv,none_0hit")])
1762 (define_expand "andqi3"
1763 [(set (match_operand:QI 0 "register_operand" "")
1764 (and:QI (match_operand:QI 1 "register_operand" "")
1765 (match_operand:QI 2 "h8300_src_operand" "")))]
1766 ""
1767 "")
1769 (define_expand "andhi3"
1770 [(set (match_operand:HI 0 "register_operand" "")
1771 (and:HI (match_operand:HI 1 "register_operand" "")
1772 (match_operand:HI 2 "h8300_src_operand" "")))]
1773 ""
1774 "")
1776 (define_insn "*andorqi3"
1777 [(set (match_operand:QI 0 "register_operand" "=r")
1778 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1779 (match_operand:QI 3 "single_one_operand" "n"))
1780 (match_operand:QI 1 "register_operand" "0")))]
1781 ""
1782 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1783 [(set_attr "length" "6")])
1785 (define_insn "*andorhi3"
1786 [(set (match_operand:HI 0 "register_operand" "=r")
1787 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1788 (match_operand:HI 3 "single_one_operand" "n"))
1789 (match_operand:HI 1 "register_operand" "0")))]
1790 ""
1791 "*
1792 {
1793 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1794 if (INTVAL (operands[3]) > 128)
1795 {
1796 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1797 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1798 }
1799 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1800 }"
1801 [(set_attr "length" "6")])
1803 (define_insn "*andorsi3"
1804 [(set (match_operand:SI 0 "register_operand" "=r")
1805 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1806 (match_operand:SI 3 "single_one_operand" "n"))
1807 (match_operand:SI 1 "register_operand" "0")))]
1808 "(INTVAL (operands[3]) & 0xffff) != 0"
1809 "*
1810 {
1811 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1812 if (INTVAL (operands[3]) > 128)
1813 {
1814 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1815 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1816 }
1817 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1818 }"
1819 [(set_attr "length" "6")])
1821 (define_insn "*andorsi3_shift_8"
1822 [(set (match_operand:SI 0 "register_operand" "=r")
1823 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1824 (const_int 8))
1825 (const_int 65280))
1826 (match_operand:SI 1 "register_operand" "0")))]
1827 ""
1828 "or.b\\t%w2,%x0"
1829 [(set_attr "length" "2")])
1831 (define_expand "andsi3"
1832 [(set (match_operand:SI 0 "register_operand" "")
1833 (and:SI (match_operand:SI 1 "register_operand" "")
1834 (match_operand:SI 2 "h8300_src_operand" "")))]
1835 ""
1836 "")
1838 ;; ----------------------------------------------------------------------
1839 ;; OR INSTRUCTIONS
1840 ;; ----------------------------------------------------------------------
1842 (define_insn "iorqi3_1"
1843 [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
1844 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1845 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1846 "TARGET_H8300SX || register_operand (operands[0], QImode)
1847 || single_one_operand (operands[2], QImode)"
1848 "@
1849 or\\t%X2,%X0
1850 bset\\t%V2,%R0"
1851 [(set_attr "length" "*,8")
1852 (set_attr "length_table" "logicb,*")
1853 (set_attr "cc" "set_znv,none_0hit")])
1855 (define_expand "iorqi3"
1856 [(set (match_operand:QI 0 "register_operand" "")
1857 (ior:QI (match_operand:QI 1 "register_operand" "")
1858 (match_operand:QI 2 "h8300_src_operand" "")))]
1859 ""
1860 "")
1862 (define_expand "iorhi3"
1863 [(set (match_operand:HI 0 "register_operand" "")
1864 (ior:HI (match_operand:HI 1 "register_operand" "")
1865 (match_operand:HI 2 "h8300_src_operand" "")))]
1866 ""
1867 "")
1869 (define_expand "iorsi3"
1870 [(set (match_operand:SI 0 "register_operand" "")
1871 (ior:SI (match_operand:SI 1 "register_operand" "")
1872 (match_operand:SI 2 "h8300_src_operand" "")))]
1873 ""
1874 "")
1876 ;; ----------------------------------------------------------------------
1877 ;; XOR INSTRUCTIONS
1878 ;; ----------------------------------------------------------------------
1880 (define_insn "xorqi3_1"
1881 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1882 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1883 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1884 "TARGET_H8300SX || register_operand (operands[0], QImode)
1885 || single_one_operand (operands[2], QImode)"
1886 "@
1887 xor\\t%X2,%X0
1888 bnot\\t%V2,%R0"
1889 [(set_attr "length" "*,8")
1890 (set_attr "length_table" "logicb,*")
1891 (set_attr "cc" "set_znv,none_0hit")])
1893 (define_expand "xorqi3"
1894 [(set (match_operand:QI 0 "register_operand" "")
1895 (xor:QI (match_operand:QI 1 "register_operand" "")
1896 (match_operand:QI 2 "h8300_src_operand" "")))]
1897 ""
1898 "")
1900 (define_expand "xorhi3"
1901 [(set (match_operand:HI 0 "register_operand" "")
1902 (xor:HI (match_operand:HI 1 "register_operand" "")
1903 (match_operand:HI 2 "h8300_src_operand" "")))]
1904 ""
1905 "")
1907 (define_expand "xorsi3"
1908 [(set (match_operand:SI 0 "register_operand" "")
1909 (xor:SI (match_operand:SI 1 "register_operand" "")
1910 (match_operand:SI 2 "h8300_src_operand" "")))]
1911 ""
1912 "")
1914 ;; ----------------------------------------------------------------------
1915 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1916 ;; ----------------------------------------------------------------------
1918 ;; We need a separate pattern here because machines other than the
1919 ;; original H8300 don't have to split the 16-bit operand into a pair
1920 ;; of high/low instructions, so we can accept literal addresses, that
1921 ;; have to be loaded into a register on H8300.
1922 (define_insn "*logicalhi3_sn"
1923 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1924 (match_operator:HI 3 "bit_operator"
1925 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1926 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1927 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1928 "* return output_logical_op (HImode, operands);"
1929 [(set (attr "length")
1930 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1931 (set (attr "cc")
1932 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1934 (define_insn "*logicalsi3_sn"
1935 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1936 (match_operator:SI 3 "bit_operator"
1937 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1938 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1939 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1940 "* return output_logical_op (SImode, operands);"
1941 [(set (attr "length")
1942 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1943 (set (attr "cc")
1944 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1946 (define_insn "*logicalhi3"
1947 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1948 (match_operator:HI 3 "bit_operator"
1949 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1950 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1951 "h8300_operands_match_p (operands)"
1952 "* return output_logical_op (HImode, operands);"
1953 [(set (attr "length")
1954 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1955 (set (attr "cc")
1956 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1958 (define_insn "*logicalsi3"
1959 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1960 (match_operator:SI 3 "bit_operator"
1961 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1962 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1963 "h8300_operands_match_p (operands)"
1964 "* return output_logical_op (SImode, operands);"
1965 [(set (attr "length")
1966 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1967 (set (attr "cc")
1968 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1969 \f
1970 ;; ----------------------------------------------------------------------
1971 ;; NEGATION INSTRUCTIONS
1972 ;; ----------------------------------------------------------------------
1974 (define_expand "negqi2"
1975 [(set (match_operand:QI 0 "register_operand" "")
1976 (neg:QI (match_operand:QI 1 "register_operand" "")))]
1977 ""
1978 "")
1980 (define_insn "*negqi2"
1981 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1982 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1983 ""
1984 "neg %X0"
1985 [(set_attr "length_table" "unary")
1986 (set_attr "cc" "set_zn")])
1988 (define_expand "neghi2"
1989 [(set (match_operand:HI 0 "register_operand" "")
1990 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1991 ""
1992 "
1993 {
1994 if (TARGET_H8300)
1995 {
1996 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1997 DONE;
1998 }
1999 }")
2001 (define_expand "neghi2_h8300"
2002 [(set (match_dup 2)
2003 (not:HI (match_operand:HI 1 "register_operand" "")))
2004 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2005 (set (match_operand:HI 0 "register_operand" "")
2006 (match_dup 2))]
2007 ""
2008 "operands[2] = gen_reg_rtx (HImode);")
2010 (define_insn "*neghi2_h8300hs"
2011 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2012 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2013 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2014 "neg.w %T0"
2015 [(set_attr "length_table" "unary")
2016 (set_attr "cc" "set_zn")])
2018 (define_expand "negsi2"
2019 [(set (match_operand:SI 0 "register_operand" "")
2020 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2021 ""
2022 "
2023 {
2024 if (TARGET_H8300)
2025 {
2026 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2027 DONE;
2028 }
2029 }")
2031 (define_expand "negsi2_h8300"
2032 [(set (match_dup 2)
2033 (not:SI (match_operand:SI 1 "register_operand" "")))
2034 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2035 (set (match_operand:SI 0 "register_operand" "")
2036 (match_dup 2))]
2037 ""
2038 "operands[2] = gen_reg_rtx (SImode);")
2040 (define_insn "*negsi2_h8300hs"
2041 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2042 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2043 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2044 "neg.l %S0"
2045 [(set_attr "length_table" "unary")
2046 (set_attr "cc" "set_zn")])
2048 (define_expand "negsf2"
2049 [(set (match_operand:SF 0 "register_operand" "")
2050 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2051 ""
2052 "")
2054 (define_insn "*negsf2_h8300"
2055 [(set (match_operand:SF 0 "register_operand" "=r")
2056 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2057 "TARGET_H8300"
2058 "xor.b\\t#128,%z0"
2059 [(set_attr "length" "2")])
2061 (define_insn "*negsf2_h8300hs"
2062 [(set (match_operand:SF 0 "register_operand" "=r")
2063 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2064 "TARGET_H8300H || TARGET_H8300S"
2065 "xor.w\\t#32768,%e0"
2066 [(set_attr "length" "4")])
2067 \f
2068 ;; ----------------------------------------------------------------------
2069 ;; ABSOLUTE VALUE INSTRUCTIONS
2070 ;; ----------------------------------------------------------------------
2072 (define_expand "abssf2"
2073 [(set (match_operand:SF 0 "register_operand" "")
2074 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2075 ""
2076 "")
2078 (define_insn "*abssf2_h8300"
2079 [(set (match_operand:SF 0 "register_operand" "=r")
2080 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2081 "TARGET_H8300"
2082 "and.b\\t#127,%z0"
2083 [(set_attr "length" "2")])
2085 (define_insn "*abssf2_h8300hs"
2086 [(set (match_operand:SF 0 "register_operand" "=r")
2087 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2088 "TARGET_H8300H || TARGET_H8300S"
2089 "and.w\\t#32767,%e0"
2090 [(set_attr "length" "4")])
2091 \f
2092 ;; ----------------------------------------------------------------------
2093 ;; NOT INSTRUCTIONS
2094 ;; ----------------------------------------------------------------------
2096 (define_expand "one_cmplqi2"
2097 [(set (match_operand:QI 0 "register_operand" "")
2098 (not:QI (match_operand:QI 1 "register_operand" "")))]
2099 ""
2100 "")
2102 (define_insn "*one_cmplqi2"
2103 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2104 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2105 ""
2106 "not %X0"
2107 [(set_attr "length_table" "unary")
2108 (set_attr "cc" "set_znv")])
2110 (define_expand "one_cmplhi2"
2111 [(set (match_operand:HI 0 "register_operand" "")
2112 (not:HI (match_operand:HI 1 "register_operand" "")))]
2113 ""
2114 "")
2116 (define_insn "*one_cmplhi2_h8300"
2117 [(set (match_operand:HI 0 "register_operand" "=r")
2118 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2119 "TARGET_H8300"
2120 "not %s0\;not %t0"
2121 [(set_attr "length" "4")])
2123 (define_insn "*one_cmplhi2_h8300hs"
2124 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2125 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2126 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2127 "not.w %T0"
2128 [(set_attr "cc" "set_znv")
2129 (set_attr "length_table" "unary")])
2131 (define_expand "one_cmplsi2"
2132 [(set (match_operand:SI 0 "register_operand" "")
2133 (not:SI (match_operand:SI 1 "register_operand" "")))]
2134 ""
2135 "")
2137 (define_insn "*one_cmplsi2_h8300"
2138 [(set (match_operand:SI 0 "register_operand" "=r")
2139 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2140 "TARGET_H8300"
2141 "not %w0\;not %x0\;not %y0\;not %z0"
2142 [(set_attr "length" "8")])
2144 (define_insn "*one_cmplsi2_h8300hs"
2145 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2146 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2147 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2148 "not.l %S0"
2149 [(set_attr "cc" "set_znv")
2150 (set_attr "length_table" "unary")])
2151 \f
2152 ;; ----------------------------------------------------------------------
2153 ;; JUMP INSTRUCTIONS
2154 ;; ----------------------------------------------------------------------
2156 ;; Conditional jump instructions
2158 (define_expand "ble"
2159 [(match_operand 0 "" "")]
2160 ""
2161 "h8300_expand_branch (LE, operands[0]); DONE;")
2163 (define_expand "bleu"
2164 [(match_operand 0 "" "")]
2165 ""
2166 "h8300_expand_branch (LEU, operands[0]); DONE;")
2168 (define_expand "bge"
2169 [(match_operand 0 "" "")]
2170 ""
2171 "h8300_expand_branch (GE, operands[0]); DONE;")
2173 (define_expand "bgeu"
2174 [(match_operand 0 "" "")]
2175 ""
2176 "h8300_expand_branch (GEU, operands[0]); DONE;")
2178 (define_expand "blt"
2179 [(match_operand 0 "" "")]
2180 ""
2181 "h8300_expand_branch (LT, operands[0]); DONE;")
2183 (define_expand "bltu"
2184 [(match_operand 0 "" "")]
2185 ""
2186 "h8300_expand_branch (LTU, operands[0]); DONE;")
2188 (define_expand "bgt"
2189 [(match_operand 0 "" "")]
2190 ""
2191 "h8300_expand_branch (GT, operands[0]); DONE;")
2193 (define_expand "bgtu"
2194 [(match_operand 0 "" "")]
2195 ""
2196 "h8300_expand_branch (GTU, operands[0]); DONE;")
2198 (define_expand "beq"
2199 [(match_operand 0 "" "")]
2200 ""
2201 "h8300_expand_branch (EQ, operands[0]); DONE;")
2203 (define_expand "bne"
2204 [(match_operand 0 "" "")]
2205 ""
2206 "h8300_expand_branch (NE, operands[0]); DONE;")
2208 (define_insn "branch_true"
2209 [(set (pc)
2210 (if_then_else (match_operator 1 "comparison_operator"
2211 [(cc0) (const_int 0)])
2212 (label_ref (match_operand 0 "" ""))
2213 (pc)))]
2214 ""
2215 "*
2216 {
2217 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2218 && (GET_CODE (operands[1]) == GT
2219 || GET_CODE (operands[1]) == GE
2220 || GET_CODE (operands[1]) == LE
2221 || GET_CODE (operands[1]) == LT))
2222 {
2223 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2224 return 0;
2225 }
2227 if (get_attr_length (insn) == 2)
2228 return \"b%j1 %l0\";
2229 else if (get_attr_length (insn) == 4)
2230 return \"b%j1 %l0:16\";
2231 else
2232 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2233 }"
2234 [(set_attr "type" "branch")
2235 (set_attr "cc" "none")])
2237 (define_insn "branch_false"
2238 [(set (pc)
2239 (if_then_else (match_operator 1 "comparison_operator"
2240 [(cc0) (const_int 0)])
2241 (pc)
2242 (label_ref (match_operand 0 "" ""))))]
2243 ""
2244 "*
2245 {
2246 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2247 && (GET_CODE (operands[1]) == GT
2248 || GET_CODE (operands[1]) == GE
2249 || GET_CODE (operands[1]) == LE
2250 || GET_CODE (operands[1]) == LT))
2251 {
2252 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2253 return 0;
2254 }
2256 if (get_attr_length (insn) == 2)
2257 return \"b%k1 %l0\";
2258 else if (get_attr_length (insn) == 4)
2259 return \"b%k1 %l0:16\";
2260 else
2261 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2262 }"
2263 [(set_attr "type" "branch")
2264 (set_attr "cc" "none")])
2266 (define_insn "*brabc"
2267 [(set (pc)
2268 (if_then_else
2269 (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2270 (const_int 1)
2271 (match_operand:QI 2 "immediate_operand" "n"))
2272 (const_int 0))
2273 (label_ref (match_operand 0 "" ""))
2274 (pc)))]
2275 "TARGET_H8300SX"
2276 "*
2277 {
2278 switch (get_attr_length (insn)
2279 - h8300_insn_length_from_table (insn, operands))
2280 {
2281 case 2:
2282 return \"bra/bc %2,%R1,%l0\";
2284 case 4:
2285 return \"bra/bc %2,%R1,%l0:16\";
2287 default:
2288 return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2289 }
2290 }"
2291 [(set_attr "type" "bitbranch")
2292 (set_attr "length_table" "bitbranch")
2293 (set_attr "cc" "none")])
2295 (define_insn "*brabs"
2296 [(set (pc)
2297 (if_then_else
2298 (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2299 (const_int 1)
2300 (match_operand:QI 2 "immediate_operand" "n"))
2301 (const_int 0))
2302 (label_ref (match_operand 0 "" ""))
2303 (pc)))]
2304 "TARGET_H8300SX"
2305 "*
2306 {
2307 switch (get_attr_length (insn)
2308 - h8300_insn_length_from_table (insn, operands))
2309 {
2310 case 2:
2311 return \"bra/bs %2,%R1,%l0\";
2313 case 4:
2314 return \"bra/bs %2,%R1,%l0:16\";
2316 default:
2317 return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2318 }
2319 }"
2320 [(set_attr "type" "bitbranch")
2321 (set_attr "length_table" "bitbranch")
2322 (set_attr "cc" "none")])
2324 ;; Unconditional and other jump instructions.
2326 (define_insn "jump"
2327 [(set (pc)
2328 (label_ref (match_operand 0 "" "")))]
2329 ""
2330 "*
2331 {
2332 if (final_sequence != 0)
2333 {
2334 if (get_attr_length (insn) == 2)
2335 return \"bra/s %l0\";
2336 else
2337 {
2338 /* The branch isn't short enough to use bra/s. Output the
2339 branch and delay slot in their normal order.
2341 If this is a backward branch, it will now be branching two
2342 bytes further than previously thought. The length-based
2343 test for bra vs. jump is very conservative though, so the
2344 branch will still be within range. */
2345 rtvec vec;
2346 int seen;
2348 vec = XVEC (final_sequence, 0);
2349 final_sequence = 0;
2350 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen);
2351 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen);
2352 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2353 return \"\";
2354 }
2355 }
2356 else if (get_attr_length (insn) == 2)
2357 return \"bra %l0\";
2358 else if (get_attr_length (insn) == 4)
2359 return \"bra %l0:16\";
2360 else
2361 return \"jmp @%l0\";
2362 }"
2363 [(set_attr "type" "branch")
2364 (set (attr "delay_slot")
2365 (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0))
2366 (const_string "jump")
2367 (const_string "none")))
2368 (set_attr "cc" "none")])
2370 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2372 (define_expand "tablejump"
2373 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2374 (use (label_ref (match_operand 1 "" "")))])]
2375 ""
2376 "")
2378 (define_insn "*tablejump_h8300"
2379 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2380 (use (label_ref (match_operand 1 "" "")))]
2381 "TARGET_H8300"
2382 "jmp @%0"
2383 [(set_attr "cc" "none")
2384 (set_attr "length" "2")])
2386 (define_insn "*tablejump_h8300hs_advanced"
2387 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2388 (use (label_ref (match_operand 1 "" "")))]
2389 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2390 "jmp @%0"
2391 [(set_attr "cc" "none")
2392 (set_attr "length" "2")])
2394 (define_insn "*tablejump_h8300hs_normal"
2395 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2396 (use (label_ref (match_operand 1 "" "")))]
2397 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2398 "jmp @%S0"
2399 [(set_attr "cc" "none")
2400 (set_attr "length" "2")])
2402 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2404 (define_expand "indirect_jump"
2405 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2406 ""
2407 "")
2409 (define_insn "*indirect_jump_h8300"
2410 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2411 "TARGET_H8300"
2412 "jmp @%0"
2413 [(set_attr "cc" "none")
2414 (set_attr "length" "2")])
2416 (define_insn "*indirect_jump_h8300hs_advanced"
2417 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2418 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2419 "jmp @%0"
2420 [(set_attr "cc" "none")
2421 (set_attr "length" "2")])
2423 (define_insn "*indirect_jump_h8300hs_normal"
2424 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2425 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2426 "jmp @%S0"
2427 [(set_attr "cc" "none")
2428 (set_attr "length" "2")])
2430 ;; Call subroutine with no return value.
2432 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2434 (define_insn "call"
2435 [(call (match_operand:QI 0 "call_insn_operand" "or")
2436 (match_operand:HI 1 "general_operand" "g"))]
2437 ""
2438 "*
2439 {
2440 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2441 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2442 return \"jsr\\t@%0:8\";
2443 else
2444 return \"jsr\\t%0\";
2445 }"
2446 [(set_attr "type" "call")
2447 (set (attr "length")
2448 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2449 (const_int 2)
2450 (const_int 4)))])
2452 ;; Call subroutine, returning value in operand 0
2453 ;; (which must be a hard register).
2455 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2457 (define_insn "call_value"
2458 [(set (match_operand 0 "" "=r")
2459 (call (match_operand:QI 1 "call_insn_operand" "or")
2460 (match_operand:HI 2 "general_operand" "g")))]
2461 ""
2462 "*
2463 {
2464 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2465 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2466 return \"jsr\\t@%1:8\";
2467 else
2468 return \"jsr\\t%1\";
2469 }"
2470 [(set_attr "type" "call")
2471 (set (attr "length")
2472 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2473 (const_int 2)
2474 (const_int 4)))])
2476 (define_insn "nop"
2477 [(const_int 0)]
2478 ""
2479 "nop"
2480 [(set_attr "cc" "none")
2481 (set_attr "length" "2")])
2482 \f
2483 ;; ----------------------------------------------------------------------
2484 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2485 ;; ----------------------------------------------------------------------
2487 (define_expand "push_h8300"
2488 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2489 (match_operand:HI 0 "register_operand" ""))]
2490 "TARGET_H8300"
2491 "")
2493 (define_expand "push_h8300hs_advanced"
2494 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2495 (match_operand:SI 0 "register_operand" ""))]
2496 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2497 "")
2499 (define_expand "push_h8300hs_normal"
2500 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2501 (match_operand:SI 0 "register_operand" ""))]
2502 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2503 "")
2505 (define_expand "pop_h8300"
2506 [(set (match_operand:HI 0 "register_operand" "")
2507 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2508 "TARGET_H8300"
2509 "")
2511 (define_expand "pop_h8300hs_advanced"
2512 [(set (match_operand:SI 0 "register_operand" "")
2513 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2514 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2515 "")
2517 (define_expand "pop_h8300hs_normal"
2518 [(set (match_operand:SI 0 "register_operand" "")
2519 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2520 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2521 "")
2523 (define_insn "ldm_h8300sx"
2524 [(match_parallel 0 "h8300_ldm_parallel"
2525 [(set (match_operand:SI 1 "register_operand" "")
2526 (match_operand:SI 2 "memory_operand" ""))])]
2527 "TARGET_H8300S"
2528 {
2529 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2530 XVECLEN (operands[0], 0) - 2));
2531 return "ldm.l\t@er7+,%S1-%S3";
2532 }
2533 [(set_attr "cc" "none")
2534 (set_attr "length" "4")])
2536 (define_insn "stm_h8300sx"
2537 [(match_parallel 0 "h8300_stm_parallel"
2538 [(set (match_operand:SI 1 "memory_operand" "")
2539 (match_operand:SI 2 "register_operand" ""))])]
2540 "TARGET_H8300S"
2541 {
2542 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2543 XVECLEN (operands[0], 0) - 2));
2544 return "stm.l\t%S2-%S3,@-er7";
2545 }
2546 [(set_attr "cc" "none")
2547 (set_attr "length" "4")])
2549 (define_insn "return_h8sx"
2550 [(match_parallel 0 "h8300_return_parallel"
2551 [(return)
2552 (set (match_operand:SI 1 "register_operand" "")
2553 (match_operand:SI 2 "memory_operand" ""))])]
2554 "TARGET_H8300SX"
2555 {
2556 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2557 XVECLEN (operands[0], 0) - 2));
2558 if (h8300_current_function_interrupt_function_p ())
2559 return "rte/l\t%S1-%S3";
2560 else
2561 return "rts/l\t%S1-%S3";
2562 }
2563 [(set_attr "cc" "none")
2564 (set_attr "can_delay" "no")
2565 (set_attr "length" "2")])
2567 (define_expand "return"
2568 [(return)]
2569 "h8300_can_use_return_insn_p ()"
2570 "")
2572 (define_insn "*return_1"
2573 [(return)]
2574 "reload_completed"
2575 "*
2576 {
2577 if (h8300_current_function_interrupt_function_p ())
2578 return \"rte\";
2579 else
2580 return \"rts\";
2581 }"
2582 [(set_attr "cc" "none")
2583 (set_attr "can_delay" "no")
2584 (set_attr "length" "2")])
2586 (define_expand "prologue"
2587 [(const_int 0)]
2588 ""
2589 "h8300_expand_prologue (); DONE;")
2591 (define_expand "epilogue"
2592 [(return)]
2593 ""
2594 "h8300_expand_epilogue (); DONE;")
2596 (define_insn "monitor_prologue"
2597 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2598 ""
2599 "*
2600 {
2601 if (TARGET_H8300)
2602 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2603 else if (TARGET_H8300H)
2604 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2605 else if (TARGET_H8300S)
2606 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2607 gcc_unreachable ();
2608 }"
2609 [(set_attr "length" "20")])
2610 \f
2611 ;; ----------------------------------------------------------------------
2612 ;; EXTEND INSTRUCTIONS
2613 ;; ----------------------------------------------------------------------
2615 (define_expand "zero_extendqihi2"
2616 [(set (match_operand:HI 0 "register_operand" "")
2617 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2618 ""
2619 "")
2621 (define_insn "*zero_extendqihi2_h8300"
2622 [(set (match_operand:HI 0 "register_operand" "=r,r")
2623 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2624 "TARGET_H8300"
2625 "@
2626 mov.b #0,%t0
2627 #"
2628 [(set_attr "length" "2,10")])
2630 (define_insn "*zero_extendqihi2_h8300hs"
2631 [(set (match_operand:HI 0 "register_operand" "=r,r")
2632 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2633 "TARGET_H8300H || TARGET_H8300S"
2634 "@
2635 extu.w %T0
2636 #"
2637 [(set_attr "length" "2,10")
2638 (set_attr "cc" "set_znv,set_znv")])
2640 ;; Split the zero extension of a general operand (actually a memory
2641 ;; operand) into a load of the operand and the actual zero extension
2642 ;; so that 1) the length will be accurate, and 2) the zero extensions
2643 ;; appearing at the end of basic blocks may be merged.
2645 (define_split
2646 [(set (match_operand:HI 0 "register_operand" "")
2647 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2648 "reload_completed"
2649 [(set (match_dup 2)
2650 (match_dup 1))
2651 (set (match_dup 0)
2652 (zero_extend:HI (match_dup 2)))]
2653 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2655 (define_expand "zero_extendqisi2"
2656 [(set (match_operand:SI 0 "register_operand" "")
2657 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2658 ""
2659 {
2660 if (TARGET_H8300SX)
2661 operands[1] = force_reg (QImode, operands[1]);
2662 })
2664 (define_insn "*zero_extendqisi2_h8300"
2665 [(set (match_operand:SI 0 "register_operand" "=r,r")
2666 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2667 "TARGET_H8300"
2668 "@
2669 mov.b #0,%x0\;sub.w %e0,%e0
2670 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2671 [(set_attr "length" "4,8")])
2673 (define_insn "*zero_extendqisi2_h8300hs"
2674 [(set (match_operand:SI 0 "register_operand" "=r,r")
2675 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2676 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2677 "#")
2679 (define_split
2680 [(set (match_operand:SI 0 "register_operand" "")
2681 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2682 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2683 && reg_overlap_mentioned_p (operands[0], operands[1])
2684 && reload_completed"
2685 [(set (match_dup 2)
2686 (match_dup 1))
2687 (set (match_dup 3)
2688 (zero_extend:HI (match_dup 2)))
2689 (set (match_dup 0)
2690 (zero_extend:SI (match_dup 3)))]
2691 "operands[2] = gen_lowpart (QImode, operands[0]);
2692 operands[3] = gen_lowpart (HImode, operands[0]);")
2694 (define_split
2695 [(set (match_operand:SI 0 "register_operand" "")
2696 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2697 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2698 && !reg_overlap_mentioned_p (operands[0], operands[1])
2699 && reload_completed"
2700 [(set (match_dup 0)
2701 (const_int 0))
2702 (set (strict_low_part (match_dup 2))
2703 (match_dup 1))]
2704 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2706 (define_insn "*zero_extendqisi2_h8sx"
2707 [(set (match_operand:SI 0 "register_operand" "=r")
2708 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2709 "TARGET_H8300SX"
2710 "extu.l\t#2,%0"
2711 [(set_attr "length" "2")
2712 (set_attr "cc" "set_znv")])
2714 (define_expand "zero_extendhisi2"
2715 [(set (match_operand:SI 0 "register_operand" "")
2716 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2717 ""
2718 "")
2720 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2721 (define_insn "*zero_extendhisi2_h8300"
2722 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2723 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2724 "TARGET_H8300"
2725 "@
2726 sub.w %e0,%e0
2727 mov.w %f1,%f0\;sub.w %e0,%e0
2728 mov.w %e1,%f0\;sub.w %e0,%e0"
2729 [(set_attr "length" "2,4,6")])
2731 (define_insn "*zero_extendhisi2_h8300hs"
2732 [(set (match_operand:SI 0 "register_operand" "=r")
2733 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2734 "TARGET_H8300H || TARGET_H8300S"
2735 "extu.l %S0"
2736 [(set_attr "length" "2")
2737 (set_attr "cc" "set_znv")])
2739 (define_expand "extendqihi2"
2740 [(set (match_operand:HI 0 "register_operand" "")
2741 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2742 ""
2743 "")
2745 (define_insn "*extendqihi2_h8300"
2746 [(set (match_operand:HI 0 "register_operand" "=r,r")
2747 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2748 "TARGET_H8300"
2749 "@
2750 bld #7,%s0\;subx %t0,%t0
2751 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2752 [(set_attr "length" "4,8")])
2754 (define_insn "*extendqihi2_h8300hs"
2755 [(set (match_operand:HI 0 "register_operand" "=r")
2756 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2757 "TARGET_H8300H || TARGET_H8300S"
2758 "exts.w %T0"
2759 [(set_attr "length" "2")
2760 (set_attr "cc" "set_znv")])
2762 (define_expand "extendqisi2"
2763 [(set (match_operand:SI 0 "register_operand" "")
2764 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2765 ""
2766 "")
2768 (define_insn "*extendqisi2_h8300"
2769 [(set (match_operand:SI 0 "register_operand" "=r,r")
2770 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2771 "TARGET_H8300"
2772 "@
2773 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2774 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2775 [(set_attr "length" "8,12")])
2777 ;; The following pattern is needed because without the pattern, the
2778 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2779 ;; shifts, one ashift and one ashiftrt.
2781 (define_insn_and_split "*extendqisi2_h8300hs"
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2784 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2785 "#"
2786 "&& reload_completed"
2787 [(set (match_dup 2)
2788 (sign_extend:HI (match_dup 1)))
2789 (set (match_dup 0)
2790 (sign_extend:SI (match_dup 2)))]
2791 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2793 (define_insn "*extendqisi2_h8sx"
2794 [(set (match_operand:SI 0 "register_operand" "=r")
2795 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2796 "TARGET_H8300SX"
2797 "exts.l\t#2,%0"
2798 [(set_attr "length" "2")
2799 (set_attr "cc" "set_znv")])
2801 (define_expand "extendhisi2"
2802 [(set (match_operand:SI 0 "register_operand" "")
2803 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2804 ""
2805 "")
2807 (define_insn "*extendhisi2_h8300"
2808 [(set (match_operand:SI 0 "register_operand" "=r,r")
2809 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2810 "TARGET_H8300"
2811 "@
2812 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2813 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2814 [(set_attr "length" "6,10")])
2816 (define_insn "*extendhisi2_h8300hs"
2817 [(set (match_operand:SI 0 "register_operand" "=r")
2818 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2819 "TARGET_H8300H || TARGET_H8300S"
2820 "exts.l %S0"
2821 [(set_attr "length" "2")
2822 (set_attr "cc" "set_znv")])
2823 \f
2824 ;; ----------------------------------------------------------------------
2825 ;; SHIFTS
2826 ;; ----------------------------------------------------------------------
2827 ;;
2828 ;; We make some attempt to provide real efficient shifting. One example is
2829 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2830 ;; reg and moving 0 into the former reg.
2831 ;;
2832 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2833 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2834 ;; give the optimizer more cracks at the code. However, we wish to do things
2835 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2836 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2837 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2838 ;; to detect cases it can optimize.
2839 ;;
2840 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2841 ;; easier "do it at insn emit time" route.
2843 ;; QI BIT SHIFTS
2845 (define_expand "ashlqi3"
2846 [(set (match_operand:QI 0 "register_operand" "")
2847 (ashift:QI (match_operand:QI 1 "register_operand" "")
2848 (match_operand:QI 2 "nonmemory_operand" "")))]
2849 ""
2850 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;")
2852 (define_expand "ashrqi3"
2853 [(set (match_operand:QI 0 "register_operand" "")
2854 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2855 (match_operand:QI 2 "nonmemory_operand" "")))]
2856 ""
2857 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;")
2859 (define_expand "lshrqi3"
2860 [(set (match_operand:QI 0 "register_operand" "")
2861 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2862 (match_operand:QI 2 "nonmemory_operand" "")))]
2863 ""
2864 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;")
2866 (define_insn ""
2867 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2868 (match_operator:QI 3 "h8sx_unary_shift_operator"
2869 [(match_operand:QI 1 "h8300_dst_operand" "0")
2870 (match_operand:QI 2 "const_int_operand" "")]))]
2871 "h8300_operands_match_p (operands)"
2872 { return output_h8sx_shift (operands, 'b', 'X'); }
2873 [(set_attr "length_table" "unary")
2874 (set_attr "cc" "set_znv")])
2876 (define_insn ""
2877 [(set (match_operand:QI 0 "register_operand" "=r")
2878 (match_operator:QI 3 "h8sx_binary_shift_operator"
2879 [(match_operand:QI 1 "register_operand" "0")
2880 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2881 ""
2882 { return output_h8sx_shift (operands, 'b', 'X'); }
2883 [(set_attr "length" "4")
2884 (set_attr "cc" "set_znv")])
2886 (define_insn "*shiftqi"
2887 [(set (match_operand:QI 0 "register_operand" "=r,r")
2888 (match_operator:QI 3 "nshift_operator"
2889 [ (match_operand:QI 1 "register_operand" "0,0")
2890 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2891 (clobber (match_scratch:QI 4 "=X,&r"))]
2892 ""
2893 "* return output_a_shift (operands);"
2894 [(set (attr "length")
2895 (symbol_ref "compute_a_shift_length (insn, operands)"))
2896 (set (attr "cc")
2897 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2899 ;; HI BIT SHIFTS
2901 (define_expand "ashlhi3"
2902 [(set (match_operand:HI 0 "register_operand" "")
2903 (ashift:HI (match_operand:HI 1 "register_operand" "")
2904 (match_operand:QI 2 "nonmemory_operand" "")))]
2905 ""
2906 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;")
2908 (define_expand "lshrhi3"
2909 [(set (match_operand:HI 0 "register_operand" "")
2910 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2911 (match_operand:QI 2 "nonmemory_operand" "")))]
2912 ""
2913 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;")
2915 (define_expand "ashrhi3"
2916 [(set (match_operand:HI 0 "register_operand" "")
2917 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2918 (match_operand:QI 2 "nonmemory_operand" "")))]
2919 ""
2920 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;")
2922 (define_insn ""
2923 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2924 (match_operator:HI 3 "h8sx_unary_shift_operator"
2925 [(match_operand:HI 1 "h8300_dst_operand" "0")
2926 (match_operand:QI 2 "const_int_operand" "")]))]
2927 "h8300_operands_match_p (operands)"
2928 { return output_h8sx_shift (operands, 'w', 'T'); }
2929 [(set_attr "length_table" "unary")
2930 (set_attr "cc" "set_znv")])
2932 (define_insn ""
2933 [(set (match_operand:HI 0 "register_operand" "=r")
2934 (match_operator:HI 3 "h8sx_binary_shift_operator"
2935 [(match_operand:HI 1 "register_operand" "0")
2936 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2937 ""
2938 { return output_h8sx_shift (operands, 'w', 'T'); }
2939 [(set_attr "length" "4")
2940 (set_attr "cc" "set_znv")])
2942 (define_insn "*shifthi"
2943 [(set (match_operand:HI 0 "register_operand" "=r,r")
2944 (match_operator:HI 3 "nshift_operator"
2945 [ (match_operand:HI 1 "register_operand" "0,0")
2946 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2947 (clobber (match_scratch:QI 4 "=X,&r"))]
2948 ""
2949 "* return output_a_shift (operands);"
2950 [(set (attr "length")
2951 (symbol_ref "compute_a_shift_length (insn, operands)"))
2952 (set (attr "cc")
2953 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2955 ;; SI BIT SHIFTS
2957 (define_expand "ashlsi3"
2958 [(set (match_operand:SI 0 "register_operand" "")
2959 (ashift:SI (match_operand:SI 1 "register_operand" "")
2960 (match_operand:QI 2 "nonmemory_operand" "")))]
2961 ""
2962 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;")
2964 (define_expand "lshrsi3"
2965 [(set (match_operand:SI 0 "register_operand" "")
2966 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2967 (match_operand:QI 2 "nonmemory_operand" "")))]
2968 ""
2969 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;")
2971 (define_expand "ashrsi3"
2972 [(set (match_operand:SI 0 "register_operand" "")
2973 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
2974 (match_operand:QI 2 "nonmemory_operand" "")))]
2975 ""
2976 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;")
2978 (define_insn ""
2979 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2980 (match_operator:SI 3 "h8sx_unary_shift_operator"
2981 [(match_operand:SI 1 "h8300_dst_operand" "0")
2982 (match_operand:QI 2 "const_int_operand" "")]))]
2983 "h8300_operands_match_p (operands)"
2984 { return output_h8sx_shift (operands, 'l', 'S'); }
2985 [(set_attr "length_table" "unary")
2986 (set_attr "cc" "set_znv")])
2988 (define_insn ""
2989 [(set (match_operand:SI 0 "register_operand" "=r")
2990 (match_operator:SI 3 "h8sx_binary_shift_operator"
2991 [(match_operand:SI 1 "register_operand" "0")
2992 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
2993 ""
2994 { return output_h8sx_shift (operands, 'l', 'S'); }
2995 [(set_attr "length" "4")
2996 (set_attr "cc" "set_znv")])
2998 (define_insn "*shiftsi"
2999 [(set (match_operand:SI 0 "register_operand" "=r,r")
3000 (match_operator:SI 3 "nshift_operator"
3001 [ (match_operand:SI 1 "register_operand" "0,0")
3002 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3003 (clobber (match_scratch:QI 4 "=X,&r"))]
3004 ""
3005 "* return output_a_shift (operands);"
3006 [(set (attr "length")
3007 (symbol_ref "compute_a_shift_length (insn, operands)"))
3008 (set (attr "cc")
3009 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3011 ;; Split a variable shift into a loop. If the register containing
3012 ;; the shift count dies, then we just use that register.
3014 (define_split
3015 [(set (match_operand 0 "register_operand" "")
3016 (match_operator 2 "nshift_operator"
3017 [(match_dup 0)
3018 (match_operand:QI 1 "register_operand" "")]))
3019 (clobber (match_operand:QI 3 "register_operand" ""))]
3020 "flow2_completed
3021 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3022 [(set (cc0)
3023 (match_dup 1))
3024 (set (pc)
3025 (if_then_else (le (cc0) (const_int 0))
3026 (label_ref (match_dup 5))
3027 (pc)))
3028 (match_dup 4)
3029 (parallel
3030 [(set (match_dup 0)
3031 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3032 (clobber (scratch:QI))])
3033 (set (match_dup 1)
3034 (plus:QI (match_dup 1) (const_int -1)))
3035 (set (cc0)
3036 (match_dup 1))
3037 (set (pc)
3038 (if_then_else (ne (cc0) (const_int 0))
3039 (label_ref (match_dup 4))
3040 (pc)))
3041 (match_dup 5)]
3042 "operands[4] = gen_label_rtx ();
3043 operands[5] = gen_label_rtx ();")
3045 (define_split
3046 [(set (match_operand 0 "register_operand" "")
3047 (match_operator 2 "nshift_operator"
3048 [(match_dup 0)
3049 (match_operand:QI 1 "register_operand" "")]))
3050 (clobber (match_operand:QI 3 "register_operand" ""))]
3051 "flow2_completed
3052 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3053 [(set (match_dup 3)
3054 (match_dup 1))
3055 (set (cc0)
3056 (match_dup 3))
3057 (set (pc)
3058 (if_then_else (le (cc0) (const_int 0))
3059 (label_ref (match_dup 5))
3060 (pc)))
3061 (match_dup 4)
3062 (parallel
3063 [(set (match_dup 0)
3064 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3065 (clobber (scratch:QI))])
3066 (set (match_dup 3)
3067 (plus:QI (match_dup 3) (const_int -1)))
3068 (set (cc0)
3069 (match_dup 3))
3070 (set (pc)
3071 (if_then_else (ne (cc0) (const_int 0))
3072 (label_ref (match_dup 4))
3073 (pc)))
3074 (match_dup 5)]
3075 "operands[4] = gen_label_rtx ();
3076 operands[5] = gen_label_rtx ();")
3077 \f
3078 ;; ----------------------------------------------------------------------
3079 ;; ROTATIONS
3080 ;; ----------------------------------------------------------------------
3082 (define_expand "rotlqi3"
3083 [(set (match_operand:QI 0 "register_operand" "")
3084 (rotate:QI (match_operand:QI 1 "register_operand" "")
3085 (match_operand:QI 2 "nonmemory_operand" "")))]
3086 ""
3087 "if (expand_a_rotate (operands)) DONE;")
3089 (define_insn "rotlqi3_1"
3090 [(set (match_operand:QI 0 "register_operand" "=r")
3091 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3092 (match_operand:QI 2 "immediate_operand" "")))]
3093 ""
3094 "* return output_a_rotate (ROTATE, operands);"
3095 [(set (attr "length")
3096 (symbol_ref "compute_a_rotate_length (operands)"))])
3098 (define_expand "rotlhi3"
3099 [(set (match_operand:HI 0 "register_operand" "")
3100 (rotate:HI (match_operand:HI 1 "register_operand" "")
3101 (match_operand:QI 2 "nonmemory_operand" "")))]
3102 ""
3103 "if (expand_a_rotate (operands)) DONE;")
3105 (define_insn "rotlhi3_1"
3106 [(set (match_operand:HI 0 "register_operand" "=r")
3107 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3108 (match_operand:QI 2 "immediate_operand" "")))]
3109 ""
3110 "* return output_a_rotate (ROTATE, operands);"
3111 [(set (attr "length")
3112 (symbol_ref "compute_a_rotate_length (operands)"))])
3114 (define_expand "rotlsi3"
3115 [(set (match_operand:SI 0 "register_operand" "")
3116 (rotate:SI (match_operand:SI 1 "register_operand" "")
3117 (match_operand:QI 2 "nonmemory_operand" "")))]
3118 "TARGET_H8300H || TARGET_H8300S"
3119 "if (expand_a_rotate (operands)) DONE;")
3121 (define_insn "rotlsi3_1"
3122 [(set (match_operand:SI 0 "register_operand" "=r")
3123 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3124 (match_operand:QI 2 "immediate_operand" "")))]
3125 "TARGET_H8300H || TARGET_H8300S"
3126 "* return output_a_rotate (ROTATE, operands);"
3127 [(set (attr "length")
3128 (symbol_ref "compute_a_rotate_length (operands)"))])
3129 \f
3130 ;; -----------------------------------------------------------------
3131 ;; BIT FIELDS
3132 ;; -----------------------------------------------------------------
3133 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3134 ;; instructions so let's use them as well as we can.
3136 ;; You'll never believe all these patterns perform one basic action --
3137 ;; load a bit from the source, optionally invert the bit, then store it
3138 ;; in the destination (which is known to be zero).
3139 ;;
3140 ;; Combine obviously need some work to better identify this situation and
3141 ;; canonicalize the form better.
3143 ;;
3144 ;; Normal loads with a 16bit destination.
3145 ;;
3147 (define_insn ""
3148 [(set (match_operand:HI 0 "register_operand" "=&r")
3149 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3150 (const_int 1)
3151 (match_operand:HI 2 "immediate_operand" "n")))]
3152 "TARGET_H8300"
3153 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3154 [(set_attr "length" "6")])
3156 ;;
3157 ;; Inverted loads with a 16bit destination.
3158 ;;
3160 (define_insn ""
3161 [(set (match_operand:HI 0 "register_operand" "=&r")
3162 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3163 (match_operand:HI 3 "const_int_operand" "n"))
3164 (const_int 1)
3165 (match_operand:HI 2 "const_int_operand" "n")))]
3166 "TARGET_H8300
3167 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3168 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3169 [(set_attr "length" "8")])
3171 ;;
3172 ;; Normal loads with a 32bit destination.
3173 ;;
3175 (define_insn "*extzv_1_r_h8300"
3176 [(set (match_operand:SI 0 "register_operand" "=&r")
3177 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3178 (const_int 1)
3179 (match_operand 2 "const_int_operand" "n")))]
3180 "TARGET_H8300
3181 && INTVAL (operands[2]) < 16"
3182 "* return output_simode_bld (0, operands);"
3183 [(set_attr "length" "8")])
3185 (define_insn "*extzv_1_r_h8300hs"
3186 [(set (match_operand:SI 0 "register_operand" "=r,r")
3187 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3188 (const_int 1)
3189 (match_operand 2 "const_int_operand" "n,n")))]
3190 "(TARGET_H8300H || TARGET_H8300S)
3191 && INTVAL (operands[2]) < 16"
3192 "* return output_simode_bld (0, operands);"
3193 [(set_attr "cc" "set_znv,set_znv")
3194 (set_attr "length" "8,6")])
3196 ;;
3197 ;; Inverted loads with a 32bit destination.
3198 ;;
3200 (define_insn "*extzv_1_r_inv_h8300"
3201 [(set (match_operand:SI 0 "register_operand" "=&r")
3202 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3203 (match_operand:HI 3 "const_int_operand" "n"))
3204 (const_int 1)
3205 (match_operand 2 "const_int_operand" "n")))]
3206 "TARGET_H8300
3207 && INTVAL (operands[2]) < 16
3208 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3209 "* return output_simode_bld (1, operands);"
3210 [(set_attr "length" "8")])
3212 (define_insn "*extzv_1_r_inv_h8300hs"
3213 [(set (match_operand:SI 0 "register_operand" "=r,r")
3214 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3215 (match_operand 3 "const_int_operand" "n,n"))
3216 (const_int 1)
3217 (match_operand 2 "const_int_operand" "n,n")))]
3218 "(TARGET_H8300H || TARGET_H8300S)
3219 && INTVAL (operands[2]) < 16
3220 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3221 "* return output_simode_bld (1, operands);"
3222 [(set_attr "cc" "set_znv,set_znv")
3223 (set_attr "length" "8,6")])
3225 (define_expand "insv"
3226 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3227 (match_operand:HI 1 "general_operand" "")
3228 (match_operand:HI 2 "general_operand" ""))
3229 (match_operand:HI 3 "general_operand" ""))]
3230 "TARGET_H8300 || TARGET_H8300SX"
3231 "
3232 {
3233 if (TARGET_H8300SX)
3234 {
3235 if (GET_CODE (operands[1]) == CONST_INT
3236 && GET_CODE (operands[2]) == CONST_INT
3237 && INTVAL (operands[1]) <= 8
3238 && INTVAL (operands[2]) >= 0
3239 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3240 && memory_operand (operands[0], GET_MODE (operands[0])))
3241 {
3242 /* If the source operand is zero, it's better to use AND rather
3243 than BFST. Likewise OR if the operand is all ones. */
3244 if (GET_CODE (operands[3]) == CONST_INT)
3245 {
3246 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3247 if ((INTVAL (operands[3]) & mask) == 0)
3248 FAIL;
3249 if ((INTVAL (operands[3]) & mask) == mask)
3250 FAIL;
3251 }
3252 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3253 {
3254 if (no_new_pseudos)
3255 FAIL;
3256 operands[0] =
3257 replace_equiv_address (operands[0],
3258 force_reg (Pmode,
3259 XEXP (operands[0], 0)));
3260 }
3261 operands[3] = gen_lowpart (QImode, operands[3]);
3262 if (! operands[3])
3263 FAIL;
3264 if (! register_operand (operands[3], QImode))
3265 {
3266 if (no_new_pseudos)
3267 FAIL;
3268 operands[3] = force_reg (QImode, operands[3]);
3269 }
3270 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3271 operands[3], operands[1], operands[2]));
3272 DONE;
3273 }
3275 FAIL;
3276 }
3278 /* We only have single bit bit-field instructions. */
3279 if (INTVAL (operands[1]) != 1)
3280 FAIL;
3282 /* For now, we don't allow memory operands. */
3283 if (GET_CODE (operands[0]) == MEM
3284 || GET_CODE (operands[3]) == MEM)
3285 FAIL;
3286 }")
3288 (define_insn ""
3289 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3290 (const_int 1)
3291 (match_operand:HI 1 "immediate_operand" "n"))
3292 (match_operand:HI 2 "register_operand" "r"))]
3293 ""
3294 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3295 [(set_attr "length" "4")])
3297 (define_expand "extzv"
3298 [(set (match_operand:HI 0 "register_operand" "")
3299 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3300 (match_operand:HI 2 "general_operand" "")
3301 (match_operand:HI 3 "general_operand" "")))]
3302 "TARGET_H8300 || TARGET_H8300SX"
3303 "
3304 {
3305 if (TARGET_H8300SX)
3306 {
3307 if (GET_CODE (operands[2]) == CONST_INT
3308 && GET_CODE (operands[3]) == CONST_INT
3309 && INTVAL (operands[2]) <= 8
3310 && INTVAL (operands[3]) >= 0
3311 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3312 && memory_operand (operands[1], QImode))
3313 {
3314 rtx temp;
3316 /* Optimize the case where we're extracting into a paradoxical
3317 subreg. It's only necessary to extend to the inner reg. */
3318 if (GET_CODE (operands[0]) == SUBREG
3319 && subreg_lowpart_p (operands[0])
3320 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3321 < GET_MODE_SIZE (GET_MODE (operands[0])))
3322 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3323 == MODE_INT))
3324 operands[0] = SUBREG_REG (operands[0]);
3326 if (no_new_pseudos)
3327 temp = gen_lowpart (QImode, operands[0]);
3328 else
3329 temp = gen_reg_rtx (QImode);
3330 if (! temp)
3331 FAIL;
3332 if (! bit_memory_operand (operands[1], QImode))
3333 {
3334 if (no_new_pseudos)
3335 FAIL;
3336 operands[1] =
3337 replace_equiv_address (operands[1],
3338 force_reg (Pmode,
3339 XEXP (operands[1], 0)));
3340 }
3341 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3342 convert_move (operands[0], temp, 1);
3343 DONE;
3344 }
3345 FAIL;
3346 }
3348 /* We only have single bit bit-field instructions. */
3349 if (INTVAL (operands[2]) != 1)
3350 FAIL;
3352 /* For now, we don't allow memory operands. */
3353 if (GET_CODE (operands[1]) == MEM)
3354 FAIL;
3355 }")
3357 ;; BAND, BOR, and BXOR patterns
3359 (define_insn ""
3360 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3361 (match_operator:HI 4 "bit_operator"
3362 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3363 (const_int 1)
3364 (match_operand:HI 2 "immediate_operand" "n"))
3365 (match_operand:HI 3 "bit_operand" "0")]))]
3366 ""
3367 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3368 [(set_attr "length" "6")])
3370 (define_insn ""
3371 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3372 (match_operator:HI 5 "bit_operator"
3373 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3374 (const_int 1)
3375 (match_operand:HI 2 "immediate_operand" "n"))
3376 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3377 (const_int 1)
3378 (match_operand:HI 4 "immediate_operand" "n"))]))]
3379 ""
3380 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3381 [(set_attr "length" "6")])
3383 (define_insn "bfld"
3384 [(set (match_operand:QI 0 "register_operand" "=r")
3385 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3386 (match_operand:QI 2 "immediate_operand" "n")
3387 (match_operand:QI 3 "immediate_operand" "n")))]
3388 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3389 "*
3390 {
3391 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3392 - (1 << INTVAL (operands[3])));
3393 return \"bfld %2,%1,%R0\";
3394 }"
3395 [(set_attr "cc" "none_0hit")
3396 (set_attr "length_table" "bitfield")])
3398 (define_insn "bfst"
3399 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3400 (match_operand:QI 2 "immediate_operand" "n")
3401 (match_operand:QI 3 "immediate_operand" "n"))
3402 (match_operand:QI 1 "register_operand" "r"))]
3403 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3404 "*
3405 {
3406 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3407 - (1 << INTVAL (operands[3])));
3408 return \"bfst %R1,%2,%0\";
3409 }"
3410 [(set_attr "cc" "none_0hit")
3411 (set_attr "length_table" "bitfield")])
3413 (define_expand "seq"
3414 [(set (match_operand:HI 0 "register_operand" "")
3415 (eq:HI (cc0) (const_int 0)))]
3416 "TARGET_H8300SX"
3417 "")
3419 (define_expand "sne"
3420 [(set (match_operand:HI 0 "register_operand" "")
3421 (ne:HI (cc0) (const_int 0)))]
3422 "TARGET_H8300SX"
3423 "")
3425 (define_insn "*bstzhireg"
3426 [(set (match_operand:HI 0 "register_operand" "=r")
3427 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3428 "TARGET_H8300SX"
3429 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3430 [(set_attr "cc" "clobber")])
3432 (define_insn_and_split "*cmpstz"
3433 [(set (zero_extract:QI
3434 (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3435 (const_int 1)
3436 (match_operand:QI 1 "immediate_operand" "n,n"))
3437 (match_operator:QI
3438 2 "eqne_operator"
3439 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3440 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3441 "TARGET_H8300SX
3442 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3443 || GET_CODE (operands[4]) == CONST_INT)
3444 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3445 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3446 "#"
3447 "reload_completed"
3448 [(set (cc0) (match_dup 5))
3449 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3450 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3451 "
3452 {
3453 if (operands[4] == const0_rtx && GET_CODE (operands[3]) == REG)
3454 operands[5] = operands[3];
3455 else
3456 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3457 }"
3458 [(set_attr "cc" "set_znv,compare")])
3460 (define_insn "*bstz"
3461 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3462 (const_int 1)
3463 (match_operand:QI 1 "immediate_operand" "n"))
3464 (eq:QI (cc0) (const_int 0)))]
3465 "TARGET_H8300SX && reload_completed"
3466 "bstz %1,%0"
3467 [(set_attr "cc" "none_0hit")
3468 (set_attr "length_table" "unary")])
3470 (define_insn "*bistz"
3471 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3472 (const_int 1)
3473 (match_operand:QI 1 "immediate_operand" "n"))
3474 (ne:QI (cc0) (const_int 0)))]
3475 "TARGET_H8300SX && reload_completed"
3476 "bistz %1,%0"
3477 [(set_attr "cc" "none_0hit")
3478 (set_attr "length_table" "unary")])
3480 (define_insn_and_split "*cmpcondbset"
3481 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3482 (if_then_else:QI
3483 (match_operator
3484 1 "eqne_operator"
3485 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3486 (match_operand 3 "h8300_src_operand" "I,rQi")])
3487 (ior:QI
3488 (match_operand:QI 4 "bit_memory_operand" "0,0")
3489 (match_operand:QI 5 "single_one_operand" "n,n"))
3490 (match_dup 4)))]
3491 "TARGET_H8300SX"
3492 "#"
3493 "reload_completed"
3494 [(set (cc0) (match_dup 6))
3495 (set (match_dup 0)
3496 (if_then_else:QI
3497 (match_op_dup 1 [(cc0) (const_int 0)])
3498 (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3499 "
3500 {
3501 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3502 operands[6] = operands[2];
3503 else
3504 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3505 }"
3506 [(set_attr "cc" "set_znv,compare")])
3508 (define_insn "*condbset"
3509 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3510 (if_then_else:QI
3511 (match_operator:QI 2 "eqne_operator"
3512 [(cc0) (const_int 0)])
3513 (ior:QI
3514 (match_operand:QI 3 "bit_memory_operand" "0")
3515 (match_operand:QI 1 "single_one_operand" "n"))
3516 (match_dup 3)))]
3517 "TARGET_H8300SX && reload_completed"
3518 "bset/%j2\t%V1,%0"
3519 [(set_attr "cc" "none_0hit")
3520 (set_attr "length_table" "logicb")])
3522 (define_insn_and_split "*cmpcondbclr"
3523 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3524 (if_then_else:QI
3525 (match_operator
3526 1 "eqne_operator"
3527 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3528 (match_operand 3 "h8300_src_operand" "I,rQi")])
3529 (and:QI
3530 (match_operand:QI 4 "bit_memory_operand" "0,0")
3531 (match_operand:QI 5 "single_zero_operand" "n,n"))
3532 (match_dup 4)))]
3533 "TARGET_H8300SX"
3534 "#"
3535 "reload_completed"
3536 [(set (cc0) (match_dup 6))
3537 (set (match_dup 0)
3538 (if_then_else:QI
3539 (match_op_dup 1 [(cc0) (const_int 0)])
3540 (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3541 "
3542 {
3543 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3544 operands[6] = operands[2];
3545 else
3546 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3547 }"
3548 [(set_attr "cc" "set_znv,compare")])
3550 (define_insn "*condbclr"
3551 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3552 (if_then_else:QI
3553 (match_operator:QI 2 "eqne_operator"
3554 [(cc0) (const_int 0)])
3555 (and:QI
3556 (match_operand:QI 3 "bit_memory_operand" "0")
3557 (match_operand:QI 1 "single_zero_operand" "n"))
3558 (match_dup 3)))]
3559 "TARGET_H8300SX && reload_completed"
3560 "bclr/%j2\t%W1,%0"
3561 [(set_attr "cc" "none_0hit")
3562 (set_attr "length_table" "logicb")])
3564 (define_insn_and_split "*cmpcondbsetreg"
3565 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3566 (if_then_else:QI
3567 (match_operator
3568 1 "eqne_operator"
3569 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3570 (match_operand 3 "h8300_src_operand" "I,rQi")])
3571 (ior:QI
3572 (match_operand:QI 4 "bit_memory_operand" "0,0")
3573 (ashift:QI (const_int 1)
3574 (match_operand:QI 5 "register_operand" "r,r")))
3575 (match_dup 4)))]
3576 "TARGET_H8300SX"
3577 "#"
3578 "reload_completed"
3579 [(set (cc0) (match_dup 6))
3580 (set (match_dup 0)
3581 (if_then_else:QI
3582 (match_op_dup 1 [(cc0) (const_int 0)])
3583 (ior:QI (match_dup 4)
3584 (ashift:QI (const_int 1)
3585 (match_operand:QI 5 "register_operand" "r,r")))
3586 (match_dup 4)))]
3587 "
3588 {
3589 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3590 operands[6] = operands[2];
3591 else
3592 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3593 }"
3594 [(set_attr "cc" "set_znv,compare")])
3596 (define_insn "*condbsetreg"
3597 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3598 (if_then_else:QI
3599 (match_operator:QI 2 "eqne_operator"
3600 [(cc0) (const_int 0)])
3601 (ior:QI
3602 (match_operand:QI 3 "bit_memory_operand" "0")
3603 (ashift:QI (const_int 1)
3604 (match_operand:QI 1 "register_operand" "r")))
3605 (match_dup 3)))]
3606 "TARGET_H8300SX && reload_completed"
3607 "bset/%j2\t%R1,%0"
3608 [(set_attr "cc" "none_0hit")
3609 (set_attr "length_table" "logicb")])
3611 (define_insn_and_split "*cmpcondbclrreg"
3612 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3613 (if_then_else:QI
3614 (match_operator
3615 1 "eqne_operator"
3616 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3617 (match_operand 3 "h8300_src_operand" "I,rQi")])
3618 (and:QI
3619 (match_operand:QI 4 "bit_memory_operand" "0,0")
3620 (ashift:QI (const_int 1)
3621 (match_operand:QI 5 "register_operand" "r,r")))
3622 (match_dup 4)))]
3623 "TARGET_H8300SX"
3624 "#"
3625 "reload_completed"
3626 [(set (cc0) (match_dup 6))
3627 (set (match_dup 0)
3628 (if_then_else:QI
3629 (match_op_dup 1 [(cc0) (const_int 0)])
3630 (and:QI (match_dup 4)
3631 (ashift:QI (const_int 1)
3632 (match_operand:QI 5 "register_operand" "r,r")))
3633 (match_dup 4)))]
3634 "
3635 {
3636 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3637 operands[6] = operands[2];
3638 else
3639 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3640 }"
3641 [(set_attr "cc" "set_znv,compare")])
3643 (define_insn "*condbclrreg"
3644 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3645 (if_then_else:QI
3646 (match_operator:QI 2 "eqne_operator"
3647 [(cc0) (const_int 0)])
3648 (and:QI
3649 (match_operand:QI 3 "bit_memory_operand" "0")
3650 (ashift:QI (const_int 1)
3651 (match_operand:QI 1 "register_operand" "r")))
3652 (match_dup 3)))]
3653 "TARGET_H8300SX && reload_completed"
3654 "bclr/%j2\t%R1,%0"
3655 [(set_attr "cc" "none_0hit")
3656 (set_attr "length_table" "logicb")])
3658 \f
3659 ;; -----------------------------------------------------------------
3660 ;; COMBINE PATTERNS
3661 ;; -----------------------------------------------------------------
3663 ;; insv:SI
3665 (define_insn "*insv_si_1_n"
3666 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3667 (const_int 1)
3668 (match_operand:SI 1 "const_int_operand" "n"))
3669 (match_operand:SI 2 "register_operand" "r"))]
3670 "(TARGET_H8300H || TARGET_H8300S)
3671 && INTVAL (operands[1]) < 16"
3672 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3673 [(set_attr "length" "4")])
3675 (define_insn "*insv_si_1_n_lshiftrt"
3676 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3677 (const_int 1)
3678 (match_operand:SI 1 "const_int_operand" "n"))
3679 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3680 (match_operand:SI 3 "const_int_operand" "n")))]
3681 "(TARGET_H8300H || TARGET_H8300S)
3682 && INTVAL (operands[1]) < 16
3683 && INTVAL (operands[3]) < 16"
3684 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3685 [(set_attr "length" "4")])
3687 (define_insn "*insv_si_1_n_lshiftrt_16"
3688 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3689 (const_int 1)
3690 (match_operand:SI 1 "const_int_operand" "n"))
3691 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3692 (const_int 16)))]
3693 "(TARGET_H8300H || TARGET_H8300S)
3694 && INTVAL (operands[1]) < 16"
3695 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3696 [(set_attr "length" "6")])
3698 (define_insn "*insv_si_8_8"
3699 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3700 (const_int 8)
3701 (const_int 8))
3702 (match_operand:SI 1 "register_operand" "r"))]
3703 "TARGET_H8300H || TARGET_H8300S"
3704 "mov.b\\t%w1,%x0"
3705 [(set_attr "length" "2")])
3707 (define_insn "*insv_si_8_8_lshiftrt_8"
3708 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3709 (const_int 8)
3710 (const_int 8))
3711 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3712 (const_int 8)))]
3713 "TARGET_H8300H || TARGET_H8300S"
3714 "mov.b\\t%x1,%x0"
3715 [(set_attr "length" "2")])
3717 ;; extzv:SI
3719 (define_insn "*extzv_8_8"
3720 [(set (match_operand:SI 0 "register_operand" "=r,r")
3721 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3722 (const_int 8)
3723 (const_int 8)))]
3724 "TARGET_H8300H || TARGET_H8300S"
3725 "@
3726 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3727 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3728 [(set_attr "cc" "set_znv,clobber")
3729 (set_attr "length" "6,4")])
3731 (define_insn "*extzv_8_16"
3732 [(set (match_operand:SI 0 "register_operand" "=r")
3733 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3734 (const_int 8)
3735 (const_int 16)))]
3736 "TARGET_H8300H || TARGET_H8300S"
3737 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3738 [(set_attr "cc" "set_znv")
3739 (set_attr "length" "6")])
3741 (define_insn "*extzv_16_8"
3742 [(set (match_operand:SI 0 "register_operand" "=r")
3743 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3744 (const_int 16)
3745 (const_int 8)))
3746 (clobber (match_scratch:SI 2 "=&r"))]
3747 "TARGET_H8300H"
3748 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3749 [(set_attr "length" "8")
3750 (set_attr "cc" "set_znv")])
3752 ;; Extract the exponent of a float.
3754 (define_insn_and_split "*extzv_8_23"
3755 [(set (match_operand:SI 0 "register_operand" "=r")
3756 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3757 (const_int 8)
3758 (const_int 23)))]
3759 "(TARGET_H8300H || TARGET_H8300S)"
3760 "#"
3761 "&& reload_completed"
3762 [(parallel [(set (match_dup 0)
3763 (ashift:SI (match_dup 0)
3764 (const_int 1)))
3765 (clobber (scratch:QI))])
3766 (parallel [(set (match_dup 0)
3767 (lshiftrt:SI (match_dup 0)
3768 (const_int 24)))
3769 (clobber (scratch:QI))])]
3770 "")
3772 ;; and:SI
3774 ;; ((SImode) HImode) << 15
3776 (define_insn_and_split "*twoshifts_l16_r1"
3777 [(set (match_operand:SI 0 "register_operand" "=r")
3778 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3779 (const_int 15))
3780 (const_int 2147450880)))]
3781 "(TARGET_H8300H || TARGET_H8300S)"
3782 "#"
3783 "&& reload_completed"
3784 [(parallel [(set (match_dup 0)
3785 (ashift:SI (match_dup 0)
3786 (const_int 16)))
3787 (clobber (scratch:QI))])
3788 (parallel [(set (match_dup 0)
3789 (lshiftrt:SI (match_dup 0)
3790 (const_int 1)))
3791 (clobber (scratch:QI))])]
3792 "")
3794 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3796 (define_insn_and_split "*andsi3_ashift_n_lower"
3797 [(set (match_operand:SI 0 "register_operand" "=r,r")
3798 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3799 (match_operand:QI 2 "const_int_operand" "S,n"))
3800 (match_operand:SI 3 "const_int_operand" "n,n")))
3801 (clobber (match_scratch:QI 4 "=X,&r"))]
3802 "(TARGET_H8300H || TARGET_H8300S)
3803 && INTVAL (operands[2]) <= 15
3804 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3805 "#"
3806 "&& reload_completed"
3807 [(parallel [(set (match_dup 5)
3808 (ashift:HI (match_dup 5)
3809 (match_dup 2)))
3810 (clobber (match_dup 4))])
3811 (set (match_dup 0)
3812 (zero_extend:SI (match_dup 5)))]
3813 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3815 ;; Accept (A >> 30) & 2 and the like.
3817 (define_insn "*andsi3_lshiftrt_n_sb"
3818 [(set (match_operand:SI 0 "register_operand" "=r")
3819 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3820 (match_operand:SI 2 "const_int_operand" "n"))
3821 (match_operand:SI 3 "single_one_operand" "n")))]
3822 "(TARGET_H8300H || TARGET_H8300S)
3823 && exact_log2 (INTVAL (operands[3])) < 16
3824 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3825 "*
3826 {
3827 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3828 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3829 }"
3830 [(set_attr "length" "8")])
3832 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3833 [(set (match_operand:SI 0 "register_operand" "=r")
3834 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3835 (const_int 9))
3836 (const_int 4194304)))]
3837 "(TARGET_H8300H || TARGET_H8300S)"
3838 "#"
3839 "&& reload_completed"
3840 [(set (match_dup 0)
3841 (and:SI (lshiftrt:SI (match_dup 0)
3842 (const_int 25))
3843 (const_int 64)))
3844 (parallel [(set (match_dup 0)
3845 (ashift:SI (match_dup 0)
3846 (const_int 16)))
3847 (clobber (scratch:QI))])]
3848 "")
3850 ;; plus:SI
3852 (define_insn "*addsi3_upper"
3853 [(set (match_operand:SI 0 "register_operand" "=r")
3854 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3855 (const_int 65536))
3856 (match_operand:SI 2 "register_operand" "0")))]
3857 "TARGET_H8300H || TARGET_H8300S"
3858 "add.w\\t%f1,%e0"
3859 [(set_attr "length" "2")])
3861 (define_insn "*addsi3_lshiftrt_16_zexthi"
3862 [(set (match_operand:SI 0 "register_operand" "=r")
3863 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3864 (const_int 16))
3865 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3866 "TARGET_H8300H || TARGET_H8300S"
3867 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3868 [(set_attr "length" "6")])
3870 (define_insn_and_split "*addsi3_and_r_1"
3871 [(set (match_operand:SI 0 "register_operand" "=r")
3872 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3873 (const_int 1))
3874 (match_operand:SI 2 "register_operand" "0")))]
3875 "(TARGET_H8300H || TARGET_H8300S)"
3876 "#"
3877 "&& reload_completed"
3878 [(set (cc0)
3879 (zero_extract:SI (match_dup 1)
3880 (const_int 1)
3881 (const_int 0)))
3882 (set (pc)
3883 (if_then_else (eq (cc0)
3884 (const_int 0))
3885 (label_ref (match_dup 3))
3886 (pc)))
3887 (set (match_dup 2)
3888 (plus:SI (match_dup 2)
3889 (const_int 1)))
3890 (match_dup 3)]
3891 "operands[3] = gen_label_rtx ();")
3893 (define_insn_and_split "*addsi3_and_not_r_1"
3894 [(set (match_operand:SI 0 "register_operand" "=r")
3895 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3896 (const_int 1))
3897 (match_operand:SI 2 "register_operand" "0")))]
3898 "(TARGET_H8300H || TARGET_H8300S)"
3899 "#"
3900 "&& reload_completed"
3901 [(set (cc0)
3902 (zero_extract:SI (match_dup 1)
3903 (const_int 1)
3904 (const_int 0)))
3905 (set (pc)
3906 (if_then_else (ne (cc0)
3907 (const_int 0))
3908 (label_ref (match_dup 3))
3909 (pc)))
3910 (set (match_dup 2)
3911 (plus:SI (match_dup 2)
3912 (const_int 1)))
3913 (match_dup 3)]
3914 "operands[3] = gen_label_rtx ();")
3916 ;; [ix]or:HI
3918 (define_insn "*ixorhi3_zext"
3919 [(set (match_operand:HI 0 "register_operand" "=r")
3920 (match_operator:HI 1 "iorxor_operator"
3921 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3922 (match_operand:HI 3 "register_operand" "0")]))]
3923 ""
3924 "%c1.b\\t%X2,%s0"
3925 [(set_attr "length" "2")])
3927 ;; [ix]or:SI
3929 (define_insn "*ixorsi3_zext_qi"
3930 [(set (match_operand:SI 0 "register_operand" "=r")
3931 (match_operator:SI 1 "iorxor_operator"
3932 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3933 (match_operand:SI 3 "register_operand" "0")]))]
3934 ""
3935 "%c1.b\\t%X2,%w0"
3936 [(set_attr "length" "2")])
3938 (define_insn "*ixorsi3_zext_hi"
3939 [(set (match_operand:SI 0 "register_operand" "=r")
3940 (match_operator:SI 1 "iorxor_operator"
3941 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3942 (match_operand:SI 3 "register_operand" "0")]))]
3943 "TARGET_H8300H || TARGET_H8300S"
3944 "%c1.w\\t%T2,%f0"
3945 [(set_attr "length" "2")])
3947 (define_insn "*ixorsi3_ashift_16"
3948 [(set (match_operand:SI 0 "register_operand" "=r")
3949 (match_operator:SI 1 "iorxor_operator"
3950 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3951 (const_int 16))
3952 (match_operand:SI 3 "register_operand" "0")]))]
3953 "TARGET_H8300H || TARGET_H8300S"
3954 "%c1.w\\t%f2,%e0"
3955 [(set_attr "length" "2")])
3957 (define_insn "*ixorsi3_lshiftrt_16"
3958 [(set (match_operand:SI 0 "register_operand" "=r")
3959 (match_operator:SI 1 "iorxor_operator"
3960 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3961 (const_int 16))
3962 (match_operand:SI 3 "register_operand" "0")]))]
3963 "TARGET_H8300H || TARGET_H8300S"
3964 "%c1.w\\t%e2,%f0"
3965 [(set_attr "length" "2")])
3967 ;; ior:HI
3969 (define_insn "*iorhi3_ashift_8"
3970 [(set (match_operand:HI 0 "register_operand" "=r")
3971 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3972 (const_int 8))
3973 (match_operand:HI 2 "register_operand" "0")))]
3974 ""
3975 "or.b\\t%s1,%t0"
3976 [(set_attr "length" "2")])
3978 (define_insn "*iorhi3_lshiftrt_8"
3979 [(set (match_operand:HI 0 "register_operand" "=r")
3980 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3981 (const_int 8))
3982 (match_operand:HI 2 "register_operand" "0")))]
3983 ""
3984 "or.b\\t%t1,%s0"
3985 [(set_attr "length" "2")])
3987 (define_insn "*iorhi3_two_qi"
3988 [(set (match_operand:HI 0 "register_operand" "=r")
3989 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3990 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3991 (const_int 8))))]
3992 ""
3993 "mov.b\\t%s2,%t0"
3994 [(set_attr "length" "2")])
3996 (define_insn "*iorhi3_two_qi_mem"
3997 [(set (match_operand:HI 0 "register_operand" "=&r")
3998 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3999 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4000 (const_int 8))))]
4001 ""
4002 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4003 [(set_attr "length" "16")])
4005 (define_split
4006 [(set (match_operand:HI 0 "register_operand" "")
4007 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4008 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4009 (const_int 8))))]
4010 "(TARGET_H8300H || TARGET_H8300S)
4011 && reload_completed
4012 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4013 [(set (match_dup 0)
4014 (match_dup 3))]
4015 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
4017 ;; ior:SI
4019 (define_insn "*iorsi3_two_hi"
4020 [(set (match_operand:SI 0 "register_operand" "=r")
4021 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4022 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4023 (const_int 16))))]
4024 "TARGET_H8300H || TARGET_H8300S"
4025 "mov.w\\t%f2,%e0"
4026 [(set_attr "length" "2")])
4028 (define_insn_and_split "*iorsi3_two_qi_zext"
4029 [(set (match_operand:SI 0 "register_operand" "=&r")
4030 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4032 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4033 (const_int 8))
4034 (const_int 65280))))]
4035 "(TARGET_H8300H || TARGET_H8300S)"
4036 "#"
4037 "&& reload_completed"
4038 [(set (match_dup 3)
4039 (ior:HI (zero_extend:HI (match_dup 1))
4040 (ashift:HI (subreg:HI (match_dup 2) 0)
4041 (const_int 8))))
4042 (set (match_dup 0)
4043 (zero_extend:SI (match_dup 3)))]
4044 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4046 (define_insn "*iorsi3_e2f"
4047 [(set (match_operand:SI 0 "register_operand" "=r")
4048 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4049 (const_int -65536))
4050 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4051 (const_int 16))))]
4052 "TARGET_H8300H || TARGET_H8300S"
4053 "mov.w\\t%e2,%f0"
4054 [(set_attr "length" "2")])
4056 (define_insn_and_split "*iorsi3_two_qi_sext"
4057 [(set (match_operand:SI 0 "register_operand" "=r")
4058 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4059 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4060 (const_int 8))))]
4061 "(TARGET_H8300H || TARGET_H8300S)"
4062 "#"
4063 "&& reload_completed"
4064 [(set (match_dup 3)
4065 (ior:HI (zero_extend:HI (match_dup 1))
4066 (ashift:HI (match_dup 4)
4067 (const_int 8))))
4068 (set (match_dup 0)
4069 (sign_extend:SI (match_dup 3)))]
4070 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4071 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4073 (define_insn "*iorsi3_w"
4074 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4075 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4076 (const_int -256))
4077 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4078 "TARGET_H8300H || TARGET_H8300S"
4079 "mov.b\\t%X2,%w0"
4080 [(set_attr "length" "2,8")])
4082 (define_insn "*iorsi3_ashift_31"
4083 [(set (match_operand:SI 0 "register_operand" "=&r")
4084 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4085 (const_int 31))
4086 (match_operand:SI 2 "register_operand" "0")))]
4087 "TARGET_H8300H || TARGET_H8300S"
4088 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4089 [(set_attr "length" "6")
4090 (set_attr "cc" "set_znv")])
4092 (define_insn "*iorsi3_and_ashift"
4093 [(set (match_operand:SI 0 "register_operand" "=r")
4094 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4095 (match_operand:SI 2 "const_int_operand" "n"))
4096 (match_operand:SI 3 "single_one_operand" "n"))
4097 (match_operand:SI 4 "register_operand" "0")))]
4098 "(TARGET_H8300H || TARGET_H8300S)
4099 && (INTVAL (operands[3]) & ~0xffff) == 0"
4100 "*
4101 {
4102 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4103 - INTVAL (operands[2]));
4104 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4105 operands[2] = srcpos;
4106 operands[3] = dstpos;
4107 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4108 }"
4109 [(set_attr "length" "6")])
4111 (define_insn "*iorsi3_and_lshiftrt"
4112 [(set (match_operand:SI 0 "register_operand" "=r")
4113 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4114 (match_operand:SI 2 "const_int_operand" "n"))
4115 (match_operand:SI 3 "single_one_operand" "n"))
4116 (match_operand:SI 4 "register_operand" "0")))]
4117 "(TARGET_H8300H || TARGET_H8300S)
4118 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4119 "*
4120 {
4121 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4122 + INTVAL (operands[2]));
4123 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4124 operands[2] = srcpos;
4125 operands[3] = dstpos;
4126 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4127 }"
4128 [(set_attr "length" "6")])
4130 (define_insn "*iorsi3_zero_extract"
4131 [(set (match_operand:SI 0 "register_operand" "=r")
4132 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4133 (const_int 1)
4134 (match_operand:SI 2 "const_int_operand" "n"))
4135 (match_operand:SI 3 "register_operand" "0")))]
4136 "(TARGET_H8300H || TARGET_H8300S)
4137 && INTVAL (operands[2]) < 16"
4138 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4139 [(set_attr "length" "6")])
4141 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4142 [(set (match_operand:SI 0 "register_operand" "=r")
4143 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4144 (const_int 30))
4145 (const_int 2))
4146 (match_operand:SI 2 "register_operand" "0")))]
4147 "(TARGET_H8300H || TARGET_H8300S)"
4148 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4149 [(set_attr "length" "8")])
4151 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4152 [(set (match_operand:SI 0 "register_operand" "=r")
4153 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4154 (const_int 9))
4155 (const_int 4194304))
4156 (match_operand:SI 2 "register_operand" "0")))
4157 (clobber (match_scratch:HI 3 "=&r"))]
4158 "(TARGET_H8300H || TARGET_H8300S)"
4159 "*
4160 {
4161 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4162 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4163 else
4164 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4165 }"
4166 [(set_attr "length" "10")])
4168 ;; Used to OR the exponent of a float.
4170 (define_insn "*iorsi3_shift"
4171 [(set (match_operand:SI 0 "register_operand" "=r")
4172 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4173 (const_int 23))
4174 (match_operand:SI 2 "register_operand" "0")))
4175 (clobber (match_scratch:SI 3 "=&r"))]
4176 "TARGET_H8300H || TARGET_H8300S"
4177 "#")
4179 (define_split
4180 [(set (match_operand:SI 0 "register_operand" "")
4181 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4182 (const_int 23))
4183 (match_dup 0)))
4184 (clobber (match_operand:SI 2 "register_operand" ""))]
4185 "(TARGET_H8300H || TARGET_H8300S)
4186 && flow2_completed
4187 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4188 && REGNO (operands[0]) != REGNO (operands[1])"
4189 [(parallel [(set (match_dup 3)
4190 (ashift:HI (match_dup 3)
4191 (const_int 7)))
4192 (clobber (scratch:QI))])
4193 (set (match_dup 0)
4194 (ior:SI (ashift:SI (match_dup 1)
4195 (const_int 16))
4196 (match_dup 0)))]
4197 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4199 (define_split
4200 [(set (match_operand:SI 0 "register_operand" "")
4201 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4202 (const_int 23))
4203 (match_dup 0)))
4204 (clobber (match_operand:SI 2 "register_operand" ""))]
4205 "(TARGET_H8300H || TARGET_H8300S)
4206 && flow2_completed
4207 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4208 && REGNO (operands[0]) != REGNO (operands[1]))"
4209 [(set (match_dup 2)
4210 (match_dup 1))
4211 (parallel [(set (match_dup 3)
4212 (ashift:HI (match_dup 3)
4213 (const_int 7)))
4214 (clobber (scratch:QI))])
4215 (set (match_dup 0)
4216 (ior:SI (ashift:SI (match_dup 2)
4217 (const_int 16))
4218 (match_dup 0)))]
4219 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4221 (define_insn "*iorsi2_and_1_lshiftrt_1"
4222 [(set (match_operand:SI 0 "register_operand" "=r")
4223 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4224 (const_int 1))
4225 (lshiftrt:SI (match_dup 1)
4226 (const_int 1))))]
4227 "TARGET_H8300H || TARGET_H8300S"
4228 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4229 [(set_attr "length" "6")])
4231 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4232 [(set (match_operand:SI 0 "register_operand" "=r")
4233 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4234 (const_int 16))
4235 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4236 (const_int 24))))]
4237 "(TARGET_H8300H || TARGET_H8300S)"
4238 "#"
4239 "&& reload_completed"
4240 [(set (match_dup 3)
4241 (ior:HI (ashift:HI (match_dup 4)
4242 (const_int 8))
4243 (match_dup 3)))
4244 (parallel [(set (match_dup 0)
4245 (ashift:SI (match_dup 0)
4246 (const_int 16)))
4247 (clobber (scratch:QI))])]
4248 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4249 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4251 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4252 [(set (match_operand:SI 0 "register_operand" "=&r")
4253 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4254 (const_int 16))
4255 (const_int 16711680))
4256 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4257 (const_int 24))))]
4258 "(TARGET_H8300H || TARGET_H8300S)"
4259 "#"
4260 "&& reload_completed"
4261 [(set (match_dup 3)
4262 (ior:HI (zero_extend:HI (match_dup 1))
4263 (ashift:HI (subreg:HI (match_dup 2) 0)
4264 (const_int 8))))
4265 (parallel [(set (match_dup 0)
4266 (ashift:SI (match_dup 0)
4267 (const_int 16)))
4268 (clobber (scratch:QI))])]
4269 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4271 ;; Used to add the exponent of a float.
4273 (define_insn "*addsi3_shift"
4274 [(set (match_operand:SI 0 "register_operand" "=r")
4275 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4276 (const_int 8388608))
4277 (match_operand:SI 2 "register_operand" "0")))
4278 (clobber (match_scratch:SI 3 "=&r"))]
4279 "TARGET_H8300H || TARGET_H8300S"
4280 "#")
4282 (define_split
4283 [(set (match_operand:SI 0 "register_operand" "")
4284 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4285 (const_int 8388608))
4286 (match_dup 0)))
4287 (clobber (match_operand:SI 2 "register_operand" ""))]
4288 "(TARGET_H8300H || TARGET_H8300S)
4289 && flow2_completed
4290 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4291 && REGNO (operands[0]) != REGNO (operands[1])"
4292 [(parallel [(set (match_dup 3)
4293 (ashift:HI (match_dup 3)
4294 (const_int 7)))
4295 (clobber (scratch:QI))])
4296 (set (match_dup 0)
4297 (plus:SI (mult:SI (match_dup 1)
4298 (const_int 65536))
4299 (match_dup 0)))]
4300 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4302 (define_split
4303 [(set (match_operand:SI 0 "register_operand" "")
4304 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4305 (const_int 8388608))
4306 (match_dup 0)))
4307 (clobber (match_operand:SI 2 "register_operand" ""))]
4308 "(TARGET_H8300H || TARGET_H8300S)
4309 && flow2_completed
4310 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4311 && REGNO (operands[0]) != REGNO (operands[1]))"
4312 [(set (match_dup 2)
4313 (match_dup 1))
4314 (parallel [(set (match_dup 3)
4315 (ashift:HI (match_dup 3)
4316 (const_int 7)))
4317 (clobber (scratch:QI))])
4318 (set (match_dup 0)
4319 (plus:SI (mult:SI (match_dup 2)
4320 (const_int 65536))
4321 (match_dup 0)))]
4322 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4324 ;; ashift:SI
4326 (define_insn_and_split "*ashiftsi_sextqi_7"
4327 [(set (match_operand:SI 0 "register_operand" "=r")
4328 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4329 (const_int 7)))]
4330 "(TARGET_H8300H || TARGET_H8300S)"
4331 "#"
4332 "&& reload_completed"
4333 [(parallel [(set (match_dup 2)
4334 (ashift:HI (match_dup 2)
4335 (const_int 8)))
4336 (clobber (scratch:QI))])
4337 (set (match_dup 0)
4338 (sign_extend:SI (match_dup 2)))
4339 (parallel [(set (match_dup 0)
4340 (ashiftrt:SI (match_dup 0)
4341 (const_int 1)))
4342 (clobber (scratch:QI))])]
4343 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4345 ;; Storing a part of HImode to QImode.
4347 (define_insn ""
4348 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4349 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4350 (const_int 8)) 1))]
4351 ""
4352 "mov.b\\t%t1,%R0"
4353 [(set_attr "cc" "set_znv")
4354 (set_attr "length" "8")])
4356 ;; Storing a part of SImode to QImode.
4358 (define_insn ""
4359 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4360 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4361 (const_int 8)) 3))]
4362 ""
4363 "mov.b\\t%x1,%R0"
4364 [(set_attr "cc" "set_znv")
4365 (set_attr "length" "8")])
4367 (define_insn ""
4368 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4369 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4370 (const_int 16)) 3))
4371 (clobber (match_scratch:SI 2 "=&r"))]
4372 "TARGET_H8300H || TARGET_H8300S"
4373 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4374 [(set_attr "cc" "set_znv")
4375 (set_attr "length" "10")])
4377 (define_insn ""
4378 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4379 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4380 (const_int 24)) 3))
4381 (clobber (match_scratch:SI 2 "=&r"))]
4382 "TARGET_H8300H || TARGET_H8300S"
4383 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4384 [(set_attr "cc" "set_znv")
4385 (set_attr "length" "10")])
4387 (define_insn_and_split ""
4388 [(set (pc)
4389 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4390 (const_int 1)
4391 (const_int 7))
4392 (const_int 0))
4393 (label_ref (match_operand 1 "" ""))
4394 (pc)))]
4395 ""
4396 "#"
4397 ""
4398 [(set (cc0)
4399 (match_dup 0))
4400 (set (pc)
4401 (if_then_else (ge (cc0)
4402 (const_int 0))
4403 (label_ref (match_dup 1))
4404 (pc)))]
4405 "")
4407 (define_insn_and_split ""
4408 [(set (pc)
4409 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4410 (const_int 1)
4411 (const_int 7))
4412 (const_int 0))
4413 (label_ref (match_operand 1 "" ""))
4414 (pc)))]
4415 ""
4416 "#"
4417 ""
4418 [(set (cc0)
4419 (match_dup 0))
4420 (set (pc)
4421 (if_then_else (lt (cc0)
4422 (const_int 0))
4423 (label_ref (match_dup 1))
4424 (pc)))]
4425 "")
4426 \f
4427 ;; -----------------------------------------------------------------
4428 ;; PEEPHOLE PATTERNS
4429 ;; -----------------------------------------------------------------
4431 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4433 (define_peephole2
4434 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4435 (lshiftrt:HI (match_dup 0)
4436 (match_operand:HI 1 "const_int_operand" "")))
4437 (clobber (match_operand:HI 2 "" ""))])
4438 (set (match_dup 0)
4439 (and:HI (match_dup 0)
4440 (match_operand:HI 3 "const_int_operand" "")))]
4441 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4442 [(set (match_dup 0)
4443 (and:HI (match_dup 0)
4444 (const_int 255)))
4445 (parallel
4446 [(set (match_dup 0)
4447 (lshiftrt:HI (match_dup 0)
4448 (match_dup 1)))
4449 (clobber (match_dup 2))])]
4450 "")
4452 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4454 (define_peephole2
4455 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4456 (ashift:HI (match_dup 0)
4457 (match_operand:HI 1 "const_int_operand" "")))
4458 (clobber (match_operand:HI 2 "" ""))])
4459 (set (match_dup 0)
4460 (and:HI (match_dup 0)
4461 (match_operand:HI 3 "const_int_operand" "")))]
4462 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4463 [(set (match_dup 0)
4464 (and:HI (match_dup 0)
4465 (const_int 255)))
4466 (parallel
4467 [(set (match_dup 0)
4468 (ashift:HI (match_dup 0)
4469 (match_dup 1)))
4470 (clobber (match_dup 2))])]
4471 "")
4473 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4475 (define_peephole2
4476 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4477 (lshiftrt:SI (match_dup 0)
4478 (match_operand:SI 1 "const_int_operand" "")))
4479 (clobber (match_operand:SI 2 "" ""))])
4480 (set (match_dup 0)
4481 (and:SI (match_dup 0)
4482 (match_operand:SI 3 "const_int_operand" "")))]
4483 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4484 [(set (match_dup 0)
4485 (and:SI (match_dup 0)
4486 (const_int 255)))
4487 (parallel
4488 [(set (match_dup 0)
4489 (lshiftrt:SI (match_dup 0)
4490 (match_dup 1)))
4491 (clobber (match_dup 2))])]
4492 "")
4494 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4496 (define_peephole2
4497 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4498 (ashift:SI (match_dup 0)
4499 (match_operand:SI 1 "const_int_operand" "")))
4500 (clobber (match_operand:SI 2 "" ""))])
4501 (set (match_dup 0)
4502 (and:SI (match_dup 0)
4503 (match_operand:SI 3 "const_int_operand" "")))]
4504 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4505 [(set (match_dup 0)
4506 (and:SI (match_dup 0)
4507 (const_int 255)))
4508 (parallel
4509 [(set (match_dup 0)
4510 (ashift:SI (match_dup 0)
4511 (match_dup 1)))
4512 (clobber (match_dup 2))])]
4513 "")
4515 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4517 (define_peephole2
4518 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4519 (lshiftrt:SI (match_dup 0)
4520 (match_operand:SI 1 "const_int_operand" "")))
4521 (clobber (match_operand:SI 2 "" ""))])
4522 (set (match_dup 0)
4523 (and:SI (match_dup 0)
4524 (match_operand:SI 3 "const_int_operand" "")))]
4525 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4526 [(set (match_dup 0)
4527 (and:SI (match_dup 0)
4528 (const_int 65535)))
4529 (parallel
4530 [(set (match_dup 0)
4531 (lshiftrt:SI (match_dup 0)
4532 (match_dup 1)))
4533 (clobber (match_dup 2))])]
4534 "")
4536 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4538 (define_peephole2
4539 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4540 (ashift:SI (match_dup 0)
4541 (match_operand:SI 1 "const_int_operand" "")))
4542 (clobber (match_operand:SI 2 "" ""))])
4543 (set (match_dup 0)
4544 (and:SI (match_dup 0)
4545 (match_operand:SI 3 "const_int_operand" "")))]
4546 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4547 [(set (match_dup 0)
4548 (and:SI (match_dup 0)
4549 (const_int 65535)))
4550 (parallel
4551 [(set (match_dup 0)
4552 (ashift:SI (match_dup 0)
4553 (match_dup 1)))
4554 (clobber (match_dup 2))])]
4555 "")
4557 ;; Convert a QImode push into an SImode push so that the
4558 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4560 (define_peephole2
4561 [(parallel [(set (reg:SI SP_REG)
4562 (plus:SI (reg:SI SP_REG) (const_int -4)))
4563 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4564 (match_operand:QI 0 "register_operand" ""))])]
4565 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4566 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4567 (match_dup 0))]
4568 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4570 (define_peephole2
4571 [(parallel [(set (reg:HI SP_REG)
4572 (plus:HI (reg:HI SP_REG) (const_int -4)))
4573 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4574 (match_operand:QI 0 "register_operand" ""))])]
4575 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4576 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4577 (match_dup 0))]
4578 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4580 ;; Convert a HImode push into an SImode push so that the
4581 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4583 (define_peephole2
4584 [(parallel [(set (reg:SI SP_REG)
4585 (plus:SI (reg:SI SP_REG) (const_int -4)))
4586 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4587 (match_operand:HI 0 "register_operand" ""))])]
4588 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4589 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4590 (match_dup 0))]
4591 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4593 (define_peephole2
4594 [(parallel [(set (reg:HI SP_REG)
4595 (plus:HI (reg:HI SP_REG) (const_int -4)))
4596 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4597 (match_operand:HI 0 "register_operand" ""))])]
4598 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4599 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4600 (match_dup 0))]
4601 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4603 ;; Cram four pushes into stm.l.
4605 (define_peephole2
4606 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4607 (match_operand:SI 0 "register_operand" ""))
4608 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4609 (match_operand:SI 1 "register_operand" ""))
4610 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4611 (match_operand:SI 2 "register_operand" ""))
4612 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4613 (match_operand:SI 3 "register_operand" ""))]
4614 "TARGET_H8300S && !TARGET_NORMAL_MODE
4615 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4616 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4617 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4618 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4619 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4620 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4621 (match_dup 0))
4622 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4623 (match_dup 1))
4624 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4625 (match_dup 2))
4626 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4627 (match_dup 3))
4628 (set (reg:SI SP_REG)
4629 (plus:SI (reg:SI SP_REG)
4630 (const_int -16)))])]
4631 "")
4633 (define_peephole2
4634 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4635 (match_operand:SI 0 "register_operand" ""))
4636 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4637 (match_operand:SI 1 "register_operand" ""))
4638 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4639 (match_operand:SI 2 "register_operand" ""))
4640 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4641 (match_operand:SI 3 "register_operand" ""))]
4642 "TARGET_H8300S && TARGET_NORMAL_MODE
4643 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4644 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4645 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4646 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4647 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4648 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4649 (match_dup 0))
4650 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4651 (match_dup 1))
4652 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4653 (match_dup 2))
4654 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4655 (match_dup 3))
4656 (set (reg:HI SP_REG)
4657 (plus:HI (reg:HI SP_REG)
4658 (const_int -16)))])]
4659 "")
4661 ;; Cram three pushes into stm.l.
4663 (define_peephole2
4664 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4665 (match_operand:SI 0 "register_operand" ""))
4666 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4667 (match_operand:SI 1 "register_operand" ""))
4668 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4669 (match_operand:SI 2 "register_operand" ""))]
4670 "TARGET_H8300S && !TARGET_NORMAL_MODE
4671 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4672 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4673 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4674 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4675 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4676 (match_dup 0))
4677 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4678 (match_dup 1))
4679 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4680 (match_dup 2))
4681 (set (reg:SI SP_REG)
4682 (plus:SI (reg:SI SP_REG)
4683 (const_int -12)))])]
4684 "")
4686 (define_peephole2
4687 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4688 (match_operand:SI 0 "register_operand" ""))
4689 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4690 (match_operand:SI 1 "register_operand" ""))
4691 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4692 (match_operand:SI 2 "register_operand" ""))]
4693 "TARGET_H8300S && TARGET_NORMAL_MODE
4694 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4695 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4696 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4697 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4698 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4699 (match_dup 0))
4700 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4701 (match_dup 1))
4702 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4703 (match_dup 2))
4704 (set (reg:HI SP_REG)
4705 (plus:HI (reg:HI SP_REG)
4706 (const_int -12)))])]
4707 "")
4709 ;; Cram two pushes into stm.l.
4711 (define_peephole2
4712 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4713 (match_operand:SI 0 "register_operand" ""))
4714 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4715 (match_operand:SI 1 "register_operand" ""))]
4716 "TARGET_H8300S && !TARGET_NORMAL_MODE
4717 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4718 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4719 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4720 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4721 (match_dup 0))
4722 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4723 (match_dup 1))
4724 (set (reg:SI SP_REG)
4725 (plus:SI (reg:SI SP_REG)
4726 (const_int -8)))])]
4727 "")
4729 (define_peephole2
4730 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4731 (match_operand:SI 0 "register_operand" ""))
4732 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4733 (match_operand:SI 1 "register_operand" ""))]
4734 "TARGET_H8300S && TARGET_NORMAL_MODE
4735 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4736 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4737 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4738 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4739 (match_dup 0))
4740 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4741 (match_dup 1))
4742 (set (reg:HI SP_REG)
4743 (plus:HI (reg:HI SP_REG)
4744 (const_int -8)))])]
4745 "")
4747 ;; Turn
4748 ;;
4749 ;; mov.w #2,r0
4750 ;; add.w r7,r0 (6 bytes)
4751 ;;
4752 ;; into
4753 ;;
4754 ;; mov.w r7,r0
4755 ;; adds #2,r0 (4 bytes)
4757 (define_peephole2
4758 [(set (match_operand:HI 0 "register_operand" "")
4759 (match_operand:HI 1 "const_int_operand" ""))
4760 (set (match_dup 0)
4761 (plus:HI (match_dup 0)
4762 (match_operand:HI 2 "register_operand" "")))]
4763 "REG_P (operands[0]) && REG_P (operands[2])
4764 && REGNO (operands[0]) != REGNO (operands[2])
4765 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4766 || CONST_OK_FOR_L (INTVAL (operands[1]))
4767 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4768 [(set (match_dup 0)
4769 (match_dup 2))
4770 (set (match_dup 0)
4771 (plus:HI (match_dup 0)
4772 (match_dup 1)))]
4773 "")
4775 ;; Turn
4776 ;;
4777 ;; sub.l er0,er0
4778 ;; add.b #4,r0l
4779 ;; add.l er7,er0 (6 bytes)
4780 ;;
4781 ;; into
4782 ;;
4783 ;; mov.l er7,er0
4784 ;; adds #4,er0 (4 bytes)
4786 (define_peephole2
4787 [(set (match_operand:SI 0 "register_operand" "")
4788 (match_operand:SI 1 "const_int_operand" ""))
4789 (set (match_dup 0)
4790 (plus:SI (match_dup 0)
4791 (match_operand:SI 2 "register_operand" "")))]
4792 "(TARGET_H8300H || TARGET_H8300S)
4793 && REG_P (operands[0]) && REG_P (operands[2])
4794 && REGNO (operands[0]) != REGNO (operands[2])
4795 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4796 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4797 [(set (match_dup 0)
4798 (match_dup 2))
4799 (set (match_dup 0)
4800 (plus:SI (match_dup 0)
4801 (match_dup 1)))]
4802 "")
4804 ;; Turn
4805 ;;
4806 ;; mov.l er7,er0
4807 ;; add.l #10,er0 (takes 8 bytes)
4808 ;;
4809 ;; into
4810 ;;
4811 ;; sub.l er0,er0
4812 ;; add.b #10,r0l
4813 ;; add.l er7,er0 (takes 6 bytes)
4815 (define_peephole2
4816 [(set (match_operand:SI 0 "register_operand" "")
4817 (match_operand:SI 1 "register_operand" ""))
4818 (set (match_dup 0)
4819 (plus:SI (match_dup 0)
4820 (match_operand:SI 2 "const_int_operand" "")))]
4821 "(TARGET_H8300H || TARGET_H8300S)
4822 && REG_P (operands[0]) && REG_P (operands[1])
4823 && REGNO (operands[0]) != REGNO (operands[1])
4824 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4825 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4826 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4827 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4828 || INTVAL (operands[2]) == 0xffff
4829 || INTVAL (operands[2]) == 0xfffe)"
4830 [(set (match_dup 0)
4831 (match_dup 2))
4832 (set (match_dup 0)
4833 (plus:SI (match_dup 0)
4834 (match_dup 1)))]
4835 "")
4837 ;; Turn
4838 ;;
4839 ;; subs #1,er4
4840 ;; mov.w r4,r4
4841 ;; bne .L2028
4842 ;;
4843 ;; into
4844 ;;
4845 ;; dec.w #1,r4
4846 ;; bne .L2028
4848 (define_peephole2
4849 [(set (match_operand:HI 0 "register_operand" "")
4850 (plus:HI (match_dup 0)
4851 (match_operand 1 "incdec_operand" "")))
4852 (set (cc0)
4853 (match_dup 0))
4854 (set (pc)
4855 (if_then_else (match_operator 3 "eqne_operator"
4856 [(cc0) (const_int 0)])
4857 (label_ref (match_operand 2 "" ""))
4858 (pc)))]
4859 "TARGET_H8300H || TARGET_H8300S"
4860 [(set (match_operand:HI 0 "register_operand" "")
4861 (unspec:HI [(match_dup 0)
4862 (match_dup 1)]
4863 UNSPEC_INCDEC))
4864 (set (cc0)
4865 (match_dup 0))
4866 (set (pc)
4867 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4868 (label_ref (match_dup 2))
4869 (pc)))]
4870 "")
4872 ;; The SImode version of the previous pattern.
4874 (define_peephole2
4875 [(set (match_operand:SI 0 "register_operand" "")
4876 (plus:SI (match_dup 0)
4877 (match_operand 1 "incdec_operand" "")))
4878 (set (cc0)
4879 (match_dup 0))
4880 (set (pc)
4881 (if_then_else (match_operator 3 "eqne_operator"
4882 [(cc0) (const_int 0)])
4883 (label_ref (match_operand 2 "" ""))
4884 (pc)))]
4885 "TARGET_H8300H || TARGET_H8300S"
4886 [(set (match_operand:SI 0 "register_operand" "")
4887 (unspec:SI [(match_dup 0)
4888 (match_dup 1)]
4889 UNSPEC_INCDEC))
4890 (set (cc0)
4891 (match_dup 0))
4892 (set (pc)
4893 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4894 (label_ref (match_dup 2))
4895 (pc)))]
4896 "")
4898 (define_peephole2
4899 [(parallel [(set (cc0)
4900 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4901 (const_int 1)
4902 (const_int 7)))
4903 (clobber (scratch:QI))])
4904 (set (pc)
4905 (if_then_else (match_operator 1 "eqne_operator"
4906 [(cc0) (const_int 0)])
4907 (label_ref (match_operand 2 "" ""))
4908 (pc)))]
4909 "(TARGET_H8300H || TARGET_H8300S)"
4910 [(set (cc0)
4911 (match_dup 0))
4912 (set (pc)
4913 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4914 (label_ref (match_dup 2))
4915 (pc)))]
4916 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4917 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4918 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4920 ;; The next three peephole2's will try to transform
4921 ;;
4922 ;; mov.b A,r0l (or mov.l A,er0)
4923 ;; and.l #CST,er0
4924 ;;
4925 ;; into
4926 ;;
4927 ;; sub.l er0
4928 ;; mov.b A,r0l
4929 ;; and.b #CST,r0l (if CST is not 255)
4931 (define_peephole2
4932 [(set (match_operand:QI 0 "register_operand" "")
4933 (match_operand:QI 1 "general_operand" ""))
4934 (set (match_operand:SI 2 "register_operand" "")
4935 (and:SI (match_dup 2)
4936 (const_int 255)))]
4937 "(TARGET_H8300H || TARGET_H8300S)
4938 && !reg_overlap_mentioned_p (operands[2], operands[1])
4939 && REGNO (operands[0]) == REGNO (operands[2])"
4940 [(set (match_dup 2)
4941 (const_int 0))
4942 (set (strict_low_part (match_dup 0))
4943 (match_dup 1))]
4944 "")
4946 (define_peephole2
4947 [(set (match_operand:SI 0 "register_operand" "")
4948 (match_operand:SI 1 "general_operand" ""))
4949 (set (match_dup 0)
4950 (and:SI (match_dup 0)
4951 (const_int 255)))]
4952 "(TARGET_H8300H || TARGET_H8300S)
4953 && !reg_overlap_mentioned_p (operands[0], operands[1])
4954 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4955 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4956 [(set (match_dup 0)
4957 (const_int 0))
4958 (set (strict_low_part (match_dup 2))
4959 (match_dup 3))]
4960 "operands[2] = gen_lowpart (QImode, operands[0]);
4961 operands[3] = gen_lowpart (QImode, operands[1]);")
4963 (define_peephole2
4964 [(set (match_operand 0 "register_operand" "")
4965 (match_operand 1 "general_operand" ""))
4966 (set (match_operand:SI 2 "register_operand" "")
4967 (and:SI (match_dup 2)
4968 (match_operand:SI 3 "const_int_qi_operand" "")))]
4969 "(TARGET_H8300H || TARGET_H8300S)
4970 && (GET_MODE (operands[0]) == QImode
4971 || GET_MODE (operands[0]) == HImode
4972 || GET_MODE (operands[0]) == SImode)
4973 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4974 && REGNO (operands[0]) == REGNO (operands[2])
4975 && !reg_overlap_mentioned_p (operands[2], operands[1])
4976 && !(GET_MODE (operands[1]) != QImode
4977 && GET_CODE (operands[1]) == MEM
4978 && !offsettable_memref_p (operands[1]))
4979 && !(GET_MODE (operands[1]) != QImode
4980 && GET_CODE (operands[1]) == MEM
4981 && MEM_VOLATILE_P (operands[1]))"
4982 [(set (match_dup 2)
4983 (const_int 0))
4984 (set (strict_low_part (match_dup 4))
4985 (match_dup 5))
4986 (set (match_dup 2)
4987 (and:SI (match_dup 2)
4988 (match_dup 6)))]
4989 "operands[4] = gen_lowpart (QImode, operands[0]);
4990 operands[5] = gen_lowpart (QImode, operands[1]);
4991 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4993 (define_peephole2
4994 [(set (match_operand:SI 0 "register_operand" "")
4995 (match_operand:SI 1 "register_operand" ""))
4996 (set (match_dup 0)
4997 (and:SI (match_dup 0)
4998 (const_int 65280)))]
4999 "(TARGET_H8300H || TARGET_H8300S)
5000 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5001 [(set (match_dup 0)
5002 (const_int 0))
5003 (set (zero_extract:SI (match_dup 0)
5004 (const_int 8)
5005 (const_int 8))
5006 (lshiftrt:SI (match_dup 1)
5007 (const_int 8)))]
5008 "")
5010 ;; If a load of mem:SI is followed by an AND that turns off the upper
5011 ;; half, then we can load mem:HI instead.
5013 (define_peephole2
5014 [(set (match_operand:SI 0 "register_operand" "")
5015 (match_operand:SI 1 "memory_operand" ""))
5016 (set (match_dup 0)
5017 (and:SI (match_dup 0)
5018 (match_operand:SI 2 "const_int_operand" "")))]
5019 "(TARGET_H8300H || TARGET_H8300S)
5020 && !MEM_VOLATILE_P (operands[1])
5021 && offsettable_memref_p (operands[1])
5022 && (INTVAL (operands[2]) & ~0xffff) == 0
5023 && INTVAL (operands[2]) != 255"
5024 [(set (match_dup 3)
5025 (match_dup 4))
5026 (set (match_dup 0)
5027 (and:SI (match_dup 0)
5028 (match_dup 2)))]
5029 "operands[3] = gen_lowpart (HImode, operands[0]);
5030 operands[4] = gen_lowpart (HImode, operands[1]);")
5032 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5033 ;; the equivalent with shorter sequences. Here is the summary. Cases
5034 ;; are grouped for each define_peephole2.
5035 ;;
5036 ;; reg const_int use insn
5037 ;; --------------------------------------------------------
5038 ;; dead -2 eq/ne inc.l
5039 ;; dead -1 eq/ne inc.l
5040 ;; dead 1 eq/ne dec.l
5041 ;; dead 2 eq/ne dec.l
5042 ;;
5043 ;; dead 1 ge/lt shar.l
5044 ;; dead 3 (H8S) ge/lt shar.l
5045 ;;
5046 ;; dead 1 geu/ltu shar.l
5047 ;; dead 3 (H8S) geu/ltu shar.l
5048 ;;
5049 ;; ---- 255 ge/lt mov.b
5050 ;;
5051 ;; ---- 255 geu/ltu mov.b
5053 ;; Transform
5054 ;;
5055 ;; cmp.w #1,r0
5056 ;; bne .L1
5057 ;;
5058 ;; into
5059 ;;
5060 ;; dec.w #1,r0
5061 ;; bne .L1
5063 (define_peephole2
5064 [(set (cc0)
5065 (compare (match_operand:HI 0 "register_operand" "")
5066 (match_operand:HI 1 "incdec_operand" "")))
5067 (set (pc)
5068 (if_then_else (match_operator 3 "eqne_operator"
5069 [(cc0) (const_int 0)])
5070 (label_ref (match_operand 2 "" ""))
5071 (pc)))]
5072 "(TARGET_H8300H || TARGET_H8300S)
5073 && peep2_reg_dead_p (1, operands[0])"
5074 [(set (match_dup 0)
5075 (unspec:HI [(match_dup 0)
5076 (match_dup 4)]
5077 UNSPEC_INCDEC))
5078 (set (cc0)
5079 (match_dup 0))
5080 (set (pc)
5081 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5082 (label_ref (match_dup 2))
5083 (pc)))]
5084 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5086 ;; Transform
5087 ;;
5088 ;; cmp.w #1,r0
5089 ;; bgt .L1
5090 ;;
5091 ;; into
5092 ;;
5093 ;; shar.w r0
5094 ;; bgt .L1
5096 (define_peephole2
5097 [(set (cc0)
5098 (compare (match_operand:HI 0 "register_operand" "")
5099 (match_operand:HI 1 "const_int_operand" "")))
5100 (set (pc)
5101 (if_then_else (match_operator 2 "gtle_operator"
5102 [(cc0) (const_int 0)])
5103 (label_ref (match_operand 3 "" ""))
5104 (pc)))]
5105 "(TARGET_H8300H || TARGET_H8300S)
5106 && peep2_reg_dead_p (1, operands[0])
5107 && (INTVAL (operands[1]) == 1
5108 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5109 [(parallel [(set (match_dup 0)
5110 (ashiftrt:HI (match_dup 0)
5111 (match_dup 4)))
5112 (clobber (scratch:QI))])
5113 (set (cc0)
5114 (match_dup 0))
5115 (set (pc)
5116 (if_then_else (match_dup 2)
5117 (label_ref (match_dup 3))
5118 (pc)))]
5119 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5121 ;; Transform
5122 ;;
5123 ;; cmp.w #1,r0
5124 ;; bhi .L1
5125 ;;
5126 ;; into
5127 ;;
5128 ;; shar.w r0
5129 ;; bne .L1
5131 (define_peephole2
5132 [(set (cc0)
5133 (compare (match_operand:HI 0 "register_operand" "")
5134 (match_operand:HI 1 "const_int_operand" "")))
5135 (set (pc)
5136 (if_then_else (match_operator 2 "gtuleu_operator"
5137 [(cc0) (const_int 0)])
5138 (label_ref (match_operand 3 "" ""))
5139 (pc)))]
5140 "(TARGET_H8300H || TARGET_H8300S)
5141 && peep2_reg_dead_p (1, operands[0])
5142 && (INTVAL (operands[1]) == 1
5143 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5144 [(parallel [(set (match_dup 0)
5145 (ashiftrt:HI (match_dup 0)
5146 (match_dup 4)))
5147 (clobber (scratch:QI))])
5148 (set (cc0)
5149 (match_dup 0))
5150 (set (pc)
5151 (if_then_else (match_dup 5)
5152 (label_ref (match_dup 3))
5153 (pc)))]
5154 {
5155 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5156 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5157 VOIDmode,
5158 cc0_rtx,
5159 const0_rtx);
5160 })
5162 ;; Transform
5163 ;;
5164 ;; cmp.w #255,r0
5165 ;; bgt .L1
5166 ;;
5167 ;; into
5168 ;;
5169 ;; mov.b r0h,r0h
5170 ;; bgt .L1
5172 (define_peephole2
5173 [(set (cc0)
5174 (compare (match_operand:HI 0 "register_operand" "")
5175 (const_int 255)))
5176 (set (pc)
5177 (if_then_else (match_operator 1 "gtle_operator"
5178 [(cc0) (const_int 0)])
5179 (label_ref (match_operand 2 "" ""))
5180 (pc)))]
5181 "TARGET_H8300H || TARGET_H8300S"
5182 [(set (cc0)
5183 (and:HI (match_dup 0)
5184 (const_int -256)))
5185 (set (pc)
5186 (if_then_else (match_dup 1)
5187 (label_ref (match_dup 2))
5188 (pc)))]
5189 "")
5191 ;; Transform
5192 ;;
5193 ;; cmp.w #255,r0
5194 ;; bhi .L1
5195 ;;
5196 ;; into
5197 ;;
5198 ;; mov.b r0h,r0h
5199 ;; bne .L1
5201 (define_peephole2
5202 [(set (cc0)
5203 (compare (match_operand:HI 0 "register_operand" "")
5204 (const_int 255)))
5205 (set (pc)
5206 (if_then_else (match_operator 1 "gtuleu_operator"
5207 [(cc0) (const_int 0)])
5208 (label_ref (match_operand 2 "" ""))
5209 (pc)))]
5210 "TARGET_H8300H || TARGET_H8300S"
5211 [(set (cc0)
5212 (and:HI (match_dup 0)
5213 (const_int -256)))
5214 (set (pc)
5215 (if_then_else (match_dup 3)
5216 (label_ref (match_dup 2))
5217 (pc)))]
5218 {
5219 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5220 VOIDmode,
5221 cc0_rtx,
5222 const0_rtx);
5223 })
5225 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5226 ;; the equivalent with shorter sequences. Here is the summary. Cases
5227 ;; are grouped for each define_peephole2.
5228 ;;
5229 ;; reg const_int use insn
5230 ;; --------------------------------------------------------
5231 ;; live -2 eq/ne copy and inc.l
5232 ;; live -1 eq/ne copy and inc.l
5233 ;; live 1 eq/ne copy and dec.l
5234 ;; live 2 eq/ne copy and dec.l
5235 ;;
5236 ;; dead -2 eq/ne inc.l
5237 ;; dead -1 eq/ne inc.l
5238 ;; dead 1 eq/ne dec.l
5239 ;; dead 2 eq/ne dec.l
5240 ;;
5241 ;; dead -131072 eq/ne inc.w and test
5242 ;; dead -65536 eq/ne inc.w and test
5243 ;; dead 65536 eq/ne dec.w and test
5244 ;; dead 131072 eq/ne dec.w and test
5245 ;;
5246 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5247 ;; dead 0x0000??00 eq/ne xor.b and test
5248 ;; dead 0x0000ffff eq/ne not.w and test
5249 ;;
5250 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5251 ;; dead 0xffff??ff eq/ne xor.b and not.l
5252 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5253 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5254 ;;
5255 ;; live 1 ge/lt copy and shar.l
5256 ;; live 3 (H8S) ge/lt copy and shar.l
5257 ;;
5258 ;; live 1 geu/ltu copy and shar.l
5259 ;; live 3 (H8S) geu/ltu copy and shar.l
5260 ;;
5261 ;; dead 1 ge/lt shar.l
5262 ;; dead 3 (H8S) ge/lt shar.l
5263 ;;
5264 ;; dead 1 geu/ltu shar.l
5265 ;; dead 3 (H8S) geu/ltu shar.l
5266 ;;
5267 ;; dead 3 (H8/300H) ge/lt and.b and test
5268 ;; dead 7 ge/lt and.b and test
5269 ;; dead 15 ge/lt and.b and test
5270 ;; dead 31 ge/lt and.b and test
5271 ;; dead 63 ge/lt and.b and test
5272 ;; dead 127 ge/lt and.b and test
5273 ;; dead 255 ge/lt and.b and test
5274 ;;
5275 ;; dead 3 (H8/300H) geu/ltu and.b and test
5276 ;; dead 7 geu/ltu and.b and test
5277 ;; dead 15 geu/ltu and.b and test
5278 ;; dead 31 geu/ltu and.b and test
5279 ;; dead 63 geu/ltu and.b and test
5280 ;; dead 127 geu/ltu and.b and test
5281 ;; dead 255 geu/ltu and.b and test
5282 ;;
5283 ;; ---- 65535 ge/lt mov.w
5284 ;;
5285 ;; ---- 65535 geu/ltu mov.w
5287 ;; Transform
5288 ;;
5289 ;; cmp.l #1,er0
5290 ;; beq .L1
5291 ;;
5292 ;; into
5293 ;;
5294 ;; dec.l #1,er0
5295 ;; beq .L1
5297 (define_peephole2
5298 [(set (cc0)
5299 (compare (match_operand:SI 0 "register_operand" "")
5300 (match_operand:SI 1 "incdec_operand" "")))
5301 (set (pc)
5302 (if_then_else (match_operator 3 "eqne_operator"
5303 [(cc0) (const_int 0)])
5304 (label_ref (match_operand 2 "" ""))
5305 (pc)))]
5306 "(TARGET_H8300H || TARGET_H8300S)
5307 && peep2_reg_dead_p (1, operands[0])"
5308 [(set (match_dup 0)
5309 (unspec:SI [(match_dup 0)
5310 (match_dup 4)]
5311 UNSPEC_INCDEC))
5312 (set (cc0)
5313 (match_dup 0))
5314 (set (pc)
5315 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5316 (label_ref (match_dup 2))
5317 (pc)))]
5318 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5320 ;; Transform
5321 ;;
5322 ;; cmp.l #65536,er0
5323 ;; beq .L1
5324 ;;
5325 ;; into
5326 ;;
5327 ;; dec.l #1,e0
5328 ;; beq .L1
5330 (define_peephole2
5331 [(set (cc0)
5332 (compare (match_operand:SI 0 "register_operand" "")
5333 (match_operand:SI 1 "const_int_operand" "")))
5334 (set (pc)
5335 (if_then_else (match_operator 3 "eqne_operator"
5336 [(cc0) (const_int 0)])
5337 (label_ref (match_operand 2 "" ""))
5338 (pc)))]
5339 "(TARGET_H8300H || TARGET_H8300S)
5340 && peep2_reg_dead_p (1, operands[0])
5341 && (INTVAL (operands[1]) == -131072
5342 || INTVAL (operands[1]) == -65536
5343 || INTVAL (operands[1]) == 65536
5344 || INTVAL (operands[1]) == 131072)"
5345 [(set (match_dup 0)
5346 (plus:SI (match_dup 0)
5347 (match_dup 4)))
5348 (set (cc0)
5349 (match_dup 0))
5350 (set (pc)
5351 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5352 (label_ref (match_dup 2))
5353 (pc)))]
5354 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5356 ;; Transform
5357 ;;
5358 ;; cmp.l #100,er0
5359 ;; beq .L1
5360 ;;
5361 ;; into
5362 ;;
5363 ;; xor.b #100,er0
5364 ;; mov.l er0,er0
5365 ;; beq .L1
5367 (define_peephole2
5368 [(set (cc0)
5369 (compare (match_operand:SI 0 "register_operand" "")
5370 (match_operand:SI 1 "const_int_operand" "")))
5371 (set (pc)
5372 (if_then_else (match_operator 3 "eqne_operator"
5373 [(cc0) (const_int 0)])
5374 (label_ref (match_operand 2 "" ""))
5375 (pc)))]
5376 "(TARGET_H8300H || TARGET_H8300S)
5377 && peep2_reg_dead_p (1, operands[0])
5378 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5379 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5380 || INTVAL (operands[1]) == 0x0000ffff)
5381 && INTVAL (operands[1]) != 1
5382 && INTVAL (operands[1]) != 2"
5383 [(set (match_dup 0)
5384 (xor:SI (match_dup 0)
5385 (match_dup 1)))
5386 (set (cc0)
5387 (match_dup 0))
5388 (set (pc)
5389 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5390 (label_ref (match_dup 2))
5391 (pc)))]
5392 "")
5394 ;; Transform
5395 ;;
5396 ;; cmp.l #-100,er0
5397 ;; beq .L1
5398 ;;
5399 ;; into
5400 ;;
5401 ;; xor.b #99,er0
5402 ;; not.l er0
5403 ;; beq .L1
5405 (define_peephole2
5406 [(set (cc0)
5407 (compare (match_operand:SI 0 "register_operand" "")
5408 (match_operand:SI 1 "const_int_operand" "")))
5409 (set (pc)
5410 (if_then_else (match_operator 3 "eqne_operator"
5411 [(cc0) (const_int 0)])
5412 (label_ref (match_operand 2 "" ""))
5413 (pc)))]
5414 "(TARGET_H8300H || TARGET_H8300S)
5415 && peep2_reg_dead_p (1, operands[0])
5416 && ((INTVAL (operands[1]) | 0x00ff) == -1
5417 || (INTVAL (operands[1]) | 0xff00) == -1)
5418 && INTVAL (operands[1]) != -1
5419 && INTVAL (operands[1]) != -2"
5420 [(set (match_dup 0)
5421 (xor:SI (match_dup 0)
5422 (match_dup 4)))
5423 (set (match_dup 0)
5424 (not:SI (match_dup 0)))
5425 (set (cc0)
5426 (match_dup 0))
5427 (set (pc)
5428 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5429 (label_ref (match_dup 2))
5430 (pc)))]
5431 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
5433 ;; Transform
5434 ;;
5435 ;; cmp.l #-2147483648,er0
5436 ;; beq .L1
5437 ;;
5438 ;; into
5439 ;;
5440 ;; rotl.l er0
5441 ;; dec.l #1,er0
5442 ;; beq .L1
5444 (define_peephole2
5445 [(set (cc0)
5446 (compare (match_operand:SI 0 "register_operand" "")
5447 (match_operand:SI 1 "const_int_operand" "")))
5448 (set (pc)
5449 (if_then_else (match_operator 3 "eqne_operator"
5450 [(cc0) (const_int 0)])
5451 (label_ref (match_operand 2 "" ""))
5452 (pc)))]
5453 "(TARGET_H8300H || TARGET_H8300S)
5454 && peep2_reg_dead_p (1, operands[0])
5455 && (INTVAL (operands[1]) == -2147483647 - 1
5456 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5457 [(set (match_dup 0)
5458 (rotate:SI (match_dup 0)
5459 (match_dup 4)))
5460 (set (match_dup 0)
5461 (unspec:SI [(match_dup 0)
5462 (const_int -1)]
5463 UNSPEC_INCDEC))
5464 (set (cc0)
5465 (match_dup 0))
5466 (set (pc)
5467 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5468 (label_ref (match_dup 2))
5469 (pc)))]
5470 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
5472 ;; Transform
5473 ;;
5474 ;; cmp.l #1,er0
5475 ;; bgt .L1
5476 ;;
5477 ;; into
5478 ;;
5479 ;; mov.l er0,er1
5480 ;; shar.l er1
5481 ;; bgt .L1
5483 ;; We avoid this transformation if we see more than one copy of the
5484 ;; same compare insn immediately before this one.
5486 (define_peephole2
5487 [(match_scratch:SI 4 "r")
5488 (set (cc0)
5489 (compare (match_operand:SI 0 "register_operand" "")
5490 (match_operand:SI 1 "const_int_operand" "")))
5491 (set (pc)
5492 (if_then_else (match_operator 2 "gtle_operator"
5493 [(cc0) (const_int 0)])
5494 (label_ref (match_operand 3 "" ""))
5495 (pc)))]
5496 "(TARGET_H8300H || TARGET_H8300S)
5497 && !peep2_reg_dead_p (1, operands[0])
5498 && (INTVAL (operands[1]) == 1
5499 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5500 && !same_cmp_preceding_p (insn)"
5501 [(set (match_dup 4)
5502 (match_dup 0))
5503 (parallel [(set (match_dup 4)
5504 (ashiftrt:SI (match_dup 4)
5505 (match_dup 5)))
5506 (clobber (scratch:QI))])
5507 (set (cc0)
5508 (match_dup 4))
5509 (set (pc)
5510 (if_then_else (match_dup 2)
5511 (label_ref (match_dup 3))
5512 (pc)))]
5513 "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5515 ;; Transform
5516 ;;
5517 ;; cmp.l #1,er0
5518 ;; bhi .L1
5519 ;;
5520 ;; into
5521 ;;
5522 ;; mov.l er0,er1
5523 ;; shar.l er1
5524 ;; bne .L1
5526 ;; We avoid this transformation if we see more than one copy of the
5527 ;; same compare insn immediately before this one.
5529 (define_peephole2
5530 [(match_scratch:SI 4 "r")
5531 (set (cc0)
5532 (compare (match_operand:SI 0 "register_operand" "")
5533 (match_operand:SI 1 "const_int_operand" "")))
5534 (set (pc)
5535 (if_then_else (match_operator 2 "gtuleu_operator"
5536 [(cc0) (const_int 0)])
5537 (label_ref (match_operand 3 "" ""))
5538 (pc)))]
5539 "(TARGET_H8300H || TARGET_H8300S)
5540 && !peep2_reg_dead_p (1, operands[0])
5541 && (INTVAL (operands[1]) == 1
5542 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5543 && !same_cmp_preceding_p (insn)"
5544 [(set (match_dup 4)
5545 (match_dup 0))
5546 (parallel [(set (match_dup 4)
5547 (ashiftrt:SI (match_dup 4)
5548 (match_dup 5)))
5549 (clobber (scratch:QI))])
5550 (set (cc0)
5551 (match_dup 4))
5552 (set (pc)
5553 (if_then_else (match_dup 6)
5554 (label_ref (match_dup 3))
5555 (pc)))]
5556 {
5557 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5558 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5559 VOIDmode,
5560 cc0_rtx,
5561 const0_rtx);
5562 })
5564 ;; Transform
5565 ;;
5566 ;; cmp.l #1,er0
5567 ;; bgt .L1
5568 ;;
5569 ;; into
5570 ;;
5571 ;; shar.l er0
5572 ;; bgt .L1
5574 (define_peephole2
5575 [(set (cc0)
5576 (compare (match_operand:SI 0 "register_operand" "")
5577 (match_operand:SI 1 "const_int_operand" "")))
5578 (set (pc)
5579 (if_then_else (match_operator 2 "gtle_operator"
5580 [(cc0) (const_int 0)])
5581 (label_ref (match_operand 3 "" ""))
5582 (pc)))]
5583 "(TARGET_H8300H || TARGET_H8300S)
5584 && peep2_reg_dead_p (1, operands[0])
5585 && (INTVAL (operands[1]) == 1
5586 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5587 [(parallel [(set (match_dup 0)
5588 (ashiftrt:SI (match_dup 0)
5589 (match_dup 4)))
5590 (clobber (scratch:QI))])
5591 (set (cc0)
5592 (match_dup 0))
5593 (set (pc)
5594 (if_then_else (match_dup 2)
5595 (label_ref (match_dup 3))
5596 (pc)))]
5597 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5599 ;; Transform
5600 ;;
5601 ;; cmp.l #1,er0
5602 ;; bhi .L1
5603 ;;
5604 ;; into
5605 ;;
5606 ;; shar.l er0
5607 ;; bne .L1
5609 (define_peephole2
5610 [(set (cc0)
5611 (compare (match_operand:SI 0 "register_operand" "")
5612 (match_operand:SI 1 "const_int_operand" "")))
5613 (set (pc)
5614 (if_then_else (match_operator 2 "gtuleu_operator"
5615 [(cc0) (const_int 0)])
5616 (label_ref (match_operand 3 "" ""))
5617 (pc)))]
5618 "(TARGET_H8300H || TARGET_H8300S)
5619 && peep2_reg_dead_p (1, operands[0])
5620 && (INTVAL (operands[1]) == 1
5621 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5622 [(parallel [(set (match_dup 0)
5623 (ashiftrt:SI (match_dup 0)
5624 (match_dup 4)))
5625 (clobber (scratch:QI))])
5626 (set (cc0)
5627 (match_dup 0))
5628 (set (pc)
5629 (if_then_else (match_dup 5)
5630 (label_ref (match_dup 3))
5631 (pc)))]
5632 {
5633 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5634 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5635 VOIDmode,
5636 cc0_rtx,
5637 const0_rtx);
5638 })
5640 ;; Transform
5641 ;;
5642 ;; cmp.l #15,er0
5643 ;; bgt .L1
5644 ;;
5645 ;; into
5646 ;;
5647 ;; and #240,r0l
5648 ;; mov.l er0,er0
5649 ;; bgt .L1
5651 (define_peephole2
5652 [(set (cc0)
5653 (compare (match_operand:SI 0 "register_operand" "")
5654 (match_operand:SI 1 "const_int_operand" "")))
5655 (set (pc)
5656 (if_then_else (match_operator 2 "gtle_operator"
5657 [(cc0) (const_int 0)])
5658 (label_ref (match_operand 3 "" ""))
5659 (pc)))]
5660 "(TARGET_H8300H || TARGET_H8300S)
5661 && peep2_reg_dead_p (1, operands[0])
5662 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5663 || INTVAL (operands[1]) == 7
5664 || INTVAL (operands[1]) == 15
5665 || INTVAL (operands[1]) == 31
5666 || INTVAL (operands[1]) == 63
5667 || INTVAL (operands[1]) == 127
5668 || INTVAL (operands[1]) == 255)"
5669 [(set (match_dup 0)
5670 (and:SI (match_dup 0)
5671 (match_dup 4)))
5672 (set (cc0)
5673 (match_dup 0))
5674 (set (pc)
5675 (if_then_else (match_dup 2)
5676 (label_ref (match_dup 3))
5677 (pc)))]
5678 "operands[4] = GEN_INT (~INTVAL (operands[1]));")
5680 ;; Transform
5681 ;;
5682 ;; cmp.l #15,er0
5683 ;; bhi .L1
5684 ;;
5685 ;; into
5686 ;;
5687 ;; and #240,r0l
5688 ;; mov.l er0,er0
5689 ;; bne .L1
5691 (define_peephole2
5692 [(set (cc0)
5693 (compare (match_operand:SI 0 "register_operand" "")
5694 (match_operand:SI 1 "const_int_operand" "")))
5695 (set (pc)
5696 (if_then_else (match_operator 2 "gtuleu_operator"
5697 [(cc0) (const_int 0)])
5698 (label_ref (match_operand 3 "" ""))
5699 (pc)))]
5700 "(TARGET_H8300H || TARGET_H8300S)
5701 && peep2_reg_dead_p (1, operands[0])
5702 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5703 || INTVAL (operands[1]) == 7
5704 || INTVAL (operands[1]) == 15
5705 || INTVAL (operands[1]) == 31
5706 || INTVAL (operands[1]) == 63
5707 || INTVAL (operands[1]) == 127
5708 || INTVAL (operands[1]) == 255)"
5709 [(set (match_dup 0)
5710 (and:SI (match_dup 0)
5711 (match_dup 4)))
5712 (set (cc0)
5713 (match_dup 0))
5714 (set (pc)
5715 (if_then_else (match_dup 5)
5716 (label_ref (match_dup 3))
5717 (pc)))]
5718 {
5719 operands[4] = GEN_INT (~INTVAL (operands[1]));
5720 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5721 VOIDmode,
5722 cc0_rtx,
5723 const0_rtx);
5724 })
5726 ;; Transform
5727 ;;
5728 ;; cmp.l #65535,er0
5729 ;; bgt .L1
5730 ;;
5731 ;; into
5732 ;;
5733 ;; mov.l e0,e0
5734 ;; bgt .L1
5736 (define_peephole2
5737 [(set (cc0)
5738 (compare (match_operand:SI 0 "register_operand" "")
5739 (const_int 65535)))
5740 (set (pc)
5741 (if_then_else (match_operator 1 "gtle_operator"
5742 [(cc0) (const_int 0)])
5743 (label_ref (match_operand 2 "" ""))
5744 (pc)))]
5745 "TARGET_H8300H || TARGET_H8300S"
5746 [(set (cc0)
5747 (and:SI (match_dup 0)
5748 (const_int -65536)))
5749 (set (pc)
5750 (if_then_else (match_dup 1)
5751 (label_ref (match_dup 2))
5752 (pc)))]
5753 "")
5755 ;; Transform
5756 ;;
5757 ;; cmp.l #65535,er0
5758 ;; bhi .L1
5759 ;;
5760 ;; into
5761 ;;
5762 ;; mov.l e0,e0
5763 ;; bne .L1
5765 (define_peephole2
5766 [(set (cc0)
5767 (compare (match_operand:SI 0 "register_operand" "")
5768 (const_int 65535)))
5769 (set (pc)
5770 (if_then_else (match_operator 1 "gtuleu_operator"
5771 [(cc0) (const_int 0)])
5772 (label_ref (match_operand 2 "" ""))
5773 (pc)))]
5774 "TARGET_H8300H || TARGET_H8300S"
5775 [(set (cc0)
5776 (and:SI (match_dup 0)
5777 (const_int -65536)))
5778 (set (pc)
5779 (if_then_else (match_dup 3)
5780 (label_ref (match_dup 2))
5781 (pc)))]
5782 {
5783 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5784 VOIDmode,
5785 cc0_rtx,
5786 const0_rtx);
5787 })
5789 ;; Transform
5790 ;;
5791 ;; cmp.l #1,er0
5792 ;; beq .L1
5793 ;;
5794 ;; into
5795 ;;
5796 ;; mov.l er0,er1
5797 ;; dec.l #1,er1
5798 ;; beq .L1
5800 ;; We avoid this transformation if we see more than one copy of the
5801 ;; same compare insn.
5803 (define_peephole2
5804 [(match_scratch:SI 4 "r")
5805 (set (cc0)
5806 (compare (match_operand:SI 0 "register_operand" "")
5807 (match_operand:SI 1 "incdec_operand" "")))
5808 (set (pc)
5809 (if_then_else (match_operator 3 "eqne_operator"
5810 [(cc0) (const_int 0)])
5811 (label_ref (match_operand 2 "" ""))
5812 (pc)))]
5813 "(TARGET_H8300H || TARGET_H8300S)
5814 && !peep2_reg_dead_p (1, operands[0])
5815 && !same_cmp_following_p (insn)"
5816 [(set (match_dup 4)
5817 (match_dup 0))
5818 (set (match_dup 4)
5819 (unspec:SI [(match_dup 4)
5820 (match_dup 5)]
5821 UNSPEC_INCDEC))
5822 (set (cc0)
5823 (match_dup 4))
5824 (set (pc)
5825 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5826 (label_ref (match_dup 2))
5827 (pc)))]
5828 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
5830 ;; Narrow the mode of testing if possible.
5832 (define_peephole2
5833 [(set (match_operand:HI 0 "register_operand" "")
5834 (and:HI (match_dup 0)
5835 (match_operand:HI 1 "const_int_qi_operand" "")))
5836 (set (cc0)
5837 (match_dup 0))
5838 (set (pc)
5839 (if_then_else (match_operator 3 "eqne_operator"
5840 [(cc0) (const_int 0)])
5841 (label_ref (match_operand 2 "" ""))
5842 (pc)))]
5843 "peep2_reg_dead_p (2, operands[0])"
5844 [(set (match_dup 4)
5845 (and:QI (match_dup 4)
5846 (match_dup 5)))
5847 (set (cc0)
5848 (match_dup 4))
5849 (set (pc)
5850 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5851 (label_ref (match_dup 2))
5852 (pc)))]
5853 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5854 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5856 (define_peephole2
5857 [(set (match_operand:SI 0 "register_operand" "")
5858 (and:SI (match_dup 0)
5859 (match_operand:SI 1 "const_int_qi_operand" "")))
5860 (set (cc0)
5861 (match_dup 0))
5862 (set (pc)
5863 (if_then_else (match_operator 3 "eqne_operator"
5864 [(cc0) (const_int 0)])
5865 (label_ref (match_operand 2 "" ""))
5866 (pc)))]
5867 "peep2_reg_dead_p (2, operands[0])"
5868 [(set (match_dup 4)
5869 (and:QI (match_dup 4)
5870 (match_dup 5)))
5871 (set (cc0)
5872 (match_dup 4))
5873 (set (pc)
5874 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5875 (label_ref (match_dup 2))
5876 (pc)))]
5877 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5878 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5880 (define_peephole2
5881 [(set (match_operand:SI 0 "register_operand" "")
5882 (and:SI (match_dup 0)
5883 (match_operand:SI 1 "const_int_hi_operand" "")))
5884 (set (cc0)
5885 (match_dup 0))
5886 (set (pc)
5887 (if_then_else (match_operator 3 "eqne_operator"
5888 [(cc0) (const_int 0)])
5889 (label_ref (match_operand 2 "" ""))
5890 (pc)))]
5891 "peep2_reg_dead_p (2, operands[0])"
5892 [(set (match_dup 4)
5893 (and:HI (match_dup 4)
5894 (match_dup 5)))
5895 (set (cc0)
5896 (match_dup 4))
5897 (set (pc)
5898 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5899 (label_ref (match_dup 2))
5900 (pc)))]
5901 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5902 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
5904 (define_peephole2
5905 [(set (match_operand:SI 0 "register_operand" "")
5906 (and:SI (match_dup 0)
5907 (match_operand:SI 1 "const_int_qi_operand" "")))
5908 (set (match_dup 0)
5909 (xor:SI (match_dup 0)
5910 (match_operand:SI 2 "const_int_qi_operand" "")))
5911 (set (cc0)
5912 (match_dup 0))
5913 (set (pc)
5914 (if_then_else (match_operator 4 "eqne_operator"
5915 [(cc0) (const_int 0)])
5916 (label_ref (match_operand 3 "" ""))
5917 (pc)))]
5918 "peep2_reg_dead_p (3, operands[0])
5919 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5920 [(set (match_dup 5)
5921 (and:QI (match_dup 5)
5922 (match_dup 6)))
5923 (set (match_dup 5)
5924 (xor:QI (match_dup 5)
5925 (match_dup 7)))
5926 (set (cc0)
5927 (match_dup 5))
5928 (set (pc)
5929 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5930 (label_ref (match_dup 3))
5931 (pc)))]
5932 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5933 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5934 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
5936 ;; These triggers right at the end of allocation of locals in the
5937 ;; prologue (and possibly at other places).
5939 ;; stack adjustment of -4, generate one push
5940 ;;
5941 ;; before : 6 bytes, 10 clocks
5942 ;; after : 4 bytes, 10 clocks
5944 (define_peephole2
5945 [(set (reg:SI SP_REG)
5946 (plus:SI (reg:SI SP_REG)
5947 (const_int -4)))
5948 (set (mem:SI (reg:SI SP_REG))
5949 (match_operand:SI 0 "register_operand" ""))]
5950 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5951 && REGNO (operands[0]) != SP_REG"
5952 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5953 (match_dup 0))]
5954 "")
5956 ;; stack adjustment of -12, generate one push
5957 ;;
5958 ;; before : 10 bytes, 14 clocks
5959 ;; after : 8 bytes, 14 clocks
5961 (define_peephole2
5962 [(set (reg:SI SP_REG)
5963 (plus:SI (reg:SI SP_REG)
5964 (const_int -12)))
5965 (set (mem:SI (reg:SI SP_REG))
5966 (match_operand:SI 0 "register_operand" ""))]
5967 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5968 && REGNO (operands[0]) != SP_REG"
5969 [(set (reg:SI SP_REG)
5970 (plus:SI (reg:SI SP_REG)
5971 (const_int -4)))
5972 (set (reg:SI SP_REG)
5973 (plus:SI (reg:SI SP_REG)
5974 (const_int -4)))
5975 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5976 (match_dup 0))]
5977 "")
5979 ;; Transform
5980 ;;
5981 ;; mov dst,reg
5982 ;; op src,reg
5983 ;; mov reg,dst
5984 ;;
5985 ;; into
5986 ;;
5987 ;; op src,dst
5988 ;;
5989 ;; if "reg" dies at the end of the sequence.
5990 (define_peephole2
5991 [(set (match_operand 0 "register_operand" "")
5992 (match_operand 1 "memory_operand" ""))
5993 (set (match_dup 0)
5994 (match_operator 2 "h8sx_binary_memory_operator"
5995 [(match_dup 0)
5996 (match_operand 3 "h8300_src_operand" "")]))
5997 (set (match_operand 4 "memory_operand" "")
5998 (match_dup 0))]
5999 "0 /* Disable because it breaks compiling fp-bit.c. */
6000 && TARGET_H8300SX
6001 && peep2_reg_dead_p (3, operands[0])
6002 && !reg_overlap_mentioned_p (operands[0], operands[3])
6003 && !reg_overlap_mentioned_p (operands[0], operands[4])
6004 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6005 [(set (match_dup 4)
6006 (match_dup 5))]
6007 {
6008 operands[5] = shallow_copy_rtx (operands[2]);
6009 XEXP (operands[5], 0) = operands[1];
6010 })
6012 ;; Transform
6013 ;;
6014 ;; mov src,reg
6015 ;; op reg,dst
6016 ;;
6017 ;; into
6018 ;;
6019 ;; op src,dst
6020 ;;
6021 ;; if "reg" dies in the second insn.
6022 (define_peephole2
6023 [(set (match_operand 0 "register_operand" "")
6024 (match_operand 1 "h8300_src_operand" ""))
6025 (set (match_operand 2 "h8300_dst_operand" "")
6026 (match_operator 3 "h8sx_binary_memory_operator"
6027 [(match_operand 4 "h8300_dst_operand" "")
6028 (match_dup 0)]))]
6029 "0 /* Disable because it breaks compiling fp-bit.c. */
6030 && TARGET_H8300SX
6031 && peep2_reg_dead_p (2, operands[0])
6032 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6033 [(set (match_dup 2)
6034 (match_dup 5))]
6035 {
6036 operands[5] = shallow_copy_rtx (operands[3]);
6037 XEXP (operands[5], 1) = operands[1];
6038 })
6040 ;; Transform
6041 ;;
6042 ;; mov dst,reg
6043 ;; op reg
6044 ;; mov reg,dst
6045 ;;
6046 ;; into
6047 ;;
6048 ;; op dst
6049 ;;
6050 ;; if "reg" dies at the end of the sequence.
6051 (define_peephole2
6052 [(set (match_operand 0 "register_operand" "")
6053 (match_operand 1 "memory_operand" ""))
6054 (set (match_dup 0)
6055 (match_operator 2 "h8sx_unary_memory_operator"
6056 [(match_dup 0)]))
6057 (set (match_operand 3 "memory_operand" "")
6058 (match_dup 0))]
6059 "TARGET_H8300SX
6060 && peep2_reg_dead_p (3, operands[0])
6061 && !reg_overlap_mentioned_p (operands[0], operands[3])
6062 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6063 [(set (match_dup 3)
6064 (match_dup 4))]
6065 {
6066 operands[4] = shallow_copy_rtx (operands[2]);
6067 XEXP (operands[4], 0) = operands[1];
6068 })
6070 ;; Transform
6071 ;;
6072 ;; mov src1,reg
6073 ;; cmp reg,src2
6074 ;;
6075 ;; into
6076 ;;
6077 ;; cmp src1,src2
6078 ;;
6079 ;; if "reg" dies in the comparison.
6080 (define_peephole2
6081 [(set (match_operand 0 "register_operand" "")
6082 (match_operand 1 "h8300_dst_operand" ""))
6083 (set (cc0)
6084 (compare (match_dup 0)
6085 (match_operand 2 "h8300_src_operand" "")))]
6086 "TARGET_H8300SX
6087 && peep2_reg_dead_p (2, operands[0])
6088 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6089 [(set (cc0)
6090 (compare (match_dup 1)
6091 (match_dup 2)))])
6093 ;; Likewise for the second operand.
6094 (define_peephole2
6095 [(set (match_operand 0 "register_operand" "")
6096 (match_operand 1 "h8300_src_operand" ""))
6097 (set (cc0)
6098 (compare (match_operand 2 "h8300_dst_operand" "")
6099 (match_dup 0)))]
6100 "TARGET_H8300SX
6101 && peep2_reg_dead_p (2, operands[0])
6102 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6103 [(set (cc0)
6104 (compare (match_dup 2)
6105 (match_dup 1)))])
6107 ;; Combine two moves.
6108 (define_peephole2
6109 [(set (match_operand 0 "register_operand" "")
6110 (match_operand 1 "h8300_src_operand" ""))
6111 (set (match_operand 2 "h8300_dst_operand" "")
6112 (match_dup 0))]
6113 "TARGET_H8300SX
6114 && peep2_reg_dead_p (2, operands[0])
6115 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6116 [(set (match_dup 2)
6117 (match_dup 1))])