| blob | 7df85f24847044d58cb31eb1d7ca647399a43fe0 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx last_death;
149 /* Record last point of modification of (hard or pseudo) register n. */
150 rtx last_set;
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
257 /* Record the luid of the last insn that invalidated memory
258 (anything that writes memory, and subroutine calls, but not pushes). */
262 /* Record the luid of the last CALL_INSN
263 so we can tell whether a potential combination crosses any calls. */
267 /* When `subst' is called, this is the insn that is being modified
268 (by combining in a previous insn). The PATTERN of this insn
269 is still the old pattern partially modified and it should not be
270 looked at, but this may be used to examine the successors of the insn
271 to judge whether a simplification is valid. */
275 /* This is the lowest LUID that `subst' is currently dealing with.
276 get_last_value will not return a value if the register was set at or
277 after this LUID. If not for this mechanism, we could get confused if
278 I2 or I1 in try_combine were an insn that used the old value of a register
279 to obtain a new value. In that case, we might erroneously get the
280 new value of the register when we wanted the old one. */
284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
285 must consider all these registers to be always live. */
289 /* This is an insn to which a LOG_LINKS entry has been added. If this
290 insn is the earlier than I2 or I3, combine should rescan starting at
291 that location. */
295 /* Basic block in which we are performing combines. */
299 \f
300 /* Length of the currently allocated uid_insn_cost array. */
304 /* The following array records the insn_rtx_cost for every insn
305 in the instruction stream. */
309 /* The following array records the LOG_LINKS for every insn in the
310 instruction stream as struct insn_link pointers. */
313 rtx insn;
315 };
319 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
320 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
322 #define FOR_EACH_LOG_LINK(L, INSN) \
323 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
325 /* Links for LOG_LINKS are allocated from this obstack. */
329 /* Allocate a link. */
333 {
340 }
342 /* Incremented for each basic block. */
346 /* Reset to label_tick for each extended basic block in scanning order. */
350 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
351 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
355 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
356 be safely used. It is zero while computing them and after combine has
357 completed. This former test prevents propagating values based on
358 previously set values, which can be incorrect if a variable is modified
359 in a loop. */
363 \f
364 /* Record one modification to rtl structure
365 to be undone by storing old_contents into *where. */
369 struct undo
370 {
375 };
377 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
378 num_undo says how many are currently recorded.
380 other_insn is nonzero if we have modified some other insn in the process
381 of working on subst_insn. It must be verified too. */
383 struct undobuf
384 {
387 rtx other_insn;
388 };
392 /* Number of times the pseudo being substituted for
393 was found and replaced. */
474 \f
476 /* It is not safe to use ordinary gen_lowpart in combine.
477 See comments in gen_lowpart_for_combine. */
478 #undef RTL_HOOKS_GEN_LOWPART
479 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
481 /* Our implementation of gen_lowpart never emits a new pseudo. */
482 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
483 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
485 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
486 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
488 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
489 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
491 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
492 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
496 \f
497 /* Convenience wrapper for the canonicalize_comparison target hook.
498 Target hooks cannot use enum rtx_code. */
502 {
506 }
508 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
509 PATTERN can not be split. Otherwise, it returns an insn sequence.
510 This is a wrapper around split_insns which ensures that the
511 reg_stat vector is made larger if the splitter creates a new
512 register. */
514 static rtx
516 {
517 rtx ret;
525 }
527 /* This is used by find_single_use to locate an rtx in LOC that
528 contains exactly one use of DEST, which is typically either a REG
529 or CC0. It returns a pointer to the innermost rtx expression
530 containing DEST. Appearances of DEST that are being used to
531 totally replace it are not counted. */
535 {
544 {
548 CASE_CONST_ANY:
553 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
554 of a REG that occupies all of the REG, the insn uses DEST if
555 it is mentioned in the destination or the source. Otherwise, we
556 need just check the source. */
576 }
578 /* If it wasn't one of the common cases above, check each expression and
579 vector of this code. Look for a unique usage of DEST. */
583 {
585 {
590 else
596 /* Duplicate usage. */
598 }
600 {
604 {
610 else
617 }
618 }
619 }
622 }
625 /* See if DEST, produced in INSN, is used only a single time in the
626 sequel. If so, return a pointer to the innermost rtx expression in which
627 it is used.
629 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
631 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
632 care about REG_DEAD notes or LOG_LINKS.
634 Otherwise, we find the single use by finding an insn that has a
635 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
636 only referenced once in that insn, we know that it must be the first
637 and last insn referencing DEST. */
641 {
642 basic_block bb;
643 rtx next;
647 #ifdef HAVE_cc0
649 {
659 }
660 #endif
670 {
676 {
681 }
682 }
685 }
686 \f
687 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
688 insn. The substitution can be undone by undo_all. If INTO is already
689 set to NEWVAL, do not record this change. Because computing NEWVAL might
690 also call SUBST, we have to compute it before we put anything into
691 the undo table. */
693 static void
695 {
702 /* We'd like to catch as many invalid transformations here as
703 possible. Unfortunately, there are way too many mode changes
704 that are perfectly valid, so we'd waste too much effort for
705 little gain doing the checks here. Focus on catching invalid
706 transformations involving integer constants. */
709 {
710 /* Sanity check that we're replacing oldval with a CONST_INT
711 that is a valid sign-extension for the original mode. */
715 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
716 CONST_INT is not valid, because after the replacement, the
717 original mode would be gone. Unfortunately, we can't tell
718 when do_SUBST is called to replace the operand thereof, so we
719 perform this test on oldval instead, checking whether an
720 invalid replacement took place before we got here. */
725 }
729 else
738 }
740 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
742 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
743 for the value of a HOST_WIDE_INT value (including CONST_INT) is
744 not safe. */
746 static void
748 {
757 else
766 }
768 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
770 /* Similar to SUBST, but just substitute the mode. This is used when
771 changing the mode of a pseudo-register, so that any other
772 references to the entry in the regno_reg_rtx array will change as
773 well. */
775 static void
777 {
786 else
795 }
797 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
799 #ifndef HAVE_cc0
800 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
802 static void
804 {
813 else
822 }
824 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
825 #endif
826 \f
827 /* Subroutine of try_combine. Determine whether the replacement patterns
828 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
829 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
830 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
831 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
832 of all the instructions can be estimated and the replacements are more
833 expensive than the original sequence. */
835 static bool
838 {
843 /* Lookup the original insn_rtx_costs. */
848 {
851 {
855 }
856 else
857 {
861 }
862 }
863 else
864 {
867 }
869 /* Calculate the replacement insn_rtx_costs. */
872 {
876 }
877 else
878 {
881 }
884 {
890 {
893 }
894 else
896 }
898 /* Disallow this combination if both new_cost and old_cost are greater than
899 zero, and new_cost is greater than old cost. */
901 {
903 {
905 {
912 }
914 {
920 }
921 else
922 {
928 }
931 {
934 }
935 else
937 }
940 }
942 /* Update the uid_insn_cost array with the replacement costs. */
946 {
950 }
953 }
956 /* Delete any insns that copy a register to itself. */
958 static void
960 {
962 basic_block bb;
965 {
967 {
970 {
975 }
976 }
977 }
978 }
980 \f
981 /* Fill in log links field for all insns. */
983 static void
985 {
986 basic_block bb;
992 /* Pass through each block from the end, recording the uses of each
993 register and establishing log links when def is encountered.
994 Note that we do not clear next_use array in order to save time,
995 so we have to test whether the use is in the same basic block as def.
997 There are a few cases below when we do not consider the definition or
998 usage -- these are taken from original flow.c did. Don't ask me why it is
999 done this way; I don't know and if it works, I don't want to know. */
1002 {
1004 {
1008 /* Log links are created only once. */
1012 {
1015 rtx use_insn;
1020 /* Do not consider if it is pre/post modification in MEM. */
1024 /* Do not make the log link for frame pointer. */
1027 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1030 #endif
1031 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1033 #endif
1034 )
1039 {
1040 /* flow.c claimed:
1042 We don't build a LOG_LINK for hard registers contained
1043 in ASM_OPERANDs. If these registers get replaced,
1044 we might wind up changing the semantics of the insn,
1045 even if reload can make what appear to be valid
1046 assignments later. */
1049 {
1050 /* Don't add duplicate links between instructions. */
1059 }
1060 }
1062 }
1065 {
1069 /* Do not consider the usage of the stack pointer
1070 by function call. */
1075 }
1076 }
1077 }
1080 }
1082 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1083 true if we found a LOG_LINK that proves that A feeds B. This only works
1084 if there are no instructions between A and B which could have a link
1085 depending on A, since in that case we would not record a link for B.
1086 We also check the implicit dependency created by a cc0 setter/user
1087 pair. */
1089 static bool
1091 {
1096 #ifdef HAVE_cc0
1099 #endif
1101 }
1102 \f
1103 /* Main entry point for combiner. F is the first insn of the function.
1104 NREGS is the first unused pseudo-reg number.
1106 Return nonzero if the combiner has turned an indirect jump
1107 instruction into a direct jump. */
1108 static int
1110 {
1112 #ifdef HAVE_cc0
1113 rtx prev;
1114 #endif
1116 rtx first;
1117 basic_block last_bb;
1137 /* Allocate array for insn info. */
1145 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1146 problems when, for example, we have j <<= 1 in a loop. */
1151 /* Scan all SETs and see if we can deduce anything about what
1152 bits are known to be zero for some registers and how many copies
1153 of the sign bit are known to exist for those registers.
1155 Also set any known values so that we can use it while searching
1156 for what bits are known to be set. */
1159 /* Allow the entry block and the first block to fall into the same EBB.
1160 Conceptually the incoming promotions are assigned to the entry block. */
1165 {
1170 label_tick++;
1178 {
1179 #ifdef AUTO_INC_DEC
1180 rtx links;
1181 #endif
1187 insn);
1190 #ifdef AUTO_INC_DEC
1194 insn);
1195 #endif
1197 /* Record the current insn_rtx_cost of this instruction. */
1200 optimize_this_for_speed_p);
1204 }
1205 }
1209 /* Now scan all the insns in forward order. */
1216 {
1222 label_tick++;
1232 {
1235 {
1245 /* See if we know about function return values before this
1246 insn based upon SUBREG flags. */
1249 /* See if we can find hardregs and subreg of pseudos in
1250 narrower modes. This could help turning TRUNCATEs
1251 into SUBREGs. */
1254 /* Try this insn with each insn it links back to. */
1262 /* Try each sequence of three linked insns ending with this one. */
1265 {
1268 /* If the linked insn has been replaced by a note, then there
1269 is no point in pursuing this chain any further. */
1278 }
1280 #ifdef HAVE_cc0
1281 /* Try to combine a jump insn that uses CC0
1282 with a preceding insn that sets CC0, and maybe with its
1283 logical predecessor as well.
1284 This is how we make decrement-and-branch insns.
1285 We need this special code because data flow connections
1286 via CC0 do not get entered in LOG_LINKS. */
1292 {
1303 }
1305 /* Do the same for an insn that explicitly references CC0. */
1312 {
1323 }
1325 /* Finally, see if any of the insns that this insn links to
1326 explicitly references CC0. If so, try this insn, that insn,
1327 and its predecessor if it sets CC0. */
1339 #endif
1341 /* Try combining an insn with two different insns whose results it
1342 uses. */
1352 /* Try four-instruction combinations. */
1354 {
1358 /* If the linked insn has been replaced by a note, then there
1359 is no point in pursuing this chain any further. */
1364 {
1368 /* I0 -> I1 -> I2 -> I3. */
1375 /* I0, I1 -> I2, I2 -> I3. */
1383 }
1386 {
1390 /* I0 -> I2; I1, I2 -> I3. */
1397 /* I0 -> I1; I1, I2 -> I3. */
1404 }
1405 }
1407 /* Try this insn with each REG_EQUAL note it links back to. */
1409 {
1415 /* Avoid using a register that may already been marked
1416 dead by an earlier instruction. */
1421 {
1422 /* Temporarily replace the set's source with the
1423 contents of the REG_EQUAL note. The insn will
1424 be deleted or recognized by try_combine. */
1432 last_combined_insn);
1437 }
1438 }
1443 retry:
1444 ;
1445 }
1446 }
1447 }
1454 /* Clean up. */
1460 {
1463 {
1466 }
1468 }
1478 /* Make recognizer allow volatile MEMs again. */
1482 }
1484 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1486 static void
1488 {
1494 }
1495 \f
1496 /* Set up any promoted values for incoming argument registers. */
1498 static void
1500 {
1501 tree arg;
1506 {
1511 /* Only continue if the incoming argument is in a register. */
1515 /* Determine, if possible, whether all call sites of the current
1516 function lie within the current compilation unit. (This does
1517 take into account the exporting of a function via taking its
1518 address, and so forth.) */
1521 /* The mode and signedness of the argument before any promotions happen
1522 (equal to the mode of the pseudo holding it at that stage). */
1526 /* The mode and signedness of the argument after any source language and
1527 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1531 /* The mode and signedness of the argument as it is actually passed,
1532 see assign_parm_setup_reg in function.c. */
1536 /* The mode of the register in which the argument is being passed. */
1539 /* Eliminate sign extensions in the callee when:
1540 (a) A mode promotion has occurred; */
1543 /* (b) The mode of the register is the same as the mode of
1544 the argument as it is passed; */
1547 /* (c) There's no language level extension; */
1549 ;
1550 /* (c.1) All callers are from the current compilation unit. If that's
1551 the case we don't have to rely on an ABI, we only have to know
1552 what we're generating right now, and we know that we will do the
1553 mode1 to mode2 promotion with the given sign. */
1556 /* (c.2) The combination of the two promotions is useful. This is
1557 true when the signs match, or if the first promotion is unsigned.
1558 In the later case, (sign_extend (zero_extend x)) is the same as
1559 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1565 /* Record that the value was promoted from mode1 to mode3,
1566 so that any sign extension at the head of the current
1567 function may be eliminated. */
1571 }
1572 }
1574 /* Called via note_stores. If X is a pseudo that is narrower than
1575 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1577 If we are setting only a portion of X and we can't figure out what
1578 portion, assume all bits will be used since we don't know what will
1579 be happening.
1581 Similarly, set how many bits of X are known to be copies of the sign bit
1582 at all locations in the function. This is the smallest number implied
1583 by any set of X. */
1585 static void
1587 {
1593 /* If this register is undefined at the start of the file, we can't
1594 say what its contents were. */
1595 && ! REGNO_REG_SET_P
1598 {
1602 {
1606 }
1608 /* If this register is being initialized using itself, and the
1609 register is uninitialized in this basic block, and there are
1610 no LOG_LINKS which set the register, then part of the
1611 register is uninitialized. In that case we can't assume
1612 anything about the number of nonzero bits.
1614 ??? We could do better if we checked this in
1615 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1616 could avoid making assumptions about the insn which initially
1617 sets the register, while still using the information in other
1618 insns. We would have to be careful to check every insn
1619 involved in the combination. */
1625 {
1632 {
1636 }
1637 }
1639 /* If this is a complex assignment, see if we can convert it into a
1640 simple assignment. */
1643 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1644 set what we know about X. */
1649 {
1652 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1653 /* If X is narrower than a word and SRC is a non-negative
1654 constant that would appear negative in the mode of X,
1655 sign-extend it for use in reg_stat[].nonzero_bits because some
1656 machines (maybe most) will actually do the sign-extension
1657 and this is the conservative approach.
1659 ??? For 2.5, try to tighten up the MD files in this regard
1660 instead of this kludge. */
1667 #endif
1669 /* Don't call nonzero_bits if it cannot change anything. */
1676 }
1677 else
1678 {
1681 }
1682 }
1683 }
1684 \f
1685 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1686 optionally insns that were previously combined into I3 or that will be
1687 combined into the merger of INSN and I3. The order is PRED, PRED2,
1688 INSN, SUCC, SUCC2, I3.
1690 Return 0 if the combination is not allowed for any reason.
1692 If the combination is allowed, *PDEST will be set to the single
1693 destination of INSN and *PSRC to the single source, and this function
1694 will return 1. */
1696 static int
1700 {
1704 rtx p;
1705 #ifdef AUTO_INC_DEC
1706 rtx link;
1707 #endif
1712 {
1714 {
1719 }
1724 }
1728 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1729 or a PARALLEL consisting of such a SET and CLOBBERs.
1731 If INSN has CLOBBER parallel parts, ignore them for our processing.
1732 By definition, these happen during the execution of the insn. When it
1733 is merged with another insn, all bets are off. If they are, in fact,
1734 needed and aren't also supplied in I3, they may be added by
1735 recog_for_combine. Otherwise, it won't match.
1737 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1738 note.
1740 Get the source and destination of INSN. If more than one, can't
1741 combine. */
1747 {
1749 {
1753 {
1754 /* This is important to combine floating point insns
1755 for the SH4 port. */
1757 /* Combining an isolated USE doesn't make sense.
1758 We depend here on combinable_i3pat to reject them. */
1759 /* The code below this loop only verifies that the inputs of
1760 the SET in INSN do not change. We call reg_set_between_p
1761 to verify that the REG in the USE does not change between
1762 I3 and INSN.
1763 If the USE in INSN was for a pseudo register, the matching
1764 insn pattern will likely match any register; combining this
1765 with any other USE would only be safe if we knew that the
1766 used registers have identical values, or if there was
1767 something to tell them apart, e.g. different modes. For
1768 now, we forgo such complicated tests and simply disallow
1769 combining of USES of pseudo registers with any other USE. */
1772 {
1777 do
1778 {
1788 }
1790 }
1793 /* We can ignore CLOBBERs. */
1798 /* Ignore SETs whose result isn't used but not those that
1799 have side-effects. */
1805 /* If we have already found a SET, this is a second one and
1806 so we cannot combine with this insn. */
1814 /* Anything else means we can't combine. */
1816 }
1817 }
1820 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1821 so don't do anything with it. */
1824 }
1825 else
1831 /* The simplification in expand_field_assignment may call back to
1832 get_last_value, so set safe guard here. */
1838 /* Do not eliminate user-specified register if it is in an
1839 asm input because we may break the register asm usage defined
1840 in GCC manual if allow to do so.
1841 Be aware that this may cover more cases than we expect but this
1842 should be harmless. */
1847 /* Don't eliminate a store in the stack pointer. */
1849 /* Don't combine with an insn that sets a register to itself if it has
1850 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1852 /* Can't merge an ASM_OPERANDS. */
1854 /* Can't merge a function call. */
1856 /* Don't eliminate a function call argument. */
1862 /* Don't substitute into an incremented register. */
1866 /* Don't substitute into a non-local goto, this confuses CFG. */
1868 /* Make sure that DEST is not used after SUCC but before I3. */
1869 || (!all_adjacent
1870 && ((succ2
1874 /* Make sure that the value that is to be substituted for the register
1875 does not use any registers whose values alter in between. However,
1876 If the insns are adjacent, a use can't cross a set even though we
1877 think it might (this can happen for a sequence of insns each setting
1878 the same destination; last_set of that register might point to
1879 a NOTE). If INSN has a REG_EQUIV note, the register is always
1880 equivalent to the memory so the substitution is valid even if there
1881 are intervening stores. Also, don't move a volatile asm or
1882 UNSPEC_VOLATILE across any other insns. */
1883 || (! all_adjacent
1889 /* Don't combine across a CALL_INSN, because that would possibly
1890 change whether the life span of some REGs crosses calls or not,
1891 and it is a pain to update that information.
1892 Exception: if source is a constant, moving it later can't hurt.
1893 Accept that as a special case. */
1897 /* DEST must either be a REG or CC0. */
1899 {
1900 /* If register alignment is being enforced for multi-word items in all
1901 cases except for parameters, it is possible to have a register copy
1902 insn referencing a hard register that is not allowed to contain the
1903 mode being copied and which would not be valid as an operand of most
1904 insns. Eliminate this problem by not combining with such an insn.
1906 Also, on some machines we don't want to extend the life of a hard
1907 register. */
1912 /* Don't extend the life of a hard register unless it is
1913 user variable (if we have few registers) or it can't
1914 fit into the desired register (meaning something special
1915 is going on).
1916 Also avoid substituting a return register into I3, because
1917 reload can't handle a conflict with constraints of other
1918 inputs. */
1922 }
1930 {
1931 /* Don't substitute for a register intended as a clobberable
1932 operand. */
1937 /* If the clobber represents an earlyclobber operand, we must not
1938 substitute an expression containing the clobbered register.
1939 As we do not analyze the constraint strings here, we have to
1940 make the conservative assumption. However, if the register is
1941 a fixed hard reg, the clobber cannot represent any operand;
1942 we leave it up to the machine description to either accept or
1943 reject use-and-clobber patterns. */
1949 }
1951 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1952 or not), reject, unless nothing volatile comes between it and I3 */
1955 {
1956 /* Make sure neither succ nor succ2 contains a volatile reference. */
1961 /* We'll check insns between INSN and I3 below. */
1962 }
1964 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1965 to be an explicit register variable, and was chosen for a reason. */
1971 /* If INSN contains volatile references (specifically volatile MEMs),
1972 we cannot combine across any other volatile references.
1973 Even if INSN doesn't contain volatile references, any intervening
1974 volatile insn might affect machine state. */
1977 ? volatile_refs_p
1984 /* If INSN contains an autoincrement or autodecrement, make sure that
1985 register is not used between there and I3, and not already used in
1986 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1987 Also insist that I3 not be a jump; if it were one
1988 and the incremented register were spilled, we would lose. */
1990 #ifdef AUTO_INC_DEC
2005 #endif
2007 #ifdef HAVE_cc0
2008 /* Don't combine an insn that follows a CC0-setting insn.
2009 An insn that uses CC0 must not be separated from the one that sets it.
2010 We do, however, allow I2 to follow a CC0-setting insn if that insn
2011 is passed as I1; in that case it will be deleted also.
2012 We also allow combining in this case if all the insns are adjacent
2013 because that would leave the two CC0 insns adjacent as well.
2014 It would be more logical to test whether CC0 occurs inside I1 or I2,
2015 but that would be much slower, and this ought to be equivalent. */
2021 #endif
2023 /* If we get here, we have passed all the tests and the combination is
2024 to be allowed. */
2030 }
2031 \f
2032 /* LOC is the location within I3 that contains its pattern or the component
2033 of a PARALLEL of the pattern. We validate that it is valid for combining.
2035 One problem is if I3 modifies its output, as opposed to replacing it
2036 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2037 doing so would produce an insn that is not equivalent to the original insns.
2039 Consider:
2041 (set (reg:DI 101) (reg:DI 100))
2042 (set (subreg:SI (reg:DI 101) 0) <foo>)
2044 This is NOT equivalent to:
2046 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2047 (set (reg:DI 101) (reg:DI 100))])
2049 Not only does this modify 100 (in which case it might still be valid
2050 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2052 We can also run into a problem if I2 sets a register that I1
2053 uses and I1 gets directly substituted into I3 (not via I2). In that
2054 case, we would be getting the wrong value of I2DEST into I3, so we
2055 must reject the combination. This case occurs when I2 and I1 both
2056 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2057 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2058 of a SET must prevent combination from occurring. The same situation
2059 can occur for I0, in which case I0_NOT_IN_SRC is set.
2061 Before doing the above check, we first try to expand a field assignment
2062 into a set of logical operations.
2064 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2065 we place a register that is both set and used within I3. If more than one
2066 such register is detected, we fail.
2068 Return 1 if the combination is valid, zero otherwise. */
2070 static int
2073 {
2077 {
2082 rtx subdest;
2089 /* Check for the case where I3 modifies its output, as discussed
2090 above. We don't want to prevent pseudos from being combined
2091 into the address of a MEM, so only prevent the combination if
2092 i1 or i2 set the same MEM. */
2102 /* This is the same test done in can_combine_p except we can't test
2103 all_adjacent; we don't have to, since this instruction will stay
2104 in place, thus we are not considering increasing the lifetime of
2105 INNER_DEST.
2107 Also, if this insn sets a function argument, combining it with
2108 something that might need a spill could clobber a previous
2109 function argument; the all_adjacent test in can_combine_p also
2110 checks this; here, we do a more specific test for this case. */
2120 /* If DEST is used in I3, it is being killed in this insn, so
2121 record that for later. We have to consider paradoxical
2122 subregs here, since they kill the whole register, but we
2123 ignore partial subregs, STRICT_LOW_PART, etc.
2124 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2125 STACK_POINTER_REGNUM, since these are always considered to be
2126 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2136 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2138 #endif
2139 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2142 #endif
2144 {
2149 }
2150 }
2153 {
2160 }
2163 }
2164 \f
2165 /* Return 1 if X is an arithmetic expression that contains a multiplication
2166 and division. We don't count multiplications by powers of two here. */
2168 static int
2170 {
2172 {
2188 }
2189 }
2190 \f
2191 /* Determine whether INSN can be used in a combination. Return nonzero if
2192 not. This is used in try_combine to detect early some cases where we
2193 can't perform combinations. */
2195 static int
2197 {
2198 rtx set;
2201 /* If this isn't really an insn, we can't do anything.
2202 This can occur when flow deletes an insn that it has merged into an
2203 auto-increment address. */
2207 /* Never combine loads and stores involving hard regs that are likely
2208 to be spilled. The register allocator can usually handle such
2209 reg-reg moves by tying. If we allow the combiner to make
2210 substitutions of likely-spilled regs, reload might die.
2211 As an exception, we allow combinations involving fixed regs; these are
2212 not available to the register allocator so there's no risk involved. */
2233 }
2235 struct likely_spilled_retval_info
2236 {
2239 };
2241 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2242 hard registers that are known to be written to / clobbered in full. */
2243 static void
2245 {
2262 else
2265 }
2267 /* Return nonzero iff part of the return value is live during INSN, and
2268 it is likely spilled. This can happen when more than one insn is needed
2269 to copy the return value, e.g. when we consider to combine into the
2270 second copy insn for a complex value. */
2272 static int
2274 {
2278 /* We assume here that no machine mode needs more than
2279 32 hard registers when the value overlaps with a register
2280 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2295 /* Disregard parts of the return value that are set later. */
2304 /* Check if any of the (probably) live return value registers is
2305 likely spilled. */
2306 nregs --;
2307 do
2308 {
2314 }
2316 /* Adjust INSN after we made a change to its destination.
2318 Changing the destination can invalidate notes that say something about
2319 the results of the insn and a LOG_LINK pointing to the insn. */
2321 static void
2323 {
2324 /* For notes, be conservative and simply remove them. */
2327 /* The new insn will have a destination that was previously the destination
2328 of an insn just above it. Call distribute_links to make a LOG_LINK from
2329 the next use of that destination. */
2333 }
2335 /* Return TRUE if combine can reuse reg X in mode MODE.
2336 ADDED_SETS is nonzero if the original set is still required. */
2337 static bool
2339 {
2346 /* Allow hard registers if the new mode is legal, and occupies no more
2347 registers than the old mode. */
2353 /* Or a pseudo that is only used once. */
2356 }
2359 /* Check whether X, the destination of a set, refers to part of
2360 the register specified by REG. */
2362 static bool
2364 {
2365 /* Check that reg is an integer mode register. */
2376 }
2378 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2379 Note that the INSN should be deleted *after* removing dead edges, so
2380 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2381 but not for a (set (pc) (label_ref FOO)). */
2383 static void
2385 {
2393 {
2394 rtx insn;
2398 /* Remove barriers from the footer if there are any. */
2401 {
2404 else
2408 }
2411 }
2412 }
2414 /* Try to combine the insns I0, I1 and I2 into I3.
2415 Here I0, I1 and I2 appear earlier than I3.
2416 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2417 I3.
2419 If we are combining more than two insns and the resulting insn is not
2420 recognized, try splitting it into two insns. If that happens, I2 and I3
2421 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2422 Otherwise, I0, I1 and I2 are pseudo-deleted.
2424 Return 0 if the combination does not work. Then nothing is changed.
2425 If we did the combination, return the insn at which combine should
2426 resume scanning.
2428 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2429 new direct jump instruction.
2431 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2432 been I3 passed to an earlier try_combine within the same basic
2433 block. */
2435 static rtx
2437 rtx last_combined_insn)
2438 {
2439 /* New patterns for I3 and I2, respectively. */
2443 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2444 dead. */
2446 /* Total number of SETs to put into I3. */
2448 /* Nonzero if I2's or I1's body now appears in I3. */
2450 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2452 /* Contains I3 if the destination of I3 is used in its source, which means
2453 that the old life of I3 is being killed. If that usage is placed into
2454 I2 and not in I3, a REG_DEAD note must be made. */
2456 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2458 /* Copy of SET_SRC of I1 and I0, if needed. */
2460 /* Set if I2DEST was reused as a scratch register. */
2462 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2464 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2469 /* Notes that must be added to REG_NOTES in I3 and I2. */
2471 /* Notes that we substituted I3 into I2 instead of the normal case. */
2473 /* Notes that I1, I2 or I3 is a MULT operation. */
2479 rtx temp;
2482 rtx new_other_notes;
2485 /* Only try four-insn combinations when there's high likelihood of
2486 success. Look for simple insns, such as loads of constants or
2487 binary operations involving a constant. */
2489 {
2498 {
2501 rtx src;
2506 {
2509 }
2511 ngood++;
2514 nshift++;
2515 }
2518 }
2520 /* Exit early if one of the insns involved can't be used for
2521 combinations. */
2529 combine_attempts++;
2532 /* Reset the hard register usage information. */
2536 {
2543 else
2546 }
2548 /* If multiple insns feed into one of I2 or I3, they can be in any
2549 order. To simplify the code below, reorder them in sequence. */
2559 /* First check for one important special case that the code below will
2560 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2561 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2562 we may be able to replace that destination with the destination of I3.
2563 This occurs in the common code where we compute both a quotient and
2564 remainder into a structure, in which case we want to do the computation
2565 directly into the structure to avoid register-register copies.
2567 Note that this case handles both multiple sets in I2 and also cases
2568 where I2 has a number of CLOBBERs inside the PARALLEL.
2570 We make very conservative checks below and only try to handle the
2571 most common cases of this. For example, we only handle the case
2572 where I2 and I3 are adjacent to avoid making difficult register
2573 usage tests. */
2581 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2582 below would need to check what is inside (and reg_overlap_mentioned_p
2583 doesn't support those codes anyway). Don't allow those destinations;
2584 the resulting insn isn't likely to be recognized anyway. */
2590 {
2593 /* Make sure that the destination of I3,
2594 which we are going to substitute into one output of I2,
2595 is not used within another output of I2. We must avoid making this:
2596 (parallel [(set (mem (reg 69)) ...)
2597 (set (reg 69) ...)])
2598 which is not well-defined as to order of actions.
2599 (Besides, reload can't handle output reloads for this.)
2601 The problem can also happen if the dest of I3 is a memory ref,
2602 if another dest in I2 is an indirect memory ref. */
2614 {
2615 combine_merges++;
2625 /* Replace the dest in I2 with our dest and make the resulting
2626 insn the new pattern for I3. Then skip to where we validate
2627 the pattern. Everything was set up above. */
2632 }
2633 }
2635 /* If I2 is setting a pseudo to a constant and I3 is setting some
2636 sub-part of it to another constant, merge them by making a new
2637 constant. */
2644 {
2650 {
2653 {
2659 }
2660 }
2661 else
2662 {
2667 }
2670 {
2671 /* If this is the low part, we're done. */
2673 ;
2674 /* Handle the case where inner is twice the size of outer. */
2678 /* Otherwise give up for now. */
2679 else
2681 }
2686 {
2700 combine_merges++;
2707 /* Replace the source in I2 with the new constant and make the
2708 resulting insn the new pattern for I3. Then skip to where we
2709 validate the pattern. Everything was set up above. */
2715 /* The dest of I3 has been replaced with the dest of I2. */
2718 }
2719 }
2721 #ifndef HAVE_cc0
2722 /* If we have no I1 and I2 looks like:
2723 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2724 (set Y OP)])
2725 make up a dummy I1 that is
2726 (set Y OP)
2727 and change I2 to be
2728 (set (reg:CC X) (compare:CC Y (const_int 0)))
2730 (We can ignore any trailing CLOBBERs.)
2732 This undoes a previous combination and allows us to match a branch-and-
2733 decrement insn. */
2746 {
2752 {
2753 /* We make I1 with the same INSN_UID as I2. This gives it
2754 the same DF_INSN_LUID for value tracking. Our fake I1 will
2755 never appear in the insn stream so giving it the same INSN_UID
2756 as I2 will not cause a problem. */
2766 }
2767 }
2768 #endif
2770 /* Verify that I2 and I1 are valid for combining. */
2776 {
2779 }
2781 /* Record whether I2DEST is used in I2SRC and similarly for the other
2782 cases. Knowing this will help in register status updating below. */
2793 /* For the earlier insns, determine which of the subsequent ones they
2794 feed. */
2801 /* Ensure that I3's pattern can be the destination of combines. */
2807 {
2810 }
2812 /* See if any of the insns is a MULT operation. Unless one is, we will
2813 reject a combination that is, since it must be slower. Be conservative
2814 here. */
2822 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2823 We used to do this EXCEPT in one case: I3 has a post-inc in an
2824 output operand. However, that exception can give rise to insns like
2825 mov r3,(r3)+
2826 which is a famous insn on the PDP-11 where the value of r3 used as the
2827 source was model-dependent. Avoid this sort of thing. */
2829 #if 0
2835 /* It's not the exception. */
2836 #endif
2837 #ifdef AUTO_INC_DEC
2838 {
2839 rtx link;
2845 {
2848 }
2849 }
2850 #endif
2852 /* See if the SETs in I1 or I2 need to be kept around in the merged
2853 instruction: whenever the value set there is still needed past I3.
2854 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2856 For the SET in I1, we have two cases: if I1 and I2 independently feed
2857 into I3, the set in I1 needs to be kept around unless I1DEST dies
2858 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2859 in I1 needs to be kept around unless I1DEST dies or is set in either
2860 I2 or I3. The same considerations apply to I0. */
2867 else
2875 else
2878 /* We are about to copy insns for the case where they need to be kept
2879 around. Check that they can be copied in the merged instruction. */
2885 {
2888 }
2890 /* If the set in I2 needs to be kept around, we must make a copy of
2891 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2892 PATTERN (I2), we are only substituting for the original I1DEST, not into
2893 an already-substituted copy. This also prevents making self-referential
2894 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2895 I2DEST. */
2898 {
2901 else
2903 }
2906 {
2909 else
2911 }
2914 {
2917 else
2919 }
2921 combine_merges++;
2923 /* Substitute in the latest insn for the regs set by the earlier ones. */
2929 #ifndef HAVE_cc0
2930 /* Many machines that don't use CC0 have insns that can both perform an
2931 arithmetic operation and set the condition code. These operations will
2932 be represented as a PARALLEL with the first element of the vector
2933 being a COMPARE of an arithmetic operation with the constant zero.
2934 The second element of the vector will set some pseudo to the result
2935 of the same arithmetic operation. If we simplify the COMPARE, we won't
2936 match such a pattern and so will generate an extra insn. Here we test
2937 for this case, where both the comparison and the operation result are
2938 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2939 I2SRC. Later we will make the PARALLEL that contains I2. */
2945 {
2946 rtx newpat_dest;
2959 {
2964 }
2966 /* Do the rest only if op1 is const0_rtx, which may be the
2967 result of simplification. */
2969 {
2970 /* If a single use of the CC is found, prepare to modify it
2971 when SELECT_CC_MODE returns a new CC-class mode, or when
2972 the above simplify_compare_const() returned a new comparison
2973 operator. undobuf.other_insn is assigned the CC use insn
2974 when modifying it. */
2976 {
2977 #ifdef SELECT_CC_MODE
2978 enum machine_mode new_mode
2983 {
2988 else
2989 {
2992 }
2993 }
2994 #endif
2995 /* Cases for modifying the CC-using comparison. */
2997 /* ??? Do we need to verify the zero rtx? */
2999 {
3000 /* Replace cc_use_loc with entire new RTX. */
3005 }
3007 {
3008 /* Just replace the CC reg with a new mode. */
3011 }
3012 }
3014 /* Now we modify the current newpat:
3015 First, SET_DEST(newpat) is updated if the CC mode has been
3016 altered. For targets without SELECT_CC_MODE, this should be
3017 optimized away. */
3020 /* This is always done to propagate i2src into newpat. */
3023 /* Create new version of i2pat if needed; the below PARALLEL
3024 creation needs this to work correctly. */
3028 }
3029 }
3030 #endif
3033 {
3034 /* It is possible that the source of I2 or I1 may be performing
3035 an unneeded operation, such as a ZERO_EXTEND of something
3036 that is known to have the high part zero. Handle that case
3037 by letting subst look at the inner insns.
3039 Another way to do this would be to have a function that tries
3040 to simplify a single insn instead of merging two or more
3041 insns. We don't do this because of the potential of infinite
3042 loops and because of the potential extra memory required.
3043 However, doing it the way we are is a bit of a kludge and
3044 doesn't catch all cases.
3046 But only do this if -fexpensive-optimizations since it slows
3047 things down and doesn't usually win.
3049 This is not done in the COMPARE case above because the
3050 unmodified I2PAT is used in the PARALLEL and so a pattern
3051 with a modified I2SRC would not match. */
3054 {
3055 /* Pass pc_rtx so no substitutions are done, just
3056 simplifications. */
3058 {
3061 }
3065 }
3070 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3071 copy of I2SRC each time we substitute it, in order to avoid creating
3072 self-referential RTL when we will be substituting I1SRC for I1DEST
3073 later. Likewise if I0 feeds into I2, either directly or indirectly
3074 through I1, and I0DEST is in I0SRC. */
3081 /* Record whether I2's body now appears within I3's body. */
3083 }
3085 /* If we already got a failure, don't try to do more. Otherwise, try to
3086 substitute I1 if we have it. */
3089 {
3090 /* Check that an autoincrement side-effect on I1 has not been lost.
3091 This happens if I1DEST is mentioned in I2 and dies there, and
3092 has disappeared from the new pattern. */
3094 && i1_feeds_i2_n
3097 /* Before we can do this substitution, we must redo the test done
3098 above (see detailed comments there) that ensures I1DEST isn't
3099 mentioned in any SETs in NEWPAT that are field assignments. */
3102 {
3105 }
3110 /* If the following substitution will modify I1SRC, make a copy of it
3111 for the case where it is substituted for I1DEST in I2PAT later. */
3115 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3116 copy of I1SRC each time we substitute it, in order to avoid creating
3117 self-referential RTL when we will be substituting I0SRC for I0DEST
3118 later. */
3123 /* Record whether I1's body now appears within I3's body. */
3125 }
3127 /* Likewise for I0 if we have it. */
3130 {
3137 {
3140 }
3142 /* If the following substitution will modify I0SRC, make a copy of it
3143 for the case where it is substituted for I0DEST in I1PAT later. */
3146 /* And a copy for I0DEST in I2PAT substitution. */
3155 }
3157 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3158 to count all the ways that I2SRC and I1SRC can be used. */
3169 /* Fail if we tried to make a new register. */
3171 /* Fail if we couldn't do something and have a CLOBBER. */
3173 /* Fail if this new pattern is a MULT and we didn't have one before
3174 at the outer level. */
3177 {
3180 }
3182 /* If the actions of the earlier insns must be kept
3183 in addition to substituting them into the latest one,
3184 we must make a new PARALLEL for the latest insn
3185 to hold additional the SETs. */
3188 {
3190 combine_extras++;
3193 {
3199 }
3200 else
3201 {
3206 }
3212 {
3218 }
3220 {
3229 }
3230 }
3232 validate_replacement:
3234 /* Note which hard regs this insn has as inputs. */
3237 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3238 consider splitting this pattern, we might need these clobbers. */
3241 {
3247 }
3249 /* Is the result of combination a valid instruction? */
3252 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3253 the second SET's destination is a register that is unused and isn't
3254 marked as an instruction that might trap in an EH region. In that case,
3255 we just need the first SET. This can occur when simplifying a divmod
3256 insn. We *must* test for this case here because the code below that
3257 splits two independent SETs doesn't handle this case correctly when it
3258 updates the register status.
3260 It's pointless doing this if we originally had two sets, one from
3261 i3, and one from i2. Combining then splitting the parallel results
3262 in the original i2 again plus an invalid insn (which we delete).
3263 The net effect is only to move instructions around, which makes
3264 debug info less accurate.
3266 Also check the case where the first SET's destination is unused.
3267 That would not cause incorrect code, but does cause an unneeded
3268 insn to remain. */
3277 {
3287 {
3290 }
3299 {
3305 }
3306 }
3308 /* If we were combining three insns and the result is a simple SET
3309 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3310 insns. There are two ways to do this. It can be split using a
3311 machine-specific method (like when you have an addition of a large
3312 constant) or by combine in the function find_split_point. */
3316 {
3319 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3320 use I2DEST as a scratch register will help. In the latter case,
3321 convert I2DEST to the mode of the source of NEWPAT if we can. */
3325 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3326 inputs of NEWPAT. */
3328 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3329 possible to try that as a scratch reg. This would require adding
3330 more code to make it work though. */
3333 {
3336 /* First try to split using the original register as a
3337 scratch register. */
3341 i2dest)));
3344 /* If that didn't work, try changing the mode of I2DEST if
3345 we can. */
3350 {
3352 rtx ni2dest;
3356 else
3357 {
3360 }
3362 parallel = (gen_rtx_PARALLEL
3366 ni2dest))));
3371 {
3379 }
3380 }
3383 }
3385 /* If recog_for_combine has discarded clobbers, try to use them
3386 again for the split. */
3388 {
3391 }
3394 {
3399 }
3403 {
3413 /* If I2 or I3 has multiple SETs, we won't know how to track
3414 register status, so don't use these insns. If I2's destination
3415 is used between I2 and I3, we also can't use these insns. */
3425 /* It is possible that both insns now set the destination of I3.
3426 If so, we must show an extra use of it. */
3429 {
3447 }
3448 }
3450 /* If we can split it and use I2DEST, go ahead and see if that
3451 helps things be recognized. Verify that none of the registers
3452 are set between I2 and I3. */
3455 #ifdef HAVE_cc0
3457 #endif
3458 /* We need I2DEST in the proper mode. If it is a hard register
3459 or the only use of a pseudo, we can change its mode.
3460 Make sure we don't change a hard register to have a mode that
3461 isn't valid for it, or change the number of registers. */
3468 /* We can't overwrite I2DEST if its value is still used by
3469 NEWPAT. */
3471 {
3480 /* *SPLIT may be part of I2SRC, so make sure we have the
3481 original expression around for later debug processing.
3482 We should not need I2SRC any more in other cases. */
3485 else
3488 /* Get NEWDEST as a register in the proper mode. We have already
3489 validated that we can do this. */
3491 {
3494 else
3495 {
3498 }
3499 }
3501 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3502 an ASHIFT. This can occur if it was inside a PLUS and hence
3503 appeared to be a memory address. This is a kludge. */
3508 {
3511 /* Update split_code because we may not have a multiply
3512 anymore. */
3514 }
3516 #ifdef INSN_SCHEDULING
3517 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3518 be written as a ZERO_EXTEND. */
3520 {
3521 #ifdef LOAD_EXTEND_OP
3522 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3523 what it really is. */
3528 else
3529 #endif
3532 }
3533 #endif
3535 /* Attempt to split binary operators using arithmetic identities. */
3539 {
3546 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3548 {
3553 }
3554 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3561 {
3567 /* Split both "((X op Y) op X) op Y" and
3568 "((X op Y) op Y) op X" as "T op T" where T is
3569 "X op Y". */
3572 {
3578 }
3579 /* Split "((X op X) op Y) op Y)" as "T op T" where
3580 T is "X op Y". */
3582 {
3588 }
3589 }
3590 }
3593 {
3596 }
3600 /* recog_for_combine might have added CLOBBERs to newi2pat.
3601 Make sure NEWPAT does not depend on the clobbered regs. */
3605 {
3608 {
3611 }
3612 }
3614 /* If the split point was a MULT and we didn't have one before,
3615 don't use one now. */
3618 }
3619 }
3621 /* Check for a case where we loaded from memory in a narrow mode and
3622 then sign extended it, but we need both registers. In that case,
3623 we have a PARALLEL with both loads from the same memory location.
3624 We can split this into a load from memory followed by a register-register
3625 copy. This saves at least one insn, more if register allocation can
3626 eliminate the copy.
3628 We cannot do this if the destination of the first assignment is a
3629 condition code register or cc0. We eliminate this case by making sure
3630 the SET_DEST and SET_SRC have the same mode.
3632 We cannot do this if the destination of the second assignment is
3633 a register that we have already assumed is zero-extended. Similarly
3634 for a SUBREG of such a register. */
3669 {
3670 rtx ni2dest;
3684 }
3686 /* Similarly, check for a case where we have a PARALLEL of two independent
3687 SETs but we started with three insns. In this case, we can do the sets
3688 as two separate insns. This case occurs when some SET allows two
3689 other insns to combine, but the destination of that SET is still live. */
3706 {
3710 /* Normally, it doesn't matter which of the two is done first,
3711 but the one that references cc0 can't be the second, and
3712 one which uses any regs/memory set in between i2 and i3 can't
3713 be first. The PARALLEL might also have been pre-existing in i3,
3714 so we need to make sure that we won't wrongly hoist a SET to i2
3715 that would conflict with a death note present in there. */
3722 #ifdef HAVE_cc0
3724 #endif
3725 /* If I3 is a jump, ensure that set0 is a jump so that
3726 we do not create invalid RTL. */
3728 )
3729 {
3732 }
3739 #ifdef HAVE_cc0
3741 #endif
3742 /* If I3 is a jump, ensure that set1 is a jump so that
3743 we do not create invalid RTL. */
3745 )
3746 {
3749 }
3750 else
3751 {
3754 }
3759 {
3760 /* recog_for_combine might have added CLOBBERs to newi2pat.
3761 Make sure NEWPAT does not depend on the clobbered regs. */
3763 {
3766 {
3769 {
3772 }
3773 }
3774 }
3777 }
3778 }
3780 /* If it still isn't recognized, fail and change things back the way they
3781 were. */
3783 /* Is the result a reasonable ASM_OPERANDS? */
3785 {
3788 }
3790 /* If we had to change another insn, make sure it is valid also. */
3792 {
3800 {
3803 }
3804 }
3806 #ifdef HAVE_cc0
3807 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3808 they are adjacent to each other or not. */
3809 {
3813 {
3816 }
3817 }
3818 #endif
3820 /* Only allow this combination if insn_rtx_costs reports that the
3821 replacement instructions are cheaper than the originals. */
3823 {
3826 }
3829 {
3834 {
3839 /* Temporarily revert mode back. */
3843 {
3844 /* If we used i2dest as a scratch register with a
3845 different mode, substitute it for the original
3846 i2src while its original mode is temporarily
3847 restored, and then clear i2scratch so that we don't
3848 do it again later. */
3850 this_basic_block);
3852 /* Put back the new mode. */
3854 }
3855 else
3856 {
3861 {
3864 }
3865 else
3866 {
3873 }
3875 /* We're dealing with a reg that changed mode but not
3876 meaning, so we want to turn it into a subreg for
3877 the new mode. However, because of REG sharing and
3878 because its mode had already changed, we have to do
3879 it in two steps. First, replace any debug uses of
3880 reg, with its original mode temporarily restored,
3881 with this copy we have created; then, replace the
3882 copy with the SUBREG of the original shared reg,
3883 once again changed to the new mode. */
3885 this_basic_block);
3889 this_basic_block);
3890 }
3891 }
3892 }
3894 /* If we will be able to accept this, we have made a
3895 change to the destination of I3. This requires us to
3896 do a few adjustments. */
3899 {
3902 }
3904 /* We now know that we can do this combination. Merge the insns and
3905 update the status of registers and LOG_LINKS. */
3908 {
3913 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3914 ensure that they are still valid. Then add any non-duplicate
3915 notes added by recog_for_combine. */
3917 {
3927 }
3931 NULL_RTX);
3932 }
3935 {
3936 rtx insn;
3938 rtx ni2dest;
3940 /* I3 now uses what used to be its destination and which is now
3941 I2's destination. This requires us to do a few adjustments. */
3945 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3946 so we still will.
3948 However, some later insn might be using I2's dest and have
3949 a LOG_LINK pointing at I3. We must remove this link.
3950 The simplest way to remove the link is to point it at I1,
3951 which we know will be a NOTE. */
3953 /* newi2pat is usually a SET here; however, recog_for_combine might
3954 have added some clobbers. */
3957 else
3964 {
3966 {
3972 }
3973 }
3974 }
3976 {
3981 /* Compute which registers we expect to eliminate. newi2pat may be setting
3982 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3983 same as i3dest, in which case newi2pat may be setting i1dest. */
3986 || !i2dest_killed
3990 || !i1dest_killed
3994 || !i0dest_killed
3997 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3998 clear them. */
4006 /* Ensure that we do not have something that should not be shared but
4007 occurs multiple times in the new insns. Check this by first
4008 resetting all the `used' flags and then copying anything is shared. */
4032 {
4039 {
4040 /* I2SRC must still be meaningful at this point. Some splitting
4041 operations can invalidate I2SRC, but those operations do not
4042 apply to calls. */
4045 }
4053 }
4058 /* We had one special case above where I2 had more than one set and
4059 we replaced a destination of one of those sets with the destination
4060 of I3. In that case, we have to update LOG_LINKS of insns later
4061 in this basic block. Note that this (expensive) case is rare.
4063 Also, in this case, we must pretend that all REG_NOTEs for I2
4064 actually came from I3, so that REG_UNUSED notes from I2 will be
4065 properly handled. */
4068 {
4077 temp
4087 {
4092 }
4093 else
4096 }
4104 {
4107 this_basic_block);
4110 }
4111 else
4112 {
4115 this_basic_block);
4117 }
4120 {
4125 this_basic_block);
4127 }
4130 {
4135 this_basic_block);
4137 }
4139 /* Get death notes for everything that is now used in either I3 or
4140 I2 and used to die in a previous insn. If we built two new
4141 patterns, move from I1 to I2 then I2 to I3 so that we get the
4142 proper movement on registers that I2 modifies. */
4148 else
4154 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4171 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4172 know these are REG_UNUSED and want them to go to the desired insn,
4173 so we always pass it as i3. */
4177 NULL_RTX);
4181 NULL_RTX);
4183 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4184 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4185 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4186 in that case, it might delete I2. Similarly for I2 and I1.
4187 Show an additional death due to the REG_DEAD note we make here. If
4188 we discard it in distribute_notes, we will decrement it again. */
4191 {
4196 else
4199 }
4202 {
4207 else
4210 }
4213 {
4218 else
4221 }
4224 {
4229 else
4232 }
4240 {
4244 /* The insn that used to set this register doesn't exist, and
4245 this life of the register may not exist either. See if one of
4246 I3's links points to an insn that sets I2DEST. If it does,
4247 that is now the last known value for I2DEST. If we don't update
4248 this and I2 set the register to a value that depended on its old
4249 contents, we will get confused. If this insn is used, thing
4250 will be set correctly in combine_instructions. */
4258 /* If the reg formerly set in I2 died only once and that was in I3,
4259 zero its use count so it won't make `reload' do any work. */
4264 }
4267 {
4280 }
4283 {
4296 }
4298 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4299 been made to this insn. The order is important, because newi2pat
4300 can affect nonzero_bits of newpat. */
4304 }
4307 {
4309 {
4312 }
4314 }
4317 {
4319 {
4322 }
4324 }
4327 {
4329 {
4332 }
4334 }
4337 {
4339 {
4342 }
4344 }
4347 {
4349 {
4352 }
4354 }
4356 /* Set new_direct_jump_p if a new return or simple jump instruction
4357 has been created. Adjust the CFG accordingly. */
4359 {
4363 }
4368 {
4371 }
4373 /* A noop might also need cleaning up of CFG, if it comes from the
4374 simplification of a jump. */
4379 {
4382 }
4389 {
4392 }
4394 combine_successes++;
4401 else
4403 }
4404 \f
4405 /* Undo all the modifications recorded in undobuf. */
4407 static void
4409 {
4413 {
4416 {
4431 }
4435 }
4438 }
4440 /* We've committed to accepting the changes we made. Move all
4441 of the undos to the free list. */
4443 static void
4445 {
4449 {
4453 }
4455 }
4456 \f
4457 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4458 where we have an arithmetic expression and return that point. LOC will
4459 be inside INSN.
4461 try_combine will call this function to see if an insn can be split into
4462 two insns. */
4466 {
4475 /* First special-case some codes. */
4477 {
4479 #ifdef INSN_SCHEDULING
4480 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4481 point. */
4484 #endif
4488 #ifdef HAVE_lo_sum
4489 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4490 using LO_SUM and HIGH. */
4493 {
4501 }
4502 #endif
4504 /* If we have a PLUS whose second operand is a constant and the
4505 address is not valid, perhaps will can split it up using
4506 the machine-specific way to split large constants. We use
4507 the first pseudo-reg (one of the virtual regs) as a placeholder;
4508 it will not remain in the result. */
4513 {
4517 subst_insn);
4519 /* This should have produced two insns, each of which sets our
4520 placeholder. If the source of the second is a valid address,
4521 we can make put both sources together and make a split point
4522 in the middle. */
4535 && memory_address_addr_space_p
4538 {
4542 /* Replace the placeholder in SRC2 with SRC1. If we can
4543 find where in SRC2 it was placed, that can become our
4544 split point and we can replace this address with SRC2.
4545 Just try two obvious places. */
4556 {
4559 }
4560 }
4562 /* If that didn't work, perhaps the first operand is complex and
4563 needs to be computed separately, so make a split point there.
4564 This will occur on machines that just support REG + CONST
4565 and have a constant moved through some previous computation. */
4571 }
4573 /* If we have a PLUS whose first operand is complex, try computing it
4574 separately by making a split there. */
4585 #ifdef HAVE_cc0
4586 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4587 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4588 we need to put the operand into a register. So split at that
4589 point. */
4598 #endif
4600 /* See if we can split SET_SRC as it stands. */
4605 /* See if we can split SET_DEST as it stands. */
4610 /* See if this is a bitfield assignment with everything constant. If
4611 so, this is an IOR of an AND, so split it into that. */
4621 {
4627 unsigned HOST_WIDE_INT mask
4629 rtx or_mask;
4638 else
4639 {
4645 or_mask));
4646 }
4653 }
4655 /* Otherwise, see if this is an operation that we can split into two.
4656 If so, try to split that. */
4660 {
4662 /* If we are AND'ing with a large constant that is only a single
4663 bit and the result is only being used in a context where we
4664 need to know if it is zero or nonzero, replace it with a bit
4665 extraction. This will avoid the large constant, which might
4666 have taken more than one insn to make. If the constant were
4667 not a valid argument to the AND but took only one insn to make,
4668 this is no worse, but if it took more than one insn, it will
4669 be better. */
4679 {
4684 {
4687 }
4688 }
4692 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4693 is known to be on, this can be converted into a NEG of a shift. */
4699 {
4711 }
4717 /* We can't optimize if either mode is a partial integer
4718 mode as we don't know how many bits are significant
4719 in those modes. */
4733 {
4741 }
4746 }
4750 {
4753 /* For unsigned, we have a choice of a shift followed by an
4754 AND or two shifts. Use two shifts for field sizes where the
4755 constant might be too large. We assume here that we can
4756 always at least get 8-bit constants in an AND insn, which is
4757 true for every current RISC. */
4760 {
4761 unsigned HOST_WIDE_INT mask
4765 gen_rtx_LSHIFTRT
4773 }
4774 else
4775 {
4777 gen_rtx_fmt_ee
4788 }
4789 }
4791 /* See if this is a simple operation with a constant as the second
4792 operand. It might be that this constant is out of range and hence
4793 could be used as a split point. */
4801 /* Finally, see if this is a simple operation with its first operand
4802 not in a register. The operation might require this operand in a
4803 register, so return it as a split point. We can always do this
4804 because if the first operand were another operation, we would have
4805 already found it as a split point. */
4814 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4815 it is better to write this as (not (ior A B)) so we can split it.
4816 Similarly for IOR. */
4818 {
4826 }
4828 /* Many RISC machines have a large set of logical insns. If the
4829 second operand is a NOT, put it first so we will try to split the
4830 other operand first. */
4832 {
4836 }
4841 /* Canonicalization can produce (minus A (mult B C)), where C is a
4842 constant. It may be better to try splitting (plus (mult B -C) A)
4843 instead if this isn't a multiply by a power of two. */
4847 {
4855 mode)),
4858 }
4860 /* Split at a multiply-accumulate instruction. However if this is
4861 the SET_SRC, we likely do not have such an instruction and it's
4862 worthless to try this split. */
4868 }
4870 /* Otherwise, select our actions depending on our rtx class. */
4872 {
4878 /* ... fall through ... */
4886 /* ... fall through ... */
4888 /* Some machines have (and (shift ...) ...) insns. If X is not
4889 an AND, but XEXP (X, 0) is, use it as our split point. */
4899 /* Otherwise, we don't have a split point. */
4901 }
4902 }
4903 \f
4904 /* Throughout X, replace FROM with TO, and return the result.
4905 The result is TO if X is FROM;
4906 otherwise the result is X, but its contents may have been modified.
4907 If they were modified, a record was made in undobuf so that
4908 undo_all will (among other things) return X to its original state.
4910 If the number of changes necessary is too much to record to undo,
4911 the excess changes are not made, so the result is invalid.
4912 The changes already made can still be undone.
4913 undobuf.num_undo is incremented for such changes, so by testing that
4914 the caller can tell whether the result is valid.
4916 `n_occurrences' is incremented each time FROM is replaced.
4918 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4920 IN_COND is nonzero if we are at the top level of a condition.
4922 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4923 by copying if `n_occurrences' is nonzero. */
4925 static rtx
4927 {
4932 rtx new_rtx;
4934 /* Two expressions are equal if they are identical copies of a shared
4935 RTX or if they are both registers with the same register number
4936 and mode. */
4938 #define COMBINE_RTX_EQUAL_P(X,Y) \
4939 ((X) == (Y) \
4940 || (REG_P (X) && REG_P (Y) \
4941 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4944 {
4945 n_occurrences++;
4947 }
4949 /* If X and FROM are the same register but different modes, they
4950 will not have been seen as equal above. However, the log links code
4951 will make a LOG_LINKS entry for that case. If we do nothing, we
4952 will try to rerecognize our original insn and, when it succeeds,
4953 we will delete the feeding insn, which is incorrect.
4955 So force this insn not to match in this (rare) case. */
4960 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4961 of which may contain things that can be combined. */
4965 /* It is possible to have a subexpression appear twice in the insn.
4966 Suppose that FROM is a register that appears within TO.
4967 Then, after that subexpression has been scanned once by `subst',
4968 the second time it is scanned, TO may be found. If we were
4969 to scan TO here, we would find FROM within it and create a
4970 self-referent rtl structure which is completely wrong. */
4974 /* Parallel asm_operands need special attention because all of the
4975 inputs are shared across the arms. Furthermore, unsharing the
4976 rtl results in recognition failures. Failure to handle this case
4977 specially can result in circular rtl.
4979 Solve this by doing a normal pass across the first entry of the
4980 parallel, and only processing the SET_DESTs of the subsequent
4981 entries. Ug. */
4986 {
4989 /* If this substitution failed, this whole thing fails. */
4997 {
5003 {
5006 /* If this substitution failed, this whole thing fails. */
5012 }
5013 }
5014 }
5015 else
5016 {
5020 /* We don't need to process a SET_DEST that is a register, CC0,
5021 or PC, so set up to skip this common case. All other cases
5022 where we want to suppress replacing something inside a
5023 SET_SRC are handled via the IN_DEST operand. */
5030 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5031 constant. */
5036 {
5038 {
5041 {
5043 {
5046 n_occurrences++;
5047 }
5048 else
5049 {
5051 unique_copy);
5053 /* If this substitution failed, this whole thing
5054 fails. */
5058 }
5061 }
5062 }
5064 {
5065 /* If this is a register being set, ignore it. */
5072 ;
5075 {
5076 /* In general, don't install a subreg involving two
5077 modes not tieable. It can worsen register
5078 allocation, and can even make invalid reload
5079 insns, since the reg inside may need to be copied
5080 from in the outside mode, and that may be invalid
5081 if it is an fp reg copied in integer mode.
5083 We allow two exceptions to this: It is valid if
5084 it is inside another SUBREG and the mode of that
5085 SUBREG and the mode of the inside of TO is
5086 tieable and it is valid if X is a SET that copies
5087 FROM to CC0. */
5095 #ifdef HAVE_cc0
5097 #endif
5098 )
5101 #ifdef CANNOT_CHANGE_MODE_CLASS
5109 #endif
5112 n_occurrences++;
5113 }
5114 else
5115 /* If we are in a SET_DEST, suppress most cases unless we
5116 have gone inside a MEM, in which case we want to
5117 simplify the address. We assume here that things that
5118 are actually part of the destination have their inner
5119 parts in the first expression. This is true for SUBREG,
5120 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5121 things aside from REG and MEM that should appear in a
5122 SET_DEST. */
5124 (((in_dest
5130 unique_copy);
5132 /* If we found that we will have to reject this combination,
5133 indicate that by returning the CLOBBER ourselves, rather than
5134 an expression containing it. This will speed things up as
5135 well as prevent accidents where two CLOBBERs are considered
5136 to be equal, thus producing an incorrect simplification. */
5142 {
5150 }
5153 {
5157 }
5158 else
5160 }
5161 }
5162 }
5164 /* Check if we are loading something from the constant pool via float
5165 extension; in this case we would undo compress_float_constant
5166 optimization and degenerate constant load to an immediate value. */
5170 {
5174 }
5176 /* Try to simplify X. If the simplification changed the code, it is likely
5177 that further simplification will help, so loop, but limit the number
5178 of repetitions that will be performed. */
5181 {
5182 /* If X is sufficiently simple, don't bother trying to do anything
5183 with it. */
5192 /* We no longer know the original mode of operand 0 since we
5193 have changed the form of X) */
5195 }
5198 }
5199 \f
5200 /* Simplify X, a piece of RTL. We just operate on the expression at the
5201 outer level; call `subst' to simplify recursively. Return the new
5202 expression.
5204 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5205 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5206 of a condition. */
5208 static rtx
5211 {
5214 rtx temp;
5217 /* If this is a commutative operation, put a constant last and a complex
5218 expression first. We don't need to do this for comparisons here. */
5221 {
5225 }
5227 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5228 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5229 things. Check for cases where both arms are testing the same
5230 condition.
5232 Don't do anything if all operands are very simple. */
5245 {
5250 /* If everything is a comparison, what we have is highly unlikely
5251 to be simpler, so don't use it. */
5254 {
5261 /* Simplify the alternative arms; this may collapse the true and
5262 false arms to store-flag values. Be careful to use copy_rtx
5263 here since true_rtx or false_rtx might share RTL with x as a
5264 result of the if_then_else_cond call above. */
5268 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5269 is unlikely to be simpler. */
5272 {
5275 /* Restarting if we generate a store-flag expression will cause
5276 us to loop. Just drop through in this case. */
5278 /* If the result values are STORE_FLAG_VALUE and zero, we can
5279 just make the comparison operation. */
5290 /* Likewise, we can make the negate of a comparison operation
5291 if the result values are - STORE_FLAG_VALUE and zero. */
5299 mode);
5310 mode);
5311 else
5314 mode,
5315 VOIDmode,
5316 cond,
5317 cop1),
5322 }
5323 }
5324 }
5326 /* Try to fold this expression in case we have constants that weren't
5327 present before. */
5330 {
5338 {
5341 {
5345 }
5348 }
5361 }
5364 {
5369 }
5371 /* First see if we can apply the inverse distributive law. */
5374 {
5378 }
5380 /* If CODE is an associative operation not otherwise handled, see if we
5381 can associate some operands. This can win if they are constants or
5382 if they are logically related (i.e. (a & b) & a). */
5388 {
5390 {
5394 rtx inner;
5396 /* Make sure we pass the constant operand if any as the second
5397 one if this is a commutative operation. */
5399 {
5403 }
5409 /* For commutative operations, try the other pair if that one
5410 didn't simplify. */
5412 {
5417 }
5421 }
5422 }
5424 /* A little bit of algebraic simplification here. */
5426 {
5428 /* Ensure that our address has any ASHIFTs converted to MULT in case
5429 address-recognizing predicates are called later. */
5438 /* See if this can be moved to simplify_subreg. */
5441 /* Don't call gen_lowpart if the inner mode
5442 is VOIDmode and we cannot simplify it, as SUBREG without
5443 inner mode is invalid. */
5450 {
5451 rtx temp;
5457 /* If op is known to have all lower bits zero, the result is zero. */
5467 }
5469 /* Don't change the mode of the MEM if that would change the meaning
5470 of the address. */
5477 /* Note that we cannot do any narrowing for non-constants since
5478 we might have been counting on using the fact that some bits were
5479 zero. We now do this in the SET. */
5486 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5487 replaced by (lshiftrt X C). This will convert
5488 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5496 /* If X has only a single bit that might be nonzero, say, bit I, convert
5497 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5498 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5499 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5500 or a SUBREG of one since we'd be making the expression more
5501 complex if it was just a register. */
5507 {
5508 rtx temp1 = simplify_shift_const
5514 /* If all we did was surround TEMP with the two shifts, we
5515 haven't improved anything, so don't use it. Otherwise,
5516 we are better off with TEMP1. */
5521 }
5525 /* We can't handle truncation to a partial integer mode here
5526 because we don't know the real bitsize of the partial
5527 integer mode. */
5536 /* We can truncate a constant value and return it. */
5540 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5541 whose value is a comparison can be replaced with a subreg if
5542 STORE_FLAG_VALUE permits. */
5551 /* (const (const X)) can become (const X). Do it this way rather than
5552 returning the inner CONST since CONST can be shared with a
5553 REG_EQUAL note. */
5558 #ifdef HAVE_lo_sum
5560 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5561 can add in an offset. find_split_point will split this address up
5562 again if it doesn't match. */
5567 #endif
5570 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5571 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5572 bit-field and can be replaced by either a sign_extend or a
5573 sign_extract. The `and' may be a zero_extend and the two
5574 <c>, -<c> constants may be reversed. */
5589 return simplify_shift_const
5596 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5597 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5598 the bitsize of the mode - 1. This allows simplification of
5599 "a = (b & 8) == 0;" */
5611 /* If we are adding two things that have no bits in common, convert
5612 the addition into an IOR. This will often be further simplified,
5613 for example in cases like ((a & 1) + (a & 2)), which can
5614 become a & 3. */
5619 {
5620 /* Try to simplify the expression further. */
5624 /* If we could, great. If not, do not go ahead with the IOR
5625 replacement, since PLUS appears in many special purpose
5626 address arithmetic instructions. */
5634 }
5638 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5639 (and <foo> (const_int pow2-1)) */
5649 /* If we have (mult (plus A B) C), apply the distributive law and then
5650 the inverse distributive law to see if things simplify. This
5651 occurs mostly in addresses, often when unrolling loops. */
5654 {
5658 }
5660 /* Try simplify a*(b/c) as (a*b)/c. */
5663 {
5669 }
5673 /* If this is a divide by a power of two, treat it as a shift if
5674 its first operand is a shift. */
5692 /* If the first operand is a condition code, we can't do anything
5693 with it. */
5697 {
5705 /* Simplify our comparison, if possible. */
5708 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5709 if only the low-order bit is possibly nonzero in X (such as when
5710 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5711 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5712 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5713 (plus X 1).
5715 Remove any ZERO_EXTRACT we made when thinking this was a
5716 comparison. It may now be simpler to use, e.g., an AND. If a
5717 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5718 the call to make_compound_operation in the SET case.
5720 Don't apply these optimizations if the caller would
5721 prefer a comparison rather than a value.
5722 E.g., for the condition in an IF_THEN_ELSE most targets need
5723 an explicit comparison. */
5726 ;
5742 {
5746 mode);
5747 }
5754 {
5758 const1_rtx);
5759 }
5767 {
5770 }
5772 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5773 those above. */
5775 ;
5790 {
5794 mode);
5795 }
5803 {
5807 mode);
5808 }
5810 /* If X is 0/1, (eq X 0) is X-1. */
5816 {
5819 }
5821 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5822 one bit that might be nonzero, we can convert (ne x 0) to
5823 (ashift x c) where C puts the bit in the sign bit. Remove any
5824 AND with STORE_FLAG_VALUE when we are done, since we are only
5825 going to test the sign bit. */
5832 {
5838 else
5840 }
5842 /* If the code changed, return a whole new comparison.
5843 We also need to avoid using SUBST in cases where
5844 simplify_comparison has widened a comparison with a CONST_INT,
5845 since in that case the wider CONST_INT may fail the sanity
5846 checks in do_SUBST. */
5853 /* Otherwise, keep this operation, but maybe change its operands.
5854 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5857 }
5867 /* If we are processing SET_DEST, we are done. */
5885 /* If this is a shift by a constant amount, simplify it. */
5901 }
5904 }
5905 \f
5906 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5908 static rtx
5910 {
5917 rtx temp;
5920 rtx reversed;
5922 /* Simplify storing of the truth value. */
5927 /* Also when the truth value has to be reversed. */
5933 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5934 in it is being compared against certain values. Get the true and false
5935 comparisons and see if that says anything about the value of each arm. */
5941 {
5942 HOST_WIDE_INT nzb;
5948 /* If FALSE_CODE is EQ, swap the codes and arms. */
5951 {
5954 }
5956 /* If we are comparing against zero and the expression being tested has
5957 only a single bit that might be nonzero, that is its value when it is
5958 not equal to zero. Similarly if it is known to be -1 or 0. */
5962 {
5965 }
5969 {
5972 }
5974 /* Now simplify an arm if we know the value of the register in the
5975 branch and it is used in the arm. Be careful due to the potential
5976 of locally-shared RTL. */
5993 }
5995 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5996 reversed, do so to avoid needing two sets of patterns for
5997 subtract-and-branch insns. Similarly if we have a constant in the true
5998 arm, the false arm is the same as the first operand of the comparison, or
5999 the false arm is more complicated than the true arm. */
6012 {
6021 /* It is possible that the conditional has been simplified out. */
6024 }
6026 /* If the two arms are identical, we don't need the comparison. */
6031 /* Convert a == b ? b : a to "a". */
6043 /* Look for cases where we have (abs x) or (neg (abs X)). */
6046 && comparison_p
6053 {
6059 return
6062 mode);
6065 }
6067 /* Look for MIN or MAX. */
6070 && comparison_p
6075 {
6090 }
6092 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6093 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6094 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6095 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6096 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6097 neither 1 or -1, but it isn't worth checking for. */
6100 && comparison_p
6103 {
6119 /* If an identity-zero op is commutative, check whether there
6120 would be a match if we swapped the operands. */
6140 {
6144 }
6156 {
6160 }
6176 {
6180 }
6192 {
6196 }
6199 {
6205 const_true_rtx));
6213 }
6214 }
6216 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6217 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6218 negation of a single bit, we can convert this operation to a shift. We
6219 can actually do this more generally, but it doesn't seem worth it. */
6228 return
6232 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6242 }
6243 \f
6244 /* Simplify X, a SET expression. Return the new expression. */
6246 static rtx
6248 {
6251 enum machine_mode mode
6253 rtx other_insn;
6256 /* (set (pc) (return)) gets written as (return). */
6260 /* Now that we know for sure which bits of SRC we are using, see if we can
6261 simplify the expression for the object knowing that we only need the
6262 low-order bits. */
6265 {
6268 }
6270 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6271 the comparison result and try to simplify it unless we already have used
6272 undobuf.other_insn. */
6280 {
6289 {
6292 {
6295 }
6296 }
6297 else
6305 {
6309 }
6310 else
6311 {
6316 /* Attempt to simplify CC user. */
6318 {
6322 }
6324 /* Convert X into a no-op move. */
6328 }
6330 /* Simplify our comparison, if possible. */
6333 #ifdef SELECT_CC_MODE
6334 /* If this machine has CC modes other than CCmode, check to see if we
6335 need to use a different CC mode here. */
6344 else
6347 #ifndef HAVE_cc0
6348 /* If the mode changed, we have to change SET_DEST, the mode in the
6349 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6350 a hard register, just build new versions with the proper mode. If it
6351 is a pseudo, we lose unless it is only time we set the pseudo, in
6352 which case we can safely change its mode. */
6354 {
6356 {
6358 rtx new_dest;
6362 else
6363 {
6366 }
6373 }
6374 }
6378 /* If the code changed, we have to build a new comparison in
6379 undobuf.other_insn. */
6381 {
6390 /* If the only change we made was to change an EQ into an NE or
6391 vice versa, OP0 has only one bit that might be nonzero, and OP1
6392 is zero, check if changing the user of the condition code will
6393 produce a valid insn. If it won't, we can keep the original code
6394 in that insn by surrounding our operation with an XOR. */
6401 {
6406 {
6413 }
6414 }
6415 }
6420 /* Otherwise, if we didn't previously have a COMPARE in the
6421 correct mode, we need one. */
6423 {
6426 }
6428 {
6431 }
6432 /* Otherwise, update the COMPARE if needed. */
6434 {
6437 }
6438 }
6439 else
6440 {
6441 /* Get SET_SRC in a form where we have placed back any
6442 compound expressions. Then do the checks below. */
6445 }
6447 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6448 and X being a REG or (subreg (reg)), we may be able to convert this to
6449 (set (subreg:m2 x) (op)).
6451 We can always do this if M1 is narrower than M2 because that means that
6452 we only care about the low bits of the result.
6454 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6455 perform a narrower operation than requested since the high-order bits will
6456 be undefined. On machine where it is defined, this transformation is safe
6457 as long as M1 and M2 have the same number of words. */
6465 #ifndef WORD_REGISTER_OPERATIONS
6468 #endif
6469 #ifdef CANNOT_CHANGE_MODE_CLASS
6474 #endif
6478 {
6481 dest));
6485 }
6487 #ifdef HAVE_cc0
6488 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6489 in SRC. */
6495 {
6499 /* Here we make sure that we don't have a sign bit on. */
6502 {
6505 }
6506 }
6507 #endif
6509 #ifdef LOAD_EXTEND_OP
6510 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6511 would require a paradoxical subreg. Replace the subreg with a
6512 zero_extend to avoid the reload that would otherwise be required. */
6520 {
6526 }
6527 #endif
6529 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6530 are comparing an item known to be 0 or -1 against 0, use a logical
6531 operation instead. Check for one of the arms being an IOR of the other
6532 arm with some value. We compute three terms to be IOR'ed together. In
6533 practice, at most two will be nonzero. Then we do the IOR's. */
6541 #ifdef HAVE_conditional_move
6543 #endif
6548 {
6574 false_rtx);
6580 term3));
6583 }
6585 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6586 whole thing fail. */
6591 else
6592 /* Convert this into a field assignment operation, if possible. */
6594 }
6595 \f
6596 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6597 result. */
6599 static rtx
6601 {
6607 {
6609 /* We can call simplify_and_const_int only if we don't lose
6610 any (sign) bits when converting INTVAL (op1) to
6611 "unsigned HOST_WIDE_INT". */
6615 {
6622 }
6624 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6625 apply the distributive law and then the inverse distributive
6626 law to see if things simplify. */
6628 {
6632 }
6634 {
6638 }
6642 /* If we have (ior (and A B) C), apply the distributive law and then
6643 the inverse distributive law to see if things simplify. */
6646 {
6650 }
6653 {
6657 }
6662 }
6665 }
6666 \f
6667 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6668 operations" because they can be replaced with two more basic operations.
6669 ZERO_EXTEND is also considered "compound" because it can be replaced with
6670 an AND operation, which is simpler, though only one operation.
6672 The function expand_compound_operation is called with an rtx expression
6673 and will convert it to the appropriate shifts and AND operations,
6674 simplifying at each stage.
6676 The function make_compound_operation is called to convert an expression
6677 consisting of shifts and ANDs into the equivalent compound expression.
6678 It is the inverse of this function, loosely speaking. */
6680 static rtx
6682 {
6686 rtx tem;
6689 {
6693 /* We can't necessarily use a const_int for a multiword mode;
6694 it depends on implicitly extending the value.
6695 Since we don't know the right way to extend it,
6696 we can't tell whether the implicit way is right.
6698 Even for a mode that is no wider than a const_int,
6699 we can't win, because we need to sign extend one of its bits through
6700 the rest of it, and we don't know which bit. */
6704 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6705 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6706 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6707 reloaded. If not for that, MEM's would very rarely be safe.
6709 Reject MODEs bigger than a word, because we might not be able
6710 to reference a two-register group starting with an arbitrary register
6711 (and currently gen_lowpart might crash for a SUBREG). */
6716 /* Reject MODEs that aren't scalar integers because turning vector
6717 or complex modes into shifts causes problems. */
6723 /* If the inner object has VOIDmode (the only way this can happen
6724 is if it is an ASM_OPERANDS), we can't do anything since we don't
6725 know how much masking to do. */
6734 /* ... fall through ... */
6737 /* If the operand is a CLOBBER, just return it. */
6746 /* Reject MODEs that aren't scalar integers because turning vector
6747 or complex modes into shifts causes problems. */
6755 /* This should stay within the object being extracted, fail otherwise. */
6766 }
6767 /* Convert sign extension to zero extension, if we know that the high
6768 bit is not set, as this is easier to optimize. It will be converted
6769 back to cheaper alternative in make_extraction. */
6777 {
6781 /* Make sure this is a profitable operation. */
6788 else
6790 }
6792 /* We can optimize some special cases of ZERO_EXTEND. */
6794 {
6795 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6796 know that the last value didn't have any inappropriate bits
6797 set. */
6805 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6814 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6815 is a comparison and STORE_FLAG_VALUE permits. This is like
6816 the first case, but it works even when GET_MODE (x) is larger
6817 than HOST_WIDE_INT. */
6826 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6836 }
6838 /* If we reach here, we want to return a pair of shifts. The inner
6839 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6840 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6841 logical depending on the value of UNSIGNEDP.
6843 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6844 converted into an AND of a shift.
6846 We must check for the case where the left shift would have a negative
6847 count. This can happen in a case like (x >> 31) & 255 on machines
6848 that can't shift by a constant. On those machines, we would first
6849 combine the shift with the AND to produce a variable-position
6850 extraction. Then the constant of 31 would be substituted in
6851 to produce such a position. */
6855 {
6864 }
6871 else
6872 /* Any other cases we can't handle. */
6875 /* If we couldn't do this for some reason, return the original
6876 expression. */
6881 }
6882 \f
6883 /* X is a SET which contains an assignment of one object into
6884 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6885 or certain SUBREGS). If possible, convert it into a series of
6886 logical operations.
6888 We half-heartedly support variable positions, but do not at all
6889 support variable lengths. */
6891 static const_rtx
6893 {
6894 rtx inner;
6900 /* Loop until we find something we can't simplify. */
6902 {
6905 {
6909 }
6912 {
6917 /* A constant position should stay within the width of INNER. */
6923 {
6931 /* If position is ADJUST - X, new position is X. */
6933 else
6934 {
6939 pos);
6940 }
6941 }
6942 }
6944 /* A SUBREG between two modes that occupy the same numbers of words
6945 can be done by moving the SUBREG to the source. */
6947 /* We need SUBREGs to compute nonzero_bits properly. */
6948 && nonzero_sign_valid
6953 {
6955 gen_lowpart
6959 }
6960 else
6968 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6970 {
6973 /* Don't do anything for vector or complex integral types. */
6977 /* Try to find an integral mode to pun with. */
6984 }
6986 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6990 /* Now compute the equivalent expression. Make a copy of INNER
6991 for the SET_DEST in case it is a MEM into which we will substitute;
6992 we don't want shared RTL in that case. */
6994 compute_mode);
6998 compute_mode,
7000 compute_mode),
7001 inner);
7006 mask),
7007 pos);
7012 }
7015 }
7016 \f
7017 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7018 it is an RTX that represents the (variable) starting position; otherwise,
7019 POS is the (constant) starting bit position. Both are counted from the LSB.
7021 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7023 IN_DEST is nonzero if this is a reference in the destination of a SET.
7024 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7025 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7026 be used.
7028 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7029 ZERO_EXTRACT should be built even for bits starting at bit 0.
7031 MODE is the desired mode of the result (if IN_DEST == 0).
7033 The result is an RTX for the extraction or NULL_RTX if the target
7034 can't handle it. */
7036 static rtx
7040 {
7041 /* This mode describes the size of the storage area
7042 to fetch the overall value from. Within that, we
7043 ignore the POS lowest bits, etc. */
7053 HOST_WIDE_INT orig_pos;
7059 {
7060 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7061 consider just the QI as the memory to extract from.
7062 The subreg adds or removes high bits; its mode is
7063 irrelevant to the meaning of this extraction,
7064 since POS and LEN count from the lsb. */
7068 }
7073 {
7074 /* We're extracting the least significant bits of an rtx
7075 (ashift X (const_int C)), where LEN > C. Extract the
7076 least significant (LEN - C) bits of X, giving an rtx
7077 whose mode is MODE, then shift it left C times. */
7083 }
7089 /* See if this can be done without an extraction. We never can if the
7090 width of the field is not the same as that of some integer mode. For
7091 registers, we can only avoid the extraction if the position is at the
7092 low-order bit and this is either not in the destination or we have the
7093 appropriate STRICT_LOW_PART operation available.
7095 For MEM, we can avoid an extract if the field starts on an appropriate
7096 boundary and we can change the mode of the memory reference. */
7105 && (! in_dest
7109 && (pos
7112 /* We can't do this if we are widening INNER_MODE (it
7113 may not be aligned, for one thing). */
7119 {
7120 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7121 field. If the original and current mode are the same, we need not
7122 adjust the offset. Otherwise, we do if bytes big endian.
7124 If INNER is not a MEM, get a piece consisting of just the field
7125 of interest (in this case POS % BITS_PER_WORD must be 0). */
7128 {
7129 HOST_WIDE_INT offset;
7131 /* POS counts from lsb, but make OFFSET count in memory order. */
7134 else
7138 }
7140 {
7142 {
7143 /* We can't call gen_lowpart in a DEST since we
7144 always want a SUBREG (see below) and it would sometimes
7145 return a new hard register. */
7147 {
7162 /* Avoid creating invalid subregs, for example when
7163 simplifying (x>>32)&255. */
7168 }
7169 else
7171 }
7172 else
7174 }
7175 else
7177 len >= HOST_BITS_PER_WIDE_INT
7182 /* If this extraction is going into the destination of a SET,
7183 make a STRICT_LOW_PART unless we made a MEM. */
7198 /* If we know that no extraneous bits are set, and that the high
7199 bit is not set, convert the extraction to the cheaper of
7200 sign and zero extension, that are equivalent in these cases. */
7206 {
7210 /* Prefer ZERO_EXTENSION, since it gives more information to
7211 backends. */
7216 }
7218 /* Otherwise, sign- or zero-extend unless we already are in the
7219 proper mode. */
7223 }
7225 /* Unless this is a COMPARE or we have a funny memory reference,
7226 don't do anything with zero-extending field extracts starting at
7227 the low-order bit since they are simple AND operations. */
7232 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7233 if the position is not a constant and the length is not 1. In all
7234 other cases, we would only be going outside our object in cases when
7235 an original shift would have been undefined. */
7244 /* If INNER is not from memory, we want it to have the mode of a register
7245 extraction pattern's structure operand, or word_mode if there is no
7246 such pattern. The same applies to extraction_mode and pos_mode
7247 and their respective operands.
7249 For memory, assume that the desired extraction_mode and pos_mode
7250 are the same as for a register operation, since at present we don't
7251 have named patterns for aligned memory structures. */
7255 {
7259 }
7261 /* Never narrow an object, since that might not be safe. */
7269 else
7270 {
7271 /* Be careful not to go beyond the extracted object and maintain the
7272 natural alignment of the memory. */
7276 {
7279 }
7280 }
7285 {
7286 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7287 BITS_BIG_ENDIAN style. If position is constant, compute new
7288 position. Otherwise, build subtraction.
7289 Note that POS is relative to the mode of the original argument.
7290 If it's a MEM we need to recompute POS relative to that.
7291 However, if we're extracting from (or inserting into) a register,
7292 we want to recompute POS relative to wanted_inner_mode. */
7299 else
7300 pos_rtx
7303 pos_rtx);
7304 /* POS may be less than 0 now, but we check for that below.
7305 Note that it can only be less than 0 if !MEM_P (inner). */
7306 }
7308 /* If INNER has a wider mode, and this is a constant extraction, try to
7309 make it smaller and adjust the byte to point to the byte containing
7310 the value. */
7313 && ! pos_rtx
7318 {
7321 /* The computations below will be correct if the machine is big
7322 endian in both bits and bytes or little endian in bits and bytes.
7323 If it is mixed, we must adjust. */
7325 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7326 adjust OFFSET to compensate. */
7331 /* We can now move to the desired byte. */
7342 }
7344 /* If INNER is not memory, get it into the proper mode. If we are changing
7345 its mode, POS must be a constant and smaller than the size of the new
7346 mode. */
7348 {
7349 /* On the LHS, don't create paradoxical subregs implicitely truncating
7350 the register unless TRULY_NOOP_TRUNCATION. */
7353 wanted_inner_mode))
7365 pos_rtx
7371 }
7373 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7374 have to zero extend. Otherwise, we can just use a SUBREG. */
7377 {
7381 /* If we know that no extraneous bits are set, and that the high
7382 bit is not set, convert extraction to cheaper one - either
7383 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7384 cases. */
7392 {
7396 /* Prefer ZERO_EXTENSION, since it gives more information to
7397 backends. */
7401 }
7403 }
7405 /* Make POS_RTX unless we already have it and it is correct. If we don't
7406 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7407 be a CONST_INT. */
7414 /* Make the required operation. See if we can use existing rtx. */
7421 }
7422 \f
7423 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7424 with any other operations in X. Return X without that shift if so. */
7426 static rtx
7428 {
7431 rtx tem;
7434 {
7436 /* This is the shift itself. If it is wide enough, we will return
7437 either the value being shifted if the shift count is equal to
7438 COUNT or a shift for the difference. */
7452 /* If we can safely shift this constant and we find the inner shift,
7453 make a new operation. */
7458 {
7462 }
7467 }
7470 }
7471 \f
7472 /* Look at the expression rooted at X. Look for expressions
7473 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7474 Form these expressions.
7476 Return the new rtx, usually just X.
7478 Also, for machines like the VAX that don't have logical shift insns,
7479 try to convert logical to arithmetic shift operations in cases where
7480 they are equivalent. This undoes the canonicalizations to logical
7481 shifts done elsewhere.
7483 We try, as much as possible, to re-use rtl expressions to save memory.
7485 IN_CODE says what kind of expression we are processing. Normally, it is
7486 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7487 being kludges), it is MEM. When processing the arguments of a comparison
7488 or a COMPARE against zero, it is COMPARE. */
7490 rtx
7492 {
7500 rtx tem;
7503 /* Select the code to be used in recursive calls. Once we are inside an
7504 address, we stay there. If we have a comparison, set to COMPARE,
7505 but once inside, go back to our default of SET. */
7514 /* Process depending on the code of this operation. If NEW is set
7515 nonzero, it will be returned. */
7518 {
7520 /* Convert shifts by constants into multiplications if inside
7521 an address. */
7526 {
7532 {
7535 }
7538 }
7548 {
7552 }
7555 {
7559 mode));
7561 }
7562 else
7563 {
7567 }
7578 {
7582 }
7585 {
7589 mode));
7591 }
7592 else
7593 {
7597 }
7601 /* If the second operand is not a constant, we can't do anything
7602 with it. */
7606 /* If the constant is a power of two minus one and the first operand
7607 is a logical right shift, make an extraction. */
7610 {
7614 }
7616 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7621 {
7623 next_code);
7627 }
7628 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7634 {
7635 /* Apply the distributive law, and then try to make extractions. */
7642 }
7644 /* If we are have (and (rotate X C) M) and C is larger than the number
7645 of bits in M, this is an extraction. */
7651 {
7657 }
7659 /* On machines without logical shifts, if the operand of the AND is
7660 a logical shift and our mask turns off all the propagated sign
7661 bits, we can replace the logical shift with an arithmetic shift. */
7669 {
7676 make_compound_operation
7679 }
7681 /* If the constant is one less than a power of two, this might be
7682 representable by an extraction even if no shift is present.
7683 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7684 we are in a COMPARE. */
7688 next_code),
7691 /* If we are in a comparison and this is an AND with a power of two,
7692 convert this into the appropriate bit extract. */
7697 next_code),
7703 /* If the sign bit is known to be zero, replace this with an
7704 arithmetic shift. */
7709 {
7712 next_code),
7715 }
7717 /* ... fall through ... */
7723 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7724 this is a SIGN_EXTRACT. */
7731 {
7738 }
7740 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7741 If so, try to merge the shifts into a SIGN_EXTEND. We could
7742 also do this for some cases of SIGN_EXTRACT, but it doesn't
7743 seem worth the effort; the case checked for occurs on Alpha. */
7759 /* Call ourselves recursively on the inner expression. If we are
7760 narrowing the object and it has a different RTL code from
7761 what it originally did, do this SUBREG as a force_to_mode. */
7762 {
7766 /* If in_code is COMPARE, it isn't always safe to pass it through
7767 to the recursive make_compound_operation call. */
7771 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7772 is (const_int 0), rather than
7773 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7783 simplified
7791 {
7792 rtx newer
7795 /* If we have something other than a SUBREG, we might have
7796 done an expansion, so rerun ourselves. */
7800 /* force_to_mode can expand compounds. If it just re-expanded the
7801 compound, use gen_lowpart to convert to the desired mode. */
7803 /* Likewise if it re-expanded the compound only partially.
7804 This happens for SUBREG of ZERO_EXTRACT if they extract
7805 the same number of bits. */
7814 }
7818 }
7823 }
7826 {
7829 }
7831 /* Now recursively process each operand of this operation. We need to
7832 handle ZERO_EXTEND specially so that we don't lose track of the
7833 inner mode. */
7835 {
7843 }
7848 {
7851 }
7854 {
7857 }
7859 maybe_swap:
7860 /* If this is a commutative operation, the changes to the operands
7861 may have made it noncanonical. */
7864 {
7868 }
7871 }
7872 \f
7873 /* Given M see if it is a value that would select a field of bits
7874 within an item, but not the entire word. Return -1 if not.
7875 Otherwise, return the starting position of the field, where 0 is the
7876 low-order bit.
7878 *PLEN is set to the length of the field. */
7880 static int
7882 {
7883 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7888 /* Now shift off the low-order zero bits and see if we have a
7889 power of two minus 1. */
7897 }
7898 \f
7899 /* If X refers to a register that equals REG in value, replace these
7900 references with REG. */
7901 static rtx
7903 {
7911 {
7947 {
7951 else
7953 }
7955 /* fall through */
7962 {
7965 {
7967 {
7970 }
7972 }
7973 }
7975 {
7978 {
7981 {
7983 {
7986 }
7988 }
7989 }
7990 }
7993 }
7996 }
7998 /* Return X converted to MODE. If the value is already truncated to
7999 MODE we can just return a subreg even though in the general case we
8000 would need an explicit truncation. */
8002 static rtx
8004 {
8009 {
8010 /* Bit-cast X into an integer mode. */
8015 }
8018 }
8020 /* See if X can be simplified knowing that we will only refer to it in
8021 MODE and will only refer to those bits that are nonzero in MASK.
8022 If other bits are being computed or if masking operations are done
8023 that select a superset of the bits in MASK, they can sometimes be
8024 ignored.
8026 Return a possibly simplified expression, but always convert X to
8027 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8029 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8030 are all off in X. This is used when X will be complemented, by either
8031 NOT, NEG, or XOR. */
8033 static rtx
8036 {
8043 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8044 code below will do the wrong thing since the mode of such an
8045 expression is VOIDmode.
8047 Also do nothing if X is a CLOBBER; this can happen if X was
8048 the return value from a call to gen_lowpart. */
8052 /* We want to perform the operation in its present mode unless we know
8053 that the operation is valid in MODE, in which case we do the operation
8054 in MODE. */
8059 /* It is not valid to do a right-shift in a narrower mode
8060 than the one it came in with. */
8065 /* Truncate MASK to fit OP_MODE. */
8069 /* When we have an arithmetic operation, or a shift whose count we
8070 do not know, we need to assume that all bits up to the highest-order
8071 bit in MASK will be needed. This is how we form such a mask. */
8074 else
8078 /* Determine what bits of X are guaranteed to be (non)zero. */
8081 /* If none of the bits in X are needed, return a zero. */
8085 /* If X is a CONST_INT, return a new one. Do this here since the
8086 test below will fail. */
8088 {
8091 else
8092 {
8095 }
8096 }
8098 /* If X is narrower than MODE and we want all the bits in X's mode, just
8099 get X in the proper mode. */
8104 /* We can ignore the effect of a SUBREG if it narrows the mode or
8105 if the constant masks to zero all the bits the mode doesn't have. */
8115 /* The arithmetic simplifications here only work for scalar integer modes. */
8120 {
8122 /* If X is a (clobber (const_int)), return it since we know we are
8123 generating something that won't match. */
8136 /* Similarly for a truncate. */
8140 /* If this is an AND with a constant, convert it into an AND
8141 whose constant is the AND of that constant with MASK. If it
8142 remains an AND of MASK, delete it since it is redundant. */
8145 {
8149 /* If X is still an AND, see if it is an AND with a mask that
8150 is just some low-order bits. If so, and it is MASK, we don't
8151 need it. */
8158 /* If it remains an AND, try making another AND with the bits
8159 in the mode mask that aren't in MASK turned on. If the
8160 constant in the AND is wide enough, this might make a
8161 cheaper constant. */
8166 {
8167 unsigned HOST_WIDE_INT cval
8170 rtx y;
8177 }
8180 }
8185 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8186 low-order bits (as in an alignment operation) and FOO is already
8187 aligned to that boundary, mask C1 to that boundary as well.
8188 This may eliminate that PLUS and, later, the AND. */
8190 {
8194 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8195 number, sign extend it. */
8208 }
8210 /* ... fall through ... */
8213 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8214 most significant bit in MASK since carries from those bits will
8215 affect the bits we are interested in. */
8220 /* If X is (minus C Y) where C's least set bit is larger than any bit
8221 in the mask, then we may replace with (neg Y). */
8224 {
8228 }
8230 /* Similarly, if C contains every bit in the fuller_mask, then we may
8231 replace with (not Y). */
8234 {
8238 }
8245 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8246 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8247 operation which may be a bitfield extraction. Ensure that the
8248 constant we form is not wider than the mode of X. */
8260 {
8269 }
8271 binop:
8272 /* For most binary operations, just propagate into the operation and
8273 change the mode if we have an operation of that mode. */
8278 /* If we ended up truncating both operands, truncate the result of the
8279 operation instead. */
8282 {
8285 }
8295 /* For left shifts, do the same, but just for the first operand.
8296 However, we cannot do anything with shifts where we cannot
8297 guarantee that the counts are smaller than the size of the mode
8298 because such a count will have a different meaning in a
8299 wider mode. */
8309 /* If the shift count is a constant and we can do arithmetic in
8310 the mode of the shift, refine which bits we need. Otherwise, use the
8311 conservative form of the mask. */
8317 else
8329 /* Here we can only do something if the shift count is a constant,
8330 this shift constant is valid for the host, and we can do arithmetic
8331 in OP_MODE. */
8337 {
8341 /* Select the mask of the bits we need for the shift operand. */
8344 /* We can only change the mode of the shift if we can do arithmetic
8345 in the mode of the shift and INNER_MASK is no wider than the
8346 width of X's mode. */
8354 }
8356 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8357 shift and AND produces only copies of the sign bit (C2 is one less
8358 than a power of two), we can do this with just a shift. */
8362 /* The shift puts one of the sign bit copies in the least significant
8363 bit. */
8368 /* Number of bits left after the shift must be more than the mask
8369 needs. */
8372 /* Must be more sign bit copies than the mask needs. */
8382 /* If we are just looking for the sign bit, we don't need this shift at
8383 all, even if it has a variable count. */
8387 /* If this is a shift by a constant, get a mask that contains those bits
8388 that are not copies of the sign bit. We then have two cases: If
8389 MASK only includes those bits, this can be a logical shift, which may
8390 allow simplifications. If MASK is a single-bit field not within
8391 those bits, we are requesting a copy of the sign bit and hence can
8392 shift the sign bit to the appropriate location. */
8396 {
8399 /* If the considered data is wider than HOST_WIDE_INT, we can't
8400 represent a mask for all its bits in a single scalar.
8401 But we only care about the lower bits, so calculate these. */
8404 {
8407 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8408 is the number of bits a full-width mask would have set.
8409 We need only shift if these are fewer than nonzero can
8410 hold. If not, we must keep all bits set in nonzero. */
8415 + HOST_BITS_PER_WIDE_INT
8417 }
8418 else
8419 {
8422 }
8425 {
8430 }
8433 {
8434 x = simplify_shift_const
8440 }
8441 }
8443 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8444 even if the shift count isn't a constant. */
8449 shiftrt:
8451 /* If this is a zero- or sign-extension operation that just affects bits
8452 we don't care about, remove it. Be sure the call above returned
8453 something that is still a shift. */
8463 next_select);
8469 /* If the shift count is constant and we can do computations
8470 in the mode of X, compute where the bits we care about are.
8471 Otherwise, we can't do anything. Don't change the mode of
8472 the shift or propagate MODE into the shift, though. */
8475 {
8485 }
8489 /* If we just want the low-order bit, the NEG isn't needed since it
8490 won't change the low-order bit. */
8494 /* We need any bits less significant than the most significant bit in
8495 MASK since carries from those bits will affect the bits we are
8496 interested in. */
8501 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8502 same as the XOR case above. Ensure that the constant we form is not
8503 wider than the mode of X. */
8511 {
8520 }
8522 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8523 use the full mask inside the NOT. */
8526 unop:
8529 next_select));
8535 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8536 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8537 which is equal to STORE_FLAG_VALUE. */
8549 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8550 written in a narrower mode. We play it safe and do not do so. */
8566 }
8568 /* Ensure we return a value of the proper mode. */
8570 }
8571 \f
8572 /* Return nonzero if X is an expression that has one of two values depending on
8573 whether some other value is zero or nonzero. In that case, we return the
8574 value that is being tested, *PTRUE is set to the value if the rtx being
8575 returned has a nonzero value, and *PFALSE is set to the other alternative.
8577 If we return zero, we set *PTRUE and *PFALSE to X. */
8579 static rtx
8581 {
8587 /* If we are comparing a value against zero, we are done. */
8590 {
8594 }
8596 /* If this is a unary operation whose operand has one of two values, apply
8597 our opcode to compute those values. */
8600 {
8605 }
8607 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8608 make can't possibly match and would suppress other optimizations. */
8610 ;
8612 /* If this is a binary operation, see if either side has only one of two
8613 values. If either one does or if both do and they are conditional on
8614 the same value, compute the new true and false values. */
8616 {
8622 {
8623 /* If if_then_else_cond returned zero, then true/false are the
8624 same rtl. We must copy one of them to prevent invalid rtl
8625 sharing. */
8632 {
8637 }
8638 else
8639 {
8642 }
8645 }
8647 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8648 operands is zero when the other is nonzero, and vice-versa,
8649 and STORE_FLAG_VALUE is 1 or -1. */
8655 {
8672 {
8679 const_true_rtx);
8681 }
8682 }
8684 /* Similarly for MULT, AND and UMIN, except that for these the result
8685 is always zero. */
8689 {
8703 {
8706 }
8707 }
8708 }
8711 {
8712 /* If we have IF_THEN_ELSE already, extract the condition and
8713 canonicalize it if it is NE or EQ. */
8719 {
8722 }
8723 else
8725 }
8727 /* If X is a SUBREG, we can narrow both the true and false values
8728 if the inner expression, if there is a condition. */
8732 {
8738 {
8742 }
8743 }
8745 /* If X is a constant, this isn't special and will cause confusions
8746 if we treat it as such. Likewise if it is equivalent to a constant. */
8749 ;
8751 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8752 will be least confusing to the rest of the compiler. */
8754 {
8757 }
8759 /* If X is known to be either 0 or -1, those are the true and
8760 false values when testing X. */
8764 {
8767 }
8769 /* Likewise for 0 or a single bit. */
8772 {
8775 }
8777 /* Otherwise fail; show no condition with true and false values the same. */
8780 }
8781 \f
8782 /* Return the value of expression X given the fact that condition COND
8783 is known to be true when applied to REG as its first operand and VAL
8784 as its second. X is known to not be shared and so can be modified in
8785 place.
8787 We only handle the simplest cases, and specifically those cases that
8788 arise with IF_THEN_ELSE expressions. */
8790 static rtx
8792 {
8794 rtx temp;
8801 /* If either operand of the condition is a floating point value,
8802 then we have to avoid collapsing an EQ comparison. */
8812 /* If X is (abs REG) and we know something about REG's relationship
8813 with zero, we may be able to simplify this. */
8817 {
8826 }
8828 /* The only other cases we handle are MIN, MAX, and comparisons if the
8829 operands are the same as REG and VAL. */
8832 {
8837 {
8839 {
8847 else
8849 }
8852 {
8855 /* Do not reverse the condition when it is NE or EQ.
8856 This is because we cannot conclude anything about
8857 the value of 'SMAX (x, y)' when x is not equal to y,
8858 but we can when x equals y. */
8864 {
8875 }
8876 }
8877 }
8878 }
8880 {
8885 {
8886 /* We must simplify subreg here, before we lose track of the
8887 original inner_mode. */
8892 else
8894 }
8897 }
8898 /* We don't have to handle SIGN_EXTEND here, because even in the
8899 case of replacing something with a modeless CONST_INT, a
8900 CONST_INT is already (supposed to be) a valid sign extension for
8901 its narrower mode, which implies it's already properly
8902 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8903 story is different. */
8905 {
8910 {
8911 /* We must simplify the zero_extend here, before we lose
8912 track of the original inner_mode. */
8917 else
8919 }
8922 }
8926 {
8933 }
8936 }
8937 \f
8938 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8939 assignment as a field assignment. */
8941 static int
8943 {
8950 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8951 Note that all SUBREGs of MEM are paradoxical; otherwise they
8952 would have been rewritten. */
8965 /* We used to see if get_last_value of X and Y were the same but that's
8966 not correct. In one direction, we'll cause the assignment to have
8967 the wrong destination and in the case, we'll import a register into this
8968 insn that might have already have been dead. So fail if none of the
8969 above cases are true. */
8971 }
8972 \f
8973 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8974 Return that assignment if so.
8976 We only handle the most common cases. */
8978 static rtx
8980 {
8983 rtx assign;
8985 HOST_WIDE_INT c1;
8986 HOST_WIDE_INT pos;
8988 rtx other;
8991 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8992 a clear of a one-bit field. We will have changed it to
8993 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8994 for a SUBREG. */
9000 {
9006 }
9016 {
9023 }
9025 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9026 one-bit field. */
9030 {
9036 }
9038 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9039 SRC is an AND with all bits of that field set, then we can discard
9040 the AND. */
9045 {
9052 else
9055 /* Complete overlap. We can remove the source AND. */
9059 /* Partial overlap. We can reduce the source AND. */
9061 {
9066 }
9067 }
9069 /* The other case we handle is assignments into a constant-position
9070 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9071 a mask that has all one bits except for a group of zero bits and
9072 OTHER is known to have zeros where C1 has ones, this is such an
9073 assignment. Compute the position and length from C1. Shift OTHER
9074 to the appropriate position, force it to the required mode, and
9075 make the extraction. Check for the AND in both operands. */
9091 else
9104 /* The mode to use for the source is the mode of the assignment, or of
9105 what is inside a possible STRICT_LOW_PART. */
9109 /* Shift OTHER right POS places and make it the source, restricting it
9110 to the proper length and mode. */
9115 dest);
9122 /* If SRC is masked by an AND that does not make a difference in
9123 the value being stored, strip it. */
9134 }
9135 \f
9136 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9137 if so. */
9139 static rtx
9141 {
9145 rtx tem;
9147 /* Distributivity is not true for floating point as it can change the
9148 value. So we don't do it unless -funsafe-math-optimizations. */
9153 /* The outer operation can only be one of the following: */
9161 /* If either operand is a primitive we can't do anything, so get out
9162 fast. */
9172 /* See if the inner and outer operations distribute. */
9174 {
9179 /* These all distribute except over PLUS. */
9190 /* This is also a multiply, so it distributes over everything. */
9193 /* This used to handle SUBREG, but this turned out to be counter-
9194 productive, since (subreg (op ...)) usually is not handled by
9195 insn patterns, and this "optimization" therefore transformed
9196 recognizable patterns into unrecognizable ones. Therefore the
9197 SUBREG case was removed from here.
9199 It is possible that distributing SUBREG over arithmetic operations
9200 leads to an intermediate result than can then be optimized further,
9201 e.g. by moving the outer SUBREG to the other side of a SET as done
9202 in simplify_set. This seems to have been the original intent of
9203 handling SUBREGs here.
9205 However, with current GCC this does not appear to actually happen,
9206 at least on major platforms. If some case is found where removing
9207 the SUBREG case here prevents follow-on optimizations, distributing
9208 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9212 }
9214 /* Set LHS and RHS to the inner operands (A and B in the example
9215 above) and set OTHER to the common operand (C in the example).
9216 There is only one way to do this unless the inner operation is
9217 commutative. */
9229 else
9232 /* Form the new inner operation, seeing if it simplifies first. */
9235 /* There is one exception to the general way of distributing:
9236 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9238 {
9241 }
9243 /* We may be able to continuing distributing the result, so call
9244 ourselves recursively on the inner operation before forming the
9245 outer operation, which we return. */
9248 }
9250 /* See if X is of the form (* (+ A B) C), and if so convert to
9251 (+ (* A C) (* B C)) and try to simplify.
9253 Most of the time, this results in no change. However, if some of
9254 the operands are the same or inverses of each other, simplifications
9255 will result.
9257 For example, (and (ior A B) (not B)) can occur as the result of
9258 expanding a bit field assignment. When we apply the distributive
9259 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9260 which then simplifies to (and (A (not B))).
9262 Note that no checks happen on the validity of applying the inverse
9263 distributive law. This is pointless since we can do it in the
9264 few places where this routine is called.
9266 N is the index of the term that is decomposed (the arithmetic operation,
9267 i.e. (+ A B) in the first example above). !N is the index of the term that
9268 is distributed, i.e. of C in the first example above. */
9269 static rtx
9271 {
9276 /* Distributivity is not true for floating point as it can change the
9277 value. So we don't do it unless -funsafe-math-optimizations. */
9294 /* Special case (and (xor B C) (not A)), which is equivalent to
9295 (xor (ior A B) (ior A C)) */
9297 {
9300 }
9303 {
9304 /* Distribute the second term. */
9307 }
9308 else
9309 {
9310 /* Distribute the first term. */
9313 }
9323 }
9324 \f
9325 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9326 in MODE. Return an equivalent form, if different from (and VAROP
9327 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9329 static rtx
9332 {
9335 rtx orig_varop;
9343 /* Simplify VAROP knowing that we will be only looking at some of the
9344 bits in it.
9346 Note by passing in CONSTOP, we guarantee that the bits not set in
9347 CONSTOP are not significant and will never be examined. We must
9348 ensure that is the case by explicitly masking out those bits
9349 before returning. */
9352 /* If VAROP is a CLOBBER, we will fail so return it. */
9356 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9357 to VAROP and return the new constant. */
9361 /* See what bits may be nonzero in VAROP. Unlike the general case of
9362 a call to nonzero_bits, here we don't care about bits outside
9363 MODE. */
9367 /* Turn off all bits in the constant that are known to already be zero.
9368 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9369 which is tested below. */
9373 /* If we don't have any bits left, return zero. */
9377 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9378 a power of two, we can replace this with an ASHIFT. */
9383 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9384 or XOR, then try to apply the distributive law. This may eliminate
9385 operations if either branch can be simplified because of the AND.
9386 It may also make some cases more complex, but those cases probably
9387 won't match a pattern either with or without this. */
9390 return
9391 gen_lowpart
9393 apply_distributive_law
9398 constop),
9402 constop))));
9404 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9405 the AND and see if one of the operands simplifies to zero. If so, we
9406 may eliminate it. */
9410 {
9419 }
9421 /* Make a SUBREG if necessary. If we can't make it, fail. */
9426 /* If we are only masking insignificant bits, return VAROP. */
9433 /* Otherwise, return an AND. */
9435 }
9438 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9439 in MODE.
9441 Return an equivalent form, if different from X. Otherwise, return X. If
9442 X is zero, we are to always construct the equivalent form. */
9444 static rtx
9447 {
9458 }
9459 \f
9460 /* Given a REG, X, compute which bits in X can be nonzero.
9461 We don't care about bits outside of those defined in MODE.
9463 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9464 a shift, AND, or zero_extract, we can do better. */
9466 static rtx
9468 const_rtx known_x ATTRIBUTE_UNUSED,
9472 {
9473 rtx tem;
9476 /* If X is a register whose nonzero bits value is current, use it.
9477 Otherwise, if X is a register whose value we can find, use that
9478 value. Otherwise, use the previously-computed global nonzero bits
9479 for this register. */
9492 && !REGNO_REG_SET_P
9495 {
9499 /* We don't know anything about the upper bits. */
9504 }
9509 {
9510 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9511 /* If X is narrower than MODE and TEM is a non-negative
9512 constant that would appear negative in the mode of X,
9513 sign-extend it for use in reg_nonzero_bits because some
9514 machines (maybe most) will actually do the sign-extension
9515 and this is the conservative approach.
9517 ??? For 2.5, try to tighten up the MD files in this regard
9518 instead of this kludge. */
9525 #endif
9527 }
9529 {
9533 /* We don't know anything about the upper bits. */
9537 }
9540 }
9542 /* Return the number of bits at the high-order end of X that are known to
9543 be equal to the sign bit. X will be used in mode MODE; if MODE is
9544 VOIDmode, X will be used in its own mode. The returned value will always
9545 be between 1 and the number of bits in MODE. */
9547 static rtx
9549 const_rtx known_x ATTRIBUTE_UNUSED,
9550 enum machine_mode known_mode
9551 ATTRIBUTE_UNUSED,
9554 {
9555 rtx tem;
9567 && !REGNO_REG_SET_P
9570 {
9573 }
9584 }
9585 \f
9586 /* Return the number of "extended" bits there are in X, when interpreted
9587 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9588 unsigned quantities, this is the number of high-order zero bits.
9589 For signed quantities, this is the number of copies of the sign bit
9590 minus 1. In both case, this function returns the number of "spare"
9591 bits. For example, if two quantities for which this function returns
9592 at least 1 are added, the addition is known not to overflow.
9594 This function will always return 0 unless called during combine, which
9595 implies that it must be called from a define_split. */
9597 unsigned int
9599 {
9609 }
9611 /* This function is called from `simplify_shift_const' to merge two
9612 outer operations. Specifically, we have already found that we need
9613 to perform operation *POP0 with constant *PCONST0 at the outermost
9614 position. We would now like to also perform OP1 with constant CONST1
9615 (with *POP0 being done last).
9617 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9618 the resulting operation. *PCOMP_P is set to 1 if we would need to
9619 complement the innermost operand, otherwise it is unchanged.
9621 MODE is the mode in which the operation will be done. No bits outside
9622 the width of this mode matter. It is assumed that the width of this mode
9623 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9625 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9626 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9627 result is simply *PCONST0.
9629 If the resulting operation cannot be expressed as one operation, we
9630 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9632 static int
9633 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9634 {
9641 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9645 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9646 if OP0 is SET. */
9655 {
9657 {
9675 }
9676 }
9678 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9682 /* If the two constants aren't the same, we can't do anything. The
9683 remaining six cases can all be done. */
9687 else
9689 {
9692 /* (a & b) | b == b */
9695 /* (a ^ b) | b == a | b */
9696 {;}
9701 /* (a & b) ^ b == (~a) & b */
9704 /* (a | b) ^ b == a & ~b */
9710 /* (a | b) & b == b */
9713 /* (a ^ b) & b) == (~a) & b */
9718 }
9720 /* Check for NO-OP cases. */
9733 /* ??? Slightly redundant with the above mask, but not entirely.
9734 Moving this above means we'd have to sign-extend the mode mask
9735 for the final test. */
9740 }
9741 \f
9742 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9743 the shift in. The original shift operation CODE is performed on OP in
9744 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9745 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9746 result of the shift is subject to operation OUTER_CODE with operand
9747 OUTER_CONST. */
9749 static enum machine_mode
9753 {
9758 /* In general we can't perform in wider mode for right shift and rotate. */
9760 {
9762 /* We can still widen if the bits brought in from the left are identical
9763 to the sign bit of ORIG_MODE. */
9771 /* Similarly here but with zero bits. */
9776 /* We can also widen if the bits brought in will be masked off. This
9777 operation is performed in ORIG_MODE. */
9779 {
9785 }
9786 /* fall through */
9796 }
9797 }
9799 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9800 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9801 if we cannot simplify it. Otherwise, return a simplified value.
9803 The shift is normally computed in the widest mode we find in VAROP, as
9804 long as it isn't a different number of words than RESULT_MODE. Exceptions
9805 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9807 static rtx
9810 {
9816 unsigned int mode_words
9818 /* We form (outer_op (code varop count) (outer_const)). */
9824 /* Make sure and truncate the "natural" shift on the way in. We don't
9825 want to do this inside the loop as it makes it more difficult to
9826 combine shifts. */
9830 /* If we were given an invalid count, don't do anything except exactly
9831 what was requested. */
9838 /* Unless one of the branches of the `if' in this loop does a `continue',
9839 we will `break' the loop after the `if'. */
9842 {
9843 /* If we have an operand of (clobber (const_int 0)), fail. */
9847 /* Convert ROTATERT to ROTATE. */
9849 {
9854 else
9856 }
9861 /* Handle cases where the count is greater than the size of the mode
9862 minus 1. For ASHIFT, use the size minus one as the count (this can
9863 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9864 take the count modulo the size. For other shifts, the result is
9865 zero.
9867 Since these shifts are being produced by the compiler by combining
9868 multiple operations, each of which are defined, we know what the
9869 result is supposed to be. */
9872 {
9877 else
9878 {
9879 /* We can't simply return zero because there may be an
9880 outer op. */
9884 }
9885 }
9887 /* If we discovered we had to complement VAROP, leave. Making a NOT
9888 here would cause an infinite loop. */
9892 /* An arithmetic right shift of a quantity known to be -1 or 0
9893 is a no-op. */
9897 {
9900 }
9902 /* If we are doing an arithmetic right shift and discarding all but
9903 the sign bit copies, this is equivalent to doing a shift by the
9904 bitsize minus one. Convert it into that shift because it will often
9905 allow other simplifications. */
9912 /* We simplify the tests below and elsewhere by converting
9913 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9914 `make_compound_operation' will convert it to an ASHIFTRT for
9915 those machines (such as VAX) that don't have an LSHIFTRT. */
9932 {
9939 {
9942 }
9946 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9947 minus the width of a smaller mode, we can do this with a
9948 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9955 {
9964 }
9968 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9969 the same number of words as what we've seen so far. Then store
9970 the widest mode in MODE. */
9976 == mode_words
9979 {
9984 }
9988 /* Some machines use MULT instead of ASHIFT because MULT
9989 is cheaper. But it is still better on those machines to
9990 merge two shifts into one. */
9993 {
9994 varop
10000 }
10004 /* Similar, for when divides are cheaper. */
10007 {
10008 varop
10014 }
10018 /* If we are extracting just the sign bit of an arithmetic
10019 right shift, that shift is not needed. However, the sign
10020 bit of a wider mode may be different from what would be
10021 interpreted as the sign bit in a narrower mode, so, if
10022 the result is narrower, don't discard the shift. */
10027 {
10030 }
10032 /* ... fall through ... */
10037 /* Here we have two nested shifts. The result is usually the
10038 AND of a new shift with a mask. We compute the result below. */
10045 {
10049 rtx mask_rtx;
10051 /* We have one common special case. We can't do any merging if
10052 the inner code is an ASHIFTRT of a smaller mode. However, if
10053 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10054 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10055 we can convert it to
10056 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10057 This simplifies certain SIGN_EXTEND operations. */
10061 {
10062 /* C3 has the low-order C1 bits zero. */
10074 }
10076 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10077 than C1 high-order bits equal to the sign bit, we can convert
10078 this to either an ASHIFT or an ASHIFTRT depending on the
10079 two counts.
10081 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10087 {
10091 {
10094 }
10097 }
10099 /* There are some cases we can't do. If CODE is ASHIFTRT,
10100 we can only do this if FIRST_CODE is also ASHIFTRT.
10102 We can't do the case when CODE is ROTATE and FIRST_CODE is
10103 ASHIFTRT.
10105 If the mode of this shift is not the mode of the outer shift,
10106 we can't do this if either shift is a right shift or ROTATE.
10108 Finally, we can't do any of these if the mode is too wide
10109 unless the codes are the same.
10111 Handle the case where the shift codes are the same
10112 first. */
10115 {
10124 }
10135 /* To compute the mask to apply after the shift, shift the
10136 nonzero bits of the inner shift the same way the
10137 outer shift will. */
10140 result_mode);
10142 mask_rtx
10146 /* Give up if we can't compute an outer operation to use. */
10154 /* If the shifts are in the same direction, we add the
10155 counts. Otherwise, we subtract them. */
10159 else
10162 /* If COUNT is positive, the new shift is usually CODE,
10163 except for the two exceptions below, in which case it is
10164 FIRST_CODE. If the count is negative, FIRST_CODE should
10165 always be used */
10175 }
10177 /* If we have (A << B << C) for any shift, we can convert this to
10178 (A << C << B). This wins if A is a constant. Only try this if
10179 B is not a constant. */
10184 {
10191 }
10198 /* Make this fit the case below. */
10205 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10206 with C the size of VAROP - 1 and the shift is logical if
10207 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10208 we have an (le X 0) operation. If we have an arithmetic shift
10209 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10210 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10218 {
10221 const0_rtx);
10227 }
10229 /* If we have (shift (logical)), move the logical to the outside
10230 to allow it to possibly combine with another logical and the
10231 shift to combine with another shift. This also canonicalizes to
10232 what a ZERO_EXTRACT looks like. Also, some machines have
10233 (and (shift)) insns. */
10236 /* We can't do this if we have (ashiftrt (xor)) and the
10237 constant has its sign bit set in shift_mode. */
10240 shift_mode))
10248 {
10251 }
10253 /* If we can't do that, try to simplify the shift in each arm of the
10254 logical expression, make a new logical expression, and apply
10255 the inverse distributive law. This also can't be done
10256 for some (ashiftrt (xor)). */
10260 shift_mode)))
10261 {
10273 }
10277 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10278 says that the sign bit can be tested, FOO has mode MODE, C is
10279 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10280 that may be nonzero. */
10290 {
10294 }
10298 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10299 than the number of bits in the mode is equivalent to A. */
10303 {
10307 }
10309 /* NEG commutes with ASHIFT since it is multiplication. Move the
10310 NEG outside to allow shifts to combine. */
10314 {
10317 }
10321 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10322 is one less than the number of bits in the mode is
10323 equivalent to (xor A 1). */
10330 {
10334 }
10336 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10337 that might be nonzero in BAR are those being shifted out and those
10338 bits are known zero in FOO, we can replace the PLUS with FOO.
10339 Similarly in the other operand order. This code occurs when
10340 we are computing the size of a variable-size array. */
10347 {
10350 }
10358 result_mode)))
10359 {
10362 }
10364 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10373 {
10376 }
10378 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10379 signbit', and attempt to change the PLUS to an XOR and move it to
10380 the outer operation as is done above in the AND/IOR/XOR case
10381 leg for shift(logical). See details in logical handling above
10382 for reasoning in doing so. */
10392 {
10395 }
10400 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10401 with C the size of VAROP - 1 and the shift is logical if
10402 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10403 we have a (gt X 0) operation. If the shift is arithmetic with
10404 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10405 we have a (neg (gt X 0)) operation. */
10414 {
10417 const0_rtx);
10423 }
10427 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10428 if the truncate does not affect the value. */
10435 {
10438 varop_inner
10441 GEN_INT
10446 }
10451 }
10454 }
10459 /* We have now finished analyzing the shift. The result should be
10460 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10461 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10462 to the result of the shift. OUTER_CONST is the relevant constant,
10463 but we must turn off all bits turned off in the shift. */
10471 /* Make a SUBREG if necessary. If we can't make it, fail. */
10476 /* If we have an outer operation and we just made a shift, it is
10477 possible that we could have simplified the shift were it not
10478 for the outer operation. So try to do the simplification
10479 recursively. */
10483 else
10489 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10490 turn off all the bits that the shift would have turned off. */
10495 /* Do the remainder of the processing in RESULT_MODE. */
10498 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10499 operation. */
10504 {
10512 {
10513 /* This means that we have determined that the result is
10514 equivalent to a constant. This should be rare. */
10517 }
10520 else
10523 }
10526 }
10528 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10529 The result of the shift is RESULT_MODE. If we cannot simplify it,
10530 return X or, if it is NULL, synthesize the expression with
10531 simplify_gen_binary. Otherwise, return a simplified value.
10533 The shift is normally computed in the widest mode we find in VAROP, as
10534 long as it isn't a different number of words than RESULT_MODE. Exceptions
10535 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10537 static rtx
10540 {
10550 }
10552 \f
10553 /* Like recog, but we receive the address of a pointer to a new pattern.
10554 We try to match the rtx that the pointer points to.
10555 If that fails, we may try to modify or replace the pattern,
10556 storing the replacement into the same pointer object.
10558 Modifications include deletion or addition of CLOBBERs.
10560 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10561 the CLOBBERs are placed.
10563 The value is the final insn code from the pattern ultimately matched,
10564 or -1. */
10566 static int
10568 {
10570 rtx pat_without_clobbers;
10578 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10579 we use to indicate that something didn't match. If we find such a
10580 thing, force rejection. */
10594 {
10597 else
10600 }
10602 /* If it isn't, there is the possibility that we previously had an insn
10603 that clobbered some register as a side effect, but the combined
10604 insn doesn't need to do that. So try once more without the clobbers
10605 unless this represents an ASM insn. */
10609 {
10614 {
10617 pos++;
10618 }
10628 {
10631 else
10634 }
10635 }
10642 /* Recognize all noop sets, these will be killed by followup pass. */
10646 /* If we had any clobbers to add, make a new pattern than contains
10647 them. Then check to make sure that all of them are dead. */
10649 {
10659 else
10666 {
10671 {
10675 }
10676 }
10678 }
10682 {
10689 /* Allow targets to reject combined insn. */
10691 {
10694 dump_file);
10696 /* Callers expect recog_for_combine to strip
10697 clobbers from the pattern on failure. */
10702 }
10707 }
10713 }
10714 \f
10715 /* Like gen_lowpart_general but for use by combine. In combine it
10716 is not possible to create any new pseudoregs. However, it is
10717 safe to create invalid memory addresses, because combine will
10718 try to recognize them and all they will do is make the combine
10719 attempt fail.
10721 If for some reason this cannot do its job, an rtx
10722 (clobber (const_int 0)) is returned.
10723 An insn containing that will not be recognized. */
10725 static rtx
10727 {
10731 rtx result;
10736 /* We can only support MODE being wider than a word if X is a
10737 constant integer or has a mode the same size. */
10742 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10743 won't know what to do. So we will strip off the SUBREG here and
10744 process normally. */
10746 {
10749 /* For use in case we fall down into the address adjustments
10750 further below, we need to adjust the known mode and size of
10751 x; imode and isize, since we just adjusted x. */
10758 }
10766 {
10769 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10770 address. */
10775 /* If we want to refer to something bigger than the original memref,
10776 generate a paradoxical subreg instead. That will force a reload
10777 of the original memref X. */
10784 /* Adjust the address so that the address-after-the-data is
10785 unchanged. */
10790 }
10792 /* If X is a comparison operator, rewrite it in a new mode. This
10793 probably won't match, but may allow further simplifications. */
10797 /* If we couldn't simplify X any other way, just enclose it in a
10798 SUBREG. Normally, this SUBREG won't match, but some patterns may
10799 include an explicit SUBREG or we may simplify it further in combine. */
10800 else
10801 {
10803 rtx res;
10807 {
10812 }
10816 }
10818 fail:
10820 }
10821 \f
10822 /* Try to simplify a comparison between OP0 and a constant OP1,
10823 where CODE is the comparison code that will be tested, into a
10824 (CODE OP0 const0_rtx) form.
10826 The result is a possibly different comparison code to use.
10827 *POP1 may be updated. */
10829 static enum rtx_code
10832 {
10836 /* Get the constant we are comparing against and turn off all bits
10837 not on in our mode. */
10841 /* If we are comparing against a constant power of two and the value
10842 being compared can only have that single bit nonzero (e.g., it was
10843 `and'ed with that bit), we can replace this with a comparison
10844 with zero. */
10852 {
10855 }
10857 /* Similarly, if we are comparing a value known to be either -1 or
10858 0 with -1, change it to the opposite comparison against zero. */
10863 {
10866 }
10868 /* Do some canonicalizations based on the comparison code. We prefer
10869 comparisons against zero and then prefer equality comparisons.
10870 If we can reduce the size of a constant, we will do that too. */
10872 {
10874 /* < C is equivalent to <= (C - 1) */
10876 {
10879 /* ... fall through to LE case below. */
10880 }
10881 else
10885 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10887 {
10890 }
10892 /* If we are doing a <= 0 comparison on a value known to have
10893 a zero sign bit, we can replace this with == 0. */
10903 /* >= C is equivalent to > (C - 1). */
10905 {
10908 /* ... fall through to GT below. */
10909 }
10910 else
10914 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10916 {
10919 }
10921 /* If we are doing a > 0 comparison on a value known to have
10922 a zero sign bit, we can replace this with != 0. */
10932 /* < C is equivalent to <= (C - 1). */
10934 {
10937 /* ... fall through ... */
10938 }
10939 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10943 {
10947 }
10948 else
10952 /* unsigned <= 0 is equivalent to == 0 */
10955 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10959 {
10962 }
10966 /* >= C is equivalent to > (C - 1). */
10968 {
10971 /* ... fall through ... */
10972 }
10974 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10978 {
10982 }
10983 else
10987 /* unsigned > 0 is equivalent to != 0 */
10990 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10994 {
10997 }
11002 }
11006 }
11007 \f
11008 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11009 comparison code that will be tested.
11011 The result is a possibly different comparison code to use. *POP0 and
11012 *POP1 may be updated.
11014 It is possible that we might detect that a comparison is either always
11015 true or always false. However, we do not perform general constant
11016 folding in combine, so this knowledge isn't useful. Such tautologies
11017 should have been detected earlier. Hence we ignore all such cases. */
11019 static enum rtx_code
11021 {
11028 /* Try a few ways of applying the same transformation to both operands. */
11030 {
11031 #ifndef WORD_REGISTER_OPERATIONS
11032 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11033 so check specially. */
11048 - (GET_MODE_PRECISION
11050 {
11053 }
11054 #endif
11056 /* If both operands are the same constant shift, see if we can ignore the
11057 shift. We can if the shift is a rotate or if the bits shifted out of
11058 this shift are known to be zero for both inputs and if the type of
11059 comparison is compatible with the shift. */
11072 {
11085 else
11087 }
11089 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11090 SUBREGs are of the same mode, and, in both cases, the AND would
11091 be redundant if the comparison was done in the narrower mode,
11092 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11093 and the operand's possibly nonzero bits are 0xffffff01; in that case
11094 if we only care about QImode, we don't need the AND). This case
11095 occurs if the output mode of an scc insn is not SImode and
11096 STORE_FLAG_VALUE == 1 (e.g., the 386).
11098 Similarly, check for a case where the AND's are ZERO_EXTEND
11099 operations from some narrower mode even though a SUBREG is not
11100 present. */
11105 {
11122 {
11126 /* The resulting comparison is always unsigned since we masked
11127 off the original sign bit. */
11131 }
11138 {
11144 }
11148 }
11150 /* If both operands are NOT, we can strip off the outer operation
11151 and adjust the comparison code for swapped operands; similarly for
11152 NEG, except that this must be an equality comparison. */
11158 else
11160 }
11162 /* If the first operand is a constant, swap the operands and adjust the
11163 comparison code appropriately, but don't do this if the second operand
11164 is already a constant integer. */
11166 {
11169 }
11171 /* We now enter a loop during which we will try to simplify the comparison.
11172 For the most part, we only are concerned with comparisons with zero,
11173 but some things may really be comparisons with zero but not start
11174 out looking that way. */
11177 {
11184 HOST_WIDE_INT const_op;
11186 /* We only want to handle integral modes. This catches VOIDmode,
11187 CCmode, and the floating-point modes. An exception is that we
11188 can handle VOIDmode if OP0 is a COMPARE or a comparison
11189 operation. */
11196 /* Try to simplify the compare to constant, possibly changing the
11197 comparison op, and/or changing op1 to zero. */
11201 /* Compute some predicates to simplify code below. */
11208 /* If this is a sign bit comparison and we can do arithmetic in
11209 MODE, say that we will only be needing the sign bit of OP0. */
11216 /* Now try cases based on the opcode of OP0. If none of the cases
11217 does a "continue", we exit this loop immediately after the
11218 switch. */
11221 {
11223 /* If we are extracting a single bit from a variable position in
11224 a constant that has only a single bit set and are comparing it
11225 with zero, we can convert this into an equality comparison
11226 between the position and the location of the single bit. */
11227 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11228 have already reduced the shift count modulo the word size. */
11234 {
11242 /* Result is nonzero iff shift count is equal to I. */
11245 }
11247 /* ... fall through ... */
11252 {
11255 }
11259 /* If testing for equality, we can take the NOT of the constant. */
11262 {
11266 }
11268 /* If just looking at the sign bit, reverse the sense of the
11269 comparison. */
11271 {
11275 }
11279 /* If testing for equality, we can take the NEG of the constant. */
11282 {
11286 }
11288 /* The remaining cases only apply to comparisons with zero. */
11292 /* When X is ABS or is known positive,
11293 (neg X) is < 0 if and only if X != 0. */
11301 {
11305 }
11307 /* If we have NEG of something whose two high-order bits are the
11308 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11310 {
11314 }
11318 /* If we are testing equality and our count is a constant, we
11319 can perform the inverse operation on our RHS. */
11323 {
11327 }
11329 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11330 a particular bit. Convert it to an AND of a constant of that
11331 bit. This will be converted into a ZERO_EXTRACT. */
11335 {
11342 }
11344 /* Fall through. */
11347 /* ABS is ignorable inside an equality comparison with zero. */
11349 {
11352 }
11356 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11357 (compare FOO CONST) if CONST fits in FOO's mode and we
11358 are either testing inequality or have an unsigned
11359 comparison with ZERO_EXTEND or a signed comparison with
11360 SIGN_EXTEND. But don't do it if we don't have a compare
11361 insn of the given mode, since we'd have to revert it
11362 later on, and then we wouldn't know whether to sign- or
11363 zero-extend. */
11366 && ! unsigned_comparison_p
11370 {
11373 }
11377 /* Check for the case where we are comparing A - C1 with C2, that is
11379 (subreg:MODE (plus (A) (-C1))) op (C2)
11381 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11382 comparison in the wider mode. One of the following two conditions
11383 must be true in order for this to be valid:
11385 1. The mode extension results in the same bit pattern being added
11386 on both sides and the comparison is equality or unsigned. As
11387 C2 has been truncated to fit in MODE, the pattern can only be
11388 all 0s or all 1s.
11390 2. The mode extension results in the sign bit being copied on
11391 each side.
11393 The difficulty here is that we have predicates for A but not for
11394 (A - C1) so we need to check that C1 is within proper bounds so
11395 as to perturbate A as little as possible. */
11402 {
11411 /* (A - C1) zero-extends if it is positive and sign-extends
11412 if it is negative, C2 both zero- and sign-extends. */
11416 /* (A - C1) sign-extends if it is positive and 1-extends
11417 if it is negative, C2 both sign- and 1-extends. */
11424 /* (A - C1) always sign-extends, like C2. */
11428 {
11431 }
11432 }
11434 /* If the inner mode is narrower and we are extracting the low part,
11435 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11439 else
11442 /* ... fall through ... */
11452 {
11455 }
11459 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11460 this for equality comparisons due to pathological cases involving
11461 overflows. */
11465 {
11469 }
11471 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11474 {
11478 }
11482 /* We used to optimize signed comparisons against zero, but that
11483 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11484 arrive here as equality comparisons, or (GEU, LTU) are
11485 optimized away. No need to special-case them. */
11487 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11488 (eq B (minus A C)), whichever simplifies. We can only do
11489 this for equality comparisons due to pathological cases involving
11490 overflows. */
11494 {
11498 }
11503 {
11507 }
11509 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11510 of bits in X minus 1, is one iff X > 0. */
11515 {
11519 }
11523 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11524 if C is zero or B is a constant. */
11528 {
11532 }
11540 /* We can't do anything if OP0 is a condition code value, rather
11541 than an actual data value. */
11547 /* Get the two operands being compared. */
11550 else
11553 /* Check for the cases where we simply want the result of the
11554 earlier test or the opposite of that result. */
11558 {
11562 else
11566 {
11571 }
11572 }
11576 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11577 iff X <= 0. */
11581 {
11585 }
11589 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11590 will be converted to a ZERO_EXTRACT later. */
11594 {
11599 }
11601 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11602 zero and X is a comparison and C1 and C2 describe only bits set
11603 in STORE_FLAG_VALUE, we can compare with X. */
11611 {
11618 {
11621 }
11622 }
11624 /* If we are doing an equality comparison of an AND of a bit equal
11625 to the sign bit, replace this with a LT or GE comparison of
11626 the underlying value. */
11633 {
11637 }
11639 /* If this AND operation is really a ZERO_EXTEND from a narrower
11640 mode, the constant fits within that mode, and this is either an
11641 equality or unsigned comparison, try to do this comparison in
11642 the narrower mode.
11644 Note that in:
11646 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11647 -> (ne:DI (reg:SI 4) (const_int 0))
11649 unless TRULY_NOOP_TRUNCATION allows it or the register is
11650 known to hold a value of the required mode the
11651 transformation is invalid. */
11662 {
11665 }
11667 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11668 fits in both M1 and M2 and the SUBREG is either paradoxical
11669 or represents the low part, permute the SUBREG and the AND
11670 and try again. */
11672 {
11675 /* Require an integral mode, to avoid creating something like
11676 (AND:SF ...). */
11678 /* It is unsafe to commute the AND into the SUBREG if the
11679 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11680 not defined. As originally written the upper bits
11681 have a defined value due to the AND operation.
11682 However, if we commute the AND inside the SUBREG then
11683 they no longer have defined values and the meaning of
11684 the code has been changed. */
11686 #ifdef WORD_REGISTER_OPERATIONS
11689 #endif
11699 {
11705 }
11706 }
11708 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11712 {
11717 }
11719 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11720 (eq (and (lshiftrt X) 1) 0).
11721 Also handle the case where (not X) is expressed using xor. */
11725 {
11737 {
11738 op0
11743 }
11744 }
11748 /* If we have (compare (ashift FOO N) (const_int C)) and
11749 the high order N bits of FOO (N+1 if an inequality comparison)
11750 are known to be zero, we can do this by comparing FOO with C
11751 shifted right N bits so long as the low-order N bits of C are
11752 zero. */
11764 {
11765 /* We must perform a logical shift, not an arithmetic one,
11766 as we want the top N bits of C to be zero. */
11773 }
11775 /* If we are doing a sign bit comparison, it means we are testing
11776 a particular bit. Convert it to the appropriate AND. */
11779 {
11786 }
11788 /* If this an equality comparison with zero and we are shifting
11789 the low bit to the sign bit, we can convert this to an AND of the
11790 low-order bit. */
11794 {
11797 }
11801 /* If this is an equality comparison with zero, we can do this
11802 as a logical shift, which might be much simpler. */
11805 {
11810 }
11812 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11813 do the comparison in a narrower mode. */
11823 {
11826 }
11828 /* Likewise if OP0 is a PLUS of a sign extension with a
11829 constant, which is usually represented with the PLUS
11830 between the shifts. */
11842 {
11850 new_const);
11852 }
11854 /* ... fall through ... */
11856 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11857 the low order N bits of FOO are known to be zero, we can do this
11858 by comparing FOO with C shifted left N bits so long as no
11859 overflow occurs. Even if the low order N bits of FOO aren't known
11860 to be zero, if the comparison is >= or < we can use the same
11861 optimization and for > or <= by setting all the low
11862 order N bits in the comparison constant. */
11873 {
11874 unsigned HOST_WIDE_INT low_bits
11879 {
11880 /* If the shift was logical, then we must make the condition
11881 unsigned. */
11889 const_op
11894 }
11895 }
11897 /* If we are using this shift to extract just the sign bit, we
11898 can replace this with an LT or GE comparison. */
11903 {
11907 }
11912 }
11915 }
11917 /* Now make any compound operations involved in this comparison. Then,
11918 check for an outmost SUBREG on OP0 that is not doing anything or is
11919 paradoxical. The latter transformation must only be performed when
11920 it is known that the "extra" bits will be the same in op0 and op1 or
11921 that they don't matter. There are three cases to consider:
11923 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11924 care bits and we can assume they have any convenient value. So
11925 making the transformation is safe.
11927 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11928 In this case the upper bits of op0 are undefined. We should not make
11929 the simplification in that case as we do not know the contents of
11930 those bits.
11932 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11933 UNKNOWN. In that case we know those bits are zeros or ones. We must
11934 also be sure that they are the same as the upper bits of op1.
11936 We can never remove a SUBREG for a non-equality comparison because
11937 the sign bit is in a different place in the underlying object. */
11946 {
11948 {
11949 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11950 implemented. */
11952 {
11955 }
11956 }
11962 {
11968 }
11969 }
11971 /* We now do the opposite procedure: Some machines don't have compare
11972 insns in all modes. If OP0's mode is an integer mode smaller than a
11973 word and we can't do a compare in that mode, see if there is a larger
11974 mode for which we can do the compare. There are a number of cases in
11975 which we can use the wider mode. */
11985 {
11988 /* If this is a test for negative, we can make an explicit
11989 test of the sign bit. Test this first so we can use
11990 a paradoxical subreg to extend OP0. */
11994 {
11995 unsigned HOST_WIDE_INT sign
12002 }
12004 /* If the only nonzero bits in OP0 and OP1 are those in the
12005 narrower mode and this is an equality or unsigned comparison,
12006 we can use the wider mode. Similarly for sign-extended
12007 values, in which case it is true for all comparisons. */
12024 {
12025 /* If OP0 is an AND and we don't have an AND in MODE either,
12026 make a new AND in the proper mode. */
12034 else
12035 {
12037 {
12040 }
12041 else
12042 {
12045 }
12047 }
12048 }
12049 }
12051 /* We may have changed the comparison operands. Re-canonicalize. */
12053 {
12056 }
12058 /* If this machine only supports a subset of valid comparisons, see if we
12059 can convert an unsupported one into a supported one. */
12066 }
12067 \f
12068 /* Utility function for record_value_for_reg. Count number of
12069 rtxs in X. */
12070 static int
12072 {
12079 {
12099 }
12110 }
12111 \f
12112 /* Utility function for following routine. Called when X is part of a value
12113 being stored into last_set_value. Sets last_set_table_tick
12114 for each register mentioned. Similar to mention_regs in cse.c */
12116 static void
12118 {
12124 {
12130 {
12133 }
12136 }
12140 {
12141 /* Check for identical subexpressions. If x contains
12142 identical subexpression we only have to traverse one of
12143 them. */
12145 {
12146 /* Note that at this point x1 has already been
12147 processed. */
12151 /* If x0 and x1 are identical then there is no need to
12152 process x0. */
12156 /* If x0 is identical to a subexpression of x1 then while
12157 processing x1, x0 has already been processed. Thus we
12158 are done with x. */
12163 /* If x1 is identical to a subexpression of x0 then we
12164 still have to process the rest of x0. */
12167 {
12170 }
12171 }
12174 }
12178 }
12180 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12181 are saying that the register is clobbered and we no longer know its
12182 value. If INSN is zero, don't update reg_stat[].last_set; this is
12183 only permitted with VALUE also zero and is used to invalidate the
12184 register. */
12186 static void
12188 {
12194 /* If VALUE contains REG and we have a previous value for REG, substitute
12195 the previous value. */
12197 {
12198 rtx tem;
12200 /* Set things up so get_last_value is allowed to see anything set up to
12201 our insn. */
12205 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12206 it isn't going to be useful and will take a lot of time to process,
12207 so just use the CLOBBER. */
12210 {
12216 {
12217 /* If there are two or more occurrences of REG in VALUE,
12218 prevent the value from growing too much. */
12221 }
12224 }
12225 }
12227 /* For each register modified, show we don't know its value, that
12228 we don't know about its bitwise content, that its value has been
12229 updated, and that we don't know the location of the death of the
12230 register. */
12232 {
12244 }
12246 /* Mark registers that are being referenced in this value. */
12250 /* Now update the status of each register being set.
12251 If someone is using this register in this block, set this register
12252 to invalid since we will get confused between the two lives in this
12253 basic block. This makes using this register always invalid. In cse, we
12254 scan the table to invalidate all entries using this register, but this
12255 is too much work for us. */
12258 {
12264 else
12266 }
12268 /* The value being assigned might refer to X (like in "x++;"). In that
12269 case, we must replace it with (clobber (const_int 0)) to prevent
12270 infinite loops. */
12273 {
12277 }
12279 /* For the main register being modified, update the value, the mode, the
12280 nonzero bits, and the number of sign bit copies. */
12285 {
12293 rsp->last_set_sign_bit_copies
12295 }
12296 }
12298 /* Called via note_stores from record_dead_and_set_regs to handle one
12299 SET or CLOBBER in an insn. DATA is the instruction in which the
12300 set is occurring. */
12302 static void
12304 {
12311 {
12315 }
12318 {
12319 /* If we are setting the whole register, we know its value. Otherwise
12320 show that we don't know the value. We can handle SUBREG in
12321 some cases. */
12332 else
12334 }
12336 /* Ignore pushes, they clobber nothing. */
12339 }
12341 /* Update the records of when each REG was most recently set or killed
12342 for the things done by INSN. This is the last thing done in processing
12343 INSN in the combiner loop.
12345 We update reg_stat[], in particular fields last_set, last_set_value,
12346 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12347 last_death, and also the similar information mem_last_set (which insn
12348 most recently modified memory) and last_call_luid (which insn was the
12349 most recent subroutine call). */
12351 static void
12353 {
12354 rtx link;
12358 {
12361 {
12366 {
12371 }
12372 }
12375 }
12378 {
12379 hard_reg_set_iterator hrsi;
12381 {
12393 }
12397 /* We can't combine into a call pattern. Remember, though, that
12398 the return value register is set at this LUID. We could
12399 still replace a register with the return value from the
12400 wrong subroutine call! */
12402 }
12403 else
12405 }
12407 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12408 register present in the SUBREG, so for each such SUBREG go back and
12409 adjust nonzero and sign bit information of the registers that are
12410 known to have some zero/sign bits set.
12412 This is needed because when combine blows the SUBREGs away, the
12413 information on zero/sign bits is lost and further combines can be
12414 missed because of that. */
12416 static void
12418 {
12420 rtx set;
12428 {
12437 {
12440 }
12444 {
12447 }
12450 {
12453 }
12454 else
12456 }
12457 }
12459 /* Check if X, a register, is known to contain a value already
12460 truncated to MODE. In this case we can use a subreg to refer to
12461 the truncated value even though in the generic case we would need
12462 an explicit truncation. */
12464 static bool
12466 {
12478 }
12480 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12481 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12482 might be able to turn a truncate into a subreg using this information.
12483 Return -1 if traversing *P is complete or 0 otherwise. */
12485 static int
12487 {
12493 {
12504 }
12505 /* ??? For hard-regs we now record everything. We might be able to
12506 optimize this using last_set_mode. */
12509 else
12517 {
12520 }
12523 }
12525 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12526 the modes they are used in. This can help truning TRUNCATEs into
12527 SUBREGs. */
12529 static void
12531 {
12533 }
12535 /* Scan X for promoted SUBREGs. For each one found,
12536 note what it implies to the registers used in it. */
12538 static void
12540 {
12545 else
12546 {
12552 {
12562 }
12563 }
12564 }
12565 \f
12566 /* Verify that all the registers and memory references mentioned in *LOC are
12567 still valid. *LOC was part of a value set in INSN when label_tick was
12568 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12569 the invalid references with (clobber (const_int 0)) and return 1. This
12570 replacement is useful because we often can get useful information about
12571 the form of a value (e.g., if it was produced by a shift that always
12572 produces -1 or 0) even though we don't know exactly what registers it
12573 was produced from. */
12575 static int
12577 {
12584 {
12590 {
12593 /* If this is a pseudo-register that was only set once and not
12594 live at the beginning of the function, it is always valid. */
12597 && (!REGNO_REG_SET_P
12599 regno)))
12601 {
12605 }
12606 }
12609 }
12610 /* If this is a memory reference, make sure that there were no stores after
12611 it that might have clobbered the value. We don't have alias info, so we
12612 assume any store invalidates it. Moreover, we only have local UIDs, so
12613 we also assume that there were stores in the intervening basic blocks. */
12616 {
12620 }
12623 {
12625 {
12626 /* Check for identical subexpressions. If x contains
12627 identical subexpression we only have to traverse one of
12628 them. */
12630 {
12631 /* Note that at this point x0 has already been checked
12632 and found valid. */
12636 /* If x0 and x1 are identical then x is also valid. */
12640 /* If x1 is identical to a subexpression of x0 then
12641 while checking x0, x1 has already been checked. Thus
12642 it is valid and so as x. */
12647 /* If x0 is identical to a subexpression of x1 then x is
12648 valid iff the rest of x1 is valid. */
12651 return
12655 }
12660 }
12666 }
12668 /* If we haven't found a reason for it to be invalid, it is valid. */
12670 }
12672 /* Get the last value assigned to X, if known. Some registers
12673 in the value may be replaced with (clobber (const_int 0)) if their value
12674 is known longer known reliably. */
12676 static rtx
12678 {
12680 rtx value;
12683 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12684 then convert it to the desired mode. If this is a paradoxical SUBREG,
12685 we cannot predict what values the "extra" bits might have. */
12699 /* If we don't have a value, or if it isn't for this basic block and
12700 it's either a hard register, set more than once, or it's a live
12701 at the beginning of the function, return 0.
12703 Because if it's not live at the beginning of the function then the reg
12704 is always set before being used (is never used without being set).
12705 And, if it's set only once, and it's always set before use, then all
12706 uses must have the same last value, even if it's not from this basic
12707 block. */
12713 || REGNO_REG_SET_P
12717 /* If the value was set in a later insn than the ones we are processing,
12718 we can't use it even if the register was only set once. */
12723 /* If the value has all its registers valid, return it. */
12727 /* Otherwise, make a copy and replace any invalid register with
12728 (clobber (const_int 0)). If that fails for some reason, return 0. */
12735 }
12736 \f
12737 /* Return nonzero if expression X refers to a REG or to memory
12738 that is set in an instruction more recent than FROM_LUID. */
12740 static int
12742 {
12748 {
12752 #ifdef PUSH_ROUNDING
12753 /* Don't allow uses of the stack pointer to be moved,
12754 because we don't know whether the move crosses a push insn. */
12757 #endif
12759 {
12765 }
12767 }
12775 {
12777 {
12782 }
12786 }
12788 }
12789 \f
12790 /* Define three variables used for communication between the following
12791 routines. */
12796 /* Function called via note_stores from reg_dead_at_p.
12798 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12799 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12801 static void
12803 {
12813 }
12815 /* Return nonzero if REG is known to be dead at INSN.
12817 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12818 referencing REG, it is dead. If we hit a SET referencing REG, it is
12819 live. Otherwise, see if it is live or dead at the start of the basic
12820 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12821 must be assumed to be always live. */
12823 static int
12825 {
12826 basic_block block;
12829 /* Set variables for reg_dead_at_p_1. */
12835 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12836 we allow the machine description to decide whether use-and-clobber
12837 patterns are OK. */
12839 {
12843 }
12845 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12846 beginning of basic block. */
12849 {
12851 {
12858 }
12864 }
12866 /* Look at live-in sets for the basic block that we were in. */
12872 }
12873 \f
12874 /* Note hard registers in X that are used. */
12876 static void
12878 {
12884 {
12888 CASE_CONST_ANY:
12893 #ifdef HAVE_cc0
12894 /* CC0 must die in the insn after it is set, so we don't need to take
12895 special note of it here. */
12897 #endif
12901 /* If we are clobbering a MEM, mark any hard registers inside the
12902 address as used. */
12909 /* A hard reg in a wide mode may really be multiple registers.
12910 If so, mark all of them just like the first. */
12912 {
12913 /* None of this applies to the stack, frame or arg pointers. */
12915 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12917 #endif
12918 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12920 #endif
12925 }
12929 {
12930 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12931 the address. */
12943 }
12948 }
12950 /* Recursively scan the operands of this expression. */
12952 {
12956 {
12960 {
12965 }
12966 }
12967 }
12968 }
12969 \f
12970 /* Remove register number REGNO from the dead registers list of INSN.
12972 Return the note used to record the death, if there was one. */
12974 rtx
12976 {
12983 }
12985 /* For each register (hardware or pseudo) used within expression X, if its
12986 death is in an instruction with luid between FROM_LUID (inclusive) and
12987 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12988 list headed by PNOTES.
12990 That said, don't move registers killed by maybe_kill_insn.
12992 This is done when X is being merged by combination into TO_INSN. These
12993 notes will then be distributed as needed. */
12995 static void
12998 {
13004 {
13008 /* Don't move the register if it gets killed in between from and to. */
13017 {
13020 /* It is possible for the call above to return 0. This can occur
13021 when last_death points to I2 or I1 that we combined with.
13022 In that case make a new note.
13024 We must also check for the case where X is a hard register
13025 and NOTE is a death note for a range of hard registers
13026 including X. In that case, we must put REG_DEAD notes for
13027 the remaining registers in place of NOTE. */
13032 {
13041 }
13043 /* If we didn't find any note, or if we found a REG_DEAD note that
13044 covers only part of the given reg, and we have a multi-reg hard
13045 register, then to be safe we must check for REG_DEAD notes
13046 for each register other than the first. They could have
13047 their own REG_DEAD notes lying around. */
13054 {
13061 else
13067 }
13070 {
13073 }
13074 else
13076 }
13079 }
13082 {
13087 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13088 that accesses one word of a multi-word item, some
13089 piece of everything register in the expression is used by
13090 this insn, so remove any old death. */
13091 /* ??? So why do we test for equality of the sizes? */
13100 {
13103 }
13105 /* If this is some other SUBREG, we know it replaces the entire
13106 value, so use that as the destination. */
13110 /* If this is a MEM, adjust deaths of anything used in the address.
13111 For a REG (the only other possibility), the entire value is
13112 being replaced so the old value is not used in this insn. */
13118 }
13127 {
13129 {
13134 }
13137 }
13138 }
13139 \f
13140 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13141 pattern of an insn. X must be a REG. */
13143 static int
13145 {
13149 {
13151 rtx target;
13158 else
13175 }
13183 }
13184 \f
13185 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13186 as appropriate. I3 and I2 are the insns resulting from the combination
13187 insns including FROM (I2 may be zero).
13189 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13190 not need REG_DEAD notes because they are being substituted for. This
13191 saves searching in the most common cases.
13193 Each note in the list is either ignored or placed on some insns, depending
13194 on the type of note. */
13196 static void
13199 {
13201 rtx tem;
13204 {
13209 {
13212 /* Doesn't matter much where we put this, as long as it's somewhere.
13213 It is preferable to keep these notes on branches, which is most
13214 likely to be i3. */
13221 else
13222 {
13225 }
13229 /* These notes must remain with the call or trapping instruction. */
13234 else
13235 {
13241 /* ??? Otherwise assume we've combined things such that we
13242 can now prove that the instructions can't trap. Drop the
13243 note in this case. */
13244 }
13248 /* ??? How to distribute between i3-i1. Assume i3 contains the
13249 entire adjustment. Assert i3 contains at least some adjust. */
13251 {
13253 /* fixup_args_size_notes looks at REG_NORETURN note,
13254 so ensure the note is placed there first. */
13256 {
13260 {
13266 }
13267 }
13269 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13270 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13273 && !ACCUMULATE_OUTGOING_ARGS
13275 }
13281 /* These notes must remain with the call. It should not be
13282 possible for both I2 and I3 to be a call. */
13285 else
13286 {
13289 }
13293 /* Any clobbers for i3 may still exist, and so we must process
13294 REG_UNUSED notes from that insn.
13296 Any clobbers from i2 or i1 can only exist if they were added by
13297 recog_for_combine. In that case, recog_for_combine created the
13298 necessary REG_UNUSED notes. Trying to keep any original
13299 REG_UNUSED notes from these insns can cause incorrect output
13300 if it is for the same register as the original i3 dest.
13301 In that case, we will notice that the register is set in i3,
13302 and then add a REG_UNUSED note for the destination of i3, which
13303 is wrong. However, it is possible to have REG_UNUSED notes from
13304 i2 or i1 for register which were both used and clobbered, so
13305 we keep notes from i2 or i1 if they will turn into REG_DEAD
13306 notes. */
13308 /* If this register is set or clobbered in I3, put the note there
13309 unless there is one already. */
13311 {
13319 }
13320 /* Otherwise, if this register is used by I3, then this register
13321 now dies here, so we must put a REG_DEAD note here unless there
13322 is one already. */
13328 {
13331 }
13337 /* These notes say something about results of an insn. We can
13338 only support them if they used to be on I3 in which case they
13339 remain on I3. Otherwise they are ignored.
13341 If the note refers to an expression that is not a constant, we
13342 must also ignore the note since we cannot tell whether the
13343 equivalence is still true. It might be possible to do
13344 slightly better than this (we only have a problem if I2DEST
13345 or I1DEST is present in the expression), but it doesn't
13346 seem worth the trouble. */
13354 /* These notes say something about how a register is used. They must
13355 be present on any use of the register in I2 or I3. */
13360 {
13363 else
13365 }
13370 /* This can show up in several ways -- either directly in the
13371 pattern, or hidden off in the constant pool with (or without?)
13372 a REG_EQUAL note. */
13373 /* ??? Ignore the without-reg_equal-note problem for now. */
13385 {
13388 else
13390 }
13392 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13393 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13394 there. */
13399 {
13406 }
13412 {
13420 }
13424 /* This note says something about the value of a register prior
13425 to the execution of an insn. It is too much trouble to see
13426 if the note is still correct in all situations. It is better
13427 to simply delete it. */
13431 /* If we replaced the right hand side of FROM_INSN with a
13432 REG_EQUAL note, the original use of the dying register
13433 will not have been combined into I3 and I2. In such cases,
13434 FROM_INSN is guaranteed to be the first of the combined
13435 instructions, so we simply need to search back before
13436 FROM_INSN for the previous use or set of this register,
13437 then alter the notes there appropriately.
13439 If the register is used as an input in I3, it dies there.
13440 Similarly for I2, if it is nonzero and adjacent to I3.
13442 If the register is not used as an input in either I3 or I2
13443 and it is not one of the registers we were supposed to eliminate,
13444 there are two possibilities. We might have a non-adjacent I2
13445 or we might have somehow eliminated an additional register
13446 from a computation. For example, we might have had A & B where
13447 we discover that B will always be zero. In this case we will
13448 eliminate the reference to A.
13450 In both cases, we must search to see if we can find a previous
13451 use of A and put the death note there. */
13457 else
13458 {
13469 && !(i2mod
13471 i2mod_old_rhs)))
13476 }
13479 {
13483 {
13485 {
13489 }
13491 /* If the register is being set at TEM, see if that is all
13492 TEM is doing. If so, delete TEM. Otherwise, make this
13493 into a REG_UNUSED note instead. Don't delete sets to
13494 global register vars. */
13498 {
13501 #ifdef HAVE_cc0
13503 #endif
13511 ;
13513 /* Verify that it was the set, and not a clobber that
13514 modified the register.
13516 CC0 targets must be careful to maintain setter/user
13517 pairs. If we cannot delete the setter due to side
13518 effects, mark the user with an UNUSED note instead
13519 of deleting it. */
13523 #ifdef HAVE_cc0
13527 #endif
13528 )
13529 {
13530 /* Move the notes and links of TEM elsewhere.
13531 This might delete other dead insns recursively.
13532 First set the pattern to something that won't use
13533 any register. */
13547 #ifdef HAVE_cc0
13548 /* Delete the setter too. */
13550 {
13563 }
13564 #endif
13565 }
13566 else
13567 {
13570 /* If there isn't already a REG_UNUSED note, put one
13571 here. Do not place a REG_DEAD note, even if
13572 the register is also used here; that would not
13573 match the algorithm used in lifetime analysis
13574 and can cause the consistency check in the
13575 scheduler to fail. */
13580 }
13581 }
13585 {
13588 /* If we are doing a 3->2 combination, and we have a
13589 register which formerly died in i3 and was not used
13590 by i2, which now no longer dies in i3 and is used in
13591 i2 but does not die in i2, and place is between i2
13592 and i3, then we may need to move a link from place to
13593 i2. */
13595 && from_insn
13598 {
13602 }
13604 }
13608 }
13610 }
13612 /* If the register is set or already dead at PLACE, we needn't do
13613 anything with this note if it is still a REG_DEAD note.
13614 We check here if it is set at all, not if is it totally replaced,
13615 which is what `dead_or_set_p' checks, so also check for it being
13616 set partially. */
13619 {
13625 {
13626 /* Unless the register previously died in PLACE, clear
13627 last_death. [I no longer understand why this is
13628 being done.] */
13632 }
13633 else
13636 /* If this is a death note for a hard reg that is occupying
13637 multiple registers, ensure that we are still using all
13638 parts of the object. If we find a piece of the object
13639 that is unused, we must arrange for an appropriate REG_DEAD
13640 note to be added for it. However, we can't just emit a USE
13641 and tag the note to it, since the register might actually
13642 be dead; so we recourse, and the recursive call then finds
13643 the previous insn that used this register. */
13647 {
13656 {
13659 }
13662 {
13663 /* Put only REG_DEAD notes for pieces that are
13664 not already dead or set. */
13668 {
13675 {
13677 NULL_RTX);
13681 NULL_RTX);
13682 }
13688 {
13690 {
13694 }
13698 {
13701 }
13702 }
13703 }
13706 }
13707 }
13708 }
13712 /* Any other notes should not be present at this point in the
13713 compilation. */
13715 }
13718 {
13721 }
13725 }
13726 }
13727 \f
13728 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13729 I3, I2, and I1 to new locations. This is also called to add a link
13730 pointing at I3 when I3's destination is changed. */
13732 static void
13734 {
13738 {
13740 rtx insn;
13745 /* If the insn that this link points to is a NOTE or isn't a single
13746 set, ignore it. In the latter case, it isn't clear what we
13747 can do other than ignore the link, since we can't tell which
13748 register it was for. Such links wouldn't be used by combine
13749 anyway.
13751 It is not possible for the destination of the target of the link to
13752 have been changed by combine. The only potential of this is if we
13753 replace I3, I2, and I1 by I3 and I2. But in that case the
13754 destination of I2 also remains unchanged. */
13765 /* A LOG_LINK is defined as being placed on the first insn that uses
13766 a register and points to the insn that sets the register. Start
13767 searching at the next insn after the target of the link and stop
13768 when we reach a set of the register or the end of the basic block.
13770 Note that this correctly handles the link that used to point from
13771 I3 to I2. Also note that not much searching is typically done here
13772 since most links don't point very far away. */
13781 {
13785 }
13788 {
13791 }
13795 /* If we found a place to put the link, place it there unless there
13796 is already a link to the same insn as LINK at that point. */
13799 {
13807 {
13811 /* Set added_links_insn to the earliest insn we added a
13812 link to. */
13816 }
13817 }
13818 }
13819 }
13820 \f
13821 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13822 Check whether the expression pointer to by LOC is a register or
13823 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13824 Otherwise return zero. */
13826 static int
13828 {
13836 }
13838 /* Check for any register or memory mentioned in EQUIV that is not
13839 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13840 of EXPR where some registers may have been replaced by constants. */
13842 static bool
13844 {
13846 }
13847 \f
13848 DEBUG_FUNCTION void
13850 {
13851 fprintf
13853 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13855 }
13857 void
13859 {
13860 fprintf
13862 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13864 }
13865 \f
13866 static bool
13868 {
13870 }
13872 /* Try combining insns through substitution. */
13873 static unsigned int
13875 {
13884 rebuild_jump_labels_after_combine
13887 /* Combining insns may have turned an indirect jump into a
13888 direct jump. Rebuild the JUMP_LABEL fields of jumping
13889 instructions. */
13891 {
13896 }
13900 }
13905 {
13917 };
13920 {
13924 {}
13926 /* opt_pass methods: */
13934 rtl_opt_pass *
13936 {
13938 }