1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack
{
73 int first_gp_reg_save
; /* first callee saved GP register used */
74 int first_fp_reg_save
; /* first callee saved FP register used */
75 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
76 int lr_save_p
; /* true if the link reg needs to be saved */
77 int cr_save_p
; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask
; /* mask of vec registers to save */
79 int toc_save_p
; /* true if the TOC needs to be saved */
80 int push_p
; /* true if we need to allocate stack space */
81 int calls_p
; /* true if the function makes any calls */
82 int world_save_p
; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi
; /* which ABI to use */
85 int gp_save_offset
; /* offset to save GP regs from initial SP */
86 int fp_save_offset
; /* offset to save FP regs from initial SP */
87 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset
; /* offset to save LR from initial SP */
89 int cr_save_offset
; /* offset to save CR from initial SP */
90 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
92 int toc_save_offset
; /* offset to save the TOC pointer */
93 int varargs_save_offset
; /* offset to save the varargs registers */
94 int ehrd_offset
; /* offset to EH return data */
95 int reg_size
; /* register size (4 or 8) */
96 int varargs_size
; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size
; /* variable save area size */
98 int parm_size
; /* outgoing parameter size */
99 int save_size
; /* save area size */
100 int fixed_size
; /* fixed size of stack frame */
101 int gp_size
; /* size of saved GP registers */
102 int fp_size
; /* size of saved FP registers */
103 int altivec_size
; /* size of saved AltiVec registers */
104 int cr_size
; /* size to hold CR if not in save_size */
105 int lr_size
; /* size to hold LR if not in save_size */
106 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size
; /* size of altivec alignment padding if
109 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size
;
111 int toc_size
; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
113 int spe_64bit_regs_used
;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu
;
119 struct rs6000_cpu_select rs6000_select
[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint
;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups
;
133 /* Support adjust_priority scheduler hook
134 and -mprioritize-restricted-insns= option. */
135 const char *rs6000_sched_restricted_insns_priority_str
;
136 int rs6000_sched_restricted_insns_priority
;
138 /* Support for -msched-costly-dep option. */
139 const char *rs6000_sched_costly_dep_str
;
140 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
142 /* Support for -minsert-sched-nops option. */
143 const char *rs6000_sched_insert_nops_str
;
144 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load
;
149 /* Size of long double */
150 const char *rs6000_long_double_size_string
;
151 int rs6000_long_double_type_size
;
153 /* Whether -mabi=altivec has appeared */
154 int rs6000_altivec_abi
;
156 /* Whether VRSAVE instructions should be generated. */
157 int rs6000_altivec_vrsave
;
159 /* String from -mvrsave= option. */
160 const char *rs6000_altivec_vrsave_string
;
162 /* Nonzero if we want SPE ABI extensions. */
165 /* Whether isel instructions should be generated. */
168 /* Whether SPE simd instructions should be generated. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs
= 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi
;
177 /* String from -mfloat-gprs=. */
178 const char *rs6000_float_gprs_string
;
180 /* String from -misel=. */
181 const char *rs6000_isel_string
;
183 /* String from -mspe=. */
184 const char *rs6000_spe_string
;
186 /* Set to nonzero once AIX common-mode calls have been defined. */
187 static GTY(()) int common_mode_defined
;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx rs6000_compare_op0
, rs6000_compare_op1
;
192 int rs6000_compare_fp_p
;
194 /* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196 int rs6000_pic_labelno
;
199 /* Which abi to adhere to */
200 const char *rs6000_abi_name
;
202 /* Semantics of the small data area */
203 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
205 /* Which small data model to use */
206 const char *rs6000_sdata_name
= (char *)0;
208 /* Counter for labels which are to be placed in .fixup. */
209 int fixuplabelno
= 0;
212 /* Bit size of immediate TLS offsets and string from which it is decoded. */
213 int rs6000_tls_size
= 32;
214 const char *rs6000_tls_size_string
;
216 /* ABI enumeration available for subtarget to use. */
217 enum rs6000_abi rs6000_current_abi
;
219 /* ABI string from -mabi= option. */
220 const char *rs6000_abi_string
;
222 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
226 const char *rs6000_debug_name
;
227 int rs6000_debug_stack
; /* debug stack applications */
228 int rs6000_debug_arg
; /* debug argument handling */
230 /* Value is TRUE if register/mode pair is acceptable. */
231 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
234 static GTY(()) tree opaque_V2SI_type_node
;
235 static GTY(()) tree opaque_V2SF_type_node
;
236 static GTY(()) tree opaque_p_V2SI_type_node
;
237 static GTY(()) tree V16QI_type_node
;
238 static GTY(()) tree V2SI_type_node
;
239 static GTY(()) tree V2SF_type_node
;
240 static GTY(()) tree V4HI_type_node
;
241 static GTY(()) tree V4SI_type_node
;
242 static GTY(()) tree V4SF_type_node
;
243 static GTY(()) tree V8HI_type_node
;
244 static GTY(()) tree unsigned_V16QI_type_node
;
245 static GTY(()) tree unsigned_V8HI_type_node
;
246 static GTY(()) tree unsigned_V4SI_type_node
;
247 static GTY(()) tree bool_char_type_node
; /* __bool char */
248 static GTY(()) tree bool_short_type_node
; /* __bool short */
249 static GTY(()) tree bool_int_type_node
; /* __bool int */
250 static GTY(()) tree pixel_type_node
; /* __pixel */
251 static GTY(()) tree bool_V16QI_type_node
; /* __vector __bool char */
252 static GTY(()) tree bool_V8HI_type_node
; /* __vector __bool short */
253 static GTY(()) tree bool_V4SI_type_node
; /* __vector __bool int */
254 static GTY(()) tree pixel_V8HI_type_node
; /* __vector __pixel */
256 int rs6000_warn_altivec_long
= 1; /* On by default. */
257 const char *rs6000_warn_altivec_long_switch
;
259 const char *rs6000_traceback_name
;
261 traceback_default
= 0,
267 /* Flag to say the TOC is initialized */
269 char toc_label_name
[10];
271 /* Alias set for saves and restores from the rs6000 stack. */
272 static GTY(()) int rs6000_sr_alias_set
;
274 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
275 The only place that looks at this is rs6000_set_default_type_attributes;
276 everywhere else should rely on the presence or absence of a longcall
277 attribute on the function declaration. Exception: init_cumulative_args
278 looks at it too, for libcalls. */
279 int rs6000_default_long_calls
;
280 const char *rs6000_longcall_switch
;
282 /* Control alignment for fields within structures. */
283 /* String from -malign-XXXXX. */
284 const char *rs6000_alignment_string
;
285 int rs6000_alignment_flags
;
287 struct builtin_description
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
293 const enum insn_code icode
;
294 const char *const name
;
295 const enum rs6000_builtins code
;
298 /* Target cpu costs. */
300 struct processor_costs
{
301 const int mulsi
; /* cost of SImode multiplication. */
302 const int mulsi_const
; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9
; /* cost of SImode mult by short constant. */
304 const int muldi
; /* cost of DImode multiplication. */
305 const int divsi
; /* cost of SImode division. */
306 const int divdi
; /* cost of DImode division. */
307 const int fp
; /* cost of simple SFmode and DFmode insns. */
308 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv
; /* cost of SFmode division (fdivs). */
310 const int ddiv
; /* cost of DFmode division (fdiv). */
313 const struct processor_costs
*rs6000_cost
;
315 /* Processor costs (relative to an add) */
317 /* Instruction size costs on 32bit processors. */
319 struct processor_costs size32_cost
= {
320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
332 /* Instruction size costs on 64bit processors. */
334 struct processor_costs size64_cost
= {
335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost
= {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
362 /* Instruction costs on RIOS2 processors. */
364 struct processor_costs rios2_cost
= {
365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
377 /* Instruction costs on RS64A processors. */
379 struct processor_costs rs64a_cost
= {
380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
392 /* Instruction costs on MPCCORE processors. */
394 struct processor_costs mpccore_cost
= {
395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
407 /* Instruction costs on PPC403 processors. */
409 struct processor_costs ppc403_cost
= {
410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
422 /* Instruction costs on PPC405 processors. */
424 struct processor_costs ppc405_cost
= {
425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
437 /* Instruction costs on PPC440 processors. */
439 struct processor_costs ppc440_cost
= {
440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
452 /* Instruction costs on PPC601 processors. */
454 struct processor_costs ppc601_cost
= {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
467 /* Instruction costs on PPC603 processors. */
469 struct processor_costs ppc603_cost
= {
470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
482 /* Instruction costs on PPC604 processors. */
484 struct processor_costs ppc604_cost
= {
485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
497 /* Instruction costs on PPC604e processors. */
499 struct processor_costs ppc604e_cost
= {
500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
512 /* Instruction costs on PPC620 processors. */
514 struct processor_costs ppc620_cost
= {
515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
527 /* Instruction costs on PPC630 processors. */
529 struct processor_costs ppc630_cost
= {
530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
542 /* Instruction costs on PPC750 and PPC7400 processors. */
544 struct processor_costs ppc750_cost
= {
545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
557 /* Instruction costs on PPC7450 processors. */
559 struct processor_costs ppc7450_cost
= {
560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
572 /* Instruction costs on PPC8540 processors. */
574 struct processor_costs ppc8540_cost
= {
575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
587 /* Instruction costs on POWER4 and POWER5 processors. */
589 struct processor_costs power4_cost
= {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
603 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
604 static rtx
rs6000_generate_compare (enum rtx_code
);
605 static void rs6000_maybe_dead (rtx
);
606 static void rs6000_emit_stack_tie (void);
607 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
608 static rtx
spe_synthesize_frame_save (rtx
);
609 static bool spe_func_has_64bit_regs_p (void);
610 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
612 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
613 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
614 static unsigned rs6000_hash_constant (rtx
);
615 static unsigned toc_hash_function (const void *);
616 static int toc_hash_eq (const void *, const void *);
617 static int constant_pool_expr_1 (rtx
, int *, int *);
618 static bool constant_pool_expr_p (rtx
);
619 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
620 static bool legitimate_indexed_address_p (rtx
, int);
621 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
622 static struct machine_function
* rs6000_init_machine_status (void);
623 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
624 #ifdef HAVE_GAS_HIDDEN
625 static void rs6000_assemble_visibility (tree
, int);
627 static int rs6000_ra_ever_killed (void);
628 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
629 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
630 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
631 static const char *rs6000_mangle_fundamental_type (tree
);
632 extern const struct attribute_spec rs6000_attribute_table
[];
633 static void rs6000_set_default_type_attributes (tree
);
634 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
635 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
636 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
638 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
639 static bool rs6000_return_in_memory (tree
, tree
);
640 static void rs6000_file_start (void);
642 static unsigned int rs6000_elf_section_type_flags (tree
, const char *, int);
643 static void rs6000_elf_asm_out_constructor (rtx
, int);
644 static void rs6000_elf_asm_out_destructor (rtx
, int);
645 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
646 static void rs6000_elf_select_section (tree
, int, unsigned HOST_WIDE_INT
);
647 static void rs6000_elf_unique_section (tree
, int);
648 static void rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
649 unsigned HOST_WIDE_INT
);
650 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
652 static bool rs6000_elf_in_small_data_p (tree
);
655 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
656 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
657 static void rs6000_xcoff_select_section (tree
, int, unsigned HOST_WIDE_INT
);
658 static void rs6000_xcoff_unique_section (tree
, int);
659 static void rs6000_xcoff_select_rtx_section (enum machine_mode
, rtx
,
660 unsigned HOST_WIDE_INT
);
661 static const char * rs6000_xcoff_strip_name_encoding (const char *);
662 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
663 static void rs6000_xcoff_file_start (void);
664 static void rs6000_xcoff_file_end (void);
667 static bool rs6000_binds_local_p (tree
);
669 static int rs6000_variable_issue (FILE *, int, rtx
, int);
670 static bool rs6000_rtx_costs (rtx
, int, int, int *);
671 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
672 static bool is_microcoded_insn (rtx
);
673 static int is_dispatch_slot_restricted (rtx
);
674 static bool is_cracked_insn (rtx
);
675 static bool is_branch_slot_insn (rtx
);
676 static int rs6000_adjust_priority (rtx
, int);
677 static int rs6000_issue_rate (void);
678 static bool rs6000_is_costly_dependence (rtx
, rtx
, rtx
, int, int);
679 static rtx
get_next_active_insn (rtx
, rtx
);
680 static bool insn_terminates_group_p (rtx
, enum group_termination
);
681 static bool is_costly_group (rtx
*, rtx
);
682 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
683 static int redefine_groups (FILE *, int, rtx
, rtx
);
684 static int pad_groups (FILE *, int, rtx
, rtx
);
685 static void rs6000_sched_finish (FILE *, int);
686 static int rs6000_use_sched_lookahead (void);
687 static tree
rs6000_builtin_mask_for_load (void);
689 static void rs6000_init_builtins (void);
690 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
691 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
692 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
693 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
694 static void altivec_init_builtins (void);
695 static void rs6000_common_init_builtins (void);
696 static void rs6000_init_libfuncs (void);
698 static void enable_mask_for_builtins (struct builtin_description
*, int,
699 enum rs6000_builtins
,
700 enum rs6000_builtins
);
701 static tree
build_opaque_vector_type (tree
, int);
702 static void spe_init_builtins (void);
703 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
704 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
705 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
706 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
707 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
708 static rs6000_stack_t
*rs6000_stack_info (void);
709 static void debug_stack_info (rs6000_stack_t
*);
711 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
712 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
713 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
714 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
715 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
716 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
717 const char *, tree
, rtx
);
718 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
719 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
720 static void rs6000_parse_abi_options (void);
721 static void rs6000_parse_alignment_option (void);
722 static void rs6000_parse_tls_size_option (void);
723 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
724 static void rs6000_parse_float_gprs_option (void);
725 static int first_altivec_reg_to_save (void);
726 static unsigned int compute_vrsave_mask (void);
727 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
728 static void is_altivec_return_reg (rtx
, void *);
729 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
730 int easy_vector_constant (rtx
, enum machine_mode
);
731 static bool is_ev64_opaque_type (tree
);
732 static rtx
rs6000_dwarf_register_span (rtx
);
733 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
734 static rtx
rs6000_tls_get_addr (void);
735 static rtx
rs6000_got_sym (void);
736 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
737 static const char *rs6000_get_some_local_dynamic_name (void);
738 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
739 static rtx
rs6000_complex_function_value (enum machine_mode
);
740 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
741 enum machine_mode
, tree
);
742 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
744 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
745 tree
, HOST_WIDE_INT
);
746 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
749 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
752 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, tree
, int, bool);
753 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
754 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
755 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
756 enum machine_mode
, tree
,
758 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
760 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
762 static const char *invalid_arg_for_unprototyped_fn (tree
, tree
, tree
);
764 static void macho_branch_islands (void);
765 static void add_compiler_branch_island (tree
, tree
, int);
766 static int no_previous_def (tree function_name
);
767 static tree
get_prev_label (tree function_name
);
768 static void rs6000_darwin_file_start (void);
771 static tree
rs6000_build_builtin_va_list (void);
772 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
773 static bool rs6000_must_pass_in_stack (enum machine_mode
, tree
);
774 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
775 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
777 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
779 static int get_vsel_insn (enum machine_mode
);
780 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
783 const int INSN_NOT_AVAILABLE
= -1;
784 static enum machine_mode
rs6000_eh_return_filter_mode (void);
786 /* Hash table stuff for keeping track of TOC entries. */
788 struct toc_hash_struct
GTY(())
790 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
791 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
793 enum machine_mode key_mode
;
797 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
799 /* Default register names. */
800 char rs6000_reg_names
[][8] =
802 "0", "1", "2", "3", "4", "5", "6", "7",
803 "8", "9", "10", "11", "12", "13", "14", "15",
804 "16", "17", "18", "19", "20", "21", "22", "23",
805 "24", "25", "26", "27", "28", "29", "30", "31",
806 "0", "1", "2", "3", "4", "5", "6", "7",
807 "8", "9", "10", "11", "12", "13", "14", "15",
808 "16", "17", "18", "19", "20", "21", "22", "23",
809 "24", "25", "26", "27", "28", "29", "30", "31",
810 "mq", "lr", "ctr","ap",
811 "0", "1", "2", "3", "4", "5", "6", "7",
813 /* AltiVec registers. */
814 "0", "1", "2", "3", "4", "5", "6", "7",
815 "8", "9", "10", "11", "12", "13", "14", "15",
816 "16", "17", "18", "19", "20", "21", "22", "23",
817 "24", "25", "26", "27", "28", "29", "30", "31",
823 #ifdef TARGET_REGNAMES
824 static const char alt_reg_names
[][8] =
826 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
827 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
828 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
829 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
830 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
831 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
832 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
833 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
834 "mq", "lr", "ctr", "ap",
835 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
837 /* AltiVec registers. */
838 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
839 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
840 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
841 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
848 #ifndef MASK_STRICT_ALIGN
849 #define MASK_STRICT_ALIGN 0
851 #ifndef TARGET_PROFILE_KERNEL
852 #define TARGET_PROFILE_KERNEL 0
855 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
856 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
858 /* Initialize the GCC target structure. */
859 #undef TARGET_ATTRIBUTE_TABLE
860 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
861 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
862 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
864 #undef TARGET_ASM_ALIGNED_DI_OP
865 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
867 /* Default unaligned ops are only provided for ELF. Find the ops needed
868 for non-ELF systems. */
869 #ifndef OBJECT_FORMAT_ELF
871 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
873 #undef TARGET_ASM_UNALIGNED_HI_OP
874 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
875 #undef TARGET_ASM_UNALIGNED_SI_OP
876 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
877 #undef TARGET_ASM_UNALIGNED_DI_OP
878 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
881 #undef TARGET_ASM_UNALIGNED_HI_OP
882 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
883 #undef TARGET_ASM_UNALIGNED_SI_OP
884 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
885 #undef TARGET_ASM_UNALIGNED_DI_OP
886 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
887 #undef TARGET_ASM_ALIGNED_DI_OP
888 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
892 /* This hook deals with fixups for relocatable code and DI-mode objects
894 #undef TARGET_ASM_INTEGER
895 #define TARGET_ASM_INTEGER rs6000_assemble_integer
897 #ifdef HAVE_GAS_HIDDEN
898 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
899 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
902 #undef TARGET_HAVE_TLS
903 #define TARGET_HAVE_TLS HAVE_AS_TLS
905 #undef TARGET_CANNOT_FORCE_CONST_MEM
906 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
908 #undef TARGET_ASM_FUNCTION_PROLOGUE
909 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
910 #undef TARGET_ASM_FUNCTION_EPILOGUE
911 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
913 #undef TARGET_SCHED_VARIABLE_ISSUE
914 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
916 #undef TARGET_SCHED_ISSUE_RATE
917 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
918 #undef TARGET_SCHED_ADJUST_COST
919 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
920 #undef TARGET_SCHED_ADJUST_PRIORITY
921 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
922 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
923 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
924 #undef TARGET_SCHED_FINISH
925 #define TARGET_SCHED_FINISH rs6000_sched_finish
927 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
928 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
930 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
931 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
933 #undef TARGET_INIT_BUILTINS
934 #define TARGET_INIT_BUILTINS rs6000_init_builtins
936 #undef TARGET_EXPAND_BUILTIN
937 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
939 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
940 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
942 #undef TARGET_INIT_LIBFUNCS
943 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
946 #undef TARGET_BINDS_LOCAL_P
947 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
950 #undef TARGET_ASM_OUTPUT_MI_THUNK
951 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
953 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
954 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
956 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
957 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
959 #undef TARGET_RTX_COSTS
960 #define TARGET_RTX_COSTS rs6000_rtx_costs
961 #undef TARGET_ADDRESS_COST
962 #define TARGET_ADDRESS_COST hook_int_rtx_0
964 #undef TARGET_VECTOR_OPAQUE_P
965 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
967 #undef TARGET_DWARF_REGISTER_SPAN
968 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
970 /* On rs6000, function arguments are promoted, as are function return
972 #undef TARGET_PROMOTE_FUNCTION_ARGS
973 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
974 #undef TARGET_PROMOTE_FUNCTION_RETURN
975 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
977 #undef TARGET_RETURN_IN_MEMORY
978 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
980 #undef TARGET_SETUP_INCOMING_VARARGS
981 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
983 /* Always strict argument naming on rs6000. */
984 #undef TARGET_STRICT_ARGUMENT_NAMING
985 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
986 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
987 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
988 #undef TARGET_SPLIT_COMPLEX_ARG
989 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
990 #undef TARGET_MUST_PASS_IN_STACK
991 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
992 #undef TARGET_PASS_BY_REFERENCE
993 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
994 #undef TARGET_ARG_PARTIAL_BYTES
995 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
997 #undef TARGET_BUILD_BUILTIN_VA_LIST
998 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1000 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1001 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1003 #undef TARGET_EH_RETURN_FILTER_MODE
1004 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1006 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1007 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1009 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1010 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1012 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1013 The PowerPC architecture requires only weak consistency among
1014 processors--that is, memory accesses between processors need not be
1015 sequentially consistent and memory accesses among processors can occur
1016 in any order. The ability to order memory accesses weakly provides
1017 opportunities for more efficient use of the system bus. Unless a
1018 dependency exists, the 604e allows read operations to precede store
1020 #undef TARGET_RELAXED_ORDERING
1021 #define TARGET_RELAXED_ORDERING true
1023 struct gcc_target targetm
= TARGET_INITIALIZER
;
1026 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1029 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1031 /* The GPRs can hold any mode, but values bigger than one register
1032 cannot go past R31. */
1033 if (INT_REGNO_P (regno
))
1034 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1036 /* The float registers can only hold floating modes and DImode. */
1037 if (FP_REGNO_P (regno
))
1039 (GET_MODE_CLASS (mode
) == MODE_FLOAT
1040 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1041 || (GET_MODE_CLASS (mode
) == MODE_INT
1042 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
);
1044 /* The CR register can only hold CC modes. */
1045 if (CR_REGNO_P (regno
))
1046 return GET_MODE_CLASS (mode
) == MODE_CC
;
1048 if (XER_REGNO_P (regno
))
1049 return mode
== PSImode
;
1051 /* AltiVec only in AldyVec registers. */
1052 if (ALTIVEC_REGNO_P (regno
))
1053 return ALTIVEC_VECTOR_MODE (mode
);
1055 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1056 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1059 /* We cannot put TImode anywhere except general register and it must be
1060 able to fit within the register set. */
1062 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1065 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1067 rs6000_init_hard_regno_mode_ok (void)
1071 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1072 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1073 if (rs6000_hard_regno_mode_ok (r
, m
))
1074 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1077 /* If not otherwise specified by a target, make 'long double' equivalent to
1080 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1081 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1084 /* Override command line options. Mostly we process the processor
1085 type and sometimes adjust other TARGET_ options. */
1088 rs6000_override_options (const char *default_cpu
)
1091 struct rs6000_cpu_select
*ptr
;
1094 /* Simplifications for entries below. */
1097 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1098 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1101 /* This table occasionally claims that a processor does not support
1102 a particular feature even though it does, but the feature is slower
1103 than the alternative. Thus, it shouldn't be relied on as a
1104 complete description of the processor's support.
1106 Please keep this list in order, and don't forget to update the
1107 documentation in invoke.texi when adding a new processor or
1111 const char *const name
; /* Canonical processor name. */
1112 const enum processor_type processor
; /* Processor type enum value. */
1113 const int target_enable
; /* Target flags to enable. */
1114 } const processor_target_table
[]
1115 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1116 {"403", PROCESSOR_PPC403
,
1117 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1118 {"405", PROCESSOR_PPC405
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1119 {"405fp", PROCESSOR_PPC405
, POWERPC_BASE_MASK
},
1120 {"440", PROCESSOR_PPC440
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1121 {"440fp", PROCESSOR_PPC440
, POWERPC_BASE_MASK
},
1122 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1123 {"601", PROCESSOR_PPC601
,
1124 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1125 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1126 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1127 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1128 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1129 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1130 {"620", PROCESSOR_PPC620
,
1131 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1132 {"630", PROCESSOR_PPC630
,
1133 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1134 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1135 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1136 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1137 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1138 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1139 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1140 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1141 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1142 /* 8548 has a dummy entry for now. */
1143 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1144 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1145 {"970", PROCESSOR_POWER4
,
1146 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1147 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1148 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1149 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1150 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1151 {"G5", PROCESSOR_POWER4
,
1152 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1153 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1154 {"power2", PROCESSOR_POWER
,
1155 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1156 {"power3", PROCESSOR_PPC630
,
1157 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1158 {"power4", PROCESSOR_POWER4
,
1159 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1160 {"power5", PROCESSOR_POWER5
,
1161 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1162 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1163 {"powerpc64", PROCESSOR_POWERPC64
,
1164 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1165 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1166 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1167 {"rios2", PROCESSOR_RIOS2
,
1168 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1169 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1170 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1171 {"rs64", PROCESSOR_RS64A
,
1172 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1175 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1177 /* Some OSs don't support saving the high part of 64-bit registers on
1178 context switch. Other OSs don't support saving Altivec registers.
1179 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1180 settings; if the user wants either, the user must explicitly specify
1181 them and we won't interfere with the user's specification. */
1184 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1185 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
1186 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1190 rs6000_init_hard_regno_mode_ok ();
1192 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1193 #ifdef OS_MISSING_POWERPC64
1194 if (OS_MISSING_POWERPC64
)
1195 set_masks
&= ~MASK_POWERPC64
;
1197 #ifdef OS_MISSING_ALTIVEC
1198 if (OS_MISSING_ALTIVEC
)
1199 set_masks
&= ~MASK_ALTIVEC
;
1202 /* Don't override by the processor default if given explicitly. */
1203 set_masks
&= ~target_flags_explicit
;
1205 /* Identify the processor type. */
1206 rs6000_select
[0].string
= default_cpu
;
1207 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1209 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1211 ptr
= &rs6000_select
[i
];
1212 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1214 for (j
= 0; j
< ptt_size
; j
++)
1215 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1217 if (ptr
->set_tune_p
)
1218 rs6000_cpu
= processor_target_table
[j
].processor
;
1220 if (ptr
->set_arch_p
)
1222 target_flags
&= ~set_masks
;
1223 target_flags
|= (processor_target_table
[j
].target_enable
1230 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1237 /* If we are optimizing big endian systems for space, use the load/store
1238 multiple and string instructions. */
1239 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1240 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1242 /* Don't allow -mmultiple or -mstring on little endian systems
1243 unless the cpu is a 750, because the hardware doesn't support the
1244 instructions used in little endian mode, and causes an alignment
1245 trap. The 750 does not cause an alignment trap (except when the
1246 target is unaligned). */
1248 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1250 if (TARGET_MULTIPLE
)
1252 target_flags
&= ~MASK_MULTIPLE
;
1253 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1254 warning ("-mmultiple is not supported on little endian systems");
1259 target_flags
&= ~MASK_STRING
;
1260 if ((target_flags_explicit
& MASK_STRING
) != 0)
1261 warning ("-mstring is not supported on little endian systems");
1265 /* Set debug flags */
1266 if (rs6000_debug_name
)
1268 if (! strcmp (rs6000_debug_name
, "all"))
1269 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1270 else if (! strcmp (rs6000_debug_name
, "stack"))
1271 rs6000_debug_stack
= 1;
1272 else if (! strcmp (rs6000_debug_name
, "arg"))
1273 rs6000_debug_arg
= 1;
1275 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1278 if (rs6000_traceback_name
)
1280 if (! strncmp (rs6000_traceback_name
, "full", 4))
1281 rs6000_traceback
= traceback_full
;
1282 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1283 rs6000_traceback
= traceback_part
;
1284 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1285 rs6000_traceback
= traceback_none
;
1287 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1288 rs6000_traceback_name
);
1291 /* Set size of long double */
1292 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1293 if (rs6000_long_double_size_string
)
1296 int size
= strtol (rs6000_long_double_size_string
, &tail
, 10);
1297 if (*tail
!= '\0' || (size
!= 64 && size
!= 128))
1298 error ("Unknown switch -mlong-double-%s",
1299 rs6000_long_double_size_string
);
1301 rs6000_long_double_type_size
= size
;
1304 /* Set Altivec ABI as default for powerpc64 linux. */
1305 if (TARGET_ELF
&& TARGET_64BIT
)
1307 rs6000_altivec_abi
= 1;
1308 rs6000_altivec_vrsave
= 1;
1311 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1312 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1314 rs6000_darwin64_abi
= 1;
1316 darwin_one_byte_bool
= 1;
1318 /* Default to natural alignment, for better performance. */
1319 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1322 /* Handle -mabi= options. */
1323 rs6000_parse_abi_options ();
1325 /* Handle -malign-XXXXX option. */
1326 rs6000_parse_alignment_option ();
1328 rs6000_parse_float_gprs_option ();
1330 /* Handle generic -mFOO=YES/NO options. */
1331 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string
,
1332 &rs6000_altivec_vrsave
);
1333 rs6000_parse_yes_no_option ("isel", rs6000_isel_string
,
1335 rs6000_parse_yes_no_option ("spe", rs6000_spe_string
, &rs6000_spe
);
1337 /* Handle -mtls-size option. */
1338 rs6000_parse_tls_size_option ();
1340 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1341 SUBTARGET_OVERRIDE_OPTIONS
;
1343 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1344 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1346 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1347 SUB3TARGET_OVERRIDE_OPTIONS
;
1353 error ("AltiVec and E500 instructions cannot coexist");
1355 /* The e500 does not have string instructions, and we set
1356 MASK_STRING above when optimizing for size. */
1357 if ((target_flags
& MASK_STRING
) != 0)
1358 target_flags
= target_flags
& ~MASK_STRING
;
1360 /* No SPE means 64-bit long doubles, even if an E500. */
1361 if (rs6000_spe_string
!= 0
1362 && !strcmp (rs6000_spe_string
, "no"))
1363 rs6000_long_double_type_size
= 64;
1365 else if (rs6000_select
[1].string
!= NULL
)
1367 /* For the powerpc-eabispe configuration, we set all these by
1368 default, so let's unset them if we manually set another
1369 CPU that is not the E500. */
1370 if (rs6000_abi_string
== 0)
1372 if (rs6000_spe_string
== 0)
1374 if (rs6000_float_gprs_string
== 0)
1375 rs6000_float_gprs
= 0;
1376 if (rs6000_isel_string
== 0)
1378 if (rs6000_long_double_size_string
== 0)
1379 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1382 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1383 && rs6000_cpu
!= PROCESSOR_POWER5
);
1384 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1385 || rs6000_cpu
== PROCESSOR_POWER5
);
1387 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1388 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1389 bits in target_flags so TARGET_SWITCHES cannot be used.
1390 Assumption here is that rs6000_longcall_switch points into the
1391 text of the complete option, rather than being a copy, so we can
1392 scan back for the presence or absence of the no- modifier. */
1393 if (rs6000_longcall_switch
)
1395 const char *base
= rs6000_longcall_switch
;
1396 while (base
[-1] != 'm') base
--;
1398 if (*rs6000_longcall_switch
!= '\0')
1399 error ("invalid option %qs", base
);
1400 rs6000_default_long_calls
= (base
[0] != 'n');
1403 /* Handle -m(no-)warn-altivec-long similarly. */
1404 if (rs6000_warn_altivec_long_switch
)
1406 const char *base
= rs6000_warn_altivec_long_switch
;
1407 while (base
[-1] != 'm') base
--;
1409 if (*rs6000_warn_altivec_long_switch
!= '\0')
1410 error ("invalid option %qs", base
);
1411 rs6000_warn_altivec_long
= (base
[0] != 'n');
1414 /* Handle -mprioritize-restricted-insns option. */
1415 rs6000_sched_restricted_insns_priority
1416 = (rs6000_sched_groups
? 1 : 0);
1417 if (rs6000_sched_restricted_insns_priority_str
)
1418 rs6000_sched_restricted_insns_priority
=
1419 atoi (rs6000_sched_restricted_insns_priority_str
);
1421 /* Handle -msched-costly-dep option. */
1422 rs6000_sched_costly_dep
1423 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1424 if (rs6000_sched_costly_dep_str
)
1426 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1427 rs6000_sched_costly_dep
= no_dep_costly
;
1428 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1429 rs6000_sched_costly_dep
= all_deps_costly
;
1430 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1431 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1432 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1433 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1435 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1438 /* Handle -minsert-sched-nops option. */
1439 rs6000_sched_insert_nops
1440 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1441 if (rs6000_sched_insert_nops_str
)
1443 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1444 rs6000_sched_insert_nops
= sched_finish_none
;
1445 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1446 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1447 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1448 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1450 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1453 #ifdef TARGET_REGNAMES
1454 /* If the user desires alternate register names, copy in the
1455 alternate names now. */
1456 if (TARGET_REGNAMES
)
1457 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1460 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1461 If -maix-struct-return or -msvr4-struct-return was explicitly
1462 used, don't override with the ABI default. */
1463 if ((target_flags_explicit
& MASK_AIX_STRUCT_RET
) == 0)
1465 if (DEFAULT_ABI
== ABI_V4
&& !DRAFT_V4_STRUCT_RET
)
1466 target_flags
= (target_flags
& ~MASK_AIX_STRUCT_RET
);
1468 target_flags
|= MASK_AIX_STRUCT_RET
;
1471 if (TARGET_LONG_DOUBLE_128
1472 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
))
1473 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1475 /* Allocate an alias set for register saves & restores from stack. */
1476 rs6000_sr_alias_set
= new_alias_set ();
1479 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1481 /* We can only guarantee the availability of DI pseudo-ops when
1482 assembling for 64-bit targets. */
1485 targetm
.asm_out
.aligned_op
.di
= NULL
;
1486 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1489 /* Set branch target alignment, if not optimizing for size. */
1492 if (rs6000_sched_groups
)
1494 if (align_functions
<= 0)
1495 align_functions
= 16;
1496 if (align_jumps
<= 0)
1498 if (align_loops
<= 0)
1501 if (align_jumps_max_skip
<= 0)
1502 align_jumps_max_skip
= 15;
1503 if (align_loops_max_skip
<= 0)
1504 align_loops_max_skip
= 15;
1507 /* Arrange to save and restore machine status around nested functions. */
1508 init_machine_status
= rs6000_init_machine_status
;
1510 /* We should always be splitting complex arguments, but we can't break
1511 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1512 if (DEFAULT_ABI
!= ABI_AIX
)
1513 targetm
.calls
.split_complex_arg
= NULL
;
1515 /* Initialize rs6000_cost with the appropriate target costs. */
1517 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1521 case PROCESSOR_RIOS1
:
1522 rs6000_cost
= &rios1_cost
;
1525 case PROCESSOR_RIOS2
:
1526 rs6000_cost
= &rios2_cost
;
1529 case PROCESSOR_RS64A
:
1530 rs6000_cost
= &rs64a_cost
;
1533 case PROCESSOR_MPCCORE
:
1534 rs6000_cost
= &mpccore_cost
;
1537 case PROCESSOR_PPC403
:
1538 rs6000_cost
= &ppc403_cost
;
1541 case PROCESSOR_PPC405
:
1542 rs6000_cost
= &ppc405_cost
;
1545 case PROCESSOR_PPC440
:
1546 rs6000_cost
= &ppc440_cost
;
1549 case PROCESSOR_PPC601
:
1550 rs6000_cost
= &ppc601_cost
;
1553 case PROCESSOR_PPC603
:
1554 rs6000_cost
= &ppc603_cost
;
1557 case PROCESSOR_PPC604
:
1558 rs6000_cost
= &ppc604_cost
;
1561 case PROCESSOR_PPC604e
:
1562 rs6000_cost
= &ppc604e_cost
;
1565 case PROCESSOR_PPC620
:
1566 rs6000_cost
= &ppc620_cost
;
1569 case PROCESSOR_PPC630
:
1570 rs6000_cost
= &ppc630_cost
;
1573 case PROCESSOR_PPC750
:
1574 case PROCESSOR_PPC7400
:
1575 rs6000_cost
= &ppc750_cost
;
1578 case PROCESSOR_PPC7450
:
1579 rs6000_cost
= &ppc7450_cost
;
1582 case PROCESSOR_PPC8540
:
1583 rs6000_cost
= &ppc8540_cost
;
1586 case PROCESSOR_POWER4
:
1587 case PROCESSOR_POWER5
:
1588 rs6000_cost
= &power4_cost
;
1596 /* Implement targetm.vectorize.builtin_mask_for_load. */
1598 rs6000_builtin_mask_for_load (void)
1601 return altivec_builtin_mask_for_load
;
1606 /* Handle generic options of the form -mfoo=yes/no.
1607 NAME is the option name.
1608 VALUE is the option value.
1609 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1610 whether the option value is 'yes' or 'no' respectively. */
1612 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1616 else if (!strcmp (value
, "yes"))
1618 else if (!strcmp (value
, "no"))
1621 error ("unknown -m%s= option specified: '%s'", name
, value
);
1624 /* Handle -mabi= options. */
1626 rs6000_parse_abi_options (void)
1628 if (rs6000_abi_string
== 0)
1630 else if (! strcmp (rs6000_abi_string
, "altivec"))
1632 rs6000_altivec_abi
= 1;
1635 else if (! strcmp (rs6000_abi_string
, "no-altivec"))
1636 rs6000_altivec_abi
= 0;
1637 else if (! strcmp (rs6000_abi_string
, "spe"))
1640 rs6000_altivec_abi
= 0;
1641 if (!TARGET_SPE_ABI
)
1642 error ("not configured for ABI: '%s'", rs6000_abi_string
);
1645 /* These are here for testing during development only, do not
1646 document in the manual please. */
1647 else if (! strcmp (rs6000_abi_string
, "d64"))
1649 rs6000_darwin64_abi
= 1;
1650 warning ("Using darwin64 ABI");
1652 else if (! strcmp (rs6000_abi_string
, "d32"))
1654 rs6000_darwin64_abi
= 0;
1655 warning ("Using old darwin ABI");
1658 else if (! strcmp (rs6000_abi_string
, "no-spe"))
1661 error ("unknown ABI specified: '%s'", rs6000_abi_string
);
1664 /* Handle -mfloat-gprs= options. */
1666 rs6000_parse_float_gprs_option (void)
1668 if (rs6000_float_gprs_string
== 0)
1670 else if (! strcmp (rs6000_float_gprs_string
, "yes")
1671 || ! strcmp (rs6000_float_gprs_string
, "single"))
1672 rs6000_float_gprs
= 1;
1673 else if (! strcmp (rs6000_float_gprs_string
, "double"))
1674 rs6000_float_gprs
= 2;
1675 else if (! strcmp (rs6000_float_gprs_string
, "no"))
1676 rs6000_float_gprs
= 0;
1678 error ("invalid option for -mfloat-gprs");
1681 /* Handle -malign-XXXXXX options. */
1683 rs6000_parse_alignment_option (void)
1685 if (rs6000_alignment_string
== 0)
1687 else if (! strcmp (rs6000_alignment_string
, "power"))
1689 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1690 some C library functions, so warn about it. The flag may be
1691 useful for performance studies from time to time though, so
1692 don't disable it entirely. */
1693 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1694 warning ("-malign-power is not supported for 64-bit Darwin;"
1695 " it is incompatible with the installed C and C++ libraries");
1696 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
1698 else if (! strcmp (rs6000_alignment_string
, "natural"))
1699 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1701 error ("unknown -malign-XXXXX option specified: '%s'",
1702 rs6000_alignment_string
);
1705 /* Validate and record the size specified with the -mtls-size option. */
1708 rs6000_parse_tls_size_option (void)
1710 if (rs6000_tls_size_string
== 0)
1712 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
1713 rs6000_tls_size
= 16;
1714 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
1715 rs6000_tls_size
= 32;
1716 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
1717 rs6000_tls_size
= 64;
1719 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
1723 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1727 /* Do anything needed at the start of the asm file. */
1730 rs6000_file_start (void)
1734 const char *start
= buffer
;
1735 struct rs6000_cpu_select
*ptr
;
1736 const char *default_cpu
= TARGET_CPU_DEFAULT
;
1737 FILE *file
= asm_out_file
;
1739 default_file_start ();
1741 #ifdef TARGET_BI_ARCH
1742 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
1746 if (flag_verbose_asm
)
1748 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
1749 rs6000_select
[0].string
= default_cpu
;
1751 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1753 ptr
= &rs6000_select
[i
];
1754 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1756 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
1761 #ifdef USING_ELFOS_H
1762 switch (rs6000_sdata
)
1764 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
1765 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
1766 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
1767 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
1770 if (rs6000_sdata
&& g_switch_value
)
1772 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
1782 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
1790 /* Return nonzero if this function is known to have a null epilogue. */
1793 direct_return (void)
1795 if (reload_completed
)
1797 rs6000_stack_t
*info
= rs6000_stack_info ();
1799 if (info
->first_gp_reg_save
== 32
1800 && info
->first_fp_reg_save
== 64
1801 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
1802 && ! info
->lr_save_p
1803 && ! info
->cr_save_p
1804 && info
->vrsave_mask
== 0
1812 /* Return the number of instructions it takes to form a constant in an
1813 integer register. */
1816 num_insns_constant_wide (HOST_WIDE_INT value
)
1818 /* signed constant loadable with {cal|addi} */
1819 if (CONST_OK_FOR_LETTER_P (value
, 'I'))
1822 /* constant loadable with {cau|addis} */
1823 else if (CONST_OK_FOR_LETTER_P (value
, 'L'))
1826 #if HOST_BITS_PER_WIDE_INT == 64
1827 else if (TARGET_POWERPC64
)
1829 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1830 HOST_WIDE_INT high
= value
>> 31;
1832 if (high
== 0 || high
== -1)
1838 return num_insns_constant_wide (high
) + 1;
1840 return (num_insns_constant_wide (high
)
1841 + num_insns_constant_wide (low
) + 1);
1850 num_insns_constant (rtx op
, enum machine_mode mode
)
1852 if (GET_CODE (op
) == CONST_INT
)
1854 #if HOST_BITS_PER_WIDE_INT == 64
1855 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
1856 && mask64_operand (op
, mode
))
1860 return num_insns_constant_wide (INTVAL (op
));
1863 else if (GET_CODE (op
) == CONST_DOUBLE
&& mode
== SFmode
)
1868 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
1869 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
1870 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
1873 else if (GET_CODE (op
) == CONST_DOUBLE
)
1879 int endian
= (WORDS_BIG_ENDIAN
== 0);
1881 if (mode
== VOIDmode
|| mode
== DImode
)
1883 high
= CONST_DOUBLE_HIGH (op
);
1884 low
= CONST_DOUBLE_LOW (op
);
1888 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
1889 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
1891 low
= l
[1 - endian
];
1895 return (num_insns_constant_wide (low
)
1896 + num_insns_constant_wide (high
));
1900 if (high
== 0 && low
>= 0)
1901 return num_insns_constant_wide (low
);
1903 else if (high
== -1 && low
< 0)
1904 return num_insns_constant_wide (low
);
1906 else if (mask64_operand (op
, mode
))
1910 return num_insns_constant_wide (high
) + 1;
1913 return (num_insns_constant_wide (high
)
1914 + num_insns_constant_wide (low
) + 1);
1922 /* Returns the constant for the splat instruction, if exists. */
1925 easy_vector_splat_const (int cst
, enum machine_mode mode
)
1930 if (EASY_VECTOR_15 (cst
)
1931 || EASY_VECTOR_15_ADD_SELF (cst
))
1933 if ((cst
& 0xffff) != ((cst
>> 16) & 0xffff))
1939 if (EASY_VECTOR_15 (cst
)
1940 || EASY_VECTOR_15_ADD_SELF (cst
))
1942 if ((cst
& 0xff) != ((cst
>> 8) & 0xff))
1948 if (EASY_VECTOR_15 (cst
)
1949 || EASY_VECTOR_15_ADD_SELF (cst
))
1957 /* Return nonzero if all elements of a vector have the same value. */
1960 easy_vector_same (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1964 units
= CONST_VECTOR_NUNITS (op
);
1966 cst
= INTVAL (CONST_VECTOR_ELT (op
, 0));
1967 for (i
= 1; i
< units
; ++i
)
1968 if (INTVAL (CONST_VECTOR_ELT (op
, i
)) != cst
)
1970 if (i
== units
&& easy_vector_splat_const (cst
, mode
))
1975 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
1978 gen_easy_vector_constant_add_self (rtx op
)
1982 units
= GET_MODE_NUNITS (GET_MODE (op
));
1983 v
= rtvec_alloc (units
);
1985 for (i
= 0; i
< units
; i
++)
1987 GEN_INT (INTVAL (CONST_VECTOR_ELT (op
, i
)) >> 1);
1988 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op
), v
);
1992 output_vec_const_move (rtx
*operands
)
1995 enum machine_mode mode
;
2001 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2002 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2003 mode
= GET_MODE (dest
);
2007 if (zero_constant (vec
, mode
))
2008 return "vxor %0,%0,%0";
2009 else if (easy_vector_constant (vec
, mode
))
2011 operands
[1] = GEN_INT (cst
);
2015 if (EASY_VECTOR_15 (cst
))
2017 operands
[1] = GEN_INT (cst
);
2018 return "vspltisw %0,%1";
2020 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2026 if (EASY_VECTOR_15 (cst
))
2028 operands
[1] = GEN_INT (cst
);
2029 return "vspltish %0,%1";
2031 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2037 if (EASY_VECTOR_15 (cst
))
2039 operands
[1] = GEN_INT (cst
);
2040 return "vspltisb %0,%1";
2042 else if (EASY_VECTOR_15_ADD_SELF (cst
))
2055 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2056 pattern of V1DI, V4HI, and V2SF.
2058 FIXME: We should probably return # and add post reload
2059 splitters for these, but this way is so easy ;-). */
2060 operands
[1] = GEN_INT (cst
);
2061 operands
[2] = GEN_INT (cst2
);
2063 return "li %0,%1\n\tevmergelo %0,%0,%0";
2065 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2072 mask64_1or2_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2075 if (GET_CODE (op
) == CONST_INT
)
2077 HOST_WIDE_INT c
, lsb
;
2082 /* Disallow all zeros. */
2086 /* We can use a single rlwinm insn if no upper bits of C are set
2087 AND there are zero, one or two transitions in the _whole_ of
2089 one_ok
= !(c
& ~(HOST_WIDE_INT
)0xffffffff);
2091 /* We don't change the number of transitions by inverting,
2092 so make sure we start with the LS bit zero. */
2096 /* Find the first transition. */
2099 /* Invert to look for a second transition. */
2102 /* Erase first transition. */
2105 /* Find the second transition. */
2108 /* Invert to look for a third transition. */
2111 /* Erase second transition. */
2114 if (one_ok
&& !(allow_one
|| c
))
2117 /* Find the third transition (if any). */
2120 /* Match if all the bits above are 1's (or c is zero). */
2126 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2127 implement ANDing by the mask IN. */
2129 build_mask64_2_operands (rtx in
, rtx
*out
)
2131 #if HOST_BITS_PER_WIDE_INT >= 64
2132 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
2135 if (GET_CODE (in
) != CONST_INT
)
2141 /* Assume c initially something like 0x00fff000000fffff. The idea
2142 is to rotate the word so that the middle ^^^^^^ group of zeros
2143 is at the MS end and can be cleared with an rldicl mask. We then
2144 rotate back and clear off the MS ^^ group of zeros with a
2146 c
= ~c
; /* c == 0xff000ffffff00000 */
2147 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
2148 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
2149 c
= ~c
; /* c == 0x00fff000000fffff */
2150 c
&= -lsb
; /* c == 0x00fff00000000000 */
2151 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2152 c
= ~c
; /* c == 0xff000fffffffffff */
2153 c
&= -lsb
; /* c == 0xff00000000000000 */
2155 while ((lsb
>>= 1) != 0)
2156 shift
++; /* shift == 44 on exit from loop */
2157 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
2158 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
2159 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
2163 /* Assume c initially something like 0xff000f0000000000. The idea
2164 is to rotate the word so that the ^^^ middle group of zeros
2165 is at the LS end and can be cleared with an rldicr mask. We then
2166 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2168 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
2169 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
2170 c
= ~c
; /* c == 0x00fff0ffffffffff */
2171 c
&= -lsb
; /* c == 0x00fff00000000000 */
2172 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2173 c
= ~c
; /* c == 0xff000fffffffffff */
2174 c
&= -lsb
; /* c == 0xff00000000000000 */
2176 while ((lsb
>>= 1) != 0)
2177 shift
++; /* shift == 44 on exit from loop */
2178 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
2179 m1
>>= shift
; /* m1 == 0x0000000000000fff */
2180 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
2183 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2184 masks will be all 1's. We are guaranteed more than one transition. */
2185 out
[0] = GEN_INT (64 - shift
);
2186 out
[1] = GEN_INT (m1
);
2187 out
[2] = GEN_INT (shift
);
2188 out
[3] = GEN_INT (m2
);
2196 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2199 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
2201 /* Reject (subreg:SI (reg:DF)). */
2202 if (GET_CODE (op
) == SUBREG
2204 && REG_P (SUBREG_REG (op
))
2205 && GET_MODE (SUBREG_REG (op
)) == DFmode
)
2208 /* Reject (subreg:DF (reg:DI)). */
2209 if (GET_CODE (op
) == SUBREG
2211 && REG_P (SUBREG_REG (op
))
2212 && GET_MODE (SUBREG_REG (op
)) == DImode
)
2218 /* Darwin, AIX increases natural record alignment to doubleword if the first
2219 field is an FP double while the FP fields remain word aligned. */
2222 rs6000_special_round_type_align (tree type
, int computed
, int specified
)
2224 tree field
= TYPE_FIELDS (type
);
2226 /* Skip all non field decls */
2227 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
2228 field
= TREE_CHAIN (field
);
2230 if (field
== NULL
|| field
== type
|| DECL_MODE (field
) != DFmode
)
2231 return MAX (computed
, specified
);
2233 return MAX (MAX (computed
, specified
), 64);
2236 /* Return 1 for an operand in small memory on V.4/eabi. */
2239 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
2240 enum machine_mode mode ATTRIBUTE_UNUSED
)
2245 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
2248 if (DEFAULT_ABI
!= ABI_V4
)
2251 if (GET_CODE (op
) == SYMBOL_REF
)
2254 else if (GET_CODE (op
) != CONST
2255 || GET_CODE (XEXP (op
, 0)) != PLUS
2256 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
2257 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
2262 rtx sum
= XEXP (op
, 0);
2263 HOST_WIDE_INT summand
;
2265 /* We have to be careful here, because it is the referenced address
2266 that must be 32k from _SDA_BASE_, not just the symbol. */
2267 summand
= INTVAL (XEXP (sum
, 1));
2268 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
2271 sym_ref
= XEXP (sum
, 0);
2274 return SYMBOL_REF_SMALL_P (sym_ref
);
2280 /* Return true if either operand is a general purpose register. */
2283 gpr_or_gpr_p (rtx op0
, rtx op1
)
2285 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
2286 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
2290 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2293 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
2295 switch (GET_CODE (op
))
2298 if (RS6000_SYMBOL_REF_TLS_P (op
))
2300 else if (CONSTANT_POOL_ADDRESS_P (op
))
2302 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
2310 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
2319 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
2320 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
2322 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
2331 constant_pool_expr_p (rtx op
)
2335 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
2339 toc_relative_expr_p (rtx op
)
2343 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
2347 legitimate_constant_pool_address_p (rtx x
)
2350 && GET_CODE (x
) == PLUS
2351 && GET_CODE (XEXP (x
, 0)) == REG
2352 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
2353 && constant_pool_expr_p (XEXP (x
, 1)));
2357 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
2359 return (DEFAULT_ABI
== ABI_V4
2360 && !flag_pic
&& !TARGET_TOC
2361 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
2362 && small_data_operand (x
, mode
));
2365 /* SPE offset addressing is limited to 5-bits worth of double words. */
2366 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2369 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
2371 unsigned HOST_WIDE_INT offset
, extra
;
2373 if (GET_CODE (x
) != PLUS
)
2375 if (GET_CODE (XEXP (x
, 0)) != REG
)
2377 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
2379 if (legitimate_constant_pool_address_p (x
))
2381 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2384 offset
= INTVAL (XEXP (x
, 1));
2392 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2393 which leaves the only valid constant offset of zero, which by
2394 canonicalization rules is also invalid. */
2401 /* SPE vector modes. */
2402 return SPE_CONST_OFFSET_OK (offset
);
2405 if (TARGET_E500_DOUBLE
)
2406 return SPE_CONST_OFFSET_OK (offset
);
2409 /* On e500v2, we may have:
2411 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2413 Which gets addressed with evldd instructions. */
2414 if (TARGET_E500_DOUBLE
)
2415 return SPE_CONST_OFFSET_OK (offset
);
2417 if (mode
== DFmode
|| !TARGET_POWERPC64
)
2419 else if (offset
& 3)
2425 if (mode
== TFmode
|| !TARGET_POWERPC64
)
2427 else if (offset
& 3)
2438 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
2442 legitimate_indexed_address_p (rtx x
, int strict
)
2446 if (GET_CODE (x
) != PLUS
)
2452 if (!REG_P (op0
) || !REG_P (op1
))
2455 return ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
2456 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
2457 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
2458 && INT_REG_OK_FOR_INDEX_P (op0
, strict
)));
2462 legitimate_indirect_address_p (rtx x
, int strict
)
2464 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
2468 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
2470 if (!TARGET_MACHO
|| !flag_pic
2471 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
2475 if (GET_CODE (x
) != LO_SUM
)
2477 if (GET_CODE (XEXP (x
, 0)) != REG
)
2479 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
2483 return CONSTANT_P (x
);
2487 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
2489 if (GET_CODE (x
) != LO_SUM
)
2491 if (GET_CODE (XEXP (x
, 0)) != REG
)
2493 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
2495 /* Restrict addressing for DI because of our SUBREG hackery. */
2496 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
2500 if (TARGET_ELF
|| TARGET_MACHO
)
2502 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
2506 if (GET_MODE_NUNITS (mode
) != 1)
2508 if (GET_MODE_BITSIZE (mode
) > 64
2509 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
2510 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& mode
== DFmode
)))
2513 return CONSTANT_P (x
);
2520 /* Try machine-dependent ways of modifying an illegitimate address
2521 to be legitimate. If we find one, return the new, valid address.
2522 This is used from only one place: `memory_address' in explow.c.
2524 OLDX is the address as it was before break_out_memory_refs was
2525 called. In some cases it is useful to look at this to decide what
2528 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2530 It is always safe for this function to do nothing. It exists to
2531 recognize opportunities to optimize the output.
2533 On RS/6000, first check for the sum of a register with a constant
2534 integer that is out of range. If so, generate code to add the
2535 constant with the low-order 16 bits masked to the register and force
2536 this result into another register (this can be done with `cau').
2537 Then generate an address of REG+(CONST&0xffff), allowing for the
2538 possibility of bit 16 being a one.
2540 Then check for the sum of a register and something not constant, try to
2541 load the other things into a register and return the sum. */
2544 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
2545 enum machine_mode mode
)
2547 if (GET_CODE (x
) == SYMBOL_REF
)
2549 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
2551 return rs6000_legitimize_tls_address (x
, model
);
2554 if (GET_CODE (x
) == PLUS
2555 && GET_CODE (XEXP (x
, 0)) == REG
2556 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2557 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000)
2559 HOST_WIDE_INT high_int
, low_int
;
2561 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2562 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
2563 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
2564 GEN_INT (high_int
)), 0);
2565 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
2567 else if (GET_CODE (x
) == PLUS
2568 && GET_CODE (XEXP (x
, 0)) == REG
2569 && GET_CODE (XEXP (x
, 1)) != CONST_INT
2570 && GET_MODE_NUNITS (mode
) == 1
2571 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2573 || (((mode
!= DImode
&& mode
!= DFmode
) || TARGET_E500_DOUBLE
)
2575 && (TARGET_POWERPC64
|| mode
!= DImode
)
2578 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
2579 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
2581 else if (ALTIVEC_VECTOR_MODE (mode
))
2585 /* Make sure both operands are registers. */
2586 if (GET_CODE (x
) == PLUS
)
2587 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
2588 force_reg (Pmode
, XEXP (x
, 1)));
2590 reg
= force_reg (Pmode
, x
);
2593 else if (SPE_VECTOR_MODE (mode
)
2594 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
2595 || mode
== DImode
)))
2599 /* We accept [reg + reg] and [reg + OFFSET]. */
2601 if (GET_CODE (x
) == PLUS
)
2603 rtx op1
= XEXP (x
, 0);
2604 rtx op2
= XEXP (x
, 1);
2606 op1
= force_reg (Pmode
, op1
);
2608 if (GET_CODE (op2
) != REG
2609 && (GET_CODE (op2
) != CONST_INT
2610 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
2611 op2
= force_reg (Pmode
, op2
);
2613 return gen_rtx_PLUS (Pmode
, op1
, op2
);
2616 return force_reg (Pmode
, x
);
2622 && GET_CODE (x
) != CONST_INT
2623 && GET_CODE (x
) != CONST_DOUBLE
2625 && GET_MODE_NUNITS (mode
) == 1
2626 && (GET_MODE_BITSIZE (mode
) <= 32
2627 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) && mode
== DFmode
)))
2629 rtx reg
= gen_reg_rtx (Pmode
);
2630 emit_insn (gen_elf_high (reg
, x
));
2631 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
2633 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
2636 && ! MACHO_DYNAMIC_NO_PIC_P
2638 && GET_CODE (x
) != CONST_INT
2639 && GET_CODE (x
) != CONST_DOUBLE
2641 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) || mode
!= DFmode
)
2645 rtx reg
= gen_reg_rtx (Pmode
);
2646 emit_insn (gen_macho_high (reg
, x
));
2647 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
2650 && constant_pool_expr_p (x
)
2651 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
2653 return create_TOC_reference (x
);
2659 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2660 We need to emit DTP-relative relocations. */
2663 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
2668 fputs ("\t.long\t", file
);
2671 fputs (DOUBLE_INT_ASM_OP
, file
);
2676 output_addr_const (file
, x
);
2677 fputs ("@dtprel+0x8000", file
);
2680 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2682 static GTY(()) rtx rs6000_tls_symbol
;
2684 rs6000_tls_get_addr (void)
2686 if (!rs6000_tls_symbol
)
2687 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2689 return rs6000_tls_symbol
;
2692 /* Construct the SYMBOL_REF for TLS GOT references. */
2694 static GTY(()) rtx rs6000_got_symbol
;
2696 rs6000_got_sym (void)
2698 if (!rs6000_got_symbol
)
2700 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2701 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
2702 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
2705 return rs6000_got_symbol
;
2708 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2709 this (thread-local) address. */
2712 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
2716 dest
= gen_reg_rtx (Pmode
);
2717 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
2723 tlsreg
= gen_rtx_REG (Pmode
, 13);
2724 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
2728 tlsreg
= gen_rtx_REG (Pmode
, 2);
2729 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
2733 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
2737 tmp
= gen_reg_rtx (Pmode
);
2740 tlsreg
= gen_rtx_REG (Pmode
, 13);
2741 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
2745 tlsreg
= gen_rtx_REG (Pmode
, 2);
2746 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
2750 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
2752 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
2757 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
2760 got
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
2764 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
2767 rtx gsym
= rs6000_got_sym ();
2768 got
= gen_reg_rtx (Pmode
);
2770 rs6000_emit_move (got
, gsym
, Pmode
);
2773 rtx tempLR
, tmp3
, mem
;
2776 tempLR
= gen_reg_rtx (Pmode
);
2777 tmp1
= gen_reg_rtx (Pmode
);
2778 tmp2
= gen_reg_rtx (Pmode
);
2779 tmp3
= gen_reg_rtx (Pmode
);
2780 mem
= gen_const_mem (Pmode
, tmp1
);
2782 first
= emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, gsym
));
2783 emit_move_insn (tmp1
, tempLR
);
2784 emit_move_insn (tmp2
, mem
);
2785 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
2786 last
= emit_move_insn (got
, tmp3
);
2787 REG_NOTES (last
) = gen_rtx_EXPR_LIST (REG_EQUAL
, gsym
,
2789 REG_NOTES (first
) = gen_rtx_INSN_LIST (REG_LIBCALL
, last
,
2791 REG_NOTES (last
) = gen_rtx_INSN_LIST (REG_RETVAL
, first
,
2797 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
2799 r3
= gen_rtx_REG (Pmode
, 3);
2801 insn
= gen_tls_gd_64 (r3
, got
, addr
);
2803 insn
= gen_tls_gd_32 (r3
, got
, addr
);
2806 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
2807 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
2808 insn
= emit_call_insn (insn
);
2809 CONST_OR_PURE_CALL_P (insn
) = 1;
2810 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
2811 insn
= get_insns ();
2813 emit_libcall_block (insn
, dest
, r3
, addr
);
2815 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
2817 r3
= gen_rtx_REG (Pmode
, 3);
2819 insn
= gen_tls_ld_64 (r3
, got
);
2821 insn
= gen_tls_ld_32 (r3
, got
);
2824 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
2825 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
2826 insn
= emit_call_insn (insn
);
2827 CONST_OR_PURE_CALL_P (insn
) = 1;
2828 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
2829 insn
= get_insns ();
2831 tmp1
= gen_reg_rtx (Pmode
);
2832 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2834 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
2835 if (rs6000_tls_size
== 16)
2838 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
2840 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
2842 else if (rs6000_tls_size
== 32)
2844 tmp2
= gen_reg_rtx (Pmode
);
2846 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
2848 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
2851 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
2853 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
2857 tmp2
= gen_reg_rtx (Pmode
);
2859 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
2861 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
2863 insn
= gen_rtx_SET (Pmode
, dest
,
2864 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
2870 /* IE, or 64 bit offset LE. */
2871 tmp2
= gen_reg_rtx (Pmode
);
2873 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
2875 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
2878 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
2880 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
2888 /* Return 1 if X contains a thread-local symbol. */
2891 rs6000_tls_referenced_p (rtx x
)
2893 if (! TARGET_HAVE_TLS
)
2896 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
2899 /* Return 1 if *X is a thread-local symbol. This is the same as
2900 rs6000_tls_symbol_ref except for the type of the unused argument. */
2903 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2905 return RS6000_SYMBOL_REF_TLS_P (*x
);
2908 /* The convention appears to be to define this wherever it is used.
2909 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2910 is now used here. */
2911 #ifndef REG_MODE_OK_FOR_BASE_P
2912 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2915 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2916 replace the input X, or the original X if no replacement is called for.
2917 The output parameter *WIN is 1 if the calling macro should goto WIN,
2920 For RS/6000, we wish to handle large displacements off a base
2921 register by splitting the addend across an addiu/addis and the mem insn.
2922 This cuts number of extra insns needed from 3 to 1.
2924 On Darwin, we use this to generate code for floating point constants.
2925 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2926 The Darwin code is inside #if TARGET_MACHO because only then is
2927 machopic_function_base_name() defined. */
2929 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
2930 int opnum
, int type
,
2931 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
2933 /* We must recognize output that we have already generated ourselves. */
2934 if (GET_CODE (x
) == PLUS
2935 && GET_CODE (XEXP (x
, 0)) == PLUS
2936 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2937 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2938 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2940 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2941 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2942 opnum
, (enum reload_type
)type
);
2948 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
2949 && GET_CODE (x
) == LO_SUM
2950 && GET_CODE (XEXP (x
, 0)) == PLUS
2951 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
2952 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
2953 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
2954 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
2955 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
2956 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
2957 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
2959 /* Result of previous invocation of this function on Darwin
2960 floating point constant. */
2961 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2962 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
2963 opnum
, (enum reload_type
)type
);
2969 /* Force ld/std non-word aligned offset into base register by wrapping
2971 if (GET_CODE (x
) == PLUS
2972 && GET_CODE (XEXP (x
, 0)) == REG
2973 && REGNO (XEXP (x
, 0)) < 32
2974 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
2975 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2976 && (INTVAL (XEXP (x
, 1)) & 3) != 0
2977 && !ALTIVEC_VECTOR_MODE (mode
)
2978 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
2979 && TARGET_POWERPC64
)
2981 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
2982 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2983 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2984 opnum
, (enum reload_type
) type
);
2989 if (GET_CODE (x
) == PLUS
2990 && GET_CODE (XEXP (x
, 0)) == REG
2991 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2992 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
2993 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2994 && !SPE_VECTOR_MODE (mode
)
2995 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
2997 && !ALTIVEC_VECTOR_MODE (mode
))
2999 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
3000 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
3002 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3004 /* Check for 32-bit overflow. */
3005 if (high
+ low
!= val
)
3011 /* Reload the high part into a base reg; leave the low part
3012 in the mem directly. */
3014 x
= gen_rtx_PLUS (GET_MODE (x
),
3015 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
3019 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3020 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3021 opnum
, (enum reload_type
)type
);
3027 if (GET_CODE (x
) == SYMBOL_REF
3028 && DEFAULT_ABI
== ABI_DARWIN
3029 && !ALTIVEC_VECTOR_MODE (mode
)
3030 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
3031 /* Don't do this for TFmode, since the result isn't offsettable.
3032 The same goes for DImode without 64-bit gprs. */
3034 && (mode
!= DImode
|| TARGET_POWERPC64
))
3038 rtx offset
= gen_rtx_CONST (Pmode
,
3039 gen_rtx_MINUS (Pmode
, x
,
3040 machopic_function_base_sym ()));
3041 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3042 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3043 gen_rtx_HIGH (Pmode
, offset
)), offset
);
3046 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3047 gen_rtx_HIGH (Pmode
, x
), x
);
3049 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3050 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3051 opnum
, (enum reload_type
)type
);
3058 && constant_pool_expr_p (x
)
3059 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
3061 (x
) = create_TOC_reference (x
);
3069 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3070 that is a valid memory address for an instruction.
3071 The MODE argument is the machine mode for the MEM expression
3072 that wants to use this address.
3074 On the RS/6000, there are four valid address: a SYMBOL_REF that
3075 refers to a constant pool entry of an address (or the sum of it
3076 plus a constant), a short (16-bit signed) constant plus a register,
3077 the sum of two registers, or a register indirect, possibly with an
3078 auto-increment. For DFmode and DImode with a constant plus register,
3079 we must ensure that both words are addressable or PowerPC64 with offset
3082 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3083 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3084 adjacent memory cells are accessed by adding word-sized offsets
3085 during assembly output. */
3087 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
3089 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3091 && ALTIVEC_VECTOR_MODE (mode
)
3092 && GET_CODE (x
) == AND
3093 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3094 && INTVAL (XEXP (x
, 1)) == -16)
3097 if (RS6000_SYMBOL_REF_TLS_P (x
))
3099 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
3101 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
3102 && !ALTIVEC_VECTOR_MODE (mode
)
3103 && !SPE_VECTOR_MODE (mode
)
3104 /* Restrict addressing for DI because of our SUBREG hackery. */
3105 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
3107 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
3109 if (legitimate_small_data_p (mode
, x
))
3111 if (legitimate_constant_pool_address_p (x
))
3113 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3115 && GET_CODE (x
) == PLUS
3116 && GET_CODE (XEXP (x
, 0)) == REG
3117 && (XEXP (x
, 0) == virtual_stack_vars_rtx
3118 || XEXP (x
, 0) == arg_pointer_rtx
)
3119 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3121 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
3125 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3127 || ((mode
!= DFmode
|| TARGET_E500_DOUBLE
) && mode
!= TFmode
))
3128 && (TARGET_POWERPC64
|| mode
!= DImode
)
3129 && legitimate_indexed_address_p (x
, reg_ok_strict
))
3131 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
3136 /* Go to LABEL if ADDR (a legitimate address expression)
3137 has an effect that depends on the machine mode it is used for.
3139 On the RS/6000 this is true of all integral offsets (since AltiVec
3140 modes don't allow them) or is a pre-increment or decrement.
3142 ??? Except that due to conceptual problems in offsettable_address_p
3143 we can't really report the problems of integral offsets. So leave
3144 this assuming that the adjustable offset must be valid for the
3145 sub-words of a TFmode operand, which is what we had before. */
3148 rs6000_mode_dependent_address (rtx addr
)
3150 switch (GET_CODE (addr
))
3153 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3155 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
3156 return val
+ 12 + 0x8000 >= 0x10000;
3165 return TARGET_UPDATE
;
3174 /* Return number of consecutive hard regs needed starting at reg REGNO
3175 to hold something of mode MODE.
3176 This is ordinarily the length in words of a value of mode MODE
3177 but can be less for certain modes in special long registers.
3179 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3180 scalar instructions. The upper 32 bits are only available to the
3183 POWER and PowerPC GPRs hold 32 bits worth;
3184 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3187 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
3189 if (FP_REGNO_P (regno
))
3190 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
3192 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
3195 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
3196 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
3198 if (ALTIVEC_REGNO_P (regno
))
3200 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
3202 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3205 /* Change register usage conditional on target flags. */
3207 rs6000_conditional_register_usage (void)
3211 /* Set MQ register fixed (already call_used) if not POWER
3212 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3217 /* 64-bit AIX reserves GPR13 for thread-private data. */
3219 fixed_regs
[13] = call_used_regs
[13]
3220 = call_really_used_regs
[13] = 1;
3222 /* Conditionally disable FPRs. */
3223 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
3224 for (i
= 32; i
< 64; i
++)
3225 fixed_regs
[i
] = call_used_regs
[i
]
3226 = call_really_used_regs
[i
] = 1;
3228 if (DEFAULT_ABI
== ABI_V4
3229 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
3231 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3233 if (DEFAULT_ABI
== ABI_V4
3234 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
3236 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3237 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3238 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3240 if (DEFAULT_ABI
== ABI_DARWIN
3241 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
3242 global_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3243 = fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3244 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3245 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3247 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
3248 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
3249 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
3252 global_regs
[VSCR_REGNO
] = 1;
3256 global_regs
[SPEFSCR_REGNO
] = 1;
3257 fixed_regs
[FIXED_SCRATCH
]
3258 = call_used_regs
[FIXED_SCRATCH
]
3259 = call_really_used_regs
[FIXED_SCRATCH
] = 1;
3262 if (! TARGET_ALTIVEC
)
3264 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
3265 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
3266 call_really_used_regs
[VRSAVE_REGNO
] = 1;
3269 if (TARGET_ALTIVEC_ABI
)
3270 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
3271 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
3274 /* Try to output insns to set TARGET equal to the constant C if it can
3275 be done in less than N insns. Do all computations in MODE.
3276 Returns the place where the output has been placed if it can be
3277 done and the insns have been emitted. If it would take more than N
3278 insns, zero is returned and no insns and emitted. */
3281 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
3282 rtx source
, int n ATTRIBUTE_UNUSED
)
3284 rtx result
, insn
, set
;
3285 HOST_WIDE_INT c0
, c1
;
3287 if (mode
== QImode
|| mode
== HImode
)
3290 dest
= gen_reg_rtx (mode
);
3291 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
3294 else if (mode
== SImode
)
3296 result
= no_new_pseudos
? dest
: gen_reg_rtx (SImode
);
3298 emit_insn (gen_rtx_SET (VOIDmode
, result
,
3299 GEN_INT (INTVAL (source
)
3300 & (~ (HOST_WIDE_INT
) 0xffff))));
3301 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
3302 gen_rtx_IOR (SImode
, result
,
3303 GEN_INT (INTVAL (source
) & 0xffff))));
3306 else if (mode
== DImode
)
3308 if (GET_CODE (source
) == CONST_INT
)
3310 c0
= INTVAL (source
);
3313 else if (GET_CODE (source
) == CONST_DOUBLE
)
3315 #if HOST_BITS_PER_WIDE_INT >= 64
3316 c0
= CONST_DOUBLE_LOW (source
);
3319 c0
= CONST_DOUBLE_LOW (source
);
3320 c1
= CONST_DOUBLE_HIGH (source
);
3326 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
3331 insn
= get_last_insn ();
3332 set
= single_set (insn
);
3333 if (! CONSTANT_P (SET_SRC (set
)))
3334 set_unique_reg_note (insn
, REG_EQUAL
, source
);
3339 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3340 fall back to a straight forward decomposition. We do this to avoid
3341 exponential run times encountered when looking for longer sequences
3342 with rs6000_emit_set_const. */
3344 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
3346 if (!TARGET_POWERPC64
)
3348 rtx operand1
, operand2
;
3350 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
3352 operand2
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
3354 emit_move_insn (operand1
, GEN_INT (c1
));
3355 emit_move_insn (operand2
, GEN_INT (c2
));
3359 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
3362 ud2
= (c1
& 0xffff0000) >> 16;
3363 #if HOST_BITS_PER_WIDE_INT >= 64
3367 ud4
= (c2
& 0xffff0000) >> 16;
3369 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
3370 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
3373 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
3375 emit_move_insn (dest
, GEN_INT (ud1
));
3378 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
3379 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
3382 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
3385 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
3387 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
3389 else if ((ud4
== 0xffff && (ud3
& 0x8000))
3390 || (ud4
== 0 && ! (ud3
& 0x8000)))
3393 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
3396 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
3399 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud2
)));
3400 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (16)));
3402 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
3407 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
3410 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
3413 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud3
)));
3415 emit_move_insn (dest
, gen_rtx_ASHIFT (DImode
, dest
, GEN_INT (32)));
3417 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
,
3418 GEN_INT (ud2
<< 16)));
3420 emit_move_insn (dest
, gen_rtx_IOR (DImode
, dest
, GEN_INT (ud1
)));
3426 /* Helper for the following. Get rid of [r+r] memory refs
3427 in cases where it won't work (TImode, TFmode). */
3430 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
3432 if (GET_CODE (operands
[0]) == MEM
3433 && GET_CODE (XEXP (operands
[0], 0)) != REG
3434 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
3435 && ! reload_in_progress
)
3437 = replace_equiv_address (operands
[0],
3438 copy_addr_to_reg (XEXP (operands
[0], 0)));
3440 if (GET_CODE (operands
[1]) == MEM
3441 && GET_CODE (XEXP (operands
[1], 0)) != REG
3442 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
3443 && ! reload_in_progress
)
3445 = replace_equiv_address (operands
[1],
3446 copy_addr_to_reg (XEXP (operands
[1], 0)));
3449 /* Emit a move from SOURCE to DEST in mode MODE. */
3451 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
3455 operands
[1] = source
;
3457 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3458 if (GET_CODE (operands
[1]) == CONST_DOUBLE
3459 && ! FLOAT_MODE_P (mode
)
3460 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3462 /* FIXME. This should never happen. */
3463 /* Since it seems that it does, do the safe thing and convert
3465 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
3467 if (GET_CODE (operands
[1]) == CONST_DOUBLE
3468 && ! FLOAT_MODE_P (mode
)
3469 && ((CONST_DOUBLE_HIGH (operands
[1]) == 0
3470 && CONST_DOUBLE_LOW (operands
[1]) >= 0)
3471 || (CONST_DOUBLE_HIGH (operands
[1]) == -1
3472 && CONST_DOUBLE_LOW (operands
[1]) < 0)))
3475 /* Check if GCC is setting up a block move that will end up using FP
3476 registers as temporaries. We must make sure this is acceptable. */
3477 if (GET_CODE (operands
[0]) == MEM
3478 && GET_CODE (operands
[1]) == MEM
3480 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
3481 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
3482 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
3483 ? 32 : MEM_ALIGN (operands
[0])))
3484 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
3486 : MEM_ALIGN (operands
[1]))))
3487 && ! MEM_VOLATILE_P (operands
[0])
3488 && ! MEM_VOLATILE_P (operands
[1]))
3490 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
3491 adjust_address (operands
[1], SImode
, 0));
3492 emit_move_insn (adjust_address (operands
[0], SImode
, 4),
3493 adjust_address (operands
[1], SImode
, 4));
3497 if (!no_new_pseudos
&& GET_CODE (operands
[0]) == MEM
3498 && !gpc_reg_operand (operands
[1], mode
))
3499 operands
[1] = force_reg (mode
, operands
[1]);
3501 if (mode
== SFmode
&& ! TARGET_POWERPC
3502 && TARGET_HARD_FLOAT
&& TARGET_FPRS
3503 && GET_CODE (operands
[0]) == MEM
)
3507 if (reload_in_progress
|| reload_completed
)
3508 regnum
= true_regnum (operands
[1]);
3509 else if (GET_CODE (operands
[1]) == REG
)
3510 regnum
= REGNO (operands
[1]);
3514 /* If operands[1] is a register, on POWER it may have
3515 double-precision data in it, so truncate it to single
3517 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
3520 newreg
= (no_new_pseudos
? operands
[1] : gen_reg_rtx (mode
));
3521 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
3522 operands
[1] = newreg
;
3526 /* Recognize the case where operand[1] is a reference to thread-local
3527 data and load its address to a register. */
3528 if (GET_CODE (operands
[1]) == SYMBOL_REF
)
3530 enum tls_model model
= SYMBOL_REF_TLS_MODEL (operands
[1]);
3532 operands
[1] = rs6000_legitimize_tls_address (operands
[1], model
);
3535 /* Handle the case where reload calls us with an invalid address. */
3536 if (reload_in_progress
&& mode
== Pmode
3537 && (! general_operand (operands
[1], mode
)
3538 || ! nonimmediate_operand (operands
[0], mode
)))
3541 /* 128-bit constant floating-point values on Darwin should really be
3542 loaded as two parts. */
3543 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
3544 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
3545 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
3547 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3548 know how to get a DFmode SUBREG of a TFmode. */
3549 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
, 0),
3550 simplify_gen_subreg (DImode
, operands
[1], mode
, 0),
3552 rs6000_emit_move (simplify_gen_subreg (DImode
, operands
[0], mode
,
3553 GET_MODE_SIZE (DImode
)),
3554 simplify_gen_subreg (DImode
, operands
[1], mode
,
3555 GET_MODE_SIZE (DImode
)),
3560 /* FIXME: In the long term, this switch statement should go away
3561 and be replaced by a sequence of tests based on things like
3567 if (CONSTANT_P (operands
[1])
3568 && GET_CODE (operands
[1]) != CONST_INT
)
3569 operands
[1] = force_const_mem (mode
, operands
[1]);
3573 rs6000_eliminate_indexed_memrefs (operands
);
3578 if (CONSTANT_P (operands
[1])
3579 && ! easy_fp_constant (operands
[1], mode
))
3580 operands
[1] = force_const_mem (mode
, operands
[1]);
3591 if (CONSTANT_P (operands
[1])
3592 && !easy_vector_constant (operands
[1], mode
))
3593 operands
[1] = force_const_mem (mode
, operands
[1]);
3598 /* Use default pattern for address of ELF small data */
3601 && DEFAULT_ABI
== ABI_V4
3602 && (GET_CODE (operands
[1]) == SYMBOL_REF
3603 || GET_CODE (operands
[1]) == CONST
)
3604 && small_data_operand (operands
[1], mode
))
3606 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
3610 if (DEFAULT_ABI
== ABI_V4
3611 && mode
== Pmode
&& mode
== SImode
3612 && flag_pic
== 1 && got_operand (operands
[1], mode
))
3614 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
3618 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
3622 && CONSTANT_P (operands
[1])
3623 && GET_CODE (operands
[1]) != HIGH
3624 && GET_CODE (operands
[1]) != CONST_INT
)
3626 rtx target
= (no_new_pseudos
? operands
[0] : gen_reg_rtx (mode
));
3628 /* If this is a function address on -mcall-aixdesc,
3629 convert it to the address of the descriptor. */
3630 if (DEFAULT_ABI
== ABI_AIX
3631 && GET_CODE (operands
[1]) == SYMBOL_REF
3632 && XSTR (operands
[1], 0)[0] == '.')
3634 const char *name
= XSTR (operands
[1], 0);
3636 while (*name
== '.')
3638 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
3639 CONSTANT_POOL_ADDRESS_P (new_ref
)
3640 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
3641 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
3642 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
3643 SYMBOL_REF_DECL (new_ref
) = SYMBOL_REF_DECL (operands
[1]);
3644 operands
[1] = new_ref
;
3647 if (DEFAULT_ABI
== ABI_DARWIN
)
3650 if (MACHO_DYNAMIC_NO_PIC_P
)
3652 /* Take care of any required data indirection. */
3653 operands
[1] = rs6000_machopic_legitimize_pic_address (
3654 operands
[1], mode
, operands
[0]);
3655 if (operands
[0] != operands
[1])
3656 emit_insn (gen_rtx_SET (VOIDmode
,
3657 operands
[0], operands
[1]));
3661 emit_insn (gen_macho_high (target
, operands
[1]));
3662 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
3666 emit_insn (gen_elf_high (target
, operands
[1]));
3667 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
3671 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3672 and we have put it in the TOC, we just need to make a TOC-relative
3675 && GET_CODE (operands
[1]) == SYMBOL_REF
3676 && constant_pool_expr_p (operands
[1])
3677 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
3678 get_pool_mode (operands
[1])))
3680 operands
[1] = create_TOC_reference (operands
[1]);
3682 else if (mode
== Pmode
3683 && CONSTANT_P (operands
[1])
3684 && ((GET_CODE (operands
[1]) != CONST_INT
3685 && ! easy_fp_constant (operands
[1], mode
))
3686 || (GET_CODE (operands
[1]) == CONST_INT
3687 && num_insns_constant (operands
[1], mode
) > 2)
3688 || (GET_CODE (operands
[0]) == REG
3689 && FP_REGNO_P (REGNO (operands
[0]))))
3690 && GET_CODE (operands
[1]) != HIGH
3691 && ! legitimate_constant_pool_address_p (operands
[1])
3692 && ! toc_relative_expr_p (operands
[1]))
3694 /* Emit a USE operation so that the constant isn't deleted if
3695 expensive optimizations are turned on because nobody
3696 references it. This should only be done for operands that
3697 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3698 This should not be done for operands that contain LABEL_REFs.
3699 For now, we just handle the obvious case. */
3700 if (GET_CODE (operands
[1]) != LABEL_REF
)
3701 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
3704 /* Darwin uses a special PIC legitimizer. */
3705 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
3708 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
3710 if (operands
[0] != operands
[1])
3711 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
3716 /* If we are to limit the number of things we put in the TOC and
3717 this is a symbol plus a constant we can add in one insn,
3718 just put the symbol in the TOC and add the constant. Don't do
3719 this if reload is in progress. */
3720 if (GET_CODE (operands
[1]) == CONST
3721 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
3722 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
3723 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
3724 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
3725 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
3726 && ! side_effects_p (operands
[0]))
3729 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
3730 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
3732 sym
= force_reg (mode
, sym
);
3734 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
3736 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
3740 operands
[1] = force_const_mem (mode
, operands
[1]);
3743 && constant_pool_expr_p (XEXP (operands
[1], 0))
3744 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3745 get_pool_constant (XEXP (operands
[1], 0)),
3746 get_pool_mode (XEXP (operands
[1], 0))))
3749 = gen_const_mem (mode
,
3750 create_TOC_reference (XEXP (operands
[1], 0)));
3751 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
3757 rs6000_eliminate_indexed_memrefs (operands
);
3761 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3763 gen_rtx_SET (VOIDmode
,
3764 operands
[0], operands
[1]),
3765 gen_rtx_CLOBBER (VOIDmode
,
3766 gen_rtx_SCRATCH (SImode
)))));
3775 /* Above, we may have called force_const_mem which may have returned
3776 an invalid address. If we can, fix this up; otherwise, reload will
3777 have to deal with it. */
3778 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
3779 operands
[1] = validize_mem (operands
[1]);
3782 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
3785 /* Nonzero if we can use a floating-point register to pass this arg. */
3786 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3787 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3788 && (CUM)->fregno <= FP_ARG_MAX_REG \
3789 && TARGET_HARD_FLOAT && TARGET_FPRS)
3791 /* Nonzero if we can use an AltiVec register to pass this arg. */
3792 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3793 (ALTIVEC_VECTOR_MODE (MODE) \
3794 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3795 && TARGET_ALTIVEC_ABI \
3798 /* Return a nonzero value to say to return the function value in
3799 memory, just as large structures are always returned. TYPE will be
3800 the data type of the value, and FNTYPE will be the type of the
3801 function doing the returning, or @code{NULL} for libcalls.
3803 The AIX ABI for the RS/6000 specifies that all structures are
3804 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3805 specifies that structures <= 8 bytes are returned in r3/r4, but a
3806 draft put them in memory, and GCC used to implement the draft
3807 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3808 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3809 compatibility can change DRAFT_V4_STRUCT_RET to override the
3810 default, and -m switches get the final word. See
3811 rs6000_override_options for more details.
3813 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3814 long double support is enabled. These values are returned in memory.
3816 int_size_in_bytes returns -1 for variable size objects, which go in
3817 memory always. The cast to unsigned makes -1 > 8. */
3820 rs6000_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
3822 /* In the darwin64 abi, try to use registers for larger structs
3824 if (rs6000_darwin64_abi
3825 && TREE_CODE (type
) == RECORD_TYPE
3826 && int_size_in_bytes (type
) > 0)
3828 CUMULATIVE_ARGS valcum
;
3832 valcum
.fregno
= FP_ARG_MIN_REG
;
3833 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
3834 /* Do a trial code generation as if this were going to be passed
3835 as an argument; if any part goes in memory, we return NULL. */
3836 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
3839 /* Otherwise fall through to more conventional ABI rules. */
3842 if (AGGREGATE_TYPE_P (type
)
3843 && (TARGET_AIX_STRUCT_RET
3844 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
3847 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3848 modes only exist for GCC vector types if -maltivec. */
3849 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
3850 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
3853 /* Return synthetic vectors in memory. */
3854 if (TREE_CODE (type
) == VECTOR_TYPE
3855 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
3857 static bool warned_for_return_big_vectors
= false;
3858 if (!warned_for_return_big_vectors
)
3860 warning ("GCC vector returned by reference: "
3861 "non-standard ABI extension with no compatibility guarantee");
3862 warned_for_return_big_vectors
= true;
3867 if (DEFAULT_ABI
== ABI_V4
&& TYPE_MODE (type
) == TFmode
)
3873 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3874 for a call to a function whose data type is FNTYPE.
3875 For a library call, FNTYPE is 0.
3877 For incoming args we set the number of arguments in the prototype large
3878 so we never return a PARALLEL. */
3881 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
3882 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
3883 int libcall
, int n_named_args
)
3885 static CUMULATIVE_ARGS zero_cumulative
;
3887 *cum
= zero_cumulative
;
3889 cum
->fregno
= FP_ARG_MIN_REG
;
3890 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
3891 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
3892 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
3893 ? CALL_LIBCALL
: CALL_NORMAL
);
3894 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
3895 cum
->stdarg
= fntype
3896 && (TYPE_ARG_TYPES (fntype
) != 0
3897 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
3898 != void_type_node
));
3900 cum
->nargs_prototype
= 0;
3901 if (incoming
|| cum
->prototype
)
3902 cum
->nargs_prototype
= n_named_args
;
3904 /* Check for a longcall attribute. */
3905 if ((!fntype
&& rs6000_default_long_calls
)
3907 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
3908 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
3909 cum
->call_cookie
|= CALL_LONG
;
3911 if (TARGET_DEBUG_ARG
)
3913 fprintf (stderr
, "\ninit_cumulative_args:");
3916 tree ret_type
= TREE_TYPE (fntype
);
3917 fprintf (stderr
, " ret code = %s,",
3918 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3921 if (cum
->call_cookie
& CALL_LONG
)
3922 fprintf (stderr
, " longcall,");
3924 fprintf (stderr
, " proto = %d, nargs = %d\n",
3925 cum
->prototype
, cum
->nargs_prototype
);
3930 && TARGET_ALTIVEC_ABI
3931 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
3933 error ("Cannot return value in vector register because"
3934 " altivec instructions are disabled, use -maltivec"
3935 " to enable them.");
3939 /* Return true if TYPE must be passed on the stack and not in registers. */
3942 rs6000_must_pass_in_stack (enum machine_mode mode
, tree type
)
3944 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
3945 return must_pass_in_stack_var_size (mode
, type
);
3947 return must_pass_in_stack_var_size_or_pad (mode
, type
);
3950 /* If defined, a C expression which determines whether, and in which
3951 direction, to pad out an argument with extra space. The value
3952 should be of type `enum direction': either `upward' to pad above
3953 the argument, `downward' to pad below, or `none' to inhibit
3956 For the AIX ABI structs are always stored left shifted in their
3960 function_arg_padding (enum machine_mode mode
, tree type
)
3962 #ifndef AGGREGATE_PADDING_FIXED
3963 #define AGGREGATE_PADDING_FIXED 0
3965 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3966 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3969 if (!AGGREGATE_PADDING_FIXED
)
3971 /* GCC used to pass structures of the same size as integer types as
3972 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3973 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3974 passed padded downward, except that -mstrict-align further
3975 muddied the water in that multi-component structures of 2 and 4
3976 bytes in size were passed padded upward.
3978 The following arranges for best compatibility with previous
3979 versions of gcc, but removes the -mstrict-align dependency. */
3980 if (BYTES_BIG_ENDIAN
)
3982 HOST_WIDE_INT size
= 0;
3984 if (mode
== BLKmode
)
3986 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
3987 size
= int_size_in_bytes (type
);
3990 size
= GET_MODE_SIZE (mode
);
3992 if (size
== 1 || size
== 2 || size
== 4)
3998 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
4000 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
4004 /* Fall back to the default. */
4005 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
4008 /* If defined, a C expression that gives the alignment boundary, in bits,
4009 of an argument with the specified mode and type. If it is not defined,
4010 PARM_BOUNDARY is used for all arguments.
4012 V.4 wants long longs to be double word aligned.
4013 Doubleword align SPE vectors.
4014 Quadword align Altivec vectors.
4015 Quadword align large synthetic vector types. */
4018 function_arg_boundary (enum machine_mode mode
, tree type
)
4020 if (DEFAULT_ABI
== ABI_V4
&& GET_MODE_SIZE (mode
) == 8)
4022 else if (SPE_VECTOR_MODE (mode
)
4023 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4024 && int_size_in_bytes (type
) >= 8
4025 && int_size_in_bytes (type
) < 16))
4027 else if (ALTIVEC_VECTOR_MODE (mode
)
4028 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4029 && int_size_in_bytes (type
) >= 16))
4031 else if (rs6000_darwin64_abi
&& mode
== BLKmode
4032 && type
&& TYPE_ALIGN (type
) > 64)
4035 return PARM_BOUNDARY
;
4038 /* For a function parm of MODE and TYPE, return the starting word in
4039 the parameter area. NWORDS of the parameter area are already used. */
4042 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
4045 unsigned int parm_offset
;
4047 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
4048 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
4049 return nwords
+ (-(parm_offset
+ nwords
) & align
);
4052 /* Compute the size (in words) of a function argument. */
4054 static unsigned long
4055 rs6000_arg_size (enum machine_mode mode
, tree type
)
4059 if (mode
!= BLKmode
)
4060 size
= GET_MODE_SIZE (mode
);
4062 size
= int_size_in_bytes (type
);
4065 return (size
+ 3) >> 2;
4067 return (size
+ 7) >> 3;
4070 /* Use this to flush pending int fields. */
4073 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
4074 HOST_WIDE_INT bitpos
)
4076 unsigned int startbit
, endbit
;
4077 int intregs
, intoffset
;
4078 enum machine_mode mode
;
4080 if (cum
->intoffset
== -1)
4083 intoffset
= cum
->intoffset
;
4084 cum
->intoffset
= -1;
4086 if (intoffset
% BITS_PER_WORD
!= 0)
4088 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4090 if (mode
== BLKmode
)
4092 /* We couldn't find an appropriate mode, which happens,
4093 e.g., in packed structs when there are 3 bytes to load.
4094 Back intoffset back to the beginning of the word in this
4096 intoffset
= intoffset
& -BITS_PER_WORD
;
4100 startbit
= intoffset
& -BITS_PER_WORD
;
4101 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4102 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
4103 cum
->words
+= intregs
;
4106 /* The darwin64 ABI calls for us to recurse down through structs,
4107 looking for elements passed in registers. Unfortunately, we have
4108 to track int register count here also because of misalignments
4109 in powerpc alignment mode. */
4112 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
4114 HOST_WIDE_INT startbitpos
)
4118 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
4119 if (TREE_CODE (f
) == FIELD_DECL
)
4121 HOST_WIDE_INT bitpos
= startbitpos
;
4122 tree ftype
= TREE_TYPE (f
);
4123 enum machine_mode mode
= TYPE_MODE (ftype
);
4125 if (DECL_SIZE (f
) != 0
4126 && host_integerp (bit_position (f
), 1))
4127 bitpos
+= int_bit_position (f
);
4129 /* ??? FIXME: else assume zero offset. */
4131 if (TREE_CODE (ftype
) == RECORD_TYPE
)
4132 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
4133 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
4135 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
4136 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4137 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4139 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
4141 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
4145 else if (cum
->intoffset
== -1)
4146 cum
->intoffset
= bitpos
;
4150 /* Update the data in CUM to advance over an argument
4151 of mode MODE and data type TYPE.
4152 (TYPE is null for libcalls where that information may not be available.)
4154 Note that for args passed by reference, function_arg will be called
4155 with MODE and TYPE set to that of the pointer to the arg, not the arg
4159 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4160 tree type
, int named
, int depth
)
4164 /* Only tick off an argument if we're not recursing. */
4166 cum
->nargs_prototype
--;
4168 if (TARGET_ALTIVEC_ABI
4169 && (ALTIVEC_VECTOR_MODE (mode
)
4170 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4171 && int_size_in_bytes (type
) == 16)))
4175 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
4178 if (!TARGET_ALTIVEC
)
4179 error ("Cannot pass argument in vector register because"
4180 " altivec instructions are disabled, use -maltivec"
4181 " to enable them.");
4183 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4184 even if it is going to be passed in a vector register.
4185 Darwin does the same for variable-argument functions. */
4186 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
4187 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
4197 /* Vector parameters must be 16-byte aligned. This places
4198 them at 2 mod 4 in terms of words in 32-bit mode, since
4199 the parameter save area starts at offset 24 from the
4200 stack. In 64-bit mode, they just have to start on an
4201 even word, since the parameter save area is 16-byte
4202 aligned. Space for GPRs is reserved even if the argument
4203 will be passed in memory. */
4205 align
= (2 - cum
->words
) & 3;
4207 align
= cum
->words
& 1;
4208 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
4210 if (TARGET_DEBUG_ARG
)
4212 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
4214 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
4215 cum
->nargs_prototype
, cum
->prototype
,
4216 GET_MODE_NAME (mode
));
4220 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
4222 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
4225 else if (rs6000_darwin64_abi
4227 && TREE_CODE (type
) == RECORD_TYPE
4228 && (size
= int_size_in_bytes (type
)) > 0)
4230 /* Variable sized types have size == -1 and are
4231 treated as if consisting entirely of ints.
4232 Pad to 16 byte boundary if needed. */
4233 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
4234 && (cum
->words
% 2) != 0)
4236 /* For varargs, we can just go up by the size of the struct. */
4238 cum
->words
+= (size
+ 7) / 8;
4241 /* It is tempting to say int register count just goes up by
4242 sizeof(type)/8, but this is wrong in a case such as
4243 { int; double; int; } [powerpc alignment]. We have to
4244 grovel through the fields for these too. */
4246 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
4247 rs6000_darwin64_record_arg_advance_flush (cum
,
4248 size
* BITS_PER_UNIT
);
4251 else if (DEFAULT_ABI
== ABI_V4
)
4253 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4254 && (mode
== SFmode
|| mode
== DFmode
))
4256 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
4261 cum
->words
+= cum
->words
& 1;
4262 cum
->words
+= rs6000_arg_size (mode
, type
);
4267 int n_words
= rs6000_arg_size (mode
, type
);
4268 int gregno
= cum
->sysv_gregno
;
4270 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4271 (r7,r8) or (r9,r10). As does any other 2 word item such
4272 as complex int due to a historical mistake. */
4274 gregno
+= (1 - gregno
) & 1;
4276 /* Multi-reg args are not split between registers and stack. */
4277 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
4279 /* Long long and SPE vectors are aligned on the stack.
4280 So are other 2 word items such as complex int due to
4281 a historical mistake. */
4283 cum
->words
+= cum
->words
& 1;
4284 cum
->words
+= n_words
;
4287 /* Note: continuing to accumulate gregno past when we've started
4288 spilling to the stack indicates the fact that we've started
4289 spilling to the stack to expand_builtin_saveregs. */
4290 cum
->sysv_gregno
= gregno
+ n_words
;
4293 if (TARGET_DEBUG_ARG
)
4295 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
4296 cum
->words
, cum
->fregno
);
4297 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
4298 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
4299 fprintf (stderr
, "mode = %4s, named = %d\n",
4300 GET_MODE_NAME (mode
), named
);
4305 int n_words
= rs6000_arg_size (mode
, type
);
4306 int start_words
= cum
->words
;
4307 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
4309 cum
->words
= align_words
+ n_words
;
4311 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4312 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4313 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
4315 if (TARGET_DEBUG_ARG
)
4317 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
4318 cum
->words
, cum
->fregno
);
4319 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
4320 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
4321 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
4322 named
, align_words
- start_words
, depth
);
4328 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
4334 r1
= gen_rtx_REG (DImode
, gregno
);
4335 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
4336 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
4338 else if (mode
== DCmode
)
4340 r1
= gen_rtx_REG (DImode
, gregno
);
4341 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
4342 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
4343 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
4344 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
4350 /* Determine where to put a SIMD argument on the SPE. */
4352 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4355 int gregno
= cum
->sysv_gregno
;
4357 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4358 are passed and returned in a pair of GPRs for ABI compatibility. */
4359 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DCmode
))
4361 int n_words
= rs6000_arg_size (mode
, type
);
4363 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4365 gregno
+= (1 - gregno
) & 1;
4367 /* Multi-reg args are not split between registers and stack. */
4368 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
4371 return spe_build_register_parallel (mode
, gregno
);
4375 int n_words
= rs6000_arg_size (mode
, type
);
4377 /* SPE vectors are put in odd registers. */
4378 if (n_words
== 2 && (gregno
& 1) == 0)
4381 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
4384 enum machine_mode m
= SImode
;
4386 r1
= gen_rtx_REG (m
, gregno
);
4387 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
4388 r2
= gen_rtx_REG (m
, gregno
+ 1);
4389 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
4390 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
4397 if (gregno
<= GP_ARG_MAX_REG
)
4398 return gen_rtx_REG (mode
, gregno
);
4404 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4405 structure between cum->intoffset and bitpos to integer registers. */
4408 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
4409 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
4411 enum machine_mode mode
;
4413 unsigned int startbit
, endbit
;
4414 int this_regno
, intregs
, intoffset
;
4417 if (cum
->intoffset
== -1)
4420 intoffset
= cum
->intoffset
;
4421 cum
->intoffset
= -1;
4423 /* If this is the trailing part of a word, try to only load that
4424 much into the register. Otherwise load the whole register. Note
4425 that in the latter case we may pick up unwanted bits. It's not a
4426 problem at the moment but may wish to revisit. */
4428 if (intoffset
% BITS_PER_WORD
!= 0)
4430 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4432 if (mode
== BLKmode
)
4434 /* We couldn't find an appropriate mode, which happens,
4435 e.g., in packed structs when there are 3 bytes to load.
4436 Back intoffset back to the beginning of the word in this
4438 intoffset
= intoffset
& -BITS_PER_WORD
;
4445 startbit
= intoffset
& -BITS_PER_WORD
;
4446 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4447 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
4448 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
4450 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
4453 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
4457 intoffset
/= BITS_PER_UNIT
;
4460 regno
= GP_ARG_MIN_REG
+ this_regno
;
4461 reg
= gen_rtx_REG (mode
, regno
);
4463 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4466 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4470 while (intregs
> 0);
4473 /* Recursive workhorse for the following. */
4476 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, tree type
,
4477 HOST_WIDE_INT startbitpos
, rtx rvec
[],
4482 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
4483 if (TREE_CODE (f
) == FIELD_DECL
)
4485 HOST_WIDE_INT bitpos
= startbitpos
;
4486 tree ftype
= TREE_TYPE (f
);
4487 enum machine_mode mode
= TYPE_MODE (ftype
);
4489 if (DECL_SIZE (f
) != 0
4490 && host_integerp (bit_position (f
), 1))
4491 bitpos
+= int_bit_position (f
);
4493 /* ??? FIXME: else assume zero offset. */
4495 if (TREE_CODE (ftype
) == RECORD_TYPE
)
4496 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
4497 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
4502 case SCmode
: mode
= SFmode
; break;
4503 case DCmode
: mode
= DFmode
; break;
4504 case TCmode
: mode
= TFmode
; break;
4508 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
4510 = gen_rtx_EXPR_LIST (VOIDmode
,
4511 gen_rtx_REG (mode
, cum
->fregno
++),
4512 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4516 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
4518 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
4520 = gen_rtx_EXPR_LIST (VOIDmode
,
4521 gen_rtx_REG (mode
, cum
->vregno
++),
4522 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4524 else if (cum
->intoffset
== -1)
4525 cum
->intoffset
= bitpos
;
4529 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4530 the register(s) to be used for each field and subfield of a struct
4531 being passed by value, along with the offset of where the
4532 register's value may be found in the block. FP fields go in FP
4533 register, vector fields go in vector registers, and everything
4534 else goes in int registers, packed as in memory.
4536 This code is also used for function return values. RETVAL indicates
4537 whether this is the case.
4539 Much of this is taken from the Sparc V9 port, which has a similar
4540 calling convention. */
4543 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, tree type
,
4544 int named
, bool retval
)
4546 rtx rvec
[FIRST_PSEUDO_REGISTER
];
4547 int k
= 1, kbase
= 1;
4548 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4549 /* This is a copy; modifications are not visible to our caller. */
4550 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
4551 CUMULATIVE_ARGS
*cum
= ©_cum
;
4553 /* Pad to 16 byte boundary if needed. */
4554 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
4555 && (cum
->words
% 2) != 0)
4562 /* Put entries into rvec[] for individual FP and vector fields, and
4563 for the chunks of memory that go in int regs. Note we start at
4564 element 1; 0 is reserved for an indication of using memory, and
4565 may or may not be filled in below. */
4566 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
4567 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
4569 /* If any part of the struct went on the stack put all of it there.
4570 This hack is because the generic code for
4571 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4572 parts of the struct are not at the beginning. */
4576 return NULL_RTX
; /* doesn't go in registers at all */
4578 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4580 if (k
> 1 || cum
->use_stack
)
4581 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
4586 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4589 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
4593 rtx rvec
[GP_ARG_NUM_REG
+ 1];
4595 if (align_words
>= GP_ARG_NUM_REG
)
4598 n_units
= rs6000_arg_size (mode
, type
);
4600 /* Optimize the simple case where the arg fits in one gpr, except in
4601 the case of BLKmode due to assign_parms assuming that registers are
4602 BITS_PER_WORD wide. */
4604 || (n_units
== 1 && mode
!= BLKmode
))
4605 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
4608 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
4609 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4610 using a magic NULL_RTX component.
4611 FIXME: This is not strictly correct. Only some of the arg
4612 belongs in memory, not all of it. However, there isn't any way
4613 to do this currently, apart from building rtx descriptions for
4614 the pieces of memory we want stored. Due to bugs in the generic
4615 code we can't use the normal function_arg_partial_nregs scheme
4616 with the PARALLEL arg description we emit here.
4617 In any case, the code to store the whole arg to memory is often
4618 more efficient than code to store pieces, and we know that space
4619 is available in the right place for the whole arg. */
4620 /* FIXME: This should be fixed since the conversion to
4621 TARGET_ARG_PARTIAL_BYTES. */
4622 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4627 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
4628 rtx off
= GEN_INT (i
++ * 4);
4629 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
4631 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
4633 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
4636 /* Determine where to put an argument to a function.
4637 Value is zero to push the argument on the stack,
4638 or a hard register in which to store the argument.
4640 MODE is the argument's machine mode.
4641 TYPE is the data type of the argument (as a tree).
4642 This is null for libcalls where that information may
4644 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4645 the preceding args and about the function being called. It is
4646 not modified in this routine.
4647 NAMED is nonzero if this argument is a named parameter
4648 (otherwise it is an extra parameter matching an ellipsis).
4650 On RS/6000 the first eight words of non-FP are normally in registers
4651 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4652 Under V.4, the first 8 FP args are in registers.
4654 If this is floating-point and no prototype is specified, we use
4655 both an FP and integer register (or possibly FP reg and stack). Library
4656 functions (when CALL_LIBCALL is set) always have the proper types for args,
4657 so we can pass the FP value just in one register. emit_library_function
4658 doesn't support PARALLEL anyway.
4660 Note that for args passed by reference, function_arg will be called
4661 with MODE and TYPE set to that of the pointer to the arg, not the arg
4665 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4666 tree type
, int named
)
4668 enum rs6000_abi abi
= DEFAULT_ABI
;
4670 /* Return a marker to indicate whether CR1 needs to set or clear the
4671 bit that V.4 uses to say fp args were passed in registers.
4672 Assume that we don't need the marker for software floating point,
4673 or compiler generated library calls. */
4674 if (mode
== VOIDmode
)
4677 && cum
->nargs_prototype
< 0
4678 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
4679 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))
4681 /* For the SPE, we need to crxor CR6 always. */
4683 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
4684 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4685 return GEN_INT (cum
->call_cookie
4686 | ((cum
->fregno
== FP_ARG_MIN_REG
)
4687 ? CALL_V4_SET_FP_ARGS
4688 : CALL_V4_CLEAR_FP_ARGS
));
4691 return GEN_INT (cum
->call_cookie
);
4694 if (rs6000_darwin64_abi
&& mode
== BLKmode
4695 && TREE_CODE (type
) == RECORD_TYPE
)
4697 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
4698 if (rslt
!= NULL_RTX
)
4700 /* Else fall through to usual handling. */
4703 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
4704 if (TARGET_64BIT
&& ! cum
->prototype
)
4706 /* Vector parameters get passed in vector register
4707 and also in GPRs or memory, in absence of prototype. */
4710 align_words
= (cum
->words
+ 1) & ~1;
4712 if (align_words
>= GP_ARG_NUM_REG
)
4718 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
4720 return gen_rtx_PARALLEL (mode
,
4722 gen_rtx_EXPR_LIST (VOIDmode
,
4724 gen_rtx_EXPR_LIST (VOIDmode
,
4725 gen_rtx_REG (mode
, cum
->vregno
),
4729 return gen_rtx_REG (mode
, cum
->vregno
);
4730 else if (TARGET_ALTIVEC_ABI
4731 && (ALTIVEC_VECTOR_MODE (mode
)
4732 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4733 && int_size_in_bytes (type
) == 16)))
4735 if (named
|| abi
== ABI_V4
)
4739 /* Vector parameters to varargs functions under AIX or Darwin
4740 get passed in memory and possibly also in GPRs. */
4741 int align
, align_words
, n_words
;
4742 enum machine_mode part_mode
;
4744 /* Vector parameters must be 16-byte aligned. This places them at
4745 2 mod 4 in terms of words in 32-bit mode, since the parameter
4746 save area starts at offset 24 from the stack. In 64-bit mode,
4747 they just have to start on an even word, since the parameter
4748 save area is 16-byte aligned. */
4750 align
= (2 - cum
->words
) & 3;
4752 align
= cum
->words
& 1;
4753 align_words
= cum
->words
+ align
;
4755 /* Out of registers? Memory, then. */
4756 if (align_words
>= GP_ARG_NUM_REG
)
4759 if (TARGET_32BIT
&& TARGET_POWERPC64
)
4760 return rs6000_mixed_function_arg (mode
, type
, align_words
);
4762 /* The vector value goes in GPRs. Only the part of the
4763 value in GPRs is reported here. */
4765 n_words
= rs6000_arg_size (mode
, type
);
4766 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
4767 /* Fortunately, there are only two possibilities, the value
4768 is either wholly in GPRs or half in GPRs and half not. */
4771 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
4774 else if (TARGET_SPE_ABI
&& TARGET_SPE
4775 && (SPE_VECTOR_MODE (mode
)
4776 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
4777 || mode
== DCmode
))))
4778 return rs6000_spe_function_arg (cum
, mode
, type
);
4780 else if (abi
== ABI_V4
)
4782 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4783 && (mode
== SFmode
|| mode
== DFmode
))
4785 if (cum
->fregno
<= FP_ARG_V4_MAX_REG
)
4786 return gen_rtx_REG (mode
, cum
->fregno
);
4792 int n_words
= rs6000_arg_size (mode
, type
);
4793 int gregno
= cum
->sysv_gregno
;
4795 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4796 (r7,r8) or (r9,r10). As does any other 2 word item such
4797 as complex int due to a historical mistake. */
4799 gregno
+= (1 - gregno
) & 1;
4801 /* Multi-reg args are not split between registers and stack. */
4802 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
4805 if (TARGET_32BIT
&& TARGET_POWERPC64
)
4806 return rs6000_mixed_function_arg (mode
, type
,
4807 gregno
- GP_ARG_MIN_REG
);
4808 return gen_rtx_REG (mode
, gregno
);
4813 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
4815 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
4817 rtx rvec
[GP_ARG_NUM_REG
+ 1];
4821 enum machine_mode fmode
= mode
;
4822 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
4824 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
4826 /* Currently, we only ever need one reg here because complex
4827 doubles are split. */
4828 if (cum
->fregno
!= FP_ARG_MAX_REG
|| fmode
!= TFmode
)
4831 /* Long double split over regs and memory. */
4835 /* Do we also need to pass this arg in the parameter save
4838 && (cum
->nargs_prototype
<= 0
4839 || (DEFAULT_ABI
== ABI_AIX
4841 && align_words
>= GP_ARG_NUM_REG
)));
4843 if (!needs_psave
&& mode
== fmode
)
4844 return gen_rtx_REG (fmode
, cum
->fregno
);
4849 /* Describe the part that goes in gprs or the stack.
4850 This piece must come first, before the fprs. */
4851 if (align_words
< GP_ARG_NUM_REG
)
4853 unsigned long n_words
= rs6000_arg_size (mode
, type
);
4855 if (align_words
+ n_words
> GP_ARG_NUM_REG
4856 || (TARGET_32BIT
&& TARGET_POWERPC64
))
4858 /* If this is partially on the stack, then we only
4859 include the portion actually in registers here. */
4860 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
4863 if (align_words
+ n_words
> GP_ARG_NUM_REG
4864 && (TARGET_32BIT
&& TARGET_POWERPC64
))
4865 /* Not all of the arg fits in gprs. Say that it
4866 goes in memory too, using a magic NULL_RTX
4867 component. Also see comment in
4868 rs6000_mixed_function_arg for why the normal
4869 function_arg_partial_nregs scheme doesn't work
4871 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
4875 r
= gen_rtx_REG (rmode
,
4876 GP_ARG_MIN_REG
+ align_words
);
4877 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
4878 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
4880 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
4884 /* The whole arg fits in gprs. */
4885 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
4886 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
4890 /* It's entirely in memory. */
4891 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4894 /* Describe where this piece goes in the fprs. */
4895 r
= gen_rtx_REG (fmode
, cum
->fregno
);
4896 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
4898 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
4900 else if (align_words
< GP_ARG_NUM_REG
)
4902 if (TARGET_32BIT
&& TARGET_POWERPC64
)
4903 return rs6000_mixed_function_arg (mode
, type
, align_words
);
4905 if (mode
== BLKmode
)
4908 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
4915 /* For an arg passed partly in registers and partly in memory, this is
4916 the number of bytes passed in registers. For args passed entirely in
4917 registers or entirely in memory, zero. When an arg is described by a
4918 PARALLEL, perhaps using more than one register type, this function
4919 returns the number of bytes used by the first element of the PARALLEL. */
4922 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4923 tree type
, bool named
)
4928 if (DEFAULT_ABI
== ABI_V4
)
4931 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
4932 && cum
->nargs_prototype
>= 0)
4935 /* In this complicated case we just disable the partial_nregs code. */
4936 if (rs6000_darwin64_abi
&& mode
== BLKmode
4937 && TREE_CODE (type
) == RECORD_TYPE
4938 && int_size_in_bytes (type
) > 0)
4941 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
4943 if (USE_FP_FOR_ARG_P (cum
, mode
, type
)
4944 /* If we are passing this arg in the fixed parameter save area
4945 (gprs or memory) as well as fprs, then this function should
4946 return the number of bytes passed in the parameter save area
4947 rather than bytes passed in fprs. */
4949 && (cum
->nargs_prototype
<= 0
4950 || (DEFAULT_ABI
== ABI_AIX
4952 && align_words
>= GP_ARG_NUM_REG
))))
4954 if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3) > FP_ARG_MAX_REG
+ 1)
4955 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
4956 else if (cum
->nargs_prototype
>= 0)
4960 if (align_words
< GP_ARG_NUM_REG
4961 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
4962 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
4964 if (ret
!= 0 && TARGET_DEBUG_ARG
)
4965 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
4970 /* A C expression that indicates when an argument must be passed by
4971 reference. If nonzero for an argument, a copy of that argument is
4972 made in memory and a pointer to the argument is passed instead of
4973 the argument itself. The pointer is passed in whatever way is
4974 appropriate for passing a pointer to that type.
4976 Under V.4, aggregates and long double are passed by reference.
4978 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
4979 reference unless the AltiVec vector extension ABI is in force.
4981 As an extension to all ABIs, variable sized types are passed by
4985 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4986 enum machine_mode mode
, tree type
,
4987 bool named ATTRIBUTE_UNUSED
)
4989 if (DEFAULT_ABI
== ABI_V4
&& mode
== TFmode
)
4991 if (TARGET_DEBUG_ARG
)
4992 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
4999 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
5001 if (TARGET_DEBUG_ARG
)
5002 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
5006 if (int_size_in_bytes (type
) < 0)
5008 if (TARGET_DEBUG_ARG
)
5009 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
5013 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5014 modes only exist for GCC vector types if -maltivec. */
5015 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
5017 if (TARGET_DEBUG_ARG
)
5018 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
5022 /* Pass synthetic vectors in memory. */
5023 if (TREE_CODE (type
) == VECTOR_TYPE
5024 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5026 static bool warned_for_pass_big_vectors
= false;
5027 if (TARGET_DEBUG_ARG
)
5028 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
5029 if (!warned_for_pass_big_vectors
)
5031 warning ("GCC vector passed by reference: "
5032 "non-standard ABI extension with no compatibility guarantee");
5033 warned_for_pass_big_vectors
= true;
5042 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
5045 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
5050 for (i
= 0; i
< nregs
; i
++)
5052 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
5053 if (reload_completed
)
5055 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
5058 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
5059 i
* GET_MODE_SIZE (reg_mode
));
5062 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
5064 if (tem
== NULL_RTX
)
5067 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
5071 /* Perform any needed actions needed for a function that is receiving a
5072 variable number of arguments.
5076 MODE and TYPE are the mode and type of the current parameter.
5078 PRETEND_SIZE is a variable that should be set to the amount of stack
5079 that must be pushed by the prolog to pretend that our caller pushed
5082 Normally, this macro will push all remaining incoming registers on the
5083 stack and set PRETEND_SIZE to the length of the registers pushed. */
5086 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5087 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5090 CUMULATIVE_ARGS next_cum
;
5091 int reg_size
= TARGET_32BIT
? 4 : 8;
5092 rtx save_area
= NULL_RTX
, mem
;
5093 int first_reg_offset
, set
;
5095 /* Skip the last named argument. */
5097 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
5099 if (DEFAULT_ABI
== ABI_V4
)
5102 save_area
= plus_constant (virtual_stack_vars_rtx
,
5103 - RS6000_VARARGS_SIZE
);
5105 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
5109 first_reg_offset
= next_cum
.words
;
5110 save_area
= virtual_incoming_args_rtx
;
5112 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5113 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
5116 set
= get_varargs_alias_set ();
5117 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
5118 && cfun
->va_list_gpr_size
)
5120 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
5122 if (va_list_gpr_counter_field
)
5124 /* V4 va_list_gpr_size counts number of registers needed. */
5125 if (nregs
> cfun
->va_list_gpr_size
)
5126 nregs
= cfun
->va_list_gpr_size
;
5130 /* char * va_list instead counts number of bytes needed. */
5131 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
5132 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
5135 mem
= gen_rtx_MEM (BLKmode
,
5136 plus_constant (save_area
,
5137 first_reg_offset
* reg_size
)),
5138 set_mem_alias_set (mem
, set
);
5139 set_mem_align (mem
, BITS_PER_WORD
);
5141 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
5145 /* Save FP registers if needed. */
5146 if (DEFAULT_ABI
== ABI_V4
5147 && TARGET_HARD_FLOAT
&& TARGET_FPRS
5149 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
5150 && cfun
->va_list_fpr_size
)
5152 int fregno
= next_cum
.fregno
, nregs
;
5153 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
5154 rtx lab
= gen_label_rtx ();
5155 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
) * 8);
5158 (gen_rtx_SET (VOIDmode
,
5160 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5161 gen_rtx_NE (VOIDmode
, cr1
,
5163 gen_rtx_LABEL_REF (VOIDmode
, lab
),
5167 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
5168 fregno
++, off
+= 8, nregs
++)
5170 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
5171 set_mem_alias_set (mem
, set
);
5172 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
5173 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
5180 /* Create the va_list data type. */
5183 rs6000_build_builtin_va_list (void)
5185 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
5187 /* For AIX, prefer 'char *' because that's what the system
5188 header files like. */
5189 if (DEFAULT_ABI
!= ABI_V4
)
5190 return build_pointer_type (char_type_node
);
5192 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5193 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5195 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
5196 unsigned_char_type_node
);
5197 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
5198 unsigned_char_type_node
);
5199 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5201 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
5202 short_unsigned_type_node
);
5203 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
5205 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
5208 va_list_gpr_counter_field
= f_gpr
;
5209 va_list_fpr_counter_field
= f_fpr
;
5211 DECL_FIELD_CONTEXT (f_gpr
) = record
;
5212 DECL_FIELD_CONTEXT (f_fpr
) = record
;
5213 DECL_FIELD_CONTEXT (f_res
) = record
;
5214 DECL_FIELD_CONTEXT (f_ovf
) = record
;
5215 DECL_FIELD_CONTEXT (f_sav
) = record
;
5217 TREE_CHAIN (record
) = type_decl
;
5218 TYPE_NAME (record
) = type_decl
;
5219 TYPE_FIELDS (record
) = f_gpr
;
5220 TREE_CHAIN (f_gpr
) = f_fpr
;
5221 TREE_CHAIN (f_fpr
) = f_res
;
5222 TREE_CHAIN (f_res
) = f_ovf
;
5223 TREE_CHAIN (f_ovf
) = f_sav
;
5225 layout_type (record
);
5227 /* The correct type is an array type of one element. */
5228 return build_array_type (record
, build_index_type (size_zero_node
));
5231 /* Implement va_start. */
5234 rs6000_va_start (tree valist
, rtx nextarg
)
5236 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
5237 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5238 tree gpr
, fpr
, ovf
, sav
, t
;
5240 /* Only SVR4 needs something special. */
5241 if (DEFAULT_ABI
!= ABI_V4
)
5243 std_expand_builtin_va_start (valist
, nextarg
);
5247 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5248 f_fpr
= TREE_CHAIN (f_gpr
);
5249 f_res
= TREE_CHAIN (f_fpr
);
5250 f_ovf
= TREE_CHAIN (f_res
);
5251 f_sav
= TREE_CHAIN (f_ovf
);
5253 valist
= build_va_arg_indirect_ref (valist
);
5254 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
5255 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
5256 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
5257 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
5259 /* Count number of gp and fp argument registers used. */
5260 words
= current_function_args_info
.words
;
5261 n_gpr
= MIN (current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
,
5263 n_fpr
= MIN (current_function_args_info
.fregno
- FP_ARG_MIN_REG
,
5266 if (TARGET_DEBUG_ARG
)
5267 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
5268 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
5269 words
, n_gpr
, n_fpr
);
5271 if (cfun
->va_list_gpr_size
)
5273 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
5274 build_int_cst (NULL_TREE
, n_gpr
));
5275 TREE_SIDE_EFFECTS (t
) = 1;
5276 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5279 if (cfun
->va_list_fpr_size
)
5281 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
5282 build_int_cst (NULL_TREE
, n_fpr
));
5283 TREE_SIDE_EFFECTS (t
) = 1;
5284 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5287 /* Find the overflow area. */
5288 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
5290 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
5291 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
5292 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
5293 TREE_SIDE_EFFECTS (t
) = 1;
5294 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5296 /* If there were no va_arg invocations, don't set up the register
5298 if (!cfun
->va_list_gpr_size
5299 && !cfun
->va_list_fpr_size
5300 && n_gpr
< GP_ARG_NUM_REG
5301 && n_fpr
< FP_ARG_V4_MAX_REG
)
5304 /* Find the register save area. */
5305 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
5306 t
= build (PLUS_EXPR
, TREE_TYPE (sav
), t
,
5307 build_int_cst (NULL_TREE
, -RS6000_VARARGS_SIZE
));
5308 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
5309 TREE_SIDE_EFFECTS (t
) = 1;
5310 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5313 /* Implement va_arg. */
5316 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
5318 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
5319 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
5320 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
5321 tree lab_false
, lab_over
, addr
;
5323 tree ptrtype
= build_pointer_type (type
);
5325 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
5327 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
5328 return build_va_arg_indirect_ref (t
);
5331 if (DEFAULT_ABI
!= ABI_V4
)
5333 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
5335 tree elem_type
= TREE_TYPE (type
);
5336 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
5337 int elem_size
= GET_MODE_SIZE (elem_mode
);
5339 if (elem_size
< UNITS_PER_WORD
)
5341 tree real_part
, imag_part
;
5342 tree post
= NULL_TREE
;
5344 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
5346 /* Copy the value into a temporary, lest the formal temporary
5347 be reused out from under us. */
5348 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
5349 append_to_statement_list (post
, pre_p
);
5351 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
5354 return build (COMPLEX_EXPR
, type
, real_part
, imag_part
);
5358 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5361 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
5362 f_fpr
= TREE_CHAIN (f_gpr
);
5363 f_res
= TREE_CHAIN (f_fpr
);
5364 f_ovf
= TREE_CHAIN (f_res
);
5365 f_sav
= TREE_CHAIN (f_ovf
);
5367 valist
= build_va_arg_indirect_ref (valist
);
5368 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
5369 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
5370 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
5371 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
5373 size
= int_size_in_bytes (type
);
5374 rsize
= (size
+ 3) / 4;
5377 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5378 && (TYPE_MODE (type
) == SFmode
|| TYPE_MODE (type
) == DFmode
))
5380 /* FP args go in FP registers, if present. */
5385 if (TYPE_MODE (type
) == DFmode
)
5390 /* Otherwise into GP registers. */
5399 /* Pull the value out of the saved registers.... */
5402 addr
= create_tmp_var (ptr_type_node
, "addr");
5403 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
5405 /* AltiVec vectors never go in registers when -mabi=altivec. */
5406 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5410 lab_false
= create_artificial_label ();
5411 lab_over
= create_artificial_label ();
5413 /* Long long and SPE vectors are aligned in the registers.
5414 As are any other 2 gpr item such as complex int due to a
5415 historical mistake. */
5419 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
5420 size_int (n_reg
- 1));
5421 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
5424 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
5425 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
5426 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
5427 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
5428 gimplify_and_add (t
, pre_p
);
5432 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
5434 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, size_int (n_reg
));
5435 u
= build1 (CONVERT_EXPR
, integer_type_node
, u
);
5436 u
= build2 (MULT_EXPR
, integer_type_node
, u
, size_int (sav_scale
));
5437 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
, u
);
5439 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
5440 gimplify_and_add (t
, pre_p
);
5442 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
5443 gimplify_and_add (t
, pre_p
);
5445 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
5446 append_to_statement_list (t
, pre_p
);
5450 /* Ensure that we don't find any more args in regs.
5451 Alignment has taken care of the n_reg == 2 case. */
5452 t
= build (MODIFY_EXPR
, TREE_TYPE (reg
), reg
, size_int (8));
5453 gimplify_and_add (t
, pre_p
);
5457 /* ... otherwise out of the overflow area. */
5459 /* Care for on-stack alignment if needed. */
5463 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
5464 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
5465 build_int_cst (NULL_TREE
, -align
));
5467 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
5469 u
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
5470 gimplify_and_add (u
, pre_p
);
5472 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
5473 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
5474 gimplify_and_add (t
, pre_p
);
5478 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
5479 append_to_statement_list (t
, pre_p
);
5482 addr
= fold_convert (ptrtype
, addr
);
5483 return build_va_arg_indirect_ref (addr
);
5488 #define def_builtin(MASK, NAME, TYPE, CODE) \
5490 if ((MASK) & target_flags) \
5491 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5495 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5497 static const struct builtin_description bdesc_3arg
[] =
5499 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
5500 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
5501 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
5502 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
5503 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
5504 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
5505 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
5506 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
5507 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
5508 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
5509 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
5510 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
5511 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
5512 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
5513 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
5514 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
5515 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
5516 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
5517 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
5518 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
5519 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
5520 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
5521 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
5524 /* DST operations: void foo (void *, const int, const char). */
5526 static const struct builtin_description bdesc_dst
[] =
5528 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
5529 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
5530 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
5531 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
}
5534 /* Simple binary operations: VECc = foo (VECa, VECb). */
5536 static struct builtin_description bdesc_2arg
[] =
5538 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
5539 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
5540 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
5541 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
5542 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
5543 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
5544 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
5545 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
5546 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
5547 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
5548 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
5549 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
5550 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
5551 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
5552 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
5553 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
5554 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
5555 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
5556 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
5557 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
5558 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
5559 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
5560 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
5561 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
5562 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
5563 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
5564 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
5565 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
5566 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
5567 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
5568 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
5569 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
5570 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
5571 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
5572 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
5573 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
5574 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
5575 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
5576 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
5577 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
5578 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
5579 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
5580 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
5581 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
5582 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
5583 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
5584 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
5585 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
5586 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
5587 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
5588 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
5589 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
5590 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
5591 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
5592 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
5593 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
5594 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
5595 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
5596 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
5597 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
5598 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
5599 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
5600 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
5601 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
5602 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
5603 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
5604 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
5605 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
5606 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
5607 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhss
, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS
},
5608 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
5609 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwss
, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS
},
5610 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
5611 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
5612 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
5613 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
5614 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
5615 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
5616 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
5617 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
5618 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
5619 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
5620 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
5621 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
5622 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
5623 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
5624 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
5625 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
5626 { MASK_ALTIVEC
, CODE_FOR_lshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
5627 { MASK_ALTIVEC
, CODE_FOR_lshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
5628 { MASK_ALTIVEC
, CODE_FOR_lshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
5629 { MASK_ALTIVEC
, CODE_FOR_ashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
5630 { MASK_ALTIVEC
, CODE_FOR_ashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
5631 { MASK_ALTIVEC
, CODE_FOR_ashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
5632 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
5633 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
5634 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
5635 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
5636 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
5637 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
5638 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
5639 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
5640 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
5641 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
5642 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
5643 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
5644 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
5645 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
5646 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
5647 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
5648 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
5649 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
5650 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
5652 /* Place holder, leave as first spe builtin. */
5653 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
5654 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
5655 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
5656 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
5657 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
5658 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
5659 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
5660 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
5661 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
5662 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
5663 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
5664 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
5665 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
5666 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
5667 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
5668 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
5669 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
5670 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
5671 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
5672 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
5673 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
5674 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
5675 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
5676 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
5677 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
5678 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
5679 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
5680 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
5681 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
5682 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
5683 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
5684 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
5685 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
5686 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
5687 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
5688 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
5689 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
5690 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
5691 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
5692 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
5693 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
5694 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
5695 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
5696 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
5697 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
5698 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
5699 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
5700 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
5701 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
5702 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
5703 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
5704 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
5705 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
5706 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
5707 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
5708 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
5709 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
5710 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
5711 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
5712 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
5713 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
5714 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
5715 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
5716 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
5717 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
5718 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
5719 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
5720 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
5721 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
5722 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
5723 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
5724 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
5725 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
5726 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
5727 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
5728 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
5729 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
5730 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
5731 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
5732 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
5733 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
5734 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
5735 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
5736 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
5737 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
5738 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
5739 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
5740 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
5741 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
5742 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
5743 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
5744 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
5745 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
5746 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
5747 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
5748 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
5749 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
5750 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
5751 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
5752 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
5753 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
5754 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
5755 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
5756 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
5757 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
5758 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
5759 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
5760 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
5761 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
5763 /* SPE binary operations expecting a 5-bit unsigned literal. */
5764 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
5766 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
5767 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
5768 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
5769 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
5770 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
5771 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
5772 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
5773 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
5774 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
5775 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
5776 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
5777 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
5778 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
5779 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
5780 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
5781 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
5782 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
5783 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
5784 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
5785 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
5786 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
5787 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
5788 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
5789 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
5790 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
5791 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
5793 /* Place-holder. Leave as last binary SPE builtin. */
5794 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
},
5797 /* AltiVec predicates. */
5799 struct builtin_description_predicates
5801 const unsigned int mask
;
5802 const enum insn_code icode
;
5804 const char *const name
;
5805 const enum rs6000_builtins code
;
5808 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
5810 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
5811 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
5812 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
5813 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
5814 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
5815 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
5816 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
5817 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
5818 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
5819 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
5820 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
5821 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
5822 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
}
5825 /* SPE predicates. */
5826 static struct builtin_description bdesc_spe_predicates
[] =
5828 /* Place-holder. Leave as first. */
5829 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
5830 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
5831 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
5832 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
5833 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
5834 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
5835 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
5836 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
5837 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
5838 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
5839 /* Place-holder. Leave as last. */
5840 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
5843 /* SPE evsel predicates. */
5844 static struct builtin_description bdesc_spe_evsel
[] =
5846 /* Place-holder. Leave as first. */
5847 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
5848 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
5849 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
5850 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
5851 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
5852 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
5853 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
5854 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
5855 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
5856 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
5857 /* Place-holder. Leave as last. */
5858 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
5861 /* ABS* operations. */
5863 static const struct builtin_description bdesc_abs
[] =
5865 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
5866 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
5867 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
5868 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
5869 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
5870 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
5871 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
5874 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5877 static struct builtin_description bdesc_1arg
[] =
5879 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
5880 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
5881 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
5882 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
5883 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
5884 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
5885 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
5886 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
5887 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
5888 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
5889 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
5890 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
5891 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
5892 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
5893 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
5894 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
5895 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
5897 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5898 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5899 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
5900 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
5901 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
5902 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
5903 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
5904 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
5905 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
5906 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
5907 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
5908 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
5909 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
5910 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
5911 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
5912 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
5913 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
5914 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
5915 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
5916 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
5917 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
5918 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
5919 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
5920 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
5921 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
5922 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
5923 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
5924 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
5925 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
5926 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
5928 /* Place-holder. Leave as last unary SPE builtin. */
5929 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
5933 rs6000_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
5936 tree arg0
= TREE_VALUE (arglist
);
5937 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5938 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5939 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5941 if (icode
== CODE_FOR_nothing
)
5942 /* Builtin not supported on this processor. */
5945 /* If we got invalid arguments bail out before generating bad rtl. */
5946 if (arg0
== error_mark_node
)
5949 if (icode
== CODE_FOR_altivec_vspltisb
5950 || icode
== CODE_FOR_altivec_vspltish
5951 || icode
== CODE_FOR_altivec_vspltisw
5952 || icode
== CODE_FOR_spe_evsplatfi
5953 || icode
== CODE_FOR_spe_evsplati
)
5955 /* Only allow 5-bit *signed* literals. */
5956 if (GET_CODE (op0
) != CONST_INT
5957 || INTVAL (op0
) > 0x1f
5958 || INTVAL (op0
) < -0x1f)
5960 error ("argument 1 must be a 5-bit signed literal");
5966 || GET_MODE (target
) != tmode
5967 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5968 target
= gen_reg_rtx (tmode
);
5970 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5971 op0
= copy_to_mode_reg (mode0
, op0
);
5973 pat
= GEN_FCN (icode
) (target
, op0
);
5982 altivec_expand_abs_builtin (enum insn_code icode
, tree arglist
, rtx target
)
5984 rtx pat
, scratch1
, scratch2
;
5985 tree arg0
= TREE_VALUE (arglist
);
5986 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5987 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5988 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5990 /* If we have invalid arguments, bail out before generating bad rtl. */
5991 if (arg0
== error_mark_node
)
5995 || GET_MODE (target
) != tmode
5996 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5997 target
= gen_reg_rtx (tmode
);
5999 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6000 op0
= copy_to_mode_reg (mode0
, op0
);
6002 scratch1
= gen_reg_rtx (mode0
);
6003 scratch2
= gen_reg_rtx (mode0
);
6005 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
6014 rs6000_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6017 tree arg0
= TREE_VALUE (arglist
);
6018 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6019 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6020 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6021 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6022 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6023 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6025 if (icode
== CODE_FOR_nothing
)
6026 /* Builtin not supported on this processor. */
6029 /* If we got invalid arguments bail out before generating bad rtl. */
6030 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6033 if (icode
== CODE_FOR_altivec_vcfux
6034 || icode
== CODE_FOR_altivec_vcfsx
6035 || icode
== CODE_FOR_altivec_vctsxs
6036 || icode
== CODE_FOR_altivec_vctuxs
6037 || icode
== CODE_FOR_altivec_vspltb
6038 || icode
== CODE_FOR_altivec_vsplth
6039 || icode
== CODE_FOR_altivec_vspltw
6040 || icode
== CODE_FOR_spe_evaddiw
6041 || icode
== CODE_FOR_spe_evldd
6042 || icode
== CODE_FOR_spe_evldh
6043 || icode
== CODE_FOR_spe_evldw
6044 || icode
== CODE_FOR_spe_evlhhesplat
6045 || icode
== CODE_FOR_spe_evlhhossplat
6046 || icode
== CODE_FOR_spe_evlhhousplat
6047 || icode
== CODE_FOR_spe_evlwhe
6048 || icode
== CODE_FOR_spe_evlwhos
6049 || icode
== CODE_FOR_spe_evlwhou
6050 || icode
== CODE_FOR_spe_evlwhsplat
6051 || icode
== CODE_FOR_spe_evlwwsplat
6052 || icode
== CODE_FOR_spe_evrlwi
6053 || icode
== CODE_FOR_spe_evslwi
6054 || icode
== CODE_FOR_spe_evsrwis
6055 || icode
== CODE_FOR_spe_evsubifw
6056 || icode
== CODE_FOR_spe_evsrwiu
)
6058 /* Only allow 5-bit unsigned literals. */
6060 if (TREE_CODE (arg1
) != INTEGER_CST
6061 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6063 error ("argument 2 must be a 5-bit unsigned literal");
6069 || GET_MODE (target
) != tmode
6070 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6071 target
= gen_reg_rtx (tmode
);
6073 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6074 op0
= copy_to_mode_reg (mode0
, op0
);
6075 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6076 op1
= copy_to_mode_reg (mode1
, op1
);
6078 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
6087 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
6088 tree arglist
, rtx target
)
6091 tree cr6_form
= TREE_VALUE (arglist
);
6092 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
6093 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6094 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6095 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6096 enum machine_mode tmode
= SImode
;
6097 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6098 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6101 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
6103 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6107 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
6112 /* If we have invalid arguments, bail out before generating bad rtl. */
6113 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6117 || GET_MODE (target
) != tmode
6118 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6119 target
= gen_reg_rtx (tmode
);
6121 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6122 op0
= copy_to_mode_reg (mode0
, op0
);
6123 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6124 op1
= copy_to_mode_reg (mode1
, op1
);
6126 scratch
= gen_reg_rtx (mode0
);
6128 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
6129 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
6134 /* The vec_any* and vec_all* predicates use the same opcodes for two
6135 different operations, but the bits in CR6 will be different
6136 depending on what information we want. So we have to play tricks
6137 with CR6 to get the right bits out.
6139 If you think this is disgusting, look at the specs for the
6140 AltiVec predicates. */
6142 switch (cr6_form_int
)
6145 emit_insn (gen_cr6_test_for_zero (target
));
6148 emit_insn (gen_cr6_test_for_zero_reverse (target
));
6151 emit_insn (gen_cr6_test_for_lt (target
));
6154 emit_insn (gen_cr6_test_for_lt_reverse (target
));
6157 error ("argument 1 of __builtin_altivec_predicate is out of range");
6165 altivec_expand_lv_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6168 tree arg0
= TREE_VALUE (arglist
);
6169 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6170 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6171 enum machine_mode mode0
= Pmode
;
6172 enum machine_mode mode1
= Pmode
;
6173 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6174 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6176 if (icode
== CODE_FOR_nothing
)
6177 /* Builtin not supported on this processor. */
6180 /* If we got invalid arguments bail out before generating bad rtl. */
6181 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6185 || GET_MODE (target
) != tmode
6186 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6187 target
= gen_reg_rtx (tmode
);
6189 op1
= copy_to_mode_reg (mode1
, op1
);
6191 if (op0
== const0_rtx
)
6193 addr
= gen_rtx_MEM (tmode
, op1
);
6197 op0
= copy_to_mode_reg (mode0
, op0
);
6198 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
6201 pat
= GEN_FCN (icode
) (target
, addr
);
6211 spe_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6213 tree arg0
= TREE_VALUE (arglist
);
6214 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6215 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6216 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6217 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6218 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6220 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
6221 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
6222 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
6224 /* Invalid arguments. Bail before doing anything stoopid! */
6225 if (arg0
== error_mark_node
6226 || arg1
== error_mark_node
6227 || arg2
== error_mark_node
)
6230 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
6231 op0
= copy_to_mode_reg (mode2
, op0
);
6232 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
6233 op1
= copy_to_mode_reg (mode0
, op1
);
6234 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
6235 op2
= copy_to_mode_reg (mode1
, op2
);
6237 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
6244 altivec_expand_stv_builtin (enum insn_code icode
, tree arglist
)
6246 tree arg0
= TREE_VALUE (arglist
);
6247 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6248 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6249 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6250 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6251 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6253 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6254 enum machine_mode mode1
= Pmode
;
6255 enum machine_mode mode2
= Pmode
;
6257 /* Invalid arguments. Bail before doing anything stoopid! */
6258 if (arg0
== error_mark_node
6259 || arg1
== error_mark_node
6260 || arg2
== error_mark_node
)
6263 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
6264 op0
= copy_to_mode_reg (tmode
, op0
);
6266 op2
= copy_to_mode_reg (mode2
, op2
);
6268 if (op1
== const0_rtx
)
6270 addr
= gen_rtx_MEM (tmode
, op2
);
6274 op1
= copy_to_mode_reg (mode1
, op1
);
6275 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
6278 pat
= GEN_FCN (icode
) (addr
, op0
);
6285 rs6000_expand_ternop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6288 tree arg0
= TREE_VALUE (arglist
);
6289 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6290 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6291 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6292 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6293 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6294 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6295 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6296 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6297 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
6299 if (icode
== CODE_FOR_nothing
)
6300 /* Builtin not supported on this processor. */
6303 /* If we got invalid arguments bail out before generating bad rtl. */
6304 if (arg0
== error_mark_node
6305 || arg1
== error_mark_node
6306 || arg2
== error_mark_node
)
6309 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
6310 || icode
== CODE_FOR_altivec_vsldoi_v4si
6311 || icode
== CODE_FOR_altivec_vsldoi_v8hi
6312 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
6314 /* Only allow 4-bit unsigned literals. */
6316 if (TREE_CODE (arg2
) != INTEGER_CST
6317 || TREE_INT_CST_LOW (arg2
) & ~0xf)
6319 error ("argument 3 must be a 4-bit unsigned literal");
6325 || GET_MODE (target
) != tmode
6326 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6327 target
= gen_reg_rtx (tmode
);
6329 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6330 op0
= copy_to_mode_reg (mode0
, op0
);
6331 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6332 op1
= copy_to_mode_reg (mode1
, op1
);
6333 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
6334 op2
= copy_to_mode_reg (mode2
, op2
);
6336 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
6344 /* Expand the lvx builtins. */
6346 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
6348 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6349 tree arglist
= TREE_OPERAND (exp
, 1);
6350 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6352 enum machine_mode tmode
, mode0
;
6354 enum insn_code icode
;
6358 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
6359 icode
= CODE_FOR_altivec_lvx_v16qi
;
6361 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
6362 icode
= CODE_FOR_altivec_lvx_v8hi
;
6364 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
6365 icode
= CODE_FOR_altivec_lvx_v4si
;
6367 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
6368 icode
= CODE_FOR_altivec_lvx_v4sf
;
6377 arg0
= TREE_VALUE (arglist
);
6378 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6379 tmode
= insn_data
[icode
].operand
[0].mode
;
6380 mode0
= insn_data
[icode
].operand
[1].mode
;
6383 || GET_MODE (target
) != tmode
6384 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6385 target
= gen_reg_rtx (tmode
);
6387 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6388 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
6390 pat
= GEN_FCN (icode
) (target
, op0
);
6397 /* Expand the stvx builtins. */
6399 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
6402 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6403 tree arglist
= TREE_OPERAND (exp
, 1);
6404 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6406 enum machine_mode mode0
, mode1
;
6408 enum insn_code icode
;
6412 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
6413 icode
= CODE_FOR_altivec_stvx_v16qi
;
6415 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
6416 icode
= CODE_FOR_altivec_stvx_v8hi
;
6418 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
6419 icode
= CODE_FOR_altivec_stvx_v4si
;
6421 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
6422 icode
= CODE_FOR_altivec_stvx_v4sf
;
6429 arg0
= TREE_VALUE (arglist
);
6430 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6431 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6432 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6433 mode0
= insn_data
[icode
].operand
[0].mode
;
6434 mode1
= insn_data
[icode
].operand
[1].mode
;
6436 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6437 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
6438 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
6439 op1
= copy_to_mode_reg (mode1
, op1
);
6441 pat
= GEN_FCN (icode
) (op0
, op1
);
6449 /* Expand the dst builtins. */
6451 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
6454 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6455 tree arglist
= TREE_OPERAND (exp
, 1);
6456 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6457 tree arg0
, arg1
, arg2
;
6458 enum machine_mode mode0
, mode1
, mode2
;
6459 rtx pat
, op0
, op1
, op2
;
6460 struct builtin_description
*d
;
6465 /* Handle DST variants. */
6466 d
= (struct builtin_description
*) bdesc_dst
;
6467 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
6468 if (d
->code
== fcode
)
6470 arg0
= TREE_VALUE (arglist
);
6471 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6472 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6473 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6474 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6475 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6476 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
6477 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
6478 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
6480 /* Invalid arguments, bail out before generating bad rtl. */
6481 if (arg0
== error_mark_node
6482 || arg1
== error_mark_node
6483 || arg2
== error_mark_node
)
6488 if (TREE_CODE (arg2
) != INTEGER_CST
6489 || TREE_INT_CST_LOW (arg2
) & ~0x3)
6491 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
6495 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
6496 op0
= copy_to_mode_reg (Pmode
, op0
);
6497 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
6498 op1
= copy_to_mode_reg (mode1
, op1
);
6500 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
6510 /* Expand the builtin in EXP and store the result in TARGET. Store
6511 true in *EXPANDEDP if we found a builtin to expand. */
6513 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
6515 struct builtin_description
*d
;
6516 struct builtin_description_predicates
*dp
;
6518 enum insn_code icode
;
6519 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6520 tree arglist
= TREE_OPERAND (exp
, 1);
6523 enum machine_mode tmode
, mode0
;
6524 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6526 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
6530 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
6534 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
6542 case ALTIVEC_BUILTIN_STVX
:
6543 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, arglist
);
6544 case ALTIVEC_BUILTIN_STVEBX
:
6545 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, arglist
);
6546 case ALTIVEC_BUILTIN_STVEHX
:
6547 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, arglist
);
6548 case ALTIVEC_BUILTIN_STVEWX
:
6549 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, arglist
);
6550 case ALTIVEC_BUILTIN_STVXL
:
6551 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, arglist
);
6553 case ALTIVEC_BUILTIN_MFVSCR
:
6554 icode
= CODE_FOR_altivec_mfvscr
;
6555 tmode
= insn_data
[icode
].operand
[0].mode
;
6558 || GET_MODE (target
) != tmode
6559 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6560 target
= gen_reg_rtx (tmode
);
6562 pat
= GEN_FCN (icode
) (target
);
6568 case ALTIVEC_BUILTIN_MTVSCR
:
6569 icode
= CODE_FOR_altivec_mtvscr
;
6570 arg0
= TREE_VALUE (arglist
);
6571 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6572 mode0
= insn_data
[icode
].operand
[0].mode
;
6574 /* If we got invalid arguments bail out before generating bad rtl. */
6575 if (arg0
== error_mark_node
)
6578 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6579 op0
= copy_to_mode_reg (mode0
, op0
);
6581 pat
= GEN_FCN (icode
) (op0
);
6586 case ALTIVEC_BUILTIN_DSSALL
:
6587 emit_insn (gen_altivec_dssall ());
6590 case ALTIVEC_BUILTIN_DSS
:
6591 icode
= CODE_FOR_altivec_dss
;
6592 arg0
= TREE_VALUE (arglist
);
6594 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6595 mode0
= insn_data
[icode
].operand
[0].mode
;
6597 /* If we got invalid arguments bail out before generating bad rtl. */
6598 if (arg0
== error_mark_node
)
6601 if (TREE_CODE (arg0
) != INTEGER_CST
6602 || TREE_INT_CST_LOW (arg0
) & ~0x3)
6604 error ("argument to dss must be a 2-bit unsigned literal");
6608 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6609 op0
= copy_to_mode_reg (mode0
, op0
);
6611 emit_insn (gen_altivec_dss (op0
));
6614 case ALTIVEC_BUILTIN_COMPILETIME_ERROR
:
6615 arg0
= TREE_VALUE (arglist
);
6616 while (TREE_CODE (arg0
) == NOP_EXPR
|| TREE_CODE (arg0
) == ADDR_EXPR
6617 || TREE_CODE (arg0
) == ARRAY_REF
)
6618 arg0
= TREE_OPERAND (arg0
, 0);
6619 error ("invalid parameter combination for %qs AltiVec intrinsic",
6620 TREE_STRING_POINTER (arg0
));
6625 /* Expand abs* operations. */
6626 d
= (struct builtin_description
*) bdesc_abs
;
6627 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
6628 if (d
->code
== fcode
)
6629 return altivec_expand_abs_builtin (d
->icode
, arglist
, target
);
6631 /* Expand the AltiVec predicates. */
6632 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
6633 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
6634 if (dp
->code
== fcode
)
6635 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
6638 /* LV* are funky. We initialized them differently. */
6641 case ALTIVEC_BUILTIN_LVSL
:
6642 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
6644 case ALTIVEC_BUILTIN_LVSR
:
6645 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
6647 case ALTIVEC_BUILTIN_LVEBX
:
6648 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
6650 case ALTIVEC_BUILTIN_LVEHX
:
6651 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
6653 case ALTIVEC_BUILTIN_LVEWX
:
6654 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
6656 case ALTIVEC_BUILTIN_LVXL
:
6657 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
6659 case ALTIVEC_BUILTIN_LVX
:
6660 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
6671 /* Binops that need to be initialized manually, but can be expanded
6672 automagically by rs6000_expand_binop_builtin. */
6673 static struct builtin_description bdesc_2arg_spe
[] =
6675 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
6676 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
6677 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
6678 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
6679 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
6680 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
6681 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
6682 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
6683 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
6684 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
6685 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
6686 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
6687 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
6688 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
6689 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
6690 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
6691 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
6692 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
6693 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
6694 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
6695 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
6696 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
6699 /* Expand the builtin in EXP and store the result in TARGET. Store
6700 true in *EXPANDEDP if we found a builtin to expand.
6702 This expands the SPE builtins that are not simple unary and binary
6705 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
6707 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6708 tree arglist
= TREE_OPERAND (exp
, 1);
6710 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6711 enum insn_code icode
;
6712 enum machine_mode tmode
, mode0
;
6714 struct builtin_description
*d
;
6719 /* Syntax check for a 5-bit unsigned immediate. */
6722 case SPE_BUILTIN_EVSTDD
:
6723 case SPE_BUILTIN_EVSTDH
:
6724 case SPE_BUILTIN_EVSTDW
:
6725 case SPE_BUILTIN_EVSTWHE
:
6726 case SPE_BUILTIN_EVSTWHO
:
6727 case SPE_BUILTIN_EVSTWWE
:
6728 case SPE_BUILTIN_EVSTWWO
:
6729 arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6730 if (TREE_CODE (arg1
) != INTEGER_CST
6731 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
6733 error ("argument 2 must be a 5-bit unsigned literal");
6741 /* The evsplat*i instructions are not quite generic. */
6744 case SPE_BUILTIN_EVSPLATFI
:
6745 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
6747 case SPE_BUILTIN_EVSPLATI
:
6748 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
6754 d
= (struct builtin_description
*) bdesc_2arg_spe
;
6755 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
6756 if (d
->code
== fcode
)
6757 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
6759 d
= (struct builtin_description
*) bdesc_spe_predicates
;
6760 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
6761 if (d
->code
== fcode
)
6762 return spe_expand_predicate_builtin (d
->icode
, arglist
, target
);
6764 d
= (struct builtin_description
*) bdesc_spe_evsel
;
6765 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
6766 if (d
->code
== fcode
)
6767 return spe_expand_evsel_builtin (d
->icode
, arglist
, target
);
6771 case SPE_BUILTIN_EVSTDDX
:
6772 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, arglist
);
6773 case SPE_BUILTIN_EVSTDHX
:
6774 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, arglist
);
6775 case SPE_BUILTIN_EVSTDWX
:
6776 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, arglist
);
6777 case SPE_BUILTIN_EVSTWHEX
:
6778 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, arglist
);
6779 case SPE_BUILTIN_EVSTWHOX
:
6780 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, arglist
);
6781 case SPE_BUILTIN_EVSTWWEX
:
6782 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, arglist
);
6783 case SPE_BUILTIN_EVSTWWOX
:
6784 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, arglist
);
6785 case SPE_BUILTIN_EVSTDD
:
6786 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, arglist
);
6787 case SPE_BUILTIN_EVSTDH
:
6788 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, arglist
);
6789 case SPE_BUILTIN_EVSTDW
:
6790 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, arglist
);
6791 case SPE_BUILTIN_EVSTWHE
:
6792 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, arglist
);
6793 case SPE_BUILTIN_EVSTWHO
:
6794 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, arglist
);
6795 case SPE_BUILTIN_EVSTWWE
:
6796 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, arglist
);
6797 case SPE_BUILTIN_EVSTWWO
:
6798 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, arglist
);
6799 case SPE_BUILTIN_MFSPEFSCR
:
6800 icode
= CODE_FOR_spe_mfspefscr
;
6801 tmode
= insn_data
[icode
].operand
[0].mode
;
6804 || GET_MODE (target
) != tmode
6805 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6806 target
= gen_reg_rtx (tmode
);
6808 pat
= GEN_FCN (icode
) (target
);
6813 case SPE_BUILTIN_MTSPEFSCR
:
6814 icode
= CODE_FOR_spe_mtspefscr
;
6815 arg0
= TREE_VALUE (arglist
);
6816 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6817 mode0
= insn_data
[icode
].operand
[0].mode
;
6819 if (arg0
== error_mark_node
)
6822 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
6823 op0
= copy_to_mode_reg (mode0
, op0
);
6825 pat
= GEN_FCN (icode
) (op0
);
6838 spe_expand_predicate_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6840 rtx pat
, scratch
, tmp
;
6841 tree form
= TREE_VALUE (arglist
);
6842 tree arg0
= TREE_VALUE (TREE_CHAIN (arglist
));
6843 tree arg1
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6844 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6845 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6846 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6847 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6851 if (TREE_CODE (form
) != INTEGER_CST
)
6853 error ("argument 1 of __builtin_spe_predicate must be a constant");
6857 form_int
= TREE_INT_CST_LOW (form
);
6862 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
6866 || GET_MODE (target
) != SImode
6867 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
6868 target
= gen_reg_rtx (SImode
);
6870 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6871 op0
= copy_to_mode_reg (mode0
, op0
);
6872 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
6873 op1
= copy_to_mode_reg (mode1
, op1
);
6875 scratch
= gen_reg_rtx (CCmode
);
6877 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
6882 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6883 _lower_. We use one compare, but look in different bits of the
6884 CR for each variant.
6886 There are 2 elements in each SPE simd type (upper/lower). The CR
6887 bits are set as follows:
6889 BIT0 | BIT 1 | BIT 2 | BIT 3
6890 U | L | (U | L) | (U & L)
6892 So, for an "all" relationship, BIT 3 would be set.
6893 For an "any" relationship, BIT 2 would be set. Etc.
6895 Following traditional nomenclature, these bits map to:
6897 BIT0 | BIT 1 | BIT 2 | BIT 3
6900 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6905 /* All variant. OV bit. */
6907 /* We need to get to the OV bit, which is the ORDERED bit. We
6908 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6909 that's ugly and will trigger a validate_condition_mode abort.
6910 So let's just use another pattern. */
6911 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
6913 /* Any variant. EQ bit. */
6917 /* Upper variant. LT bit. */
6921 /* Lower variant. GT bit. */
6926 error ("argument 1 of __builtin_spe_predicate is out of range");
6930 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
6931 emit_move_insn (target
, tmp
);
6936 /* The evsel builtins look like this:
6938 e = __builtin_spe_evsel_OP (a, b, c, d);
6942 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6943 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6947 spe_expand_evsel_builtin (enum insn_code icode
, tree arglist
, rtx target
)
6950 tree arg0
= TREE_VALUE (arglist
);
6951 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
6952 tree arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
6953 tree arg3
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist
))));
6954 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
6955 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
6956 rtx op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
6957 rtx op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0);
6958 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
6959 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
6964 if (arg0
== error_mark_node
|| arg1
== error_mark_node
6965 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
6969 || GET_MODE (target
) != mode0
6970 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
6971 target
= gen_reg_rtx (mode0
);
6973 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
6974 op0
= copy_to_mode_reg (mode0
, op0
);
6975 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
6976 op1
= copy_to_mode_reg (mode0
, op1
);
6977 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
6978 op2
= copy_to_mode_reg (mode0
, op2
);
6979 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
6980 op3
= copy_to_mode_reg (mode0
, op3
);
6982 /* Generate the compare. */
6983 scratch
= gen_reg_rtx (CCmode
);
6984 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
6989 if (mode0
== V2SImode
)
6990 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
6992 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
6997 /* Expand an expression EXP that calls a built-in function,
6998 with result going to TARGET if that's convenient
6999 (and in mode MODE if that's convenient).
7000 SUBTARGET may be used as the target for computing one of EXP's operands.
7001 IGNORE is nonzero if the value is to be ignored. */
7004 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
7005 enum machine_mode mode ATTRIBUTE_UNUSED
,
7006 int ignore ATTRIBUTE_UNUSED
)
7008 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7009 tree arglist
= TREE_OPERAND (exp
, 1);
7010 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7011 struct builtin_description
*d
;
7016 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
7017 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7019 int icode
= (int) CODE_FOR_altivec_lvsr
;
7020 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7021 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
7025 if (!TARGET_ALTIVEC
)
7028 arg
= TREE_VALUE (arglist
);
7029 if (TREE_CODE (TREE_TYPE (arg
)) != POINTER_TYPE
)
7031 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
7032 addr
= memory_address (mode
, op
);
7033 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
7037 /* For the load case need to negate the address. */
7038 op
= gen_reg_rtx (GET_MODE (addr
));
7039 emit_insn (gen_rtx_SET (VOIDmode
, op
,
7040 gen_rtx_NEG (GET_MODE (addr
), addr
)));
7042 op
= gen_rtx_MEM (mode
, op
);
7045 || GET_MODE (target
) != tmode
7046 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7047 target
= gen_reg_rtx (tmode
);
7049 /*pat = gen_altivec_lvsr (target, op);*/
7050 pat
= GEN_FCN (icode
) (target
, op
);
7060 ret
= altivec_expand_builtin (exp
, target
, &success
);
7067 ret
= spe_expand_builtin (exp
, target
, &success
);
7073 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7075 /* Handle simple unary operations. */
7076 d
= (struct builtin_description
*) bdesc_1arg
;
7077 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
7078 if (d
->code
== fcode
)
7079 return rs6000_expand_unop_builtin (d
->icode
, arglist
, target
);
7081 /* Handle simple binary operations. */
7082 d
= (struct builtin_description
*) bdesc_2arg
;
7083 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
7084 if (d
->code
== fcode
)
7085 return rs6000_expand_binop_builtin (d
->icode
, arglist
, target
);
7087 /* Handle simple ternary operations. */
7088 d
= (struct builtin_description
*) bdesc_3arg
;
7089 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7090 if (d
->code
== fcode
)
7091 return rs6000_expand_ternop_builtin (d
->icode
, arglist
, target
);
7099 build_opaque_vector_type (tree node
, int nunits
)
7101 node
= copy_node (node
);
7102 TYPE_MAIN_VARIANT (node
) = node
;
7103 return build_vector_type (node
, nunits
);
7107 rs6000_init_builtins (void)
7109 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
7110 V2SF_type_node
= build_vector_type (float_type_node
, 2);
7111 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
7112 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
7113 V4SF_type_node
= build_vector_type (float_type_node
, 4);
7114 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
7115 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
7117 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
7118 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
7119 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
7121 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
7122 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
7123 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
7125 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7126 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7127 'vector unsigned short'. */
7129 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
7130 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7131 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
7132 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
7134 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7135 get_identifier ("__bool char"),
7136 bool_char_type_node
));
7137 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7138 get_identifier ("__bool short"),
7139 bool_short_type_node
));
7140 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7141 get_identifier ("__bool int"),
7142 bool_int_type_node
));
7143 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7144 get_identifier ("__pixel"),
7147 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
7148 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
7149 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
7150 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
7152 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7153 get_identifier ("__vector unsigned char"),
7154 unsigned_V16QI_type_node
));
7155 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7156 get_identifier ("__vector signed char"),
7158 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7159 get_identifier ("__vector __bool char"),
7160 bool_V16QI_type_node
));
7162 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7163 get_identifier ("__vector unsigned short"),
7164 unsigned_V8HI_type_node
));
7165 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7166 get_identifier ("__vector signed short"),
7168 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7169 get_identifier ("__vector __bool short"),
7170 bool_V8HI_type_node
));
7172 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7173 get_identifier ("__vector unsigned int"),
7174 unsigned_V4SI_type_node
));
7175 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7176 get_identifier ("__vector signed int"),
7178 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7179 get_identifier ("__vector __bool int"),
7180 bool_V4SI_type_node
));
7182 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7183 get_identifier ("__vector float"),
7185 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
7186 get_identifier ("__vector __pixel"),
7187 pixel_V8HI_type_node
));
7190 spe_init_builtins ();
7192 altivec_init_builtins ();
7193 if (TARGET_ALTIVEC
|| TARGET_SPE
)
7194 rs6000_common_init_builtins ();
7197 /* Search through a set of builtins and enable the mask bits.
7198 DESC is an array of builtins.
7199 SIZE is the total number of builtins.
7200 START is the builtin enum at which to start.
7201 END is the builtin enum at which to end. */
7203 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
7204 enum rs6000_builtins start
,
7205 enum rs6000_builtins end
)
7209 for (i
= 0; i
< size
; ++i
)
7210 if (desc
[i
].code
== start
)
7216 for (; i
< size
; ++i
)
7218 /* Flip all the bits on. */
7219 desc
[i
].mask
= target_flags
;
7220 if (desc
[i
].code
== end
)
7226 spe_init_builtins (void)
7228 tree endlink
= void_list_node
;
7229 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
7230 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
7231 struct builtin_description
*d
;
7234 tree v2si_ftype_4_v2si
7235 = build_function_type
7236 (opaque_V2SI_type_node
,
7237 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7238 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7239 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7240 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7243 tree v2sf_ftype_4_v2sf
7244 = build_function_type
7245 (opaque_V2SF_type_node
,
7246 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7247 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7248 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7249 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7252 tree int_ftype_int_v2si_v2si
7253 = build_function_type
7255 tree_cons (NULL_TREE
, integer_type_node
,
7256 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7257 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7260 tree int_ftype_int_v2sf_v2sf
7261 = build_function_type
7263 tree_cons (NULL_TREE
, integer_type_node
,
7264 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7265 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
7268 tree void_ftype_v2si_puint_int
7269 = build_function_type (void_type_node
,
7270 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7271 tree_cons (NULL_TREE
, puint_type_node
,
7272 tree_cons (NULL_TREE
,
7276 tree void_ftype_v2si_puint_char
7277 = build_function_type (void_type_node
,
7278 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7279 tree_cons (NULL_TREE
, puint_type_node
,
7280 tree_cons (NULL_TREE
,
7284 tree void_ftype_v2si_pv2si_int
7285 = build_function_type (void_type_node
,
7286 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7287 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
7288 tree_cons (NULL_TREE
,
7292 tree void_ftype_v2si_pv2si_char
7293 = build_function_type (void_type_node
,
7294 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
7295 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
7296 tree_cons (NULL_TREE
,
7301 = build_function_type (void_type_node
,
7302 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
7305 = build_function_type (integer_type_node
, endlink
);
7307 tree v2si_ftype_pv2si_int
7308 = build_function_type (opaque_V2SI_type_node
,
7309 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
7310 tree_cons (NULL_TREE
, integer_type_node
,
7313 tree v2si_ftype_puint_int
7314 = build_function_type (opaque_V2SI_type_node
,
7315 tree_cons (NULL_TREE
, puint_type_node
,
7316 tree_cons (NULL_TREE
, integer_type_node
,
7319 tree v2si_ftype_pushort_int
7320 = build_function_type (opaque_V2SI_type_node
,
7321 tree_cons (NULL_TREE
, pushort_type_node
,
7322 tree_cons (NULL_TREE
, integer_type_node
,
7325 tree v2si_ftype_signed_char
7326 = build_function_type (opaque_V2SI_type_node
,
7327 tree_cons (NULL_TREE
, signed_char_type_node
,
7330 /* The initialization of the simple binary and unary builtins is
7331 done in rs6000_common_init_builtins, but we have to enable the
7332 mask bits here manually because we have run out of `target_flags'
7333 bits. We really need to redesign this mask business. */
7335 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
7336 ARRAY_SIZE (bdesc_2arg
),
7339 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
7340 ARRAY_SIZE (bdesc_1arg
),
7342 SPE_BUILTIN_EVSUBFUSIAAW
);
7343 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
7344 ARRAY_SIZE (bdesc_spe_predicates
),
7345 SPE_BUILTIN_EVCMPEQ
,
7346 SPE_BUILTIN_EVFSTSTLT
);
7347 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
7348 ARRAY_SIZE (bdesc_spe_evsel
),
7349 SPE_BUILTIN_EVSEL_CMPGTS
,
7350 SPE_BUILTIN_EVSEL_FSTSTEQ
);
7352 (*lang_hooks
.decls
.pushdecl
)
7353 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
7354 opaque_V2SI_type_node
));
7356 /* Initialize irregular SPE builtins. */
7358 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
7359 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
7360 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
7361 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
7362 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
7363 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
7364 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
7365 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
7366 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
7367 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
7368 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
7369 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
7370 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
7371 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
7372 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
7373 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
7374 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
7375 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
7378 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
7379 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
7380 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
7381 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
7382 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
7383 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
7384 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
7385 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
7386 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
7387 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
7388 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
7389 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
7390 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
7391 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
7392 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
7393 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
7394 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
7395 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
7396 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
7397 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
7398 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
7399 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
7402 d
= (struct builtin_description
*) bdesc_spe_predicates
;
7403 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
7407 switch (insn_data
[d
->icode
].operand
[1].mode
)
7410 type
= int_ftype_int_v2si_v2si
;
7413 type
= int_ftype_int_v2sf_v2sf
;
7419 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7422 /* Evsel predicates. */
7423 d
= (struct builtin_description
*) bdesc_spe_evsel
;
7424 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
7428 switch (insn_data
[d
->icode
].operand
[1].mode
)
7431 type
= v2si_ftype_4_v2si
;
7434 type
= v2sf_ftype_4_v2sf
;
7440 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7445 altivec_init_builtins (void)
7447 struct builtin_description
*d
;
7448 struct builtin_description_predicates
*dp
;
7450 tree pfloat_type_node
= build_pointer_type (float_type_node
);
7451 tree pint_type_node
= build_pointer_type (integer_type_node
);
7452 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
7453 tree pchar_type_node
= build_pointer_type (char_type_node
);
7455 tree pvoid_type_node
= build_pointer_type (void_type_node
);
7457 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
7458 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
7459 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
7460 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
7462 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
7464 tree int_ftype_int_v4si_v4si
7465 = build_function_type_list (integer_type_node
,
7466 integer_type_node
, V4SI_type_node
,
7467 V4SI_type_node
, NULL_TREE
);
7468 tree v4sf_ftype_pcfloat
7469 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
7470 tree void_ftype_pfloat_v4sf
7471 = build_function_type_list (void_type_node
,
7472 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
7473 tree v4si_ftype_pcint
7474 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
7475 tree void_ftype_pint_v4si
7476 = build_function_type_list (void_type_node
,
7477 pint_type_node
, V4SI_type_node
, NULL_TREE
);
7478 tree v8hi_ftype_pcshort
7479 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
7480 tree void_ftype_pshort_v8hi
7481 = build_function_type_list (void_type_node
,
7482 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
7483 tree v16qi_ftype_pcchar
7484 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
7485 tree void_ftype_pchar_v16qi
7486 = build_function_type_list (void_type_node
,
7487 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
7488 tree void_ftype_v4si
7489 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
7490 tree v8hi_ftype_void
7491 = build_function_type (V8HI_type_node
, void_list_node
);
7492 tree void_ftype_void
7493 = build_function_type (void_type_node
, void_list_node
);
7495 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
7497 tree v16qi_ftype_long_pcvoid
7498 = build_function_type_list (V16QI_type_node
,
7499 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
7500 tree v8hi_ftype_long_pcvoid
7501 = build_function_type_list (V8HI_type_node
,
7502 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
7503 tree v4si_ftype_long_pcvoid
7504 = build_function_type_list (V4SI_type_node
,
7505 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
7507 tree void_ftype_v4si_long_pvoid
7508 = build_function_type_list (void_type_node
,
7509 V4SI_type_node
, long_integer_type_node
,
7510 pvoid_type_node
, NULL_TREE
);
7511 tree void_ftype_v16qi_long_pvoid
7512 = build_function_type_list (void_type_node
,
7513 V16QI_type_node
, long_integer_type_node
,
7514 pvoid_type_node
, NULL_TREE
);
7515 tree void_ftype_v8hi_long_pvoid
7516 = build_function_type_list (void_type_node
,
7517 V8HI_type_node
, long_integer_type_node
,
7518 pvoid_type_node
, NULL_TREE
);
7519 tree int_ftype_int_v8hi_v8hi
7520 = build_function_type_list (integer_type_node
,
7521 integer_type_node
, V8HI_type_node
,
7522 V8HI_type_node
, NULL_TREE
);
7523 tree int_ftype_int_v16qi_v16qi
7524 = build_function_type_list (integer_type_node
,
7525 integer_type_node
, V16QI_type_node
,
7526 V16QI_type_node
, NULL_TREE
);
7527 tree int_ftype_int_v4sf_v4sf
7528 = build_function_type_list (integer_type_node
,
7529 integer_type_node
, V4SF_type_node
,
7530 V4SF_type_node
, NULL_TREE
);
7531 tree v4si_ftype_v4si
7532 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7533 tree v8hi_ftype_v8hi
7534 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7535 tree v16qi_ftype_v16qi
7536 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7537 tree v4sf_ftype_v4sf
7538 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7539 tree void_ftype_pcvoid_int_int
7540 = build_function_type_list (void_type_node
,
7541 pcvoid_type_node
, integer_type_node
,
7542 integer_type_node
, NULL_TREE
);
7543 tree int_ftype_pcchar
7544 = build_function_type_list (integer_type_node
,
7545 pcchar_type_node
, NULL_TREE
);
7547 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
7548 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
7549 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
7550 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
7551 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
7552 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
7553 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
7554 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
7555 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
7556 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
7557 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
7558 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
7559 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
7560 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
7561 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
7562 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
7563 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
7564 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
7565 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
7566 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
7567 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
7568 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
7569 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
7570 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
7571 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
7572 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
7573 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
7574 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
7575 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
7576 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
7577 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
7578 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
7580 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7581 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_compiletime_error", int_ftype_pcchar
,
7582 ALTIVEC_BUILTIN_COMPILETIME_ERROR
);
7584 /* Add the DST variants. */
7585 d
= (struct builtin_description
*) bdesc_dst
;
7586 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
7587 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
7589 /* Initialize the predicates. */
7590 dp
= (struct builtin_description_predicates
*) bdesc_altivec_preds
;
7591 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
7593 enum machine_mode mode1
;
7596 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
7601 type
= int_ftype_int_v4si_v4si
;
7604 type
= int_ftype_int_v8hi_v8hi
;
7607 type
= int_ftype_int_v16qi_v16qi
;
7610 type
= int_ftype_int_v4sf_v4sf
;
7616 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
7619 /* Initialize the abs* operators. */
7620 d
= (struct builtin_description
*) bdesc_abs
;
7621 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
7623 enum machine_mode mode0
;
7626 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7631 type
= v4si_ftype_v4si
;
7634 type
= v8hi_ftype_v8hi
;
7637 type
= v16qi_ftype_v16qi
;
7640 type
= v4sf_ftype_v4sf
;
7646 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7653 /* Initialize target builtin that implements
7654 targetm.vectorize.builtin_mask_for_load. */
7656 decl
= lang_hooks
.builtin_function ("__builtin_altivec_mask_for_load",
7657 v16qi_ftype_long_pcvoid
,
7658 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
7660 tree_cons (get_identifier ("const"),
7661 NULL_TREE
, NULL_TREE
));
7662 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7663 altivec_builtin_mask_for_load
= decl
;
7668 rs6000_common_init_builtins (void)
7670 struct builtin_description
*d
;
7673 tree v4sf_ftype_v4sf_v4sf_v16qi
7674 = build_function_type_list (V4SF_type_node
,
7675 V4SF_type_node
, V4SF_type_node
,
7676 V16QI_type_node
, NULL_TREE
);
7677 tree v4si_ftype_v4si_v4si_v16qi
7678 = build_function_type_list (V4SI_type_node
,
7679 V4SI_type_node
, V4SI_type_node
,
7680 V16QI_type_node
, NULL_TREE
);
7681 tree v8hi_ftype_v8hi_v8hi_v16qi
7682 = build_function_type_list (V8HI_type_node
,
7683 V8HI_type_node
, V8HI_type_node
,
7684 V16QI_type_node
, NULL_TREE
);
7685 tree v16qi_ftype_v16qi_v16qi_v16qi
7686 = build_function_type_list (V16QI_type_node
,
7687 V16QI_type_node
, V16QI_type_node
,
7688 V16QI_type_node
, NULL_TREE
);
7690 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
7692 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
7693 tree v16qi_ftype_int
7694 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
7695 tree v8hi_ftype_v16qi
7696 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
7697 tree v4sf_ftype_v4sf
7698 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7700 tree v2si_ftype_v2si_v2si
7701 = build_function_type_list (opaque_V2SI_type_node
,
7702 opaque_V2SI_type_node
,
7703 opaque_V2SI_type_node
, NULL_TREE
);
7705 tree v2sf_ftype_v2sf_v2sf
7706 = build_function_type_list (opaque_V2SF_type_node
,
7707 opaque_V2SF_type_node
,
7708 opaque_V2SF_type_node
, NULL_TREE
);
7710 tree v2si_ftype_int_int
7711 = build_function_type_list (opaque_V2SI_type_node
,
7712 integer_type_node
, integer_type_node
,
7715 tree v2si_ftype_v2si
7716 = build_function_type_list (opaque_V2SI_type_node
,
7717 opaque_V2SI_type_node
, NULL_TREE
);
7719 tree v2sf_ftype_v2sf
7720 = build_function_type_list (opaque_V2SF_type_node
,
7721 opaque_V2SF_type_node
, NULL_TREE
);
7723 tree v2sf_ftype_v2si
7724 = build_function_type_list (opaque_V2SF_type_node
,
7725 opaque_V2SI_type_node
, NULL_TREE
);
7727 tree v2si_ftype_v2sf
7728 = build_function_type_list (opaque_V2SI_type_node
,
7729 opaque_V2SF_type_node
, NULL_TREE
);
7731 tree v2si_ftype_v2si_char
7732 = build_function_type_list (opaque_V2SI_type_node
,
7733 opaque_V2SI_type_node
,
7734 char_type_node
, NULL_TREE
);
7736 tree v2si_ftype_int_char
7737 = build_function_type_list (opaque_V2SI_type_node
,
7738 integer_type_node
, char_type_node
, NULL_TREE
);
7740 tree v2si_ftype_char
7741 = build_function_type_list (opaque_V2SI_type_node
,
7742 char_type_node
, NULL_TREE
);
7744 tree int_ftype_int_int
7745 = build_function_type_list (integer_type_node
,
7746 integer_type_node
, integer_type_node
,
7749 tree v4si_ftype_v4si_v4si
7750 = build_function_type_list (V4SI_type_node
,
7751 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7752 tree v4sf_ftype_v4si_int
7753 = build_function_type_list (V4SF_type_node
,
7754 V4SI_type_node
, integer_type_node
, NULL_TREE
);
7755 tree v4si_ftype_v4sf_int
7756 = build_function_type_list (V4SI_type_node
,
7757 V4SF_type_node
, integer_type_node
, NULL_TREE
);
7758 tree v4si_ftype_v4si_int
7759 = build_function_type_list (V4SI_type_node
,
7760 V4SI_type_node
, integer_type_node
, NULL_TREE
);
7761 tree v8hi_ftype_v8hi_int
7762 = build_function_type_list (V8HI_type_node
,
7763 V8HI_type_node
, integer_type_node
, NULL_TREE
);
7764 tree v16qi_ftype_v16qi_int
7765 = build_function_type_list (V16QI_type_node
,
7766 V16QI_type_node
, integer_type_node
, NULL_TREE
);
7767 tree v16qi_ftype_v16qi_v16qi_int
7768 = build_function_type_list (V16QI_type_node
,
7769 V16QI_type_node
, V16QI_type_node
,
7770 integer_type_node
, NULL_TREE
);
7771 tree v8hi_ftype_v8hi_v8hi_int
7772 = build_function_type_list (V8HI_type_node
,
7773 V8HI_type_node
, V8HI_type_node
,
7774 integer_type_node
, NULL_TREE
);
7775 tree v4si_ftype_v4si_v4si_int
7776 = build_function_type_list (V4SI_type_node
,
7777 V4SI_type_node
, V4SI_type_node
,
7778 integer_type_node
, NULL_TREE
);
7779 tree v4sf_ftype_v4sf_v4sf_int
7780 = build_function_type_list (V4SF_type_node
,
7781 V4SF_type_node
, V4SF_type_node
,
7782 integer_type_node
, NULL_TREE
);
7783 tree v4sf_ftype_v4sf_v4sf
7784 = build_function_type_list (V4SF_type_node
,
7785 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7786 tree v4sf_ftype_v4sf_v4sf_v4si
7787 = build_function_type_list (V4SF_type_node
,
7788 V4SF_type_node
, V4SF_type_node
,
7789 V4SI_type_node
, NULL_TREE
);
7790 tree v4sf_ftype_v4sf_v4sf_v4sf
7791 = build_function_type_list (V4SF_type_node
,
7792 V4SF_type_node
, V4SF_type_node
,
7793 V4SF_type_node
, NULL_TREE
);
7794 tree v4si_ftype_v4si_v4si_v4si
7795 = build_function_type_list (V4SI_type_node
,
7796 V4SI_type_node
, V4SI_type_node
,
7797 V4SI_type_node
, NULL_TREE
);
7798 tree v8hi_ftype_v8hi_v8hi
7799 = build_function_type_list (V8HI_type_node
,
7800 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7801 tree v8hi_ftype_v8hi_v8hi_v8hi
7802 = build_function_type_list (V8HI_type_node
,
7803 V8HI_type_node
, V8HI_type_node
,
7804 V8HI_type_node
, NULL_TREE
);
7805 tree v4si_ftype_v8hi_v8hi_v4si
7806 = build_function_type_list (V4SI_type_node
,
7807 V8HI_type_node
, V8HI_type_node
,
7808 V4SI_type_node
, NULL_TREE
);
7809 tree v4si_ftype_v16qi_v16qi_v4si
7810 = build_function_type_list (V4SI_type_node
,
7811 V16QI_type_node
, V16QI_type_node
,
7812 V4SI_type_node
, NULL_TREE
);
7813 tree v16qi_ftype_v16qi_v16qi
7814 = build_function_type_list (V16QI_type_node
,
7815 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7816 tree v4si_ftype_v4sf_v4sf
7817 = build_function_type_list (V4SI_type_node
,
7818 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7819 tree v8hi_ftype_v16qi_v16qi
7820 = build_function_type_list (V8HI_type_node
,
7821 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7822 tree v4si_ftype_v8hi_v8hi
7823 = build_function_type_list (V4SI_type_node
,
7824 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7825 tree v8hi_ftype_v4si_v4si
7826 = build_function_type_list (V8HI_type_node
,
7827 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7828 tree v16qi_ftype_v8hi_v8hi
7829 = build_function_type_list (V16QI_type_node
,
7830 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7831 tree v4si_ftype_v16qi_v4si
7832 = build_function_type_list (V4SI_type_node
,
7833 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
7834 tree v4si_ftype_v16qi_v16qi
7835 = build_function_type_list (V4SI_type_node
,
7836 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7837 tree v4si_ftype_v8hi_v4si
7838 = build_function_type_list (V4SI_type_node
,
7839 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
7840 tree v4si_ftype_v8hi
7841 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
7842 tree int_ftype_v4si_v4si
7843 = build_function_type_list (integer_type_node
,
7844 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
7845 tree int_ftype_v4sf_v4sf
7846 = build_function_type_list (integer_type_node
,
7847 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
7848 tree int_ftype_v16qi_v16qi
7849 = build_function_type_list (integer_type_node
,
7850 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
7851 tree int_ftype_v8hi_v8hi
7852 = build_function_type_list (integer_type_node
,
7853 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
7855 /* Add the simple ternary operators. */
7856 d
= (struct builtin_description
*) bdesc_3arg
;
7857 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
7860 enum machine_mode mode0
, mode1
, mode2
, mode3
;
7863 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
7866 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7867 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7868 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7869 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
7871 /* When all four are of the same mode. */
7872 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
7877 type
= v4si_ftype_v4si_v4si_v4si
;
7880 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
7883 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
7886 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
7892 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
7897 type
= v4si_ftype_v4si_v4si_v16qi
;
7900 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
7903 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
7906 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
7912 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
7913 && mode3
== V4SImode
)
7914 type
= v4si_ftype_v16qi_v16qi_v4si
;
7915 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
7916 && mode3
== V4SImode
)
7917 type
= v4si_ftype_v8hi_v8hi_v4si
;
7918 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
7919 && mode3
== V4SImode
)
7920 type
= v4sf_ftype_v4sf_v4sf_v4si
;
7922 /* vchar, vchar, vchar, 4 bit literal. */
7923 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
7925 type
= v16qi_ftype_v16qi_v16qi_int
;
7927 /* vshort, vshort, vshort, 4 bit literal. */
7928 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
7930 type
= v8hi_ftype_v8hi_v8hi_int
;
7932 /* vint, vint, vint, 4 bit literal. */
7933 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
7935 type
= v4si_ftype_v4si_v4si_int
;
7937 /* vfloat, vfloat, vfloat, 4 bit literal. */
7938 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
7940 type
= v4sf_ftype_v4sf_v4sf_int
;
7945 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
7948 /* Add the simple binary operators. */
7949 d
= (struct builtin_description
*) bdesc_2arg
;
7950 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
7952 enum machine_mode mode0
, mode1
, mode2
;
7955 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
7958 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7959 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7960 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7962 /* When all three operands are of the same mode. */
7963 if (mode0
== mode1
&& mode1
== mode2
)
7968 type
= v4sf_ftype_v4sf_v4sf
;
7971 type
= v4si_ftype_v4si_v4si
;
7974 type
= v16qi_ftype_v16qi_v16qi
;
7977 type
= v8hi_ftype_v8hi_v8hi
;
7980 type
= v2si_ftype_v2si_v2si
;
7983 type
= v2sf_ftype_v2sf_v2sf
;
7986 type
= int_ftype_int_int
;
7993 /* A few other combos we really don't want to do manually. */
7995 /* vint, vfloat, vfloat. */
7996 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
7997 type
= v4si_ftype_v4sf_v4sf
;
7999 /* vshort, vchar, vchar. */
8000 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8001 type
= v8hi_ftype_v16qi_v16qi
;
8003 /* vint, vshort, vshort. */
8004 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8005 type
= v4si_ftype_v8hi_v8hi
;
8007 /* vshort, vint, vint. */
8008 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
8009 type
= v8hi_ftype_v4si_v4si
;
8011 /* vchar, vshort, vshort. */
8012 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
8013 type
= v16qi_ftype_v8hi_v8hi
;
8015 /* vint, vchar, vint. */
8016 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
8017 type
= v4si_ftype_v16qi_v4si
;
8019 /* vint, vchar, vchar. */
8020 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
8021 type
= v4si_ftype_v16qi_v16qi
;
8023 /* vint, vshort, vint. */
8024 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
8025 type
= v4si_ftype_v8hi_v4si
;
8027 /* vint, vint, 5 bit literal. */
8028 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
8029 type
= v4si_ftype_v4si_int
;
8031 /* vshort, vshort, 5 bit literal. */
8032 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
8033 type
= v8hi_ftype_v8hi_int
;
8035 /* vchar, vchar, 5 bit literal. */
8036 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
8037 type
= v16qi_ftype_v16qi_int
;
8039 /* vfloat, vint, 5 bit literal. */
8040 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
8041 type
= v4sf_ftype_v4si_int
;
8043 /* vint, vfloat, 5 bit literal. */
8044 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
8045 type
= v4si_ftype_v4sf_int
;
8047 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
8048 type
= v2si_ftype_int_int
;
8050 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
8051 type
= v2si_ftype_v2si_char
;
8053 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
8054 type
= v2si_ftype_int_char
;
8057 else if (mode0
== SImode
)
8062 type
= int_ftype_v4si_v4si
;
8065 type
= int_ftype_v4sf_v4sf
;
8068 type
= int_ftype_v16qi_v16qi
;
8071 type
= int_ftype_v8hi_v8hi
;
8081 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8084 /* Add the simple unary operators. */
8085 d
= (struct builtin_description
*) bdesc_1arg
;
8086 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
8088 enum machine_mode mode0
, mode1
;
8091 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
8094 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8095 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8097 if (mode0
== V4SImode
&& mode1
== QImode
)
8098 type
= v4si_ftype_int
;
8099 else if (mode0
== V8HImode
&& mode1
== QImode
)
8100 type
= v8hi_ftype_int
;
8101 else if (mode0
== V16QImode
&& mode1
== QImode
)
8102 type
= v16qi_ftype_int
;
8103 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
8104 type
= v4sf_ftype_v4sf
;
8105 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
8106 type
= v8hi_ftype_v16qi
;
8107 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
8108 type
= v4si_ftype_v8hi
;
8109 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
8110 type
= v2si_ftype_v2si
;
8111 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
8112 type
= v2sf_ftype_v2sf
;
8113 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
8114 type
= v2sf_ftype_v2si
;
8115 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
8116 type
= v2si_ftype_v2sf
;
8117 else if (mode0
== V2SImode
&& mode1
== QImode
)
8118 type
= v2si_ftype_char
;
8122 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
8127 rs6000_init_libfuncs (void)
8129 if (!TARGET_HARD_FLOAT
)
8132 if (DEFAULT_ABI
!= ABI_V4
)
8134 if (TARGET_XCOFF
&& ! TARGET_POWER2
&& ! TARGET_POWERPC
)
8136 /* AIX library routines for float->int conversion. */
8137 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
8138 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
8139 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
8140 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
8143 /* AIX/Darwin/64-bit Linux quad floating point routines. */
8144 if (!TARGET_XL_COMPAT
)
8146 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
8147 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
8148 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
8149 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
8153 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
8154 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
8155 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
8156 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
8161 /* 32-bit SVR4 quad floating point routines. */
8163 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
8164 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
8165 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
8166 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
8167 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
8168 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
8169 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
8171 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
8172 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
8173 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
8174 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
8175 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
8176 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
8178 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
8179 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
8180 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
8181 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
8182 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
8183 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
8184 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
8189 /* Expand a block clear operation, and return 1 if successful. Return 0
8190 if we should let the compiler generate normal code.
8192 operands[0] is the destination
8193 operands[1] is the length
8194 operands[2] is the alignment */
8197 expand_block_clear (rtx operands
[])
8199 rtx orig_dest
= operands
[0];
8200 rtx bytes_rtx
= operands
[1];
8201 rtx align_rtx
= operands
[2];
8202 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
8203 HOST_WIDE_INT align
;
8204 HOST_WIDE_INT bytes
;
8209 /* If this is not a fixed size move, just call memcpy */
8213 /* If this is not a fixed size alignment, abort */
8214 if (GET_CODE (align_rtx
) != CONST_INT
)
8216 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
8218 /* Anything to clear? */
8219 bytes
= INTVAL (bytes_rtx
);
8223 /* Use the builtin memset after a point, to avoid huge code bloat.
8224 When optimize_size, avoid any significant code bloat; calling
8225 memset is about 4 instructions, so allow for one instruction to
8226 load zero and three to do clearing. */
8227 if (TARGET_ALTIVEC
&& align
>= 128)
8229 else if (TARGET_POWERPC64
&& align
>= 32)
8234 if (optimize_size
&& bytes
> 3 * clear_step
)
8236 if (! optimize_size
&& bytes
> 8 * clear_step
)
8239 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
8241 enum machine_mode mode
= BLKmode
;
8244 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
8249 else if (bytes
>= 8 && TARGET_POWERPC64
8250 /* 64-bit loads and stores require word-aligned
8252 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
8257 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
8258 { /* move 4 bytes */
8262 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
8263 { /* move 2 bytes */
8267 else /* move 1 byte at a time */
8273 dest
= adjust_address (orig_dest
, mode
, offset
);
8275 emit_move_insn (dest
, CONST0_RTX (mode
));
8282 /* Expand a block move operation, and return 1 if successful. Return 0
8283 if we should let the compiler generate normal code.
8285 operands[0] is the destination
8286 operands[1] is the source
8287 operands[2] is the length
8288 operands[3] is the alignment */
8290 #define MAX_MOVE_REG 4
8293 expand_block_move (rtx operands
[])
8295 rtx orig_dest
= operands
[0];
8296 rtx orig_src
= operands
[1];
8297 rtx bytes_rtx
= operands
[2];
8298 rtx align_rtx
= operands
[3];
8299 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
8304 rtx stores
[MAX_MOVE_REG
];
8307 /* If this is not a fixed size move, just call memcpy */
8311 /* If this is not a fixed size alignment, abort */
8312 if (GET_CODE (align_rtx
) != CONST_INT
)
8314 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
8316 /* Anything to move? */
8317 bytes
= INTVAL (bytes_rtx
);
8321 /* store_one_arg depends on expand_block_move to handle at least the size of
8322 reg_parm_stack_space. */
8323 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
8326 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
8329 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
8330 rtx (*mov
) (rtx
, rtx
);
8332 enum machine_mode mode
= BLKmode
;
8335 /* Altivec first, since it will be faster than a string move
8336 when it applies, and usually not significantly larger. */
8337 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
8341 gen_func
.mov
= gen_movv4si
;
8343 else if (TARGET_STRING
8344 && bytes
> 24 /* move up to 32 bytes at a time */
8352 && ! fixed_regs
[12])
8354 move_bytes
= (bytes
> 32) ? 32 : bytes
;
8355 gen_func
.movmemsi
= gen_movmemsi_8reg
;
8357 else if (TARGET_STRING
8358 && bytes
> 16 /* move up to 24 bytes at a time */
8364 && ! fixed_regs
[10])
8366 move_bytes
= (bytes
> 24) ? 24 : bytes
;
8367 gen_func
.movmemsi
= gen_movmemsi_6reg
;
8369 else if (TARGET_STRING
8370 && bytes
> 8 /* move up to 16 bytes at a time */
8376 move_bytes
= (bytes
> 16) ? 16 : bytes
;
8377 gen_func
.movmemsi
= gen_movmemsi_4reg
;
8379 else if (bytes
>= 8 && TARGET_POWERPC64
8380 /* 64-bit loads and stores require word-aligned
8382 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
8386 gen_func
.mov
= gen_movdi
;
8388 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
8389 { /* move up to 8 bytes at a time */
8390 move_bytes
= (bytes
> 8) ? 8 : bytes
;
8391 gen_func
.movmemsi
= gen_movmemsi_2reg
;
8393 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
8394 { /* move 4 bytes */
8397 gen_func
.mov
= gen_movsi
;
8399 else if (bytes
== 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
8400 { /* move 2 bytes */
8403 gen_func
.mov
= gen_movhi
;
8405 else if (TARGET_STRING
&& bytes
> 1)
8406 { /* move up to 4 bytes at a time */
8407 move_bytes
= (bytes
> 4) ? 4 : bytes
;
8408 gen_func
.movmemsi
= gen_movmemsi_1reg
;
8410 else /* move 1 byte at a time */
8414 gen_func
.mov
= gen_movqi
;
8417 src
= adjust_address (orig_src
, mode
, offset
);
8418 dest
= adjust_address (orig_dest
, mode
, offset
);
8420 if (mode
!= BLKmode
)
8422 rtx tmp_reg
= gen_reg_rtx (mode
);
8424 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
8425 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
8428 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
8431 for (i
= 0; i
< num_reg
; i
++)
8432 emit_insn (stores
[i
]);
8436 if (mode
== BLKmode
)
8438 /* Move the address into scratch registers. The movmemsi
8439 patterns require zero offset. */
8440 if (!REG_P (XEXP (src
, 0)))
8442 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
8443 src
= replace_equiv_address (src
, src_reg
);
8445 set_mem_size (src
, GEN_INT (move_bytes
));
8447 if (!REG_P (XEXP (dest
, 0)))
8449 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
8450 dest
= replace_equiv_address (dest
, dest_reg
);
8452 set_mem_size (dest
, GEN_INT (move_bytes
));
8454 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
8455 GEN_INT (move_bytes
& 31),
8464 /* Return a string to perform a load_multiple operation.
8465 operands[0] is the vector.
8466 operands[1] is the source address.
8467 operands[2] is the first destination register. */
8470 rs6000_output_load_multiple (rtx operands
[3])
8472 /* We have to handle the case where the pseudo used to contain the address
8473 is assigned to one of the output registers. */
8475 int words
= XVECLEN (operands
[0], 0);
8478 if (XVECLEN (operands
[0], 0) == 1)
8479 return "{l|lwz} %2,0(%1)";
8481 for (i
= 0; i
< words
; i
++)
8482 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
8483 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
8487 xop
[0] = GEN_INT (4 * (words
-1));
8488 xop
[1] = operands
[1];
8489 xop
[2] = operands
[2];
8490 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
8495 xop
[0] = GEN_INT (4 * (words
-1));
8496 xop
[1] = operands
[1];
8497 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
8498 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
8503 for (j
= 0; j
< words
; j
++)
8506 xop
[0] = GEN_INT (j
* 4);
8507 xop
[1] = operands
[1];
8508 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
8509 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
8511 xop
[0] = GEN_INT (i
* 4);
8512 xop
[1] = operands
[1];
8513 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
8518 return "{lsi|lswi} %2,%1,%N0";
8522 /* A validation routine: say whether CODE, a condition code, and MODE
8523 match. The other alternatives either don't make sense or should
8524 never be generated. */
8527 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
8529 if ((GET_RTX_CLASS (code
) != RTX_COMPARE
8530 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
)
8531 || GET_MODE_CLASS (mode
) != MODE_CC
)
8534 /* These don't make sense. */
8535 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
8536 && mode
== CCUNSmode
)
8539 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
8540 && mode
!= CCUNSmode
)
8543 if (mode
!= CCFPmode
8544 && (code
== ORDERED
|| code
== UNORDERED
8545 || code
== UNEQ
|| code
== LTGT
8546 || code
== UNGT
|| code
== UNLT
8547 || code
== UNGE
|| code
== UNLE
))
8550 /* These should never be generated except for
8551 flag_finite_math_only. */
8552 if (mode
== CCFPmode
8553 && ! flag_finite_math_only
8554 && (code
== LE
|| code
== GE
8555 || code
== UNEQ
|| code
== LTGT
8556 || code
== UNGT
|| code
== UNLT
))
8559 /* These are invalid; the information is not there. */
8560 if (mode
== CCEQmode
8561 && code
!= EQ
&& code
!= NE
)
8566 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8567 mask required to convert the result of a rotate insn into a shift
8568 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8571 includes_lshift_p (rtx shiftop
, rtx andop
)
8573 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8575 shift_mask
<<= INTVAL (shiftop
);
8577 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
8580 /* Similar, but for right shift. */
8583 includes_rshift_p (rtx shiftop
, rtx andop
)
8585 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8587 shift_mask
>>= INTVAL (shiftop
);
8589 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
8592 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8593 to perform a left shift. It must have exactly SHIFTOP least
8594 significant 0's, then one or more 1's, then zero or more 0's. */
8597 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
8599 if (GET_CODE (andop
) == CONST_INT
)
8601 HOST_WIDE_INT c
, lsb
, shift_mask
;
8604 if (c
== 0 || c
== ~0)
8608 shift_mask
<<= INTVAL (shiftop
);
8610 /* Find the least significant one bit. */
8613 /* It must coincide with the LSB of the shift mask. */
8614 if (-lsb
!= shift_mask
)
8617 /* Invert to look for the next transition (if any). */
8620 /* Remove the low group of ones (originally low group of zeros). */
8623 /* Again find the lsb, and check we have all 1's above. */
8627 else if (GET_CODE (andop
) == CONST_DOUBLE
8628 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
8630 HOST_WIDE_INT low
, high
, lsb
;
8631 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
8633 low
= CONST_DOUBLE_LOW (andop
);
8634 if (HOST_BITS_PER_WIDE_INT
< 64)
8635 high
= CONST_DOUBLE_HIGH (andop
);
8637 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
8638 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
8641 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
8643 shift_mask_high
= ~0;
8644 if (INTVAL (shiftop
) > 32)
8645 shift_mask_high
<<= INTVAL (shiftop
) - 32;
8649 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
8656 return high
== -lsb
;
8659 shift_mask_low
= ~0;
8660 shift_mask_low
<<= INTVAL (shiftop
);
8664 if (-lsb
!= shift_mask_low
)
8667 if (HOST_BITS_PER_WIDE_INT
< 64)
8672 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
8675 return high
== -lsb
;
8679 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
8685 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8686 to perform a left shift. It must have SHIFTOP or more least
8687 significant 0's, with the remainder of the word 1's. */
8690 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
8692 if (GET_CODE (andop
) == CONST_INT
)
8694 HOST_WIDE_INT c
, lsb
, shift_mask
;
8697 shift_mask
<<= INTVAL (shiftop
);
8700 /* Find the least significant one bit. */
8703 /* It must be covered by the shift mask.
8704 This test also rejects c == 0. */
8705 if ((lsb
& shift_mask
) == 0)
8708 /* Check we have all 1's above the transition, and reject all 1's. */
8709 return c
== -lsb
&& lsb
!= 1;
8711 else if (GET_CODE (andop
) == CONST_DOUBLE
8712 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
8714 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
8716 low
= CONST_DOUBLE_LOW (andop
);
8718 if (HOST_BITS_PER_WIDE_INT
< 64)
8720 HOST_WIDE_INT high
, shift_mask_high
;
8722 high
= CONST_DOUBLE_HIGH (andop
);
8726 shift_mask_high
= ~0;
8727 if (INTVAL (shiftop
) > 32)
8728 shift_mask_high
<<= INTVAL (shiftop
) - 32;
8732 if ((lsb
& shift_mask_high
) == 0)
8735 return high
== -lsb
;
8741 shift_mask_low
= ~0;
8742 shift_mask_low
<<= INTVAL (shiftop
);
8746 if ((lsb
& shift_mask_low
) == 0)
8749 return low
== -lsb
&& lsb
!= 1;
8755 /* Return 1 if operands will generate a valid arguments to rlwimi
8756 instruction for insert with right shift in 64-bit mode. The mask may
8757 not start on the first bit or stop on the last bit because wrap-around
8758 effects of instruction do not correspond to semantics of RTL insn. */
8761 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
8763 if (INTVAL (startop
) < 64
8764 && INTVAL (startop
) > 32
8765 && (INTVAL (sizeop
) + INTVAL (startop
) < 64)
8766 && (INTVAL (sizeop
) + INTVAL (startop
) > 33)
8767 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) < 96)
8768 && (INTVAL (sizeop
) + INTVAL (startop
) + INTVAL (shiftop
) >= 64)
8769 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
8775 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8776 for lfq and stfq insns iff the registers are hard registers. */
8779 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
8781 /* We might have been passed a SUBREG. */
8782 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8785 /* We might have been passed non floating point registers. */
8786 if (!FP_REGNO_P (REGNO (reg1
))
8787 || !FP_REGNO_P (REGNO (reg2
)))
8790 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8793 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8794 addr1 and addr2 must be in consecutive memory locations
8795 (addr2 == addr1 + 8). */
8798 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
8804 /* The mems cannot be volatile. */
8805 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8808 addr1
= XEXP (mem1
, 0);
8809 addr2
= XEXP (mem2
, 0);
8811 /* Extract an offset (if used) from the first addr. */
8812 if (GET_CODE (addr1
) == PLUS
)
8814 /* If not a REG, return zero. */
8815 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8819 reg1
= REGNO (XEXP (addr1
, 0));
8820 /* The offset must be constant! */
8821 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8823 offset1
= INTVAL (XEXP (addr1
, 1));
8826 else if (GET_CODE (addr1
) != REG
)
8830 reg1
= REGNO (addr1
);
8831 /* This was a simple (mem (reg)) expression. Offset is 0. */
8835 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8836 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8837 register as addr1. */
8838 if (offset1
== -8 && GET_CODE (addr2
) == REG
&& reg1
== REGNO (addr2
))
8840 if (GET_CODE (addr2
) != PLUS
)
8843 if (GET_CODE (XEXP (addr2
, 0)) != REG
8844 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8847 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8850 /* The offset for the second addr must be 8 more than the first addr. */
8851 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 8)
8854 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8859 /* Return the register class of a scratch register needed to copy IN into
8860 or out of a register in CLASS in MODE. If it can be done directly,
8861 NO_REGS is returned. */
8864 secondary_reload_class (enum reg_class
class,
8865 enum machine_mode mode ATTRIBUTE_UNUSED
,
8870 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
8872 && MACHOPIC_INDIRECT
8876 /* We cannot copy a symbolic operand directly into anything
8877 other than BASE_REGS for TARGET_ELF. So indicate that a
8878 register from BASE_REGS is needed as an intermediate
8881 On Darwin, pic addresses require a load from memory, which
8882 needs a base register. */
8883 if (class != BASE_REGS
8884 && (GET_CODE (in
) == SYMBOL_REF
8885 || GET_CODE (in
) == HIGH
8886 || GET_CODE (in
) == LABEL_REF
8887 || GET_CODE (in
) == CONST
))
8891 if (GET_CODE (in
) == REG
)
8894 if (regno
>= FIRST_PSEUDO_REGISTER
)
8896 regno
= true_regnum (in
);
8897 if (regno
>= FIRST_PSEUDO_REGISTER
)
8901 else if (GET_CODE (in
) == SUBREG
)
8903 regno
= true_regnum (in
);
8904 if (regno
>= FIRST_PSEUDO_REGISTER
)
8910 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8912 if (class == GENERAL_REGS
|| class == BASE_REGS
8913 || (regno
>= 0 && INT_REGNO_P (regno
)))
8916 /* Constants, memory, and FP registers can go into FP registers. */
8917 if ((regno
== -1 || FP_REGNO_P (regno
))
8918 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
8921 /* Memory, and AltiVec registers can go into AltiVec registers. */
8922 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
8923 && class == ALTIVEC_REGS
)
8926 /* We can copy among the CR registers. */
8927 if ((class == CR_REGS
|| class == CR0_REGS
)
8928 && regno
>= 0 && CR_REGNO_P (regno
))
8931 /* Otherwise, we need GENERAL_REGS. */
8932 return GENERAL_REGS
;
8935 /* Given a comparison operation, return the bit number in CCR to test. We
8936 know this is a valid comparison.
8938 SCC_P is 1 if this is for an scc. That means that %D will have been
8939 used instead of %C, so the bits will be in different places.
8941 Return -1 if OP isn't a valid comparison for some reason. */
8944 ccr_bit (rtx op
, int scc_p
)
8946 enum rtx_code code
= GET_CODE (op
);
8947 enum machine_mode cc_mode
;
8952 if (!COMPARISON_P (op
))
8957 if (GET_CODE (reg
) != REG
8958 || ! CR_REGNO_P (REGNO (reg
)))
8961 cc_mode
= GET_MODE (reg
);
8962 cc_regnum
= REGNO (reg
);
8963 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
8965 validate_condition_mode (code
, cc_mode
);
8967 /* When generating a sCOND operation, only positive conditions are
8969 if (scc_p
&& code
!= EQ
&& code
!= GT
&& code
!= LT
&& code
!= UNORDERED
8970 && code
!= GTU
&& code
!= LTU
)
8976 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
8978 return base_bit
+ 2;
8979 case GT
: case GTU
: case UNLE
:
8980 return base_bit
+ 1;
8981 case LT
: case LTU
: case UNGE
:
8983 case ORDERED
: case UNORDERED
:
8984 return base_bit
+ 3;
8987 /* If scc, we will have done a cror to put the bit in the
8988 unordered position. So test that bit. For integer, this is ! LT
8989 unless this is an scc insn. */
8990 return scc_p
? base_bit
+ 3 : base_bit
;
8993 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
9000 /* Return the GOT register. */
9003 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
9005 /* The second flow pass currently (June 1999) can't update
9006 regs_ever_live without disturbing other parts of the compiler, so
9007 update it here to make the prolog/epilogue code happy. */
9008 if (no_new_pseudos
&& ! regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
])
9009 regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9011 current_function_uses_pic_offset_table
= 1;
9013 return pic_offset_table_rtx
;
9016 /* Function to init struct machine_function.
9017 This will be called, via a pointer variable,
9018 from push_function_context. */
9020 static struct machine_function
*
9021 rs6000_init_machine_status (void)
9023 return ggc_alloc_cleared (sizeof (machine_function
));
9026 /* These macros test for integers and extract the low-order bits. */
9028 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9029 && GET_MODE (X) == VOIDmode)
9031 #define INT_LOWPART(X) \
9032 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9038 unsigned long val
= INT_LOWPART (op
);
9040 /* If the high bit is zero, the value is the first 1 bit we find
9042 if ((val
& 0x80000000) == 0)
9044 if ((val
& 0xffffffff) == 0)
9048 while (((val
<<= 1) & 0x80000000) == 0)
9053 /* If the high bit is set and the low bit is not, or the mask is all
9054 1's, the value is zero. */
9055 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
9058 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9061 while (((val
>>= 1) & 1) != 0)
9071 unsigned long val
= INT_LOWPART (op
);
9073 /* If the low bit is zero, the value is the first 1 bit we find from
9077 if ((val
& 0xffffffff) == 0)
9081 while (((val
>>= 1) & 1) == 0)
9087 /* If the low bit is set and the high bit is not, or the mask is all
9088 1's, the value is 31. */
9089 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
9092 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9095 while (((val
<<= 1) & 0x80000000) != 0)
9101 /* Locate some local-dynamic symbol still in use by this function
9102 so that we can print its name in some tls_ld pattern. */
9105 rs6000_get_some_local_dynamic_name (void)
9109 if (cfun
->machine
->some_ld_name
)
9110 return cfun
->machine
->some_ld_name
;
9112 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9114 && for_each_rtx (&PATTERN (insn
),
9115 rs6000_get_some_local_dynamic_name_1
, 0))
9116 return cfun
->machine
->some_ld_name
;
9121 /* Helper function for rs6000_get_some_local_dynamic_name. */
9124 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
9128 if (GET_CODE (x
) == SYMBOL_REF
)
9130 const char *str
= XSTR (x
, 0);
9131 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
9133 cfun
->machine
->some_ld_name
= str
;
9141 /* Write out a function code label. */
9144 rs6000_output_function_entry (FILE *file
, const char *fname
)
9146 if (fname
[0] != '.')
9148 switch (DEFAULT_ABI
)
9157 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
9166 RS6000_OUTPUT_BASENAME (file
, fname
);
9168 assemble_name (file
, fname
);
9171 /* Print an operand. Recognize special options, documented below. */
9174 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9175 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9177 #define SMALL_DATA_RELOC "sda21"
9178 #define SMALL_DATA_REG 0
9182 print_operand (FILE *file
, rtx x
, int code
)
9186 unsigned HOST_WIDE_INT uval
;
9191 /* Write out an instruction after the call which may be replaced
9192 with glue code by the loader. This depends on the AIX version. */
9193 asm_fprintf (file
, RS6000_CALL_GLUE
);
9196 /* %a is output_address. */
9199 /* If X is a constant integer whose low-order 5 bits are zero,
9200 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9201 in the AIX assembler where "sri" with a zero shift count
9202 writes a trash instruction. */
9203 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
9210 /* If constant, low-order 16 bits of constant, unsigned.
9211 Otherwise, write normally. */
9213 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
9215 print_operand (file
, x
, 0);
9219 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9220 for 64-bit mask direction. */
9221 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
9224 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9228 /* X is a CR register. Print the number of the GT bit of the CR. */
9229 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9230 output_operand_lossage ("invalid %%E value");
9232 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
9236 /* Like 'J' but get to the EQ bit. */
9237 if (GET_CODE (x
) != REG
)
9240 /* Bit 1 is EQ bit. */
9241 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 2;
9243 fprintf (file
, "%d", i
);
9247 /* X is a CR register. Print the number of the EQ bit of the CR */
9248 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9249 output_operand_lossage ("invalid %%E value");
9251 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
9255 /* X is a CR register. Print the shift count needed to move it
9256 to the high-order four bits. */
9257 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9258 output_operand_lossage ("invalid %%f value");
9260 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
9264 /* Similar, but print the count for the rotate in the opposite
9266 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9267 output_operand_lossage ("invalid %%F value");
9269 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
9273 /* X is a constant integer. If it is negative, print "m",
9274 otherwise print "z". This is to make an aze or ame insn. */
9275 if (GET_CODE (x
) != CONST_INT
)
9276 output_operand_lossage ("invalid %%G value");
9277 else if (INTVAL (x
) >= 0)
9284 /* If constant, output low-order five bits. Otherwise, write
9287 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
9289 print_operand (file
, x
, 0);
9293 /* If constant, output low-order six bits. Otherwise, write
9296 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
9298 print_operand (file
, x
, 0);
9302 /* Print `i' if this is a constant, else nothing. */
9308 /* Write the bit number in CCR for jump. */
9311 output_operand_lossage ("invalid %%j code");
9313 fprintf (file
, "%d", i
);
9317 /* Similar, but add one for shift count in rlinm for scc and pass
9318 scc flag to `ccr_bit'. */
9321 output_operand_lossage ("invalid %%J code");
9323 /* If we want bit 31, write a shift count of zero, not 32. */
9324 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
9328 /* X must be a constant. Write the 1's complement of the
9331 output_operand_lossage ("invalid %%k value");
9333 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
9337 /* X must be a symbolic constant on ELF. Write an
9338 expression suitable for an 'addi' that adds in the low 16
9340 if (GET_CODE (x
) != CONST
)
9342 print_operand_address (file
, x
);
9347 if (GET_CODE (XEXP (x
, 0)) != PLUS
9348 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
9349 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
9350 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
9351 output_operand_lossage ("invalid %%K value");
9352 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
9354 /* For GNU as, there must be a non-alphanumeric character
9355 between 'l' and the number. The '-' is added by
9356 print_operand() already. */
9357 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
9359 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
9363 /* %l is output_asm_label. */
9366 /* Write second word of DImode or DFmode reference. Works on register
9367 or non-indexed memory only. */
9368 if (GET_CODE (x
) == REG
)
9369 fputs (reg_names
[REGNO (x
) + 1], file
);
9370 else if (GET_CODE (x
) == MEM
)
9372 /* Handle possible auto-increment. Since it is pre-increment and
9373 we have already done it, we can just use an offset of word. */
9374 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
9375 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
9376 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
9379 output_address (XEXP (adjust_address_nv (x
, SImode
,
9383 if (small_data_operand (x
, GET_MODE (x
)))
9384 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
9385 reg_names
[SMALL_DATA_REG
]);
9390 /* MB value for a mask operand. */
9391 if (! mask_operand (x
, SImode
))
9392 output_operand_lossage ("invalid %%m value");
9394 fprintf (file
, "%d", extract_MB (x
));
9398 /* ME value for a mask operand. */
9399 if (! mask_operand (x
, SImode
))
9400 output_operand_lossage ("invalid %%M value");
9402 fprintf (file
, "%d", extract_ME (x
));
9405 /* %n outputs the negative of its operand. */
9408 /* Write the number of elements in the vector times 4. */
9409 if (GET_CODE (x
) != PARALLEL
)
9410 output_operand_lossage ("invalid %%N value");
9412 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
9416 /* Similar, but subtract 1 first. */
9417 if (GET_CODE (x
) != PARALLEL
)
9418 output_operand_lossage ("invalid %%O value");
9420 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
9424 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9426 || INT_LOWPART (x
) < 0
9427 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
9428 output_operand_lossage ("invalid %%p value");
9430 fprintf (file
, "%d", i
);
9434 /* The operand must be an indirect memory reference. The result
9435 is the register name. */
9436 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
9437 || REGNO (XEXP (x
, 0)) >= 32)
9438 output_operand_lossage ("invalid %%P value");
9440 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
9444 /* This outputs the logical code corresponding to a boolean
9445 expression. The expression may have one or both operands
9446 negated (if one, only the first one). For condition register
9447 logical operations, it will also treat the negated
9448 CR codes as NOTs, but not handle NOTs of them. */
9450 const char *const *t
= 0;
9452 enum rtx_code code
= GET_CODE (x
);
9453 static const char * const tbl
[3][3] = {
9454 { "and", "andc", "nor" },
9455 { "or", "orc", "nand" },
9456 { "xor", "eqv", "xor" } };
9460 else if (code
== IOR
)
9462 else if (code
== XOR
)
9465 output_operand_lossage ("invalid %%q value");
9467 if (GET_CODE (XEXP (x
, 0)) != NOT
)
9471 if (GET_CODE (XEXP (x
, 1)) == NOT
)
9489 /* X is a CR register. Print the mask for `mtcrf'. */
9490 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
9491 output_operand_lossage ("invalid %%R value");
9493 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
9497 /* Low 5 bits of 32 - value */
9499 output_operand_lossage ("invalid %%s value");
9501 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
9505 /* PowerPC64 mask position. All 0's is excluded.
9506 CONST_INT 32-bit mask is considered sign-extended so any
9507 transition must occur within the CONST_INT, not on the boundary. */
9508 if (! mask64_operand (x
, DImode
))
9509 output_operand_lossage ("invalid %%S value");
9511 uval
= INT_LOWPART (x
);
9513 if (uval
& 1) /* Clear Left */
9515 #if HOST_BITS_PER_WIDE_INT > 64
9516 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
9520 else /* Clear Right */
9523 #if HOST_BITS_PER_WIDE_INT > 64
9524 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
9532 fprintf (file
, "%d", i
);
9536 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9537 if (GET_CODE (x
) != REG
|| GET_MODE (x
) != CCmode
)
9540 /* Bit 3 is OV bit. */
9541 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
9543 /* If we want bit 31, write a shift count of zero, not 32. */
9544 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
9548 /* Print the symbolic name of a branch target register. */
9549 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LINK_REGISTER_REGNUM
9550 && REGNO (x
) != COUNT_REGISTER_REGNUM
))
9551 output_operand_lossage ("invalid %%T value");
9552 else if (REGNO (x
) == LINK_REGISTER_REGNUM
)
9553 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
9555 fputs ("ctr", file
);
9559 /* High-order 16 bits of constant for use in unsigned operand. */
9561 output_operand_lossage ("invalid %%u value");
9563 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
9564 (INT_LOWPART (x
) >> 16) & 0xffff);
9568 /* High-order 16 bits of constant for use in signed operand. */
9570 output_operand_lossage ("invalid %%v value");
9572 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
9573 (INT_LOWPART (x
) >> 16) & 0xffff);
9577 /* Print `u' if this has an auto-increment or auto-decrement. */
9578 if (GET_CODE (x
) == MEM
9579 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
9580 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
9585 /* Print the trap code for this operand. */
9586 switch (GET_CODE (x
))
9589 fputs ("eq", file
); /* 4 */
9592 fputs ("ne", file
); /* 24 */
9595 fputs ("lt", file
); /* 16 */
9598 fputs ("le", file
); /* 20 */
9601 fputs ("gt", file
); /* 8 */
9604 fputs ("ge", file
); /* 12 */
9607 fputs ("llt", file
); /* 2 */
9610 fputs ("lle", file
); /* 6 */
9613 fputs ("lgt", file
); /* 1 */
9616 fputs ("lge", file
); /* 5 */
9624 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9627 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
9628 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
9630 print_operand (file
, x
, 0);
9634 /* MB value for a PowerPC64 rldic operand. */
9635 val
= (GET_CODE (x
) == CONST_INT
9636 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
9641 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
9642 if ((val
<<= 1) < 0)
9645 #if HOST_BITS_PER_WIDE_INT == 32
9646 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
9647 i
+= 32; /* zero-extend high-part was all 0's */
9648 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
9650 val
= CONST_DOUBLE_LOW (x
);
9657 for ( ; i
< 64; i
++)
9658 if ((val
<<= 1) < 0)
9663 fprintf (file
, "%d", i
+ 1);
9667 if (GET_CODE (x
) == MEM
9668 && legitimate_indexed_address_p (XEXP (x
, 0), 0))
9673 /* Like 'L', for third word of TImode */
9674 if (GET_CODE (x
) == REG
)
9675 fputs (reg_names
[REGNO (x
) + 2], file
);
9676 else if (GET_CODE (x
) == MEM
)
9678 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
9679 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
9680 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
9682 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
9683 if (small_data_operand (x
, GET_MODE (x
)))
9684 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
9685 reg_names
[SMALL_DATA_REG
]);
9690 /* X is a SYMBOL_REF. Write out the name preceded by a
9691 period and without any trailing data in brackets. Used for function
9692 names. If we are configured for System V (or the embedded ABI) on
9693 the PowerPC, do not emit the period, since those systems do not use
9694 TOCs and the like. */
9695 if (GET_CODE (x
) != SYMBOL_REF
)
9698 /* Mark the decl as referenced so that cgraph will output the
9700 if (SYMBOL_REF_DECL (x
))
9701 mark_decl_referenced (SYMBOL_REF_DECL (x
));
9703 /* For macho, check to see if we need a stub. */
9706 const char *name
= XSTR (x
, 0);
9708 if (MACHOPIC_INDIRECT
9709 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
9710 name
= machopic_indirection_name (x
, /*stub_p=*/true);
9712 assemble_name (file
, name
);
9714 else if (!DOT_SYMBOLS
)
9715 assemble_name (file
, XSTR (x
, 0));
9717 rs6000_output_function_entry (file
, XSTR (x
, 0));
9721 /* Like 'L', for last word of TImode. */
9722 if (GET_CODE (x
) == REG
)
9723 fputs (reg_names
[REGNO (x
) + 3], file
);
9724 else if (GET_CODE (x
) == MEM
)
9726 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
9727 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
9728 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
9730 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
9731 if (small_data_operand (x
, GET_MODE (x
)))
9732 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
9733 reg_names
[SMALL_DATA_REG
]);
9737 /* Print AltiVec or SPE memory operand. */
9742 if (GET_CODE (x
) != MEM
)
9750 if (GET_CODE (tmp
) == REG
)
9752 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
9755 /* Handle [reg+UIMM]. */
9756 else if (GET_CODE (tmp
) == PLUS
&&
9757 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
9761 if (GET_CODE (XEXP (tmp
, 0)) != REG
)
9764 x
= INTVAL (XEXP (tmp
, 1));
9765 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
9769 /* Fall through. Must be [reg+reg]. */
9772 && GET_CODE (tmp
) == AND
9773 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
9774 && INTVAL (XEXP (tmp
, 1)) == -16)
9775 tmp
= XEXP (tmp
, 0);
9776 if (GET_CODE (tmp
) == REG
)
9777 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
9778 else if (GET_CODE (tmp
) == PLUS
&& GET_CODE (XEXP (tmp
, 1)) == REG
)
9780 if (REGNO (XEXP (tmp
, 0)) == 0)
9781 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
9782 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
9784 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
9785 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
9793 if (GET_CODE (x
) == REG
)
9794 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
9795 else if (GET_CODE (x
) == MEM
)
9797 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9798 know the width from the mode. */
9799 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
9800 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
9801 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
9802 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
9803 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
9804 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
9806 output_address (XEXP (x
, 0));
9809 output_addr_const (file
, x
);
9813 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
9817 output_operand_lossage ("invalid %%xn code");
9821 /* Print the address of an operand. */
9824 print_operand_address (FILE *file
, rtx x
)
9826 if (GET_CODE (x
) == REG
)
9827 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
9828 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
9829 || GET_CODE (x
) == LABEL_REF
)
9831 output_addr_const (file
, x
);
9832 if (small_data_operand (x
, GET_MODE (x
)))
9833 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
9834 reg_names
[SMALL_DATA_REG
]);
9835 else if (TARGET_TOC
)
9838 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
9840 if (REGNO (XEXP (x
, 0)) == 0)
9841 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
9842 reg_names
[ REGNO (XEXP (x
, 0)) ]);
9844 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
9845 reg_names
[ REGNO (XEXP (x
, 1)) ]);
9847 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9848 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
9849 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
9851 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
9852 && CONSTANT_P (XEXP (x
, 1)))
9854 output_addr_const (file
, XEXP (x
, 1));
9855 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
9859 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
9860 && CONSTANT_P (XEXP (x
, 1)))
9862 fprintf (file
, "lo16(");
9863 output_addr_const (file
, XEXP (x
, 1));
9864 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
9867 else if (legitimate_constant_pool_address_p (x
))
9869 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
9871 rtx contains_minus
= XEXP (x
, 1);
9875 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9876 turn it into (sym) for output_addr_const. */
9877 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
9878 contains_minus
= XEXP (contains_minus
, 0);
9880 minus
= XEXP (contains_minus
, 0);
9881 symref
= XEXP (minus
, 0);
9882 XEXP (contains_minus
, 0) = symref
;
9887 name
= XSTR (symref
, 0);
9888 newname
= alloca (strlen (name
) + sizeof ("@toc"));
9889 strcpy (newname
, name
);
9890 strcat (newname
, "@toc");
9891 XSTR (symref
, 0) = newname
;
9893 output_addr_const (file
, XEXP (x
, 1));
9895 XSTR (symref
, 0) = name
;
9896 XEXP (contains_minus
, 0) = minus
;
9899 output_addr_const (file
, XEXP (x
, 1));
9901 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
9907 /* Target hook for assembling integer objects. The PowerPC version has
9908 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9909 is defined. It also needs to handle DI-mode objects on 64-bit
9913 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9915 #ifdef RELOCATABLE_NEEDS_FIXUP
9916 /* Special handling for SI values. */
9917 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
9919 extern int in_toc_section (void);
9920 static int recurse
= 0;
9922 /* For -mrelocatable, we mark all addresses that need to be fixed up
9923 in the .fixup section. */
9924 if (TARGET_RELOCATABLE
9925 && !in_toc_section ()
9926 && !in_text_section ()
9927 && !in_unlikely_text_section ()
9929 && GET_CODE (x
) != CONST_INT
9930 && GET_CODE (x
) != CONST_DOUBLE
9936 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
9938 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
9939 fprintf (asm_out_file
, "\t.long\t(");
9940 output_addr_const (asm_out_file
, x
);
9941 fprintf (asm_out_file
, ")@fixup\n");
9942 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
9943 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
9944 fprintf (asm_out_file
, "\t.long\t");
9945 assemble_name (asm_out_file
, buf
);
9946 fprintf (asm_out_file
, "\n\t.previous\n");
9950 /* Remove initial .'s to turn a -mcall-aixdesc function
9951 address into the address of the descriptor, not the function
9953 else if (GET_CODE (x
) == SYMBOL_REF
9954 && XSTR (x
, 0)[0] == '.'
9955 && DEFAULT_ABI
== ABI_AIX
)
9957 const char *name
= XSTR (x
, 0);
9958 while (*name
== '.')
9961 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
9965 #endif /* RELOCATABLE_NEEDS_FIXUP */
9966 return default_assemble_integer (x
, size
, aligned_p
);
9969 #ifdef HAVE_GAS_HIDDEN
9970 /* Emit an assembler directive to set symbol visibility for DECL to
9974 rs6000_assemble_visibility (tree decl
, int vis
)
9976 /* Functions need to have their entry point symbol visibility set as
9977 well as their descriptor symbol visibility. */
9978 if (DEFAULT_ABI
== ABI_AIX
9980 && TREE_CODE (decl
) == FUNCTION_DECL
)
9982 static const char * const visibility_types
[] = {
9983 NULL
, "internal", "hidden", "protected"
9986 const char *name
, *type
;
9988 name
= ((* targetm
.strip_name_encoding
)
9989 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
9990 type
= visibility_types
[vis
];
9992 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
9993 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
9996 default_assemble_visibility (decl
, vis
);
10001 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
10003 /* Reversal of FP compares takes care -- an ordered compare
10004 becomes an unordered compare and vice versa. */
10005 if (mode
== CCFPmode
10006 && (!flag_finite_math_only
10007 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
10008 || code
== UNEQ
|| code
== LTGT
))
10009 return reverse_condition_maybe_unordered (code
);
10011 return reverse_condition (code
);
10014 /* Generate a compare for CODE. Return a brand-new rtx that
10015 represents the result of the compare. */
10018 rs6000_generate_compare (enum rtx_code code
)
10020 enum machine_mode comp_mode
;
10021 rtx compare_result
;
10023 if (rs6000_compare_fp_p
)
10024 comp_mode
= CCFPmode
;
10025 else if (code
== GTU
|| code
== LTU
10026 || code
== GEU
|| code
== LEU
)
10027 comp_mode
= CCUNSmode
;
10028 else if ((code
== EQ
|| code
== NE
)
10029 && GET_CODE (rs6000_compare_op0
) == SUBREG
10030 && GET_CODE (rs6000_compare_op1
) == SUBREG
10031 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
10032 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
10033 /* These are unsigned values, perhaps there will be a later
10034 ordering compare that can be shared with this one.
10035 Unfortunately we cannot detect the signedness of the operands
10036 for non-subregs. */
10037 comp_mode
= CCUNSmode
;
10039 comp_mode
= CCmode
;
10041 /* First, the compare. */
10042 compare_result
= gen_reg_rtx (comp_mode
);
10044 /* SPE FP compare instructions on the GPRs. Yuck! */
10045 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
10046 && rs6000_compare_fp_p
)
10048 rtx cmp
, or_result
, compare_result2
;
10049 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
10051 if (op_mode
== VOIDmode
)
10052 op_mode
= GET_MODE (rs6000_compare_op1
);
10054 /* Note: The E500 comparison instructions set the GT bit (x +
10055 1), on success. This explains the mess. */
10059 case EQ
: case UNEQ
: case NE
: case LTGT
:
10060 if (op_mode
== SFmode
)
10061 cmp
= flag_unsafe_math_optimizations
10062 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
10063 rs6000_compare_op1
)
10064 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
10065 rs6000_compare_op1
);
10066 else if (op_mode
== DFmode
)
10067 cmp
= flag_unsafe_math_optimizations
10068 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
10069 rs6000_compare_op1
)
10070 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
10071 rs6000_compare_op1
);
10074 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
10075 if (op_mode
== SFmode
)
10076 cmp
= flag_unsafe_math_optimizations
10077 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
10078 rs6000_compare_op1
)
10079 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
10080 rs6000_compare_op1
);
10081 else if (op_mode
== DFmode
)
10082 cmp
= flag_unsafe_math_optimizations
10083 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
10084 rs6000_compare_op1
)
10085 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
10086 rs6000_compare_op1
);
10089 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
10090 if (op_mode
== SFmode
)
10091 cmp
= flag_unsafe_math_optimizations
10092 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
10093 rs6000_compare_op1
)
10094 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
10095 rs6000_compare_op1
);
10096 else if (op_mode
== DFmode
)
10097 cmp
= flag_unsafe_math_optimizations
10098 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
10099 rs6000_compare_op1
)
10100 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
10101 rs6000_compare_op1
);
10108 /* Synthesize LE and GE from LT/GT || EQ. */
10109 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
10115 case LE
: code
= LT
; break;
10116 case GE
: code
= GT
; break;
10117 case LEU
: code
= LT
; break;
10118 case GEU
: code
= GT
; break;
10122 compare_result2
= gen_reg_rtx (CCFPmode
);
10125 if (op_mode
== SFmode
)
10126 cmp
= flag_unsafe_math_optimizations
10127 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
10128 rs6000_compare_op1
)
10129 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
10130 rs6000_compare_op1
);
10131 else if (op_mode
== DFmode
)
10132 cmp
= flag_unsafe_math_optimizations
10133 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
10134 rs6000_compare_op1
)
10135 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
10136 rs6000_compare_op1
);
10140 /* OR them together. */
10141 or_result
= gen_reg_rtx (CCFPmode
);
10142 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
10144 compare_result
= or_result
;
10149 if (code
== NE
|| code
== LTGT
)
10159 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10160 CLOBBERs to match cmptf_internal2 pattern. */
10161 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
10162 && GET_MODE (rs6000_compare_op0
) == TFmode
10163 && (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_DARWIN
)
10164 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
10165 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
10167 gen_rtx_SET (VOIDmode
,
10169 gen_rtx_COMPARE (comp_mode
,
10170 rs6000_compare_op0
,
10171 rs6000_compare_op1
)),
10172 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10173 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10174 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10175 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10176 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10177 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10178 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
10179 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
10181 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
10182 gen_rtx_COMPARE (comp_mode
,
10183 rs6000_compare_op0
,
10184 rs6000_compare_op1
)));
10187 /* Some kinds of FP comparisons need an OR operation;
10188 under flag_finite_math_only we don't bother. */
10189 if (rs6000_compare_fp_p
10190 && !flag_finite_math_only
10191 && !(TARGET_HARD_FLOAT
&& TARGET_E500
&& !TARGET_FPRS
)
10192 && (code
== LE
|| code
== GE
10193 || code
== UNEQ
|| code
== LTGT
10194 || code
== UNGT
|| code
== UNLT
))
10196 enum rtx_code or1
, or2
;
10197 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
10198 rtx or_result
= gen_reg_rtx (CCEQmode
);
10202 case LE
: or1
= LT
; or2
= EQ
; break;
10203 case GE
: or1
= GT
; or2
= EQ
; break;
10204 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
10205 case LTGT
: or1
= LT
; or2
= GT
; break;
10206 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
10207 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
10210 validate_condition_mode (or1
, comp_mode
);
10211 validate_condition_mode (or2
, comp_mode
);
10212 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
10213 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
10214 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
10215 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
10217 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
10219 compare_result
= or_result
;
10223 validate_condition_mode (code
, GET_MODE (compare_result
));
10225 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
10229 /* Emit the RTL for an sCOND pattern. */
10232 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
10235 enum machine_mode op_mode
;
10236 enum rtx_code cond_code
;
10238 condition_rtx
= rs6000_generate_compare (code
);
10239 cond_code
= GET_CODE (condition_rtx
);
10241 if (TARGET_E500
&& rs6000_compare_fp_p
10242 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
10246 PUT_MODE (condition_rtx
, SImode
);
10247 t
= XEXP (condition_rtx
, 0);
10249 if (cond_code
!= NE
&& cond_code
!= EQ
)
10252 if (cond_code
== NE
)
10253 emit_insn (gen_e500_flip_gt_bit (t
, t
));
10255 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
10259 if (cond_code
== NE
10260 || cond_code
== GE
|| cond_code
== LE
10261 || cond_code
== GEU
|| cond_code
== LEU
10262 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
10264 rtx not_result
= gen_reg_rtx (CCEQmode
);
10265 rtx not_op
, rev_cond_rtx
;
10266 enum machine_mode cc_mode
;
10268 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
10270 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
10271 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
10272 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
10273 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
10274 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
10277 op_mode
= GET_MODE (rs6000_compare_op0
);
10278 if (op_mode
== VOIDmode
)
10279 op_mode
= GET_MODE (rs6000_compare_op1
);
10281 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
10283 PUT_MODE (condition_rtx
, DImode
);
10284 convert_move (result
, condition_rtx
, 0);
10288 PUT_MODE (condition_rtx
, SImode
);
10289 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
10293 /* Emit a branch of kind CODE to location LOC. */
10296 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
10298 rtx condition_rtx
, loc_ref
;
10300 condition_rtx
= rs6000_generate_compare (code
);
10301 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
10302 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
10303 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
10304 loc_ref
, pc_rtx
)));
10307 /* Return the string to output a conditional branch to LABEL, which is
10308 the operand number of the label, or -1 if the branch is really a
10309 conditional return.
10311 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10312 condition code register and its mode specifies what kind of
10313 comparison we made.
10315 REVERSED is nonzero if we should reverse the sense of the comparison.
10317 INSN is the insn. */
10320 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
10322 static char string
[64];
10323 enum rtx_code code
= GET_CODE (op
);
10324 rtx cc_reg
= XEXP (op
, 0);
10325 enum machine_mode mode
= GET_MODE (cc_reg
);
10326 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
10327 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
10328 int really_reversed
= reversed
^ need_longbranch
;
10334 validate_condition_mode (code
, mode
);
10336 /* Work out which way this really branches. We could use
10337 reverse_condition_maybe_unordered here always but this
10338 makes the resulting assembler clearer. */
10339 if (really_reversed
)
10341 /* Reversal of FP compares takes care -- an ordered compare
10342 becomes an unordered compare and vice versa. */
10343 if (mode
== CCFPmode
)
10344 code
= reverse_condition_maybe_unordered (code
);
10346 code
= reverse_condition (code
);
10349 if ((TARGET_E500
&& !TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
10351 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10354 /* Opposite of GT. */
10356 else if (code
== NE
)
10364 /* Not all of these are actually distinct opcodes, but
10365 we distinguish them for clarity of the resulting assembler. */
10366 case NE
: case LTGT
:
10367 ccode
= "ne"; break;
10368 case EQ
: case UNEQ
:
10369 ccode
= "eq"; break;
10371 ccode
= "ge"; break;
10372 case GT
: case GTU
: case UNGT
:
10373 ccode
= "gt"; break;
10375 ccode
= "le"; break;
10376 case LT
: case LTU
: case UNLT
:
10377 ccode
= "lt"; break;
10378 case UNORDERED
: ccode
= "un"; break;
10379 case ORDERED
: ccode
= "nu"; break;
10380 case UNGE
: ccode
= "nl"; break;
10381 case UNLE
: ccode
= "ng"; break;
10386 /* Maybe we have a guess as to how likely the branch is.
10387 The old mnemonics don't have a way to specify this information. */
10389 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
10390 if (note
!= NULL_RTX
)
10392 /* PROB is the difference from 50%. */
10393 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
10395 /* Only hint for highly probable/improbable branches on newer
10396 cpus as static prediction overrides processor dynamic
10397 prediction. For older cpus we may as well always hint, but
10398 assume not taken for branches that are very close to 50% as a
10399 mispredicted taken branch is more expensive than a
10400 mispredicted not-taken branch. */
10401 if (rs6000_always_hint
10402 || abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48)
10404 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
10405 && ((prob
> 0) ^ need_longbranch
))
10413 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
10415 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
10417 /* We need to escape any '%' characters in the reg_names string.
10418 Assume they'd only be the first character.... */
10419 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
10421 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
10425 /* If the branch distance was too far, we may have to use an
10426 unconditional branch to go the distance. */
10427 if (need_longbranch
)
10428 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
10430 s
+= sprintf (s
, ",%s", label
);
10436 /* Return the string to flip the GT bit on a CR. */
10438 output_e500_flip_gt_bit (rtx dst
, rtx src
)
10440 static char string
[64];
10443 if (GET_CODE (dst
) != REG
|| ! CR_REGNO_P (REGNO (dst
))
10444 || GET_CODE (src
) != REG
|| ! CR_REGNO_P (REGNO (src
)))
10448 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
10449 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
10451 sprintf (string
, "crnot %d,%d", a
, b
);
10455 /* Return insn index for the vector compare instruction for given CODE,
10456 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10460 get_vec_cmp_insn (enum rtx_code code
,
10461 enum machine_mode dest_mode
,
10462 enum machine_mode op_mode
)
10464 if (!TARGET_ALTIVEC
)
10465 return INSN_NOT_AVAILABLE
;
10470 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
10471 return UNSPEC_VCMPEQUB
;
10472 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
10473 return UNSPEC_VCMPEQUH
;
10474 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
10475 return UNSPEC_VCMPEQUW
;
10476 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
10477 return UNSPEC_VCMPEQFP
;
10480 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
10481 return UNSPEC_VCMPGEFP
;
10483 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
10484 return UNSPEC_VCMPGTSB
;
10485 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
10486 return UNSPEC_VCMPGTSH
;
10487 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
10488 return UNSPEC_VCMPGTSW
;
10489 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
10490 return UNSPEC_VCMPGTFP
;
10493 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
10494 return UNSPEC_VCMPGTUB
;
10495 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
10496 return UNSPEC_VCMPGTUH
;
10497 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
10498 return UNSPEC_VCMPGTUW
;
10503 return INSN_NOT_AVAILABLE
;
10506 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
10507 DMODE is expected destination mode. This is a recursive function. */
10510 rs6000_emit_vector_compare (enum rtx_code rcode
,
10512 enum machine_mode dmode
)
10516 enum machine_mode dest_mode
;
10517 enum machine_mode op_mode
= GET_MODE (op1
);
10519 #ifdef ENABLE_CHECKING
10520 if (!TARGET_ALTIVEC
)
10523 if (GET_MODE (op0
) != GET_MODE (op1
))
10527 /* Floating point vector compare instructions uses destination V4SImode.
10528 Move destination to appropriate mode later. */
10529 if (dmode
== V4SFmode
)
10530 dest_mode
= V4SImode
;
10534 mask
= gen_reg_rtx (dest_mode
);
10535 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
10537 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
10539 bool swap_operands
= false;
10540 bool try_again
= false;
10545 swap_operands
= true;
10550 swap_operands
= true;
10554 /* Treat A != B as ~(A==B). */
10556 enum insn_code nor_code
;
10557 rtx eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
10560 nor_code
= one_cmpl_optab
->handlers
[(int)dest_mode
].insn_code
;
10561 if (nor_code
== CODE_FOR_nothing
)
10563 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
10565 if (dmode
!= dest_mode
)
10567 rtx temp
= gen_reg_rtx (dest_mode
);
10568 convert_move (temp
, mask
, 0);
10578 /* Try GT/GTU/LT/LTU OR EQ */
10581 enum insn_code ior_code
;
10582 enum rtx_code new_code
;
10586 else if (rcode
== GEU
)
10588 else if (rcode
== LE
)
10590 else if (rcode
== LEU
)
10595 c_rtx
= rs6000_emit_vector_compare (new_code
,
10596 op0
, op1
, dest_mode
);
10597 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
10600 ior_code
= ior_optab
->handlers
[(int)dest_mode
].insn_code
;
10601 if (ior_code
== CODE_FOR_nothing
)
10603 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
10604 if (dmode
!= dest_mode
)
10606 rtx temp
= gen_reg_rtx (dest_mode
);
10607 convert_move (temp
, mask
, 0);
10619 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
10620 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
10621 /* You only get two chances. */
10634 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10635 gen_rtx_UNSPEC (dest_mode
,
10636 gen_rtvec (2, op0
, op1
),
10638 if (dmode
!= dest_mode
)
10640 rtx temp
= gen_reg_rtx (dest_mode
);
10641 convert_move (temp
, mask
, 0);
10647 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10648 valid insn doesn exist for given mode. */
10651 get_vsel_insn (enum machine_mode mode
)
10656 return UNSPEC_VSEL4SI
;
10659 return UNSPEC_VSEL4SF
;
10662 return UNSPEC_VSEL8HI
;
10665 return UNSPEC_VSEL16QI
;
10668 return INSN_NOT_AVAILABLE
;
10671 return INSN_NOT_AVAILABLE
;
10674 /* Emit vector select insn where DEST is destination using
10675 operands OP1, OP2 and MASK. */
10678 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
10681 enum machine_mode dest_mode
= GET_MODE (dest
);
10682 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
10684 temp
= gen_reg_rtx (dest_mode
);
10686 /* For each vector element, select op1 when mask is 1 otherwise
10688 t
= gen_rtx_SET (VOIDmode
, temp
,
10689 gen_rtx_UNSPEC (dest_mode
,
10690 gen_rtvec (3, op2
, op1
, mask
),
10693 emit_move_insn (dest
, temp
);
10697 /* Emit vector conditional expression.
10698 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10699 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10702 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
10703 rtx cond
, rtx cc_op0
, rtx cc_op1
)
10705 enum machine_mode dest_mode
= GET_MODE (dest
);
10706 enum rtx_code rcode
= GET_CODE (cond
);
10709 if (!TARGET_ALTIVEC
)
10712 /* Get the vector mask for the given relational operations. */
10713 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
10715 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
10720 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10721 operands of the last comparison is nonzero/true, FALSE_COND if it
10722 is zero/false. Return 0 if the hardware has no such operation. */
10725 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
10727 enum rtx_code code
= GET_CODE (op
);
10728 rtx op0
= rs6000_compare_op0
;
10729 rtx op1
= rs6000_compare_op1
;
10730 REAL_VALUE_TYPE c1
;
10731 enum machine_mode compare_mode
= GET_MODE (op0
);
10732 enum machine_mode result_mode
= GET_MODE (dest
);
10734 bool is_against_zero
;
10736 /* These modes should always match. */
10737 if (GET_MODE (op1
) != compare_mode
10738 /* In the isel case however, we can use a compare immediate, so
10739 op1 may be a small constant. */
10740 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
10742 if (GET_MODE (true_cond
) != result_mode
)
10744 if (GET_MODE (false_cond
) != result_mode
)
10747 /* First, work out if the hardware can do this at all, or
10748 if it's too slow.... */
10749 if (! rs6000_compare_fp_p
)
10752 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
10755 else if (TARGET_E500
&& TARGET_HARD_FLOAT
&& !TARGET_FPRS
10756 && GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
)
10759 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
10761 /* A floating-point subtract might overflow, underflow, or produce
10762 an inexact result, thus changing the floating-point flags, so it
10763 can't be generated if we care about that. It's safe if one side
10764 of the construct is zero, since then no subtract will be
10766 if (GET_MODE_CLASS (compare_mode
) == MODE_FLOAT
10767 && flag_trapping_math
&& ! is_against_zero
)
10770 /* Eliminate half of the comparisons by switching operands, this
10771 makes the remaining code simpler. */
10772 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
10773 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
10775 code
= reverse_condition_maybe_unordered (code
);
10777 true_cond
= false_cond
;
10781 /* UNEQ and LTGT take four instructions for a comparison with zero,
10782 it'll probably be faster to use a branch here too. */
10783 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
10786 if (GET_CODE (op1
) == CONST_DOUBLE
)
10787 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
10789 /* We're going to try to implement comparisons by performing
10790 a subtract, then comparing against zero. Unfortunately,
10791 Inf - Inf is NaN which is not zero, and so if we don't
10792 know that the operand is finite and the comparison
10793 would treat EQ different to UNORDERED, we can't do it. */
10794 if (HONOR_INFINITIES (compare_mode
)
10795 && code
!= GT
&& code
!= UNGE
10796 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
10797 /* Constructs of the form (a OP b ? a : b) are safe. */
10798 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
10799 || (! rtx_equal_p (op0
, true_cond
)
10800 && ! rtx_equal_p (op1
, true_cond
))))
10803 /* At this point we know we can use fsel. */
10805 /* Reduce the comparison to a comparison against zero. */
10806 if (! is_against_zero
)
10808 temp
= gen_reg_rtx (compare_mode
);
10809 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
10810 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
10812 op1
= CONST0_RTX (compare_mode
);
10815 /* If we don't care about NaNs we can reduce some of the comparisons
10816 down to faster ones. */
10817 if (! HONOR_NANS (compare_mode
))
10823 true_cond
= false_cond
;
10836 /* Now, reduce everything down to a GE. */
10843 temp
= gen_reg_rtx (compare_mode
);
10844 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
10849 temp
= gen_reg_rtx (compare_mode
);
10850 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
10855 temp
= gen_reg_rtx (compare_mode
);
10856 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
10857 gen_rtx_NEG (compare_mode
,
10858 gen_rtx_ABS (compare_mode
, op0
))));
10863 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10864 temp
= gen_reg_rtx (result_mode
);
10865 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
10866 gen_rtx_IF_THEN_ELSE (result_mode
,
10867 gen_rtx_GE (VOIDmode
,
10869 true_cond
, false_cond
)));
10870 false_cond
= true_cond
;
10873 temp
= gen_reg_rtx (compare_mode
);
10874 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
10879 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10880 temp
= gen_reg_rtx (result_mode
);
10881 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
10882 gen_rtx_IF_THEN_ELSE (result_mode
,
10883 gen_rtx_GE (VOIDmode
,
10885 true_cond
, false_cond
)));
10886 true_cond
= false_cond
;
10889 temp
= gen_reg_rtx (compare_mode
);
10890 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
10898 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
10899 gen_rtx_IF_THEN_ELSE (result_mode
,
10900 gen_rtx_GE (VOIDmode
,
10902 true_cond
, false_cond
)));
10906 /* Same as above, but for ints (isel). */
10909 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
10911 rtx condition_rtx
, cr
;
10913 /* All isel implementations thus far are 32-bits. */
10914 if (GET_MODE (rs6000_compare_op0
) != SImode
)
10917 /* We still have to do the compare, because isel doesn't do a
10918 compare, it just looks at the CRx bits set by a previous compare
10920 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
10921 cr
= XEXP (condition_rtx
, 0);
10923 if (GET_MODE (cr
) == CCmode
)
10924 emit_insn (gen_isel_signed (dest
, condition_rtx
,
10925 true_cond
, false_cond
, cr
));
10927 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
10928 true_cond
, false_cond
, cr
));
10934 output_isel (rtx
*operands
)
10936 enum rtx_code code
;
10938 code
= GET_CODE (operands
[1]);
10939 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
10941 PUT_CODE (operands
[1], reverse_condition (code
));
10942 return "isel %0,%3,%2,%j1";
10945 return "isel %0,%2,%3,%j1";
10949 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
10951 enum machine_mode mode
= GET_MODE (op0
);
10955 if (code
== SMAX
|| code
== SMIN
)
10960 if (code
== SMAX
|| code
== UMAX
)
10961 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
10962 op0
, op1
, mode
, 0);
10964 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
10965 op1
, op0
, mode
, 0);
10966 if (target
== NULL_RTX
)
10968 if (target
!= dest
)
10969 emit_move_insn (dest
, target
);
10972 /* Emit instructions to perform a load-reserved/store-conditional operation.
10973 The operation performed is an atomic
10974 (set M (CODE:MODE M OP))
10975 If not NULL, BEFORE is atomically set to M before the operation, and
10976 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
10977 If SYNC_P then a memory barrier is emitted before the operation.
10978 Either OP or M may be wrapped in a NOT operation. */
10981 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
10982 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
10985 enum machine_mode used_mode
;
10986 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
10989 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
10990 rtx shift
= NULL_RTX
;
10993 emit_insn (gen_memory_barrier ());
10995 if (GET_CODE (m
) == NOT
)
10996 used_m
= XEXP (m
, 0);
11000 /* If this is smaller than SImode, we'll have to use SImode with
11002 if (mode
== QImode
|| mode
== HImode
)
11006 if (MEM_ALIGN (used_m
) >= 32)
11009 if (BYTES_BIG_ENDIAN
)
11010 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
11012 shift
= GEN_INT (ishift
);
11016 rtx addrSI
, aligned_addr
;
11018 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
,
11019 XEXP (used_m
, 0)));
11020 shift
= gen_reg_rtx (SImode
);
11022 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
11025 aligned_addr
= expand_binop (Pmode
, and_optab
,
11027 GEN_INT (-4), NULL_RTX
,
11028 1, OPTAB_LIB_WIDEN
);
11029 used_m
= change_address (used_m
, SImode
, aligned_addr
);
11030 set_mem_align (used_m
, 32);
11031 /* It's safe to keep the old alias set of USED_M, because
11032 the operation is atomic and only affects the original
11034 if (GET_CODE (m
) == NOT
)
11035 m
= gen_rtx_NOT (SImode
, used_m
);
11040 if (GET_CODE (op
) == NOT
)
11042 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
11043 oldop
= gen_rtx_NOT (SImode
, oldop
);
11046 oldop
= lowpart_subreg (SImode
, op
, mode
);
11051 newop
= expand_binop (SImode
, and_optab
,
11052 oldop
, GEN_INT (imask
), NULL_RTX
,
11053 1, OPTAB_LIB_WIDEN
);
11054 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
11058 newop
= expand_binop (SImode
, ior_optab
,
11059 oldop
, GEN_INT (~imask
), NULL_RTX
,
11060 1, OPTAB_LIB_WIDEN
);
11061 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
11068 newop
= expand_binop (SImode
, and_optab
,
11069 oldop
, GEN_INT (imask
), NULL_RTX
,
11070 1, OPTAB_LIB_WIDEN
);
11071 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
11073 mask
= gen_reg_rtx (SImode
);
11074 emit_move_insn (mask
, GEN_INT (imask
));
11075 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
11077 newop
= gen_rtx_AND (SImode
, gen_rtx_PLUS (SImode
, m
, newop
),
11079 newop
= gen_rtx_IOR (SImode
, newop
,
11080 gen_rtx_AND (SImode
,
11081 gen_rtx_NOT (SImode
, mask
),
11087 gcc_unreachable ();
11091 used_mode
= SImode
;
11092 before
= gen_reg_rtx (used_mode
);
11093 after
= gen_reg_rtx (used_mode
);
11098 before
= before_param
;
11099 after
= after_param
;
11101 if (before
== NULL_RTX
)
11102 before
= gen_reg_rtx (used_mode
);
11103 if (after
== NULL_RTX
)
11104 after
= gen_reg_rtx (used_mode
);
11107 if (code
== PLUS
&& used_mode
!= mode
)
11108 the_op
= op
; /* Computed above. */
11109 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
11110 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
11112 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
11114 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
11115 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
11116 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
11117 gen_rtx_UNSPEC (used_mode
, gen_rtvec (1, the_op
),
11119 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
11121 if (code
== PLUS
&& used_mode
!= mode
)
11122 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
11123 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
11125 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
11126 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
11128 /* Shift and mask the return values properly. */
11129 if (used_mode
!= mode
&& before_param
)
11131 emit_insn (gen_lshrsi3 (before
, before
, shift
));
11132 convert_move (before_param
, before
, 1);
11135 if (used_mode
!= mode
&& after_param
)
11137 emit_insn (gen_lshrsi3 (after
, after
, shift
));
11138 convert_move (after_param
, after
, 1);
11141 /* The previous sequence will end with a branch that's dependent on
11142 the conditional store, so placing an isync will ensure that no
11143 other instructions (especially, no load or store instructions)
11144 can start before the atomic operation completes. */
11146 emit_insn (gen_isync ());
11149 /* Emit instructions to move SRC to DST. Called by splitters for
11150 multi-register moves. It will emit at most one instruction for
11151 each register that is accessed; that is, it won't emit li/lis pairs
11152 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11156 rs6000_split_multireg_move (rtx dst
, rtx src
)
11158 /* The register number of the first register being moved. */
11160 /* The mode that is to be moved. */
11161 enum machine_mode mode
;
11162 /* The mode that the move is being done in, and its size. */
11163 enum machine_mode reg_mode
;
11165 /* The number of registers that will be moved. */
11168 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
11169 mode
= GET_MODE (dst
);
11170 nregs
= HARD_REGNO_NREGS (reg
, mode
);
11171 if (FP_REGNO_P (reg
))
11173 else if (ALTIVEC_REGNO_P (reg
))
11174 reg_mode
= V16QImode
;
11176 reg_mode
= word_mode
;
11177 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
11179 if (reg_mode_size
* nregs
!= GET_MODE_SIZE (mode
))
11182 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
11184 /* Move register range backwards, if we might have destructive
11187 for (i
= nregs
- 1; i
>= 0; i
--)
11188 emit_insn (gen_rtx_SET (VOIDmode
,
11189 simplify_gen_subreg (reg_mode
, dst
, mode
,
11190 i
* reg_mode_size
),
11191 simplify_gen_subreg (reg_mode
, src
, mode
,
11192 i
* reg_mode_size
)));
11198 bool used_update
= false;
11200 if (MEM_P (src
) && INT_REGNO_P (reg
))
11204 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
11205 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
11208 breg
= XEXP (XEXP (src
, 0), 0);
11209 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
11210 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
11211 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
11212 emit_insn (TARGET_32BIT
11213 ? gen_addsi3 (breg
, breg
, delta_rtx
)
11214 : gen_adddi3 (breg
, breg
, delta_rtx
));
11215 src
= gen_rtx_MEM (mode
, breg
);
11217 else if (! offsettable_memref_p (src
))
11219 rtx newsrc
, basereg
;
11220 basereg
= gen_rtx_REG (Pmode
, reg
);
11221 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
11222 newsrc
= gen_rtx_MEM (GET_MODE (src
), basereg
);
11223 MEM_COPY_ATTRIBUTES (newsrc
, src
);
11227 breg
= XEXP (src
, 0);
11228 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
11229 breg
= XEXP (breg
, 0);
11231 /* If the base register we are using to address memory is
11232 also a destination reg, then change that register last. */
11234 && REGNO (breg
) >= REGNO (dst
)
11235 && REGNO (breg
) < REGNO (dst
) + nregs
)
11236 j
= REGNO (breg
) - REGNO (dst
);
11239 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
11243 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
11244 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
11247 breg
= XEXP (XEXP (dst
, 0), 0);
11248 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
11249 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
11250 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
11252 /* We have to update the breg before doing the store.
11253 Use store with update, if available. */
11257 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
11258 emit_insn (TARGET_32BIT
11259 ? (TARGET_POWERPC64
11260 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
11261 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
11262 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
11263 used_update
= true;
11266 emit_insn (TARGET_32BIT
11267 ? gen_addsi3 (breg
, breg
, delta_rtx
)
11268 : gen_adddi3 (breg
, breg
, delta_rtx
));
11269 dst
= gen_rtx_MEM (mode
, breg
);
11271 else if (! offsettable_memref_p (dst
))
11275 for (i
= 0; i
< nregs
; i
++)
11277 /* Calculate index to next subword. */
11282 /* If compiler already emitted move of first word by
11283 store with update, no need to do anything. */
11284 if (j
== 0 && used_update
)
11287 emit_insn (gen_rtx_SET (VOIDmode
,
11288 simplify_gen_subreg (reg_mode
, dst
, mode
,
11289 j
* reg_mode_size
),
11290 simplify_gen_subreg (reg_mode
, src
, mode
,
11291 j
* reg_mode_size
)));
11297 /* This page contains routines that are used to determine what the
11298 function prologue and epilogue code will do and write them out. */
11300 /* Return the first fixed-point register that is required to be
11301 saved. 32 if none. */
11304 first_reg_to_save (void)
11308 /* Find lowest numbered live register. */
11309 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
11310 if (regs_ever_live
[first_reg
]
11311 && (! call_used_regs
[first_reg
]
11312 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
11313 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
11314 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
11315 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
11320 && current_function_uses_pic_offset_table
11321 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
11322 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
11328 /* Similar, for FP regs. */
11331 first_fp_reg_to_save (void)
11335 /* Find lowest numbered live register. */
11336 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
11337 if (regs_ever_live
[first_reg
])
11343 /* Similar, for AltiVec regs. */
11346 first_altivec_reg_to_save (void)
11350 /* Stack frame remains as is unless we are in AltiVec ABI. */
11351 if (! TARGET_ALTIVEC_ABI
)
11352 return LAST_ALTIVEC_REGNO
+ 1;
11354 /* Find lowest numbered live register. */
11355 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
11356 if (regs_ever_live
[i
])
11362 /* Return a 32-bit mask of the AltiVec registers we need to set in
11363 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11364 the 32-bit word is 0. */
11366 static unsigned int
11367 compute_vrsave_mask (void)
11369 unsigned int i
, mask
= 0;
11371 /* First, find out if we use _any_ altivec registers. */
11372 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
11373 if (regs_ever_live
[i
])
11374 mask
|= ALTIVEC_REG_BIT (i
);
11379 /* Next, remove the argument registers from the set. These must
11380 be in the VRSAVE mask set by the caller, so we don't need to add
11381 them in again. More importantly, the mask we compute here is
11382 used to generate CLOBBERs in the set_vrsave insn, and we do not
11383 wish the argument registers to die. */
11384 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
11385 mask
&= ~ALTIVEC_REG_BIT (i
);
11387 /* Similarly, remove the return value from the set. */
11390 diddle_return_value (is_altivec_return_reg
, &yes
);
11392 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
11398 /* For a very restricted set of circumstances, we can cut down the
11399 size of prologues/epilogues by calling our own save/restore-the-world
11403 compute_save_world_info (rs6000_stack_t
*info_ptr
)
11405 info_ptr
->world_save_p
= 1;
11406 info_ptr
->world_save_p
11407 = (WORLD_SAVE_P (info_ptr
)
11408 && DEFAULT_ABI
== ABI_DARWIN
11409 && ! (current_function_calls_setjmp
&& flag_exceptions
)
11410 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
11411 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
11412 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
11413 && info_ptr
->cr_save_p
);
11415 /* This will not work in conjunction with sibcalls. Make sure there
11416 are none. (This check is expensive, but seldom executed.) */
11417 if (WORLD_SAVE_P (info_ptr
))
11420 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
11421 if ( GET_CODE (insn
) == CALL_INSN
11422 && SIBLING_CALL_P (insn
))
11424 info_ptr
->world_save_p
= 0;
11429 if (WORLD_SAVE_P (info_ptr
))
11431 /* Even if we're not touching VRsave, make sure there's room on the
11432 stack for it, if it looks like we're calling SAVE_WORLD, which
11433 will attempt to save it. */
11434 info_ptr
->vrsave_size
= 4;
11436 /* "Save" the VRsave register too if we're saving the world. */
11437 if (info_ptr
->vrsave_mask
== 0)
11438 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
11440 /* Because the Darwin register save/restore routines only handle
11441 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11442 check and abort if there's something worng. */
11443 if (info_ptr
->first_fp_reg_save
< FIRST_SAVED_FP_REGNO
11444 || info_ptr
->first_altivec_reg_save
< FIRST_SAVED_ALTIVEC_REGNO
)
11452 is_altivec_return_reg (rtx reg
, void *xyes
)
11454 bool *yes
= (bool *) xyes
;
11455 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
11460 /* Calculate the stack information for the current function. This is
11461 complicated by having two separate calling sequences, the AIX calling
11462 sequence and the V.4 calling sequence.
11464 AIX (and Darwin/Mac OS X) stack frames look like:
11466 SP----> +---------------------------------------+
11467 | back chain to caller | 0 0
11468 +---------------------------------------+
11469 | saved CR | 4 8 (8-11)
11470 +---------------------------------------+
11472 +---------------------------------------+
11473 | reserved for compilers | 12 24
11474 +---------------------------------------+
11475 | reserved for binders | 16 32
11476 +---------------------------------------+
11477 | saved TOC pointer | 20 40
11478 +---------------------------------------+
11479 | Parameter save area (P) | 24 48
11480 +---------------------------------------+
11481 | Alloca space (A) | 24+P etc.
11482 +---------------------------------------+
11483 | Local variable space (L) | 24+P+A
11484 +---------------------------------------+
11485 | Float/int conversion temporary (X) | 24+P+A+L
11486 +---------------------------------------+
11487 | Save area for AltiVec registers (W) | 24+P+A+L+X
11488 +---------------------------------------+
11489 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11490 +---------------------------------------+
11491 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11492 +---------------------------------------+
11493 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11494 +---------------------------------------+
11495 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11496 +---------------------------------------+
11497 old SP->| back chain to caller's caller |
11498 +---------------------------------------+
11500 The required alignment for AIX configurations is two words (i.e., 8
11504 V.4 stack frames look like:
11506 SP----> +---------------------------------------+
11507 | back chain to caller | 0
11508 +---------------------------------------+
11509 | caller's saved LR | 4
11510 +---------------------------------------+
11511 | Parameter save area (P) | 8
11512 +---------------------------------------+
11513 | Alloca space (A) | 8+P
11514 +---------------------------------------+
11515 | Varargs save area (V) | 8+P+A
11516 +---------------------------------------+
11517 | Local variable space (L) | 8+P+A+V
11518 +---------------------------------------+
11519 | Float/int conversion temporary (X) | 8+P+A+V+L
11520 +---------------------------------------+
11521 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11522 +---------------------------------------+
11523 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11524 +---------------------------------------+
11525 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11526 +---------------------------------------+
11527 | SPE: area for 64-bit GP registers |
11528 +---------------------------------------+
11529 | SPE alignment padding |
11530 +---------------------------------------+
11531 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11532 +---------------------------------------+
11533 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11534 +---------------------------------------+
11535 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11536 +---------------------------------------+
11537 old SP->| back chain to caller's caller |
11538 +---------------------------------------+
11540 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11541 given. (But note below and in sysv4.h that we require only 8 and
11542 may round up the size of our stack frame anyways. The historical
11543 reason is early versions of powerpc-linux which didn't properly
11544 align the stack at program startup. A happy side-effect is that
11545 -mno-eabi libraries can be used with -meabi programs.)
11547 The EABI configuration defaults to the V.4 layout. However,
11548 the stack alignment requirements may differ. If -mno-eabi is not
11549 given, the required stack alignment is 8 bytes; if -mno-eabi is
11550 given, the required alignment is 16 bytes. (But see V.4 comment
11553 #ifndef ABI_STACK_BOUNDARY
11554 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11557 static rs6000_stack_t
*
11558 rs6000_stack_info (void)
11560 static rs6000_stack_t info
, zero_info
;
11561 rs6000_stack_t
*info_ptr
= &info
;
11562 int reg_size
= TARGET_32BIT
? 4 : 8;
11565 HOST_WIDE_INT non_fixed_size
;
11567 /* Zero all fields portably. */
11572 /* Cache value so we don't rescan instruction chain over and over. */
11573 if (cfun
->machine
->insn_chain_scanned_p
== 0)
11574 cfun
->machine
->insn_chain_scanned_p
11575 = spe_func_has_64bit_regs_p () + 1;
11576 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
11579 /* Select which calling sequence. */
11580 info_ptr
->abi
= DEFAULT_ABI
;
11582 /* Calculate which registers need to be saved & save area size. */
11583 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
11584 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11585 even if it currently looks like we won't. */
11586 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
11587 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
11588 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
11589 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
11590 info_ptr
->gp_size
= reg_size
* (32 - RS6000_PIC_OFFSET_TABLE_REGNUM
);
11592 info_ptr
->gp_size
= reg_size
* (32 - info_ptr
->first_gp_reg_save
);
11594 /* For the SPE, we have an additional upper 32-bits on each GPR.
11595 Ideally we should save the entire 64-bits only when the upper
11596 half is used in SIMD instructions. Since we only record
11597 registers live (not the size they are used in), this proves
11598 difficult because we'd have to traverse the instruction chain at
11599 the right time, taking reload into account. This is a real pain,
11600 so we opt to save the GPRs in 64-bits always if but one register
11601 gets used in 64-bits. Otherwise, all the registers in the frame
11602 get saved in 32-bits.
11604 So... since when we save all GPRs (except the SP) in 64-bits, the
11605 traditional GP save area will be empty. */
11606 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
11607 info_ptr
->gp_size
= 0;
11609 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
11610 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
11612 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
11613 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
11614 - info_ptr
->first_altivec_reg_save
);
11616 /* Does this function call anything? */
11617 info_ptr
->calls_p
= (! current_function_is_leaf
11618 || cfun
->machine
->ra_needs_full_frame
);
11620 /* Determine if we need to save the link register. */
11621 if (rs6000_ra_ever_killed ()
11622 || (DEFAULT_ABI
== ABI_AIX
11623 && current_function_profile
11624 && !TARGET_PROFILE_KERNEL
)
11625 #ifdef TARGET_RELOCATABLE
11626 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
11628 || (info_ptr
->first_fp_reg_save
!= 64
11629 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
11630 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
11631 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
11632 || (DEFAULT_ABI
== ABI_DARWIN
11634 && current_function_uses_pic_offset_table
)
11635 || info_ptr
->calls_p
)
11637 info_ptr
->lr_save_p
= 1;
11638 regs_ever_live
[LINK_REGISTER_REGNUM
] = 1;
11641 /* Determine if we need to save the condition code registers. */
11642 if (regs_ever_live
[CR2_REGNO
]
11643 || regs_ever_live
[CR3_REGNO
]
11644 || regs_ever_live
[CR4_REGNO
])
11646 info_ptr
->cr_save_p
= 1;
11647 if (DEFAULT_ABI
== ABI_V4
)
11648 info_ptr
->cr_size
= reg_size
;
11651 /* If the current function calls __builtin_eh_return, then we need
11652 to allocate stack space for registers that will hold data for
11653 the exception handler. */
11654 if (current_function_calls_eh_return
)
11657 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
11660 /* SPE saves EH registers in 64-bits. */
11661 ehrd_size
= i
* (TARGET_SPE_ABI
11662 && info_ptr
->spe_64bit_regs_used
!= 0
11663 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
11668 /* Determine various sizes. */
11669 info_ptr
->reg_size
= reg_size
;
11670 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
11671 info_ptr
->varargs_size
= RS6000_VARARGS_AREA
;
11672 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
11673 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
11674 TARGET_ALTIVEC
? 16 : 8);
11676 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
11677 info_ptr
->spe_gp_size
= 8 * (32 - info_ptr
->first_gp_reg_save
);
11679 info_ptr
->spe_gp_size
= 0;
11681 if (TARGET_ALTIVEC_ABI
)
11682 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
11684 info_ptr
->vrsave_mask
= 0;
11686 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
11687 info_ptr
->vrsave_size
= 4;
11689 info_ptr
->vrsave_size
= 0;
11691 compute_save_world_info (info_ptr
);
11693 /* Calculate the offsets. */
11694 switch (DEFAULT_ABI
)
11702 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
11703 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
11705 if (TARGET_ALTIVEC_ABI
)
11707 info_ptr
->vrsave_save_offset
11708 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
11710 /* Align stack so vector save area is on a quadword boundary. */
11711 if (info_ptr
->altivec_size
!= 0)
11712 info_ptr
->altivec_padding_size
11713 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
11715 info_ptr
->altivec_padding_size
= 0;
11717 info_ptr
->altivec_save_offset
11718 = info_ptr
->vrsave_save_offset
11719 - info_ptr
->altivec_padding_size
11720 - info_ptr
->altivec_size
;
11722 /* Adjust for AltiVec case. */
11723 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
11726 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
11727 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
11728 info_ptr
->lr_save_offset
= 2*reg_size
;
11732 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
11733 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
11734 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
11736 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
11738 /* Align stack so SPE GPR save area is aligned on a
11739 double-word boundary. */
11740 if (info_ptr
->spe_gp_size
!= 0)
11741 info_ptr
->spe_padding_size
11742 = 8 - (-info_ptr
->cr_save_offset
% 8);
11744 info_ptr
->spe_padding_size
= 0;
11746 info_ptr
->spe_gp_save_offset
11747 = info_ptr
->cr_save_offset
11748 - info_ptr
->spe_padding_size
11749 - info_ptr
->spe_gp_size
;
11751 /* Adjust for SPE case. */
11752 info_ptr
->toc_save_offset
11753 = info_ptr
->spe_gp_save_offset
- info_ptr
->toc_size
;
11755 else if (TARGET_ALTIVEC_ABI
)
11757 info_ptr
->vrsave_save_offset
11758 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
11760 /* Align stack so vector save area is on a quadword boundary. */
11761 if (info_ptr
->altivec_size
!= 0)
11762 info_ptr
->altivec_padding_size
11763 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
11765 info_ptr
->altivec_padding_size
= 0;
11767 info_ptr
->altivec_save_offset
11768 = info_ptr
->vrsave_save_offset
11769 - info_ptr
->altivec_padding_size
11770 - info_ptr
->altivec_size
;
11772 /* Adjust for AltiVec case. */
11773 info_ptr
->toc_save_offset
11774 = info_ptr
->altivec_save_offset
- info_ptr
->toc_size
;
11777 info_ptr
->toc_save_offset
= info_ptr
->cr_save_offset
- info_ptr
->toc_size
;
11778 info_ptr
->ehrd_offset
= info_ptr
->toc_save_offset
- ehrd_size
;
11779 info_ptr
->lr_save_offset
= reg_size
;
11783 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
11784 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
11785 + info_ptr
->gp_size
11786 + info_ptr
->altivec_size
11787 + info_ptr
->altivec_padding_size
11788 + info_ptr
->spe_gp_size
11789 + info_ptr
->spe_padding_size
11791 + info_ptr
->cr_size
11792 + info_ptr
->lr_size
11793 + info_ptr
->vrsave_size
11794 + info_ptr
->toc_size
,
11797 non_fixed_size
= (info_ptr
->vars_size
11798 + info_ptr
->parm_size
11799 + info_ptr
->save_size
11800 + info_ptr
->varargs_size
);
11802 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
11803 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
11805 /* Determine if we need to allocate any stack frame:
11807 For AIX we need to push the stack if a frame pointer is needed
11808 (because the stack might be dynamically adjusted), if we are
11809 debugging, if we make calls, or if the sum of fp_save, gp_save,
11810 and local variables are more than the space needed to save all
11811 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11812 + 18*8 = 288 (GPR13 reserved).
11814 For V.4 we don't have the stack cushion that AIX uses, but assume
11815 that the debugger can handle stackless frames. */
11817 if (info_ptr
->calls_p
)
11818 info_ptr
->push_p
= 1;
11820 else if (DEFAULT_ABI
== ABI_V4
)
11821 info_ptr
->push_p
= non_fixed_size
!= 0;
11823 else if (frame_pointer_needed
)
11824 info_ptr
->push_p
= 1;
11826 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
11827 info_ptr
->push_p
= 1;
11830 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
11832 /* Zero offsets if we're not saving those registers. */
11833 if (info_ptr
->fp_size
== 0)
11834 info_ptr
->fp_save_offset
= 0;
11836 if (info_ptr
->gp_size
== 0)
11837 info_ptr
->gp_save_offset
= 0;
11839 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
11840 info_ptr
->altivec_save_offset
= 0;
11842 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
11843 info_ptr
->vrsave_save_offset
= 0;
11845 if (! TARGET_SPE_ABI
11846 || info_ptr
->spe_64bit_regs_used
== 0
11847 || info_ptr
->spe_gp_size
== 0)
11848 info_ptr
->spe_gp_save_offset
= 0;
11850 if (! info_ptr
->lr_save_p
)
11851 info_ptr
->lr_save_offset
= 0;
11853 if (! info_ptr
->cr_save_p
)
11854 info_ptr
->cr_save_offset
= 0;
11856 if (! info_ptr
->toc_save_p
)
11857 info_ptr
->toc_save_offset
= 0;
11862 /* Return true if the current function uses any GPRs in 64-bit SIMD
11866 spe_func_has_64bit_regs_p (void)
11870 /* Functions that save and restore all the call-saved registers will
11871 need to save/restore the registers in 64-bits. */
11872 if (current_function_calls_eh_return
11873 || current_function_calls_setjmp
11874 || current_function_has_nonlocal_goto
)
11877 insns
= get_insns ();
11879 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11885 /* FIXME: This should be implemented with attributes...
11887 (set_attr "spe64" "true")....then,
11888 if (get_spe64(insn)) return true;
11890 It's the only reliable way to do the stuff below. */
11892 i
= PATTERN (insn
);
11893 if (GET_CODE (i
) == SET
)
11895 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
11897 if (SPE_VECTOR_MODE (mode
))
11899 if (TARGET_E500_DOUBLE
&& mode
== DFmode
)
11909 debug_stack_info (rs6000_stack_t
*info
)
11911 const char *abi_string
;
11914 info
= rs6000_stack_info ();
11916 fprintf (stderr
, "\nStack information for function %s:\n",
11917 ((current_function_decl
&& DECL_NAME (current_function_decl
))
11918 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
11923 default: abi_string
= "Unknown"; break;
11924 case ABI_NONE
: abi_string
= "NONE"; break;
11925 case ABI_AIX
: abi_string
= "AIX"; break;
11926 case ABI_DARWIN
: abi_string
= "Darwin"; break;
11927 case ABI_V4
: abi_string
= "V.4"; break;
11930 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
11932 if (TARGET_ALTIVEC_ABI
)
11933 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
11935 if (TARGET_SPE_ABI
)
11936 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
11938 if (info
->first_gp_reg_save
!= 32)
11939 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
11941 if (info
->first_fp_reg_save
!= 64)
11942 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
11944 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
11945 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
11946 info
->first_altivec_reg_save
);
11948 if (info
->lr_save_p
)
11949 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
11951 if (info
->cr_save_p
)
11952 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
11954 if (info
->toc_save_p
)
11955 fprintf (stderr
, "\ttoc_save_p = %5d\n", info
->toc_save_p
);
11957 if (info
->vrsave_mask
)
11958 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
11961 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
11964 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
11966 if (info
->gp_save_offset
)
11967 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
11969 if (info
->fp_save_offset
)
11970 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
11972 if (info
->altivec_save_offset
)
11973 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
11974 info
->altivec_save_offset
);
11976 if (info
->spe_gp_save_offset
)
11977 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
11978 info
->spe_gp_save_offset
);
11980 if (info
->vrsave_save_offset
)
11981 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
11982 info
->vrsave_save_offset
);
11984 if (info
->lr_save_offset
)
11985 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
11987 if (info
->cr_save_offset
)
11988 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
11990 if (info
->toc_save_offset
)
11991 fprintf (stderr
, "\ttoc_save_offset = %5d\n", info
->toc_save_offset
);
11993 if (info
->varargs_save_offset
)
11994 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
11996 if (info
->total_size
)
11997 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
12000 if (info
->varargs_size
)
12001 fprintf (stderr
, "\tvarargs_size = %5d\n", info
->varargs_size
);
12003 if (info
->vars_size
)
12004 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
12007 if (info
->parm_size
)
12008 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
12010 if (info
->fixed_size
)
12011 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
12014 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
12016 if (info
->spe_gp_size
)
12017 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
12020 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
12022 if (info
->altivec_size
)
12023 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
12025 if (info
->vrsave_size
)
12026 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
12028 if (info
->altivec_padding_size
)
12029 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
12030 info
->altivec_padding_size
);
12032 if (info
->spe_padding_size
)
12033 fprintf (stderr
, "\tspe_padding_size = %5d\n",
12034 info
->spe_padding_size
);
12037 fprintf (stderr
, "\tlr_size = %5d\n", info
->lr_size
);
12040 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
12042 if (info
->toc_size
)
12043 fprintf (stderr
, "\ttoc_size = %5d\n", info
->toc_size
);
12045 if (info
->save_size
)
12046 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
12048 if (info
->reg_size
!= 4)
12049 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
12051 fprintf (stderr
, "\n");
12055 rs6000_return_addr (int count
, rtx frame
)
12057 /* Currently we don't optimize very well between prolog and body
12058 code and for PIC code the code can be actually quite bad, so
12059 don't try to be too clever here. */
12060 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
12062 cfun
->machine
->ra_needs_full_frame
= 1;
12069 plus_constant (copy_to_reg
12070 (gen_rtx_MEM (Pmode
,
12071 memory_address (Pmode
, frame
))),
12072 RETURN_ADDRESS_OFFSET
)));
12075 cfun
->machine
->ra_need_lr
= 1;
12076 return get_hard_reg_initial_val (Pmode
, LINK_REGISTER_REGNUM
);
12079 /* Say whether a function is a candidate for sibcall handling or not.
12080 We do not allow indirect calls to be optimized into sibling calls.
12081 Also, we can't do it if there are any vector parameters; there's
12082 nowhere to put the VRsave code so it works; note that functions with
12083 vector parameters are required to have a prototype, so the argument
12084 type info must be available here. (The tail recursion case can work
12085 with vector parameters, but there's no way to distinguish here.) */
12087 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
12092 if (TARGET_ALTIVEC_VRSAVE
)
12094 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
12095 type
; type
= TREE_CHAIN (type
))
12097 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
12101 if (DEFAULT_ABI
== ABI_DARWIN
12102 || (*targetm
.binds_local_p
) (decl
))
12104 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
12106 if (!lookup_attribute ("longcall", attr_list
)
12107 || lookup_attribute ("shortcall", attr_list
))
12115 rs6000_ra_ever_killed (void)
12121 if (current_function_is_thunk
)
12124 /* regs_ever_live has LR marked as used if any sibcalls are present,
12125 but this should not force saving and restoring in the
12126 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
12127 clobbers LR, so that is inappropriate. */
12129 /* Also, the prologue can generate a store into LR that
12130 doesn't really count, like this:
12133 bcl to set PIC register
12137 When we're called from the epilogue, we need to avoid counting
12138 this as a store. */
12140 push_topmost_sequence ();
12141 top
= get_insns ();
12142 pop_topmost_sequence ();
12143 reg
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
12145 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12149 if (FIND_REG_INC_NOTE (insn
, reg
))
12151 else if (GET_CODE (insn
) == CALL_INSN
12152 && !SIBLING_CALL_P (insn
))
12154 else if (set_of (reg
, insn
) != NULL_RTX
12155 && !prologue_epilogue_contains (insn
))
12162 /* Add a REG_MAYBE_DEAD note to the insn. */
12164 rs6000_maybe_dead (rtx insn
)
12166 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
12171 /* Emit instructions needed to load the TOC register.
12172 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
12173 a constant pool; or for SVR4 -fpic. */
12176 rs6000_emit_load_toc_table (int fromprolog
)
12179 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
12181 if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
12183 rtx temp
= (fromprolog
12184 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
12185 : gen_reg_rtx (Pmode
));
12186 insn
= emit_insn (gen_load_toc_v4_pic_si (temp
));
12188 rs6000_maybe_dead (insn
);
12189 insn
= emit_move_insn (dest
, temp
);
12191 rs6000_maybe_dead (insn
);
12193 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
12196 rtx tempLR
= (fromprolog
12197 ? gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
)
12198 : gen_reg_rtx (Pmode
));
12199 rtx temp0
= (fromprolog
12200 ? gen_rtx_REG (Pmode
, 0)
12201 : gen_reg_rtx (Pmode
));
12207 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
12208 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12210 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
12211 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12213 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR
,
12215 rs6000_maybe_dead (emit_move_insn (dest
, tempLR
));
12216 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
,
12224 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
12225 emit_insn (gen_load_toc_v4_PIC_1b (tempLR
, tocsym
));
12226 emit_move_insn (dest
, tempLR
);
12227 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
12229 insn
= emit_insn (gen_addsi3 (dest
, temp0
, dest
));
12231 rs6000_maybe_dead (insn
);
12233 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
12235 /* This is for AIX code running in non-PIC ELF32. */
12238 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
12239 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
12241 insn
= emit_insn (gen_elf_high (dest
, realsym
));
12243 rs6000_maybe_dead (insn
);
12244 insn
= emit_insn (gen_elf_low (dest
, dest
, realsym
));
12246 rs6000_maybe_dead (insn
);
12248 else if (DEFAULT_ABI
== ABI_AIX
)
12251 insn
= emit_insn (gen_load_toc_aix_si (dest
));
12253 insn
= emit_insn (gen_load_toc_aix_di (dest
));
12255 rs6000_maybe_dead (insn
);
12261 /* Emit instructions to restore the link register after determining where
12262 its value has been stored. */
12265 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
12267 rs6000_stack_t
*info
= rs6000_stack_info ();
12270 operands
[0] = source
;
12271 operands
[1] = scratch
;
12273 if (info
->lr_save_p
)
12275 rtx frame_rtx
= stack_pointer_rtx
;
12276 HOST_WIDE_INT sp_offset
= 0;
12279 if (frame_pointer_needed
12280 || current_function_calls_alloca
12281 || info
->total_size
> 32767)
12283 emit_move_insn (operands
[1], gen_rtx_MEM (Pmode
, frame_rtx
));
12284 frame_rtx
= operands
[1];
12286 else if (info
->push_p
)
12287 sp_offset
= info
->total_size
;
12289 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
12290 tmp
= gen_rtx_MEM (Pmode
, tmp
);
12291 emit_move_insn (tmp
, operands
[0]);
12294 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
), operands
[0]);
12297 static GTY(()) int set
= -1;
12300 get_TOC_alias_set (void)
12303 set
= new_alias_set ();
12307 /* This returns nonzero if the current function uses the TOC. This is
12308 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12309 is generated by the ABI_V4 load_toc_* patterns. */
12316 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12319 rtx pat
= PATTERN (insn
);
12322 if (GET_CODE (pat
) == PARALLEL
)
12323 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
12325 rtx sub
= XVECEXP (pat
, 0, i
);
12326 if (GET_CODE (sub
) == USE
)
12328 sub
= XEXP (sub
, 0);
12329 if (GET_CODE (sub
) == UNSPEC
12330 && XINT (sub
, 1) == UNSPEC_TOC
)
12340 create_TOC_reference (rtx symbol
)
12342 return gen_rtx_PLUS (Pmode
,
12343 gen_rtx_REG (Pmode
, TOC_REGISTER
),
12344 gen_rtx_CONST (Pmode
,
12345 gen_rtx_MINUS (Pmode
, symbol
,
12346 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
12349 /* If _Unwind_* has been called from within the same module,
12350 toc register is not guaranteed to be saved to 40(1) on function
12351 entry. Save it there in that case. */
12354 rs6000_aix_emit_builtin_unwind_init (void)
12357 rtx stack_top
= gen_reg_rtx (Pmode
);
12358 rtx opcode_addr
= gen_reg_rtx (Pmode
);
12359 rtx opcode
= gen_reg_rtx (SImode
);
12360 rtx tocompare
= gen_reg_rtx (SImode
);
12361 rtx no_toc_save_needed
= gen_label_rtx ();
12363 mem
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
12364 emit_move_insn (stack_top
, mem
);
12366 mem
= gen_rtx_MEM (Pmode
,
12367 gen_rtx_PLUS (Pmode
, stack_top
,
12368 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
12369 emit_move_insn (opcode_addr
, mem
);
12370 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
12371 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
12372 : 0xE8410028, SImode
));
12374 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
12375 SImode
, NULL_RTX
, NULL_RTX
,
12376 no_toc_save_needed
);
12378 mem
= gen_rtx_MEM (Pmode
,
12379 gen_rtx_PLUS (Pmode
, stack_top
,
12380 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
12381 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
12382 emit_label (no_toc_save_needed
);
12385 /* This ties together stack memory (MEM with an alias set of
12386 rs6000_sr_alias_set) and the change to the stack pointer. */
12389 rs6000_emit_stack_tie (void)
12391 rtx mem
= gen_rtx_MEM (BLKmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
12393 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12394 emit_insn (gen_stack_tie (mem
));
12397 /* Emit the correct code for allocating stack space, as insns.
12398 If COPY_R12, make sure a copy of the old frame is left in r12.
12399 The generated code may use hard register 0 as a temporary. */
12402 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
12405 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
12406 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
12407 rtx todec
= gen_int_mode (-size
, Pmode
);
12409 if (INTVAL (todec
) != -size
)
12411 warning ("stack frame too large");
12412 emit_insn (gen_trap ());
12416 if (current_function_limit_stack
)
12418 if (REG_P (stack_limit_rtx
)
12419 && REGNO (stack_limit_rtx
) > 1
12420 && REGNO (stack_limit_rtx
) <= 31)
12422 emit_insn (TARGET_32BIT
12423 ? gen_addsi3 (tmp_reg
,
12426 : gen_adddi3 (tmp_reg
,
12430 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
12433 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
12435 && DEFAULT_ABI
== ABI_V4
)
12437 rtx toload
= gen_rtx_CONST (VOIDmode
,
12438 gen_rtx_PLUS (Pmode
,
12442 emit_insn (gen_elf_high (tmp_reg
, toload
));
12443 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
12444 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
12448 warning ("stack limit expression is not supported");
12451 if (copy_r12
|| ! TARGET_UPDATE
)
12452 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
12458 /* Need a note here so that try_split doesn't get confused. */
12459 if (get_last_insn () == NULL_RTX
)
12460 emit_note (NOTE_INSN_DELETED
);
12461 insn
= emit_move_insn (tmp_reg
, todec
);
12462 try_split (PATTERN (insn
), insn
, 0);
12466 insn
= emit_insn (TARGET_32BIT
12467 ? gen_movsi_update (stack_reg
, stack_reg
,
12469 : gen_movdi_di_update (stack_reg
, stack_reg
,
12470 todec
, stack_reg
));
12474 insn
= emit_insn (TARGET_32BIT
12475 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
12476 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
12477 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
12478 gen_rtx_REG (Pmode
, 12));
12481 RTX_FRAME_RELATED_P (insn
) = 1;
12483 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
12484 gen_rtx_SET (VOIDmode
, stack_reg
,
12485 gen_rtx_PLUS (Pmode
, stack_reg
,
12490 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12491 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12492 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12493 deduce these equivalences by itself so it wasn't necessary to hold
12494 its hand so much. */
12497 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
12498 rtx reg2
, rtx rreg
)
12502 /* copy_rtx will not make unique copies of registers, so we need to
12503 ensure we don't have unwanted sharing here. */
12505 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
12508 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
12510 real
= copy_rtx (PATTERN (insn
));
12512 if (reg2
!= NULL_RTX
)
12513 real
= replace_rtx (real
, reg2
, rreg
);
12515 real
= replace_rtx (real
, reg
,
12516 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
12517 STACK_POINTER_REGNUM
),
12520 /* We expect that 'real' is either a SET or a PARALLEL containing
12521 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12522 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12524 if (GET_CODE (real
) == SET
)
12528 temp
= simplify_rtx (SET_SRC (set
));
12530 SET_SRC (set
) = temp
;
12531 temp
= simplify_rtx (SET_DEST (set
));
12533 SET_DEST (set
) = temp
;
12534 if (GET_CODE (SET_DEST (set
)) == MEM
)
12536 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
12538 XEXP (SET_DEST (set
), 0) = temp
;
12541 else if (GET_CODE (real
) == PARALLEL
)
12544 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
12545 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
12547 rtx set
= XVECEXP (real
, 0, i
);
12549 temp
= simplify_rtx (SET_SRC (set
));
12551 SET_SRC (set
) = temp
;
12552 temp
= simplify_rtx (SET_DEST (set
));
12554 SET_DEST (set
) = temp
;
12555 if (GET_CODE (SET_DEST (set
)) == MEM
)
12557 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
12559 XEXP (SET_DEST (set
), 0) = temp
;
12561 RTX_FRAME_RELATED_P (set
) = 1;
12568 real
= spe_synthesize_frame_save (real
);
12570 RTX_FRAME_RELATED_P (insn
) = 1;
12571 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
12576 /* Given an SPE frame note, return a PARALLEL of SETs with the
12577 original note, plus a synthetic register save. */
12580 spe_synthesize_frame_save (rtx real
)
12582 rtx synth
, offset
, reg
, real2
;
12584 if (GET_CODE (real
) != SET
12585 || GET_MODE (SET_SRC (real
)) != V2SImode
)
12588 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12589 frame related note. The parallel contains a set of the register
12590 being saved, and another set to a synthetic register (n+1200).
12591 This is so we can differentiate between 64-bit and 32-bit saves.
12592 Words cannot describe this nastiness. */
12594 if (GET_CODE (SET_DEST (real
)) != MEM
12595 || GET_CODE (XEXP (SET_DEST (real
), 0)) != PLUS
12596 || GET_CODE (SET_SRC (real
)) != REG
)
12600 (set (mem (plus (reg x) (const y)))
12603 (set (mem (plus (reg x) (const y+4)))
12607 real2
= copy_rtx (real
);
12608 PUT_MODE (SET_DEST (real2
), SImode
);
12609 reg
= SET_SRC (real2
);
12610 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
12611 synth
= copy_rtx (real2
);
12613 if (BYTES_BIG_ENDIAN
)
12615 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
12616 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
12619 reg
= SET_SRC (synth
);
12621 synth
= replace_rtx (synth
, reg
,
12622 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
12624 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
12625 synth
= replace_rtx (synth
, offset
,
12626 GEN_INT (INTVAL (offset
)
12627 + (BYTES_BIG_ENDIAN
? 0 : 4)));
12629 RTX_FRAME_RELATED_P (synth
) = 1;
12630 RTX_FRAME_RELATED_P (real2
) = 1;
12631 if (BYTES_BIG_ENDIAN
)
12632 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
12634 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
12639 /* Returns an insn that has a vrsave set operation with the
12640 appropriate CLOBBERs. */
12643 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
12646 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
12647 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
12650 = gen_rtx_SET (VOIDmode
,
12652 gen_rtx_UNSPEC_VOLATILE (SImode
,
12653 gen_rtvec (2, reg
, vrsave
),
12658 /* We need to clobber the registers in the mask so the scheduler
12659 does not move sets to VRSAVE before sets of AltiVec registers.
12661 However, if the function receives nonlocal gotos, reload will set
12662 all call saved registers live. We will end up with:
12664 (set (reg 999) (mem))
12665 (parallel [ (set (reg vrsave) (unspec blah))
12666 (clobber (reg 999))])
12668 The clobber will cause the store into reg 999 to be dead, and
12669 flow will attempt to delete an epilogue insn. In this case, we
12670 need an unspec use/set of the register. */
12672 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12673 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
12675 if (!epiloguep
|| call_used_regs
[i
])
12676 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
12677 gen_rtx_REG (V4SImode
, i
));
12680 rtx reg
= gen_rtx_REG (V4SImode
, i
);
12683 = gen_rtx_SET (VOIDmode
,
12685 gen_rtx_UNSPEC (V4SImode
,
12686 gen_rtvec (1, reg
), 27));
12690 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
12692 for (i
= 0; i
< nclobs
; ++i
)
12693 XVECEXP (insn
, 0, i
) = clobs
[i
];
12698 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12699 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12702 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
12703 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
12705 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
12706 rtx replacea
, replaceb
;
12708 int_rtx
= GEN_INT (offset
);
12710 /* Some cases that need register indexed addressing. */
12711 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12712 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
12714 && SPE_VECTOR_MODE (mode
)
12715 && !SPE_CONST_OFFSET_OK (offset
)))
12717 /* Whomever calls us must make sure r11 is available in the
12718 flow path of instructions in the prologue. */
12719 offset_rtx
= gen_rtx_REG (Pmode
, 11);
12720 emit_move_insn (offset_rtx
, int_rtx
);
12722 replacea
= offset_rtx
;
12723 replaceb
= int_rtx
;
12727 offset_rtx
= int_rtx
;
12728 replacea
= NULL_RTX
;
12729 replaceb
= NULL_RTX
;
12732 reg
= gen_rtx_REG (mode
, regno
);
12733 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
12734 mem
= gen_rtx_MEM (mode
, addr
);
12735 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12737 insn
= emit_move_insn (mem
, reg
);
12739 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
12742 /* Emit an offset memory reference suitable for a frame store, while
12743 converting to a valid addressing mode. */
12746 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
12748 rtx int_rtx
, offset_rtx
;
12750 int_rtx
= GEN_INT (offset
);
12752 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
12753 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
12755 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
12756 emit_move_insn (offset_rtx
, int_rtx
);
12759 offset_rtx
= int_rtx
;
12761 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
12764 #ifndef TARGET_FIX_AND_CONTINUE
12765 #define TARGET_FIX_AND_CONTINUE 0
12768 /* Emit function prologue as insns. */
12771 rs6000_emit_prologue (void)
12773 rs6000_stack_t
*info
= rs6000_stack_info ();
12774 enum machine_mode reg_mode
= Pmode
;
12775 int reg_size
= TARGET_32BIT
? 4 : 8;
12776 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
12777 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
12778 rtx frame_reg_rtx
= sp_reg_rtx
;
12779 rtx cr_save_rtx
= NULL_RTX
;
12781 int saving_FPRs_inline
;
12782 int using_store_multiple
;
12783 HOST_WIDE_INT sp_offset
= 0;
12785 if (TARGET_FIX_AND_CONTINUE
)
12787 /* gdb on darwin arranges to forward a function from the old
12788 address by modifying the first 5 instructions of the function
12789 to branch to the overriding function. This is necessary to
12790 permit function pointers that point to the old function to
12791 actually forward to the new function. */
12792 emit_insn (gen_nop ());
12793 emit_insn (gen_nop ());
12794 emit_insn (gen_nop ());
12795 emit_insn (gen_nop ());
12796 emit_insn (gen_nop ());
12799 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
12801 reg_mode
= V2SImode
;
12805 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
12806 && (!TARGET_SPE_ABI
12807 || info
->spe_64bit_regs_used
== 0)
12808 && info
->first_gp_reg_save
< 31);
12809 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
12810 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
12811 || current_function_calls_eh_return
12812 || cfun
->machine
->ra_need_lr
);
12814 /* For V.4, update stack before we do any saving and set back pointer. */
12816 && (DEFAULT_ABI
== ABI_V4
12817 || current_function_calls_eh_return
))
12819 if (info
->total_size
< 32767)
12820 sp_offset
= info
->total_size
;
12822 frame_reg_rtx
= frame_ptr_rtx
;
12823 rs6000_emit_allocate_stack (info
->total_size
,
12824 (frame_reg_rtx
!= sp_reg_rtx
12825 && (info
->cr_save_p
12827 || info
->first_fp_reg_save
< 64
12828 || info
->first_gp_reg_save
< 32
12830 if (frame_reg_rtx
!= sp_reg_rtx
)
12831 rs6000_emit_stack_tie ();
12834 /* Handle world saves specially here. */
12835 if (WORLD_SAVE_P (info
))
12841 /* save_world expects lr in r0. */
12842 if (info
->lr_save_p
)
12844 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
12845 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
12846 RTX_FRAME_RELATED_P (insn
) = 1;
12849 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
12850 assumptions about the offsets of various bits of the stack
12851 frame. Abort if things aren't what they should be. */
12852 if (info
->gp_save_offset
!= -220
12853 || info
->fp_save_offset
!= -144
12854 || info
->lr_save_offset
!= 8
12855 || info
->cr_save_offset
!= 4
12857 || !info
->lr_save_p
12858 || (current_function_calls_eh_return
&& info
->ehrd_offset
!= -432)
12859 || (info
->vrsave_save_offset
!= -224
12860 || info
->altivec_save_offset
!= (-224 -16 -192)))
12863 treg
= gen_rtx_REG (SImode
, 11);
12864 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
12866 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
12867 in R11. It also clobbers R12, so beware! */
12869 /* Preserve CR2 for save_world prologues */
12871 sz
+= 32 - info
->first_gp_reg_save
;
12872 sz
+= 64 - info
->first_fp_reg_save
;
12873 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
12874 p
= rtvec_alloc (sz
);
12876 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
12877 gen_rtx_REG (Pmode
,
12878 LINK_REGISTER_REGNUM
));
12879 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
12880 gen_rtx_SYMBOL_REF (Pmode
,
12882 /* We do floats first so that the instruction pattern matches
12884 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
12886 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
12887 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
12888 GEN_INT (info
->fp_save_offset
12889 + sp_offset
+ 8 * i
));
12890 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
12891 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12893 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
12895 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
12897 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
12898 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
12899 GEN_INT (info
->altivec_save_offset
12900 + sp_offset
+ 16 * i
));
12901 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
12902 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12904 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
12906 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
12908 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
12909 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
12910 GEN_INT (info
->gp_save_offset
12911 + sp_offset
+ reg_size
* i
));
12912 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
12913 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12915 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
12919 /* CR register traditionally saved as CR2. */
12920 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
12921 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
12922 GEN_INT (info
->cr_save_offset
12924 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
12925 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12927 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
12929 /* Prevent any attempt to delete the setting of r0 and treg! */
12930 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
12931 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
, treg
);
12932 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
, sp_reg_rtx
);
12934 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
12935 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
12936 NULL_RTX
, NULL_RTX
);
12938 if (current_function_calls_eh_return
)
12943 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
12944 if (regno
== INVALID_REGNUM
)
12946 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
12947 info
->ehrd_offset
+ sp_offset
12948 + reg_size
* (int) i
,
12954 /* Save AltiVec registers if needed. */
12955 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
12959 /* There should be a non inline version of this, for when we
12960 are saving lots of vector registers. */
12961 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
12962 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
12964 rtx areg
, savereg
, mem
;
12967 offset
= info
->altivec_save_offset
+ sp_offset
12968 + 16 * (i
- info
->first_altivec_reg_save
);
12970 savereg
= gen_rtx_REG (V4SImode
, i
);
12972 areg
= gen_rtx_REG (Pmode
, 0);
12973 emit_move_insn (areg
, GEN_INT (offset
));
12975 /* AltiVec addressing mode is [reg+reg]. */
12976 mem
= gen_rtx_MEM (V4SImode
,
12977 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
12979 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
12981 insn
= emit_move_insn (mem
, savereg
);
12983 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
12984 areg
, GEN_INT (offset
));
12988 /* VRSAVE is a bit vector representing which AltiVec registers
12989 are used. The OS uses this to determine which vector
12990 registers to save on a context switch. We need to save
12991 VRSAVE on the stack frame, add whatever AltiVec registers we
12992 used in this function, and do the corresponding magic in the
12995 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
12996 && !WORLD_SAVE_P (info
) && info
->vrsave_mask
!= 0)
12998 rtx reg
, mem
, vrsave
;
13001 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
13002 as frame_reg_rtx and r11 as the static chain pointer for
13003 nested functions. */
13004 reg
= gen_rtx_REG (SImode
, 0);
13005 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
13007 emit_insn (gen_get_vrsave_internal (reg
));
13009 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
13012 offset
= info
->vrsave_save_offset
+ sp_offset
;
13014 = gen_rtx_MEM (SImode
,
13015 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, GEN_INT (offset
)));
13016 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13017 insn
= emit_move_insn (mem
, reg
);
13019 /* Include the registers in the mask. */
13020 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
13022 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
13025 /* If we use the link register, get it into r0. */
13026 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
13028 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
13029 gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
));
13030 RTX_FRAME_RELATED_P (insn
) = 1;
13033 /* If we need to save CR, put it into r12. */
13034 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
13038 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
13039 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
13040 RTX_FRAME_RELATED_P (insn
) = 1;
13041 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13042 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13043 But that's OK. All we have to do is specify that _one_ condition
13044 code register is saved in this stack slot. The thrower's epilogue
13045 will then restore all the call-saved registers.
13046 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13047 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
13048 gen_rtx_REG (SImode
, CR2_REGNO
));
13049 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13054 /* Do any required saving of fpr's. If only one or two to save, do
13055 it ourselves. Otherwise, call function. */
13056 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
13059 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13060 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
13061 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
13062 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
13063 info
->first_fp_reg_save
+ i
,
13064 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
13067 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
13071 const char *alloc_rname
;
13073 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
13075 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
13076 gen_rtx_REG (Pmode
,
13077 LINK_REGISTER_REGNUM
));
13078 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
13079 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
13080 alloc_rname
= ggc_strdup (rname
);
13081 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
13082 gen_rtx_SYMBOL_REF (Pmode
,
13084 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13086 rtx addr
, reg
, mem
;
13087 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
13088 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13089 GEN_INT (info
->fp_save_offset
13090 + sp_offset
+ 8*i
));
13091 mem
= gen_rtx_MEM (DFmode
, addr
);
13092 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13094 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13096 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13097 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13098 NULL_RTX
, NULL_RTX
);
13101 /* Save GPRs. This is done as a PARALLEL if we are using
13102 the store-multiple instructions. */
13103 if (!WORLD_SAVE_P (info
) && using_store_multiple
)
13107 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
13108 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13110 rtx addr
, reg
, mem
;
13111 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13112 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13113 GEN_INT (info
->gp_save_offset
13116 mem
= gen_rtx_MEM (reg_mode
, addr
);
13117 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13119 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
13121 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13122 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13123 NULL_RTX
, NULL_RTX
);
13125 else if (!WORLD_SAVE_P (info
))
13128 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13129 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
13130 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
13131 || (i
+info
->first_gp_reg_save
13132 == RS6000_PIC_OFFSET_TABLE_REGNUM
13133 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
13134 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
13135 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
13136 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
13138 rtx addr
, reg
, mem
;
13139 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13141 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13143 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
13146 if (!SPE_CONST_OFFSET_OK (offset
))
13148 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13149 emit_move_insn (b
, GEN_INT (offset
));
13152 b
= GEN_INT (offset
);
13154 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
13155 mem
= gen_rtx_MEM (V2SImode
, addr
);
13156 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13157 insn
= emit_move_insn (mem
, reg
);
13159 if (GET_CODE (b
) == CONST_INT
)
13160 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13161 NULL_RTX
, NULL_RTX
);
13163 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13164 b
, GEN_INT (offset
));
13168 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13169 GEN_INT (info
->gp_save_offset
13172 mem
= gen_rtx_MEM (reg_mode
, addr
);
13173 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13175 insn
= emit_move_insn (mem
, reg
);
13176 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13177 NULL_RTX
, NULL_RTX
);
13182 /* ??? There's no need to emit actual instructions here, but it's the
13183 easiest way to get the frame unwind information emitted. */
13184 if (!WORLD_SAVE_P (info
) && current_function_calls_eh_return
)
13186 unsigned int i
, regno
;
13188 /* In AIX ABI we need to pretend we save r2 here. */
13191 rtx addr
, reg
, mem
;
13193 reg
= gen_rtx_REG (reg_mode
, 2);
13194 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13195 GEN_INT (sp_offset
+ 5 * reg_size
));
13196 mem
= gen_rtx_MEM (reg_mode
, addr
);
13197 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13199 insn
= emit_move_insn (mem
, reg
);
13200 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13201 NULL_RTX
, NULL_RTX
);
13202 PATTERN (insn
) = gen_blockage ();
13207 regno
= EH_RETURN_DATA_REGNO (i
);
13208 if (regno
== INVALID_REGNUM
)
13211 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
13212 info
->ehrd_offset
+ sp_offset
13213 + reg_size
* (int) i
,
13218 /* Save lr if we used it. */
13219 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
13221 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13222 GEN_INT (info
->lr_save_offset
+ sp_offset
));
13223 rtx reg
= gen_rtx_REG (Pmode
, 0);
13224 rtx mem
= gen_rtx_MEM (Pmode
, addr
);
13225 /* This should not be of rs6000_sr_alias_set, because of
13226 __builtin_return_address. */
13228 insn
= emit_move_insn (mem
, reg
);
13229 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13230 NULL_RTX
, NULL_RTX
);
13233 /* Save CR if we use any that must be preserved. */
13234 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
13236 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13237 GEN_INT (info
->cr_save_offset
+ sp_offset
));
13238 rtx mem
= gen_rtx_MEM (SImode
, addr
);
13239 /* See the large comment above about why CR2_REGNO is used. */
13240 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
13242 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13244 /* If r12 was used to hold the original sp, copy cr into r0 now
13246 if (REGNO (frame_reg_rtx
) == 12)
13250 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
13251 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
13252 RTX_FRAME_RELATED_P (insn
) = 1;
13253 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
13254 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
13259 insn
= emit_move_insn (mem
, cr_save_rtx
);
13261 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
13262 NULL_RTX
, NULL_RTX
);
13265 /* Update stack and set back pointer unless this is V.4,
13266 for which it was done previously. */
13267 if (!WORLD_SAVE_P (info
) && info
->push_p
13268 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
13269 rs6000_emit_allocate_stack (info
->total_size
, FALSE
);
13271 /* Set frame pointer, if needed. */
13272 if (frame_pointer_needed
)
13274 insn
= emit_move_insn (gen_rtx_REG (Pmode
, FRAME_POINTER_REGNUM
),
13276 RTX_FRAME_RELATED_P (insn
) = 1;
13279 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13280 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
13281 || (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1
13282 && regs_ever_live
[RS6000_PIC_OFFSET_TABLE_REGNUM
]))
13284 /* If emit_load_toc_table will use the link register, we need to save
13285 it. We use R12 for this purpose because emit_load_toc_table
13286 can use register 0. This allows us to use a plain 'blr' to return
13287 from the procedure more often. */
13288 int save_LR_around_toc_setup
= (TARGET_ELF
13289 && DEFAULT_ABI
!= ABI_AIX
13291 && ! info
->lr_save_p
13292 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
13293 if (save_LR_around_toc_setup
)
13295 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13297 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
13298 rs6000_maybe_dead (insn
);
13299 RTX_FRAME_RELATED_P (insn
) = 1;
13301 rs6000_emit_load_toc_table (TRUE
);
13303 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
13304 rs6000_maybe_dead (insn
);
13305 RTX_FRAME_RELATED_P (insn
) = 1;
13308 rs6000_emit_load_toc_table (TRUE
);
13312 if (DEFAULT_ABI
== ABI_DARWIN
13313 && flag_pic
&& current_function_uses_pic_offset_table
)
13315 rtx lr
= gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
);
13316 rtx src
= machopic_function_base_sym ();
13318 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr
, src
)));
13320 insn
= emit_move_insn (gen_rtx_REG (Pmode
,
13321 RS6000_PIC_OFFSET_TABLE_REGNUM
),
13323 rs6000_maybe_dead (insn
);
13328 /* Write function prologue. */
13331 rs6000_output_function_prologue (FILE *file
,
13332 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13334 rs6000_stack_t
*info
= rs6000_stack_info ();
13336 if (TARGET_DEBUG_STACK
)
13337 debug_stack_info (info
);
13339 /* Write .extern for any function we will call to save and restore
13341 if (info
->first_fp_reg_save
< 64
13342 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
13343 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13344 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
13345 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
13346 RESTORE_FP_SUFFIX
);
13348 /* Write .extern for AIX common mode routines, if needed. */
13349 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
13351 fputs ("\t.extern __mulh\n", file
);
13352 fputs ("\t.extern __mull\n", file
);
13353 fputs ("\t.extern __divss\n", file
);
13354 fputs ("\t.extern __divus\n", file
);
13355 fputs ("\t.extern __quoss\n", file
);
13356 fputs ("\t.extern __quous\n", file
);
13357 common_mode_defined
= 1;
13360 if (! HAVE_prologue
)
13364 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13365 the "toplevel" insn chain. */
13366 emit_note (NOTE_INSN_DELETED
);
13367 rs6000_emit_prologue ();
13368 emit_note (NOTE_INSN_DELETED
);
13370 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13374 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
13376 INSN_ADDRESSES_NEW (insn
, addr
);
13381 if (TARGET_DEBUG_STACK
)
13382 debug_rtx_list (get_insns (), 100);
13383 final (get_insns (), file
, FALSE
);
13387 rs6000_pic_labelno
++;
13390 /* Emit function epilogue as insns.
13392 At present, dwarf2out_frame_debug_expr doesn't understand
13393 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13394 anywhere in the epilogue. Most of the insns below would in any case
13395 need special notes to explain where r11 is in relation to the stack. */
13398 rs6000_emit_epilogue (int sibcall
)
13400 rs6000_stack_t
*info
;
13401 int restoring_FPRs_inline
;
13402 int using_load_multiple
;
13403 int using_mfcr_multiple
;
13404 int use_backchain_to_restore_sp
;
13406 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
13407 rtx frame_reg_rtx
= sp_reg_rtx
;
13408 enum machine_mode reg_mode
= Pmode
;
13409 int reg_size
= TARGET_32BIT
? 4 : 8;
13412 info
= rs6000_stack_info ();
13414 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13416 reg_mode
= V2SImode
;
13420 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
13421 && (!TARGET_SPE_ABI
13422 || info
->spe_64bit_regs_used
== 0)
13423 && info
->first_gp_reg_save
< 31);
13424 restoring_FPRs_inline
= (sibcall
13425 || current_function_calls_eh_return
13426 || info
->first_fp_reg_save
== 64
13427 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
13428 use_backchain_to_restore_sp
= (frame_pointer_needed
13429 || current_function_calls_alloca
13430 || info
->total_size
> 32767);
13431 using_mfcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
13432 || rs6000_cpu
== PROCESSOR_PPC603
13433 || rs6000_cpu
== PROCESSOR_PPC750
13436 if (WORLD_SAVE_P (info
))
13440 const char *alloc_rname
;
13443 /* eh_rest_world_r10 will return to the location saved in the LR
13444 stack slot (which is not likely to be our caller.)
13445 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13446 rest_world is similar, except any R10 parameter is ignored.
13447 The exception-handling stuff that was here in 2.95 is no
13448 longer necessary. */
13452 + 32 - info
->first_gp_reg_save
13453 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
13454 + 63 + 1 - info
->first_fp_reg_save
);
13456 strcpy (rname
, ((current_function_calls_eh_return
) ?
13457 "*eh_rest_world_r10" : "*rest_world"));
13458 alloc_rname
= ggc_strdup (rname
);
13461 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
13462 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
13463 gen_rtx_REG (Pmode
,
13464 LINK_REGISTER_REGNUM
));
13466 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
13467 /* The instruction pattern requires a clobber here;
13468 it is shared with the restVEC helper. */
13470 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
13473 /* CR register traditionally saved as CR2. */
13474 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
13475 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13476 GEN_INT (info
->cr_save_offset
));
13477 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13478 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13480 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13483 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13485 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
13486 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13487 GEN_INT (info
->gp_save_offset
13489 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13490 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13492 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13494 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
13496 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
13497 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13498 GEN_INT (info
->altivec_save_offset
13500 rtx mem
= gen_rtx_MEM (V4SImode
, addr
);
13501 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13503 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13505 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
13507 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
13508 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13509 GEN_INT (info
->fp_save_offset
13511 rtx mem
= gen_rtx_MEM (DFmode
, addr
);
13512 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13514 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
13517 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
13519 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
13521 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
13523 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
13525 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
13526 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13531 /* If we have a frame pointer, a call to alloca, or a large stack
13532 frame, restore the old stack pointer using the backchain. Otherwise,
13533 we know what size to update it with. */
13534 if (use_backchain_to_restore_sp
)
13536 /* Under V.4, don't reset the stack pointer until after we're done
13537 loading the saved registers. */
13538 if (DEFAULT_ABI
== ABI_V4
)
13539 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
13541 emit_move_insn (frame_reg_rtx
,
13542 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
13545 else if (info
->push_p
)
13547 if (DEFAULT_ABI
== ABI_V4
13548 || current_function_calls_eh_return
)
13549 sp_offset
= info
->total_size
;
13552 emit_insn (TARGET_32BIT
13553 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
13554 GEN_INT (info
->total_size
))
13555 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
13556 GEN_INT (info
->total_size
)));
13560 /* Restore AltiVec registers if needed. */
13561 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
13565 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13566 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
13568 rtx addr
, areg
, mem
;
13570 areg
= gen_rtx_REG (Pmode
, 0);
13572 (areg
, GEN_INT (info
->altivec_save_offset
13574 + 16 * (i
- info
->first_altivec_reg_save
)));
13576 /* AltiVec addressing mode is [reg+reg]. */
13577 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
13578 mem
= gen_rtx_MEM (V4SImode
, addr
);
13579 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13581 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
13585 /* Restore VRSAVE if needed. */
13586 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
13587 && info
->vrsave_mask
!= 0)
13589 rtx addr
, mem
, reg
;
13591 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13592 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
13593 mem
= gen_rtx_MEM (SImode
, addr
);
13594 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13595 reg
= gen_rtx_REG (SImode
, 12);
13596 emit_move_insn (reg
, mem
);
13598 emit_insn (generate_set_vrsave (reg
, info
, 1));
13601 /* Get the old lr if we saved it. */
13602 if (info
->lr_save_p
)
13604 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
13605 info
->lr_save_offset
+ sp_offset
);
13607 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13609 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
13612 /* Get the old cr if we saved it. */
13613 if (info
->cr_save_p
)
13615 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13616 GEN_INT (info
->cr_save_offset
+ sp_offset
));
13617 rtx mem
= gen_rtx_MEM (SImode
, addr
);
13619 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13621 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
13624 /* Set LR here to try to overlap restores below. */
13625 if (info
->lr_save_p
)
13626 emit_move_insn (gen_rtx_REG (Pmode
, LINK_REGISTER_REGNUM
),
13627 gen_rtx_REG (Pmode
, 0));
13629 /* Load exception handler data registers, if needed. */
13630 if (current_function_calls_eh_return
)
13632 unsigned int i
, regno
;
13636 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13637 GEN_INT (sp_offset
+ 5 * reg_size
));
13638 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13640 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13642 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
13649 regno
= EH_RETURN_DATA_REGNO (i
);
13650 if (regno
== INVALID_REGNUM
)
13653 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
13654 info
->ehrd_offset
+ sp_offset
13655 + reg_size
* (int) i
);
13656 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13658 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
13662 /* Restore GPRs. This is done as a PARALLEL if we are using
13663 the load-multiple instructions. */
13664 if (using_load_multiple
)
13667 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
13668 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13670 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13671 GEN_INT (info
->gp_save_offset
13674 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13676 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13679 gen_rtx_SET (VOIDmode
,
13680 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
13683 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13686 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
13687 if ((regs_ever_live
[info
->first_gp_reg_save
+i
]
13688 && (! call_used_regs
[info
->first_gp_reg_save
+i
]
13689 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
13690 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
13691 || (i
+info
->first_gp_reg_save
== RS6000_PIC_OFFSET_TABLE_REGNUM
13692 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
13693 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))))
13695 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13696 GEN_INT (info
->gp_save_offset
13699 rtx mem
= gen_rtx_MEM (reg_mode
, addr
);
13701 /* Restore 64-bit quantities for SPE. */
13702 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
13704 int offset
= info
->spe_gp_save_offset
+ sp_offset
+ 8 * i
;
13707 if (!SPE_CONST_OFFSET_OK (offset
))
13709 b
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
13710 emit_move_insn (b
, GEN_INT (offset
));
13713 b
= GEN_INT (offset
);
13715 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, b
);
13716 mem
= gen_rtx_MEM (V2SImode
, addr
);
13719 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13721 emit_move_insn (gen_rtx_REG (reg_mode
,
13722 info
->first_gp_reg_save
+ i
), mem
);
13725 /* Restore fpr's if we need to do it without calling a function. */
13726 if (restoring_FPRs_inline
)
13727 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13728 if ((regs_ever_live
[info
->first_fp_reg_save
+i
]
13729 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
13732 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
13733 GEN_INT (info
->fp_save_offset
13736 mem
= gen_rtx_MEM (DFmode
, addr
);
13737 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13739 emit_move_insn (gen_rtx_REG (DFmode
,
13740 info
->first_fp_reg_save
+ i
),
13744 /* If we saved cr, restore it here. Just those that were used. */
13745 if (info
->cr_save_p
)
13747 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
13750 if (using_mfcr_multiple
)
13752 for (i
= 0; i
< 8; i
++)
13753 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
13759 if (using_mfcr_multiple
&& count
> 1)
13764 p
= rtvec_alloc (count
);
13767 for (i
= 0; i
< 8; i
++)
13768 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
13770 rtvec r
= rtvec_alloc (2);
13771 RTVEC_ELT (r
, 0) = r12_rtx
;
13772 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
13773 RTVEC_ELT (p
, ndx
) =
13774 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
13775 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
13778 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13783 for (i
= 0; i
< 8; i
++)
13784 if (regs_ever_live
[CR0_REGNO
+i
] && ! call_used_regs
[CR0_REGNO
+i
])
13786 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
13792 /* If this is V.4, unwind the stack pointer after all of the loads
13793 have been done. We need to emit a block here so that sched
13794 doesn't decide to move the sp change before the register restores
13795 (which may not have any obvious dependency on the stack). This
13796 doesn't hurt performance, because there is no scheduling that can
13797 be done after this point. */
13798 if (DEFAULT_ABI
== ABI_V4
13799 || current_function_calls_eh_return
)
13801 if (frame_reg_rtx
!= sp_reg_rtx
)
13802 rs6000_emit_stack_tie ();
13804 if (use_backchain_to_restore_sp
)
13806 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
13808 else if (sp_offset
!= 0)
13810 emit_insn (TARGET_32BIT
13811 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
13812 GEN_INT (sp_offset
))
13813 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
13814 GEN_INT (sp_offset
)));
13818 if (current_function_calls_eh_return
)
13820 rtx sa
= EH_RETURN_STACKADJ_RTX
;
13821 emit_insn (TARGET_32BIT
13822 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
13823 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
13829 if (! restoring_FPRs_inline
)
13830 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
13832 p
= rtvec_alloc (2);
13834 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
13835 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
13836 gen_rtx_REG (Pmode
,
13837 LINK_REGISTER_REGNUM
));
13839 /* If we have to restore more than two FP registers, branch to the
13840 restore function. It will return to our caller. */
13841 if (! restoring_FPRs_inline
)
13845 const char *alloc_rname
;
13847 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
13848 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
13849 alloc_rname
= ggc_strdup (rname
);
13850 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
13851 gen_rtx_SYMBOL_REF (Pmode
,
13854 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
13857 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
13858 GEN_INT (info
->fp_save_offset
+ 8*i
));
13859 mem
= gen_rtx_MEM (DFmode
, addr
);
13860 set_mem_alias_set (mem
, rs6000_sr_alias_set
);
13862 RTVEC_ELT (p
, i
+3) =
13863 gen_rtx_SET (VOIDmode
,
13864 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
13869 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
13873 /* Write function epilogue. */
13876 rs6000_output_function_epilogue (FILE *file
,
13877 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13879 rs6000_stack_t
*info
= rs6000_stack_info ();
13881 if (! HAVE_epilogue
)
13883 rtx insn
= get_last_insn ();
13884 /* If the last insn was a BARRIER, we don't have to write anything except
13885 the trace table. */
13886 if (GET_CODE (insn
) == NOTE
)
13887 insn
= prev_nonnote_insn (insn
);
13888 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
13890 /* This is slightly ugly, but at least we don't have two
13891 copies of the epilogue-emitting code. */
13894 /* A NOTE_INSN_DELETED is supposed to be at the start
13895 and end of the "toplevel" insn chain. */
13896 emit_note (NOTE_INSN_DELETED
);
13897 rs6000_emit_epilogue (FALSE
);
13898 emit_note (NOTE_INSN_DELETED
);
13900 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13904 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
13906 INSN_ADDRESSES_NEW (insn
, addr
);
13911 if (TARGET_DEBUG_STACK
)
13912 debug_rtx_list (get_insns (), 100);
13913 final (get_insns (), file
, FALSE
);
13919 macho_branch_islands ();
13920 /* Mach-O doesn't support labels at the end of objects, so if
13921 it looks like we might want one, insert a NOP. */
13923 rtx insn
= get_last_insn ();
13926 && NOTE_LINE_NUMBER (insn
) != NOTE_INSN_DELETED_LABEL
)
13927 insn
= PREV_INSN (insn
);
13931 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED_LABEL
)))
13932 fputs ("\tnop\n", file
);
13936 /* Output a traceback table here. See /usr/include/sys/debug.h for info
13939 We don't output a traceback table if -finhibit-size-directive was
13940 used. The documentation for -finhibit-size-directive reads
13941 ``don't output a @code{.size} assembler directive, or anything
13942 else that would cause trouble if the function is split in the
13943 middle, and the two halves are placed at locations far apart in
13944 memory.'' The traceback table has this property, since it
13945 includes the offset from the start of the function to the
13946 traceback table itself.
13948 System V.4 Powerpc's (and the embedded ABI derived from it) use a
13949 different traceback table. */
13950 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
13951 && rs6000_traceback
!= traceback_none
)
13953 const char *fname
= NULL
;
13954 const char *language_string
= lang_hooks
.name
;
13955 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
13957 int optional_tbtab
;
13959 if (rs6000_traceback
== traceback_full
)
13960 optional_tbtab
= 1;
13961 else if (rs6000_traceback
== traceback_part
)
13962 optional_tbtab
= 0;
13964 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
13966 if (optional_tbtab
)
13968 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13969 while (*fname
== '.') /* V.4 encodes . in the name */
13972 /* Need label immediately before tbtab, so we can compute
13973 its offset from the function start. */
13974 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
13975 ASM_OUTPUT_LABEL (file
, fname
);
13978 /* The .tbtab pseudo-op can only be used for the first eight
13979 expressions, since it can't handle the possibly variable
13980 length fields that follow. However, if you omit the optional
13981 fields, the assembler outputs zeros for all optional fields
13982 anyways, giving each variable length field is minimum length
13983 (as defined in sys/debug.h). Thus we can not use the .tbtab
13984 pseudo-op at all. */
13986 /* An all-zero word flags the start of the tbtab, for debuggers
13987 that have to find it by searching forward from the entry
13988 point or from the current pc. */
13989 fputs ("\t.long 0\n", file
);
13991 /* Tbtab format type. Use format type 0. */
13992 fputs ("\t.byte 0,", file
);
13994 /* Language type. Unfortunately, there does not seem to be any
13995 official way to discover the language being compiled, so we
13996 use language_string.
13997 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13998 Java is 13. Objective-C is 14. */
13999 if (! strcmp (language_string
, "GNU C"))
14001 else if (! strcmp (language_string
, "GNU F77")
14002 || ! strcmp (language_string
, "GNU F95"))
14004 else if (! strcmp (language_string
, "GNU Pascal"))
14006 else if (! strcmp (language_string
, "GNU Ada"))
14008 else if (! strcmp (language_string
, "GNU C++"))
14010 else if (! strcmp (language_string
, "GNU Java"))
14012 else if (! strcmp (language_string
, "GNU Objective-C"))
14016 fprintf (file
, "%d,", i
);
14018 /* 8 single bit fields: global linkage (not set for C extern linkage,
14019 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14020 from start of procedure stored in tbtab, internal function, function
14021 has controlled storage, function has no toc, function uses fp,
14022 function logs/aborts fp operations. */
14023 /* Assume that fp operations are used if any fp reg must be saved. */
14024 fprintf (file
, "%d,",
14025 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
14027 /* 6 bitfields: function is interrupt handler, name present in
14028 proc table, function calls alloca, on condition directives
14029 (controls stack walks, 3 bits), saves condition reg, saves
14031 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14032 set up as a frame pointer, even when there is no alloca call. */
14033 fprintf (file
, "%d,",
14034 ((optional_tbtab
<< 6)
14035 | ((optional_tbtab
& frame_pointer_needed
) << 5)
14036 | (info
->cr_save_p
<< 1)
14037 | (info
->lr_save_p
)));
14039 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
14041 fprintf (file
, "%d,",
14042 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
14044 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14045 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
14047 if (optional_tbtab
)
14049 /* Compute the parameter info from the function decl argument
14052 int next_parm_info_bit
= 31;
14054 for (decl
= DECL_ARGUMENTS (current_function_decl
);
14055 decl
; decl
= TREE_CHAIN (decl
))
14057 rtx parameter
= DECL_INCOMING_RTL (decl
);
14058 enum machine_mode mode
= GET_MODE (parameter
);
14060 if (GET_CODE (parameter
) == REG
)
14062 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
14068 if (mode
== SFmode
)
14070 else if (mode
== DFmode
|| mode
== TFmode
)
14075 /* If only one bit will fit, don't or in this entry. */
14076 if (next_parm_info_bit
> 0)
14077 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
14078 next_parm_info_bit
-= 2;
14082 fixed_parms
+= ((GET_MODE_SIZE (mode
)
14083 + (UNITS_PER_WORD
- 1))
14085 next_parm_info_bit
-= 1;
14091 /* Number of fixed point parameters. */
14092 /* This is actually the number of words of fixed point parameters; thus
14093 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14094 fprintf (file
, "%d,", fixed_parms
);
14096 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14098 /* This is actually the number of fp registers that hold parameters;
14099 and thus the maximum value is 13. */
14100 /* Set parameters on stack bit if parameters are not in their original
14101 registers, regardless of whether they are on the stack? Xlc
14102 seems to set the bit when not optimizing. */
14103 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
14105 if (! optional_tbtab
)
14108 /* Optional fields follow. Some are variable length. */
14110 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14111 11 double float. */
14112 /* There is an entry for each parameter in a register, in the order that
14113 they occur in the parameter list. Any intervening arguments on the
14114 stack are ignored. If the list overflows a long (max possible length
14115 34 bits) then completely leave off all elements that don't fit. */
14116 /* Only emit this long if there was at least one parameter. */
14117 if (fixed_parms
|| float_parms
)
14118 fprintf (file
, "\t.long %d\n", parm_info
);
14120 /* Offset from start of code to tb table. */
14121 fputs ("\t.long ", file
);
14122 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
14124 RS6000_OUTPUT_BASENAME (file
, fname
);
14126 assemble_name (file
, fname
);
14128 rs6000_output_function_entry (file
, fname
);
14131 /* Interrupt handler mask. */
14132 /* Omit this long, since we never set the interrupt handler bit
14135 /* Number of CTL (controlled storage) anchors. */
14136 /* Omit this long, since the has_ctl bit is never set above. */
14138 /* Displacement into stack of each CTL anchor. */
14139 /* Omit this list of longs, because there are no CTL anchors. */
14141 /* Length of function name. */
14144 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
14146 /* Function name. */
14147 assemble_string (fname
, strlen (fname
));
14149 /* Register for alloca automatic storage; this is always reg 31.
14150 Only emit this if the alloca bit was set above. */
14151 if (frame_pointer_needed
)
14152 fputs ("\t.byte 31\n", file
);
14154 fputs ("\t.align 2\n", file
);
14158 /* A C compound statement that outputs the assembler code for a thunk
14159 function, used to implement C++ virtual function calls with
14160 multiple inheritance. The thunk acts as a wrapper around a virtual
14161 function, adjusting the implicit object parameter before handing
14162 control off to the real function.
14164 First, emit code to add the integer DELTA to the location that
14165 contains the incoming first argument. Assume that this argument
14166 contains a pointer, and is the one used to pass the `this' pointer
14167 in C++. This is the incoming argument *before* the function
14168 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14169 values of all other incoming arguments.
14171 After the addition, emit code to jump to FUNCTION, which is a
14172 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14173 not touch the return address. Hence returning from FUNCTION will
14174 return to whoever called the current `thunk'.
14176 The effect must be as if FUNCTION had been called directly with the
14177 adjusted first argument. This macro is responsible for emitting
14178 all of the code for a thunk function; output_function_prologue()
14179 and output_function_epilogue() are not invoked.
14181 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14182 been extracted from it.) It might possibly be useful on some
14183 targets, but probably not.
14185 If you do not define this macro, the target-independent code in the
14186 C++ frontend will generate a less efficient heavyweight thunk that
14187 calls FUNCTION instead of jumping to it. The generic approach does
14188 not support varargs. */
14191 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
14192 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
14195 rtx
this, insn
, funexp
;
14197 reload_completed
= 1;
14198 epilogue_completed
= 1;
14199 no_new_pseudos
= 1;
14200 reset_block_changes ();
14202 /* Mark the end of the (empty) prologue. */
14203 emit_note (NOTE_INSN_PROLOGUE_END
);
14205 /* Find the "this" pointer. If the function returns a structure,
14206 the structure return pointer is in r3. */
14207 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
14208 this = gen_rtx_REG (Pmode
, 4);
14210 this = gen_rtx_REG (Pmode
, 3);
14212 /* Apply the constant offset, if required. */
14215 rtx delta_rtx
= GEN_INT (delta
);
14216 emit_insn (TARGET_32BIT
14217 ? gen_addsi3 (this, this, delta_rtx
)
14218 : gen_adddi3 (this, this, delta_rtx
));
14221 /* Apply the offset from the vtable, if required. */
14224 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
14225 rtx tmp
= gen_rtx_REG (Pmode
, 12);
14227 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
14228 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
14230 emit_insn (TARGET_32BIT
14231 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
14232 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
14233 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
14237 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
14239 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
14241 emit_insn (TARGET_32BIT
14242 ? gen_addsi3 (this, this, tmp
)
14243 : gen_adddi3 (this, this, tmp
));
14246 /* Generate a tail call to the target function. */
14247 if (!TREE_USED (function
))
14249 assemble_external (function
);
14250 TREE_USED (function
) = 1;
14252 funexp
= XEXP (DECL_RTL (function
), 0);
14253 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
14256 if (MACHOPIC_INDIRECT
)
14257 funexp
= machopic_indirect_call_target (funexp
);
14260 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14261 generate sibcall RTL explicitly to avoid constraint abort. */
14262 insn
= emit_call_insn (
14263 gen_rtx_PARALLEL (VOIDmode
,
14265 gen_rtx_CALL (VOIDmode
,
14266 funexp
, const0_rtx
),
14267 gen_rtx_USE (VOIDmode
, const0_rtx
),
14268 gen_rtx_USE (VOIDmode
,
14269 gen_rtx_REG (SImode
,
14270 LINK_REGISTER_REGNUM
)),
14271 gen_rtx_RETURN (VOIDmode
))));
14272 SIBLING_CALL_P (insn
) = 1;
14275 /* Run just enough of rest_of_compilation to get the insns emitted.
14276 There's not really enough bulk here to make other passes such as
14277 instruction scheduling worth while. Note that use_thunk calls
14278 assemble_start_function and assemble_end_function. */
14279 insn
= get_insns ();
14280 insn_locators_initialize ();
14281 shorten_branches (insn
);
14282 final_start_function (insn
, file
, 1);
14283 final (insn
, file
, 1);
14284 final_end_function ();
14286 reload_completed
= 0;
14287 epilogue_completed
= 0;
14288 no_new_pseudos
= 0;
14291 /* A quick summary of the various types of 'constant-pool tables'
14294 Target Flags Name One table per
14295 AIX (none) AIX TOC object file
14296 AIX -mfull-toc AIX TOC object file
14297 AIX -mminimal-toc AIX minimal TOC translation unit
14298 SVR4/EABI (none) SVR4 SDATA object file
14299 SVR4/EABI -fpic SVR4 pic object file
14300 SVR4/EABI -fPIC SVR4 PIC translation unit
14301 SVR4/EABI -mrelocatable EABI TOC function
14302 SVR4/EABI -maix AIX TOC object file
14303 SVR4/EABI -maix -mminimal-toc
14304 AIX minimal TOC translation unit
14306 Name Reg. Set by entries contains:
14307 made by addrs? fp? sum?
14309 AIX TOC 2 crt0 as Y option option
14310 AIX minimal TOC 30 prolog gcc Y Y option
14311 SVR4 SDATA 13 crt0 gcc N Y N
14312 SVR4 pic 30 prolog ld Y not yet N
14313 SVR4 PIC 30 prolog gcc Y option option
14314 EABI TOC 30 prolog gcc Y option option
14318 /* Hash functions for the hash table. */
14321 rs6000_hash_constant (rtx k
)
14323 enum rtx_code code
= GET_CODE (k
);
14324 enum machine_mode mode
= GET_MODE (k
);
14325 unsigned result
= (code
<< 3) ^ mode
;
14326 const char *format
;
14329 format
= GET_RTX_FORMAT (code
);
14330 flen
= strlen (format
);
14336 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
14339 if (mode
!= VOIDmode
)
14340 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
14352 for (; fidx
< flen
; fidx
++)
14353 switch (format
[fidx
])
14358 const char *str
= XSTR (k
, fidx
);
14359 len
= strlen (str
);
14360 result
= result
* 613 + len
;
14361 for (i
= 0; i
< len
; i
++)
14362 result
= result
* 613 + (unsigned) str
[i
];
14367 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
14371 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
14374 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
14375 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
14379 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
14380 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
14394 toc_hash_function (const void *hash_entry
)
14396 const struct toc_hash_struct
*thc
=
14397 (const struct toc_hash_struct
*) hash_entry
;
14398 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
14401 /* Compare H1 and H2 for equivalence. */
14404 toc_hash_eq (const void *h1
, const void *h2
)
14406 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
14407 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
14409 if (((const struct toc_hash_struct
*) h1
)->key_mode
14410 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
14413 return rtx_equal_p (r1
, r2
);
14416 /* These are the names given by the C++ front-end to vtables, and
14417 vtable-like objects. Ideally, this logic should not be here;
14418 instead, there should be some programmatic way of inquiring as
14419 to whether or not an object is a vtable. */
14421 #define VTABLE_NAME_P(NAME) \
14422 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
14423 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14424 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14425 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14426 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14429 rs6000_output_symbol_ref (FILE *file
, rtx x
)
14431 /* Currently C++ toc references to vtables can be emitted before it
14432 is decided whether the vtable is public or private. If this is
14433 the case, then the linker will eventually complain that there is
14434 a reference to an unknown section. Thus, for vtables only,
14435 we emit the TOC reference to reference the symbol and not the
14437 const char *name
= XSTR (x
, 0);
14439 if (VTABLE_NAME_P (name
))
14441 RS6000_OUTPUT_BASENAME (file
, name
);
14444 assemble_name (file
, name
);
14447 /* Output a TOC entry. We derive the entry name from what is being
14451 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
14454 const char *name
= buf
;
14455 const char *real_name
;
14462 /* When the linker won't eliminate them, don't output duplicate
14463 TOC entries (this happens on AIX if there is any kind of TOC,
14464 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14466 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
14468 struct toc_hash_struct
*h
;
14471 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14472 time because GGC is not initialized at that point. */
14473 if (toc_hash_table
== NULL
)
14474 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
14475 toc_hash_eq
, NULL
);
14477 h
= ggc_alloc (sizeof (*h
));
14479 h
->key_mode
= mode
;
14480 h
->labelno
= labelno
;
14482 found
= htab_find_slot (toc_hash_table
, h
, 1);
14483 if (*found
== NULL
)
14485 else /* This is indeed a duplicate.
14486 Set this label equal to that label. */
14488 fputs ("\t.set ", file
);
14489 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
14490 fprintf (file
, "%d,", labelno
);
14491 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
14492 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
14498 /* If we're going to put a double constant in the TOC, make sure it's
14499 aligned properly when strict alignment is on. */
14500 if (GET_CODE (x
) == CONST_DOUBLE
14501 && STRICT_ALIGNMENT
14502 && GET_MODE_BITSIZE (mode
) >= 64
14503 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
14504 ASM_OUTPUT_ALIGN (file
, 3);
14507 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
14509 /* Handle FP constants specially. Note that if we have a minimal
14510 TOC, things we put here aren't actually in the TOC, so we can allow
14512 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == TFmode
)
14514 REAL_VALUE_TYPE rv
;
14517 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
14518 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
14522 if (TARGET_MINIMAL_TOC
)
14523 fputs (DOUBLE_INT_ASM_OP
, file
);
14525 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14526 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14527 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14528 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
14529 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14530 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14535 if (TARGET_MINIMAL_TOC
)
14536 fputs ("\t.long ", file
);
14538 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14539 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14540 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14541 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14542 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
14543 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
14547 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
14549 REAL_VALUE_TYPE rv
;
14552 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
14553 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
14557 if (TARGET_MINIMAL_TOC
)
14558 fputs (DOUBLE_INT_ASM_OP
, file
);
14560 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
14561 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14562 fprintf (file
, "0x%lx%08lx\n",
14563 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14568 if (TARGET_MINIMAL_TOC
)
14569 fputs ("\t.long ", file
);
14571 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
14572 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14573 fprintf (file
, "0x%lx,0x%lx\n",
14574 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
14578 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
14580 REAL_VALUE_TYPE rv
;
14583 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
14584 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
14588 if (TARGET_MINIMAL_TOC
)
14589 fputs (DOUBLE_INT_ASM_OP
, file
);
14591 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
14592 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
14597 if (TARGET_MINIMAL_TOC
)
14598 fputs ("\t.long ", file
);
14600 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
14601 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
14605 else if (GET_MODE (x
) == VOIDmode
14606 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
14608 unsigned HOST_WIDE_INT low
;
14609 HOST_WIDE_INT high
;
14611 if (GET_CODE (x
) == CONST_DOUBLE
)
14613 low
= CONST_DOUBLE_LOW (x
);
14614 high
= CONST_DOUBLE_HIGH (x
);
14617 #if HOST_BITS_PER_WIDE_INT == 32
14620 high
= (low
& 0x80000000) ? ~0 : 0;
14624 low
= INTVAL (x
) & 0xffffffff;
14625 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
14629 /* TOC entries are always Pmode-sized, but since this
14630 is a bigendian machine then if we're putting smaller
14631 integer constants in the TOC we have to pad them.
14632 (This is still a win over putting the constants in
14633 a separate constant pool, because then we'd have
14634 to have both a TOC entry _and_ the actual constant.)
14636 For a 32-bit target, CONST_INT values are loaded and shifted
14637 entirely within `low' and can be stored in one TOC entry. */
14639 if (TARGET_64BIT
&& POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
14640 abort ();/* It would be easy to make this work, but it doesn't now. */
14642 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
14644 #if HOST_BITS_PER_WIDE_INT == 32
14645 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
14646 POINTER_SIZE
, &low
, &high
, 0);
14649 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
14650 high
= (HOST_WIDE_INT
) low
>> 32;
14657 if (TARGET_MINIMAL_TOC
)
14658 fputs (DOUBLE_INT_ASM_OP
, file
);
14660 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
14661 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14662 fprintf (file
, "0x%lx%08lx\n",
14663 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14668 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
14670 if (TARGET_MINIMAL_TOC
)
14671 fputs ("\t.long ", file
);
14673 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
14674 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14675 fprintf (file
, "0x%lx,0x%lx\n",
14676 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
14680 if (TARGET_MINIMAL_TOC
)
14681 fputs ("\t.long ", file
);
14683 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
14684 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
14690 if (GET_CODE (x
) == CONST
)
14692 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
14695 base
= XEXP (XEXP (x
, 0), 0);
14696 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
14699 if (GET_CODE (base
) == SYMBOL_REF
)
14700 name
= XSTR (base
, 0);
14701 else if (GET_CODE (base
) == LABEL_REF
)
14702 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (base
, 0)));
14703 else if (GET_CODE (base
) == CODE_LABEL
)
14704 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
14708 real_name
= (*targetm
.strip_name_encoding
) (name
);
14709 if (TARGET_MINIMAL_TOC
)
14710 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
14713 fprintf (file
, "\t.tc %s", real_name
);
14716 fprintf (file
, ".N%d", - offset
);
14718 fprintf (file
, ".P%d", offset
);
14720 fputs ("[TC],", file
);
14723 /* Currently C++ toc references to vtables can be emitted before it
14724 is decided whether the vtable is public or private. If this is
14725 the case, then the linker will eventually complain that there is
14726 a TOC reference to an unknown section. Thus, for vtables only,
14727 we emit the TOC reference to reference the symbol and not the
14729 if (VTABLE_NAME_P (name
))
14731 RS6000_OUTPUT_BASENAME (file
, name
);
14733 fprintf (file
, "%d", offset
);
14734 else if (offset
> 0)
14735 fprintf (file
, "+%d", offset
);
14738 output_addr_const (file
, x
);
14742 /* Output an assembler pseudo-op to write an ASCII string of N characters
14743 starting at P to FILE.
14745 On the RS/6000, we have to do this using the .byte operation and
14746 write out special characters outside the quoted string.
14747 Also, the assembler is broken; very long strings are truncated,
14748 so we must artificially break them up early. */
14751 output_ascii (FILE *file
, const char *p
, int n
)
14754 int i
, count_string
;
14755 const char *for_string
= "\t.byte \"";
14756 const char *for_decimal
= "\t.byte ";
14757 const char *to_close
= NULL
;
14760 for (i
= 0; i
< n
; i
++)
14763 if (c
>= ' ' && c
< 0177)
14766 fputs (for_string
, file
);
14769 /* Write two quotes to get one. */
14777 for_decimal
= "\"\n\t.byte ";
14781 if (count_string
>= 512)
14783 fputs (to_close
, file
);
14785 for_string
= "\t.byte \"";
14786 for_decimal
= "\t.byte ";
14794 fputs (for_decimal
, file
);
14795 fprintf (file
, "%d", c
);
14797 for_string
= "\n\t.byte \"";
14798 for_decimal
= ", ";
14804 /* Now close the string if we have written one. Then end the line. */
14806 fputs (to_close
, file
);
14809 /* Generate a unique section name for FILENAME for a section type
14810 represented by SECTION_DESC. Output goes into BUF.
14812 SECTION_DESC can be any string, as long as it is different for each
14813 possible section type.
14815 We name the section in the same manner as xlc. The name begins with an
14816 underscore followed by the filename (after stripping any leading directory
14817 names) with the last period replaced by the string SECTION_DESC. If
14818 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14822 rs6000_gen_section_name (char **buf
, const char *filename
,
14823 const char *section_desc
)
14825 const char *q
, *after_last_slash
, *last_period
= 0;
14829 after_last_slash
= filename
;
14830 for (q
= filename
; *q
; q
++)
14833 after_last_slash
= q
+ 1;
14834 else if (*q
== '.')
14838 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
14839 *buf
= (char *) xmalloc (len
);
14844 for (q
= after_last_slash
; *q
; q
++)
14846 if (q
== last_period
)
14848 strcpy (p
, section_desc
);
14849 p
+= strlen (section_desc
);
14853 else if (ISALNUM (*q
))
14857 if (last_period
== 0)
14858 strcpy (p
, section_desc
);
14863 /* Emit profile function. */
14866 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
14868 if (TARGET_PROFILE_KERNEL
)
14871 if (DEFAULT_ABI
== ABI_AIX
)
14873 #ifndef NO_PROFILE_COUNTERS
14874 # define NO_PROFILE_COUNTERS 0
14876 if (NO_PROFILE_COUNTERS
)
14877 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
14881 const char *label_name
;
14884 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
14885 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
14886 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
14888 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
14892 else if (DEFAULT_ABI
== ABI_DARWIN
)
14894 const char *mcount_name
= RS6000_MCOUNT
;
14895 int caller_addr_regno
= LINK_REGISTER_REGNUM
;
14897 /* Be conservative and always set this, at least for now. */
14898 current_function_uses_pic_offset_table
= 1;
14901 /* For PIC code, set up a stub and collect the caller's address
14902 from r0, which is where the prologue puts it. */
14903 if (MACHOPIC_INDIRECT
14904 && current_function_uses_pic_offset_table
)
14905 caller_addr_regno
= 0;
14907 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
14909 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
14913 /* Write function profiler code. */
14916 output_function_profiler (FILE *file
, int labelno
)
14921 switch (DEFAULT_ABI
)
14930 warning ("no profiling of 64-bit code for this ABI");
14933 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
14934 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
14937 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
14938 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
14939 reg_names
[0], save_lr
, reg_names
[1]);
14940 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
14941 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
14942 assemble_name (file
, buf
);
14943 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
14945 else if (flag_pic
> 1)
14947 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
14948 reg_names
[0], save_lr
, reg_names
[1]);
14949 /* Now, we need to get the address of the label. */
14950 fputs ("\tbl 1f\n\t.long ", file
);
14951 assemble_name (file
, buf
);
14952 fputs ("-.\n1:", file
);
14953 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
14954 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
14955 reg_names
[0], reg_names
[11]);
14956 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
14957 reg_names
[0], reg_names
[0], reg_names
[11]);
14961 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
14962 assemble_name (file
, buf
);
14963 fputs ("@ha\n", file
);
14964 asm_fprintf (file
, "\t{st|stw} %s,%d(%s)\n",
14965 reg_names
[0], save_lr
, reg_names
[1]);
14966 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
14967 assemble_name (file
, buf
);
14968 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
14971 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
14972 fprintf (file
, "\tbl %s%s\n",
14973 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
14978 if (!TARGET_PROFILE_KERNEL
)
14980 /* Don't do anything, done in output_profile_hook (). */
14987 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
14988 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
14990 if (cfun
->static_chain_decl
!= NULL
)
14992 asm_fprintf (file
, "\tstd %s,24(%s)\n",
14993 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
14994 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
14995 asm_fprintf (file
, "\tld %s,24(%s)\n",
14996 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
14999 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
15006 /* Power4 load update and store update instructions are cracked into a
15007 load or store and an integer insn which are executed in the same cycle.
15008 Branches have their own dispatch slot which does not count against the
15009 GCC issue rate, but it changes the program flow so there are no other
15010 instructions to issue in this cycle. */
15013 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
15014 int verbose ATTRIBUTE_UNUSED
,
15015 rtx insn
, int more
)
15017 if (GET_CODE (PATTERN (insn
)) == USE
15018 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15021 if (rs6000_sched_groups
)
15023 if (is_microcoded_insn (insn
))
15025 else if (is_cracked_insn (insn
))
15026 return more
> 2 ? more
- 2 : 0;
15032 /* Adjust the cost of a scheduling dependency. Return the new cost of
15033 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15036 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
15038 if (! recog_memoized (insn
))
15041 if (REG_NOTE_KIND (link
) != 0)
15044 if (REG_NOTE_KIND (link
) == 0)
15046 /* Data dependency; DEP_INSN writes a register that INSN reads
15047 some cycles later. */
15049 /* Separate a load from a narrower, dependent store. */
15050 if (rs6000_sched_groups
15051 && GET_CODE (PATTERN (insn
)) == SET
15052 && GET_CODE (PATTERN (dep_insn
)) == SET
15053 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
15054 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
15055 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
15056 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
15059 switch (get_attr_type (insn
))
15062 /* Tell the first scheduling pass about the latency between
15063 a mtctr and bctr (and mtlr and br/blr). The first
15064 scheduling pass will not know about this latency since
15065 the mtctr instruction, which has the latency associated
15066 to it, will be generated by reload. */
15067 return TARGET_POWER
? 5 : 4;
15069 /* Leave some extra cycles between a compare and its
15070 dependent branch, to inhibit expensive mispredicts. */
15071 if ((rs6000_cpu_attr
== CPU_PPC603
15072 || rs6000_cpu_attr
== CPU_PPC604
15073 || rs6000_cpu_attr
== CPU_PPC604E
15074 || rs6000_cpu_attr
== CPU_PPC620
15075 || rs6000_cpu_attr
== CPU_PPC630
15076 || rs6000_cpu_attr
== CPU_PPC750
15077 || rs6000_cpu_attr
== CPU_PPC7400
15078 || rs6000_cpu_attr
== CPU_PPC7450
15079 || rs6000_cpu_attr
== CPU_POWER4
15080 || rs6000_cpu_attr
== CPU_POWER5
)
15081 && recog_memoized (dep_insn
)
15082 && (INSN_CODE (dep_insn
) >= 0)
15083 && (get_attr_type (dep_insn
) == TYPE_CMP
15084 || get_attr_type (dep_insn
) == TYPE_COMPARE
15085 || get_attr_type (dep_insn
) == TYPE_DELAYED_COMPARE
15086 || get_attr_type (dep_insn
) == TYPE_IMUL_COMPARE
15087 || get_attr_type (dep_insn
) == TYPE_LMUL_COMPARE
15088 || get_attr_type (dep_insn
) == TYPE_FPCOMPARE
15089 || get_attr_type (dep_insn
) == TYPE_CR_LOGICAL
15090 || get_attr_type (dep_insn
) == TYPE_DELAYED_CR
))
15095 /* Fall out to return default cost. */
15101 /* The function returns a true if INSN is microcoded.
15102 Return false otherwise. */
15105 is_microcoded_insn (rtx insn
)
15107 if (!insn
|| !INSN_P (insn
)
15108 || GET_CODE (PATTERN (insn
)) == USE
15109 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15112 if (rs6000_sched_groups
)
15114 enum attr_type type
= get_attr_type (insn
);
15115 if (type
== TYPE_LOAD_EXT_U
15116 || type
== TYPE_LOAD_EXT_UX
15117 || type
== TYPE_LOAD_UX
15118 || type
== TYPE_STORE_UX
15119 || type
== TYPE_MFCR
)
15126 /* The function returns a nonzero value if INSN can be scheduled only
15127 as the first insn in a dispatch group ("dispatch-slot restricted").
15128 In this case, the returned value indicates how many dispatch slots
15129 the insn occupies (at the beginning of the group).
15130 Return 0 otherwise. */
15133 is_dispatch_slot_restricted (rtx insn
)
15135 enum attr_type type
;
15137 if (!rs6000_sched_groups
)
15141 || insn
== NULL_RTX
15142 || GET_CODE (insn
) == NOTE
15143 || GET_CODE (PATTERN (insn
)) == USE
15144 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15147 type
= get_attr_type (insn
);
15154 case TYPE_DELAYED_CR
:
15155 case TYPE_CR_LOGICAL
:
15163 if (rs6000_cpu
== PROCESSOR_POWER5
15164 && is_cracked_insn (insn
))
15170 /* The function returns true if INSN is cracked into 2 instructions
15171 by the processor (and therefore occupies 2 issue slots). */
15174 is_cracked_insn (rtx insn
)
15176 if (!insn
|| !INSN_P (insn
)
15177 || GET_CODE (PATTERN (insn
)) == USE
15178 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15181 if (rs6000_sched_groups
)
15183 enum attr_type type
= get_attr_type (insn
);
15184 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
15185 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
15186 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
15187 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
15188 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
15189 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
15190 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
15191 || type
== TYPE_INSERT_WORD
)
15198 /* The function returns true if INSN can be issued only from
15199 the branch slot. */
15202 is_branch_slot_insn (rtx insn
)
15204 if (!insn
|| !INSN_P (insn
)
15205 || GET_CODE (PATTERN (insn
)) == USE
15206 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
15209 if (rs6000_sched_groups
)
15211 enum attr_type type
= get_attr_type (insn
);
15212 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
15220 /* A C statement (sans semicolon) to update the integer scheduling
15221 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15222 INSN earlier, reduce the priority to execute INSN later. Do not
15223 define this macro if you do not need to adjust the scheduling
15224 priorities of insns. */
15227 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
15229 /* On machines (like the 750) which have asymmetric integer units,
15230 where one integer unit can do multiply and divides and the other
15231 can't, reduce the priority of multiply/divide so it is scheduled
15232 before other integer operations. */
15235 if (! INSN_P (insn
))
15238 if (GET_CODE (PATTERN (insn
)) == USE
)
15241 switch (rs6000_cpu_attr
) {
15243 switch (get_attr_type (insn
))
15250 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
15251 priority
, priority
);
15252 if (priority
>= 0 && priority
< 0x01000000)
15259 if (is_dispatch_slot_restricted (insn
)
15260 && reload_completed
15261 && current_sched_info
->sched_max_insns_priority
15262 && rs6000_sched_restricted_insns_priority
)
15265 /* Prioritize insns that can be dispatched only in the first
15267 if (rs6000_sched_restricted_insns_priority
== 1)
15268 /* Attach highest priority to insn. This means that in
15269 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15270 precede 'priority' (critical path) considerations. */
15271 return current_sched_info
->sched_max_insns_priority
;
15272 else if (rs6000_sched_restricted_insns_priority
== 2)
15273 /* Increase priority of insn by a minimal amount. This means that in
15274 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15275 considerations precede dispatch-slot restriction considerations. */
15276 return (priority
+ 1);
15282 /* Return how many instructions the machine can issue per cycle. */
15285 rs6000_issue_rate (void)
15287 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15288 if (!reload_completed
)
15291 switch (rs6000_cpu_attr
) {
15292 case CPU_RIOS1
: /* ? */
15294 case CPU_PPC601
: /* ? */
15317 /* Return how many instructions to look ahead for better insn
15321 rs6000_use_sched_lookahead (void)
15323 if (rs6000_cpu_attr
== CPU_PPC8540
)
15328 /* Determine is PAT refers to memory. */
15331 is_mem_ref (rtx pat
)
15337 if (GET_CODE (pat
) == MEM
)
15340 /* Recursively process the pattern. */
15341 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
15343 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
15346 ret
|= is_mem_ref (XEXP (pat
, i
));
15347 else if (fmt
[i
] == 'E')
15348 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
15349 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
15355 /* Determine if PAT is a PATTERN of a load insn. */
15358 is_load_insn1 (rtx pat
)
15360 if (!pat
|| pat
== NULL_RTX
)
15363 if (GET_CODE (pat
) == SET
)
15364 return is_mem_ref (SET_SRC (pat
));
15366 if (GET_CODE (pat
) == PARALLEL
)
15370 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15371 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
15378 /* Determine if INSN loads from memory. */
15381 is_load_insn (rtx insn
)
15383 if (!insn
|| !INSN_P (insn
))
15386 if (GET_CODE (insn
) == CALL_INSN
)
15389 return is_load_insn1 (PATTERN (insn
));
15392 /* Determine if PAT is a PATTERN of a store insn. */
15395 is_store_insn1 (rtx pat
)
15397 if (!pat
|| pat
== NULL_RTX
)
15400 if (GET_CODE (pat
) == SET
)
15401 return is_mem_ref (SET_DEST (pat
));
15403 if (GET_CODE (pat
) == PARALLEL
)
15407 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15408 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
15415 /* Determine if INSN stores to memory. */
15418 is_store_insn (rtx insn
)
15420 if (!insn
|| !INSN_P (insn
))
15423 return is_store_insn1 (PATTERN (insn
));
15426 /* Returns whether the dependence between INSN and NEXT is considered
15427 costly by the given target. */
15430 rs6000_is_costly_dependence (rtx insn
, rtx next
, rtx link
, int cost
,
15433 /* If the flag is not enabled - no dependence is considered costly;
15434 allow all dependent insns in the same group.
15435 This is the most aggressive option. */
15436 if (rs6000_sched_costly_dep
== no_dep_costly
)
15439 /* If the flag is set to 1 - a dependence is always considered costly;
15440 do not allow dependent instructions in the same group.
15441 This is the most conservative option. */
15442 if (rs6000_sched_costly_dep
== all_deps_costly
)
15445 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
15446 && is_load_insn (next
)
15447 && is_store_insn (insn
))
15448 /* Prevent load after store in the same group. */
15451 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
15452 && is_load_insn (next
)
15453 && is_store_insn (insn
)
15454 && (!link
|| (int) REG_NOTE_KIND (link
) == 0))
15455 /* Prevent load after store in the same group if it is a true
15459 /* The flag is set to X; dependences with latency >= X are considered costly,
15460 and will not be scheduled in the same group. */
15461 if (rs6000_sched_costly_dep
<= max_dep_latency
15462 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
15468 /* Return the next insn after INSN that is found before TAIL is reached,
15469 skipping any "non-active" insns - insns that will not actually occupy
15470 an issue slot. Return NULL_RTX if such an insn is not found. */
15473 get_next_active_insn (rtx insn
, rtx tail
)
15477 if (!insn
|| insn
== tail
)
15480 next_insn
= NEXT_INSN (insn
);
15483 && next_insn
!= tail
15484 && (GET_CODE (next_insn
) == NOTE
15485 || GET_CODE (PATTERN (next_insn
)) == USE
15486 || GET_CODE (PATTERN (next_insn
)) == CLOBBER
))
15488 next_insn
= NEXT_INSN (next_insn
);
15491 if (!next_insn
|| next_insn
== tail
)
15497 /* Return whether the presence of INSN causes a dispatch group termination
15498 of group WHICH_GROUP.
15500 If WHICH_GROUP == current_group, this function will return true if INSN
15501 causes the termination of the current group (i.e, the dispatch group to
15502 which INSN belongs). This means that INSN will be the last insn in the
15503 group it belongs to.
15505 If WHICH_GROUP == previous_group, this function will return true if INSN
15506 causes the termination of the previous group (i.e, the dispatch group that
15507 precedes the group to which INSN belongs). This means that INSN will be
15508 the first insn in the group it belongs to). */
15511 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
15513 enum attr_type type
;
15518 type
= get_attr_type (insn
);
15520 if (is_microcoded_insn (insn
))
15523 if (which_group
== current_group
)
15525 if (is_branch_slot_insn (insn
))
15529 else if (which_group
== previous_group
)
15531 if (is_dispatch_slot_restricted (insn
))
15539 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15540 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15543 is_costly_group (rtx
*group_insns
, rtx next_insn
)
15548 int issue_rate
= rs6000_issue_rate ();
15550 for (i
= 0; i
< issue_rate
; i
++)
15552 rtx insn
= group_insns
[i
];
15555 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
15557 rtx next
= XEXP (link
, 0);
15558 if (next
== next_insn
)
15560 cost
= insn_cost (insn
, link
, next_insn
);
15561 if (rs6000_is_costly_dependence (insn
, next_insn
, link
, cost
, 0))
15570 /* Utility of the function redefine_groups.
15571 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15572 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15573 to keep it "far" (in a separate group) from GROUP_INSNS, following
15574 one of the following schemes, depending on the value of the flag
15575 -minsert_sched_nops = X:
15576 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15577 in order to force NEXT_INSN into a separate group.
15578 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15579 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15580 insertion (has a group just ended, how many vacant issue slots remain in the
15581 last group, and how many dispatch groups were encountered so far). */
15584 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
15585 rtx next_insn
, bool *group_end
, int can_issue_more
,
15590 int issue_rate
= rs6000_issue_rate ();
15591 bool end
= *group_end
;
15594 if (next_insn
== NULL_RTX
)
15595 return can_issue_more
;
15597 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
15598 return can_issue_more
;
15600 force
= is_costly_group (group_insns
, next_insn
);
15602 return can_issue_more
;
15604 if (sched_verbose
> 6)
15605 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
15606 *group_count
,can_issue_more
);
15608 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
15611 can_issue_more
= 0;
15613 /* Since only a branch can be issued in the last issue_slot, it is
15614 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15615 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15616 in this case the last nop will start a new group and the branch
15617 will be forced to the new group. */
15618 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
15621 while (can_issue_more
> 0)
15624 emit_insn_before (nop
, next_insn
);
15632 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
15634 int n_nops
= rs6000_sched_insert_nops
;
15636 /* Nops can't be issued from the branch slot, so the effective
15637 issue_rate for nops is 'issue_rate - 1'. */
15638 if (can_issue_more
== 0)
15639 can_issue_more
= issue_rate
;
15641 if (can_issue_more
== 0)
15643 can_issue_more
= issue_rate
- 1;
15646 for (i
= 0; i
< issue_rate
; i
++)
15648 group_insns
[i
] = 0;
15655 emit_insn_before (nop
, next_insn
);
15656 if (can_issue_more
== issue_rate
- 1) /* new group begins */
15659 if (can_issue_more
== 0)
15661 can_issue_more
= issue_rate
- 1;
15664 for (i
= 0; i
< issue_rate
; i
++)
15666 group_insns
[i
] = 0;
15672 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15675 /* Is next_insn going to start a new group? */
15678 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
15679 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
15680 || (can_issue_more
< issue_rate
&&
15681 insn_terminates_group_p (next_insn
, previous_group
)));
15682 if (*group_end
&& end
)
15685 if (sched_verbose
> 6)
15686 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
15687 *group_count
, can_issue_more
);
15688 return can_issue_more
;
15691 return can_issue_more
;
15694 /* This function tries to synch the dispatch groups that the compiler "sees"
15695 with the dispatch groups that the processor dispatcher is expected to
15696 form in practice. It tries to achieve this synchronization by forcing the
15697 estimated processor grouping on the compiler (as opposed to the function
15698 'pad_goups' which tries to force the scheduler's grouping on the processor).
15700 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15701 examines the (estimated) dispatch groups that will be formed by the processor
15702 dispatcher. It marks these group boundaries to reflect the estimated
15703 processor grouping, overriding the grouping that the scheduler had marked.
15704 Depending on the value of the flag '-minsert-sched-nops' this function can
15705 force certain insns into separate groups or force a certain distance between
15706 them by inserting nops, for example, if there exists a "costly dependence"
15709 The function estimates the group boundaries that the processor will form as
15710 folllows: It keeps track of how many vacant issue slots are available after
15711 each insn. A subsequent insn will start a new group if one of the following
15713 - no more vacant issue slots remain in the current dispatch group.
15714 - only the last issue slot, which is the branch slot, is vacant, but the next
15715 insn is not a branch.
15716 - only the last 2 or less issue slots, including the branch slot, are vacant,
15717 which means that a cracked insn (which occupies two issue slots) can't be
15718 issued in this group.
15719 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15720 start a new group. */
15723 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
15725 rtx insn
, next_insn
;
15727 int can_issue_more
;
15730 int group_count
= 0;
15734 issue_rate
= rs6000_issue_rate ();
15735 group_insns
= alloca (issue_rate
* sizeof (rtx
));
15736 for (i
= 0; i
< issue_rate
; i
++)
15738 group_insns
[i
] = 0;
15740 can_issue_more
= issue_rate
;
15742 insn
= get_next_active_insn (prev_head_insn
, tail
);
15745 while (insn
!= NULL_RTX
)
15747 slot
= (issue_rate
- can_issue_more
);
15748 group_insns
[slot
] = insn
;
15750 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
15751 if (insn_terminates_group_p (insn
, current_group
))
15752 can_issue_more
= 0;
15754 next_insn
= get_next_active_insn (insn
, tail
);
15755 if (next_insn
== NULL_RTX
)
15756 return group_count
+ 1;
15758 /* Is next_insn going to start a new group? */
15760 = (can_issue_more
== 0
15761 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
15762 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
15763 || (can_issue_more
< issue_rate
&&
15764 insn_terminates_group_p (next_insn
, previous_group
)));
15766 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
15767 next_insn
, &group_end
, can_issue_more
,
15773 can_issue_more
= 0;
15774 for (i
= 0; i
< issue_rate
; i
++)
15776 group_insns
[i
] = 0;
15780 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
15781 PUT_MODE (next_insn
, VOIDmode
);
15782 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
15783 PUT_MODE (next_insn
, TImode
);
15786 if (can_issue_more
== 0)
15787 can_issue_more
= issue_rate
;
15790 return group_count
;
15793 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15794 dispatch group boundaries that the scheduler had marked. Pad with nops
15795 any dispatch groups which have vacant issue slots, in order to force the
15796 scheduler's grouping on the processor dispatcher. The function
15797 returns the number of dispatch groups found. */
15800 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
15802 rtx insn
, next_insn
;
15805 int can_issue_more
;
15807 int group_count
= 0;
15809 /* Initialize issue_rate. */
15810 issue_rate
= rs6000_issue_rate ();
15811 can_issue_more
= issue_rate
;
15813 insn
= get_next_active_insn (prev_head_insn
, tail
);
15814 next_insn
= get_next_active_insn (insn
, tail
);
15816 while (insn
!= NULL_RTX
)
15819 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
15821 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
15823 if (next_insn
== NULL_RTX
)
15828 /* If the scheduler had marked group termination at this location
15829 (between insn and next_indn), and neither insn nor next_insn will
15830 force group termination, pad the group with nops to force group
15833 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
15834 && !insn_terminates_group_p (insn
, current_group
)
15835 && !insn_terminates_group_p (next_insn
, previous_group
))
15837 if (!is_branch_slot_insn (next_insn
))
15840 while (can_issue_more
)
15843 emit_insn_before (nop
, next_insn
);
15848 can_issue_more
= issue_rate
;
15853 next_insn
= get_next_active_insn (insn
, tail
);
15856 return group_count
;
15859 /* The following function is called at the end of scheduling BB.
15860 After reload, it inserts nops at insn group bundling. */
15863 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
15868 fprintf (dump
, "=== Finishing schedule.\n");
15870 if (reload_completed
&& rs6000_sched_groups
)
15872 if (rs6000_sched_insert_nops
== sched_finish_none
)
15875 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
15876 n_groups
= pad_groups (dump
, sched_verbose
,
15877 current_sched_info
->prev_head
,
15878 current_sched_info
->next_tail
);
15880 n_groups
= redefine_groups (dump
, sched_verbose
,
15881 current_sched_info
->prev_head
,
15882 current_sched_info
->next_tail
);
15884 if (sched_verbose
>= 6)
15886 fprintf (dump
, "ngroups = %d\n", n_groups
);
15887 print_rtl (dump
, current_sched_info
->prev_head
);
15888 fprintf (dump
, "Done finish_sched\n");
15893 /* Length in units of the trampoline for entering a nested function. */
15896 rs6000_trampoline_size (void)
15900 switch (DEFAULT_ABI
)
15906 ret
= (TARGET_32BIT
) ? 12 : 24;
15911 ret
= (TARGET_32BIT
) ? 40 : 48;
15918 /* Emit RTL insns to initialize the variable parts of a trampoline.
15919 FNADDR is an RTX for the address of the function's pure code.
15920 CXT is an RTX for the static chain value for the function. */
15923 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
15925 enum machine_mode pmode
= Pmode
;
15926 int regsize
= (TARGET_32BIT
) ? 4 : 8;
15927 rtx ctx_reg
= force_reg (pmode
, cxt
);
15929 switch (DEFAULT_ABI
)
15934 /* Macros to shorten the code expansions below. */
15935 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
15936 #define MEM_PLUS(addr,offset) \
15937 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
15939 /* Under AIX, just build the 3 word function descriptor */
15942 rtx fn_reg
= gen_reg_rtx (pmode
);
15943 rtx toc_reg
= gen_reg_rtx (pmode
);
15944 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
15945 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
15946 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
15947 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
15948 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
15952 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15955 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
15956 FALSE
, VOIDmode
, 4,
15958 GEN_INT (rs6000_trampoline_size ()), SImode
,
15968 /* Table of valid machine attributes. */
15970 const struct attribute_spec rs6000_attribute_table
[] =
15972 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
15973 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
15974 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
15975 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
15976 #ifdef SUBTARGET_ATTRIBUTE_TABLE
15977 SUBTARGET_ATTRIBUTE_TABLE
,
15979 { NULL
, 0, 0, false, false, false, NULL
}
15982 /* Handle the "altivec" attribute. The attribute may have
15983 arguments as follows:
15985 __attribute__((altivec(vector__)))
15986 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15987 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15989 and may appear more than once (e.g., 'vector bool char') in a
15990 given declaration. */
15993 rs6000_handle_altivec_attribute (tree
*node
,
15994 tree name ATTRIBUTE_UNUSED
,
15996 int flags ATTRIBUTE_UNUSED
,
15997 bool *no_add_attrs
)
15999 tree type
= *node
, result
= NULL_TREE
;
16000 enum machine_mode mode
;
16003 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
16004 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
16005 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
16008 while (POINTER_TYPE_P (type
)
16009 || TREE_CODE (type
) == FUNCTION_TYPE
16010 || TREE_CODE (type
) == METHOD_TYPE
16011 || TREE_CODE (type
) == ARRAY_TYPE
)
16012 type
= TREE_TYPE (type
);
16014 mode
= TYPE_MODE (type
);
16016 /* Check for invalid AltiVec type qualifiers. */
16017 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
16020 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
16021 else if (rs6000_warn_altivec_long
)
16022 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
16024 else if (type
== long_long_unsigned_type_node
16025 || type
== long_long_integer_type_node
)
16026 error ("use of %<long long%> in AltiVec types is invalid");
16027 else if (type
== double_type_node
)
16028 error ("use of %<double%> in AltiVec types is invalid");
16029 else if (type
== long_double_type_node
)
16030 error ("use of %<long double%> in AltiVec types is invalid");
16031 else if (type
== boolean_type_node
)
16032 error ("use of boolean types in AltiVec types is invalid");
16033 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
16034 error ("use of %<complex%> in AltiVec types is invalid");
16036 switch (altivec_type
)
16039 unsigned_p
= TYPE_UNSIGNED (type
);
16043 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
16046 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
16049 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
16051 case SFmode
: result
= V4SF_type_node
; break;
16052 /* If the user says 'vector int bool', we may be handed the 'bool'
16053 attribute _before_ the 'vector' attribute, and so select the
16054 proper type in the 'b' case below. */
16055 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
16063 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
16064 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
16065 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
16072 case V8HImode
: result
= pixel_V8HI_type_node
;
16078 if (result
&& result
!= type
&& TYPE_READONLY (type
))
16079 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
16081 *no_add_attrs
= true; /* No need to hang on to the attribute. */
16084 *node
= reconstruct_complex_type (*node
, result
);
16089 /* AltiVec defines four built-in scalar types that serve as vector
16090 elements; we must teach the compiler how to mangle them. */
16092 static const char *
16093 rs6000_mangle_fundamental_type (tree type
)
16095 if (type
== bool_char_type_node
) return "U6__boolc";
16096 if (type
== bool_short_type_node
) return "U6__bools";
16097 if (type
== pixel_type_node
) return "u7__pixel";
16098 if (type
== bool_int_type_node
) return "U6__booli";
16100 /* For all other types, use normal C++ mangling. */
16104 /* Handle a "longcall" or "shortcall" attribute; arguments as in
16105 struct attribute_spec.handler. */
16108 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
16109 tree args ATTRIBUTE_UNUSED
,
16110 int flags ATTRIBUTE_UNUSED
,
16111 bool *no_add_attrs
)
16113 if (TREE_CODE (*node
) != FUNCTION_TYPE
16114 && TREE_CODE (*node
) != FIELD_DECL
16115 && TREE_CODE (*node
) != TYPE_DECL
)
16117 warning ("%qs attribute only applies to functions",
16118 IDENTIFIER_POINTER (name
));
16119 *no_add_attrs
= true;
16125 /* Set longcall attributes on all functions declared when
16126 rs6000_default_long_calls is true. */
16128 rs6000_set_default_type_attributes (tree type
)
16130 if (rs6000_default_long_calls
16131 && (TREE_CODE (type
) == FUNCTION_TYPE
16132 || TREE_CODE (type
) == METHOD_TYPE
))
16133 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
16135 TYPE_ATTRIBUTES (type
));
16138 /* Return a reference suitable for calling a function with the
16139 longcall attribute. */
16142 rs6000_longcall_ref (rtx call_ref
)
16144 const char *call_name
;
16147 if (GET_CODE (call_ref
) != SYMBOL_REF
)
16150 /* System V adds '.' to the internal name, so skip them. */
16151 call_name
= XSTR (call_ref
, 0);
16152 if (*call_name
== '.')
16154 while (*call_name
== '.')
16157 node
= get_identifier (call_name
);
16158 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
16161 return force_reg (Pmode
, call_ref
);
16164 #ifdef USING_ELFOS_H
16166 /* A C statement or statements to switch to the appropriate section
16167 for output of RTX in mode MODE. You can assume that RTX is some
16168 kind of constant in RTL. The argument MODE is redundant except in
16169 the case of a `const_int' rtx. Select the section by calling
16170 `text_section' or one of the alternatives for other sections.
16172 Do not define this macro if you put all constants in the read-only
16176 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
16177 unsigned HOST_WIDE_INT align
)
16179 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
16182 default_elf_select_rtx_section (mode
, x
, align
);
16185 /* A C statement or statements to switch to the appropriate
16186 section for output of DECL. DECL is either a `VAR_DECL' node
16187 or a constant of some sort. RELOC indicates whether forming
16188 the initial value of DECL requires link-time relocations. */
16191 rs6000_elf_select_section (tree decl
, int reloc
,
16192 unsigned HOST_WIDE_INT align
)
16194 /* Pretend that we're always building for a shared library when
16195 ABI_AIX, because otherwise we end up with dynamic relocations
16196 in read-only sections. This happens for function pointers,
16197 references to vtables in typeinfo, and probably other cases. */
16198 default_elf_select_section_1 (decl
, reloc
, align
,
16199 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
16202 /* A C statement to build up a unique section name, expressed as a
16203 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16204 RELOC indicates whether the initial value of EXP requires
16205 link-time relocations. If you do not define this macro, GCC will use
16206 the symbol name prefixed by `.' as the section name. Note - this
16207 macro can now be called for uninitialized data items as well as
16208 initialized data and functions. */
16211 rs6000_elf_unique_section (tree decl
, int reloc
)
16213 /* As above, pretend that we're always building for a shared library
16214 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16215 default_unique_section_1 (decl
, reloc
,
16216 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
16219 /* For a SYMBOL_REF, set generic flags and then perform some
16220 target-specific processing.
16222 When the AIX ABI is requested on a non-AIX system, replace the
16223 function name with the real name (with a leading .) rather than the
16224 function descriptor name. This saves a lot of overriding code to
16225 read the prefixes. */
16228 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
16230 default_encode_section_info (decl
, rtl
, first
);
16233 && TREE_CODE (decl
) == FUNCTION_DECL
16235 && DEFAULT_ABI
== ABI_AIX
)
16237 rtx sym_ref
= XEXP (rtl
, 0);
16238 size_t len
= strlen (XSTR (sym_ref
, 0));
16239 char *str
= alloca (len
+ 2);
16241 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
16242 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
16247 rs6000_elf_in_small_data_p (tree decl
)
16249 if (rs6000_sdata
== SDATA_NONE
)
16252 /* We want to merge strings, so we never consider them small data. */
16253 if (TREE_CODE (decl
) == STRING_CST
)
16256 /* Functions are never in the small data area. */
16257 if (TREE_CODE (decl
) == FUNCTION_DECL
)
16260 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
16262 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
16263 if (strcmp (section
, ".sdata") == 0
16264 || strcmp (section
, ".sdata2") == 0
16265 || strcmp (section
, ".sbss") == 0
16266 || strcmp (section
, ".sbss2") == 0
16267 || strcmp (section
, ".PPC.EMB.sdata0") == 0
16268 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
16273 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
16276 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
16277 /* If it's not public, and we're not going to reference it there,
16278 there's no need to put it in the small data section. */
16279 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
16286 #endif /* USING_ELFOS_H */
16289 /* Return a REG that occurs in ADDR with coefficient 1.
16290 ADDR can be effectively incremented by incrementing REG.
16292 r0 is special and we must not select it as an address
16293 register by this routine since our caller will try to
16294 increment the returned register via an "la" instruction. */
16297 find_addr_reg (rtx addr
)
16299 while (GET_CODE (addr
) == PLUS
)
16301 if (GET_CODE (XEXP (addr
, 0)) == REG
16302 && REGNO (XEXP (addr
, 0)) != 0)
16303 addr
= XEXP (addr
, 0);
16304 else if (GET_CODE (XEXP (addr
, 1)) == REG
16305 && REGNO (XEXP (addr
, 1)) != 0)
16306 addr
= XEXP (addr
, 1);
16307 else if (CONSTANT_P (XEXP (addr
, 0)))
16308 addr
= XEXP (addr
, 1);
16309 else if (CONSTANT_P (XEXP (addr
, 1)))
16310 addr
= XEXP (addr
, 0);
16314 if (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0)
16320 rs6000_fatal_bad_address (rtx op
)
16322 fatal_insn ("bad address", op
);
16327 static tree branch_island_list
= 0;
16329 /* Remember to generate a branch island for far calls to the given
16333 add_compiler_branch_island (tree label_name
, tree function_name
,
16336 tree branch_island
= build_tree_list (function_name
, label_name
);
16337 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
16338 TREE_CHAIN (branch_island
) = branch_island_list
;
16339 branch_island_list
= branch_island
;
16342 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16343 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16344 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16345 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16347 /* Generate far-jump branch islands for everything on the
16348 branch_island_list. Invoked immediately after the last instruction
16349 of the epilogue has been emitted; the branch-islands must be
16350 appended to, and contiguous with, the function body. Mach-O stubs
16351 are generated in machopic_output_stub(). */
16354 macho_branch_islands (void)
16357 tree branch_island
;
16359 for (branch_island
= branch_island_list
;
16361 branch_island
= TREE_CHAIN (branch_island
))
16363 const char *label
=
16364 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
16366 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
16367 char name_buf
[512];
16368 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16369 if (name
[0] == '*' || name
[0] == '&')
16370 strcpy (name_buf
, name
+1);
16374 strcpy (name_buf
+1, name
);
16376 strcpy (tmp_buf
, "\n");
16377 strcat (tmp_buf
, label
);
16378 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16379 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
16380 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
16381 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16384 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
16385 strcat (tmp_buf
, label
);
16386 strcat (tmp_buf
, "_pic\n");
16387 strcat (tmp_buf
, label
);
16388 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
16390 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
16391 strcat (tmp_buf
, name_buf
);
16392 strcat (tmp_buf
, " - ");
16393 strcat (tmp_buf
, label
);
16394 strcat (tmp_buf
, "_pic)\n");
16396 strcat (tmp_buf
, "\tmtlr r0\n");
16398 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
16399 strcat (tmp_buf
, name_buf
);
16400 strcat (tmp_buf
, " - ");
16401 strcat (tmp_buf
, label
);
16402 strcat (tmp_buf
, "_pic)\n");
16404 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
16408 strcat (tmp_buf
, ":\nlis r12,hi16(");
16409 strcat (tmp_buf
, name_buf
);
16410 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
16411 strcat (tmp_buf
, name_buf
);
16412 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
16414 output_asm_insn (tmp_buf
, 0);
16415 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16416 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
16417 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
16418 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16421 branch_island_list
= 0;
16424 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16425 already there or not. */
16428 no_previous_def (tree function_name
)
16430 tree branch_island
;
16431 for (branch_island
= branch_island_list
;
16433 branch_island
= TREE_CHAIN (branch_island
))
16434 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
16439 /* GET_PREV_LABEL gets the label name from the previous definition of
16443 get_prev_label (tree function_name
)
16445 tree branch_island
;
16446 for (branch_island
= branch_island_list
;
16448 branch_island
= TREE_CHAIN (branch_island
))
16449 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
16450 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
16454 /* INSN is either a function call or a millicode call. It may have an
16455 unconditional jump in its delay slot.
16457 CALL_DEST is the routine we are calling. */
16460 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
16461 int cookie_operand_number
)
16463 static char buf
[256];
16464 if (GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
16465 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
16468 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
16470 if (no_previous_def (funname
))
16472 int line_number
= 0;
16473 rtx label_rtx
= gen_label_rtx ();
16474 char *label_buf
, temp_buf
[256];
16475 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
16476 CODE_LABEL_NUMBER (label_rtx
));
16477 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
16478 labelname
= get_identifier (label_buf
);
16479 for (; insn
&& GET_CODE (insn
) != NOTE
; insn
= PREV_INSN (insn
));
16481 line_number
= NOTE_LINE_NUMBER (insn
);
16482 add_compiler_branch_island (labelname
, funname
, line_number
);
16485 labelname
= get_prev_label (funname
);
16487 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16488 instruction will reach 'foo', otherwise link as 'bl L42'".
16489 "L42" should be a 'branch island', that will do a far jump to
16490 'foo'. Branch islands are generated in
16491 macho_branch_islands(). */
16492 sprintf (buf
, "jbsr %%z%d,%.246s",
16493 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
16496 sprintf (buf
, "bl %%z%d", dest_operand_number
);
16500 /* Generate PIC and indirect symbol stubs. */
16503 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
16505 unsigned int length
;
16506 char *symbol_name
, *lazy_ptr_name
;
16507 char *local_label_0
;
16508 static int label
= 0;
16510 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16511 symb
= (*targetm
.strip_name_encoding
) (symb
);
16514 length
= strlen (symb
);
16515 symbol_name
= alloca (length
+ 32);
16516 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
16518 lazy_ptr_name
= alloca (length
+ 32);
16519 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
16522 machopic_picsymbol_stub1_section ();
16524 machopic_symbol_stub1_section ();
16528 fprintf (file
, "\t.align 5\n");
16530 fprintf (file
, "%s:\n", stub
);
16531 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
16534 local_label_0
= alloca (sizeof ("\"L00000000000$spb\""));
16535 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
16537 fprintf (file
, "\tmflr r0\n");
16538 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
16539 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
16540 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
16541 lazy_ptr_name
, local_label_0
);
16542 fprintf (file
, "\tmtlr r0\n");
16543 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
16544 (TARGET_64BIT
? "ldu" : "lwzu"),
16545 lazy_ptr_name
, local_label_0
);
16546 fprintf (file
, "\tmtctr r12\n");
16547 fprintf (file
, "\tbctr\n");
16551 fprintf (file
, "\t.align 4\n");
16553 fprintf (file
, "%s:\n", stub
);
16554 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
16556 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
16557 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
16558 (TARGET_64BIT
? "ldu" : "lwzu"),
16560 fprintf (file
, "\tmtctr r12\n");
16561 fprintf (file
, "\tbctr\n");
16564 machopic_lazy_symbol_ptr_section ();
16565 fprintf (file
, "%s:\n", lazy_ptr_name
);
16566 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
16567 fprintf (file
, "%sdyld_stub_binding_helper\n",
16568 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
16571 /* Legitimize PIC addresses. If the address is already
16572 position-independent, we return ORIG. Newly generated
16573 position-independent addresses go into a reg. This is REG if non
16574 zero, otherwise we allocate register(s) as necessary. */
16576 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
16579 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
16584 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
16585 reg
= gen_reg_rtx (Pmode
);
16587 if (GET_CODE (orig
) == CONST
)
16589 if (GET_CODE (XEXP (orig
, 0)) == PLUS
16590 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
16593 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
16595 /* Use a different reg for the intermediate value, as
16596 it will be marked UNCHANGING. */
16597 rtx reg_temp
= no_new_pseudos
? reg
: gen_reg_rtx (Pmode
);
16600 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
16603 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
16609 if (GET_CODE (offset
) == CONST_INT
)
16611 if (SMALL_INT (offset
))
16612 return plus_constant (base
, INTVAL (offset
));
16613 else if (! reload_in_progress
&& ! reload_completed
)
16614 offset
= force_reg (Pmode
, offset
);
16617 rtx mem
= force_const_mem (Pmode
, orig
);
16618 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
16621 return gen_rtx_PLUS (Pmode
, base
, offset
);
16624 /* Fall back on generic machopic code. */
16625 return machopic_legitimize_pic_address (orig
, mode
, reg
);
16628 /* This is just a placeholder to make linking work without having to
16629 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16630 ever needed for Darwin (not too likely!) this would have to get a
16631 real definition. */
16638 /* Output a .machine directive for the Darwin assembler, and call
16639 the generic start_file routine. */
16642 rs6000_darwin_file_start (void)
16644 static const struct
16650 { "ppc64", "ppc64", MASK_64BIT
},
16651 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
16652 { "power4", "ppc970", 0 },
16653 { "G5", "ppc970", 0 },
16654 { "7450", "ppc7450", 0 },
16655 { "7400", "ppc7400", MASK_ALTIVEC
},
16656 { "G4", "ppc7400", 0 },
16657 { "750", "ppc750", 0 },
16658 { "740", "ppc750", 0 },
16659 { "G3", "ppc750", 0 },
16660 { "604e", "ppc604e", 0 },
16661 { "604", "ppc604", 0 },
16662 { "603e", "ppc603", 0 },
16663 { "603", "ppc603", 0 },
16664 { "601", "ppc601", 0 },
16665 { NULL
, "ppc", 0 } };
16666 const char *cpu_id
= "";
16669 rs6000_file_start ();
16671 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16672 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
16673 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
16674 && rs6000_select
[i
].string
[0] != '\0')
16675 cpu_id
= rs6000_select
[i
].string
;
16677 /* Look through the mapping array. Pick the first name that either
16678 matches the argument, has a bit set in IF_SET that is also set
16679 in the target flags, or has a NULL name. */
16682 while (mapping
[i
].arg
!= NULL
16683 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
16684 && (mapping
[i
].if_set
& target_flags
) == 0)
16687 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
16690 #endif /* TARGET_MACHO */
16693 static unsigned int
16694 rs6000_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
16696 return default_section_type_flags_1 (decl
, name
, reloc
,
16697 flag_pic
|| DEFAULT_ABI
== ABI_AIX
);
16700 /* Record an element in the table of global constructors. SYMBOL is
16701 a SYMBOL_REF of the function to be called; PRIORITY is a number
16702 between 0 and MAX_INIT_PRIORITY.
16704 This differs from default_named_section_asm_out_constructor in
16705 that we have special handling for -mrelocatable. */
16708 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
16710 const char *section
= ".ctors";
16713 if (priority
!= DEFAULT_INIT_PRIORITY
)
16715 sprintf (buf
, ".ctors.%.5u",
16716 /* Invert the numbering so the linker puts us in the proper
16717 order; constructors are run from right to left, and the
16718 linker sorts in increasing order. */
16719 MAX_INIT_PRIORITY
- priority
);
16723 named_section_flags (section
, SECTION_WRITE
);
16724 assemble_align (POINTER_SIZE
);
16726 if (TARGET_RELOCATABLE
)
16728 fputs ("\t.long (", asm_out_file
);
16729 output_addr_const (asm_out_file
, symbol
);
16730 fputs (")@fixup\n", asm_out_file
);
16733 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
16737 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
16739 const char *section
= ".dtors";
16742 if (priority
!= DEFAULT_INIT_PRIORITY
)
16744 sprintf (buf
, ".dtors.%.5u",
16745 /* Invert the numbering so the linker puts us in the proper
16746 order; constructors are run from right to left, and the
16747 linker sorts in increasing order. */
16748 MAX_INIT_PRIORITY
- priority
);
16752 named_section_flags (section
, SECTION_WRITE
);
16753 assemble_align (POINTER_SIZE
);
16755 if (TARGET_RELOCATABLE
)
16757 fputs ("\t.long (", asm_out_file
);
16758 output_addr_const (asm_out_file
, symbol
);
16759 fputs (")@fixup\n", asm_out_file
);
16762 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
16766 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
16770 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
16771 ASM_OUTPUT_LABEL (file
, name
);
16772 fputs (DOUBLE_INT_ASM_OP
, file
);
16773 rs6000_output_function_entry (file
, name
);
16774 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
16777 fputs ("\t.size\t", file
);
16778 assemble_name (file
, name
);
16779 fputs (",24\n\t.type\t.", file
);
16780 assemble_name (file
, name
);
16781 fputs (",@function\n", file
);
16782 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
16784 fputs ("\t.globl\t.", file
);
16785 assemble_name (file
, name
);
16790 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
16791 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
16792 rs6000_output_function_entry (file
, name
);
16793 fputs (":\n", file
);
16797 if (TARGET_RELOCATABLE
16798 && (get_pool_size () != 0 || current_function_profile
)
16803 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
16805 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
16806 fprintf (file
, "\t.long ");
16807 assemble_name (file
, buf
);
16809 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
16810 assemble_name (file
, buf
);
16814 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
16815 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
16817 if (DEFAULT_ABI
== ABI_AIX
)
16819 const char *desc_name
, *orig_name
;
16821 orig_name
= (*targetm
.strip_name_encoding
) (name
);
16822 desc_name
= orig_name
;
16823 while (*desc_name
== '.')
16826 if (TREE_PUBLIC (decl
))
16827 fprintf (file
, "\t.globl %s\n", desc_name
);
16829 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
16830 fprintf (file
, "%s:\n", desc_name
);
16831 fprintf (file
, "\t.long %s\n", orig_name
);
16832 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
16833 if (DEFAULT_ABI
== ABI_AIX
)
16834 fputs ("\t.long 0\n", file
);
16835 fprintf (file
, "\t.previous\n");
16837 ASM_OUTPUT_LABEL (file
, name
);
16841 rs6000_elf_end_indicate_exec_stack (void)
16844 file_end_indicate_exec_stack ();
16850 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
16852 fputs (GLOBAL_ASM_OP
, stream
);
16853 RS6000_OUTPUT_BASENAME (stream
, name
);
16854 putc ('\n', stream
);
16858 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
16859 tree decl ATTRIBUTE_UNUSED
)
16862 static const char * const suffix
[3] = { "PR", "RO", "RW" };
16864 if (flags
& SECTION_CODE
)
16866 else if (flags
& SECTION_WRITE
)
16871 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
16872 (flags
& SECTION_CODE
) ? "." : "",
16873 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
16877 rs6000_xcoff_select_section (tree decl
, int reloc
,
16878 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
16880 if (decl_readonly_section_1 (decl
, reloc
, 1))
16882 if (TREE_PUBLIC (decl
))
16883 read_only_data_section ();
16885 read_only_private_data_section ();
16889 if (TREE_PUBLIC (decl
))
16892 private_data_section ();
16897 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
16901 /* Use select_section for private and uninitialized data. */
16902 if (!TREE_PUBLIC (decl
)
16903 || DECL_COMMON (decl
)
16904 || DECL_INITIAL (decl
) == NULL_TREE
16905 || DECL_INITIAL (decl
) == error_mark_node
16906 || (flag_zero_initialized_in_bss
16907 && initializer_zerop (DECL_INITIAL (decl
))))
16910 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
16911 name
= (*targetm
.strip_name_encoding
) (name
);
16912 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
16915 /* Select section for constant in constant pool.
16917 On RS/6000, all constants are in the private read-only data area.
16918 However, if this is being placed in the TOC it must be output as a
16922 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
16923 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
16925 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
16928 read_only_private_data_section ();
16931 /* Remove any trailing [DS] or the like from the symbol name. */
16933 static const char *
16934 rs6000_xcoff_strip_name_encoding (const char *name
)
16939 len
= strlen (name
);
16940 if (name
[len
- 1] == ']')
16941 return ggc_alloc_string (name
, len
- 4);
16946 /* Section attributes. AIX is always PIC. */
16948 static unsigned int
16949 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
16951 unsigned int align
;
16952 unsigned int flags
= default_section_type_flags_1 (decl
, name
, reloc
, 1);
16954 /* Align to at least UNIT size. */
16955 if (flags
& SECTION_CODE
)
16956 align
= MIN_UNITS_PER_WORD
;
16958 /* Increase alignment of large objects if not already stricter. */
16959 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
16960 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
16961 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
16963 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
16966 /* Output at beginning of assembler file.
16968 Initialize the section names for the RS/6000 at this point.
16970 Specify filename, including full path, to assembler.
16972 We want to go into the TOC section so at least one .toc will be emitted.
16973 Also, in order to output proper .bs/.es pairs, we need at least one static
16974 [RW] section emitted.
16976 Finally, declare mcount when profiling to make the assembler happy. */
16979 rs6000_xcoff_file_start (void)
16981 rs6000_gen_section_name (&xcoff_bss_section_name
,
16982 main_input_filename
, ".bss_");
16983 rs6000_gen_section_name (&xcoff_private_data_section_name
,
16984 main_input_filename
, ".rw_");
16985 rs6000_gen_section_name (&xcoff_read_only_section_name
,
16986 main_input_filename
, ".ro_");
16988 fputs ("\t.file\t", asm_out_file
);
16989 output_quoted_string (asm_out_file
, main_input_filename
);
16990 fputc ('\n', asm_out_file
);
16991 if (write_symbols
!= NO_DEBUG
)
16992 private_data_section ();
16995 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
16996 rs6000_file_start ();
16999 /* Output at end of assembler file.
17000 On the RS/6000, referencing data should automatically pull in text. */
17003 rs6000_xcoff_file_end (void)
17006 fputs ("_section_.text:\n", asm_out_file
);
17008 fputs (TARGET_32BIT
17009 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17012 #endif /* TARGET_XCOFF */
17015 /* Cross-module name binding. Darwin does not support overriding
17016 functions at dynamic-link time. */
17019 rs6000_binds_local_p (tree decl
)
17021 return default_binds_local_p_1 (decl
, 0);
17025 /* Compute a (partial) cost for rtx X. Return true if the complete
17026 cost has been computed, and false if subexpressions should be
17027 scanned. In either case, *TOTAL contains the cost result. */
17030 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
17032 enum machine_mode mode
= GET_MODE (x
);
17036 /* On the RS/6000, if it is valid in the insn, it is free. */
17038 if (((outer_code
== SET
17039 || outer_code
== PLUS
17040 || outer_code
== MINUS
)
17041 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
17042 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')))
17043 || (outer_code
== AND
17044 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17045 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
17046 mode
== SImode
? 'L' : 'J'))
17047 || mask_operand (x
, VOIDmode
)))
17048 || ((outer_code
== IOR
|| outer_code
== XOR
)
17049 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17050 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
17051 mode
== SImode
? 'L' : 'J'))))
17052 || outer_code
== ASHIFT
17053 || outer_code
== ASHIFTRT
17054 || outer_code
== LSHIFTRT
17055 || outer_code
== ROTATE
17056 || outer_code
== ROTATERT
17057 || outer_code
== ZERO_EXTRACT
17058 || (outer_code
== MULT
17059 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
17060 || ((outer_code
== DIV
|| outer_code
== UDIV
17061 || outer_code
== MOD
|| outer_code
== UMOD
)
17062 && exact_log2 (INTVAL (x
)) >= 0)
17063 || (outer_code
== COMPARE
17064 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
17065 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')))
17066 || (outer_code
== EQ
17067 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I')
17068 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17069 || (CONST_OK_FOR_LETTER_P (INTVAL (x
),
17070 mode
== SImode
? 'L' : 'J'))))
17071 || (outer_code
== GTU
17072 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'I'))
17073 || (outer_code
== LTU
17074 && CONST_OK_FOR_LETTER_P (INTVAL (x
), 'P')))
17079 else if ((outer_code
== PLUS
17080 && reg_or_add_cint64_operand (x
, VOIDmode
))
17081 || (outer_code
== MINUS
17082 && reg_or_sub_cint64_operand (x
, VOIDmode
))
17083 || ((outer_code
== SET
17084 || outer_code
== IOR
17085 || outer_code
== XOR
)
17087 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
17089 *total
= COSTS_N_INSNS (1);
17096 && ((outer_code
== AND
17097 && (CONST_OK_FOR_LETTER_P (INTVAL (x
), 'K')
17098 || CONST_OK_FOR_LETTER_P (INTVAL (x
), 'L')
17099 || mask64_operand (x
, DImode
)))
17100 || ((outer_code
== IOR
|| outer_code
== XOR
)
17101 && CONST_DOUBLE_HIGH (x
) == 0
17102 && (CONST_DOUBLE_LOW (x
)
17103 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)))
17108 else if (mode
== DImode
17109 && (outer_code
== SET
17110 || outer_code
== IOR
17111 || outer_code
== XOR
)
17112 && CONST_DOUBLE_HIGH (x
) == 0)
17114 *total
= COSTS_N_INSNS (1);
17123 /* When optimizing for size, MEM should be slightly more expensive
17124 than generating address, e.g., (plus (reg) (const)).
17125 L1 cache latency is about two instructions. */
17126 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
17134 if (mode
== DFmode
)
17136 if (GET_CODE (XEXP (x
, 0)) == MULT
)
17138 /* FNMA accounted in outer NEG. */
17139 if (outer_code
== NEG
)
17140 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
17142 *total
= rs6000_cost
->dmul
;
17145 *total
= rs6000_cost
->fp
;
17147 else if (mode
== SFmode
)
17149 /* FNMA accounted in outer NEG. */
17150 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
17153 *total
= rs6000_cost
->fp
;
17155 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
17157 /* The rs6000 doesn't have shift-and-add instructions. */
17158 rs6000_rtx_costs (XEXP (x
, 0), MULT
, PLUS
, total
);
17159 *total
+= COSTS_N_INSNS (1);
17162 *total
= COSTS_N_INSNS (1);
17166 if (mode
== DFmode
)
17168 if (GET_CODE (XEXP (x
, 0)) == MULT
)
17170 /* FNMA accounted in outer NEG. */
17171 if (outer_code
== NEG
)
17174 *total
= rs6000_cost
->dmul
;
17177 *total
= rs6000_cost
->fp
;
17179 else if (mode
== SFmode
)
17181 /* FNMA accounted in outer NEG. */
17182 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
17185 *total
= rs6000_cost
->fp
;
17187 else if (GET_CODE (XEXP (x
, 0)) == MULT
)
17189 /* The rs6000 doesn't have shift-and-sub instructions. */
17190 rs6000_rtx_costs (XEXP (x
, 0), MULT
, MINUS
, total
);
17191 *total
+= COSTS_N_INSNS (1);
17194 *total
= COSTS_N_INSNS (1);
17198 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
17199 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
17201 if (INTVAL (XEXP (x
, 1)) >= -256
17202 && INTVAL (XEXP (x
, 1)) <= 255)
17203 *total
= rs6000_cost
->mulsi_const9
;
17205 *total
= rs6000_cost
->mulsi_const
;
17207 /* FMA accounted in outer PLUS/MINUS. */
17208 else if ((mode
== DFmode
|| mode
== SFmode
)
17209 && (outer_code
== PLUS
|| outer_code
== MINUS
))
17211 else if (mode
== DFmode
)
17212 *total
= rs6000_cost
->dmul
;
17213 else if (mode
== SFmode
)
17214 *total
= rs6000_cost
->fp
;
17215 else if (mode
== DImode
)
17216 *total
= rs6000_cost
->muldi
;
17218 *total
= rs6000_cost
->mulsi
;
17223 if (FLOAT_MODE_P (mode
))
17225 *total
= mode
== DFmode
? rs6000_cost
->ddiv
17226 : rs6000_cost
->sdiv
;
17233 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
17234 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
17236 if (code
== DIV
|| code
== MOD
)
17238 *total
= COSTS_N_INSNS (2);
17241 *total
= COSTS_N_INSNS (1);
17245 if (GET_MODE (XEXP (x
, 1)) == DImode
)
17246 *total
= rs6000_cost
->divdi
;
17248 *total
= rs6000_cost
->divsi
;
17250 /* Add in shift and subtract for MOD. */
17251 if (code
== MOD
|| code
== UMOD
)
17252 *total
+= COSTS_N_INSNS (2);
17256 *total
= COSTS_N_INSNS (4);
17260 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
17271 *total
= COSTS_N_INSNS (1);
17279 /* Handle mul_highpart. */
17280 if (outer_code
== TRUNCATE
17281 && GET_CODE (XEXP (x
, 0)) == MULT
)
17283 if (mode
== DImode
)
17284 *total
= rs6000_cost
->muldi
;
17286 *total
= rs6000_cost
->mulsi
;
17289 else if (outer_code
== AND
)
17292 *total
= COSTS_N_INSNS (1);
17297 if (GET_CODE (XEXP (x
, 0)) == MEM
)
17300 *total
= COSTS_N_INSNS (1);
17306 if (!FLOAT_MODE_P (mode
))
17308 *total
= COSTS_N_INSNS (1);
17314 case UNSIGNED_FLOAT
:
17318 case FLOAT_TRUNCATE
:
17319 *total
= rs6000_cost
->fp
;
17323 switch (XINT (x
, 1))
17326 *total
= rs6000_cost
->fp
;
17338 *total
= COSTS_N_INSNS (1);
17341 else if (FLOAT_MODE_P (mode
)
17342 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17344 *total
= rs6000_cost
->fp
;
17352 /* Carry bit requires mode == Pmode.
17353 NEG or PLUS already counted so only add one. */
17355 && (outer_code
== NEG
|| outer_code
== PLUS
))
17357 *total
= COSTS_N_INSNS (1);
17360 if (outer_code
== SET
)
17362 if (XEXP (x
, 1) == const0_rtx
)
17364 *total
= COSTS_N_INSNS (2);
17367 else if (mode
== Pmode
)
17369 *total
= COSTS_N_INSNS (3);
17378 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
17380 *total
= COSTS_N_INSNS (2);
17384 if (outer_code
== COMPARE
)
17398 /* A C expression returning the cost of moving data from a register of class
17399 CLASS1 to one of CLASS2. */
17402 rs6000_register_move_cost (enum machine_mode mode
,
17403 enum reg_class from
, enum reg_class to
)
17405 /* Moves from/to GENERAL_REGS. */
17406 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
17407 || reg_classes_intersect_p (from
, GENERAL_REGS
))
17409 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
17412 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
17413 return (rs6000_memory_move_cost (mode
, from
, 0)
17414 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
17416 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17418 else if (from
== CR_REGS
)
17422 /* A move will cost one instruction per GPR moved. */
17423 return 2 * HARD_REGNO_NREGS (0, mode
);
17426 /* Moving between two similar registers is just one instruction. */
17427 else if (reg_classes_intersect_p (to
, from
))
17428 return mode
== TFmode
? 4 : 2;
17430 /* Everything else has to go through GENERAL_REGS. */
17432 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
17433 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
17436 /* A C expressions returning the cost of moving data of MODE from a register to
17440 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
17441 int in ATTRIBUTE_UNUSED
)
17443 if (reg_classes_intersect_p (class, GENERAL_REGS
))
17444 return 4 * HARD_REGNO_NREGS (0, mode
);
17445 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
17446 return 4 * HARD_REGNO_NREGS (32, mode
);
17447 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
17448 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO
, mode
);
17450 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
17453 /* Return an RTX representing where to find the function value of a
17454 function returning MODE. */
17456 rs6000_complex_function_value (enum machine_mode mode
)
17458 unsigned int regno
;
17460 enum machine_mode inner
= GET_MODE_INNER (mode
);
17461 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
17463 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17464 regno
= FP_ARG_RETURN
;
17467 regno
= GP_ARG_RETURN
;
17469 /* 32-bit is OK since it'll go in r3/r4. */
17470 if (TARGET_32BIT
&& inner_bytes
>= 4)
17471 return gen_rtx_REG (mode
, regno
);
17474 if (inner_bytes
>= 8)
17475 return gen_rtx_REG (mode
, regno
);
17477 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
17479 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
17480 GEN_INT (inner_bytes
));
17481 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
17484 /* Define how to find the value returned by a function.
17485 VALTYPE is the data type of the value (as a tree).
17486 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17487 otherwise, FUNC is 0.
17489 On the SPE, both FPs and vectors are returned in r3.
17491 On RS/6000 an integer value is in r3 and a floating-point value is in
17492 fp1, unless -msoft-float. */
17495 rs6000_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
17497 enum machine_mode mode
;
17498 unsigned int regno
;
17500 /* Special handling for structs in darwin64. */
17501 if (rs6000_darwin64_abi
17502 && TYPE_MODE (valtype
) == BLKmode
17503 && TREE_CODE (valtype
) == RECORD_TYPE
17504 && int_size_in_bytes (valtype
) > 0)
17506 CUMULATIVE_ARGS valcum
;
17510 valcum
.fregno
= FP_ARG_MIN_REG
;
17511 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
17512 /* Do a trial code generation as if this were going to be passed as
17513 an argument; if any part goes in memory, we return NULL. */
17514 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
17517 /* Otherwise fall through to standard ABI rules. */
17520 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
17522 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17523 return gen_rtx_PARALLEL (DImode
,
17525 gen_rtx_EXPR_LIST (VOIDmode
,
17526 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
17528 gen_rtx_EXPR_LIST (VOIDmode
,
17529 gen_rtx_REG (SImode
,
17530 GP_ARG_RETURN
+ 1),
17534 if ((INTEGRAL_TYPE_P (valtype
)
17535 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
17536 || POINTER_TYPE_P (valtype
))
17537 mode
= TARGET_32BIT
? SImode
: DImode
;
17539 mode
= TYPE_MODE (valtype
);
17541 if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17542 regno
= FP_ARG_RETURN
;
17543 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
17544 && targetm
.calls
.split_complex_arg
)
17545 return rs6000_complex_function_value (mode
);
17546 else if (TREE_CODE (valtype
) == VECTOR_TYPE
17547 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
17548 && ALTIVEC_VECTOR_MODE (mode
))
17549 regno
= ALTIVEC_ARG_RETURN
;
17550 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
17551 && (mode
== DFmode
|| mode
== DCmode
))
17552 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
17554 regno
= GP_ARG_RETURN
;
17556 return gen_rtx_REG (mode
, regno
);
17559 /* Define how to find the value returned by a library function
17560 assuming the value has mode MODE. */
17562 rs6000_libcall_value (enum machine_mode mode
)
17564 unsigned int regno
;
17566 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
17568 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17569 return gen_rtx_PARALLEL (DImode
,
17571 gen_rtx_EXPR_LIST (VOIDmode
,
17572 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
17574 gen_rtx_EXPR_LIST (VOIDmode
,
17575 gen_rtx_REG (SImode
,
17576 GP_ARG_RETURN
+ 1),
17580 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
17581 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
17582 regno
= FP_ARG_RETURN
;
17583 else if (ALTIVEC_VECTOR_MODE (mode
)
17584 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
17585 regno
= ALTIVEC_ARG_RETURN
;
17586 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
17587 return rs6000_complex_function_value (mode
);
17588 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
17589 && (mode
== DFmode
|| mode
== DCmode
))
17590 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
17592 regno
= GP_ARG_RETURN
;
17594 return gen_rtx_REG (mode
, regno
);
17597 /* Define the offset between two registers, FROM to be eliminated and its
17598 replacement TO, at the start of a routine. */
17600 rs6000_initial_elimination_offset (int from
, int to
)
17602 rs6000_stack_t
*info
= rs6000_stack_info ();
17603 HOST_WIDE_INT offset
;
17605 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
17606 offset
= info
->push_p
? 0 : -info
->total_size
;
17607 else if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
17608 offset
= info
->total_size
;
17609 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
17610 offset
= info
->push_p
? info
->total_size
: 0;
17611 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
17619 /* Return true if TYPE is of type __ev64_opaque__. */
17622 is_ev64_opaque_type (tree type
)
17625 && (type
== opaque_V2SI_type_node
17626 || type
== opaque_V2SF_type_node
17627 || type
== opaque_p_V2SI_type_node
));
17631 rs6000_dwarf_register_span (rtx reg
)
17636 && (SPE_VECTOR_MODE (GET_MODE (reg
))
17637 || (TARGET_E500_DOUBLE
&& GET_MODE (reg
) == DFmode
)))
17642 regno
= REGNO (reg
);
17644 /* The duality of the SPE register size wreaks all kinds of havoc.
17645 This is a way of distinguishing r0 in 32-bits from r0 in
17648 gen_rtx_PARALLEL (VOIDmode
,
17651 gen_rtx_REG (SImode
, regno
+ 1200),
17652 gen_rtx_REG (SImode
, regno
))
17654 gen_rtx_REG (SImode
, regno
),
17655 gen_rtx_REG (SImode
, regno
+ 1200)));
17658 /* Map internal gcc register numbers to DWARF2 register numbers. */
17661 rs6000_dbx_register_number (unsigned int regno
)
17663 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
17665 if (regno
== MQ_REGNO
)
17667 if (regno
== LINK_REGISTER_REGNUM
)
17669 if (regno
== COUNT_REGISTER_REGNUM
)
17671 if (CR_REGNO_P (regno
))
17672 return regno
- CR0_REGNO
+ 86;
17673 if (regno
== XER_REGNO
)
17675 if (ALTIVEC_REGNO_P (regno
))
17676 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
17677 if (regno
== VRSAVE_REGNO
)
17679 if (regno
== VSCR_REGNO
)
17681 if (regno
== SPE_ACC_REGNO
)
17683 if (regno
== SPEFSCR_REGNO
)
17685 /* SPE high reg number. We get these values of regno from
17686 rs6000_dwarf_register_span. */
17687 if (regno
>= 1200 && regno
< 1232)
17693 /* target hook eh_return_filter_mode */
17694 static enum machine_mode
17695 rs6000_eh_return_filter_mode (void)
17697 return TARGET_32BIT
? SImode
: word_mode
;
17700 /* Target hook for vector_mode_supported_p. */
17702 rs6000_vector_mode_supported_p (enum machine_mode mode
)
17705 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
17708 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
17715 /* Target hook for invalid_arg_for_unprototyped_fn. */
17716 static const char *
17717 invalid_arg_for_unprototyped_fn (tree typelist
, tree funcdecl
, tree val
)
17719 return (!rs6000_darwin64_abi
17721 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
17722 && (funcdecl
== NULL_TREE
17723 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
17724 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
17725 ? N_("AltiVec argument passed to unprototyped function")
17729 #include "gt-rs6000.h"