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* config/m32c/bitops.md, config/m32c/jump.md,
[official-gcc.git] / gcc / config / mips / mips.h
blobde926be4fd8fdfe6f22e525ea047b4633736825b
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
25
26
27 /* MIPS external variables defined in mips.c. */
28
29 /* Which processor to schedule for. Since there is no difference between
30 a R2000 and R3000 in terms of the scheduler, we collapse them into
31 just an R3000. The elements of the enumeration must match exactly
32 the cpu attribute in the mips.md machine description. */
33
34 enum processor_type {
35 PROCESSOR_R3000,
36 PROCESSOR_4KC,
37 PROCESSOR_4KP,
38 PROCESSOR_5KC,
39 PROCESSOR_5KF,
40 PROCESSOR_20KC,
41 PROCESSOR_24KC,
42 PROCESSOR_24KF,
43 PROCESSOR_24KX,
44 PROCESSOR_M4K,
45 PROCESSOR_R3900,
46 PROCESSOR_R6000,
47 PROCESSOR_R4000,
48 PROCESSOR_R4100,
49 PROCESSOR_R4111,
50 PROCESSOR_R4120,
51 PROCESSOR_R4130,
52 PROCESSOR_R4300,
53 PROCESSOR_R4600,
54 PROCESSOR_R4650,
55 PROCESSOR_R5000,
56 PROCESSOR_R5400,
57 PROCESSOR_R5500,
58 PROCESSOR_R7000,
59 PROCESSOR_R8000,
60 PROCESSOR_R9000,
61 PROCESSOR_SB1,
62 PROCESSOR_SB1A,
63 PROCESSOR_SR71000,
64 PROCESSOR_MAX
65 };
66
67 /* Costs of various operations on the different architectures. */
68
69 struct mips_rtx_cost_data
70 {
71 unsigned short fp_add;
72 unsigned short fp_mult_sf;
73 unsigned short fp_mult_df;
74 unsigned short fp_div_sf;
75 unsigned short fp_div_df;
76 unsigned short int_mult_si;
77 unsigned short int_mult_di;
78 unsigned short int_div_si;
79 unsigned short int_div_di;
80 unsigned short branch_cost;
81 unsigned short memory_latency;
82 };
83
84 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
85 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
86 to work on a 64-bit machine. */
87
88 #define ABI_32 0
89 #define ABI_N32 1
90 #define ABI_64 2
91 #define ABI_EABI 3
92 #define ABI_O64 4
93
94 /* Information about one recognized processor. Defined here for the
95 benefit of TARGET_CPU_CPP_BUILTINS. */
96 struct mips_cpu_info {
97 /* The 'canonical' name of the processor as far as GCC is concerned.
98 It's typically a manufacturer's prefix followed by a numerical
99 designation. It should be lowercase. */
100 const char *name;
101
102 /* The internal processor number that most closely matches this
103 entry. Several processors can have the same value, if there's no
104 difference between them from GCC's point of view. */
105 enum processor_type cpu;
106
107 /* The ISA level that the processor implements. */
108 int isa;
109 };
110
111 #ifndef USED_FOR_TARGET
112 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
113 extern const char *current_function_file; /* filename current function is in */
114 extern int num_source_filenames; /* current .file # */
115 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
116 extern int sym_lineno; /* sgi next label # for each stmt */
117 extern int set_noreorder; /* # of nested .set noreorder's */
118 extern int set_nomacro; /* # of nested .set nomacro's */
119 extern int set_noat; /* # of nested .set noat's */
120 extern int set_volatile; /* # of nested .set volatile's */
121 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
122 extern int mips_dbx_regno[]; /* Map register # to debug register # */
123 extern bool mips_split_p[];
124 extern GTY(()) rtx cmp_operands[2];
125 extern enum processor_type mips_arch; /* which cpu to codegen for */
126 extern enum processor_type mips_tune; /* which cpu to schedule for */
127 extern int mips_isa; /* architectural level */
128 extern int mips_abi; /* which ABI to use */
129 extern int mips16_hard_float; /* mips16 without -msoft-float */
130 extern const struct mips_cpu_info mips_cpu_info_table[];
131 extern const struct mips_cpu_info *mips_arch_info;
132 extern const struct mips_cpu_info *mips_tune_info;
133 extern const struct mips_rtx_cost_data *mips_cost;
134 #endif
135
136 /* Macros to silence warnings about numbers being signed in traditional
137 C and unsigned in ISO C when compiled on 32-bit hosts. */
138
139 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
140 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
141 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
142
143 \f
144 /* Run-time compilation parameters selecting different hardware subsets. */
145
146 /* True if the call patterns should be split into a jalr followed by
147 an instruction to restore $gp. This is only ever true for SVR4 PIC,
148 in which $gp is call-clobbered. It is only safe to split the load
149 from the call when every use of $gp is explicit. */
150
151 #define TARGET_SPLIT_CALLS \
152 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
153
154 /* True if we're generating a form of -mabicalls in which we can use
155 operators like %hi and %lo to refer to locally-binding symbols.
156 We can only do this for -mno-shared, and only then if we can use
157 relocation operations instead of assembly macros. It isn't really
158 worth using absolute sequences for 64-bit symbols because GOT
159 accesses are so much shorter. */
160
161 #define TARGET_ABSOLUTE_ABICALLS \
162 (TARGET_ABICALLS \
163 && !TARGET_SHARED \
164 && TARGET_EXPLICIT_RELOCS \
165 && !ABI_HAS_64BIT_SYMBOLS)
166
167 /* True if we can optimize sibling calls. For simplicity, we only
168 handle cases in which call_insn_operand will reject invalid
169 sibcall addresses. There are two cases in which this isn't true:
170
171 - TARGET_MIPS16. call_insn_operand accepts constant addresses
172 but there is no direct jump instruction. It isn't worth
173 using sibling calls in this case anyway; they would usually
174 be longer than normal calls.
175
176 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
177 accepts global constants, but "jr $25" is the only allowed
178 sibcall. */
179
180 #define TARGET_SIBCALLS \
181 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
182
183 /* True if .gpword or .gpdword should be used for switch tables.
184
185 Although GAS does understand .gpdword, the SGI linker mishandles
186 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
187 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
188 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
189
190 /* Generate mips16 code */
191 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
192 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
193 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
194
195 /* Generic ISA defines. */
196 #define ISA_MIPS1 (mips_isa == 1)
197 #define ISA_MIPS2 (mips_isa == 2)
198 #define ISA_MIPS3 (mips_isa == 3)
199 #define ISA_MIPS4 (mips_isa == 4)
200 #define ISA_MIPS32 (mips_isa == 32)
201 #define ISA_MIPS32R2 (mips_isa == 33)
202 #define ISA_MIPS64 (mips_isa == 64)
203
204 /* Architecture target defines. */
205 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
206 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
207 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
208 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
209 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
210 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
211 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
212 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
213 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
214 || mips_arch == PROCESSOR_SB1A)
215 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
216
217 /* Scheduling target defines. */
218 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
219 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
220 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
221 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
222 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
223 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
224 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
225 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
226 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
227 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
228 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
229 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
230 || mips_tune == PROCESSOR_SB1A)
231
232 /* True if the pre-reload scheduler should try to create chains of
233 multiply-add or multiply-subtract instructions. For example,
234 suppose we have:
235
236 t1 = a * b
237 t2 = t1 + c * d
238 t3 = e * f
239 t4 = t3 - g * h
240
241 t1 will have a higher priority than t2 and t3 will have a higher
242 priority than t4. However, before reload, there is no dependence
243 between t1 and t3, and they can often have similar priorities.
244 The scheduler will then tend to prefer:
245
246 t1 = a * b
247 t3 = e * f
248 t2 = t1 + c * d
249 t4 = t3 - g * h
250
251 which stops us from making full use of macc/madd-style instructions.
252 This sort of situation occurs frequently in Fourier transforms and
253 in unrolled loops.
254
255 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
256 queue so that chained multiply-add and multiply-subtract instructions
257 appear ahead of any other instruction that is likely to clobber lo.
258 In the example above, if t2 and t3 become ready at the same time,
259 the code ensures that t2 is scheduled first.
260
261 Multiply-accumulate instructions are a bigger win for some targets
262 than others, so this macro is defined on an opt-in basis. */
263 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
264 || TUNE_MIPS4120 \
265 || TUNE_MIPS4130)
266
267 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
268 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
269
270 /* IRIX specific stuff. */
271 #define TARGET_IRIX 0
272 #define TARGET_IRIX6 0
273
274 /* Define preprocessor macros for the -march and -mtune options.
275 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
276 processor. If INFO's canonical name is "foo", define PREFIX to
277 be "foo", and define an additional macro PREFIX_FOO. */
278 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
279 do \
280 { \
281 char *macro, *p; \
282 \
283 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
284 for (p = macro; *p != 0; p++) \
285 *p = TOUPPER (*p); \
286 \
287 builtin_define (macro); \
288 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
289 free (macro); \
290 } \
291 while (0)
292
293 /* Target CPU builtins. */
294 #define TARGET_CPU_CPP_BUILTINS() \
295 do \
296 { \
297 /* Everyone but IRIX defines this to mips. */ \
298 if (!TARGET_IRIX) \
299 builtin_assert ("machine=mips"); \
300 \
301 builtin_assert ("cpu=mips"); \
302 builtin_define ("__mips__"); \
303 builtin_define ("_mips"); \
304 \
305 /* We do this here because __mips is defined below \
306 and so we can't use builtin_define_std. */ \
307 if (!flag_iso) \
308 builtin_define ("mips"); \
309 \
310 if (TARGET_64BIT) \
311 builtin_define ("__mips64"); \
312 \
313 if (!TARGET_IRIX) \
314 { \
315 /* Treat _R3000 and _R4000 like register-size \
316 defines, which is how they've historically \
317 been used. */ \
318 if (TARGET_64BIT) \
319 { \
320 builtin_define_std ("R4000"); \
321 builtin_define ("_R4000"); \
322 } \
323 else \
324 { \
325 builtin_define_std ("R3000"); \
326 builtin_define ("_R3000"); \
327 } \
328 } \
329 if (TARGET_FLOAT64) \
330 builtin_define ("__mips_fpr=64"); \
331 else \
332 builtin_define ("__mips_fpr=32"); \
333 \
334 if (TARGET_MIPS16) \
335 builtin_define ("__mips16"); \
336 \
337 if (TARGET_MIPS3D) \
338 builtin_define ("__mips3d"); \
339 \
340 if (TARGET_DSP) \
341 builtin_define ("__mips_dsp"); \
342 \
343 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
344 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
345 \
346 if (ISA_MIPS1) \
347 { \
348 builtin_define ("__mips=1"); \
349 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
350 } \
351 else if (ISA_MIPS2) \
352 { \
353 builtin_define ("__mips=2"); \
354 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
355 } \
356 else if (ISA_MIPS3) \
357 { \
358 builtin_define ("__mips=3"); \
359 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
360 } \
361 else if (ISA_MIPS4) \
362 { \
363 builtin_define ("__mips=4"); \
364 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
365 } \
366 else if (ISA_MIPS32) \
367 { \
368 builtin_define ("__mips=32"); \
369 builtin_define ("__mips_isa_rev=1"); \
370 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
371 } \
372 else if (ISA_MIPS32R2) \
373 { \
374 builtin_define ("__mips=32"); \
375 builtin_define ("__mips_isa_rev=2"); \
376 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
377 } \
378 else if (ISA_MIPS64) \
379 { \
380 builtin_define ("__mips=64"); \
381 builtin_define ("__mips_isa_rev=1"); \
382 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
383 } \
384 \
385 if (TARGET_HARD_FLOAT) \
386 builtin_define ("__mips_hard_float"); \
387 else if (TARGET_SOFT_FLOAT) \
388 builtin_define ("__mips_soft_float"); \
389 \
390 if (TARGET_SINGLE_FLOAT) \
391 builtin_define ("__mips_single_float"); \
392 \
393 if (TARGET_PAIRED_SINGLE_FLOAT) \
394 builtin_define ("__mips_paired_single_float"); \
395 \
396 if (TARGET_BIG_ENDIAN) \
397 { \
398 builtin_define_std ("MIPSEB"); \
399 builtin_define ("_MIPSEB"); \
400 } \
401 else \
402 { \
403 builtin_define_std ("MIPSEL"); \
404 builtin_define ("_MIPSEL"); \
405 } \
406 \
407 /* Macros dependent on the C dialect. */ \
408 if (preprocessing_asm_p ()) \
409 { \
410 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
411 builtin_define ("_LANGUAGE_ASSEMBLY"); \
412 } \
413 else if (c_dialect_cxx ()) \
414 { \
415 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
416 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
417 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
418 } \
419 else \
420 { \
421 builtin_define_std ("LANGUAGE_C"); \
422 builtin_define ("_LANGUAGE_C"); \
423 } \
424 if (c_dialect_objc ()) \
425 { \
426 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
427 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
428 /* Bizarre, but needed at least for Irix. */ \
429 builtin_define_std ("LANGUAGE_C"); \
430 builtin_define ("_LANGUAGE_C"); \
431 } \
432 \
433 if (mips_abi == ABI_EABI) \
434 builtin_define ("__mips_eabi"); \
435 \
436 } while (0)
437
438 /* Default target_flags if no switches are specified */
439
440 #ifndef TARGET_DEFAULT
441 #define TARGET_DEFAULT 0
442 #endif
443
444 #ifndef TARGET_CPU_DEFAULT
445 #define TARGET_CPU_DEFAULT 0
446 #endif
447
448 #ifndef TARGET_ENDIAN_DEFAULT
449 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
450 #endif
451
452 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
453 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
454 #endif
455
456 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
457 #ifndef MIPS_ISA_DEFAULT
458 #ifndef MIPS_CPU_STRING_DEFAULT
459 #define MIPS_CPU_STRING_DEFAULT "from-abi"
460 #endif
461 #endif
462
463 #ifdef IN_LIBGCC2
464 #undef TARGET_64BIT
465 /* Make this compile time constant for libgcc2 */
466 #ifdef __mips64
467 #define TARGET_64BIT 1
468 #else
469 #define TARGET_64BIT 0
470 #endif
471 #endif /* IN_LIBGCC2 */
472
473 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
474
475 #ifndef MULTILIB_ENDIAN_DEFAULT
476 #if TARGET_ENDIAN_DEFAULT == 0
477 #define MULTILIB_ENDIAN_DEFAULT "EL"
478 #else
479 #define MULTILIB_ENDIAN_DEFAULT "EB"
480 #endif
481 #endif
482
483 #ifndef MULTILIB_ISA_DEFAULT
484 # if MIPS_ISA_DEFAULT == 1
485 # define MULTILIB_ISA_DEFAULT "mips1"
486 # else
487 # if MIPS_ISA_DEFAULT == 2
488 # define MULTILIB_ISA_DEFAULT "mips2"
489 # else
490 # if MIPS_ISA_DEFAULT == 3
491 # define MULTILIB_ISA_DEFAULT "mips3"
492 # else
493 # if MIPS_ISA_DEFAULT == 4
494 # define MULTILIB_ISA_DEFAULT "mips4"
495 # else
496 # if MIPS_ISA_DEFAULT == 32
497 # define MULTILIB_ISA_DEFAULT "mips32"
498 # else
499 # if MIPS_ISA_DEFAULT == 33
500 # define MULTILIB_ISA_DEFAULT "mips32r2"
501 # else
502 # if MIPS_ISA_DEFAULT == 64
503 # define MULTILIB_ISA_DEFAULT "mips64"
504 # else
505 # define MULTILIB_ISA_DEFAULT "mips1"
506 # endif
507 # endif
508 # endif
509 # endif
510 # endif
511 # endif
512 # endif
513 #endif
514
515 #ifndef MULTILIB_DEFAULTS
516 #define MULTILIB_DEFAULTS \
517 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
518 #endif
519
520 /* We must pass -EL to the linker by default for little endian embedded
521 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
522 linker will default to using big-endian output files. The OUTPUT_FORMAT
523 line must be in the linker script, otherwise -EB/-EL will not work. */
524
525 #ifndef ENDIAN_SPEC
526 #if TARGET_ENDIAN_DEFAULT == 0
527 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
528 #else
529 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
530 #endif
531 #endif
532
533 /* Support for a compile-time default CPU, et cetera. The rules are:
534 --with-arch is ignored if -march is specified or a -mips is specified
535 (other than -mips16).
536 --with-tune is ignored if -mtune is specified.
537 --with-abi is ignored if -mabi is specified.
538 --with-float is ignored if -mhard-float or -msoft-float are
539 specified.
540 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
541 specified. */
542 #define OPTION_DEFAULT_SPECS \
543 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
544 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
545 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
546 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
547 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
548
549
550 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
551 && ISA_HAS_COND_TRAP)
552
553 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
554 && !TARGET_SR71K \
555 && !TARGET_MIPS16)
556
557 /* True if the ABI can only work with 64-bit integer registers. We
558 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
559 otherwise floating-point registers must also be 64-bit. */
560 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
561
562 /* Likewise for 32-bit regs. */
563 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
564
565 /* True if symbols are 64 bits wide. At present, n64 is the only
566 ABI for which this is true. */
567 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
568
569 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
570 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
571 || ISA_MIPS4 \
572 || ISA_MIPS64)
573
574 /* ISA has branch likely instructions (e.g. mips2). */
575 /* Disable branchlikely for tx39 until compare rewrite. They haven't
576 been generated up to this point. */
577 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
578
579 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
580 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
581 || TARGET_MIPS5400 \
582 || TARGET_MIPS5500 \
583 || TARGET_MIPS7000 \
584 || TARGET_MIPS9000 \
585 || TARGET_MAD \
586 || ISA_MIPS32 \
587 || ISA_MIPS32R2 \
588 || ISA_MIPS64) \
589 && !TARGET_MIPS16)
590
591 /* ISA has the conditional move instructions introduced in mips4. */
592 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
593 || ISA_MIPS32 \
594 || ISA_MIPS32R2 \
595 || ISA_MIPS64) \
596 && !TARGET_MIPS5500 \
597 && !TARGET_MIPS16)
598
599 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
600 branch on CC, and move (both FP and non-FP) on CC. */
601 #define ISA_HAS_8CC (ISA_MIPS4 \
602 || ISA_MIPS32 \
603 || ISA_MIPS32R2 \
604 || ISA_MIPS64)
605
606 /* This is a catch all for other mips4 instructions: indexed load, the
607 FP madd and msub instructions, and the FP recip and recip sqrt
608 instructions. */
609 #define ISA_HAS_FP4 ((ISA_MIPS4 \
610 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
611 || ISA_MIPS64) \
612 && !TARGET_MIPS16)
613
614 /* ISA has conditional trap instructions. */
615 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
616 && !TARGET_MIPS16)
617
618 /* ISA has integer multiply-accumulate instructions, madd and msub. */
619 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
620 || ISA_MIPS32R2 \
621 || ISA_MIPS64) \
622 && !TARGET_MIPS16)
623
624 /* ISA has floating-point nmadd and nmsub instructions. */
625 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
626 || ISA_MIPS64) \
627 && (!TARGET_MIPS5400 || TARGET_MAD) \
628 && !TARGET_MIPS16)
629
630 /* ISA has count leading zeroes/ones instruction (not implemented). */
631 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
632 || ISA_MIPS32R2 \
633 || ISA_MIPS64) \
634 && !TARGET_MIPS16)
635
636 /* ISA has three operand multiply instructions that put
637 the high part in an accumulator: mulhi or mulhiu. */
638 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
639 || TARGET_MIPS5500 \
640 || TARGET_SR71K) \
641 && !TARGET_MIPS16)
642
643 /* ISA has three operand multiply instructions that
644 negates the result and puts the result in an accumulator. */
645 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
646 || TARGET_MIPS5500 \
647 || TARGET_SR71K) \
648 && !TARGET_MIPS16)
649
650 /* ISA has three operand multiply instructions that subtracts the
651 result from a 4th operand and puts the result in an accumulator. */
652 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
653 || TARGET_MIPS5500 \
654 || TARGET_SR71K) \
655 && !TARGET_MIPS16)
656
657 /* ISA has three operand multiply instructions that the result
658 from a 4th operand and puts the result in an accumulator. */
659 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
660 || TARGET_MIPS4130 \
661 || TARGET_MIPS5400 \
662 || TARGET_MIPS5500 \
663 || TARGET_SR71K) \
664 && !TARGET_MIPS16)
665
666 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
667 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
668 || TARGET_MIPS4130) \
669 && !TARGET_MIPS16)
670
671 /* ISA has the "ror" (rotate right) instructions. */
672 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
673 || TARGET_MIPS5400 \
674 || TARGET_MIPS5500 \
675 || TARGET_SR71K) \
676 && !TARGET_MIPS16)
677
678 /* ISA has data prefetch instructions. This controls use of 'pref'. */
679 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
680 || ISA_MIPS32 \
681 || ISA_MIPS32R2 \
682 || ISA_MIPS64) \
683 && !TARGET_MIPS16)
684
685 /* ISA has data indexed prefetch instructions. This controls use of
686 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
687 (prefx is a cop1x instruction, so can only be used if FP is
688 enabled.) */
689 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
690 || ISA_MIPS32R2 \
691 || ISA_MIPS64) \
692 && !TARGET_MIPS16)
693
694 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
695 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
696 also requires TARGET_DOUBLE_FLOAT. */
697 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
698
699 /* ISA includes the MIPS32r2 seb and seh instructions. */
700 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
701 && !TARGET_MIPS16)
702
703 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
704 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
705 && !TARGET_MIPS16)
706
707 /* ISA has instructions for accessing top part of 64-bit fp regs. */
708 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
709
710 /* True if the result of a load is not available to the next instruction.
711 A nop will then be needed between instructions like "lw $4,..."
712 and "addiu $4,$4,1". */
713 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
714 && !TARGET_MIPS3900 \
715 && !TARGET_MIPS16)
716
717 /* Likewise mtc1 and mfc1. */
718 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
719
720 /* Likewise floating-point comparisons. */
721 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
722
723 /* True if mflo and mfhi can be immediately followed by instructions
724 which write to the HI and LO registers.
725
726 According to MIPS specifications, MIPS ISAs I, II, and III need
727 (at least) two instructions between the reads of HI/LO and
728 instructions which write them, and later ISAs do not. Contradicting
729 the MIPS specifications, some MIPS IV processor user manuals (e.g.
730 the UM for the NEC Vr5000) document needing the instructions between
731 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
732 MIPS64 and later ISAs to have the interlocks, plus any specific
733 earlier-ISA CPUs for which CPU documentation declares that the
734 instructions are really interlocked. */
735 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
736 || ISA_MIPS32R2 \
737 || ISA_MIPS64 \
738 || TARGET_MIPS5500)
739 \f
740 /* Add -G xx support. */
741
742 #undef SWITCH_TAKES_ARG
743 #define SWITCH_TAKES_ARG(CHAR) \
744 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
745
746 #define OVERRIDE_OPTIONS override_options ()
747
748 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
749
750 /* Show we can debug even without a frame pointer. */
751 #define CAN_DEBUG_WITHOUT_FP
752 \f
753 /* Tell collect what flags to pass to nm. */
754 #ifndef NM_FLAGS
755 #define NM_FLAGS "-Bn"
756 #endif
757
758 \f
759 #ifndef MIPS_ABI_DEFAULT
760 #define MIPS_ABI_DEFAULT ABI_32
761 #endif
762
763 /* Use the most portable ABI flag for the ASM specs. */
764
765 #if MIPS_ABI_DEFAULT == ABI_32
766 #define MULTILIB_ABI_DEFAULT "mabi=32"
767 #endif
768
769 #if MIPS_ABI_DEFAULT == ABI_O64
770 #define MULTILIB_ABI_DEFAULT "mabi=o64"
771 #endif
772
773 #if MIPS_ABI_DEFAULT == ABI_N32
774 #define MULTILIB_ABI_DEFAULT "mabi=n32"
775 #endif
776
777 #if MIPS_ABI_DEFAULT == ABI_64
778 #define MULTILIB_ABI_DEFAULT "mabi=64"
779 #endif
780
781 #if MIPS_ABI_DEFAULT == ABI_EABI
782 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
783 #endif
784
785 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
786 to the assembler. It may be overridden by subtargets. */
787 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
788 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
789 %{noasmopt:-O0} \
790 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
791 #endif
792
793 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
794 the assembler. It may be overridden by subtargets.
795
796 Beginning with gas 2.13, -mdebug must be passed to correctly handle
797 COFF debugging info. */
798
799 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
800 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
801 %{g} %{g0} %{g1} %{g2} %{g3} \
802 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
803 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
804 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
805 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
806 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
807 #endif
808
809 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
810 overridden by subtargets. */
811
812 #ifndef SUBTARGET_ASM_SPEC
813 #define SUBTARGET_ASM_SPEC ""
814 #endif
815
816 #undef ASM_SPEC
817 #define ASM_SPEC "\
818 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
819 %{mips32} %{mips32r2} %{mips64} \
820 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
821 %{mips3d:-mips3d} \
822 %{mdsp} \
823 %{mfix-vr4120} %{mfix-vr4130} \
824 %(subtarget_asm_optimizing_spec) \
825 %(subtarget_asm_debugging_spec) \
826 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
827 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
828 %{mfp32} %{mfp64} \
829 %{mshared} %{mno-shared} \
830 %{msym32} %{mno-sym32} \
831 %{mtune=*} %{v} \
832 %(subtarget_asm_spec)"
833
834 /* Extra switches sometimes passed to the linker. */
835 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
836 will interpret it as a -b option. */
837
838 #ifndef LINK_SPEC
839 #define LINK_SPEC "\
840 %(endian_spec) \
841 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
842 %{bestGnum} %{shared} %{non_shared}"
843 #endif /* LINK_SPEC defined */
844
845
846 /* Specs for the compiler proper */
847
848 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
849 overridden by subtargets. */
850 #ifndef SUBTARGET_CC1_SPEC
851 #define SUBTARGET_CC1_SPEC ""
852 #endif
853
854 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
855
856 #undef CC1_SPEC
857 #define CC1_SPEC "\
858 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
859 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
860 %{save-temps: } \
861 %(subtarget_cc1_spec)"
862
863 /* Preprocessor specs. */
864
865 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
866 overridden by subtargets. */
867 #ifndef SUBTARGET_CPP_SPEC
868 #define SUBTARGET_CPP_SPEC ""
869 #endif
870
871 #define CPP_SPEC "%(subtarget_cpp_spec)"
872
873 /* This macro defines names of additional specifications to put in the specs
874 that can be used in various specifications like CC1_SPEC. Its definition
875 is an initializer with a subgrouping for each command option.
876
877 Each subgrouping contains a string constant, that defines the
878 specification name, and a string constant that used by the GCC driver
879 program.
880
881 Do not define this macro if it does not need to do anything. */
882
883 #define EXTRA_SPECS \
884 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
885 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
886 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
887 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
888 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
889 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
890 { "endian_spec", ENDIAN_SPEC }, \
891 SUBTARGET_EXTRA_SPECS
892
893 #ifndef SUBTARGET_EXTRA_SPECS
894 #define SUBTARGET_EXTRA_SPECS
895 #endif
896 \f
897 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
898 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
899 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
900
901 #ifndef PREFERRED_DEBUGGING_TYPE
902 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
903 #endif
904
905 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
906
907 /* By default, turn on GDB extensions. */
908 #define DEFAULT_GDB_EXTENSIONS 1
909
910 /* Local compiler-generated symbols must have a prefix that the assembler
911 understands. By default, this is $, although some targets (e.g.,
912 NetBSD-ELF) need to override this. */
913
914 #ifndef LOCAL_LABEL_PREFIX
915 #define LOCAL_LABEL_PREFIX "$"
916 #endif
917
918 /* By default on the mips, external symbols do not have an underscore
919 prepended, but some targets (e.g., NetBSD) require this. */
920
921 #ifndef USER_LABEL_PREFIX
922 #define USER_LABEL_PREFIX ""
923 #endif
924
925 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
926 since the length can run past this up to a continuation point. */
927 #undef DBX_CONTIN_LENGTH
928 #define DBX_CONTIN_LENGTH 1500
929
930 /* How to renumber registers for dbx and gdb. */
931 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
932
933 /* The mapping from gcc register number to DWARF 2 CFA column number. */
934 #define DWARF_FRAME_REGNUM(REG) (REG)
935
936 /* The DWARF 2 CFA column which tracks the return address. */
937 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
938
939 /* The DWARF 2 CFA column which tracks the return address from a
940 signal handler context. */
941 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
942
943 /* Before the prologue, RA lives in r31. */
944 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
945
946 /* Describe how we implement __builtin_eh_return. */
947 #define EH_RETURN_DATA_REGNO(N) \
948 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
949
950 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
951
952 /* Offsets recorded in opcodes are a multiple of this alignment factor.
953 The default for this in 64-bit mode is 8, which causes problems with
954 SFmode register saves. */
955 #define DWARF_CIE_DATA_ALIGNMENT -4
956
957 /* Correct the offset of automatic variables and arguments. Note that
958 the MIPS debug format wants all automatic variables and arguments
959 to be in terms of the virtual frame pointer (stack pointer before
960 any adjustment in the function), while the MIPS 3.0 linker wants
961 the frame pointer to be the stack pointer after the initial
962 adjustment. */
963
964 #define DEBUGGER_AUTO_OFFSET(X) \
965 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
966 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
967 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
968 \f
969 /* Target machine storage layout */
970
971 #define BITS_BIG_ENDIAN 0
972 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
973 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
974
975 /* Define this to set the endianness to use in libgcc2.c, which can
976 not depend on target_flags. */
977 #if !defined(MIPSEL) && !defined(__MIPSEL__)
978 #define LIBGCC2_WORDS_BIG_ENDIAN 1
979 #else
980 #define LIBGCC2_WORDS_BIG_ENDIAN 0
981 #endif
982
983 #define MAX_BITS_PER_WORD 64
984
985 /* Width of a word, in units (bytes). */
986 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
987 #ifndef IN_LIBGCC2
988 #define MIN_UNITS_PER_WORD 4
989 #endif
990
991 /* For MIPS, width of a floating point register. */
992 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
993
994 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
995 the next available register. */
996 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
997
998 /* The largest size of value that can be held in floating-point
999 registers and moved with a single instruction. */
1000 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1001
1002 /* The largest size of value that can be held in floating-point
1003 registers. */
1004 #define UNITS_PER_FPVALUE \
1005 (TARGET_SOFT_FLOAT ? 0 \
1006 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1007 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1008
1009 /* The number of bytes in a double. */
1010 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1011
1012 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1013
1014 /* Set the sizes of the core types. */
1015 #define SHORT_TYPE_SIZE 16
1016 #define INT_TYPE_SIZE 32
1017 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1018 #define LONG_LONG_TYPE_SIZE 64
1019
1020 #define FLOAT_TYPE_SIZE 32
1021 #define DOUBLE_TYPE_SIZE 64
1022 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1023
1024 /* long double is not a fixed mode, but the idea is that, if we
1025 support long double, we also want a 128-bit integer type. */
1026 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1027
1028 #ifdef IN_LIBGCC2
1029 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1030 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1031 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1032 # else
1033 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1034 # endif
1035 #endif
1036
1037 /* Width in bits of a pointer. */
1038 #ifndef POINTER_SIZE
1039 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1040 #endif
1041
1042 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1043 #define PARM_BOUNDARY BITS_PER_WORD
1044
1045 /* Allocation boundary (in *bits*) for the code of a function. */
1046 #define FUNCTION_BOUNDARY 32
1047
1048 /* Alignment of field after `int : 0' in a structure. */
1049 #define EMPTY_FIELD_BOUNDARY 32
1050
1051 /* Every structure's size must be a multiple of this. */
1052 /* 8 is observed right on a DECstation and on riscos 4.02. */
1053 #define STRUCTURE_SIZE_BOUNDARY 8
1054
1055 /* There is no point aligning anything to a rounder boundary than this. */
1056 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1057
1058 /* All accesses must be aligned. */
1059 #define STRICT_ALIGNMENT 1
1060
1061 /* Define this if you wish to imitate the way many other C compilers
1062 handle alignment of bitfields and the structures that contain
1063 them.
1064
1065 The behavior is that the type written for a bit-field (`int',
1066 `short', or other integer type) imposes an alignment for the
1067 entire structure, as if the structure really did contain an
1068 ordinary field of that type. In addition, the bit-field is placed
1069 within the structure so that it would fit within such a field,
1070 not crossing a boundary for it.
1071
1072 Thus, on most machines, a bit-field whose type is written as `int'
1073 would not cross a four-byte boundary, and would force four-byte
1074 alignment for the whole structure. (The alignment used may not
1075 be four bytes; it is controlled by the other alignment
1076 parameters.)
1077
1078 If the macro is defined, its definition should be a C expression;
1079 a nonzero value for the expression enables this behavior. */
1080
1081 #define PCC_BITFIELD_TYPE_MATTERS 1
1082
1083 /* If defined, a C expression to compute the alignment given to a
1084 constant that is being placed in memory. CONSTANT is the constant
1085 and ALIGN is the alignment that the object would ordinarily have.
1086 The value of this macro is used instead of that alignment to align
1087 the object.
1088
1089 If this macro is not defined, then ALIGN is used.
1090
1091 The typical use of this macro is to increase alignment for string
1092 constants to be word aligned so that `strcpy' calls that copy
1093 constants can be done inline. */
1094
1095 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1096 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1097 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1098
1099 /* If defined, a C expression to compute the alignment for a static
1100 variable. TYPE is the data type, and ALIGN is the alignment that
1101 the object would ordinarily have. The value of this macro is used
1102 instead of that alignment to align the object.
1103
1104 If this macro is not defined, then ALIGN is used.
1105
1106 One use of this macro is to increase alignment of medium-size
1107 data to make it all fit in fewer cache lines. Another is to
1108 cause character arrays to be word-aligned so that `strcpy' calls
1109 that copy constants to character arrays can be done inline. */
1110
1111 #undef DATA_ALIGNMENT
1112 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1113 ((((ALIGN) < BITS_PER_WORD) \
1114 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1115 || TREE_CODE (TYPE) == UNION_TYPE \
1116 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1117
1118
1119 #define PAD_VARARGS_DOWN \
1120 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1121
1122 /* Define if operations between registers always perform the operation
1123 on the full register even if a narrower mode is specified. */
1124 #define WORD_REGISTER_OPERATIONS
1125
1126 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1127 moves. All other references are zero extended. */
1128 #define LOAD_EXTEND_OP(MODE) \
1129 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1130 ? SIGN_EXTEND : ZERO_EXTEND)
1131
1132 /* Define this macro if it is advisable to hold scalars in registers
1133 in a wider mode than that declared by the program. In such cases,
1134 the value is constrained to be within the bounds of the declared
1135 type, but kept valid in the wider mode. The signedness of the
1136 extension may differ from that of the type. */
1137
1138 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1139 if (GET_MODE_CLASS (MODE) == MODE_INT \
1140 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1141 { \
1142 if ((MODE) == SImode) \
1143 (UNSIGNEDP) = 0; \
1144 (MODE) = Pmode; \
1145 }
1146
1147 /* Define if loading short immediate values into registers sign extends. */
1148 #define SHORT_IMMEDIATES_SIGN_EXTEND
1149
1150 /* The [d]clz instructions have the natural values at 0. */
1151
1152 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1153 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1154 \f
1155 /* Standard register usage. */
1156
1157 /* Number of hardware registers. We have:
1158
1159 - 32 integer registers
1160 - 32 floating point registers
1161 - 8 condition code registers
1162 - 2 accumulator registers (hi and lo)
1163 - 32 registers each for coprocessors 0, 2 and 3
1164 - 3 fake registers:
1165 - ARG_POINTER_REGNUM
1166 - FRAME_POINTER_REGNUM
1167 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1168 - 3 dummy entries that were used at various times in the past.
1169 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1170 - 6 DSP control registers */
1171
1172 #define FIRST_PSEUDO_REGISTER 188
1173
1174 /* By default, fix the kernel registers ($26 and $27), the global
1175 pointer ($28) and the stack pointer ($29). This can change
1176 depending on the command-line options.
1177
1178 Regarding coprocessor registers: without evidence to the contrary,
1179 it's best to assume that each coprocessor register has a unique
1180 use. This can be overridden, in, e.g., override_options() or
1181 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1182 for a particular target. */
1183
1184 #define FIXED_REGISTERS \
1185 { \
1186 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1187 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1188 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1190 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1191 /* COP0 registers */ \
1192 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1193 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1194 /* COP2 registers */ \
1195 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1196 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1197 /* COP3 registers */ \
1198 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1199 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1200 /* 6 DSP accumulator registers & 6 control registers */ \
1201 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1202 }
1203
1204
1205 /* Set up this array for o32 by default.
1206
1207 Note that we don't mark $31 as a call-clobbered register. The idea is
1208 that it's really the call instructions themselves which clobber $31.
1209 We don't care what the called function does with it afterwards.
1210
1211 This approach makes it easier to implement sibcalls. Unlike normal
1212 calls, sibcalls don't clobber $31, so the register reaches the
1213 called function in tact. EPILOGUE_USES says that $31 is useful
1214 to the called function. */
1215
1216 #define CALL_USED_REGISTERS \
1217 { \
1218 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1219 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1220 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1221 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1222 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1223 /* COP0 registers */ \
1224 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1225 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1226 /* COP2 registers */ \
1227 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1228 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1229 /* COP3 registers */ \
1230 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1231 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1232 /* 6 DSP accumulator registers & 6 control registers */ \
1233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1234 }
1235
1236
1237 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1238
1239 #define CALL_REALLY_USED_REGISTERS \
1240 { /* General registers. */ \
1241 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1242 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1243 /* Floating-point registers. */ \
1244 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1245 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1246 /* Others. */ \
1247 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1248 /* COP0 registers */ \
1249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1251 /* COP2 registers */ \
1252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1254 /* COP3 registers */ \
1255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1257 /* 6 DSP accumulator registers & 6 control registers */ \
1258 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1259 }
1260
1261 /* Internal macros to classify a register number as to whether it's a
1262 general purpose register, a floating point register, a
1263 multiply/divide register, or a status register. */
1264
1265 #define GP_REG_FIRST 0
1266 #define GP_REG_LAST 31
1267 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1268 #define GP_DBX_FIRST 0
1269
1270 #define FP_REG_FIRST 32
1271 #define FP_REG_LAST 63
1272 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1273 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1274
1275 #define MD_REG_FIRST 64
1276 #define MD_REG_LAST 65
1277 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1278 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1279
1280 #define ST_REG_FIRST 67
1281 #define ST_REG_LAST 74
1282 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1283
1284
1285 /* FIXME: renumber. */
1286 #define COP0_REG_FIRST 80
1287 #define COP0_REG_LAST 111
1288 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1289
1290 #define COP2_REG_FIRST 112
1291 #define COP2_REG_LAST 143
1292 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1293
1294 #define COP3_REG_FIRST 144
1295 #define COP3_REG_LAST 175
1296 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1297 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1298 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1299
1300 #define DSP_ACC_REG_FIRST 176
1301 #define DSP_ACC_REG_LAST 181
1302 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1303
1304 #define AT_REGNUM (GP_REG_FIRST + 1)
1305 #define HI_REGNUM (MD_REG_FIRST + 0)
1306 #define LO_REGNUM (MD_REG_FIRST + 1)
1307 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1308 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1309 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1310 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1311 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1312 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1313
1314 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1315 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1316 should be used instead. */
1317 #define FPSW_REGNUM ST_REG_FIRST
1318
1319 #define GP_REG_P(REGNO) \
1320 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1321 #define M16_REG_P(REGNO) \
1322 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1323 #define FP_REG_P(REGNO) \
1324 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1325 #define MD_REG_P(REGNO) \
1326 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1327 #define ST_REG_P(REGNO) \
1328 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1329 #define COP0_REG_P(REGNO) \
1330 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1331 #define COP2_REG_P(REGNO) \
1332 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1333 #define COP3_REG_P(REGNO) \
1334 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1335 #define ALL_COP_REG_P(REGNO) \
1336 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1337 /* Test if REGNO is one of the 6 new DSP accumulators. */
1338 #define DSP_ACC_REG_P(REGNO) \
1339 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1340 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1341 #define ACC_REG_P(REGNO) \
1342 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1343 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1344 #define ACC_HI_REG_P(REGNO) \
1345 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1346 || (REGNO) == AC3HI_REGNUM)
1347
1348 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1349
1350 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1351 to initialize the mips16 gp pseudo register. */
1352 #define CONST_GP_P(X) \
1353 (GET_CODE (X) == CONST \
1354 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1355 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1356
1357 /* Return coprocessor number from register number. */
1358
1359 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1360 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1361 : COP3_REG_P (REGNO) ? '3' : '?')
1362
1363
1364 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1365
1366 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1367 array built in override_options. Because machmodes.h is not yet
1368 included before this file is processed, the MODE bound can't be
1369 expressed here. */
1370
1371 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1372
1373 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1374 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1375
1376 /* Value is 1 if it is a good idea to tie two pseudo registers
1377 when one has mode MODE1 and one has mode MODE2.
1378 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1379 for any hard reg, then this must be 0 for correct output. */
1380 #define MODES_TIEABLE_P(MODE1, MODE2) \
1381 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1382 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1383 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1384 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1385
1386 /* Register to use for pushing function arguments. */
1387 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1388
1389 /* These two registers don't really exist: they get eliminated to either
1390 the stack or hard frame pointer. */
1391 #define ARG_POINTER_REGNUM 77
1392 #define FRAME_POINTER_REGNUM 78
1393
1394 /* $30 is not available on the mips16, so we use $17 as the frame
1395 pointer. */
1396 #define HARD_FRAME_POINTER_REGNUM \
1397 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1398
1399 /* Value should be nonzero if functions must have frame pointers.
1400 Zero means the frame pointer need not be set up (and parms
1401 may be accessed via the stack pointer) in functions that seem suitable.
1402 This is computed in `reload', in reload1.c. */
1403 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1404
1405 /* Register in which static-chain is passed to a function. */
1406 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1407
1408 /* Registers used as temporaries in prologue/epilogue code. If we're
1409 generating mips16 code, these registers must come from the core set
1410 of 8. The prologue register mustn't conflict with any incoming
1411 arguments, the static chain pointer, or the frame pointer. The
1412 epilogue temporary mustn't conflict with the return registers, the
1413 frame pointer, the EH stack adjustment, or the EH data registers. */
1414
1415 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1416 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1417
1418 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1419 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1420
1421 /* Define this macro if it is as good or better to call a constant
1422 function address than to call an address kept in a register. */
1423 #define NO_FUNCTION_CSE 1
1424
1425 /* The ABI-defined global pointer. Sometimes we use a different
1426 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1427 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1428
1429 /* We normally use $28 as the global pointer. However, when generating
1430 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1431 register instead. They can then avoid saving and restoring $28
1432 and perhaps avoid using a frame at all.
1433
1434 When a leaf function uses something other than $28, mips_expand_prologue
1435 will modify pic_offset_table_rtx in place. Take the register number
1436 from there after reload. */
1437 #define PIC_OFFSET_TABLE_REGNUM \
1438 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1439
1440 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1441 \f
1442 /* Define the classes of registers for register constraints in the
1443 machine description. Also define ranges of constants.
1444
1445 One of the classes must always be named ALL_REGS and include all hard regs.
1446 If there is more than one class, another class must be named NO_REGS
1447 and contain no registers.
1448
1449 The name GENERAL_REGS must be the name of a class (or an alias for
1450 another name such as ALL_REGS). This is the class of registers
1451 that is allowed by "g" or "r" in a register constraint.
1452 Also, registers outside this class are allocated only when
1453 instructions express preferences for them.
1454
1455 The classes must be numbered in nondecreasing order; that is,
1456 a larger-numbered class must never be contained completely
1457 in a smaller-numbered class.
1458
1459 For any two classes, it is very desirable that there be another
1460 class that represents their union. */
1461
1462 enum reg_class
1463 {
1464 NO_REGS, /* no registers in set */
1465 M16_NA_REGS, /* mips16 regs not used to pass args */
1466 M16_REGS, /* mips16 directly accessible registers */
1467 T_REG, /* mips16 T register ($24) */
1468 M16_T_REGS, /* mips16 registers plus T register */
1469 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1470 V1_REG, /* Register $v1 ($3) used for TLS access. */
1471 LEA_REGS, /* Every GPR except $25 */
1472 GR_REGS, /* integer registers */
1473 FP_REGS, /* floating point registers */
1474 HI_REG, /* hi register */
1475 LO_REG, /* lo register */
1476 MD_REGS, /* multiply/divide registers (hi/lo) */
1477 COP0_REGS, /* generic coprocessor classes */
1478 COP2_REGS,
1479 COP3_REGS,
1480 HI_AND_GR_REGS, /* union classes */
1481 LO_AND_GR_REGS,
1482 HI_AND_FP_REGS,
1483 COP0_AND_GR_REGS,
1484 COP2_AND_GR_REGS,
1485 COP3_AND_GR_REGS,
1486 ALL_COP_REGS,
1487 ALL_COP_AND_GR_REGS,
1488 ST_REGS, /* status registers (fp status) */
1489 DSP_ACC_REGS, /* DSP accumulator registers */
1490 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1491 ALL_REGS, /* all registers */
1492 LIM_REG_CLASSES /* max value + 1 */
1493 };
1494
1495 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1496
1497 #define GENERAL_REGS GR_REGS
1498
1499 /* An initializer containing the names of the register classes as C
1500 string constants. These names are used in writing some of the
1501 debugging dumps. */
1502
1503 #define REG_CLASS_NAMES \
1504 { \
1505 "NO_REGS", \
1506 "M16_NA_REGS", \
1507 "M16_REGS", \
1508 "T_REG", \
1509 "M16_T_REGS", \
1510 "PIC_FN_ADDR_REG", \
1511 "V1_REG", \
1512 "LEA_REGS", \
1513 "GR_REGS", \
1514 "FP_REGS", \
1515 "HI_REG", \
1516 "LO_REG", \
1517 "MD_REGS", \
1518 /* coprocessor registers */ \
1519 "COP0_REGS", \
1520 "COP2_REGS", \
1521 "COP3_REGS", \
1522 "HI_AND_GR_REGS", \
1523 "LO_AND_GR_REGS", \
1524 "HI_AND_FP_REGS", \
1525 "COP0_AND_GR_REGS", \
1526 "COP2_AND_GR_REGS", \
1527 "COP3_AND_GR_REGS", \
1528 "ALL_COP_REGS", \
1529 "ALL_COP_AND_GR_REGS", \
1530 "ST_REGS", \
1531 "DSP_ACC_REGS", \
1532 "ACC_REGS", \
1533 "ALL_REGS" \
1534 }
1535
1536 /* An initializer containing the contents of the register classes,
1537 as integers which are bit masks. The Nth integer specifies the
1538 contents of class N. The way the integer MASK is interpreted is
1539 that register R is in the class if `MASK & (1 << R)' is 1.
1540
1541 When the machine has more than 32 registers, an integer does not
1542 suffice. Then the integers are replaced by sub-initializers,
1543 braced groupings containing several integers. Each
1544 sub-initializer must be suitable as an initializer for the type
1545 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1546
1547 #define REG_CLASS_CONTENTS \
1548 { \
1549 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1550 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1551 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1552 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1553 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1554 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1555 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1556 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1557 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1558 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1559 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1560 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1561 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1562 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1563 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1564 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1565 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1566 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1567 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1568 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1569 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1570 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1571 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1572 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1573 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1574 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1575 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1576 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1577 }
1578
1579
1580 /* A C expression whose value is a register class containing hard
1581 register REGNO. In general there is more that one such class;
1582 choose a class which is "minimal", meaning that no smaller class
1583 also contains the register. */
1584
1585 extern const enum reg_class mips_regno_to_class[];
1586
1587 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1588
1589 /* A macro whose definition is the name of the class to which a
1590 valid base register must belong. A base register is one used in
1591 an address which is the register value plus a displacement. */
1592
1593 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1594
1595 /* A macro whose definition is the name of the class to which a
1596 valid index register must belong. An index register is one used
1597 in an address where its value is either multiplied by a scale
1598 factor or added to another register (as well as added to a
1599 displacement). */
1600
1601 #define INDEX_REG_CLASS NO_REGS
1602
1603 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1604 registers explicitly used in the rtl to be used as spill registers
1605 but prevents the compiler from extending the lifetime of these
1606 registers. */
1607
1608 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1609
1610 /* This macro is used later on in the file. */
1611 #define GR_REG_CLASS_P(CLASS) \
1612 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1613 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1614 || (CLASS) == V1_REG \
1615 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1616
1617 /* This macro is also used later on in the file. */
1618 #define COP_REG_CLASS_P(CLASS) \
1619 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1620
1621 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1622 is the default value (allocate the registers in numeric order). We
1623 define it just so that we can override it for the mips16 target in
1624 ORDER_REGS_FOR_LOCAL_ALLOC. */
1625
1626 #define REG_ALLOC_ORDER \
1627 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1628 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1629 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1630 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1631 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1632 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1633 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1634 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1635 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1636 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1637 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1638 176,177,178,179,180,181,182,183,184,185,186,187 \
1639 }
1640
1641 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1642 to be rearranged based on a particular function. On the mips16, we
1643 want to allocate $24 (T_REG) before other registers for
1644 instructions for which it is possible. */
1645
1646 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1647
1648 /* True if VALUE is an unsigned 6-bit number. */
1649
1650 #define UIMM6_OPERAND(VALUE) \
1651 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1652
1653 /* True if VALUE is a signed 10-bit number. */
1654
1655 #define IMM10_OPERAND(VALUE) \
1656 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1657
1658 /* True if VALUE is a signed 16-bit number. */
1659
1660 #define SMALL_OPERAND(VALUE) \
1661 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1662
1663 /* True if VALUE is an unsigned 16-bit number. */
1664
1665 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1666 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1667
1668 /* True if VALUE can be loaded into a register using LUI. */
1669
1670 #define LUI_OPERAND(VALUE) \
1671 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1672 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1673
1674 /* Return a value X with the low 16 bits clear, and such that
1675 VALUE - X is a signed 16-bit value. */
1676
1677 #define CONST_HIGH_PART(VALUE) \
1678 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1679
1680 #define CONST_LOW_PART(VALUE) \
1681 ((VALUE) - CONST_HIGH_PART (VALUE))
1682
1683 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1684 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1685 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1686
1687 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1688 mips_preferred_reload_class (X, CLASS)
1689
1690 /* Certain machines have the property that some registers cannot be
1691 copied to some other registers without using memory. Define this
1692 macro on those machines to be a C expression that is nonzero if
1693 objects of mode MODE in registers of CLASS1 can only be copied to
1694 registers of class CLASS2 by storing a register of CLASS1 into
1695 memory and loading that memory location into a register of CLASS2.
1696
1697 Do not define this macro if its value would always be zero. */
1698 #if 0
1699 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1700 ((!TARGET_DEBUG_H_MODE \
1701 && GET_MODE_CLASS (MODE) == MODE_INT \
1702 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1703 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1704 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1705 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1706 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1707 #endif
1708 /* The HI and LO registers can only be reloaded via the general
1709 registers. Condition code registers can only be loaded to the
1710 general registers, and from the floating point registers. */
1711
1712 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1713 mips_secondary_reload_class (CLASS, MODE, X, 1)
1714 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1715 mips_secondary_reload_class (CLASS, MODE, X, 0)
1716
1717 /* Return the maximum number of consecutive registers
1718 needed to represent mode MODE in a register of class CLASS. */
1719
1720 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1721
1722 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1723 mips_cannot_change_mode_class (FROM, TO, CLASS)
1724 \f
1725 /* Stack layout; function entry, exit and calling. */
1726
1727 #define STACK_GROWS_DOWNWARD
1728
1729 /* The offset of the first local variable from the beginning of the frame.
1730 See compute_frame_size for details about the frame layout.
1731
1732 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1733 we assume that we will need 16 bytes of argument space. This is because
1734 the value profiling code may emit calls to cmpdi2 in leaf functions.
1735 Without this hack, the local variables will start at sp+8 and the gp save
1736 area will be at sp+16, and thus they will overlap. compute_frame_size is
1737 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1738 will end up as 24 instead of 8. This won't be needed if profiling code is
1739 inserted before virtual register instantiation. */
1740
1741 #define STARTING_FRAME_OFFSET \
1742 ((flag_profile_values && ! TARGET_64BIT \
1743 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1744 : current_function_outgoing_args_size) \
1745 + (TARGET_ABICALLS && !TARGET_NEWABI \
1746 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1747
1748 #define RETURN_ADDR_RTX mips_return_addr
1749
1750 /* Since the mips16 ISA mode is encoded in the least-significant bit
1751 of the address, mask it off return addresses for purposes of
1752 finding exception handling regions. */
1753
1754 #define MASK_RETURN_ADDR GEN_INT (-2)
1755
1756
1757 /* Similarly, don't use the least-significant bit to tell pointers to
1758 code from vtable index. */
1759
1760 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1761
1762 /* The eliminations to $17 are only used for mips16 code. See the
1763 definition of HARD_FRAME_POINTER_REGNUM. */
1764
1765 #define ELIMINABLE_REGS \
1766 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1767 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1768 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1769 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1770 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1771 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1772
1773 /* We can always eliminate to the hard frame pointer. We can eliminate
1774 to the stack pointer unless a frame pointer is needed.
1775
1776 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1777 reload may be unable to compute the address of a local variable,
1778 since there is no way to add a large constant to the stack pointer
1779 without using a temporary register. */
1780 #define CAN_ELIMINATE(FROM, TO) \
1781 ((TO) == HARD_FRAME_POINTER_REGNUM \
1782 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1783 && (!TARGET_MIPS16 \
1784 || compute_frame_size (get_frame_size ()) < 32768)))
1785
1786 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1787 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1788
1789 /* Allocate stack space for arguments at the beginning of each function. */
1790 #define ACCUMULATE_OUTGOING_ARGS 1
1791
1792 /* The argument pointer always points to the first argument. */
1793 #define FIRST_PARM_OFFSET(FNDECL) 0
1794
1795 /* o32 and o64 reserve stack space for all argument registers. */
1796 #define REG_PARM_STACK_SPACE(FNDECL) \
1797 (TARGET_OLDABI \
1798 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1799 : 0)
1800
1801 /* Define this if it is the responsibility of the caller to
1802 allocate the area reserved for arguments passed in registers.
1803 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1804 of this macro is to determine whether the space is included in
1805 `current_function_outgoing_args_size'. */
1806 #define OUTGOING_REG_PARM_STACK_SPACE
1807
1808 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1809 \f
1810 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1811
1812 /* Symbolic macros for the registers used to return integer and floating
1813 point values. */
1814
1815 #define GP_RETURN (GP_REG_FIRST + 2)
1816 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1817
1818 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1819
1820 /* Symbolic macros for the first/last argument registers. */
1821
1822 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1823 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1824 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1825 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1826
1827 #define LIBCALL_VALUE(MODE) \
1828 mips_function_value (NULL_TREE, NULL, (MODE))
1829
1830 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1831 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1832
1833 /* 1 if N is a possible register number for a function value.
1834 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1835 Currently, R2 and F0 are only implemented here (C has no complex type) */
1836
1837 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1838 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1839 && (N) == FP_RETURN + 2))
1840
1841 /* 1 if N is a possible register number for function argument passing.
1842 We have no FP argument registers when soft-float. When FP registers
1843 are 32 bits, we can't directly reference the odd numbered ones. */
1844
1845 #define FUNCTION_ARG_REGNO_P(N) \
1846 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1847 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1848 && !fixed_regs[N])
1849 \f
1850 /* This structure has to cope with two different argument allocation
1851 schemes. Most MIPS ABIs view the arguments as a structure, of which
1852 the first N words go in registers and the rest go on the stack. If I
1853 < N, the Ith word might go in Ith integer argument register or in a
1854 floating-point register. For these ABIs, we only need to remember
1855 the offset of the current argument into the structure.
1856
1857 The EABI instead allocates the integer and floating-point arguments
1858 separately. The first N words of FP arguments go in FP registers,
1859 the rest go on the stack. Likewise, the first N words of the other
1860 arguments go in integer registers, and the rest go on the stack. We
1861 need to maintain three counts: the number of integer registers used,
1862 the number of floating-point registers used, and the number of words
1863 passed on the stack.
1864
1865 We could keep separate information for the two ABIs (a word count for
1866 the standard ABIs, and three separate counts for the EABI). But it
1867 seems simpler to view the standard ABIs as forms of EABI that do not
1868 allocate floating-point registers.
1869
1870 So for the standard ABIs, the first N words are allocated to integer
1871 registers, and function_arg decides on an argument-by-argument basis
1872 whether that argument should really go in an integer register, or in
1873 a floating-point one. */
1874
1875 typedef struct mips_args {
1876 /* Always true for varargs functions. Otherwise true if at least
1877 one argument has been passed in an integer register. */
1878 int gp_reg_found;
1879
1880 /* The number of arguments seen so far. */
1881 unsigned int arg_number;
1882
1883 /* The number of integer registers used so far. For all ABIs except
1884 EABI, this is the number of words that have been added to the
1885 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1886 unsigned int num_gprs;
1887
1888 /* For EABI, the number of floating-point registers used so far. */
1889 unsigned int num_fprs;
1890
1891 /* The number of words passed on the stack. */
1892 unsigned int stack_words;
1893
1894 /* On the mips16, we need to keep track of which floating point
1895 arguments were passed in general registers, but would have been
1896 passed in the FP regs if this were a 32-bit function, so that we
1897 can move them to the FP regs if we wind up calling a 32-bit
1898 function. We record this information in fp_code, encoded in base
1899 four. A zero digit means no floating point argument, a one digit
1900 means an SFmode argument, and a two digit means a DFmode argument,
1901 and a three digit is not used. The low order digit is the first
1902 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1903 an SFmode argument. ??? A more sophisticated approach will be
1904 needed if MIPS_ABI != ABI_32. */
1905 int fp_code;
1906
1907 /* True if the function has a prototype. */
1908 int prototype;
1909 } CUMULATIVE_ARGS;
1910
1911 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1912 for a call to a function whose data type is FNTYPE.
1913 For a library call, FNTYPE is 0. */
1914
1915 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1916 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1917
1918 /* Update the data in CUM to advance over an argument
1919 of mode MODE and data type TYPE.
1920 (TYPE is null for libcalls where that information may not be available.) */
1921
1922 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1923 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1924
1925 /* Determine where to put an argument to a function.
1926 Value is zero to push the argument on the stack,
1927 or a hard register in which to store the argument.
1928
1929 MODE is the argument's machine mode.
1930 TYPE is the data type of the argument (as a tree).
1931 This is null for libcalls where that information may
1932 not be available.
1933 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1934 the preceding args and about the function being called.
1935 NAMED is nonzero if this argument is a named parameter
1936 (otherwise it is an extra parameter matching an ellipsis). */
1937
1938 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1939 function_arg( &CUM, MODE, TYPE, NAMED)
1940
1941 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1942
1943 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1944 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1945
1946 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1947 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1948
1949 /* True if using EABI and varargs can be passed in floating-point
1950 registers. Under these conditions, we need a more complex form
1951 of va_list, which tracks GPR, FPR and stack arguments separately. */
1952 #define EABI_FLOAT_VARARGS_P \
1953 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
1954
1955 \f
1956 /* Say that the epilogue uses the return address register. Note that
1957 in the case of sibcalls, the values "used by the epilogue" are
1958 considered live at the start of the called function. */
1959 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
1960
1961 /* Treat LOC as a byte offset from the stack pointer and round it up
1962 to the next fully-aligned offset. */
1963 #define MIPS_STACK_ALIGN(LOC) \
1964 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
1965
1966 \f
1967 /* Implement `va_start' for varargs and stdarg. */
1968 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1969 mips_va_start (valist, nextarg)
1970 \f
1971 /* Output assembler code to FILE to increment profiler label # LABELNO
1972 for profiling a function entry. */
1973
1974 #define FUNCTION_PROFILER(FILE, LABELNO) \
1975 { \
1976 if (TARGET_MIPS16) \
1977 sorry ("mips16 function profiling"); \
1978 fprintf (FILE, "\t.set\tnoat\n"); \
1979 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
1980 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
1981 if (!TARGET_NEWABI) \
1982 { \
1983 fprintf (FILE, \
1984 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
1985 TARGET_64BIT ? "dsubu" : "subu", \
1986 reg_names[STACK_POINTER_REGNUM], \
1987 reg_names[STACK_POINTER_REGNUM], \
1988 Pmode == DImode ? 16 : 8); \
1989 } \
1990 fprintf (FILE, "\tjal\t_mcount\n"); \
1991 fprintf (FILE, "\t.set\tat\n"); \
1992 }
1993
1994 /* No mips port has ever used the profiler counter word, so don't emit it
1995 or the label for it. */
1996
1997 #define NO_PROFILE_COUNTERS 1
1998
1999 /* Define this macro if the code for function profiling should come
2000 before the function prologue. Normally, the profiling code comes
2001 after. */
2002
2003 /* #define PROFILE_BEFORE_PROLOGUE */
2004
2005 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2006 the stack pointer does not matter. The value is tested only in
2007 functions that have frame pointers.
2008 No definition is equivalent to always zero. */
2009
2010 #define EXIT_IGNORE_STACK 1
2011
2012 \f
2013 /* A C statement to output, on the stream FILE, assembler code for a
2014 block of data that contains the constant parts of a trampoline.
2015 This code should not include a label--the label is taken care of
2016 automatically. */
2017
2018 #define TRAMPOLINE_TEMPLATE(STREAM) \
2019 { \
2020 if (ptr_mode == DImode) \
2021 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2022 else \
2023 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2024 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2025 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2026 if (ptr_mode == DImode) \
2027 { \
2028 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2029 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2030 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2031 } \
2032 else \
2033 { \
2034 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2035 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2036 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2037 } \
2038 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2039 if (ptr_mode == DImode) \
2040 { \
2041 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2042 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2043 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2044 } \
2045 else \
2046 { \
2047 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2048 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2049 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2050 } \
2051 }
2052
2053 /* A C expression for the size in bytes of the trampoline, as an
2054 integer. */
2055
2056 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2057
2058 /* Alignment required for trampolines, in bits. */
2059
2060 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2061
2062 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2063 program and data caches. */
2064
2065 #ifndef CACHE_FLUSH_FUNC
2066 #define CACHE_FLUSH_FUNC "_flush_cache"
2067 #endif
2068
2069 /* A C statement to initialize the variable parts of a trampoline.
2070 ADDR is an RTX for the address of the trampoline; FNADDR is an
2071 RTX for the address of the nested function; STATIC_CHAIN is an
2072 RTX for the static chain value that should be passed to the
2073 function when it is called. */
2074
2075 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2076 { \
2077 rtx func_addr, chain_addr; \
2078 \
2079 func_addr = plus_constant (ADDR, 32); \
2080 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2081 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2082 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2083 \
2084 /* Flush both caches. We need to flush the data cache in case \
2085 the system has a write-back cache. */ \
2086 /* ??? Should check the return value for errors. */ \
2087 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2088 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2089 0, VOIDmode, 3, ADDR, Pmode, \
2090 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2091 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2092 }
2093 \f
2094 /* Addressing modes, and classification of registers for them. */
2095
2096 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2097 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2098 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2099
2100 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2101 and check its validity for a certain class.
2102 We have two alternate definitions for each of them.
2103 The usual definition accepts all pseudo regs; the other rejects them all.
2104 The symbol REG_OK_STRICT causes the latter definition to be used.
2105
2106 Most source files want to accept pseudo regs in the hope that
2107 they will get allocated to the class that the insn wants them to be in.
2108 Some source files that are used after register allocation
2109 need to be strict. */
2110
2111 #ifndef REG_OK_STRICT
2112 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2113 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2114 #else
2115 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2116 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2117 #endif
2118
2119 #define REG_OK_FOR_INDEX_P(X) 0
2120
2121 \f
2122 /* Maximum number of registers that can appear in a valid memory address. */
2123
2124 #define MAX_REGS_PER_ADDRESS 1
2125
2126 #ifdef REG_OK_STRICT
2127 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2128 { \
2129 if (mips_legitimate_address_p (MODE, X, 1)) \
2130 goto ADDR; \
2131 }
2132 #else
2133 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2134 { \
2135 if (mips_legitimate_address_p (MODE, X, 0)) \
2136 goto ADDR; \
2137 }
2138 #endif
2139
2140 /* Check for constness inline but use mips_legitimate_address_p
2141 to check whether a constant really is an address. */
2142
2143 #define CONSTANT_ADDRESS_P(X) \
2144 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2145
2146 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2147
2148 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2149 do { \
2150 if (mips_legitimize_address (&(X), MODE)) \
2151 goto WIN; \
2152 } while (0)
2153
2154
2155 /* A C statement or compound statement with a conditional `goto
2156 LABEL;' executed if memory address X (an RTX) can have different
2157 meanings depending on the machine mode of the memory reference it
2158 is used for.
2159
2160 Autoincrement and autodecrement addresses typically have
2161 mode-dependent effects because the amount of the increment or
2162 decrement is the size of the operand being addressed. Some
2163 machines have other mode-dependent addresses. Many RISC machines
2164 have no mode-dependent addresses.
2165
2166 You may assume that ADDR is a valid address for the machine. */
2167
2168 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2169
2170 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2171 'the start of the function that this code is output in'. */
2172
2173 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2174 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2175 asm_fprintf ((FILE), "%U%s", \
2176 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2177 else \
2178 asm_fprintf ((FILE), "%U%s", (NAME))
2179 \f
2180 /* Flag to mark a function decl symbol that requires a long call. */
2181 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2182 #define SYMBOL_REF_LONG_CALL_P(X) \
2183 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2184
2185 /* Specify the machine mode that this machine uses
2186 for the index in the tablejump instruction.
2187 ??? Using HImode in mips16 mode can cause overflow. */
2188 #define CASE_VECTOR_MODE \
2189 (TARGET_MIPS16 ? HImode : ptr_mode)
2190
2191 /* Define as C expression which evaluates to nonzero if the tablejump
2192 instruction expects the table to contain offsets from the address of the
2193 table.
2194 Do not define this if the table should contain absolute addresses. */
2195 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2196
2197 /* Define this as 1 if `char' should by default be signed; else as 0. */
2198 #ifndef DEFAULT_SIGNED_CHAR
2199 #define DEFAULT_SIGNED_CHAR 1
2200 #endif
2201
2202 /* Max number of bytes we can move from memory to memory
2203 in one reasonably fast instruction. */
2204 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2205 #define MAX_MOVE_MAX 8
2206
2207 /* Define this macro as a C expression which is nonzero if
2208 accessing less than a word of memory (i.e. a `char' or a
2209 `short') is no faster than accessing a word of memory, i.e., if
2210 such access require more than one instruction or if there is no
2211 difference in cost between byte and (aligned) word loads.
2212
2213 On RISC machines, it tends to generate better code to define
2214 this as 1, since it avoids making a QI or HI mode register. */
2215 #define SLOW_BYTE_ACCESS 1
2216
2217 /* Define this to be nonzero if shift instructions ignore all but the low-order
2218 few bits. */
2219 #define SHIFT_COUNT_TRUNCATED 1
2220
2221 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2222 is done just by pretending it is already truncated. */
2223 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2224 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2225
2226
2227 /* Specify the machine mode that pointers have.
2228 After generation of rtl, the compiler makes no further distinction
2229 between pointers and any other objects of this machine mode. */
2230
2231 #ifndef Pmode
2232 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2233 #endif
2234
2235 /* Give call MEMs SImode since it is the "most permissive" mode
2236 for both 32-bit and 64-bit targets. */
2237
2238 #define FUNCTION_MODE SImode
2239
2240 \f
2241 /* The cost of loading values from the constant pool. It should be
2242 larger than the cost of any constant we want to synthesize in-line. */
2243
2244 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2245
2246 /* A C expression for the cost of moving data from a register in
2247 class FROM to one in class TO. The classes are expressed using
2248 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2249 the default; other values are interpreted relative to that.
2250
2251 It is not required that the cost always equal 2 when FROM is the
2252 same as TO; on some machines it is expensive to move between
2253 registers if they are not general registers.
2254
2255 If reload sees an insn consisting of a single `set' between two
2256 hard registers, and if `REGISTER_MOVE_COST' applied to their
2257 classes returns a value of 2, reload does not check to ensure
2258 that the constraints of the insn are met. Setting a cost of
2259 other than 2 will allow reload to verify that the constraints are
2260 met. You should do this if the `movM' pattern's constraints do
2261 not allow such copying. */
2262
2263 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2264 mips_register_move_cost (MODE, FROM, TO)
2265
2266 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2267 (mips_cost->memory_latency \
2268 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2269
2270 /* Define if copies to/from condition code registers should be avoided.
2271
2272 This is needed for the MIPS because reload_outcc is not complete;
2273 it needs to handle cases where the source is a general or another
2274 condition code register. */
2275 #define AVOID_CCMODE_COPIES
2276
2277 /* A C expression for the cost of a branch instruction. A value of
2278 1 is the default; other values are interpreted relative to that. */
2279
2280 #define BRANCH_COST mips_cost->branch_cost
2281 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2282
2283 /* If defined, modifies the length assigned to instruction INSN as a
2284 function of the context in which it is used. LENGTH is an lvalue
2285 that contains the initially computed length of the insn and should
2286 be updated with the correct length of the insn. */
2287 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2288 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2289
2290 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2291 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2292 its operands. */
2293 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2294 "%*" OPCODE "%?\t" OPERANDS "%/"
2295
2296 /* Return the asm template for a call. INSN is the instruction's mnemonic
2297 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2298 of the target.
2299
2300 When generating -mabicalls without explicit relocation operators,
2301 all calls should use assembly macros. Otherwise, all indirect
2302 calls should use "jr" or "jalr"; we will arrange to restore $gp
2303 afterwards if necessary. Finally, we can only generate direct
2304 calls for -mabicalls by temporarily switching to non-PIC mode. */
2305 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2306 (TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS \
2307 ? "%*" INSN "\t%" #OPNO "%/" \
2308 : REG_P (OPERANDS[OPNO]) \
2309 ? "%*" INSN "r\t%" #OPNO "%/" \
2310 : TARGET_ABICALLS \
2311 ? (".option\tpic0\n\t" \
2312 "%*" INSN "\t%" #OPNO "%/\n\t" \
2313 ".option\tpic2") \
2314 : "%*" INSN "\t%" #OPNO "%/")
2315 \f
2316 /* Control the assembler format that we output. */
2317
2318 /* Output to assembler file text saying following lines
2319 may contain character constants, extra white space, comments, etc. */
2320
2321 #ifndef ASM_APP_ON
2322 #define ASM_APP_ON " #APP\n"
2323 #endif
2324
2325 /* Output to assembler file text saying following lines
2326 no longer contain unusual constructs. */
2327
2328 #ifndef ASM_APP_OFF
2329 #define ASM_APP_OFF " #NO_APP\n"
2330 #endif
2331
2332 #define REGISTER_NAMES \
2333 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2336 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2337 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2338 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2339 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2340 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2341 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2342 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2343 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2344 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2345 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2346 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2347 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2348 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2349 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2350 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2351 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2352 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2353 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2354 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2355 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2356 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2357
2358 /* List the "software" names for each register. Also list the numerical
2359 names for $fp and $sp. */
2360
2361 #define ADDITIONAL_REGISTER_NAMES \
2362 { \
2363 { "$29", 29 + GP_REG_FIRST }, \
2364 { "$30", 30 + GP_REG_FIRST }, \
2365 { "at", 1 + GP_REG_FIRST }, \
2366 { "v0", 2 + GP_REG_FIRST }, \
2367 { "v1", 3 + GP_REG_FIRST }, \
2368 { "a0", 4 + GP_REG_FIRST }, \
2369 { "a1", 5 + GP_REG_FIRST }, \
2370 { "a2", 6 + GP_REG_FIRST }, \
2371 { "a3", 7 + GP_REG_FIRST }, \
2372 { "t0", 8 + GP_REG_FIRST }, \
2373 { "t1", 9 + GP_REG_FIRST }, \
2374 { "t2", 10 + GP_REG_FIRST }, \
2375 { "t3", 11 + GP_REG_FIRST }, \
2376 { "t4", 12 + GP_REG_FIRST }, \
2377 { "t5", 13 + GP_REG_FIRST }, \
2378 { "t6", 14 + GP_REG_FIRST }, \
2379 { "t7", 15 + GP_REG_FIRST }, \
2380 { "s0", 16 + GP_REG_FIRST }, \
2381 { "s1", 17 + GP_REG_FIRST }, \
2382 { "s2", 18 + GP_REG_FIRST }, \
2383 { "s3", 19 + GP_REG_FIRST }, \
2384 { "s4", 20 + GP_REG_FIRST }, \
2385 { "s5", 21 + GP_REG_FIRST }, \
2386 { "s6", 22 + GP_REG_FIRST }, \
2387 { "s7", 23 + GP_REG_FIRST }, \
2388 { "t8", 24 + GP_REG_FIRST }, \
2389 { "t9", 25 + GP_REG_FIRST }, \
2390 { "k0", 26 + GP_REG_FIRST }, \
2391 { "k1", 27 + GP_REG_FIRST }, \
2392 { "gp", 28 + GP_REG_FIRST }, \
2393 { "sp", 29 + GP_REG_FIRST }, \
2394 { "fp", 30 + GP_REG_FIRST }, \
2395 { "ra", 31 + GP_REG_FIRST }, \
2396 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2397 }
2398
2399 /* This is meant to be redefined in the host dependent files. It is a
2400 set of alternative names and regnums for mips coprocessors. */
2401
2402 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2403
2404 /* A C compound statement to output to stdio stream STREAM the
2405 assembler syntax for an instruction operand X. X is an RTL
2406 expression.
2407
2408 CODE is a value that can be used to specify one of several ways
2409 of printing the operand. It is used when identical operands
2410 must be printed differently depending on the context. CODE
2411 comes from the `%' specification that was used to request
2412 printing of the operand. If the specification was just `%DIGIT'
2413 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2414 is the ASCII code for LTR.
2415
2416 If X is a register, this macro should print the register's name.
2417 The names can be found in an array `reg_names' whose type is
2418 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2419
2420 When the machine description has a specification `%PUNCT' (a `%'
2421 followed by a punctuation character), this macro is called with
2422 a null pointer for X and the punctuation character for CODE.
2423
2424 See mips.c for the MIPS specific codes. */
2425
2426 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2427
2428 /* A C expression which evaluates to true if CODE is a valid
2429 punctuation character for use in the `PRINT_OPERAND' macro. If
2430 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2431 punctuation characters (except for the standard one, `%') are
2432 used in this way. */
2433
2434 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2435
2436 /* A C compound statement to output to stdio stream STREAM the
2437 assembler syntax for an instruction operand that is a memory
2438 reference whose address is ADDR. ADDR is an RTL expression. */
2439
2440 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2441
2442
2443 /* A C statement, to be executed after all slot-filler instructions
2444 have been output. If necessary, call `dbr_sequence_length' to
2445 determine the number of slots filled in a sequence (zero if not
2446 currently outputting a sequence), to decide how many no-ops to
2447 output, or whatever.
2448
2449 Don't define this macro if it has nothing to do, but it is
2450 helpful in reading assembly output if the extent of the delay
2451 sequence is made explicit (e.g. with white space).
2452
2453 Note that output routines for instructions with delay slots must
2454 be prepared to deal with not being output as part of a sequence
2455 (i.e. when the scheduling pass is not run, or when no slot
2456 fillers could be found.) The variable `final_sequence' is null
2457 when not processing a sequence, otherwise it contains the
2458 `sequence' rtx being output. */
2459
2460 #define DBR_OUTPUT_SEQEND(STREAM) \
2461 do \
2462 { \
2463 if (set_nomacro > 0 && --set_nomacro == 0) \
2464 fputs ("\t.set\tmacro\n", STREAM); \
2465 \
2466 if (set_noreorder > 0 && --set_noreorder == 0) \
2467 fputs ("\t.set\treorder\n", STREAM); \
2468 \
2469 fputs ("\n", STREAM); \
2470 } \
2471 while (0)
2472
2473
2474 /* How to tell the debugger about changes of source files. */
2475 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2476 mips_output_filename (STREAM, NAME)
2477
2478 /* mips-tfile does not understand .stabd directives. */
2479 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2480 dbxout_begin_stabn_sline (LINE); \
2481 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2482 } while (0)
2483
2484 /* Use .loc directives for SDB line numbers. */
2485 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2486 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2487
2488 /* The MIPS implementation uses some labels for its own purpose. The
2489 following lists what labels are created, and are all formed by the
2490 pattern $L[a-z].*. The machine independent portion of GCC creates
2491 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2492
2493 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2494 $Lb[0-9]+ Begin blocks for MIPS debug support
2495 $Lc[0-9]+ Label for use in s<xx> operation.
2496 $Le[0-9]+ End blocks for MIPS debug support */
2497
2498 #undef ASM_DECLARE_OBJECT_NAME
2499 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2500 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2501
2502 /* Globalizing directive for a label. */
2503 #define GLOBAL_ASM_OP "\t.globl\t"
2504
2505 /* This says how to define a global common symbol. */
2506
2507 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2508
2509 /* This says how to define a local common symbol (i.e., not visible to
2510 linker). */
2511
2512 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2513 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2514 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2515 #endif
2516
2517 /* This says how to output an external. It would be possible not to
2518 output anything and let undefined symbol become external. However
2519 the assembler uses length information on externals to allocate in
2520 data/sdata bss/sbss, thereby saving exec time. */
2521
2522 #undef ASM_OUTPUT_EXTERNAL
2523 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2524 mips_output_external(STREAM,DECL,NAME)
2525
2526 /* This is how to declare a function name. The actual work of
2527 emitting the label is moved to function_prologue, so that we can
2528 get the line number correctly emitted before the .ent directive,
2529 and after any .file directives. Define as empty so that the function
2530 is not declared before the .ent directive elsewhere. */
2531
2532 #undef ASM_DECLARE_FUNCTION_NAME
2533 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2534
2535 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2536 #define FUNCTION_NAME_ALREADY_DECLARED 0
2537 #endif
2538
2539 /* This is how to store into the string LABEL
2540 the symbol_ref name of an internal numbered label where
2541 PREFIX is the class of label and NUM is the number within the class.
2542 This is suitable for output with `assemble_name'. */
2543
2544 #undef ASM_GENERATE_INTERNAL_LABEL
2545 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2546 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2547
2548 /* This is how to output an element of a case-vector that is absolute. */
2549
2550 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2551 fprintf (STREAM, "\t%s\t%sL%d\n", \
2552 ptr_mode == DImode ? ".dword" : ".word", \
2553 LOCAL_LABEL_PREFIX, \
2554 VALUE)
2555
2556 /* This is how to output an element of a case-vector. We can make the
2557 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2558 is supported. */
2559
2560 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2561 do { \
2562 if (TARGET_MIPS16) \
2563 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2564 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2565 else if (TARGET_GPWORD) \
2566 fprintf (STREAM, "\t%s\t%sL%d\n", \
2567 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2568 LOCAL_LABEL_PREFIX, VALUE); \
2569 else \
2570 fprintf (STREAM, "\t%s\t%sL%d\n", \
2571 ptr_mode == DImode ? ".dword" : ".word", \
2572 LOCAL_LABEL_PREFIX, VALUE); \
2573 } while (0)
2574
2575 /* When generating MIPS16 code, we want the jump table to be in the text
2576 section so that we can load its address using a PC-relative addition. */
2577 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2578
2579 /* This is how to output an assembler line
2580 that says to advance the location counter
2581 to a multiple of 2**LOG bytes. */
2582
2583 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2584 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2585
2586 /* This is how to output an assembler line to advance the location
2587 counter by SIZE bytes. */
2588
2589 #undef ASM_OUTPUT_SKIP
2590 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2591 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2592
2593 /* This is how to output a string. */
2594 #undef ASM_OUTPUT_ASCII
2595 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2596 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2597
2598 /* Output #ident as a in the read-only data section. */
2599 #undef ASM_OUTPUT_IDENT
2600 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2601 { \
2602 const char *p = STRING; \
2603 int size = strlen (p) + 1; \
2604 switch_to_section (readonly_data_section); \
2605 assemble_string (p, size); \
2606 }
2607 \f
2608 /* Default to -G 8 */
2609 #ifndef MIPS_DEFAULT_GVALUE
2610 #define MIPS_DEFAULT_GVALUE 8
2611 #endif
2612
2613 /* Define the strings to put out for each section in the object file. */
2614 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2615 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2616
2617 #undef READONLY_DATA_SECTION_ASM_OP
2618 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2619 \f
2620 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2621 do \
2622 { \
2623 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2624 TARGET_64BIT ? "dsubu" : "subu", \
2625 reg_names[STACK_POINTER_REGNUM], \
2626 reg_names[STACK_POINTER_REGNUM], \
2627 TARGET_64BIT ? "sd" : "sw", \
2628 reg_names[REGNO], \
2629 reg_names[STACK_POINTER_REGNUM]); \
2630 } \
2631 while (0)
2632
2633 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2634 do \
2635 { \
2636 if (! set_noreorder) \
2637 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2638 \
2639 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2640 TARGET_64BIT ? "ld" : "lw", \
2641 reg_names[REGNO], \
2642 reg_names[STACK_POINTER_REGNUM], \
2643 TARGET_64BIT ? "daddu" : "addu", \
2644 reg_names[STACK_POINTER_REGNUM], \
2645 reg_names[STACK_POINTER_REGNUM]); \
2646 \
2647 if (! set_noreorder) \
2648 fprintf (STREAM, "\t.set\treorder\n"); \
2649 } \
2650 while (0)
2651
2652 /* How to start an assembler comment.
2653 The leading space is important (the mips native assembler requires it). */
2654 #ifndef ASM_COMMENT_START
2655 #define ASM_COMMENT_START " #"
2656 #endif
2657 \f
2658 /* Default definitions for size_t and ptrdiff_t. We must override the
2659 definitions from ../svr4.h on mips-*-linux-gnu. */
2660
2661 #undef SIZE_TYPE
2662 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2663
2664 #undef PTRDIFF_TYPE
2665 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2666 \f
2667 #ifndef __mips16
2668 /* Since the bits of the _init and _fini function is spread across
2669 many object files, each potentially with its own GP, we must assume
2670 we need to load our GP. We don't preserve $gp or $ra, since each
2671 init/fini chunk is supposed to initialize $gp, and crti/crtn
2672 already take care of preserving $ra and, when appropriate, $gp. */
2673 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2674 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2675 asm (SECTION_OP "\n\
2676 .set noreorder\n\
2677 bal 1f\n\
2678 nop\n\
2679 1: .cpload $31\n\
2680 .set reorder\n\
2681 jal " USER_LABEL_PREFIX #FUNC "\n\
2682 " TEXT_SECTION_ASM_OP);
2683 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2684 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2685 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2686 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2687 asm (SECTION_OP "\n\
2688 .set noreorder\n\
2689 bal 1f\n\
2690 nop\n\
2691 1: .set reorder\n\
2692 .cpsetup $31, $2, 1b\n\
2693 jal " USER_LABEL_PREFIX #FUNC "\n\
2694 " TEXT_SECTION_ASM_OP);
2695 #endif
2696 #endif
2697
2698 #ifndef HAVE_AS_TLS
2699 #define HAVE_AS_TLS 0
2700 #endif
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