| blob | a4db130ece2f0ad862ab4d26c324c3605ed26f5f |
1 ;; Machine description of the Renesas M32R cpu for GNU C compiler
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005,
3 ; 2007 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 \f
24 ;; UNSPEC_VOLATILE usage
25 (define_constants
26 [(UNSPECV_BLOCKAGE 0)
27 (UNSPECV_FLUSH_ICACHE 1)])
29 ;; UNSPEC usage
30 (define_constants
31 [(UNSPEC_LOAD_SDA_BASE 2)
32 (UNSPEC_SET_CBIT 3)
33 (UNSPEC_PIC_LOAD_ADDR 4)
34 (UNSPEC_GET_PC 5)
35 (UNSPEC_GOTOFF 6)
36 ])
38 ;; Insn type. Used to default other attribute values.
39 (define_attr "type"
40 "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
41 (const_string "misc"))
43 ;; Length in bytes.
44 (define_attr "length" ""
45 (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")
46 (const_int 2)
48 (eq_attr "type" "int4,load4,store4,shift4,div4")
49 (const_int 4)
51 (eq_attr "type" "multi")
52 (const_int 8)
54 (eq_attr "type" "uncond_branch,branch,call")
55 (const_int 4)]
57 (const_int 4)))
59 ;; The length here is the length of a single asm. Unfortunately it might be
60 ;; 2 or 4 so we must allow for 4. That's ok though.
61 (define_asm_attributes
62 [(set_attr "length" "4")
63 (set_attr "type" "multi")])
65 ;; Whether an instruction is short (16-bit) or long (32-bit).
66 (define_attr "insn_size" "short,long"
67 (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")
68 (const_string "short")
69 (const_string "long")))
71 ;; The target CPU we're compiling for.
72 (define_attr "cpu" "m32r,m32r2,m32rx"
73 (cond [(ne (symbol_ref "TARGET_M32RX") (const_int 0))
74 (const_string "m32rx")
75 (ne (symbol_ref "TARGET_M32R2") (const_int 0))
76 (const_string "m32r2")]
77 (const_string "m32r")))
79 ;; Defines the pipeline where an instruction can be executed on.
80 ;; For the M32R, a short instruction can execute one of the two pipes.
81 ;; For the M32Rx, the restrictions are modelled in the second
82 ;; condition of this attribute definition.
83 (define_attr "m32r_pipeline" "either,s,o,long"
84 (cond [(and (eq_attr "cpu" "m32r")
85 (eq_attr "insn_size" "short"))
86 (const_string "either")
87 (eq_attr "insn_size" "!short")
88 (const_string "long")]
89 (cond [(eq_attr "type" "int2")
90 (const_string "either")
91 (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
92 (const_string "o")
93 (eq_attr "type" "mul2")
94 (const_string "s")]
95 (const_string "long"))))
96 \f
97 ;; ::::::::::::::::::::
98 ;; ::
99 ;; :: Pipeline description
100 ;; ::
101 ;; ::::::::::::::::::::
103 ;; This model is based on Chapter 2, Appendix 3 and Appendix 4 of the
104 ;; "M32R-FPU Software Manual", Revision 1.01, plus additional information
105 ;; obtained by our best friend and mine, Google.
106 ;;
107 ;; The pipeline is modelled as a fetch unit, and a core with a memory unit,
108 ;; two execution units, where "fetch" models IF and D, "memory" for MEM1
109 ;; and MEM2, and "EXEC" for E, E1, E2, EM, and EA. Writeback and
110 ;; bypasses are not modelled.
111 (define_automaton "m32r")
113 ;; We pretend there are two short (16 bits) instruction fetchers. The
114 ;; "s" short fetcher cannot be reserved until the "o" short fetcher is
115 ;; reserved. Some instructions reserve both the left and right fetchers.
116 ;; These fetch units are a hack to get GCC to better pack the instructions
117 ;; for the M32Rx processor, which has two execution pipes.
118 ;;
119 ;; In reality there is only one decoder, which can decode either two 16-bit
120 ;; instructions, or a single 32-bit instruction.
121 ;;
122 ;; Note, "fetch" models both the IF and the D pipeline stages.
123 ;;
124 ;; The m32rx core has two execution pipes. We name them o_E and s_E.
125 ;; In addition, there's a memory unit.
127 (define_cpu_unit "o_IF,s_IF,o_E,s_E,memory" "m32r")
129 ;; Prevent the s pipe from being reserved before the o pipe.
130 (absence_set "s_IF" "o_IF")
131 (absence_set "s_E" "o_E")
133 ;; On the M32Rx, long instructions execute on both pipes, so reserve
134 ;; both fetch slots and both pipes.
135 (define_reservation "long_IF" "o_IF+s_IF")
136 (define_reservation "long_E" "o_E+s_E")
138 ;; ::::::::::::::::::::
140 ;; Simple instructions do 4 stages: IF D E WB. WB is not modelled.
141 ;; Hence, ready latency is 1.
142 (define_insn_reservation "short_left" 1
143 (and (eq_attr "m32r_pipeline" "o")
144 (and (eq_attr "insn_size" "short")
145 (eq_attr "type" "!load2")))
146 "o_IF,o_E")
148 (define_insn_reservation "short_right" 1
149 (and (eq_attr "m32r_pipeline" "s")
150 (and (eq_attr "insn_size" "short")
151 (eq_attr "type" "!load2")))
152 "s_IF,s_E")
154 (define_insn_reservation "short_either" 1
155 (and (eq_attr "m32r_pipeline" "either")
156 (and (eq_attr "insn_size" "short")
157 (eq_attr "type" "!load2")))
158 "o_IF|s_IF,o_E|s_E")
160 (define_insn_reservation "long_m32r" 1
161 (and (eq_attr "cpu" "m32r")
162 (and (eq_attr "insn_size" "long")
163 (eq_attr "type" "!load4,load8")))
164 "long_IF,long_E")
166 (define_insn_reservation "long_m32rx" 2
167 (and (eq_attr "m32r_pipeline" "long")
168 (and (eq_attr "insn_size" "long")
169 (eq_attr "type" "!load4,load8")))
170 "long_IF,long_E")
172 ;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
173 ;; MEM1 may require more than one cycle depending on locality. We
174 ;; optimistically assume all memory is nearby, i.e. MEM1 takes only
175 ;; one cycle. Hence, ready latency is 3.
177 ;; The M32Rx can do short load/store only on the left pipe.
178 (define_insn_reservation "short_load_left" 3
179 (and (eq_attr "m32r_pipeline" "o")
180 (and (eq_attr "insn_size" "short")
181 (eq_attr "type" "load2")))
182 "o_IF,o_E,memory*2")
184 (define_insn_reservation "short_load" 3
185 (and (eq_attr "m32r_pipeline" "either")
186 (and (eq_attr "insn_size" "short")
187 (eq_attr "type" "load2")))
188 "s_IF|o_IF,s_E|o_E,memory*2")
190 (define_insn_reservation "long_load" 3
191 (and (eq_attr "cpu" "m32r")
192 (and (eq_attr "insn_size" "long")
193 (eq_attr "type" "load4,load8")))
194 "long_IF,long_E,memory*2")
196 (define_insn_reservation "long_load_m32rx" 3
197 (and (eq_attr "m32r_pipeline" "long")
198 (eq_attr "type" "load4,load8"))
199 "long_IF,long_E,memory*2")
201 \f
202 (include "predicates.md")
204 ;; Expand prologue as RTL
205 (define_expand "prologue"
206 [(const_int 1)]
207 ""
208 "
209 {
210 m32r_expand_prologue ();
211 DONE;
212 }")
214 ;; Expand epilogue as RTL
215 (define_expand "epilogue"
216 [(return)]
217 ""
218 "
219 {
220 m32r_expand_epilogue ();
221 emit_jump_insn (gen_return_normal ());
222 DONE;
223 }")
224 \f
225 ;; Move instructions.
226 ;;
227 ;; For QI and HI moves, the register must contain the full properly
228 ;; sign-extended value. nonzero_bits assumes this [otherwise
229 ;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it
230 ;; says it's a kludge and the .md files should be fixed instead].
232 (define_expand "movqi"
233 [(set (match_operand:QI 0 "general_operand" "")
234 (match_operand:QI 1 "general_operand" ""))]
235 ""
236 "
237 {
238 /* Fixup PIC cases. */
239 if (flag_pic)
240 {
241 if (symbolic_operand (operands[1], QImode))
242 {
243 if (reload_in_progress || reload_completed)
244 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
245 else
246 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
247 }
248 }
250 /* Everything except mem = const or mem = mem can be done easily.
251 Objects in the small data area are handled too. */
253 if (GET_CODE (operands[0]) == MEM)
254 operands[1] = force_reg (QImode, operands[1]);
255 }")
257 (define_insn "*movqi_insn"
258 [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
259 (match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]
260 "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
261 "@
262 mv %0,%1
263 ldi %0,%#%1
264 ldi %0,%#%1
265 ldub %0,%1
266 ldub %0,%1
267 stb %1,%0
268 stb %1,%0"
269 [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")
270 (set_attr "length" "2,2,4,2,4,2,4")])
272 (define_expand "movhi"
273 [(set (match_operand:HI 0 "general_operand" "")
274 (match_operand:HI 1 "general_operand" ""))]
275 ""
276 "
277 {
278 /* Fixup PIC cases. */
279 if (flag_pic)
280 {
281 if (symbolic_operand (operands[1], HImode))
282 {
283 if (reload_in_progress || reload_completed)
284 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
285 else
286 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
287 }
288 }
290 /* Everything except mem = const or mem = mem can be done easily. */
292 if (GET_CODE (operands[0]) == MEM)
293 operands[1] = force_reg (HImode, operands[1]);
294 }")
296 (define_insn "*movhi_insn"
297 [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
298 (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]
299 "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
300 "@
301 mv %0,%1
302 ldi %0,%#%1
303 ldi %0,%#%1
304 ld24 %0,%#%1
305 lduh %0,%1
306 lduh %0,%1
307 sth %1,%0
308 sth %1,%0"
309 [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")
310 (set_attr "length" "2,2,4,4,2,4,2,4")])
312 (define_expand "movsi_push"
313 [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))
314 (match_operand:SI 1 "register_operand" ""))]
315 ""
316 "")
318 (define_expand "movsi_pop"
319 [(set (match_operand:SI 0 "register_operand" "")
320 (mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]
321 ""
322 "")
324 (define_expand "movsi"
325 [(set (match_operand:SI 0 "general_operand" "")
326 (match_operand:SI 1 "general_operand" ""))]
327 ""
328 "
329 {
330 /* Fixup PIC cases. */
331 if (flag_pic)
332 {
333 if (symbolic_operand (operands[1], SImode))
334 {
335 if (reload_in_progress || reload_completed)
336 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
337 else
338 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
339 }
340 }
342 /* Everything except mem = const or mem = mem can be done easily. */
344 if (GET_CODE (operands[0]) == MEM)
345 operands[1] = force_reg (SImode, operands[1]);
347 /* Small Data Area reference? */
348 if (small_data_operand (operands[1], SImode))
349 {
350 emit_insn (gen_movsi_sda (operands[0], operands[1]));
351 DONE;
352 }
354 /* If medium or large code model, symbols have to be loaded with
355 seth/add3. */
356 if (addr32_operand (operands[1], SImode))
357 {
358 emit_insn (gen_movsi_addr32 (operands[0], operands[1]));
359 DONE;
360 }
361 }")
363 ;; ??? Do we need a const_double constraint here for large unsigned values?
364 (define_insn "*movsi_insn"
365 [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
366 (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
367 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
368 "*
369 {
370 if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == SUBREG)
371 {
372 switch (GET_CODE (operands[1]))
373 {
374 HOST_WIDE_INT value;
376 default:
377 break;
379 case REG:
380 case SUBREG:
381 return \"mv %0,%1\";
383 case MEM:
384 if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
385 && XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
386 return \"pop %0\";
388 return \"ld %0,%1\";
390 case CONST_INT:
391 value = INTVAL (operands[1]);
392 if (INT16_P (value))
393 return \"ldi %0,%#%1\\t; %X1\";
395 if (UINT24_P (value))
396 return \"ld24 %0,%#%1\\t; %X1\";
398 if (UPPER16_P (value))
399 return \"seth %0,%#%T1\\t; %X1\";
401 return \"#\";
403 case CONST:
404 case SYMBOL_REF:
405 case LABEL_REF:
406 if (TARGET_ADDR24)
407 return \"ld24 %0,%#%1\";
409 return \"#\";
410 }
411 }
413 else if (GET_CODE (operands[0]) == MEM
414 && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
415 {
416 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
417 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
418 return \"push %1\";
420 return \"st %1,%0\";
421 }
423 gcc_unreachable ();
424 }"
425 [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
426 (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
428 ; Try to use a four byte / two byte pair for constants not loadable with
429 ; ldi, ld24, seth.
431 (define_split
432 [(set (match_operand:SI 0 "register_operand" "")
433 (match_operand:SI 1 "two_insn_const_operand" ""))]
434 ""
435 [(set (match_dup 0) (match_dup 2))
436 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
437 "
438 {
439 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
440 unsigned HOST_WIDE_INT tmp;
441 int shift;
443 /* In all cases we will emit two instructions. However we try to
444 use 2 byte instructions wherever possible. We can assume the
445 constant isn't loadable with any of ldi, ld24, or seth. */
447 /* See if we can load a 24-bit unsigned value and invert it. */
448 if (UINT24_P (~ val))
449 {
450 emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
451 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
452 DONE;
453 }
455 /* See if we can load a 24-bit unsigned value and shift it into place.
456 0x01fffffe is just beyond ld24's range. */
457 for (shift = 1, tmp = 0x01fffffe;
458 shift < 8;
459 ++shift, tmp <<= 1)
460 {
461 if ((val & ~tmp) == 0)
462 {
463 emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));
464 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));
465 DONE;
466 }
467 }
469 /* Can't use any two byte insn, fall back to seth/or3. Use ~0xffff instead
470 of 0xffff0000, since the later fails on a 64-bit host. */
471 operands[2] = GEN_INT ((val) & ~0xffff);
472 operands[3] = GEN_INT ((val) & 0xffff);
473 }")
475 (define_split
476 [(set (match_operand:SI 0 "register_operand" "")
477 (match_operand:SI 1 "seth_add3_operand" ""))]
478 "TARGET_ADDR32"
479 [(set (match_dup 0)
480 (high:SI (match_dup 1)))
481 (set (match_dup 0)
482 (lo_sum:SI (match_dup 0)
483 (match_dup 1)))]
484 "")
486 ;; Small data area support.
487 ;; The address of _SDA_BASE_ is loaded into a register and all objects in
488 ;; the small data area are indexed off that. This is done for each reference
489 ;; but cse will clean things up for us. We let the compiler choose the
490 ;; register to use so we needn't allocate (and maybe even fix) a special
491 ;; register to use. Since the load and store insns have a 16-bit offset the
492 ;; total size of the data area can be 64K. However, if the data area lives
493 ;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
494 ;; would then yield 3 instructions to reference an object [though there would
495 ;; be no net loss if two or more objects were referenced]. The 3 insns can be
496 ;; reduced back to 2 if the size of the small data area were reduced to 32K
497 ;; [then seth + ld/st would work for any object in the area]. Doing this
498 ;; would require special handling of _SDA_BASE_ (its value would be
499 ;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different
500 ;; [I think]. What to do about this is deferred until later and for now we
501 ;; require .sdata to be in the first 16M.
503 (define_expand "movsi_sda"
504 [(set (match_dup 2)
505 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
506 (set (match_operand:SI 0 "register_operand" "")
507 (lo_sum:SI (match_dup 2)
508 (match_operand:SI 1 "small_data_operand" "")))]
509 ""
510 "
511 {
512 if (reload_in_progress || reload_completed)
513 operands[2] = operands[0];
514 else
515 operands[2] = gen_reg_rtx (SImode);
516 }")
518 (define_insn "*load_sda_base_32"
519 [(set (match_operand:SI 0 "register_operand" "=r")
520 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
521 "TARGET_ADDR32"
522 "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
523 [(set_attr "type" "multi")
524 (set_attr "length" "8")])
526 (define_insn "*load_sda_base"
527 [(set (match_operand:SI 0 "register_operand" "=r")
528 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
529 ""
530 "ld24 %0,#_SDA_BASE_"
531 [(set_attr "type" "int4")
532 (set_attr "length" "4")])
534 ;; 32-bit address support.
536 (define_expand "movsi_addr32"
537 [(set (match_dup 2)
538 ; addr32_operand isn't used because it's too restrictive,
539 ; seth_add3_operand is more general and thus safer.
540 (high:SI (match_operand:SI 1 "seth_add3_operand" "")))
541 (set (match_operand:SI 0 "register_operand" "")
542 (lo_sum:SI (match_dup 2) (match_dup 1)))]
543 ""
544 "
545 {
546 if (reload_in_progress || reload_completed)
547 operands[2] = operands[0];
548 else
549 operands[2] = gen_reg_rtx (SImode);
550 }")
552 (define_insn "set_hi_si"
553 [(set (match_operand:SI 0 "register_operand" "=r")
554 (high:SI (match_operand 1 "symbolic_operand" "")))]
555 ""
556 "seth %0,%#shigh(%1)"
557 [(set_attr "type" "int4")
558 (set_attr "length" "4")])
560 (define_insn "lo_sum_si"
561 [(set (match_operand:SI 0 "register_operand" "=r")
562 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
563 (match_operand:SI 2 "immediate_operand" "in")))]
564 ""
565 "add3 %0,%1,%#%B2"
566 [(set_attr "type" "int4")
567 (set_attr "length" "4")])
569 (define_expand "movdi"
570 [(set (match_operand:DI 0 "general_operand" "")
571 (match_operand:DI 1 "general_operand" ""))]
572 ""
573 "
574 {
575 /* Fixup PIC cases. */
576 if (flag_pic)
577 {
578 if (symbolic_operand (operands[1], DImode))
579 {
580 if (reload_in_progress || reload_completed)
581 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
582 else
583 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
584 }
585 }
587 /* Everything except mem = const or mem = mem can be done easily. */
589 if (GET_CODE (operands[0]) == MEM)
590 operands[1] = force_reg (DImode, operands[1]);
591 }")
593 (define_insn "*movdi_insn"
594 [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
595 (match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]
596 "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
597 "#"
598 [(set_attr "type" "multi,multi,multi,load8,store8")
599 (set_attr "length" "4,4,16,6,6")])
601 (define_split
602 [(set (match_operand:DI 0 "move_dest_operand" "")
603 (match_operand:DI 1 "move_double_src_operand" ""))]
604 "reload_completed"
605 [(match_dup 2)]
606 "operands[2] = gen_split_move_double (operands);")
607 \f
608 ;; Floating point move insns.
610 (define_expand "movsf"
611 [(set (match_operand:SF 0 "general_operand" "")
612 (match_operand:SF 1 "general_operand" ""))]
613 ""
614 "
615 {
616 /* Fixup PIC cases. */
617 if (flag_pic)
618 {
619 if (symbolic_operand (operands[1], SFmode))
620 {
621 if (reload_in_progress || reload_completed)
622 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
623 else
624 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
625 }
626 }
628 /* Everything except mem = const or mem = mem can be done easily. */
630 if (GET_CODE (operands[0]) == MEM)
631 operands[1] = force_reg (SFmode, operands[1]);
632 }")
634 (define_insn "*movsf_insn"
635 [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
636 (match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
637 "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
638 "@
639 mv %0,%1
640 #
641 ld %0,%1
642 ld %0,%1
643 ld %0,%1
644 st %1,%0
645 st %1,%0
646 st %1,%0"
647 ;; ??? Length of alternative 1 is either 2, 4 or 8.
648 [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
649 (set_attr "length" "2,8,2,2,4,2,2,4")])
651 (define_split
652 [(set (match_operand:SF 0 "register_operand" "")
653 (match_operand:SF 1 "const_double_operand" ""))]
654 "reload_completed"
655 [(set (match_dup 2) (match_dup 3))]
656 "
657 {
658 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
659 operands[3] = operand_subword (operands[1], 0, 0, SFmode);
660 }")
662 (define_expand "movdf"
663 [(set (match_operand:DF 0 "general_operand" "")
664 (match_operand:DF 1 "general_operand" ""))]
665 ""
666 "
667 {
668 /* Fixup PIC cases. */
669 if (flag_pic)
670 {
671 if (symbolic_operand (operands[1], DFmode))
672 {
673 if (reload_in_progress || reload_completed)
674 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
675 else
676 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
677 }
678 }
680 /* Everything except mem = const or mem = mem can be done easily. */
682 if (GET_CODE (operands[0]) == MEM)
683 operands[1] = force_reg (DFmode, operands[1]);
684 }")
686 (define_insn "*movdf_insn"
687 [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
688 (match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]
689 "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
690 "#"
691 [(set_attr "type" "multi,multi,load8,store8")
692 (set_attr "length" "4,16,6,6")])
694 (define_split
695 [(set (match_operand:DF 0 "move_dest_operand" "")
696 (match_operand:DF 1 "move_double_src_operand" ""))]
697 "reload_completed"
698 [(match_dup 2)]
699 "operands[2] = gen_split_move_double (operands);")
700 \f
701 ;; Zero extension instructions.
703 (define_insn "zero_extendqihi2"
704 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
705 (zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
706 ""
707 "@
708 and3 %0,%1,%#255
709 ldub %0,%1
710 ldub %0,%1"
711 [(set_attr "type" "int4,load2,load4")
712 (set_attr "length" "4,2,4")])
714 (define_insn "zero_extendqisi2"
715 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
716 (zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
717 ""
718 "@
719 and3 %0,%1,%#255
720 ldub %0,%1
721 ldub %0,%1"
722 [(set_attr "type" "int4,load2,load4")
723 (set_attr "length" "4,2,4")])
725 (define_insn "zero_extendhisi2"
726 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
727 (zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
728 ""
729 "@
730 and3 %0,%1,%#65535
731 lduh %0,%1
732 lduh %0,%1"
733 [(set_attr "type" "int4,load2,load4")
734 (set_attr "length" "4,2,4")])
735 \f
736 ;; Signed conversions from a smaller integer to a larger integer
737 (define_insn "extendqihi2"
738 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
739 (sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
740 ""
741 "@
742 #
743 ldb %0,%1
744 ldb %0,%1"
745 [(set_attr "type" "multi,load2,load4")
746 (set_attr "length" "2,2,4")])
748 (define_split
749 [(set (match_operand:HI 0 "register_operand" "")
750 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
751 "reload_completed"
752 [(match_dup 2)
753 (match_dup 3)]
754 "
755 {
756 rtx op0 = gen_lowpart (SImode, operands[0]);
757 rtx shift = GEN_INT (24);
759 operands[2] = gen_ashlsi3 (op0, op0, shift);
760 operands[3] = gen_ashrsi3 (op0, op0, shift);
761 }")
763 (define_insn "extendqisi2"
764 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
765 (sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
766 ""
767 "@
768 #
769 ldb %0,%1
770 ldb %0,%1"
771 [(set_attr "type" "multi,load2,load4")
772 (set_attr "length" "4,2,4")])
774 (define_split
775 [(set (match_operand:SI 0 "register_operand" "")
776 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
777 "reload_completed"
778 [(match_dup 2)
779 (match_dup 3)]
780 "
781 {
782 rtx shift = GEN_INT (24);
784 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
785 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
786 }")
788 (define_insn "extendhisi2"
789 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
790 (sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
791 ""
792 "@
793 #
794 ldh %0,%1
795 ldh %0,%1"
796 [(set_attr "type" "multi,load2,load4")
797 (set_attr "length" "4,2,4")])
799 (define_split
800 [(set (match_operand:SI 0 "register_operand" "")
801 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
802 "reload_completed"
803 [(match_dup 2)
804 (match_dup 3)]
805 "
806 {
807 rtx shift = GEN_INT (16);
809 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
810 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
811 }")
812 \f
813 ;; Arithmetic instructions.
815 ; ??? Adding an alternative to split add3 of small constants into two
816 ; insns yields better instruction packing but slower code. Adds of small
817 ; values is done a lot.
819 (define_insn "addsi3"
820 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
821 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
822 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]
823 ""
824 "@
825 add %0,%2
826 addi %0,%#%2
827 add3 %0,%1,%#%2"
828 [(set_attr "type" "int2,int2,int4")
829 (set_attr "length" "2,2,4")])
831 ;(define_split
832 ; [(set (match_operand:SI 0 "register_operand" "")
833 ; (plus:SI (match_operand:SI 1 "register_operand" "")
834 ; (match_operand:SI 2 "int8_operand" "")))]
835 ; "reload_completed
836 ; && REGNO (operands[0]) != REGNO (operands[1])
837 ; && INT8_P (INTVAL (operands[2]))
838 ; && INTVAL (operands[2]) != 0"
839 ; [(set (match_dup 0) (match_dup 1))
840 ; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
841 ; "")
843 (define_insn "adddi3"
844 [(set (match_operand:DI 0 "register_operand" "=r")
845 (plus:DI (match_operand:DI 1 "register_operand" "%0")
846 (match_operand:DI 2 "register_operand" "r")))
847 (clobber (reg:CC 17))]
848 ""
849 "#"
850 [(set_attr "type" "multi")
851 (set_attr "length" "6")])
853 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
854 (define_split
855 [(set (match_operand:DI 0 "register_operand" "")
856 (plus:DI (match_operand:DI 1 "register_operand" "")
857 (match_operand:DI 2 "register_operand" "")))
858 (clobber (reg:CC 17))]
859 "reload_completed"
860 [(parallel [(set (reg:CC 17)
861 (const_int 0))
862 (use (match_dup 4))])
863 (parallel [(set (match_dup 4)
864 (plus:SI (match_dup 4)
865 (plus:SI (match_dup 5)
866 (ne:SI (reg:CC 17) (const_int 0)))))
867 (set (reg:CC 17)
868 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
869 (parallel [(set (match_dup 6)
870 (plus:SI (match_dup 6)
871 (plus:SI (match_dup 7)
872 (ne:SI (reg:CC 17) (const_int 0)))))
873 (set (reg:CC 17)
874 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
875 "
876 {
877 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
878 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
879 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
880 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
881 }")
883 (define_insn "*clear_c"
884 [(set (reg:CC 17)
885 (const_int 0))
886 (use (match_operand:SI 0 "register_operand" "r"))]
887 ""
888 "cmp %0,%0"
889 [(set_attr "type" "int2")
890 (set_attr "length" "2")])
892 (define_insn "*add_carry"
893 [(set (match_operand:SI 0 "register_operand" "=r")
894 (plus:SI (match_operand:SI 1 "register_operand" "%0")
895 (plus:SI (match_operand:SI 2 "register_operand" "r")
896 (ne:SI (reg:CC 17) (const_int 0)))))
897 (set (reg:CC 17)
898 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
899 ""
900 "addx %0,%2"
901 [(set_attr "type" "int2")
902 (set_attr "length" "2")])
904 (define_insn "subsi3"
905 [(set (match_operand:SI 0 "register_operand" "=r")
906 (minus:SI (match_operand:SI 1 "register_operand" "0")
907 (match_operand:SI 2 "register_operand" "r")))]
908 ""
909 "sub %0,%2"
910 [(set_attr "type" "int2")
911 (set_attr "length" "2")])
913 (define_insn "subdi3"
914 [(set (match_operand:DI 0 "register_operand" "=r")
915 (minus:DI (match_operand:DI 1 "register_operand" "0")
916 (match_operand:DI 2 "register_operand" "r")))
917 (clobber (reg:CC 17))]
918 ""
919 "#"
920 [(set_attr "type" "multi")
921 (set_attr "length" "6")])
923 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
924 (define_split
925 [(set (match_operand:DI 0 "register_operand" "")
926 (minus:DI (match_operand:DI 1 "register_operand" "")
927 (match_operand:DI 2 "register_operand" "")))
928 (clobber (reg:CC 17))]
929 "reload_completed"
930 [(parallel [(set (reg:CC 17)
931 (const_int 0))
932 (use (match_dup 4))])
933 (parallel [(set (match_dup 4)
934 (minus:SI (match_dup 4)
935 (minus:SI (match_dup 5)
936 (ne:SI (reg:CC 17) (const_int 0)))))
937 (set (reg:CC 17)
938 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
939 (parallel [(set (match_dup 6)
940 (minus:SI (match_dup 6)
941 (minus:SI (match_dup 7)
942 (ne:SI (reg:CC 17) (const_int 0)))))
943 (set (reg:CC 17)
944 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
945 "
946 {
947 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
948 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
949 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
950 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
951 }")
953 (define_insn "*sub_carry"
954 [(set (match_operand:SI 0 "register_operand" "=r")
955 (minus:SI (match_operand:SI 1 "register_operand" "%0")
956 (minus:SI (match_operand:SI 2 "register_operand" "r")
957 (ne:SI (reg:CC 17) (const_int 0)))))
958 (set (reg:CC 17)
959 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
960 ""
961 "subx %0,%2"
962 [(set_attr "type" "int2")
963 (set_attr "length" "2")])
964 \f
965 ; Multiply/Divide instructions.
967 (define_insn "mulhisi3"
968 [(set (match_operand:SI 0 "register_operand" "=r")
969 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
970 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
971 ""
972 "mullo %1,%2\;mvfacmi %0"
973 [(set_attr "type" "multi")
974 (set_attr "length" "4")])
976 (define_insn "mulsi3"
977 [(set (match_operand:SI 0 "register_operand" "=r")
978 (mult:SI (match_operand:SI 1 "register_operand" "%0")
979 (match_operand:SI 2 "register_operand" "r")))]
980 ""
981 "mul %0,%2"
982 [(set_attr "type" "mul2")
983 (set_attr "length" "2")])
985 (define_insn "divsi3"
986 [(set (match_operand:SI 0 "register_operand" "=r")
987 (div:SI (match_operand:SI 1 "register_operand" "0")
988 (match_operand:SI 2 "register_operand" "r")))]
989 ""
990 "div %0,%2"
991 [(set_attr "type" "div4")
992 (set_attr "length" "4")])
994 (define_insn "udivsi3"
995 [(set (match_operand:SI 0 "register_operand" "=r")
996 (udiv:SI (match_operand:SI 1 "register_operand" "0")
997 (match_operand:SI 2 "register_operand" "r")))]
998 ""
999 "divu %0,%2"
1000 [(set_attr "type" "div4")
1001 (set_attr "length" "4")])
1003 (define_insn "modsi3"
1004 [(set (match_operand:SI 0 "register_operand" "=r")
1005 (mod:SI (match_operand:SI 1 "register_operand" "0")
1006 (match_operand:SI 2 "register_operand" "r")))]
1007 ""
1008 "rem %0,%2"
1009 [(set_attr "type" "div4")
1010 (set_attr "length" "4")])
1012 (define_insn "umodsi3"
1013 [(set (match_operand:SI 0 "register_operand" "=r")
1014 (umod:SI (match_operand:SI 1 "register_operand" "0")
1015 (match_operand:SI 2 "register_operand" "r")))]
1016 ""
1017 "remu %0,%2"
1018 [(set_attr "type" "div4")
1019 (set_attr "length" "4")])
1020 \f
1021 ;; Boolean instructions.
1022 ;;
1023 ;; We don't define the DImode versions as expand_binop does a good enough job.
1024 ;; And if it doesn't it should be fixed.
1026 (define_insn "andsi3"
1027 [(set (match_operand:SI 0 "register_operand" "=r,r")
1028 (and:SI (match_operand:SI 1 "register_operand" "%0,r")
1029 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1030 ""
1031 "*
1032 {
1033 /* If we are worried about space, see if we can break this up into two
1034 short instructions, which might eliminate a NOP being inserted. */
1035 if (optimize_size
1036 && m32r_not_same_reg (operands[0], operands[1])
1037 && GET_CODE (operands[2]) == CONST_INT
1038 && INT8_P (INTVAL (operands[2])))
1039 return \"#\";
1041 else if (GET_CODE (operands[2]) == CONST_INT)
1042 return \"and3 %0,%1,%#%X2\";
1044 return \"and %0,%2\";
1045 }"
1046 [(set_attr "type" "int2,int4")
1047 (set_attr "length" "2,4")])
1049 (define_split
1050 [(set (match_operand:SI 0 "register_operand" "")
1051 (and:SI (match_operand:SI 1 "register_operand" "")
1052 (match_operand:SI 2 "int8_operand" "")))]
1053 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1054 [(set (match_dup 0) (match_dup 2))
1055 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
1056 "")
1058 (define_insn "iorsi3"
1059 [(set (match_operand:SI 0 "register_operand" "=r,r")
1060 (ior:SI (match_operand:SI 1 "register_operand" "%0,r")
1061 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1062 ""
1063 "*
1064 {
1065 /* If we are worried about space, see if we can break this up into two
1066 short instructions, which might eliminate a NOP being inserted. */
1067 if (optimize_size
1068 && m32r_not_same_reg (operands[0], operands[1])
1069 && GET_CODE (operands[2]) == CONST_INT
1070 && INT8_P (INTVAL (operands[2])))
1071 return \"#\";
1073 else if (GET_CODE (operands[2]) == CONST_INT)
1074 return \"or3 %0,%1,%#%X2\";
1076 return \"or %0,%2\";
1077 }"
1078 [(set_attr "type" "int2,int4")
1079 (set_attr "length" "2,4")])
1081 (define_split
1082 [(set (match_operand:SI 0 "register_operand" "")
1083 (ior:SI (match_operand:SI 1 "register_operand" "")
1084 (match_operand:SI 2 "int8_operand" "")))]
1085 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1086 [(set (match_dup 0) (match_dup 2))
1087 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
1088 "")
1090 (define_insn "xorsi3"
1091 [(set (match_operand:SI 0 "register_operand" "=r,r")
1092 (xor:SI (match_operand:SI 1 "register_operand" "%0,r")
1093 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1094 ""
1095 "*
1096 {
1097 /* If we are worried about space, see if we can break this up into two
1098 short instructions, which might eliminate a NOP being inserted. */
1099 if (optimize_size
1100 && m32r_not_same_reg (operands[0], operands[1])
1101 && GET_CODE (operands[2]) == CONST_INT
1102 && INT8_P (INTVAL (operands[2])))
1103 return \"#\";
1105 else if (GET_CODE (operands[2]) == CONST_INT)
1106 return \"xor3 %0,%1,%#%X2\";
1108 return \"xor %0,%2\";
1109 }"
1110 [(set_attr "type" "int2,int4")
1111 (set_attr "length" "2,4")])
1113 (define_split
1114 [(set (match_operand:SI 0 "register_operand" "")
1115 (xor:SI (match_operand:SI 1 "register_operand" "")
1116 (match_operand:SI 2 "int8_operand" "")))]
1117 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1118 [(set (match_dup 0) (match_dup 2))
1119 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
1120 "")
1122 (define_insn "negsi2"
1123 [(set (match_operand:SI 0 "register_operand" "=r")
1124 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1125 ""
1126 "neg %0,%1"
1127 [(set_attr "type" "int2")
1128 (set_attr "length" "2")])
1130 (define_insn "one_cmplsi2"
1131 [(set (match_operand:SI 0 "register_operand" "=r")
1132 (not:SI (match_operand:SI 1 "register_operand" "r")))]
1133 ""
1134 "not %0,%1"
1135 [(set_attr "type" "int2")
1136 (set_attr "length" "2")])
1137 \f
1138 ;; Shift instructions.
1140 (define_insn "ashlsi3"
1141 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1142 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1143 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1144 ""
1145 "@
1146 sll %0,%2
1147 slli %0,%#%2
1148 sll3 %0,%1,%#%2"
1149 [(set_attr "type" "shift2,shift2,shift4")
1150 (set_attr "length" "2,2,4")])
1152 (define_insn "ashrsi3"
1153 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1154 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1155 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1156 ""
1157 "@
1158 sra %0,%2
1159 srai %0,%#%2
1160 sra3 %0,%1,%#%2"
1161 [(set_attr "type" "shift2,shift2,shift4")
1162 (set_attr "length" "2,2,4")])
1164 (define_insn "lshrsi3"
1165 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1166 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1167 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1168 ""
1169 "@
1170 srl %0,%2
1171 srli %0,%#%2
1172 srl3 %0,%1,%#%2"
1173 [(set_attr "type" "shift2,shift2,shift4")
1174 (set_attr "length" "2,2,4")])
1175 \f
1176 ;; Compare instructions.
1177 ;; This controls RTL generation and register allocation.
1179 ;; We generate RTL for comparisons and branches by having the cmpxx
1180 ;; patterns store away the operands. Then the bcc patterns
1181 ;; emit RTL for both the compare and the branch.
1182 ;;
1183 ;; On the m32r it is more efficient to use the bxxz instructions and
1184 ;; thus merge the compare and branch into one instruction, so they are
1185 ;; preferred.
1187 (define_expand "cmpsi"
1188 [(set (reg:CC 17)
1189 (compare:CC (match_operand:SI 0 "register_operand" "")
1190 (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
1191 ""
1192 "
1193 {
1194 m32r_compare_op0 = operands[0];
1195 m32r_compare_op1 = operands[1];
1196 DONE;
1197 }")
1199 (define_insn "cmp_eqsi_zero_insn"
1200 [(set (reg:CC 17)
1201 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1202 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
1203 "TARGET_M32RX || TARGET_M32R2"
1204 "@
1205 cmpeq %0, %1
1206 cmpz %0"
1207 [(set_attr "type" "int4")
1208 (set_attr "length" "4")])
1210 ;; The cmp_xxx_insn patterns set the condition bit to the result of the
1211 ;; comparison. There isn't a "compare equal" instruction so cmp_eqsi_insn
1212 ;; is quite inefficient. However, it is rarely used.
1214 (define_insn "cmp_eqsi_insn"
1215 [(set (reg:CC 17)
1216 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1217 (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
1218 (clobber (match_scratch:SI 2 "=&r,&r"))]
1219 ""
1220 "*
1221 {
1222 if (which_alternative == 0)
1223 {
1224 return \"mv %2,%0\;sub %2,%1\;cmpui %2,#1\";
1225 }
1226 else
1227 {
1228 if (INTVAL (operands [1]) == 0)
1229 return \"cmpui %0, #1\";
1230 else if (REGNO (operands [2]) == REGNO (operands [0]))
1231 return \"addi %0,%#%N1\;cmpui %2,#1\";
1232 else
1233 return \"add3 %2,%0,%#%N1\;cmpui %2,#1\";
1234 }
1235 }"
1236 [(set_attr "type" "multi,multi")
1237 (set_attr "length" "8,8")])
1239 (define_insn "cmp_ltsi_insn"
1240 [(set (reg:CC 17)
1241 (lt:CC (match_operand:SI 0 "register_operand" "r,r")
1242 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1243 ""
1244 "@
1245 cmp %0,%1
1246 cmpi %0,%#%1"
1247 [(set_attr "type" "int2,int4")
1248 (set_attr "length" "2,4")])
1250 (define_insn "cmp_ltusi_insn"
1251 [(set (reg:CC 17)
1252 (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
1253 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1254 ""
1255 "@
1256 cmpu %0,%1
1257 cmpui %0,%#%1"
1258 [(set_attr "type" "int2,int4")
1259 (set_attr "length" "2,4")])
1260 \f
1261 ;; These control RTL generation for conditional jump insns.
1263 (define_expand "beq"
1264 [(set (pc)
1265 (if_then_else (match_dup 1)
1266 (label_ref (match_operand 0 "" ""))
1267 (pc)))]
1268 ""
1269 "
1270 {
1271 operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE);
1272 }")
1274 (define_expand "bne"
1275 [(set (pc)
1276 (if_then_else (match_dup 1)
1277 (label_ref (match_operand 0 "" ""))
1278 (pc)))]
1279 ""
1280 "
1281 {
1282 operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE);
1283 }")
1285 (define_expand "bgt"
1286 [(set (pc)
1287 (if_then_else (match_dup 1)
1288 (label_ref (match_operand 0 "" ""))
1289 (pc)))]
1290 ""
1291 "
1292 {
1293 operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE);
1294 }")
1296 (define_expand "ble"
1297 [(set (pc)
1298 (if_then_else (match_dup 1)
1299 (label_ref (match_operand 0 "" ""))
1300 (pc)))]
1301 ""
1302 "
1303 {
1304 operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE);
1305 }")
1307 (define_expand "bge"
1308 [(set (pc)
1309 (if_then_else (match_dup 1)
1310 (label_ref (match_operand 0 "" ""))
1311 (pc)))]
1312 ""
1313 "
1314 {
1315 operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE);
1316 }")
1318 (define_expand "blt"
1319 [(set (pc)
1320 (if_then_else (match_dup 1)
1321 (label_ref (match_operand 0 "" ""))
1322 (pc)))]
1323 ""
1324 "
1325 {
1326 operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE);
1327 }")
1329 (define_expand "bgtu"
1330 [(set (pc)
1331 (if_then_else (match_dup 1)
1332 (label_ref (match_operand 0 "" ""))
1333 (pc)))]
1334 ""
1335 "
1336 {
1337 operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
1338 }")
1340 (define_expand "bleu"
1341 [(set (pc)
1342 (if_then_else (match_dup 1)
1343 (label_ref (match_operand 0 "" ""))
1344 (pc)))]
1345 ""
1346 "
1347 {
1348 operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
1349 }")
1351 (define_expand "bgeu"
1352 [(set (pc)
1353 (if_then_else (match_dup 1)
1354 (label_ref (match_operand 0 "" ""))
1355 (pc)))]
1356 ""
1357 "
1358 {
1359 operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
1360 }")
1362 (define_expand "bltu"
1363 [(set (pc)
1364 (if_then_else (match_dup 1)
1365 (label_ref (match_operand 0 "" ""))
1366 (pc)))]
1367 ""
1368 "
1369 {
1370 operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
1371 }")
1373 ;; Now match both normal and inverted jump.
1375 (define_insn "*branch_insn"
1376 [(set (pc)
1377 (if_then_else (match_operator 1 "eqne_comparison_operator"
1378 [(reg 17) (const_int 0)])
1379 (label_ref (match_operand 0 "" ""))
1380 (pc)))]
1381 ""
1382 "*
1383 {
1384 static char instruction[40];
1385 sprintf (instruction, \"%s%s %%l0\",
1386 (GET_CODE (operands[1]) == NE) ? \"bc\" : \"bnc\",
1387 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1388 return instruction;
1389 }"
1390 [(set_attr "type" "branch")
1391 ; cf PR gcc/28508
1392 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1393 ; lengths and insn alignments that are complex to track.
1394 ; It's not important that we be hyper-precise here. It may be more
1395 ; important blah blah blah when the chip supports parallel execution
1396 ; blah blah blah but until then blah blah blah this is simple and
1397 ; suffices.
1398 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1399 (const_int 300))
1400 (const_int 600))
1401 (const_int 2)
1402 (const_int 4)))])
1404 (define_insn "*rev_branch_insn"
1405 [(set (pc)
1406 (if_then_else (match_operator 1 "eqne_comparison_operator"
1407 [(reg 17) (const_int 0)])
1408 (pc)
1409 (label_ref (match_operand 0 "" ""))))]
1410 ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
1411 ""
1412 "*
1413 {
1414 static char instruction[40];
1415 sprintf (instruction, \"%s%s %%l0\",
1416 (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
1417 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1418 return instruction;
1419 }"
1420 [(set_attr "type" "branch")
1421 ; cf PR gcc/28508
1422 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1423 ; lengths and insn alignments that are complex to track.
1424 ; It's not important that we be hyper-precise here. It may be more
1425 ; important blah blah blah when the chip supports parallel execution
1426 ; blah blah blah but until then blah blah blah this is simple and
1427 ; suffices.
1428 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1429 (const_int 300))
1430 (const_int 600))
1431 (const_int 2)
1432 (const_int 4)))])
1434 ; reg/reg compare and branch insns
1436 (define_insn "*reg_branch_insn"
1437 [(set (pc)
1438 (if_then_else (match_operator 1 "eqne_comparison_operator"
1439 [(match_operand:SI 2 "register_operand" "r")
1440 (match_operand:SI 3 "register_operand" "r")])
1441 (label_ref (match_operand 0 "" ""))
1442 (pc)))]
1443 ""
1444 "*
1445 {
1446 /* Is branch target reachable with beq/bne? */
1447 if (get_attr_length (insn) == 4)
1448 {
1449 if (GET_CODE (operands[1]) == EQ)
1450 return \"beq %2,%3,%l0\";
1451 else
1452 return \"bne %2,%3,%l0\";
1453 }
1454 else
1455 {
1456 if (GET_CODE (operands[1]) == EQ)
1457 return \"bne %2,%3,1f\;bra %l0\;1:\";
1458 else
1459 return \"beq %2,%3,1f\;bra %l0\;1:\";
1460 }
1461 }"
1462 [(set_attr "type" "branch")
1463 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1464 ; which is complex to track and inaccurate length specs.
1465 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1466 (const_int 25000))
1467 (const_int 50000))
1468 (const_int 4)
1469 (const_int 8)))])
1471 (define_insn "*rev_reg_branch_insn"
1472 [(set (pc)
1473 (if_then_else (match_operator 1 "eqne_comparison_operator"
1474 [(match_operand:SI 2 "register_operand" "r")
1475 (match_operand:SI 3 "register_operand" "r")])
1476 (pc)
1477 (label_ref (match_operand 0 "" ""))))]
1478 ""
1479 "*
1480 {
1481 /* Is branch target reachable with beq/bne? */
1482 if (get_attr_length (insn) == 4)
1483 {
1484 if (GET_CODE (operands[1]) == NE)
1485 return \"beq %2,%3,%l0\";
1486 else
1487 return \"bne %2,%3,%l0\";
1488 }
1489 else
1490 {
1491 if (GET_CODE (operands[1]) == NE)
1492 return \"bne %2,%3,1f\;bra %l0\;1:\";
1493 else
1494 return \"beq %2,%3,1f\;bra %l0\;1:\";
1495 }
1496 }"
1497 [(set_attr "type" "branch")
1498 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1499 ; which is complex to track and inaccurate length specs.
1500 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1501 (const_int 25000))
1502 (const_int 50000))
1503 (const_int 4)
1504 (const_int 8)))])
1506 ; reg/zero compare and branch insns
1508 (define_insn "*zero_branch_insn"
1509 [(set (pc)
1510 (if_then_else (match_operator 1 "signed_comparison_operator"
1511 [(match_operand:SI 2 "register_operand" "r")
1512 (const_int 0)])
1513 (label_ref (match_operand 0 "" ""))
1514 (pc)))]
1515 ""
1516 "*
1517 {
1518 const char *br,*invbr;
1519 char asmtext[40];
1521 switch (GET_CODE (operands[1]))
1522 {
1523 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1524 case NE : br = \"ne\"; invbr = \"eq\"; break;
1525 case LE : br = \"le\"; invbr = \"gt\"; break;
1526 case GT : br = \"gt\"; invbr = \"le\"; break;
1527 case LT : br = \"lt\"; invbr = \"ge\"; break;
1528 case GE : br = \"ge\"; invbr = \"lt\"; break;
1530 default: gcc_unreachable ();
1531 }
1533 /* Is branch target reachable with bxxz? */
1534 if (get_attr_length (insn) == 4)
1535 {
1536 sprintf (asmtext, \"b%sz %%2,%%l0\", br);
1537 output_asm_insn (asmtext, operands);
1538 }
1539 else
1540 {
1541 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
1542 output_asm_insn (asmtext, operands);
1543 }
1544 return \"\";
1545 }"
1546 [(set_attr "type" "branch")
1547 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1548 ; which is complex to track and inaccurate length specs.
1549 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1550 (const_int 25000))
1551 (const_int 50000))
1552 (const_int 4)
1553 (const_int 8)))])
1555 (define_insn "*rev_zero_branch_insn"
1556 [(set (pc)
1557 (if_then_else (match_operator 1 "eqne_comparison_operator"
1558 [(match_operand:SI 2 "register_operand" "r")
1559 (const_int 0)])
1560 (pc)
1561 (label_ref (match_operand 0 "" ""))))]
1562 ""
1563 "*
1564 {
1565 const char *br,*invbr;
1566 char asmtext[40];
1568 switch (GET_CODE (operands[1]))
1569 {
1570 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1571 case NE : br = \"ne\"; invbr = \"eq\"; break;
1572 case LE : br = \"le\"; invbr = \"gt\"; break;
1573 case GT : br = \"gt\"; invbr = \"le\"; break;
1574 case LT : br = \"lt\"; invbr = \"ge\"; break;
1575 case GE : br = \"ge\"; invbr = \"lt\"; break;
1577 default: gcc_unreachable ();
1578 }
1580 /* Is branch target reachable with bxxz? */
1581 if (get_attr_length (insn) == 4)
1582 {
1583 sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
1584 output_asm_insn (asmtext, operands);
1585 }
1586 else
1587 {
1588 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
1589 output_asm_insn (asmtext, operands);
1590 }
1591 return \"\";
1592 }"
1593 [(set_attr "type" "branch")
1594 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1595 ; which is complex to track and inaccurate length specs.
1596 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1597 (const_int 25000))
1598 (const_int 50000))
1599 (const_int 4)
1600 (const_int 8)))])
1601 \f
1602 ;; S<cc> operations to set a register to 1/0 based on a comparison
1604 (define_expand "seq"
1605 [(match_operand:SI 0 "register_operand" "")]
1606 ""
1607 "
1608 {
1609 rtx op0 = operands[0];
1610 rtx op1 = m32r_compare_op0;
1611 rtx op2 = m32r_compare_op1;
1612 enum machine_mode mode = GET_MODE (op0);
1614 if (mode != SImode)
1615 FAIL;
1617 if (! register_operand (op1, mode))
1618 op1 = force_reg (mode, op1);
1620 if (TARGET_M32RX || TARGET_M32R2)
1621 {
1622 if (! reg_or_zero_operand (op2, mode))
1623 op2 = force_reg (mode, op2);
1625 emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
1626 DONE;
1627 }
1628 if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
1629 {
1630 emit_insn (gen_seq_zero_insn (op0, op1));
1631 DONE;
1632 }
1634 if (! reg_or_eq_int16_operand (op2, mode))
1635 op2 = force_reg (mode, op2);
1637 emit_insn (gen_seq_insn (op0, op1, op2));
1638 DONE;
1639 }")
1641 (define_insn "seq_insn_m32rx"
1642 [(set (match_operand:SI 0 "register_operand" "=r")
1643 (eq:SI (match_operand:SI 1 "register_operand" "%r")
1644 (match_operand:SI 2 "reg_or_zero_operand" "rP")))
1645 (clobber (reg:CC 17))]
1646 "TARGET_M32RX || TARGET_M32R2"
1647 "#"
1648 [(set_attr "type" "multi")
1649 (set_attr "length" "6")])
1651 (define_split
1652 [(set (match_operand:SI 0 "register_operand" "")
1653 (eq:SI (match_operand:SI 1 "register_operand" "")
1654 (match_operand:SI 2 "reg_or_zero_operand" "")))
1655 (clobber (reg:CC 17))]
1656 "TARGET_M32RX || TARGET_M32R2"
1657 [(set (reg:CC 17)
1658 (eq:CC (match_dup 1)
1659 (match_dup 2)))
1660 (set (match_dup 0)
1661 (ne:SI (reg:CC 17) (const_int 0)))]
1662 "")
1664 (define_insn "seq_zero_insn"
1665 [(set (match_operand:SI 0 "register_operand" "=r")
1666 (eq:SI (match_operand:SI 1 "register_operand" "r")
1667 (const_int 0)))
1668 (clobber (reg:CC 17))]
1669 "TARGET_M32R"
1670 "#"
1671 [(set_attr "type" "multi")
1672 (set_attr "length" "6")])
1674 (define_split
1675 [(set (match_operand:SI 0 "register_operand" "")
1676 (eq:SI (match_operand:SI 1 "register_operand" "")
1677 (const_int 0)))
1678 (clobber (reg:CC 17))]
1679 "TARGET_M32R"
1680 [(match_dup 3)]
1681 "
1682 {
1683 rtx op0 = operands[0];
1684 rtx op1 = operands[1];
1686 start_sequence ();
1687 emit_insn (gen_cmp_ltusi_insn (op1, const1_rtx));
1688 emit_insn (gen_movcc_insn (op0));
1689 operands[3] = get_insns ();
1690 end_sequence ();
1691 }")
1693 (define_insn "seq_insn"
1694 [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
1695 (eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
1696 (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
1697 (clobber (reg:CC 17))
1698 (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
1699 "TARGET_M32R"
1700 "#"
1701 [(set_attr "type" "multi")
1702 (set_attr "length" "8,8,10,10")])
1704 (define_split
1705 [(set (match_operand:SI 0 "register_operand" "")
1706 (eq:SI (match_operand:SI 1 "register_operand" "")
1707 (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
1708 (clobber (reg:CC 17))
1709 (clobber (match_scratch:SI 3 ""))]
1710 "TARGET_M32R && reload_completed"
1711 [(match_dup 4)]
1712 "
1713 {
1714 rtx op0 = operands[0];
1715 rtx op1 = operands[1];
1716 rtx op2 = operands[2];
1717 rtx op3 = operands[3];
1718 HOST_WIDE_INT value;
1720 if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
1721 && REGNO (op2) == REGNO (op3))
1722 {
1723 op1 = operands[2];
1724 op2 = operands[1];
1725 }
1727 start_sequence ();
1728 if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
1729 && REGNO (op1) != REGNO (op3))
1730 {
1731 emit_move_insn (op3, op1);
1732 op1 = op3;
1733 }
1735 if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
1736 && CMP_INT16_P (value))
1737 emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
1738 else
1739 emit_insn (gen_xorsi3 (op3, op1, op2));
1741 emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
1742 emit_insn (gen_movcc_insn (op0));
1743 operands[4] = get_insns ();
1744 end_sequence ();
1745 }")
1747 (define_expand "sne"
1748 [(match_operand:SI 0 "register_operand" "")]
1749 ""
1750 "
1751 {
1752 rtx op0 = operands[0];
1753 rtx op1 = m32r_compare_op0;
1754 rtx op2 = m32r_compare_op1;
1755 enum machine_mode mode = GET_MODE (op0);
1757 if (mode != SImode)
1758 FAIL;
1760 if (GET_CODE (op2) != CONST_INT
1761 || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
1762 {
1763 rtx reg;
1765 if (reload_completed || reload_in_progress)
1766 FAIL;
1768 reg = gen_reg_rtx (SImode);
1769 emit_insn (gen_xorsi3 (reg, op1, op2));
1770 op1 = reg;
1772 if (! register_operand (op1, mode))
1773 op1 = force_reg (mode, op1);
1775 emit_insn (gen_sne_zero_insn (op0, op1));
1776 DONE;
1777 }
1778 else
1779 FAIL;
1780 }")
1782 (define_insn "sne_zero_insn"
1783 [(set (match_operand:SI 0 "register_operand" "=r")
1784 (ne:SI (match_operand:SI 1 "register_operand" "r")
1785 (const_int 0)))
1786 (clobber (reg:CC 17))
1787 (clobber (match_scratch:SI 2 "=&r"))]
1788 ""
1789 "#"
1790 [(set_attr "type" "multi")
1791 (set_attr "length" "6")])
1793 (define_split
1794 [(set (match_operand:SI 0 "register_operand" "")
1795 (ne:SI (match_operand:SI 1 "register_operand" "")
1796 (const_int 0)))
1797 (clobber (reg:CC 17))
1798 (clobber (match_scratch:SI 2 ""))]
1799 "reload_completed"
1800 [(set (match_dup 2)
1801 (const_int 0))
1802 (set (reg:CC 17)
1803 (ltu:CC (match_dup 2)
1804 (match_dup 1)))
1805 (set (match_dup 0)
1806 (ne:SI (reg:CC 17) (const_int 0)))]
1807 "")
1809 (define_expand "slt"
1810 [(match_operand:SI 0 "register_operand" "")]
1811 ""
1812 "
1813 {
1814 rtx op0 = operands[0];
1815 rtx op1 = m32r_compare_op0;
1816 rtx op2 = m32r_compare_op1;
1817 enum machine_mode mode = GET_MODE (op0);
1819 if (mode != SImode)
1820 FAIL;
1822 if (! register_operand (op1, mode))
1823 op1 = force_reg (mode, op1);
1825 if (! reg_or_int16_operand (op2, mode))
1826 op2 = force_reg (mode, op2);
1828 emit_insn (gen_slt_insn (op0, op1, op2));
1829 DONE;
1830 }")
1832 (define_insn "slt_insn"
1833 [(set (match_operand:SI 0 "register_operand" "=r,r")
1834 (lt:SI (match_operand:SI 1 "register_operand" "r,r")
1835 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1836 (clobber (reg:CC 17))]
1837 ""
1838 "#"
1839 [(set_attr "type" "multi")
1840 (set_attr "length" "4,6")])
1842 (define_split
1843 [(set (match_operand:SI 0 "register_operand" "")
1844 (lt:SI (match_operand:SI 1 "register_operand" "")
1845 (match_operand:SI 2 "reg_or_int16_operand" "")))
1846 (clobber (reg:CC 17))]
1847 ""
1848 [(set (reg:CC 17)
1849 (lt:CC (match_dup 1)
1850 (match_dup 2)))
1851 (set (match_dup 0)
1852 (ne:SI (reg:CC 17) (const_int 0)))]
1853 "")
1855 (define_expand "sle"
1856 [(match_operand:SI 0 "register_operand" "")]
1857 ""
1858 "
1859 {
1860 rtx op0 = operands[0];
1861 rtx op1 = m32r_compare_op0;
1862 rtx op2 = m32r_compare_op1;
1863 enum machine_mode mode = GET_MODE (op0);
1865 if (mode != SImode)
1866 FAIL;
1868 if (! register_operand (op1, mode))
1869 op1 = force_reg (mode, op1);
1871 if (GET_CODE (op2) == CONST_INT)
1872 {
1873 HOST_WIDE_INT value = INTVAL (op2);
1874 if (value >= 2147483647)
1875 {
1876 emit_move_insn (op0, const1_rtx);
1877 DONE;
1878 }
1880 op2 = GEN_INT (value+1);
1881 if (value < -32768 || value >= 32767)
1882 op2 = force_reg (mode, op2);
1884 emit_insn (gen_slt_insn (op0, op1, op2));
1885 DONE;
1886 }
1888 if (! register_operand (op2, mode))
1889 op2 = force_reg (mode, op2);
1891 emit_insn (gen_sle_insn (op0, op1, op2));
1892 DONE;
1893 }")
1895 (define_insn "sle_insn"
1896 [(set (match_operand:SI 0 "register_operand" "=r")
1897 (le:SI (match_operand:SI 1 "register_operand" "r")
1898 (match_operand:SI 2 "register_operand" "r")))
1899 (clobber (reg:CC 17))]
1900 ""
1901 "#"
1902 [(set_attr "type" "multi")
1903 (set_attr "length" "8")])
1905 (define_split
1906 [(set (match_operand:SI 0 "register_operand" "")
1907 (le:SI (match_operand:SI 1 "register_operand" "")
1908 (match_operand:SI 2 "register_operand" "")))
1909 (clobber (reg:CC 17))]
1910 "!optimize_size"
1911 [(set (reg:CC 17)
1912 (lt:CC (match_dup 2)
1913 (match_dup 1)))
1914 (set (match_dup 0)
1915 (ne:SI (reg:CC 17) (const_int 0)))
1916 (set (match_dup 0)
1917 (xor:SI (match_dup 0)
1918 (const_int 1)))]
1919 "")
1921 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1922 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1923 (define_split
1924 [(set (match_operand:SI 0 "register_operand" "")
1925 (le:SI (match_operand:SI 1 "register_operand" "")
1926 (match_operand:SI 2 "register_operand" "")))
1927 (clobber (reg:CC 17))]
1928 "optimize_size"
1929 [(set (reg:CC 17)
1930 (lt:CC (match_dup 2)
1931 (match_dup 1)))
1932 (set (match_dup 0)
1933 (ne:SI (reg:CC 17) (const_int 0)))
1934 (set (match_dup 0)
1935 (plus:SI (match_dup 0)
1936 (const_int -1)))
1937 (set (match_dup 0)
1938 (neg:SI (match_dup 0)))]
1939 "")
1941 (define_expand "sgt"
1942 [(match_operand:SI 0 "register_operand" "")]
1943 ""
1944 "
1945 {
1946 rtx op0 = operands[0];
1947 rtx op1 = m32r_compare_op0;
1948 rtx op2 = m32r_compare_op1;
1949 enum machine_mode mode = GET_MODE (op0);
1951 if (mode != SImode)
1952 FAIL;
1954 if (! register_operand (op1, mode))
1955 op1 = force_reg (mode, op1);
1957 if (! register_operand (op2, mode))
1958 op2 = force_reg (mode, op2);
1960 emit_insn (gen_slt_insn (op0, op2, op1));
1961 DONE;
1962 }")
1964 (define_expand "sge"
1965 [(match_operand:SI 0 "register_operand" "")]
1966 ""
1967 "
1968 {
1969 rtx op0 = operands[0];
1970 rtx op1 = m32r_compare_op0;
1971 rtx op2 = m32r_compare_op1;
1972 enum machine_mode mode = GET_MODE (op0);
1974 if (mode != SImode)
1975 FAIL;
1977 if (! register_operand (op1, mode))
1978 op1 = force_reg (mode, op1);
1980 if (! reg_or_int16_operand (op2, mode))
1981 op2 = force_reg (mode, op2);
1983 emit_insn (gen_sge_insn (op0, op1, op2));
1984 DONE;
1985 }")
1987 (define_insn "sge_insn"
1988 [(set (match_operand:SI 0 "register_operand" "=r,r")
1989 (ge:SI (match_operand:SI 1 "register_operand" "r,r")
1990 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1991 (clobber (reg:CC 17))]
1992 ""
1993 "#"
1994 [(set_attr "type" "multi")
1995 (set_attr "length" "8,10")])
1997 (define_split
1998 [(set (match_operand:SI 0 "register_operand" "")
1999 (ge:SI (match_operand:SI 1 "register_operand" "")
2000 (match_operand:SI 2 "reg_or_int16_operand" "")))
2001 (clobber (reg:CC 17))]
2002 "!optimize_size"
2003 [(set (reg:CC 17)
2004 (lt:CC (match_dup 1)
2005 (match_dup 2)))
2006 (set (match_dup 0)
2007 (ne:SI (reg:CC 17) (const_int 0)))
2008 (set (match_dup 0)
2009 (xor:SI (match_dup 0)
2010 (const_int 1)))]
2011 "")
2013 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
2014 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
2015 (define_split
2016 [(set (match_operand:SI 0 "register_operand" "")
2017 (ge:SI (match_operand:SI 1 "register_operand" "")
2018 (match_operand:SI 2 "reg_or_int16_operand" "")))
2019 (clobber (reg:CC 17))]
2020 "optimize_size"
2021 [(set (reg:CC 17)
2022 (lt:CC (match_dup 1)
2023 (match_dup 2)))
2024 (set (match_dup 0)
2025 (ne:SI (reg:CC 17) (const_int 0)))
2026 (set (match_dup 0)
2027 (plus:SI (match_dup 0)
2028 (const_int -1)))
2029 (set (match_dup 0)
2030 (neg:SI (match_dup 0)))]
2031 "")
2033 (define_expand "sltu"
2034 [(match_operand:SI 0 "register_operand" "")]
2035 ""
2036 "
2037 {
2038 rtx op0 = operands[0];
2039 rtx op1 = m32r_compare_op0;
2040 rtx op2 = m32r_compare_op1;
2041 enum machine_mode mode = GET_MODE (op0);
2043 if (mode != SImode)
2044 FAIL;
2046 if (! register_operand (op1, mode))
2047 op1 = force_reg (mode, op1);
2049 if (! reg_or_int16_operand (op2, mode))
2050 op2 = force_reg (mode, op2);
2052 emit_insn (gen_sltu_insn (op0, op1, op2));
2053 DONE;
2054 }")
2056 (define_insn "sltu_insn"
2057 [(set (match_operand:SI 0 "register_operand" "=r,r")
2058 (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
2059 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
2060 (clobber (reg:CC 17))]
2061 ""
2062 "#"
2063 [(set_attr "type" "multi")
2064 (set_attr "length" "6,8")])
2066 (define_split
2067 [(set (match_operand:SI 0 "register_operand" "")
2068 (ltu:SI (match_operand:SI 1 "register_operand" "")
2069 (match_operand:SI 2 "reg_or_int16_operand" "")))
2070 (clobber (reg:CC 17))]
2071 ""
2072 [(set (reg:CC 17)
2073 (ltu:CC (match_dup 1)
2074 (match_dup 2)))
2075 (set (match_dup 0)
2076 (ne:SI (reg:CC 17) (const_int 0)))]
2077 "")
2079 (define_expand "sleu"
2080 [(match_operand:SI 0 "register_operand" "")]
2081 ""
2082 "
2083 {
2084 rtx op0 = operands[0];
2085 rtx op1 = m32r_compare_op0;
2086 rtx op2 = m32r_compare_op1;
2087 enum machine_mode mode = GET_MODE (op0);
2089 if (mode != SImode)
2090 FAIL;
2092 if (GET_CODE (op2) == CONST_INT)
2093 {
2094 HOST_WIDE_INT value = INTVAL (op2);
2095 if (value >= 2147483647)
2096 {
2097 emit_move_insn (op0, const1_rtx);
2098 DONE;
2099 }
2101 op2 = GEN_INT (value+1);
2102 if (value < 0 || value >= 32767)
2103 op2 = force_reg (mode, op2);
2105 emit_insn (gen_sltu_insn (op0, op1, op2));
2106 DONE;
2107 }
2109 if (! register_operand (op2, mode))
2110 op2 = force_reg (mode, op2);
2112 emit_insn (gen_sleu_insn (op0, op1, op2));
2113 DONE;
2114 }")
2116 (define_insn "sleu_insn"
2117 [(set (match_operand:SI 0 "register_operand" "=r")
2118 (leu:SI (match_operand:SI 1 "register_operand" "r")
2119 (match_operand:SI 2 "register_operand" "r")))
2120 (clobber (reg:CC 17))]
2121 ""
2122 "#"
2123 [(set_attr "type" "multi")
2124 (set_attr "length" "8")])
2126 (define_split
2127 [(set (match_operand:SI 0 "register_operand" "")
2128 (leu:SI (match_operand:SI 1 "register_operand" "")
2129 (match_operand:SI 2 "register_operand" "")))
2130 (clobber (reg:CC 17))]
2131 "!optimize_size"
2132 [(set (reg:CC 17)
2133 (ltu:CC (match_dup 2)
2134 (match_dup 1)))
2135 (set (match_dup 0)
2136 (ne:SI (reg:CC 17) (const_int 0)))
2137 (set (match_dup 0)
2138 (xor:SI (match_dup 0)
2139 (const_int 1)))]
2140 "")
2142 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
2143 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
2144 (define_split
2145 [(set (match_operand:SI 0 "register_operand" "")
2146 (leu:SI (match_operand:SI 1 "register_operand" "")
2147 (match_operand:SI 2 "register_operand" "")))
2148 (clobber (reg:CC 17))]
2149 "optimize_size"
2150 [(set (reg:CC 17)
2151 (ltu:CC (match_dup 2)
2152 (match_dup 1)))
2153 (set (match_dup 0)
2154 (ne:SI (reg:CC 17) (const_int 0)))
2155 (set (match_dup 0)
2156 (plus:SI (match_dup 0)
2157 (const_int -1)))
2158 (set (match_dup 0)
2159 (neg:SI (match_dup 0)))]
2160 "")
2162 (define_expand "sgtu"
2163 [(match_operand:SI 0 "register_operand" "")]
2164 ""
2165 "
2166 {
2167 rtx op0 = operands[0];
2168 rtx op1 = m32r_compare_op0;
2169 rtx op2 = m32r_compare_op1;
2170 enum machine_mode mode = GET_MODE (op0);
2172 if (mode != SImode)
2173 FAIL;
2175 if (! register_operand (op1, mode))
2176 op1 = force_reg (mode, op1);
2178 if (! register_operand (op2, mode))
2179 op2 = force_reg (mode, op2);
2181 emit_insn (gen_sltu_insn (op0, op2, op1));
2182 DONE;
2183 }")
2185 (define_expand "sgeu"
2186 [(match_operand:SI 0 "register_operand" "")]
2187 ""
2188 "
2189 {
2190 rtx op0 = operands[0];
2191 rtx op1 = m32r_compare_op0;
2192 rtx op2 = m32r_compare_op1;
2193 enum machine_mode mode = GET_MODE (op0);
2195 if (mode != SImode)
2196 FAIL;
2198 if (! register_operand (op1, mode))
2199 op1 = force_reg (mode, op1);
2201 if (! reg_or_int16_operand (op2, mode))
2202 op2 = force_reg (mode, op2);
2204 emit_insn (gen_sgeu_insn (op0, op1, op2));
2205 DONE;
2206 }")
2208 (define_insn "sgeu_insn"
2209 [(set (match_operand:SI 0 "register_operand" "=r,r")
2210 (geu:SI (match_operand:SI 1 "register_operand" "r,r")
2211 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
2212 (clobber (reg:CC 17))]
2213 ""
2214 "#"
2215 [(set_attr "type" "multi")
2216 (set_attr "length" "8,10")])
2218 (define_split
2219 [(set (match_operand:SI 0 "register_operand" "")
2220 (geu:SI (match_operand:SI 1 "register_operand" "")
2221 (match_operand:SI 2 "reg_or_int16_operand" "")))
2222 (clobber (reg:CC 17))]
2223 "!optimize_size"
2224 [(set (reg:CC 17)
2225 (ltu:CC (match_dup 1)
2226 (match_dup 2)))
2227 (set (match_dup 0)
2228 (ne:SI (reg:CC 17) (const_int 0)))
2229 (set (match_dup 0)
2230 (xor:SI (match_dup 0)
2231 (const_int 1)))]
2232 "")
2234 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
2235 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
2236 (define_split
2237 [(set (match_operand:SI 0 "register_operand" "")
2238 (geu:SI (match_operand:SI 1 "register_operand" "")
2239 (match_operand:SI 2 "reg_or_int16_operand" "")))
2240 (clobber (reg:CC 17))]
2241 "optimize_size"
2242 [(set (reg:CC 17)
2243 (ltu:CC (match_dup 1)
2244 (match_dup 2)))
2245 (set (match_dup 0)
2246 (ne:SI (reg:CC 17) (const_int 0)))
2247 (set (match_dup 0)
2248 (plus:SI (match_dup 0)
2249 (const_int -1)))
2250 (set (match_dup 0)
2251 (neg:SI (match_dup 0)))]
2252 "")
2254 (define_insn "movcc_insn"
2255 [(set (match_operand:SI 0 "register_operand" "=r")
2256 (ne:SI (reg:CC 17) (const_int 0)))]
2257 ""
2258 "mvfc %0, cbr"
2259 [(set_attr "type" "misc")
2260 (set_attr "length" "2")])
2262 \f
2263 ;; Unconditional and other jump instructions.
2265 (define_insn "jump"
2266 [(set (pc) (label_ref (match_operand 0 "" "")))]
2267 ""
2268 "bra %l0"
2269 [(set_attr "type" "uncond_branch")
2270 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
2271 (const_int 400))
2272 (const_int 800))
2273 (const_int 2)
2274 (const_int 4)))])
2276 (define_insn "indirect_jump"
2277 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
2278 ""
2279 "jmp %a0"
2280 [(set_attr "type" "uncond_branch")
2281 (set_attr "length" "2")])
2283 (define_insn "return_lr"
2284 [(parallel [(return) (use (reg:SI 14))])]
2285 ""
2286 "jmp lr"
2287 [(set_attr "type" "uncond_branch")
2288 (set_attr "length" "2")])
2290 (define_insn "return_rte"
2291 [(return)]
2292 ""
2293 "rte"
2294 [(set_attr "type" "uncond_branch")
2295 (set_attr "length" "2")])
2297 (define_expand "return"
2298 [(return)]
2299 "direct_return ()"
2300 "
2301 {
2302 emit_jump_insn (gen_return_lr ());
2303 DONE;
2304 }")
2306 (define_expand "return_normal"
2307 [(return)]
2308 "!direct_return ()"
2309 "
2310 {
2311 enum m32r_function_type fn_type;
2313 fn_type = m32r_compute_function_type (current_function_decl);
2314 if (M32R_INTERRUPT_P (fn_type))
2315 {
2316 emit_jump_insn (gen_return_rte ());
2317 DONE;
2318 }
2320 emit_jump_insn (gen_return_lr ());
2321 DONE;
2322 }")
2324 (define_expand "tablejump"
2325 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
2326 (use (label_ref (match_operand 1 "" "")))])]
2327 ""
2328 "
2329 {
2330 /* In pic mode, our address differences are against the base of the
2331 table. Add that base value back in; CSE ought to be able to combine
2332 the two address loads. */
2333 if (flag_pic)
2334 {
2335 rtx tmp, tmp2;
2337 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
2338 tmp2 = operands[0];
2339 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
2340 operands[0] = memory_address (Pmode, tmp);
2341 }
2342 }")
2344 (define_insn "*tablejump_insn"
2345 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
2346 (use (label_ref (match_operand 1 "" "")))]
2347 ""
2348 "jmp %a0"
2349 [(set_attr "type" "uncond_branch")
2350 (set_attr "length" "2")])
2352 (define_expand "call"
2353 ;; operands[1] is stack_size_rtx
2354 ;; operands[2] is next_arg_register
2355 [(parallel [(call (match_operand:SI 0 "call_operand" "")
2356 (match_operand 1 "" ""))
2357 (clobber (reg:SI 14))])]
2358 ""
2359 "
2360 {
2361 if (flag_pic)
2362 current_function_uses_pic_offset_table = 1;
2363 }")
2365 (define_insn "*call_via_reg"
2366 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
2367 (match_operand 1 "" ""))
2368 (clobber (reg:SI 14))]
2369 ""
2370 "jl %0"
2371 [(set_attr "type" "call")
2372 (set_attr "length" "2")])
2374 (define_insn "*call_via_label"
2375 [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
2376 (match_operand 1 "" ""))
2377 (clobber (reg:SI 14))]
2378 ""
2379 "*
2380 {
2381 int call26_p = call26_operand (operands[0], FUNCTION_MODE);
2383 if (! call26_p)
2384 {
2385 /* We may not be able to reach with a `bl' insn so punt and leave it to
2386 the linker.
2387 We do this here, rather than doing a force_reg in the define_expand
2388 so these insns won't be separated, say by scheduling, thus simplifying
2389 the linker. */
2390 return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
2391 }
2392 else
2393 return \"bl %0\";
2394 }"
2395 [(set_attr "type" "call")
2396 (set (attr "length")
2397 (if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
2398 (const_int 0))
2399 (const_int 12) ; 10 + 2 for nop filler
2400 ; The return address must be on a 4 byte boundary so
2401 ; there's no point in using a value of 2 here. A 2 byte
2402 ; insn may go in the left slot but we currently can't
2403 ; use such knowledge.
2404 (const_int 4)))])
2406 (define_expand "call_value"
2407 ;; operand 2 is stack_size_rtx
2408 ;; operand 3 is next_arg_register
2409 [(parallel [(set (match_operand 0 "register_operand" "=r")
2410 (call (match_operand:SI 1 "call_operand" "")
2411 (match_operand 2 "" "")))
2412 (clobber (reg:SI 14))])]
2413 ""
2414 "
2415 {
2416 if (flag_pic)
2417 current_function_uses_pic_offset_table = 1;
2418 }")
2420 (define_insn "*call_value_via_reg"
2421 [(set (match_operand 0 "register_operand" "=r")
2422 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
2423 (match_operand 2 "" "")))
2424 (clobber (reg:SI 14))]
2425 ""
2426 "jl %1"
2427 [(set_attr "type" "call")
2428 (set_attr "length" "2")])
2430 (define_insn "*call_value_via_label"
2431 [(set (match_operand 0 "register_operand" "=r")
2432 (call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
2433 (match_operand 2 "" "")))
2434 (clobber (reg:SI 14))]
2435 ""
2436 "*
2437 {
2438 int call26_p = call26_operand (operands[1], FUNCTION_MODE);
2440 if (flag_pic)
2441 current_function_uses_pic_offset_table = 1;
2443 if (! call26_p)
2444 {
2445 /* We may not be able to reach with a `bl' insn so punt and leave it to
2446 the linker.
2447 We do this here, rather than doing a force_reg in the define_expand
2448 so these insns won't be separated, say by scheduling, thus simplifying
2449 the linker. */
2450 return \"seth r14,%T1\;add3 r14,r14,%B1\;jl r14\";
2451 }
2452 else
2453 return \"bl %1\";
2454 }"
2455 [(set_attr "type" "call")
2456 (set (attr "length")
2457 (if_then_else (eq (symbol_ref "call26_operand (operands[1], FUNCTION_MODE)")
2458 (const_int 0))
2459 (const_int 12) ; 10 + 2 for nop filler
2460 ; The return address must be on a 4 byte boundary so
2461 ; there's no point in using a value of 2 here. A 2 byte
2462 ; insn may go in the left slot but we currently can't
2463 ; use such knowledge.
2464 (const_int 4)))])
2465 \f
2466 (define_insn "nop"
2467 [(const_int 0)]
2468 ""
2469 "nop"
2470 [(set_attr "type" "int2")
2471 (set_attr "length" "2")])
2473 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2474 ;; all of memory. This blocks insns from being moved across this point.
2476 (define_insn "blockage"
2477 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
2478 ""
2479 "")
2481 ;; Special pattern to flush the icache.
2483 (define_insn "flush_icache"
2484 [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
2485 UNSPECV_FLUSH_ICACHE)
2486 (match_operand 1 "" "")
2487 (clobber (reg:SI 17))]
2488 ""
2489 "* return \"trap %#%1 ; flush-icache\";"
2490 [(set_attr "type" "int4")
2491 (set_attr "length" "4")])
2492 \f
2493 ;; Speed up fabs and provide correct sign handling for -0
2495 (define_insn "absdf2"
2496 [(set (match_operand:DF 0 "register_operand" "=r")
2497 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
2498 ""
2499 "#"
2500 [(set_attr "type" "multi")
2501 (set_attr "length" "4")])
2503 (define_split
2504 [(set (match_operand:DF 0 "register_operand" "")
2505 (abs:DF (match_operand:DF 1 "register_operand" "")))]
2506 "reload_completed"
2507 [(set (match_dup 2)
2508 (ashift:SI (match_dup 2)
2509 (const_int 1)))
2510 (set (match_dup 2)
2511 (lshiftrt:SI (match_dup 2)
2512 (const_int 1)))]
2513 "operands[2] = gen_highpart (SImode, operands[0]);")
2515 (define_insn "abssf2"
2516 [(set (match_operand:SF 0 "register_operand" "=r")
2517 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2518 ""
2519 "#"
2520 [(set_attr "type" "multi")
2521 (set_attr "length" "4")])
2523 (define_split
2524 [(set (match_operand:SF 0 "register_operand" "")
2525 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2526 "reload_completed"
2527 [(set (match_dup 2)
2528 (ashift:SI (match_dup 2)
2529 (const_int 1)))
2530 (set (match_dup 2)
2531 (lshiftrt:SI (match_dup 2)
2532 (const_int 1)))]
2533 "operands[2] = gen_highpart (SImode, operands[0]);")
2534 \f
2535 ;; Conditional move instructions
2536 ;; Based on those done for the d10v
2538 (define_expand "movsicc"
2539 [
2540 (set (match_operand:SI 0 "register_operand" "r")
2541 (if_then_else:SI (match_operand 1 "" "")
2542 (match_operand:SI 2 "conditional_move_operand" "O")
2543 (match_operand:SI 3 "conditional_move_operand" "O")
2544 )
2545 )
2546 ]
2547 ""
2548 "
2549 {
2550 if (! zero_and_one (operands [2], operands [3]))
2551 FAIL;
2553 /* Generate the comparison that will set the carry flag. */
2554 operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0,
2555 m32r_compare_op1, TRUE);
2557 /* See other movsicc pattern below for reason why. */
2558 emit_insn (gen_blockage ());
2559 }")
2561 ;; Generate the conditional instructions based on how the carry flag is examined.
2562 (define_insn "*movsicc_internal"
2563 [(set (match_operand:SI 0 "register_operand" "=r")
2564 (if_then_else:SI (match_operand 1 "carry_compare_operand" "")
2565 (match_operand:SI 2 "conditional_move_operand" "O")
2566 (match_operand:SI 3 "conditional_move_operand" "O")
2567 )
2568 )]
2569 "zero_and_one (operands [2], operands[3])"
2570 "* return emit_cond_move (operands, insn);"
2571 [(set_attr "type" "multi")
2572 (set_attr "length" "8")
2573 ]
2574 )
2576 \f
2577 ;; Block moves, see m32r.c for more details.
2578 ;; Argument 0 is the destination
2579 ;; Argument 1 is the source
2580 ;; Argument 2 is the length
2581 ;; Argument 3 is the alignment
2583 (define_expand "movmemsi"
2584 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
2585 (match_operand:BLK 1 "general_operand" ""))
2586 (use (match_operand:SI 2 "immediate_operand" ""))
2587 (use (match_operand:SI 3 "immediate_operand" ""))])]
2588 ""
2589 "
2590 {
2591 if (operands[0]) /* Avoid unused code messages. */
2592 {
2593 if (m32r_expand_block_move (operands))
2594 DONE;
2595 else
2596 FAIL;
2597 }
2598 }")
2600 ;; Insn generated by block moves
2602 (define_insn "movmemsi_internal"
2603 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination
2604 (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source
2605 (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
2606 (set (match_operand:SI 3 "register_operand" "=0")
2607 (plus:SI (minus (match_dup 2) (const_int 4))
2608 (match_dup 0)))
2609 (set (match_operand:SI 4 "register_operand" "=1")
2610 (plus:SI (match_dup 1)
2611 (match_dup 2)))
2612 (clobber (match_scratch:SI 5 "=&r")) ;; temp1
2613 (clobber (match_scratch:SI 6 "=&r"))] ;; temp2
2614 ""
2615 "* m32r_output_block_move (insn, operands); return \"\"; "
2616 [(set_attr "type" "store8")
2617 (set_attr "length" "72")]) ;; Maximum
2619 ;; PIC
2621 /* When generating pic, we need to load the symbol offset into a register.
2622 So that the optimizer does not confuse this with a normal symbol load
2623 we use an unspec. The offset will be loaded from a constant pool entry,
2624 since that is the only type of relocation we can use. */
2626 (define_insn "pic_load_addr"
2627 [(set (match_operand:SI 0 "register_operand" "=r")
2628 (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
2629 "flag_pic"
2630 "ld24 %0,%#%1"
2631 [(set_attr "type" "int4")])
2633 (define_insn "gotoff_load_addr"
2634 [(set (match_operand:SI 0 "register_operand" "=r")
2635 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
2636 "flag_pic"
2637 "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
2638 [(set_attr "type" "int4")
2639 (set_attr "length" "8")])
2641 ;; Load program counter insns.
2643 (define_insn "get_pc"
2644 [(clobber (reg:SI 14))
2645 (set (match_operand 0 "register_operand" "=r")
2646 (unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
2647 (use (match_operand:SI 2 "immediate_operand" ""))]
2648 "flag_pic"
2649 "*
2650 {
2651 if (INTVAL(operands[2]))
2652 return \"bl.s .+4\;ld24 %0,%#%1\;add %0,lr\";
2653 else
2654 return \"bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr\";}"
2655 [(set (attr "length") (if_then_else (ne (match_dup 2) (const_int 0))
2656 (const_int 8)
2657 (const_int 12)))])
2659 (define_expand "builtin_setjmp_receiver"
2660 [(label_ref (match_operand 0 "" ""))]
2661 "flag_pic"
2662 "
2663 {
2664 m32r_load_pic_register ();
2665 DONE;
2666 }")