gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 2, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #ifndef GCC_M32C_H
  24 #define GCC_M32C_H
  25
  26 /* Controlling the Compilation Driver, `gcc'.  */
  27
  28 #undef  STARTFILE_SPEC
  29 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  30
  31 /* There are four CPU series we support, but they basically break down
  32    into two families - the R8C/M16C families, with 16-bit address
  33    registers and one set of opcodes, and the M32CM/M32C group, with
  34    24-bit address registers and a different set of opcodes.  The
  35    assembler doesn't care except for which opcode set is needed; the
  36    big difference is in the memory maps, which we cover in
  37    LIB_SPEC.  */
  38
  39 #undef  ASM_SPEC
  40 #define ASM_SPEC "\
  41 %{mcpu=r8c:--m16c} \
  42 %{mcpu=m16c:--m16c} \
  43 %{mcpu=m32cm:--m32c} \
  44 %{mcpu=m32c:--m32c} "
  45
  46 /* The default is R8C hardware.  We support a simulator, which has its
  47    own libgloss and link map, plus one default link map for each chip
  48    family.  Most of the logic here is making sure we do the right
  49    thing when no CPU is specified, which defaults to R8C.  */
  50 #undef  LIB_SPEC
  51 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
  52 %{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \
  53         %{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \
  54 %{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \
  55                 %{mcpu=m32cm:-Tm32cm.ld} \
  56                 %{mcpu=m32c:-Tm32c.ld} \
  57                 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \
  58 "
  59
  60 /* Run-time Target Specification */
  61
  62 /* Nothing unusual here.  */
  63 #define TARGET_CPU_CPP_BUILTINS() \
  64   { \
  65     builtin_assert ("cpu=m32c"); \
  66     builtin_assert ("machine=m32c"); \
  67     builtin_define ("__m32c__=1"); \
  68     if (TARGET_R8C) \
  69       builtin_define ("__r8c_cpu__=1"); \
  70     if (TARGET_M16C) \
  71       builtin_define ("__m16c_cpu__=1"); \
  72     if (TARGET_M32CM) \
  73       builtin_define ("__m32cm_cpu__=1"); \
  74     if (TARGET_M32C) \
  75       builtin_define ("__m32c_cpu__=1"); \
  76   }
  77
  78 /* The pragma handlers need to know if we've started processing
  79    functions yet, as the memregs pragma should only be given at the
  80    beginning of the file.  This variable starts off TRUE and later
  81    becomes FALSE.  */
  82 extern int ok_to_change_target_memregs;
  83 extern int target_memregs;
  84
  85 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  86    use enums or defines for this, this and m32c.opt are the only
  87    places that know (or care) what values are being used.  */
  88 #define TARGET_R8C      (target_cpu == 'r')
  89 #define TARGET_M16C     (target_cpu == '6')
  90 #define TARGET_M32CM    (target_cpu == 'm')
  91 #define TARGET_M32C     (target_cpu == '3')
  92
  93 /* Address register sizes.  Warning: these are used all over the place
  94    to select between the two CPU families in general.  */
  95 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
  96 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
  97
  98 #define TARGET_VERSION fprintf (stderr, " (m32c)");
  99
 100 #define OVERRIDE_OPTIONS m32c_override_options ();
 101
 102 /* Defining data structures for per-function information */
 103
 104 typedef struct machine_function GTY (())
 105 {
 106   /* How much we adjust the stack when returning from an exception
 107      handler.  */
 108   rtx eh_stack_adjust;
 109
 110   /* TRUE if the current function is an interrupt handler.  */
 111   int is_interrupt;
 112
 113   /* TRUE if the current function is a leaf function.  Currently, this
 114      only affects saving $a0 in interrupt functions.  */
 115   int is_leaf;
 116
 117   /* Bitmask that keeps track of which registers are used in an
 118      interrupt function, so we know which ones need to be saved and
 119      restored.  */
 120   int intr_pushm;
 121   /* Likewise, one element for each memreg that needs to be saved.  */
 122   char intr_pushmem[16];
 123
 124   /* TRUE if the current function can use a simple RTS to return, instead
 125      of the longer ENTER/EXIT pair.  */
 126   int use_rts;
 127 }
 128 machine_function;
 129
 130 #define INIT_EXPANDERS m32c_init_expanders ()
 131
 132 /* Storage Layout */
 133
 134 #define BITS_BIG_ENDIAN 0
 135 #define BYTES_BIG_ENDIAN 0
 136 #define WORDS_BIG_ENDIAN 0
 137
 138 /* We can do QI, HI, and SI operations pretty much equally well, but
 139    GCC expects us to have a "native" format, so we pick the one that
 140    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 141    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 142    24-bit pointers are stored in 32-bit words.  */
 143 #define BITS_PER_UNIT 8
 144 #define UNITS_PER_WORD 2
 145 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 146 #define POINTERS_EXTEND_UNSIGNED 1
 147
 148 /* These match the alignment enforced by the two types of stack operations.  */
 149 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 150 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 151
 152 /* We do this because we care more about space than about speed.  For
 153    the chips with 16-bit busses, we could set these to 16 if
 154    desired.  */
 155 #define FUNCTION_BOUNDARY 8
 156 #define BIGGEST_ALIGNMENT 8
 157
 158 #define STRICT_ALIGNMENT 0
 159 #define SLOW_BYTE_ACCESS 1
 160
 161 /* Layout of Source Language Data Types */
 162
 163 #define INT_TYPE_SIZE 16
 164 #define SHORT_TYPE_SIZE 16
 165 #define LONG_TYPE_SIZE 32
 166 #define LONG_LONG_TYPE_SIZE 64
 167
 168 #define FLOAT_TYPE_SIZE 32
 169 #define DOUBLE_TYPE_SIZE 64
 170 #define LONG_DOUBLE_TYPE_SIZE 64
 171
 172 #define DEFAULT_SIGNED_CHAR 1
 173
 174 #undef PTRDIFF_TYPE
 175 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 176
 177 /* REGISTER USAGE */
 178
 179 /* Register Basics */
 180
 181 /* Register layout:
 182
 183         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 184         [--------]  $r2  (16 bits)
 185         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 186         [--------]  $r3  (16 bits)
 187    [---][--------]  $a0  (might be 24 bits)
 188    [---][--------]  $a1  (might be 24 bits)
 189    [---][--------]  $sb  (might be 24 bits)
 190    [---][--------]  $fb  (might be 24 bits)
 191    [---][--------]  $sp  (might be 24 bits)
 192    [-------------]  $pc  (20 or 24 bits)
 193              [---]  $flg (CPU flags)
 194    [---][--------]  $argp (virtual)
 195         [--------]  $mem0 (all 16 bits)
 196           . . .
 197         [--------]  $mem14
 198 */
 199
 200 #define FIRST_PSEUDO_REGISTER   20
 201
 202 /* Note that these two tables are modified based on which CPU family
 203    you select; see m32c_conditional_register_usage for details.  */
 204
 205 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 206 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 207                               0, 0, 1, 0, \
 208                               1, 1, 0, 1, \
 209                               0, 0, 0, 0, 0, 0, 0, 0 }
 210 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 211                               1, 1, 1, 0, \
 212                               1, 1, 1, 1, \
 213                               1, 1, 1, 1, 1, 1, 1, 1 }
 214
 215 #define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage ();
 216
 217 /* The *_REGNO theme matches m32c.md and most register number
 218    arguments; the PC_REGNUM is the odd one out.  */
 219 #ifndef PC_REGNO
 220 #define PC_REGNO 9
 221 #endif
 222 #define PC_REGNUM PC_REGNO
 223
 224 /* Order of Allocation of Registers */
 225
 226 #define REG_ALLOC_ORDER { \
 227         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 228         12, 13, 14, 15, 16, 17, 18, /* mem0..mem7 */  \
 229         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 230
 231 /* How Values Fit in Registers */
 232
 233 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
 234 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
 235 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
 236 #define AVOID_CCMODE_COPIES
 237
 238 /* Register Classes */
 239
 240 /* Most registers are special purpose in some form or another, so this
 241    table is pretty big.  Class names are used for constraints also;
 242    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 243    See m32c_reg_class_from_constraint for the mapping.  There's some
 244    duplication so that we can better isolate the reason for using
 245    constraints in the md files from the actual registers used; for
 246    example we may want to exclude a1a0 from SI_REGS in the future,
 247    without precluding their use as HImode registers.  */
 248
 249 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 250 /*       mmPAR */
 251 #define REG_CLASS_CONTENTS \
 252 { { 0x00000000 }, /* NO */\
 253   { 0x00000100 }, /* SP  - sp */\
 254   { 0x00000080 }, /* FB  - fb */\
 255   { 0x00000040 }, /* SB  - sb */\
 256   { 0x000001c0 }, /* CR  - sb fb sp */\
 257   { 0x00000001 }, /* R0  - r0 */\
 258   { 0x00000004 }, /* R1  - r1 */\
 259   { 0x00000002 }, /* R2  - r2 */\
 260   { 0x00000008 }, /* R3  - r3 */\
 261   { 0x00000003 }, /* R02 - r0r2 */\
 262   { 0x00000005 }, /* HL  - r0 r1 */\
 263   { 0x00000005 }, /* QI  - r0 r1 */\
 264   { 0x0000000a }, /* R23 - r2 r3 */\
 265   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 266   { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
 267   { 0x00000010 }, /* A0  - a0 */\
 268   { 0x00000020 }, /* A1  - a1 */\
 269   { 0x00000030 }, /* A   - a0 a1 */\
 270   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 271   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 272   { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
 273   { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
 274   { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
 275   { 0x0000007f }, /* GENERAL */\
 276   { 0x00000400 }, /* FLG */\
 277   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 278   { 0x000ff000 }, /* MEM */\
 279   { 0x000ff003 }, /* R02_A_MEM */\
 280   { 0x000ff005 }, /* A_HL_MEM */\
 281   { 0x000ff00c }, /* R1_R3_A_MEM */\
 282   { 0x000ff00f }, /* R03_MEM */\
 283   { 0x000ff03f }, /* A_HI_MEM */\
 284   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 285   { 0x000ff1ff }, /* ALL */\
 286 }
 287
 288 enum reg_class
 289 {
 290   NO_REGS,
 291   SP_REGS,
 292   FB_REGS,
 293   SB_REGS,
 294   CR_REGS,
 295   R0_REGS,
 296   R1_REGS,
 297   R2_REGS,
 298   R3_REGS,
 299   R02_REGS,
 300   HL_REGS,
 301   QI_REGS,
 302   R23_REGS,
 303   R03_REGS,
 304   DI_REGS,
 305   A0_REGS,
 306   A1_REGS,
 307   A_REGS,
 308   AD_REGS,
 309   PS_REGS,
 310   SI_REGS,
 311   HI_REGS,
 312   RA_REGS,
 313   GENERAL_REGS,
 314   FLG_REGS,
 315   HC_REGS,
 316   MEM_REGS,
 317   R02_A_MEM_REGS,
 318   A_HL_MEM_REGS,
 319   R1_R3_A_MEM_REGS,
 320   R03_MEM_REGS,
 321   A_HI_MEM_REGS,
 322   A_AD_CR_MEM_SI_REGS,
 323   ALL_REGS,
 324   LIM_REG_CLASSES
 325 };
 326
 327 #define N_REG_CLASSES LIM_REG_CLASSES
 328
 329 #define REG_CLASS_NAMES {\
 330 "NO_REGS", \
 331 "SP_REGS", \
 332 "FB_REGS", \
 333 "SB_REGS", \
 334 "CR_REGS", \
 335 "R0_REGS", \
 336 "R1_REGS", \
 337 "R2_REGS", \
 338 "R3_REGS", \
 339 "R02_REGS", \
 340 "HL_REGS", \
 341 "QI_REGS", \
 342 "R23_REGS", \
 343 "R03_REGS", \
 344 "DI_REGS", \
 345 "A0_REGS", \
 346 "A1_REGS", \
 347 "A_REGS", \
 348 "AD_REGS", \
 349 "PS_REGS", \
 350 "SI_REGS", \
 351 "HI_REGS", \
 352 "RA_REGS", \
 353 "GENERAL_REGS", \
 354 "FLG_REGS", \
 355 "HC_REGS", \
 356 "MEM_REGS", \
 357 "R02_A_MEM_REGS", \
 358 "A_HL_MEM_REGS", \
 359 "R1_R3_A_MEM_REGS", \
 360 "R03_MEM_REGS", \
 361 "A_HI_MEM_REGS", \
 362 "A_AD_CR_MEM_SI_REGS", \
 363 "ALL_REGS", \
 364 }
 365
 366 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 367
 368 /* We support simple displacements off address registers, nothing else.  */
 369 #define BASE_REG_CLASS A_REGS
 370 #define INDEX_REG_CLASS NO_REGS
 371
 372 /* We primarily use the new "long" constraint names, with the initial
 373    letter classifying the constraint type and following letters
 374    specifying which.  The types are:
 375
 376    I - integer values
 377    R - register classes
 378    S - memory references (M was used)
 379    A - addresses (currently unused)
 380 */
 381
 382 #define CONSTRAINT_LEN(CHAR,STR) \
 383         ((CHAR) == 'I' ? 3 \
 384          : (CHAR) == 'R' ? 3 \
 385          : (CHAR) == 'S' ? 2 \
 386          : (CHAR) == 'A' ? 2 \
 387          : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
 388 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
 389         m32c_reg_class_from_constraint (CHAR, STR)
 390
 391 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 392 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 393
 394 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
 395 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
 396 #define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS)
 397
 398 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X)
 399
 400 #define SMALL_REGISTER_CLASSES 1
 401
 402 #define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C)
 403
 404 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
 405
 406 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
 407
 408 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
 409         m32c_const_ok_for_constraint_p (VALUE, C, STR)
 410 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
 411 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
 412         m32c_extra_constraint_p (VALUE, C, STR)
 413 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \
 414         m32c_extra_memory_constraint (C, STR)
 415 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
 416         m32c_extra_address_constraint (C, STR)
 417
 418 /* STACK AND CALLING */
 419
 420 /* Frame Layout */
 421
 422 /* Standard push/pop stack, no surprises here.  */
 423
 424 #define STACK_GROWS_DOWNWARD 1
 425 #define STACK_PUSH_CODE PRE_DEC
 426 #define FRAME_GROWS_DOWNWARD 1
 427
 428 #define STARTING_FRAME_OFFSET 0
 429 #define FIRST_PARM_OFFSET(F) 0
 430
 431 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 432
 433 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 434 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 435
 436 /* Exception Handling Support */
 437
 438 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 439 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 440
 441 /* Registers That Address the Stack Frame */
 442
 443 #ifndef FP_REGNO
 444 #define FP_REGNO 7
 445 #endif
 446 #ifndef SP_REGNO
 447 #define SP_REGNO 8
 448 #endif
 449 #define AP_REGNO 11
 450
 451 #define STACK_POINTER_REGNUM    SP_REGNO
 452 #define FRAME_POINTER_REGNUM    FP_REGNO
 453 #define ARG_POINTER_REGNUM      AP_REGNO
 454
 455 /* The static chain must be pointer-capable.  */
 456 #define STATIC_CHAIN_REGNUM A0_REGNO
 457
 458 #define DWARF_FRAME_REGISTERS 20
 459 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 460 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
 461
 462 /* Eliminating Frame Pointer and Arg Pointer */
 463
 464 /* If the frame pointer isn't used, we detect it manually.  But the
 465    stack pointer doesn't have as flexible addressing as the frame
 466    pointer, so we always assume we have it.  */
 467 #define FRAME_POINTER_REQUIRED 1
 468
 469 #define ELIMINABLE_REGS \
 470   {{AP_REGNO, SP_REGNO}, \
 471    {AP_REGNO, FB_REGNO}, \
 472    {FB_REGNO, SP_REGNO}}
 473
 474 #define CAN_ELIMINATE(FROM,TO) 1
 475 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 476         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 477
 478 /* Passing Function Arguments on the Stack */
 479
 480 #define PUSH_ARGS 1
 481 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 482 #define RETURN_POPS_ARGS(D,T,S) 0
 483 #define CALL_POPS_ARGS(C) 0
 484
 485 /* Passing Arguments in Registers */
 486
 487 #define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \
 488         m32c_function_arg (&(CA),MODE,TYPE,NAMED)
 489
 490 typedef struct m32c_cumulative_args
 491 {
 492   /* For address of return value buffer (structures are returned by
 493      passing the address of a buffer as an invisible first argument.
 494      This identifies it).  If set, the current parameter will be put
 495      on the stack, regardless of type.  */
 496   int force_mem;
 497   /* First parm is 1, parm 0 is hidden pointer for returning
 498      aggregates.  */
 499   int parm_num;
 500 } m32c_cumulative_args;
 501
 502 #define CUMULATIVE_ARGS m32c_cumulative_args
 503 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 504         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 505 #define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \
 506         m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED)
 507 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16)
 508 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 509
 510 /* How Scalar Function Values Are Returned */
 511
 512 #define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F)
 513 #define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE)
 514
 515 #define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO)
 516
 517 /* How Large Values Are Returned */
 518
 519 #define DEFAULT_PCC_STRUCT_RETURN 1
 520
 521 /* Function Entry and Exit */
 522
 523 #define EXIT_IGNORE_STACK 0
 524 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 525 #define EH_USES(REGNO) 0        /* FIXME */
 526
 527 /* Generating Code for Profiling */
 528
 529 #define FUNCTION_PROFILER(FILE,LABELNO)
 530
 531 /* Implementing the Varargs Macros */
 532
 533 /* Trampolines for Nested Functions */
 534
 535 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 536 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 537 #define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc)
 538
 539 /* Addressing Modes */
 540
 541 #define HAVE_PRE_DECREMENT 1
 542 #define HAVE_POST_INCREMENT 1
 543 #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
 544 #define MAX_REGS_PER_ADDRESS 1
 545
 546 /* This is passed to the macros below, so that they can be implemented
 547    in m32c.c.  */
 548 #ifdef REG_OK_STRICT
 549 #define REG_OK_STRICT_V 1
 550 #else
 551 #define REG_OK_STRICT_V 0
 552 #endif
 553
 554 #define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \
 555         if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \
 556           goto LABEL;
 557
 558 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 559 #define REG_OK_FOR_INDEX_P(X) 0
 560
 561 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 562
 563 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
 564         if (m32c_legitimize_address(&(X),OLDX,MODE)) \
 565           goto win;
 566
 567 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 568         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 569           goto win;
 570
 571 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
 572
 573 #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
 574
 575 /* Condition Code Status */
 576
 577 #define REVERSIBLE_CC_MODE(MODE) 1
 578
 579 /* Describing Relative Costs of Operations */
 580
 581 #define REGISTER_MOVE_COST(MODE,FROM,TO) \
 582         m32c_register_move_cost (MODE, FROM, TO)
 583 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
 584         m32c_memory_move_cost (MODE, CLASS, IN)
 585
 586 /* Dividing the Output into Sections (Texts, Data, ...) */
 587
 588 #define TEXT_SECTION_ASM_OP ".text"
 589 #define DATA_SECTION_ASM_OP ".data"
 590 #define BSS_SECTION_ASM_OP ".bss"
 591
 592 #define CTOR_LIST_BEGIN
 593 #define CTOR_LIST_END
 594 #define DTOR_LIST_BEGIN
 595 #define DTOR_LIST_END
 596 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 597 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 598 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 599 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 600
 601 /* The Overall Framework of an Assembler File */
 602
 603 #define ASM_COMMENT_START ";"
 604 #define ASM_APP_ON ""
 605 #define ASM_APP_OFF ""
 606
 607 /* Output and Generation of Labels */
 608
 609 #define GLOBAL_ASM_OP "\t.global\t"
 610
 611 /* Output of Assembler Instructions */
 612
 613 #define REGISTER_NAMES {        \
 614   "r0", "r2", "r1", "r3", \
 615   "a0", "a1", "sb", "fb", "sp", \
 616   "pc", "flg", "argp", \
 617   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 618 }
 619
 620 #define ADDITIONAL_REGISTER_NAMES { \
 621   {"r0l", 0}, \
 622   {"r1l", 2}, \
 623   {"r0r2", 0}, \
 624   {"r1r3", 2}, \
 625   {"a0a1", 4}, \
 626   {"r0r2r1r3", 0} }
 627
 628 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
 629 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
 630 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
 631
 632 #undef USER_LABEL_PREFIX
 633 #define USER_LABEL_PREFIX "_"
 634
 635 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 636 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 637
 638 /* Output of Dispatch Tables */
 639
 640 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 641         fprintf (S, "\t.word L%d\n", V)
 642
 643 /* Assembler Commands for Exception Regions */
 644
 645 #define DWARF_CIE_DATA_ALIGNMENT -1
 646
 647 /* Assembler Commands for Alignment */
 648
 649 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 650         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 651
 652 /* Controlling Debugging Information Format */
 653
 654 #define DWARF2_ADDR_SIZE        4
 655
 656 /* Miscellaneous Parameters */
 657
 658 #define HAS_LONG_COND_BRANCH false
 659 #define HAS_LONG_UNCOND_BRANCH true
 660 #define CASE_VECTOR_MODE SImode
 661 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 662
 663 #define MOVE_MAX 4
 664 #define TRULY_NOOP_TRUNCATION(op,ip) 1
 665
 666 #define STORE_FLAG_VALUE 1
 667
 668 /* 16- or 24-bit pointers */
 669 #define Pmode (TARGET_A16 ? HImode : PSImode)
 670 #define FUNCTION_MODE QImode
 671
 672 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 673
 674 #endif