1 ;; Machine Descriptions for R8C/M16C/M32C
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the Free
20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
23 ;; Bit-wise operations (and, ior, xor, shift)
25 ; On the R8C and M16C, "address" for bit instructions is usually (but
26 ; not always!) the *bit* address, not the *byte* address. This
27 ; confuses gcc, so we avoid cases where gcc would produce the wrong
28 ; code. We're left with absolute addresses and registers, and the odd
29 ; case of shifting a bit by a variable.
31 ; On the M32C, "address" for bit instructions is a regular address,
32 ; and the bit number is stored in a separate field. Thus, we can let
33 ; gcc do more interesting things. However, the M32C cannot set all
34 ; the bits in a 16-bit register, which the R8C/M16C can do.
36 ; However, it all means that we end up with two sets of patterns, one
39 ;;----------------------------------------------------------------------
41 ;; First off, all the ways we can set one bit, other than plain IOR.
43 (define_insn "bset_qi"
44 [(set (match_operand:QI 0 "memsym_operand" "+Si")
45 (ior:QI (subreg:QI (ashift:HI (const_int 1)
46 (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
47 (match_operand:QI 2 "" "0")))]
50 [(set_attr "flags" "n")]
53 (define_insn "bset_hi"
54 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
56 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
60 [(set_attr "flags" "n")]
63 ;;----------------------------------------------------------------------
65 ;; Now all the ways we can clear one bit, other than plain AND.
67 ; This is odd because the shift patterns use QI counts, but we can't
68 ; easily put QI in $aN without causing problems elsewhere.
69 (define_insn "bclr_qi"
70 [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
72 (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
76 [(set_attr "flags" "n")]
80 ;;----------------------------------------------------------------------
82 ;; Now the generic patterns.
84 (define_insn "andqi3_16"
85 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
86 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
87 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
96 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
99 (define_insn "andhi3_16"
100 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
101 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
102 (match_operand:HI 2 "mrai_operand" "Imb,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
113 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
116 (define_insn "andsi3"
117 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
118 (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
119 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
122 switch (which_alternative)
125 output_asm_insn (\"and.w %X2,%h0\",operands);
126 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
127 return \"and.w %X2,%H0\";
129 return \"and.w %h2,%h0\;and.w %H2,%H0\";
131 output_asm_insn (\"and.w %X2,%h0\",operands);
132 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
133 return \"and.w %X2,%H0\";
135 return \"and.w %h2,%h0\;and.w %H2,%H0\";
137 return \"and.w %h2,%h0\;and.w %H2,%H0\";
139 return \"and.w %h2,%h0\;and.w %H2,%H0\";
141 [(set_attr "flags" "x,x,x,x,x,x")]
145 (define_insn "iorqi3_16"
146 [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
147 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
148 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
157 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
160 (define_insn "iorhi3_16"
161 [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
162 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
163 (match_operand:HI 2 "mrai_operand" "Imb,Imw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
173 [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
176 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
178 (define_insn "andqi3_24"
179 [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
180 (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
181 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
190 [(set_attr "flags" "n,n,sz,sz,sz,sz")]
193 (define_insn "andhi3_24"
194 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,??Rmm,RhiSd,??Rmm")
195 (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
196 (match_operand:HI 2 "mrai_operand" "Imb,Imw,Imb,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
207 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
212 (define_insn "iorqi3_24"
213 [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
214 (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
215 (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
223 [(set_attr "flags" "n,sz,sz,sz,sz")]
226 (define_insn "iorhi3_24"
227 [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,RhiSd,??Rmm,??Rmm")
228 (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
229 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
240 [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
244 ; ----------------------------------------------------------------------
246 (define_expand "andqi3"
247 [(set (match_operand:QI 0 "mra_operand" "")
248 (and:QI (match_operand:QI 1 "mra_operand" "")
249 (match_operand:QI 2 "mrai_operand" "")))]
252 emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
254 emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
258 (define_expand "andhi3"
259 [(set (match_operand:HI 0 "mra_operand" "")
260 (and:HI (match_operand:HI 1 "mra_operand" "")
261 (match_operand:HI 2 "mrai_operand" "")))]
264 emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
266 emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
270 (define_expand "iorqi3"
271 [(set (match_operand:QI 0 "mra_operand" "")
272 (ior:QI (match_operand:QI 1 "mra_operand" "")
273 (match_operand:QI 2 "mrai_operand" "")))]
276 emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
278 emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
282 (define_expand "iorhi3"
283 [(set (match_operand:HI 0 "mra_operand" "")
284 (ior:HI (match_operand:HI 1 "mra_operand" "")
285 (match_operand:HI 2 "mrai_operand" "")))]
288 emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
290 emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
294 (define_insn "iorsi3"
295 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
296 (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
297 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
300 switch (which_alternative)
303 output_asm_insn (\"or.w %X2,%h0\",operands);
304 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
305 return \"or.w %X2,%H0\";
307 return \"or.w %h2,%h0\;or.w %H2,%H0\";
309 output_asm_insn (\"or.w %X2,%h0\",operands);
310 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
311 return \"or.w %X2,%H0\";
313 return \"or.w %h2,%h0\;or.w %H2,%H0\";
315 return \"or.w %h2,%h0\;or.w %H2,%H0\";
317 return \"or.w %h2,%h0\;or.w %H2,%H0\";
319 [(set_attr "flags" "x,x,x,x,x,x")]
322 (define_insn "xorqi3"
323 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
324 (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
325 (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
328 [(set_attr "flags" "sz,sz,sz,sz")]
331 (define_insn "xorhi3"
332 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
333 (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
334 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
337 [(set_attr "flags" "sz,sz,sz,sz")]
340 (define_insn "xorsi3"
341 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
342 (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
343 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
346 switch (which_alternative)
349 output_asm_insn (\"xor.w %X2,%h0\",operands);
350 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
351 return \"xor.w %X2,%H0\";
353 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
355 output_asm_insn (\"xor.w %X2,%h0\",operands);
356 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
357 return \"xor.w %X2,%H0\";
359 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
361 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
363 return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
365 [(set_attr "flags" "x,x,x,x,x,x")]
368 (define_insn "one_cmplqi2"
369 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
370 (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
373 [(set_attr "flags" "sz,sz")]
376 (define_insn "one_cmplhi2"
377 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
378 (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
381 [(set_attr "flags" "sz,sz")]
384 ; Optimizations using bit opcodes
386 ; We need this because combine only looks at three insns at a time,
387 ; and the bclr_qi pattern uses four - mov, shift, not, and. GCC
388 ; should never expand this pattern, because it only shifts a constant
389 ; by a constant, so gcc should do that itself.
390 (define_insn "shift1_qi"
391 [(set (match_operand:QI 0 "mra_operand" "=Rqi")
392 (ashift:QI (const_int 1)
393 (match_operand 1 "const_int_operand" "In4")))]
395 "mov.b\t#1,%0\n\tshl.b\t%1,%0"
397 (define_insn "shift1_hi"
398 [(set (match_operand:HI 0 "mra_operand" "=Rhi")
399 (ashift:HI (const_int 1)
400 (match_operand 1 "const_int_operand" "In4")))]
402 "mov.w\t#1,%0\n\tshl.w\t%1,%0"
405 ; Generic insert-bit expander, needed so that we can use the bit
406 ; opcodes for volatile bitfields.
408 (define_expand "insv"
409 [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
410 (match_operand 1 "const_int_operand" "")
411 (match_operand 2 "const_int_operand" ""))
412 (match_operand:HI 3 "const_int_operand" ""))]
414 "if (m32c_expand_insv (operands))