| blob | 468b5b315071a53f6abcaac76b6a1e9dab3ec94a |
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
29 /* The architecture define. */
32 /* Target CPU builtins. */
33 #define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
36 /* Define __arm__ even when in thumb mode, for \
40 if (TARGET_THUMB) \
42 \
43 if (TARGET_BIG_END) \
44 { \
46 if (TARGET_THUMB) \
48 if (TARGET_LITTLE_WORDS) \
50 } \
51 else \
52 { \
54 if (TARGET_THUMB) \
56 } \
57 \
58 if (TARGET_SOFT_FLOAT) \
60 \
61 if (TARGET_VFP) \
63 \
64 /* Add a define for interworking. \
66 if (arm_cpp_interwork) \
68 \
71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
75 if (arm_arch_xscale) \
77 if (arm_arch_iwmmxt) \
79 if (TARGET_AAPCS_BASED) \
81 } while (0)
83 /* The various ARM cores. */
84 enum processor_type
85 {
86 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
89 #undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92 };
94 enum target_cpus
95 {
96 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
99 #undef ARM_CORE
100 TARGET_CPU_generic
101 };
103 /* The processor for which instructions should be scheduled. */
107 {
110 }
111 arm_cc;
115 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
124 /* The label of the current constant pool. */
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
129 /* Used to produce AOF syntax assembler. */
131 \f
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
135 #endif
138 #undef CPP_SPEC
140 %{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142 %{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
145 #ifndef CC1_SPEC
147 #endif
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
155 program.
157 Do not define this macro if it does not need to do anything. */
158 #define EXTRA_SPECS \
160 SUBTARGET_EXTRA_SPECS
162 #ifndef SUBTARGET_EXTRA_SPECS
163 #define SUBTARGET_EXTRA_SPECS
164 #endif
166 #ifndef SUBTARGET_CPP_SPEC
168 #endif
169 \f
170 /* Run-time Target Specification. */
171 #ifndef TARGET_VERSION
173 #endif
175 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
176 /* Use hardware floating point instructions. */
177 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178 /* Use hardware floating point calling convention. */
179 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
180 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
183 #define TARGET_IWMMXT (arm_arch_iwmmxt)
184 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
185 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
186 #define TARGET_ARM (! TARGET_THUMB)
188 #define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
191 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
192 #define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
195 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
196 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
198 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
199 then TARGET_AAPCS_BASED must be true -- but the converse does not
200 hold. TARGET_BPABI implies the use of the BPABI runtime library,
201 etc., in addition to just the AAPCS calling conventions. */
202 #ifndef TARGET_BPABI
203 #define TARGET_BPABI false
204 #endif
206 /* Support for a compile-time default CPU, et cetera. The rules are:
207 --with-arch is ignored if -march or -mcpu are specified.
208 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
209 by --with-arch.
210 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
211 by -march).
212 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
213 specified.
214 --with-fpu is ignored if -mfpu is specified.
215 --with-abi is ignored is -mabi is specified. */
216 #define OPTION_DEFAULT_SPECS \
226 /* Which floating point model to use. */
227 enum arm_fp_model
228 {
229 ARM_FP_MODEL_UNKNOWN,
230 /* FPA model (Hardware or software). */
231 ARM_FP_MODEL_FPA,
232 /* Cirrus Maverick floating point model. */
233 ARM_FP_MODEL_MAVERICK,
234 /* VFP floating point model. */
235 ARM_FP_MODEL_VFP
236 };
240 /* Which floating point hardware is available. Also update
241 fp_model_for_fpu in arm.c when adding entries to this list. */
242 enum fputype
243 {
244 /* No FP hardware. */
245 FPUTYPE_NONE,
246 /* Full FPA support. */
247 FPUTYPE_FPA,
248 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
249 FPUTYPE_FPA_EMU2,
250 /* Emulated FPA hardware, Issue 3 emulator. */
251 FPUTYPE_FPA_EMU3,
252 /* Cirrus Maverick floating point co-processor. */
253 FPUTYPE_MAVERICK,
254 /* VFP. */
255 FPUTYPE_VFP
256 };
258 /* Recast the floating point class to be the floating point attribute. */
259 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
261 /* What type of floating point to tune for */
264 /* What type of floating point instructions are available */
267 enum float_abi_type
268 {
269 ARM_FLOAT_ABI_SOFT,
270 ARM_FLOAT_ABI_SOFTFP,
271 ARM_FLOAT_ABI_HARD
272 };
276 #ifndef TARGET_DEFAULT_FLOAT_ABI
277 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
278 #endif
280 /* Which ABI to use. */
281 enum arm_abi_type
282 {
283 ARM_ABI_APCS,
284 ARM_ABI_ATPCS,
285 ARM_ABI_AAPCS,
286 ARM_ABI_IWMMXT,
287 ARM_ABI_AAPCS_LINUX
288 };
292 #ifndef ARM_DEFAULT_ABI
293 #define ARM_DEFAULT_ABI ARM_ABI_APCS
294 #endif
296 /* Which thread pointer access sequence to use. */
298 TP_AUTO,
299 TP_SOFT,
300 TP_CP15
301 };
305 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
308 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
311 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
314 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
317 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
320 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
323 /* Nonzero if this chip can benefit from load scheduling. */
326 /* Nonzero if generating thumb code. */
329 /* Nonzero if this chip is a StrongARM. */
332 /* Nonzero if this chip is a Cirrus variant. */
335 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
338 /* Nonzero if this chip is an XScale. */
341 /* Nonzero if tuning for XScale. */
344 /* Nonzero if tuning for stores via the write buffer. */
347 /* Nonzero if we should define __THUMB_INTERWORK__ in the
348 preprocessor.
349 XXX This is a bit of a hack, it's intended to help work around
350 problems in GLD which doesn't understand that armv5t code is
351 interworking clean. */
354 #ifndef TARGET_DEFAULT
355 #define TARGET_DEFAULT (MASK_APCS_FRAME)
356 #endif
358 /* The frame pointer register used in gcc has nothing to do with debugging;
359 that is controlled by the APCS-FRAME option. */
360 #define CAN_DEBUG_WITHOUT_FP
362 #define OVERRIDE_OPTIONS arm_override_options ()
364 /* Nonzero if PIC code requires explicit qualifiers to generate
365 PLT and GOT relocs rather than the assembler doing so implicitly.
366 Subtargets can override these if required. */
367 #ifndef NEED_GOT_RELOC
368 #define NEED_GOT_RELOC 0
369 #endif
370 #ifndef NEED_PLT_RELOC
371 #define NEED_PLT_RELOC 0
372 #endif
374 /* Nonzero if we need to refer to the GOT with a PC-relative
375 offset. In other words, generate
377 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
379 rather than
381 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
383 The default is true, which matches NetBSD. Subtargets can
384 override this if required. */
385 #ifndef GOT_PCREL
386 #define GOT_PCREL 1
387 #endif
388 \f
389 /* Target machine storage Layout. */
392 /* Define this macro if it is advisable to hold scalars in registers
393 in a wider mode than that declared by the program. In such cases,
394 the value is constrained to be within the bounds of the declared
395 type, but kept valid in the wider mode. The signedness of the
396 extension may differ from that of the type. */
398 /* It is far faster to zero extend chars than to sign extend them */
400 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
401 if (GET_MODE_CLASS (MODE) == MODE_INT \
402 && GET_MODE_SIZE (MODE) < 4) \
403 { \
404 if (MODE == QImode) \
405 UNSIGNEDP = 1; \
406 else if (MODE == HImode) \
407 UNSIGNEDP = 1; \
408 (MODE) = SImode; \
409 }
411 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
412 if ((GET_MODE_CLASS (MODE) == MODE_INT \
413 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
414 && GET_MODE_SIZE (MODE) < 4) \
415 (MODE) = SImode; \
417 /* Define this if most significant bit is lowest numbered
418 in instructions that operate on numbered bit-fields. */
419 #define BITS_BIG_ENDIAN 0
421 /* Define this if most significant byte of a word is the lowest numbered.
422 Most ARM processors are run in little endian mode, so that is the default.
423 If you want to have it run-time selectable, change the definition in a
424 cover file to be TARGET_BIG_ENDIAN. */
425 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
427 /* Define this if most significant word of a multiword number is the lowest
428 numbered.
429 This is always false, even when in big-endian mode. */
430 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
432 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
433 on processor pre-defineds when compiling libgcc2.c. */
434 #if defined(__ARMEB__) && !defined(__ARMWEL__)
435 #define LIBGCC2_WORDS_BIG_ENDIAN 1
436 #else
437 #define LIBGCC2_WORDS_BIG_ENDIAN 0
438 #endif
440 /* Define this if most significant word of doubles is the lowest numbered.
441 The rules are different based on whether or not we use FPA-format,
442 VFP-format or some other floating point co-processor's format doubles. */
443 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
445 #define UNITS_PER_WORD 4
447 /* True if natural alignment is used for doubleword types. */
448 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
450 #define DOUBLEWORD_ALIGNMENT 64
452 #define PARM_BOUNDARY 32
454 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
456 #define PREFERRED_STACK_BOUNDARY \
457 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
459 #define FUNCTION_BOUNDARY 32
461 /* The lowest bit is used to indicate Thumb-mode functions, so the
462 vbit must go into the delta field of pointers to member
463 functions. */
464 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
466 #define EMPTY_FIELD_BOUNDARY 32
468 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
470 /* XXX Blah -- this macro is used directly by libobjc. Since it
471 supports no vector modes, cut out the complexity and fall back
472 on BIGGEST_FIELD_ALIGNMENT. */
473 #ifdef IN_TARGET_LIBS
474 #define BIGGEST_FIELD_ALIGNMENT 64
475 #endif
477 /* Make strings word-aligned so strcpy from constants will be faster. */
478 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
480 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
481 ((TREE_CODE (EXP) == STRING_CST \
482 && !optimize_size \
483 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
484 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
486 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
487 value set in previous versions of this toolchain was 8, which produces more
488 compact structures. The command line option -mstructure_size_boundary=<n>
489 can be used to change this value. For compatibility with the ARM SDK
490 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
491 0020D) page 2-20 says "Structures are aligned on word boundaries".
492 The AAPCS specifies a value of 8. */
493 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
496 /* This is the value used to initialize arm_structure_size_boundary. If a
497 particular arm target wants to change the default value it should change
498 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
499 for an example of this. */
500 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
501 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
502 #endif
504 /* Nonzero if move instructions will actually fail to work
505 when given unaligned data. */
506 #define STRICT_ALIGNMENT 1
508 /* wchar_t is unsigned under the AAPCS. */
509 #ifndef WCHAR_TYPE
512 #define WCHAR_TYPE_SIZE BITS_PER_WORD
513 #endif
515 #ifndef SIZE_TYPE
517 #endif
519 #ifndef PTRDIFF_TYPE
521 #endif
523 /* AAPCS requires that structure alignment is affected by bitfields. */
524 #ifndef PCC_BITFIELD_TYPE_MATTERS
525 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
526 #endif
528 \f
529 /* Standard register usage. */
531 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
532 (S - saved over call).
534 r0 * argument word/integer result
535 r1-r3 argument word
537 r4-r8 S register variable
538 r9 S (rfp) register variable (real frame pointer)
540 r10 F S (sl) stack limit (used by -mapcs-stack-check)
541 r11 F S (fp) argument pointer
542 r12 (ip) temp workspace
543 r13 F S (sp) lower end of current stack frame
544 r14 (lr) link address/workspace
545 r15 F (pc) program counter
547 f0 floating point result
548 f1-f3 floating point scratch
550 f4-f7 S floating point variable
552 cc This is NOT a real register, but is used internally
553 to represent things that use or set the condition
554 codes.
555 sfp This isn't either. It is used during rtl generation
556 since the offset between the frame pointer and the
557 auto's isn't known until after register allocation.
558 afp Nor this, we only need this because of non-local
559 goto. Without it fp appears to be used and the
560 elimination code won't get rid of sfp. It tracks
561 fp exactly at all times.
563 *: See CONDITIONAL_REGISTER_USAGE */
565 /*
566 mvf0 Cirrus floating point result
567 mvf1-mvf3 Cirrus floating point scratch
568 mvf4-mvf15 S Cirrus floating point variable. */
570 /* s0-s15 VFP scratch (aka d0-d7).
571 s16-s31 S VFP variable (aka d8-d15).
572 vfpcc Not a real register. Represents the VFP condition
573 code flags. */
575 /* The stack backtrace structure is as follows:
576 fp points to here: | save code pointer | [fp]
577 | return link value | [fp, #-4]
578 | return sp value | [fp, #-8]
579 | return fp value | [fp, #-12]
580 [| saved r10 value |]
581 [| saved r9 value |]
582 [| saved r8 value |]
583 [| saved r7 value |]
584 [| saved r6 value |]
585 [| saved r5 value |]
586 [| saved r4 value |]
587 [| saved r3 value |]
588 [| saved r2 value |]
589 [| saved r1 value |]
590 [| saved r0 value |]
591 [| saved f7 value |] three words
592 [| saved f6 value |] three words
593 [| saved f5 value |] three words
594 [| saved f4 value |] three words
595 r0-r3 are not normally saved in a C function. */
597 /* 1 for registers that have pervasive standard uses
598 and are not available for the register allocator. */
599 #define FIXED_REGISTERS \
600 { \
601 0,0,0,0,0,0,0,0, \
602 0,0,0,0,0,1,0,1, \
603 0,0,0,0,0,0,0,0, \
604 1,1,1, \
605 1,1,1,1,1,1,1,1, \
606 1,1,1,1,1,1,1,1, \
607 1,1,1,1,1,1,1,1, \
608 1,1,1,1,1,1,1,1, \
609 1,1,1,1, \
610 1,1,1,1,1,1,1,1, \
611 1,1,1,1,1,1,1,1, \
612 1,1,1,1,1,1,1,1, \
613 1,1,1,1,1,1,1,1, \
614 1 \
615 }
617 /* 1 for registers not available across function calls.
618 These must include the FIXED_REGISTERS and also any
619 registers that can be used without being saved.
620 The latter must include the registers where values are returned
621 and the register where structure-value addresses are passed.
622 Aside from that, you can include as many other registers as you like.
623 The CC is not preserved over function calls on the ARM 6, so it is
624 easier to assume this for all. SFP is preserved, since FP is. */
625 #define CALL_USED_REGISTERS \
626 { \
627 1,1,1,1,0,0,0,0, \
628 0,0,0,0,1,1,1,1, \
629 1,1,1,1,0,0,0,0, \
630 1,1,1, \
631 1,1,1,1,1,1,1,1, \
632 1,1,1,1,1,1,1,1, \
633 1,1,1,1,1,1,1,1, \
634 1,1,1,1,1,1,1,1, \
635 1,1,1,1, \
636 1,1,1,1,1,1,1,1, \
637 1,1,1,1,1,1,1,1, \
638 1,1,1,1,1,1,1,1, \
639 1,1,1,1,1,1,1,1, \
640 1 \
641 }
643 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
644 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
645 #endif
647 #define CONDITIONAL_REGISTER_USAGE \
648 { \
649 int regno; \
650 \
651 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
652 { \
653 for (regno = FIRST_FPA_REGNUM; \
654 regno <= LAST_FPA_REGNUM; ++regno) \
655 fixed_regs[regno] = call_used_regs[regno] = 1; \
656 } \
657 \
658 if (TARGET_THUMB && optimize_size) \
659 { \
660 /* When optimizing for size, it's better not to use \
661 the HI regs, because of the overhead of stacking \
663 for (regno = FIRST_HI_REGNUM; \
664 regno <= LAST_HI_REGNUM; ++regno) \
665 fixed_regs[regno] = call_used_regs[regno] = 1; \
666 } \
667 \
668 /* The link register can be clobbered by any branch insn, \
669 but we have no way to track that at present, so mark \
671 if (TARGET_THUMB) \
672 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
673 \
674 if (TARGET_ARM && TARGET_HARD_FLOAT) \
675 { \
676 if (TARGET_MAVERICK) \
677 { \
678 for (regno = FIRST_FPA_REGNUM; \
679 regno <= LAST_FPA_REGNUM; ++ regno) \
680 fixed_regs[regno] = call_used_regs[regno] = 1; \
681 for (regno = FIRST_CIRRUS_FP_REGNUM; \
682 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
683 { \
684 fixed_regs[regno] = 0; \
685 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
686 } \
687 } \
688 if (TARGET_VFP) \
689 { \
690 for (regno = FIRST_VFP_REGNUM; \
691 regno <= LAST_VFP_REGNUM; ++ regno) \
692 { \
693 fixed_regs[regno] = 0; \
694 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
695 } \
696 } \
697 } \
698 \
699 if (TARGET_REALLY_IWMMXT) \
700 { \
701 regno = FIRST_IWMMXT_GR_REGNUM; \
702 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
703 and wCG1 as call-preserved registers. The 2002/11/21 \
704 revision changed this so that all wCG registers are \
706 for (regno = FIRST_IWMMXT_GR_REGNUM; \
707 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
708 fixed_regs[regno] = 0; \
709 /* The XScale ABI has wR0 - wR9 as scratch registers, \
711 for (regno = FIRST_IWMMXT_REGNUM; \
712 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
713 { \
714 fixed_regs[regno] = 0; \
715 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
716 } \
717 } \
718 \
719 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
720 { \
721 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
722 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
723 } \
724 else if (TARGET_APCS_STACK) \
725 { \
726 fixed_regs[10] = 1; \
727 call_used_regs[10] = 1; \
728 } \
729 /* -mcaller-super-interworking reserves r11 for calls to \
730 _interwork_r11_call_via_rN(). Making the register global \
731 is an easy way of ensuring that it remains valid for all \
733 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
734 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
735 { \
736 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
737 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
738 if (TARGET_CALLER_INTERWORKING) \
739 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
740 } \
741 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
742 }
744 /* These are a couple of extensions to the formats accepted
745 by asm_fprintf:
746 %@ prints out ASM_COMMENT_START
747 %r prints out REGISTER_PREFIX reg_names[arg] */
748 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
750 fputs (ASM_COMMENT_START, FILE); \
751 break; \
752 \
754 fputs (REGISTER_PREFIX, FILE); \
755 fputs (reg_names [va_arg (ARGS, int)], FILE); \
756 break;
758 /* Round X up to the nearest word. */
759 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
761 /* Convert fron bytes to ints. */
762 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
764 /* The number of (integer) registers required to hold a quantity of type MODE.
765 Also used for VFP registers. */
766 #define ARM_NUM_REGS(MODE) \
767 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
769 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
770 #define ARM_NUM_REGS2(MODE, TYPE) \
771 ARM_NUM_INTS ((MODE) == BLKmode ? \
772 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
774 /* The number of (integer) argument register available. */
775 #define NUM_ARG_REGS 4
777 /* Return the register number of the N'th (integer) argument. */
778 #define ARG_REGISTER(N) (N - 1)
780 /* Specify the registers used for certain standard purposes.
781 The values of these macros are register numbers. */
783 /* The number of the last argument register. */
784 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
786 /* The numbers of the Thumb register ranges. */
787 #define FIRST_LO_REGNUM 0
788 #define LAST_LO_REGNUM 7
789 #define FIRST_HI_REGNUM 8
790 #define LAST_HI_REGNUM 11
792 #ifndef TARGET_UNWIND_INFO
793 /* We use sjlj exceptions for backwards compatibility. */
794 #define MUST_USE_SJLJ_EXCEPTIONS 1
795 #endif
797 /* We can generate DWARF2 Unwind info, even though we don't use it. */
798 #define DWARF2_UNWIND_INFO 1
800 /* Use r0 and r1 to pass exception handling information. */
801 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
803 /* The register that holds the return address in exception handlers. */
804 #define ARM_EH_STACKADJ_REGNUM 2
805 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
807 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
808 as an invisible last argument (possible since varargs don't exist in
809 Pascal), so the following is not true. */
810 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
812 /* Define this to be where the real frame pointer is if it is not possible to
813 work out the offset between the frame pointer and the automatic variables
814 until after register allocation has taken place. FRAME_POINTER_REGNUM
815 should point to a special register that we will make sure is eliminated.
817 For the Thumb we have another problem. The TPCS defines the frame pointer
818 as r11, and GCC believes that it is always possible to use the frame pointer
819 as base register for addressing purposes. (See comments in
820 find_reloads_address()). But - the Thumb does not allow high registers,
821 including r11, to be used as base address registers. Hence our problem.
823 The solution used here, and in the old thumb port is to use r7 instead of
824 r11 as the hard frame pointer and to have special code to generate
825 backtrace structures on the stack (if required to do so via a command line
826 option) using r11. This is the only 'user visible' use of r11 as a frame
827 pointer. */
828 #define ARM_HARD_FRAME_POINTER_REGNUM 11
829 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
831 #define HARD_FRAME_POINTER_REGNUM \
832 (TARGET_ARM \
833 ? ARM_HARD_FRAME_POINTER_REGNUM \
834 : THUMB_HARD_FRAME_POINTER_REGNUM)
836 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
838 /* Register to use for pushing function arguments. */
839 #define STACK_POINTER_REGNUM SP_REGNUM
841 /* ARM floating pointer registers. */
842 #define FIRST_FPA_REGNUM 16
843 #define LAST_FPA_REGNUM 23
844 #define IS_FPA_REGNUM(REGNUM) \
845 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
847 #define FIRST_IWMMXT_GR_REGNUM 43
848 #define LAST_IWMMXT_GR_REGNUM 46
849 #define FIRST_IWMMXT_REGNUM 47
850 #define LAST_IWMMXT_REGNUM 62
851 #define IS_IWMMXT_REGNUM(REGNUM) \
852 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
853 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
854 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
856 /* Base register for access to local variables of the function. */
857 #define FRAME_POINTER_REGNUM 25
859 /* Base register for access to arguments of the function. */
860 #define ARG_POINTER_REGNUM 26
862 #define FIRST_CIRRUS_FP_REGNUM 27
863 #define LAST_CIRRUS_FP_REGNUM 42
864 #define IS_CIRRUS_REGNUM(REGNUM) \
865 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
867 #define FIRST_VFP_REGNUM 63
868 #define LAST_VFP_REGNUM 94
869 #define IS_VFP_REGNUM(REGNUM) \
870 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
872 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
873 /* + 16 Cirrus registers take us up to 43. */
874 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
875 /* VFP adds 32 + 1 more. */
876 #define FIRST_PSEUDO_REGISTER 96
878 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
880 /* Value should be nonzero if functions must have frame pointers.
881 Zero means the frame pointer need not be set up (and parms may be accessed
882 via the stack pointer) in functions that seem suitable.
883 If we have to have a frame pointer we might as well make use of it.
884 APCS says that the frame pointer does not need to be pushed in leaf
885 functions, or simple tail call functions. */
887 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
888 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
889 #endif
891 #define FRAME_POINTER_REQUIRED \
892 (current_function_has_nonlocal_label \
893 || SUBTARGET_FRAME_POINTER_REQUIRED \
894 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
896 /* Return number of consecutive hard regs needed starting at reg REGNO
897 to hold something of mode MODE.
898 This is ordinarily the length in words of a value of mode MODE
899 but can be less for certain modes in special long registers.
901 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
902 mode. */
903 #define HARD_REGNO_NREGS(REGNO, MODE) \
904 ((TARGET_ARM \
905 && REGNO >= FIRST_FPA_REGNUM \
906 && REGNO != FRAME_POINTER_REGNUM \
907 && REGNO != ARG_POINTER_REGNUM) \
908 && !IS_VFP_REGNUM (REGNO) \
909 ? 1 : ARM_NUM_REGS (MODE))
911 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
912 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
913 arm_hard_regno_mode_ok ((REGNO), (MODE))
915 /* Value is 1 if it is a good idea to tie two pseudo registers
916 when one has mode MODE1 and one has mode MODE2.
917 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
918 for any hard reg, then this must be 0 for correct output. */
919 #define MODES_TIEABLE_P(MODE1, MODE2) \
920 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
922 #define VALID_IWMMXT_REG_MODE(MODE) \
923 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
925 /* The order in which register should be allocated. It is good to use ip
926 since no saving is required (though calls clobber it) and it never contains
927 function parameters. It is quite good to use lr since other calls may
928 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
929 least likely to contain a function parameter; in addition results are
930 returned in r0. */
932 #define REG_ALLOC_ORDER \
933 { \
934 3, 2, 1, 0, 12, 14, 4, 5, \
935 6, 7, 8, 10, 9, 11, 13, 15, \
936 16, 17, 18, 19, 20, 21, 22, 23, \
937 27, 28, 29, 30, 31, 32, 33, 34, \
938 35, 36, 37, 38, 39, 40, 41, 42, \
939 43, 44, 45, 46, 47, 48, 49, 50, \
940 51, 52, 53, 54, 55, 56, 57, 58, \
941 59, 60, 61, 62, \
942 24, 25, 26, \
943 78, 77, 76, 75, 74, 73, 72, 71, \
944 70, 69, 68, 67, 66, 65, 64, 63, \
945 79, 80, 81, 82, 83, 84, 85, 86, \
946 87, 88, 89, 90, 91, 92, 93, 94, \
947 95 \
948 }
950 /* Interrupt functions can only use registers that have already been
951 saved by the prologue, even if they would normally be
952 call-clobbered. */
953 #define HARD_REGNO_RENAME_OK(SRC, DST) \
954 (! IS_INTERRUPT (cfun->machine->func_type) || \
955 regs_ever_live[DST])
956 \f
957 /* Register and constant classes. */
959 /* Register classes: used to be simple, just all ARM regs or all FPA regs
960 Now that the Thumb is involved it has become more complicated. */
961 enum reg_class
962 {
963 NO_REGS,
964 FPA_REGS,
965 CIRRUS_REGS,
966 VFP_REGS,
967 IWMMXT_GR_REGS,
968 IWMMXT_REGS,
969 LO_REGS,
970 STACK_REG,
971 BASE_REGS,
972 HI_REGS,
973 CC_REG,
974 VFPCC_REG,
975 GENERAL_REGS,
976 ALL_REGS,
977 LIM_REG_CLASSES
978 };
980 #define N_REG_CLASSES (int) LIM_REG_CLASSES
982 /* Give names of register classes as strings for dump file. */
983 #define REG_CLASS_NAMES \
984 { \
999 }
1001 /* Define which registers fit in which classes.
1002 This is an initializer for a vector of HARD_REG_SET
1003 of length N_REG_CLASSES. */
1004 #define REG_CLASS_CONTENTS \
1005 { \
1020 }
1022 /* The same information, inverted:
1023 Return the class number of the smallest class containing
1024 reg number REGNO. This could be a conditional expression
1025 or could index an array. */
1026 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1028 /* FPA registers can't do subreg as all values are reformatted to internal
1029 precision. VFP registers may only be accessed in the mode they
1030 were set. */
1031 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1032 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1033 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1034 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1035 : 0)
1037 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1038 using r0-r4 for function arguments, r7 for the stack frame and don't
1039 have enough left over to do doubleword arithmetic. */
1040 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1041 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1042 || (CLASS) == CC_REG)
1044 /* The class value for index registers, and the one for base regs. */
1045 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1046 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1048 /* For the Thumb the high registers cannot be used as base registers
1049 when addressing quantities in QI or HI mode; if we don't know the
1050 mode, then we must be conservative. */
1051 #define MODE_BASE_REG_CLASS(MODE) \
1052 (TARGET_ARM ? GENERAL_REGS : \
1053 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1055 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1056 instead of BASE_REGS. */
1057 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1059 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1060 registers explicitly used in the rtl to be used as spill registers
1061 but prevents the compiler from extending the lifetime of these
1062 registers. */
1063 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1065 /* Given an rtx X being reloaded into a reg required to be
1066 in class CLASS, return the class of reg to actually use.
1067 In general this is just CLASS, but for the Thumb we prefer
1068 a LO_REGS class or a subset. */
1069 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1070 (TARGET_ARM ? (CLASS) : \
1071 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1073 /* Must leave BASE_REGS reloads alone */
1074 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1075 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1076 ? ((true_regnum (X) == -1 ? LO_REGS \
1077 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1078 : NO_REGS)) \
1079 : NO_REGS)
1081 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1082 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1083 ? ((true_regnum (X) == -1 ? LO_REGS \
1084 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1085 : NO_REGS)) \
1086 : NO_REGS)
1088 /* Return the register class of a scratch register needed to copy IN into
1089 or out of a register in CLASS in MODE. If it can be done directly,
1090 NO_REGS is returned. */
1091 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1093 ((TARGET_VFP && TARGET_HARD_FLOAT \
1094 && (CLASS) == VFP_REGS) \
1095 ? vfp_secondary_reload_class (MODE, X) \
1096 : TARGET_ARM \
1097 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1098 ? GENERAL_REGS : NO_REGS) \
1099 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1101 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1102 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1104 ((TARGET_VFP && TARGET_HARD_FLOAT \
1105 && (CLASS) == VFP_REGS) \
1106 ? vfp_secondary_reload_class (MODE, X) : \
1108 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1109 && (CLASS) == CIRRUS_REGS \
1110 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1111 ? GENERAL_REGS : \
1112 (TARGET_ARM ? \
1113 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1114 && CONSTANT_P (X)) \
1115 ? GENERAL_REGS : \
1116 (((MODE) == HImode && ! arm_arch4 \
1117 && (GET_CODE (X) == MEM \
1118 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1119 && true_regnum (X) == -1))) \
1120 ? GENERAL_REGS : NO_REGS) \
1121 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1123 /* Try a machine-dependent way of reloading an illegitimate address
1124 operand. If we find one, push the reload and jump to WIN. This
1125 macro is used in only one place: `find_reloads_address' in reload.c.
1127 For the ARM, we wish to handle large displacements off a base
1128 register by splitting the addend across a MOV and the mem insn.
1129 This can cut the number of reloads needed. */
1130 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1131 do \
1132 { \
1133 if (GET_CODE (X) == PLUS \
1134 && GET_CODE (XEXP (X, 0)) == REG \
1135 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1136 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1137 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1138 { \
1139 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1140 HOST_WIDE_INT low, high; \
1141 \
1142 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1143 low = ((val & 0xf) ^ 0x8) - 0x8; \
1144 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1146 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1147 else if (MODE == SImode \
1148 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1149 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1151 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1152 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1154 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1155 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1156 && TARGET_HARD_FLOAT && TARGET_FPA) \
1158 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1159 else \
1160 break; \
1161 \
1162 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1163 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1164 - (unsigned HOST_WIDE_INT) 0x80000000); \
1166 if (low == 0 || high == 0 || (high + low != val)) \
1167 break; \
1168 \
1169 /* Reload the high part into a base reg; leave the low part \
1171 X = gen_rtx_PLUS (GET_MODE (X), \
1172 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1173 GEN_INT (high)), \
1174 GEN_INT (low)); \
1175 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1176 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1177 VOIDmode, 0, 0, OPNUM, TYPE); \
1178 goto WIN; \
1179 } \
1180 } \
1181 while (0)
1183 /* XXX If an HImode FP+large_offset address is converted to an HImode
1184 SP+large_offset address, then reload won't know how to fix it. It sees
1185 only that SP isn't valid for HImode, and so reloads the SP into an index
1186 register, but the resulting address is still invalid because the offset
1187 is too big. We fix it here instead by reloading the entire address. */
1188 /* We could probably achieve better results by defining PROMOTE_MODE to help
1189 cope with the variances between the Thumb's signed and unsigned byte and
1190 halfword load instructions. */
1191 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1192 do { \
1193 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1194 if (new_x) \
1195 { \
1196 X = new_x; \
1197 goto WIN; \
1198 } \
1199 } while (0)
1201 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1202 if (TARGET_ARM) \
1203 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1204 else \
1205 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1207 /* Return the maximum number of consecutive registers
1208 needed to represent mode MODE in a register of class CLASS.
1209 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1210 #define CLASS_MAX_NREGS(CLASS, MODE) \
1211 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1213 /* If defined, gives a class of registers that cannot be used as the
1214 operand of a SUBREG that changes the mode of the object illegally. */
1216 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1217 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1218 (TARGET_ARM ? \
1219 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1220 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1221 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1222 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
1223 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1224 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1225 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1226 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1227 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1228 2) \
1229 : \
1230 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1231 \f
1232 /* Stack layout; function entry, exit and calling. */
1234 /* Define this if pushing a word on the stack
1235 makes the stack pointer a smaller address. */
1236 #define STACK_GROWS_DOWNWARD 1
1238 /* Define this to nonzero if the nominal address of the stack frame
1239 is at the high-address end of the local variables;
1240 that is, each additional local variable allocated
1241 goes at a more negative offset in the frame. */
1242 #define FRAME_GROWS_DOWNWARD 1
1244 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1245 When present, it is one word in size, and sits at the top of the frame,
1246 between the soft frame pointer and either r7 or r11.
1248 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1249 and only then if some outgoing arguments are passed on the stack. It would
1250 be tempting to also check whether the stack arguments are passed by indirect
1251 calls, but there seems to be no reason in principle why a post-reload pass
1252 couldn't convert a direct call into an indirect one. */
1253 #define CALLER_INTERWORKING_SLOT_SIZE \
1254 (TARGET_CALLER_INTERWORKING \
1255 && current_function_outgoing_args_size != 0 \
1256 ? UNITS_PER_WORD : 0)
1258 /* Offset within stack frame to start allocating local variables at.
1259 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1260 first local allocated. Otherwise, it is the offset to the BEGINNING
1261 of the first local allocated. */
1262 #define STARTING_FRAME_OFFSET 0
1264 /* If we generate an insn to push BYTES bytes,
1265 this says how many the stack pointer really advances by. */
1266 /* The push insns do not do this rounding implicitly.
1267 So don't define this. */
1268 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1270 /* Define this if the maximum size of all the outgoing args is to be
1271 accumulated and pushed during the prologue. The amount can be
1272 found in the variable current_function_outgoing_args_size. */
1273 #define ACCUMULATE_OUTGOING_ARGS 1
1275 /* Offset of first parameter from the argument pointer register value. */
1276 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1278 /* Value is the number of byte of arguments automatically
1279 popped when returning from a subroutine call.
1280 FUNDECL is the declaration node of the function (as a tree),
1281 FUNTYPE is the data type of the function (as a tree),
1282 or for a library call it is an identifier node for the subroutine name.
1283 SIZE is the number of bytes of arguments passed on the stack.
1285 On the ARM, the caller does not pop any of its arguments that were passed
1286 on the stack. */
1287 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1289 /* Define how to find the value returned by a library function
1290 assuming the value has mode MODE. */
1291 #define LIBCALL_VALUE(MODE) \
1292 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1293 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1294 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1295 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1296 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1297 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1298 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1299 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1300 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1302 /* Define how to find the value returned by a function.
1303 VALTYPE is the data type of the value (as a tree).
1304 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1305 otherwise, FUNC is 0. */
1306 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1307 arm_function_value (VALTYPE, FUNC);
1309 /* 1 if N is a possible register number for a function value.
1310 On the ARM, only r0 and f0 can return results. */
1311 /* On a Cirrus chip, mvf0 can return results. */
1312 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1313 ((REGNO) == ARG_REGISTER (1) \
1314 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1315 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1316 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1317 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
1318 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1320 /* Amount of memory needed for an untyped call to save all possible return
1321 registers. */
1322 #define APPLY_RESULT_SIZE arm_apply_result_size()
1324 /* How large values are returned */
1325 /* A C expression which can inhibit the returning of certain function values
1326 in registers, based on the type of value. */
1327 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1329 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1330 values must be in memory. On the ARM, they need only do so if larger
1331 than a word, or if they contain elements offset from zero in the struct. */
1332 #define DEFAULT_PCC_STRUCT_RETURN 0
1334 /* Flags for the call/call_value rtl operations set up by function_arg. */
1339 /* These bits describe the different types of function supported
1340 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1341 normal function and an interworked function, for example. Knowing the
1342 type of a function is important for determining its prologue and
1343 epilogue sequences.
1344 Note value 7 is currently unassigned. Also note that the interrupt
1345 function types all have bit 2 set, so that they can be tested for easily.
1346 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1347 machine_function structure is initialized (to zero) func_type will
1348 default to unknown. This will force the first use of arm_current_func_type
1349 to call arm_compute_func_type. */
1357 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1359 /* In addition functions can have several type modifiers,
1360 outlined by these bit masks: */
1366 /* Some macros to test these flags. */
1367 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1368 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1369 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1370 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1371 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1374 /* Structure used to hold the function stack frame layout. Offsets are
1375 relative to the stack pointer on function entry. Positive offsets are
1376 in the direction of stack growth.
1377 Only soft_frame is used in thumb mode. */
1380 {
1387 }
1388 arm_stack_offsets;
1390 /* A C structure for machine-specific, per-function data.
1391 This is added to the cfun structure. */
1393 {
1394 /* Additional stack adjustment in __builtin_eh_throw. */
1395 rtx eh_epilogue_sp_ofs;
1396 /* Records if LR has to be saved for far jumps. */
1398 /* Records if ARG_POINTER was ever live. */
1400 /* Records if the save of LR has been eliminated. */
1402 /* The size of the stack frame. Only valid after reload. */
1403 arm_stack_offsets stack_offsets;
1404 /* Records the type of the current function. */
1406 /* Record if the function has a variable argument list. */
1408 /* Records if sibcalls are blocked because an argument
1409 register is needed to preserve stack alignment. */
1411 /* The PIC register for this function. This might be a pseudo. */
1412 rtx pic_reg;
1413 /* Labels for per-function Thumb call-via stubs. One per potential calling
1414 register. We can never call via LR or PC. We can call via SP if a
1415 trampoline happens to be on the top of the stack. */
1417 }
1418 machine_function;
1420 /* As in the machine_function, a global set of call-via labels, for code
1421 that is in text_section. */
1424 /* A C type for declaring a variable that is used as the first argument of
1425 `FUNCTION_ARG' and other related values. For some target machines, the
1426 type `int' suffices and can hold the number of bytes of argument so far. */
1428 {
1429 /* This is the number of registers of arguments scanned so far. */
1431 /* This is the number of iWMMXt register arguments scanned so far. */
1435 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1440 /* Define where to put the arguments to a function.
1441 Value is zero to push the argument on the stack,
1442 or a hard register in which to store the argument.
1444 MODE is the argument's machine mode.
1445 TYPE is the data type of the argument (as a tree).
1446 This is null for libcalls where that information may
1447 not be available.
1448 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1449 the preceding args and about the function being called.
1450 NAMED is nonzero if this argument is a named parameter
1451 (otherwise it is an extra parameter matching an ellipsis).
1453 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1454 other arguments are passed on the stack. If (NAMED == 0) (which happens
1455 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1456 defined), say it is passed in the stack (function_prologue will
1457 indeed make it pass in the stack if necessary). */
1458 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1459 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1461 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1462 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1464 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1465 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1467 /* For AAPCS, padding should never be below the argument. For other ABIs,
1468 * mimic the default. */
1469 #define PAD_VARARGS_DOWN \
1470 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1472 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1473 for a call to a function whose data type is FNTYPE.
1474 For a library call, FNTYPE is 0.
1475 On the ARM, the offset starts at 0. */
1476 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1477 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1479 /* Update the data in CUM to advance over an argument
1480 of mode MODE and data type TYPE.
1481 (TYPE is null for libcalls where that information may not be available.) */
1482 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1483 (CUM).nargs += 1; \
1484 if (arm_vector_mode_supported_p (MODE) \
1485 && (CUM).named_count > (CUM).nargs \
1486 && TARGET_IWMMXT_ABI) \
1487 (CUM).iwmmxt_nregs += 1; \
1488 else \
1489 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1491 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1492 argument with the specified mode and type. If it is not defined,
1493 `PARM_BOUNDARY' is used for all arguments. */
1494 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1495 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1496 ? DOUBLEWORD_ALIGNMENT \
1497 : PARM_BOUNDARY )
1499 /* 1 if N is a possible register number for function argument passing.
1500 On the ARM, r0-r3 are used to pass args. */
1501 #define FUNCTION_ARG_REGNO_P(REGNO) \
1502 (IN_RANGE ((REGNO), 0, 3) \
1503 || (TARGET_IWMMXT_ABI \
1504 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1506 \f
1507 /* If your target environment doesn't prefix user functions with an
1508 underscore, you may wish to re-define this to prevent any conflicts.
1509 e.g. AOF may prefix mcount with an underscore. */
1510 #ifndef ARM_MCOUNT_NAME
1512 #endif
1514 /* Call the function profiler with a given profile label. The Acorn
1515 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1516 On the ARM the full profile code will look like:
1517 .data
1518 LP1
1519 .word 0
1520 .text
1521 mov ip, lr
1522 bl mcount
1523 .word LP1
1525 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1526 will output the .text section.
1528 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1529 ``prof'' doesn't seem to mind about this!
1531 Note - this version of the code is designed to work in both ARM and
1532 Thumb modes. */
1533 #ifndef ARM_FUNCTION_PROFILER
1534 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1535 { \
1536 char temp[20]; \
1537 rtx sym; \
1538 \
1540 IP_REGNUM, LR_REGNUM); \
1541 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1544 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1545 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1546 }
1547 #endif
1549 #ifdef THUMB_FUNCTION_PROFILER
1550 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1551 if (TARGET_ARM) \
1552 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1553 else \
1554 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1555 #else
1556 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1557 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1558 #endif
1560 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1561 the stack pointer does not matter. The value is tested only in
1562 functions that have frame pointers.
1563 No definition is equivalent to always zero.
1565 On the ARM, the function epilogue recovers the stack pointer from the
1566 frame. */
1567 #define EXIT_IGNORE_STACK 1
1569 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1571 /* Determine if the epilogue should be output as RTL.
1572 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1573 #define USE_RETURN_INSN(ISCOND) \
1574 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1576 /* Definitions for register eliminations.
1578 This is an array of structures. Each structure initializes one pair
1579 of eliminable registers. The "from" register number is given first,
1580 followed by "to". Eliminations of the same "from" register are listed
1581 in order of preference.
1583 We have two registers that can be eliminated on the ARM. First, the
1584 arg pointer register can often be eliminated in favor of the stack
1585 pointer register. Secondly, the pseudo frame pointer register can always
1586 be eliminated; it is replaced with either the stack or the real frame
1587 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1588 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1590 #define ELIMINABLE_REGS \
1591 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1592 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1593 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1594 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1595 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1596 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1597 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1599 /* Given FROM and TO register numbers, say whether this elimination is
1600 allowed. Frame pointer elimination is automatically handled.
1602 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1603 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1604 pointer, we must eliminate FRAME_POINTER_REGNUM into
1605 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1606 ARG_POINTER_REGNUM. */
1607 #define CAN_ELIMINATE(FROM, TO) \
1608 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1609 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1610 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1611 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1612 1)
1614 /* Define the offset between two registers, one to be eliminated, and the
1615 other its replacement, at the start of a routine. */
1616 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1617 if (TARGET_ARM) \
1618 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1619 else \
1620 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1622 /* Special case handling of the location of arguments passed on the stack. */
1623 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1625 /* Initialize data used by insn expanders. This is called from insn_emit,
1626 once for every function before code is generated. */
1627 #define INIT_EXPANDERS arm_init_expanders ()
1629 /* Output assembler code for a block containing the constant parts
1630 of a trampoline, leaving space for the variable parts.
1632 On the ARM, (if r8 is the static chain regnum, and remembering that
1633 referencing pc adds an offset of 8) the trampoline looks like:
1634 ldr r8, [pc, #0]
1635 ldr pc, [pc]
1636 .word static chain value
1637 .word function's address
1638 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1639 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1640 { \
1642 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1644 PC_REGNUM, PC_REGNUM); \
1645 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1646 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1647 }
1649 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1650 Why - because it is easier. This code will always be branched to via
1651 a BX instruction and since the compiler magically generates the address
1652 of the function the linker has no opportunity to ensure that the
1653 bottom bit is set. Thus the processor will be in ARM mode when it
1654 reaches this code. So we duplicate the ARM trampoline code and add
1655 a switch into Thumb mode as well. */
1656 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1657 { \
1661 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1663 IP_REGNUM, PC_REGNUM); \
1665 IP_REGNUM, IP_REGNUM); \
1670 }
1672 #define TRAMPOLINE_TEMPLATE(FILE) \
1673 if (TARGET_ARM) \
1674 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1675 else \
1676 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1678 /* Length in units of the trampoline for entering a nested function. */
1679 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1681 /* Alignment required for a trampoline in bits. */
1682 #define TRAMPOLINE_ALIGNMENT 32
1685 /* Emit RTL insns to initialize the variable parts of a trampoline.
1686 FNADDR is an RTX for the address of the function's pure code.
1687 CXT is an RTX for the static chain value for the function. */
1688 #ifndef INITIALIZE_TRAMPOLINE
1689 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1690 { \
1691 emit_move_insn (gen_rtx_MEM (SImode, \
1692 plus_constant (TRAMP, \
1693 TARGET_ARM ? 8 : 16)), \
1694 CXT); \
1695 emit_move_insn (gen_rtx_MEM (SImode, \
1696 plus_constant (TRAMP, \
1697 TARGET_ARM ? 12 : 20)), \
1698 FNADDR); \
1700 0, VOIDmode, 2, TRAMP, Pmode, \
1701 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1702 }
1703 #endif
1705 \f
1706 /* Addressing modes, and classification of registers for them. */
1707 #define HAVE_POST_INCREMENT 1
1708 #define HAVE_PRE_INCREMENT TARGET_ARM
1709 #define HAVE_POST_DECREMENT TARGET_ARM
1710 #define HAVE_PRE_DECREMENT TARGET_ARM
1711 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1712 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1713 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1714 #define HAVE_POST_MODIFY_REG TARGET_ARM
1716 /* Macros to check register numbers against specific register classes. */
1718 /* These assume that REGNO is a hard or pseudo reg number.
1719 They give nonzero only if REGNO is a hard reg of the suitable class
1720 or a pseudo reg currently allocated to a suitable hard reg.
1721 Since they use reg_renumber, they are safe only once reg_renumber
1722 has been allocated, which happens in local-alloc.c. */
1723 #define TEST_REGNO(R, TEST, VALUE) \
1724 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1726 /* On the ARM, don't allow the pc to be used. */
1727 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1728 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1729 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1730 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1732 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1733 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1734 || (GET_MODE_SIZE (MODE) >= 4 \
1735 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1737 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1738 (TARGET_THUMB \
1739 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1740 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1742 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1743 For Thumb, we can not use SP + reg, so reject SP. */
1744 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1745 REGNO_OK_FOR_INDEX_P (X)
1747 /* For ARM code, we don't care about the mode, but for Thumb, the index
1748 must be suitable for use in a QImode load. */
1749 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1750 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1752 /* Maximum number of registers that can appear in a valid memory address.
1753 Shifts in addresses can't be by a register. */
1754 #define MAX_REGS_PER_ADDRESS 2
1756 /* Recognize any constant value that is a valid address. */
1757 /* XXX We can address any constant, eventually... */
1759 #ifdef AOF_ASSEMBLER
1761 #define CONSTANT_ADDRESS_P(X) \
1762 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1764 #else
1766 #define CONSTANT_ADDRESS_P(X) \
1767 (GET_CODE (X) == SYMBOL_REF \
1768 && (CONSTANT_POOL_ADDRESS_P (X) \
1769 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1773 /* Nonzero if the constant value X is a legitimate general operand.
1774 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1776 On the ARM, allow any integer (invalid ones are removed later by insn
1777 patterns), nice doubles and symbol_refs which refer to the function's
1778 constant pool XXX.
1780 When generating pic allow anything. */
1781 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1783 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1784 ( GET_CODE (X) == CONST_INT \
1785 || GET_CODE (X) == CONST_DOUBLE \
1786 || CONSTANT_ADDRESS_P (X) \
1787 || flag_pic)
1789 #define LEGITIMATE_CONSTANT_P(X) \
1790 (!arm_tls_referenced_p (X) \
1791 && (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) \
1792 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1794 /* Special characters prefixed to function names
1795 in order to encode attribute like information.
1796 Note, '@' and '*' have already been taken. */
1800 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1801 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1803 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1804 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1806 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1807 #define SUBTARGET_NAME_ENCODING_LENGTHS
1808 #endif
1810 /* This is a C fragment for the inside of a switch statement.
1811 Each case label should return the number of characters to
1812 be stripped from the start of a function's name, if that
1813 name starts with the indicated character. */
1814 #define ARM_NAME_ENCODING_LENGTHS \
1815 case SHORT_CALL_FLAG_CHAR: return 1; \
1816 case LONG_CALL_FLAG_CHAR: return 1; \
1818 SUBTARGET_NAME_ENCODING_LENGTHS
1820 /* This is how to output a reference to a user-level label named NAME.
1821 `assemble_name' uses this. */
1822 #undef ASM_OUTPUT_LABELREF
1823 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1824 arm_asm_output_labelref (FILE, NAME)
1826 /* The EABI specifies that constructors should go in .init_array.
1827 Other targets use .ctors for compatibility. */
1828 #ifndef ARM_EABI_CTORS_SECTION_OP
1829 #define ARM_EABI_CTORS_SECTION_OP \
1831 #endif
1832 #ifndef ARM_EABI_DTORS_SECTION_OP
1833 #define ARM_EABI_DTORS_SECTION_OP \
1835 #endif
1836 #define ARM_CTORS_SECTION_OP \
1838 #define ARM_DTORS_SECTION_OP \
1841 /* Define CTORS_SECTION_ASM_OP. */
1842 #undef CTORS_SECTION_ASM_OP
1843 #undef DTORS_SECTION_ASM_OP
1844 #ifndef IN_LIBGCC2
1845 # define CTORS_SECTION_ASM_OP \
1846 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1847 # define DTORS_SECTION_ASM_OP \
1848 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1850 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1851 so we cannot use the definition above. */
1852 # ifdef __ARM_EABI__
1853 /* The .ctors section is not part of the EABI, so we do not define
1854 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1855 from trying to use it. We do define it when doing normal
1856 compilation, as .init_array can be used instead of .ctors. */
1857 /* There is no need to emit begin or end markers when using
1858 init_array; the dynamic linker will compute the size of the
1859 array itself based on special symbols created by the static
1860 linker. However, we do need to arrange to set up
1861 exception-handling here. */
1862 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1864 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1867 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1868 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1872 /* True if the operating system can merge entities with vague linkage
1873 (e.g., symbols in COMDAT group) during dynamic linking. */
1874 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1875 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1876 #endif
1878 /* Set the short-call flag for any function compiled in the current
1879 compilation unit. We skip this for functions with the section
1880 attribute when long-calls are in effect as this tells the compiler
1881 that the section might be placed a long way from the caller.
1882 See arm_is_longcall_p() for more information. */
1883 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1884 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1885 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1887 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1889 #ifdef TARGET_UNWIND_INFO
1890 #define ARM_EABI_UNWIND_TABLES \
1891 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1892 #else
1893 #define ARM_EABI_UNWIND_TABLES 0
1894 #endif
1896 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1897 and check its validity for a certain class.
1898 We have two alternate definitions for each of them.
1899 The usual definition accepts all pseudo regs; the other rejects
1900 them unless they have been allocated suitable hard regs.
1901 The symbol REG_OK_STRICT causes the latter definition to be used. */
1902 #ifndef REG_OK_STRICT
1904 #define ARM_REG_OK_FOR_BASE_P(X) \
1905 (REGNO (X) <= LAST_ARM_REGNUM \
1906 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1907 || REGNO (X) == FRAME_POINTER_REGNUM \
1908 || REGNO (X) == ARG_POINTER_REGNUM)
1910 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1911 (REGNO (X) <= LAST_LO_REGNUM \
1912 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1913 || (GET_MODE_SIZE (MODE) >= 4 \
1914 && (REGNO (X) == STACK_POINTER_REGNUM \
1915 || (X) == hard_frame_pointer_rtx \
1916 || (X) == arg_pointer_rtx)))
1918 #define REG_STRICT_P 0
1922 #define ARM_REG_OK_FOR_BASE_P(X) \
1923 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1925 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1926 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1928 #define REG_STRICT_P 1
1932 /* Now define some helpers in terms of the above. */
1934 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1935 (TARGET_THUMB \
1936 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1937 : ARM_REG_OK_FOR_BASE_P (X))
1939 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1941 /* For Thumb, a valid index register is anything that can be used in
1942 a byte load instruction. */
1943 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1945 /* Nonzero if X is a hard reg that can be used as an index
1946 or if it is a pseudo reg. On the Thumb, the stack pointer
1947 is not suitable. */
1948 #define REG_OK_FOR_INDEX_P(X) \
1949 (TARGET_THUMB \
1950 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1951 : ARM_REG_OK_FOR_INDEX_P (X))
1953 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1954 For Thumb, we can not use SP + reg, so reject SP. */
1955 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1956 REG_OK_FOR_INDEX_P (X)
1957 \f
1958 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1959 that is a valid memory address for an instruction.
1960 The MODE argument is the machine mode for the MEM expression
1961 that wants to use this address. */
1963 #define ARM_BASE_REGISTER_RTX_P(X) \
1964 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1966 #define ARM_INDEX_REGISTER_RTX_P(X) \
1967 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1969 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
1970 { \
1971 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
1972 goto WIN; \
1973 }
1975 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
1976 { \
1977 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
1978 goto WIN; \
1979 }
1981 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1982 if (TARGET_ARM) \
1983 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
1985 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
1987 \f
1988 /* Try machine-dependent ways of modifying an illegitimate address
1989 to be legitimate. If we find one, return the new, valid address. */
1990 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1991 do { \
1992 X = arm_legitimize_address (X, OLDX, MODE); \
1993 } while (0)
1995 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1996 do { \
1997 X = thumb_legitimize_address (X, OLDX, MODE); \
1998 } while (0)
2000 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2001 do { \
2002 if (TARGET_ARM) \
2003 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2004 else \
2005 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2006 \
2007 if (memory_address_p (MODE, X)) \
2008 goto WIN; \
2009 } while (0)
2011 /* Go to LABEL if ADDR (a legitimate address expression)
2012 has an effect that depends on the machine mode it is used for. */
2013 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2014 { \
2015 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2016 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2017 goto LABEL; \
2018 }
2020 /* Nothing helpful to do for the Thumb */
2021 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2022 if (TARGET_ARM) \
2023 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2024 \f
2026 /* Specify the machine mode that this machine uses
2027 for the index in the tablejump instruction. */
2028 #define CASE_VECTOR_MODE Pmode
2030 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2031 unsigned is probably best, but may break some code. */
2032 #ifndef DEFAULT_SIGNED_CHAR
2033 #define DEFAULT_SIGNED_CHAR 0
2034 #endif
2036 /* Max number of bytes we can move from memory to memory
2037 in one reasonably fast instruction. */
2038 #define MOVE_MAX 4
2040 #undef MOVE_RATIO
2041 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2043 /* Define if operations between registers always perform the operation
2044 on the full register even if a narrower mode is specified. */
2045 #define WORD_REGISTER_OPERATIONS
2047 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2048 will either zero-extend or sign-extend. The value of this macro should
2049 be the code that says which one of the two operations is implicitly
2050 done, UNKNOWN if none. */
2051 #define LOAD_EXTEND_OP(MODE) \
2052 (TARGET_THUMB ? ZERO_EXTEND : \
2053 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2054 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2056 /* Nonzero if access to memory by bytes is slow and undesirable. */
2057 #define SLOW_BYTE_ACCESS 0
2059 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2061 /* Immediate shift counts are truncated by the output routines (or was it
2062 the assembler?). Shift counts in a register are truncated by ARM. Note
2063 that the native compiler puts too large (> 32) immediate shift counts
2064 into a register and shifts by the register, letting the ARM decide what
2065 to do instead of doing that itself. */
2066 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2067 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2068 On the arm, Y in a register is used modulo 256 for the shift. Only for
2069 rotates is modulo 32 used. */
2070 /* #define SHIFT_COUNT_TRUNCATED 1 */
2072 /* All integers have the same format so truncation is easy. */
2073 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2075 /* Calling from registers is a massive pain. */
2076 #define NO_FUNCTION_CSE 1
2078 /* The machine modes of pointers and functions */
2079 #define Pmode SImode
2080 #define FUNCTION_MODE Pmode
2082 #define ARM_FRAME_RTX(X) \
2083 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2084 || (X) == arg_pointer_rtx)
2086 /* Moves to and from memory are quite expensive */
2087 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2088 (TARGET_ARM ? 10 : \
2089 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2090 * (CLASS == LO_REGS ? 1 : 2)))
2092 /* Try to generate sequences that don't involve branches, we can then use
2093 conditional instructions */
2094 #define BRANCH_COST \
2095 (TARGET_ARM ? 4 : (optimize > 0 ? 2 : 0))
2096 \f
2097 /* Position Independent Code. */
2098 /* We decide which register to use based on the compilation options and
2099 the assembler in use; this is more general than the APCS restriction of
2100 using sb (r9) all the time. */
2103 /* The register number of the register used to address a table of static
2104 data addresses in memory. */
2105 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2107 /* We can't directly access anything that contains a symbol,
2108 nor can we indirect via the constant pool. One exception is
2109 UNSPEC_TLS, which is always PIC. */
2110 #define LEGITIMATE_PIC_OPERAND_P(X) \
2111 (!(symbol_mentioned_p (X) \
2112 || label_mentioned_p (X) \
2113 || (GET_CODE (X) == SYMBOL_REF \
2114 && CONSTANT_POOL_ADDRESS_P (X) \
2115 && (symbol_mentioned_p (get_pool_constant (X)) \
2116 || label_mentioned_p (get_pool_constant (X))))) \
2117 || tls_mentioned_p (X))
2119 /* We need to know when we are making a constant pool; this determines
2120 whether data needs to be in the GOT or can be referenced via a GOT
2121 offset. */
2123 \f
2124 /* Handle pragmas for compatibility with Intel's compilers. */
2125 #define REGISTER_TARGET_PRAGMAS() do { \
2129 } while (0)
2131 /* Condition code information. */
2132 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2133 return the mode to be used for the comparison. */
2135 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2137 #define REVERSIBLE_CC_MODE(MODE) 1
2139 #define REVERSE_CONDITION(CODE,MODE) \
2140 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2141 ? reverse_condition_maybe_unordered (code) \
2142 : reverse_condition (code))
2144 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2145 do \
2146 { \
2147 if (GET_CODE (OP1) == CONST_INT \
2148 && ! (const_ok_for_arm (INTVAL (OP1)) \
2149 || (const_ok_for_arm (- INTVAL (OP1))))) \
2150 { \
2151 rtx const_op = OP1; \
2152 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2153 &const_op); \
2154 OP1 = const_op; \
2155 } \
2156 } \
2157 while (0)
2159 /* The arm5 clz instruction returns 32. */
2160 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2161 \f
2162 #undef ASM_APP_OFF
2165 /* Output a push or a pop instruction (only used when profiling). */
2166 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2167 do \
2168 { \
2169 if (TARGET_ARM) \
2171 STACK_POINTER_REGNUM, REGNO); \
2172 else \
2174 } while (0)
2177 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2178 do \
2179 { \
2180 if (TARGET_ARM) \
2182 STACK_POINTER_REGNUM, REGNO); \
2183 else \
2185 } while (0)
2187 /* This is how to output a label which precedes a jumptable. Since
2188 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2189 #undef ASM_OUTPUT_CASE_LABEL
2190 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2191 do \
2192 { \
2193 if (TARGET_THUMB) \
2194 ASM_OUTPUT_ALIGN (FILE, 2); \
2195 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2196 } \
2197 while (0)
2199 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2200 do \
2201 { \
2202 if (TARGET_THUMB) \
2203 { \
2204 if (is_called_in_ARM_mode (DECL) \
2205 || current_function_is_thunk) \
2207 else \
2209 } \
2210 if (TARGET_POKE_FUNCTION_NAME) \
2211 arm_poke_function_name (STREAM, (char *) NAME); \
2212 } \
2213 while (0)
2215 /* For aliases of functions we use .thumb_set instead. */
2216 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2217 do \
2218 { \
2219 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2220 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2221 \
2222 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2223 { \
2225 assemble_name (FILE, LABEL1); \
2227 assemble_name (FILE, LABEL2); \
2229 } \
2230 else \
2231 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2232 } \
2233 while (0)
2235 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2236 /* To support -falign-* switches we need to use .p2align so
2237 that alignment directives in code sections will be padded
2238 with no-op instructions, rather than zeroes. */
2239 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2240 if ((LOG) != 0) \
2241 { \
2242 if ((MAX_SKIP) == 0) \
2244 else \
2246 (int) (LOG), (int) (MAX_SKIP)); \
2247 }
2248 #endif
2249 \f
2250 /* Only perform branch elimination (by making instructions conditional) if
2251 we're optimizing. Otherwise it's of no use anyway. */
2252 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2253 if (TARGET_ARM && optimize) \
2254 arm_final_prescan_insn (INSN); \
2255 else if (TARGET_THUMB) \
2256 thumb_final_prescan_insn (INSN)
2258 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2263 /* Output an operand of an instruction. */
2264 #define PRINT_OPERAND(STREAM, X, CODE) \
2265 arm_print_operand (STREAM, X, CODE)
2267 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2268 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2269 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2270 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2271 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2272 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2273 : 0))))
2275 /* Output the address of an operand. */
2276 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2277 { \
2278 int is_minus = GET_CODE (X) == MINUS; \
2279 \
2280 if (GET_CODE (X) == REG) \
2282 else if (GET_CODE (X) == PLUS || is_minus) \
2283 { \
2284 rtx base = XEXP (X, 0); \
2285 rtx index = XEXP (X, 1); \
2286 HOST_WIDE_INT offset = 0; \
2287 if (GET_CODE (base) != REG) \
2288 { \
2291 rtx temp = base; \
2292 base = index; \
2293 index = temp; \
2294 } \
2295 switch (GET_CODE (index)) \
2296 { \
2297 case CONST_INT: \
2298 offset = INTVAL (index); \
2299 if (is_minus) \
2300 offset = -offset; \
2302 REGNO (base), offset); \
2303 break; \
2304 \
2305 case REG: \
2308 REGNO (index)); \
2309 break; \
2310 \
2311 case MULT: \
2312 case ASHIFTRT: \
2313 case LSHIFTRT: \
2314 case ASHIFT: \
2315 case ROTATERT: \
2316 { \
2319 REGNO (XEXP (index, 0))); \
2322 break; \
2323 } \
2324 \
2325 default: \
2326 gcc_unreachable (); \
2327 } \
2328 } \
2329 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2330 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2331 { \
2332 extern enum machine_mode output_memory_reference_mode; \
2333 \
2334 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2335 \
2336 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2338 REGNO (XEXP (X, 0)), \
2340 GET_MODE_SIZE (output_memory_reference_mode)); \
2341 else \
2343 REGNO (XEXP (X, 0)), \
2345 GET_MODE_SIZE (output_memory_reference_mode)); \
2346 } \
2347 else if (GET_CODE (X) == PRE_MODIFY) \
2348 { \
2350 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2352 INTVAL (XEXP (XEXP (X, 1), 1))); \
2353 else \
2355 REGNO (XEXP (XEXP (X, 1), 1))); \
2356 } \
2357 else if (GET_CODE (X) == POST_MODIFY) \
2358 { \
2360 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2362 INTVAL (XEXP (XEXP (X, 1), 1))); \
2363 else \
2365 REGNO (XEXP (XEXP (X, 1), 1))); \
2366 } \
2367 else output_addr_const (STREAM, X); \
2368 }
2370 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2371 { \
2372 if (GET_CODE (X) == REG) \
2374 else if (GET_CODE (X) == POST_INC) \
2376 else if (GET_CODE (X) == PLUS) \
2377 { \
2378 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2379 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2381 REGNO (XEXP (X, 0)), \
2382 INTVAL (XEXP (X, 1))); \
2383 else \
2385 REGNO (XEXP (X, 0)), \
2386 REGNO (XEXP (X, 1))); \
2387 } \
2388 else \
2389 output_addr_const (STREAM, X); \
2390 }
2392 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2393 if (TARGET_ARM) \
2394 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2395 else \
2396 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2398 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2399 if (arm_output_addr_const_extra (file, x) == FALSE) \
2400 goto fail
2402 /* A C expression whose value is RTL representing the value of the return
2403 address for the frame COUNT steps up from the current frame. */
2405 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2406 arm_return_addr (COUNT, FRAME)
2408 /* Mask of the bits in the PC that contain the real return address
2409 when running in 26-bit mode. */
2410 #define RETURN_ADDR_MASK26 (0x03fffffc)
2412 /* Pick up the return address upon entry to a procedure. Used for
2413 dwarf2 unwind information. This also enables the table driven
2414 mechanism. */
2415 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2416 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2418 /* Used to mask out junk bits from the return address, such as
2419 processor state, interrupt status, condition codes and the like. */
2420 #define MASK_RETURN_ADDR \
2421 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2422 in 26 bit mode, the condition codes must be masked out of the \
2423 return address. This does not apply to ARM6 and later processors \
2425 ((arm_arch4 || TARGET_THUMB) \
2426 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2427 : arm_gen_return_addr_mask ())
2429 \f
2430 enum arm_builtins
2431 {
2432 ARM_BUILTIN_GETWCX,
2433 ARM_BUILTIN_SETWCX,
2435 ARM_BUILTIN_WZERO,
2437 ARM_BUILTIN_WAVG2BR,
2438 ARM_BUILTIN_WAVG2HR,
2439 ARM_BUILTIN_WAVG2B,
2440 ARM_BUILTIN_WAVG2H,
2442 ARM_BUILTIN_WACCB,
2443 ARM_BUILTIN_WACCH,
2444 ARM_BUILTIN_WACCW,
2446 ARM_BUILTIN_WMACS,
2447 ARM_BUILTIN_WMACSZ,
2448 ARM_BUILTIN_WMACU,
2449 ARM_BUILTIN_WMACUZ,
2451 ARM_BUILTIN_WSADB,
2452 ARM_BUILTIN_WSADBZ,
2453 ARM_BUILTIN_WSADH,
2454 ARM_BUILTIN_WSADHZ,
2456 ARM_BUILTIN_WALIGN,
2458 ARM_BUILTIN_TMIA,
2459 ARM_BUILTIN_TMIAPH,
2460 ARM_BUILTIN_TMIABB,
2461 ARM_BUILTIN_TMIABT,
2462 ARM_BUILTIN_TMIATB,
2463 ARM_BUILTIN_TMIATT,
2465 ARM_BUILTIN_TMOVMSKB,
2466 ARM_BUILTIN_TMOVMSKH,
2467 ARM_BUILTIN_TMOVMSKW,
2469 ARM_BUILTIN_TBCSTB,
2470 ARM_BUILTIN_TBCSTH,
2471 ARM_BUILTIN_TBCSTW,
2473 ARM_BUILTIN_WMADDS,
2474 ARM_BUILTIN_WMADDU,
2476 ARM_BUILTIN_WPACKHSS,
2477 ARM_BUILTIN_WPACKWSS,
2478 ARM_BUILTIN_WPACKDSS,
2479 ARM_BUILTIN_WPACKHUS,
2480 ARM_BUILTIN_WPACKWUS,
2481 ARM_BUILTIN_WPACKDUS,
2483 ARM_BUILTIN_WADDB,
2484 ARM_BUILTIN_WADDH,
2485 ARM_BUILTIN_WADDW,
2486 ARM_BUILTIN_WADDSSB,
2487 ARM_BUILTIN_WADDSSH,
2488 ARM_BUILTIN_WADDSSW,
2489 ARM_BUILTIN_WADDUSB,
2490 ARM_BUILTIN_WADDUSH,
2491 ARM_BUILTIN_WADDUSW,
2492 ARM_BUILTIN_WSUBB,
2493 ARM_BUILTIN_WSUBH,
2494 ARM_BUILTIN_WSUBW,
2495 ARM_BUILTIN_WSUBSSB,
2496 ARM_BUILTIN_WSUBSSH,
2497 ARM_BUILTIN_WSUBSSW,
2498 ARM_BUILTIN_WSUBUSB,
2499 ARM_BUILTIN_WSUBUSH,
2500 ARM_BUILTIN_WSUBUSW,
2502 ARM_BUILTIN_WAND,
2503 ARM_BUILTIN_WANDN,
2504 ARM_BUILTIN_WOR,
2505 ARM_BUILTIN_WXOR,
2507 ARM_BUILTIN_WCMPEQB,
2508 ARM_BUILTIN_WCMPEQH,
2509 ARM_BUILTIN_WCMPEQW,
2510 ARM_BUILTIN_WCMPGTUB,
2511 ARM_BUILTIN_WCMPGTUH,
2512 ARM_BUILTIN_WCMPGTUW,
2513 ARM_BUILTIN_WCMPGTSB,
2514 ARM_BUILTIN_WCMPGTSH,
2515 ARM_BUILTIN_WCMPGTSW,
2517 ARM_BUILTIN_TEXTRMSB,
2518 ARM_BUILTIN_TEXTRMSH,
2519 ARM_BUILTIN_TEXTRMSW,
2520 ARM_BUILTIN_TEXTRMUB,
2521 ARM_BUILTIN_TEXTRMUH,
2522 ARM_BUILTIN_TEXTRMUW,
2523 ARM_BUILTIN_TINSRB,
2524 ARM_BUILTIN_TINSRH,
2525 ARM_BUILTIN_TINSRW,
2527 ARM_BUILTIN_WMAXSW,
2528 ARM_BUILTIN_WMAXSH,
2529 ARM_BUILTIN_WMAXSB,
2530 ARM_BUILTIN_WMAXUW,
2531 ARM_BUILTIN_WMAXUH,
2532 ARM_BUILTIN_WMAXUB,
2533 ARM_BUILTIN_WMINSW,
2534 ARM_BUILTIN_WMINSH,
2535 ARM_BUILTIN_WMINSB,
2536 ARM_BUILTIN_WMINUW,
2537 ARM_BUILTIN_WMINUH,
2538 ARM_BUILTIN_WMINUB,
2540 ARM_BUILTIN_WMULUM,
2541 ARM_BUILTIN_WMULSM,
2542 ARM_BUILTIN_WMULUL,
2544 ARM_BUILTIN_PSADBH,
2545 ARM_BUILTIN_WSHUFH,
2547 ARM_BUILTIN_WSLLH,
2548 ARM_BUILTIN_WSLLW,
2549 ARM_BUILTIN_WSLLD,
2550 ARM_BUILTIN_WSRAH,
2551 ARM_BUILTIN_WSRAW,
2552 ARM_BUILTIN_WSRAD,
2553 ARM_BUILTIN_WSRLH,
2554 ARM_BUILTIN_WSRLW,
2555 ARM_BUILTIN_WSRLD,
2556 ARM_BUILTIN_WRORH,
2557 ARM_BUILTIN_WRORW,
2558 ARM_BUILTIN_WRORD,
2559 ARM_BUILTIN_WSLLHI,
2560 ARM_BUILTIN_WSLLWI,
2561 ARM_BUILTIN_WSLLDI,
2562 ARM_BUILTIN_WSRAHI,
2563 ARM_BUILTIN_WSRAWI,
2564 ARM_BUILTIN_WSRADI,
2565 ARM_BUILTIN_WSRLHI,
2566 ARM_BUILTIN_WSRLWI,
2567 ARM_BUILTIN_WSRLDI,
2568 ARM_BUILTIN_WRORHI,
2569 ARM_BUILTIN_WRORWI,
2570 ARM_BUILTIN_WRORDI,
2572 ARM_BUILTIN_WUNPCKIHB,
2573 ARM_BUILTIN_WUNPCKIHH,
2574 ARM_BUILTIN_WUNPCKIHW,
2575 ARM_BUILTIN_WUNPCKILB,
2576 ARM_BUILTIN_WUNPCKILH,
2577 ARM_BUILTIN_WUNPCKILW,
2579 ARM_BUILTIN_WUNPCKEHSB,
2580 ARM_BUILTIN_WUNPCKEHSH,
2581 ARM_BUILTIN_WUNPCKEHSW,
2582 ARM_BUILTIN_WUNPCKEHUB,
2583 ARM_BUILTIN_WUNPCKEHUH,
2584 ARM_BUILTIN_WUNPCKEHUW,
2585 ARM_BUILTIN_WUNPCKELSB,
2586 ARM_BUILTIN_WUNPCKELSH,
2587 ARM_BUILTIN_WUNPCKELSW,
2588 ARM_BUILTIN_WUNPCKELUB,
2589 ARM_BUILTIN_WUNPCKELUH,
2590 ARM_BUILTIN_WUNPCKELUW,
2592 ARM_BUILTIN_THREAD_POINTER,
2594 ARM_BUILTIN_MAX
2595 };
2597 /* Do not emit .note.GNU-stack by default. */
2598 #ifndef NEED_INDICATE_EXEC_STACK
2599 #define NEED_INDICATE_EXEC_STACK 0
2600 #endif