1 /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ------------------------------------------------------------------------ */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
32 #include "tree-pass.h"
33 #include "stringpool.h"
38 #include "optabs.h" /* For GEN_FCN. */
42 #include "diagnostic-core.h"
43 #include "stor-layout.h"
49 #include "tm-constrs.h"
54 /* This file should be included last. */
55 #include "target-def.h"
57 /* ------------------------------------------------------------------------ */
59 /* This file is divided into five parts:
61 PART 1: Auxiliary static variable definitions and
62 target hook static variable definitions.
64 PART 2: Auxiliary static function definitions.
66 PART 3: Implement target hook stuff definitions.
68 PART 4: Implemet extern function definitions,
69 the prototype is in nds32-protos.h.
71 PART 5: Initialize target hook structure and definitions. */
73 /* ------------------------------------------------------------------------ */
75 /* PART 1: Auxiliary static variable definitions and
76 target hook static variable definitions. */
78 /* Define intrinsic register names.
79 Please refer to nds32_intrinsic.h file, the index is corresponding to
80 'enum nds32_intrinsic_registers' data type values.
81 NOTE that the base value starting from 1024. */
82 static const char * const nds32_intrinsic_register_names
[] =
240 /* Define instrinsic cctl names. */
241 static const char * const nds32_cctl_names
[] =
269 static const char * const nds32_dpref_names
[] =
279 /* Defining register allocation order for performance.
280 We want to allocate callee-saved registers after others.
281 It may be used by nds32_adjust_reg_alloc_order(). */
282 static const int nds32_reg_alloc_order_for_speed
[] =
284 0, 1, 2, 3, 4, 5, 16, 17,
285 18, 19, 20, 21, 22, 23, 24, 25,
286 26, 27, 6, 7, 8, 9, 10, 11,
290 /* Defining target-specific uses of __attribute__. */
291 static const struct attribute_spec nds32_attribute_table
[] =
293 /* Syntax: { name, min_len, max_len, decl_required, type_required,
294 function_type_required, affects_type_identity, handler,
297 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */
298 { "interrupt", 1, 64, false, false, false, false, NULL
, NULL
},
299 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */
300 { "exception", 1, 8, false, false, false, false, NULL
, NULL
},
301 /* Argument is user's interrupt numbers. The vector number is always 0. */
302 { "reset", 1, 1, false, false, false, false, NULL
, NULL
},
304 /* The attributes describing isr nested type. */
305 { "nested", 0, 0, false, false, false, false, NULL
, NULL
},
306 { "not_nested", 0, 0, false, false, false, false, NULL
, NULL
},
307 { "nested_ready", 0, 0, false, false, false, false, NULL
, NULL
},
309 /* The attributes describing isr register save scheme. */
310 { "save_all", 0, 0, false, false, false, false, NULL
, NULL
},
311 { "partial_save", 0, 0, false, false, false, false, NULL
, NULL
},
313 /* The attributes used by reset attribute. */
314 { "nmi", 1, 1, false, false, false, false, NULL
, NULL
},
315 { "warm", 1, 1, false, false, false, false, NULL
, NULL
},
317 /* The attribute telling no prologue/epilogue. */
318 { "naked", 0, 0, false, false, false, false, NULL
, NULL
},
320 /* The attribute is used to tell this function to be ROM patch. */
321 { "indirect_call",0, 0, false, false, false, false, NULL
, NULL
},
323 /* FOR BACKWARD COMPATIBILITY,
324 this attribute also tells no prologue/epilogue. */
325 { "no_prologue", 0, 0, false, false, false, false, NULL
, NULL
},
327 /* The last attribute spec is set to be NULL. */
328 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
332 /* ------------------------------------------------------------------------ */
334 /* PART 2: Auxiliary static function definitions. */
336 /* Function to save and restore machine-specific function data. */
337 static struct machine_function
*
338 nds32_init_machine_status (void)
340 struct machine_function
*machine
;
341 machine
= ggc_cleared_alloc
<machine_function
> ();
343 /* Initially assume this function does not use __builtin_eh_return. */
344 machine
->use_eh_return_p
= 0;
346 /* Initially assume this function needs prologue/epilogue. */
347 machine
->naked_p
= 0;
349 /* Initially assume this function does NOT use fp_as_gp optimization. */
350 machine
->fp_as_gp_p
= 0;
352 /* Initially this function is not under strictly aligned situation. */
353 machine
->strict_aligned_p
= 0;
355 /* Initially this function has no naked and no_prologue attributes. */
356 machine
->attr_naked_p
= 0;
357 machine
->attr_no_prologue_p
= 0;
362 /* Function to compute stack frame size and
363 store into cfun->machine structure. */
365 nds32_compute_stack_frame (void)
371 /* Because nds32_compute_stack_frame() will be called from different place,
372 everytime we enter this function, we have to assume this function
373 needs prologue/epilogue. */
374 cfun
->machine
->naked_p
= 0;
376 /* We need to mark whether this function has naked and no_prologue
377 attribute so that we can distinguish the difference if users applies
378 -mret-in-naked-func option. */
379 cfun
->machine
->attr_naked_p
380 = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
))
382 cfun
->machine
->attr_no_prologue_p
383 = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl
))
386 /* If __builtin_eh_return is used, we better have frame pointer needed
387 so that we can easily locate the stack slot of return address. */
388 if (crtl
->calls_eh_return
)
390 frame_pointer_needed
= 1;
392 /* We need to mark eh data registers that need to be saved
394 cfun
->machine
->eh_return_data_first_regno
= EH_RETURN_DATA_REGNO (0);
395 for (r
= 0; EH_RETURN_DATA_REGNO (r
) != INVALID_REGNUM
; r
++)
396 cfun
->machine
->eh_return_data_last_regno
= r
;
398 cfun
->machine
->eh_return_data_regs_size
399 = 4 * (cfun
->machine
->eh_return_data_last_regno
400 - cfun
->machine
->eh_return_data_first_regno
402 cfun
->machine
->use_eh_return_p
= 1;
406 /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we
407 do not need to handle __builtin_eh_return case in this function. */
408 cfun
->machine
->eh_return_data_first_regno
= SP_REGNUM
;
409 cfun
->machine
->eh_return_data_last_regno
= SP_REGNUM
;
411 cfun
->machine
->eh_return_data_regs_size
= 0;
412 cfun
->machine
->use_eh_return_p
= 0;
415 /* Get variadic arguments size to prepare pretend arguments and
416 we will push them into stack at prologue by ourself. */
417 cfun
->machine
->va_args_size
= crtl
->args
.pretend_args_size
;
418 if (cfun
->machine
->va_args_size
!= 0)
420 cfun
->machine
->va_args_first_regno
421 = NDS32_GPR_ARG_FIRST_REGNUM
422 + NDS32_MAX_GPR_REGS_FOR_ARGS
423 - (crtl
->args
.pretend_args_size
/ UNITS_PER_WORD
);
424 cfun
->machine
->va_args_last_regno
425 = NDS32_GPR_ARG_FIRST_REGNUM
+ NDS32_MAX_GPR_REGS_FOR_ARGS
- 1;
429 cfun
->machine
->va_args_first_regno
= SP_REGNUM
;
430 cfun
->machine
->va_args_last_regno
= SP_REGNUM
;
433 /* Important: We need to make sure that varargs area is 8-byte alignment. */
434 block_size
= cfun
->machine
->va_args_size
;
435 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
437 cfun
->machine
->va_args_area_padding_bytes
438 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
) - block_size
;
441 /* Get local variables, incoming variables, and temporary variables size.
442 Note that we need to make sure it is 8-byte alignment because
443 there may be no padding bytes if we are using LRA. */
444 cfun
->machine
->local_size
= NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ());
446 /* Get outgoing arguments size. */
447 cfun
->machine
->out_args_size
= crtl
->outgoing_args_size
;
449 /* If $fp value is required to be saved on stack, it needs 4 bytes space.
450 Check whether $fp is ever live. */
451 cfun
->machine
->fp_size
= (df_regs_ever_live_p (FP_REGNUM
)) ? 4 : 0;
453 /* If $gp value is required to be saved on stack, it needs 4 bytes space.
454 Check whether we are using PIC code genration. */
455 cfun
->machine
->gp_size
=
456 (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
)) ? 4 : 0;
458 /* If $lp value is required to be saved on stack, it needs 4 bytes space.
459 Check whether $lp is ever live. */
460 cfun
->machine
->lp_size
461 = (flag_always_save_lp
|| df_regs_ever_live_p (LP_REGNUM
)) ? 4 : 0;
463 /* Initially there is no padding bytes. */
464 cfun
->machine
->callee_saved_area_gpr_padding_bytes
= 0;
466 /* Calculate the bytes of saving callee-saved registers on stack. */
467 cfun
->machine
->callee_saved_gpr_regs_size
= 0;
468 cfun
->machine
->callee_saved_first_gpr_regno
= SP_REGNUM
;
469 cfun
->machine
->callee_saved_last_gpr_regno
= SP_REGNUM
;
470 cfun
->machine
->callee_saved_fpr_regs_size
= 0;
471 cfun
->machine
->callee_saved_first_fpr_regno
= SP_REGNUM
;
472 cfun
->machine
->callee_saved_last_fpr_regno
= SP_REGNUM
;
474 /* Currently, there is no need to check $r28~$r31
475 because we will save them in another way. */
476 for (r
= 0; r
< 28; r
++)
478 if (NDS32_REQUIRED_CALLEE_SAVED_P (r
))
480 /* Mark the first required callee-saved register
481 (only need to set it once).
482 If first regno == SP_REGNUM, we can tell that
483 it is the first time to be here. */
484 if (cfun
->machine
->callee_saved_first_gpr_regno
== SP_REGNUM
)
485 cfun
->machine
->callee_saved_first_gpr_regno
= r
;
486 /* Mark the last required callee-saved register. */
487 cfun
->machine
->callee_saved_last_gpr_regno
= r
;
491 /* Recording fpu callee-saved register. */
492 if (TARGET_HARD_FLOAT
)
494 for (r
= NDS32_FIRST_FPR_REGNUM
; r
< NDS32_LAST_FPR_REGNUM
; r
++)
496 if (NDS32_REQUIRED_CALLEE_SAVED_P (r
))
498 /* Mark the first required callee-saved register. */
499 if (cfun
->machine
->callee_saved_first_fpr_regno
== SP_REGNUM
)
501 /* Make first callee-saved number is even,
502 bacause we use doubleword access, and this way
503 promise 8-byte alignemt. */
504 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r
))
505 cfun
->machine
->callee_saved_first_fpr_regno
= r
- 1;
507 cfun
->machine
->callee_saved_first_fpr_regno
= r
;
509 cfun
->machine
->callee_saved_last_fpr_regno
= r
;
513 /* Make last callee-saved register number is odd,
514 we hope callee-saved register is even. */
515 int last_fpr
= cfun
->machine
->callee_saved_last_fpr_regno
;
516 if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr
))
517 cfun
->machine
->callee_saved_last_fpr_regno
++;
520 /* Check if this function can omit prologue/epilogue code fragment.
521 If there is 'no_prologue'/'naked' attribute in this function,
522 we can set 'naked_p' flag to indicate that
523 we do not have to generate prologue/epilogue.
524 Or, if all the following conditions succeed,
525 we can set this function 'naked_p' as well:
526 condition 1: first_regno == last_regno == SP_REGNUM,
527 which means we do not have to save
528 any callee-saved registers.
529 condition 2: Both $lp and $fp are NOT live in this function,
530 which means we do not need to save them and there
532 condition 3: There is no local_size, which means
533 we do not need to adjust $sp. */
534 if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl
))
535 || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
))
536 || (cfun
->machine
->callee_saved_first_gpr_regno
== SP_REGNUM
537 && cfun
->machine
->callee_saved_last_gpr_regno
== SP_REGNUM
538 && cfun
->machine
->callee_saved_first_fpr_regno
== SP_REGNUM
539 && cfun
->machine
->callee_saved_last_fpr_regno
== SP_REGNUM
540 && !df_regs_ever_live_p (FP_REGNUM
)
541 && !df_regs_ever_live_p (LP_REGNUM
)
542 && cfun
->machine
->local_size
== 0
545 /* Set this function 'naked_p' and other functions can check this flag.
546 Note that in nds32 port, the 'naked_p = 1' JUST means there is no
547 callee-saved, local size, and outgoing size.
548 The varargs space and ret instruction may still present in
549 the prologue/epilogue expanding. */
550 cfun
->machine
->naked_p
= 1;
552 /* No need to save $fp, $gp, and $lp.
553 We should set these value to be zero
554 so that nds32_initial_elimination_offset() can work properly. */
555 cfun
->machine
->fp_size
= 0;
556 cfun
->machine
->gp_size
= 0;
557 cfun
->machine
->lp_size
= 0;
559 /* If stack usage computation is required,
560 we need to provide the static stack size. */
561 if (flag_stack_usage_info
)
562 current_function_static_stack_size
= 0;
564 /* No need to do following adjustment, return immediately. */
568 v3pushpop_p
= NDS32_V3PUSH_AVAILABLE_P
;
570 /* Adjustment for v3push instructions:
571 If we are using v3push (push25/pop25) instructions,
572 we need to make sure Rb is $r6 and Re is
573 located on $r6, $r8, $r10, or $r14.
574 Some results above will be discarded and recomputed.
575 Note that it is only available under V3/V3M ISA and we
576 DO NOT setup following stuff for isr or variadic function. */
580 cfun->machine->fp_size
581 cfun->machine->gp_size
582 cfun->machine->lp_size
583 cfun->machine->callee_saved_first_gpr_regno
584 cfun->machine->callee_saved_last_gpr_regno */
586 /* For v3push instructions, $fp, $gp, and $lp are always saved. */
587 cfun
->machine
->fp_size
= 4;
588 cfun
->machine
->gp_size
= 4;
589 cfun
->machine
->lp_size
= 4;
591 /* Remember to set Rb = $r6. */
592 cfun
->machine
->callee_saved_first_gpr_regno
= 6;
594 if (cfun
->machine
->callee_saved_last_gpr_regno
<= 6)
597 cfun
->machine
->callee_saved_last_gpr_regno
= 6;
599 else if (cfun
->machine
->callee_saved_last_gpr_regno
<= 8)
602 cfun
->machine
->callee_saved_last_gpr_regno
= 8;
604 else if (cfun
->machine
->callee_saved_last_gpr_regno
<= 10)
607 cfun
->machine
->callee_saved_last_gpr_regno
= 10;
609 else if (cfun
->machine
->callee_saved_last_gpr_regno
<= 14)
612 cfun
->machine
->callee_saved_last_gpr_regno
= 14;
614 else if (cfun
->machine
->callee_saved_last_gpr_regno
== SP_REGNUM
)
616 /* If last_regno is SP_REGNUM, which means
617 it is never changed, so set it to Re = $r6. */
618 cfun
->machine
->callee_saved_last_gpr_regno
= 6;
622 /* The program flow should not go here. */
627 int sp_adjust
= cfun
->machine
->local_size
628 + cfun
->machine
->out_args_size
629 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
630 + cfun
->machine
->callee_saved_fpr_regs_size
;
634 && !frame_pointer_needed
)
636 block_size
= cfun
->machine
->fp_size
637 + cfun
->machine
->gp_size
638 + cfun
->machine
->lp_size
;
640 if (cfun
->machine
->callee_saved_last_gpr_regno
!= SP_REGNUM
)
641 block_size
+= (4 * (cfun
->machine
->callee_saved_last_gpr_regno
642 - cfun
->machine
->callee_saved_first_gpr_regno
645 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
647 /* $r14 is last callee save register. */
648 if (cfun
->machine
->callee_saved_last_gpr_regno
649 < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM
)
651 cfun
->machine
->callee_saved_last_gpr_regno
++;
653 else if (cfun
->machine
->callee_saved_first_gpr_regno
== SP_REGNUM
)
655 cfun
->machine
->callee_saved_first_gpr_regno
656 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM
;
657 cfun
->machine
->callee_saved_last_gpr_regno
658 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM
;
663 /* We have correctly set callee_saved_first_gpr_regno
664 and callee_saved_last_gpr_regno.
665 Initially, the callee_saved_gpr_regs_size is supposed to be 0.
666 As long as callee_saved_last_gpr_regno is not SP_REGNUM,
667 we can update callee_saved_gpr_regs_size with new size. */
668 if (cfun
->machine
->callee_saved_last_gpr_regno
!= SP_REGNUM
)
670 /* Compute pushed size of callee-saved registers. */
671 cfun
->machine
->callee_saved_gpr_regs_size
672 = 4 * (cfun
->machine
->callee_saved_last_gpr_regno
673 - cfun
->machine
->callee_saved_first_gpr_regno
677 if (TARGET_HARD_FLOAT
)
679 /* Compute size of callee svaed floating-point registers. */
680 if (cfun
->machine
->callee_saved_last_fpr_regno
!= SP_REGNUM
)
682 cfun
->machine
->callee_saved_fpr_regs_size
683 = 4 * (cfun
->machine
->callee_saved_last_fpr_regno
684 - cfun
->machine
->callee_saved_first_fpr_regno
689 /* Important: We need to make sure that
690 (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size)
692 If it is not, calculate the padding bytes. */
693 block_size
= cfun
->machine
->fp_size
694 + cfun
->machine
->gp_size
695 + cfun
->machine
->lp_size
696 + cfun
->machine
->callee_saved_gpr_regs_size
;
697 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size
))
699 cfun
->machine
->callee_saved_area_gpr_padding_bytes
700 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
) - block_size
;
703 /* If stack usage computation is required,
704 we need to provide the static stack size. */
705 if (flag_stack_usage_info
)
707 current_function_static_stack_size
708 = NDS32_ROUND_UP_DOUBLE_WORD (block_size
)
709 + cfun
->machine
->local_size
710 + cfun
->machine
->out_args_size
;
714 /* Function to create a parallel rtx pattern
715 which presents stack push multiple behavior.
716 The overall concept are:
717 "push registers to memory",
718 "adjust stack pointer". */
720 nds32_emit_stack_push_multiple (unsigned Rb
, unsigned Re
,
721 bool save_fp_p
, bool save_gp_p
, bool save_lp_p
,
737 /* We need to provide a customized rtx which contains
738 necessary information for data analysis,
739 so we create a parallel rtx like this:
740 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
742 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
745 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
747 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
749 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
751 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
753 (set (reg:SI SP_REGNUM)
754 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */
756 /* Calculate the number of registers that will be pushed. */
764 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
765 if (Rb
== SP_REGNUM
&& Re
== SP_REGNUM
)
766 num_use_regs
= extra_count
;
768 num_use_regs
= Re
- Rb
+ 1 + extra_count
;
770 /* In addition to used registers,
771 we need one more space for (set sp sp-x) rtx. */
772 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
773 rtvec_alloc (num_use_regs
+ 1));
776 /* Initialize offset and start to create push behavior. */
777 offset
= -(num_use_regs
* 4);
779 /* Create (set mem regX) from Rb, Rb+1 up to Re. */
780 for (regno
= Rb
; regno
<= Re
; regno
++)
782 /* Rb and Re may be SP_REGNUM.
783 We need to break this loop immediately. */
784 if (regno
== SP_REGNUM
)
787 reg
= gen_rtx_REG (SImode
, regno
);
788 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
791 push_rtx
= gen_rtx_SET (mem
, reg
);
792 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
793 RTX_FRAME_RELATED_P (push_rtx
) = 1;
798 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */
801 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
802 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
805 push_rtx
= gen_rtx_SET (mem
, reg
);
806 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
807 RTX_FRAME_RELATED_P (push_rtx
) = 1;
813 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
814 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
817 push_rtx
= gen_rtx_SET (mem
, reg
);
818 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
819 RTX_FRAME_RELATED_P (push_rtx
) = 1;
825 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
826 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
829 push_rtx
= gen_rtx_SET (mem
, reg
);
830 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
831 RTX_FRAME_RELATED_P (push_rtx
) = 1;
836 /* Create (set sp sp-x). */
838 /* We need to re-calculate the offset value again for adjustment. */
839 offset
= -(num_use_regs
* 4);
841 = gen_rtx_SET (stack_pointer_rtx
,
842 plus_constant (Pmode
, stack_pointer_rtx
, offset
));
843 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
844 RTX_FRAME_RELATED_P (adjust_sp_rtx
) = 1;
846 parallel_insn
= emit_insn (parallel_insn
);
848 /* The insn rtx 'parallel_insn' will change frame layout.
849 We need to use RTX_FRAME_RELATED_P so that GCC is able to
850 generate CFI (Call Frame Information) stuff. */
851 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
853 /* Don't use GCC's logic for CFI info if we are generate a push for VAARG
854 since we will not restore those register at epilogue. */
857 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
,
858 copy_rtx (adjust_sp_rtx
), NULL_RTX
);
859 REG_NOTES (parallel_insn
) = dwarf
;
863 /* Function to create a parallel rtx pattern
864 which presents stack pop multiple behavior.
865 The overall concept are:
866 "pop registers from memory",
867 "adjust stack pointer". */
869 nds32_emit_stack_pop_multiple (unsigned Rb
, unsigned Re
,
870 bool save_fp_p
, bool save_gp_p
, bool save_lp_p
)
883 rtx dwarf
= NULL_RTX
;
885 /* We need to provide a customized rtx which contains
886 necessary information for data analysis,
887 so we create a parallel rtx like this:
888 (parallel [(set (reg:SI Rb)
889 (mem (reg:SI SP_REGNUM)))
891 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
894 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
895 (set (reg:SI FP_REGNUM)
896 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
897 (set (reg:SI GP_REGNUM)
898 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
899 (set (reg:SI LP_REGNUM)
900 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
901 (set (reg:SI SP_REGNUM)
902 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
904 /* Calculate the number of registers that will be poped. */
912 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */
913 if (Rb
== SP_REGNUM
&& Re
== SP_REGNUM
)
914 num_use_regs
= extra_count
;
916 num_use_regs
= Re
- Rb
+ 1 + extra_count
;
918 /* In addition to used registers,
919 we need one more space for (set sp sp+x) rtx. */
920 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
921 rtvec_alloc (num_use_regs
+ 1));
924 /* Initialize offset and start to create pop behavior. */
927 /* Create (set regX mem) from Rb, Rb+1 up to Re. */
928 for (regno
= Rb
; regno
<= Re
; regno
++)
930 /* Rb and Re may be SP_REGNUM.
931 We need to break this loop immediately. */
932 if (regno
== SP_REGNUM
)
935 reg
= gen_rtx_REG (SImode
, regno
);
936 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
939 pop_rtx
= gen_rtx_SET (reg
, mem
);
940 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
941 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
945 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
948 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */
951 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
952 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
955 pop_rtx
= gen_rtx_SET (reg
, mem
);
956 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
957 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
961 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
965 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
966 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
969 pop_rtx
= gen_rtx_SET (reg
, mem
);
970 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
971 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
975 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
979 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
980 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
983 pop_rtx
= gen_rtx_SET (reg
, mem
);
984 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
985 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
989 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
992 /* Create (set sp sp+x). */
994 /* The offset value is already in place. No need to re-calculate it. */
996 = gen_rtx_SET (stack_pointer_rtx
,
997 plus_constant (Pmode
, stack_pointer_rtx
, offset
));
998 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
1000 /* Tell gcc we adjust SP in this insn. */
1001 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, copy_rtx (adjust_sp_rtx
), dwarf
);
1003 parallel_insn
= emit_insn (parallel_insn
);
1005 /* The insn rtx 'parallel_insn' will change frame layout.
1006 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1007 generate CFI (Call Frame Information) stuff. */
1008 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
1010 /* Add CFI info by manual. */
1011 REG_NOTES (parallel_insn
) = dwarf
;
1014 /* Function to create a parallel rtx pattern
1015 which presents stack v3push behavior.
1016 The overall concept are:
1017 "push registers to memory",
1018 "adjust stack pointer". */
1020 nds32_emit_stack_v3push (unsigned Rb
,
1035 /* We need to provide a customized rtx which contains
1036 necessary information for data analysis,
1037 so we create a parallel rtx like this:
1038 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
1040 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
1043 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
1045 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
1047 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
1049 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
1051 (set (reg:SI SP_REGNUM)
1052 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */
1054 /* Calculate the number of registers that will be pushed.
1055 Since $fp, $gp, and $lp is always pushed with v3push instruction,
1056 we need to count these three registers.
1057 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1058 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1059 num_use_regs
= Re
- Rb
+ 1 + 3;
1061 /* In addition to used registers,
1062 we need one more space for (set sp sp-x-imm8u) rtx. */
1063 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
1064 rtvec_alloc (num_use_regs
+ 1));
1067 /* Initialize offset and start to create push behavior. */
1068 offset
= -(num_use_regs
* 4);
1070 /* Create (set mem regX) from Rb, Rb+1 up to Re.
1071 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1072 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1073 for (regno
= Rb
; regno
<= Re
; regno
++)
1075 reg
= gen_rtx_REG (SImode
, regno
);
1076 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1079 push_rtx
= gen_rtx_SET (mem
, reg
);
1080 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1081 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1082 offset
= offset
+ 4;
1086 /* Create (set mem fp). */
1087 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
1088 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1091 push_rtx
= gen_rtx_SET (mem
, reg
);
1092 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1093 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1094 offset
= offset
+ 4;
1096 /* Create (set mem gp). */
1097 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
1098 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1101 push_rtx
= gen_rtx_SET (mem
, reg
);
1102 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1103 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1104 offset
= offset
+ 4;
1106 /* Create (set mem lp). */
1107 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
1108 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1111 push_rtx
= gen_rtx_SET (mem
, reg
);
1112 XVECEXP (parallel_insn
, 0, par_index
) = push_rtx
;
1113 RTX_FRAME_RELATED_P (push_rtx
) = 1;
1114 offset
= offset
+ 4;
1117 /* Create (set sp sp-x-imm8u). */
1119 /* We need to re-calculate the offset value again for adjustment. */
1120 offset
= -(num_use_regs
* 4);
1122 = gen_rtx_SET (stack_pointer_rtx
,
1123 plus_constant (Pmode
,
1126 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
1127 RTX_FRAME_RELATED_P (adjust_sp_rtx
) = 1;
1129 parallel_insn
= emit_insn (parallel_insn
);
1131 /* The insn rtx 'parallel_insn' will change frame layout.
1132 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1133 generate CFI (Call Frame Information) stuff. */
1134 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
1137 /* Function to create a parallel rtx pattern
1138 which presents stack v3pop behavior.
1139 The overall concept are:
1140 "pop registers from memory",
1141 "adjust stack pointer". */
1143 nds32_emit_stack_v3pop (unsigned Rb
,
1157 rtx dwarf
= NULL_RTX
;
1159 /* We need to provide a customized rtx which contains
1160 necessary information for data analysis,
1161 so we create a parallel rtx like this:
1162 (parallel [(set (reg:SI Rb)
1163 (mem (reg:SI SP_REGNUM)))
1165 (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
1168 (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
1169 (set (reg:SI FP_REGNUM)
1170 (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
1171 (set (reg:SI GP_REGNUM)
1172 (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
1173 (set (reg:SI LP_REGNUM)
1174 (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
1175 (set (reg:SI SP_REGNUM)
1176 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */
1178 /* Calculate the number of registers that will be poped.
1179 Since $fp, $gp, and $lp is always poped with v3pop instruction,
1180 we need to count these three registers.
1181 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1182 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1183 num_use_regs
= Re
- Rb
+ 1 + 3;
1185 /* In addition to used registers,
1186 we need one more space for (set sp sp+x+imm8u) rtx. */
1187 parallel_insn
= gen_rtx_PARALLEL (VOIDmode
,
1188 rtvec_alloc (num_use_regs
+ 1));
1191 /* Initialize offset and start to create pop behavior. */
1194 /* Create (set regX mem) from Rb, Rb+1 up to Re.
1195 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14.
1196 So there is no need to worry about Rb=Re=SP_REGNUM case. */
1197 for (regno
= Rb
; regno
<= Re
; regno
++)
1199 reg
= gen_rtx_REG (SImode
, regno
);
1200 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1203 pop_rtx
= gen_rtx_SET (reg
, mem
);
1204 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1205 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1206 offset
= offset
+ 4;
1209 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1212 /* Create (set fp mem). */
1213 reg
= gen_rtx_REG (SImode
, FP_REGNUM
);
1214 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1217 pop_rtx
= gen_rtx_SET (reg
, mem
);
1218 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1219 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1220 offset
= offset
+ 4;
1222 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1224 /* Create (set gp mem). */
1225 reg
= gen_rtx_REG (SImode
, GP_REGNUM
);
1226 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1229 pop_rtx
= gen_rtx_SET (reg
, mem
);
1230 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1231 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1232 offset
= offset
+ 4;
1234 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1236 /* Create (set lp mem ). */
1237 reg
= gen_rtx_REG (SImode
, LP_REGNUM
);
1238 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
1241 pop_rtx
= gen_rtx_SET (reg
, mem
);
1242 XVECEXP (parallel_insn
, 0, par_index
) = pop_rtx
;
1243 RTX_FRAME_RELATED_P (pop_rtx
) = 1;
1244 offset
= offset
+ 4;
1246 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
1248 /* Create (set sp sp+x+imm8u). */
1250 /* The offset value is already in place. No need to re-calculate it. */
1252 = gen_rtx_SET (stack_pointer_rtx
,
1253 plus_constant (Pmode
,
1256 XVECEXP (parallel_insn
, 0, par_index
) = adjust_sp_rtx
;
1258 if (frame_pointer_needed
)
1260 /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp)
1262 mean reset frame pointer to $sp and reset to offset 0. */
1263 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
1265 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
1269 /* Tell gcc we adjust SP in this insn. */
1270 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
,
1271 copy_rtx (adjust_sp_rtx
), dwarf
);
1274 parallel_insn
= emit_insn (parallel_insn
);
1276 /* The insn rtx 'parallel_insn' will change frame layout.
1277 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1278 generate CFI (Call Frame Information) stuff. */
1279 RTX_FRAME_RELATED_P (parallel_insn
) = 1;
1281 /* Add CFI info by manual. */
1282 REG_NOTES (parallel_insn
) = dwarf
;
1286 nds32_emit_load_gp (void)
1288 rtx got_symbol
, pat
;
1290 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
1291 emit_insn (gen_blockage ());
1293 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1294 /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */
1295 pat
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, got_symbol
), UNSPEC_GOTINIT
);
1296 pat
= gen_rtx_CONST (SImode
, gen_rtx_PLUS (Pmode
, pat
, GEN_INT (-8)));
1297 emit_insn (gen_sethi (pic_offset_table_rtx
,pat
));
1299 /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */
1300 pat
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, got_symbol
), UNSPEC_GOTINIT
);
1301 pat
= gen_rtx_CONST (SImode
, gen_rtx_PLUS (Pmode
, pat
, GEN_INT (-4)));
1302 emit_insn (gen_lo_sum (pic_offset_table_rtx
, pic_offset_table_rtx
, pat
));
1305 emit_insn (gen_add_pc (pic_offset_table_rtx
, pic_offset_table_rtx
));
1307 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */
1308 emit_insn (gen_blockage ());
1311 /* Function that may creates more instructions
1312 for large value on adjusting stack pointer.
1314 In nds32 target, 'addi' can be used for stack pointer
1315 adjustment in prologue/epilogue stage.
1316 However, sometimes there are too many local variables so that
1317 the adjustment value is not able to be fit in the 'addi' instruction.
1318 One solution is to move value into a register
1319 and then use 'add' instruction.
1320 In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */
1322 nds32_emit_adjust_frame (rtx to_reg
, rtx from_reg
, int adjust_value
)
1325 rtx frame_adjust_insn
;
1326 rtx adjust_value_rtx
= GEN_INT (adjust_value
);
1328 if (adjust_value
== 0)
1331 if (!satisfies_constraint_Is15 (adjust_value_rtx
))
1333 /* The value is not able to fit in single addi instruction.
1334 Create more instructions of moving value into a register
1335 and then add stack pointer with it. */
1337 /* $r15 is going to be temporary register to hold the value. */
1338 tmp_reg
= gen_rtx_REG (SImode
, TA_REGNUM
);
1340 /* Create one more instruction to move value
1341 into the temporary register. */
1342 emit_move_insn (tmp_reg
, adjust_value_rtx
);
1344 /* Create new 'add' rtx. */
1345 frame_adjust_insn
= gen_addsi3 (to_reg
,
1348 /* Emit rtx into insn list and receive its transformed insn rtx. */
1349 frame_adjust_insn
= emit_insn (frame_adjust_insn
);
1351 /* Because (tmp_reg <- full_value) may be split into two
1352 rtl patterns, we can not set its RTX_FRAME_RELATED_P.
1353 We need to construct another (sp <- sp + full_value)
1354 and then insert it into sp_adjust_insn's reg note to
1355 represent a frame related expression.
1356 GCC knows how to refer it and output debug information. */
1361 plus_rtx
= plus_constant (Pmode
, from_reg
, adjust_value
);
1362 set_rtx
= gen_rtx_SET (to_reg
, plus_rtx
);
1363 add_reg_note (frame_adjust_insn
, REG_FRAME_RELATED_EXPR
, set_rtx
);
1367 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */
1368 frame_adjust_insn
= gen_addsi3 (to_reg
,
1371 /* Emit rtx into instructions list and receive INSN rtx form. */
1372 frame_adjust_insn
= emit_insn (frame_adjust_insn
);
1375 /* The insn rtx 'sp_adjust_insn' will change frame layout.
1376 We need to use RTX_FRAME_RELATED_P so that GCC is able to
1377 generate CFI (Call Frame Information) stuff. */
1378 RTX_FRAME_RELATED_P (frame_adjust_insn
) = 1;
1381 /* Return true if MODE/TYPE need double word alignment. */
1383 nds32_needs_double_word_align (machine_mode mode
, const_tree type
)
1387 /* Pick up the alignment according to the mode or type. */
1388 align
= NDS32_MODE_TYPE_ALIGN (mode
, type
);
1390 return (align
> PARM_BOUNDARY
);
1393 /* Return true if FUNC is a naked function. */
1395 nds32_naked_function_p (tree func
)
1397 /* FOR BACKWARD COMPATIBILITY,
1398 we need to support 'no_prologue' attribute as well. */
1402 if (TREE_CODE (func
) != FUNCTION_DECL
)
1405 /* We have to use lookup_attribute() to check attributes.
1406 Because attr_naked_p and attr_no_prologue_p are set in
1407 nds32_compute_stack_frame() and the function has not been
1409 t_naked
= lookup_attribute ("naked", DECL_ATTRIBUTES (func
));
1410 t_no_prologue
= lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func
));
1412 return ((t_naked
!= NULL_TREE
) || (t_no_prologue
!= NULL_TREE
));
1415 /* Function that determine whether a load postincrement is a good thing to use
1416 for a given mode. */
1418 nds32_use_load_post_increment (machine_mode mode
)
1420 return (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE(E_DImode
));
1423 /* Function that check if 'X' is a valid address register.
1424 The variable 'STRICT' is very important to
1425 make decision for register number.
1428 => We are in reload pass or after reload pass.
1429 The register number should be strictly limited in general registers.
1432 => Before reload pass, we are free to use any register number. */
1434 nds32_address_register_rtx_p (rtx x
, bool strict
)
1438 if (GET_CODE (x
) != REG
)
1444 return REGNO_OK_FOR_BASE_P (regno
);
1449 /* Function that check if 'INDEX' is valid to be a index rtx for address.
1451 OUTER_MODE : Machine mode of outer address rtx.
1452 INDEX : Check if this rtx is valid to be a index for address.
1453 STRICT : If it is true, we are in reload pass or after reload pass. */
1455 nds32_legitimate_index_p (machine_mode outer_mode
,
1463 switch (GET_CODE (index
))
1466 regno
= REGNO (index
);
1467 /* If we are in reload pass or after reload pass,
1468 we need to limit it to general register. */
1470 return REGNO_OK_FOR_INDEX_P (regno
);
1475 /* The alignment of the integer value is determined by 'outer_mode'. */
1476 switch (GET_MODE_SIZE (outer_mode
))
1479 /* Further check if the value is legal for the 'outer_mode'. */
1480 if (satisfies_constraint_Is15 (index
))
1485 /* Further check if the value is legal for the 'outer_mode'. */
1486 if (satisfies_constraint_Is16 (index
))
1488 /* If it is not under strictly aligned situation,
1489 we can return true without checking alignment. */
1490 if (!cfun
->machine
->strict_aligned_p
)
1492 /* Make sure address is half word alignment. */
1493 else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index
)))
1499 /* Further check if the value is legal for the 'outer_mode'. */
1500 if (satisfies_constraint_Is17 (index
))
1502 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
))
1504 if (!satisfies_constraint_Is14 (index
))
1508 /* If it is not under strictly aligned situation,
1509 we can return true without checking alignment. */
1510 if (!cfun
->machine
->strict_aligned_p
)
1512 /* Make sure address is word alignment. */
1513 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index
)))
1519 if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index
) + 4,
1522 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
))
1524 if (!satisfies_constraint_Is14 (index
))
1528 /* If it is not under strictly aligned situation,
1529 we can return true without checking alignment. */
1530 if (!cfun
->machine
->strict_aligned_p
)
1532 /* Make sure address is word alignment.
1533 Currently we do not have 64-bit load/store yet,
1534 so we will use two 32-bit load/store instructions to do
1535 memory access and they are single word alignment. */
1536 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index
)))
1548 op0
= XEXP (index
, 0);
1549 op1
= XEXP (index
, 1);
1551 if (REG_P (op0
) && CONST_INT_P (op1
))
1554 multiplier
= INTVAL (op1
);
1556 /* We only allow (mult reg const_int_1), (mult reg const_int_2),
1557 (mult reg const_int_4) or (mult reg const_int_8). */
1558 if (multiplier
!= 1 && multiplier
!= 2
1559 && multiplier
!= 4 && multiplier
!= 8)
1562 regno
= REGNO (op0
);
1563 /* Limit it in general registers if we are
1564 in reload pass or after reload pass. */
1566 return REGNO_OK_FOR_INDEX_P (regno
);
1574 op0
= XEXP (index
, 0);
1575 op1
= XEXP (index
, 1);
1577 if (REG_P (op0
) && CONST_INT_P (op1
))
1580 /* op1 is already the sv value for use to do left shift. */
1583 /* We only allow (ashift reg const_int_0)
1584 or (ashift reg const_int_1) or (ashift reg const_int_2) or
1585 (ashift reg const_int_3). */
1586 if (sv
!= 0 && sv
!= 1 && sv
!=2 && sv
!= 3)
1589 regno
= REGNO (op0
);
1590 /* Limit it in general registers if we are
1591 in reload pass or after reload pass. */
1593 return REGNO_OK_FOR_INDEX_P (regno
);
1606 nds32_register_pass (
1607 rtl_opt_pass
*(*make_pass_func
) (gcc::context
*),
1608 enum pass_positioning_ops pass_pos
,
1609 const char *ref_pass_name
)
1611 opt_pass
*new_opt_pass
= make_pass_func (g
);
1613 struct register_pass_info insert_pass
=
1615 new_opt_pass
, /* pass */
1616 ref_pass_name
, /* reference_pass_name */
1617 1, /* ref_pass_instance_number */
1618 pass_pos
/* po_op */
1621 register_pass (&insert_pass
);
1624 /* This function is called from nds32_option_override ().
1625 All new passes should be registered here. */
1627 nds32_register_passes (void)
1629 nds32_register_pass (
1630 make_pass_nds32_fp_as_gp
,
1631 PASS_POS_INSERT_BEFORE
,
1634 nds32_register_pass (
1635 make_pass_nds32_relax_opt
,
1636 PASS_POS_INSERT_AFTER
,
1640 /* ------------------------------------------------------------------------ */
1642 /* PART 3: Implement target hook stuff definitions. */
1645 /* Computing the Length of an Insn.
1646 Modifies the length assigned to instruction INSN.
1647 LEN is the initially computed length of the insn. */
1649 nds32_adjust_insn_length (rtx_insn
*insn
, int length
)
1651 int adjust_value
= 0;
1652 switch (recog_memoized (insn
))
1654 case CODE_FOR_call_internal
:
1655 case CODE_FOR_call_value_internal
:
1657 if (NDS32_ALIGN_P ())
1659 rtx_insn
*next_insn
= next_active_insn (insn
);
1660 if (next_insn
&& get_attr_length (next_insn
) != 2)
1663 /* We need insert a nop after a noretun function call
1664 to prevent software breakpoint corrupt the next function. */
1665 if (find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
1673 return length
+ adjust_value
;
1680 /* Storage Layout. */
1682 /* This function will be called just before expansion into rtl. */
1684 nds32_expand_to_rtl_hook (void)
1686 /* We need to set strictly aligned situation.
1687 After that, the memory address checking in nds32_legitimate_address_p()
1688 will take alignment offset into consideration so that it will not create
1689 unaligned [base + offset] access during the rtl optimization. */
1690 cfun
->machine
->strict_aligned_p
= 1;
1694 /* Register Usage. */
1697 nds32_conditional_register_usage (void)
1701 if (TARGET_LINUX_ABI
)
1702 fixed_regs
[TP_REGNUM
] = 1;
1704 if (TARGET_HARD_FLOAT
)
1706 for (regno
= NDS32_FIRST_FPR_REGNUM
;
1707 regno
<= NDS32_LAST_FPR_REGNUM
; regno
++)
1709 fixed_regs
[regno
] = 0;
1710 if (regno
< NDS32_FIRST_FPR_REGNUM
+ NDS32_MAX_FPR_REGS_FOR_ARGS
)
1711 call_used_regs
[regno
] = 1;
1712 else if (regno
>= NDS32_FIRST_FPR_REGNUM
+ 22
1713 && regno
< NDS32_FIRST_FPR_REGNUM
+ 48)
1714 call_used_regs
[regno
] = 1;
1716 call_used_regs
[regno
] = 0;
1719 else if (TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
1721 for (regno
= NDS32_FIRST_FPR_REGNUM
;
1722 regno
<= NDS32_LAST_FPR_REGNUM
;
1724 fixed_regs
[regno
] = 0;
1729 /* Register Classes. */
1731 static unsigned char
1732 nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED
,
1735 /* Return the maximum number of consecutive registers
1736 needed to represent "mode" in a register of "rclass". */
1737 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1741 nds32_register_priority (int hard_regno
)
1743 /* Encourage to use r0-r7 for LRA when optimize for size. */
1748 else if (hard_regno
< 16)
1750 else if (hard_regno
< 28)
1757 if (hard_regno
> 27)
1765 nds32_can_change_mode_class (machine_mode from
,
1769 /* Don't spill double-precision register to two singal-precision
1771 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
1772 && GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
1774 return !reg_classes_intersect_p (rclass
, FP_REGS
);
1781 /* Stack Layout and Calling Conventions. */
1783 /* There are three kinds of pointer concepts using in GCC compiler:
1785 frame pointer: A pointer to the first location of local variables.
1786 stack pointer: A pointer to the top of a stack frame.
1787 argument pointer: A pointer to the incoming arguments.
1789 In nds32 target calling convention, we are using 8-byte alignment.
1790 Besides, we would like to have each stack frame of a function includes:
1793 1. previous hard frame pointer
1795 3. callee-saved registers
1796 4. <padding bytes> (we will calculte in nds32_compute_stack_frame()
1798 cfun->machine->callee_saved_area_padding_bytes)
1802 2. spilling location
1803 3. <padding bytes> (it will be calculated by GCC itself)
1804 4. incoming arguments
1805 5. <padding bytes> (it will be calculated by GCC itself)
1808 1. <padding bytes> (it will be calculated by GCC itself)
1809 2. outgoing arguments
1811 We 'wrap' these blocks together with
1812 hard frame pointer ($r28) and stack pointer ($r31).
1813 By applying the basic frame/stack/argument pointers concept,
1814 the layout of a stack frame shoule be like this:
1817 old stack pointer -> ----
1819 | | saved arguments for
1820 | | vararg functions
1822 hard frame pointer -> --
1823 & argument pointer | | \
1824 | | previous hardware frame pointer
1826 | | callee-saved registers
1831 | | and incoming arguments
1838 stack pointer -> ----
1840 $SFP and $AP are used to represent frame pointer and arguments pointer,
1841 which will be both eliminated as hard frame pointer. */
1843 /* -- Eliminating Frame Pointer and Arg Pointer. */
1846 nds32_can_eliminate (const int from_reg
, const int to_reg
)
1848 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
1851 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== HARD_FRAME_POINTER_REGNUM
)
1854 if (from_reg
== FRAME_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
1857 if (from_reg
== FRAME_POINTER_REGNUM
&& to_reg
== HARD_FRAME_POINTER_REGNUM
)
1863 /* -- Passing Arguments in Registers. */
1866 nds32_function_arg (cumulative_args_t ca
, machine_mode mode
,
1867 const_tree type
, bool named
)
1870 CUMULATIVE_ARGS
*cum
= get_cumulative_args (ca
);
1872 /* The last time this hook is called,
1873 it is called with MODE == VOIDmode. */
1874 if (mode
== VOIDmode
)
1877 /* For nameless arguments, we need to take care it individually. */
1880 /* If we are under hard float abi, we have arguments passed on the
1881 stack and all situation can be handled by GCC itself. */
1882 if (TARGET_HARD_FLOAT
)
1885 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum
->gpr_offset
, mode
, type
))
1887 /* If we still have enough registers to pass argument, pick up
1888 next available register number. */
1890 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1891 return gen_rtx_REG (mode
, regno
);
1894 /* No register available, return NULL_RTX.
1895 The compiler will use stack to pass argument instead. */
1899 /* The following is to handle named argument.
1900 Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT
1902 if (TARGET_HARD_FLOAT
)
1904 /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR
1905 to pass argument. We have to further check TYPE and MODE so
1906 that we can determine which kind of register we shall use. */
1908 /* Note that we need to pass argument entirely in registers under
1910 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1911 && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum
->fpr_offset
, mode
, type
))
1913 /* Pick up the next available FPR register number. */
1915 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum
->fpr_offset
, mode
, type
);
1916 return gen_rtx_REG (mode
, regno
);
1918 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
1919 && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum
->gpr_offset
, mode
, type
))
1921 /* Pick up the next available GPR register number. */
1923 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1924 return gen_rtx_REG (mode
, regno
);
1929 /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass
1930 argument. Since we allow to pass argument partially in registers,
1931 we can just return it if there are still registers available. */
1932 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum
->gpr_offset
, mode
, type
))
1934 /* Pick up the next available register number. */
1936 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
);
1937 return gen_rtx_REG (mode
, regno
);
1942 /* No register available, return NULL_RTX.
1943 The compiler will use stack to pass argument instead. */
1948 nds32_must_pass_in_stack (machine_mode mode
, const_tree type
)
1950 /* Return true if a type must be passed in memory.
1951 If it is NOT using hard float abi, small aggregates can be
1952 passed in a register even we are calling a variadic function.
1953 So there is no need to take padding into consideration. */
1954 if (TARGET_HARD_FLOAT
)
1955 return must_pass_in_stack_var_size_or_pad (mode
, type
);
1957 return must_pass_in_stack_var_size (mode
, type
);
1961 nds32_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
1962 tree type
, bool named ATTRIBUTE_UNUSED
)
1964 /* Returns the number of bytes at the beginning of an argument that
1965 must be put in registers. The value must be zero for arguments that are
1966 passed entirely in registers or that are entirely pushed on the stack.
1967 Besides, TARGET_FUNCTION_ARG for these arguments should return the
1968 first register to be used by the caller for this argument. */
1969 unsigned int needed_reg_count
;
1970 unsigned int remaining_reg_count
;
1971 CUMULATIVE_ARGS
*cum
;
1973 cum
= get_cumulative_args (ca
);
1975 /* Under hard float abi, we better have argument entirely passed in
1976 registers or pushed on the stack so that we can reduce the complexity
1977 of dealing with cum->gpr_offset and cum->fpr_offset. */
1978 if (TARGET_HARD_FLOAT
)
1981 /* If we have already runned out of argument registers, return zero
1982 so that the argument will be entirely pushed on the stack. */
1983 if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
1984 >= NDS32_GPR_ARG_FIRST_REGNUM
+ NDS32_MAX_GPR_REGS_FOR_ARGS
)
1987 /* Calculate how many registers do we need for this argument. */
1988 needed_reg_count
= NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
1990 /* Calculate how many argument registers have left for passing argument.
1991 Note that we should count it from next available register number. */
1993 = NDS32_MAX_GPR_REGS_FOR_ARGS
1994 - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
1995 - NDS32_GPR_ARG_FIRST_REGNUM
);
1997 /* Note that we have to return the nubmer of bytes, not registers count. */
1998 if (needed_reg_count
> remaining_reg_count
)
1999 return remaining_reg_count
* UNITS_PER_WORD
;
2005 nds32_function_arg_advance (cumulative_args_t ca
, machine_mode mode
,
2006 const_tree type
, bool named
)
2008 CUMULATIVE_ARGS
*cum
= get_cumulative_args (ca
);
2012 /* We need to further check TYPE and MODE so that we can determine
2013 which kind of register we shall advance. */
2015 /* Under hard float abi, we may advance FPR registers. */
2016 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2019 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum
->fpr_offset
, mode
, type
)
2020 - NDS32_FPR_ARG_FIRST_REGNUM
2021 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2026 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
2027 - NDS32_GPR_ARG_FIRST_REGNUM
2028 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2033 /* If this nameless argument is NOT under TARGET_HARD_FLOAT,
2034 we can advance next register as well so that caller is
2035 able to pass arguments in registers and callee must be
2036 in charge of pushing all of them into stack. */
2037 if (!TARGET_HARD_FLOAT
)
2040 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
2041 - NDS32_GPR_ARG_FIRST_REGNUM
2042 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2048 nds32_function_arg_boundary (machine_mode mode
, const_tree type
)
2050 return (nds32_needs_double_word_align (mode
, type
)
2051 ? NDS32_DOUBLE_WORD_ALIGNMENT
2056 nds32_vector_mode_supported_p (machine_mode mode
)
2058 if (mode
== V4QImode
2059 || mode
== V2HImode
)
2060 return NDS32_EXT_DSP_P ();
2065 /* -- How Scalar Function Values Are Returned. */
2068 nds32_function_value (const_tree ret_type
,
2069 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
2070 bool outgoing ATTRIBUTE_UNUSED
)
2075 mode
= TYPE_MODE (ret_type
);
2076 unsignedp
= TYPE_UNSIGNED (ret_type
);
2078 if (INTEGRAL_TYPE_P (ret_type
))
2079 mode
= promote_mode (ret_type
, mode
, &unsignedp
);
2081 if (TARGET_HARD_FLOAT
&& (mode
== SFmode
|| mode
== DFmode
))
2082 return gen_rtx_REG (mode
, NDS32_FPR_RET_FIRST_REGNUM
);
2084 return gen_rtx_REG (mode
, NDS32_GPR_RET_FIRST_REGNUM
);
2088 nds32_libcall_value (machine_mode mode
,
2089 const_rtx fun ATTRIBUTE_UNUSED
)
2091 if (TARGET_HARD_FLOAT
&& (mode
== SFmode
|| mode
== DFmode
))
2092 return gen_rtx_REG (mode
, NDS32_FPR_RET_FIRST_REGNUM
);
2094 return gen_rtx_REG (mode
, NDS32_GPR_RET_FIRST_REGNUM
);
2098 nds32_function_value_regno_p (const unsigned int regno
)
2100 if (regno
== NDS32_GPR_RET_FIRST_REGNUM
2101 || (TARGET_HARD_FLOAT
2102 && regno
== NDS32_FPR_RET_FIRST_REGNUM
))
2108 /* -- How Large Values Are Returned. */
2111 nds32_return_in_memory (const_tree type
,
2112 const_tree fntype ATTRIBUTE_UNUSED
)
2114 /* Note that int_size_in_bytes can return -1 if the size can vary
2115 or is larger than an integer. */
2116 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2118 /* For COMPLEX_TYPE, if the total size cannot be hold within two registers,
2119 the return value is supposed to be in memory. We need to be aware of
2120 that the size may be -1. */
2121 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2122 if (size
< 0 || size
> 2 * UNITS_PER_WORD
)
2125 /* If it is BLKmode and the total size cannot be hold within two registers,
2126 the return value is supposed to be in memory. We need to be aware of
2127 that the size may be -1. */
2128 if (TYPE_MODE (type
) == BLKmode
)
2129 if (size
< 0 || size
> 2 * UNITS_PER_WORD
)
2132 /* For other cases, having result in memory is unnecessary. */
2136 /* -- Function Entry and Exit. */
2138 /* The content produced from this function
2139 will be placed before prologue body. */
2141 nds32_asm_function_prologue (FILE *file
)
2144 const char *func_name
;
2148 /* All stack frame information is supposed to be
2149 already computed when expanding prologue.
2150 The result is in cfun->machine.
2151 DO NOT call nds32_compute_stack_frame() here
2152 because it may corrupt the essential information. */
2154 fprintf (file
, "\t! BEGIN PROLOGUE\n");
2155 fprintf (file
, "\t! fp needed: %d\n", frame_pointer_needed
);
2156 fprintf (file
, "\t! pretend_args: %d\n", cfun
->machine
->va_args_size
);
2157 fprintf (file
, "\t! local_size: %d\n", cfun
->machine
->local_size
);
2158 fprintf (file
, "\t! out_args_size: %d\n", cfun
->machine
->out_args_size
);
2160 /* Use df_regs_ever_live_p() to detect if the register
2161 is ever used in the current function. */
2162 fprintf (file
, "\t! registers ever_live: ");
2163 for (r
= 0; r
< 65; r
++)
2165 if (df_regs_ever_live_p (r
))
2166 fprintf (file
, "%s, ", reg_names
[r
]);
2170 /* Display the attributes of this function. */
2171 fprintf (file
, "\t! function attributes: ");
2172 /* Get the attributes tree list.
2173 Note that GCC builds attributes list with reverse order. */
2174 attrs
= DECL_ATTRIBUTES (current_function_decl
);
2176 /* If there is no any attribute, print out "None". */
2178 fprintf (file
, "None");
2180 /* If there are some attributes, try if we need to
2181 construct isr vector information. */
2182 func_name
= IDENTIFIER_POINTER (DECL_NAME (current_function_decl
));
2183 nds32_construct_isr_vectors_information (attrs
, func_name
);
2185 /* Display all attributes of this function. */
2188 name
= TREE_PURPOSE (attrs
);
2189 fprintf (file
, "%s ", IDENTIFIER_POINTER (name
));
2191 /* Pick up the next attribute. */
2192 attrs
= TREE_CHAIN (attrs
);
2197 /* After rtl prologue has been expanded, this function is used. */
2199 nds32_asm_function_end_prologue (FILE *file
)
2201 fprintf (file
, "\t! END PROLOGUE\n");
2204 /* Before rtl epilogue has been expanded, this function is used. */
2206 nds32_asm_function_begin_epilogue (FILE *file
)
2208 fprintf (file
, "\t! BEGIN EPILOGUE\n");
2211 /* The content produced from this function
2212 will be placed after epilogue body. */
2214 nds32_asm_function_epilogue (FILE *file
)
2216 fprintf (file
, "\t! END EPILOGUE\n");
2220 nds32_asm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
2221 HOST_WIDE_INT delta
,
2222 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2227 /* Make sure unwind info is emitted for the thunk if needed. */
2228 final_start_function (emit_barrier (), file
, 1);
2230 this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
2236 fprintf (file
, "\tsmw.adm\t$r31, [$r31], $r31, 4\n");
2237 fprintf (file
, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n",
2238 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
2239 fprintf (file
, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n",
2240 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
2241 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
2244 fprintf (file
, "\tadd5.pc\t$gp\n");
2247 fprintf (file
, "\tmfusr\t$ta, $pc\n");
2248 fprintf (file
, "\tadd\t%s, $ta, %s\n",
2249 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
2250 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
2256 if (satisfies_constraint_Is15 (GEN_INT (delta
)))
2258 fprintf (file
, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC
"\n",
2259 this_regno
, this_regno
, delta
);
2261 else if (satisfies_constraint_Is20 (GEN_INT (delta
)))
2263 fprintf (file
, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC
"\n", delta
);
2264 fprintf (file
, "\tadd\t$r%d, $r%d, $ta\n", this_regno
, this_regno
);
2269 "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC
")\n",
2272 "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC
")\n",
2274 fprintf (file
, "\tadd\t$r%d, $r%d, $ta\n", this_regno
, this_regno
);
2280 fprintf (file
, "\tla\t$ta, ");
2281 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2282 fprintf (file
, "@PLT\n");
2283 fprintf (file
, "\t! epilogue\n");
2284 fprintf (file
, "\tlwi.bi\t%s, [%s], 4\n",
2285 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
2286 reg_names
[STACK_POINTER_REGNUM
]);
2287 fprintf (file
, "\tbr\t$ta\n");
2291 fprintf (file
, "\tb\t");
2292 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2293 fprintf (file
, "\n");
2296 final_end_function ();
2299 /* -- Permitting tail calls. */
2301 /* Return true if it is ok to do sibling call optimization. */
2303 nds32_function_ok_for_sibcall (tree decl
,
2304 tree exp ATTRIBUTE_UNUSED
)
2306 /* The DECL is NULL if it is an indirect call. */
2308 /* 1. Do not apply sibling call if -mv3push is enabled,
2309 because pop25 instruction also represents return behavior.
2310 2. If this function is a variadic function, do not apply sibling call
2311 because the stack layout may be a mess.
2312 3. We don't want to apply sibling call optimization for indirect
2313 sibcall because the pop behavior in epilogue may pollute the
2314 content of caller-saved regsiter when the register is used for
2316 4. In pic mode, it may use some registers for PLT call. */
2317 return (!TARGET_V3PUSH
2318 && (cfun
->machine
->va_args_size
== 0)
2323 /* Determine whether we need to enable warning for function return check. */
2325 nds32_warn_func_return (tree decl
)
2327 /* Naked functions are implemented entirely in assembly, including the
2328 return sequence, so suppress warnings about this. */
2329 return !nds32_naked_function_p (decl
);
2333 /* Implementing the Varargs Macros. */
2336 nds32_setup_incoming_varargs (cumulative_args_t ca
,
2339 int *pretend_args_size
,
2340 int second_time ATTRIBUTE_UNUSED
)
2342 unsigned int total_args_regs
;
2343 unsigned int num_of_used_regs
;
2344 unsigned int remaining_reg_count
;
2345 CUMULATIVE_ARGS
*cum
;
2347 /* If we are under hard float abi, we do not need to set *pretend_args_size.
2348 So that all nameless arguments are pushed by caller and all situation
2349 can be handled by GCC itself. */
2350 if (TARGET_HARD_FLOAT
)
2353 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers,
2354 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments.
2355 However, for nameless(anonymous) arguments, we should push them on the
2356 stack so that all the nameless arguments appear to have been passed
2357 consecutively in the memory for accessing. Hence, we need to check and
2358 exclude the registers that are used for named arguments. */
2360 cum
= get_cumulative_args (ca
);
2362 /* The MODE and TYPE describe the last argument.
2363 We need those information to determine the remaining registers
2366 = NDS32_MAX_GPR_REGS_FOR_ARGS
+ NDS32_GPR_ARG_FIRST_REGNUM
;
2368 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum
->gpr_offset
, mode
, type
)
2369 + NDS32_NEED_N_REGS_FOR_ARG (mode
, type
);
2371 remaining_reg_count
= total_args_regs
- num_of_used_regs
;
2372 *pretend_args_size
= remaining_reg_count
* UNITS_PER_WORD
;
2378 nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
2380 /* If this hook returns true, the named argument of FUNCTION_ARG is always
2381 true for named arguments, and false for unnamed arguments. */
2386 /* Trampolines for Nested Functions. */
2389 nds32_asm_trampoline_template (FILE *f
)
2391 if (TARGET_REDUCED_REGS
)
2393 /* Trampoline is not supported on reduced-set registers yet. */
2394 sorry ("a nested function is not supported for reduced registers");
2398 asm_fprintf (f
, "\t! Trampoline code template\n");
2399 asm_fprintf (f
, "\t! This code fragment will be copied "
2400 "into stack on demand\n");
2402 asm_fprintf (f
, "\tmfusr\t$r16,$pc\n");
2403 asm_fprintf (f
, "\tlwi\t$r15,[$r16 + 20] "
2404 "! load nested function address\n");
2405 asm_fprintf (f
, "\tlwi\t$r16,[$r16 + 16] "
2406 "! load chain_value\n");
2407 asm_fprintf (f
, "\tjr\t$r15\n");
2410 /* Preserve space ($pc + 16) for saving chain_value,
2411 nds32_trampoline_init will fill the value in this slot. */
2412 asm_fprintf (f
, "\t! space for saving chain_value\n");
2413 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2415 /* Preserve space ($pc + 20) for saving nested function address,
2416 nds32_trampoline_init will fill the value in this slot. */
2417 asm_fprintf (f
, "\t! space for saving nested function address\n");
2418 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2421 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2423 nds32_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2427 /* Nested function address. */
2429 /* The memory rtx that is going to
2430 be filled with chain_value. */
2431 rtx chain_value_mem
;
2432 /* The memory rtx that is going to
2433 be filled with nested function address. */
2434 rtx nested_func_mem
;
2436 /* Start address of trampoline code in stack, for doing cache sync. */
2437 rtx sync_cache_addr
;
2438 /* Temporary register for sync instruction. */
2440 /* Instruction-cache sync instruction,
2441 requesting an argument as starting address. */
2443 /* For convenience reason of doing comparison. */
2444 int tramp_align_in_bytes
;
2446 /* Trampoline is not supported on reduced-set registers yet. */
2447 if (TARGET_REDUCED_REGS
)
2448 sorry ("a nested function is not supported for reduced registers");
2450 /* STEP 1: Copy trampoline code template into stack,
2451 fill up essential data into stack. */
2453 /* Extract nested function address rtx. */
2454 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2456 /* m_tramp is memory rtx that is going to be filled with trampoline code.
2457 We have nds32_asm_trampoline_template() to emit template pattern. */
2458 emit_block_move (m_tramp
, assemble_trampoline_template (),
2459 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2461 /* After copying trampoline code into stack,
2462 fill chain_value into stack. */
2463 chain_value_mem
= adjust_address (m_tramp
, SImode
, 16);
2464 emit_move_insn (chain_value_mem
, chain_value
);
2465 /* After copying trampoline code int stack,
2466 fill nested function address into stack. */
2467 nested_func_mem
= adjust_address (m_tramp
, SImode
, 20);
2468 emit_move_insn (nested_func_mem
, fnaddr
);
2470 /* STEP 2: Sync instruction-cache. */
2472 /* We have successfully filled trampoline code into stack.
2473 However, in order to execute code in stack correctly,
2474 we must sync instruction cache. */
2475 sync_cache_addr
= XEXP (m_tramp
, 0);
2476 tmp_reg
= gen_reg_rtx (SImode
);
2477 isync_insn
= gen_unspec_volatile_isync (tmp_reg
);
2479 /* Because nds32_cache_block_size is in bytes,
2480 we get trampoline alignment in bytes for convenient comparison. */
2481 tramp_align_in_bytes
= TRAMPOLINE_ALIGNMENT
/ BITS_PER_UNIT
;
2483 if (tramp_align_in_bytes
>= nds32_cache_block_size
2484 && (tramp_align_in_bytes
% nds32_cache_block_size
) == 0)
2486 /* Under this condition, the starting address of trampoline
2487 must be aligned to the starting address of each cache block
2488 and we do not have to worry about cross-boundary issue. */
2490 i
< (TRAMPOLINE_SIZE
+ nds32_cache_block_size
- 1)
2491 / nds32_cache_block_size
;
2494 emit_move_insn (tmp_reg
,
2495 plus_constant (Pmode
, sync_cache_addr
,
2496 nds32_cache_block_size
* i
));
2497 emit_insn (isync_insn
);
2500 else if (TRAMPOLINE_SIZE
> nds32_cache_block_size
)
2502 /* The starting address of trampoline code
2503 may not be aligned to the cache block,
2504 so the trampoline code may be across two cache block.
2505 We need to sync the last element, which is 4-byte size,
2506 of trampoline template. */
2508 i
< (TRAMPOLINE_SIZE
+ nds32_cache_block_size
- 1)
2509 / nds32_cache_block_size
;
2512 emit_move_insn (tmp_reg
,
2513 plus_constant (Pmode
, sync_cache_addr
,
2514 nds32_cache_block_size
* i
));
2515 emit_insn (isync_insn
);
2518 /* The last element of trampoline template is 4-byte size. */
2519 emit_move_insn (tmp_reg
,
2520 plus_constant (Pmode
, sync_cache_addr
,
2521 TRAMPOLINE_SIZE
- 4));
2522 emit_insn (isync_insn
);
2526 /* This is the simplest case.
2527 Because TRAMPOLINE_SIZE is less than or
2528 equal to nds32_cache_block_size,
2529 we can just sync start address and
2530 the last element of trampoline code. */
2532 /* Sync starting address of tampoline code. */
2533 emit_move_insn (tmp_reg
, sync_cache_addr
);
2534 emit_insn (isync_insn
);
2535 /* Sync the last element, which is 4-byte size,
2536 of trampoline template. */
2537 emit_move_insn (tmp_reg
,
2538 plus_constant (Pmode
, sync_cache_addr
,
2539 TRAMPOLINE_SIZE
- 4));
2540 emit_insn (isync_insn
);
2543 /* Set instruction serialization barrier
2544 to guarantee the correct operations. */
2545 emit_insn (gen_unspec_volatile_isb ());
2549 /* Addressing Modes. */
2552 nds32_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2554 if (TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
2556 /* When using floating-point instructions,
2557 we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */
2558 if ((mode
== DFmode
|| mode
== SFmode
)
2559 && (GET_CODE (x
) == SYMBOL_REF
2560 || GET_CODE(x
) == CONST
))
2563 /* Allow [post_modify] addressing mode, when using FPU instructions. */
2564 if (GET_CODE (x
) == POST_MODIFY
2567 if (GET_CODE (XEXP (x
, 0)) == REG
2568 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2570 rtx plus_op
= XEXP (x
, 1);
2571 rtx op0
= XEXP (plus_op
, 0);
2572 rtx op1
= XEXP (plus_op
, 1);
2574 if (nds32_address_register_rtx_p (op0
, strict
)
2575 && CONST_INT_P (op1
))
2577 if (satisfies_constraint_Is14 (op1
))
2579 /* If it is not under strictly aligned situation,
2580 we can return true without checking alignment. */
2581 if (!cfun
->machine
->strict_aligned_p
)
2583 /* Make sure address is word alignment.
2584 Currently we do not have 64-bit load/store yet,
2585 so we will use two 32-bit load/store instructions to do
2586 memory access and they are single word alignment. */
2587 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1
)))
2595 /* For (mem:DI addr) or (mem:DF addr) case,
2596 we only allow 'addr' to be [reg], [symbol_ref],
2597 [const], or [reg + const_int] pattern. */
2598 if (mode
== DImode
|| mode
== DFmode
)
2600 /* Allow [Reg + const_int] addressing mode. */
2601 if (GET_CODE (x
) == PLUS
)
2603 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
)
2604 && nds32_legitimate_index_p (mode
, XEXP (x
, 1), strict
)
2605 && CONST_INT_P (XEXP (x
, 1)))
2607 else if (nds32_address_register_rtx_p (XEXP (x
, 1), strict
)
2608 && nds32_legitimate_index_p (mode
, XEXP (x
, 0), strict
)
2609 && CONST_INT_P (XEXP (x
, 0)))
2613 /* Allow [post_inc] and [post_dec] addressing mode. */
2614 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == POST_DEC
)
2616 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
))
2620 /* Now check [reg], [symbol_ref], and [const]. */
2621 if (GET_CODE (x
) != REG
2622 && GET_CODE (x
) != SYMBOL_REF
2623 && GET_CODE (x
) != CONST
)
2627 /* Check if 'x' is a valid address. */
2628 switch (GET_CODE (x
))
2631 /* (mem (reg A)) => [Ra] */
2632 return nds32_address_register_rtx_p (x
, strict
);
2635 /* (mem (symbol_ref A)) => [symbol_ref] */
2637 if (flag_pic
|| SYMBOL_REF_TLS_MODEL (x
))
2640 if (TARGET_ICT_MODEL_LARGE
&& nds32_indirect_call_referenced_p (x
))
2643 /* If -mcmodel=large, the 'symbol_ref' is not a valid address
2644 during or after LRA/reload phase. */
2645 if (TARGET_CMODEL_LARGE
2646 && (reload_completed
2647 || reload_in_progress
2648 || lra_in_progress
))
2650 /* If -mcmodel=medium and the symbol references to rodata section,
2651 the 'symbol_ref' is not a valid address during or after
2652 LRA/reload phase. */
2653 if (TARGET_CMODEL_MEDIUM
2654 && (NDS32_SYMBOL_REF_RODATA_P (x
)
2655 || CONSTANT_POOL_ADDRESS_P (x
))
2656 && (reload_completed
2657 || reload_in_progress
2658 || lra_in_progress
))
2664 /* (mem (const (...)))
2665 => [ + const_addr ], where const_addr = symbol_ref + const_int */
2666 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2668 rtx plus_op
= XEXP (x
, 0);
2670 rtx op0
= XEXP (plus_op
, 0);
2671 rtx op1
= XEXP (plus_op
, 1);
2673 if (GET_CODE (op0
) == SYMBOL_REF
&& CONST_INT_P (op1
))
2675 /* Now we see the [ + const_addr ] pattern, but we need
2676 some further checking. */
2681 /* If -mcmodel=large, the 'const_addr' is not a valid address
2682 during or after LRA/reload phase. */
2683 if (TARGET_CMODEL_LARGE
2684 && (reload_completed
2685 || reload_in_progress
2686 || lra_in_progress
))
2688 /* If -mcmodel=medium and the symbol references to rodata section,
2689 the 'const_addr' is not a valid address during or after
2690 LRA/reload phase. */
2691 if (TARGET_CMODEL_MEDIUM
2692 && NDS32_SYMBOL_REF_RODATA_P (op0
)
2693 && (reload_completed
2694 || reload_in_progress
2695 || lra_in_progress
))
2698 /* At this point we can make sure 'const_addr' is a
2707 /* (mem (post_modify (reg) (plus (reg) (reg))))
2709 /* (mem (post_modify (reg) (plus (reg) (const_int))))
2710 => [Ra], const_int */
2711 if (GET_CODE (XEXP (x
, 0)) == REG
2712 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2714 rtx plus_op
= XEXP (x
, 1);
2716 rtx op0
= XEXP (plus_op
, 0);
2717 rtx op1
= XEXP (plus_op
, 1);
2719 if (nds32_address_register_rtx_p (op0
, strict
)
2720 && nds32_legitimate_index_p (mode
, op1
, strict
))
2730 /* (mem (post_inc reg)) => [Ra], 1/2/4 */
2731 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */
2732 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
2733 We only need to deal with register Ra. */
2734 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
))
2740 /* (mem (plus reg const_int))
2742 /* (mem (plus reg reg))
2744 /* (mem (plus (mult reg const_int) reg))
2745 => [Ra + Rb << sv] */
2746 if (nds32_address_register_rtx_p (XEXP (x
, 0), strict
)
2747 && nds32_legitimate_index_p (mode
, XEXP (x
, 1), strict
))
2749 else if (nds32_address_register_rtx_p (XEXP (x
, 1), strict
)
2750 && nds32_legitimate_index_p (mode
, XEXP (x
, 0), strict
))
2756 /* (mem (lo_sum (reg) (symbol_ref))) */
2757 /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */
2758 /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */
2759 /* The LO_SUM is a valid address if and only if we would like to
2760 generate 32-bit full address memory access with any of following
2763 2. -mcmodel=medium and the symbol_ref references to rodata. */
2770 if (!REG_P (XEXP (x
, 0)))
2773 if (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
2775 else if (GET_CODE (XEXP (x
, 1)) == CONST
)
2777 rtx plus
= XEXP(XEXP (x
, 1), 0);
2778 if (GET_CODE (plus
) == PLUS
)
2779 sym
= XEXP (plus
, 0);
2780 else if (GET_CODE (plus
) == UNSPEC
)
2781 sym
= XVECEXP (plus
, 0, 0);
2786 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
);
2788 if (TARGET_ICT_MODEL_LARGE
2789 && nds32_indirect_call_referenced_p (sym
))
2792 if (TARGET_CMODEL_LARGE
)
2794 else if (TARGET_CMODEL_MEDIUM
2795 && NDS32_SYMBOL_REF_RODATA_P (sym
))
2807 nds32_legitimize_address (rtx x
,
2808 rtx oldx ATTRIBUTE_UNUSED
,
2809 machine_mode mode ATTRIBUTE_UNUSED
)
2811 if (nds32_tls_referenced_p (x
))
2812 x
= nds32_legitimize_tls_address (x
);
2813 else if (flag_pic
&& SYMBOLIC_CONST_P (x
))
2814 x
= nds32_legitimize_pic_address (x
);
2815 else if (TARGET_ICT_MODEL_LARGE
&& nds32_indirect_call_referenced_p (x
))
2816 x
= nds32_legitimize_ict_address (x
);
2822 nds32_legitimate_constant_p (machine_mode mode
, rtx x
)
2824 switch (GET_CODE (x
))
2827 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
2828 && (mode
== DFmode
|| mode
== SFmode
))
2834 if (GET_CODE (x
) == PLUS
)
2836 if (!CONST_INT_P (XEXP (x
, 1)))
2841 if (GET_CODE (x
) == UNSPEC
)
2843 switch (XINT (x
, 1))
2860 /* TLS symbols need a call to resolve in
2861 precompute_register_parameters. */
2862 if (SYMBOL_REF_TLS_MODEL (x
))
2872 /* Reorgnize the UNSPEC CONST and return its direct symbol. */
2874 nds32_delegitimize_address (rtx x
)
2876 x
= delegitimize_mem_from_attrs (x
);
2878 if (GET_CODE(x
) == CONST
)
2880 rtx inner
= XEXP (x
, 0);
2882 /* Handle for GOTOFF. */
2883 if (GET_CODE (inner
) == PLUS
)
2884 inner
= XEXP (inner
, 0);
2886 if (GET_CODE (inner
) == UNSPEC
)
2888 switch (XINT (inner
, 1))
2890 case UNSPEC_GOTINIT
:
2899 x
= XVECEXP (inner
, 0, 0);
2910 nds32_vectorize_preferred_simd_mode (scalar_mode mode
)
2912 if (!NDS32_EXT_DSP_P ())
2927 nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2929 switch (GET_CODE (x
))
2932 return !nds32_legitimate_constant_p (mode
, x
);
2934 /* All symbols have to be accessed through gp-relative in PIC mode. */
2935 /* We don't want to force symbol as constant pool in .text section,
2936 because we use the gp-relatived instruction to load in small
2939 || SYMBOL_REF_TLS_MODEL (x
)
2940 || TARGET_CMODEL_SMALL
2941 || TARGET_CMODEL_MEDIUM
)
2946 if (flag_pic
&& (lra_in_progress
|| reload_completed
))
2956 /* Condition Code Status. */
2958 /* -- Representation of condition codes using registers. */
2961 nds32_canonicalize_comparison (int *code
,
2962 rtx
*op0 ATTRIBUTE_UNUSED
,
2964 bool op0_preserve_value ATTRIBUTE_UNUSED
)
2966 /* When the instruction combination pass tries to combine a comparison insn
2967 with its previous insns, it also transforms the operator in order to
2968 minimize its constant field. For example, it tries to transform a
2969 comparison insn from
2972 (const_int 10 [0xa])))
2976 (const_int 9 [0x9])))
2978 However, the nds32 target only provides instructions supporting the LTU
2979 operation directly, and the implementation of the pattern "cbranchsi4"
2980 only expands the LTU form. In order to handle the non-LTU operations
2981 generated from passes other than the RTL expansion pass, we have to
2982 implement this hook to revert those changes. Since we only expand the LTU
2983 operator in the RTL expansion pass, we might only need to handle the LEU
2984 case, unless we find other optimization passes perform more aggressive
2987 if (*code
== LEU
&& CONST_INT_P (*op1
))
2989 *op1
= gen_int_mode (INTVAL (*op1
) + 1, SImode
);
2995 /* Describing Relative Costs of Operations. */
2998 nds32_register_move_cost (machine_mode mode
,
3002 /* In garywolf cpu, FPR to GPR is chaper than other cpu. */
3003 if (TARGET_PIPELINE_GRAYWOLF
)
3005 if (GET_MODE_SIZE (mode
) == 8)
3008 if (from
== FP_REGS
&& to
!= FP_REGS
)
3011 if (from
!= FP_REGS
&& to
== FP_REGS
)
3016 if ((from
== FP_REGS
&& to
!= FP_REGS
)
3017 || (from
!= FP_REGS
&& to
== FP_REGS
))
3022 if ((from
== FP_REGS
&& to
!= FP_REGS
)
3023 || (from
!= FP_REGS
&& to
== FP_REGS
))
3025 else if (from
== HIGH_REGS
|| to
== HIGH_REGS
)
3026 return optimize_size
? 6 : 2;
3032 nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3033 reg_class_t rclass ATTRIBUTE_UNUSED
,
3034 bool in ATTRIBUTE_UNUSED
)
3039 /* This target hook describes the relative costs of RTL expressions.
3040 Return 'true' when all subexpressions of x have been processed.
3041 Return 'false' to sum the costs of sub-rtx, plus cost of this operation.
3042 Refer to gcc/rtlanal.c for more information. */
3044 nds32_rtx_costs (rtx x
,
3051 return nds32_rtx_costs_impl (x
, mode
, outer_code
, opno
, total
, speed
);
3055 nds32_address_cost (rtx address
,
3060 return nds32_address_cost_impl (address
, mode
, as
, speed
);
3064 /* Dividing the Output into Sections (Texts, Data, . . . ). */
3066 /* If references to a symbol or a constant must be treated differently
3067 depending on something about the variable or function named by the symbol
3068 (such as what section it is in), we use this hook to store flags
3069 in symbol_ref rtx. */
3071 nds32_encode_section_info (tree decl
, rtx rtl
, int new_decl_p
)
3073 default_encode_section_info (decl
, rtl
, new_decl_p
);
3075 /* For the memory rtx, if it references to rodata section, we can store
3076 NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the
3077 nds32_legitimate_address_p() can determine how to treat such symbol_ref
3078 based on -mcmodel=X and this information. */
3079 if (MEM_P (rtl
) && MEM_READONLY_P (rtl
))
3081 rtx addr
= XEXP (rtl
, 0);
3083 if (GET_CODE (addr
) == SYMBOL_REF
)
3085 /* For (mem (symbol_ref X)) case. */
3086 SYMBOL_REF_FLAGS (addr
) |= NDS32_SYMBOL_FLAG_RODATA
;
3088 else if (GET_CODE (addr
) == CONST
3089 && GET_CODE (XEXP (addr
, 0)) == PLUS
)
3091 /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */
3092 rtx plus_op
= XEXP (addr
, 0);
3093 rtx op0
= XEXP (plus_op
, 0);
3094 rtx op1
= XEXP (plus_op
, 1);
3096 if (GET_CODE (op0
) == SYMBOL_REF
&& CONST_INT_P (op1
))
3097 SYMBOL_REF_FLAGS (op0
) |= NDS32_SYMBOL_FLAG_RODATA
;
3103 /* Defining the Output Assembler Language. */
3105 /* -- The Overall Framework of an Assembler File. */
3108 nds32_asm_file_start (void)
3110 default_file_start ();
3113 fprintf (asm_out_file
, "\t.pic\n");
3115 /* Tell assembler which ABI we are using. */
3116 fprintf (asm_out_file
, "\t! ABI version\n");
3117 if (TARGET_HARD_FLOAT
)
3118 fprintf (asm_out_file
, "\t.abi_2fp_plus\n");
3120 fprintf (asm_out_file
, "\t.abi_2\n");
3122 /* Tell assembler that this asm code is generated by compiler. */
3123 fprintf (asm_out_file
, "\t! This asm file is generated by compiler\n");
3124 fprintf (asm_out_file
, "\t.flag\tverbatim\n");
3126 /* Insert directive for linker to distinguish object's ict flag. */
3127 if (!TARGET_LINUX_ABI
)
3129 if (TARGET_ICT_MODEL_LARGE
)
3130 fprintf (asm_out_file
, "\t.ict_model\tlarge\n");
3132 fprintf (asm_out_file
, "\t.ict_model\tsmall\n");
3135 /* We need to provide the size of each vector for interrupt handler
3136 under elf toolchain. */
3137 if (!TARGET_LINUX_ABI
)
3139 fprintf (asm_out_file
, "\t! This vector size directive is required "
3140 "for checking inconsistency on interrupt handler\n");
3141 fprintf (asm_out_file
, "\t.vec_size\t%d\n", nds32_isr_vector_size
);
3144 /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os,
3145 the compiler may produce 'la $fp,_FP_BASE_' instruction
3146 at prologue for fp-as-gp optimization.
3147 We should emit weak reference of _FP_BASE_ to avoid undefined reference
3148 in case user does not pass '--relax' option to linker. */
3149 if (!TARGET_LINUX_ABI
&& (TARGET_FORCE_FP_AS_GP
|| optimize_size
))
3151 fprintf (asm_out_file
, "\t! This weak reference is required to do "
3152 "fp-as-gp link time optimization\n");
3153 fprintf (asm_out_file
, "\t.weak\t_FP_BASE_\n");
3156 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3159 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V2");
3161 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V3");
3163 fprintf (asm_out_file
, "\t! ISA family\t\t: %s\n", "V3M");
3165 switch (nds32_cpu_option
)
3168 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N6");
3172 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N7");
3176 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N8");
3180 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "E8");
3184 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N9");
3188 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N10");
3192 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "Graywolf");
3197 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "N13");
3201 fprintf (asm_out_file
, "\t! Pipeline model\t: %s\n", "SIMPLE");
3208 if (TARGET_CMODEL_SMALL
)
3209 fprintf (asm_out_file
, "\t! Code model\t\t: %s\n", "SMALL");
3210 if (TARGET_CMODEL_MEDIUM
)
3211 fprintf (asm_out_file
, "\t! Code model\t\t: %s\n", "MEDIUM");
3212 if (TARGET_CMODEL_LARGE
)
3213 fprintf (asm_out_file
, "\t! Code model\t\t: %s\n", "LARGE");
3215 fprintf (asm_out_file
, "\t! Endian setting\t: %s\n",
3216 ((TARGET_BIG_ENDIAN
) ? "big-endian"
3217 : "little-endian"));
3218 fprintf (asm_out_file
, "\t! Use SP floating-point instruction\t: %s\n",
3219 ((TARGET_FPU_SINGLE
) ? "Yes"
3221 fprintf (asm_out_file
, "\t! Use DP floating-point instruction\t: %s\n",
3222 ((TARGET_FPU_DOUBLE
) ? "Yes"
3224 fprintf (asm_out_file
, "\t! ABI version\t\t: %s\n",
3225 ((TARGET_HARD_FLOAT
) ? "ABI2FP+"
3228 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3230 fprintf (asm_out_file
, "\t! Use conditional move\t\t: %s\n",
3231 ((TARGET_CMOV
) ? "Yes"
3233 fprintf (asm_out_file
, "\t! Use performance extension\t: %s\n",
3234 ((TARGET_EXT_PERF
) ? "Yes"
3236 fprintf (asm_out_file
, "\t! Use performance extension 2\t: %s\n",
3237 ((TARGET_EXT_PERF2
) ? "Yes"
3239 fprintf (asm_out_file
, "\t! Use string extension\t\t: %s\n",
3240 ((TARGET_EXT_STRING
) ? "Yes"
3243 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3245 fprintf (asm_out_file
, "\t! V3PUSH instructions\t: %s\n",
3246 ((TARGET_V3PUSH
) ? "Yes"
3248 fprintf (asm_out_file
, "\t! 16-bit instructions\t: %s\n",
3249 ((TARGET_16_BIT
) ? "Yes"
3251 fprintf (asm_out_file
, "\t! Reduced registers set\t: %s\n",
3252 ((TARGET_REDUCED_REGS
) ? "Yes"
3255 fprintf (asm_out_file
, "\t! Support unaligned access\t\t: %s\n",
3256 (flag_unaligned_access
? "Yes"
3259 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3262 fprintf (asm_out_file
, "\t! Optimization level\t: -Os\n");
3263 else if (optimize_fast
)
3264 fprintf (asm_out_file
, "\t! Optimization level\t: -Ofast\n");
3265 else if (optimize_debug
)
3266 fprintf (asm_out_file
, "\t! Optimization level\t: -Og\n");
3268 fprintf (asm_out_file
, "\t! Optimization level\t: -O%d\n", optimize
);
3270 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3272 fprintf (asm_out_file
, "\t! Cache block size\t: %d\n",
3273 nds32_cache_block_size
);
3275 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3277 nds32_asm_file_start_for_isr ();
3281 nds32_asm_file_end (void)
3283 nds32_asm_file_end_for_isr ();
3285 /* The NDS32 Linux stack is mapped non-executable by default, so add a
3286 .note.GNU-stack section. */
3287 if (TARGET_LINUX_ABI
)
3288 file_end_indicate_exec_stack ();
3290 fprintf (asm_out_file
, "\t! ------------------------------------\n");
3294 nds32_asm_output_addr_const_extra (FILE *file
, rtx x
)
3296 if (GET_CODE (x
) == UNSPEC
)
3298 switch (XINT (x
, 1))
3300 case UNSPEC_GOTINIT
:
3301 output_addr_const (file
, XVECEXP (x
, 0, 0));
3304 output_addr_const (file
, XVECEXP (x
, 0, 0));
3305 fputs ("@GOTOFF", file
);
3308 output_addr_const (file
, XVECEXP (x
, 0, 0));
3309 fputs ("@GOT", file
);
3312 output_addr_const (file
, XVECEXP (x
, 0, 0));
3313 fputs ("@PLT", file
);
3316 output_addr_const (file
, XVECEXP (x
, 0, 0));
3317 fputs ("@TLSDESC", file
);
3320 output_addr_const (file
, XVECEXP (x
, 0, 0));
3321 fputs ("@TLSDESC", file
);
3324 output_addr_const (file
, XVECEXP (x
, 0, 0));
3325 fputs ("@GOTTPOFF", file
);
3328 output_addr_const (file
, XVECEXP (x
, 0, 0));
3329 fputs ("@TPOFF", file
);
3332 output_addr_const (file
, XVECEXP (x
, 0, 0));
3333 fputs ("@ICT", file
);
3344 /* -- Output and Generation of Labels. */
3347 nds32_asm_globalize_label (FILE *stream
, const char *name
)
3349 fputs ("\t.global\t", stream
);
3350 assemble_name (stream
, name
);
3351 fputs ("\n", stream
);
3354 /* -- Output of Assembler Instructions. */
3357 nds32_print_operand (FILE *stream
, rtx x
, int code
)
3359 HOST_WIDE_INT op_value
= 0;
3360 HOST_WIDE_INT one_position
;
3361 HOST_WIDE_INT zero_position
;
3362 bool pick_lsb_p
= false;
3363 bool pick_msb_p
= false;
3366 if (CONST_INT_P (x
))
3367 op_value
= INTVAL (x
);
3372 /* Do nothing special. */
3376 /* Use exact_log2() to search the 0-bit position. */
3377 gcc_assert (CONST_INT_P (x
));
3378 zero_position
= exact_log2 (~UINTVAL (x
) & GET_MODE_MASK (SImode
));
3379 gcc_assert (zero_position
!= -1);
3380 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, zero_position
);
3382 /* No need to handle following process, so return immediately. */
3386 gcc_assert (MEM_P (x
)
3387 && GET_CODE (XEXP (x
, 0)) == PLUS
3388 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
3389 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (XEXP (XEXP (x
, 0), 1)));
3391 /* No need to handle following process, so return immediately. */
3395 gcc_assert (CONST_INT_P (x
)
3399 || INTVAL (x
) == 24));
3400 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) / 8);
3402 /* No need to handle following process, so return immediately. */
3406 /* Use exact_log2() to search the 1-bit position. */
3407 gcc_assert (CONST_INT_P (x
));
3408 one_position
= exact_log2 (UINTVAL (x
) & GET_MODE_MASK (SImode
));
3409 gcc_assert (one_position
!= -1);
3410 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, one_position
);
3412 /* No need to handle following process, so return immediately. */
3416 /* X is supposed to be REG rtx. */
3417 gcc_assert (REG_P (x
));
3418 /* Claim that we are going to pick LSB part of X. */
3423 /* X is supposed to be REG rtx. */
3424 gcc_assert (REG_P (x
));
3425 /* Claim that we are going to pick MSB part of X. */
3430 /* 'x' is supposed to be CONST_INT, get the value. */
3431 gcc_assert (CONST_INT_P (x
));
3433 /* According to the Andes architecture,
3434 the system/user register index range is 0 ~ 1023.
3435 In order to avoid conflict between user-specified-integer value
3436 and enum-specified-register value,
3437 the 'enum nds32_intrinsic_registers' value
3438 in nds32_intrinsic.h starts from 1024. */
3439 if (op_value
< 1024 && op_value
>= 0)
3441 /* If user gives integer value directly (0~1023),
3442 we just print out the value. */
3443 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, op_value
);
3445 else if (op_value
< 0
3446 || op_value
>= ((int) ARRAY_SIZE (nds32_intrinsic_register_names
)
3449 /* The enum index value for array size is out of range. */
3450 error ("intrinsic register index is out of range");
3454 /* If user applies normal way with __NDS32_REG_XXX__ enum data,
3455 we can print out register name. Remember to substract 1024. */
3456 fprintf (stream
, "%s",
3457 nds32_intrinsic_register_names
[op_value
- 1024]);
3460 /* No need to handle following process, so return immediately. */
3463 case 'R': /* cctl valck */
3464 /* Note the cctl divide to 5 group and share the same name table. */
3465 if (op_value
< 0 || op_value
> 4)
3466 error ("CCTL intrinsic function subtype out of range!");
3467 fprintf (stream
, "%s", nds32_cctl_names
[op_value
]);
3470 case 'T': /* cctl idxwbinv */
3471 /* Note the cctl divide to 5 group and share the same name table. */
3472 if (op_value
< 0 || op_value
> 4)
3473 error ("CCTL intrinsic function subtype out of range!");
3474 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 4]);
3477 case 'U': /* cctl vawbinv */
3478 /* Note the cctl divide to 5 group and share the same name table. */
3479 if (op_value
< 0 || op_value
> 4)
3480 error ("CCTL intrinsic function subtype out of range!");
3481 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 8]);
3484 case 'X': /* cctl idxread */
3485 /* Note the cctl divide to 5 group and share the same name table. */
3486 if (op_value
< 0 || op_value
> 4)
3487 error ("CCTL intrinsic function subtype out of range!");
3488 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 12]);
3491 case 'W': /* cctl idxwitre */
3492 /* Note the cctl divide to 5 group and share the same name table. */
3493 if (op_value
< 0 || op_value
> 4)
3494 error ("CCTL intrinsic function subtype out of range!");
3495 fprintf (stream
, "%s", nds32_cctl_names
[op_value
+ 16]);
3498 case 'Z': /* dpref */
3499 fprintf (stream
, "%s", nds32_dpref_names
[op_value
]);
3504 output_operand_lossage ("invalid operand output code");
3508 switch (GET_CODE (x
))
3511 output_addr_const (stream
, x
);
3515 output_addr_const (stream
, x
);
3517 if (!TARGET_LINUX_ABI
&& nds32_indirect_call_referenced_p (x
))
3518 fprintf (stream
, "@ICT");
3523 /* Print a Double-precision register name. */
3524 if ((GET_MODE (x
) == DImode
|| GET_MODE (x
) == DFmode
)
3525 && NDS32_IS_FPR_REGNUM (REGNO (x
)))
3528 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno
))
3530 output_operand_lossage ("invalid operand for code '%c'", code
);
3533 fprintf (stream
, "$fd%d", (regno
- NDS32_FIRST_FPR_REGNUM
) >> 1);
3537 /* Print LSB or MSB part of register pair if the
3538 constraint modifier 'L' or 'H' is specified. */
3539 if ((GET_MODE (x
) == DImode
|| GET_MODE (x
) == DFmode
)
3540 && NDS32_IS_GPR_REGNUM (REGNO (x
)))
3542 if ((pick_lsb_p
&& WORDS_BIG_ENDIAN
)
3543 || (pick_msb_p
&& !WORDS_BIG_ENDIAN
))
3545 /* If we would like to print out LSB register under big-endian,
3546 or print out MSB register under little-endian, we need to
3547 increase register number. */
3550 fputs (reg_names
[regno
], stream
);
3555 /* Forbid using static chain register ($r16)
3556 on reduced-set registers configuration. */
3557 if (TARGET_REDUCED_REGS
3558 && REGNO (x
) == STATIC_CHAIN_REGNUM
)
3559 sorry ("a nested function is not supported for reduced registers");
3561 /* Normal cases, print out register name. */
3562 fputs (reg_names
[REGNO (x
)], stream
);
3566 output_address (GET_MODE (x
), XEXP (x
, 0));
3570 if (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
)
3572 const REAL_VALUE_TYPE
*rv
;
3574 gcc_assert (GET_MODE (x
) == SFmode
);
3576 rv
= CONST_DOUBLE_REAL_VALUE (XEXP (x
, 0));
3577 REAL_VALUE_TO_TARGET_SINGLE (*rv
, val
);
3579 fprintf (stream
, "hi20(0x%lx)", val
);
3586 const REAL_VALUE_TYPE
*rv
;
3588 gcc_assert (GET_MODE (x
) == SFmode
);
3590 rv
= CONST_DOUBLE_REAL_VALUE (x
);
3591 REAL_VALUE_TO_TARGET_SINGLE (*rv
, val
);
3593 fprintf (stream
, "0x%lx", val
);
3599 output_addr_const (stream
, x
);
3603 fprintf (stream
, HOST_WIDE_INT_PRINT_HEX
, const_vector_to_hwint (x
));
3607 /* This is a special case for inline assembly using memory address 'p'.
3608 The inline assembly code is expected to use pesudo instruction
3609 for the operand. EX: la */
3610 output_addr_const (stream
, XEXP(x
, 1));
3614 /* Generally, output_addr_const () is able to handle most cases.
3615 We want to see what CODE could appear,
3616 so we use gcc_unreachable() to stop it. */
3624 nds32_print_operand_address (FILE *stream
,
3625 machine_mode mode ATTRIBUTE_UNUSED
,
3630 switch (GET_CODE (x
))
3634 /* [ + symbol_ref] */
3635 /* [ + const_addr], where const_addr = symbol_ref + const_int */
3636 fputs ("[ + ", stream
);
3637 output_addr_const (stream
, x
);
3638 fputs ("]", stream
);
3642 /* This is a special case for inline assembly using memory operand 'm'.
3643 The inline assembly code is expected to use pesudo instruction
3644 for the operand. EX: [ls].[bhw] */
3645 fputs ("[ + ", stream
);
3647 output_addr_const (stream
, op1
);
3648 fputs ("]", stream
);
3652 /* Forbid using static chain register ($r16)
3653 on reduced-set registers configuration. */
3654 if (TARGET_REDUCED_REGS
3655 && REGNO (x
) == STATIC_CHAIN_REGNUM
)
3656 sorry ("a nested function is not supported for reduced registers");
3659 fprintf (stream
, "[%s]", reg_names
[REGNO (x
)]);
3666 /* Checking op0, forbid using static chain register ($r16)
3667 on reduced-set registers configuration. */
3668 if (TARGET_REDUCED_REGS
3670 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
3671 sorry ("a nested function is not supported for reduced registers");
3672 /* Checking op1, forbid using static chain register ($r16)
3673 on reduced-set registers configuration. */
3674 if (TARGET_REDUCED_REGS
3676 && REGNO (op1
) == STATIC_CHAIN_REGNUM
)
3677 sorry ("a nested function is not supported for reduced registers");
3679 if (REG_P (op0
) && CONST_INT_P (op1
))
3682 fprintf (stream
, "[%s + (" HOST_WIDE_INT_PRINT_DEC
")]",
3683 reg_names
[REGNO (op0
)], INTVAL (op1
));
3685 else if (REG_P (op0
) && REG_P (op1
))
3688 fprintf (stream
, "[%s + %s]",
3689 reg_names
[REGNO (op0
)], reg_names
[REGNO (op1
)]);
3691 else if (GET_CODE (op0
) == MULT
&& REG_P (op1
))
3694 From observation, the pattern looks like:
3695 (plus:SI (mult:SI (reg:SI 58)
3696 (const_int 4 [0x4]))
3700 /* We need to set sv to output shift value. */
3701 if (INTVAL (XEXP (op0
, 1)) == 1)
3703 else if (INTVAL (XEXP (op0
, 1)) == 2)
3705 else if (INTVAL (XEXP (op0
, 1)) == 4)
3707 else if (INTVAL (XEXP (op0
, 1)) == 8)
3712 fprintf (stream
, "[%s + %s << %d]",
3713 reg_names
[REGNO (op1
)],
3714 reg_names
[REGNO (XEXP (op0
, 0))],
3717 else if (GET_CODE (op0
) == ASHIFT
&& REG_P (op1
))
3720 In normal, ASHIFT can be converted to MULT like above case.
3721 But when the address rtx does not go through canonicalize_address
3722 defined in fwprop, we'll need this case. */
3723 int sv
= INTVAL (XEXP (op0
, 1));
3724 gcc_assert (sv
<= 3 && sv
>=0);
3726 fprintf (stream
, "[%s + %s << %d]",
3727 reg_names
[REGNO (op1
)],
3728 reg_names
[REGNO (XEXP (op0
, 0))],
3733 /* The control flow is not supposed to be here. */
3741 /* (post_modify (regA) (plus (regA) (regB)))
3742 (post_modify (regA) (plus (regA) (const_int)))
3743 We would like to extract
3744 regA and regB (or const_int) from plus rtx. */
3745 op0
= XEXP (XEXP (x
, 1), 0);
3746 op1
= XEXP (XEXP (x
, 1), 1);
3748 /* Checking op0, forbid using static chain register ($r16)
3749 on reduced-set registers configuration. */
3750 if (TARGET_REDUCED_REGS
3752 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
3753 sorry ("a nested function is not supported for reduced registers");
3754 /* Checking op1, forbid using static chain register ($r16)
3755 on reduced-set registers configuration. */
3756 if (TARGET_REDUCED_REGS
3758 && REGNO (op1
) == STATIC_CHAIN_REGNUM
)
3759 sorry ("a nested function is not supported for reduced registers");
3761 if (REG_P (op0
) && REG_P (op1
))
3764 fprintf (stream
, "[%s], %s",
3765 reg_names
[REGNO (op0
)], reg_names
[REGNO (op1
)]);
3767 else if (REG_P (op0
) && CONST_INT_P (op1
))
3770 fprintf (stream
, "[%s], " HOST_WIDE_INT_PRINT_DEC
,
3771 reg_names
[REGNO (op0
)], INTVAL (op1
));
3775 /* The control flow is not supposed to be here. */
3786 /* Checking op0, forbid using static chain register ($r16)
3787 on reduced-set registers configuration. */
3788 if (TARGET_REDUCED_REGS
3790 && REGNO (op0
) == STATIC_CHAIN_REGNUM
)
3791 sorry ("a nested function is not supported for reduced registers");
3795 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4"
3796 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md.
3797 We only need to deal with register Ra. */
3798 fprintf (stream
, "[%s]", reg_names
[REGNO (op0
)]);
3802 /* The control flow is not supposed to be here. */
3810 /* Generally, output_addr_const () is able to handle most cases.
3811 We want to see what CODE could appear,
3812 so we use gcc_unreachable() to stop it. */
3819 /* -- Assembler Commands for Exception Regions. */
3822 nds32_dwarf_register_span (rtx reg
)
3824 rtx dwarf_high
, dwarf_low
;
3829 mode
= GET_MODE (reg
);
3830 regno
= REGNO (reg
);
3832 /* We need to adjust dwarf register information for floating-point registers
3833 rather than using default register number mapping. */
3834 if (regno
>= NDS32_FIRST_FPR_REGNUM
3835 && regno
<= NDS32_LAST_FPR_REGNUM
)
3837 if (mode
== DFmode
|| mode
== SCmode
)
3839 /* By default, GCC maps increasing register numbers to increasing
3840 memory locations, but paired FPRs in NDS32 target are always
3846 We must return parallel rtx to represent such layout. */
3847 dwarf_high
= gen_rtx_REG (word_mode
, regno
);
3848 dwarf_low
= gen_rtx_REG (word_mode
, regno
+ 1);
3849 return gen_rtx_PARALLEL (VOIDmode
,
3850 gen_rtvec (2, dwarf_low
, dwarf_high
));
3852 else if (mode
== DCmode
)
3854 rtx dwarf_high_re
= gen_rtx_REG (word_mode
, regno
);
3855 rtx dwarf_low_re
= gen_rtx_REG (word_mode
, regno
+ 1);
3856 rtx dwarf_high_im
= gen_rtx_REG (word_mode
, regno
);
3857 rtx dwarf_low_im
= gen_rtx_REG (word_mode
, regno
+ 1);
3858 return gen_rtx_PARALLEL (VOIDmode
,
3859 gen_rtvec (4, dwarf_low_re
, dwarf_high_re
,
3860 dwarf_high_im
, dwarf_low_im
));
3862 else if (mode
== SFmode
|| mode
== SImode
)
3864 /* Create new dwarf information with adjusted register number. */
3865 dwarf_single
= gen_rtx_REG (word_mode
, regno
);
3866 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, dwarf_single
));
3870 /* We should not be here. */
3878 /* Map internal gcc register numbers to DWARF2 register numbers. */
3881 nds32_dbx_register_number (unsigned int regno
)
3883 /* The nds32 port in GDB maintains a mapping between dwarf register
3884 number and displayed register name. For backward compatibility to
3885 previous toolchain, currently our gdb still has four registers
3886 (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler
3887 does not count those four registers in its register number table.
3888 So we have to add 4 on its register number and then create new
3889 dwarf information. Hopefully we can discard such workaround
3891 if (NDS32_IS_FPR_REGNUM (regno
))
3898 /* Defining target-specific uses of __attribute__. */
3900 /* Add some checking after merging attributes. */
3902 nds32_merge_decl_attributes (tree olddecl
, tree newdecl
)
3904 tree combined_attrs
;
3906 /* Create combined attributes. */
3907 combined_attrs
= merge_attributes (DECL_ATTRIBUTES (olddecl
),
3908 DECL_ATTRIBUTES (newdecl
));
3910 /* Since newdecl is acutally a duplicate of olddecl,
3911 we can take olddecl for some operations. */
3912 if (TREE_CODE (olddecl
) == FUNCTION_DECL
)
3914 /* Check isr-specific attributes conflict. */
3915 nds32_check_isr_attrs_conflict (olddecl
, combined_attrs
);
3918 return combined_attrs
;
3921 /* Add some checking when inserting attributes. */
3923 nds32_insert_attributes (tree decl
, tree
*attributes
)
3925 /* A "indirect_call" function attribute implies "noinline" and "noclone"
3926 for elf toolchain to support ROM patch mechanism. */
3927 if (TREE_CODE (decl
) == FUNCTION_DECL
3928 && lookup_attribute ("indirect_call", *attributes
) != NULL
)
3930 tree new_attrs
= *attributes
;
3932 if (TARGET_LINUX_ABI
)
3933 error("cannot use indirect_call attribute under linux toolchain");
3935 if (lookup_attribute ("noinline", new_attrs
) == NULL
)
3936 new_attrs
= tree_cons (get_identifier ("noinline"), NULL
, new_attrs
);
3937 if (lookup_attribute ("noclone", new_attrs
) == NULL
)
3938 new_attrs
= tree_cons (get_identifier ("noclone"), NULL
, new_attrs
);
3940 if (!TREE_PUBLIC (decl
))
3941 error("indirect_call attribute can't apply for static function");
3943 *attributes
= new_attrs
;
3946 /* For function declaration, we need to check isr-specific attributes:
3947 1. Call nds32_check_isr_attrs_conflict() to check any conflict.
3948 2. Check valid integer value for interrupt/exception.
3949 3. Check valid integer value for reset.
3950 4. Check valid function for nmi/warm. */
3951 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3954 tree intr
, excp
, reset
;
3956 /* Pick up function attributes. */
3957 func_attrs
= *attributes
;
3959 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */
3960 nds32_check_isr_attrs_conflict (decl
, func_attrs
);
3962 /* Now we are starting to check valid id value
3963 for interrupt/exception/reset.
3964 Note that we ONLY check its validity here.
3965 To construct isr vector information, it is still performed
3966 by nds32_construct_isr_vectors_information(). */
3967 intr
= lookup_attribute ("interrupt", func_attrs
);
3968 excp
= lookup_attribute ("exception", func_attrs
);
3969 reset
= lookup_attribute ("reset", func_attrs
);
3973 /* Deal with interrupt/exception. */
3975 unsigned int lower_bound
, upper_bound
;
3977 /* The way to handle interrupt or exception is the same,
3978 we just need to take care of actual vector number.
3979 For interrupt(0..63), the actual vector number is (9..72).
3980 For exception(1..8), the actual vector number is (1..8). */
3981 lower_bound
= (intr
) ? (0) : (1);
3982 upper_bound
= (intr
) ? (63) : (8);
3984 /* Prepare id list so that we can traverse id value. */
3985 id_list
= (intr
) ? (TREE_VALUE (intr
)) : (TREE_VALUE (excp
));
3987 /* 2. Check valid integer value for interrupt/exception. */
3992 /* Pick up each vector id value. */
3993 id
= TREE_VALUE (id_list
);
3994 /* Issue error if it is not a valid integer value. */
3995 if (TREE_CODE (id
) != INTEGER_CST
3996 || wi::ltu_p (wi::to_wide (id
), lower_bound
)
3997 || wi::gtu_p (wi::to_wide (id
), upper_bound
))
3998 error ("invalid id value for interrupt/exception attribute");
4000 /* Advance to next id. */
4001 id_list
= TREE_CHAIN (id_list
);
4006 /* Deal with reset. */
4010 unsigned int lower_bound
;
4011 unsigned int upper_bound
;
4013 /* Prepare id_list and identify id value so that
4014 we can check if total number of vectors is valid. */
4015 id_list
= TREE_VALUE (reset
);
4016 id
= TREE_VALUE (id_list
);
4018 /* The maximum numbers for user's interrupt is 64. */
4022 /* 3. Check valid integer value for reset. */
4023 if (TREE_CODE (id
) != INTEGER_CST
4024 || wi::ltu_p (wi::to_wide (id
), lower_bound
)
4025 || wi::gtu_p (wi::to_wide (id
), upper_bound
))
4026 error ("invalid id value for reset attribute");
4028 /* 4. Check valid function for nmi/warm. */
4029 nmi
= lookup_attribute ("nmi", func_attrs
);
4030 warm
= lookup_attribute ("warm", func_attrs
);
4032 if (nmi
!= NULL_TREE
)
4037 nmi_func_list
= TREE_VALUE (nmi
);
4038 nmi_func
= TREE_VALUE (nmi_func_list
);
4040 /* Issue error if it is not a valid nmi function. */
4041 if (TREE_CODE (nmi_func
) != IDENTIFIER_NODE
)
4042 error ("invalid nmi function for reset attribute");
4045 if (warm
!= NULL_TREE
)
4047 tree warm_func_list
;
4050 warm_func_list
= TREE_VALUE (warm
);
4051 warm_func
= TREE_VALUE (warm_func_list
);
4053 /* Issue error if it is not a valid warm function. */
4054 if (TREE_CODE (warm_func
) != IDENTIFIER_NODE
)
4055 error ("invalid warm function for reset attribute");
4060 /* No interrupt, exception, or reset attribute is set. */
4067 nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED
,
4068 tree pop_target ATTRIBUTE_UNUSED
)
4070 /* Currently, we do not parse any pragma target by ourself,
4071 so just simply return false. */
4076 nds32_option_override (void)
4078 /* After all the command options have been parsed,
4079 we shall deal with some flags for changing compiler settings. */
4081 /* At first, we check if we have to strictly
4082 set some flags based on ISA family. */
4085 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */
4086 target_flags
&= ~MASK_V3PUSH
;
4090 /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */
4091 if (nds32_arch_option
== ARCH_V3J
)
4092 target_flags
|= MASK_REDUCED_REGS
;
4096 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
4097 target_flags
|= MASK_REDUCED_REGS
;
4098 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
4099 target_flags
&= ~MASK_EXT_PERF
;
4100 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
4101 target_flags
&= ~MASK_EXT_PERF2
;
4102 /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
4103 target_flags
&= ~MASK_EXT_STRING
;
4106 error ("not support -fpic option for v3m toolchain");
4109 /* See if we are using reduced-set registers:
4110 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31
4111 If so, we must forbid using $r11~$r14, $r16~$r27. */
4112 if (TARGET_REDUCED_REGS
)
4116 /* Prevent register allocator from
4117 choosing it as doing register allocation. */
4118 for (r
= 11; r
<= 14; r
++)
4119 fixed_regs
[r
] = call_used_regs
[r
] = 1;
4120 for (r
= 16; r
<= 27; r
++)
4121 fixed_regs
[r
] = call_used_regs
[r
] = 1;
4124 /* See if user explicitly would like to use fp-as-gp optimization.
4125 If so, we must prevent $fp from being allocated
4126 during register allocation. */
4127 if (TARGET_FORCE_FP_AS_GP
)
4128 fixed_regs
[FP_REGNUM
] = call_used_regs
[FP_REGNUM
] = 1;
4132 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */
4133 target_flags
&= ~MASK_V3PUSH
;
4136 if (TARGET_HARD_FLOAT
&& !(TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
))
4138 if (nds32_arch_option
== ARCH_V3S
|| nds32_arch_option
== ARCH_V3F
)
4139 error ("Disable FPU ISA, "
4140 "the ABI option must be enable '-mfloat-abi=soft'");
4142 error ("'-mabi=2fp+' option only support when FPU available, "
4143 "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'");
4146 nds32_init_rtx_costs ();
4148 nds32_register_passes ();
4152 /* Miscellaneous Parameters. */
4155 nds32_md_asm_adjust (vec
<rtx
> &outputs ATTRIBUTE_UNUSED
,
4156 vec
<rtx
> &inputs ATTRIBUTE_UNUSED
,
4157 vec
<const char *> &constraints ATTRIBUTE_UNUSED
,
4158 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
4160 if (!flag_inline_asm_r15
)
4162 clobbers
.safe_push (gen_rtx_REG (SImode
, TA_REGNUM
));
4163 SET_HARD_REG_BIT (clobbered_regs
, TA_REGNUM
);
4169 nds32_init_builtins (void)
4171 nds32_init_builtins_impl ();
4175 nds32_builtin_decl (unsigned code
, bool initialize_p
)
4177 /* Implement in nds32-intrinsic.c. */
4178 return nds32_builtin_decl_impl (code
, initialize_p
);
4182 nds32_expand_builtin (tree exp
,
4188 return nds32_expand_builtin_impl (exp
, target
, subtarget
, mode
, ignore
);
4191 /* Implement TARGET_INIT_LIBFUNCS. */
4193 nds32_init_libfuncs (void)
4195 if (TARGET_LINUX_ABI
)
4196 init_sync_libfuncs (UNITS_PER_WORD
);
4199 /* ------------------------------------------------------------------------ */
4201 /* PART 4: Implemet extern function definitions,
4202 the prototype is in nds32-protos.h. */
4204 /* Run-time Target Specification. */
4207 nds32_cpu_cpp_builtins(struct cpp_reader
*pfile
)
4209 #define builtin_define(TXT) cpp_define (pfile, TXT)
4210 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
4211 builtin_define ("__nds32__");
4212 builtin_define ("__NDS32__");
4214 if (TARGET_HARD_FLOAT
)
4215 builtin_define ("__NDS32_ABI_2FP_PLUS__");
4217 builtin_define ("__NDS32_ABI_2__");
4220 builtin_define ("__NDS32_ISA_V2__");
4222 builtin_define ("__NDS32_ISA_V3__");
4224 builtin_define ("__NDS32_ISA_V3M__");
4226 if (TARGET_FPU_SINGLE
)
4227 builtin_define ("__NDS32_EXT_FPU_SP__");
4228 if (TARGET_FPU_DOUBLE
)
4229 builtin_define ("__NDS32_EXT_FPU_DP__");
4231 if (TARGET_EXT_FPU_FMA
)
4232 builtin_define ("__NDS32_EXT_FPU_FMA__");
4233 if (NDS32_EXT_FPU_DOT_E
)
4234 builtin_define ("__NDS32_EXT_FPU_DOT_E__");
4235 if (TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
4237 switch (nds32_fp_regnum
)
4241 builtin_define ("__NDS32_EXT_FPU_CONFIG_0__");
4245 builtin_define ("__NDS32_EXT_FPU_CONFIG_1__");
4249 builtin_define ("__NDS32_EXT_FPU_CONFIG_2__");
4253 builtin_define ("__NDS32_EXT_FPU_CONFIG_3__");
4260 if (TARGET_BIG_ENDIAN
)
4261 builtin_define ("__NDS32_EB__");
4263 builtin_define ("__NDS32_EL__");
4265 if (TARGET_REDUCED_REGS
)
4266 builtin_define ("__NDS32_REDUCED_REGS__");
4268 builtin_define ("__NDS32_CMOV__");
4269 if (TARGET_EXT_PERF
)
4270 builtin_define ("__NDS32_EXT_PERF__");
4271 if (TARGET_EXT_PERF2
)
4272 builtin_define ("__NDS32_EXT_PERF2__");
4273 if (TARGET_EXT_STRING
)
4274 builtin_define ("__NDS32_EXT_STRING__");
4276 builtin_define ("__NDS32_16_BIT__");
4277 if (TARGET_GP_DIRECT
)
4278 builtin_define ("__NDS32_GP_DIRECT__");
4280 builtin_define ("__NDS32_VH__");
4281 if (NDS32_EXT_DSP_P ())
4282 builtin_define ("__NDS32_EXT_DSP__");
4284 if (TARGET_BIG_ENDIAN
)
4285 builtin_define ("__big_endian__");
4287 builtin_assert ("cpu=nds32");
4288 builtin_assert ("machine=nds32");
4290 if (TARGET_HARD_FLOAT
)
4291 builtin_define ("__NDS32_ABI_2FP_PLUS");
4293 builtin_define ("__NDS32_ABI_2");
4295 #undef builtin_define
4296 #undef builtin_assert
4300 /* Defining Data Structures for Per-function Information. */
4303 nds32_init_expanders (void)
4305 /* Arrange to initialize and mark the machine per-function status. */
4306 init_machine_status
= nds32_init_machine_status
;
4310 /* Register Usage. */
4312 /* -- Order of Allocation of Registers. */
4315 nds32_adjust_reg_alloc_order (void)
4317 const int nds32_reg_alloc_order
[] = REG_ALLOC_ORDER
;
4319 /* Copy the default register allocation order, which is designed
4320 to optimize for code size. */
4321 memcpy(reg_alloc_order
, nds32_reg_alloc_order
, sizeof (reg_alloc_order
));
4323 /* Adjust few register allocation order when optimizing for speed. */
4326 memcpy (reg_alloc_order
, nds32_reg_alloc_order_for_speed
,
4327 sizeof (nds32_reg_alloc_order_for_speed
));
4331 /* -- How Values Fit in Registers. */
4334 nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED
,
4337 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
4340 /* Implement TARGET_HARD_REGNO_MODE_OK. */
4343 nds32_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
4345 if (regno
>= FIRST_PSEUDO_REGISTER
)
4348 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
) && NDS32_IS_FPR_REGNUM (regno
))
4350 if (NDS32_IS_EXT_FPR_REGNUM(regno
))
4351 return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno
) && (mode
== DFmode
));
4352 else if (mode
== SFmode
|| mode
== SImode
)
4353 return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno
);
4354 else if (mode
== DFmode
)
4355 return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno
);
4360 /* Restrict double-word quantities to even register pairs. */
4361 if (regno
<= NDS32_LAST_GPR_REGNUM
)
4362 return (targetm
.hard_regno_nregs (regno
, mode
) == 1
4368 /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to
4369 tie QI/HI/SI modes together. */
4372 nds32_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4374 if ((GET_MODE_CLASS (mode1
) == MODE_INT
4375 && GET_MODE_CLASS (mode2
) == MODE_INT
)
4376 && GET_MODE_SIZE (mode1
) <= UNITS_PER_WORD
4377 && GET_MODE_SIZE (mode2
) <= UNITS_PER_WORD
)
4380 if (GET_MODE_SIZE (mode1
) == GET_MODE_SIZE (mode2
))
4382 if ((TARGET_FPU_SINGLE
&& !TARGET_FPU_DOUBLE
)
4383 && (mode1
== DFmode
|| mode2
== DFmode
))
4392 /* Register Classes. */
4395 nds32_regno_reg_class (int regno
)
4397 /* Refer to nds32.h for more register class details. */
4399 if (regno
>= 0 && regno
<= 7)
4401 else if (regno
>= 8 && regno
<= 11)
4403 else if (regno
>= 12 && regno
<= 14)
4405 else if (regno
== 15)
4407 else if (regno
>= 16 && regno
<= 19)
4409 else if (regno
>= 20 && regno
<= 31)
4411 else if (regno
== 32 || regno
== 33)
4413 /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't
4414 know how to allocate register for $SFP and $AP, just tell IRA they
4415 are GENERAL_REGS, and ARM do this hack too. */
4416 return GENERAL_REGS
;
4418 else if (regno
>= 34 && regno
<= 97)
4425 /* Stack Layout and Calling Conventions. */
4427 /* -- Basic Stack Layout. */
4430 nds32_dynamic_chain_address (rtx frameaddr
)
4434 /* If -mv3push is specified, we push $fp, $gp, and $lp into stack.
4435 We can access dynamic chain address from stack by [$fp - 12]. */
4436 return plus_constant (Pmode
, frameaddr
, -12);
4440 /* For general case we push $fp and $lp into stack at prologue.
4441 We can access dynamic chain address from stack by [$fp - 8]. */
4442 return plus_constant (Pmode
, frameaddr
, -8);
4447 nds32_return_addr_rtx (int count
,
4455 /* In nds32 ABI design, we can expect that $lp is always available
4456 from stack by [$fp - 4] location. */
4458 addr
= plus_constant (Pmode
, frameaddr
, offset
);
4459 addr
= memory_address (Pmode
, addr
);
4461 return gen_rtx_MEM (Pmode
, addr
);
4464 /* If count == 0, it means we are at current frame,
4465 the return address is $r30 ($lp). */
4466 return get_hard_reg_initial_val (Pmode
, LP_REGNUM
);
4469 /* -- Eliminating Frame Pointer and Arg Pointer. */
4472 nds32_initial_elimination_offset (unsigned int from_reg
, unsigned int to_reg
)
4474 HOST_WIDE_INT offset
;
4476 /* Compute and setup stack frame size.
4477 The result will be in cfun->machine. */
4478 nds32_compute_stack_frame ();
4480 /* Remember to consider
4481 cfun->machine->callee_saved_area_gpr_padding_bytes and
4482 cfun->machine->eh_return_data_regs_size
4483 when calculating offset. */
4484 if (from_reg
== ARG_POINTER_REGNUM
&& to_reg
== STACK_POINTER_REGNUM
)
4486 offset
= (cfun
->machine
->fp_size
4487 + cfun
->machine
->gp_size
4488 + cfun
->machine
->lp_size
4489 + cfun
->machine
->callee_saved_gpr_regs_size
4490 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4491 + cfun
->machine
->callee_saved_fpr_regs_size
4492 + cfun
->machine
->eh_return_data_regs_size
4493 + cfun
->machine
->local_size
4494 + cfun
->machine
->out_args_size
);
4496 else if (from_reg
== ARG_POINTER_REGNUM
4497 && to_reg
== HARD_FRAME_POINTER_REGNUM
)
4501 else if (from_reg
== FRAME_POINTER_REGNUM
4502 && to_reg
== STACK_POINTER_REGNUM
)
4504 offset
= (cfun
->machine
->local_size
+ cfun
->machine
->out_args_size
);
4506 else if (from_reg
== FRAME_POINTER_REGNUM
4507 && to_reg
== HARD_FRAME_POINTER_REGNUM
)
4509 offset
= (-1) * (cfun
->machine
->fp_size
4510 + cfun
->machine
->gp_size
4511 + cfun
->machine
->lp_size
4512 + cfun
->machine
->callee_saved_gpr_regs_size
4513 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4514 + cfun
->machine
->callee_saved_fpr_regs_size
4515 + cfun
->machine
->eh_return_data_regs_size
);
4525 /* -- Passing Arguments in Registers. */
4528 nds32_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
4529 tree fntype ATTRIBUTE_UNUSED
,
4530 rtx libname ATTRIBUTE_UNUSED
,
4531 tree fndecl ATTRIBUTE_UNUSED
,
4532 int n_named_args ATTRIBUTE_UNUSED
)
4534 /* Initial available registers. The values are offset against
4535 NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM
4536 for passing arguments. */
4537 cum
->gpr_offset
= 0;
4538 cum
->fpr_offset
= 0;
4541 /* -- Function Entry and Exit. */
4543 /* Function for normal multiple push prologue. */
4545 nds32_expand_prologue (void)
4551 /* Compute and setup stack frame size.
4552 The result will be in cfun->machine. */
4553 nds32_compute_stack_frame ();
4555 /* Check frame_pointer_needed again to prevent fp is need after reload. */
4556 if (frame_pointer_needed
)
4557 cfun
->machine
->fp_as_gp_p
= false;
4559 /* If this is a variadic function, first we need to push argument
4560 registers that hold the unnamed argument value. */
4561 if (cfun
->machine
->va_args_size
!= 0)
4563 Rb
= cfun
->machine
->va_args_first_regno
;
4564 Re
= cfun
->machine
->va_args_last_regno
;
4565 /* No need to push $fp, $gp, or $lp. */
4566 nds32_emit_stack_push_multiple (Rb
, Re
, false, false, false, true);
4568 /* We may also need to adjust stack pointer for padding bytes
4569 because varargs may cause $sp not 8-byte aligned. */
4570 if (cfun
->machine
->va_args_area_padding_bytes
)
4572 /* Generate sp adjustment instruction. */
4573 sp_adjust
= cfun
->machine
->va_args_area_padding_bytes
;
4575 nds32_emit_adjust_frame (stack_pointer_rtx
,
4581 /* If the function is 'naked',
4582 we do not have to generate prologue code fragment. */
4583 if (cfun
->machine
->naked_p
&& !flag_pic
)
4586 /* Get callee_first_regno and callee_last_regno. */
4587 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
4588 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
4590 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4591 to be saved, we don't have to create multiple push instruction.
4592 Otherwise, a multiple push instruction is needed. */
4593 if (!(Rb
== SP_REGNUM
&& Re
== SP_REGNUM
4594 && cfun
->machine
->fp_size
== 0
4595 && cfun
->machine
->gp_size
== 0
4596 && cfun
->machine
->lp_size
== 0))
4598 /* Create multiple push instruction rtx. */
4599 nds32_emit_stack_push_multiple (
4601 cfun
->machine
->fp_size
, cfun
->machine
->gp_size
, cfun
->machine
->lp_size
,
4605 /* Save eh data registers. */
4606 if (cfun
->machine
->use_eh_return_p
)
4608 Rb
= cfun
->machine
->eh_return_data_first_regno
;
4609 Re
= cfun
->machine
->eh_return_data_last_regno
;
4611 /* No need to push $fp, $gp, or $lp.
4612 Also, this is not variadic arguments push. */
4613 nds32_emit_stack_push_multiple (Rb
, Re
, false, false, false, false);
4616 /* Check frame_pointer_needed to see
4617 if we shall emit fp adjustment instruction. */
4618 if (frame_pointer_needed
)
4620 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size)
4621 + (4 * callee-saved-registers)
4622 + (4 * exception-handling-data-registers)
4623 Note: No need to adjust
4624 cfun->machine->callee_saved_area_gpr_padding_bytes,
4625 because, at this point, stack pointer is just
4626 at the position after push instruction. */
4627 fp_adjust
= cfun
->machine
->fp_size
4628 + cfun
->machine
->gp_size
4629 + cfun
->machine
->lp_size
4630 + cfun
->machine
->callee_saved_gpr_regs_size
4631 + cfun
->machine
->eh_return_data_regs_size
;
4633 nds32_emit_adjust_frame (hard_frame_pointer_rtx
,
4638 /* Save fpu registers. */
4639 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4641 /* When $sp moved to bottom of stack, we need to check whether
4642 the range of offset in the FPU instruction. */
4643 int fpr_offset
= cfun
->machine
->local_size
4644 + cfun
->machine
->out_args_size
4645 + cfun
->machine
->callee_saved_fpr_regs_size
;
4647 /* Check FPU instruction offset imm14s. */
4648 if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset
)))
4650 int fpr_space
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
4651 + cfun
->machine
->callee_saved_fpr_regs_size
;
4653 /* Save fpu registers, need to allocate stack space
4654 for fpu callee registers. And now $sp position
4655 on callee saved fpr registers. */
4656 nds32_emit_adjust_frame (stack_pointer_rtx
,
4660 /* Emit fpu store instruction, using [$sp + offset] store
4662 nds32_emit_push_fpr_callee_saved (0);
4664 /* Adjust $sp = $sp - local_size - out_args_size. */
4665 sp_adjust
= cfun
->machine
->local_size
4666 + cfun
->machine
->out_args_size
;
4668 /* Allocate stack space for local size and out args size. */
4669 nds32_emit_adjust_frame (stack_pointer_rtx
,
4675 /* Offset range in Is14, so $sp moved to bottom of stack. */
4677 /* Adjust $sp = $sp - local_size - out_args_size
4678 - callee_saved_area_gpr_padding_bytes
4679 - callee_saved_fpr_regs_size. */
4680 sp_adjust
= cfun
->machine
->local_size
4681 + cfun
->machine
->out_args_size
4682 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4683 + cfun
->machine
->callee_saved_fpr_regs_size
;
4685 nds32_emit_adjust_frame (stack_pointer_rtx
,
4689 /* Emit fpu store instruction, using [$sp + offset] store
4691 int fpr_position
= cfun
->machine
->out_args_size
4692 + cfun
->machine
->local_size
;
4693 nds32_emit_push_fpr_callee_saved (fpr_position
);
4698 /* Adjust $sp = $sp - local_size - out_args_size
4699 - callee_saved_area_gpr_padding_bytes. */
4700 sp_adjust
= cfun
->machine
->local_size
4701 + cfun
->machine
->out_args_size
4702 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4704 /* sp_adjust value may be out of range of the addi instruction,
4705 create alternative add behavior with TA_REGNUM if necessary,
4706 using NEGATIVE value to tell that we are decreasing address. */
4707 nds32_emit_adjust_frame (stack_pointer_rtx
,
4712 /* Emit gp setup instructions for -fpic. */
4713 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
4714 nds32_emit_load_gp ();
4716 /* Prevent the instruction scheduler from
4717 moving instructions across the boundary. */
4718 emit_insn (gen_blockage ());
4721 /* Function for normal multiple pop epilogue. */
4723 nds32_expand_epilogue (bool sibcall_p
)
4728 /* Compute and setup stack frame size.
4729 The result will be in cfun->machine. */
4730 nds32_compute_stack_frame ();
4732 /* Prevent the instruction scheduler from
4733 moving instructions across the boundary. */
4734 emit_insn (gen_blockage ());
4736 /* If the function is 'naked', we do not have to generate
4737 epilogue code fragment BUT 'ret' instruction.
4738 However, if this function is also a variadic function,
4739 we need to create adjust stack pointer before 'ret' instruction. */
4740 if (cfun
->machine
->naked_p
)
4742 /* If this is a variadic function, we do not have to restore argument
4743 registers but need to adjust stack pointer back to previous stack
4744 frame location before return. */
4745 if (cfun
->machine
->va_args_size
!= 0)
4747 /* Generate sp adjustment instruction.
4748 We need to consider padding bytes here. */
4749 sp_adjust
= cfun
->machine
->va_args_size
4750 + cfun
->machine
->va_args_area_padding_bytes
;
4752 nds32_emit_adjust_frame (stack_pointer_rtx
,
4757 /* Generate return instruction by using 'return_internal' pattern.
4758 Make sure this instruction is after gen_blockage(). */
4761 /* We need to further check attributes to determine whether
4762 there should be return instruction at epilogue.
4763 If the attribute naked exists but -mno-ret-in-naked-func
4764 is issued, there is NO need to generate return instruction. */
4765 if (cfun
->machine
->attr_naked_p
&& !flag_ret_in_naked_func
)
4768 emit_jump_insn (gen_return_internal ());
4773 if (frame_pointer_needed
)
4775 /* Restore fpu registers. */
4776 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4778 int gpr_padding
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4780 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4781 - (4 * callee-saved-registers)
4782 - (4 * exception-handling-data-registers)
4783 - (4 * callee-saved-gpr-registers padding byte)
4784 - (4 * callee-saved-fpr-registers)
4785 Note: we want to adjust stack pointer
4786 to the position for callee-saved fpr register,
4787 And restore fpu register use .bi instruction to adjust $sp
4788 from callee-saved fpr register to pop instruction. */
4789 sp_adjust
= cfun
->machine
->fp_size
4790 + cfun
->machine
->gp_size
4791 + cfun
->machine
->lp_size
4792 + cfun
->machine
->callee_saved_gpr_regs_size
4793 + cfun
->machine
->eh_return_data_regs_size
4794 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4795 + cfun
->machine
->callee_saved_fpr_regs_size
;
4797 nds32_emit_adjust_frame (stack_pointer_rtx
,
4798 hard_frame_pointer_rtx
,
4801 /* Emit fpu load instruction, using .bi instruction
4802 load fpu registers. */
4803 nds32_emit_pop_fpr_callee_saved (gpr_padding
);
4807 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size)
4808 - (4 * callee-saved-registers)
4809 - (4 * exception-handling-data-registers)
4810 Note: No need to adjust
4811 cfun->machine->callee_saved_area_gpr_padding_bytes,
4812 because we want to adjust stack pointer
4813 to the position for pop instruction. */
4814 sp_adjust
= cfun
->machine
->fp_size
4815 + cfun
->machine
->gp_size
4816 + cfun
->machine
->lp_size
4817 + cfun
->machine
->callee_saved_gpr_regs_size
4818 + cfun
->machine
->eh_return_data_regs_size
;
4820 nds32_emit_adjust_frame (stack_pointer_rtx
,
4821 hard_frame_pointer_rtx
,
4827 /* Restore fpu registers. */
4828 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4830 int gpr_padding
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4832 /* Adjust $sp = $sp + local_size + out_args_size. */
4833 sp_adjust
= cfun
->machine
->local_size
4834 + cfun
->machine
->out_args_size
;
4836 nds32_emit_adjust_frame (stack_pointer_rtx
,
4840 /* Emit fpu load instruction, using .bi instruction
4841 load fpu registers, and adjust $sp from callee-saved fpr register
4842 to callee-saved gpr register. */
4843 nds32_emit_pop_fpr_callee_saved (gpr_padding
);
4847 /* If frame pointer is NOT needed,
4848 we cannot calculate the sp adjustment from frame pointer.
4849 Instead, we calculate the adjustment by local_size,
4850 out_args_size, and callee_saved_area_gpr_padding_bytes.
4851 Notice that such sp adjustment value may be out of range,
4852 so we have to deal with it as well. */
4854 /* Adjust $sp = $sp + local_size + out_args_size
4855 + callee_saved_area_gpr_padding_bytes. */
4856 sp_adjust
= cfun
->machine
->local_size
4857 + cfun
->machine
->out_args_size
4858 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
;
4860 nds32_emit_adjust_frame (stack_pointer_rtx
,
4866 /* Restore eh data registers. */
4867 if (cfun
->machine
->use_eh_return_p
)
4869 Rb
= cfun
->machine
->eh_return_data_first_regno
;
4870 Re
= cfun
->machine
->eh_return_data_last_regno
;
4872 /* No need to pop $fp, $gp, or $lp. */
4873 nds32_emit_stack_pop_multiple (Rb
, Re
, false, false, false);
4876 /* Get callee_first_regno and callee_last_regno. */
4877 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
4878 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
4880 /* If $fp, $gp, $lp, and all callee-save registers are NOT required
4881 to be saved, we don't have to create multiple pop instruction.
4882 Otherwise, a multiple pop instruction is needed. */
4883 if (!(Rb
== SP_REGNUM
&& Re
== SP_REGNUM
4884 && cfun
->machine
->fp_size
== 0
4885 && cfun
->machine
->gp_size
== 0
4886 && cfun
->machine
->lp_size
== 0))
4888 /* Create multiple pop instruction rtx. */
4889 nds32_emit_stack_pop_multiple (
4891 cfun
->machine
->fp_size
, cfun
->machine
->gp_size
, cfun
->machine
->lp_size
);
4894 /* If this is a variadic function, we do not have to restore argument
4895 registers but need to adjust stack pointer back to previous stack
4896 frame location before return. */
4897 if (cfun
->machine
->va_args_size
!= 0)
4899 /* Generate sp adjustment instruction.
4900 We need to consider padding bytes here. */
4901 sp_adjust
= cfun
->machine
->va_args_size
4902 + cfun
->machine
->va_args_area_padding_bytes
;
4904 nds32_emit_adjust_frame (stack_pointer_rtx
,
4909 /* If this function uses __builtin_eh_return, make stack adjustment
4910 for exception handler. */
4911 if (cfun
->machine
->use_eh_return_p
)
4913 /* We need to unwind the stack by the offset computed by
4914 EH_RETURN_STACKADJ_RTX. However, at this point the CFA is
4915 based on SP. Ideally we would update the SP and define the
4916 CFA along the lines of:
4918 SP = SP + EH_RETURN_STACKADJ_RTX
4919 (regnote CFA = SP - EH_RETURN_STACKADJ_RTX)
4921 However the dwarf emitter only understands a constant
4924 The solution chosen here is to use the otherwise $ta ($r15)
4925 as a temporary register to hold the current SP value. The
4926 CFA is described using $ta then SP is modified. */
4931 ta_reg
= gen_rtx_REG (SImode
, TA_REGNUM
);
4933 insn
= emit_move_insn (ta_reg
, stack_pointer_rtx
);
4934 add_reg_note (insn
, REG_CFA_DEF_CFA
, ta_reg
);
4935 RTX_FRAME_RELATED_P (insn
) = 1;
4937 emit_insn (gen_addsi3 (stack_pointer_rtx
,
4939 EH_RETURN_STACKADJ_RTX
));
4941 /* Ensure the assignment to $ta does not get optimized away. */
4945 /* Generate return instruction. */
4947 emit_jump_insn (gen_return_internal ());
4950 /* Function for v3push prologue. */
4952 nds32_expand_prologue_v3push (void)
4959 /* Compute and setup stack frame size.
4960 The result will be in cfun->machine. */
4961 nds32_compute_stack_frame ();
4963 if (cfun
->machine
->callee_saved_gpr_regs_size
> 0)
4964 df_set_regs_ever_live (FP_REGNUM
, 1);
4966 /* Check frame_pointer_needed again to prevent fp is need after reload. */
4967 if (frame_pointer_needed
)
4968 cfun
->machine
->fp_as_gp_p
= false;
4970 /* If the function is 'naked',
4971 we do not have to generate prologue code fragment. */
4972 if (cfun
->machine
->naked_p
&& !flag_pic
)
4975 /* Get callee_first_regno and callee_last_regno. */
4976 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
4977 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
4979 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available,
4980 where imm8u has to be 8-byte alignment. */
4981 sp_adjust
= cfun
->machine
->local_size
4982 + cfun
->machine
->out_args_size
4983 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
4984 + cfun
->machine
->callee_saved_fpr_regs_size
;
4986 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
4987 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
))
4989 /* We can use 'push25 Re,imm8u'. */
4991 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
4992 the pattern 'stack_v3push' is implemented in nds32.md. */
4993 nds32_emit_stack_v3push (Rb
, Re
, sp_adjust
);
4995 /* Save fpu registers. */
4996 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
4998 /* Calculate fpr position. */
4999 int fpr_position
= cfun
->machine
->local_size
5000 + cfun
->machine
->out_args_size
;
5001 /* Emit fpu store instruction, using [$sp + offset] store
5003 nds32_emit_push_fpr_callee_saved (fpr_position
);
5006 /* Check frame_pointer_needed to see
5007 if we shall emit fp adjustment instruction. */
5008 if (frame_pointer_needed
)
5010 /* adjust $fp = $sp + 4 ($fp size)
5013 + (4 * n) (callee-saved registers)
5014 + sp_adjust ('push25 Re,imm8u')
5015 Note: Since we use 'push25 Re,imm8u',
5016 the position of stack pointer is further
5017 changed after push instruction.
5018 Hence, we need to take sp_adjust value
5019 into consideration. */
5020 fp_adjust
= cfun
->machine
->fp_size
5021 + cfun
->machine
->gp_size
5022 + cfun
->machine
->lp_size
5023 + cfun
->machine
->callee_saved_gpr_regs_size
5026 nds32_emit_adjust_frame (hard_frame_pointer_rtx
,
5033 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5035 /* Calculate fpr space. */
5036 fpr_space
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
5037 + cfun
->machine
->callee_saved_fpr_regs_size
;
5039 /* We have to use 'push25 Re, fpr_space', to pre-allocate
5040 callee saved fpr registers space. */
5041 nds32_emit_stack_v3push (Rb
, Re
, fpr_space
);
5042 nds32_emit_push_fpr_callee_saved (0);
5046 /* We have to use 'push25 Re,0' and
5047 expand one more instruction to adjust $sp later. */
5049 /* nds32_emit_stack_v3push(last_regno, sp_adjust),
5050 the pattern 'stack_v3push' is implemented in nds32.md. */
5051 nds32_emit_stack_v3push (Rb
, Re
, 0);
5054 /* Check frame_pointer_needed to see
5055 if we shall emit fp adjustment instruction. */
5056 if (frame_pointer_needed
)
5058 /* adjust $fp = $sp + 4 ($fp size)
5061 + (4 * n) (callee-saved registers)
5062 Note: Since we use 'push25 Re,0',
5063 the stack pointer is just at the position
5064 after push instruction.
5065 No need to take sp_adjust into consideration. */
5066 fp_adjust
= cfun
->machine
->fp_size
5067 + cfun
->machine
->gp_size
5068 + cfun
->machine
->lp_size
5069 + cfun
->machine
->callee_saved_gpr_regs_size
;
5071 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5073 /* We use 'push25 Re, fpr_space', the $sp is
5074 on callee saved fpr position, so need to consider
5076 fp_adjust
= fp_adjust
+ fpr_space
;
5079 nds32_emit_adjust_frame (hard_frame_pointer_rtx
,
5084 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5086 /* We use 'push25 Re, fpr_space',
5087 the $sp is on callee saved fpr position,
5088 no need to consider fpr space. */
5089 sp_adjust
= sp_adjust
- fpr_space
;
5092 /* Because we use 'push25 Re,0',
5093 we need to expand one more instruction to adjust $sp.
5094 using NEGATIVE value to tell that we are decreasing address. */
5095 nds32_emit_adjust_frame (stack_pointer_rtx
,
5100 /* Emit gp setup instructions for -fpic. */
5101 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
5102 nds32_emit_load_gp ();
5104 /* Prevent the instruction scheduler from
5105 moving instructions across the boundary. */
5106 emit_insn (gen_blockage ());
5109 /* Function for v3pop epilogue. */
5111 nds32_expand_epilogue_v3pop (bool sibcall_p
)
5116 /* Compute and setup stack frame size.
5117 The result will be in cfun->machine. */
5118 nds32_compute_stack_frame ();
5120 /* Prevent the instruction scheduler from
5121 moving instructions across the boundary. */
5122 emit_insn (gen_blockage ());
5124 /* If the function is 'naked', we do not have to generate
5125 epilogue code fragment BUT 'ret' instruction. */
5126 if (cfun
->machine
->naked_p
)
5128 /* Generate return instruction by using 'return_internal' pattern.
5129 Make sure this instruction is after gen_blockage().
5130 First we need to check this is a function without sibling call. */
5133 /* We need to further check attributes to determine whether
5134 there should be return instruction at epilogue.
5135 If the attribute naked exists but -mno-ret-in-naked-func
5136 is issued, there is NO need to generate return instruction. */
5137 if (cfun
->machine
->attr_naked_p
&& !flag_ret_in_naked_func
)
5140 emit_jump_insn (gen_return_internal ());
5145 /* Get callee_first_regno and callee_last_regno. */
5146 Rb
= cfun
->machine
->callee_saved_first_gpr_regno
;
5147 Re
= cfun
->machine
->callee_saved_last_gpr_regno
;
5149 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available,
5150 where imm8u has to be 8-byte alignment. */
5151 sp_adjust
= cfun
->machine
->local_size
5152 + cfun
->machine
->out_args_size
5153 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5154 + cfun
->machine
->callee_saved_fpr_regs_size
;
5156 /* We have to consider alloca issue as well.
5157 If the function does call alloca(), the stack pointer is not fixed.
5158 In that case, we cannot use 'pop25 Re,imm8u' directly.
5159 We have to caculate stack pointer from frame pointer
5160 and then use 'pop25 Re,0'.
5161 Of course, the frame_pointer_needed should be nonzero
5162 if the function calls alloca(). */
5163 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
5164 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
)
5165 && !cfun
->calls_alloca
)
5167 /* Restore fpu registers. */
5168 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5170 int fpr_position
= cfun
->machine
->local_size
5171 + cfun
->machine
->out_args_size
;
5172 /* Emit fpu load instruction, using [$sp + offset] restore
5174 nds32_emit_v3pop_fpr_callee_saved (fpr_position
);
5177 /* We can use 'pop25 Re,imm8u'. */
5179 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
5180 the pattern 'stack_v3pop' is implementad in nds32.md. */
5181 nds32_emit_stack_v3pop (Rb
, Re
, sp_adjust
);
5185 /* We have to use 'pop25 Re,0', and prior to it,
5186 we must expand one more instruction to adjust $sp. */
5188 if (frame_pointer_needed
)
5190 /* adjust $sp = $fp - 4 ($fp size)
5193 - (4 * n) (callee-saved registers)
5194 Note: No need to adjust
5195 cfun->machine->callee_saved_area_gpr_padding_bytes,
5196 because we want to adjust stack pointer
5197 to the position for pop instruction. */
5198 sp_adjust
= cfun
->machine
->fp_size
5199 + cfun
->machine
->gp_size
5200 + cfun
->machine
->lp_size
5201 + cfun
->machine
->callee_saved_gpr_regs_size
;
5203 /* Restore fpu registers. */
5204 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5206 /* Set $sp to callee saved fpr position, we need to restore
5208 sp_adjust
= sp_adjust
5209 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5210 + cfun
->machine
->callee_saved_fpr_regs_size
;
5212 nds32_emit_adjust_frame (stack_pointer_rtx
,
5213 hard_frame_pointer_rtx
,
5216 /* Emit fpu load instruction, using [$sp + offset] restore
5218 nds32_emit_v3pop_fpr_callee_saved (0);
5222 nds32_emit_adjust_frame (stack_pointer_rtx
,
5223 hard_frame_pointer_rtx
,
5229 /* If frame pointer is NOT needed,
5230 we cannot calculate the sp adjustment from frame pointer.
5231 Instead, we calculate the adjustment by local_size,
5232 out_args_size, and callee_saved_area_padding_bytes.
5233 Notice that such sp adjustment value may be out of range,
5234 so we have to deal with it as well. */
5236 /* Adjust $sp = $sp + local_size + out_args_size
5237 + callee_saved_area_gpr_padding_bytes
5238 + callee_saved_fpr_regs_size. */
5239 sp_adjust
= cfun
->machine
->local_size
5240 + cfun
->machine
->out_args_size
5241 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5242 + cfun
->machine
->callee_saved_fpr_regs_size
;
5244 /* Restore fpu registers. */
5245 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5247 /* Set $sp to callee saved fpr position, we need to restore
5249 sp_adjust
= sp_adjust
5250 - cfun
->machine
->callee_saved_area_gpr_padding_bytes
5251 - cfun
->machine
->callee_saved_fpr_regs_size
;
5253 nds32_emit_adjust_frame (stack_pointer_rtx
,
5257 /* Emit fpu load instruction, using [$sp + offset] restore
5259 nds32_emit_v3pop_fpr_callee_saved (0);
5263 /* sp_adjust value may be out of range of the addi instruction,
5264 create alternative add behavior with TA_REGNUM if necessary,
5265 using POSITIVE value to tell that we are increasing
5267 nds32_emit_adjust_frame (stack_pointer_rtx
,
5273 if (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)
5275 /* We have fpr need to restore, so $sp is set on callee saved fpr
5276 position. And we use 'pop25 Re, fpr_space' to adjust $sp. */
5277 int fpr_space
= cfun
->machine
->callee_saved_area_gpr_padding_bytes
5278 + cfun
->machine
->callee_saved_fpr_regs_size
;
5279 nds32_emit_stack_v3pop (Rb
, Re
, fpr_space
);
5283 /* nds32_emit_stack_v3pop(last_regno, sp_adjust),
5284 the pattern 'stack_v3pop' is implementad in nds32.md. */
5285 nds32_emit_stack_v3pop (Rb
, Re
, 0);
5288 /* Generate return instruction. */
5289 emit_jump_insn (gen_pop25return ());
5292 /* Return nonzero if this function is known to have a null epilogue.
5293 This allows the optimizer to omit jumps to jumps if no stack
5296 nds32_can_use_return_insn (void)
5300 /* Prior to reloading, we can't tell how many registers must be saved.
5301 Thus we can not determine whether this function has null epilogue. */
5302 if (!reload_completed
)
5305 /* If attribute 'naked' appears but -mno-ret-in-naked-func is used,
5306 we cannot use return instruction. */
5307 if (cfun
->machine
->attr_naked_p
&& !flag_ret_in_naked_func
)
5310 sp_adjust
= cfun
->machine
->local_size
5311 + cfun
->machine
->out_args_size
5312 + cfun
->machine
->callee_saved_area_gpr_padding_bytes
5313 + cfun
->machine
->callee_saved_fpr_regs_size
;
5314 if (!cfun
->machine
->fp_as_gp_p
5315 && satisfies_constraint_Iu08 (GEN_INT (sp_adjust
))
5316 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust
)
5317 && !cfun
->calls_alloca
5318 && NDS32_V3PUSH_AVAILABLE_P
5319 && !(TARGET_HARD_FLOAT
5320 && (cfun
->machine
->callee_saved_first_fpr_regno
!= SP_REGNUM
)))
5323 /* If no stack was created, two conditions must be satisfied:
5324 1. This is a naked function.
5325 So there is no callee-saved, local size, or outgoing size.
5326 2. This is NOT a variadic function.
5327 So there is no pushing arguement registers into the stack. */
5328 return (cfun
->machine
->naked_p
&& (cfun
->machine
->va_args_size
== 0));
5332 nds32_case_vector_shorten_mode (int min_offset
, int max_offset
,
5333 rtx body ATTRIBUTE_UNUSED
)
5335 if (min_offset
< 0 || max_offset
>= 0x2000)
5339 /* The jump table maybe need to 2 byte alignment,
5340 so reserved 1 byte for check max_offset. */
5341 if (max_offset
>= 0xff)
5348 /* ------------------------------------------------------------------------ */
5350 /* Return alignment for the label. */
5352 nds32_target_alignment (rtx_insn
*label
)
5356 if (!NDS32_ALIGN_P ())
5359 insn
= next_active_insn (label
);
5361 /* Always align to 4 byte when first instruction after label is jump
5362 instruction since length for that might changed, so let's always align
5363 it for make sure we don't lose any perfomance here. */
5365 || (get_attr_length (insn
) == 2
5366 && !JUMP_P (insn
) && !CALL_P (insn
)))
5372 /* Return alignment for data. */
5374 nds32_data_alignment (tree data
,
5375 unsigned int basic_align
)
5377 if ((basic_align
< BITS_PER_WORD
)
5378 && (TREE_CODE (data
) == ARRAY_TYPE
5379 || TREE_CODE (data
) == UNION_TYPE
5380 || TREE_CODE (data
) == RECORD_TYPE
))
5381 return BITS_PER_WORD
;
5386 /* Return alignment for constant value. */
5387 static HOST_WIDE_INT
5388 nds32_constant_alignment (const_tree constant
,
5389 HOST_WIDE_INT basic_align
)
5391 /* Make string literal and constant for constructor to word align. */
5392 if (((TREE_CODE (constant
) == STRING_CST
5393 || TREE_CODE (constant
) == CONSTRUCTOR
5394 || TREE_CODE (constant
) == UNION_TYPE
5395 || TREE_CODE (constant
) == RECORD_TYPE
5396 || TREE_CODE (constant
) == ARRAY_TYPE
)
5397 && basic_align
< BITS_PER_WORD
))
5398 return BITS_PER_WORD
;
5403 /* Return alignment for local variable. */
5405 nds32_local_alignment (tree local ATTRIBUTE_UNUSED
,
5406 unsigned int basic_align
)
5408 bool at_least_align_to_word
= false;
5409 /* Make local array, struct and union at least align to word for make
5410 sure it can unroll memcpy when initialize by constant. */
5411 switch (TREE_CODE (local
))
5416 at_least_align_to_word
= true;
5419 at_least_align_to_word
= false;
5422 if (at_least_align_to_word
5423 && (basic_align
< BITS_PER_WORD
))
5424 return BITS_PER_WORD
;
5430 nds32_split_double_word_load_store_p(rtx
*operands
, bool load_p
)
5432 rtx mem
= load_p
? operands
[1] : operands
[0];
5433 /* Do split at split2 if -O0 or schedule 2 not enable. */
5434 if (optimize
== 0 || !flag_schedule_insns_after_reload
)
5435 return !satisfies_constraint_Da (mem
) || MEM_VOLATILE_P (mem
);
5437 /* Split double word load store after copy propgation. */
5438 if (current_pass
== NULL
)
5441 const char *pass_name
= current_pass
->name
;
5442 if (pass_name
&& ((strcmp (pass_name
, "split4") == 0)
5443 || (strcmp (pass_name
, "split5") == 0)))
5444 return !satisfies_constraint_Da (mem
) || MEM_VOLATILE_P (mem
);
5450 nds32_use_blocks_for_constant_p (machine_mode mode
,
5451 const_rtx x ATTRIBUTE_UNUSED
)
5453 if ((TARGET_FPU_SINGLE
|| TARGET_FPU_DOUBLE
)
5454 && (mode
== DFmode
|| mode
== SFmode
))
5460 /* ------------------------------------------------------------------------ */
5462 /* PART 5: Initialize target hook structure and definitions. */
5464 /* Controlling the Compilation Driver. */
5467 /* Run-time Target Specification. */
5470 /* Defining Data Structures for Per-function Information. */
5473 /* Storage Layout. */
5475 #undef TARGET_PROMOTE_FUNCTION_MODE
5476 #define TARGET_PROMOTE_FUNCTION_MODE \
5477 default_promote_function_mode_always_promote
5479 #undef TARGET_EXPAND_TO_RTL_HOOK
5480 #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook
5482 #undef TARGET_CONSTANT_ALIGNMENT
5483 #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment
5486 /* Layout of Source Language Data Types. */
5489 /* Register Usage. */
5491 /* -- Basic Characteristics of Registers. */
5493 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5494 #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage
5496 /* -- Order of Allocation of Registers. */
5498 /* -- How Values Fit in Registers. */
5500 #undef TARGET_HARD_REGNO_NREGS
5501 #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs
5503 #undef TARGET_HARD_REGNO_MODE_OK
5504 #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok
5506 #undef TARGET_MODES_TIEABLE_P
5507 #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p
5509 /* -- Handling Leaf Functions. */
5511 /* -- Registers That Form a Stack. */
5514 /* Register Classes. */
5516 #undef TARGET_CLASS_MAX_NREGS
5517 #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs
5519 #undef TARGET_REGISTER_PRIORITY
5520 #define TARGET_REGISTER_PRIORITY nds32_register_priority
5522 #undef TARGET_CAN_CHANGE_MODE_CLASS
5523 #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class
5526 /* Obsolete Macros for Defining Constraints. */
5529 /* Stack Layout and Calling Conventions. */
5531 /* -- Basic Stack Layout. */
5533 /* -- Exception Handling Support. */
5535 /* -- Specifying How Stack Checking is Done. */
5537 /* -- Registers That Address the Stack Frame. */
5539 /* -- Eliminating Frame Pointer and Arg Pointer. */
5541 #undef TARGET_CAN_ELIMINATE
5542 #define TARGET_CAN_ELIMINATE nds32_can_eliminate
5544 /* -- Passing Function Arguments on the Stack. */
5546 /* -- Passing Arguments in Registers. */
5548 #undef TARGET_FUNCTION_ARG
5549 #define TARGET_FUNCTION_ARG nds32_function_arg
5551 #undef TARGET_MUST_PASS_IN_STACK
5552 #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack
5554 #undef TARGET_ARG_PARTIAL_BYTES
5555 #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes
5557 #undef TARGET_FUNCTION_ARG_ADVANCE
5558 #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance
5560 #undef TARGET_FUNCTION_ARG_BOUNDARY
5561 #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary
5563 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5564 #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p
5566 /* -- How Scalar Function Values Are Returned. */
5568 #undef TARGET_FUNCTION_VALUE
5569 #define TARGET_FUNCTION_VALUE nds32_function_value
5571 #undef TARGET_LIBCALL_VALUE
5572 #define TARGET_LIBCALL_VALUE nds32_libcall_value
5574 #undef TARGET_FUNCTION_VALUE_REGNO_P
5575 #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p
5577 /* -- How Large Values Are Returned. */
5579 #undef TARGET_RETURN_IN_MEMORY
5580 #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory
5582 /* -- Caller-Saves Register Allocation. */
5584 /* -- Function Entry and Exit. */
5586 #undef TARGET_ASM_FUNCTION_PROLOGUE
5587 #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue
5589 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
5590 #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue
5592 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
5593 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue
5595 #undef TARGET_ASM_FUNCTION_EPILOGUE
5596 #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue
5598 #undef TARGET_ASM_OUTPUT_MI_THUNK
5599 #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk
5601 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5602 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
5604 /* -- Generating Code for Profiling. */
5606 /* -- Permitting tail calls. */
5608 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5609 #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall
5611 #undef TARGET_WARN_FUNC_RETURN
5612 #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return
5614 /* Stack smashing protection. */
5617 /* Implementing the Varargs Macros. */
5619 #undef TARGET_SETUP_INCOMING_VARARGS
5620 #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs
5622 #undef TARGET_STRICT_ARGUMENT_NAMING
5623 #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming
5626 /* Trampolines for Nested Functions. */
5628 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
5629 #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template
5631 #undef TARGET_TRAMPOLINE_INIT
5632 #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init
5635 /* Implicit Calls to Library Routines. */
5638 /* Addressing Modes. */
5640 #undef TARGET_LEGITIMATE_ADDRESS_P
5641 #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p
5643 #undef TARGET_LEGITIMIZE_ADDRESS
5644 #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address
5646 #undef TARGET_LEGITIMATE_CONSTANT_P
5647 #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p
5649 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
5650 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode
5652 #undef TARGET_CANNOT_FORCE_CONST_MEM
5653 #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem
5655 #undef TARGET_DELEGITIMIZE_ADDRESS
5656 #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address
5659 /* Anchored Addresses. */
5662 /* Condition Code Status. */
5664 /* -- Representation of condition codes using (cc0). */
5666 /* -- Representation of condition codes using registers. */
5668 #undef TARGET_CANONICALIZE_COMPARISON
5669 #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison
5671 /* -- Macros to control conditional execution. */
5674 /* Describing Relative Costs of Operations. */
5676 #undef TARGET_REGISTER_MOVE_COST
5677 #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost
5679 #undef TARGET_MEMORY_MOVE_COST
5680 #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost
5682 #undef TARGET_RTX_COSTS
5683 #define TARGET_RTX_COSTS nds32_rtx_costs
5685 #undef TARGET_ADDRESS_COST
5686 #define TARGET_ADDRESS_COST nds32_address_cost
5689 /* Adjusting the Instruction Scheduler. */
5692 /* Dividing the Output into Sections (Texts, Data, . . . ). */
5694 #undef TARGET_ENCODE_SECTION_INFO
5695 #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info
5698 /* Position Independent Code. */
5701 /* Defining the Output Assembler Language. */
5703 /* -- The Overall Framework of an Assembler File. */
5705 #undef TARGET_ASM_FILE_START
5706 #define TARGET_ASM_FILE_START nds32_asm_file_start
5707 #undef TARGET_ASM_FILE_END
5708 #define TARGET_ASM_FILE_END nds32_asm_file_end
5710 /* -- Output of Data. */
5712 #undef TARGET_ASM_ALIGNED_HI_OP
5713 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
5715 #undef TARGET_ASM_ALIGNED_SI_OP
5716 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
5718 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
5719 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra
5721 /* -- Output of Uninitialized Variables. */
5723 /* -- Output and Generation of Labels. */
5725 #undef TARGET_ASM_GLOBALIZE_LABEL
5726 #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label
5728 /* -- How Initialization Functions Are Handled. */
5730 /* -- Macros Controlling Initialization Routines. */
5732 /* -- Output of Assembler Instructions. */
5734 #undef TARGET_PRINT_OPERAND
5735 #define TARGET_PRINT_OPERAND nds32_print_operand
5736 #undef TARGET_PRINT_OPERAND_ADDRESS
5737 #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address
5739 /* -- Output of Dispatch Tables. */
5741 /* -- Assembler Commands for Exception Regions. */
5743 #undef TARGET_DWARF_REGISTER_SPAN
5744 #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span
5746 /* -- Assembler Commands for Alignment. */
5749 /* Controlling Debugging Information Format. */
5751 /* -- Macros Affecting All Debugging Formats. */
5753 /* -- Specific Options for DBX Output. */
5755 /* -- Open-Ended Hooks for DBX Format. */
5757 /* -- File Names in DBX Format. */
5759 /* -- Macros for DWARF Output. */
5761 /* -- Macros for VMS Debug Format. */
5764 /* Cross Compilation and Floating Point. */
5767 /* Mode Switching Instructions. */
5770 /* Defining target-specific uses of __attribute__. */
5772 #undef TARGET_ATTRIBUTE_TABLE
5773 #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table
5775 #undef TARGET_MERGE_DECL_ATTRIBUTES
5776 #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes
5778 #undef TARGET_INSERT_ATTRIBUTES
5779 #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes
5781 #undef TARGET_OPTION_PRAGMA_PARSE
5782 #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse
5784 #undef TARGET_OPTION_OVERRIDE
5785 #define TARGET_OPTION_OVERRIDE nds32_option_override
5788 /* Emulating TLS. */
5790 #undef TARGET_HAVE_TLS
5791 #define TARGET_HAVE_TLS TARGET_LINUX_ABI
5794 /* Defining coprocessor specifics for MIPS targets. */
5797 /* Parameters for Precompiled Header Validity Checking. */
5800 /* C++ ABI parameters. */
5803 /* Adding support for named address spaces. */
5806 /* Miscellaneous Parameters. */
5808 #undef TARGET_MD_ASM_ADJUST
5809 #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust
5811 #undef TARGET_INIT_BUILTINS
5812 #define TARGET_INIT_BUILTINS nds32_init_builtins
5814 #undef TARGET_BUILTIN_DECL
5815 #define TARGET_BUILTIN_DECL nds32_builtin_decl
5817 #undef TARGET_EXPAND_BUILTIN
5818 #define TARGET_EXPAND_BUILTIN nds32_expand_builtin
5820 #undef TARGET_INIT_LIBFUNCS
5821 #define TARGET_INIT_LIBFUNCS nds32_init_libfuncs
5823 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
5824 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p
5827 /* ------------------------------------------------------------------------ */
5829 /* Initialize the GCC target structure. */
5831 struct gcc_target targetm
= TARGET_INITIALIZER
;
5833 /* ------------------------------------------------------------------------ */