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* config/m32r/m32r.c: Include integrate.h in order to get the prototype for
[official-gcc.git] / gcc / config / m32r / m32r.c
blob52dbb770555fe7fc52f30f9265a96e3e13ffbfd6
1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "tree.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "output.h"
34 #include "insn-attr.h"
35 #include "flags.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "ggc.h"
41 #include "integrate.h"
42 #include "tm_p.h"
43 #include "target.h"
44 #include "target-def.h"
45
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0, m32r_compare_op1;
49
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars[256];
52
53 /* Selected code model. */
54 const char * m32r_model_string = M32R_MODEL_DEFAULT;
55 enum m32r_model m32r_model;
56
57 /* Selected SDA support. */
58 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
59 enum m32r_sdata m32r_sdata;
60
61 /* Machine-specific symbol_ref flags. */
62 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
63 #define SYMBOL_REF_MODEL(X) \
64 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
65
66 /* For string literals, etc. */
67 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
68
69 /* Cache-flush support. Cache-flush is used at trampoline.
70 Default cache-flush is "trap 12".
71 default cache-flush function is "_flush_cache" (CACHE_FLUSH_FUNC)
72 default cache-flush trap-interrupt number is "12". (CACHE_FLUSH_TRAP)
73 You can change how to generate code of cache-flush with following options.
74 -flush-func=FLUSH-FUNC-NAME
75 -no-flush-func
76 -fluch-trap=TRAP-NUMBER
77 -no-flush-trap. */
78 const char *m32r_cache_flush_func = CACHE_FLUSH_FUNC;
79 const char *m32r_cache_flush_trap_string = CACHE_FLUSH_TRAP;
80 int m32r_cache_flush_trap = 12;
81
82 /* Forward declaration. */
83 static void init_reg_tables (void);
84 static void block_move_call (rtx, rtx, rtx);
85 static int m32r_is_insn (rtx);
86 const struct attribute_spec m32r_attribute_table[];
87 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
88 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
89 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
90
91 static void m32r_file_start (void);
92
93 static int m32r_adjust_priority (rtx, int);
94 static int m32r_issue_rate (void);
95
96 static void m32r_encode_section_info (tree, rtx, int);
97 static bool m32r_in_small_data_p (tree);
98 static bool m32r_return_in_memory (tree, tree);
99 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
100 tree, int *, int);
101 static void init_idents (void);
102 static bool m32r_rtx_costs (rtx, int, int, int *);
103 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
104 tree, bool);
105 \f
106 /* Initialize the GCC target structure. */
107 #undef TARGET_ATTRIBUTE_TABLE
108 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
109
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
112 #undef TARGET_ASM_ALIGNED_SI_OP
113 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
114
115 #undef TARGET_ASM_FUNCTION_PROLOGUE
116 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
117 #undef TARGET_ASM_FUNCTION_EPILOGUE
118 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
119
120 #undef TARGET_ASM_FILE_START
121 #define TARGET_ASM_FILE_START m32r_file_start
122
123 #undef TARGET_SCHED_ADJUST_PRIORITY
124 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
125 #undef TARGET_SCHED_ISSUE_RATE
126 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
127
128 #undef TARGET_ENCODE_SECTION_INFO
129 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
130 #undef TARGET_IN_SMALL_DATA_P
131 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
132
133 #undef TARGET_RTX_COSTS
134 #define TARGET_RTX_COSTS m32r_rtx_costs
135 #undef TARGET_ADDRESS_COST
136 #define TARGET_ADDRESS_COST hook_int_rtx_0
137
138 #undef TARGET_PROMOTE_PROTOTYPES
139 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
140 #undef TARGET_RETURN_IN_MEMORY
141 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
142 #undef TARGET_SETUP_INCOMING_VARARGS
143 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
144 #undef TARGET_MUST_PASS_IN_STACK
145 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
146 #undef TARGET_PASS_BY_REFERENCE
147 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
148
149 struct gcc_target targetm = TARGET_INITIALIZER;
150 \f
151 /* Called by OVERRIDE_OPTIONS to initialize various things. */
152
153 void
154 m32r_init (void)
155 {
156 init_reg_tables ();
157
158 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
159 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
160 m32r_punct_chars['#'] = 1;
161 m32r_punct_chars['@'] = 1; /* ??? no longer used */
162
163 /* Provide default value if not specified. */
164 if (!g_switch_set)
165 g_switch_value = SDATA_DEFAULT_SIZE;
166
167 if (strcmp (m32r_model_string, "small") == 0)
168 m32r_model = M32R_MODEL_SMALL;
169 else if (strcmp (m32r_model_string, "medium") == 0)
170 m32r_model = M32R_MODEL_MEDIUM;
171 else if (strcmp (m32r_model_string, "large") == 0)
172 m32r_model = M32R_MODEL_LARGE;
173 else
174 error ("bad value (%s) for -mmodel switch", m32r_model_string);
175
176 if (strcmp (m32r_sdata_string, "none") == 0)
177 m32r_sdata = M32R_SDATA_NONE;
178 else if (strcmp (m32r_sdata_string, "sdata") == 0)
179 m32r_sdata = M32R_SDATA_SDATA;
180 else if (strcmp (m32r_sdata_string, "use") == 0)
181 m32r_sdata = M32R_SDATA_USE;
182 else
183 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
184
185 if (m32r_cache_flush_trap_string)
186 {
187 /* Change trap-number (12) for cache-flush to the others (0 - 15). */
188 m32r_cache_flush_trap = atoi (m32r_cache_flush_trap_string);
189 if (m32r_cache_flush_trap < 0 || m32r_cache_flush_trap > 15)
190 error ("bad value (%s) for -flush-trap=n (0=<n<=15)",
191 m32r_cache_flush_trap_string);
192 }
193 }
194
195 /* Vectors to keep interesting information about registers where it can easily
196 be got. We use to use the actual mode value as the bit number, but there
197 is (or may be) more than 32 modes now. Instead we use two tables: one
198 indexed by hard register number, and one indexed by mode. */
199
200 /* The purpose of m32r_mode_class is to shrink the range of modes so that
201 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
202 mapped into one m32r_mode_class mode. */
203
204 enum m32r_mode_class
205 {
206 C_MODE,
207 S_MODE, D_MODE, T_MODE, O_MODE,
208 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
209 };
210
211 /* Modes for condition codes. */
212 #define C_MODES (1 << (int) C_MODE)
213
214 /* Modes for single-word and smaller quantities. */
215 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
216
217 /* Modes for double-word and smaller quantities. */
218 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
219
220 /* Modes for quad-word and smaller quantities. */
221 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
222
223 /* Modes for accumulators. */
224 #define A_MODES (1 << (int) A_MODE)
225
226 /* Value is 1 if register/mode pair is acceptable on arc. */
227
228 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
229 {
230 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
231 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
232 S_MODES, C_MODES, A_MODES, A_MODES
233 };
234
235 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
236
237 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
238
239 static void
240 init_reg_tables (void)
241 {
242 int i;
243
244 for (i = 0; i < NUM_MACHINE_MODES; i++)
245 {
246 switch (GET_MODE_CLASS (i))
247 {
248 case MODE_INT:
249 case MODE_PARTIAL_INT:
250 case MODE_COMPLEX_INT:
251 if (GET_MODE_SIZE (i) <= 4)
252 m32r_mode_class[i] = 1 << (int) S_MODE;
253 else if (GET_MODE_SIZE (i) == 8)
254 m32r_mode_class[i] = 1 << (int) D_MODE;
255 else if (GET_MODE_SIZE (i) == 16)
256 m32r_mode_class[i] = 1 << (int) T_MODE;
257 else if (GET_MODE_SIZE (i) == 32)
258 m32r_mode_class[i] = 1 << (int) O_MODE;
259 else
260 m32r_mode_class[i] = 0;
261 break;
262 case MODE_FLOAT:
263 case MODE_COMPLEX_FLOAT:
264 if (GET_MODE_SIZE (i) <= 4)
265 m32r_mode_class[i] = 1 << (int) SF_MODE;
266 else if (GET_MODE_SIZE (i) == 8)
267 m32r_mode_class[i] = 1 << (int) DF_MODE;
268 else if (GET_MODE_SIZE (i) == 16)
269 m32r_mode_class[i] = 1 << (int) TF_MODE;
270 else if (GET_MODE_SIZE (i) == 32)
271 m32r_mode_class[i] = 1 << (int) OF_MODE;
272 else
273 m32r_mode_class[i] = 0;
274 break;
275 case MODE_CC:
276 m32r_mode_class[i] = 1 << (int) C_MODE;
277 break;
278 default:
279 m32r_mode_class[i] = 0;
280 break;
281 }
282 }
283
284 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
285 {
286 if (GPR_P (i))
287 m32r_regno_reg_class[i] = GENERAL_REGS;
288 else if (i == ARG_POINTER_REGNUM)
289 m32r_regno_reg_class[i] = GENERAL_REGS;
290 else
291 m32r_regno_reg_class[i] = NO_REGS;
292 }
293 }
294 \f
295 /* M32R specific attribute support.
296
297 interrupt - for interrupt functions
298
299 model - select code model used to access object
300
301 small: addresses use 24 bits, use bl to make calls
302 medium: addresses use 32 bits, use bl to make calls
303 large: addresses use 32 bits, use seth/add3/jl to make calls
304
305 Grep for MODEL in m32r.h for more info. */
306
307 static tree small_ident1;
308 static tree small_ident2;
309 static tree medium_ident1;
310 static tree medium_ident2;
311 static tree large_ident1;
312 static tree large_ident2;
313
314 static void
315 init_idents (void)
316 {
317 if (small_ident1 == 0)
318 {
319 small_ident1 = get_identifier ("small");
320 small_ident2 = get_identifier ("__small__");
321 medium_ident1 = get_identifier ("medium");
322 medium_ident2 = get_identifier ("__medium__");
323 large_ident1 = get_identifier ("large");
324 large_ident2 = get_identifier ("__large__");
325 }
326 }
327
328 const struct attribute_spec m32r_attribute_table[] =
329 {
330 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
331 { "interrupt", 0, 0, true, false, false, NULL },
332 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
333 { NULL, 0, 0, false, false, false, NULL }
334 };
335
336
337 /* Handle an "model" attribute; arguments as in
338 struct attribute_spec.handler. */
339 static tree
340 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
341 tree args, int flags ATTRIBUTE_UNUSED,
342 bool *no_add_attrs)
343 {
344 tree arg;
345
346 init_idents ();
347 arg = TREE_VALUE (args);
348
349 if (arg != small_ident1
350 && arg != small_ident2
351 && arg != medium_ident1
352 && arg != medium_ident2
353 && arg != large_ident1
354 && arg != large_ident2)
355 {
356 warning ("invalid argument of `%s' attribute",
357 IDENTIFIER_POINTER (name));
358 *no_add_attrs = true;
359 }
360
361 return NULL_TREE;
362 }
363 \f
364 /* Encode section information of DECL, which is either a VAR_DECL,
365 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
366
367 For the M32R we want to record:
368
369 - whether the object lives in .sdata/.sbss.
370 - what code model should be used to access the object
371 */
372
373 static void
374 m32r_encode_section_info (tree decl, rtx rtl, int first)
375 {
376 int extra_flags = 0;
377 tree model_attr;
378 enum m32r_model model;
379
380 default_encode_section_info (decl, rtl, first);
381
382 if (!DECL_P (decl))
383 return;
384
385 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
386 if (model_attr)
387 {
388 tree id;
389
390 init_idents ();
391
392 id = TREE_VALUE (TREE_VALUE (model_attr));
393
394 if (id == small_ident1 || id == small_ident2)
395 model = M32R_MODEL_SMALL;
396 else if (id == medium_ident1 || id == medium_ident2)
397 model = M32R_MODEL_MEDIUM;
398 else if (id == large_ident1 || id == large_ident2)
399 model = M32R_MODEL_LARGE;
400 else
401 abort (); /* shouldn't happen */
402 }
403 else
404 {
405 if (TARGET_MODEL_SMALL)
406 model = M32R_MODEL_SMALL;
407 else if (TARGET_MODEL_MEDIUM)
408 model = M32R_MODEL_MEDIUM;
409 else if (TARGET_MODEL_LARGE)
410 model = M32R_MODEL_LARGE;
411 else
412 abort (); /* shouldn't happen */
413 }
414 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
415
416 if (extra_flags)
417 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
418 }
419
420 /* Only mark the object as being small data area addressable if
421 it hasn't been explicitly marked with a code model.
422
423 The user can explicitly put an object in the small data area with the
424 section attribute. If the object is in sdata/sbss and marked with a
425 code model do both [put the object in .sdata and mark it as being
426 addressed with a specific code model - don't mark it as being addressed
427 with an SDA reloc though]. This is ok and might be useful at times. If
428 the object doesn't fit the linker will give an error. */
429
430 static bool
431 m32r_in_small_data_p (tree decl)
432 {
433 tree section;
434
435 if (TREE_CODE (decl) != VAR_DECL)
436 return false;
437
438 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
439 return false;
440
441 section = DECL_SECTION_NAME (decl);
442 if (section)
443 {
444 char *name = (char *) TREE_STRING_POINTER (section);
445 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
446 return true;
447 }
448 else
449 {
450 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
451 {
452 int size = int_size_in_bytes (TREE_TYPE (decl));
453
454 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
455 return true;
456 }
457 }
458
459 return false;
460 }
461
462 /* Do anything needed before RTL is emitted for each function. */
463
464 void
465 m32r_init_expanders (void)
466 {
467 /* ??? At one point there was code here. The function is left in
468 to make it easy to experiment. */
469 }
470 \f
471 /* Acceptable arguments to the call insn. */
472
473 int
474 call_address_operand (rtx op, enum machine_mode mode)
475 {
476 return symbolic_operand (op, mode);
477
478 /* Constants and values in registers are not OK, because
479 the m32r BL instruction can only support PC relative branching. */
480 }
481
482 int
483 call_operand (rtx op, enum machine_mode mode)
484 {
485 if (GET_CODE (op) != MEM)
486 return 0;
487 op = XEXP (op, 0);
488 return call_address_operand (op, mode);
489 }
490
491 /* Returns 1 if OP is a symbol reference. */
492
493 int
494 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
495 {
496 switch (GET_CODE (op))
497 {
498 case SYMBOL_REF:
499 case LABEL_REF:
500 case CONST :
501 return 1;
502
503 default:
504 return 0;
505 }
506 }
507
508 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
509
510 int
511 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
512 {
513 if (! TARGET_SDATA_USE)
514 return 0;
515
516 if (GET_CODE (op) == SYMBOL_REF)
517 return SYMBOL_REF_SMALL_P (op);
518
519 if (GET_CODE (op) == CONST
520 && GET_CODE (XEXP (op, 0)) == PLUS
521 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
522 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
523 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
524 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
525
526 return 0;
527 }
528
529 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
530
531 int
532 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
533 {
534 rtx sym;
535
536 if (flag_pic)
537 return 0;
538
539 if (GET_CODE (op) == LABEL_REF)
540 return TARGET_ADDR24;
541
542 if (GET_CODE (op) == SYMBOL_REF)
543 sym = op;
544 else if (GET_CODE (op) == CONST
545 && GET_CODE (XEXP (op, 0)) == PLUS
546 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
547 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
548 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
549 sym = XEXP (XEXP (op, 0), 0);
550 else
551 return 0;
552
553 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
554 return 1;
555
556 if (TARGET_ADDR24
557 && (CONSTANT_POOL_ADDRESS_P (sym)
558 || LIT_NAME_P (XSTR (sym, 0))))
559 return 1;
560
561 return 0;
562 }
563
564 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
565
566 int
567 addr32_operand (rtx op, enum machine_mode mode)
568 {
569 rtx sym;
570
571 if (GET_CODE (op) == LABEL_REF)
572 return TARGET_ADDR32;
573
574 if (GET_CODE (op) == SYMBOL_REF)
575 sym = op;
576 else if (GET_CODE (op) == CONST
577 && GET_CODE (XEXP (op, 0)) == PLUS
578 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
579 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
580 && ! flag_pic)
581 sym = XEXP (XEXP (op, 0), 0);
582 else
583 return 0;
584
585 return (! addr24_operand (sym, mode)
586 && ! small_data_operand (sym, mode));
587 }
588
589 /* Return 1 if OP is a function that can be called with the `bl' insn. */
590
591 int
592 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
593 {
594 if (flag_pic)
595 return 1;
596
597 if (GET_CODE (op) == SYMBOL_REF)
598 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
599
600 return TARGET_CALL26;
601 }
602
603 /* Returns 1 if OP is an acceptable operand for seth/add3. */
604
605 int
606 seth_add3_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
607 {
608 if (flag_pic)
609 return 0;
610
611 if (GET_CODE (op) == SYMBOL_REF
612 || GET_CODE (op) == LABEL_REF)
613 return 1;
614
615 if (GET_CODE (op) == CONST
616 && GET_CODE (XEXP (op, 0)) == PLUS
617 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
618 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
619 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
620 return 1;
621
622 return 0;
623 }
624
625 /* Return true if OP is a signed 8 bit immediate value. */
626
627 int
628 int8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
629 {
630 if (GET_CODE (op) != CONST_INT)
631 return 0;
632 return INT8_P (INTVAL (op));
633 }
634
635 /* Return true if OP is a signed 16 bit immediate value
636 useful in comparisons. */
637
638 int
639 cmp_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
640 {
641 if (GET_CODE (op) != CONST_INT)
642 return 0;
643 return CMP_INT16_P (INTVAL (op));
644 }
645
646 /* Return true if OP is an unsigned 16 bit immediate value. */
647
648 int
649 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
650 {
651 if (GET_CODE (op) != CONST_INT)
652 return 0;
653 return UINT16_P (INTVAL (op));
654 }
655
656 /* Return true if OP is a register or signed 16 bit value. */
657
658 int
659 reg_or_int16_operand (rtx op, enum machine_mode mode)
660 {
661 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
662 return register_operand (op, mode);
663 if (GET_CODE (op) != CONST_INT)
664 return 0;
665 return INT16_P (INTVAL (op));
666 }
667
668 /* Return true if OP is a register or an unsigned 16 bit value. */
669
670 int
671 reg_or_uint16_operand (rtx op, enum machine_mode mode)
672 {
673 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
674 return register_operand (op, mode);
675 if (GET_CODE (op) != CONST_INT)
676 return 0;
677 return UINT16_P (INTVAL (op));
678 }
679
680 /* Return true if OP is a register or an integer value that can be
681 used is SEQ/SNE. We can use either XOR of the value or ADD of
682 the negative of the value for the constant. Don't allow 0,
683 because that is special cased. */
684
685 int
686 reg_or_eq_int16_operand (rtx op, enum machine_mode mode)
687 {
688 HOST_WIDE_INT value;
689
690 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
691 return register_operand (op, mode);
692
693 if (GET_CODE (op) != CONST_INT)
694 return 0;
695
696 value = INTVAL (op);
697 return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
698 }
699
700 /* Return true if OP is a register or signed 16 bit value for compares. */
701
702 int
703 reg_or_cmp_int16_operand (rtx op, enum machine_mode mode)
704 {
705 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
706 return register_operand (op, mode);
707 if (GET_CODE (op) != CONST_INT)
708 return 0;
709 return CMP_INT16_P (INTVAL (op));
710 }
711
712 /* Return true if OP is a register or the constant 0. */
713
714 int
715 reg_or_zero_operand (rtx op, enum machine_mode mode)
716 {
717 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
718 return register_operand (op, mode);
719
720 if (GET_CODE (op) != CONST_INT)
721 return 0;
722
723 return INTVAL (op) == 0;
724 }
725
726 /* Return true if OP is a const_int requiring two instructions to load. */
727
728 int
729 two_insn_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
730 {
731 if (GET_CODE (op) != CONST_INT)
732 return 0;
733 if (INT16_P (INTVAL (op))
734 || UINT24_P (INTVAL (op))
735 || UPPER16_P (INTVAL (op)))
736 return 0;
737 return 1;
738 }
739
740 /* Return true if OP is an acceptable argument for a single word
741 move source. */
742
743 int
744 move_src_operand (rtx op, enum machine_mode mode)
745 {
746 switch (GET_CODE (op))
747 {
748 case LABEL_REF :
749 case SYMBOL_REF :
750 case CONST :
751 return addr24_operand (op, mode);
752 case CONST_INT :
753 /* ??? We allow more cse opportunities if we only allow constants
754 loadable with one insn, and split the rest into two. The instances
755 where this would help should be rare and the current way is
756 simpler. */
757 if (HOST_BITS_PER_WIDE_INT > 32)
758 {
759 HOST_WIDE_INT rest = INTVAL (op) >> 31;
760 return (rest == 0 || rest == -1);
761 }
762 else
763 return 1;
764 case CONST_DOUBLE :
765 if (mode == SFmode)
766 return 1;
767 else if (mode == SImode)
768 {
769 /* Large unsigned constants are represented as const_double's. */
770 unsigned HOST_WIDE_INT low, high;
771
772 low = CONST_DOUBLE_LOW (op);
773 high = CONST_DOUBLE_HIGH (op);
774 return high == 0 && low <= (unsigned) 0xffffffff;
775 }
776 else
777 return 0;
778 case REG :
779 return register_operand (op, mode);
780 case SUBREG :
781 /* (subreg (mem ...) ...) can occur here if the inner part was once a
782 pseudo-reg and is now a stack slot. */
783 if (GET_CODE (SUBREG_REG (op)) == MEM)
784 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
785 else
786 return register_operand (op, mode);
787 case MEM :
788 if (GET_CODE (XEXP (op, 0)) == PRE_INC
789 || GET_CODE (XEXP (op, 0)) == PRE_DEC)
790 return 0; /* loads can't do pre-{inc,dec} */
791 return address_operand (XEXP (op, 0), mode);
792 default :
793 return 0;
794 }
795 }
796
797 /* Return true if OP is an acceptable argument for a double word
798 move source. */
799
800 int
801 move_double_src_operand (rtx op, enum machine_mode mode)
802 {
803 switch (GET_CODE (op))
804 {
805 case CONST_INT :
806 case CONST_DOUBLE :
807 return 1;
808 case REG :
809 return register_operand (op, mode);
810 case SUBREG :
811 /* (subreg (mem ...) ...) can occur here if the inner part was once a
812 pseudo-reg and is now a stack slot. */
813 if (GET_CODE (SUBREG_REG (op)) == MEM)
814 return move_double_src_operand (SUBREG_REG (op), mode);
815 else
816 return register_operand (op, mode);
817 case MEM :
818 /* Disallow auto inc/dec for now. */
819 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
820 || GET_CODE (XEXP (op, 0)) == PRE_INC)
821 return 0;
822 return address_operand (XEXP (op, 0), mode);
823 default :
824 return 0;
825 }
826 }
827
828 /* Return true if OP is an acceptable argument for a move destination. */
829
830 int
831 move_dest_operand (rtx op, enum machine_mode mode)
832 {
833 switch (GET_CODE (op))
834 {
835 case REG :
836 return register_operand (op, mode);
837 case SUBREG :
838 /* (subreg (mem ...) ...) can occur here if the inner part was once a
839 pseudo-reg and is now a stack slot. */
840 if (GET_CODE (SUBREG_REG (op)) == MEM)
841 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
842 else
843 return register_operand (op, mode);
844 case MEM :
845 if (GET_CODE (XEXP (op, 0)) == POST_INC)
846 return 0; /* stores can't do post inc */
847 return address_operand (XEXP (op, 0), mode);
848 default :
849 return 0;
850 }
851 }
852
853 /* Return 1 if OP is a DImode const we want to handle inline.
854 This must match the code in the movdi pattern.
855 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
856
857 int
858 easy_di_const (rtx op)
859 {
860 rtx high_rtx, low_rtx;
861 HOST_WIDE_INT high, low;
862
863 split_double (op, &high_rtx, &low_rtx);
864 high = INTVAL (high_rtx);
865 low = INTVAL (low_rtx);
866 /* Pick constants loadable with 2 16 bit `ldi' insns. */
867 if (high >= -128 && high <= 127
868 && low >= -128 && low <= 127)
869 return 1;
870 return 0;
871 }
872
873 /* Return 1 if OP is a DFmode const we want to handle inline.
874 This must match the code in the movdf pattern.
875 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
876
877 int
878 easy_df_const (rtx op)
879 {
880 REAL_VALUE_TYPE r;
881 long l[2];
882
883 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
884 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
885 if (l[0] == 0 && l[1] == 0)
886 return 1;
887 if ((l[0] & 0xffff) == 0 && l[1] == 0)
888 return 1;
889 return 0;
890 }
891
892 /* Return 1 if OP is an EQ or NE comparison operator. */
893
894 int
895 eqne_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
896 {
897 enum rtx_code code = GET_CODE (op);
898
899 return (code == EQ || code == NE);
900 }
901
902 /* Return 1 if OP is a signed comparison operator. */
903
904 int
905 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
906 {
907 enum rtx_code code = GET_CODE (op);
908
909 return (COMPARISON_P (op)
910 && (code == EQ || code == NE
911 || code == LT || code == LE || code == GT || code == GE));
912 }
913
914 /* Return 1 if OP is (mem (reg ...)).
915 This is used in insn length calcs. */
916
917 int
918 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
919 {
920 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
921 }
922
923 /* Return true if OP is an acceptable input argument for a zero/sign extend
924 operation. */
925
926 int
927 extend_operand (rtx op, enum machine_mode mode)
928 {
929 rtx addr;
930
931 switch (GET_CODE (op))
932 {
933 case REG :
934 case SUBREG :
935 return register_operand (op, mode);
936
937 case MEM :
938 addr = XEXP (op, 0);
939 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
940 return 0; /* loads can't do pre inc/pre dec */
941
942 return address_operand (addr, mode);
943
944 default :
945 return 0;
946 }
947 }
948
949 /* Return nonzero if the operand is an insn that is a small insn.
950 Allow const_int 0 as well, which is a placeholder for NOP slots. */
951
952 int
953 small_insn_p (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
954 {
955 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
956 return 1;
957
958 if (! INSN_P (op))
959 return 0;
960
961 return get_attr_length (op) == 2;
962 }
963
964 /* Return nonzero if the operand is an insn that is a large insn. */
965
966 int
967 large_insn_p (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
968 {
969 if (! INSN_P (op))
970 return 0;
971
972 return get_attr_length (op) != 2;
973 }
974
975 /* Return nonzero if TYPE must be passed by indirect reference. */
976
977 static bool
978 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
979 enum machine_mode mode, tree type,
980 bool named ATTRIBUTE_UNUSED)
981 {
982 int size;
983
984 if (type)
985 size = int_size_in_bytes (type);
986 else
987 size = GET_MODE_SIZE (mode);
988
989 return (size < 0 || size > 8);
990 }
991 \f
992 /* Comparisons. */
993
994 /* X and Y are two things to compare using CODE. Emit the compare insn and
995 return the rtx for compare [arg0 of the if_then_else].
996 If need_compare is true then the comparison insn must be generated, rather
997 than being subsumed into the following branch instruction. */
998
999 rtx
1000 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
1001 {
1002 enum rtx_code compare_code;
1003 enum rtx_code branch_code;
1004 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
1005 int must_swap = 0;
1006
1007 switch (code)
1008 {
1009 case EQ: compare_code = EQ; branch_code = NE; break;
1010 case NE: compare_code = EQ; branch_code = EQ; break;
1011 case LT: compare_code = LT; branch_code = NE; break;
1012 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
1013 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
1014 case GE: compare_code = LT; branch_code = EQ; break;
1015 case LTU: compare_code = LTU; branch_code = NE; break;
1016 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1017 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1018 case GEU: compare_code = LTU; branch_code = EQ; break;
1019
1020 default:
1021 abort ();
1022 }
1023
1024 if (need_compare)
1025 {
1026 switch (compare_code)
1027 {
1028 case EQ:
1029 if (GET_CODE (y) == CONST_INT
1030 && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
1031 && y != const0_rtx)
1032 {
1033 rtx tmp = gen_reg_rtx (SImode);
1034
1035 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
1036 x = tmp;
1037 y = const0_rtx;
1038 }
1039 else if (CONSTANT_P (y)) /* Reg equal to const. */
1040 {
1041 rtx tmp = force_reg (GET_MODE (x), y);
1042 y = tmp;
1043 }
1044
1045 if (register_operand (y, SImode) /* Reg equal to reg. */
1046 || y == const0_rtx) /* Reg equal to zero. */
1047 {
1048 emit_insn (gen_cmp_eqsi_insn (x, y));
1049
1050 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1051 }
1052 break;
1053
1054 case LT:
1055 if (register_operand (y, SImode)
1056 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1057 {
1058 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
1059
1060 switch (code)
1061 {
1062 case LT:
1063 emit_insn (gen_cmp_ltsi_insn (x, y));
1064 code = EQ;
1065 break;
1066 case LE:
1067 if (y == const0_rtx)
1068 tmp = const1_rtx;
1069 else
1070 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1071 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1072 code = EQ;
1073 break;
1074 case GT:
1075 if (GET_CODE (y) == CONST_INT)
1076 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
1077 else
1078 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1079 emit_insn (gen_cmp_ltsi_insn (x, tmp));
1080 code = NE;
1081 break;
1082 case GE:
1083 emit_insn (gen_cmp_ltsi_insn (x, y));
1084 code = NE;
1085 break;
1086 default:
1087 abort ();
1088 }
1089
1090 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1091 }
1092 break;
1093
1094 case LTU:
1095 if (register_operand (y, SImode)
1096 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1097 {
1098 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
1099
1100 switch (code)
1101 {
1102 case LTU:
1103 emit_insn (gen_cmp_ltusi_insn (x, y));
1104 code = EQ;
1105 break;
1106 case LEU:
1107 if (y == const0_rtx)
1108 tmp = const1_rtx;
1109 else
1110 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1111 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1112 code = EQ;
1113 break;
1114 case GTU:
1115 if (GET_CODE (y) == CONST_INT)
1116 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
1117 else
1118 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
1119 emit_insn (gen_cmp_ltusi_insn (x, tmp));
1120 code = NE;
1121 break;
1122 case GEU:
1123 emit_insn (gen_cmp_ltusi_insn (x, y));
1124 code = NE;
1125 break;
1126 default:
1127 abort();
1128 }
1129
1130 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
1131 }
1132 break;
1133
1134 default:
1135 abort();
1136 }
1137 }
1138 else
1139 {
1140 /* Reg/reg equal comparison. */
1141 if (compare_code == EQ
1142 && register_operand (y, SImode))
1143 return gen_rtx_fmt_ee (code, CCmode, x, y);
1144
1145 /* Reg/zero signed comparison. */
1146 if ((compare_code == EQ || compare_code == LT)
1147 && y == const0_rtx)
1148 return gen_rtx_fmt_ee (code, CCmode, x, y);
1149
1150 /* Reg/smallconst equal comparison. */
1151 if (compare_code == EQ
1152 && GET_CODE (y) == CONST_INT
1153 && CMP_INT16_P (INTVAL (y)))
1154 {
1155 rtx tmp = gen_reg_rtx (SImode);
1156
1157 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
1158 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
1159 }
1160
1161 /* Reg/const equal comparison. */
1162 if (compare_code == EQ
1163 && CONSTANT_P (y))
1164 {
1165 rtx tmp = force_reg (GET_MODE (x), y);
1166
1167 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
1168 }
1169 }
1170
1171 if (CONSTANT_P (y))
1172 {
1173 if (must_swap)
1174 y = force_reg (GET_MODE (x), y);
1175 else
1176 {
1177 int ok_const =
1178 (code == LTU || code == LEU || code == GTU || code == GEU)
1179 ? uint16_operand (y, GET_MODE (y))
1180 : reg_or_cmp_int16_operand (y, GET_MODE (y));
1181
1182 if (! ok_const)
1183 y = force_reg (GET_MODE (x), y);
1184 }
1185 }
1186
1187 switch (compare_code)
1188 {
1189 case EQ :
1190 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1191 break;
1192 case LT :
1193 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1194 break;
1195 case LTU :
1196 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1197 break;
1198
1199 default:
1200 abort ();
1201 }
1202
1203 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
1204 }
1205 \f
1206 /* Split a 2 word move (DI or DF) into component parts. */
1207
1208 rtx
1209 gen_split_move_double (rtx operands[])
1210 {
1211 enum machine_mode mode = GET_MODE (operands[0]);
1212 rtx dest = operands[0];
1213 rtx src = operands[1];
1214 rtx val;
1215
1216 /* We might have (SUBREG (MEM)) here, so just get rid of the
1217 subregs to make this code simpler. It is safe to call
1218 alter_subreg any time after reload. */
1219 if (GET_CODE (dest) == SUBREG)
1220 alter_subreg (&dest);
1221 if (GET_CODE (src) == SUBREG)
1222 alter_subreg (&src);
1223
1224 start_sequence ();
1225 if (GET_CODE (dest) == REG)
1226 {
1227 int dregno = REGNO (dest);
1228
1229 /* Reg = reg. */
1230 if (GET_CODE (src) == REG)
1231 {
1232 int sregno = REGNO (src);
1233
1234 int reverse = (dregno == sregno + 1);
1235
1236 /* We normally copy the low-numbered register first. However, if
1237 the first register operand 0 is the same as the second register of
1238 operand 1, we must copy in the opposite order. */
1239 emit_insn (gen_rtx_SET (VOIDmode,
1240 operand_subword (dest, reverse, TRUE, mode),
1241 operand_subword (src, reverse, TRUE, mode)));
1242
1243 emit_insn (gen_rtx_SET (VOIDmode,
1244 operand_subword (dest, !reverse, TRUE, mode),
1245 operand_subword (src, !reverse, TRUE, mode)));
1246 }
1247
1248 /* Reg = constant. */
1249 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1250 {
1251 rtx words[2];
1252 split_double (src, &words[0], &words[1]);
1253 emit_insn (gen_rtx_SET (VOIDmode,
1254 operand_subword (dest, 0, TRUE, mode),
1255 words[0]));
1256
1257 emit_insn (gen_rtx_SET (VOIDmode,
1258 operand_subword (dest, 1, TRUE, mode),
1259 words[1]));
1260 }
1261
1262 /* Reg = mem. */
1263 else if (GET_CODE (src) == MEM)
1264 {
1265 /* If the high-address word is used in the address, we must load it
1266 last. Otherwise, load it first. */
1267 int reverse
1268 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
1269
1270 /* We used to optimize loads from single registers as
1271
1272 ld r1,r3+; ld r2,r3
1273
1274 if r3 were not used subsequently. However, the REG_NOTES aren't
1275 propagated correctly by the reload phase, and it can cause bad
1276 code to be generated. We could still try:
1277
1278 ld r1,r3+; ld r2,r3; addi r3,-4
1279
1280 which saves 2 bytes and doesn't force longword alignment. */
1281 emit_insn (gen_rtx_SET (VOIDmode,
1282 operand_subword (dest, reverse, TRUE, mode),
1283 adjust_address (src, SImode,
1284 reverse * UNITS_PER_WORD)));
1285
1286 emit_insn (gen_rtx_SET (VOIDmode,
1287 operand_subword (dest, !reverse, TRUE, mode),
1288 adjust_address (src, SImode,
1289 !reverse * UNITS_PER_WORD)));
1290 }
1291 else
1292 abort ();
1293 }
1294
1295 /* Mem = reg. */
1296 /* We used to optimize loads from single registers as
1297
1298 st r1,r3; st r2,+r3
1299
1300 if r3 were not used subsequently. However, the REG_NOTES aren't
1301 propagated correctly by the reload phase, and it can cause bad
1302 code to be generated. We could still try:
1303
1304 st r1,r3; st r2,+r3; addi r3,-4
1305
1306 which saves 2 bytes and doesn't force longword alignment. */
1307 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1308 {
1309 emit_insn (gen_rtx_SET (VOIDmode,
1310 adjust_address (dest, SImode, 0),
1311 operand_subword (src, 0, TRUE, mode)));
1312
1313 emit_insn (gen_rtx_SET (VOIDmode,
1314 adjust_address (dest, SImode, UNITS_PER_WORD),
1315 operand_subword (src, 1, TRUE, mode)));
1316 }
1317
1318 else
1319 abort ();
1320
1321 val = get_insns ();
1322 end_sequence ();
1323 return val;
1324 }
1325
1326 \f
1327 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1328
1329 int
1330 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1331 tree type, int named ATTRIBUTE_UNUSED)
1332 {
1333 int ret;
1334 unsigned int size =
1335 (((mode == BLKmode && type)
1336 ? (unsigned int) int_size_in_bytes (type)
1337 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1338 / UNITS_PER_WORD;
1339
1340 if (*cum >= M32R_MAX_PARM_REGS)
1341 ret = 0;
1342 else if (*cum + size > M32R_MAX_PARM_REGS)
1343 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1344 else
1345 ret = 0;
1346
1347 return ret;
1348 }
1349
1350 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1351
1352 static bool
1353 m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1354 {
1355 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1356 }
1357
1358 /* Do any needed setup for a variadic function. For the M32R, we must
1359 create a register parameter block, and then copy any anonymous arguments
1360 in registers to memory.
1361
1362 CUM has not been updated for the last named argument which has type TYPE
1363 and mode MODE, and we rely on this fact. */
1364
1365 static void
1366 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1367 tree type, int *pretend_size, int no_rtl)
1368 {
1369 int first_anon_arg;
1370
1371 if (no_rtl)
1372 return;
1373
1374 /* All BLKmode values are passed by reference. */
1375 if (mode == BLKmode)
1376 abort ();
1377
1378 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1379 + ROUND_ADVANCE_ARG (mode, type));
1380
1381 if (first_anon_arg < M32R_MAX_PARM_REGS)
1382 {
1383 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1384 int first_reg_offset = first_anon_arg;
1385 /* Size in words to "pretend" allocate. */
1386 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1387 rtx regblock;
1388
1389 regblock = gen_rtx_MEM (BLKmode,
1390 plus_constant (arg_pointer_rtx,
1391 FIRST_PARM_OFFSET (0)));
1392 set_mem_alias_set (regblock, get_varargs_alias_set ());
1393 move_block_from_reg (first_reg_offset, regblock, size);
1394
1395 *pretend_size = (size * UNITS_PER_WORD);
1396 }
1397 }
1398
1399 \f
1400 /* Return true if INSN is real instruction bearing insn. */
1401
1402 static int
1403 m32r_is_insn (rtx insn)
1404 {
1405 return (INSN_P (insn)
1406 && GET_CODE (PATTERN (insn)) != USE
1407 && GET_CODE (PATTERN (insn)) != CLOBBER
1408 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1409 }
1410
1411 /* Increase the priority of long instructions so that the
1412 short instructions are scheduled ahead of the long ones. */
1413
1414 static int
1415 m32r_adjust_priority (rtx insn, int priority)
1416 {
1417 if (m32r_is_insn (insn)
1418 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1419 priority <<= 3;
1420
1421 return priority;
1422 }
1423
1424 \f
1425 /* Indicate how many instructions can be issued at the same time.
1426 This is sort of a lie. The m32r can issue only 1 long insn at
1427 once, but it can issue 2 short insns. The default therefore is
1428 set at 2, but this can be overridden by the command line option
1429 -missue-rate=1. */
1430
1431 static int
1432 m32r_issue_rate (void)
1433 {
1434 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1435 }
1436 \f
1437 /* Cost functions. */
1438
1439 static bool
1440 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1441 {
1442 switch (code)
1443 {
1444 /* Small integers are as cheap as registers. 4 byte values can be
1445 fetched as immediate constants - let's give that the cost of an
1446 extra insn. */
1447 case CONST_INT:
1448 if (INT16_P (INTVAL (x)))
1449 {
1450 *total = 0;
1451 return true;
1452 }
1453 /* FALLTHRU */
1454
1455 case CONST:
1456 case LABEL_REF:
1457 case SYMBOL_REF:
1458 *total = COSTS_N_INSNS (1);
1459 return true;
1460
1461 case CONST_DOUBLE:
1462 {
1463 rtx high, low;
1464
1465 split_double (x, &high, &low);
1466 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1467 + !INT16_P (INTVAL (low)));
1468 return true;
1469 }
1470
1471 case MULT:
1472 *total = COSTS_N_INSNS (3);
1473 return true;
1474
1475 case DIV:
1476 case UDIV:
1477 case MOD:
1478 case UMOD:
1479 *total = COSTS_N_INSNS (10);
1480 return true;
1481
1482 default:
1483 return false;
1484 }
1485 }
1486 \f
1487 /* Type of function DECL.
1488
1489 The result is cached. To reset the cache at the end of a function,
1490 call with DECL = NULL_TREE. */
1491
1492 enum m32r_function_type
1493 m32r_compute_function_type (tree decl)
1494 {
1495 /* Cached value. */
1496 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1497 /* Last function we were called for. */
1498 static tree last_fn = NULL_TREE;
1499
1500 /* Resetting the cached value? */
1501 if (decl == NULL_TREE)
1502 {
1503 fn_type = M32R_FUNCTION_UNKNOWN;
1504 last_fn = NULL_TREE;
1505 return fn_type;
1506 }
1507
1508 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1509 return fn_type;
1510
1511 /* Compute function type. */
1512 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1513 ? M32R_FUNCTION_INTERRUPT
1514 : M32R_FUNCTION_NORMAL);
1515
1516 last_fn = decl;
1517 return fn_type;
1518 }
1519 \f/* Function prologue/epilogue handlers. */
1520
1521 /* M32R stack frames look like:
1522
1523 Before call After call
1524 +-----------------------+ +-----------------------+
1525 | | | |
1526 high | local variables, | | local variables, |
1527 mem | reg save area, etc. | | reg save area, etc. |
1528 | | | |
1529 +-----------------------+ +-----------------------+
1530 | | | |
1531 | arguments on stack. | | arguments on stack. |
1532 | | | |
1533 SP+0->+-----------------------+ +-----------------------+
1534 | reg parm save area, |
1535 | only created for |
1536 | variable argument |
1537 | functions |
1538 +-----------------------+
1539 | previous frame ptr |
1540 +-----------------------+
1541 | |
1542 | register save area |
1543 | |
1544 +-----------------------+
1545 | return address |
1546 +-----------------------+
1547 | |
1548 | local variables |
1549 | |
1550 +-----------------------+
1551 | |
1552 | alloca allocations |
1553 | |
1554 +-----------------------+
1555 | |
1556 low | arguments on stack |
1557 memory | |
1558 SP+0->+-----------------------+
1559
1560 Notes:
1561 1) The "reg parm save area" does not exist for non variable argument fns.
1562 2) The "reg parm save area" can be eliminated completely if we saved regs
1563 containing anonymous args separately but that complicates things too
1564 much (so it's not done).
1565 3) The return address is saved after the register save area so as to have as
1566 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1567
1568 /* Structure to be filled in by m32r_compute_frame_size with register
1569 save masks, and offsets for the current function. */
1570 struct m32r_frame_info
1571 {
1572 unsigned int total_size; /* # bytes that the entire frame takes up. */
1573 unsigned int extra_size; /* # bytes of extra stuff. */
1574 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1575 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1576 unsigned int reg_size; /* # bytes needed to store regs. */
1577 unsigned int var_size; /* # bytes that variables take up. */
1578 unsigned int gmask; /* Mask of saved gp registers. */
1579 unsigned int save_fp; /* Nonzero if fp must be saved. */
1580 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1581 int initialized; /* Nonzero if frame size already calculated. */
1582 };
1583
1584 /* Current frame information calculated by m32r_compute_frame_size. */
1585 static struct m32r_frame_info current_frame_info;
1586
1587 /* Zero structure to initialize current_frame_info. */
1588 static struct m32r_frame_info zero_frame_info;
1589
1590 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1591 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1592
1593 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1594 The return address and frame pointer are treated separately.
1595 Don't consider them here. */
1596 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1597 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1598 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1599
1600 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1601 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1602
1603 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1604 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1605
1606 /* Return the bytes needed to compute the frame pointer from the current
1607 stack pointer.
1608
1609 SIZE is the size needed for local variables. */
1610
1611 unsigned int
1612 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1613 {
1614 int regno;
1615 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1616 unsigned int reg_size, frame_size;
1617 unsigned int gmask;
1618 enum m32r_function_type fn_type;
1619 int interrupt_p;
1620 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1621
1622 var_size = M32R_STACK_ALIGN (size);
1623 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1624 pretend_size = current_function_pretend_args_size;
1625 extra_size = FIRST_PARM_OFFSET (0);
1626 total_size = extra_size + pretend_size + args_size + var_size;
1627 reg_size = 0;
1628 gmask = 0;
1629
1630 /* See if this is an interrupt handler. Call used registers must be saved
1631 for them too. */
1632 fn_type = m32r_compute_function_type (current_function_decl);
1633 interrupt_p = M32R_INTERRUPT_P (fn_type);
1634
1635 /* Calculate space needed for registers. */
1636 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1637 {
1638 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1639 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1640 {
1641 reg_size += UNITS_PER_WORD;
1642 gmask |= 1 << regno;
1643 }
1644 }
1645
1646 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1647 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1648
1649 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1650 * UNITS_PER_WORD);
1651 total_size += reg_size;
1652
1653 /* ??? Not sure this is necessary, and I don't think the epilogue
1654 handler will do the right thing if this changes total_size. */
1655 total_size = M32R_STACK_ALIGN (total_size);
1656
1657 frame_size = total_size - (pretend_size + reg_size);
1658
1659 /* Save computed information. */
1660 current_frame_info.total_size = total_size;
1661 current_frame_info.extra_size = extra_size;
1662 current_frame_info.pretend_size = pretend_size;
1663 current_frame_info.var_size = var_size;
1664 current_frame_info.args_size = args_size;
1665 current_frame_info.reg_size = reg_size;
1666 current_frame_info.gmask = gmask;
1667 current_frame_info.initialized = reload_completed;
1668
1669 /* Ok, we're done. */
1670 return total_size;
1671 }
1672 \f
1673 /* The table we use to reference PIC data. */
1674 static rtx global_offset_table;
1675
1676 static void
1677 m32r_reload_lr (rtx sp, int size)
1678 {
1679 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1680
1681 if (size == 0)
1682 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1683 else if (size <= 32768)
1684 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1685 gen_rtx_PLUS (Pmode, sp,
1686 GEN_INT (size)))));
1687 else
1688 {
1689 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1690
1691 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1692 emit_insn (gen_addsi3 (tmp, tmp, sp));
1693 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1694 }
1695
1696 emit_insn (gen_rtx_USE (VOIDmode, lr));
1697 }
1698
1699 void
1700 m32r_load_pic_register (void)
1701 {
1702 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1703 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1704 GEN_INT (TARGET_MODEL_SMALL)));
1705
1706 /* Need to emit this whether or not we obey regdecls,
1707 since setjmp/longjmp can cause life info to screw up. */
1708 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1709 }
1710
1711 /* Expand the m32r prologue as a series of insns. */
1712
1713 void
1714 m32r_expand_prologue (void)
1715 {
1716 int regno;
1717 int frame_size;
1718 unsigned int gmask;
1719 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1720
1721 if (! current_frame_info.initialized)
1722 m32r_compute_frame_size (get_frame_size ());
1723
1724 gmask = current_frame_info.gmask;
1725
1726 /* These cases shouldn't happen. Catch them now. */
1727 if (current_frame_info.total_size == 0 && gmask)
1728 abort ();
1729
1730 /* Allocate space for register arguments if this is a variadic function. */
1731 if (current_frame_info.pretend_size != 0)
1732 {
1733 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1734 the wrong result on a 64-bit host. */
1735 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1736 emit_insn (gen_addsi3 (stack_pointer_rtx,
1737 stack_pointer_rtx,
1738 GEN_INT (-pretend_size)));
1739 }
1740
1741 /* Save any registers we need to and set up fp. */
1742 if (current_frame_info.save_fp)
1743 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1744
1745 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1746
1747 /* Save any needed call-saved regs (and call-used if this is an
1748 interrupt handler). */
1749 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1750 {
1751 if ((gmask & (1 << regno)) != 0)
1752 emit_insn (gen_movsi_push (stack_pointer_rtx,
1753 gen_rtx_REG (Pmode, regno)));
1754 }
1755
1756 if (current_frame_info.save_lr)
1757 emit_insn (gen_movsi_push (stack_pointer_rtx,
1758 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1759
1760 /* Allocate the stack frame. */
1761 frame_size = (current_frame_info.total_size
1762 - (current_frame_info.pretend_size
1763 + current_frame_info.reg_size));
1764
1765 if (frame_size == 0)
1766 ; /* Nothing to do. */
1767 else if (frame_size <= 32768)
1768 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1769 GEN_INT (-frame_size)));
1770 else
1771 {
1772 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1773
1774 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1775 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1776 }
1777
1778 if (frame_pointer_needed)
1779 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1780
1781 if (current_function_profile)
1782 /* Push lr for mcount (form_pc, x). */
1783 emit_insn (gen_movsi_push (stack_pointer_rtx,
1784 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1785
1786 if (pic_reg_used)
1787 {
1788 m32r_load_pic_register ();
1789 m32r_reload_lr (stack_pointer_rtx,
1790 (current_function_profile ? 0 : frame_size));
1791 }
1792
1793 if (current_function_profile && !pic_reg_used)
1794 emit_insn (gen_blockage ());
1795 }
1796
1797 \f
1798 /* Set up the stack and frame pointer (if desired) for the function.
1799 Note, if this is changed, you need to mirror the changes in
1800 m32r_compute_frame_size which calculates the prolog size. */
1801
1802 static void
1803 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1804 {
1805 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1806
1807 /* If this is an interrupt handler, mark it as such. */
1808 if (M32R_INTERRUPT_P (fn_type))
1809 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1810
1811 if (! current_frame_info.initialized)
1812 m32r_compute_frame_size (size);
1813
1814 /* This is only for the human reader. */
1815 fprintf (file,
1816 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1817 ASM_COMMENT_START,
1818 current_frame_info.var_size,
1819 current_frame_info.reg_size / 4,
1820 current_frame_info.args_size,
1821 current_frame_info.extra_size);
1822 }
1823 \f
1824 /* Do any necessary cleanup after a function to restore stack, frame,
1825 and regs. */
1826
1827 static void
1828 m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1829 {
1830 int regno;
1831 int noepilogue = FALSE;
1832 int total_size;
1833 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1834
1835 /* This is only for the human reader. */
1836 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1837
1838 if (!current_frame_info.initialized)
1839 abort ();
1840 total_size = current_frame_info.total_size;
1841
1842 if (total_size == 0)
1843 {
1844 rtx insn = get_last_insn ();
1845
1846 /* If the last insn was a BARRIER, we don't have to write any code
1847 because a jump (aka return) was put there. */
1848 if (GET_CODE (insn) == NOTE)
1849 insn = prev_nonnote_insn (insn);
1850 if (insn && GET_CODE (insn) == BARRIER)
1851 noepilogue = TRUE;
1852 }
1853
1854 if (!noepilogue)
1855 {
1856 unsigned int var_size = current_frame_info.var_size;
1857 unsigned int args_size = current_frame_info.args_size;
1858 unsigned int gmask = current_frame_info.gmask;
1859 int can_trust_sp_p = !current_function_calls_alloca;
1860 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1861 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1862
1863 /* The first thing to do is point the sp at the bottom of the register
1864 save area. */
1865 if (can_trust_sp_p)
1866 {
1867 unsigned int reg_offset = var_size + args_size;
1868 if (reg_offset == 0)
1869 ; /* Nothing to do. */
1870 else if (reg_offset < 128)
1871 fprintf (file, "\taddi %s,%s%d\n",
1872 sp_str, IMMEDIATE_PREFIX, reg_offset);
1873 else if (reg_offset < 32768)
1874 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1875 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1876 else
1877 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1878 reg_names[PROLOGUE_TMP_REGNUM],
1879 IMMEDIATE_PREFIX, reg_offset,
1880 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1881 }
1882 else if (frame_pointer_needed)
1883 {
1884 unsigned int reg_offset = var_size + args_size;
1885
1886 if (reg_offset == 0)
1887 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1888 else if (reg_offset < 32768)
1889 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1890 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1891 else
1892 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1893 reg_names[PROLOGUE_TMP_REGNUM],
1894 IMMEDIATE_PREFIX, reg_offset,
1895 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1896 }
1897 else
1898 abort ();
1899
1900 if (current_frame_info.save_lr)
1901 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1902
1903 /* Restore any saved registers, in reverse order of course. */
1904 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1905 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1906 {
1907 if ((gmask & (1L << regno)) != 0)
1908 fprintf (file, "\tpop %s\n", reg_names[regno]);
1909 }
1910
1911 if (current_frame_info.save_fp)
1912 fprintf (file, "\tpop %s\n", fp_str);
1913
1914 /* Remove varargs area if present. */
1915 if (current_frame_info.pretend_size != 0)
1916 fprintf (file, "\taddi %s,%s%d\n",
1917 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1918
1919 /* Emit the return instruction. */
1920 if (M32R_INTERRUPT_P (fn_type))
1921 fprintf (file, "\trte\n");
1922 else
1923 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1924 }
1925
1926 /* Reset state info for each function. */
1927 current_frame_info = zero_frame_info;
1928 m32r_compute_function_type (NULL_TREE);
1929 }
1930 \f
1931 /* Return nonzero if this function is known to have a null or 1 instruction
1932 epilogue. */
1933
1934 int
1935 direct_return (void)
1936 {
1937 if (!reload_completed)
1938 return FALSE;
1939
1940 if (! current_frame_info.initialized)
1941 m32r_compute_frame_size (get_frame_size ());
1942
1943 return current_frame_info.total_size == 0;
1944 }
1945
1946 \f
1947 /* PIC. */
1948
1949 int
1950 m32r_legitimate_pic_operand_p (rtx x)
1951 {
1952 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1953 return 0;
1954
1955 if (GET_CODE (x) == CONST
1956 && GET_CODE (XEXP (x, 0)) == PLUS
1957 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1958 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1959 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1960 return 0;
1961
1962 return 1;
1963 }
1964
1965 rtx
1966 m32r_legitimize_pic_address (rtx orig, rtx reg)
1967 {
1968 #ifdef DEBUG_PIC
1969 printf("m32r_legitimize_pic_address()\n");
1970 #endif
1971
1972 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1973 {
1974 rtx pic_ref, address;
1975 rtx insn;
1976 int subregs = 0;
1977
1978 if (reg == 0)
1979 {
1980 if (reload_in_progress || reload_completed)
1981 abort ();
1982 else
1983 reg = gen_reg_rtx (Pmode);
1984
1985 subregs = 1;
1986 }
1987
1988 if (subregs)
1989 address = gen_reg_rtx (Pmode);
1990 else
1991 address = reg;
1992
1993 emit_insn (gen_pic_load_addr (address, orig));
1994
1995 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1996 pic_ref = gen_rtx_MEM (Pmode, address);
1997
1998 RTX_UNCHANGING_P (pic_ref) = 1;
1999 insn = emit_move_insn (reg, pic_ref);
2000 current_function_uses_pic_offset_table = 1;
2001 #if 0
2002 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2003 by loop. */
2004 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2005 REG_NOTES (insn));
2006 #endif
2007 return reg;
2008 }
2009 else if (GET_CODE (orig) == CONST)
2010 {
2011 rtx base, offset;
2012
2013 if (GET_CODE (XEXP (orig, 0)) == PLUS
2014 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
2015 return orig;
2016
2017 if (reg == 0)
2018 {
2019 if (reload_in_progress || reload_completed)
2020 abort ();
2021 else
2022 reg = gen_reg_rtx (Pmode);
2023 }
2024
2025 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2026 {
2027 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
2028 if (base == reg)
2029 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
2030 else
2031 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
2032 }
2033 else
2034 return orig;
2035
2036 if (GET_CODE (offset) == CONST_INT)
2037 {
2038 if (INT16_P (INTVAL (offset)))
2039 return plus_constant (base, INTVAL (offset));
2040 else if (! reload_in_progress && ! reload_completed)
2041 offset = force_reg (Pmode, offset);
2042 else
2043 /* If we reach here, then something is seriously wrong. */
2044 abort ();
2045 }
2046
2047 return gen_rtx_PLUS (Pmode, base, offset);
2048 }
2049
2050 return orig;
2051 }
2052
2053 /* Emit special PIC prologues and epilogues. */
2054
2055 void
2056 m32r_finalize_pic (void)
2057 {
2058 current_function_uses_pic_offset_table |= current_function_profile;
2059 }
2060 \f
2061 /* Nested function support. */
2062
2063 /* Emit RTL insns to initialize the variable parts of a trampoline.
2064 FNADDR is an RTX for the address of the function's pure code.
2065 CXT is an RTX for the static chain value for the function. */
2066
2067 void
2068 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
2069 rtx fnaddr ATTRIBUTE_UNUSED,
2070 rtx cxt ATTRIBUTE_UNUSED)
2071 {
2072 }
2073 \f
2074 static void
2075 m32r_file_start (void)
2076 {
2077 default_file_start ();
2078
2079 if (flag_verbose_asm)
2080 fprintf (asm_out_file,
2081 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
2082 ASM_COMMENT_START, g_switch_value);
2083
2084 if (TARGET_LITTLE_ENDIAN)
2085 fprintf (asm_out_file, "\t.little\n");
2086 }
2087 \f
2088 /* Print operand X (an rtx) in assembler syntax to file FILE.
2089 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2090 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2091
2092 void
2093 m32r_print_operand (FILE * file, rtx x, int code)
2094 {
2095 rtx addr;
2096
2097 switch (code)
2098 {
2099 /* The 's' and 'p' codes are used by output_block_move() to
2100 indicate post-increment 's'tores and 'p're-increment loads. */
2101 case 's':
2102 if (GET_CODE (x) == REG)
2103 fprintf (file, "@+%s", reg_names [REGNO (x)]);
2104 else
2105 output_operand_lossage ("invalid operand to %%s code");
2106 return;
2107
2108 case 'p':
2109 if (GET_CODE (x) == REG)
2110 fprintf (file, "@%s+", reg_names [REGNO (x)]);
2111 else
2112 output_operand_lossage ("invalid operand to %%p code");
2113 return;
2114
2115 case 'R' :
2116 /* Write second word of DImode or DFmode reference,
2117 register or memory. */
2118 if (GET_CODE (x) == REG)
2119 fputs (reg_names[REGNO (x)+1], file);
2120 else if (GET_CODE (x) == MEM)
2121 {
2122 fprintf (file, "@(");
2123 /* Handle possible auto-increment. Since it is pre-increment and
2124 we have already done it, we can just use an offset of four. */
2125 /* ??? This is taken from rs6000.c I think. I don't think it is
2126 currently necessary, but keep it around. */
2127 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2128 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2129 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2130 else
2131 output_address (plus_constant (XEXP (x, 0), 4));
2132 fputc (')', file);
2133 }
2134 else
2135 output_operand_lossage ("invalid operand to %%R code");
2136 return;
2137
2138 case 'H' : /* High word. */
2139 case 'L' : /* Low word. */
2140 if (GET_CODE (x) == REG)
2141 {
2142 /* L = least significant word, H = most significant word. */
2143 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2144 fputs (reg_names[REGNO (x)], file);
2145 else
2146 fputs (reg_names[REGNO (x)+1], file);
2147 }
2148 else if (GET_CODE (x) == CONST_INT
2149 || GET_CODE (x) == CONST_DOUBLE)
2150 {
2151 rtx first, second;
2152
2153 split_double (x, &first, &second);
2154 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2155 code == 'L' ? INTVAL (first) : INTVAL (second));
2156 }
2157 else
2158 output_operand_lossage ("invalid operand to %%H/%%L code");
2159 return;
2160
2161 case 'A' :
2162 {
2163 char str[30];
2164
2165 if (GET_CODE (x) != CONST_DOUBLE
2166 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2167 fatal_insn ("bad insn for 'A'", x);
2168
2169 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
2170 fprintf (file, "%s", str);
2171 return;
2172 }
2173
2174 case 'B' : /* Bottom half. */
2175 case 'T' : /* Top half. */
2176 /* Output the argument to a `seth' insn (sets the Top half-word).
2177 For constants output arguments to a seth/or3 pair to set Top and
2178 Bottom halves. For symbols output arguments to a seth/add3 pair to
2179 set Top and Bottom halves. The difference exists because for
2180 constants seth/or3 is more readable but for symbols we need to use
2181 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
2182 switch (GET_CODE (x))
2183 {
2184 case CONST_INT :
2185 case CONST_DOUBLE :
2186 {
2187 rtx first, second;
2188
2189 split_double (x, &first, &second);
2190 x = WORDS_BIG_ENDIAN ? second : first;
2191 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2192 (code == 'B'
2193 ? INTVAL (x) & 0xffff
2194 : (INTVAL (x) >> 16) & 0xffff));
2195 }
2196 return;
2197 case CONST :
2198 case SYMBOL_REF :
2199 if (code == 'B'
2200 && small_data_operand (x, VOIDmode))
2201 {
2202 fputs ("sda(", file);
2203 output_addr_const (file, x);
2204 fputc (')', file);
2205 return;
2206 }
2207 /* fall through */
2208 case LABEL_REF :
2209 fputs (code == 'T' ? "shigh(" : "low(", file);
2210 output_addr_const (file, x);
2211 fputc (')', file);
2212 return;
2213 default :
2214 output_operand_lossage ("invalid operand to %%T/%%B code");
2215 return;
2216 }
2217 break;
2218
2219 case 'U' :
2220 /* ??? wip */
2221 /* Output a load/store with update indicator if appropriate. */
2222 if (GET_CODE (x) == MEM)
2223 {
2224 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2225 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2226 fputs (".a", file);
2227 }
2228 else
2229 output_operand_lossage ("invalid operand to %%U code");
2230 return;
2231
2232 case 'N' :
2233 /* Print a constant value negated. */
2234 if (GET_CODE (x) == CONST_INT)
2235 output_addr_const (file, GEN_INT (- INTVAL (x)));
2236 else
2237 output_operand_lossage ("invalid operand to %%N code");
2238 return;
2239
2240 case 'X' :
2241 /* Print a const_int in hex. Used in comments. */
2242 if (GET_CODE (x) == CONST_INT)
2243 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
2244 return;
2245
2246 case '#' :
2247 fputs (IMMEDIATE_PREFIX, file);
2248 return;
2249
2250 case 0 :
2251 /* Do nothing special. */
2252 break;
2253
2254 default :
2255 /* Unknown flag. */
2256 output_operand_lossage ("invalid operand output code");
2257 }
2258
2259 switch (GET_CODE (x))
2260 {
2261 case REG :
2262 fputs (reg_names[REGNO (x)], file);
2263 break;
2264
2265 case MEM :
2266 addr = XEXP (x, 0);
2267 if (GET_CODE (addr) == PRE_INC)
2268 {
2269 if (GET_CODE (XEXP (addr, 0)) != REG)
2270 fatal_insn ("pre-increment address is not a register", x);
2271
2272 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2273 }
2274 else if (GET_CODE (addr) == PRE_DEC)
2275 {
2276 if (GET_CODE (XEXP (addr, 0)) != REG)
2277 fatal_insn ("pre-decrement address is not a register", x);
2278
2279 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2280 }
2281 else if (GET_CODE (addr) == POST_INC)
2282 {
2283 if (GET_CODE (XEXP (addr, 0)) != REG)
2284 fatal_insn ("post-increment address is not a register", x);
2285
2286 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2287 }
2288 else
2289 {
2290 fputs ("@(", file);
2291 output_address (XEXP (x, 0));
2292 fputc (')', file);
2293 }
2294 break;
2295
2296 case CONST_DOUBLE :
2297 /* We handle SFmode constants here as output_addr_const doesn't. */
2298 if (GET_MODE (x) == SFmode)
2299 {
2300 REAL_VALUE_TYPE d;
2301 long l;
2302
2303 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2304 REAL_VALUE_TO_TARGET_SINGLE (d, l);
2305 fprintf (file, "0x%08lx", l);
2306 break;
2307 }
2308
2309 /* Fall through. Let output_addr_const deal with it. */
2310
2311 default :
2312 output_addr_const (file, x);
2313 break;
2314 }
2315 }
2316
2317 /* Print a memory address as an operand to reference that memory location. */
2318
2319 void
2320 m32r_print_operand_address (FILE * file, rtx addr)
2321 {
2322 rtx base;
2323 rtx index = 0;
2324 int offset = 0;
2325
2326 switch (GET_CODE (addr))
2327 {
2328 case REG :
2329 fputs (reg_names[REGNO (addr)], file);
2330 break;
2331
2332 case PLUS :
2333 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2334 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2335 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2336 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2337 else
2338 base = XEXP (addr, 0), index = XEXP (addr, 1);
2339 if (GET_CODE (base) == REG)
2340 {
2341 /* Print the offset first (if present) to conform to the manual. */
2342 if (index == 0)
2343 {
2344 if (offset != 0)
2345 fprintf (file, "%d,", offset);
2346 fputs (reg_names[REGNO (base)], file);
2347 }
2348 /* The chip doesn't support this, but left in for generality. */
2349 else if (GET_CODE (index) == REG)
2350 fprintf (file, "%s,%s",
2351 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2352 /* Not sure this can happen, but leave in for now. */
2353 else if (GET_CODE (index) == SYMBOL_REF)
2354 {
2355 output_addr_const (file, index);
2356 fputc (',', file);
2357 fputs (reg_names[REGNO (base)], file);
2358 }
2359 else
2360 fatal_insn ("bad address", addr);
2361 }
2362 else if (GET_CODE (base) == LO_SUM)
2363 {
2364 if (index != 0
2365 || GET_CODE (XEXP (base, 0)) != REG)
2366 abort ();
2367 if (small_data_operand (XEXP (base, 1), VOIDmode))
2368 fputs ("sda(", file);
2369 else
2370 fputs ("low(", file);
2371 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2372 fputs ("),", file);
2373 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2374 }
2375 else
2376 fatal_insn ("bad address", addr);
2377 break;
2378
2379 case LO_SUM :
2380 if (GET_CODE (XEXP (addr, 0)) != REG)
2381 fatal_insn ("lo_sum not of register", addr);
2382 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2383 fputs ("sda(", file);
2384 else
2385 fputs ("low(", file);
2386 output_addr_const (file, XEXP (addr, 1));
2387 fputs ("),", file);
2388 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2389 break;
2390
2391 case PRE_INC : /* Assume SImode. */
2392 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2393 break;
2394
2395 case PRE_DEC : /* Assume SImode. */
2396 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2397 break;
2398
2399 case POST_INC : /* Assume SImode. */
2400 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2401 break;
2402
2403 default :
2404 output_addr_const (file, addr);
2405 break;
2406 }
2407 }
2408
2409 /* Return true if the operands are the constants 0 and 1. */
2410
2411 int
2412 zero_and_one (rtx operand1, rtx operand2)
2413 {
2414 return
2415 GET_CODE (operand1) == CONST_INT
2416 && GET_CODE (operand2) == CONST_INT
2417 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2418 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2419 }
2420
2421 /* Return nonzero if the operand is suitable for use in a conditional move sequence. */
2422
2423 int
2424 conditional_move_operand (rtx operand, enum machine_mode mode)
2425 {
2426 /* Only defined for simple integers so far... */
2427 if (mode != SImode && mode != HImode && mode != QImode)
2428 return FALSE;
2429
2430 /* At the moment we can handle moving registers and loading constants. */
2431 /* To be added: Addition/subtraction/bitops/multiplication of registers. */
2432
2433 switch (GET_CODE (operand))
2434 {
2435 case REG:
2436 return 1;
2437
2438 case CONST_INT:
2439 return INT8_P (INTVAL (operand));
2440
2441 default:
2442 #if 0
2443 fprintf (stderr, "Test for cond move op of type: %s\n",
2444 GET_RTX_NAME (GET_CODE (operand)));
2445 #endif
2446 return 0;
2447 }
2448 }
2449
2450 /* Return true if the code is a test of the carry bit. */
2451
2452 int
2453 carry_compare_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2454 {
2455 rtx x;
2456
2457 if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2458 return FALSE;
2459
2460 if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2461 return FALSE;
2462
2463 x = XEXP (op, 0);
2464 if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2465 return FALSE;
2466
2467 x = XEXP (op, 1);
2468 if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2469 return FALSE;
2470
2471 return TRUE;
2472 }
2473
2474 /* Generate the correct assembler code to handle the conditional loading of a
2475 value into a register. It is known that the operands satisfy the
2476 conditional_move_operand() function above. The destination is operand[0].
2477 The condition is operand [1]. The 'true' value is operand [2] and the
2478 'false' value is operand [3]. */
2479
2480 char *
2481 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2482 {
2483 static char buffer [100];
2484 const char * dest = reg_names [REGNO (operands [0])];
2485
2486 buffer [0] = 0;
2487
2488 /* Destination must be a register. */
2489 if (GET_CODE (operands [0]) != REG)
2490 abort();
2491 if (! conditional_move_operand (operands [2], SImode))
2492 abort();
2493 if (! conditional_move_operand (operands [3], SImode))
2494 abort();
2495
2496 /* Check to see if the test is reversed. */
2497 if (GET_CODE (operands [1]) == NE)
2498 {
2499 rtx tmp = operands [2];
2500 operands [2] = operands [3];
2501 operands [3] = tmp;
2502 }
2503
2504 sprintf (buffer, "mvfc %s, cbr", dest);
2505
2506 /* If the true value was '0' then we need to invert the results of the move. */
2507 if (INTVAL (operands [2]) == 0)
2508 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2509 dest, dest);
2510
2511 return buffer;
2512 }
2513
2514 /* Returns true if the registers contained in the two
2515 rtl expressions are different. */
2516
2517 int
2518 m32r_not_same_reg (rtx a, rtx b)
2519 {
2520 int reg_a = -1;
2521 int reg_b = -2;
2522
2523 while (GET_CODE (a) == SUBREG)
2524 a = SUBREG_REG (a);
2525
2526 if (GET_CODE (a) == REG)
2527 reg_a = REGNO (a);
2528
2529 while (GET_CODE (b) == SUBREG)
2530 b = SUBREG_REG (b);
2531
2532 if (GET_CODE (b) == REG)
2533 reg_b = REGNO (b);
2534
2535 return reg_a != reg_b;
2536 }
2537
2538 \f
2539 rtx
2540 m32r_function_symbol (const char *name)
2541 {
2542 int extra_flags = 0;
2543 enum m32r_model model;
2544 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2545
2546 if (TARGET_MODEL_SMALL)
2547 model = M32R_MODEL_SMALL;
2548 else if (TARGET_MODEL_MEDIUM)
2549 model = M32R_MODEL_MEDIUM;
2550 else if (TARGET_MODEL_LARGE)
2551 model = M32R_MODEL_LARGE;
2552 else
2553 abort (); /* Shouldn't happen. */
2554 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2555
2556 if (extra_flags)
2557 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2558
2559 return sym;
2560 }
2561
2562 /* Use a library function to move some bytes. */
2563
2564 static void
2565 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2566 {
2567 /* We want to pass the size as Pmode, which will normally be SImode
2568 but will be DImode if we are using 64 bit longs and pointers. */
2569 if (GET_MODE (bytes_rtx) != VOIDmode
2570 && GET_MODE (bytes_rtx) != Pmode)
2571 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2572
2573 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2574 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2575 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2576 TYPE_UNSIGNED (sizetype)),
2577 TYPE_MODE (sizetype));
2578 }
2579
2580 /* The maximum number of bytes to copy using pairs of load/store instructions.
2581 If a block is larger than this then a loop will be generated to copy
2582 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
2583 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2584 string copy in it. */
2585 #define MAX_MOVE_BYTES 32
2586
2587 /* Expand string/block move operations.
2588
2589 operands[0] is the pointer to the destination.
2590 operands[1] is the pointer to the source.
2591 operands[2] is the number of bytes to move.
2592 operands[3] is the alignment. */
2593
2594 void
2595 m32r_expand_block_move (rtx operands[])
2596 {
2597 rtx orig_dst = operands[0];
2598 rtx orig_src = operands[1];
2599 rtx bytes_rtx = operands[2];
2600 rtx align_rtx = operands[3];
2601 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2602 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2603 int align = INTVAL (align_rtx);
2604 int leftover;
2605 rtx src_reg;
2606 rtx dst_reg;
2607
2608 if (constp && bytes <= 0)
2609 return;
2610
2611 /* Move the address into scratch registers. */
2612 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2613 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2614
2615 if (align > UNITS_PER_WORD)
2616 align = UNITS_PER_WORD;
2617
2618 /* If we prefer size over speed, always use a function call.
2619 If we do not know the size, use a function call.
2620 If the blocks are not word aligned, use a function call. */
2621 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2622 {
2623 block_move_call (dst_reg, src_reg, bytes_rtx);
2624 return;
2625 }
2626
2627 leftover = bytes % MAX_MOVE_BYTES;
2628 bytes -= leftover;
2629
2630 /* If necessary, generate a loop to handle the bulk of the copy. */
2631 if (bytes)
2632 {
2633 rtx label = NULL_RTX;
2634 rtx final_src = NULL_RTX;
2635 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2636 rtx rounded_total = GEN_INT (bytes);
2637 rtx new_dst_reg = gen_reg_rtx (SImode);
2638 rtx new_src_reg = gen_reg_rtx (SImode);
2639
2640 /* If we are going to have to perform this loop more than
2641 once, then generate a label and compute the address the
2642 source register will contain upon completion of the final
2643 iteration. */
2644 if (bytes > MAX_MOVE_BYTES)
2645 {
2646 final_src = gen_reg_rtx (Pmode);
2647
2648 if (INT16_P(bytes))
2649 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2650 else
2651 {
2652 emit_insn (gen_movsi (final_src, rounded_total));
2653 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2654 }
2655
2656 label = gen_label_rtx ();
2657 emit_label (label);
2658 }
2659
2660 /* It is known that output_block_move() will update src_reg to point
2661 to the word after the end of the source block, and dst_reg to point
2662 to the last word of the destination block, provided that the block
2663 is MAX_MOVE_BYTES long. */
2664 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2665 new_dst_reg, new_src_reg));
2666 emit_move_insn (dst_reg, new_dst_reg);
2667 emit_move_insn (src_reg, new_src_reg);
2668 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2669
2670 if (bytes > MAX_MOVE_BYTES)
2671 {
2672 emit_insn (gen_cmpsi (src_reg, final_src));
2673 emit_jump_insn (gen_bne (label));
2674 }
2675 }
2676
2677 if (leftover)
2678 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2679 gen_reg_rtx (SImode),
2680 gen_reg_rtx (SImode)));
2681 }
2682
2683 \f
2684 /* Emit load/stores for a small constant word aligned block_move.
2685
2686 operands[0] is the memory address of the destination.
2687 operands[1] is the memory address of the source.
2688 operands[2] is the number of bytes to move.
2689 operands[3] is a temp register.
2690 operands[4] is a temp register. */
2691
2692 void
2693 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2694 {
2695 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2696 int first_time;
2697 int got_extra = 0;
2698
2699 if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2700 abort ();
2701
2702 /* We do not have a post-increment store available, so the first set of
2703 stores are done without any increment, then the remaining ones can use
2704 the pre-increment addressing mode.
2705
2706 Note: expand_block_move() also relies upon this behavior when building
2707 loops to copy large blocks. */
2708 first_time = 1;
2709
2710 while (bytes > 0)
2711 {
2712 if (bytes >= 8)
2713 {
2714 if (first_time)
2715 {
2716 output_asm_insn ("ld\t%5, %p1", operands);
2717 output_asm_insn ("ld\t%6, %p1", operands);
2718 output_asm_insn ("st\t%5, @%0", operands);
2719 output_asm_insn ("st\t%6, %s0", operands);
2720 }
2721 else
2722 {
2723 output_asm_insn ("ld\t%5, %p1", operands);
2724 output_asm_insn ("ld\t%6, %p1", operands);
2725 output_asm_insn ("st\t%5, %s0", operands);
2726 output_asm_insn ("st\t%6, %s0", operands);
2727 }
2728
2729 bytes -= 8;
2730 }
2731 else if (bytes >= 4)
2732 {
2733 if (bytes > 4)
2734 got_extra = 1;
2735
2736 output_asm_insn ("ld\t%5, %p1", operands);
2737
2738 if (got_extra)
2739 output_asm_insn ("ld\t%6, %p1", operands);
2740
2741 if (first_time)
2742 output_asm_insn ("st\t%5, @%0", operands);
2743 else
2744 output_asm_insn ("st\t%5, %s0", operands);
2745
2746 bytes -= 4;
2747 }
2748 else
2749 {
2750 /* Get the entire next word, even though we do not want all of it.
2751 The saves us from doing several smaller loads, and we assume that
2752 we cannot cause a page fault when at least part of the word is in
2753 valid memory [since we don't get called if things aren't properly
2754 aligned]. */
2755 int dst_offset = first_time ? 0 : 4;
2756 /* The amount of increment we have to make to the
2757 destination pointer. */
2758 int dst_inc_amount = dst_offset + bytes - 4;
2759 /* The same for the source pointer. */
2760 int src_inc_amount = bytes;
2761 int last_shift;
2762 rtx my_operands[3];
2763
2764 /* If got_extra is true then we have already loaded
2765 the next word as part of loading and storing the previous word. */
2766 if (! got_extra)
2767 output_asm_insn ("ld\t%6, @%1", operands);
2768
2769 if (bytes >= 2)
2770 {
2771 bytes -= 2;
2772
2773 output_asm_insn ("sra3\t%5, %6, #16", operands);
2774 my_operands[0] = operands[5];
2775 my_operands[1] = GEN_INT (dst_offset);
2776 my_operands[2] = operands[0];
2777 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2778
2779 /* If there is a byte left to store then increment the
2780 destination address and shift the contents of the source
2781 register down by 8 bits. We could not do the address
2782 increment in the store half word instruction, because it does
2783 not have an auto increment mode. */
2784 if (bytes > 0) /* assert (bytes == 1) */
2785 {
2786 dst_offset += 2;
2787 last_shift = 8;
2788 }
2789 }
2790 else
2791 last_shift = 24;
2792
2793 if (bytes > 0)
2794 {
2795 my_operands[0] = operands[6];
2796 my_operands[1] = GEN_INT (last_shift);
2797 output_asm_insn ("srai\t%0, #%1", my_operands);
2798 my_operands[0] = operands[6];
2799 my_operands[1] = GEN_INT (dst_offset);
2800 my_operands[2] = operands[0];
2801 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2802 }
2803
2804 /* Update the destination pointer if needed. We have to do
2805 this so that the patterns matches what we output in this
2806 function. */
2807 if (dst_inc_amount
2808 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2809 {
2810 my_operands[0] = operands[0];
2811 my_operands[1] = GEN_INT (dst_inc_amount);
2812 output_asm_insn ("addi\t%0, #%1", my_operands);
2813 }
2814
2815 /* Update the source pointer if needed. We have to do this
2816 so that the patterns matches what we output in this
2817 function. */
2818 if (src_inc_amount
2819 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2820 {
2821 my_operands[0] = operands[1];
2822 my_operands[1] = GEN_INT (src_inc_amount);
2823 output_asm_insn ("addi\t%0, #%1", my_operands);
2824 }
2825
2826 bytes = 0;
2827 }
2828
2829 first_time = 0;
2830 }
2831 }
2832
2833 /* Return true if op is an integer constant, less than or equal to
2834 MAX_MOVE_BYTES. */
2835
2836 int
2837 m32r_block_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2838 {
2839 if (GET_CODE (op) != CONST_INT
2840 || INTVAL (op) > MAX_MOVE_BYTES
2841 || INTVAL (op) <= 0)
2842 return 0;
2843
2844 return 1;
2845 }
2846
2847 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2848
2849 int
2850 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2851 unsigned int new_reg)
2852 {
2853 /* Interrupt routines can't clobber any register that isn't already used. */
2854 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2855 && !regs_ever_live[new_reg])
2856 return 0;
2857
2858 /* We currently emit epilogues as text, not rtl, so the liveness
2859 of the return address register isn't visible. */
2860 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2861 return 0;
2862
2863 return 1;
2864 }
2865
2866 rtx
2867 m32r_return_addr (int count)
2868 {
2869 if (count != 0)
2870 return const0_rtx;
2871
2872 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2873 }
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