gcc/config/mips/irix-csr.c

   1 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
   2 #include <sys/fpu.h>
   3
   4 /* n32 and n64 applications usually run with the MIPS IV Flush to Zero
   5    bit set.  Clear it here so that gcc-generated code will handle
   6    subnormals correctly by default.  */
   7
   8 static void __attribute__((constructor))
   9 clear_flush_to_zero (void)
  10 {
  11   union fpc_csr csr;
  12
  13   csr.fc_word = get_fpc_csr ();
  14   csr.fc_struct.flush = 0;
  15   set_fpc_csr (csr.fc_word);
  16 }
  17 #endif