| blob | 63c1e4f3f6031d5fd0885d3f4274707307348649 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
125 /* Number of attempts to combine instructions in this function. */
129 /* Number of attempts that got as far as substitution in this function. */
133 /* Number of instructions combined with added SETs in this function. */
137 /* Number of instructions combined in this function. */
141 /* Totals over entire compilation. */
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
161 \f
163 /* Record last point of death of (hard or pseudo) register n. */
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
176 following ways:
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
191 register's value
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
196 table.
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
214 rtx last_set_value;
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
221 /* Record the value of label_tick when the value for register n is placed in
222 last_set_value. */
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
249 zero.
251 If an entry is zero, it means that we don't know anything special. */
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
266 value. */
274 /* Record the luid of the last insn that invalidated memory
275 (anything that writes memory, and subroutine calls, but not pushes). */
279 /* Record the luid of the last CALL_INSN
280 so we can tell whether a potential combination crosses any calls. */
284 /* When `subst' is called, this is the insn that is being modified
285 (by combining in a previous insn). The PATTERN of this insn
286 is still the old pattern partially modified and it should not be
287 looked at, but this may be used to examine the successors of the insn
288 to judge whether a simplification is valid. */
292 /* This is the lowest LUID that `subst' is currently dealing with.
293 get_last_value will not return a value if the register was set at or
294 after this LUID. If not for this mechanism, we could get confused if
295 I2 or I1 in try_combine were an insn that used the old value of a register
296 to obtain a new value. In that case, we might erroneously get the
297 new value of the register when we wanted the old one. */
301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
302 must consider all these registers to be always live. */
306 /* This is an insn to which a LOG_LINKS entry has been added. If this
307 insn is the earlier than I2 or I3, combine should rescan starting at
308 that location. */
312 /* Basic block in which we are performing combines. */
316 \f
317 /* Length of the currently allocated uid_insn_cost array. */
321 /* The following array records the insn_rtx_cost for every insn
322 in the instruction stream. */
326 /* The following array records the LOG_LINKS for every insn in the
327 instruction stream as struct insn_link pointers. */
333 };
337 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
338 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
340 #define FOR_EACH_LOG_LINK(L, INSN) \
341 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
343 /* Links for LOG_LINKS are allocated from this obstack. */
347 /* Allocate a link. */
351 {
359 }
361 /* Incremented for each basic block. */
365 /* Reset to label_tick for each extended basic block in scanning order. */
369 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
370 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
374 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
375 be safely used. It is zero while computing them and after combine has
376 completed. This former test prevents propagating values based on
377 previously set values, which can be incorrect if a variable is modified
378 in a loop. */
382 \f
383 /* Record one modification to rtl structure
384 to be undone by storing old_contents into *where. */
388 struct undo
389 {
394 };
396 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
397 num_undo says how many are currently recorded.
399 other_insn is nonzero if we have modified some other insn in the process
400 of working on subst_insn. It must be verified too. */
402 struct undobuf
403 {
407 };
411 /* Number of times the pseudo being substituted for
412 was found and replaced. */
417 machine_mode,
421 machine_mode,
493 \f
495 /* It is not safe to use ordinary gen_lowpart in combine.
496 See comments in gen_lowpart_for_combine. */
497 #undef RTL_HOOKS_GEN_LOWPART
498 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
500 /* Our implementation of gen_lowpart never emits a new pseudo. */
501 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
502 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
504 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
505 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
507 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
508 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
510 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
511 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
515 \f
516 /* Convenience wrapper for the canonicalize_comparison target hook.
517 Target hooks cannot use enum rtx_code. */
521 {
525 }
527 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
528 PATTERN can not be split. Otherwise, it returns an insn sequence.
529 This is a wrapper around split_insns which ensures that the
530 reg_stat vector is made larger if the splitter creates a new
531 register. */
535 {
544 }
546 /* This is used by find_single_use to locate an rtx in LOC that
547 contains exactly one use of DEST, which is typically either a REG
548 or CC0. It returns a pointer to the innermost rtx expression
549 containing DEST. Appearances of DEST that are being used to
550 totally replace it are not counted. */
554 {
563 {
567 CASE_CONST_ANY:
572 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
573 of a REG that occupies all of the REG, the insn uses DEST if
574 it is mentioned in the destination or the source. Otherwise, we
575 need just check the source. */
595 }
597 /* If it wasn't one of the common cases above, check each expression and
598 vector of this code. Look for a unique usage of DEST. */
602 {
604 {
609 else
615 /* Duplicate usage. */
617 }
619 {
623 {
629 else
636 }
637 }
638 }
641 }
644 /* See if DEST, produced in INSN, is used only a single time in the
645 sequel. If so, return a pointer to the innermost rtx expression in which
646 it is used.
648 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
650 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
651 care about REG_DEAD notes or LOG_LINKS.
653 Otherwise, we find the single use by finding an insn that has a
654 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
655 only referenced once in that insn, we know that it must be the first
656 and last insn referencing DEST. */
660 {
661 basic_block bb;
666 #ifdef HAVE_cc0
668 {
678 }
679 #endif
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 #ifndef HAVE_cc0
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 static void
823 {
832 else
841 }
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 #endif
845 \f
846 /* Subroutine of try_combine. Determine whether the replacement patterns
847 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
848 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
849 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
850 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
851 of all the instructions can be estimated and the replacements are more
852 expensive than the original sequence. */
854 static bool
857 {
862 /* Lookup the original insn_rtx_costs. */
867 {
870 {
874 }
875 else
876 {
880 }
881 }
882 else
883 {
886 }
888 /* Calculate the replacement insn_rtx_costs. */
891 {
895 }
896 else
897 {
900 }
903 {
909 {
912 }
913 else
915 }
917 /* Disallow this combination if both new_cost and old_cost are greater than
918 zero, and new_cost is greater than old cost. */
922 {
941 else
943 }
948 /* Update the uid_insn_cost array with the replacement costs. */
952 {
956 }
959 }
962 /* Delete any insns that copy a register to itself. */
964 static void
966 {
968 basic_block bb;
971 {
973 {
976 {
981 }
982 }
983 }
984 }
986 \f
987 /* Return false if we do not want to (or cannot) combine DEF. */
988 static bool
990 {
991 /* Do not consider if it is pre/post modification in MEM. */
997 /* Do not combine frame pointer adjustments. */
1000 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1003 #endif
1004 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1006 #endif
1007 )
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1117 #ifdef HAVE_cc0
1120 #endif
1122 }
1123 \f
1124 /* Main entry point for combiner. F is the first insn of the function.
1125 NREGS is the first unused pseudo-reg number.
1127 Return nonzero if the combiner has turned an indirect jump
1128 instruction into a direct jump. */
1129 static int
1131 {
1133 #ifdef HAVE_cc0
1135 #endif
1138 basic_block last_bb;
1158 /* Allocate array for insn info. */
1166 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1167 problems when, for example, we have j <<= 1 in a loop. */
1172 /* Scan all SETs and see if we can deduce anything about what
1173 bits are known to be zero for some registers and how many copies
1174 of the sign bit are known to exist for those registers.
1176 Also set any known values so that we can use it while searching
1177 for what bits are known to be set. */
1180 /* Allow the entry block and the first block to fall into the same EBB.
1181 Conceptually the incoming promotions are assigned to the entry block. */
1186 {
1191 label_tick++;
1199 {
1200 #ifdef AUTO_INC_DEC
1201 rtx links;
1202 #endif
1208 insn);
1211 #ifdef AUTO_INC_DEC
1215 insn);
1216 #endif
1218 /* Record the current insn_rtx_cost of this instruction. */
1221 optimize_this_for_speed_p);
1225 }
1226 }
1230 /* Now scan all the insns in forward order. */
1238 {
1244 label_tick++;
1254 {
1268 /* See if we know about function return values before this
1269 insn based upon SUBREG flags. */
1272 /* See if we can find hardregs and subreg of pseudos in
1273 narrower modes. This could help turning TRUNCATEs
1274 into SUBREGs. */
1277 /* Try this insn with each insn it links back to. */
1283 {
1286 }
1288 /* Try each sequence of three linked insns ending with this one. */
1292 {
1295 /* If the linked insn has been replaced by a note, then there
1296 is no point in pursuing this chain any further. */
1304 {
1307 }
1308 }
1310 #ifdef HAVE_cc0
1311 /* Try to combine a jump insn that uses CC0
1312 with a preceding insn that sets CC0, and maybe with its
1313 logical predecessor as well.
1314 This is how we make decrement-and-branch insns.
1315 We need this special code because data flow connections
1316 via CC0 do not get entered in LOG_LINKS. */
1322 {
1333 }
1335 /* Do the same for an insn that explicitly references CC0. */
1342 {
1353 }
1355 /* Finally, see if any of the insns that this insn links to
1356 explicitly references CC0. If so, try this insn, that insn,
1357 and its predecessor if it sets CC0. */
1369 #endif
1371 /* Try combining an insn with two different insns whose results it
1372 uses. */
1382 {
1385 }
1387 /* Try four-instruction combinations. */
1390 {
1394 /* If the linked insn has been replaced by a note, then there
1395 is no point in pursuing this chain any further. */
1400 {
1404 /* I0 -> I1 -> I2 -> I3. */
1410 {
1413 }
1414 /* I0, I1 -> I2, I2 -> I3. */
1421 {
1424 }
1425 }
1428 {
1432 /* I0 -> I2; I1, I2 -> I3. */
1438 {
1441 }
1442 /* I0 -> I1; I1, I2 -> I3. */
1448 {
1451 }
1452 }
1453 }
1455 /* Try this insn with each REG_EQUAL note it links back to. */
1457 {
1463 /* Avoid using a register that may already been marked
1464 dead by an earlier instruction. */
1469 {
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1480 last_combined_insn);
1483 {
1486 }
1488 }
1489 }
1494 retry:
1495 ;
1496 }
1497 }
1504 /* Clean up. */
1510 {
1513 {
1516 }
1518 }
1528 /* Make recognizer allow volatile MEMs again. */
1532 }
1534 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1536 static void
1538 {
1544 }
1545 \f
1546 /* Set up any promoted values for incoming argument registers. */
1548 static void
1550 {
1551 tree arg;
1556 {
1561 /* Only continue if the incoming argument is in a register. */
1565 /* Determine, if possible, whether all call sites of the current
1566 function lie within the current compilation unit. (This does
1567 take into account the exporting of a function via taking its
1568 address, and so forth.) */
1571 /* The mode and signedness of the argument before any promotions happen
1572 (equal to the mode of the pseudo holding it at that stage). */
1576 /* The mode and signedness of the argument after any source language and
1577 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1581 /* The mode and signedness of the argument as it is actually passed,
1582 see assign_parm_setup_reg in function.c. */
1586 /* The mode of the register in which the argument is being passed. */
1589 /* Eliminate sign extensions in the callee when:
1590 (a) A mode promotion has occurred; */
1593 /* (b) The mode of the register is the same as the mode of
1594 the argument as it is passed; */
1597 /* (c) There's no language level extension; */
1599 ;
1600 /* (c.1) All callers are from the current compilation unit. If that's
1601 the case we don't have to rely on an ABI, we only have to know
1602 what we're generating right now, and we know that we will do the
1603 mode1 to mode2 promotion with the given sign. */
1606 /* (c.2) The combination of the two promotions is useful. This is
1607 true when the signs match, or if the first promotion is unsigned.
1608 In the later case, (sign_extend (zero_extend x)) is the same as
1609 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1615 /* Record that the value was promoted from mode1 to mode3,
1616 so that any sign extension at the head of the current
1617 function may be eliminated. */
1621 }
1622 }
1624 /* Called via note_stores. If X is a pseudo that is narrower than
1625 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1627 If we are setting only a portion of X and we can't figure out what
1628 portion, assume all bits will be used since we don't know what will
1629 be happening.
1631 Similarly, set how many bits of X are known to be copies of the sign bit
1632 at all locations in the function. This is the smallest number implied
1633 by any set of X. */
1635 static void
1637 {
1643 /* If this register is undefined at the start of the file, we can't
1644 say what its contents were. */
1645 && ! REGNO_REG_SET_P
1648 {
1652 {
1656 }
1658 /* If this register is being initialized using itself, and the
1659 register is uninitialized in this basic block, and there are
1660 no LOG_LINKS which set the register, then part of the
1661 register is uninitialized. In that case we can't assume
1662 anything about the number of nonzero bits.
1664 ??? We could do better if we checked this in
1665 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1666 could avoid making assumptions about the insn which initially
1667 sets the register, while still using the information in other
1668 insns. We would have to be careful to check every insn
1669 involved in the combination. */
1675 {
1682 {
1686 }
1687 }
1689 /* If this is a complex assignment, see if we can convert it into a
1690 simple assignment. */
1693 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1694 set what we know about X. */
1699 {
1702 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1703 /* If X is narrower than a word and SRC is a non-negative
1704 constant that would appear negative in the mode of X,
1705 sign-extend it for use in reg_stat[].nonzero_bits because some
1706 machines (maybe most) will actually do the sign-extension
1707 and this is the conservative approach.
1709 ??? For 2.5, try to tighten up the MD files in this regard
1710 instead of this kludge. */
1717 #endif
1719 /* Don't call nonzero_bits if it cannot change anything. */
1726 }
1727 else
1728 {
1731 }
1732 }
1733 }
1734 \f
1735 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1736 optionally insns that were previously combined into I3 or that will be
1737 combined into the merger of INSN and I3. The order is PRED, PRED2,
1738 INSN, SUCC, SUCC2, I3.
1740 Return 0 if the combination is not allowed for any reason.
1742 If the combination is allowed, *PDEST will be set to the single
1743 destination of INSN and *PSRC to the single source, and this function
1744 will return 1. */
1746 static int
1750 {
1755 #ifdef AUTO_INC_DEC
1756 rtx link;
1757 #endif
1762 {
1764 {
1769 }
1774 }
1778 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1779 or a PARALLEL consisting of such a SET and CLOBBERs.
1781 If INSN has CLOBBER parallel parts, ignore them for our processing.
1782 By definition, these happen during the execution of the insn. When it
1783 is merged with another insn, all bets are off. If they are, in fact,
1784 needed and aren't also supplied in I3, they may be added by
1785 recog_for_combine. Otherwise, it won't match.
1787 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1788 note.
1790 Get the source and destination of INSN. If more than one, can't
1791 combine. */
1797 {
1799 {
1803 {
1804 /* This is important to combine floating point insns
1805 for the SH4 port. */
1807 /* Combining an isolated USE doesn't make sense.
1808 We depend here on combinable_i3pat to reject them. */
1809 /* The code below this loop only verifies that the inputs of
1810 the SET in INSN do not change. We call reg_set_between_p
1811 to verify that the REG in the USE does not change between
1812 I3 and INSN.
1813 If the USE in INSN was for a pseudo register, the matching
1814 insn pattern will likely match any register; combining this
1815 with any other USE would only be safe if we knew that the
1816 used registers have identical values, or if there was
1817 something to tell them apart, e.g. different modes. For
1818 now, we forgo such complicated tests and simply disallow
1819 combining of USES of pseudo registers with any other USE. */
1822 {
1827 do
1828 {
1838 }
1840 }
1843 /* We can ignore CLOBBERs. */
1848 /* Ignore SETs whose result isn't used but not those that
1849 have side-effects. */
1855 /* If we have already found a SET, this is a second one and
1856 so we cannot combine with this insn. */
1864 /* Anything else means we can't combine. */
1866 }
1867 }
1870 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1871 so don't do anything with it. */
1874 }
1875 else
1881 /* The simplification in expand_field_assignment may call back to
1882 get_last_value, so set safe guard here. */
1888 /* Don't eliminate a store in the stack pointer. */
1890 /* Don't combine with an insn that sets a register to itself if it has
1891 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1893 /* Can't merge an ASM_OPERANDS. */
1895 /* Can't merge a function call. */
1897 /* Don't eliminate a function call argument. */
1903 /* Don't substitute into an incremented register. */
1907 /* Don't substitute into a non-local goto, this confuses CFG. */
1909 /* Make sure that DEST is not used after SUCC but before I3. */
1910 || (!all_adjacent
1911 && ((succ2
1915 /* Make sure that the value that is to be substituted for the register
1916 does not use any registers whose values alter in between. However,
1917 If the insns are adjacent, a use can't cross a set even though we
1918 think it might (this can happen for a sequence of insns each setting
1919 the same destination; last_set of that register might point to
1920 a NOTE). If INSN has a REG_EQUIV note, the register is always
1921 equivalent to the memory so the substitution is valid even if there
1922 are intervening stores. Also, don't move a volatile asm or
1923 UNSPEC_VOLATILE across any other insns. */
1924 || (! all_adjacent
1930 /* Don't combine across a CALL_INSN, because that would possibly
1931 change whether the life span of some REGs crosses calls or not,
1932 and it is a pain to update that information.
1933 Exception: if source is a constant, moving it later can't hurt.
1934 Accept that as a special case. */
1938 /* DEST must either be a REG or CC0. */
1940 {
1941 /* If register alignment is being enforced for multi-word items in all
1942 cases except for parameters, it is possible to have a register copy
1943 insn referencing a hard register that is not allowed to contain the
1944 mode being copied and which would not be valid as an operand of most
1945 insns. Eliminate this problem by not combining with such an insn.
1947 Also, on some machines we don't want to extend the life of a hard
1948 register. */
1953 /* Don't extend the life of a hard register unless it is
1954 user variable (if we have few registers) or it can't
1955 fit into the desired register (meaning something special
1956 is going on).
1957 Also avoid substituting a return register into I3, because
1958 reload can't handle a conflict with constraints of other
1959 inputs. */
1963 }
1971 {
1974 /* If the clobber represents an earlyclobber operand, we must not
1975 substitute an expression containing the clobbered register.
1976 As we do not analyze the constraint strings here, we have to
1977 make the conservative assumption. However, if the register is
1978 a fixed hard reg, the clobber cannot represent any operand;
1979 we leave it up to the machine description to either accept or
1980 reject use-and-clobber patterns. */
1986 }
1988 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 or not), reject, unless nothing volatile comes between it and I3 */
1992 {
1993 /* Make sure neither succ nor succ2 contains a volatile reference. */
1998 /* We'll check insns between INSN and I3 below. */
1999 }
2001 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 to be an explicit register variable, and was chosen for a reason. */
2008 /* If INSN contains volatile references (specifically volatile MEMs),
2009 we cannot combine across any other volatile references.
2010 Even if INSN doesn't contain volatile references, any intervening
2011 volatile insn might affect machine state. */
2014 ? volatile_refs_p
2021 /* If INSN contains an autoincrement or autodecrement, make sure that
2022 register is not used between there and I3, and not already used in
2023 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 Also insist that I3 not be a jump; if it were one
2025 and the incremented register were spilled, we would lose. */
2027 #ifdef AUTO_INC_DEC
2042 #endif
2044 #ifdef HAVE_cc0
2045 /* Don't combine an insn that follows a CC0-setting insn.
2046 An insn that uses CC0 must not be separated from the one that sets it.
2047 We do, however, allow I2 to follow a CC0-setting insn if that insn
2048 is passed as I1; in that case it will be deleted also.
2049 We also allow combining in this case if all the insns are adjacent
2050 because that would leave the two CC0 insns adjacent as well.
2051 It would be more logical to test whether CC0 occurs inside I1 or I2,
2052 but that would be much slower, and this ought to be equivalent. */
2058 #endif
2060 /* If we get here, we have passed all the tests and the combination is
2061 to be allowed. */
2067 }
2068 \f
2069 /* LOC is the location within I3 that contains its pattern or the component
2070 of a PARALLEL of the pattern. We validate that it is valid for combining.
2072 One problem is if I3 modifies its output, as opposed to replacing it
2073 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2074 doing so would produce an insn that is not equivalent to the original insns.
2076 Consider:
2078 (set (reg:DI 101) (reg:DI 100))
2079 (set (subreg:SI (reg:DI 101) 0) <foo>)
2081 This is NOT equivalent to:
2083 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2084 (set (reg:DI 101) (reg:DI 100))])
2086 Not only does this modify 100 (in which case it might still be valid
2087 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2089 We can also run into a problem if I2 sets a register that I1
2090 uses and I1 gets directly substituted into I3 (not via I2). In that
2091 case, we would be getting the wrong value of I2DEST into I3, so we
2092 must reject the combination. This case occurs when I2 and I1 both
2093 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2094 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2095 of a SET must prevent combination from occurring. The same situation
2096 can occur for I0, in which case I0_NOT_IN_SRC is set.
2098 Before doing the above check, we first try to expand a field assignment
2099 into a set of logical operations.
2101 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2102 we place a register that is both set and used within I3. If more than one
2103 such register is detected, we fail.
2105 Return 1 if the combination is valid, zero otherwise. */
2107 static int
2110 {
2114 {
2119 rtx subdest;
2126 /* Check for the case where I3 modifies its output, as discussed
2127 above. We don't want to prevent pseudos from being combined
2128 into the address of a MEM, so only prevent the combination if
2129 i1 or i2 set the same MEM. */
2139 /* This is the same test done in can_combine_p except we can't test
2140 all_adjacent; we don't have to, since this instruction will stay
2141 in place, thus we are not considering increasing the lifetime of
2142 INNER_DEST.
2144 Also, if this insn sets a function argument, combining it with
2145 something that might need a spill could clobber a previous
2146 function argument; the all_adjacent test in can_combine_p also
2147 checks this; here, we do a more specific test for this case. */
2157 /* If DEST is used in I3, it is being killed in this insn, so
2158 record that for later. We have to consider paradoxical
2159 subregs here, since they kill the whole register, but we
2160 ignore partial subregs, STRICT_LOW_PART, etc.
2161 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2162 STACK_POINTER_REGNUM, since these are always considered to be
2163 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2173 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2175 #endif
2176 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2179 #endif
2181 {
2186 }
2187 }
2190 {
2197 }
2200 }
2201 \f
2202 /* Return 1 if X is an arithmetic expression that contains a multiplication
2203 and division. We don't count multiplications by powers of two here. */
2205 static int
2207 {
2209 {
2225 }
2226 }
2227 \f
2228 /* Determine whether INSN can be used in a combination. Return nonzero if
2229 not. This is used in try_combine to detect early some cases where we
2230 can't perform combinations. */
2232 static int
2234 {
2235 rtx set;
2238 /* If this isn't really an insn, we can't do anything.
2239 This can occur when flow deletes an insn that it has merged into an
2240 auto-increment address. */
2244 /* Never combine loads and stores involving hard regs that are likely
2245 to be spilled. The register allocator can usually handle such
2246 reg-reg moves by tying. If we allow the combiner to make
2247 substitutions of likely-spilled regs, reload might die.
2248 As an exception, we allow combinations involving fixed regs; these are
2249 not available to the register allocator so there's no risk involved. */
2270 }
2272 struct likely_spilled_retval_info
2273 {
2276 };
2278 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2279 hard registers that are known to be written to / clobbered in full. */
2280 static void
2282 {
2299 else
2302 }
2304 /* Return nonzero iff part of the return value is live during INSN, and
2305 it is likely spilled. This can happen when more than one insn is needed
2306 to copy the return value, e.g. when we consider to combine into the
2307 second copy insn for a complex value. */
2309 static int
2311 {
2313 rtx reg;
2316 /* We assume here that no machine mode needs more than
2317 32 hard registers when the value overlaps with a register
2318 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2333 /* Disregard parts of the return value that are set later. */
2342 /* Check if any of the (probably) live return value registers is
2343 likely spilled. */
2344 nregs --;
2345 do
2346 {
2352 }
2354 /* Adjust INSN after we made a change to its destination.
2356 Changing the destination can invalidate notes that say something about
2357 the results of the insn and a LOG_LINK pointing to the insn. */
2359 static void
2361 {
2362 /* For notes, be conservative and simply remove them. */
2365 /* The new insn will have a destination that was previously the destination
2366 of an insn just above it. Call distribute_links to make a LOG_LINK from
2367 the next use of that destination. */
2383 }
2385 /* Return TRUE if combine can reuse reg X in mode MODE.
2386 ADDED_SETS is nonzero if the original set is still required. */
2387 static bool
2389 {
2396 /* Allow hard registers if the new mode is legal, and occupies no more
2397 registers than the old mode. */
2403 /* Or a pseudo that is only used once. */
2406 }
2409 /* Check whether X, the destination of a set, refers to part of
2410 the register specified by REG. */
2412 static bool
2414 {
2415 /* Check that reg is an integer mode register. */
2426 }
2428 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2429 Note that the INSN should be deleted *after* removing dead edges, so
2430 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2431 but not for a (set (pc) (label_ref FOO)). */
2433 static void
2435 {
2443 {
2448 /* Remove barriers from the footer if there are any. */
2451 {
2454 else
2458 }
2461 }
2462 }
2464 /* Return whether INSN is a PARALLEL of exactly N register SETs followed
2465 by an arbitrary number of CLOBBERs. */
2466 static bool
2468 {
2488 }
2490 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2491 CLOBBERs), can be split into individual SETs in that order, without
2492 changing semantics. */
2493 static bool
2495 {
2503 {
2512 }
2515 }
2517 /* Try to combine the insns I0, I1 and I2 into I3.
2518 Here I0, I1 and I2 appear earlier than I3.
2519 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2520 I3.
2522 If we are combining more than two insns and the resulting insn is not
2523 recognized, try splitting it into two insns. If that happens, I2 and I3
2524 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2525 Otherwise, I0, I1 and I2 are pseudo-deleted.
2527 Return 0 if the combination does not work. Then nothing is changed.
2528 If we did the combination, return the insn at which combine should
2529 resume scanning.
2531 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2532 new direct jump instruction.
2534 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2535 been I3 passed to an earlier try_combine within the same basic
2536 block. */
2541 {
2542 /* New patterns for I3 and I2, respectively. */
2546 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2547 dead. */
2549 /* Total number of SETs to put into I3. */
2551 /* Nonzero if I2's or I1's body now appears in I3. */
2553 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2555 /* Contains I3 if the destination of I3 is used in its source, which means
2556 that the old life of I3 is being killed. If that usage is placed into
2557 I2 and not in I3, a REG_DEAD note must be made. */
2559 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2561 /* Copy of SET_SRC of I1 and I0, if needed. */
2563 /* Set if I2DEST was reused as a scratch register. */
2565 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2567 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2572 /* Notes that must be added to REG_NOTES in I3 and I2. */
2574 /* Notes that we substituted I3 into I2 instead of the normal case. */
2576 /* Notes that I1, I2 or I3 is a MULT operation. */
2583 rtx temp_expr;
2586 rtx new_other_notes;
2589 /* Only try four-insn combinations when there's high likelihood of
2590 success. Look for simple insns, such as loads of constants or
2591 binary operations involving a constant. */
2593 {
2602 {
2605 rtx src;
2610 {
2613 }
2615 ngood++;
2618 nshift++;
2619 }
2622 }
2624 /* Exit early if one of the insns involved can't be used for
2625 combinations. */
2636 combine_attempts++;
2639 /* Reset the hard register usage information. */
2643 {
2650 else
2653 }
2655 /* If multiple insns feed into one of I2 or I3, they can be in any
2656 order. To simplify the code below, reorder them in sequence. */
2666 /* First check for one important special case that the code below will
2667 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2668 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2669 we may be able to replace that destination with the destination of I3.
2670 This occurs in the common code where we compute both a quotient and
2671 remainder into a structure, in which case we want to do the computation
2672 directly into the structure to avoid register-register copies.
2674 Note that this case handles both multiple sets in I2 and also cases
2675 where I2 has a number of CLOBBERs inside the PARALLEL.
2677 We make very conservative checks below and only try to handle the
2678 most common cases of this. For example, we only handle the case
2679 where I2 and I3 are adjacent to avoid making difficult register
2680 usage tests. */
2688 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2689 below would need to check what is inside (and reg_overlap_mentioned_p
2690 doesn't support those codes anyway). Don't allow those destinations;
2691 the resulting insn isn't likely to be recognized anyway. */
2697 {
2700 /* Make sure that the destination of I3,
2701 which we are going to substitute into one output of I2,
2702 is not used within another output of I2. We must avoid making this:
2703 (parallel [(set (mem (reg 69)) ...)
2704 (set (reg 69) ...)])
2705 which is not well-defined as to order of actions.
2706 (Besides, reload can't handle output reloads for this.)
2708 The problem can also happen if the dest of I3 is a memory ref,
2709 if another dest in I2 is an indirect memory ref. */
2721 {
2722 combine_merges++;
2732 /* Replace the dest in I2 with our dest and make the resulting
2733 insn the new pattern for I3. Then skip to where we validate
2734 the pattern. Everything was set up above. */
2739 }
2740 }
2742 /* If I2 is setting a pseudo to a constant and I3 is setting some
2743 sub-part of it to another constant, merge them by making a new
2744 constant. */
2751 {
2757 {
2760 {
2766 }
2767 }
2768 else
2769 {
2774 }
2777 {
2778 /* If this is the low part, we're done. */
2780 ;
2781 /* Handle the case where inner is twice the size of outer. */
2785 /* Otherwise give up for now. */
2786 else
2788 }
2791 {
2795 wide_int o
2800 combine_merges++;
2807 /* Replace the source in I2 with the new constant and make the
2808 resulting insn the new pattern for I3. Then skip to where we
2809 validate the pattern. Everything was set up above. */
2815 /* The dest of I3 has been replaced with the dest of I2. */
2818 }
2819 }
2821 #ifndef HAVE_cc0
2822 /* If we have no I1 and I2 looks like:
2823 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2824 (set Y OP)])
2825 make up a dummy I1 that is
2826 (set Y OP)
2827 and change I2 to be
2828 (set (reg:CC X) (compare:CC Y (const_int 0)))
2830 (We can ignore any trailing CLOBBERs.)
2832 This undoes a previous combination and allows us to match a branch-and-
2833 decrement insn. */
2845 {
2846 /* We make I1 with the same INSN_UID as I2. This gives it
2847 the same DF_INSN_LUID for value tracking. Our fake I1 will
2848 never appear in the insn stream so giving it the same INSN_UID
2849 as I2 will not cause a problem. */
2862 }
2864 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2865 make those two SETs separate I1 and I2 insns, and make an I0 that is
2866 the original I1. */
2872 {
2873 /* If there is no I1, there is no I0 either. */
2876 /* We make I1 with the same INSN_UID as I2. This gives it
2877 the same DF_INSN_LUID for value tracking. Our fake I1 will
2878 never appear in the insn stream so giving it the same INSN_UID
2879 as I2 will not cause a problem. */
2887 }
2888 #endif
2890 /* Verify that I2 and I1 are valid for combining. */
2896 {
2899 }
2901 /* Record whether I2DEST is used in I2SRC and similarly for the other
2902 cases. Knowing this will help in register status updating below. */
2913 /* For the earlier insns, determine which of the subsequent ones they
2914 feed. */
2921 /* Ensure that I3's pattern can be the destination of combines. */
2927 {
2930 }
2932 /* See if any of the insns is a MULT operation. Unless one is, we will
2933 reject a combination that is, since it must be slower. Be conservative
2934 here. */
2942 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2943 We used to do this EXCEPT in one case: I3 has a post-inc in an
2944 output operand. However, that exception can give rise to insns like
2945 mov r3,(r3)+
2946 which is a famous insn on the PDP-11 where the value of r3 used as the
2947 source was model-dependent. Avoid this sort of thing. */
2949 #if 0
2955 /* It's not the exception. */
2956 #endif
2957 #ifdef AUTO_INC_DEC
2958 {
2959 rtx link;
2965 {
2968 }
2969 }
2970 #endif
2972 /* See if the SETs in I1 or I2 need to be kept around in the merged
2973 instruction: whenever the value set there is still needed past I3.
2974 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2976 For the SET in I1, we have two cases: if I1 and I2 independently feed
2977 into I3, the set in I1 needs to be kept around unless I1DEST dies
2978 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2979 in I1 needs to be kept around unless I1DEST dies or is set in either
2980 I2 or I3. The same considerations apply to I0. */
2987 else
2995 else
2998 /* We are about to copy insns for the case where they need to be kept
2999 around. Check that they can be copied in the merged instruction. */
3005 {
3008 }
3010 /* If the set in I2 needs to be kept around, we must make a copy of
3011 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3012 PATTERN (I2), we are only substituting for the original I1DEST, not into
3013 an already-substituted copy. This also prevents making self-referential
3014 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3015 I2DEST. */
3018 {
3021 else
3023 }
3026 {
3029 else
3031 }
3034 {
3037 else
3039 }
3041 combine_merges++;
3043 /* Substitute in the latest insn for the regs set by the earlier ones. */
3049 #ifndef HAVE_cc0
3050 /* Many machines that don't use CC0 have insns that can both perform an
3051 arithmetic operation and set the condition code. These operations will
3052 be represented as a PARALLEL with the first element of the vector
3053 being a COMPARE of an arithmetic operation with the constant zero.
3054 The second element of the vector will set some pseudo to the result
3055 of the same arithmetic operation. If we simplify the COMPARE, we won't
3056 match such a pattern and so will generate an extra insn. Here we test
3057 for this case, where both the comparison and the operation result are
3058 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3059 I2SRC. Later we will make the PARALLEL that contains I2. */
3065 {
3066 rtx newpat_dest;
3080 {
3085 }
3087 /* Do the rest only if op1 is const0_rtx, which may be the
3088 result of simplification. */
3090 {
3091 /* If a single use of the CC is found, prepare to modify it
3092 when SELECT_CC_MODE returns a new CC-class mode, or when
3093 the above simplify_compare_const() returned a new comparison
3094 operator. undobuf.other_insn is assigned the CC use insn
3095 when modifying it. */
3097 {
3098 #ifdef SELECT_CC_MODE
3099 machine_mode new_mode
3104 {
3109 else
3110 {
3113 }
3114 }
3115 #endif
3116 /* Cases for modifying the CC-using comparison. */
3118 /* ??? Do we need to verify the zero rtx? */
3120 {
3121 /* Replace cc_use_loc with entire new RTX. */
3126 }
3128 {
3129 /* Just replace the CC reg with a new mode. */
3132 }
3133 }
3135 /* Now we modify the current newpat:
3136 First, SET_DEST(newpat) is updated if the CC mode has been
3137 altered. For targets without SELECT_CC_MODE, this should be
3138 optimized away. */
3141 /* This is always done to propagate i2src into newpat. */
3144 /* Create new version of i2pat if needed; the below PARALLEL
3145 creation needs this to work correctly. */
3149 }
3150 }
3151 #endif
3154 {
3155 /* It is possible that the source of I2 or I1 may be performing
3156 an unneeded operation, such as a ZERO_EXTEND of something
3157 that is known to have the high part zero. Handle that case
3158 by letting subst look at the inner insns.
3160 Another way to do this would be to have a function that tries
3161 to simplify a single insn instead of merging two or more
3162 insns. We don't do this because of the potential of infinite
3163 loops and because of the potential extra memory required.
3164 However, doing it the way we are is a bit of a kludge and
3165 doesn't catch all cases.
3167 But only do this if -fexpensive-optimizations since it slows
3168 things down and doesn't usually win.
3170 This is not done in the COMPARE case above because the
3171 unmodified I2PAT is used in the PARALLEL and so a pattern
3172 with a modified I2SRC would not match. */
3175 {
3176 /* Pass pc_rtx so no substitutions are done, just
3177 simplifications. */
3179 {
3182 }
3186 }
3191 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3192 copy of I2SRC each time we substitute it, in order to avoid creating
3193 self-referential RTL when we will be substituting I1SRC for I1DEST
3194 later. Likewise if I0 feeds into I2, either directly or indirectly
3195 through I1, and I0DEST is in I0SRC. */
3202 /* Record whether I2's body now appears within I3's body. */
3204 }
3206 /* If we already got a failure, don't try to do more. Otherwise, try to
3207 substitute I1 if we have it. */
3210 {
3211 /* Check that an autoincrement side-effect on I1 has not been lost.
3212 This happens if I1DEST is mentioned in I2 and dies there, and
3213 has disappeared from the new pattern. */
3215 && i1_feeds_i2_n
3218 /* Before we can do this substitution, we must redo the test done
3219 above (see detailed comments there) that ensures I1DEST isn't
3220 mentioned in any SETs in NEWPAT that are field assignments. */
3223 {
3226 }
3231 /* If the following substitution will modify I1SRC, make a copy of it
3232 for the case where it is substituted for I1DEST in I2PAT later. */
3236 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3237 copy of I1SRC each time we substitute it, in order to avoid creating
3238 self-referential RTL when we will be substituting I0SRC for I0DEST
3239 later. */
3244 /* Record whether I1's body now appears within I3's body. */
3246 }
3248 /* Likewise for I0 if we have it. */
3251 {
3258 {
3261 }
3263 /* If the following substitution will modify I0SRC, make a copy of it
3264 for the case where it is substituted for I0DEST in I1PAT later. */
3267 /* And a copy for I0DEST in I2PAT substitution. */
3276 }
3278 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3279 to count all the ways that I2SRC and I1SRC can be used. */
3290 /* Fail if we tried to make a new register. */
3292 /* Fail if we couldn't do something and have a CLOBBER. */
3294 /* Fail if this new pattern is a MULT and we didn't have one before
3295 at the outer level. */
3298 {
3301 }
3303 /* If the actions of the earlier insns must be kept
3304 in addition to substituting them into the latest one,
3305 we must make a new PARALLEL for the latest insn
3306 to hold additional the SETs. */
3309 {
3311 combine_extras++;
3314 {
3320 }
3321 else
3322 {
3327 }
3333 {
3339 }
3341 {
3350 }
3351 }
3353 validate_replacement:
3355 /* Note which hard regs this insn has as inputs. */
3358 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3359 consider splitting this pattern, we might need these clobbers. */
3362 {
3368 }
3370 /* We have recognized nothing yet. */
3373 /* See if this is a PARALLEL of two SETs where one SET's destination is
3374 a register that is unused and this isn't marked as an instruction that
3375 might trap in an EH region. In that case, we just need the other SET.
3376 We prefer this over the PARALLEL.
3378 This can occur when simplifying a divmod insn. We *must* test for this
3379 case here because the code below that splits two independent SETs doesn't
3380 handle this case correctly when it updates the register status.
3382 It's pointless doing this if we originally had two sets, one from
3383 i3, and one from i2. Combining then splitting the parallel results
3384 in the original i2 again plus an invalid insn (which we delete).
3385 The net effect is only to move instructions around, which makes
3386 debug info less accurate. */
3394 {
3405 {
3408 }
3417 {
3423 }
3427 }
3429 /* Is the result of combination a valid instruction? */
3433 /* If we were combining three insns and the result is a simple SET
3434 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3435 insns. There are two ways to do this. It can be split using a
3436 machine-specific method (like when you have an addition of a large
3437 constant) or by combine in the function find_split_point. */
3441 {
3445 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3446 use I2DEST as a scratch register will help. In the latter case,
3447 convert I2DEST to the mode of the source of NEWPAT if we can. */
3451 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3452 inputs of NEWPAT. */
3454 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3455 possible to try that as a scratch reg. This would require adding
3456 more code to make it work though. */
3459 {
3462 /* First try to split using the original register as a
3463 scratch register. */
3467 i2dest)));
3470 /* If that didn't work, try changing the mode of I2DEST if
3471 we can. */
3476 {
3478 rtx ni2dest;
3482 else
3483 {
3486 }
3488 parallel = (gen_rtx_PARALLEL
3492 ni2dest))));
3497 {
3505 }
3506 }
3509 }
3511 /* If recog_for_combine has discarded clobbers, try to use them
3512 again for the split. */
3514 {
3517 }
3520 {
3525 }
3529 {
3539 /* If I2 or I3 has multiple SETs, we won't know how to track
3540 register status, so don't use these insns. If I2's destination
3541 is used between I2 and I3, we also can't use these insns. */
3551 /* It is possible that both insns now set the destination of I3.
3552 If so, we must show an extra use of it. */
3555 {
3573 }
3574 }
3576 /* If we can split it and use I2DEST, go ahead and see if that
3577 helps things be recognized. Verify that none of the registers
3578 are set between I2 and I3. */
3581 #ifdef HAVE_cc0
3583 #endif
3584 /* We need I2DEST in the proper mode. If it is a hard register
3585 or the only use of a pseudo, we can change its mode.
3586 Make sure we don't change a hard register to have a mode that
3587 isn't valid for it, or change the number of registers. */
3594 /* We can't overwrite I2DEST if its value is still used by
3595 NEWPAT. */
3597 {
3606 /* *SPLIT may be part of I2SRC, so make sure we have the
3607 original expression around for later debug processing.
3608 We should not need I2SRC any more in other cases. */
3611 else
3614 /* Get NEWDEST as a register in the proper mode. We have already
3615 validated that we can do this. */
3617 {
3620 else
3621 {
3624 }
3625 }
3627 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3628 an ASHIFT. This can occur if it was inside a PLUS and hence
3629 appeared to be a memory address. This is a kludge. */
3634 {
3637 /* Update split_code because we may not have a multiply
3638 anymore. */
3640 }
3642 #ifdef INSN_SCHEDULING
3643 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3644 be written as a ZERO_EXTEND. */
3646 {
3647 #ifdef LOAD_EXTEND_OP
3648 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3649 what it really is. */
3654 else
3655 #endif
3658 }
3659 #endif
3661 /* Attempt to split binary operators using arithmetic identities. */
3665 {
3672 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3674 {
3679 }
3680 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3687 {
3693 /* Split both "((X op Y) op X) op Y" and
3694 "((X op Y) op Y) op X" as "T op T" where T is
3695 "X op Y". */
3698 {
3704 }
3705 /* Split "((X op X) op Y) op Y)" as "T op T" where
3706 T is "X op Y". */
3708 {
3714 }
3715 }
3716 }
3719 {
3722 }
3726 /* recog_for_combine might have added CLOBBERs to newi2pat.
3727 Make sure NEWPAT does not depend on the clobbered regs. */
3731 {
3734 {
3737 }
3738 }
3740 /* If the split point was a MULT and we didn't have one before,
3741 don't use one now. */
3744 }
3745 }
3747 /* Check for a case where we loaded from memory in a narrow mode and
3748 then sign extended it, but we need both registers. In that case,
3749 we have a PARALLEL with both loads from the same memory location.
3750 We can split this into a load from memory followed by a register-register
3751 copy. This saves at least one insn, more if register allocation can
3752 eliminate the copy.
3754 We cannot do this if the destination of the first assignment is a
3755 condition code register or cc0. We eliminate this case by making sure
3756 the SET_DEST and SET_SRC have the same mode.
3758 We cannot do this if the destination of the second assignment is
3759 a register that we have already assumed is zero-extended. Similarly
3760 for a SUBREG of such a register. */
3795 {
3796 rtx ni2dest;
3810 }
3812 /* Similarly, check for a case where we have a PARALLEL of two independent
3813 SETs but we started with three insns. In this case, we can do the sets
3814 as two separate insns. This case occurs when some SET allows two
3815 other insns to combine, but the destination of that SET is still live. */
3832 {
3836 /* Normally, it doesn't matter which of the two is done first,
3837 but the one that references cc0 can't be the second, and
3838 one which uses any regs/memory set in between i2 and i3 can't
3839 be first. The PARALLEL might also have been pre-existing in i3,
3840 so we need to make sure that we won't wrongly hoist a SET to i2
3841 that would conflict with a death note present in there. */
3848 #ifdef HAVE_cc0
3850 #endif
3851 /* If I3 is a jump, ensure that set0 is a jump so that
3852 we do not create invalid RTL. */
3854 )
3855 {
3858 }
3865 #ifdef HAVE_cc0
3867 #endif
3868 /* If I3 is a jump, ensure that set1 is a jump so that
3869 we do not create invalid RTL. */
3871 )
3872 {
3875 }
3876 else
3877 {
3880 }
3885 {
3886 /* recog_for_combine might have added CLOBBERs to newi2pat.
3887 Make sure NEWPAT does not depend on the clobbered regs. */
3889 {
3892 {
3895 {
3898 }
3899 }
3900 }
3903 }
3904 }
3906 /* If it still isn't recognized, fail and change things back the way they
3907 were. */
3909 /* Is the result a reasonable ASM_OPERANDS? */
3911 {
3914 }
3916 /* If we had to change another insn, make sure it is valid also. */
3918 {
3926 {
3929 }
3930 }
3932 #ifdef HAVE_cc0
3933 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3934 they are adjacent to each other or not. */
3935 {
3939 {
3942 }
3943 }
3944 #endif
3946 /* Only allow this combination if insn_rtx_costs reports that the
3947 replacement instructions are cheaper than the originals. */
3949 {
3952 }
3955 {
3960 {
3965 /* Temporarily revert mode back. */
3969 {
3970 /* If we used i2dest as a scratch register with a
3971 different mode, substitute it for the original
3972 i2src while its original mode is temporarily
3973 restored, and then clear i2scratch so that we don't
3974 do it again later. */
3976 this_basic_block);
3978 /* Put back the new mode. */
3980 }
3981 else
3982 {
3987 {
3990 }
3991 else
3992 {
3999 }
4001 /* We're dealing with a reg that changed mode but not
4002 meaning, so we want to turn it into a subreg for
4003 the new mode. However, because of REG sharing and
4004 because its mode had already changed, we have to do
4005 it in two steps. First, replace any debug uses of
4006 reg, with its original mode temporarily restored,
4007 with this copy we have created; then, replace the
4008 copy with the SUBREG of the original shared reg,
4009 once again changed to the new mode. */
4011 this_basic_block);
4015 this_basic_block);
4016 }
4017 }
4018 }
4020 /* If we will be able to accept this, we have made a
4021 change to the destination of I3. This requires us to
4022 do a few adjustments. */
4025 {
4028 }
4030 /* We now know that we can do this combination. Merge the insns and
4031 update the status of registers and LOG_LINKS. */
4034 {
4039 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4040 ensure that they are still valid. Then add any non-duplicate
4041 notes added by recog_for_combine. */
4043 {
4053 }
4057 NULL_RTX);
4058 }
4061 {
4064 rtx ni2dest;
4066 /* I3 now uses what used to be its destination and which is now
4067 I2's destination. This requires us to do a few adjustments. */
4071 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4072 so we still will.
4074 However, some later insn might be using I2's dest and have
4075 a LOG_LINK pointing at I3. We must remove this link.
4076 The simplest way to remove the link is to point it at I1,
4077 which we know will be a NOTE. */
4079 /* newi2pat is usually a SET here; however, recog_for_combine might
4080 have added some clobbers. */
4083 else
4090 {
4092 {
4098 }
4099 }
4100 }
4102 {
4107 /* Compute which registers we expect to eliminate. newi2pat may be setting
4108 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4109 same as i3dest, in which case newi2pat may be setting i1dest. */
4112 || !i2dest_killed
4116 || !i1dest_killed
4120 || !i0dest_killed
4123 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4124 clear them. */
4132 /* Ensure that we do not have something that should not be shared but
4133 occurs multiple times in the new insns. Check this by first
4134 resetting all the `used' flags and then copying anything is shared. */
4158 {
4165 {
4166 /* I2SRC must still be meaningful at this point. Some splitting
4167 operations can invalidate I2SRC, but those operations do not
4168 apply to calls. */
4171 }
4179 }
4184 /* We had one special case above where I2 had more than one set and
4185 we replaced a destination of one of those sets with the destination
4186 of I3. In that case, we have to update LOG_LINKS of insns later
4187 in this basic block. Note that this (expensive) case is rare.
4189 Also, in this case, we must pretend that all REG_NOTEs for I2
4190 actually came from I3, so that REG_UNUSED notes from I2 will be
4191 properly handled. */
4194 {
4203 temp_insn
4213 {
4218 }
4219 else
4222 }
4230 {
4233 this_basic_block);
4236 }
4237 else
4238 {
4241 this_basic_block);
4243 }
4246 {
4251 this_basic_block);
4253 }
4256 {
4261 this_basic_block);
4263 }
4265 /* Get death notes for everything that is now used in either I3 or
4266 I2 and used to die in a previous insn. If we built two new
4267 patterns, move from I1 to I2 then I2 to I3 so that we get the
4268 proper movement on registers that I2 modifies. */
4274 else
4280 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4297 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4298 know these are REG_UNUSED and want them to go to the desired insn,
4299 so we always pass it as i3. */
4303 NULL_RTX);
4307 NULL_RTX);
4309 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4310 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4311 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4312 in that case, it might delete I2. Similarly for I2 and I1.
4313 Show an additional death due to the REG_DEAD note we make here. If
4314 we discard it in distribute_notes, we will decrement it again. */
4317 {
4322 else
4325 }
4328 {
4333 else
4336 }
4339 {
4344 else
4347 }
4350 {
4355 else
4358 }
4366 {
4371 /* The insn that used to set this register doesn't exist, and
4372 this life of the register may not exist either. See if one of
4373 I3's links points to an insn that sets I2DEST. If it does,
4374 that is now the last known value for I2DEST. If we don't update
4375 this and I2 set the register to a value that depended on its old
4376 contents, we will get confused. If this insn is used, thing
4377 will be set correctly in combine_instructions. */
4385 /* If the reg formerly set in I2 died only once and that was in I3,
4386 zero its use count so it won't make `reload' do any work. */
4391 }
4394 {
4408 }
4411 {
4425 }
4427 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4428 been made to this insn. The order is important, because newi2pat
4429 can affect nonzero_bits of newpat. */
4433 }
4436 {
4438 {
4441 }
4443 }
4446 {
4448 {
4451 }
4453 }
4456 {
4458 {
4461 }
4463 }
4466 {
4468 {
4471 }
4473 }
4476 {
4478 {
4481 }
4483 }
4485 /* Set new_direct_jump_p if a new return or simple jump instruction
4486 has been created. Adjust the CFG accordingly. */
4488 {
4492 }
4497 {
4500 }
4502 /* A noop might also need cleaning up of CFG, if it comes from the
4503 simplification of a jump. */
4508 {
4511 }
4518 {
4521 }
4523 combine_successes++;
4530 else
4532 }
4533 \f
4534 /* Undo all the modifications recorded in undobuf. */
4536 static void
4538 {
4542 {
4545 {
4560 }
4564 }
4567 }
4569 /* We've committed to accepting the changes we made. Move all
4570 of the undos to the free list. */
4572 static void
4574 {
4578 {
4582 }
4584 }
4585 \f
4586 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4587 where we have an arithmetic expression and return that point. LOC will
4588 be inside INSN.
4590 try_combine will call this function to see if an insn can be split into
4591 two insns. */
4595 {
4604 /* First special-case some codes. */
4606 {
4608 #ifdef INSN_SCHEDULING
4609 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4610 point. */
4613 #endif
4617 #ifdef HAVE_lo_sum
4618 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4619 using LO_SUM and HIGH. */
4622 {
4630 }
4631 #endif
4633 /* If we have a PLUS whose second operand is a constant and the
4634 address is not valid, perhaps will can split it up using
4635 the machine-specific way to split large constants. We use
4636 the first pseudo-reg (one of the virtual regs) as a placeholder;
4637 it will not remain in the result. */
4642 {
4646 subst_insn);
4648 /* This should have produced two insns, each of which sets our
4649 placeholder. If the source of the second is a valid address,
4650 we can make put both sources together and make a split point
4651 in the middle. */
4664 && memory_address_addr_space_p
4667 {
4671 /* Replace the placeholder in SRC2 with SRC1. If we can
4672 find where in SRC2 it was placed, that can become our
4673 split point and we can replace this address with SRC2.
4674 Just try two obvious places. */
4685 {
4688 }
4689 }
4691 /* If that didn't work, perhaps the first operand is complex and
4692 needs to be computed separately, so make a split point there.
4693 This will occur on machines that just support REG + CONST
4694 and have a constant moved through some previous computation. */
4700 }
4702 /* If we have a PLUS whose first operand is complex, try computing it
4703 separately by making a split there. */
4714 #ifdef HAVE_cc0
4715 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4716 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4717 we need to put the operand into a register. So split at that
4718 point. */
4727 #endif
4729 /* See if we can split SET_SRC as it stands. */
4734 /* See if we can split SET_DEST as it stands. */
4739 /* See if this is a bitfield assignment with everything constant. If
4740 so, this is an IOR of an AND, so split it into that. */
4750 {
4756 unsigned HOST_WIDE_INT mask
4758 rtx or_mask;
4767 else
4768 {
4774 or_mask));
4775 }
4782 }
4784 /* Otherwise, see if this is an operation that we can split into two.
4785 If so, try to split that. */
4789 {
4791 /* If we are AND'ing with a large constant that is only a single
4792 bit and the result is only being used in a context where we
4793 need to know if it is zero or nonzero, replace it with a bit
4794 extraction. This will avoid the large constant, which might
4795 have taken more than one insn to make. If the constant were
4796 not a valid argument to the AND but took only one insn to make,
4797 this is no worse, but if it took more than one insn, it will
4798 be better. */
4808 {
4813 {
4816 }
4817 }
4821 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4822 is known to be on, this can be converted into a NEG of a shift. */
4828 {
4840 }
4846 /* We can't optimize if either mode is a partial integer
4847 mode as we don't know how many bits are significant
4848 in those modes. */
4862 {
4870 }
4875 }
4879 {
4882 /* For unsigned, we have a choice of a shift followed by an
4883 AND or two shifts. Use two shifts for field sizes where the
4884 constant might be too large. We assume here that we can
4885 always at least get 8-bit constants in an AND insn, which is
4886 true for every current RISC. */
4889 {
4890 unsigned HOST_WIDE_INT mask
4894 gen_rtx_LSHIFTRT
4902 }
4903 else
4904 {
4906 gen_rtx_fmt_ee
4917 }
4918 }
4920 /* See if this is a simple operation with a constant as the second
4921 operand. It might be that this constant is out of range and hence
4922 could be used as a split point. */
4930 /* Finally, see if this is a simple operation with its first operand
4931 not in a register. The operation might require this operand in a
4932 register, so return it as a split point. We can always do this
4933 because if the first operand were another operation, we would have
4934 already found it as a split point. */
4943 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4944 it is better to write this as (not (ior A B)) so we can split it.
4945 Similarly for IOR. */
4947 {
4955 }
4957 /* Many RISC machines have a large set of logical insns. If the
4958 second operand is a NOT, put it first so we will try to split the
4959 other operand first. */
4961 {
4965 }
4970 /* Canonicalization can produce (minus A (mult B C)), where C is a
4971 constant. It may be better to try splitting (plus (mult B -C) A)
4972 instead if this isn't a multiply by a power of two. */
4976 {
4984 mode)),
4987 }
4989 /* Split at a multiply-accumulate instruction. However if this is
4990 the SET_SRC, we likely do not have such an instruction and it's
4991 worthless to try this split. */
4997 }
4999 /* Otherwise, select our actions depending on our rtx class. */
5001 {
5007 /* ... fall through ... */
5015 /* ... fall through ... */
5017 /* Some machines have (and (shift ...) ...) insns. If X is not
5018 an AND, but XEXP (X, 0) is, use it as our split point. */
5028 /* Otherwise, we don't have a split point. */
5030 }
5031 }
5032 \f
5033 /* Throughout X, replace FROM with TO, and return the result.
5034 The result is TO if X is FROM;
5035 otherwise the result is X, but its contents may have been modified.
5036 If they were modified, a record was made in undobuf so that
5037 undo_all will (among other things) return X to its original state.
5039 If the number of changes necessary is too much to record to undo,
5040 the excess changes are not made, so the result is invalid.
5041 The changes already made can still be undone.
5042 undobuf.num_undo is incremented for such changes, so by testing that
5043 the caller can tell whether the result is valid.
5045 `n_occurrences' is incremented each time FROM is replaced.
5047 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5049 IN_COND is nonzero if we are at the top level of a condition.
5051 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5052 by copying if `n_occurrences' is nonzero. */
5054 static rtx
5056 {
5061 rtx new_rtx;
5063 /* Two expressions are equal if they are identical copies of a shared
5064 RTX or if they are both registers with the same register number
5065 and mode. */
5067 #define COMBINE_RTX_EQUAL_P(X,Y) \
5068 ((X) == (Y) \
5069 || (REG_P (X) && REG_P (Y) \
5070 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5072 /* Do not substitute into clobbers of regs -- this will never result in
5073 valid RTL. */
5078 {
5079 n_occurrences++;
5081 }
5083 /* If X and FROM are the same register but different modes, they
5084 will not have been seen as equal above. However, the log links code
5085 will make a LOG_LINKS entry for that case. If we do nothing, we
5086 will try to rerecognize our original insn and, when it succeeds,
5087 we will delete the feeding insn, which is incorrect.
5089 So force this insn not to match in this (rare) case. */
5094 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5095 of which may contain things that can be combined. */
5099 /* It is possible to have a subexpression appear twice in the insn.
5100 Suppose that FROM is a register that appears within TO.
5101 Then, after that subexpression has been scanned once by `subst',
5102 the second time it is scanned, TO may be found. If we were
5103 to scan TO here, we would find FROM within it and create a
5104 self-referent rtl structure which is completely wrong. */
5108 /* Parallel asm_operands need special attention because all of the
5109 inputs are shared across the arms. Furthermore, unsharing the
5110 rtl results in recognition failures. Failure to handle this case
5111 specially can result in circular rtl.
5113 Solve this by doing a normal pass across the first entry of the
5114 parallel, and only processing the SET_DESTs of the subsequent
5115 entries. Ug. */
5120 {
5123 /* If this substitution failed, this whole thing fails. */
5131 {
5137 {
5140 /* If this substitution failed, this whole thing fails. */
5146 }
5147 }
5148 }
5149 else
5150 {
5154 /* We don't need to process a SET_DEST that is a register, CC0,
5155 or PC, so set up to skip this common case. All other cases
5156 where we want to suppress replacing something inside a
5157 SET_SRC are handled via the IN_DEST operand. */
5164 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5165 constant. */
5170 {
5172 {
5175 {
5177 {
5180 n_occurrences++;
5181 }
5182 else
5183 {
5185 unique_copy);
5187 /* If this substitution failed, this whole thing
5188 fails. */
5192 }
5195 }
5196 }
5198 {
5199 /* If this is a register being set, ignore it. */
5206 ;
5209 {
5210 /* In general, don't install a subreg involving two
5211 modes not tieable. It can worsen register
5212 allocation, and can even make invalid reload
5213 insns, since the reg inside may need to be copied
5214 from in the outside mode, and that may be invalid
5215 if it is an fp reg copied in integer mode.
5217 We allow two exceptions to this: It is valid if
5218 it is inside another SUBREG and the mode of that
5219 SUBREG and the mode of the inside of TO is
5220 tieable and it is valid if X is a SET that copies
5221 FROM to CC0. */
5229 #ifdef HAVE_cc0
5231 #endif
5232 )
5244 n_occurrences++;
5245 }
5246 else
5247 /* If we are in a SET_DEST, suppress most cases unless we
5248 have gone inside a MEM, in which case we want to
5249 simplify the address. We assume here that things that
5250 are actually part of the destination have their inner
5251 parts in the first expression. This is true for SUBREG,
5252 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5253 things aside from REG and MEM that should appear in a
5254 SET_DEST. */
5256 (((in_dest
5262 unique_copy);
5264 /* If we found that we will have to reject this combination,
5265 indicate that by returning the CLOBBER ourselves, rather than
5266 an expression containing it. This will speed things up as
5267 well as prevent accidents where two CLOBBERs are considered
5268 to be equal, thus producing an incorrect simplification. */
5274 {
5282 }
5285 {
5289 }
5290 else
5292 }
5293 }
5294 }
5296 /* Check if we are loading something from the constant pool via float
5297 extension; in this case we would undo compress_float_constant
5298 optimization and degenerate constant load to an immediate value. */
5302 {
5306 }
5308 /* Try to simplify X. If the simplification changed the code, it is likely
5309 that further simplification will help, so loop, but limit the number
5310 of repetitions that will be performed. */
5313 {
5314 /* If X is sufficiently simple, don't bother trying to do anything
5315 with it. */
5324 /* We no longer know the original mode of operand 0 since we
5325 have changed the form of X) */
5327 }
5330 }
5331 \f
5332 /* Simplify X, a piece of RTL. We just operate on the expression at the
5333 outer level; call `subst' to simplify recursively. Return the new
5334 expression.
5336 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5337 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5338 of a condition. */
5340 static rtx
5343 {
5346 rtx temp;
5349 /* If this is a commutative operation, put a constant last and a complex
5350 expression first. We don't need to do this for comparisons here. */
5353 {
5357 }
5359 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5360 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5361 things. Check for cases where both arms are testing the same
5362 condition.
5364 Don't do anything if all operands are very simple. */
5377 {
5382 /* If everything is a comparison, what we have is highly unlikely
5383 to be simpler, so don't use it. */
5386 {
5393 /* Simplify the alternative arms; this may collapse the true and
5394 false arms to store-flag values. Be careful to use copy_rtx
5395 here since true_rtx or false_rtx might share RTL with x as a
5396 result of the if_then_else_cond call above. */
5400 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5401 is unlikely to be simpler. */
5404 {
5407 /* Restarting if we generate a store-flag expression will cause
5408 us to loop. Just drop through in this case. */
5410 /* If the result values are STORE_FLAG_VALUE and zero, we can
5411 just make the comparison operation. */
5422 /* Likewise, we can make the negate of a comparison operation
5423 if the result values are - STORE_FLAG_VALUE and zero. */
5431 mode);
5442 mode);
5443 else
5446 mode,
5447 VOIDmode,
5448 cond,
5449 cop1),
5454 }
5455 }
5456 }
5458 /* Try to fold this expression in case we have constants that weren't
5459 present before. */
5462 {
5470 {
5473 {
5477 }
5480 }
5493 }
5496 {
5501 }
5503 /* First see if we can apply the inverse distributive law. */
5506 {
5510 }
5512 /* If CODE is an associative operation not otherwise handled, see if we
5513 can associate some operands. This can win if they are constants or
5514 if they are logically related (i.e. (a & b) & a). */
5520 {
5522 {
5526 rtx inner;
5528 /* Make sure we pass the constant operand if any as the second
5529 one if this is a commutative operation. */
5531 {
5535 }
5541 /* For commutative operations, try the other pair if that one
5542 didn't simplify. */
5544 {
5549 }
5553 }
5554 }
5556 /* A little bit of algebraic simplification here. */
5558 {
5560 /* Ensure that our address has any ASHIFTs converted to MULT in case
5561 address-recognizing predicates are called later. */
5570 /* See if this can be moved to simplify_subreg. */
5573 /* Don't call gen_lowpart if the inner mode
5574 is VOIDmode and we cannot simplify it, as SUBREG without
5575 inner mode is invalid. */
5582 {
5583 rtx temp;
5589 /* If op is known to have all lower bits zero, the result is zero. */
5599 }
5601 /* Don't change the mode of the MEM if that would change the meaning
5602 of the address. */
5609 /* Note that we cannot do any narrowing for non-constants since
5610 we might have been counting on using the fact that some bits were
5611 zero. We now do this in the SET. */
5618 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5619 replaced by (lshiftrt X C). This will convert
5620 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5628 /* If X has only a single bit that might be nonzero, say, bit I, convert
5629 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5630 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5631 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5632 or a SUBREG of one since we'd be making the expression more
5633 complex if it was just a register. */
5639 {
5640 rtx temp1 = simplify_shift_const
5646 /* If all we did was surround TEMP with the two shifts, we
5647 haven't improved anything, so don't use it. Otherwise,
5648 we are better off with TEMP1. */
5653 }
5657 /* We can't handle truncation to a partial integer mode here
5658 because we don't know the real bitsize of the partial
5659 integer mode. */
5668 /* We can truncate a constant value and return it. */
5672 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5673 whose value is a comparison can be replaced with a subreg if
5674 STORE_FLAG_VALUE permits. */
5683 /* (const (const X)) can become (const X). Do it this way rather than
5684 returning the inner CONST since CONST can be shared with a
5685 REG_EQUAL note. */
5690 #ifdef HAVE_lo_sum
5692 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5693 can add in an offset. find_split_point will split this address up
5694 again if it doesn't match. */
5699 #endif
5702 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5703 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5704 bit-field and can be replaced by either a sign_extend or a
5705 sign_extract. The `and' may be a zero_extend and the two
5706 <c>, -<c> constants may be reversed. */
5721 return simplify_shift_const
5728 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5729 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5730 the bitsize of the mode - 1. This allows simplification of
5731 "a = (b & 8) == 0;" */
5743 /* If we are adding two things that have no bits in common, convert
5744 the addition into an IOR. This will often be further simplified,
5745 for example in cases like ((a & 1) + (a & 2)), which can
5746 become a & 3. */
5751 {
5752 /* Try to simplify the expression further. */
5756 /* If we could, great. If not, do not go ahead with the IOR
5757 replacement, since PLUS appears in many special purpose
5758 address arithmetic instructions. */
5766 }
5770 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5771 (and <foo> (const_int pow2-1)) */
5781 /* If we have (mult (plus A B) C), apply the distributive law and then
5782 the inverse distributive law to see if things simplify. This
5783 occurs mostly in addresses, often when unrolling loops. */
5786 {
5790 }
5792 /* Try simplify a*(b/c) as (a*b)/c. */
5795 {
5801 }
5805 /* If this is a divide by a power of two, treat it as a shift if
5806 its first operand is a shift. */
5824 /* If the first operand is a condition code, we can't do anything
5825 with it. */
5829 {
5837 /* Simplify our comparison, if possible. */
5840 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5841 if only the low-order bit is possibly nonzero in X (such as when
5842 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5843 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5844 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5845 (plus X 1).
5847 Remove any ZERO_EXTRACT we made when thinking this was a
5848 comparison. It may now be simpler to use, e.g., an AND. If a
5849 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5850 the call to make_compound_operation in the SET case.
5852 Don't apply these optimizations if the caller would
5853 prefer a comparison rather than a value.
5854 E.g., for the condition in an IF_THEN_ELSE most targets need
5855 an explicit comparison. */
5858 ;
5874 {
5878 mode);
5879 }
5886 {
5890 const1_rtx);
5891 }
5899 {
5902 }
5904 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5905 those above. */
5907 ;
5923 {
5927 mode);
5928 }
5936 {
5940 mode);
5941 }
5943 /* If X is 0/1, (eq X 0) is X-1. */
5949 {
5952 }
5954 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5955 one bit that might be nonzero, we can convert (ne x 0) to
5956 (ashift x c) where C puts the bit in the sign bit. Remove any
5957 AND with STORE_FLAG_VALUE when we are done, since we are only
5958 going to test the sign bit. */
5965 {
5971 else
5973 }
5975 /* If the code changed, return a whole new comparison.
5976 We also need to avoid using SUBST in cases where
5977 simplify_comparison has widened a comparison with a CONST_INT,
5978 since in that case the wider CONST_INT may fail the sanity
5979 checks in do_SUBST. */
5986 /* Otherwise, keep this operation, but maybe change its operands.
5987 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5990 }
6000 /* If we are processing SET_DEST, we are done. */
6018 /* If this is a shift by a constant amount, simplify it. */
6034 }
6037 }
6038 \f
6039 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6041 static rtx
6043 {
6050 rtx temp;
6053 rtx reversed;
6055 /* Simplify storing of the truth value. */
6060 /* Also when the truth value has to be reversed. */
6066 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6067 in it is being compared against certain values. Get the true and false
6068 comparisons and see if that says anything about the value of each arm. */
6074 {
6075 HOST_WIDE_INT nzb;
6081 /* If FALSE_CODE is EQ, swap the codes and arms. */
6084 {
6087 }
6089 /* If we are comparing against zero and the expression being tested has
6090 only a single bit that might be nonzero, that is its value when it is
6091 not equal to zero. Similarly if it is known to be -1 or 0. */
6095 {
6098 }
6102 {
6105 }
6107 /* Now simplify an arm if we know the value of the register in the
6108 branch and it is used in the arm. Be careful due to the potential
6109 of locally-shared RTL. */
6126 }
6128 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6129 reversed, do so to avoid needing two sets of patterns for
6130 subtract-and-branch insns. Similarly if we have a constant in the true
6131 arm, the false arm is the same as the first operand of the comparison, or
6132 the false arm is more complicated than the true arm. */
6145 {
6154 /* It is possible that the conditional has been simplified out. */
6157 }
6159 /* If the two arms are identical, we don't need the comparison. */
6164 /* Convert a == b ? b : a to "a". */
6176 /* Look for cases where we have (abs x) or (neg (abs X)). */
6179 && comparison_p
6186 {
6192 return
6195 mode);
6198 }
6200 /* Look for MIN or MAX. */
6203 && comparison_p
6208 {
6223 }
6225 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6226 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6227 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6228 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6229 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6230 neither 1 or -1, but it isn't worth checking for. */
6233 && comparison_p
6236 {
6252 /* If an identity-zero op is commutative, check whether there
6253 would be a match if we swapped the operands. */
6273 {
6277 }
6289 {
6293 }
6309 {
6313 }
6325 {
6329 }
6332 {
6338 const_true_rtx));
6346 }
6347 }
6349 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6350 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6351 negation of a single bit, we can convert this operation to a shift. We
6352 can actually do this more generally, but it doesn't seem worth it. */
6361 return
6365 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6375 }
6376 \f
6377 /* Simplify X, a SET expression. Return the new expression. */
6379 static rtx
6381 {
6384 machine_mode mode
6389 /* (set (pc) (return)) gets written as (return). */
6393 /* Now that we know for sure which bits of SRC we are using, see if we can
6394 simplify the expression for the object knowing that we only need the
6395 low-order bits. */
6398 {
6401 }
6403 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6404 the comparison result and try to simplify it unless we already have used
6405 undobuf.other_insn. */
6413 {
6422 {
6425 {
6428 }
6429 }
6430 else
6438 {
6442 }
6443 else
6444 {
6449 /* Attempt to simplify CC user. */
6451 {
6455 }
6457 /* Convert X into a no-op move. */
6461 }
6463 /* Simplify our comparison, if possible. */
6466 #ifdef SELECT_CC_MODE
6467 /* If this machine has CC modes other than CCmode, check to see if we
6468 need to use a different CC mode here. */
6477 else
6480 #ifndef HAVE_cc0
6481 /* If the mode changed, we have to change SET_DEST, the mode in the
6482 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6483 a hard register, just build new versions with the proper mode. If it
6484 is a pseudo, we lose unless it is only time we set the pseudo, in
6485 which case we can safely change its mode. */
6487 {
6489 {
6491 rtx new_dest;
6495 else
6496 {
6499 }
6506 }
6507 }
6511 /* If the code changed, we have to build a new comparison in
6512 undobuf.other_insn. */
6514 {
6523 /* If the only change we made was to change an EQ into an NE or
6524 vice versa, OP0 has only one bit that might be nonzero, and OP1
6525 is zero, check if changing the user of the condition code will
6526 produce a valid insn. If it won't, we can keep the original code
6527 in that insn by surrounding our operation with an XOR. */
6534 {
6539 {
6546 }
6547 }
6548 }
6553 /* Otherwise, if we didn't previously have a COMPARE in the
6554 correct mode, we need one. */
6556 {
6559 }
6561 {
6564 }
6565 /* Otherwise, update the COMPARE if needed. */
6567 {
6570 }
6571 }
6572 else
6573 {
6574 /* Get SET_SRC in a form where we have placed back any
6575 compound expressions. Then do the checks below. */
6578 }
6580 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6581 and X being a REG or (subreg (reg)), we may be able to convert this to
6582 (set (subreg:m2 x) (op)).
6584 We can always do this if M1 is narrower than M2 because that means that
6585 we only care about the low bits of the result.
6587 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6588 perform a narrower operation than requested since the high-order bits will
6589 be undefined. On machine where it is defined, this transformation is safe
6590 as long as M1 and M2 have the same number of words. */
6598 #ifndef WORD_REGISTER_OPERATIONS
6601 #endif
6602 #ifdef CANNOT_CHANGE_MODE_CLASS
6607 #endif
6611 {
6614 dest));
6618 }
6620 #ifdef HAVE_cc0
6621 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6622 in SRC. */
6628 {
6632 /* Here we make sure that we don't have a sign bit on. */
6635 {
6638 }
6639 }
6640 #endif
6642 #ifdef LOAD_EXTEND_OP
6643 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6644 would require a paradoxical subreg. Replace the subreg with a
6645 zero_extend to avoid the reload that would otherwise be required. */
6653 {
6659 }
6660 #endif
6662 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6663 are comparing an item known to be 0 or -1 against 0, use a logical
6664 operation instead. Check for one of the arms being an IOR of the other
6665 arm with some value. We compute three terms to be IOR'ed together. In
6666 practice, at most two will be nonzero. Then we do the IOR's. */
6674 #ifdef HAVE_conditional_move
6676 #endif
6681 {
6707 false_rtx);
6713 term3));
6716 }
6718 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6719 whole thing fail. */
6724 else
6725 /* Convert this into a field assignment operation, if possible. */
6727 }
6728 \f
6729 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6730 result. */
6732 static rtx
6734 {
6740 {
6742 /* We can call simplify_and_const_int only if we don't lose
6743 any (sign) bits when converting INTVAL (op1) to
6744 "unsigned HOST_WIDE_INT". */
6748 {
6755 }
6757 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6758 apply the distributive law and then the inverse distributive
6759 law to see if things simplify. */
6761 {
6765 }
6767 {
6771 }
6775 /* If we have (ior (and A B) C), apply the distributive law and then
6776 the inverse distributive law to see if things simplify. */
6779 {
6783 }
6786 {
6790 }
6795 }
6798 }
6799 \f
6800 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6801 operations" because they can be replaced with two more basic operations.
6802 ZERO_EXTEND is also considered "compound" because it can be replaced with
6803 an AND operation, which is simpler, though only one operation.
6805 The function expand_compound_operation is called with an rtx expression
6806 and will convert it to the appropriate shifts and AND operations,
6807 simplifying at each stage.
6809 The function make_compound_operation is called to convert an expression
6810 consisting of shifts and ANDs into the equivalent compound expression.
6811 It is the inverse of this function, loosely speaking. */
6813 static rtx
6815 {
6819 rtx tem;
6822 {
6826 /* We can't necessarily use a const_int for a multiword mode;
6827 it depends on implicitly extending the value.
6828 Since we don't know the right way to extend it,
6829 we can't tell whether the implicit way is right.
6831 Even for a mode that is no wider than a const_int,
6832 we can't win, because we need to sign extend one of its bits through
6833 the rest of it, and we don't know which bit. */
6837 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6838 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6839 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6840 reloaded. If not for that, MEM's would very rarely be safe.
6842 Reject MODEs bigger than a word, because we might not be able
6843 to reference a two-register group starting with an arbitrary register
6844 (and currently gen_lowpart might crash for a SUBREG). */
6849 /* Reject MODEs that aren't scalar integers because turning vector
6850 or complex modes into shifts causes problems. */
6856 /* If the inner object has VOIDmode (the only way this can happen
6857 is if it is an ASM_OPERANDS), we can't do anything since we don't
6858 know how much masking to do. */
6867 /* ... fall through ... */
6870 /* If the operand is a CLOBBER, just return it. */
6879 /* Reject MODEs that aren't scalar integers because turning vector
6880 or complex modes into shifts causes problems. */
6888 /* This should stay within the object being extracted, fail otherwise. */
6899 }
6900 /* Convert sign extension to zero extension, if we know that the high
6901 bit is not set, as this is easier to optimize. It will be converted
6902 back to cheaper alternative in make_extraction. */
6910 {
6914 /* Make sure this is a profitable operation. */
6921 else
6923 }
6925 /* We can optimize some special cases of ZERO_EXTEND. */
6927 {
6928 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6929 know that the last value didn't have any inappropriate bits
6930 set. */
6938 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6947 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6948 is a comparison and STORE_FLAG_VALUE permits. This is like
6949 the first case, but it works even when GET_MODE (x) is larger
6950 than HOST_WIDE_INT. */
6959 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6969 }
6971 /* If we reach here, we want to return a pair of shifts. The inner
6972 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6973 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6974 logical depending on the value of UNSIGNEDP.
6976 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6977 converted into an AND of a shift.
6979 We must check for the case where the left shift would have a negative
6980 count. This can happen in a case like (x >> 31) & 255 on machines
6981 that can't shift by a constant. On those machines, we would first
6982 combine the shift with the AND to produce a variable-position
6983 extraction. Then the constant of 31 would be substituted in
6984 to produce such a position. */
6988 {
6997 }
7004 else
7005 /* Any other cases we can't handle. */
7008 /* If we couldn't do this for some reason, return the original
7009 expression. */
7014 }
7015 \f
7016 /* X is a SET which contains an assignment of one object into
7017 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7018 or certain SUBREGS). If possible, convert it into a series of
7019 logical operations.
7021 We half-heartedly support variable positions, but do not at all
7022 support variable lengths. */
7024 static const_rtx
7026 {
7027 rtx inner;
7031 machine_mode compute_mode;
7033 /* Loop until we find something we can't simplify. */
7035 {
7038 {
7042 }
7045 {
7050 /* A constant position should stay within the width of INNER. */
7056 {
7064 /* If position is ADJUST - X, new position is X. */
7066 else
7067 {
7072 pos);
7073 }
7074 }
7075 }
7077 /* A SUBREG between two modes that occupy the same numbers of words
7078 can be done by moving the SUBREG to the source. */
7080 /* We need SUBREGs to compute nonzero_bits properly. */
7081 && nonzero_sign_valid
7086 {
7088 gen_lowpart
7092 }
7093 else
7101 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7103 {
7104 machine_mode imode;
7106 /* Don't do anything for vector or complex integral types. */
7110 /* Try to find an integral mode to pun with. */
7117 }
7119 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7123 /* Now compute the equivalent expression. Make a copy of INNER
7124 for the SET_DEST in case it is a MEM into which we will substitute;
7125 we don't want shared RTL in that case. */
7127 compute_mode);
7131 compute_mode,
7133 compute_mode),
7134 inner);
7139 mask),
7140 pos);
7145 }
7148 }
7149 \f
7150 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7151 it is an RTX that represents the (variable) starting position; otherwise,
7152 POS is the (constant) starting bit position. Both are counted from the LSB.
7154 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7156 IN_DEST is nonzero if this is a reference in the destination of a SET.
7157 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7158 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7159 be used.
7161 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7162 ZERO_EXTRACT should be built even for bits starting at bit 0.
7164 MODE is the desired mode of the result (if IN_DEST == 0).
7166 The result is an RTX for the extraction or NULL_RTX if the target
7167 can't handle it. */
7169 static rtx
7173 {
7174 /* This mode describes the size of the storage area
7175 to fetch the overall value from. Within that, we
7176 ignore the POS lowest bits, etc. */
7178 machine_mode inner_mode;
7179 machine_mode wanted_inner_mode;
7186 HOST_WIDE_INT orig_pos;
7192 {
7193 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7194 consider just the QI as the memory to extract from.
7195 The subreg adds or removes high bits; its mode is
7196 irrelevant to the meaning of this extraction,
7197 since POS and LEN count from the lsb. */
7201 }
7206 {
7207 /* We're extracting the least significant bits of an rtx
7208 (ashift X (const_int C)), where LEN > C. Extract the
7209 least significant (LEN - C) bits of X, giving an rtx
7210 whose mode is MODE, then shift it left C times. */
7216 }
7222 /* See if this can be done without an extraction. We never can if the
7223 width of the field is not the same as that of some integer mode. For
7224 registers, we can only avoid the extraction if the position is at the
7225 low-order bit and this is either not in the destination or we have the
7226 appropriate STRICT_LOW_PART operation available.
7228 For MEM, we can avoid an extract if the field starts on an appropriate
7229 boundary and we can change the mode of the memory reference. */
7238 && (! in_dest
7242 && (pos
7245 /* We can't do this if we are widening INNER_MODE (it
7246 may not be aligned, for one thing). */
7252 {
7253 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7254 field. If the original and current mode are the same, we need not
7255 adjust the offset. Otherwise, we do if bytes big endian.
7257 If INNER is not a MEM, get a piece consisting of just the field
7258 of interest (in this case POS % BITS_PER_WORD must be 0). */
7261 {
7262 HOST_WIDE_INT offset;
7264 /* POS counts from lsb, but make OFFSET count in memory order. */
7267 else
7271 }
7273 {
7275 {
7276 /* We can't call gen_lowpart in a DEST since we
7277 always want a SUBREG (see below) and it would sometimes
7278 return a new hard register. */
7280 {
7295 /* Avoid creating invalid subregs, for example when
7296 simplifying (x>>32)&255. */
7301 }
7302 else
7304 }
7305 else
7307 }
7308 else
7310 len >= HOST_BITS_PER_WIDE_INT
7315 /* If this extraction is going into the destination of a SET,
7316 make a STRICT_LOW_PART unless we made a MEM. */
7331 /* If we know that no extraneous bits are set, and that the high
7332 bit is not set, convert the extraction to the cheaper of
7333 sign and zero extension, that are equivalent in these cases. */
7339 {
7343 /* Prefer ZERO_EXTENSION, since it gives more information to
7344 backends. */
7349 }
7351 /* Otherwise, sign- or zero-extend unless we already are in the
7352 proper mode. */
7356 }
7358 /* Unless this is a COMPARE or we have a funny memory reference,
7359 don't do anything with zero-extending field extracts starting at
7360 the low-order bit since they are simple AND operations. */
7365 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7366 if the position is not a constant and the length is not 1. In all
7367 other cases, we would only be going outside our object in cases when
7368 an original shift would have been undefined. */
7377 /* If INNER is not from memory, we want it to have the mode of a register
7378 extraction pattern's structure operand, or word_mode if there is no
7379 such pattern. The same applies to extraction_mode and pos_mode
7380 and their respective operands.
7382 For memory, assume that the desired extraction_mode and pos_mode
7383 are the same as for a register operation, since at present we don't
7384 have named patterns for aligned memory structures. */
7388 {
7392 }
7394 /* Never narrow an object, since that might not be safe. */
7402 else
7403 {
7404 /* Be careful not to go beyond the extracted object and maintain the
7405 natural alignment of the memory. */
7409 {
7412 }
7413 }
7418 {
7419 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7420 BITS_BIG_ENDIAN style. If position is constant, compute new
7421 position. Otherwise, build subtraction.
7422 Note that POS is relative to the mode of the original argument.
7423 If it's a MEM we need to recompute POS relative to that.
7424 However, if we're extracting from (or inserting into) a register,
7425 we want to recompute POS relative to wanted_inner_mode. */
7432 else
7433 pos_rtx
7436 pos_rtx);
7437 /* POS may be less than 0 now, but we check for that below.
7438 Note that it can only be less than 0 if !MEM_P (inner). */
7439 }
7441 /* If INNER has a wider mode, and this is a constant extraction, try to
7442 make it smaller and adjust the byte to point to the byte containing
7443 the value. */
7446 && ! pos_rtx
7451 {
7454 /* The computations below will be correct if the machine is big
7455 endian in both bits and bytes or little endian in bits and bytes.
7456 If it is mixed, we must adjust. */
7458 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7459 adjust OFFSET to compensate. */
7464 /* We can now move to the desired byte. */
7475 }
7477 /* If INNER is not memory, get it into the proper mode. If we are changing
7478 its mode, POS must be a constant and smaller than the size of the new
7479 mode. */
7481 {
7482 /* On the LHS, don't create paradoxical subregs implicitely truncating
7483 the register unless TRULY_NOOP_TRUNCATION. */
7486 wanted_inner_mode))
7498 pos_rtx
7504 }
7506 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7507 have to zero extend. Otherwise, we can just use a SUBREG. */
7510 {
7514 /* If we know that no extraneous bits are set, and that the high
7515 bit is not set, convert extraction to cheaper one - either
7516 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7517 cases. */
7525 {
7529 /* Prefer ZERO_EXTENSION, since it gives more information to
7530 backends. */
7534 }
7536 }
7538 /* Make POS_RTX unless we already have it and it is correct. If we don't
7539 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7540 be a CONST_INT. */
7547 /* Make the required operation. See if we can use existing rtx. */
7554 }
7555 \f
7556 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7557 with any other operations in X. Return X without that shift if so. */
7559 static rtx
7561 {
7564 rtx tem;
7567 {
7569 /* This is the shift itself. If it is wide enough, we will return
7570 either the value being shifted if the shift count is equal to
7571 COUNT or a shift for the difference. */
7585 /* If we can safely shift this constant and we find the inner shift,
7586 make a new operation. */
7591 {
7595 }
7600 }
7603 }
7604 \f
7605 /* Look at the expression rooted at X. Look for expressions
7606 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7607 Form these expressions.
7609 Return the new rtx, usually just X.
7611 Also, for machines like the VAX that don't have logical shift insns,
7612 try to convert logical to arithmetic shift operations in cases where
7613 they are equivalent. This undoes the canonicalizations to logical
7614 shifts done elsewhere.
7616 We try, as much as possible, to re-use rtl expressions to save memory.
7618 IN_CODE says what kind of expression we are processing. Normally, it is
7619 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7620 being kludges), it is MEM. When processing the arguments of a comparison
7621 or a COMPARE against zero, it is COMPARE. */
7623 rtx
7625 {
7633 rtx tem;
7636 /* Select the code to be used in recursive calls. Once we are inside an
7637 address, we stay there. If we have a comparison, set to COMPARE,
7638 but once inside, go back to our default of SET. */
7647 /* Process depending on the code of this operation. If NEW is set
7648 nonzero, it will be returned. */
7651 {
7653 /* Convert shifts by constants into multiplications if inside
7654 an address. */
7659 {
7665 {
7668 }
7671 }
7681 {
7685 }
7688 {
7692 mode));
7694 }
7695 else
7696 {
7700 }
7711 {
7715 }
7718 {
7722 mode));
7724 }
7725 else
7726 {
7730 }
7734 /* If the second operand is not a constant, we can't do anything
7735 with it. */
7739 /* If the constant is a power of two minus one and the first operand
7740 is a logical right shift, make an extraction. */
7743 {
7747 }
7749 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7754 {
7756 next_code);
7760 }
7761 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7767 {
7768 /* Apply the distributive law, and then try to make extractions. */
7775 }
7777 /* If we are have (and (rotate X C) M) and C is larger than the number
7778 of bits in M, this is an extraction. */
7784 {
7790 }
7792 /* On machines without logical shifts, if the operand of the AND is
7793 a logical shift and our mask turns off all the propagated sign
7794 bits, we can replace the logical shift with an arithmetic shift. */
7802 {
7809 make_compound_operation
7812 }
7814 /* If the constant is one less than a power of two, this might be
7815 representable by an extraction even if no shift is present.
7816 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7817 we are in a COMPARE. */
7821 next_code),
7824 /* If we are in a comparison and this is an AND with a power of two,
7825 convert this into the appropriate bit extract. */
7830 next_code),
7836 /* If the sign bit is known to be zero, replace this with an
7837 arithmetic shift. */
7842 {
7845 next_code),
7848 }
7850 /* ... fall through ... */
7856 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7857 this is a SIGN_EXTRACT. */
7864 {
7871 }
7873 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7874 If so, try to merge the shifts into a SIGN_EXTEND. We could
7875 also do this for some cases of SIGN_EXTRACT, but it doesn't
7876 seem worth the effort; the case checked for occurs on Alpha. */
7892 /* Call ourselves recursively on the inner expression. If we are
7893 narrowing the object and it has a different RTL code from
7894 what it originally did, do this SUBREG as a force_to_mode. */
7895 {
7899 /* If in_code is COMPARE, it isn't always safe to pass it through
7900 to the recursive make_compound_operation call. */
7904 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7905 is (const_int 0), rather than
7906 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7916 simplified
7924 {
7925 rtx newer
7928 /* If we have something other than a SUBREG, we might have
7929 done an expansion, so rerun ourselves. */
7933 /* force_to_mode can expand compounds. If it just re-expanded the
7934 compound, use gen_lowpart to convert to the desired mode. */
7936 /* Likewise if it re-expanded the compound only partially.
7937 This happens for SUBREG of ZERO_EXTRACT if they extract
7938 the same number of bits. */
7947 }
7951 }
7956 }
7959 {
7962 }
7964 /* Now recursively process each operand of this operation. We need to
7965 handle ZERO_EXTEND specially so that we don't lose track of the
7966 inner mode. */
7968 {
7976 }
7981 {
7984 }
7987 {
7990 }
7992 maybe_swap:
7993 /* If this is a commutative operation, the changes to the operands
7994 may have made it noncanonical. */
7997 {
8001 }
8004 }
8005 \f
8006 /* Given M see if it is a value that would select a field of bits
8007 within an item, but not the entire word. Return -1 if not.
8008 Otherwise, return the starting position of the field, where 0 is the
8009 low-order bit.
8011 *PLEN is set to the length of the field. */
8013 static int
8015 {
8016 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8021 /* Now shift off the low-order zero bits and see if we have a
8022 power of two minus 1. */
8030 }
8031 \f
8032 /* If X refers to a register that equals REG in value, replace these
8033 references with REG. */
8034 static rtx
8036 {
8044 {
8080 {
8084 else
8086 }
8088 /* fall through */
8095 {
8098 {
8100 {
8103 }
8105 }
8106 }
8108 {
8111 {
8114 {
8116 {
8119 }
8121 }
8122 }
8123 }
8126 }
8129 }
8131 /* Return X converted to MODE. If the value is already truncated to
8132 MODE we can just return a subreg even though in the general case we
8133 would need an explicit truncation. */
8135 static rtx
8137 {
8142 {
8143 /* Bit-cast X into an integer mode. */
8148 }
8151 }
8153 /* See if X can be simplified knowing that we will only refer to it in
8154 MODE and will only refer to those bits that are nonzero in MASK.
8155 If other bits are being computed or if masking operations are done
8156 that select a superset of the bits in MASK, they can sometimes be
8157 ignored.
8159 Return a possibly simplified expression, but always convert X to
8160 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8162 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8163 are all off in X. This is used when X will be complemented, by either
8164 NOT, NEG, or XOR. */
8166 static rtx
8169 {
8172 machine_mode op_mode;
8176 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8177 code below will do the wrong thing since the mode of such an
8178 expression is VOIDmode.
8180 Also do nothing if X is a CLOBBER; this can happen if X was
8181 the return value from a call to gen_lowpart. */
8185 /* We want to perform the operation in its present mode unless we know
8186 that the operation is valid in MODE, in which case we do the operation
8187 in MODE. */
8192 /* It is not valid to do a right-shift in a narrower mode
8193 than the one it came in with. */
8198 /* Truncate MASK to fit OP_MODE. */
8202 /* When we have an arithmetic operation, or a shift whose count we
8203 do not know, we need to assume that all bits up to the highest-order
8204 bit in MASK will be needed. This is how we form such a mask. */
8207 else
8211 /* Determine what bits of X are guaranteed to be (non)zero. */
8214 /* If none of the bits in X are needed, return a zero. */
8218 /* If X is a CONST_INT, return a new one. Do this here since the
8219 test below will fail. */
8221 {
8224 else
8225 {
8228 }
8229 }
8231 /* If X is narrower than MODE and we want all the bits in X's mode, just
8232 get X in the proper mode. */
8237 /* We can ignore the effect of a SUBREG if it narrows the mode or
8238 if the constant masks to zero all the bits the mode doesn't have. */
8248 /* The arithmetic simplifications here only work for scalar integer modes. */
8253 {
8255 /* If X is a (clobber (const_int)), return it since we know we are
8256 generating something that won't match. */
8269 /* Similarly for a truncate. */
8273 /* If this is an AND with a constant, convert it into an AND
8274 whose constant is the AND of that constant with MASK. If it
8275 remains an AND of MASK, delete it since it is redundant. */
8278 {
8282 /* If X is still an AND, see if it is an AND with a mask that
8283 is just some low-order bits. If so, and it is MASK, we don't
8284 need it. */
8291 /* If it remains an AND, try making another AND with the bits
8292 in the mode mask that aren't in MASK turned on. If the
8293 constant in the AND is wide enough, this might make a
8294 cheaper constant. */
8299 {
8300 unsigned HOST_WIDE_INT cval
8303 rtx y;
8310 }
8313 }
8318 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8319 low-order bits (as in an alignment operation) and FOO is already
8320 aligned to that boundary, mask C1 to that boundary as well.
8321 This may eliminate that PLUS and, later, the AND. */
8323 {
8327 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8328 number, sign extend it. */
8341 }
8343 /* ... fall through ... */
8346 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8347 most significant bit in MASK since carries from those bits will
8348 affect the bits we are interested in. */
8353 /* If X is (minus C Y) where C's least set bit is larger than any bit
8354 in the mask, then we may replace with (neg Y). */
8357 {
8361 }
8363 /* Similarly, if C contains every bit in the fuller_mask, then we may
8364 replace with (not Y). */
8367 {
8371 }
8378 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8379 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8380 operation which may be a bitfield extraction. Ensure that the
8381 constant we form is not wider than the mode of X. */
8393 {
8402 }
8404 binop:
8405 /* For most binary operations, just propagate into the operation and
8406 change the mode if we have an operation of that mode. */
8411 /* If we ended up truncating both operands, truncate the result of the
8412 operation instead. */
8415 {
8418 }
8428 /* For left shifts, do the same, but just for the first operand.
8429 However, we cannot do anything with shifts where we cannot
8430 guarantee that the counts are smaller than the size of the mode
8431 because such a count will have a different meaning in a
8432 wider mode. */
8442 /* If the shift count is a constant and we can do arithmetic in
8443 the mode of the shift, refine which bits we need. Otherwise, use the
8444 conservative form of the mask. */
8450 else
8462 /* Here we can only do something if the shift count is a constant,
8463 this shift constant is valid for the host, and we can do arithmetic
8464 in OP_MODE. */
8470 {
8474 /* Select the mask of the bits we need for the shift operand. */
8477 /* We can only change the mode of the shift if we can do arithmetic
8478 in the mode of the shift and INNER_MASK is no wider than the
8479 width of X's mode. */
8487 }
8489 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8490 shift and AND produces only copies of the sign bit (C2 is one less
8491 than a power of two), we can do this with just a shift. */
8495 /* The shift puts one of the sign bit copies in the least significant
8496 bit. */
8501 /* Number of bits left after the shift must be more than the mask
8502 needs. */
8505 /* Must be more sign bit copies than the mask needs. */
8515 /* If we are just looking for the sign bit, we don't need this shift at
8516 all, even if it has a variable count. */
8520 /* If this is a shift by a constant, get a mask that contains those bits
8521 that are not copies of the sign bit. We then have two cases: If
8522 MASK only includes those bits, this can be a logical shift, which may
8523 allow simplifications. If MASK is a single-bit field not within
8524 those bits, we are requesting a copy of the sign bit and hence can
8525 shift the sign bit to the appropriate location. */
8529 {
8532 /* If the considered data is wider than HOST_WIDE_INT, we can't
8533 represent a mask for all its bits in a single scalar.
8534 But we only care about the lower bits, so calculate these. */
8537 {
8540 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8541 is the number of bits a full-width mask would have set.
8542 We need only shift if these are fewer than nonzero can
8543 hold. If not, we must keep all bits set in nonzero. */
8548 + HOST_BITS_PER_WIDE_INT
8550 }
8551 else
8552 {
8555 }
8558 {
8563 }
8566 {
8567 x = simplify_shift_const
8573 }
8574 }
8576 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8577 even if the shift count isn't a constant. */
8582 shiftrt:
8584 /* If this is a zero- or sign-extension operation that just affects bits
8585 we don't care about, remove it. Be sure the call above returned
8586 something that is still a shift. */
8596 next_select);
8602 /* If the shift count is constant and we can do computations
8603 in the mode of X, compute where the bits we care about are.
8604 Otherwise, we can't do anything. Don't change the mode of
8605 the shift or propagate MODE into the shift, though. */
8608 {
8618 }
8622 /* If we just want the low-order bit, the NEG isn't needed since it
8623 won't change the low-order bit. */
8627 /* We need any bits less significant than the most significant bit in
8628 MASK since carries from those bits will affect the bits we are
8629 interested in. */
8634 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8635 same as the XOR case above. Ensure that the constant we form is not
8636 wider than the mode of X. */
8644 {
8653 }
8655 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8656 use the full mask inside the NOT. */
8659 unop:
8662 next_select));
8668 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8669 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8670 which is equal to STORE_FLAG_VALUE. */
8682 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8683 written in a narrower mode. We play it safe and do not do so. */
8699 }
8701 /* Ensure we return a value of the proper mode. */
8703 }
8704 \f
8705 /* Return nonzero if X is an expression that has one of two values depending on
8706 whether some other value is zero or nonzero. In that case, we return the
8707 value that is being tested, *PTRUE is set to the value if the rtx being
8708 returned has a nonzero value, and *PFALSE is set to the other alternative.
8710 If we return zero, we set *PTRUE and *PFALSE to X. */
8712 static rtx
8714 {
8720 /* If we are comparing a value against zero, we are done. */
8723 {
8727 }
8729 /* If this is a unary operation whose operand has one of two values, apply
8730 our opcode to compute those values. */
8733 {
8738 }
8740 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8741 make can't possibly match and would suppress other optimizations. */
8743 ;
8745 /* If this is a binary operation, see if either side has only one of two
8746 values. If either one does or if both do and they are conditional on
8747 the same value, compute the new true and false values. */
8749 {
8755 {
8756 /* If if_then_else_cond returned zero, then true/false are the
8757 same rtl. We must copy one of them to prevent invalid rtl
8758 sharing. */
8765 {
8770 }
8771 else
8772 {
8775 }
8778 }
8780 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8781 operands is zero when the other is nonzero, and vice-versa,
8782 and STORE_FLAG_VALUE is 1 or -1. */
8788 {
8805 {
8812 const_true_rtx);
8814 }
8815 }
8817 /* Similarly for MULT, AND and UMIN, except that for these the result
8818 is always zero. */
8822 {
8836 {
8839 }
8840 }
8841 }
8844 {
8845 /* If we have IF_THEN_ELSE already, extract the condition and
8846 canonicalize it if it is NE or EQ. */
8852 {
8855 }
8856 else
8858 }
8860 /* If X is a SUBREG, we can narrow both the true and false values
8861 if the inner expression, if there is a condition. */
8865 {
8871 {
8875 }
8876 }
8878 /* If X is a constant, this isn't special and will cause confusions
8879 if we treat it as such. Likewise if it is equivalent to a constant. */
8882 ;
8884 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8885 will be least confusing to the rest of the compiler. */
8887 {
8890 }
8892 /* If X is known to be either 0 or -1, those are the true and
8893 false values when testing X. */
8897 {
8900 }
8902 /* Likewise for 0 or a single bit. */
8905 {
8908 }
8910 /* Otherwise fail; show no condition with true and false values the same. */
8913 }
8914 \f
8915 /* Return the value of expression X given the fact that condition COND
8916 is known to be true when applied to REG as its first operand and VAL
8917 as its second. X is known to not be shared and so can be modified in
8918 place.
8920 We only handle the simplest cases, and specifically those cases that
8921 arise with IF_THEN_ELSE expressions. */
8923 static rtx
8925 {
8927 rtx temp;
8934 /* If either operand of the condition is a floating point value,
8935 then we have to avoid collapsing an EQ comparison. */
8945 /* If X is (abs REG) and we know something about REG's relationship
8946 with zero, we may be able to simplify this. */
8950 {
8959 }
8961 /* The only other cases we handle are MIN, MAX, and comparisons if the
8962 operands are the same as REG and VAL. */
8965 {
8970 {
8972 {
8980 else
8982 }
8985 {
8988 /* Do not reverse the condition when it is NE or EQ.
8989 This is because we cannot conclude anything about
8990 the value of 'SMAX (x, y)' when x is not equal to y,
8991 but we can when x equals y. */
8997 {
9008 }
9009 }
9010 }
9011 }
9013 {
9018 {
9019 /* We must simplify subreg here, before we lose track of the
9020 original inner_mode. */
9025 else
9027 }
9030 }
9031 /* We don't have to handle SIGN_EXTEND here, because even in the
9032 case of replacing something with a modeless CONST_INT, a
9033 CONST_INT is already (supposed to be) a valid sign extension for
9034 its narrower mode, which implies it's already properly
9035 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9036 story is different. */
9038 {
9043 {
9044 /* We must simplify the zero_extend here, before we lose
9045 track of the original inner_mode. */
9050 else
9052 }
9055 }
9059 {
9066 }
9069 }
9070 \f
9071 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9072 assignment as a field assignment. */
9074 static int
9076 {
9083 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9084 Note that all SUBREGs of MEM are paradoxical; otherwise they
9085 would have been rewritten. */
9098 /* We used to see if get_last_value of X and Y were the same but that's
9099 not correct. In one direction, we'll cause the assignment to have
9100 the wrong destination and in the case, we'll import a register into this
9101 insn that might have already have been dead. So fail if none of the
9102 above cases are true. */
9104 }
9105 \f
9106 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9107 Return that assignment if so.
9109 We only handle the most common cases. */
9111 static rtx
9113 {
9116 rtx assign;
9118 HOST_WIDE_INT c1;
9119 HOST_WIDE_INT pos;
9121 rtx other;
9122 machine_mode mode;
9124 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9125 a clear of a one-bit field. We will have changed it to
9126 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9127 for a SUBREG. */
9133 {
9139 }
9149 {
9156 }
9158 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9159 one-bit field. */
9163 {
9169 }
9171 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9172 SRC is an AND with all bits of that field set, then we can discard
9173 the AND. */
9178 {
9185 else
9188 /* Complete overlap. We can remove the source AND. */
9192 /* Partial overlap. We can reduce the source AND. */
9194 {
9199 }
9200 }
9202 /* The other case we handle is assignments into a constant-position
9203 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9204 a mask that has all one bits except for a group of zero bits and
9205 OTHER is known to have zeros where C1 has ones, this is such an
9206 assignment. Compute the position and length from C1. Shift OTHER
9207 to the appropriate position, force it to the required mode, and
9208 make the extraction. Check for the AND in both operands. */
9224 else
9237 /* The mode to use for the source is the mode of the assignment, or of
9238 what is inside a possible STRICT_LOW_PART. */
9242 /* Shift OTHER right POS places and make it the source, restricting it
9243 to the proper length and mode. */
9248 dest);
9255 /* If SRC is masked by an AND that does not make a difference in
9256 the value being stored, strip it. */
9267 }
9268 \f
9269 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9270 if so. */
9272 static rtx
9274 {
9278 rtx tem;
9280 /* Distributivity is not true for floating point as it can change the
9281 value. So we don't do it unless -funsafe-math-optimizations. */
9286 /* The outer operation can only be one of the following: */
9294 /* If either operand is a primitive we can't do anything, so get out
9295 fast. */
9305 /* See if the inner and outer operations distribute. */
9307 {
9312 /* These all distribute except over PLUS. */
9323 /* This is also a multiply, so it distributes over everything. */
9326 /* This used to handle SUBREG, but this turned out to be counter-
9327 productive, since (subreg (op ...)) usually is not handled by
9328 insn patterns, and this "optimization" therefore transformed
9329 recognizable patterns into unrecognizable ones. Therefore the
9330 SUBREG case was removed from here.
9332 It is possible that distributing SUBREG over arithmetic operations
9333 leads to an intermediate result than can then be optimized further,
9334 e.g. by moving the outer SUBREG to the other side of a SET as done
9335 in simplify_set. This seems to have been the original intent of
9336 handling SUBREGs here.
9338 However, with current GCC this does not appear to actually happen,
9339 at least on major platforms. If some case is found where removing
9340 the SUBREG case here prevents follow-on optimizations, distributing
9341 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9345 }
9347 /* Set LHS and RHS to the inner operands (A and B in the example
9348 above) and set OTHER to the common operand (C in the example).
9349 There is only one way to do this unless the inner operation is
9350 commutative. */
9362 else
9365 /* Form the new inner operation, seeing if it simplifies first. */
9368 /* There is one exception to the general way of distributing:
9369 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9371 {
9374 }
9376 /* We may be able to continuing distributing the result, so call
9377 ourselves recursively on the inner operation before forming the
9378 outer operation, which we return. */
9381 }
9383 /* See if X is of the form (* (+ A B) C), and if so convert to
9384 (+ (* A C) (* B C)) and try to simplify.
9386 Most of the time, this results in no change. However, if some of
9387 the operands are the same or inverses of each other, simplifications
9388 will result.
9390 For example, (and (ior A B) (not B)) can occur as the result of
9391 expanding a bit field assignment. When we apply the distributive
9392 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9393 which then simplifies to (and (A (not B))).
9395 Note that no checks happen on the validity of applying the inverse
9396 distributive law. This is pointless since we can do it in the
9397 few places where this routine is called.
9399 N is the index of the term that is decomposed (the arithmetic operation,
9400 i.e. (+ A B) in the first example above). !N is the index of the term that
9401 is distributed, i.e. of C in the first example above. */
9402 static rtx
9404 {
9405 machine_mode mode;
9409 /* Distributivity is not true for floating point as it can change the
9410 value. So we don't do it unless -funsafe-math-optimizations. */
9427 /* Special case (and (xor B C) (not A)), which is equivalent to
9428 (xor (ior A B) (ior A C)) */
9430 {
9433 }
9436 {
9437 /* Distribute the second term. */
9440 }
9441 else
9442 {
9443 /* Distribute the first term. */
9446 }
9456 }
9457 \f
9458 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9459 in MODE. Return an equivalent form, if different from (and VAROP
9460 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9462 static rtx
9465 {
9468 rtx orig_varop;
9476 /* Simplify VAROP knowing that we will be only looking at some of the
9477 bits in it.
9479 Note by passing in CONSTOP, we guarantee that the bits not set in
9480 CONSTOP are not significant and will never be examined. We must
9481 ensure that is the case by explicitly masking out those bits
9482 before returning. */
9485 /* If VAROP is a CLOBBER, we will fail so return it. */
9489 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9490 to VAROP and return the new constant. */
9494 /* See what bits may be nonzero in VAROP. Unlike the general case of
9495 a call to nonzero_bits, here we don't care about bits outside
9496 MODE. */
9500 /* Turn off all bits in the constant that are known to already be zero.
9501 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9502 which is tested below. */
9506 /* If we don't have any bits left, return zero. */
9510 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9511 a power of two, we can replace this with an ASHIFT. */
9516 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9517 or XOR, then try to apply the distributive law. This may eliminate
9518 operations if either branch can be simplified because of the AND.
9519 It may also make some cases more complex, but those cases probably
9520 won't match a pattern either with or without this. */
9523 return
9524 gen_lowpart
9526 apply_distributive_law
9531 constop),
9535 constop))));
9537 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9538 the AND and see if one of the operands simplifies to zero. If so, we
9539 may eliminate it. */
9543 {
9552 }
9554 /* Make a SUBREG if necessary. If we can't make it, fail. */
9559 /* If we are only masking insignificant bits, return VAROP. */
9566 /* Otherwise, return an AND. */
9568 }
9571 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9572 in MODE.
9574 Return an equivalent form, if different from X. Otherwise, return X. If
9575 X is zero, we are to always construct the equivalent form. */
9577 static rtx
9580 {
9591 }
9592 \f
9593 /* Given a REG, X, compute which bits in X can be nonzero.
9594 We don't care about bits outside of those defined in MODE.
9596 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9597 a shift, AND, or zero_extract, we can do better. */
9599 static rtx
9601 const_rtx known_x ATTRIBUTE_UNUSED,
9602 machine_mode known_mode ATTRIBUTE_UNUSED,
9605 {
9606 rtx tem;
9609 /* If X is a register whose nonzero bits value is current, use it.
9610 Otherwise, if X is a register whose value we can find, use that
9611 value. Otherwise, use the previously-computed global nonzero bits
9612 for this register. */
9625 && !REGNO_REG_SET_P
9628 {
9632 /* We don't know anything about the upper bits. */
9637 }
9642 {
9643 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9644 /* If X is narrower than MODE and TEM is a non-negative
9645 constant that would appear negative in the mode of X,
9646 sign-extend it for use in reg_nonzero_bits because some
9647 machines (maybe most) will actually do the sign-extension
9648 and this is the conservative approach.
9650 ??? For 2.5, try to tighten up the MD files in this regard
9651 instead of this kludge. */
9658 #endif
9660 }
9662 {
9666 /* We don't know anything about the upper bits. */
9670 }
9673 }
9675 /* Return the number of bits at the high-order end of X that are known to
9676 be equal to the sign bit. X will be used in mode MODE; if MODE is
9677 VOIDmode, X will be used in its own mode. The returned value will always
9678 be between 1 and the number of bits in MODE. */
9680 static rtx
9682 const_rtx known_x ATTRIBUTE_UNUSED,
9683 machine_mode known_mode
9684 ATTRIBUTE_UNUSED,
9687 {
9688 rtx tem;
9700 && !REGNO_REG_SET_P
9703 {
9706 }
9717 }
9718 \f
9719 /* Return the number of "extended" bits there are in X, when interpreted
9720 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9721 unsigned quantities, this is the number of high-order zero bits.
9722 For signed quantities, this is the number of copies of the sign bit
9723 minus 1. In both case, this function returns the number of "spare"
9724 bits. For example, if two quantities for which this function returns
9725 at least 1 are added, the addition is known not to overflow.
9727 This function will always return 0 unless called during combine, which
9728 implies that it must be called from a define_split. */
9730 unsigned int
9732 {
9742 }
9744 /* This function is called from `simplify_shift_const' to merge two
9745 outer operations. Specifically, we have already found that we need
9746 to perform operation *POP0 with constant *PCONST0 at the outermost
9747 position. We would now like to also perform OP1 with constant CONST1
9748 (with *POP0 being done last).
9750 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9751 the resulting operation. *PCOMP_P is set to 1 if we would need to
9752 complement the innermost operand, otherwise it is unchanged.
9754 MODE is the mode in which the operation will be done. No bits outside
9755 the width of this mode matter. It is assumed that the width of this mode
9756 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9758 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9759 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9760 result is simply *PCONST0.
9762 If the resulting operation cannot be expressed as one operation, we
9763 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9765 static int
9766 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9767 {
9774 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9778 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9779 if OP0 is SET. */
9788 {
9790 {
9808 }
9809 }
9811 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9815 /* If the two constants aren't the same, we can't do anything. The
9816 remaining six cases can all be done. */
9820 else
9822 {
9825 /* (a & b) | b == b */
9828 /* (a ^ b) | b == a | b */
9829 {;}
9834 /* (a & b) ^ b == (~a) & b */
9837 /* (a | b) ^ b == a & ~b */
9843 /* (a | b) & b == b */
9846 /* (a ^ b) & b) == (~a) & b */
9851 }
9853 /* Check for NO-OP cases. */
9866 /* ??? Slightly redundant with the above mask, but not entirely.
9867 Moving this above means we'd have to sign-extend the mode mask
9868 for the final test. */
9873 }
9874 \f
9875 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9876 the shift in. The original shift operation CODE is performed on OP in
9877 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9878 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9879 result of the shift is subject to operation OUTER_CODE with operand
9880 OUTER_CONST. */
9882 static machine_mode
9886 {
9891 /* In general we can't perform in wider mode for right shift and rotate. */
9893 {
9895 /* We can still widen if the bits brought in from the left are identical
9896 to the sign bit of ORIG_MODE. */
9904 /* Similarly here but with zero bits. */
9909 /* We can also widen if the bits brought in will be masked off. This
9910 operation is performed in ORIG_MODE. */
9912 {
9918 }
9919 /* fall through */
9929 }
9930 }
9932 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9933 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9934 if we cannot simplify it. Otherwise, return a simplified value.
9936 The shift is normally computed in the widest mode we find in VAROP, as
9937 long as it isn't a different number of words than RESULT_MODE. Exceptions
9938 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9940 static rtx
9943 {
9949 unsigned int mode_words
9951 /* We form (outer_op (code varop count) (outer_const)). */
9957 /* Make sure and truncate the "natural" shift on the way in. We don't
9958 want to do this inside the loop as it makes it more difficult to
9959 combine shifts. */
9963 /* If we were given an invalid count, don't do anything except exactly
9964 what was requested. */
9971 /* Unless one of the branches of the `if' in this loop does a `continue',
9972 we will `break' the loop after the `if'. */
9975 {
9976 /* If we have an operand of (clobber (const_int 0)), fail. */
9980 /* Convert ROTATERT to ROTATE. */
9982 {
9987 else
9989 }
9994 /* Handle cases where the count is greater than the size of the mode
9995 minus 1. For ASHIFT, use the size minus one as the count (this can
9996 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9997 take the count modulo the size. For other shifts, the result is
9998 zero.
10000 Since these shifts are being produced by the compiler by combining
10001 multiple operations, each of which are defined, we know what the
10002 result is supposed to be. */
10005 {
10010 else
10011 {
10012 /* We can't simply return zero because there may be an
10013 outer op. */
10017 }
10018 }
10020 /* If we discovered we had to complement VAROP, leave. Making a NOT
10021 here would cause an infinite loop. */
10025 /* An arithmetic right shift of a quantity known to be -1 or 0
10026 is a no-op. */
10030 {
10033 }
10035 /* If we are doing an arithmetic right shift and discarding all but
10036 the sign bit copies, this is equivalent to doing a shift by the
10037 bitsize minus one. Convert it into that shift because it will often
10038 allow other simplifications. */
10045 /* We simplify the tests below and elsewhere by converting
10046 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10047 `make_compound_operation' will convert it to an ASHIFTRT for
10048 those machines (such as VAX) that don't have an LSHIFTRT. */
10065 {
10072 {
10075 }
10079 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10080 minus the width of a smaller mode, we can do this with a
10081 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10088 {
10097 }
10101 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10102 the same number of words as what we've seen so far. Then store
10103 the widest mode in MODE. */
10109 == mode_words
10112 {
10117 }
10121 /* Some machines use MULT instead of ASHIFT because MULT
10122 is cheaper. But it is still better on those machines to
10123 merge two shifts into one. */
10126 {
10127 varop
10133 }
10137 /* Similar, for when divides are cheaper. */
10140 {
10141 varop
10147 }
10151 /* If we are extracting just the sign bit of an arithmetic
10152 right shift, that shift is not needed. However, the sign
10153 bit of a wider mode may be different from what would be
10154 interpreted as the sign bit in a narrower mode, so, if
10155 the result is narrower, don't discard the shift. */
10160 {
10163 }
10165 /* ... fall through ... */
10170 /* Here we have two nested shifts. The result is usually the
10171 AND of a new shift with a mask. We compute the result below. */
10178 {
10182 rtx mask_rtx;
10184 /* We have one common special case. We can't do any merging if
10185 the inner code is an ASHIFTRT of a smaller mode. However, if
10186 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10187 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10188 we can convert it to
10189 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10190 This simplifies certain SIGN_EXTEND operations. */
10194 {
10195 /* C3 has the low-order C1 bits zero. */
10207 }
10209 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10210 than C1 high-order bits equal to the sign bit, we can convert
10211 this to either an ASHIFT or an ASHIFTRT depending on the
10212 two counts.
10214 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10220 {
10224 {
10227 }
10230 }
10232 /* There are some cases we can't do. If CODE is ASHIFTRT,
10233 we can only do this if FIRST_CODE is also ASHIFTRT.
10235 We can't do the case when CODE is ROTATE and FIRST_CODE is
10236 ASHIFTRT.
10238 If the mode of this shift is not the mode of the outer shift,
10239 we can't do this if either shift is a right shift or ROTATE.
10241 Finally, we can't do any of these if the mode is too wide
10242 unless the codes are the same.
10244 Handle the case where the shift codes are the same
10245 first. */
10248 {
10257 }
10268 /* To compute the mask to apply after the shift, shift the
10269 nonzero bits of the inner shift the same way the
10270 outer shift will. */
10273 result_mode);
10275 mask_rtx
10279 /* Give up if we can't compute an outer operation to use. */
10287 /* If the shifts are in the same direction, we add the
10288 counts. Otherwise, we subtract them. */
10292 else
10295 /* If COUNT is positive, the new shift is usually CODE,
10296 except for the two exceptions below, in which case it is
10297 FIRST_CODE. If the count is negative, FIRST_CODE should
10298 always be used */
10308 }
10310 /* If we have (A << B << C) for any shift, we can convert this to
10311 (A << C << B). This wins if A is a constant. Only try this if
10312 B is not a constant. */
10317 {
10324 }
10331 /* Make this fit the case below. */
10338 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10339 with C the size of VAROP - 1 and the shift is logical if
10340 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10341 we have an (le X 0) operation. If we have an arithmetic shift
10342 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10343 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10351 {
10354 const0_rtx);
10360 }
10362 /* If we have (shift (logical)), move the logical to the outside
10363 to allow it to possibly combine with another logical and the
10364 shift to combine with another shift. This also canonicalizes to
10365 what a ZERO_EXTRACT looks like. Also, some machines have
10366 (and (shift)) insns. */
10369 /* We can't do this if we have (ashiftrt (xor)) and the
10370 constant has its sign bit set in shift_mode with shift_mode
10371 wider than result_mode. */
10375 shift_mode))
10383 {
10386 }
10388 /* If we can't do that, try to simplify the shift in each arm of the
10389 logical expression, make a new logical expression, and apply
10390 the inverse distributive law. This also can't be done for
10391 (ashiftrt (xor)) where we've widened the shift and the constant
10392 changes the sign bit. */
10397 shift_mode)))
10398 {
10410 }
10414 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10415 says that the sign bit can be tested, FOO has mode MODE, C is
10416 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10417 that may be nonzero. */
10427 {
10431 }
10435 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10436 than the number of bits in the mode is equivalent to A. */
10440 {
10444 }
10446 /* NEG commutes with ASHIFT since it is multiplication. Move the
10447 NEG outside to allow shifts to combine. */
10451 {
10454 }
10458 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10459 is one less than the number of bits in the mode is
10460 equivalent to (xor A 1). */
10467 {
10471 }
10473 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10474 that might be nonzero in BAR are those being shifted out and those
10475 bits are known zero in FOO, we can replace the PLUS with FOO.
10476 Similarly in the other operand order. This code occurs when
10477 we are computing the size of a variable-size array. */
10484 {
10487 }
10495 result_mode)))
10496 {
10499 }
10501 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10511 {
10514 }
10516 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10517 signbit', and attempt to change the PLUS to an XOR and move it to
10518 the outer operation as is done above in the AND/IOR/XOR case
10519 leg for shift(logical). See details in logical handling above
10520 for reasoning in doing so. */
10531 {
10534 }
10539 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10540 with C the size of VAROP - 1 and the shift is logical if
10541 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10542 we have a (gt X 0) operation. If the shift is arithmetic with
10543 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10544 we have a (neg (gt X 0)) operation. */
10553 {
10556 const0_rtx);
10562 }
10566 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10567 if the truncate does not affect the value. */
10574 {
10577 varop_inner
10580 GEN_INT
10585 }
10590 }
10593 }
10598 /* We have now finished analyzing the shift. The result should be
10599 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10600 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10601 to the result of the shift. OUTER_CONST is the relevant constant,
10602 but we must turn off all bits turned off in the shift. */
10610 /* Make a SUBREG if necessary. If we can't make it, fail. */
10615 /* If we have an outer operation and we just made a shift, it is
10616 possible that we could have simplified the shift were it not
10617 for the outer operation. So try to do the simplification
10618 recursively. */
10622 else
10628 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10629 turn off all the bits that the shift would have turned off. */
10634 /* Do the remainder of the processing in RESULT_MODE. */
10637 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10638 operation. */
10643 {
10651 {
10652 /* This means that we have determined that the result is
10653 equivalent to a constant. This should be rare. */
10656 }
10659 else
10662 }
10665 }
10667 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10668 The result of the shift is RESULT_MODE. If we cannot simplify it,
10669 return X or, if it is NULL, synthesize the expression with
10670 simplify_gen_binary. Otherwise, return a simplified value.
10672 The shift is normally computed in the widest mode we find in VAROP, as
10673 long as it isn't a different number of words than RESULT_MODE. Exceptions
10674 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10676 static rtx
10679 {
10689 }
10691 \f
10692 /* Like recog, but we receive the address of a pointer to a new pattern.
10693 We try to match the rtx that the pointer points to.
10694 If that fails, we may try to modify or replace the pattern,
10695 storing the replacement into the same pointer object.
10697 Modifications include deletion or addition of CLOBBERs.
10699 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10700 the CLOBBERs are placed.
10702 The value is the final insn code from the pattern ultimately matched,
10703 or -1. */
10705 static int
10707 {
10709 rtx pat_without_clobbers;
10717 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10718 we use to indicate that something didn't match. If we find such a
10719 thing, force rejection. */
10733 {
10736 else
10739 }
10741 /* If it isn't, there is the possibility that we previously had an insn
10742 that clobbered some register as a side effect, but the combined
10743 insn doesn't need to do that. So try once more without the clobbers
10744 unless this represents an ASM insn. */
10748 {
10753 {
10756 pos++;
10757 }
10767 {
10770 else
10773 }
10774 }
10781 /* Recognize all noop sets, these will be killed by followup pass. */
10785 /* If we had any clobbers to add, make a new pattern than contains
10786 them. Then check to make sure that all of them are dead. */
10788 {
10798 else
10805 {
10810 {
10814 }
10815 }
10817 }
10821 {
10828 /* Allow targets to reject combined insn. */
10830 {
10833 dump_file);
10835 /* Callers expect recog_for_combine to strip
10836 clobbers from the pattern on failure. */
10841 }
10846 }
10852 }
10853 \f
10854 /* Like gen_lowpart_general but for use by combine. In combine it
10855 is not possible to create any new pseudoregs. However, it is
10856 safe to create invalid memory addresses, because combine will
10857 try to recognize them and all they will do is make the combine
10858 attempt fail.
10860 If for some reason this cannot do its job, an rtx
10861 (clobber (const_int 0)) is returned.
10862 An insn containing that will not be recognized. */
10864 static rtx
10866 {
10870 rtx result;
10875 /* We can only support MODE being wider than a word if X is a
10876 constant integer or has a mode the same size. */
10881 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10882 won't know what to do. So we will strip off the SUBREG here and
10883 process normally. */
10885 {
10888 /* For use in case we fall down into the address adjustments
10889 further below, we need to adjust the known mode and size of
10890 x; imode and isize, since we just adjusted x. */
10897 }
10905 {
10908 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10909 address. */
10914 /* If we want to refer to something bigger than the original memref,
10915 generate a paradoxical subreg instead. That will force a reload
10916 of the original memref X. */
10923 /* Adjust the address so that the address-after-the-data is
10924 unchanged. */
10929 }
10931 /* If X is a comparison operator, rewrite it in a new mode. This
10932 probably won't match, but may allow further simplifications. */
10936 /* If we couldn't simplify X any other way, just enclose it in a
10937 SUBREG. Normally, this SUBREG won't match, but some patterns may
10938 include an explicit SUBREG or we may simplify it further in combine. */
10939 else
10940 {
10942 rtx res;
10946 {
10951 }
10955 }
10957 fail:
10959 }
10960 \f
10961 /* Try to simplify a comparison between OP0 and a constant OP1,
10962 where CODE is the comparison code that will be tested, into a
10963 (CODE OP0 const0_rtx) form.
10965 The result is a possibly different comparison code to use.
10966 *POP1 may be updated. */
10968 static enum rtx_code
10971 {
10975 /* Get the constant we are comparing against and turn off all bits
10976 not on in our mode. */
10980 /* If we are comparing against a constant power of two and the value
10981 being compared can only have that single bit nonzero (e.g., it was
10982 `and'ed with that bit), we can replace this with a comparison
10983 with zero. */
10991 {
10994 }
10996 /* Similarly, if we are comparing a value known to be either -1 or
10997 0 with -1, change it to the opposite comparison against zero. */
11002 {
11005 }
11007 /* Do some canonicalizations based on the comparison code. We prefer
11008 comparisons against zero and then prefer equality comparisons.
11009 If we can reduce the size of a constant, we will do that too. */
11011 {
11013 /* < C is equivalent to <= (C - 1) */
11015 {
11018 /* ... fall through to LE case below. */
11019 }
11020 else
11024 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11026 {
11029 }
11031 /* If we are doing a <= 0 comparison on a value known to have
11032 a zero sign bit, we can replace this with == 0. */
11042 /* >= C is equivalent to > (C - 1). */
11044 {
11047 /* ... fall through to GT below. */
11048 }
11049 else
11053 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11055 {
11058 }
11060 /* If we are doing a > 0 comparison on a value known to have
11061 a zero sign bit, we can replace this with != 0. */
11071 /* < C is equivalent to <= (C - 1). */
11073 {
11076 /* ... fall through ... */
11077 }
11078 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11082 {
11086 }
11087 else
11091 /* unsigned <= 0 is equivalent to == 0 */
11094 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11098 {
11101 }
11105 /* >= C is equivalent to > (C - 1). */
11107 {
11110 /* ... fall through ... */
11111 }
11113 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11117 {
11121 }
11122 else
11126 /* unsigned > 0 is equivalent to != 0 */
11129 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11133 {
11136 }
11141 }
11145 }
11146 \f
11147 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11148 comparison code that will be tested.
11150 The result is a possibly different comparison code to use. *POP0 and
11151 *POP1 may be updated.
11153 It is possible that we might detect that a comparison is either always
11154 true or always false. However, we do not perform general constant
11155 folding in combine, so this knowledge isn't useful. Such tautologies
11156 should have been detected earlier. Hence we ignore all such cases. */
11158 static enum rtx_code
11160 {
11167 /* Try a few ways of applying the same transformation to both operands. */
11169 {
11170 #ifndef WORD_REGISTER_OPERATIONS
11171 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11172 so check specially. */
11187 - (GET_MODE_PRECISION
11189 {
11192 }
11193 #endif
11195 /* If both operands are the same constant shift, see if we can ignore the
11196 shift. We can if the shift is a rotate or if the bits shifted out of
11197 this shift are known to be zero for both inputs and if the type of
11198 comparison is compatible with the shift. */
11211 {
11224 else
11226 }
11228 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11229 SUBREGs are of the same mode, and, in both cases, the AND would
11230 be redundant if the comparison was done in the narrower mode,
11231 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11232 and the operand's possibly nonzero bits are 0xffffff01; in that case
11233 if we only care about QImode, we don't need the AND). This case
11234 occurs if the output mode of an scc insn is not SImode and
11235 STORE_FLAG_VALUE == 1 (e.g., the 386).
11237 Similarly, check for a case where the AND's are ZERO_EXTEND
11238 operations from some narrower mode even though a SUBREG is not
11239 present. */
11244 {
11261 {
11265 /* The resulting comparison is always unsigned since we masked
11266 off the original sign bit. */
11270 }
11277 {
11283 }
11287 }
11289 /* If both operands are NOT, we can strip off the outer operation
11290 and adjust the comparison code for swapped operands; similarly for
11291 NEG, except that this must be an equality comparison. */
11297 else
11299 }
11301 /* If the first operand is a constant, swap the operands and adjust the
11302 comparison code appropriately, but don't do this if the second operand
11303 is already a constant integer. */
11305 {
11308 }
11310 /* We now enter a loop during which we will try to simplify the comparison.
11311 For the most part, we only are concerned with comparisons with zero,
11312 but some things may really be comparisons with zero but not start
11313 out looking that way. */
11316 {
11323 HOST_WIDE_INT const_op;
11325 /* We only want to handle integral modes. This catches VOIDmode,
11326 CCmode, and the floating-point modes. An exception is that we
11327 can handle VOIDmode if OP0 is a COMPARE or a comparison
11328 operation. */
11335 /* Try to simplify the compare to constant, possibly changing the
11336 comparison op, and/or changing op1 to zero. */
11340 /* Compute some predicates to simplify code below. */
11347 /* If this is a sign bit comparison and we can do arithmetic in
11348 MODE, say that we will only be needing the sign bit of OP0. */
11355 /* Now try cases based on the opcode of OP0. If none of the cases
11356 does a "continue", we exit this loop immediately after the
11357 switch. */
11360 {
11362 /* If we are extracting a single bit from a variable position in
11363 a constant that has only a single bit set and are comparing it
11364 with zero, we can convert this into an equality comparison
11365 between the position and the location of the single bit. */
11366 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11367 have already reduced the shift count modulo the word size. */
11373 {
11381 /* Result is nonzero iff shift count is equal to I. */
11384 }
11386 /* ... fall through ... */
11391 {
11394 }
11398 /* If testing for equality, we can take the NOT of the constant. */
11401 {
11405 }
11407 /* If just looking at the sign bit, reverse the sense of the
11408 comparison. */
11410 {
11414 }
11418 /* If testing for equality, we can take the NEG of the constant. */
11421 {
11425 }
11427 /* The remaining cases only apply to comparisons with zero. */
11431 /* When X is ABS or is known positive,
11432 (neg X) is < 0 if and only if X != 0. */
11440 {
11444 }
11446 /* If we have NEG of something whose two high-order bits are the
11447 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11449 {
11453 }
11457 /* If we are testing equality and our count is a constant, we
11458 can perform the inverse operation on our RHS. */
11462 {
11466 }
11468 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11469 a particular bit. Convert it to an AND of a constant of that
11470 bit. This will be converted into a ZERO_EXTRACT. */
11474 {
11481 }
11483 /* Fall through. */
11486 /* ABS is ignorable inside an equality comparison with zero. */
11488 {
11491 }
11495 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11496 (compare FOO CONST) if CONST fits in FOO's mode and we
11497 are either testing inequality or have an unsigned
11498 comparison with ZERO_EXTEND or a signed comparison with
11499 SIGN_EXTEND. But don't do it if we don't have a compare
11500 insn of the given mode, since we'd have to revert it
11501 later on, and then we wouldn't know whether to sign- or
11502 zero-extend. */
11505 && ! unsigned_comparison_p
11509 {
11512 }
11516 /* Check for the case where we are comparing A - C1 with C2, that is
11518 (subreg:MODE (plus (A) (-C1))) op (C2)
11520 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11521 comparison in the wider mode. One of the following two conditions
11522 must be true in order for this to be valid:
11524 1. The mode extension results in the same bit pattern being added
11525 on both sides and the comparison is equality or unsigned. As
11526 C2 has been truncated to fit in MODE, the pattern can only be
11527 all 0s or all 1s.
11529 2. The mode extension results in the sign bit being copied on
11530 each side.
11532 The difficulty here is that we have predicates for A but not for
11533 (A - C1) so we need to check that C1 is within proper bounds so
11534 as to perturbate A as little as possible. */
11541 {
11550 /* (A - C1) zero-extends if it is positive and sign-extends
11551 if it is negative, C2 both zero- and sign-extends. */
11555 /* (A - C1) sign-extends if it is positive and 1-extends
11556 if it is negative, C2 both sign- and 1-extends. */
11563 /* (A - C1) always sign-extends, like C2. */
11567 {
11570 }
11571 }
11573 /* If the inner mode is narrower and we are extracting the low part,
11574 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11578 else
11581 /* ... fall through ... */
11591 {
11594 }
11598 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11599 this for equality comparisons due to pathological cases involving
11600 overflows. */
11604 {
11608 }
11610 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11613 {
11617 }
11621 /* We used to optimize signed comparisons against zero, but that
11622 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11623 arrive here as equality comparisons, or (GEU, LTU) are
11624 optimized away. No need to special-case them. */
11626 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11627 (eq B (minus A C)), whichever simplifies. We can only do
11628 this for equality comparisons due to pathological cases involving
11629 overflows. */
11633 {
11637 }
11642 {
11646 }
11648 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11649 of bits in X minus 1, is one iff X > 0. */
11654 {
11658 }
11662 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11663 if C is zero or B is a constant. */
11667 {
11671 }
11679 /* We can't do anything if OP0 is a condition code value, rather
11680 than an actual data value. */
11686 /* Get the two operands being compared. */
11689 else
11692 /* Check for the cases where we simply want the result of the
11693 earlier test or the opposite of that result. */
11697 {
11701 else
11705 {
11710 }
11711 }
11715 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11716 iff X <= 0. */
11720 {
11724 }
11728 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11729 will be converted to a ZERO_EXTRACT later. */
11733 {
11738 }
11740 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11741 zero and X is a comparison and C1 and C2 describe only bits set
11742 in STORE_FLAG_VALUE, we can compare with X. */
11750 {
11757 {
11760 }
11761 }
11763 /* If we are doing an equality comparison of an AND of a bit equal
11764 to the sign bit, replace this with a LT or GE comparison of
11765 the underlying value. */
11772 {
11776 }
11778 /* If this AND operation is really a ZERO_EXTEND from a narrower
11779 mode, the constant fits within that mode, and this is either an
11780 equality or unsigned comparison, try to do this comparison in
11781 the narrower mode.
11783 Note that in:
11785 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11786 -> (ne:DI (reg:SI 4) (const_int 0))
11788 unless TRULY_NOOP_TRUNCATION allows it or the register is
11789 known to hold a value of the required mode the
11790 transformation is invalid. */
11801 {
11804 }
11806 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11807 fits in both M1 and M2 and the SUBREG is either paradoxical
11808 or represents the low part, permute the SUBREG and the AND
11809 and try again. */
11811 {
11814 /* Require an integral mode, to avoid creating something like
11815 (AND:SF ...). */
11817 /* It is unsafe to commute the AND into the SUBREG if the
11818 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11819 not defined. As originally written the upper bits
11820 have a defined value due to the AND operation.
11821 However, if we commute the AND inside the SUBREG then
11822 they no longer have defined values and the meaning of
11823 the code has been changed. */
11825 #ifdef WORD_REGISTER_OPERATIONS
11828 #endif
11838 {
11844 }
11845 }
11847 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11851 {
11856 }
11858 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11859 (eq (and (lshiftrt X) 1) 0).
11860 Also handle the case where (not X) is expressed using xor. */
11864 {
11876 {
11877 op0
11882 }
11883 }
11887 /* If we have (compare (ashift FOO N) (const_int C)) and
11888 the high order N bits of FOO (N+1 if an inequality comparison)
11889 are known to be zero, we can do this by comparing FOO with C
11890 shifted right N bits so long as the low-order N bits of C are
11891 zero. */
11903 {
11904 /* We must perform a logical shift, not an arithmetic one,
11905 as we want the top N bits of C to be zero. */
11912 }
11914 /* If we are doing a sign bit comparison, it means we are testing
11915 a particular bit. Convert it to the appropriate AND. */
11918 {
11925 }
11927 /* If this an equality comparison with zero and we are shifting
11928 the low bit to the sign bit, we can convert this to an AND of the
11929 low-order bit. */
11933 {
11936 }
11940 /* If this is an equality comparison with zero, we can do this
11941 as a logical shift, which might be much simpler. */
11944 {
11949 }
11951 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11952 do the comparison in a narrower mode. */
11962 {
11965 }
11967 /* Likewise if OP0 is a PLUS of a sign extension with a
11968 constant, which is usually represented with the PLUS
11969 between the shifts. */
11981 {
11989 new_const);
11991 }
11993 /* ... fall through ... */
11995 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11996 the low order N bits of FOO are known to be zero, we can do this
11997 by comparing FOO with C shifted left N bits so long as no
11998 overflow occurs. Even if the low order N bits of FOO aren't known
11999 to be zero, if the comparison is >= or < we can use the same
12000 optimization and for > or <= by setting all the low
12001 order N bits in the comparison constant. */
12012 {
12013 unsigned HOST_WIDE_INT low_bits
12018 {
12019 /* If the shift was logical, then we must make the condition
12020 unsigned. */
12028 const_op
12033 }
12034 }
12036 /* If we are using this shift to extract just the sign bit, we
12037 can replace this with an LT or GE comparison. */
12042 {
12046 }
12051 }
12054 }
12056 /* Now make any compound operations involved in this comparison. Then,
12057 check for an outmost SUBREG on OP0 that is not doing anything or is
12058 paradoxical. The latter transformation must only be performed when
12059 it is known that the "extra" bits will be the same in op0 and op1 or
12060 that they don't matter. There are three cases to consider:
12062 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12063 care bits and we can assume they have any convenient value. So
12064 making the transformation is safe.
12066 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12067 In this case the upper bits of op0 are undefined. We should not make
12068 the simplification in that case as we do not know the contents of
12069 those bits.
12071 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12072 UNKNOWN. In that case we know those bits are zeros or ones. We must
12073 also be sure that they are the same as the upper bits of op1.
12075 We can never remove a SUBREG for a non-equality comparison because
12076 the sign bit is in a different place in the underlying object. */
12085 {
12087 {
12088 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12089 implemented. */
12091 {
12094 }
12095 }
12101 {
12107 }
12108 }
12110 /* We now do the opposite procedure: Some machines don't have compare
12111 insns in all modes. If OP0's mode is an integer mode smaller than a
12112 word and we can't do a compare in that mode, see if there is a larger
12113 mode for which we can do the compare. There are a number of cases in
12114 which we can use the wider mode. */
12124 {
12127 /* If this is a test for negative, we can make an explicit
12128 test of the sign bit. Test this first so we can use
12129 a paradoxical subreg to extend OP0. */
12133 {
12134 unsigned HOST_WIDE_INT sign
12141 }
12143 /* If the only nonzero bits in OP0 and OP1 are those in the
12144 narrower mode and this is an equality or unsigned comparison,
12145 we can use the wider mode. Similarly for sign-extended
12146 values, in which case it is true for all comparisons. */
12163 {
12164 /* If OP0 is an AND and we don't have an AND in MODE either,
12165 make a new AND in the proper mode. */
12173 else
12174 {
12176 {
12179 }
12180 else
12181 {
12184 }
12186 }
12187 }
12188 }
12190 /* We may have changed the comparison operands. Re-canonicalize. */
12192 {
12195 }
12197 /* If this machine only supports a subset of valid comparisons, see if we
12198 can convert an unsupported one into a supported one. */
12205 }
12206 \f
12207 /* Utility function for record_value_for_reg. Count number of
12208 rtxs in X. */
12209 static int
12211 {
12218 {
12238 }
12249 }
12250 \f
12251 /* Utility function for following routine. Called when X is part of a value
12252 being stored into last_set_value. Sets last_set_table_tick
12253 for each register mentioned. Similar to mention_regs in cse.c */
12255 static void
12257 {
12263 {
12269 {
12272 }
12275 }
12279 {
12280 /* Check for identical subexpressions. If x contains
12281 identical subexpression we only have to traverse one of
12282 them. */
12284 {
12285 /* Note that at this point x1 has already been
12286 processed. */
12290 /* If x0 and x1 are identical then there is no need to
12291 process x0. */
12295 /* If x0 is identical to a subexpression of x1 then while
12296 processing x1, x0 has already been processed. Thus we
12297 are done with x. */
12302 /* If x1 is identical to a subexpression of x0 then we
12303 still have to process the rest of x0. */
12306 {
12309 }
12310 }
12313 }
12317 }
12319 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12320 are saying that the register is clobbered and we no longer know its
12321 value. If INSN is zero, don't update reg_stat[].last_set; this is
12322 only permitted with VALUE also zero and is used to invalidate the
12323 register. */
12325 static void
12327 {
12333 /* If VALUE contains REG and we have a previous value for REG, substitute
12334 the previous value. */
12336 {
12337 rtx tem;
12339 /* Set things up so get_last_value is allowed to see anything set up to
12340 our insn. */
12344 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12345 it isn't going to be useful and will take a lot of time to process,
12346 so just use the CLOBBER. */
12349 {
12355 {
12356 /* If there are two or more occurrences of REG in VALUE,
12357 prevent the value from growing too much. */
12360 }
12363 }
12364 }
12366 /* For each register modified, show we don't know its value, that
12367 we don't know about its bitwise content, that its value has been
12368 updated, and that we don't know the location of the death of the
12369 register. */
12371 {
12383 }
12385 /* Mark registers that are being referenced in this value. */
12389 /* Now update the status of each register being set.
12390 If someone is using this register in this block, set this register
12391 to invalid since we will get confused between the two lives in this
12392 basic block. This makes using this register always invalid. In cse, we
12393 scan the table to invalidate all entries using this register, but this
12394 is too much work for us. */
12397 {
12403 else
12405 }
12407 /* The value being assigned might refer to X (like in "x++;"). In that
12408 case, we must replace it with (clobber (const_int 0)) to prevent
12409 infinite loops. */
12412 {
12416 }
12418 /* For the main register being modified, update the value, the mode, the
12419 nonzero bits, and the number of sign bit copies. */
12424 {
12432 rsp->last_set_sign_bit_copies
12434 }
12435 }
12437 /* Called via note_stores from record_dead_and_set_regs to handle one
12438 SET or CLOBBER in an insn. DATA is the instruction in which the
12439 set is occurring. */
12441 static void
12443 {
12450 {
12454 }
12457 {
12458 /* If we are setting the whole register, we know its value. Otherwise
12459 show that we don't know the value. We can handle SUBREG in
12460 some cases. */
12471 else
12473 }
12475 /* Ignore pushes, they clobber nothing. */
12478 }
12480 /* Update the records of when each REG was most recently set or killed
12481 for the things done by INSN. This is the last thing done in processing
12482 INSN in the combiner loop.
12484 We update reg_stat[], in particular fields last_set, last_set_value,
12485 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12486 last_death, and also the similar information mem_last_set (which insn
12487 most recently modified memory) and last_call_luid (which insn was the
12488 most recent subroutine call). */
12490 static void
12492 {
12493 rtx link;
12497 {
12500 {
12505 {
12510 }
12511 }
12514 }
12517 {
12518 hard_reg_set_iterator hrsi;
12520 {
12532 }
12536 /* We can't combine into a call pattern. Remember, though, that
12537 the return value register is set at this LUID. We could
12538 still replace a register with the return value from the
12539 wrong subroutine call! */
12541 }
12542 else
12544 }
12546 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12547 register present in the SUBREG, so for each such SUBREG go back and
12548 adjust nonzero and sign bit information of the registers that are
12549 known to have some zero/sign bits set.
12551 This is needed because when combine blows the SUBREGs away, the
12552 information on zero/sign bits is lost and further combines can be
12553 missed because of that. */
12555 static void
12557 {
12559 rtx set;
12567 {
12576 {
12579 }
12583 {
12586 }
12589 {
12592 }
12593 else
12595 }
12596 }
12598 /* Check if X, a register, is known to contain a value already
12599 truncated to MODE. In this case we can use a subreg to refer to
12600 the truncated value even though in the generic case we would need
12601 an explicit truncation. */
12603 static bool
12605 {
12617 }
12619 /* If X is a hard reg or a subreg record the mode that the register is
12620 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12621 to turn a truncate into a subreg using this information. Return true
12622 if traversing X is complete. */
12624 static bool
12626 {
12627 machine_mode truncated_mode;
12631 {
12642 }
12643 /* ??? For hard-regs we now record everything. We might be able to
12644 optimize this using last_set_mode. */
12647 else
12655 {
12658 }
12661 }
12663 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12664 the modes they are used in. This can help truning TRUNCATEs into
12665 SUBREGs. */
12667 static void
12669 {
12674 }
12676 /* Scan X for promoted SUBREGs. For each one found,
12677 note what it implies to the registers used in it. */
12679 static void
12681 {
12686 else
12687 {
12693 {
12703 }
12704 }
12705 }
12706 \f
12707 /* Verify that all the registers and memory references mentioned in *LOC are
12708 still valid. *LOC was part of a value set in INSN when label_tick was
12709 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12710 the invalid references with (clobber (const_int 0)) and return 1. This
12711 replacement is useful because we often can get useful information about
12712 the form of a value (e.g., if it was produced by a shift that always
12713 produces -1 or 0) even though we don't know exactly what registers it
12714 was produced from. */
12716 static int
12718 {
12725 {
12731 {
12734 /* If this is a pseudo-register that was only set once and not
12735 live at the beginning of the function, it is always valid. */
12738 && (!REGNO_REG_SET_P
12740 regno)))
12742 {
12746 }
12747 }
12750 }
12751 /* If this is a memory reference, make sure that there were no stores after
12752 it that might have clobbered the value. We don't have alias info, so we
12753 assume any store invalidates it. Moreover, we only have local UIDs, so
12754 we also assume that there were stores in the intervening basic blocks. */
12757 {
12761 }
12764 {
12766 {
12767 /* Check for identical subexpressions. If x contains
12768 identical subexpression we only have to traverse one of
12769 them. */
12771 {
12772 /* Note that at this point x0 has already been checked
12773 and found valid. */
12777 /* If x0 and x1 are identical then x is also valid. */
12781 /* If x1 is identical to a subexpression of x0 then
12782 while checking x0, x1 has already been checked. Thus
12783 it is valid and so as x. */
12788 /* If x0 is identical to a subexpression of x1 then x is
12789 valid iff the rest of x1 is valid. */
12792 return
12796 }
12801 }
12807 }
12809 /* If we haven't found a reason for it to be invalid, it is valid. */
12811 }
12813 /* Get the last value assigned to X, if known. Some registers
12814 in the value may be replaced with (clobber (const_int 0)) if their value
12815 is known longer known reliably. */
12817 static rtx
12819 {
12821 rtx value;
12824 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12825 then convert it to the desired mode. If this is a paradoxical SUBREG,
12826 we cannot predict what values the "extra" bits might have. */
12840 /* If we don't have a value, or if it isn't for this basic block and
12841 it's either a hard register, set more than once, or it's a live
12842 at the beginning of the function, return 0.
12844 Because if it's not live at the beginning of the function then the reg
12845 is always set before being used (is never used without being set).
12846 And, if it's set only once, and it's always set before use, then all
12847 uses must have the same last value, even if it's not from this basic
12848 block. */
12854 || REGNO_REG_SET_P
12858 /* If the value was set in a later insn than the ones we are processing,
12859 we can't use it even if the register was only set once. */
12864 /* If the value has all its registers valid, return it. */
12868 /* Otherwise, make a copy and replace any invalid register with
12869 (clobber (const_int 0)). If that fails for some reason, return 0. */
12876 }
12877 \f
12878 /* Return nonzero if expression X refers to a REG or to memory
12879 that is set in an instruction more recent than FROM_LUID. */
12881 static int
12883 {
12889 {
12893 #ifdef PUSH_ROUNDING
12894 /* Don't allow uses of the stack pointer to be moved,
12895 because we don't know whether the move crosses a push insn. */
12898 #endif
12900 {
12906 }
12908 }
12916 {
12918 {
12923 }
12927 }
12929 }
12930 \f
12931 /* Define three variables used for communication between the following
12932 routines. */
12937 /* Function called via note_stores from reg_dead_at_p.
12939 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12940 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12942 static void
12944 {
12954 }
12956 /* Return nonzero if REG is known to be dead at INSN.
12958 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12959 referencing REG, it is dead. If we hit a SET referencing REG, it is
12960 live. Otherwise, see if it is live or dead at the start of the basic
12961 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12962 must be assumed to be always live. */
12964 static int
12966 {
12967 basic_block block;
12970 /* Set variables for reg_dead_at_p_1. */
12976 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12977 we allow the machine description to decide whether use-and-clobber
12978 patterns are OK. */
12980 {
12984 }
12986 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12987 beginning of basic block. */
12990 {
12992 {
13002 }
13008 }
13010 /* Look at live-in sets for the basic block that we were in. */
13016 }
13017 \f
13018 /* Note hard registers in X that are used. */
13020 static void
13022 {
13028 {
13032 CASE_CONST_ANY:
13037 #ifdef HAVE_cc0
13038 /* CC0 must die in the insn after it is set, so we don't need to take
13039 special note of it here. */
13041 #endif
13045 /* If we are clobbering a MEM, mark any hard registers inside the
13046 address as used. */
13053 /* A hard reg in a wide mode may really be multiple registers.
13054 If so, mark all of them just like the first. */
13056 {
13057 /* None of this applies to the stack, frame or arg pointers. */
13059 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13061 #endif
13062 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13064 #endif
13069 }
13073 {
13074 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13075 the address. */
13087 }
13092 }
13094 /* Recursively scan the operands of this expression. */
13096 {
13100 {
13104 {
13109 }
13110 }
13111 }
13112 }
13113 \f
13114 /* Remove register number REGNO from the dead registers list of INSN.
13116 Return the note used to record the death, if there was one. */
13118 rtx
13120 {
13127 }
13129 /* For each register (hardware or pseudo) used within expression X, if its
13130 death is in an instruction with luid between FROM_LUID (inclusive) and
13131 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13132 list headed by PNOTES.
13134 That said, don't move registers killed by maybe_kill_insn.
13136 This is done when X is being merged by combination into TO_INSN. These
13137 notes will then be distributed as needed. */
13139 static void
13142 {
13148 {
13152 /* Don't move the register if it gets killed in between from and to. */
13161 {
13164 /* It is possible for the call above to return 0. This can occur
13165 when last_death points to I2 or I1 that we combined with.
13166 In that case make a new note.
13168 We must also check for the case where X is a hard register
13169 and NOTE is a death note for a range of hard registers
13170 including X. In that case, we must put REG_DEAD notes for
13171 the remaining registers in place of NOTE. */
13176 {
13185 }
13187 /* If we didn't find any note, or if we found a REG_DEAD note that
13188 covers only part of the given reg, and we have a multi-reg hard
13189 register, then to be safe we must check for REG_DEAD notes
13190 for each register other than the first. They could have
13191 their own REG_DEAD notes lying around. */
13198 {
13205 else
13211 }
13214 {
13217 }
13218 else
13220 }
13223 }
13226 {
13231 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13232 that accesses one word of a multi-word item, some
13233 piece of everything register in the expression is used by
13234 this insn, so remove any old death. */
13235 /* ??? So why do we test for equality of the sizes? */
13244 {
13247 }
13249 /* If this is some other SUBREG, we know it replaces the entire
13250 value, so use that as the destination. */
13254 /* If this is a MEM, adjust deaths of anything used in the address.
13255 For a REG (the only other possibility), the entire value is
13256 being replaced so the old value is not used in this insn. */
13262 }
13271 {
13273 {
13278 }
13281 }
13282 }
13283 \f
13284 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13285 pattern of an insn. X must be a REG. */
13287 static int
13289 {
13293 {
13295 rtx target;
13302 else
13319 }
13327 }
13328 \f
13329 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13330 as appropriate. I3 and I2 are the insns resulting from the combination
13331 insns including FROM (I2 may be zero).
13333 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13334 not need REG_DEAD notes because they are being substituted for. This
13335 saves searching in the most common cases.
13337 Each note in the list is either ignored or placed on some insns, depending
13338 on the type of note. */
13340 static void
13343 {
13345 rtx tem_note;
13349 {
13354 {
13357 /* Doesn't matter much where we put this, as long as it's somewhere.
13358 It is preferable to keep these notes on branches, which is most
13359 likely to be i3. */
13366 else
13367 {
13370 }
13374 /* These notes must remain with the call or trapping instruction. */
13379 else
13380 {
13386 /* ??? Otherwise assume we've combined things such that we
13387 can now prove that the instructions can't trap. Drop the
13388 note in this case. */
13389 }
13393 /* ??? How to distribute between i3-i1. Assume i3 contains the
13394 entire adjustment. Assert i3 contains at least some adjust. */
13396 {
13398 /* fixup_args_size_notes looks at REG_NORETURN note,
13399 so ensure the note is placed there first. */
13401 {
13405 {
13411 }
13412 }
13414 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13415 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13418 && !ACCUMULATE_OUTGOING_ARGS
13420 }
13427 /* These notes must remain with the call. It should not be
13428 possible for both I2 and I3 to be a call. */
13431 else
13432 {
13435 }
13439 /* Any clobbers for i3 may still exist, and so we must process
13440 REG_UNUSED notes from that insn.
13442 Any clobbers from i2 or i1 can only exist if they were added by
13443 recog_for_combine. In that case, recog_for_combine created the
13444 necessary REG_UNUSED notes. Trying to keep any original
13445 REG_UNUSED notes from these insns can cause incorrect output
13446 if it is for the same register as the original i3 dest.
13447 In that case, we will notice that the register is set in i3,
13448 and then add a REG_UNUSED note for the destination of i3, which
13449 is wrong. However, it is possible to have REG_UNUSED notes from
13450 i2 or i1 for register which were both used and clobbered, so
13451 we keep notes from i2 or i1 if they will turn into REG_DEAD
13452 notes. */
13454 /* If this register is set or clobbered in I3, put the note there
13455 unless there is one already. */
13457 {
13465 }
13466 /* Otherwise, if this register is used by I3, then this register
13467 now dies here, so we must put a REG_DEAD note here unless there
13468 is one already. */
13474 {
13477 }
13483 /* These notes say something about results of an insn. We can
13484 only support them if they used to be on I3 in which case they
13485 remain on I3. Otherwise they are ignored.
13487 If the note refers to an expression that is not a constant, we
13488 must also ignore the note since we cannot tell whether the
13489 equivalence is still true. It might be possible to do
13490 slightly better than this (we only have a problem if I2DEST
13491 or I1DEST is present in the expression), but it doesn't
13492 seem worth the trouble. */
13500 /* These notes say something about how a register is used. They must
13501 be present on any use of the register in I2 or I3. */
13506 {
13509 else
13511 }
13516 /* This can show up in several ways -- either directly in the
13517 pattern, or hidden off in the constant pool with (or without?)
13518 a REG_EQUAL note. */
13519 /* ??? Ignore the without-reg_equal-note problem for now. */
13531 {
13534 else
13536 }
13538 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13539 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13540 there. */
13545 {
13552 }
13558 {
13566 }
13570 /* This note says something about the value of a register prior
13571 to the execution of an insn. It is too much trouble to see
13572 if the note is still correct in all situations. It is better
13573 to simply delete it. */
13577 /* If we replaced the right hand side of FROM_INSN with a
13578 REG_EQUAL note, the original use of the dying register
13579 will not have been combined into I3 and I2. In such cases,
13580 FROM_INSN is guaranteed to be the first of the combined
13581 instructions, so we simply need to search back before
13582 FROM_INSN for the previous use or set of this register,
13583 then alter the notes there appropriately.
13585 If the register is used as an input in I3, it dies there.
13586 Similarly for I2, if it is nonzero and adjacent to I3.
13588 If the register is not used as an input in either I3 or I2
13589 and it is not one of the registers we were supposed to eliminate,
13590 there are two possibilities. We might have a non-adjacent I2
13591 or we might have somehow eliminated an additional register
13592 from a computation. For example, we might have had A & B where
13593 we discover that B will always be zero. In this case we will
13594 eliminate the reference to A.
13596 In both cases, we must search to see if we can find a previous
13597 use of A and put the death note there. */
13603 else
13604 {
13615 && !(i2mod
13617 i2mod_old_rhs)))
13622 }
13625 {
13629 {
13631 {
13635 }
13637 /* If the register is being set at TEM_INSN, see if that is all
13638 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13639 into a REG_UNUSED note instead. Don't delete sets to
13640 global register vars. */
13644 {
13647 #ifdef HAVE_cc0
13649 #endif
13657 ;
13659 /* Verify that it was the set, and not a clobber that
13660 modified the register.
13662 CC0 targets must be careful to maintain setter/user
13663 pairs. If we cannot delete the setter due to side
13664 effects, mark the user with an UNUSED note instead
13665 of deleting it. */
13669 #ifdef HAVE_cc0
13673 #endif
13674 )
13675 {
13676 /* Move the notes and links of TEM_INSN elsewhere.
13677 This might delete other dead insns recursively.
13678 First set the pattern to something that won't use
13679 any register. */
13693 #ifdef HAVE_cc0
13694 /* Delete the setter too. */
13696 {
13709 }
13710 #endif
13711 }
13712 else
13713 {
13716 /* If there isn't already a REG_UNUSED note, put one
13717 here. Do not place a REG_DEAD note, even if
13718 the register is also used here; that would not
13719 match the algorithm used in lifetime analysis
13720 and can cause the consistency check in the
13721 scheduler to fail. */
13726 }
13727 }
13731 {
13734 /* If we are doing a 3->2 combination, and we have a
13735 register which formerly died in i3 and was not used
13736 by i2, which now no longer dies in i3 and is used in
13737 i2 but does not die in i2, and place is between i2
13738 and i3, then we may need to move a link from place to
13739 i2. */
13741 && from_insn
13744 {
13748 }
13750 }
13754 }
13756 }
13758 /* If the register is set or already dead at PLACE, we needn't do
13759 anything with this note if it is still a REG_DEAD note.
13760 We check here if it is set at all, not if is it totally replaced,
13761 which is what `dead_or_set_p' checks, so also check for it being
13762 set partially. */
13765 {
13771 {
13772 /* Unless the register previously died in PLACE, clear
13773 last_death. [I no longer understand why this is
13774 being done.] */
13778 }
13779 else
13782 /* If this is a death note for a hard reg that is occupying
13783 multiple registers, ensure that we are still using all
13784 parts of the object. If we find a piece of the object
13785 that is unused, we must arrange for an appropriate REG_DEAD
13786 note to be added for it. However, we can't just emit a USE
13787 and tag the note to it, since the register might actually
13788 be dead; so we recourse, and the recursive call then finds
13789 the previous insn that used this register. */
13793 {
13802 {
13805 }
13808 {
13809 /* Put only REG_DEAD notes for pieces that are
13810 not already dead or set. */
13814 {
13821 {
13823 NULL_RTX);
13827 NULL_RTX);
13828 }
13834 {
13836 {
13840 }
13844 {
13847 }
13848 }
13849 }
13852 }
13853 }
13854 }
13858 /* Any other notes should not be present at this point in the
13859 compilation. */
13861 }
13864 {
13867 }
13871 }
13872 }
13873 \f
13874 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13875 I3, I2, and I1 to new locations. This is also called to add a link
13876 pointing at I3 when I3's destination is changed. */
13878 static void
13880 {
13884 {
13891 /* If the insn that this link points to is a NOTE, ignore it. */
13900 {
13903 {
13919 }
13922 }
13923 else
13933 /* A LOG_LINK is defined as being placed on the first insn that uses
13934 a register and points to the insn that sets the register. Start
13935 searching at the next insn after the target of the link and stop
13936 when we reach a set of the register or the end of the basic block.
13938 Note that this correctly handles the link that used to point from
13939 I3 to I2. Also note that not much searching is typically done here
13940 since most links don't point very far away. */
13949 {
13953 }
13956 {
13959 }
13963 /* If we found a place to put the link, place it there unless there
13964 is already a link to the same insn as LINK at that point. */
13967 {
13975 {
13979 /* Set added_links_insn to the earliest insn we added a
13980 link to. */
13984 }
13985 }
13986 }
13987 }
13988 \f
13989 /* Check for any register or memory mentioned in EQUIV that is not
13990 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13991 of EXPR where some registers may have been replaced by constants. */
13993 static bool
13995 {
13998 {
14003 }
14005 }
14006 \f
14007 DEBUG_FUNCTION void
14009 {
14010 fprintf
14012 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14014 }
14016 void
14018 {
14019 fprintf
14021 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14023 }
14024 \f
14025 /* Try combining insns through substitution. */
14026 static unsigned int
14028 {
14037 rebuild_jump_labels_after_combine
14040 /* Combining insns may have turned an indirect jump into a
14041 direct jump. Rebuild the JUMP_LABEL fields of jumping
14042 instructions. */
14044 {
14049 }
14053 }
14058 {
14068 };
14071 {
14075 {}
14077 /* opt_pass methods: */
14080 {
14082 }
14088 rtl_opt_pass *
14090 {
14092 }