1 ;; Pipeline description for Freescale PowerPC e6500 core.
2 ;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
24 (define_automaton "e6500_most,e6500_long,e6500_vec")
25 (define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
28 (define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
31 (define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
33 ;; Non-pipelined division.
34 (define_cpu_unit "e6500_cfx_div" "e6500_long")
37 (define_cpu_unit "e6500_lsu" "e6500_most")
40 (define_cpu_unit "e6500_fpu" "e6500_long")
43 (define_cpu_unit "e6500_bu" "e6500_most")
46 (define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
48 ;; The following units are used to make the automata deterministic.
49 (define_cpu_unit "present_e6500_decode_0" "e6500_most")
50 (define_cpu_unit "present_e6500_sfx_0" "e6500_most")
51 (presence_set "present_e6500_decode_0" "e6500_decode_0")
52 (presence_set "present_e6500_sfx_0" "e6500_sfx_0")
54 ;; Some useful abbreviations.
55 (define_reservation "e6500_decode"
56 "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
57 (define_reservation "e6500_sfx"
58 "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
61 (define_insn_reservation "e6500_sfx" 1
62 (and (eq_attr "type" "integer,insert,delayed_compare,\
64 (eq_attr "cpu" "ppce6500"))
65 "e6500_decode,e6500_sfx")
67 (define_insn_reservation "e6500_sfx2" 2
68 (and (eq_attr "type" "cmp,compare,fast_compare,trap")
69 (eq_attr "cpu" "ppce6500"))
70 "e6500_decode,e6500_sfx")
72 (define_insn_reservation "e6500_delayed" 2
73 (and (eq_attr "type" "var_shift_rotate,var_delayed_compare")
74 (eq_attr "cpu" "ppce6500"))
75 "e6500_decode,e6500_sfx*2")
77 (define_insn_reservation "e6500_two" 2
78 (and (eq_attr "type" "two")
79 (eq_attr "cpu" "ppce6500"))
80 "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
82 (define_insn_reservation "e6500_three" 3
83 (and (eq_attr "type" "three")
84 (eq_attr "cpu" "ppce6500"))
85 "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
88 (define_insn_reservation "e6500_mfcr" 4
89 (and (eq_attr "type" "mfcr")
90 (eq_attr "cpu" "ppce6500"))
91 "e6500_decode,e6500_sfx_0*4")
94 (define_insn_reservation "e6500_mtcrf" 1
95 (and (eq_attr "type" "mtcr")
96 (eq_attr "cpu" "ppce6500"))
97 "e6500_decode,e6500_sfx_0")
100 (define_insn_reservation "e6500_mtjmpr" 1
101 (and (eq_attr "type" "mtjmpr,mfjmpr")
102 (eq_attr "cpu" "ppce6500"))
103 "e6500_decode,e6500_sfx")
106 (define_insn_reservation "e6500_multiply" 4
107 (and (eq_attr "type" "mul")
109 (eq_attr "size" "32")
110 (eq_attr "cpu" "ppce6500"))
111 "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
113 (define_insn_reservation "e6500_multiply_i" 5
114 (and (eq_attr "type" "mul")
115 (ior (eq_attr "dot" "yes")
116 (eq_attr "size" "8,16"))
117 (eq_attr "cpu" "ppce6500"))
118 "e6500_decode,e6500_cfx_stage0,\
119 e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
122 (define_insn_reservation "e6500_divide" 16
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "ppce6500"))
125 "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
128 (define_insn_reservation "e6500_divide_d" 26
129 (and (eq_attr "type" "ldiv")
130 (eq_attr "cpu" "ppce6500"))
131 "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
135 (define_insn_reservation "e6500_load" 3
136 (and (eq_attr "type" "load,load_l,sync")
137 (eq_attr "cpu" "ppce6500"))
138 "e6500_decode,e6500_lsu")
140 (define_insn_reservation "e6500_fpload" 4
141 (and (eq_attr "type" "fpload")
142 (eq_attr "cpu" "ppce6500"))
143 "e6500_decode,e6500_lsu")
145 (define_insn_reservation "e6500_vecload" 4
146 (and (eq_attr "type" "vecload")
147 (eq_attr "cpu" "ppce6500"))
148 "e6500_decode,e6500_lsu")
151 (define_insn_reservation "e6500_store" 3
152 (and (eq_attr "type" "store,store_c")
153 (eq_attr "cpu" "ppce6500"))
154 "e6500_decode,e6500_lsu")
156 (define_insn_reservation "e6500_fpstore" 3
157 (and (eq_attr "type" "fpstore")
158 (eq_attr "cpu" "ppce6500"))
159 "e6500_decode,e6500_lsu")
161 (define_insn_reservation "e6500_vecstore" 4
162 (and (eq_attr "type" "vecstore")
163 (eq_attr "cpu" "ppce6500"))
164 "e6500_decode,e6500_lsu")
167 (define_insn_reservation "e6500_float" 7
168 (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
169 (eq_attr "cpu" "ppce6500"))
170 "e6500_decode,e6500_fpu")
172 (define_insn_reservation "e6500_sdiv" 20
173 (and (eq_attr "type" "sdiv")
174 (eq_attr "cpu" "ppce6500"))
175 "e6500_decode,e6500_fpu*20")
177 (define_insn_reservation "e6500_ddiv" 35
178 (and (eq_attr "type" "ddiv")
179 (eq_attr "cpu" "ppce6500"))
180 "e6500_decode,e6500_fpu*35")
183 (define_insn_reservation "e6500_branch" 1
184 (and (eq_attr "type" "jmpreg,branch,isync")
185 (eq_attr "cpu" "ppce6500"))
186 "e6500_decode,e6500_bu")
189 (define_insn_reservation "e6500_cr_logical" 1
190 (and (eq_attr "type" "cr_logical,delayed_cr")
191 (eq_attr "cpu" "ppce6500"))
192 "e6500_decode,e6500_bu")
195 (define_insn_reservation "e6500_vecsimple" 1
196 (and (eq_attr "type" "vecsimple,veccmp")
197 (eq_attr "cpu" "ppce6500"))
198 "e6500_decode,e6500_vec")
201 (define_insn_reservation "e6500_veccomplex" 4
202 (and (eq_attr "type" "veccomplex")
203 (eq_attr "cpu" "ppce6500"))
204 "e6500_decode,e6500_vec")
207 (define_insn_reservation "e6500_vecfloat" 6
208 (and (eq_attr "type" "vecfloat")
209 (eq_attr "cpu" "ppce6500"))
210 "e6500_decode,e6500_vec")
213 (define_insn_reservation "e6500_vecperm" 2
214 (and (eq_attr "type" "vecperm")
215 (eq_attr "cpu" "ppce6500"))
216 "e6500_decode,e6500_vecperm")