1 ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published
8 ;; by the Free Software Foundation; either version 3, or (at your
9 ;; option) any later version.
11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 ;; License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_automaton "ppc40x,ppc40xiu")
21 (define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
22 (define_cpu_unit "iu_40x" "ppc40xiu")
24 ;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
25 ;; Embedded PowerPC controller
27 ;; Max issue two insns/cycle (includes one branch)
28 (define_insn_reservation "ppc403-load" 2
29 (and (eq_attr "type" "load,load_l,store_c,sync")
30 (eq_attr "cpu" "ppc403,ppc405"))
33 (define_insn_reservation "ppc403-store" 2
34 (and (eq_attr "type" "store")
35 (eq_attr "cpu" "ppc403,ppc405"))
38 (define_insn_reservation "ppc403-integer" 1
39 (and (eq_attr "type" "integer,insert,shift,trap,\
40 var_shift_rotate,cntlz,exts,isel")
41 (eq_attr "cpu" "ppc403,ppc405"))
44 (define_insn_reservation "ppc403-two" 1
45 (and (eq_attr "type" "two")
46 (eq_attr "cpu" "ppc403,ppc405"))
49 (define_insn_reservation "ppc403-three" 1
50 (and (eq_attr "type" "three")
51 (eq_attr "cpu" "ppc403,ppc405"))
52 "iu_40x,iu_40x,iu_40x")
54 (define_insn_reservation "ppc403-compare" 3
55 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
57 (eq_attr "cpu" "ppc403,ppc405"))
58 "iu_40x,nothing,bpu_40x")
60 (define_insn_reservation "ppc403-imul" 4
61 (and (eq_attr "type" "mul")
62 (eq_attr "cpu" "ppc403"))
65 (define_insn_reservation "ppc405-imul" 5
66 (and (eq_attr "type" "mul")
68 (eq_attr "cpu" "ppc405"))
71 (define_insn_reservation "ppc405-imul2" 3
72 (and (eq_attr "type" "mul")
74 (eq_attr "cpu" "ppc405"))
77 (define_insn_reservation "ppc405-imul3" 2
78 (and (ior (eq_attr "type" "halfmul")
79 (and (eq_attr "type" "mul")
80 (eq_attr "size" "8")))
81 (eq_attr "cpu" "ppc405"))
84 (define_insn_reservation "ppc403-idiv" 33
85 (and (eq_attr "type" "idiv")
86 (eq_attr "cpu" "ppc403,ppc405"))
89 (define_insn_reservation "ppc403-mfcr" 2
90 (and (eq_attr "type" "mfcr")
91 (eq_attr "cpu" "ppc403,ppc405"))
94 (define_insn_reservation "ppc403-mtcr" 3
95 (and (eq_attr "type" "mtcr")
96 (eq_attr "cpu" "ppc403,ppc405"))
99 (define_insn_reservation "ppc403-mtjmpr" 4
100 (and (eq_attr "type" "mtjmpr")
101 (eq_attr "cpu" "ppc403,ppc405"))
104 (define_insn_reservation "ppc403-mfjmpr" 2
105 (and (eq_attr "type" "mfjmpr")
106 (eq_attr "cpu" "ppc403,ppc405"))
109 (define_insn_reservation "ppc403-jmpreg" 1
110 (and (eq_attr "type" "jmpreg,branch,isync")
111 (eq_attr "cpu" "ppc403,ppc405"))
114 (define_insn_reservation "ppc403-cr" 2
115 (and (eq_attr "type" "cr_logical,delayed_cr")
116 (eq_attr "cpu" "ppc403,ppc405"))
119 (define_insn_reservation "ppc405-float" 11
120 (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv")
121 (eq_attr "cpu" "ppc405"))