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* config/xtensa/xtensa.c (xtensa_va_start): Unshare valist.
[official-gcc.git] / gcc / config / xtensa / xtensa.c
blob392eafa0eee04dbff59cd53fbf319704a34cba04
1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "regs.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
36 #include "recog.h"
37 #include "output.h"
38 #include "tree.h"
39 #include "expr.h"
40 #include "flags.h"
41 #include "reload.h"
42 #include "tm_p.h"
43 #include "function.h"
44 #include "toplev.h"
45 #include "optabs.h"
46 #include "libfuncs.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "langhooks.h"
51 #include "gimple.h"
52 #include "df.h"
53
54
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
57 of EQ, NE, etc. */
58
59 enum internal_test
60 {
61 ITEST_EQ,
62 ITEST_NE,
63 ITEST_GT,
64 ITEST_GE,
65 ITEST_LT,
66 ITEST_LE,
67 ITEST_GTU,
68 ITEST_GEU,
69 ITEST_LTU,
70 ITEST_LEU,
71 ITEST_MAX
72 };
73
74 /* Cached operands, and operator to compare for use in set/branch on
75 condition codes. */
76 rtx branch_cmp[2];
77
78 /* what type of branch to use */
79 enum cmp_type branch_type;
80
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
84
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size;
87
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
90
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function GTY(())
93 {
94 int accesses_prev_frame;
95 bool need_a7_copy;
96 bool vararg_a7;
97 rtx vararg_a7_copy;
98 rtx set_frame_ptr_insn;
99 };
100
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
103 treatment. */
104
105 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
106 {
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
108 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
110 1
111 };
112
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
115 {
116 RL_REGS, SP_REG, RL_REGS, RL_REGS,
117 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
118 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
119 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
120 AR_REGS, AR_REGS, BR_REGS,
121 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
122 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
123 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
124 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
125 ACC_REG,
126 };
127
128 static enum internal_test map_test_to_internal_test (enum rtx_code);
129 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
130 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
131 static rtx gen_conditional_move (rtx);
132 static rtx fixup_subreg_mem (rtx);
133 static struct machine_function * xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (const_tree);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
137 static rtx xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
139 int) ATTRIBUTE_UNUSED;
140 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
141 unsigned HOST_WIDE_INT);
142 static bool xtensa_rtx_costs (rtx, int, int, int *);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree, const_tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
146 gimple_seq *);
147 static rtx xtensa_function_value (const_tree, const_tree, bool);
148 static void xtensa_init_builtins (void);
149 static tree xtensa_fold_builtin (tree, tree, bool);
150 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
151 static void xtensa_va_start (tree, rtx);
152
153 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
154 REG_ALLOC_ORDER;
155 \f
156
157 /* This macro generates the assembly code for function exit,
158 on machines that need it. If FUNCTION_EPILOGUE is not defined
159 then individual return instructions are generated for each
160 return statement. Args are same as for FUNCTION_PROLOGUE. */
161
162 #undef TARGET_ASM_FUNCTION_EPILOGUE
163 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
164
165 /* These hooks specify assembly directives for creating certain kinds
166 of integer object. */
167
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
170
171 #undef TARGET_ASM_SELECT_RTX_SECTION
172 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
173
174 #undef TARGET_DEFAULT_TARGET_FLAGS
175 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
176
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS xtensa_rtx_costs
179 #undef TARGET_ADDRESS_COST
180 #define TARGET_ADDRESS_COST hook_int_rtx_0
181
182 #undef TARGET_BUILD_BUILTIN_VA_LIST
183 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
184
185 #undef TARGET_EXPAND_BUILTIN_VA_START
186 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
187
188 #undef TARGET_PROMOTE_FUNCTION_ARGS
189 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
190 #undef TARGET_PROMOTE_FUNCTION_RETURN
191 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
192 #undef TARGET_PROMOTE_PROTOTYPES
193 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
194
195 #undef TARGET_RETURN_IN_MEMORY
196 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
197 #undef TARGET_FUNCTION_VALUE
198 #define TARGET_FUNCTION_VALUE xtensa_function_value
199 #undef TARGET_SPLIT_COMPLEX_ARG
200 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
201 #undef TARGET_MUST_PASS_IN_STACK
202 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
203
204 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
205 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
206 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
207 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
208
209 #undef TARGET_RETURN_IN_MSB
210 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
211
212 #undef TARGET_INIT_BUILTINS
213 #define TARGET_INIT_BUILTINS xtensa_init_builtins
214 #undef TARGET_FOLD_BUILTIN
215 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
216 #undef TARGET_EXPAND_BUILTIN
217 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
218
219 struct gcc_target targetm = TARGET_INITIALIZER;
220
221 \f
222 /* Functions to test Xtensa immediate operand validity. */
223
224 bool
225 xtensa_simm8 (HOST_WIDE_INT v)
226 {
227 return v >= -128 && v <= 127;
228 }
229
230
231 bool
232 xtensa_simm8x256 (HOST_WIDE_INT v)
233 {
234 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
235 }
236
237
238 bool
239 xtensa_simm12b (HOST_WIDE_INT v)
240 {
241 return v >= -2048 && v <= 2047;
242 }
243
244
245 static bool
246 xtensa_uimm8 (HOST_WIDE_INT v)
247 {
248 return v >= 0 && v <= 255;
249 }
250
251
252 static bool
253 xtensa_uimm8x2 (HOST_WIDE_INT v)
254 {
255 return (v & 1) == 0 && (v >= 0 && v <= 510);
256 }
257
258
259 static bool
260 xtensa_uimm8x4 (HOST_WIDE_INT v)
261 {
262 return (v & 3) == 0 && (v >= 0 && v <= 1020);
263 }
264
265
266 static bool
267 xtensa_b4const (HOST_WIDE_INT v)
268 {
269 switch (v)
270 {
271 case -1:
272 case 1:
273 case 2:
274 case 3:
275 case 4:
276 case 5:
277 case 6:
278 case 7:
279 case 8:
280 case 10:
281 case 12:
282 case 16:
283 case 32:
284 case 64:
285 case 128:
286 case 256:
287 return true;
288 }
289 return false;
290 }
291
292
293 bool
294 xtensa_b4const_or_zero (HOST_WIDE_INT v)
295 {
296 if (v == 0)
297 return true;
298 return xtensa_b4const (v);
299 }
300
301
302 bool
303 xtensa_b4constu (HOST_WIDE_INT v)
304 {
305 switch (v)
306 {
307 case 32768:
308 case 65536:
309 case 2:
310 case 3:
311 case 4:
312 case 5:
313 case 6:
314 case 7:
315 case 8:
316 case 10:
317 case 12:
318 case 16:
319 case 32:
320 case 64:
321 case 128:
322 case 256:
323 return true;
324 }
325 return false;
326 }
327
328
329 bool
330 xtensa_mask_immediate (HOST_WIDE_INT v)
331 {
332 #define MAX_MASK_SIZE 16
333 int mask_size;
334
335 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
336 {
337 if ((v & 1) == 0)
338 return false;
339 v = v >> 1;
340 if (v == 0)
341 return true;
342 }
343
344 return false;
345 }
346
347
348 /* This is just like the standard true_regnum() function except that it
349 works even when reg_renumber is not initialized. */
350
351 int
352 xt_true_regnum (rtx x)
353 {
354 if (GET_CODE (x) == REG)
355 {
356 if (reg_renumber
357 && REGNO (x) >= FIRST_PSEUDO_REGISTER
358 && reg_renumber[REGNO (x)] >= 0)
359 return reg_renumber[REGNO (x)];
360 return REGNO (x);
361 }
362 if (GET_CODE (x) == SUBREG)
363 {
364 int base = xt_true_regnum (SUBREG_REG (x));
365 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
366 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
367 GET_MODE (SUBREG_REG (x)),
368 SUBREG_BYTE (x), GET_MODE (x));
369 }
370 return -1;
371 }
372
373
374 int
375 xtensa_valid_move (enum machine_mode mode, rtx *operands)
376 {
377 /* Either the destination or source must be a register, and the
378 MAC16 accumulator doesn't count. */
379
380 if (register_operand (operands[0], mode))
381 {
382 int dst_regnum = xt_true_regnum (operands[0]);
383
384 /* The stack pointer can only be assigned with a MOVSP opcode. */
385 if (dst_regnum == STACK_POINTER_REGNUM)
386 return (mode == SImode
387 && register_operand (operands[1], mode)
388 && !ACC_REG_P (xt_true_regnum (operands[1])));
389
390 if (!ACC_REG_P (dst_regnum))
391 return true;
392 }
393 if (register_operand (operands[1], mode))
394 {
395 int src_regnum = xt_true_regnum (operands[1]);
396 if (!ACC_REG_P (src_regnum))
397 return true;
398 }
399 return FALSE;
400 }
401
402
403 int
404 smalloffset_mem_p (rtx op)
405 {
406 if (GET_CODE (op) == MEM)
407 {
408 rtx addr = XEXP (op, 0);
409 if (GET_CODE (addr) == REG)
410 return BASE_REG_P (addr, 0);
411 if (GET_CODE (addr) == PLUS)
412 {
413 rtx offset = XEXP (addr, 0);
414 HOST_WIDE_INT val;
415 if (GET_CODE (offset) != CONST_INT)
416 offset = XEXP (addr, 1);
417 if (GET_CODE (offset) != CONST_INT)
418 return FALSE;
419
420 val = INTVAL (offset);
421 return (val & 3) == 0 && (val >= 0 && val <= 60);
422 }
423 }
424 return FALSE;
425 }
426
427
428 int
429 constantpool_address_p (rtx addr)
430 {
431 rtx sym = addr;
432
433 if (GET_CODE (addr) == CONST)
434 {
435 rtx offset;
436
437 /* Only handle (PLUS (SYM, OFFSET)) form. */
438 addr = XEXP (addr, 0);
439 if (GET_CODE (addr) != PLUS)
440 return FALSE;
441
442 /* Make sure the address is word aligned. */
443 offset = XEXP (addr, 1);
444 if ((GET_CODE (offset) != CONST_INT)
445 || ((INTVAL (offset) & 3) != 0))
446 return FALSE;
447
448 sym = XEXP (addr, 0);
449 }
450
451 if ((GET_CODE (sym) == SYMBOL_REF)
452 && CONSTANT_POOL_ADDRESS_P (sym))
453 return TRUE;
454 return FALSE;
455 }
456
457
458 int
459 constantpool_mem_p (rtx op)
460 {
461 if (GET_CODE (op) == SUBREG)
462 op = SUBREG_REG (op);
463 if (GET_CODE (op) == MEM)
464 return constantpool_address_p (XEXP (op, 0));
465 return FALSE;
466 }
467
468
469 void
470 xtensa_extend_reg (rtx dst, rtx src)
471 {
472 rtx temp = gen_reg_rtx (SImode);
473 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
474
475 /* Generate paradoxical subregs as needed so that the modes match. */
476 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
477 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
478
479 emit_insn (gen_ashlsi3 (temp, src, shift));
480 emit_insn (gen_ashrsi3 (dst, temp, shift));
481 }
482
483
484 bool
485 xtensa_mem_offset (unsigned v, enum machine_mode mode)
486 {
487 switch (mode)
488 {
489 case BLKmode:
490 /* Handle the worst case for block moves. See xtensa_expand_block_move
491 where we emit an optimized block move operation if the block can be
492 moved in < "move_ratio" pieces. The worst case is when the block is
493 aligned but has a size of (3 mod 4) (does this happen?) so that the
494 last piece requires a byte load/store. */
495 return (xtensa_uimm8 (v)
496 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
497
498 case QImode:
499 return xtensa_uimm8 (v);
500
501 case HImode:
502 return xtensa_uimm8x2 (v);
503
504 case DFmode:
505 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
506
507 default:
508 break;
509 }
510
511 return xtensa_uimm8x4 (v);
512 }
513
514
515 /* Make normal rtx_code into something we can index from an array. */
516
517 static enum internal_test
518 map_test_to_internal_test (enum rtx_code test_code)
519 {
520 enum internal_test test = ITEST_MAX;
521
522 switch (test_code)
523 {
524 default: break;
525 case EQ: test = ITEST_EQ; break;
526 case NE: test = ITEST_NE; break;
527 case GT: test = ITEST_GT; break;
528 case GE: test = ITEST_GE; break;
529 case LT: test = ITEST_LT; break;
530 case LE: test = ITEST_LE; break;
531 case GTU: test = ITEST_GTU; break;
532 case GEU: test = ITEST_GEU; break;
533 case LTU: test = ITEST_LTU; break;
534 case LEU: test = ITEST_LEU; break;
535 }
536
537 return test;
538 }
539
540
541 /* Generate the code to compare two integer values. The return value is
542 the comparison expression. */
543
544 static rtx
545 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
546 rtx cmp0, /* first operand to compare */
547 rtx cmp1, /* second operand to compare */
548 int *p_invert /* whether branch needs to reverse test */)
549 {
550 struct cmp_info
551 {
552 enum rtx_code test_code; /* test code to use in insn */
553 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
554 int const_add; /* constant to add (convert LE -> LT) */
555 int reverse_regs; /* reverse registers in test */
556 int invert_const; /* != 0 if invert value if cmp1 is constant */
557 int invert_reg; /* != 0 if invert value if cmp1 is register */
558 int unsignedp; /* != 0 for unsigned comparisons. */
559 };
560
561 static struct cmp_info info[ (int)ITEST_MAX ] = {
562
563 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
564 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
565
566 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
567 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
568 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
569 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
570
571 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
572 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
573 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
574 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
575 };
576
577 enum internal_test test;
578 enum machine_mode mode;
579 struct cmp_info *p_info;
580
581 test = map_test_to_internal_test (test_code);
582 gcc_assert (test != ITEST_MAX);
583
584 p_info = &info[ (int)test ];
585
586 mode = GET_MODE (cmp0);
587 if (mode == VOIDmode)
588 mode = GET_MODE (cmp1);
589
590 /* Make sure we can handle any constants given to us. */
591 if (GET_CODE (cmp1) == CONST_INT)
592 {
593 HOST_WIDE_INT value = INTVAL (cmp1);
594 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
595
596 /* if the immediate overflows or does not fit in the immediate field,
597 spill it to a register */
598
599 if ((p_info->unsignedp ?
600 (uvalue + p_info->const_add > uvalue) :
601 (value + p_info->const_add > value)) != (p_info->const_add > 0))
602 {
603 cmp1 = force_reg (mode, cmp1);
604 }
605 else if (!(p_info->const_range_p) (value + p_info->const_add))
606 {
607 cmp1 = force_reg (mode, cmp1);
608 }
609 }
610 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
611 {
612 cmp1 = force_reg (mode, cmp1);
613 }
614
615 /* See if we need to invert the result. */
616 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
617 ? p_info->invert_const
618 : p_info->invert_reg);
619
620 /* Comparison to constants, may involve adding 1 to change a LT into LE.
621 Comparison between two registers, may involve switching operands. */
622 if (GET_CODE (cmp1) == CONST_INT)
623 {
624 if (p_info->const_add != 0)
625 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
626
627 }
628 else if (p_info->reverse_regs)
629 {
630 rtx temp = cmp0;
631 cmp0 = cmp1;
632 cmp1 = temp;
633 }
634
635 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
636 }
637
638
639 /* Generate the code to compare two float values. The return value is
640 the comparison expression. */
641
642 static rtx
643 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
644 rtx cmp0, /* first operand to compare */
645 rtx cmp1 /* second operand to compare */)
646 {
647 rtx (*gen_fn) (rtx, rtx, rtx);
648 rtx brtmp;
649 int reverse_regs, invert;
650
651 switch (test_code)
652 {
653 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
654 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
655 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
656 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
657 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
658 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
659 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
660 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
661 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
662 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
663 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
664 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
665 case UNORDERED:
666 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
667 case ORDERED:
668 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
669 default:
670 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
671 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
672 }
673
674 if (reverse_regs)
675 {
676 rtx temp = cmp0;
677 cmp0 = cmp1;
678 cmp1 = temp;
679 }
680
681 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
682 emit_insn (gen_fn (brtmp, cmp0, cmp1));
683
684 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
685 }
686
687
688 void
689 xtensa_expand_conditional_branch (rtx *operands, enum rtx_code test_code)
690 {
691 enum cmp_type type = branch_type;
692 rtx cmp0 = branch_cmp[0];
693 rtx cmp1 = branch_cmp[1];
694 rtx cmp;
695 int invert;
696 rtx label1, label2;
697
698 switch (type)
699 {
700 case CMP_DF:
701 default:
702 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
703
704 case CMP_SI:
705 invert = FALSE;
706 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
707 break;
708
709 case CMP_SF:
710 if (!TARGET_HARD_FLOAT)
711 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
712 cmp0, cmp1));
713 invert = FALSE;
714 cmp = gen_float_relational (test_code, cmp0, cmp1);
715 break;
716 }
717
718 /* Generate the branch. */
719
720 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
721 label2 = pc_rtx;
722
723 if (invert)
724 {
725 label2 = label1;
726 label1 = pc_rtx;
727 }
728
729 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
730 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
731 label1,
732 label2)));
733 }
734
735
736 static rtx
737 gen_conditional_move (rtx cmp)
738 {
739 enum rtx_code code = GET_CODE (cmp);
740 rtx op0 = branch_cmp[0];
741 rtx op1 = branch_cmp[1];
742
743 if (branch_type == CMP_SI)
744 {
745 /* Jump optimization calls get_condition() which canonicalizes
746 comparisons like (GE x <const>) to (GT x <const-1>).
747 Transform those comparisons back to GE, since that is the
748 comparison supported in Xtensa. We shouldn't have to
749 transform <LE x const> comparisons, because neither
750 xtensa_expand_conditional_branch() nor get_condition() will
751 produce them. */
752
753 if ((code == GT) && (op1 == constm1_rtx))
754 {
755 code = GE;
756 op1 = const0_rtx;
757 }
758 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
759
760 if (boolean_operator (cmp, VOIDmode))
761 {
762 /* Swap the operands to make const0 second. */
763 if (op0 == const0_rtx)
764 {
765 op0 = op1;
766 op1 = const0_rtx;
767 }
768
769 /* If not comparing against zero, emit a comparison (subtract). */
770 if (op1 != const0_rtx)
771 {
772 op0 = expand_binop (SImode, sub_optab, op0, op1,
773 0, 0, OPTAB_LIB_WIDEN);
774 op1 = const0_rtx;
775 }
776 }
777 else if (branch_operator (cmp, VOIDmode))
778 {
779 /* Swap the operands to make const0 second. */
780 if (op0 == const0_rtx)
781 {
782 op0 = op1;
783 op1 = const0_rtx;
784
785 switch (code)
786 {
787 case LT: code = GE; break;
788 case GE: code = LT; break;
789 default: gcc_unreachable ();
790 }
791 }
792
793 if (op1 != const0_rtx)
794 return 0;
795 }
796 else
797 return 0;
798
799 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
800 }
801
802 if (TARGET_HARD_FLOAT && (branch_type == CMP_SF))
803 return gen_float_relational (code, op0, op1);
804
805 return 0;
806 }
807
808
809 int
810 xtensa_expand_conditional_move (rtx *operands, int isflt)
811 {
812 rtx cmp;
813 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
814
815 if (!(cmp = gen_conditional_move (operands[1])))
816 return 0;
817
818 if (isflt)
819 gen_fn = (branch_type == CMP_SI
820 ? gen_movsfcc_internal0
821 : gen_movsfcc_internal1);
822 else
823 gen_fn = (branch_type == CMP_SI
824 ? gen_movsicc_internal0
825 : gen_movsicc_internal1);
826
827 emit_insn (gen_fn (operands[0], XEXP (cmp, 0),
828 operands[2], operands[3], cmp));
829 return 1;
830 }
831
832
833 int
834 xtensa_expand_scc (rtx *operands)
835 {
836 rtx dest = operands[0];
837 rtx cmp = operands[1];
838 rtx one_tmp, zero_tmp;
839 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
840
841 if (!(cmp = gen_conditional_move (cmp)))
842 return 0;
843
844 one_tmp = gen_reg_rtx (SImode);
845 zero_tmp = gen_reg_rtx (SImode);
846 emit_insn (gen_movsi (one_tmp, const_true_rtx));
847 emit_insn (gen_movsi (zero_tmp, const0_rtx));
848
849 gen_fn = (branch_type == CMP_SI
850 ? gen_movsicc_internal0
851 : gen_movsicc_internal1);
852 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
853 return 1;
854 }
855
856
857 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
858 for the output, i.e., the input operands are twice as big as MODE. */
859
860 void
861 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
862 {
863 switch (GET_CODE (operands[1]))
864 {
865 case REG:
866 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
867 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
868 break;
869
870 case MEM:
871 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
872 operands[2] = adjust_address (operands[1], mode, 0);
873 break;
874
875 case CONST_INT:
876 case CONST_DOUBLE:
877 split_double (operands[1], &operands[2], &operands[3]);
878 break;
879
880 default:
881 gcc_unreachable ();
882 }
883
884 switch (GET_CODE (operands[0]))
885 {
886 case REG:
887 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
888 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
889 break;
890
891 case MEM:
892 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
893 operands[0] = adjust_address (operands[0], mode, 0);
894 break;
895
896 default:
897 gcc_unreachable ();
898 }
899 }
900
901
902 /* Emit insns to move operands[1] into operands[0].
903 Return 1 if we have written out everything that needs to be done to
904 do the move. Otherwise, return 0 and the caller will emit the move
905 normally. */
906
907 int
908 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
909 {
910 if (CONSTANT_P (operands[1])
911 && (GET_CODE (operands[1]) != CONST_INT
912 || !xtensa_simm12b (INTVAL (operands[1]))))
913 {
914 if (!TARGET_CONST16)
915 operands[1] = force_const_mem (SImode, operands[1]);
916
917 /* PC-relative loads are always SImode, and CONST16 is only
918 supported in the movsi pattern, so add a SUBREG for any other
919 (smaller) mode. */
920
921 if (mode != SImode)
922 {
923 if (register_operand (operands[0], mode))
924 {
925 operands[0] = simplify_gen_subreg (SImode, operands[0], mode, 0);
926 emit_move_insn (operands[0], operands[1]);
927 return 1;
928 }
929 else
930 {
931 operands[1] = force_reg (SImode, operands[1]);
932 operands[1] = gen_lowpart_SUBREG (mode, operands[1]);
933 }
934 }
935 }
936
937 if (!(reload_in_progress | reload_completed)
938 && !xtensa_valid_move (mode, operands))
939 operands[1] = force_reg (mode, operands[1]);
940
941 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
942
943 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
944 instruction won't be recognized after reload, so we remove the
945 subreg and adjust mem accordingly. */
946 if (reload_in_progress)
947 {
948 operands[0] = fixup_subreg_mem (operands[0]);
949 operands[1] = fixup_subreg_mem (operands[1]);
950 }
951 return 0;
952 }
953
954
955 static rtx
956 fixup_subreg_mem (rtx x)
957 {
958 if (GET_CODE (x) == SUBREG
959 && GET_CODE (SUBREG_REG (x)) == REG
960 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
961 {
962 rtx temp =
963 gen_rtx_SUBREG (GET_MODE (x),
964 reg_equiv_mem [REGNO (SUBREG_REG (x))],
965 SUBREG_BYTE (x));
966 x = alter_subreg (&temp);
967 }
968 return x;
969 }
970
971
972 /* Check if an incoming argument in a7 is expected to be used soon and
973 if OPND is a register or register pair that includes a7. If so,
974 create a new pseudo and copy a7 into that pseudo at the very
975 beginning of the function, followed by the special "set_frame_ptr"
976 unspec_volatile insn. The return value is either the original
977 operand, if it is not a7, or the new pseudo containing a copy of
978 the incoming argument. This is necessary because the register
979 allocator will ignore conflicts with a7 and may either assign some
980 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
981 the incoming argument in a7. By copying the argument out of a7 as
982 the very first thing, and then immediately following that with an
983 unspec_volatile to keep the scheduler away, we should avoid any
984 problems. Putting the set_frame_ptr insn at the beginning, with
985 only the a7 copy before it, also makes it easier for the prologue
986 expander to initialize the frame pointer after the a7 copy and to
987 fix up the a7 copy to use the stack pointer instead of the frame
988 pointer. */
989
990 rtx
991 xtensa_copy_incoming_a7 (rtx opnd)
992 {
993 rtx entry_insns = 0;
994 rtx reg, tmp;
995 enum machine_mode mode;
996
997 if (!cfun->machine->need_a7_copy)
998 return opnd;
999
1000 /* This function should never be called again once a7 has been copied. */
1001 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1002
1003 mode = GET_MODE (opnd);
1004
1005 /* The operand using a7 may come in a later instruction, so just return
1006 the original operand if it doesn't use a7. */
1007 reg = opnd;
1008 if (GET_CODE (reg) == SUBREG)
1009 {
1010 gcc_assert (SUBREG_BYTE (reg) == 0);
1011 reg = SUBREG_REG (reg);
1012 }
1013 if (GET_CODE (reg) != REG
1014 || REGNO (reg) > A7_REG
1015 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1016 return opnd;
1017
1018 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1019 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1020
1021 cfun->machine->need_a7_copy = false;
1022
1023 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1024 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1025
1026 start_sequence ();
1027 tmp = gen_reg_rtx (mode);
1028
1029 switch (mode)
1030 {
1031 case DFmode:
1032 case DImode:
1033 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1034 gen_rtx_REG (SImode, A7_REG - 1)));
1035 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1036 gen_raw_REG (SImode, A7_REG)));
1037 break;
1038 case SFmode:
1039 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1040 break;
1041 case SImode:
1042 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1043 break;
1044 case HImode:
1045 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1046 break;
1047 case QImode:
1048 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1049 break;
1050 default:
1051 gcc_unreachable ();
1052 }
1053
1054 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1055 entry_insns = get_insns ();
1056 end_sequence ();
1057
1058 if (cfun->machine->vararg_a7)
1059 {
1060 /* This is called from within builtin_saveregs, which will insert the
1061 saveregs code at the function entry, ahead of anything placed at
1062 the function entry now. Instead, save the sequence to be inserted
1063 at the beginning of the saveregs code. */
1064 cfun->machine->vararg_a7_copy = entry_insns;
1065 }
1066 else
1067 {
1068 /* Put entry_insns after the NOTE that starts the function. If
1069 this is inside a start_sequence, make the outer-level insn
1070 chain current, so the code is placed at the start of the
1071 function. */
1072 push_topmost_sequence ();
1073 /* Do not use entry_of_function() here. This is called from within
1074 expand_function_start, when the CFG still holds GIMPLE. */
1075 emit_insn_after (entry_insns, get_insns ());
1076 pop_topmost_sequence ();
1077 }
1078
1079 return tmp;
1080 }
1081
1082
1083 /* Try to expand a block move operation to a sequence of RTL move
1084 instructions. If not optimizing, or if the block size is not a
1085 constant, or if the block is too large, the expansion fails and GCC
1086 falls back to calling memcpy().
1087
1088 operands[0] is the destination
1089 operands[1] is the source
1090 operands[2] is the length
1091 operands[3] is the alignment */
1092
1093 int
1094 xtensa_expand_block_move (rtx *operands)
1095 {
1096 static const enum machine_mode mode_from_align[] =
1097 {
1098 VOIDmode, QImode, HImode, VOIDmode, SImode,
1099 };
1100
1101 rtx dst_mem = operands[0];
1102 rtx src_mem = operands[1];
1103 HOST_WIDE_INT bytes, align;
1104 int num_pieces, move_ratio;
1105 rtx temp[2];
1106 enum machine_mode mode[2];
1107 int amount[2];
1108 bool active[2];
1109 int phase = 0;
1110 int next;
1111 int offset_ld = 0;
1112 int offset_st = 0;
1113 rtx x;
1114
1115 /* If this is not a fixed size move, just call memcpy. */
1116 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1117 return 0;
1118
1119 bytes = INTVAL (operands[2]);
1120 align = INTVAL (operands[3]);
1121
1122 /* Anything to move? */
1123 if (bytes <= 0)
1124 return 0;
1125
1126 if (align > MOVE_MAX)
1127 align = MOVE_MAX;
1128
1129 /* Decide whether to expand inline based on the optimization level. */
1130 move_ratio = 4;
1131 if (optimize > 2)
1132 move_ratio = LARGEST_MOVE_RATIO;
1133 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1134 if (num_pieces > move_ratio)
1135 return 0;
1136
1137 x = XEXP (dst_mem, 0);
1138 if (!REG_P (x))
1139 {
1140 x = force_reg (Pmode, x);
1141 dst_mem = replace_equiv_address (dst_mem, x);
1142 }
1143
1144 x = XEXP (src_mem, 0);
1145 if (!REG_P (x))
1146 {
1147 x = force_reg (Pmode, x);
1148 src_mem = replace_equiv_address (src_mem, x);
1149 }
1150
1151 active[0] = active[1] = false;
1152
1153 do
1154 {
1155 next = phase;
1156 phase ^= 1;
1157
1158 if (bytes > 0)
1159 {
1160 int next_amount;
1161
1162 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1163 next_amount = MIN (next_amount, align);
1164
1165 amount[next] = next_amount;
1166 mode[next] = mode_from_align[next_amount];
1167 temp[next] = gen_reg_rtx (mode[next]);
1168
1169 x = adjust_address (src_mem, mode[next], offset_ld);
1170 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1171
1172 offset_ld += next_amount;
1173 bytes -= next_amount;
1174 active[next] = true;
1175 }
1176
1177 if (active[phase])
1178 {
1179 active[phase] = false;
1180
1181 x = adjust_address (dst_mem, mode[phase], offset_st);
1182 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1183
1184 offset_st += amount[phase];
1185 }
1186 }
1187 while (active[next]);
1188
1189 return 1;
1190 }
1191
1192
1193 void
1194 xtensa_expand_nonlocal_goto (rtx *operands)
1195 {
1196 rtx goto_handler = operands[1];
1197 rtx containing_fp = operands[3];
1198
1199 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1200 is too big to generate in-line. */
1201
1202 if (GET_CODE (containing_fp) != REG)
1203 containing_fp = force_reg (Pmode, containing_fp);
1204
1205 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1206 0, VOIDmode, 2,
1207 containing_fp, Pmode,
1208 goto_handler, Pmode);
1209 }
1210
1211
1212 static struct machine_function *
1213 xtensa_init_machine_status (void)
1214 {
1215 return GGC_CNEW (struct machine_function);
1216 }
1217
1218
1219 /* Shift VAL of mode MODE left by COUNT bits. */
1220
1221 static inline rtx
1222 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1223 {
1224 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1225 NULL_RTX, 1, OPTAB_DIRECT);
1226 return expand_simple_binop (SImode, ASHIFT, val, count,
1227 NULL_RTX, 1, OPTAB_DIRECT);
1228 }
1229
1230
1231 /* Structure to hold the initial parameters for a compare_and_swap operation
1232 in HImode and QImode. */
1233
1234 struct alignment_context
1235 {
1236 rtx memsi; /* SI aligned memory location. */
1237 rtx shift; /* Bit offset with regard to lsb. */
1238 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1239 rtx modemaski; /* ~modemask */
1240 };
1241
1242
1243 /* Initialize structure AC for word access to HI and QI mode memory. */
1244
1245 static void
1246 init_alignment_context (struct alignment_context *ac, rtx mem)
1247 {
1248 enum machine_mode mode = GET_MODE (mem);
1249 rtx byteoffset = NULL_RTX;
1250 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1251
1252 if (aligned)
1253 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1254 else
1255 {
1256 /* Alignment is unknown. */
1257 rtx addr, align;
1258
1259 /* Force the address into a register. */
1260 addr = force_reg (Pmode, XEXP (mem, 0));
1261
1262 /* Align it to SImode. */
1263 align = expand_simple_binop (Pmode, AND, addr,
1264 GEN_INT (-GET_MODE_SIZE (SImode)),
1265 NULL_RTX, 1, OPTAB_DIRECT);
1266 /* Generate MEM. */
1267 ac->memsi = gen_rtx_MEM (SImode, align);
1268 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1269 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1270 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1271
1272 byteoffset = expand_simple_binop (Pmode, AND, addr,
1273 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1274 NULL_RTX, 1, OPTAB_DIRECT);
1275 }
1276
1277 /* Calculate shiftcount. */
1278 if (TARGET_BIG_ENDIAN)
1279 {
1280 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1281 if (!aligned)
1282 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1283 NULL_RTX, 1, OPTAB_DIRECT);
1284 }
1285 else
1286 {
1287 if (aligned)
1288 ac->shift = NULL_RTX;
1289 else
1290 ac->shift = byteoffset;
1291 }
1292
1293 if (ac->shift != NULL_RTX)
1294 {
1295 /* Shift is the byte count, but we need the bitcount. */
1296 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1297 GEN_INT (BITS_PER_UNIT),
1298 NULL_RTX, 1, OPTAB_DIRECT);
1299 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1300 GEN_INT (GET_MODE_MASK (mode)),
1301 ac->shift,
1302 NULL_RTX, 1, OPTAB_DIRECT);
1303 }
1304 else
1305 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1306
1307 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1308 }
1309
1310
1311 /* Expand an atomic compare and swap operation for HImode and QImode.
1312 MEM is the memory location, CMP the old value to compare MEM with
1313 and NEW the value to set if CMP == MEM. */
1314
1315 void
1316 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new)
1317 {
1318 enum machine_mode mode = GET_MODE (mem);
1319 struct alignment_context ac;
1320 rtx tmp, cmpv, newv, val;
1321 rtx oldval = gen_reg_rtx (SImode);
1322 rtx res = gen_reg_rtx (SImode);
1323 rtx csloop = gen_label_rtx ();
1324 rtx csend = gen_label_rtx ();
1325
1326 init_alignment_context (&ac, mem);
1327
1328 if (ac.shift != NULL_RTX)
1329 {
1330 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1331 new = xtensa_expand_mask_and_shift (new, mode, ac.shift);
1332 }
1333
1334 /* Load the surrounding word into VAL with the MEM value masked out. */
1335 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1336 ac.modemaski, NULL_RTX, 1,
1337 OPTAB_DIRECT));
1338 emit_label (csloop);
1339
1340 /* Patch CMP and NEW into VAL at correct position. */
1341 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1342 NULL_RTX, 1, OPTAB_DIRECT));
1343 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
1344 NULL_RTX, 1, OPTAB_DIRECT));
1345
1346 /* Jump to end if we're done. */
1347 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1348 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1349
1350 /* Check for changes outside mode. */
1351 emit_move_insn (oldval, val);
1352 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1353 val, 1, OPTAB_DIRECT);
1354 if (tmp != val)
1355 emit_move_insn (val, tmp);
1356
1357 /* Loop internal if so. */
1358 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1359
1360 emit_label (csend);
1361
1362 /* Return the correct part of the bitfield. */
1363 convert_move (target,
1364 (ac.shift == NULL_RTX ? res
1365 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1366 NULL_RTX, 1, OPTAB_DIRECT)),
1367 1);
1368 }
1369
1370
1371 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1372 the default expansion works fine for SImode). MEM is the memory location
1373 and VAL the value to play with. If AFTER is true then store the value
1374 MEM holds after the operation, if AFTER is false then store the value MEM
1375 holds before the operation. If TARGET is zero then discard that value, else
1376 store it to TARGET. */
1377
1378 void
1379 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1380 bool after)
1381 {
1382 enum machine_mode mode = GET_MODE (mem);
1383 struct alignment_context ac;
1384 rtx csloop = gen_label_rtx ();
1385 rtx cmp, tmp;
1386 rtx old = gen_reg_rtx (SImode);
1387 rtx new = gen_reg_rtx (SImode);
1388 rtx orig = NULL_RTX;
1389
1390 init_alignment_context (&ac, mem);
1391
1392 /* Prepare values before the compare-and-swap loop. */
1393 if (ac.shift != NULL_RTX)
1394 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1395 switch (code)
1396 {
1397 case PLUS:
1398 case MINUS:
1399 orig = gen_reg_rtx (SImode);
1400 convert_move (orig, val, 1);
1401 break;
1402
1403 case SET:
1404 case IOR:
1405 case XOR:
1406 break;
1407
1408 case MULT: /* NAND */
1409 case AND:
1410 /* val = "11..1<val>11..1" */
1411 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1412 NULL_RTX, 1, OPTAB_DIRECT);
1413 break;
1414
1415 default:
1416 gcc_unreachable ();
1417 }
1418
1419 /* Load full word. Subsequent loads are performed by S32C1I. */
1420 cmp = force_reg (SImode, ac.memsi);
1421
1422 emit_label (csloop);
1423 emit_move_insn (old, cmp);
1424
1425 switch (code)
1426 {
1427 case PLUS:
1428 case MINUS:
1429 val = expand_simple_binop (SImode, code, old, orig,
1430 NULL_RTX, 1, OPTAB_DIRECT);
1431 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1432 NULL_RTX, 1, OPTAB_DIRECT);
1433 /* FALLTHRU */
1434 case SET:
1435 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1436 NULL_RTX, 1, OPTAB_DIRECT);
1437 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1438 new, 1, OPTAB_DIRECT);
1439 break;
1440
1441 case AND:
1442 case IOR:
1443 case XOR:
1444 tmp = expand_simple_binop (SImode, code, old, val,
1445 new, 1, OPTAB_DIRECT);
1446 break;
1447
1448 case MULT: /* NAND */
1449 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1450 NULL_RTX, 1, OPTAB_DIRECT);
1451 tmp = expand_simple_binop (SImode, AND, tmp, val,
1452 new, 1, OPTAB_DIRECT);
1453 break;
1454
1455 default:
1456 gcc_unreachable ();
1457 }
1458
1459 if (tmp != new)
1460 emit_move_insn (new, tmp);
1461 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new));
1462 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1463
1464 if (target)
1465 {
1466 tmp = (after ? new : cmp);
1467 convert_move (target,
1468 (ac.shift == NULL_RTX ? tmp
1469 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1470 NULL_RTX, 1, OPTAB_DIRECT)),
1471 1);
1472 }
1473 }
1474
1475
1476 void
1477 xtensa_setup_frame_addresses (void)
1478 {
1479 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1480 cfun->machine->accesses_prev_frame = 1;
1481
1482 emit_library_call
1483 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1484 0, VOIDmode, 0);
1485 }
1486
1487
1488 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1489 a comment showing where the end of the loop is. However, if there is a
1490 label or a branch at the end of the loop then we need to place a nop
1491 there. If the loop ends with a label we need the nop so that branches
1492 targeting that label will target the nop (and thus remain in the loop),
1493 instead of targeting the instruction after the loop (and thus exiting
1494 the loop). If the loop ends with a branch, we need the nop in case the
1495 branch is targeting a location inside the loop. When the branch
1496 executes it will cause the loop count to be decremented even if it is
1497 taken (because it is the last instruction in the loop), so we need to
1498 nop after the branch to prevent the loop count from being decremented
1499 when the branch is taken. */
1500
1501 void
1502 xtensa_emit_loop_end (rtx insn, rtx *operands)
1503 {
1504 char done = 0;
1505
1506 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1507 {
1508 switch (GET_CODE (insn))
1509 {
1510 case NOTE:
1511 case BARRIER:
1512 break;
1513
1514 case CODE_LABEL:
1515 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1516 done = 1;
1517 break;
1518
1519 default:
1520 {
1521 rtx body = PATTERN (insn);
1522
1523 if (GET_CODE (body) == JUMP_INSN)
1524 {
1525 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1526 done = 1;
1527 }
1528 else if ((GET_CODE (body) != USE)
1529 && (GET_CODE (body) != CLOBBER))
1530 done = 1;
1531 }
1532 break;
1533 }
1534 }
1535
1536 output_asm_insn ("# loop end for %0", operands);
1537 }
1538
1539
1540 char *
1541 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1542 {
1543 static char result[64];
1544 enum rtx_code code;
1545 const char *op;
1546
1547 code = GET_CODE (operands[3]);
1548 switch (code)
1549 {
1550 case EQ: op = inverted ? "ne" : "eq"; break;
1551 case NE: op = inverted ? "eq" : "ne"; break;
1552 case LT: op = inverted ? "ge" : "lt"; break;
1553 case GE: op = inverted ? "lt" : "ge"; break;
1554 case LTU: op = inverted ? "geu" : "ltu"; break;
1555 case GEU: op = inverted ? "ltu" : "geu"; break;
1556 default: gcc_unreachable ();
1557 }
1558
1559 if (immed)
1560 {
1561 if (INTVAL (operands[1]) == 0)
1562 sprintf (result, "b%sz%s\t%%0, %%2", op,
1563 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1564 else
1565 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1566 }
1567 else
1568 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1569
1570 return result;
1571 }
1572
1573
1574 char *
1575 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1576 {
1577 static char result[64];
1578 const char *op;
1579
1580 switch (GET_CODE (operands[3]))
1581 {
1582 case EQ: op = inverted ? "bs" : "bc"; break;
1583 case NE: op = inverted ? "bc" : "bs"; break;
1584 default: gcc_unreachable ();
1585 }
1586
1587 if (immed)
1588 {
1589 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1590 operands[1] = GEN_INT (bitnum);
1591 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1592 }
1593 else
1594 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1595
1596 return result;
1597 }
1598
1599
1600 char *
1601 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1602 {
1603 static char result[64];
1604 enum rtx_code code;
1605 const char *op;
1606
1607 code = GET_CODE (operands[4]);
1608 if (isbool)
1609 {
1610 switch (code)
1611 {
1612 case EQ: op = inverted ? "t" : "f"; break;
1613 case NE: op = inverted ? "f" : "t"; break;
1614 default: gcc_unreachable ();
1615 }
1616 }
1617 else
1618 {
1619 switch (code)
1620 {
1621 case EQ: op = inverted ? "nez" : "eqz"; break;
1622 case NE: op = inverted ? "eqz" : "nez"; break;
1623 case LT: op = inverted ? "gez" : "ltz"; break;
1624 case GE: op = inverted ? "ltz" : "gez"; break;
1625 default: gcc_unreachable ();
1626 }
1627 }
1628
1629 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1630 op, isfp ? ".s" : "", inverted ? 3 : 2);
1631 return result;
1632 }
1633
1634
1635 char *
1636 xtensa_emit_call (int callop, rtx *operands)
1637 {
1638 static char result[64];
1639 rtx tgt = operands[callop];
1640
1641 if (GET_CODE (tgt) == CONST_INT)
1642 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1643 else if (register_operand (tgt, VOIDmode))
1644 sprintf (result, "callx8\t%%%d", callop);
1645 else
1646 sprintf (result, "call8\t%%%d", callop);
1647
1648 return result;
1649 }
1650
1651
1652 bool
1653 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1654 {
1655 /* Allow constant pool addresses. */
1656 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1657 && ! TARGET_CONST16 && constantpool_address_p (addr))
1658 return true;
1659
1660 while (GET_CODE (addr) == SUBREG)
1661 addr = SUBREG_REG (addr);
1662
1663 /* Allow base registers. */
1664 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1665 return true;
1666
1667 /* Check for "register + offset" addressing. */
1668 if (GET_CODE (addr) == PLUS)
1669 {
1670 rtx xplus0 = XEXP (addr, 0);
1671 rtx xplus1 = XEXP (addr, 1);
1672 enum rtx_code code0;
1673 enum rtx_code code1;
1674
1675 while (GET_CODE (xplus0) == SUBREG)
1676 xplus0 = SUBREG_REG (xplus0);
1677 code0 = GET_CODE (xplus0);
1678
1679 while (GET_CODE (xplus1) == SUBREG)
1680 xplus1 = SUBREG_REG (xplus1);
1681 code1 = GET_CODE (xplus1);
1682
1683 /* Swap operands if necessary so the register is first. */
1684 if (code0 != REG && code1 == REG)
1685 {
1686 xplus0 = XEXP (addr, 1);
1687 xplus1 = XEXP (addr, 0);
1688 code0 = GET_CODE (xplus0);
1689 code1 = GET_CODE (xplus1);
1690 }
1691
1692 if (code0 == REG && BASE_REG_P (xplus0, strict)
1693 && code1 == CONST_INT
1694 && xtensa_mem_offset (INTVAL (xplus1), mode))
1695 return true;
1696 }
1697
1698 return false;
1699 }
1700
1701
1702 rtx
1703 xtensa_legitimize_address (rtx x,
1704 rtx oldx ATTRIBUTE_UNUSED,
1705 enum machine_mode mode)
1706 {
1707 if (GET_CODE (x) == PLUS)
1708 {
1709 rtx plus0 = XEXP (x, 0);
1710 rtx plus1 = XEXP (x, 1);
1711
1712 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1713 {
1714 plus0 = XEXP (x, 1);
1715 plus1 = XEXP (x, 0);
1716 }
1717
1718 /* Try to split up the offset to use an ADDMI instruction. */
1719 if (GET_CODE (plus0) == REG
1720 && GET_CODE (plus1) == CONST_INT
1721 && !xtensa_mem_offset (INTVAL (plus1), mode)
1722 && !xtensa_simm8 (INTVAL (plus1))
1723 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1724 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1725 {
1726 rtx temp = gen_reg_rtx (Pmode);
1727 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1728 emit_insn (gen_rtx_SET (Pmode, temp,
1729 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1730 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1731 }
1732 }
1733
1734 return NULL_RTX;
1735 }
1736
1737
1738 /* Return the debugger register number to use for 'regno'. */
1739
1740 int
1741 xtensa_dbx_register_number (int regno)
1742 {
1743 int first = -1;
1744
1745 if (GP_REG_P (regno))
1746 {
1747 regno -= GP_REG_FIRST;
1748 first = 0;
1749 }
1750 else if (BR_REG_P (regno))
1751 {
1752 regno -= BR_REG_FIRST;
1753 first = 16;
1754 }
1755 else if (FP_REG_P (regno))
1756 {
1757 regno -= FP_REG_FIRST;
1758 first = 48;
1759 }
1760 else if (ACC_REG_P (regno))
1761 {
1762 first = 0x200; /* Start of Xtensa special registers. */
1763 regno = 16; /* ACCLO is special register 16. */
1764 }
1765
1766 /* When optimizing, we sometimes get asked about pseudo-registers
1767 that don't represent hard registers. Return 0 for these. */
1768 if (first == -1)
1769 return 0;
1770
1771 return first + regno;
1772 }
1773
1774
1775 /* Argument support functions. */
1776
1777 /* Initialize CUMULATIVE_ARGS for a function. */
1778
1779 void
1780 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
1781 {
1782 cum->arg_words = 0;
1783 cum->incoming = incoming;
1784 }
1785
1786
1787 /* Advance the argument to the next argument position. */
1788
1789 void
1790 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type)
1791 {
1792 int words, max;
1793 int *arg_words;
1794
1795 arg_words = &cum->arg_words;
1796 max = MAX_ARGS_IN_REGISTERS;
1797
1798 words = (((mode != BLKmode)
1799 ? (int) GET_MODE_SIZE (mode)
1800 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1801
1802 if (*arg_words < max
1803 && (targetm.calls.must_pass_in_stack (mode, type)
1804 || *arg_words + words > max))
1805 *arg_words = max;
1806
1807 *arg_words += words;
1808 }
1809
1810
1811 /* Return an RTL expression containing the register for the given mode,
1812 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1813 if this is an incoming argument to the current function. */
1814
1815 rtx
1816 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1817 int incoming_p)
1818 {
1819 int regbase, words, max;
1820 int *arg_words;
1821 int regno;
1822
1823 arg_words = &cum->arg_words;
1824 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
1825 max = MAX_ARGS_IN_REGISTERS;
1826
1827 words = (((mode != BLKmode)
1828 ? (int) GET_MODE_SIZE (mode)
1829 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1830
1831 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
1832 {
1833 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
1834 *arg_words = (*arg_words + align - 1) & -align;
1835 }
1836
1837 if (*arg_words + words > max)
1838 return (rtx)0;
1839
1840 regno = regbase + *arg_words;
1841
1842 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
1843 cfun->machine->need_a7_copy = true;
1844
1845 return gen_rtx_REG (mode, regno);
1846 }
1847
1848
1849 int
1850 function_arg_boundary (enum machine_mode mode, tree type)
1851 {
1852 unsigned int alignment;
1853
1854 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
1855 if (alignment < PARM_BOUNDARY)
1856 alignment = PARM_BOUNDARY;
1857 if (alignment > STACK_BOUNDARY)
1858 alignment = STACK_BOUNDARY;
1859 return alignment;
1860 }
1861
1862
1863 static bool
1864 xtensa_return_in_msb (const_tree valtype)
1865 {
1866 return (TARGET_BIG_ENDIAN
1867 && AGGREGATE_TYPE_P (valtype)
1868 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
1869 }
1870
1871
1872 void
1873 override_options (void)
1874 {
1875 int regno;
1876 enum machine_mode mode;
1877
1878 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
1879 error ("boolean registers required for the floating-point option");
1880
1881 /* Set up array giving whether a given register can hold a given mode. */
1882 for (mode = VOIDmode;
1883 mode != MAX_MACHINE_MODE;
1884 mode = (enum machine_mode) ((int) mode + 1))
1885 {
1886 int size = GET_MODE_SIZE (mode);
1887 enum mode_class class = GET_MODE_CLASS (mode);
1888
1889 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1890 {
1891 int temp;
1892
1893 if (ACC_REG_P (regno))
1894 temp = (TARGET_MAC16
1895 && (class == MODE_INT) && (size <= UNITS_PER_WORD));
1896 else if (GP_REG_P (regno))
1897 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
1898 else if (FP_REG_P (regno))
1899 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
1900 else if (BR_REG_P (regno))
1901 temp = (TARGET_BOOLEANS && (mode == CCmode));
1902 else
1903 temp = FALSE;
1904
1905 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
1906 }
1907 }
1908
1909 init_machine_status = xtensa_init_machine_status;
1910
1911 /* Check PIC settings. PIC is only supported when using L32R
1912 instructions, and some targets need to always use PIC. */
1913 if (flag_pic && TARGET_CONST16)
1914 error ("-f%s is not supported with CONST16 instructions",
1915 (flag_pic > 1 ? "PIC" : "pic"));
1916 else if (XTENSA_ALWAYS_PIC)
1917 {
1918 if (TARGET_CONST16)
1919 error ("PIC is required but not supported with CONST16 instructions");
1920 flag_pic = 1;
1921 }
1922 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1923 if (flag_pic > 1)
1924 flag_pic = 1;
1925 if (flag_pic && !flag_pie)
1926 flag_shlib = 1;
1927
1928 /* Hot/cold partitioning does not work on this architecture, because of
1929 constant pools (the load instruction cannot necessarily reach that far).
1930 Therefore disable it on this architecture. */
1931 if (flag_reorder_blocks_and_partition)
1932 {
1933 flag_reorder_blocks_and_partition = 0;
1934 flag_reorder_blocks = 1;
1935 }
1936 }
1937
1938
1939 /* A C compound statement to output to stdio stream STREAM the
1940 assembler syntax for an instruction operand X. X is an RTL
1941 expression.
1942
1943 CODE is a value that can be used to specify one of several ways
1944 of printing the operand. It is used when identical operands
1945 must be printed differently depending on the context. CODE
1946 comes from the '%' specification that was used to request
1947 printing of the operand. If the specification was just '%DIGIT'
1948 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1949 is the ASCII code for LTR.
1950
1951 If X is a register, this macro should print the register's name.
1952 The names can be found in an array 'reg_names' whose type is
1953 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1954
1955 When the machine description has a specification '%PUNCT' (a '%'
1956 followed by a punctuation character), this macro is called with
1957 a null pointer for X and the punctuation character for CODE.
1958
1959 'a', 'c', 'l', and 'n' are reserved.
1960
1961 The Xtensa specific codes are:
1962
1963 'd' CONST_INT, print as signed decimal
1964 'x' CONST_INT, print as signed hexadecimal
1965 'K' CONST_INT, print number of bits in mask for EXTUI
1966 'R' CONST_INT, print (X & 0x1f)
1967 'L' CONST_INT, print ((32 - X) & 0x1f)
1968 'D' REG, print second register of double-word register operand
1969 'N' MEM, print address of next word following a memory operand
1970 'v' MEM, if memory reference is volatile, output a MEMW before it
1971 't' any constant, add "@h" suffix for top 16 bits
1972 'b' any constant, add "@l" suffix for bottom 16 bits
1973 */
1974
1975 static void
1976 printx (FILE *file, signed int val)
1977 {
1978 /* Print a hexadecimal value in a nice way. */
1979 if ((val > -0xa) && (val < 0xa))
1980 fprintf (file, "%d", val);
1981 else if (val < 0)
1982 fprintf (file, "-0x%x", -val);
1983 else
1984 fprintf (file, "0x%x", val);
1985 }
1986
1987
1988 void
1989 print_operand (FILE *file, rtx x, int letter)
1990 {
1991 if (!x)
1992 error ("PRINT_OPERAND null pointer");
1993
1994 switch (letter)
1995 {
1996 case 'D':
1997 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
1998 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
1999 else
2000 output_operand_lossage ("invalid %%D value");
2001 break;
2002
2003 case 'v':
2004 if (GET_CODE (x) == MEM)
2005 {
2006 /* For a volatile memory reference, emit a MEMW before the
2007 load or store. */
2008 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2009 fprintf (file, "memw\n\t");
2010 }
2011 else
2012 output_operand_lossage ("invalid %%v value");
2013 break;
2014
2015 case 'N':
2016 if (GET_CODE (x) == MEM
2017 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2018 {
2019 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2020 output_address (XEXP (x, 0));
2021 }
2022 else
2023 output_operand_lossage ("invalid %%N value");
2024 break;
2025
2026 case 'K':
2027 if (GET_CODE (x) == CONST_INT)
2028 {
2029 int num_bits = 0;
2030 unsigned val = INTVAL (x);
2031 while (val & 1)
2032 {
2033 num_bits += 1;
2034 val = val >> 1;
2035 }
2036 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2037 fatal_insn ("invalid mask", x);
2038
2039 fprintf (file, "%d", num_bits);
2040 }
2041 else
2042 output_operand_lossage ("invalid %%K value");
2043 break;
2044
2045 case 'L':
2046 if (GET_CODE (x) == CONST_INT)
2047 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2048 else
2049 output_operand_lossage ("invalid %%L value");
2050 break;
2051
2052 case 'R':
2053 if (GET_CODE (x) == CONST_INT)
2054 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2055 else
2056 output_operand_lossage ("invalid %%R value");
2057 break;
2058
2059 case 'x':
2060 if (GET_CODE (x) == CONST_INT)
2061 printx (file, INTVAL (x));
2062 else
2063 output_operand_lossage ("invalid %%x value");
2064 break;
2065
2066 case 'd':
2067 if (GET_CODE (x) == CONST_INT)
2068 fprintf (file, "%ld", INTVAL (x));
2069 else
2070 output_operand_lossage ("invalid %%d value");
2071 break;
2072
2073 case 't':
2074 case 'b':
2075 if (GET_CODE (x) == CONST_INT)
2076 {
2077 printx (file, INTVAL (x));
2078 fputs (letter == 't' ? "@h" : "@l", file);
2079 }
2080 else if (GET_CODE (x) == CONST_DOUBLE)
2081 {
2082 REAL_VALUE_TYPE r;
2083 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2084 if (GET_MODE (x) == SFmode)
2085 {
2086 long l;
2087 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2088 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2089 }
2090 else
2091 output_operand_lossage ("invalid %%t/%%b value");
2092 }
2093 else if (GET_CODE (x) == CONST)
2094 {
2095 /* X must be a symbolic constant on ELF. Write an expression
2096 suitable for 'const16' that sets the high or low 16 bits. */
2097 if (GET_CODE (XEXP (x, 0)) != PLUS
2098 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2099 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2100 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2101 output_operand_lossage ("invalid %%t/%%b value");
2102 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2103 fputs (letter == 't' ? "@h" : "@l", file);
2104 /* There must be a non-alphanumeric character between 'h' or 'l'
2105 and the number. The '-' is added by print_operand() already. */
2106 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2107 fputs ("+", file);
2108 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2109 }
2110 else
2111 {
2112 output_addr_const (file, x);
2113 fputs (letter == 't' ? "@h" : "@l", file);
2114 }
2115 break;
2116
2117 default:
2118 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2119 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2120 else if (GET_CODE (x) == MEM)
2121 output_address (XEXP (x, 0));
2122 else if (GET_CODE (x) == CONST_INT)
2123 fprintf (file, "%ld", INTVAL (x));
2124 else
2125 output_addr_const (file, x);
2126 }
2127 }
2128
2129
2130 /* A C compound statement to output to stdio stream STREAM the
2131 assembler syntax for an instruction operand that is a memory
2132 reference whose address is ADDR. ADDR is an RTL expression. */
2133
2134 void
2135 print_operand_address (FILE *file, rtx addr)
2136 {
2137 if (!addr)
2138 error ("PRINT_OPERAND_ADDRESS, null pointer");
2139
2140 switch (GET_CODE (addr))
2141 {
2142 default:
2143 fatal_insn ("invalid address", addr);
2144 break;
2145
2146 case REG:
2147 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2148 break;
2149
2150 case PLUS:
2151 {
2152 rtx reg = (rtx)0;
2153 rtx offset = (rtx)0;
2154 rtx arg0 = XEXP (addr, 0);
2155 rtx arg1 = XEXP (addr, 1);
2156
2157 if (GET_CODE (arg0) == REG)
2158 {
2159 reg = arg0;
2160 offset = arg1;
2161 }
2162 else if (GET_CODE (arg1) == REG)
2163 {
2164 reg = arg1;
2165 offset = arg0;
2166 }
2167 else
2168 fatal_insn ("no register in address", addr);
2169
2170 if (CONSTANT_P (offset))
2171 {
2172 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2173 output_addr_const (file, offset);
2174 }
2175 else
2176 fatal_insn ("address offset not a constant", addr);
2177 }
2178 break;
2179
2180 case LABEL_REF:
2181 case SYMBOL_REF:
2182 case CONST_INT:
2183 case CONST:
2184 output_addr_const (file, addr);
2185 break;
2186 }
2187 }
2188
2189
2190 bool
2191 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2192 {
2193 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2194 {
2195 switch (XINT (x, 1))
2196 {
2197 case UNSPEC_PLT:
2198 if (flag_pic)
2199 {
2200 output_addr_const (fp, XVECEXP (x, 0, 0));
2201 fputs ("@PLT", fp);
2202 return true;
2203 }
2204 break;
2205 default:
2206 break;
2207 }
2208 }
2209 return false;
2210 }
2211
2212
2213 void
2214 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2215 {
2216 long value_long[2];
2217 REAL_VALUE_TYPE r;
2218 int size;
2219 rtx first, second;
2220
2221 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2222
2223 switch (GET_MODE_CLASS (mode))
2224 {
2225 case MODE_FLOAT:
2226 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2227
2228 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2229 switch (mode)
2230 {
2231 case SFmode:
2232 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2233 if (HOST_BITS_PER_LONG > 32)
2234 value_long[0] &= 0xffffffff;
2235 fprintf (file, "0x%08lx\n", value_long[0]);
2236 break;
2237
2238 case DFmode:
2239 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2240 if (HOST_BITS_PER_LONG > 32)
2241 {
2242 value_long[0] &= 0xffffffff;
2243 value_long[1] &= 0xffffffff;
2244 }
2245 fprintf (file, "0x%08lx, 0x%08lx\n",
2246 value_long[0], value_long[1]);
2247 break;
2248
2249 default:
2250 gcc_unreachable ();
2251 }
2252
2253 break;
2254
2255 case MODE_INT:
2256 case MODE_PARTIAL_INT:
2257 size = GET_MODE_SIZE (mode);
2258 switch (size)
2259 {
2260 case 4:
2261 output_addr_const (file, x);
2262 fputs ("\n", file);
2263 break;
2264
2265 case 8:
2266 split_double (x, &first, &second);
2267 output_addr_const (file, first);
2268 fputs (", ", file);
2269 output_addr_const (file, second);
2270 fputs ("\n", file);
2271 break;
2272
2273 default:
2274 gcc_unreachable ();
2275 }
2276 break;
2277
2278 default:
2279 gcc_unreachable ();
2280 }
2281 }
2282
2283
2284 /* Return the bytes needed to compute the frame pointer from the current
2285 stack pointer. */
2286
2287 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2288 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2289
2290 long
2291 compute_frame_size (int size)
2292 {
2293 /* Add space for the incoming static chain value. */
2294 if (cfun->static_chain_decl != NULL)
2295 size += (1 * UNITS_PER_WORD);
2296
2297 xtensa_current_frame_size =
2298 XTENSA_STACK_ALIGN (size
2299 + crtl->outgoing_args_size
2300 + (WINDOW_SIZE * UNITS_PER_WORD));
2301 return xtensa_current_frame_size;
2302 }
2303
2304
2305 int
2306 xtensa_frame_pointer_required (void)
2307 {
2308 /* The code to expand builtin_frame_addr and builtin_return_addr
2309 currently uses the hard_frame_pointer instead of frame_pointer.
2310 This seems wrong but maybe it's necessary for other architectures.
2311 This function is derived from the i386 code. */
2312
2313 if (cfun->machine->accesses_prev_frame)
2314 return 1;
2315
2316 return 0;
2317 }
2318
2319
2320 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2321 and the total number of words must be a multiple of 128 bits. */
2322 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2323
2324 void
2325 xtensa_expand_prologue (void)
2326 {
2327 HOST_WIDE_INT total_size;
2328 rtx size_rtx;
2329 rtx insn, note_rtx;
2330
2331 total_size = compute_frame_size (get_frame_size ());
2332 size_rtx = GEN_INT (total_size);
2333
2334 if (total_size < (1 << (12+3)))
2335 insn = emit_insn (gen_entry (size_rtx));
2336 else
2337 {
2338 /* Use a8 as a temporary since a0-a7 may be live. */
2339 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2340 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2341 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2342 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2343 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2344 }
2345
2346 if (frame_pointer_needed)
2347 {
2348 if (cfun->machine->set_frame_ptr_insn)
2349 {
2350 rtx first;
2351
2352 push_topmost_sequence ();
2353 first = get_insns ();
2354 pop_topmost_sequence ();
2355
2356 /* For all instructions prior to set_frame_ptr_insn, replace
2357 hard_frame_pointer references with stack_pointer. */
2358 for (insn = first;
2359 insn != cfun->machine->set_frame_ptr_insn;
2360 insn = NEXT_INSN (insn))
2361 {
2362 if (INSN_P (insn))
2363 {
2364 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2365 hard_frame_pointer_rtx,
2366 stack_pointer_rtx);
2367 df_insn_rescan (insn);
2368 }
2369 }
2370 }
2371 else
2372 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2373 stack_pointer_rtx));
2374 }
2375
2376 /* Create a note to describe the CFA. Because this is only used to set
2377 DW_AT_frame_base for debug info, don't bother tracking changes through
2378 each instruction in the prologue. It just takes up space. */
2379 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2380 ? hard_frame_pointer_rtx
2381 : stack_pointer_rtx),
2382 plus_constant (stack_pointer_rtx, -total_size));
2383 RTX_FRAME_RELATED_P (insn) = 1;
2384 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2385 note_rtx, REG_NOTES (insn));
2386 }
2387
2388
2389 /* Clear variables at function end. */
2390
2391 void
2392 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2393 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2394 {
2395 xtensa_current_frame_size = 0;
2396 }
2397
2398
2399 rtx
2400 xtensa_return_addr (int count, rtx frame)
2401 {
2402 rtx result, retaddr, curaddr, label;
2403
2404 if (count == -1)
2405 retaddr = gen_rtx_REG (Pmode, A0_REG);
2406 else
2407 {
2408 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2409 addr = memory_address (Pmode, addr);
2410 retaddr = gen_reg_rtx (Pmode);
2411 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2412 }
2413
2414 /* The 2 most-significant bits of the return address on Xtensa hold
2415 the register window size. To get the real return address, these
2416 bits must be replaced with the high bits from some address in the
2417 code. */
2418
2419 /* Get the 2 high bits of a local label in the code. */
2420 curaddr = gen_reg_rtx (Pmode);
2421 label = gen_label_rtx ();
2422 emit_label (label);
2423 LABEL_PRESERVE_P (label) = 1;
2424 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2425 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2426 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2427
2428 /* Clear the 2 high bits of the return address. */
2429 result = gen_reg_rtx (Pmode);
2430 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2431 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2432
2433 /* Combine them to get the result. */
2434 emit_insn (gen_iorsi3 (result, result, curaddr));
2435 return result;
2436 }
2437
2438
2439 /* Create the va_list data type.
2440
2441 This structure is set up by __builtin_saveregs. The __va_reg field
2442 points to a stack-allocated region holding the contents of the
2443 incoming argument registers. The __va_ndx field is an index
2444 initialized to the position of the first unnamed (variable)
2445 argument. This same index is also used to address the arguments
2446 passed in memory. Thus, the __va_stk field is initialized to point
2447 to the position of the first argument in memory offset to account
2448 for the arguments passed in registers and to account for the size
2449 of the argument registers not being 16-byte aligned. E.G., there
2450 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2451 for the first stack argument to have the maximal alignment of 16
2452 bytes, so we offset the __va_stk address by 32 bytes so that
2453 __va_stk[32] references the first argument on the stack. */
2454
2455 static tree
2456 xtensa_build_builtin_va_list (void)
2457 {
2458 tree f_stk, f_reg, f_ndx, record, type_decl;
2459
2460 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2461 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2462
2463 f_stk = build_decl (FIELD_DECL, get_identifier ("__va_stk"),
2464 ptr_type_node);
2465 f_reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"),
2466 ptr_type_node);
2467 f_ndx = build_decl (FIELD_DECL, get_identifier ("__va_ndx"),
2468 integer_type_node);
2469
2470 DECL_FIELD_CONTEXT (f_stk) = record;
2471 DECL_FIELD_CONTEXT (f_reg) = record;
2472 DECL_FIELD_CONTEXT (f_ndx) = record;
2473
2474 TREE_CHAIN (record) = type_decl;
2475 TYPE_NAME (record) = type_decl;
2476 TYPE_FIELDS (record) = f_stk;
2477 TREE_CHAIN (f_stk) = f_reg;
2478 TREE_CHAIN (f_reg) = f_ndx;
2479
2480 layout_type (record);
2481 return record;
2482 }
2483
2484
2485 /* Save the incoming argument registers on the stack. Returns the
2486 address of the saved registers. */
2487
2488 static rtx
2489 xtensa_builtin_saveregs (void)
2490 {
2491 rtx gp_regs;
2492 int arg_words = crtl->args.info.arg_words;
2493 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2494
2495 if (gp_left <= 0)
2496 return const0_rtx;
2497
2498 /* Allocate the general-purpose register space. */
2499 gp_regs = assign_stack_local
2500 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2501 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2502
2503 /* Now store the incoming registers. */
2504 cfun->machine->need_a7_copy = true;
2505 cfun->machine->vararg_a7 = true;
2506 move_block_from_reg (GP_ARG_FIRST + arg_words,
2507 adjust_address (gp_regs, BLKmode,
2508 arg_words * UNITS_PER_WORD),
2509 gp_left);
2510 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2511 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2512
2513 return XEXP (gp_regs, 0);
2514 }
2515
2516
2517 /* Implement `va_start' for varargs and stdarg. We look at the
2518 current function to fill in an initial va_list. */
2519
2520 static void
2521 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2522 {
2523 tree f_stk, stk;
2524 tree f_reg, reg;
2525 tree f_ndx, ndx;
2526 tree t, u;
2527 int arg_words;
2528
2529 arg_words = crtl->args.info.arg_words;
2530
2531 f_stk = TYPE_FIELDS (va_list_type_node);
2532 f_reg = TREE_CHAIN (f_stk);
2533 f_ndx = TREE_CHAIN (f_reg);
2534
2535 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2536 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2537 f_reg, NULL_TREE);
2538 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2539 f_ndx, NULL_TREE);
2540
2541 /* Call __builtin_saveregs; save the result in __va_reg */
2542 u = make_tree (sizetype, expand_builtin_saveregs ());
2543 u = fold_convert (ptr_type_node, u);
2544 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2545 TREE_SIDE_EFFECTS (t) = 1;
2546 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2547
2548 /* Set the __va_stk member to ($arg_ptr - 32). */
2549 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2550 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2551 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2552 TREE_SIDE_EFFECTS (t) = 1;
2553 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2554
2555 /* Set the __va_ndx member. If the first variable argument is on
2556 the stack, adjust __va_ndx by 2 words to account for the extra
2557 alignment offset for __va_stk. */
2558 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2559 arg_words += 2;
2560 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2561 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2562 TREE_SIDE_EFFECTS (t) = 1;
2563 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2564 }
2565
2566
2567 /* Implement `va_arg'. */
2568
2569 static tree
2570 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2571 gimple_seq *post_p ATTRIBUTE_UNUSED)
2572 {
2573 tree f_stk, stk;
2574 tree f_reg, reg;
2575 tree f_ndx, ndx;
2576 tree type_size, array, orig_ndx, addr, size, va_size, t;
2577 tree lab_false, lab_over, lab_false2;
2578 bool indirect;
2579
2580 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2581 if (indirect)
2582 type = build_pointer_type (type);
2583
2584 /* Handle complex values as separate real and imaginary parts. */
2585 if (TREE_CODE (type) == COMPLEX_TYPE)
2586 {
2587 tree real_part, imag_part;
2588
2589 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2590 pre_p, NULL);
2591 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2592
2593 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2594 TREE_TYPE (type),
2595 pre_p, NULL);
2596 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2597
2598 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2599 }
2600
2601 f_stk = TYPE_FIELDS (va_list_type_node);
2602 f_reg = TREE_CHAIN (f_stk);
2603 f_ndx = TREE_CHAIN (f_reg);
2604
2605 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2606 f_stk, NULL_TREE);
2607 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2608 f_reg, NULL_TREE);
2609 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2610 f_ndx, NULL_TREE);
2611
2612 type_size = size_in_bytes (type);
2613 va_size = round_up (type_size, UNITS_PER_WORD);
2614 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2615
2616
2617 /* First align __va_ndx if necessary for this arg:
2618
2619 orig_ndx = (AP).__va_ndx;
2620 if (__alignof__ (TYPE) > 4 )
2621 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2622 & -__alignof__ (TYPE)); */
2623
2624 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2625
2626 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2627 {
2628 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2629
2630 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2631 build_int_cst (integer_type_node, align - 1));
2632 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2633 build_int_cst (integer_type_node, -align));
2634 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2635 }
2636
2637
2638 /* Increment __va_ndx to point past the argument:
2639
2640 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2641
2642 t = fold_convert (integer_type_node, va_size);
2643 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2644 gimplify_assign (unshare_expr (ndx), t, pre_p);
2645
2646
2647 /* Check if the argument is in registers:
2648
2649 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2650 && !must_pass_in_stack (type))
2651 __array = (AP).__va_reg; */
2652
2653 array = create_tmp_var (ptr_type_node, NULL);
2654
2655 lab_over = NULL;
2656 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2657 {
2658 lab_false = create_artificial_label ();
2659 lab_over = create_artificial_label ();
2660
2661 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2662 build_int_cst (integer_type_node,
2663 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2664 t = build3 (COND_EXPR, void_type_node, t,
2665 build1 (GOTO_EXPR, void_type_node, lab_false),
2666 NULL_TREE);
2667 gimplify_and_add (t, pre_p);
2668
2669 gimplify_assign (unshare_expr (array), reg, pre_p);
2670
2671 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2672 gimplify_and_add (t, pre_p);
2673
2674 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2675 gimplify_and_add (t, pre_p);
2676 }
2677
2678
2679 /* ...otherwise, the argument is on the stack (never split between
2680 registers and the stack -- change __va_ndx if necessary):
2681
2682 else
2683 {
2684 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2685 (AP).__va_ndx = 32 + __va_size (TYPE);
2686 __array = (AP).__va_stk;
2687 } */
2688
2689 lab_false2 = create_artificial_label ();
2690
2691 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
2692 build_int_cst (integer_type_node,
2693 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2694 t = build3 (COND_EXPR, void_type_node, t,
2695 build1 (GOTO_EXPR, void_type_node, lab_false2),
2696 NULL_TREE);
2697 gimplify_and_add (t, pre_p);
2698
2699 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
2700 t = fold_convert (integer_type_node, t);
2701 gimplify_assign (unshare_expr (ndx), t, pre_p);
2702
2703 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2704 gimplify_and_add (t, pre_p);
2705
2706 gimplify_assign (array, stk, pre_p);
2707
2708 if (lab_over)
2709 {
2710 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2711 gimplify_and_add (t, pre_p);
2712 }
2713
2714
2715 /* Given the base array pointer (__array) and index to the subsequent
2716 argument (__va_ndx), find the address:
2717
2718 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2719 ? sizeof (TYPE)
2720 : __va_size (TYPE))
2721
2722 The results are endian-dependent because values smaller than one word
2723 are aligned differently. */
2724
2725
2726 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2727 {
2728 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
2729 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2730 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
2731 unshare_expr (type_size));
2732 size = t;
2733 }
2734 else
2735 size = unshare_expr (va_size);
2736
2737 t = fold_convert (sizetype, unshare_expr (ndx));
2738 t = build2 (MINUS_EXPR, sizetype, t, size);
2739 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, unshare_expr (array), t);
2740
2741 addr = fold_convert (build_pointer_type (type), addr);
2742 if (indirect)
2743 addr = build_va_arg_indirect_ref (addr);
2744 return build_va_arg_indirect_ref (addr);
2745 }
2746
2747
2748 /* Builtins. */
2749
2750 enum xtensa_builtin
2751 {
2752 XTENSA_BUILTIN_UMULSIDI3,
2753 XTENSA_BUILTIN_max
2754 };
2755
2756
2757 static void
2758 xtensa_init_builtins (void)
2759 {
2760 tree ftype;
2761
2762 ftype = build_function_type_list (unsigned_intDI_type_node,
2763 unsigned_intSI_type_node,
2764 unsigned_intSI_type_node, NULL_TREE);
2765
2766 add_builtin_function ("__builtin_umulsidi3", ftype,
2767 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
2768 "__umulsidi3", NULL_TREE);
2769 }
2770
2771
2772 static tree
2773 xtensa_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
2774 {
2775 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2776 tree arg0, arg1;
2777
2778 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2779 {
2780 arg0 = TREE_VALUE (arglist);
2781 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
2782 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
2783 || TARGET_MUL32_HIGH)
2784 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
2785 fold_convert (unsigned_intDI_type_node, arg0),
2786 fold_convert (unsigned_intDI_type_node, arg1));
2787 else
2788 return NULL;
2789 }
2790
2791 internal_error ("bad builtin code");
2792 return NULL;
2793 }
2794
2795
2796 static rtx
2797 xtensa_expand_builtin (tree exp, rtx target,
2798 rtx subtarget ATTRIBUTE_UNUSED,
2799 enum machine_mode mode ATTRIBUTE_UNUSED,
2800 int ignore)
2801 {
2802 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2803 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2804
2805 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2806 __umulsidi3 function when the Xtensa configuration can directly
2807 implement it. If not, just call the function. */
2808 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2809 return expand_call (exp, target, ignore);
2810
2811 internal_error ("bad builtin code");
2812 return NULL_RTX;
2813 }
2814
2815
2816 enum reg_class
2817 xtensa_preferred_reload_class (rtx x, enum reg_class class, int isoutput)
2818 {
2819 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
2820 return NO_REGS;
2821
2822 /* Don't use the stack pointer or hard frame pointer for reloads!
2823 The hard frame pointer would normally be OK except that it may
2824 briefly hold an incoming argument in the prologue, and reload
2825 won't know that it is live because the hard frame pointer is
2826 treated specially. */
2827
2828 if (class == AR_REGS || class == GR_REGS)
2829 return RL_REGS;
2830
2831 return class;
2832 }
2833
2834
2835 enum reg_class
2836 xtensa_secondary_reload_class (enum reg_class class,
2837 enum machine_mode mode ATTRIBUTE_UNUSED,
2838 rtx x, int isoutput)
2839 {
2840 int regno;
2841
2842 if (GET_CODE (x) == SIGN_EXTEND)
2843 x = XEXP (x, 0);
2844 regno = xt_true_regnum (x);
2845
2846 if (!isoutput)
2847 {
2848 if ((class == FP_REGS || GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2849 && constantpool_mem_p (x))
2850 return RL_REGS;
2851 }
2852
2853 if (ACC_REG_P (regno))
2854 return ((class == GR_REGS || class == RL_REGS) ? NO_REGS : RL_REGS);
2855 if (class == ACC_REG)
2856 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
2857
2858 return NO_REGS;
2859 }
2860
2861
2862 void
2863 order_regs_for_local_alloc (void)
2864 {
2865 if (!leaf_function_p ())
2866 {
2867 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
2868 FIRST_PSEUDO_REGISTER * sizeof (int));
2869 }
2870 else
2871 {
2872 int i, num_arg_regs;
2873 int nxt = 0;
2874
2875 /* Use the AR registers in increasing order (skipping a0 and a1)
2876 but save the incoming argument registers for a last resort. */
2877 num_arg_regs = crtl->args.info.arg_words;
2878 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
2879 num_arg_regs = MAX_ARGS_IN_REGISTERS;
2880 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
2881 reg_alloc_order[nxt++] = i + num_arg_regs;
2882 for (i = 0; i < num_arg_regs; i++)
2883 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
2884
2885 /* List the coprocessor registers in order. */
2886 for (i = 0; i < BR_REG_NUM; i++)
2887 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
2888
2889 /* List the FP registers in order for now. */
2890 for (i = 0; i < 16; i++)
2891 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
2892
2893 /* GCC requires that we list *all* the registers.... */
2894 reg_alloc_order[nxt++] = 0; /* a0 = return address */
2895 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
2896 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
2897 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
2898
2899 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
2900 }
2901 }
2902
2903
2904 /* Some Xtensa targets support multiple bss sections. If the section
2905 name ends with ".bss", add SECTION_BSS to the flags. */
2906
2907 static unsigned int
2908 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
2909 {
2910 unsigned int flags = default_section_type_flags (decl, name, reloc);
2911 const char *suffix;
2912
2913 suffix = strrchr (name, '.');
2914 if (suffix && strcmp (suffix, ".bss") == 0)
2915 {
2916 if (!decl || (TREE_CODE (decl) == VAR_DECL
2917 && DECL_INITIAL (decl) == NULL_TREE))
2918 flags |= SECTION_BSS; /* @nobits */
2919 else
2920 warning (0, "only uninitialized variables can be placed in a "
2921 ".bss section");
2922 }
2923
2924 return flags;
2925 }
2926
2927
2928 /* The literal pool stays with the function. */
2929
2930 static section *
2931 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
2932 rtx x ATTRIBUTE_UNUSED,
2933 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
2934 {
2935 return function_section (current_function_decl);
2936 }
2937
2938
2939 /* Compute a (partial) cost for rtx X. Return true if the complete
2940 cost has been computed, and false if subexpressions should be
2941 scanned. In either case, *TOTAL contains the cost result. */
2942
2943 static bool
2944 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total)
2945 {
2946 switch (code)
2947 {
2948 case CONST_INT:
2949 switch (outer_code)
2950 {
2951 case SET:
2952 if (xtensa_simm12b (INTVAL (x)))
2953 {
2954 *total = 4;
2955 return true;
2956 }
2957 break;
2958 case PLUS:
2959 if (xtensa_simm8 (INTVAL (x))
2960 || xtensa_simm8x256 (INTVAL (x)))
2961 {
2962 *total = 0;
2963 return true;
2964 }
2965 break;
2966 case AND:
2967 if (xtensa_mask_immediate (INTVAL (x)))
2968 {
2969 *total = 0;
2970 return true;
2971 }
2972 break;
2973 case COMPARE:
2974 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
2975 {
2976 *total = 0;
2977 return true;
2978 }
2979 break;
2980 case ASHIFT:
2981 case ASHIFTRT:
2982 case LSHIFTRT:
2983 case ROTATE:
2984 case ROTATERT:
2985 /* No way to tell if X is the 2nd operand so be conservative. */
2986 default: break;
2987 }
2988 if (xtensa_simm12b (INTVAL (x)))
2989 *total = 5;
2990 else if (TARGET_CONST16)
2991 *total = COSTS_N_INSNS (2);
2992 else
2993 *total = 6;
2994 return true;
2995
2996 case CONST:
2997 case LABEL_REF:
2998 case SYMBOL_REF:
2999 if (TARGET_CONST16)
3000 *total = COSTS_N_INSNS (2);
3001 else
3002 *total = 5;
3003 return true;
3004
3005 case CONST_DOUBLE:
3006 if (TARGET_CONST16)
3007 *total = COSTS_N_INSNS (4);
3008 else
3009 *total = 7;
3010 return true;
3011
3012 case MEM:
3013 {
3014 int num_words =
3015 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3016
3017 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3018 *total = COSTS_N_INSNS (num_words);
3019 else
3020 *total = COSTS_N_INSNS (2*num_words);
3021 return true;
3022 }
3023
3024 case FFS:
3025 case CTZ:
3026 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3027 return true;
3028
3029 case CLZ:
3030 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3031 return true;
3032
3033 case NOT:
3034 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3035 return true;
3036
3037 case AND:
3038 case IOR:
3039 case XOR:
3040 if (GET_MODE (x) == DImode)
3041 *total = COSTS_N_INSNS (2);
3042 else
3043 *total = COSTS_N_INSNS (1);
3044 return true;
3045
3046 case ASHIFT:
3047 case ASHIFTRT:
3048 case LSHIFTRT:
3049 if (GET_MODE (x) == DImode)
3050 *total = COSTS_N_INSNS (50);
3051 else
3052 *total = COSTS_N_INSNS (1);
3053 return true;
3054
3055 case ABS:
3056 {
3057 enum machine_mode xmode = GET_MODE (x);
3058 if (xmode == SFmode)
3059 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3060 else if (xmode == DFmode)
3061 *total = COSTS_N_INSNS (50);
3062 else
3063 *total = COSTS_N_INSNS (4);
3064 return true;
3065 }
3066
3067 case PLUS:
3068 case MINUS:
3069 {
3070 enum machine_mode xmode = GET_MODE (x);
3071 if (xmode == SFmode)
3072 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3073 else if (xmode == DFmode || xmode == DImode)
3074 *total = COSTS_N_INSNS (50);
3075 else
3076 *total = COSTS_N_INSNS (1);
3077 return true;
3078 }
3079
3080 case NEG:
3081 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3082 return true;
3083
3084 case MULT:
3085 {
3086 enum machine_mode xmode = GET_MODE (x);
3087 if (xmode == SFmode)
3088 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3089 else if (xmode == DFmode)
3090 *total = COSTS_N_INSNS (50);
3091 else if (xmode == DImode)
3092 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3093 else if (TARGET_MUL32)
3094 *total = COSTS_N_INSNS (4);
3095 else if (TARGET_MAC16)
3096 *total = COSTS_N_INSNS (16);
3097 else if (TARGET_MUL16)
3098 *total = COSTS_N_INSNS (12);
3099 else
3100 *total = COSTS_N_INSNS (50);
3101 return true;
3102 }
3103
3104 case DIV:
3105 case MOD:
3106 {
3107 enum machine_mode xmode = GET_MODE (x);
3108 if (xmode == SFmode)
3109 {
3110 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3111 return true;
3112 }
3113 else if (xmode == DFmode)
3114 {
3115 *total = COSTS_N_INSNS (50);
3116 return true;
3117 }
3118 }
3119 /* Fall through. */
3120
3121 case UDIV:
3122 case UMOD:
3123 {
3124 enum machine_mode xmode = GET_MODE (x);
3125 if (xmode == DImode)
3126 *total = COSTS_N_INSNS (50);
3127 else if (TARGET_DIV32)
3128 *total = COSTS_N_INSNS (32);
3129 else
3130 *total = COSTS_N_INSNS (50);
3131 return true;
3132 }
3133
3134 case SQRT:
3135 if (GET_MODE (x) == SFmode)
3136 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3137 else
3138 *total = COSTS_N_INSNS (50);
3139 return true;
3140
3141 case SMIN:
3142 case UMIN:
3143 case SMAX:
3144 case UMAX:
3145 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3146 return true;
3147
3148 case SIGN_EXTRACT:
3149 case SIGN_EXTEND:
3150 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3151 return true;
3152
3153 case ZERO_EXTRACT:
3154 case ZERO_EXTEND:
3155 *total = COSTS_N_INSNS (1);
3156 return true;
3157
3158 default:
3159 return false;
3160 }
3161 }
3162
3163 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3164
3165 static bool
3166 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3167 {
3168 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3169 > 4 * UNITS_PER_WORD);
3170 }
3171
3172 /* Worker function for TARGET_FUNCTION_VALUE. */
3173
3174 rtx
3175 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3176 bool outgoing)
3177 {
3178 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3179 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3180 ? SImode : TYPE_MODE (valtype),
3181 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3182 }
3183
3184 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3185 instruction with a minimal stack frame in order to get some free
3186 registers. Once the actual call target is known, the proper stack frame
3187 size is extracted from the ENTRY instruction at the target and the
3188 current frame is adjusted to match. The trampoline then transfers
3189 control to the instruction following the ENTRY at the target. Note:
3190 this assumes that the target begins with an ENTRY instruction. */
3191
3192 void
3193 xtensa_trampoline_template (FILE *stream)
3194 {
3195 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3196
3197 fprintf (stream, "\t.begin no-transform\n");
3198 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3199
3200 if (use_call0)
3201 {
3202 /* Save the return address. */
3203 fprintf (stream, "\tmov\ta10, a0\n");
3204
3205 /* Use a CALL0 instruction to skip past the constants and in the
3206 process get the PC into A0. This allows PC-relative access to
3207 the constants without relying on L32R. */
3208 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3209 }
3210 else
3211 fprintf (stream, "\tj\t.Lskipconsts\n");
3212
3213 fprintf (stream, "\t.align\t4\n");
3214 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3215 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3216 fprintf (stream, ".Lskipconsts:\n");
3217
3218 /* Load the static chain and function address from the trampoline. */
3219 if (use_call0)
3220 {
3221 fprintf (stream, "\taddi\ta0, a0, 3\n");
3222 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3223 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3224 }
3225 else
3226 {
3227 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3228 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3229 }
3230
3231 /* Store the static chain. */
3232 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3233
3234 /* Set the proper stack pointer value. */
3235 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3236 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3237 TARGET_BIG_ENDIAN ? 8 : 12);
3238 fprintf (stream, "\tslli\ta9, a9, 3\n");
3239 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3240 fprintf (stream, "\tsub\ta9, sp, a9\n");
3241 fprintf (stream, "\tmovsp\tsp, a9\n");
3242
3243 if (use_call0)
3244 /* Restore the return address. */
3245 fprintf (stream, "\tmov\ta0, a10\n");
3246
3247 /* Jump to the instruction following the ENTRY. */
3248 fprintf (stream, "\taddi\ta8, a8, 3\n");
3249 fprintf (stream, "\tjx\ta8\n");
3250
3251 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3252 if (use_call0)
3253 fprintf (stream, "\t.byte\t0\n");
3254 else
3255 fprintf (stream, "\tnop\n");
3256
3257 fprintf (stream, "\t.end no-transform\n");
3258 }
3259
3260
3261 void
3262 xtensa_initialize_trampoline (rtx addr, rtx func, rtx chain)
3263 {
3264 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3265 int chain_off = use_call0 ? 12 : 8;
3266 int func_off = use_call0 ? 16 : 12;
3267 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, chain_off)), chain);
3268 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, func_off)), func);
3269 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3270 0, VOIDmode, 1, addr, Pmode);
3271 }
3272
3273
3274 #include "gt-xtensa.h"
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