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1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
58 /* Not really meaningful values, but at least something. */
59 #ifndef SIMULTANEOUS_PREFETCHES
60 #define SIMULTANEOUS_PREFETCHES 3
61 #endif
62 #ifndef PREFETCH_BLOCK
63 #define PREFETCH_BLOCK 32
64 #endif
65 #ifndef HAVE_prefetch
66 #define HAVE_prefetch 0
67 #define CODE_FOR_prefetch 0
68 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
69 #endif
71 /* Give up the prefetch optimizations once we exceed a given threshhold.
72 It is unlikely that we would be able to optimize something in a loop
73 with so many detected prefetches. */
74 #define MAX_PREFETCHES 100
75 /* The number of prefetch blocks that are beneficial to fetch at once before
76 a loop with a known (and low) iteration count. */
77 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
78 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
79 since it is likely that the data are already in the cache. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* Parameterize some prefetch heuristics so they can be turned on and off
83 easily for performance testing on new architecures. These can be
84 defined in target-dependent files. */
86 /* Prefetch is worthwhile only when loads/stores are dense. */
87 #ifndef PREFETCH_ONLY_DENSE_MEM
88 #define PREFETCH_ONLY_DENSE_MEM 1
89 #endif
91 /* Define what we mean by "dense" loads and stores; This value divided by 256
92 is the minimum percentage of memory references that worth prefetching. */
93 #ifndef PREFETCH_DENSE_MEM
94 #define PREFETCH_DENSE_MEM 220
95 #endif
97 /* Do not prefetch for a loop whose iteration count is known to be low. */
98 #ifndef PREFETCH_NO_LOW_LOOPCNT
99 #define PREFETCH_NO_LOW_LOOPCNT 1
100 #endif
102 /* Define what we mean by a "low" iteration count. */
103 #ifndef PREFETCH_LOW_LOOPCNT
104 #define PREFETCH_LOW_LOOPCNT 32
105 #endif
107 /* Do not prefetch for a loop that contains a function call; such a loop is
108 probably not an internal loop. */
109 #ifndef PREFETCH_NO_CALL
110 #define PREFETCH_NO_CALL 1
111 #endif
113 /* Do not prefetch accesses with an extreme stride. */
114 #ifndef PREFETCH_NO_EXTREME_STRIDE
115 #define PREFETCH_NO_EXTREME_STRIDE 1
116 #endif
118 /* Define what we mean by an "extreme" stride. */
119 #ifndef PREFETCH_EXTREME_STRIDE
120 #define PREFETCH_EXTREME_STRIDE 4096
121 #endif
123 /* Define a limit to how far apart indices can be and still be merged
124 into a single prefetch. */
125 #ifndef PREFETCH_EXTREME_DIFFERENCE
126 #define PREFETCH_EXTREME_DIFFERENCE 4096
127 #endif
129 /* Issue prefetch instructions before the loop to fetch data to be used
130 in the first few loop iterations. */
131 #ifndef PREFETCH_BEFORE_LOOP
132 #define PREFETCH_BEFORE_LOOP 1
133 #endif
135 /* Do not handle reversed order prefetches (negative stride). */
136 #ifndef PREFETCH_NO_REVERSE_ORDER
137 #define PREFETCH_NO_REVERSE_ORDER 1
138 #endif
140 /* Prefetch even if the GIV is in conditional code. */
141 #ifndef PREFETCH_CONDITIONAL
142 #define PREFETCH_CONDITIONAL 1
143 #endif
145 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
146 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
148 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
150 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
152 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
153 ((REGNO) < FIRST_PSEUDO_REGISTER \
154 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
157 /* Vector mapping INSN_UIDs to luids.
158 The luids are like uids but increase monotonically always.
159 We use them to see whether a jump comes from outside a given loop. */
163 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
164 number the insn is contained in. */
168 /* 1 + largest uid of any insn. */
172 /* 1 + luid of last insn. */
176 /* Number of loops detected in current function. Used as index to the
177 next few tables. */
181 /* Bound on pseudo register number before loop optimization.
182 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
185 /* The value to pass to the next call of reg_scan_update. */
187 \f
188 /* During the analysis of a loop, a chain of `struct movable's
189 is made to record all the movable insns found.
190 Then the entire chain can be scanned to decide which to move. */
192 struct movable
193 {
198 of any registers used within the LIBCALL. */
200 that must be moved with this one. */
203 may be adjusted when matching movables
204 that load the same value are found. */
206 including other movables that force this
207 or match this one. */
211 /* If PARTIAL is 1, GLOBAL means something different:
212 that the reg is live outside the range from where it is set
213 to the following label. */
217 In particular, moving it does not make it
218 invariant. */
220 load SRC, rather than copying INSN. */
222 first insn of a consecutive sets group. */
225 that we should avoid changing when clearing
226 the rest of the reg. */
230 };
235 /* Forward declarations. */
250 #if 0
252 #endif
282 rtx *));
365 {
366 rtx r1;
367 rtx r2;
371 {
372 rtx match;
373 rtx replacement;
374 rtx insn;
377 /* Nonzero iff INSN is between START and END, inclusive. */
378 #define INSN_IN_RANGE_P(INSN, START, END) \
379 (INSN_UID (INSN) < max_uid_for_loop \
380 && INSN_LUID (INSN) >= INSN_LUID (START) \
381 && INSN_LUID (INSN) <= INSN_LUID (END))
383 /* Indirect_jump_in_function is computed once per function. */
391 rtx));
392 \f
393 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
394 copy the value of the strength reduced giv to its original register. */
397 /* Cost of using a register, to normalize the benefits of a giv. */
400 void
402 {
408 }
409 \f
410 /* Compute the mapping from uids to luids.
411 LUIDs are numbers assigned to insns, like uids,
412 except that luids increase monotonically through the code.
413 Start at insn START and stop just before END. Assign LUIDs
414 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
415 static int
419 {
421 rtx insn;
424 {
427 /* Don't assign luids to line-number NOTEs, so that the distance in
428 luids between two insns is not affected by -g. */
432 else
433 /* Give a line number note the same luid as preceding insn. */
435 }
437 }
438 \f
439 /* Entry point of this file. Perform loop optimization
440 on the current function. F is the first insn of the function
441 and DUMPFILE is a stream for output of a trace of actions taken
442 (or 0 if none should be output). */
444 void
446 /* f is the first instruction of a chain of insns for one function */
447 rtx f;
450 {
451 rtx insn;
466 /* Count the number of loops. */
470 {
473 max_loop_num++;
474 }
476 /* Don't waste time if no loops. */
482 /* Get size to use for tables indexed by uids.
483 Leave some space for labels allocated by find_and_verify_loops. */
490 /* Allocate storage for array of loops. */
494 /* Find and process each loop.
495 First, find them, and record them in order of their beginnings. */
498 /* Allocate and initialize auxiliary loop information. */
503 /* Now find all register lifetimes. This must be done after
504 find_and_verify_loops, because it might reorder the insns in the
505 function. */
508 /* This must occur after reg_scan so that registers created by gcse
509 will have entries in the register tables.
511 We could have added a call to reg_scan after gcse_main in toplev.c,
512 but moving this call to init_alias_analysis is more efficient. */
515 /* See if we went too far. Note that get_max_uid already returns
516 one more that the maximum uid of all insn. */
519 /* Now reset it to the actual size we need. See above. */
522 /* find_and_verify_loops has already called compute_luids, but it
523 might have rearranged code afterwards, so we need to recompute
524 the luids now. */
527 /* Don't leave gaps in uid_luid for insns that have been
528 deleted. It is possible that the first or last insn
529 using some register has been deleted by cross-jumping.
530 Make sure that uid_luid for that former insn's uid
531 points to the general area where that insn used to be. */
533 {
537 }
542 /* Determine if the function has indirect jump. On some systems
543 this prevents low overhead loop instructions from being used. */
546 /* Now scan the loops, last ones first, since this means inner ones are done
547 before outer ones. */
549 {
554 }
558 /* Clean up. */
563 }
564 \f
565 /* Returns the next insn, in execution order, after INSN. START and
566 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
567 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
568 insn-stream; it is used with loops that are entered near the
569 bottom. */
571 static rtx
574 rtx insn;
575 {
579 {
581 /* Go to the top of the loop, and continue there. */
583 else
584 /* We're done. */
586 }
589 /* We're done. */
593 }
595 /* Optimize one loop described by LOOP. */
597 /* ??? Could also move memory writes out of loops if the destination address
598 is invariant, the source is invariant, the memory write is not volatile,
599 and if we can prove that no read inside the loop can read this address
600 before the write occurs. If there is a read of this address after the
601 write, then we can also mark the memory read as invariant. */
603 static void
607 {
613 rtx p;
614 /* 1 if we are scanning insns that could be executed zero times. */
616 /* 1 if we are scanning insns that might never be executed
617 due to a subroutine call which might exit before they are reached. */
619 /* Jump insn that enters the loop, or 0 if control drops in. */
621 /* Number of insns in the loop. */
625 /* The SET from an insn, if it is the only SET in the insn. */
627 /* Chain describing insns movable in current loop. */
629 /* Ratio of extra register life span we can justify
630 for saving an instruction. More if loop doesn't call subroutines
631 since in that case saving an insn makes more difference
632 and more registers are available. */
634 /* Nonzero if we are scanning instructions in a sub-loop. */
642 /* Determine whether this loop starts with a jump down to a test at
643 the end. This will occur for a small number of loops with a test
644 that is too complex to duplicate in front of the loop.
646 We search for the first insn or label in the loop, skipping NOTEs.
647 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
648 (because we might have a loop executed only once that contains a
649 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
650 (in case we have a degenerate loop).
652 Note that if we mistakenly think that a loop is entered at the top
653 when, in fact, it is entered at the exit test, the only effect will be
654 slightly poorer optimization. Making the opposite error can generate
655 incorrect code. Since very few loops now start with a jump to the
656 exit test, the code here to detect that case is very conservative. */
659 p != loop_end
665 ;
669 /* If loop end is the end of the current function, then emit a
670 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
671 note insn. This is the position we use when sinking insns out of
672 the loop. */
675 else
678 /* Set up variables describing this loop. */
682 /* If loop has a jump before the first label,
683 the true entry is the target of that jump.
684 Start scan from there.
685 But record in LOOP->TOP the place where the end-test jumps
686 back to so we can scan that after the end of the loop. */
688 {
691 /* Loop entry must be unconditional jump (and not a RETURN) */
694 /* Check to see whether the jump actually
695 jumps out of the loop (meaning it's no loop).
696 This case can happen for things like
697 do {..} while (0). If this label was generated previously
698 by loop, we can't tell anything about it and have to reject
699 the loop. */
701 {
704 }
705 }
707 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
708 as required by loop_reg_used_before_p. So skip such loops. (This
709 test may never be true, but it's best to play it safe.)
711 Also, skip loops where we do not start scanning at a label. This
712 test also rejects loops starting with a JUMP_INSN that failed the
713 test above. */
717 {
722 }
724 /* Allocate extra space for REGs that might be created by load_mems.
725 We allocate a little extra slop as well, in the hopes that we
726 won't have to reallocate the regs array. */
731 {
737 }
739 /* Scan through the loop finding insns that are safe to move.
740 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
741 this reg will be considered invariant for subsequent insns.
742 We consider whether subsequent insns use the reg
743 in deciding whether it is worth actually moving.
745 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
746 and therefore it is possible that the insns we are scanning
747 would never be executed. At such times, we must make sure
748 that it is safe to execute the insn once instead of zero times.
749 When MAYBE_NEVER is 0, all insns will be executed at least once
750 so that is not a problem. */
755 {
759 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
761 #endif
763 {
770 /* Figure out what to use as a source of this insn. If a REG_EQUIV
771 note is given or if a REG_EQUAL note with a constant operand is
772 specified, use it as the source and mark that we should move
773 this insn by calling emit_move_insn rather that duplicating the
774 insn.
776 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
777 is present. */
781 else
782 {
787 {
789 /* A libcall block can use regs that don't appear in
790 the equivalent expression. To move the libcall,
791 we must move those regs too. */
793 }
794 }
796 /* For parallels, add any possible uses to the depencies, as we can't move
797 the insn without resolving them first. */
799 {
801 {
805 }
806 }
808 /* Don't try to optimize a register that was made
809 by loop-optimization for an inner loop.
810 We don't know its life-span, so we can't compute the benefit. */
812 ;
814 than the one where it is set (meaning that
815 something after this point in the loop might
816 depend on its value before the set). */
818 /* And the set is not guaranteed to be executed once
819 the loop starts, or the value before the set is
820 needed before the set occurs...
822 ??? Note we have quadratic behaviour here, mitigated
823 by the fact that the previous test will often fail for
824 large loops. Rather than re-scanning the entire loop
825 each time for register usage, we should build tables
826 of the register usage and use them here instead. */
827 && (maybe_never
829 /* It is unsafe to move the set.
831 This code used to consider it OK to move a set of a variable
832 which was not created by the user and not used in an exit test.
833 That behavior is incorrect and was removed. */
834 ;
839 || (tem1
840 = consec_sets_invariant_p
843 p)))
844 /* If the insn can cause a trap (such as divide by zero),
845 can't move it unless it's guaranteed to be executed
846 once loop is entered. Even a function call might
847 prevent the trap insn from being reached
848 (since it might exit!) */
851 {
855 /* A potential lossage is where we have a case where two insns
856 can be combined as long as they are both in the loop, but
857 we move one of them outside the loop. For large loops,
858 this can lose. The most common case of this is the address
859 of a function being called.
861 Therefore, if this register is marked as being used exactly
862 once if we are in a loop with calls (a "large loop"), see if
863 we can replace the usage of this register with the source
864 of this SET. If we can, delete this insn.
866 Don't do this if P has a REG_RETVAL note or if we have
867 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
879 && (! SMALL_REGISTER_CLASSES
882 /* This test is not redundant; SET_SRC (set) might be
883 a call-clobbered register and the life of REGNO
884 might span a call. */
890 {
891 /* Replace any usage in a REG_EQUAL note. Must copy the
892 new source, so that we don't get rtx sharing between the
893 SET_SOURCE and REG_NOTES of insn p. */
902 }
920 /* Set M->cond if either loop_invariant_p
921 or consec_sets_invariant_p returned 2
922 (only conditionally invariant). */
932 /* Add M to the end of the chain MOVABLES. */
936 {
937 /* It is possible for the first instruction to have a
938 REG_EQUAL note but a non-invariant SET_SRC, so we must
939 remember the status of the first instruction in case
940 the last instruction doesn't have a REG_EQUAL note. */
943 /* Skip this insn, not checking REG_LIBCALL notes. */
945 /* Skip the consecutive insns, if there are any. */
947 /* Back up to the last insn of the consecutive group. */
950 /* We must now reset m->move_insn, m->is_equiv, and possibly
951 m->set_src to correspond to the effects of all the
952 insns. */
956 else
957 {
961 else
964 }
966 }
967 }
968 /* If this register is always set within a STRICT_LOW_PART
969 or set to zero, then its high bytes are constant.
970 So clear them outside the loop and within the loop
971 just load the low bytes.
972 We must check that the machine has an instruction to do so.
973 Also, if the value loaded into the register
974 depends on the same register, this cannot be done. */
984 {
987 {
1001 /* If the insn may not be executed on some cycles,
1002 we can't clear the whole reg; clear just high part.
1003 Not even if the reg is used only within this loop.
1004 Consider this:
1005 while (1)
1006 while (s != t) {
1007 if (foo ()) x = *s;
1008 use (x);
1009 }
1010 Clearing x before the inner loop could clobber a value
1011 being saved from the last time around the outer loop.
1012 However, if the reg is not used outside this loop
1013 and all uses of the register are in the same
1014 basic block as the store, there is no problem.
1016 If this insn was made by loop, we don't know its
1017 INSN_LUID and hence must make a conservative
1018 assumption. */
1021 || (labels_in_range_p
1025 else
1034 /* Add M to the end of the chain MOVABLES. */
1036 }
1037 }
1038 }
1039 /* Past a call insn, we get to insns which might not be executed
1040 because the call might exit. This matters for insns that trap.
1041 Constant and pure call insns always return, so they don't count. */
1044 /* Past a label or a jump, we get to insns for which we
1045 can't count on whether or how many times they will be
1046 executed during each iteration. Therefore, we can
1047 only move out sets of trivial variables
1048 (those not used after the loop). */
1049 /* Similar code appears twice in strength_reduce. */
1051 /* If we enter the loop in the middle, and scan around to the
1052 beginning, don't set maybe_never for that. This must be an
1053 unconditional jump, otherwise the code at the top of the
1054 loop might never be executed. Unconditional jumps are
1055 followed by a barrier then the loop_end. */
1061 {
1062 /* At the virtual top of a converted loop, insns are again known to
1063 be executed: logically, the loop begins here even though the exit
1064 code has been duplicated. */
1068 loop_depth++;
1070 loop_depth--;
1071 }
1072 }
1074 /* If one movable subsumes another, ignore that other. */
1078 /* For each movable insn, see if the reg that it loads
1079 leads when it dies right into another conditionally movable insn.
1080 If so, record that the second insn "forces" the first one,
1081 since the second can be moved only if the first is. */
1085 /* See if there are multiple movable insns that load the same value.
1086 If there are, make all but the first point at the first one
1087 through the `match' field, and add the priorities of them
1088 all together as the priority of the first. */
1092 /* Now consider each movable insn to decide whether it is worth moving.
1093 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1095 Generally this increases code size, so do not move moveables when
1096 optimizing for code size. */
1099 {
1102 /* Recalculate regs->array if move_movables has created new
1103 registers. */
1105 {
1111 ;
1116 }
1117 }
1119 /* Now candidates that still are negative are those not moved.
1120 Change regs->array[I].set_in_loop to indicate that those are not actually
1121 invariant. */
1126 /* Now that we've moved some things out of the loop, we might be able to
1127 hoist even more memory references. */
1130 /* Recalculate regs->array if load_mems has created new registers. */
1138 ;
1145 {
1147 /* Ensure our label doesn't go away. */
1158 }
1161 /* The movable information is required for strength reduction. */
1167 }
1168 \f
1169 /* Add elements to *OUTPUT to record all the pseudo-regs
1170 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1172 void
1176 {
1184 {
1202 }
1206 {
1210 {
1219 }
1220 }
1221 }
1222 \f
1223 /* Check what regs are referred to in the libcall block ending with INSN,
1224 aside from those mentioned in the equivalent value.
1225 If there are none, return 0.
1226 If there are one or more, return an EXPR_LIST containing all of them. */
1228 rtx
1231 {
1236 /* First, find all the regs used in the libcall block
1237 that are not mentioned as inputs to the result. */
1240 {
1245 }
1248 }
1249 \f
1250 /* Return 1 if all uses of REG
1251 are between INSN and the end of the basic block. */
1253 static int
1256 {
1258 rtx p;
1263 /* Search this basic block for the already recorded last use of the reg. */
1265 {
1267 {
1273 /* Ordinary insn: if this is the last use, we win. */
1279 /* Jump insn: if this is the last use, we win. */
1282 /* Otherwise, it's the end of the basic block, so we lose. */
1287 /* It's the end of the basic block, so we lose. */
1292 }
1293 }
1295 /* The "last use" that was recorded can't be found after the first
1296 use. This can happen when the last use was deleted while
1297 processing an inner loop, this inner loop was then completely
1298 unrolled, and the outer loop is always exited after the inner loop,
1299 so that everything after the first use becomes a single basic block. */
1301 }
1302 \f
1303 /* Compute the benefit of eliminating the insns in the block whose
1304 last insn is LAST. This may be a group of insns used to compute a
1305 value directly or can contain a library call. */
1307 static int
1309 rtx last;
1310 {
1311 rtx insn;
1316 {
1319 routine. */
1323 benefit++;
1324 }
1327 }
1328 \f
1329 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1331 static rtx
1333 rtx insn;
1335 {
1337 {
1338 rtx temp;
1340 /* If first insn of libcall sequence, skip to end. */
1341 /* Do this at start of loop, since INSN is guaranteed to
1342 be an insn here. */
1347 do
1350 }
1353 }
1355 /* Ignore any movable whose insn falls within a libcall
1356 which is part of another movable.
1357 We make use of the fact that the movable for the libcall value
1358 was made later and so appears later on the chain. */
1360 static void
1363 {
1367 {
1368 /* Is this a movable for the value of a libcall? */
1371 {
1372 rtx insn;
1373 /* Check for earlier movables inside that range,
1374 and mark them invalid. We cannot use LUIDs here because
1375 insns created by loop.c for prior loops don't have LUIDs.
1376 Rather than reject all such insns from movables, we just
1377 explicitly check each insn in the libcall (since invariant
1378 libcalls aren't that common). */
1383 }
1384 }
1385 }
1387 /* For each movable insn, see if the reg that it loads
1388 leads when it dies right into another conditionally movable insn.
1389 If so, record that the second insn "forces" the first one,
1390 since the second can be moved only if the first is. */
1392 static void
1395 {
1399 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1401 {
1404 /* ??? Could this be a bug? What if CSE caused the
1405 register of M1 to be used after this insn?
1406 Since CSE does not update regno_last_uid,
1407 this insn M->insn might not be where it dies.
1408 But very likely this doesn't matter; what matters is
1409 that M's reg is computed from M1's reg. */
1414 /* If m->consec, m->set_src isn't valid. */
1418 /* Increase the priority of the moving the first insn
1419 since it permits the second to be moved as well. */
1421 {
1425 }
1426 }
1427 }
1428 \f
1429 /* Find invariant expressions that are equal and can be combined into
1430 one register. */
1432 static void
1436 {
1441 /* Regs that are set more than once are not allowed to match
1442 or be matched. I'm no longer sure why not. */
1443 /* Only pseudo registers are allowed to match or be matched,
1444 since move_movables does not validate the change. */
1445 /* Perhaps testing m->consec_sets would be more appropriate here? */
1451 {
1458 /* We want later insns to match the first one. Don't make the first
1459 one match any later ones. So start this loop at m->next. */
1464 /* A reg used outside the loop mustn't be eliminated. */
1466 /* A reg used for zero-extending mustn't be eliminated. */
1469 ||
1470 (
1471 /* Can combine regs with different modes loaded from the
1472 same constant only if the modes are the same or
1473 if both are integer modes with M wider or the same
1474 width as M1. The check for integer is redundant, but
1475 safe, since the only case of differing destination
1476 modes with equal sources is when both sources are
1477 VOIDmode, i.e., CONST_INT. */
1483 /* See if the source of M1 says it matches M. */
1490 {
1496 }
1497 }
1499 /* Now combine the regs used for zero-extension.
1500 This can be done for those not marked `global'
1501 provided their lives don't overlap. */
1505 {
1508 /* Combine all the registers for extension from mode MODE.
1509 Don't combine any that are used outside this loop. */
1513 {
1520 {
1521 /* First one: don't check for overlap, just record it. */
1524 }
1526 /* Make sure they extend to the same mode.
1527 (Almost always true.) */
1531 /* We already have one: check for overlap with those
1532 already combined together. */
1539 /* No overlap: we can combine this with the others. */
1545 overlap:
1546 ;
1547 }
1548 }
1550 /* Clean up. */
1552 }
1554 /* Returns the number of movable instructions in LOOP that were not
1555 moved outside the loop. */
1557 static int
1560 {
1569 }
1571 \f
1572 /* Return 1 if regs X and Y will become the same if moved. */
1574 static int
1578 {
1595 }
1597 /* Return 1 if X and Y are identical-looking rtx's.
1598 This is the Lisp function EQUAL for rtx arguments.
1600 If two registers are matching movables or a movable register and an
1601 equivalent constant, consider them equal. */
1603 static int
1608 {
1622 /* If we have a register and a constant, they may sometimes be
1623 equal. */
1626 {
1631 }
1634 {
1639 }
1641 /* Otherwise, rtx's of different codes cannot be equal. */
1645 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1646 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1651 /* These three types of rtx's can be compared nonrecursively. */
1660 /* Compare the elements. If any pair of corresponding elements
1661 fail to match, return 0 for the whole things. */
1665 {
1667 {
1679 /* Two vectors must have the same length. */
1683 /* And the corresponding elements must match. */
1702 /* These are just backpointers, so they don't matter. */
1708 /* It is believed that rtx's at this level will never
1709 contain anything but integers and other rtx's,
1710 except for within LABEL_REFs and SYMBOL_REFs. */
1713 }
1714 }
1716 }
1717 \f
1718 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1719 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1720 references is incremented once for each added note. */
1722 static void
1724 rtx x;
1725 rtx insns;
1726 {
1730 rtx insn;
1733 {
1734 /* This code used to ignore labels that referred to dispatch tables to
1735 avoid flow generating (slighly) worse code.
1737 We no longer ignore such label references (see LABEL_REF handling in
1738 mark_jump_label for additional information). */
1741 {
1746 }
1747 }
1751 {
1757 }
1758 }
1759 \f
1760 /* Scan MOVABLES, and move the insns that deserve to be moved.
1761 If two matching movables are combined, replace one reg with the
1762 other throughout. */
1764 static void
1770 {
1775 rtx p;
1778 /* Map of pseudo-register replacements to handle combining
1779 when we move several insns that load the same value
1780 into different pseudo-registers. */
1785 {
1786 /* Describe this movable insn. */
1789 {
1810 }
1812 /* Ignore the insn if it's already done (it matched something else).
1813 Otherwise, see if it is now safe to move. */
1825 {
1827 rtx p;
1830 /* We have an insn that is safe to move.
1831 Compute its desirability. */
1842 /* An insn MUST be moved if we already moved something else
1843 which is safe only if this one is moved too: that is,
1844 if already_moved[REGNO] is nonzero. */
1846 /* An insn is desirable to move if the new lifetime of the
1847 register is no more than THRESHOLD times the old lifetime.
1848 If it's not desirable, it means the loop is so big
1849 that moving won't speed things up much,
1850 and it is liable to make register usage worse. */
1852 /* It is also desirable to move if it can be moved at no
1853 extra cost because something else was already moved. */
1856 || flag_move_all_movables
1861 {
1866 /* Now move the insns that set the reg. */
1869 {
1872 /* Find the end of this chain of matching regs.
1873 Thus, we load each reg in the chain from that one reg.
1874 And that reg is loaded with 0 directly,
1875 since it has ->match == 0. */
1881 /* Mark the moved, invariant reg as being allowed to
1882 share a hard reg with the other matching invariant. */
1886 regs_may_share
1889 regs_may_share));
1897 }
1898 /* If we are to re-generate the item being moved with a
1899 new move insn, first delete what we have and then emit
1900 the move insn before the loop. */
1902 {
1906 {
1907 /* If this is the first insn of a library call sequence,
1908 skip to the end. */
1913 /* If this is the last insn of a libcall sequence, then
1914 delete every insn in the sequence except the last.
1915 The last insn is handled in the normal manner. */
1918 {
1922 }
1927 /* simplify_giv_expr expects that it can walk the insns
1928 at m->insn forwards and see this old sequence we are
1929 tossing here. delete_insn does preserve the next
1930 pointers, but when we skip over a NOTE we must fix
1931 it up. Otherwise that code walks into the non-deleted
1932 insn stream. */
1935 }
1953 /* The more regs we move, the less we like moving them. */
1955 }
1956 else
1957 {
1959 {
1962 /* If first insn of libcall sequence, skip to end. */
1963 /* Do this at start of loop, since p is guaranteed to
1964 be an insn here. */
1969 /* If last insn of libcall sequence, move all
1970 insns except the last before the loop. The last
1971 insn is handled in the normal manner. */
1974 {
1982 {
1983 rtx body;
1984 rtx n;
1985 rtx next;
1992 /* Find the next insn after TEMP,
1993 not counting USE or NOTE insns. */
2001 /* If that is the call, this may be the insn
2002 that loads the function address.
2004 Extract the function address from the insn
2005 that loads it into a register.
2006 If this insn was cse'd, we get incorrect code.
2008 So emit a new move insn that copies the
2009 function address into the register that the
2010 call insn will use. flow.c will delete any
2011 redundant stores that we have created. */
2016 NULL_RTX)))
2017 {
2023 }
2024 /* We have the call insn.
2025 If it uses the register we suspect it might,
2026 load it with the correct address directly. */
2031 gen_move_insn
2035 {
2037 /* Because the USAGE information potentially
2038 contains objects other than hard registers
2039 we need to copy it. */
2043 }
2044 else
2053 }
2056 }
2058 {
2059 /* P sets REG to zero; but we should clear only
2060 the bits that are not covered by the mode
2061 m->savemode. */
2063 rtx sequence;
2064 rtx tem;
2067 tem = expand_simple_binop
2080 }
2082 {
2084 /* Because the USAGE information potentially
2085 contains objects other than hard registers
2086 we need to copy it. */
2090 }
2092 {
2093 rtx seq;
2094 /* The SET_SRC might not be invariant, so we must
2095 use the REG_EQUAL note. */
2107 }
2108 else
2112 {
2116 /* If there is a REG_EQUAL note present whose value
2117 is not loop invariant, then delete it, since it
2118 may cause problems with later optimization passes.
2119 It is possible for cse to create such notes
2120 like this as a result of record_jump_cond. */
2125 }
2134 /* If library call, now fix the REG_NOTES that contain
2135 insn pointers, namely REG_LIBCALL on FIRST
2136 and REG_RETVAL on I1. */
2138 {
2142 }
2148 /* simplify_giv_expr expects that it can walk the insns
2149 at m->insn forwards and see this old sequence we are
2150 tossing here. delete_insn does preserve the next
2151 pointers, but when we skip over a NOTE we must fix
2152 it up. Otherwise that code walks into the non-deleted
2153 insn stream. */
2156 }
2158 /* The more regs we move, the less we like moving them. */
2160 }
2162 /* Any other movable that loads the same register
2163 MUST be moved. */
2166 /* This reg has been moved out of one loop. */
2169 /* The reg set here is now invariant. */
2171 {
2175 }
2179 /* Change the length-of-life info for the register
2180 to say it lives at least the full length of this loop.
2181 This will help guide optimizations in outer loops. */
2184 /* This is the old insn before all the moved insns.
2185 We can't use the moved insn because it is out of range
2186 in uid_luid. Only the old insns have luids. */
2191 /* Combine with this moved insn any other matching movables. */
2196 {
2197 rtx temp;
2199 /* Schedule the reg loaded by M1
2200 for replacement so that shares the reg of M.
2201 If the modes differ (only possible in restricted
2202 circumstances, make a SUBREG.
2204 Note this assumes that the target dependent files
2205 treat REG and SUBREG equally, including within
2206 GO_IF_LEGITIMATE_ADDRESS and in all the
2207 predicates since we never verify that replacing the
2208 original register with a SUBREG results in a
2209 recognizable insn. */
2212 else
2217 /* Get rid of the matching insn
2218 and prevent further processing of it. */
2221 /* if library call, delete all insns. */
2223 NULL_RTX)))
2225 else
2228 /* Any other movable that loads the same register
2229 MUST be moved. */
2232 /* The reg merged here is now invariant,
2233 if the reg it matches is invariant. */
2235 {
2239 i++)
2241 }
2242 }
2243 }
2246 }
2252 }
2257 /* Go through all the instructions in the loop, making
2258 all the register substitutions scheduled in REG_MAP. */
2262 {
2266 }
2268 /* Clean up. */
2271 }
2274 static void
2278 {
2281 else
2284 }
2287 static void
2290 {
2295 {
2298 }
2299 }
2300 \f
2301 #if 0
2302 /* Scan X and replace the address of any MEM in it with ADDR.
2303 REG is the address that MEM should have before the replacement. */
2305 static void
2308 {
2317 {
2329 /* Short cut for very common case. */
2334 /* Short cut for very common case. */
2339 /* If this MEM uses a reg other than the one we expected,
2340 something is wrong. */
2348 }
2352 {
2356 {
2360 }
2361 }
2362 }
2363 #endif
2364 \f
2365 /* Return the number of memory refs to addresses that vary
2366 in the rtx X. */
2368 static int
2371 rtx x;
2372 {
2383 {
2400 }
2405 {
2409 {
2413 }
2414 }
2416 }
2417 \f
2418 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2419 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2420 `unknown_address_altered', `unknown_constant_address_altered', and
2421 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2422 list `store_mems' in LOOP. */
2424 static void
2427 {
2429 rtx insn;
2433 /* The label after END. Jumping here is just like falling off the
2434 end of the loop. We use next_nonnote_insn instead of next_label
2435 as a hedge against the (pathological) case where some actual insn
2436 might end up between the two. */
2459 {
2461 {
2464 }
2465 }
2469 {
2471 {
2474 {
2476 /* Count number of loops contained in this one. */
2478 }
2485 {
2488 }
2498 {
2502 {
2507 {
2510 }
2511 else
2512 {
2515 }
2517 do
2518 {
2520 {
2522 {
2523 /* Something tricky. */
2526 }
2529 {
2530 /* A jump outside the current loop. */
2533 }
2534 }
2538 }
2540 }
2541 else
2542 {
2543 /* A return, or something tricky. */
2545 }
2546 }
2547 /* FALLTHRU */
2568 }
2569 }
2571 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2573 anywhere. */
2575 /* We don't want loads for MEMs moved to a location before the
2576 one at which their stack memory becomes allocated. (Note
2577 that this is not a problem for malloc, etc., since those
2578 require actual function calls. */
2579 && ! current_function_calls_alloca
2580 /* There are ways to leave the loop other than falling off the
2581 end. */
2587 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2588 that loop_invariant_p and load_mems can use true_dependence
2589 to determine what is really clobbered. */
2591 {
2594 loop_info->store_mems
2596 }
2598 {
2602 loop_info->store_mems
2604 }
2605 }
2606 \f
2607 /* Invalidate all loops containing LABEL. */
2609 static void
2611 rtx label;
2612 {
2616 }
2618 /* Scan the function looking for loops. Record the start and end of each loop.
2619 Also mark as invalid loops any loops that contain a setjmp or are branched
2620 to from outside the loop. */
2622 static void
2624 rtx f;
2626 {
2627 rtx insn;
2628 rtx label;
2638 /* If there are jumps to undefined labels,
2639 treat them as jumps out of any/all loops.
2640 This also avoids writing past end of tables when there are no loops. */
2643 /* Find boundaries of loops, mark which loops are contained within
2644 loops, and invalidate loops that have setjmp. */
2649 {
2652 {
2656 num_loops++;
2680 }
2684 {
2685 /* In this case, we must invalidate our current loop and any
2686 enclosing loop. */
2688 {
2694 }
2695 }
2697 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2698 enclosing loop, but this doesn't matter. */
2700 }
2702 /* Any loop containing a label used in an initializer must be invalidated,
2703 because it can be jumped into from anywhere. */
2707 /* Any loop containing a label used for an exception handler must be
2708 invalidated, because it can be jumped into from anywhere. */
2711 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2712 loop that it is not contained within, that loop is marked invalid.
2713 If any INSN or CALL_INSN uses a label's address, then the loop containing
2714 that label is marked invalid, because it could be jumped into from
2715 anywhere.
2717 Also look for blocks of code ending in an unconditional branch that
2718 exits the loop. If such a block is surrounded by a conditional
2719 branch around the block, move the block elsewhere (see below) and
2720 invert the jump to point to the code block. This may eliminate a
2721 label in our loop and will simplify processing by both us and a
2722 possible second cse pass. */
2726 {
2730 {
2734 }
2741 /* See if this is an unconditional branch outside the loop. */
2749 {
2750 rtx p;
2756 /* Go backwards until we reach the start of the loop, a label,
2757 or a JUMP_INSN. */
2764 ;
2766 /* Check for the case where we have a jump to an inner nested
2767 loop, and do not perform the optimization in that case. */
2770 {
2773 {
2778 }
2779 }
2781 /* Make sure that the target of P is within the current loop. */
2787 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2788 we have a block of code to try to move.
2790 We look backward and then forward from the target of INSN
2791 to find a BARRIER at the same loop depth as the target.
2792 If we find such a BARRIER, we make a new label for the start
2793 of the block, invert the jump in P and point it to that label,
2794 and move the block of code to the spot we found. */
2799 /* Just ignore jumps to labels that were never emitted.
2800 These always indicate compilation errors. */
2804 /* If it's not safe to move the sequence, then we
2805 mustn't try. */
2808 {
2809 rtx target
2813 rtx tmp;
2815 /* Search for possible garbage past the conditional jumps
2816 and look for the last barrier. */
2824 /* Don't move things inside a tablejump. */
2837 /* Don't move things inside a tablejump. */
2848 {
2852 /* Ensure our label doesn't go away. */
2855 /* Verify that uid_loop is large enough and that
2856 we can invert P. */
2858 {
2861 /* If no suitable BARRIER was found, create a suitable
2862 one before TARGET. Since TARGET is a fall through
2863 path, we'll need to insert an jump around our block
2864 and add a BARRIER before TARGET.
2866 This creates an extra unconditional jump outside
2867 the loop. However, the benefits of removing rarely
2868 executed instructions from inside the loop usually
2869 outweighs the cost of the extra unconditional jump
2870 outside the loop. */
2872 {
2873 rtx temp;
2880 }
2882 /* Include the BARRIER after INSN and copy the
2883 block after LOC. */
2888 /* All those insns are now in TARGET_LOOP. */
2894 /* The label jumped to by INSN is no longer a loop
2895 exit. Unless INSN does not have a label (e.g.,
2896 it is a RETURN insn), search loop->exit_labels
2897 to find its label_ref, and remove it. Also turn
2898 off LABEL_OUTSIDE_LOOP_P bit. */
2900 {
2902 r;
2905 {
2909 else
2912 }
2918 /* If we didn't find it, then something is
2919 wrong. */
2922 }
2924 /* P is now a jump outside the loop, so it must be put
2925 in loop->exit_labels, and marked as such.
2926 The easiest way to do this is to just call
2927 mark_loop_jump again for P. */
2930 /* If INSN now jumps to the insn after it,
2931 delete INSN. */
2936 }
2938 /* Continue the loop after where the conditional
2939 branch used to jump, since the only branch insn
2940 in the block (if it still remains) is an inter-loop
2941 branch and hence needs no processing. */
2947 /* This loop will be continued with NEXT_INSN (insn). */
2949 }
2950 }
2951 }
2952 }
2953 }
2955 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2956 loops it is contained in, mark the target loop invalid.
2958 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2960 static void
2962 rtx x;
2964 {
2970 {
2982 /* There could be a label reference in here. */
2994 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3006 /* Link together all labels that branch outside the loop. This
3007 is used by final_[bg]iv_value and the loop unrolling code. Also
3008 mark this LABEL_REF so we know that this branch should predict
3009 false. */
3011 /* A check to make sure the label is not in an inner nested loop,
3012 since this does not count as a loop exit. */
3014 {
3019 }
3020 else
3024 {
3033 }
3035 /* If this is inside a loop, but not in the current loop or one enclosed
3036 by it, it invalidates at least one loop. */
3041 /* We must invalidate every nested loop containing the target of this
3042 label, except those that also contain the jump insn. */
3045 {
3046 /* Stop when we reach a loop that also contains the jump insn. */
3051 /* If we get here, we know we need to invalidate a loop. */
3058 }
3062 /* If this is not setting pc, ignore. */
3084 /* Strictly speaking this is not a jump into the loop, only a possible
3085 jump out of the loop. However, we have no way to link the destination
3086 of this jump onto the list of exit labels. To be safe we mark this
3087 loop and any containing loops as invalid. */
3089 {
3091 {
3097 }
3098 }
3100 }
3101 }
3102 \f
3103 /* Return nonzero if there is a label in the range from
3104 insn INSN to and including the insn whose luid is END
3105 INSN must have an assigned luid (i.e., it must not have
3106 been previously created by loop.c). */
3108 static int
3110 rtx insn;
3112 {
3114 {
3118 }
3121 }
3123 /* Record that a memory reference X is being set. */
3125 static void
3127 rtx x;
3128 rtx y ATTRIBUTE_UNUSED;
3130 {
3136 /* Count number of memory writes.
3137 This affects heuristics in strength_reduce. */
3140 /* BLKmode MEM means all memory is clobbered. */
3142 {
3145 else
3149 }
3153 }
3155 /* X is a value modified by an INSN that references a biv inside a loop
3156 exit test (ie, X is somehow related to the value of the biv). If X
3157 is a pseudo that is used more than once, then the biv is (effectively)
3158 used more than once. DATA is a pointer to a loop_regs structure. */
3160 static void
3162 rtx x;
3163 rtx y ATTRIBUTE_UNUSED;
3165 {
3180 /* If we do not have usage information, or if we know the register
3181 is used more than once, note that fact for check_dbra_loop. */
3186 }
3187 \f
3188 /* Return nonzero if the rtx X is invariant over the current loop.
3190 The value is 2 if we refer to something only conditionally invariant.
3192 A memory ref is invariant if it is not volatile and does not conflict
3193 with anything stored in `loop_info->store_mems'. */
3195 int
3198 rtx x;
3199 {
3206 rtx mem_list_entry;
3212 {
3220 /* A LABEL_REF is normally invariant, however, if we are unrolling
3221 loops, and this label is inside the loop, then it isn't invariant.
3222 This is because each unrolled copy of the loop body will have
3223 a copy of this label. If this was invariant, then an insn loading
3224 the address of this label into a register might get moved outside
3225 the loop, and then each loop body would end up using the same label.
3227 We don't know the loop bounds here though, so just fail for all
3228 labels. */
3231 else
3240 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3241 since the reg might be set by initialization within the loop. */
3258 /* Volatile memory references must be rejected. Do this before
3259 checking for read-only items, so that volatile read-only items
3260 will be rejected also. */
3264 /* See if there is any dependence between a store and this load. */
3267 {
3273 }
3275 /* It's not invalidated by a store in memory
3276 but we must still verify the address is invariant. */
3280 /* Don't mess with insns declared volatile. */
3287 }
3291 {
3293 {
3299 }
3301 {
3304 {
3310 }
3312 }
3313 }
3316 }
3317 \f
3318 /* Return nonzero if all the insns in the loop that set REG
3319 are INSN and the immediately following insns,
3320 and if each of those insns sets REG in an invariant way
3321 (not counting uses of REG in them).
3323 The value is 2 if some of these insns are only conditionally invariant.
3325 We assume that INSN itself is the first set of REG
3326 and that its source is invariant. */
3328 static int
3333 {
3337 rtx temp;
3338 /* Number of sets we have to insist on finding after INSN. */
3344 /* If N_SETS hit the limit, we can't rely on its value. */
3351 {
3353 rtx set;
3358 /* If library call, skip to end of it. */
3367 {
3372 {
3373 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3374 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3375 notes are OK. */
3381 }
3382 }
3384 count--;
3386 {
3389 }
3390 }
3393 /* If loop_invariant_p ever returned 2, we return 2. */
3395 }
3397 #if 0
3398 /* I don't think this condition is sufficient to allow INSN
3399 to be moved, so we no longer test it. */
3401 /* Return 1 if all insns in the basic block of INSN and following INSN
3402 that set REG are invariant according to TABLE. */
3404 static int
3408 {
3413 {
3422 {
3425 }
3426 }
3427 }
3429 \f
3430 /* Look at all uses (not sets) of registers in X. For each, if it is
3431 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3432 a different insn, set USAGE[REGNO] to const0_rtx. */
3434 static void
3437 rtx insn;
3438 rtx x;
3439 {
3451 {
3452 /* Don't count SET_DEST if it is a REG; otherwise count things
3453 in SET_DEST because if a register is partially modified, it won't
3454 show up as a potential movable so we don't care how USAGE is set
3455 for it. */
3459 }
3460 else
3462 {
3468 }
3469 }
3470 \f
3471 /* Count and record any set in X which is contained in INSN. Update
3472 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3473 in X. */
3475 static void
3480 {
3482 /* Don't move a reg that has an explicit clobber.
3483 It's not worth the pain to try to do it correctly. */
3487 {
3495 {
3499 {
3500 /* If this is the first setting of this reg
3501 in current basic block, and it was set before,
3502 it must be set in two basic blocks, so it cannot
3503 be moved out of the loop. */
3507 /* If this is not first setting in current basic block,
3508 see if reg was used in between previous one and this.
3509 If so, neither one can be moved. */
3516 }
3517 }
3518 }
3519 }
3520 \f
3521 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3522 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3523 contained in insn INSN is used by any insn that precedes INSN in
3524 cyclic order starting from the loop entry point.
3526 We don't want to use INSN_LUID here because if we restrict INSN to those
3527 that have a valid INSN_LUID, it means we cannot move an invariant out
3528 from an inner loop past two loops. */
3530 static int
3534 {
3536 rtx p;
3538 /* Scan forward checking for register usage. If we hit INSN, we
3539 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3541 {
3547 }
3550 }
3551 \f
3553 /* Information we collect about arrays that we might want to prefetch. */
3554 struct prefetch_info
3555 {
3559 index. */
3560 HOST_WIDE_INT index;
3562 iteration. */
3564 prefetch area in one iteration. */
3566 This is set only for loops with known
3567 iteration counts and is 0xffffffff
3568 otherwise. */
3572 };
3574 /* Data used by check_store function. */
3575 struct check_store_data
3576 {
3577 rtx mem_address;
3579 };
3585 /* Set mem_write when mem_address is found. Used as callback to
3586 note_stores. */
3587 static void
3591 {
3596 }
3597 \f
3598 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3599 important to get some addresses combined. Later more sophisticated
3600 transformations can be added when necesary.
3602 ??? Same trick with swapping operand is done at several other places.
3603 It can be nice to develop some common way to handle this. */
3605 static int
3608 {
3622 {
3627 }
3628 /* Compare the elements. If any pair of corresponding elements fails to
3629 match, return 0 for the whole thing. */
3633 {
3635 {
3647 /* Two vectors must have the same length. */
3651 /* And the corresponding elements must match. */
3669 /* These are just backpointers, so they don't matter. */
3675 /* It is believed that rtx's at this level will never
3676 contain anything but integers and other rtx's,
3677 except for within LABEL_REFs and SYMBOL_REFs. */
3680 }
3681 }
3683 }
3684 \f
3685 /* Remove constant addition value from the expression X (when present)
3686 and return it. */
3688 static HOST_WIDE_INT
3691 {
3695 /* Avoid clobbering a shared CONST expression. */
3697 {
3701 {
3704 }
3706 }
3709 {
3712 }
3714 /* For plus expression recurse on ourself. */
3716 {
3720 /* In case our parameter was constant, remove extra zero from the
3721 expression. */
3726 }
3729 }
3731 /* Attempt to identify accesses to arrays that are most likely to cause cache
3732 misses, and emit prefetch instructions a few prefetch blocks forward.
3734 To detect the arrays we use the GIV information that was collected by the
3735 strength reduction pass.
3737 The prefetch instructions are generated after the GIV information is done
3738 and before the strength reduction process. The new GIVs are injected into
3739 the strength reduction tables, so the prefetch addresses are optimized as
3740 well.
3742 GIVs are split into base address, stride, and constant addition values.
3743 GIVs with the same address, stride and close addition values are combined
3744 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3745 for write instructions can be used for the block we write to, on machines
3746 that support write prefetches.
3748 Several heuristics are used to determine when to prefetch. They are
3749 controlled by defined symbols that can be overridden for each target. */
3751 static void
3754 {
3770 /* Consider only loops w/o calls. When a call is done, the loop is probably
3771 slow enough to read the memory. */
3773 {
3778 }
3780 /* Don't prefetch in loops known to have few iterations. */
3784 {
3789 }
3791 /* Search all induction variables and pick those interesting for the prefetch
3792 machinery. */
3794 {
3800 /* Expect all BIVs to be executed in each iteration. This makes our
3801 analysis more conservative. */
3803 {
3804 /* Discard non-constant additions that we can't handle well yet, and
3805 BIVs that are executed multiple times; such BIVs ought to be
3806 handled in the nested loop. We accept not_every_iteration BIVs,
3807 since these only result in larger strides and make our
3808 heuristics more conservative. */
3810 {
3812 {
3818 }
3820 }
3823 {
3825 {
3831 }
3833 }
3837 }
3843 {
3844 rtx address;
3845 rtx temp;
3854 /* See whether an induction variable is interesting to us and if
3855 not, report the reason. */
3859 /* We are interested only in constant stride memory references
3860 in order to be able to compute density easily. */
3864 else
3865 {
3868 {
3871 }
3873 /* On some targets, reversed order prefetches are not
3874 worthwhile. */
3878 /* Prefetch of accesses with an extreme stride might not be
3879 worthwhile, either. */
3884 /* Ignore GIVs with varying add values; we can't predict the
3885 value for the next iteration. */
3889 /* Ignore GIVs in the nested loops; they ought to have been
3890 handled already. */
3893 }
3896 {
3902 }
3904 /* Determine the pointer to the basic array we are examining. It is
3905 the sum of the BIV's initial value and the GIV's add_val. */
3915 /* When the GIV is not always executed, we might be better off by
3916 not dirtying the cache pages. */
3919 else
3920 {
3925 }
3927 /* Attempt to find another prefetch to the same array and see if we
3928 can merge this one. */
3932 {
3933 /* In case both access same array (same location
3934 just with small difference in constant indexes), merge
3935 the prefetches. Just do the later and the earlier will
3936 get prefetched from previous iteration.
3937 The artificial threshold should not be too small,
3938 but also not bigger than small portion of memory usually
3939 traversed by single loop. */
3942 {
3951 }
3955 {
3960 }
3961 }
3963 /* Merging failed. */
3965 {
3973 num_prefetches++;
3975 {
3980 }
3981 }
3982 }
3983 }
3986 {
3989 /* Attempt to calculate the total number of bytes fetched by all
3990 iterations of the loop. Avoid overflow. */
3995 else
4000 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4005 {
4010 }
4011 else
4012 {
4018 }
4019 else
4022 /* Find how many prefetch instructions we'll use within the loop. */
4024 {
4030 }
4031 }
4033 /* Determine how many iterations ahead to prefetch within the loop, based
4034 on how many prefetches we currently expect to do within the loop. */
4036 {
4038 {
4044 }
4045 }
4046 /* We'll also use AHEAD to determine how many prefetch instructions to
4047 emit before a loop, so don't leave it zero. */
4052 {
4053 /* Update if we've decided not to prefetch anything within the loop. */
4057 /* Find how many prefetch instructions we'll use before the loop. */
4059 {
4067 }
4070 {
4092 }
4093 }
4096 {
4097 /* Record that this loop uses prefetch instructions. */
4101 {
4106 }
4107 }
4110 {
4114 {
4116 rtx insn;
4120 rtx seq;
4122 /* We can save some effort by offsetting the address on
4123 architectures with offsettable memory references. */
4126 else
4127 {
4133 }
4136 /* Make sure the address operand is valid for prefetch. */
4146 /* Check all insns emitted and record the new GIV
4147 information. */
4150 {
4155 }
4156 }
4159 {
4160 /* Emit insns before the loop to fetch the first cache lines or,
4161 if we're not prefetching within the loop, everything we expect
4162 to need. */
4164 {
4172 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4173 non-constant INIT_VAL to have the same mode as REG, which
4174 in this case we know to be Pmode. */
4182 loop_start);
4183 }
4184 }
4185 }
4188 }
4189 \f
4190 /* A "basic induction variable" or biv is a pseudo reg that is set
4191 (within this loop) only by incrementing or decrementing it. */
4192 /* A "general induction variable" or giv is a pseudo reg whose
4193 value is a linear function of a biv. */
4195 /* Bivs are recognized by `basic_induction_var';
4196 Givs by `general_induction_var'. */
4198 /* Communication with routines called via `note_stores'. */
4202 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4206 /* ??? Unfinished optimizations, and possible future optimizations,
4207 for the strength reduction code. */
4209 /* ??? The interaction of biv elimination, and recognition of 'constant'
4210 bivs, may cause problems. */
4212 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4213 performance problems.
4215 Perhaps don't eliminate things that can be combined with an addressing
4216 mode. Find all givs that have the same biv, mult_val, and add_val;
4217 then for each giv, check to see if its only use dies in a following
4218 memory address. If so, generate a new memory address and check to see
4219 if it is valid. If it is valid, then store the modified memory address,
4220 otherwise, mark the giv as not done so that it will get its own iv. */
4222 /* ??? Could try to optimize branches when it is known that a biv is always
4223 positive. */
4225 /* ??? When replace a biv in a compare insn, we should replace with closest
4226 giv so that an optimized branch can still be recognized by the combiner,
4227 e.g. the VAX acb insn. */
4229 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4230 was rerun in loop_optimize whenever a register was added or moved.
4231 Also, some of the optimizations could be a little less conservative. */
4232 \f
4233 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4234 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4235 callback.
4237 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4238 least once for every loop iteration except for the last one.
4240 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4241 loop iteration.
4242 */
4243 void
4246 loop_insn_callback fncall;
4247 {
4252 rtx p;
4254 /* If loop_scan_start points to the loop exit test, we have to be wary of
4255 subversive use of gotos inside expression statements. */
4259 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4263 {
4266 /* Past CODE_LABEL, we get to insns that may be executed multiple
4267 times. The only way we can be sure that they can't is if every
4268 jump insn between here and the end of the loop either
4269 returns, exits the loop, is a jump to a location that is still
4270 behind the label, or is a jump to the loop start. */
4273 {
4279 {
4284 {
4287 else
4291 }
4299 {
4302 }
4303 }
4304 }
4306 /* Past a jump, we get to insns for which we can't count
4307 on whether they will be executed during each iteration. */
4308 /* This code appears twice in strength_reduce. There is also similar
4309 code in scan_loop. */
4311 /* If we enter the loop in the middle, and scan around to the
4312 beginning, don't set not_every_iteration for that.
4313 This can be any kind of jump, since we want to know if insns
4314 will be executed if the loop is executed. */
4319 {
4322 /* If this is a jump outside the loop, then it also doesn't
4323 matter. Check to see if the target of this branch is on the
4324 loop->exits_labels list. */
4332 }
4335 {
4336 /* At the virtual top of a converted loop, insns are again known to
4337 be executed each iteration: logically, the loop begins here
4338 even though the exit code has been duplicated.
4340 Insns are also again known to be executed each iteration at
4341 the LOOP_CONT note. */
4347 loop_depth++;
4349 loop_depth--;
4350 }
4352 /* Note if we pass a loop latch. If we do, then we can not clear
4353 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4354 a loop since a jump before the last CODE_LABEL may have started
4355 a new loop iteration.
4357 Note that LOOP_TOP is only set for rotated loops and we need
4358 this check for all loops, so compare against the CODE_LABEL
4359 which immediately follows LOOP_START. */
4364 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4365 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4366 or not an insn is known to be executed each iteration of the
4367 loop, whether or not any iterations are known to occur.
4369 Therefore, if we have just passed a label and have no more labels
4370 between here and the test insn of the loop, and we have not passed
4371 a jump to the top of the loop, then we know these insns will be
4372 executed each iteration. */
4375 && !past_loop_latch
4380 }
4381 }
4382 \f
4383 static void
4386 {
4389 /* Temporary list pointers for traversing ivs->list. */
4396 /* Scan ivs->list to remove all regs that proved not to be bivs.
4397 Make a sanity check against regs->n_times_set. */
4399 {
4401 /* Above happens if register modified by subreg, etc. */
4402 /* Make sure it is not recognized as a basic induction var: */
4404 /* If never incremented, it is invariant that we decided not to
4405 move. So leave it alone. */
4407 {
4418 }
4419 else
4420 {
4425 }
4426 }
4427 }
4430 /* Determine how BIVS are initialised by looking through pre-header
4431 extended basic block. */
4432 static void
4435 {
4437 /* Temporary list pointers for traversing ivs->list. */
4440 rtx p;
4442 /* Find initial value for each biv by searching backwards from loop_start,
4443 halting at first label. Also record any test condition. */
4447 {
4448 rtx test;
4458 /* Record any test of a biv that branches around the loop if no store
4459 between it and the start of loop. We only care about tests with
4460 constants and registers and only certain of those. */
4470 {
4471 /* If an NE test, we have an initial value! */
4473 {
4477 }
4478 else
4480 }
4481 }
4482 }
4485 /* Look at the each biv and see if we can say anything better about its
4486 initial value from any initializing insns set up above. (This is done
4487 in two passes to avoid missing SETs in a PARALLEL.) */
4488 static void
4491 {
4493 /* Temporary list pointers for traversing ivs->list. */
4498 {
4499 rtx src;
4500 rtx note;
4505 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4506 is a constant, use the value of that. */
4512 else
4525 {
4529 {
4532 }
4533 }
4534 /* If we can't make it a giv,
4535 let biv keep initial value of "itself". */
4538 }
4539 }
4542 /* Search the loop for general induction variables. */
4544 static void
4547 {
4549 }
4552 /* For each giv for which we still don't know whether or not it is
4553 replaceable, check to see if it is replaceable because its final value
4554 can be calculated. */
4556 static void
4559 {
4564 {
4570 }
4571 }
4574 /* Return non-zero if it is possible to eliminate the biv BL provided
4575 all givs are reduced. This is possible if either the reg is not
4576 used outside the loop, or we can compute what its final value will
4577 be. */
4579 static int
4585 {
4586 /* For architectures with a decrement_and_branch_until_zero insn,
4587 don't do this if we put a REG_NONNEG note on the endtest for this
4588 biv. */
4590 #ifdef HAVE_decrement_and_branch_until_zero
4592 {
4597 }
4598 #endif
4600 /* Check that biv is used outside loop or if it has a final value.
4601 Compare against bl->init_insn rather than loop->start. We aren't
4602 concerned with any uses of the biv between init_insn and
4603 loop->start since these won't be affected by the value of the biv
4604 elsewhere in the function, so long as init_insn doesn't use the
4605 biv itself. */
4616 {
4624 }
4626 }
4629 /* Reduce each giv of BL that we have decided to reduce. */
4631 static void
4635 {
4639 {
4642 {
4645 /* If the code for derived givs immediately below has already
4646 allocated a new_reg, we must keep it. */
4650 #ifdef AUTO_INC_DEC
4651 /* If the target has auto-increment addressing modes, and
4652 this is an address giv, then try to put the increment
4653 immediately after its use, so that flow can create an
4654 auto-increment addressing mode. */
4657 /* We don't handle reversed biv's because bl->biv->insn
4658 does not have a valid INSN_LUID. */
4662 {
4663 /* If other giv's have been combined with this one, then
4664 this will work only if all uses of the other giv's occur
4665 before this giv's insn. This is difficult to check.
4667 We simplify this by looking for the common case where
4668 there is one DEST_REG giv, and this giv's insn is the
4669 last use of the dest_reg of that DEST_REG giv. If the
4670 increment occurs after the address giv, then we can
4671 perform the optimization. (Otherwise, the increment
4672 would have to go before other_giv, and we would not be
4673 able to combine it with the address giv to get an
4674 auto-inc address.) */
4676 {
4681 {
4684 else
4686 }
4693 }
4694 /* Check for case where increment is before the address
4695 giv. Do this test in "loop order". */
4704 else
4707 #ifdef HAVE_cc0
4708 {
4709 rtx prev;
4711 /* We can't put an insn immediately after one setting
4712 cc0, or immediately before one using cc0. */
4719 }
4720 #endif
4724 }
4725 #endif
4727 /* For each place where the biv is incremented, add an insn
4728 to increment the new, reduced reg for the giv. */
4730 {
4731 rtx insert_before;
4737 else
4745 /* A multiply is acceptable here
4746 since this is presumed to be seldom executed. */
4750 }
4752 /* Add code at loop start to initialize giv's reduced reg. */
4757 }
4758 }
4759 }
4762 /* Check for givs whose first use is their definition and whose
4763 last use is the definition of another giv. If so, it is likely
4764 dead and should not be used to derive another giv nor to
4765 eliminate a biv. */
4767 static void
4771 {
4775 {
4782 {
4788 }
4789 }
4790 }
4793 static void
4798 {
4802 {
4809 /* Update expression if this was combined, in case other giv was
4810 replaced. */
4815 /* See if this register is known to be a pointer to something. If
4816 so, see if we can find the alignment. First see if there is a
4817 destination register that is a pointer. If so, this shares the
4818 alignment too. Next see if we can deduce anything from the
4819 computational information. If not, and this is a DEST_ADDR
4820 giv, at least we know that it's a pointer, though we don't know
4821 the alignment. */
4829 {
4838 }
4842 {
4850 }
4855 /* Store reduced reg as the address in the memref where we found
4856 this giv. */
4859 {
4861 }
4862 else
4863 {
4865 rtx note;
4867 /* Not replaceable; emit an insn to set the original giv reg from
4868 the reduced giv, same as above. */
4873 /* The original insn may have a REG_EQUAL note. This note is
4874 now incorrect and may result in invalid substitutions later.
4875 The original insn is dead, but may be part of a libcall
4876 sequence, which doesn't seem worth the bother of handling. */
4880 }
4882 /* When a loop is reversed, givs which depend on the reversed
4883 biv, and which are live outside the loop, must be set to their
4884 correct final value. This insn is only needed if the giv is
4885 not replaceable. The correct final value is the same as the
4886 value that the giv starts the reversed loop with. */
4897 {
4902 }
4903 }
4904 }
4907 static int
4912 rtx test_reg;
4913 {
4922 /* Reduce benefit if not replaceable, since we will insert a
4923 move-insn to replace the insn that calculates this giv. Don't do
4924 this unless the giv is a user variable, since it will often be
4925 marked non-replaceable because of the duplication of the exit
4926 code outside the loop. In such a case, the copies we insert are
4927 dead and will be deleted. So they don't have a cost. Similar
4928 situations exist. */
4929 /* ??? The new final_[bg]iv_value code does a much better job of
4930 finding replaceable giv's, and hence this code may no longer be
4931 necessary. */
4936 /* Decrease the benefit to count the add-insns that we will insert
4937 to increment the reduced reg for the giv. ??? This can
4938 overestimate the run-time cost of the additional insns, e.g. if
4939 there are multiple basic blocks that increment the biv, but only
4940 one of these blocks is executed during each iteration. There is
4941 no good way to detect cases like this with the current structure
4942 of the loop optimizer. This code is more accurate for
4943 determining code size than run-time benefits. */
4946 /* Decide whether to strength-reduce this giv or to leave the code
4947 unchanged (recompute it from the biv each time it is used). This
4948 decision can be made independently for each giv. */
4950 #ifdef AUTO_INC_DEC
4951 /* Attempt to guess whether autoincrement will handle some of the
4952 new add insns; if so, increase BENEFIT (undo the subtraction of
4953 add_cost that was done above). */
4955 /* Increasing the benefit is risky, since this is only a guess.
4956 Avoid increasing register pressure in cases where there would
4957 be no other benefit from reducing this giv. */
4960 {
4975 }
4976 #endif
4979 }
4982 /* Free IV structures for LOOP. */
4984 static void
4987 {
4994 {
5000 {
5003 }
5005 {
5008 }
5012 }
5013 }
5016 /* Perform strength reduction and induction variable elimination.
5018 Pseudo registers created during this function will be beyond the
5019 last valid index in several tables including
5020 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5021 problem here, because the added registers cannot be givs outside of
5022 their loop, and hence will never be reconsidered. But scan_loop
5023 must check regnos to make sure they are in bounds. */
5025 static void
5029 {
5033 rtx p;
5034 /* Temporary list pointer for traversing ivs->list. */
5036 /* Ratio of extra register life span we can justify
5037 for saving an instruction. More if loop doesn't call subroutines
5038 since in that case saving an insn makes more difference
5039 and more registers are available. */
5040 /* ??? could set this to last value of threshold in move_movables */
5042 /* Map of pseudo-register replacements. */
5054 /* Find all BIVs in loop. */
5057 /* Exit if there are no bivs. */
5059 {
5060 /* Can still unroll the loop anyways, but indicate that there is no
5061 strength reduction info available. */
5067 }
5069 /* Determine how BIVS are initialised by looking through pre-header
5070 extended basic block. */
5073 /* Look at the each biv and see if we can say anything better about its
5074 initial value from any initializing insns set up above. */
5077 /* Search the loop for general induction variables. */
5080 /* Try to calculate and save the number of loop iterations. This is
5081 set to zero if the actual number can not be calculated. This must
5082 be called after all giv's have been identified, since otherwise it may
5083 fail if the iteration variable is a giv. */
5086 #ifdef HAVE_prefetch
5089 #endif
5091 /* Now for each giv for which we still don't know whether or not it is
5092 replaceable, check to see if it is replaceable because its final value
5093 can be calculated. This must be done after loop_iterations is called,
5094 so that final_giv_value will work correctly. */
5097 /* Try to prove that the loop counter variable (if any) is always
5098 nonnegative; if so, record that fact with a REG_NONNEG note
5099 so that "decrement and branch until zero" insn can be used. */
5102 /* Create reg_map to hold substitutions for replaceable giv regs.
5103 Some givs might have been made from biv increments, so look at
5104 ivs->reg_iv_type for a suitable size. */
5108 /* Examine each iv class for feasibility of strength reduction/induction
5109 variable elimination. */
5112 {
5116 /* Test whether it will be possible to eliminate this biv
5117 provided all givs are reduced. */
5120 /* This will be true at the end, if all givs which depend on this
5121 biv have been strength reduced.
5122 We can't (currently) eliminate the biv unless this is so. */
5125 /* Check each extension dependent giv in this class to see if its
5126 root biv is safe from wrapping in the interior mode. */
5129 /* Combine all giv's for this iv_class. */
5133 {
5141 /* If an insn is not to be strength reduced, then set its ignore
5142 flag, and clear bl->all_reduced. */
5144 /* A giv that depends on a reversed biv must be reduced if it is
5145 used after the loop exit, otherwise, it would have the wrong
5146 value after the loop exit. To make it simple, just reduce all
5147 of such giv's whether or not we know they are used after the loop
5148 exit. */
5153 {
5161 }
5162 else
5163 {
5164 /* Check that we can increment the reduced giv without a
5165 multiply insn. If not, reject it. */
5170 {
5178 }
5179 }
5180 }
5182 /* Check for givs whose first use is their definition and whose
5183 last use is the definition of another giv. If so, it is likely
5184 dead and should not be used to derive another giv nor to
5185 eliminate a biv. */
5188 /* Reduce each giv that we decided to reduce. */
5191 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5192 as not reduced.
5194 For each giv register that can be reduced now: if replaceable,
5195 substitute reduced reg wherever the old giv occurs;
5196 else add new move insn "giv_reg = reduced_reg". */
5199 /* All the givs based on the biv bl have been reduced if they
5200 merit it. */
5202 /* For each giv not marked as maybe dead that has been combined with a
5203 second giv, clear any "maybe dead" mark on that second giv.
5204 v->new_reg will either be or refer to the register of the giv it
5205 combined with.
5207 Doing this clearing avoids problems in biv elimination where
5208 a giv's new_reg is a complex value that can't be put in the
5209 insn but the giv combined with (with a reg as new_reg) is
5210 marked maybe_dead. Since the register will be used in either
5211 case, we'd prefer it be used from the simpler giv. */
5217 /* Try to eliminate the biv, if it is a candidate.
5218 This won't work if ! bl->all_reduced,
5219 since the givs we planned to use might not have been reduced.
5221 We have to be careful that we didn't initially think we could
5222 eliminate this biv because of a giv that we now think may be
5223 dead and shouldn't be used as a biv replacement.
5225 Also, there is the possibility that we may have a giv that looks
5226 like it can be used to eliminate a biv, but the resulting insn
5227 isn't valid. This can happen, for example, on the 88k, where a
5228 JUMP_INSN can compare a register only with zero. Attempts to
5229 replace it with a compare with a constant will fail.
5231 Note that in cases where this call fails, we may have replaced some
5232 of the occurrences of the biv with a giv, but no harm was done in
5233 doing so in the rare cases where it can occur. */
5237 {
5238 /* ?? If we created a new test to bypass the loop entirely,
5239 or otherwise drop straight in, based on this test, then
5240 we might want to rewrite it also. This way some later
5241 pass has more hope of removing the initialization of this
5242 biv entirely. */
5244 /* If final_value != 0, then the biv may be used after loop end
5245 and we must emit an insn to set it just in case.
5247 Reversed bivs already have an insn after the loop setting their
5248 value, so we don't need another one. We can't calculate the
5249 proper final value for such a biv here anyways. */
5258 }
5259 /* See above note wrt final_value. But since we couldn't eliminate
5260 the biv, we must set the value after the loop instead of before. */
5264 }
5266 /* Go through all the instructions in the loop, making all the
5267 register substitutions scheduled in REG_MAP. */
5272 {
5276 }
5279 {
5280 /* When we completely unroll a loop we will likely not need the increment
5281 of the loop BIV and we will not need the conditional branch at the
5282 end of the loop. */
5285 #ifdef HAVE_cc0
5286 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5287 need the comparison before the conditional branch at the end of the
5288 loop. */
5290 #endif
5292 /* We'll need one copy for each loop iteration. */
5295 /* A little slop to account for the ability to remove initialization
5296 code, better CSE, and other secondary benefits of completely
5297 unrolling some loops. */
5300 /* Clamp the value. */
5303 }
5305 /* Unroll loops from within strength reduction so that we can use the
5306 induction variable information that strength_reduce has already
5307 collected. Always unroll loops that would be as small or smaller
5308 unrolled than when rolled. */
5315 #ifdef HAVE_doloop_end
5320 /* In case number of iterations is known, drop branch prediction note
5321 in the branch. Do that only in second loop pass, as loop unrolling
5322 may change the number of iterations performed. */
5324 {
5325 unsigned HOST_WIDE_INT n
5330 }
5338 }
5339 \f
5340 /*Record all basic induction variables calculated in the insn. */
5341 static rtx
5344 rtx p;
5347 {
5349 rtx set;
5350 rtx dest_reg;
5351 rtx inc_val;
5352 rtx mult_val;
5358 {
5363 {
5368 {
5369 /* It is a possible basic induction variable.
5370 Create and initialize an induction structure for it. */
5378 }
5381 }
5382 }
5384 }
5385 \f
5386 /* Record all givs calculated in the insn.
5387 A register is a giv if: it is only set once, it is a function of a
5388 biv and a constant (or invariant), and it is not a biv. */
5389 static rtx
5392 rtx p;
5395 {
5398 rtx set;
5399 /* Look for a general induction variable in a register. */
5404 {
5405 rtx src_reg;
5406 rtx dest_reg;
5407 rtx add_val;
5408 rtx mult_val;
5409 rtx ext_val;
5412 rtx last_consec_insn;
5421 /* Equivalent expression is a giv. */
5426 /* Don't try to handle any regs made by loop optimization.
5427 We have nothing on them in regno_first_uid, etc. */
5429 /* Don't recognize a BASIC_INDUCT_VAR here. */
5431 /* This must be the only place where the register is set. */
5433 /* or all sets must be consecutive and make a giv. */
5438 {
5442 /* If this is a library call, increase benefit. */
5446 /* Skip the consecutive insns, if there are any. */
5454 }
5455 }
5457 #ifndef DONT_REDUCE_ADDR
5458 /* Look for givs which are memory addresses. */
5459 /* This resulted in worse code on a VAX 8600. I wonder if it
5460 still does. */
5463 maybe_multiple);
5464 #endif
5466 /* Update the status of whether giv can derive other givs. This can
5467 change when we pass a label or an insn that updates a biv. */
5472 }
5473 \f
5474 /* Return 1 if X is a valid source for an initial value (or as value being
5475 compared against in an initial test).
5477 X must be either a register or constant and must not be clobbered between
5478 the current insn and the start of the loop.
5480 INSN is the insn containing X. */
5482 static int
5484 rtx x;
5485 rtx insn;
5487 rtx loop_start;
5488 {
5492 /* Only consider pseudos we know about initialized in insns whose luids
5493 we know. */
5498 /* Don't use call-clobbered registers across a call which clobbers it. On
5499 some machines, don't use any hard registers at all. */
5501 && (SMALL_REGISTER_CLASSES
5505 /* Don't use registers that have been clobbered before the start of the
5506 loop. */
5511 }
5512 \f
5513 /* Scan X for memory refs and check each memory address
5514 as a possible giv. INSN is the insn whose pattern X comes from.
5515 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5516 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5517 more thanonce in each loop iteration. */
5519 static void
5522 rtx x;
5523 rtx insn;
5525 {
5535 {
5551 {
5552 rtx src_reg;
5553 rtx add_val;
5554 rtx mult_val;
5555 rtx ext_val;
5558 /* This code used to disable creating GIVs with mult_val == 1 and
5559 add_val == 0. However, this leads to lost optimizations when
5560 it comes time to combine a set of related DEST_ADDR GIVs, since
5561 this one would not be seen. */
5566 {
5567 /* Found one; record it. */
5576 }
5577 }
5582 }
5584 /* Recursively scan the subexpressions for other mem refs. */
5590 maybe_multiple);
5594 maybe_multiple);
5595 }
5596 \f
5597 /* Fill in the data about one biv update.
5598 V is the `struct induction' in which we record the biv. (It is
5599 allocated by the caller, with alloca.)
5600 INSN is the insn that sets it.
5601 DEST_REG is the biv's reg.
5603 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5604 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5605 being set to INC_VAL.
5607 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5608 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5609 can be executed more than once per iteration. If MAYBE_MULTIPLE
5610 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5611 executed exactly once per iteration. */
5613 static void
5618 rtx insn;
5619 rtx dest_reg;
5620 rtx inc_val;
5621 rtx mult_val;
5625 {
5641 /* Add this to the reg's iv_class, creating a class
5642 if this is the first incrementation of the reg. */
5646 {
5647 /* Create and initialize new iv_class. */
5657 /* Set initial value to the reg itself. */
5660 /* We haven't seen the initializing insn yet */
5670 /* Add this class to ivs->list. */
5674 /* Put it in the array of biv register classes. */
5676 }
5678 /* Update IV_CLASS entry for this biv. */
5687 }
5688 \f
5689 /* Fill in the data about one giv.
5690 V is the `struct induction' in which we record the giv. (It is
5691 allocated by the caller, with alloca.)
5692 INSN is the insn that sets it.
5693 BENEFIT estimates the savings from deleting this insn.
5694 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5695 into a register or is used as a memory address.
5697 SRC_REG is the biv reg which the giv is computed from.
5698 DEST_REG is the giv's reg (if the giv is stored in a reg).
5699 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5700 LOCATION points to the place where this giv's value appears in INSN. */
5702 static void
5707 rtx insn;
5708 rtx src_reg;
5709 rtx dest_reg;
5715 {
5720 rtx temp;
5722 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5723 undo the MULT canonicalization that we performed earlier. */
5753 /* The v->always_computable field is used in update_giv_derive, to
5754 determine whether a giv can be used to derive another giv. For a
5755 DEST_REG giv, INSN computes a new value for the giv, so its value
5756 isn't computable if INSN insn't executed every iteration.
5757 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5758 it does not compute a new value. Hence the value is always computable
5759 regardless of whether INSN is executed each iteration. */
5763 else
5769 {
5772 }
5774 {
5779 /* If the lifetime is zero, it means that this register is
5780 really a dead store. So mark this as a giv that can be
5781 ignored. This will not prevent the biv from being eliminated. */
5787 }
5789 /* Add the giv to the class of givs computed from one biv. */
5793 {
5796 /* Don't count DEST_ADDR. This is supposed to count the number of
5797 insns that calculate givs. */
5801 }
5802 else
5803 /* Fatal error, biv missing for this giv? */
5808 else
5809 {
5810 /* The giv can be replaced outright by the reduced register only if all
5811 of the following conditions are true:
5812 - the insn that sets the giv is always executed on any iteration
5813 on which the giv is used at all
5814 (there are two ways to deduce this:
5815 either the insn is executed on every iteration,
5816 or all uses follow that insn in the same basic block),
5817 - the giv is not used outside the loop
5818 - no assignments to the biv occur during the giv's lifetime. */
5821 /* Previous line always fails if INSN was moved by loop opt. */
5824 && (! not_every_iteration
5826 {
5827 /* Now check that there are no assignments to the biv within the
5828 giv's lifetime. This requires two separate checks. */
5830 /* Check each biv update, and fail if any are between the first
5831 and last use of the giv.
5833 If this loop contains an inner loop that was unrolled, then
5834 the insn modifying the biv may have been emitted by the loop
5835 unrolling code, and hence does not have a valid luid. Just
5836 mark the biv as not replaceable in this case. It is not very
5837 useful as a biv, because it is used in two different loops.
5838 It is very unlikely that we would be able to optimize the giv
5839 using this biv anyways. */
5843 {
5849 {
5853 }
5854 }
5856 /* If there are any backwards branches that go from after the
5857 biv update to before it, then this giv is not replaceable. */
5861 {
5865 }
5866 }
5867 else
5868 {
5869 /* May still be replaceable, we don't have enough info here to
5870 decide. */
5873 }
5874 }
5876 /* Record whether the add_val contains a const_int, for later use by
5877 combine_givs. */
5878 {
5883 ;
5887 {
5889 {
5894 else
5896 }
5899 }
5900 }
5904 }
5906 /* All this does is determine whether a giv can be made replaceable because
5907 its final value can be calculated. This code can not be part of record_giv
5908 above, because final_giv_value requires that the number of loop iterations
5909 be known, and that can not be accurately calculated until after all givs
5910 have been identified. */
5912 static void
5916 {
5923 /* DEST_ADDR givs will never reach here, because they are always marked
5924 replaceable above in record_giv. */
5926 /* The giv can be replaced outright by the reduced register only if all
5927 of the following conditions are true:
5928 - the insn that sets the giv is always executed on any iteration
5929 on which the giv is used at all
5930 (there are two ways to deduce this:
5931 either the insn is executed on every iteration,
5932 or all uses follow that insn in the same basic block),
5933 - its final value can be calculated (this condition is different
5934 than the one above in record_giv)
5935 - it's not used before the it's set
5936 - no assignments to the biv occur during the giv's lifetime. */
5938 #if 0
5939 /* This is only called now when replaceable is known to be false. */
5940 /* Clear replaceable, so that it won't confuse final_giv_value. */
5942 #endif
5947 {
5950 rtx last_giv_use;
5954 /* When trying to determine whether or not a biv increment occurs
5955 during the lifetime of the giv, we can ignore uses of the variable
5956 outside the loop because final_value is true. Hence we can not
5957 use regno_last_uid and regno_first_uid as above in record_giv. */
5959 /* Search the loop to determine whether any assignments to the
5960 biv occur during the giv's lifetime. Start with the insn
5961 that sets the giv, and search around the loop until we come
5962 back to that insn again.
5964 Also fail if there is a jump within the giv's lifetime that jumps
5965 to somewhere outside the lifetime but still within the loop. This
5966 catches spaghetti code where the execution order is not linear, and
5967 hence the above test fails. Here we assume that the giv lifetime
5968 does not extend from one iteration of the loop to the next, so as
5969 to make the test easier. Since the lifetime isn't known yet,
5970 this requires two loops. See also record_giv above. */
5975 {
5978 {
5981 }
5987 {
5988 /* It is possible for the BIV increment to use the GIV if we
5989 have a cycle. Thus we must be sure to check each insn for
5990 both BIV and GIV uses, and we must check for BIV uses
5991 first. */
5998 {
6000 {
6004 }
6006 }
6007 }
6008 }
6010 /* Now that the lifetime of the giv is known, check for branches
6011 from within the lifetime to outside the lifetime if it is still
6012 replaceable. */
6015 {
6018 {
6031 {
6040 }
6041 }
6042 }
6044 /* If it is replaceable, then save the final value. */
6047 }
6052 }
6053 \f
6054 /* Update the status of whether a giv can derive other givs.
6056 We need to do something special if there is or may be an update to the biv
6057 between the time the giv is defined and the time it is used to derive
6058 another giv.
6060 In addition, a giv that is only conditionally set is not allowed to
6061 derive another giv once a label has been passed.
6063 The cases we look at are when a label or an update to a biv is passed. */
6065 static void
6068 rtx p;
6069 {
6073 rtx tem;
6076 /* Search all IV classes, then all bivs, and finally all givs.
6078 There are three cases we are concerned with. First we have the situation
6079 of a giv that is only updated conditionally. In that case, it may not
6080 derive any givs after a label is passed.
6082 The second case is when a biv update occurs, or may occur, after the
6083 definition of a giv. For certain biv updates (see below) that are
6084 known to occur between the giv definition and use, we can adjust the
6085 giv definition. For others, or when the biv update is conditional,
6086 we must prevent the giv from deriving any other givs. There are two
6087 sub-cases within this case.
6089 If this is a label, we are concerned with any biv update that is done
6090 conditionally, since it may be done after the giv is defined followed by
6091 a branch here (actually, we need to pass both a jump and a label, but
6092 this extra tracking doesn't seem worth it).
6094 If this is a jump, we are concerned about any biv update that may be
6095 executed multiple times. We are actually only concerned about
6096 backward jumps, but it is probably not worth performing the test
6097 on the jump again here.
6099 If this is a biv update, we must adjust the giv status to show that a
6100 subsequent biv update was performed. If this adjustment cannot be done,
6101 the giv cannot derive further givs. */
6107 {
6109 {
6110 /* If cant_derive is already true, there is no point in
6111 checking all of these conditions again. */
6115 /* If this giv is conditionally set and we have passed a label,
6116 it cannot derive anything. */
6120 /* Skip givs that have mult_val == 0, since
6121 they are really invariants. Also skip those that are
6122 replaceable, since we know their lifetime doesn't contain
6123 any biv update. */
6127 /* The only way we can allow this giv to derive another
6128 is if this is a biv increment and we can form the product
6129 of biv->add_val and giv->mult_val. In this case, we will
6130 be able to compute a compensation. */
6132 {
6133 rtx ext_val_dummy;
6144 tem = simplify_giv_expr
6151 else
6153 }
6157 }
6158 }
6159 }
6160 \f
6161 /* Check whether an insn is an increment legitimate for a basic induction var.
6162 X is the source of insn P, or a part of it.
6163 MODE is the mode in which X should be interpreted.
6165 DEST_REG is the putative biv, also the destination of the insn.
6166 We accept patterns of these forms:
6167 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6168 REG = INVARIANT + REG
6170 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6171 store the additive term into *INC_VAL, and store the place where
6172 we found the additive term into *LOCATION.
6174 If X is an assignment of an invariant into DEST_REG, we set
6175 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6177 We also want to detect a BIV when it corresponds to a variable
6178 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6179 of the variable may be a PLUS that adds a SUBREG of that variable to
6180 an invariant and then sign- or zero-extends the result of the PLUS
6181 into the variable.
6183 Most GIVs in such cases will be in the promoted mode, since that is the
6184 probably the natural computation mode (and almost certainly the mode
6185 used for addresses) on the machine. So we view the pseudo-reg containing
6186 the variable as the BIV, as if it were simply incremented.
6188 Note that treating the entire pseudo as a BIV will result in making
6189 simple increments to any GIVs based on it. However, if the variable
6190 overflows in its declared mode but not its promoted mode, the result will
6191 be incorrect. This is acceptable if the variable is signed, since
6192 overflows in such cases are undefined, but not if it is unsigned, since
6193 those overflows are defined. So we only check for SIGN_EXTEND and
6194 not ZERO_EXTEND.
6196 If we cannot find a biv, we return 0. */
6198 static int
6201 rtx x;
6203 rtx dest_reg;
6204 rtx p;
6208 {
6216 {
6222 {
6224 }
6229 {
6231 }
6232 else
6245 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6246 handle addition of promoted variables.
6247 ??? The comment at the start of this function is wrong: promoted
6248 variable increments don't look like it says they do. */
6254 /* If this register is assigned in a previous insn, look at its
6255 source, but don't go outside the loop or past a label. */
6257 /* If this sets a register to itself, we would repeat any previous
6258 biv increment if we applied this strategy blindly. */
6264 {
6265 rtx dest;
6266 do
6267 {
6269 }
6298 }
6299 /* Fall through. */
6301 /* Can accept constant setting of biv only when inside inner most loop.
6302 Otherwise, a biv of an inner loop may be incorrectly recognized
6303 as a biv of the outer loop,
6304 causing code to be moved INTO the inner loop. */
6311 /* convert_modes aborts if we try to convert to or from CCmode, so just
6312 exclude that case. It is very unlikely that a condition code value
6313 would be a useful iterator anyways. convert_modes aborts if we try to
6314 convert a float mode to non-float or vice versa too. */
6318 {
6319 /* Possible bug here? Perhaps we don't know the mode of X. */
6323 }
6324 else
6332 /* Similar, since this can be a sign extension. */
6337 ;
6351 location);
6356 }
6357 }
6358 \f
6359 /* A general induction variable (giv) is any quantity that is a linear
6360 function of a basic induction variable,
6361 i.e. giv = biv * mult_val + add_val.
6362 The coefficients can be any loop invariant quantity.
6363 A giv need not be computed directly from the biv;
6364 it can be computed by way of other givs. */
6366 /* Determine whether X computes a giv.
6367 If it does, return a nonzero value
6368 which is the benefit from eliminating the computation of X;
6369 set *SRC_REG to the register of the biv that it is computed from;
6370 set *ADD_VAL and *MULT_VAL to the coefficients,
6371 such that the value of X is biv * mult + add; */
6373 static int
6377 rtx x;
6385 {
6389 /* If this is an invariant, forget it, it isn't a giv. */
6400 {
6403 /* Since this is now an invariant and wasn't before, it must be a giv
6404 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6405 with. */
6412 /* This is equivalent to a BIV. */
6419 /* Either (plus (biv) (invar)) or
6420 (plus (mult (biv) (invar_1)) (invar_2)). */
6422 {
6425 }
6426 else
6427 {
6430 }
6435 /* ADD_VAL is zero. */
6443 }
6445 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6446 unless they are CONST_INT). */
6454 else
6457 /* Always return true if this is a giv so it will be detected as such,
6458 even if the benefit is zero or negative. This allows elimination
6459 of bivs that might otherwise not be eliminated. */
6461 }
6462 \f
6463 /* Given an expression, X, try to form it as a linear function of a biv.
6464 We will canonicalize it to be of the form
6465 (plus (mult (BIV) (invar_1))
6466 (invar_2))
6467 with possible degeneracies.
6469 The invariant expressions must each be of a form that can be used as a
6470 machine operand. We surround then with a USE rtx (a hack, but localized
6471 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6472 routine; it is the caller's responsibility to strip them.
6474 If no such canonicalization is possible (i.e., two biv's are used or an
6475 expression that is neither invariant nor a biv or giv), this routine
6476 returns 0.
6478 For a non-zero return, the result will have a code of CONST_INT, USE,
6479 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6481 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6486 static rtx
6489 rtx x;
6492 {
6497 rtx tem;
6499 /* If this is not an integer mode, or if we cannot do arithmetic in this
6500 mode, this can't be a giv. */
6507 {
6514 /* Put constant last, CONST_INT last if both constant. */
6522 /* Handle addition of zero, then addition of an invariant. */
6527 {
6530 /* Adding two invariants must result in an invariant, so enclose
6531 addition operation inside a USE and return it. */
6541 else
6550 /* biv + invar or mult + invar. Return sum. */
6554 /* (a + invar_1) + invar_2. Associate. */
6555 return
6561 arg1)),
6566 }
6568 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6569 MULT to reduce cases. */
6575 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6576 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6577 Recurse to associate the second PLUS. */
6582 return
6590 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6606 /* Handle "a - b" as "a + b * (-1)". */
6612 constm1_rtx)),
6621 /* Put constant last, CONST_INT last if both constant. */
6626 /* If second argument is not now constant, not giv. */
6630 /* Handle multiply by 0 or 1. */
6638 {
6640 /* biv * invar. Done. */
6644 /* Product of two constants. */
6648 /* invar * invar is a giv, but attempt to simplify it somehow. */
6654 {
6655 /* (invar_0 * invar_1) * invar_2. Associate. */
6662 arg1)),
6664 }
6665 /* Porpagate the MULT expressions to the intermost nodes. */
6667 {
6668 /* (invar_0 + invar_1) * invar_2. Distribute. */
6674 arg1),
6678 arg1)),
6680 }
6684 /* (a * invar_1) * invar_2. Associate. */
6690 arg1)),
6694 /* (a + invar_1) * invar_2. Distribute. */
6699 arg1),
6702 arg1)),
6707 }
6710 /* Shift by constant is multiply by power of two. */
6714 return
6723 /* "-a" is "a * (-1)" */
6729 /* "~a" is "-a - 1". Silly, but easy. */
6733 const1_rtx),
6737 /* Already in proper form for invariant. */
6743 /* Conditionally recognize extensions of simple IVs. After we've
6744 computed loop traversal counts and verified the range of the
6745 source IV, we'll reevaluate this as a GIV. */
6747 {
6750 {
6753 }
6754 }
6758 /* If this is a new register, we can't deal with it. */
6762 /* Check for biv or giv. */
6764 {
6768 {
6771 /* Form expression from giv and add benefit. Ensure this giv
6772 can derive another and subtract any needed adjustment if so. */
6774 /* Increasing the benefit here is risky. The only case in which it
6775 is arguably correct is if this is the only use of V. In other
6776 cases, this will artificially inflate the benefit of the current
6777 giv, and lead to suboptimal code. Thus, it is disabled, since
6778 potentially not reducing an only marginally beneficial giv is
6779 less harmful than reducing many givs that are not really
6780 beneficial. */
6781 {
6785 }
6798 {
6801 }
6802 else
6803 {
6806 }
6808 }
6811 do_default:
6812 /* If it isn't an induction variable, and it is invariant, we
6813 may be able to simplify things further by looking through
6814 the bits we just moved outside the loop. */
6816 {
6822 {
6823 /* Ok, we found a match. Substitute and simplify. */
6825 /* If we match another movable, we must use that, as
6826 this one is going away. */
6831 /* If consec is non-zero, this is a member of a group of
6832 instructions that were moved together. We handle this
6833 case only to the point of seeking to the last insn and
6834 looking for a REG_EQUAL. Fail if we don't find one. */
6836 {
6839 do
6840 {
6842 }
6848 }
6849 else
6850 {
6854 }
6857 {
6858 /* What we are most interested in is pointer
6859 arithmetic on invariants -- only take
6860 patterns we may be able to do something with. */
6866 {
6868 benefit);
6871 }
6876 {
6881 }
6882 }
6884 }
6885 }
6887 }
6889 /* Fall through to general case. */
6891 /* If invariant, return as USE (unless CONST_INT).
6892 Otherwise, not giv. */
6897 {
6906 }
6907 else
6909 }
6910 }
6912 /* This routine folds invariants such that there is only ever one
6913 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6915 static rtx
6918 {
6924 {
6927 }
6930 {
6933 }
6934 else
6935 {
6938 }
6939 }
6941 static rtx
6945 {
6947 {
6951 else
6954 }
6957 else
6960 }
6961 \f
6962 /* Help detect a giv that is calculated by several consecutive insns;
6963 for example,
6964 giv = biv * M
6965 giv = giv + A
6966 The caller has already identified the first insn P as having a giv as dest;
6967 we check that all other insns that set the same register follow
6968 immediately after P, that they alter nothing else,
6969 and that the result of the last is still a giv.
6971 The value is 0 if the reg set in P is not really a giv.
6972 Otherwise, the value is the amount gained by eliminating
6973 all the consecutive insns that compute the value.
6975 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6976 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6978 The coefficients of the ultimate giv value are stored in
6979 *MULT_VAL and *ADD_VAL. */
6981 static int
6986 rtx p;
6987 rtx src_reg;
6988 rtx dest_reg;
6993 {
6999 rtx temp;
7000 rtx set;
7002 /* Indicate that this is a giv so that we can update the value produced in
7003 each insn of the multi-insn sequence.
7005 This induction structure will be used only by the call to
7006 general_induction_var below, so we can allocate it on our stack.
7007 If this is a giv, our caller will replace the induct var entry with
7008 a new induction structure. */
7029 {
7033 /* If libcall, skip to end of call sequence. */
7044 /* Giv created by equivalent expression. */
7050 {
7054 count--;
7058 }
7060 {
7061 /* Allow insns that set something other than this giv to a
7062 constant. Such insns are needed on machines which cannot
7063 include long constants and should not disqualify a giv. */
7072 }
7073 }
7078 }
7079 \f
7080 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7081 represented by G1. If no such expression can be found, or it is clear that
7082 it cannot possibly be a valid address, 0 is returned.
7084 To perform the computation, we note that
7085 G1 = x * v + a and
7086 G2 = y * v + b
7087 where `v' is the biv.
7089 So G2 = (y/b) * G1 + (b - a*y/x).
7091 Note that MULT = y/x.
7093 Update: A and B are now allowed to be additive expressions such that
7094 B contains all variables in A. That is, computing B-A will not require
7095 subtracting variables. */
7097 static rtx
7100 {
7101 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7106 /* If MULT is not 1, we cannot handle A with non-constants, since we
7107 would then be required to subtract multiples of the registers in A.
7108 This is theoretically possible, and may even apply to some Fortran
7109 constructs, but it is a lot of work and we do not attempt it here. */
7114 /* In general these structures are sorted top to bottom (down the PLUS
7115 chain), but not left to right across the PLUS. If B is a higher
7116 order giv than A, we can strip one level and recurse. If A is higher
7117 order, we'll eventually bail out, but won't know that until the end.
7118 If they are the same, we'll strip one level around this loop. */
7121 {
7133 /* We matched: remove one reg completely. */
7136 /* An alternate match. */
7139 /* An alternate match. */
7141 else
7142 {
7143 /* Indicates an extra register in B. Strip one level from B and
7144 recurse, hoping B was the higher order expression. */
7149 }
7150 }
7152 /* Here we are at the last level of A, go through the cases hoping to
7153 get rid of everything but a constant. */
7156 {
7169 }
7171 {
7173 }
7175 {
7180 }
7182 {
7187 else
7189 }
7194 }
7196 rtx
7199 {
7202 /* The value that G1 will be multiplied by must be a constant integer. Also,
7203 the only chance we have of getting a valid address is if b*c/a (see above
7204 for notation) is also an integer. */
7207 {
7212 }
7215 else
7216 {
7217 /* ??? Find out if the one is a multiple of the other? */
7219 }
7223 {
7224 /* Failed. If we've got a multiplication factor between G1 and G2,
7225 scale G1's addend and try again. */
7227 {
7231 {
7232 HOST_WIDE_INT m;
7236 }
7237 else
7238 {
7240 mult);
7241 }
7244 }
7245 }
7249 /* Form simplified final result. */
7254 else
7259 else
7260 {
7263 {
7267 }
7270 }
7271 }
7272 \f
7273 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7274 represented by G1. This indicates that G2 should be combined with G1 and
7275 that G2 can use (either directly or via an address expression) a register
7276 used to represent G1. */
7278 static rtx
7281 {
7284 /* With the introduction of ext dependent givs, we must care for modes.
7285 G2 must not use a wider mode than G1. */
7295 /* If these givs are identical, they can be combined. We use the results
7296 of express_from because the addends are not in a canonical form, so
7297 rtx_equal_p is a weaker test. */
7298 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7299 combination to be the other way round. */
7302 {
7304 }
7306 /* If G2 can be expressed as a function of G1 and that function is valid
7307 as an address and no more expensive than using a register for G2,
7308 the expression of G2 in terms of G1 can be used. */
7312 /* ??? Looses, especially with -fforce-addr, where *g2->location
7313 will always be a register, and so anything more complicated
7314 gets discarded. */
7315 #if 0
7316 #ifdef ADDRESS_COST
7318 #else
7320 #endif
7321 #endif
7322 )
7323 {
7325 }
7328 }
7329 \f
7330 /* Check each extension dependent giv in this class to see if its
7331 root biv is safe from wrapping in the interior mode, which would
7332 make the giv illegal. */
7334 static void
7338 {
7341 HOST_WIDE_INT start_val;
7347 /* Make sure the iteration data is available. We must have
7348 constants in order to be certain of no overflow. */
7349 /* ??? An unknown iteration count with an increment of +-1
7350 combined with friendly exit tests of against an invariant
7351 value is also ameanable to optimization. Not implemented. */
7357 /* Make sure the host can represent the arithmetic. */
7359 {
7361 HOST_WIDE_INT s_end_val;
7373 /* Check for host arithmatic overflow. */
7375 {
7377 HOST_WIDE_INT s_max;
7384 /* Check zero extension of biv ok. */
7386 /* Check for host arithmatic overflow. */
7387 && (neg_incr
7390 /* Check for target arithmetic overflow. */
7391 && (neg_incr
7394 {
7396 }
7398 /* Check sign extension of biv ok. */
7399 /* ??? While it is true that overflow with signed and pointer
7400 arithmetic is undefined, I fear too many programmers don't
7401 keep this fact in mind -- myself included on occasion.
7402 So leave alone with the signed overflow optimizations. */
7404 /* Check for host arithmatic overflow. */
7405 && (neg_incr
7408 /* Check for target arithmetic overflow. */
7409 && (neg_incr
7412 {
7414 }
7415 }
7416 }
7418 /* Invalidate givs that fail the tests. */
7421 {
7426 {
7435 /* We don't know whether this value is being used as either
7436 signed or unsigned, so to safely truncate we must satisfy
7437 both. The initial check here verifies the BIV itself;
7438 once that is successful we may check its range wrt the
7439 derived GIV. */
7441 {
7445 /* We know from the above that both endpoints are nonnegative,
7446 and that there is no wrapping. Verify that both endpoints
7447 are within the (signed) range of the outer mode. */
7450 }
7455 }
7458 {
7460 {
7464 }
7465 }
7466 else
7467 {
7469 {
7474 else
7475 {
7480 else
7482 }
7487 }
7490 }
7491 }
7492 }
7494 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7496 rtx
7499 rtx value;
7500 {
7506 /* Recall that check_ext_dependent_givs verified that the known bounds
7507 of a biv did not overflow or wrap with respect to the extension for
7508 the giv. Therefore, constants need no additional adjustment. */
7512 /* Otherwise, we must adjust the value to compensate for the
7513 differing modes of the biv and the giv. */
7515 }
7516 \f
7517 struct combine_givs_stats
7518 {
7521 };
7523 static int
7527 {
7534 /* Stabilize the sort. */
7538 }
7540 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7541 any other. If so, point SAME to the giv combined with and set NEW_REG to
7542 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7543 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7545 static void
7549 {
7550 /* Additional benefit to add for being combined multiple times. */
7558 /* Count givs, because bl->giv_count is incorrect here. */
7562 giv_count++;
7564 giv_array
7575 {
7577 rtx single_use;
7582 /* If a DEST_REG GIV is used only once, do not allow it to combine
7583 with anything, for in doing so we will gain nothing that cannot
7584 be had by simply letting the GIV with which we would have combined
7585 to be reduced on its own. The losage shows up in particular with
7586 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7587 be seen elsewhere as well. */
7594 /* Add an additional weight for zero addends. */
7599 {
7600 rtx this_combine;
7605 {
7608 }
7609 }
7611 }
7613 /* Iterate, combining until we can't. */
7614 restart:
7618 {
7621 {
7627 }
7629 }
7632 {
7638 /* If it has already been combined, skip. */
7643 {
7646 /* If it has already been combined, skip. */
7648 {
7653 /* For destination, we now may replace by mem expression instead
7654 of register. This changes the costs considerably, so add the
7655 compensation. */
7665 /* ??? The new final_[bg]iv_value code does a much better job
7666 of finding replaceable giv's, and hence this code may no
7667 longer be necessary. */
7671 /* To help optimize the next set of combinations, remove
7672 this giv from the benefits of other potential mates. */
7674 {
7678 }
7685 }
7686 }
7688 /* To help optimize the next set of combinations, remove
7689 this giv from the benefits of other potential mates. */
7691 {
7693 {
7697 }
7701 /* We've finished with this giv, and everything it touched.
7702 Restart the combination so that proper weights for the
7703 rest of the givs are properly taken into account. */
7704 /* ??? Ideally we would compact the arrays at this point, so
7705 as to not cover old ground. But sanely compacting
7706 can_combine is tricky. */
7708 }
7709 }
7711 /* Clean up. */
7714 }
7715 \f
7716 /* Generate sequence for REG = B * M + A. */
7718 static rtx
7724 {
7725 rtx seq;
7726 rtx result;
7729 /* Use unsigned arithmetic. */
7737 }
7740 /* Update registers created in insn sequence SEQ. */
7742 static void
7745 rtx seq;
7746 {
7747 rtx insn;
7749 /* Update register info for alias analysis. */
7755 {
7758 {
7765 }
7766 }
7770 }
7773 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7775 void
7782 basic_block before_bb;
7783 rtx before_insn;
7784 {
7785 rtx seq;
7788 {
7791 }
7793 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7796 /* Increase the lifetime of any invariants moved further in code. */
7803 /* It is possible that the expansion created lots of new registers.
7804 Iterate over the sequence we just created and record them all. */
7806 }
7809 /* Emit insns in loop pre-header to set REG = B * M + A. */
7811 void
7818 {
7819 rtx seq;
7821 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7824 /* Increase the lifetime of any invariants moved further in code.
7825 ???? Is this really necessary? */
7832 /* It is possible that the expansion created lots of new registers.
7833 Iterate over the sequence we just created and record them all. */
7835 }
7838 /* Emit insns after loop to set REG = B * M + A. */
7840 void
7847 {
7848 rtx seq;
7850 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7855 /* It is possible that the expansion created lots of new registers.
7856 Iterate over the sequence we just created and record them all. */
7858 }
7862 /* Similar to gen_add_mult, but compute cost rather than generating
7863 sequence. */
7865 static int
7871 {
7881 {
7886 }
7889 }
7890 \f
7891 /* Test whether A * B can be computed without
7892 an actual multiply insn. Value is 1 if so.
7894 ??? This function stinks because it generates a ton of wasted RTL
7895 ??? and as a result fragments GC memory to no end. There are other
7896 ??? places in the compiler which are invoked a lot and do the same
7897 ??? thing, generate wasted RTL just to see if something is possible. */
7899 static int
7901 rtx a;
7902 rtx b;
7903 {
7904 rtx tmp;
7907 /* If only one is constant, make it B. */
7911 /* If first constant, both constant, so don't need multiply. */
7915 /* If second not constant, neither is constant, so would need multiply. */
7919 /* One operand is constant, so might not need multiply insn. Generate the
7920 code for the multiply and see if a call or multiply, or long sequence
7921 of insns is generated. */
7930 {
7933 {
7943 {
7946 }
7949 }
7950 }
7960 }
7961 \f
7962 /* Check to see if loop can be terminated by a "decrement and branch until
7963 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7964 Also try reversing an increment loop to a decrement loop
7965 to see if the optimization can be performed.
7966 Value is nonzero if optimization was performed. */
7968 /* This is useful even if the architecture doesn't have such an insn,
7969 because it might change a loops which increments from 0 to n to a loop
7970 which decrements from n to 0. A loop that decrements to zero is usually
7971 faster than one that increments from zero. */
7973 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7974 such as approx_final_value, biv_total_increment, loop_iterations, and
7975 final_[bg]iv_value. */
7977 static int
7981 {
7986 rtx reg;
7987 rtx jump_label;
7988 rtx final_value;
7989 rtx start_value;
7990 rtx new_add_val;
7991 rtx comparison;
7992 rtx before_comparison;
7993 rtx p;
7994 rtx jump;
7995 rtx first_compare;
8000 /* If last insn is a conditional branch, and the insn before tests a
8001 register value, try to optimize it. Otherwise, we can't do anything. */
8010 /* Try to compute whether the compare/branch at the loop end is one or
8011 two instructions. */
8017 else
8020 {
8021 /* If more than one condition is present to control the loop, then
8022 do not proceed, as this function does not know how to rewrite
8023 loop tests with more than one condition.
8025 Look backwards from the first insn in the last comparison
8026 sequence and see if we've got another comparison sequence. */
8028 rtx jump1;
8032 }
8034 /* Check all of the bivs to see if the compare uses one of them.
8035 Skip biv's set more than once because we can't guarantee that
8036 it will be zero on the last iteration. Also skip if the biv is
8037 used between its update and the test insn. */
8040 {
8045 first_compare))
8047 }
8052 /* Look for the case where the basic induction variable is always
8053 nonnegative, and equals zero on the last iteration.
8054 In this case, add a reg_note REG_NONNEG, which allows the
8055 m68k DBRA instruction to be used. */
8063 {
8064 /* Initial value must be greater than 0,
8065 init_val % -dec_value == 0 to ensure that it equals zero on
8066 the last iteration */
8072 {
8073 /* register always nonnegative, add REG_NOTE to branch */
8081 }
8083 /* If the decrement is 1 and the value was tested as >= 0 before
8084 the loop, then we can safely optimize. */
8086 {
8099 {
8107 }
8108 }
8109 }
8112 {
8113 /* Try to change inc to dec, so can apply above optimization. */
8114 /* Can do this if:
8115 all registers modified are induction variables or invariant,
8116 all memory references have non-overlapping addresses
8117 (obviously true if only one write)
8118 allow 2 insns for the compare/jump at the end of the loop. */
8119 /* Also, we must avoid any instructions which use both the reversed
8120 biv and another biv. Such instructions will fail if the loop is
8121 reversed. We meet this condition by requiring that either
8122 no_use_except_counting is true, or else that there is only
8123 one biv. */
8125 /* 1 if the iteration var is used only to count iterations. */
8127 /* 1 if the loop has no memory store, or it has a single memory store
8128 which is reversible. */
8134 {
8138 /* If there are no givs for this biv, and the only exit is the
8139 fall through at the end of the loop, then
8140 see if perhaps there are no uses except to count. */
8144 {
8149 /* An insn that sets the biv is okay. */
8150 ;
8154 {
8155 /* If either of these insns uses the biv and sets a pseudo
8156 that has more than one usage, then the biv has uses
8157 other than counting since it's used to derive a value
8158 that is used more than one time. */
8160 regs);
8162 {
8165 }
8166 }
8168 {
8171 }
8172 }
8174 /* A biv has uses besides counting if it is used to set
8175 another biv. */
8179 {
8182 }
8183 }
8186 /* No need to worry about MEMs. */
8187 ;
8189 {
8194 /* If the loop has a single store, and the destination address is
8195 invariant, then we can't reverse the loop, because this address
8196 might then have the wrong value at loop exit.
8197 This would work if the source was invariant also, however, in that
8198 case, the insn should have been moved out of the loop. */
8201 {
8204 /* If we could prove that each of the memory locations
8205 written to was different, then we could reverse the
8206 store -- but we don't presently have any way of
8207 knowing that. */
8210 /* If the store depends on a register that is set after the
8211 store, it depends on the initial value, and is thus not
8212 reversible. */
8214 {
8221 }
8222 }
8223 }
8224 else
8227 /* This code only acts for innermost loops. Also it simplifies
8228 the memory address check by only reversing loops with
8229 zero or one memory access.
8230 Two memory accesses could involve parts of the same array,
8231 and that can't be reversed.
8232 If the biv is used only for counting, than we don't need to worry
8233 about all these things. */
8239 && reversible_mem_store
8244 {
8245 rtx tem;
8247 /* Loop can be reversed. */
8251 /* Now check other conditions:
8253 The increment must be a constant, as must the initial value,
8254 and the comparison code must be LT.
8256 This test can probably be improved since +/- 1 in the constant
8257 can be obtained by changing LT to LE and vice versa; this is
8258 confusing. */
8261 /* for constants, LE gets turned into LT */
8265 {
8276 comparison_const_width
8278 else
8279 comparison_const_width
8283 comparison_sign_mask
8286 /* If the comparison value is not a loop invariant, then we
8287 can not reverse this loop.
8289 ??? If the insns which initialize the comparison value as
8290 a whole compute an invariant result, then we could move
8291 them out of the loop and proceed with loop reversal. */
8299 /* Normalize the initial value if it is an integer and
8300 has no other use except as a counter. This will allow
8301 a few more loops to be reversed. */
8305 {
8307 /* The code below requires comparison_val to be a multiple
8308 of add_val in order to do the loop reversal, so
8309 round up comparison_val to a multiple of add_val.
8310 Since comparison_value is constant, we know that the
8311 current comparison code is LT. */
8313 comparison_val
8315 /* We postpone overflow checks for COMPARISON_VAL here;
8316 even if there is an overflow, we might still be able to
8317 reverse the loop, if converting the loop exit test to
8318 NE is possible. */
8320 }
8322 /* First check if we can do a vanilla loop reversal. */
8324 /* If we have a decrement_and_branch_on_count,
8325 prefer the NE test, since this will allow that
8326 instruction to be generated. Note that we must
8327 use a vanilla loop reversal if the biv is used to
8328 calculate a giv or has a non-counting use. */
8329 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8330 && defined (HAVE_decrement_and_branch_on_count)
8334 #endif
8336 /* Now do postponed overflow checks on COMPARISON_VAL. */
8339 {
8340 /* Register will always be nonnegative, with value
8341 0 on last iteration */
8345 }
8349 {
8352 }
8353 else
8359 /* If the initial value is not zero, or if the comparison
8360 value is not an exact multiple of the increment, then we
8361 can not reverse this loop. */
8364 {
8367 }
8368 else
8369 {
8372 }
8376 /* Reset these in case we normalized the initial value
8377 and comparison value above. */
8380 {
8382 final_value
8384 }
8387 /* Save some info needed to produce the new insns. */
8392 /* Set start_value; if this is not a CONST_INT, we need
8393 to generate a SUB.
8394 Initialize biv to start_value before loop start.
8395 The old initializing insn will be deleted as a
8396 dead store by flow.c. */
8399 {
8402 }
8404 {
8412 start_value
8418 }
8420 {
8423 initial_value);
8427 start_value
8430 }
8431 else
8432 /* We could handle the other cases too, but it'll be
8433 better to have a testcase first. */
8436 /* We may not have a single insn which can increment a reg, so
8437 create a sequence to hold all the insns from expand_inc. */
8446 /* Update biv info to reflect its new status. */
8451 /* Update loop info. */
8460 /* Inc LABEL_NUSES so that delete_insn will
8461 not delete the label. */
8464 /* Emit an insn after the end of the loop to set the biv's
8465 proper exit value if it is used anywhere outside the loop. */
8471 /* Delete compare/branch at end of loop. */
8476 /* Add new compare/branch insn at end of loop. */
8488 ;
8494 {
8496 {
8497 /* Increment of LABEL_NUSES done above. */
8498 /* Register is now always nonnegative,
8499 so add REG_NONNEG note to the branch. */
8502 }
8504 }
8506 /* No insn may reference both the reversed and another biv or it
8507 will fail (see comment near the top of the loop reversal
8508 code).
8509 Earlier on, we have verified that the biv has no use except
8510 counting, or it is the only biv in this function.
8511 However, the code that computes no_use_except_counting does
8512 not verify reg notes. It's possible to have an insn that
8513 references another biv, and has a REG_EQUAL note with an
8514 expression based on the reversed biv. To avoid this case,
8515 remove all REG_EQUAL notes based on the reversed biv
8516 here. */
8519 {
8522 /* If this is a set of a GIV based on the reversed biv, any
8523 REG_EQUAL notes should still be correct. */
8530 {
8535 else
8537 }
8538 }
8540 /* Mark that this biv has been reversed. Each giv which depends
8541 on this biv, and which is also live past the end of the loop
8542 will have to be fixed up. */
8547 {
8551 else
8553 }
8556 }
8557 }
8558 }
8561 }
8562 \f
8563 /* Verify whether the biv BL appears to be eliminable,
8564 based on the insns in the loop that refer to it.
8566 If ELIMINATE_P is non-zero, actually do the elimination.
8568 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8569 determine whether invariant insns should be placed inside or at the
8570 start of the loop. */
8572 static int
8578 {
8581 rtx p;
8583 /* Scan all insns in the loop, stopping if we find one that uses the
8584 biv in a way that we cannot eliminate. */
8587 {
8592 /* If this is a libcall that sets a giv, skip ahead to its end. */
8594 {
8598 {
8603 {
8610 }
8611 }
8612 }
8617 {
8623 }
8624 }
8627 {
8632 }
8635 }
8636 \f
8637 /* INSN and REFERENCE are instructions in the same insn chain.
8638 Return non-zero if INSN is first. */
8640 int
8643 {
8647 {
8648 /* Start with test for not first so that INSN == REFERENCE yields not
8649 first. */
8655 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8656 previous insn, hence the <= comparison below does not work if
8657 P is a note. */
8668 }
8669 }
8671 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8672 the offset that we have to take into account due to auto-increment /
8673 div derivation is zero. */
8674 static int
8677 rtx insn;
8678 {
8679 /* If the giv V had the auto-inc address optimization applied
8680 to it, and INSN occurs between the giv insn and the biv
8681 insn, then we'd have to adjust the value used here.
8682 This is rare, so we don't bother to make this possible. */
8691 }
8693 /* If BL appears in X (part of the pattern of INSN), see if we can
8694 eliminate its use. If so, return 1. If not, return 0.
8696 If BIV does not appear in X, return 1.
8698 If ELIMINATE_P is non-zero, actually do the elimination.
8699 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8700 Depending on how many items have been moved out of the loop, it
8701 will either be before INSN (when WHERE_INSN is non-zero) or at the
8702 start of the loop (when WHERE_INSN is zero). */
8704 static int
8710 basic_block where_bb;
8711 rtx where_insn;
8712 {
8718 #ifdef HAVE_cc0
8720 #endif
8726 {
8728 /* If we haven't already been able to do something with this BIV,
8729 we can't eliminate it. */
8735 /* If this sets the BIV, it is not a problem. */
8739 /* If this is an insn that defines a giv, it is also ok because
8740 it will go away when the giv is reduced. */
8745 #ifdef HAVE_cc0
8747 {
8748 /* Can replace with any giv that was reduced and
8749 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8750 Require a constant for MULT_VAL, so we know it's nonzero.
8751 ??? We disable this optimization to avoid potential
8752 overflows. */
8760 {
8767 /* If the giv has the opposite direction of change,
8768 then reverse the comparison. */
8772 else
8775 /* We can probably test that giv's reduced reg. */
8778 }
8780 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8781 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8782 Require a constant for MULT_VAL, so we know it's nonzero.
8783 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8784 overflow problem. */
8796 {
8803 /* If the giv has the opposite direction of change,
8804 then reverse the comparison. */
8808 else
8812 /* Replace biv with the giv's reduced register. */
8817 /* Insn doesn't support that constant or invariant. Copy it
8818 into a register (it will be a loop invariant.) */
8825 /* Substitute the new register for its invariant value in
8826 the compare expression. */
8830 }
8831 }
8832 #endif
8839 /* See if either argument is the biv. */
8844 else
8848 {
8849 /* First try to replace with any giv that has constant positive
8850 mult_val and constant add_val. We might be able to support
8851 negative mult_val, but it seems complex to do it in general. */
8863 {
8867 /* Don't eliminate if the linear combination that makes up
8868 the giv overflows when it is applied to ARG. */
8870 {
8871 rtx add_val;
8875 else
8881 }
8886 /* Replace biv with the giv's reduced reg. */
8889 /* If all constants are actually constant integers and
8890 the derived constant can be directly placed in the COMPARE,
8891 do so. */
8894 {
8897 }
8898 else
8899 {
8900 /* Otherwise, load it into a register. */
8905 }
8911 }
8913 /* Look for giv with positive constant mult_val and nonconst add_val.
8914 Insert insns to calculate new compare value.
8915 ??? Turn this off due to possible overflow. */
8923 {
8924 rtx tem;
8934 /* Replace biv with giv's reduced register. */
8938 /* Compute value to compare against. */
8942 /* Use it in this insn. */
8946 }
8947 }
8949 {
8951 {
8952 /* Look for giv with constant positive mult_val and nonconst
8953 add_val. Insert insns to compute new compare value.
8954 ??? Turn this off due to possible overflow. */
8961 {
8962 rtx tem;
8972 /* Replace biv with giv's reduced register. */
8976 /* Compute value to compare against. */
8983 }
8984 }
8986 /* This code has problems. Basically, you can't know when
8987 seeing if we will eliminate BL, whether a particular giv
8988 of ARG will be reduced. If it isn't going to be reduced,
8989 we can't eliminate BL. We can try forcing it to be reduced,
8990 but that can generate poor code.
8992 The problem is that the benefit of reducing TV, below should
8993 be increased if BL can actually be eliminated, but this means
8994 we might have to do a topological sort of the order in which
8995 we try to process biv. It doesn't seem worthwhile to do
8996 this sort of thing now. */
8998 #if 0
8999 /* Otherwise the reg compared with had better be a biv. */
9004 /* Look for a pair of givs, one for each biv,
9005 with identical coefficients. */
9007 {
9019 {
9026 /* Replace biv with its giv's reduced reg. */
9028 /* Replace other operand with the other giv's
9029 reduced reg. */
9032 }
9033 }
9034 #endif
9035 }
9037 /* If we get here, the biv can't be eliminated. */
9041 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9042 biv is used in it, since it will be replaced. */
9050 }
9052 /* See if any subexpression fails elimination. */
9055 {
9057 {
9070 }
9071 }
9074 }
9075 \f
9076 /* Return nonzero if the last use of REG
9077 is in an insn following INSN in the same basic block. */
9079 static int
9081 rtx reg;
9082 rtx insn;
9083 {
9084 rtx n;
9088 {
9091 }
9093 }
9094 \f
9095 /* Called via `note_stores' to record the initial value of a biv. Here we
9096 just record the location of the set and process it later. */
9098 static void
9100 rtx dest;
9101 rtx set;
9103 {
9114 /* If this is the first set found, record it. */
9116 {
9119 }
9120 }
9121 \f
9122 /* If any of the registers in X are "old" and currently have a last use earlier
9123 than INSN, update them to have a last use of INSN. Their actual last use
9124 will be the previous insn but it will not have a valid uid_luid so we can't
9125 use it. X must be a source expression only. */
9127 static void
9129 rtx x;
9130 rtx insn;
9131 {
9132 /* Check for the case where INSN does not have a valid luid. In this case,
9133 there is no need to modify the regno_last_uid, as this can only happen
9134 when code is inserted after the loop_end to set a pseudo's final value,
9135 and hence this insn will never be the last use of x.
9136 ???? This comment is not correct. See for example loop_givs_reduce.
9137 This may insert an insn before another new insn. */
9141 {
9143 }
9144 else
9145 {
9149 {
9155 }
9156 }
9157 }
9158 \f
9159 /* Given an insn INSN and condition COND, return the condition in a
9160 canonical form to simplify testing by callers. Specifically:
9162 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9163 (2) Both operands will be machine operands; (cc0) will have been replaced.
9164 (3) If an operand is a constant, it will be the second operand.
9165 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9166 for GE, GEU, and LEU.
9168 If the condition cannot be understood, or is an inequality floating-point
9169 comparison which needs to be reversed, 0 will be returned.
9171 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9173 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9174 insn used in locating the condition was found. If a replacement test
9175 of the condition is desired, it should be placed in front of that
9176 insn and we will be sure that the inputs are still valid.
9178 If WANT_REG is non-zero, we wish the condition to be relative to that
9179 register, if possible. Therefore, do not canonicalize the condition
9180 further. */
9182 rtx
9184 rtx insn;
9185 rtx cond;
9188 rtx want_reg;
9189 {
9192 rtx set;
9193 rtx tem;
9211 /* If we are comparing a register with zero, see if the register is set
9212 in the previous insn to a COMPARE or a comparison operation. Perform
9213 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9214 in cse.c */
9219 {
9220 /* Set non-zero when we find something of interest. */
9223 #ifdef HAVE_cc0
9224 /* If comparison with cc0, import actual comparison from compare
9225 insn. */
9227 {
9238 }
9239 #endif
9241 /* If this is a COMPARE, pick up the two things being compared. */
9243 {
9247 }
9251 /* Go back to the previous insn. Stop if it is not an INSN. We also
9252 stop if it isn't a single set or if it has a REG_INC note because
9253 we don't want to bother dealing with it. */
9267 /* If this is setting OP0, get what it sets it to if it looks
9268 relevant. */
9270 {
9273 /* ??? We may not combine comparisons done in a CCmode with
9274 comparisons not done in a CCmode. This is to aid targets
9275 like Alpha that have an IEEE compliant EQ instruction, and
9276 a non-IEEE compliant BEQ instruction. The use of CCmode is
9277 actually artificial, simply to prevent the combination, but
9278 should not affect other platforms.
9280 However, we must allow VOIDmode comparisons to match either
9281 CCmode or non-CCmode comparison, because some ports have
9282 modeless comparisons inside branch patterns.
9284 ??? This mode check should perhaps look more like the mode check
9285 in simplify_comparison in combine. */
9293 && (STORE_FLAG_VALUE
9296 #ifdef FLOAT_STORE_FLAG_VALUE
9299 && (REAL_VALUE_NEGATIVE
9301 #endif
9302 ))
9313 && (STORE_FLAG_VALUE
9316 #ifdef FLOAT_STORE_FLAG_VALUE
9319 && (REAL_VALUE_NEGATIVE
9321 #endif
9322 ))
9328 {
9331 }
9332 else
9334 }
9337 /* If this sets OP0, but not directly, we have to give up. */
9341 {
9345 {
9350 }
9355 }
9356 }
9358 /* If constant is first, put it last. */
9362 /* If OP0 is the result of a comparison, we weren't able to find what
9363 was really being compared, so fail. */
9367 /* Canonicalize any ordered comparison with integers involving equality
9368 if we can do computations in the relevant mode and we do not
9369 overflow. */
9374 {
9377 unsigned HOST_WIDE_INT max_val
9381 {
9387 /* When cross-compiling, const_val might be sign-extended from
9388 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9408 }
9409 }
9411 #ifdef HAVE_cc0
9412 /* Never return CC0; return zero instead. */
9415 #endif
9418 }
9420 /* Given a jump insn JUMP, return the condition that will cause it to branch
9421 to its JUMP_LABEL. If the condition cannot be understood, or is an
9422 inequality floating-point comparison which needs to be reversed, 0 will
9423 be returned.
9425 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9426 insn used in locating the condition was found. If a replacement test
9427 of the condition is desired, it should be placed in front of that
9428 insn and we will be sure that the inputs are still valid. */
9430 rtx
9432 rtx jump;
9434 {
9435 rtx cond;
9437 rtx set;
9439 /* If this is not a standard conditional jump, we can't parse it. */
9447 /* If this branches to JUMP_LABEL when the condition is false, reverse
9448 the condition. */
9449 reverse
9454 }
9456 /* Similar to above routine, except that we also put an invariant last
9457 unless both operands are invariants. */
9459 rtx
9462 rtx x;
9463 {
9473 }
9475 /* Scan the function and determine whether it has indirect (computed) jumps.
9477 This is taken mostly from flow.c; similar code exists elsewhere
9478 in the compiler. It may be useful to put this into rtlanal.c. */
9479 static int
9481 rtx start;
9482 {
9483 rtx insn;
9490 }
9492 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9493 documentation for LOOP_MEMS for the definition of `appropriate'.
9494 This function is called from prescan_loop via for_each_rtx. */
9496 static int
9500 {
9509 {
9514 /* We're not interested in MEMs that are only clobbered. */
9518 /* We're not interested in the MEM associated with a
9519 CONST_DOUBLE, so there's no need to traverse into this. */
9523 /* We're not interested in any MEMs that only appear in notes. */
9527 /* This is not a MEM. */
9529 }
9531 /* See if we've already seen this MEM. */
9534 {
9536 /* The modes of the two memory accesses are different. If
9537 this happens, something tricky is going on, and we just
9538 don't optimize accesses to this MEM. */
9542 }
9544 /* Resize the array, if necessary. */
9546 {
9549 else
9555 }
9557 /* Actually insert the MEM. */
9559 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9560 because we can't put it in a register. We still store it in the
9561 table, though, so that if we see the same address later, but in a
9562 non-BLK mode, we'll not think we can optimize it at that point. */
9568 }
9571 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9573 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9574 register that is modified by an insn between FROM and TO. If the
9575 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9576 more, stop incrementing it, to avoid overflow.
9578 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9579 register I is used, if it is only used once. Otherwise, it is set
9580 to 0 (for no uses) or const0_rtx for more than one use. This
9581 parameter may be zero, in which case this processing is not done.
9583 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9584 optimize register I. */
9586 static void
9590 {
9593 /* last_set[n] is nonzero iff reg n has been set in the current
9594 basic block. In that case, it is the insn that last set reg n. */
9596 rtx insn;
9602 /* Grow the regs array if not allocated or too small. */
9604 {
9610 /* Zero the new elements. */
9613 }
9615 /* Clear previously scanned fields but do not clear n_times_set. */
9617 {
9621 }
9625 /* Scan the loop, recording register usage. */
9628 {
9630 {
9631 /* Record registers that have exactly one use. */
9634 /* Include uses in REG_EQUAL notes. */
9642 {
9646 last_set);
9647 }
9648 }
9652 }
9654 /* Invalidate all hard registers clobbered by calls. With one exception:
9655 a call-clobbered PIC register is still function-invariant for our
9656 purposes, since we can hoist any PIC calculations out of the loop.
9657 Thus the call to rtx_varies_p. */
9662 {
9665 }
9667 #ifdef AVOID_CCMODE_COPIES
9668 /* Don't try to move insns which set CC registers if we should not
9669 create CCmode register copies. */
9673 #endif
9675 /* Set regs->array[I].n_times_set for the new registers. */
9680 }
9682 /* Returns the number of real INSNs in the LOOP. */
9684 static int
9687 {
9689 rtx insn;
9697 }
9699 /* Move MEMs into registers for the duration of the loop. */
9701 static void
9704 {
9711 rtx end_label;
9712 /* Nonzero if the next instruction may never be executed. */
9719 /* We cannot use next_label here because it skips over normal insns. */
9724 /* Check to see if it's possible that some instructions in the loop are
9725 never executed. Also check if there is a goto out of the loop other
9726 than right after the end of the loop. */
9730 {
9734 /* If we enter the loop in the middle, and scan
9735 around to the beginning, don't set maybe_never
9736 for that. This must be an unconditional jump,
9737 otherwise the code at the top of the loop might
9738 never be executed. Unconditional jumps are
9739 followed a by barrier then loop end. */
9744 {
9745 /* If this is a jump outside of the loop but not right
9746 after the end of the loop, we would have to emit new fixup
9747 sequences for each such label. */
9749 JUMP_INSN is executed, we must be conservative. */
9758 /* Something complicated. */
9760 else
9761 /* If there are any more instructions in the loop, they
9762 might not be reached. */
9764 }
9767 }
9769 /* Find start of the extended basic block that enters the loop. */
9773 ;
9778 /* Build table of mems that get set to constant values before the
9779 loop. */
9783 /* Actually move the MEMs. */
9785 {
9786 regset_head load_copies;
9787 regset_head store_copies;
9789 rtx reg;
9791 rtx mem_list_entry;
9795 /* There's no telling whether or not MEM is modified. */
9798 /* Go through the MEMs written to in the loop to see if this
9799 one is aliased by one of them. */
9802 {
9807 {
9808 /* MEM is indeed aliased by this store. */
9811 }
9813 }
9819 /* If this MEM is written to, we must be sure that there
9820 are no reads from another MEM that aliases this one. */
9822 {
9826 {
9830 VOIDmode,
9832 rtx_varies_p))
9833 {
9834 /* It's not safe to hoist loop_info->mems[i] out of
9835 the loop because writes to it might not be
9836 seen by reads from loop_info->mems[j]. */
9839 }
9840 }
9841 }
9844 /* We can't access the MEM outside the loop; it might
9845 cause a trap that wouldn't have happened otherwise. */
9849 /* We thought we were going to lift this MEM out of the
9850 loop, but later discovered that we could not. */
9856 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9857 order to keep scan_loop from moving stores to this MEM
9858 out of the loop just because this REG is neither a
9859 user-variable nor used in the loop test. */
9864 /* Now, replace all references to the MEM with the
9865 corresponding pseudos. */
9870 {
9872 {
9873 rtx set;
9877 /* See if this copies the mem into a register that isn't
9878 modified afterwards. We'll try to do copy propagation
9879 a little further on. */
9881 /* @@@ This test is _way_ too conservative. */
9882 && ! maybe_never
9890 /* See if this copies the mem from a register that isn't
9891 modified afterwards. We'll try to remove the
9892 redundant copy later on by doing a little register
9893 renaming and copy propagation. This will help
9894 to untangle things for the BIV detection code. */
9896 && ! maybe_never
9904 /* If this is a call which uses / clobbers this memory
9905 location, we must not change the interface here. */
9909 {
9913 }
9914 else
9915 /* Replace the memory reference with the shadow register. */
9918 }
9923 }
9928 /* We couldn't replace all occurrences of the MEM. */
9930 else
9931 {
9932 /* Load the memory immediately before LOOP->START, which is
9933 the NOTE_LOOP_BEG. */
9935 rtx set;
9941 {
9945 {
9949 /* Extending hard register lifetimes causes crash
9950 on SRC targets. Doing so on non-SRC is
9951 probably also not good idea, since we most
9952 probably have pseudoregister equivalence as
9953 well. */
9956 }
9957 /* Use the constant equivalence if that is cheap enough. */
9963 {
9966 }
9968 /* If best_equiv is nonzero, we know that MEM is set to a
9969 constant or register before the loop. We will use this
9970 knowledge to initialize the shadow register with that
9971 constant or reg rather than by loading from MEM. */
9974 }
9979 {
9982 {
9985 }
9986 }
9992 {
9994 {
9997 }
9999 /* Store the memory immediately after END, which is
10000 the NOTE_LOOP_END. */
10003 }
10006 {
10011 }
10013 /* Attempt a bit of copy propagation. This helps untangle the
10014 data flow, and enables {basic,general}_induction_var to find
10015 more bivs/givs. */
10016 EXECUTE_IF_SET_IN_REG_SET
10018 {
10020 });
10023 EXECUTE_IF_SET_IN_REG_SET
10025 {
10027 });
10029 }
10030 }
10033 {
10034 /* Now, we need to replace all references to the previous exit
10035 label with the new one. */
10036 rtx_pair rr;
10041 {
10044 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10045 field. This is not handled by for_each_rtx because it doesn't
10046 handle unprinted ('0') fields. We need to update JUMP_LABEL
10047 because the immediately following unroll pass will use it.
10048 replace_label would not work anyways, because that only handles
10049 LABEL_REFs. */
10052 }
10053 }
10056 }
10058 /* For communication between note_reg_stored and its caller. */
10059 struct note_reg_stored_arg
10060 {
10062 rtx reg;
10063 };
10065 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10066 is equal to ARG. */
10067 static void
10071 {
10075 }
10077 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10078 There must be exactly one insn that sets this pseudo; it will be
10079 deleted if all replacements succeed and we can prove that the register
10080 is not used after the loop. */
10082 static void
10085 rtx replacement;
10087 {
10088 /* This is the reg that we are copying from. */
10091 rtx insn;
10092 /* These help keep track of whether we replaced all uses of the reg. */
10099 {
10100 rtx set;
10102 /* Only substitute within one extended basic block from the initializing
10103 insn. */
10110 /* Is this the initializing insn? */
10115 {
10122 }
10124 /* Only substitute after seeing the initializing insn. */
10126 {
10133 /* Stop replacing when REPLACEMENT is modified. */
10138 {
10141 /* It is possible that we've turned previously valid REG_EQUAL to
10142 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10143 REPLACEMENT is modified, we get different meaning. */
10147 }
10148 }
10149 }
10153 {
10157 {
10158 rtx first;
10159 rtx retval_note;
10161 /* Assume we're just deleting INIT_INSN. */
10163 /* Look for REG_RETVAL note. If we're deleting the end of
10164 the libcall sequence, the whole sequence can go. */
10166 /* If we found a REG_RETVAL note, find the first instruction
10167 in the sequence. */
10171 /* Delete the instructions. */
10173 }
10176 }
10177 }
10179 /* Replace all the instructions from FIRST up to and including LAST
10180 with NOTE_INSN_DELETED notes. */
10182 static void
10184 rtx first;
10185 rtx last;
10186 {
10188 {
10194 /* If this was the LAST instructions we're supposed to delete,
10195 we're done. */
10200 }
10201 }
10203 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10204 loop LOOP if the order of the sets of these registers can be
10205 swapped. There must be exactly one insn within the loop that sets
10206 this pseudo followed immediately by a move insn that sets
10207 REPLACEMENT with REGNO. */
10208 static void
10211 rtx replacement;
10213 {
10214 rtx insn;
10223 {
10224 /* Search for the insn that copies REGNO to NEW_REGNO? */
10232 }
10235 {
10236 rtx prev_insn;
10237 rtx prev_set;
10239 /* Some DEF-USE info would come in handy here to make this
10240 function more general. For now, just check the previous insn
10241 which is the most likely candidate for setting REGNO. */
10249 {
10250 /* We have:
10251 (set (reg regno) (expr))
10252 (set (reg new_regno) (reg regno))
10254 so try converting this to:
10255 (set (reg new_regno) (expr))
10256 (set (reg regno) (reg new_regno))
10258 The former construct is often generated when a global
10259 variable used for an induction variable is shadowed by a
10260 register (NEW_REGNO). The latter construct improves the
10261 chances of GIV replacement and BIV elimination. */
10271 {
10278 /* Update first use of REGNO. */
10282 /* Now perform copy propagation to hopefully
10283 remove all uses of REGNO within the loop. */
10285 }
10286 }
10287 }
10288 }
10290 /* Replace MEM with its associated pseudo register. This function is
10291 called from load_mems via for_each_rtx. DATA is actually a pointer
10292 to a structure describing the instruction currently being scanned
10293 and the MEM we are currently replacing. */
10295 static int
10299 {
10307 {
10312 /* We're not interested in the MEM associated with a
10313 CONST_DOUBLE, so there's no need to traverse into one. */
10317 /* This is not a MEM. */
10319 }
10322 /* This is not the MEM we are currently replacing. */
10325 /* Actually replace the MEM. */
10329 }
10331 static void
10333 rtx insn;
10334 rtx mem;
10335 rtx reg;
10336 {
10337 loop_replace_args args;
10344 }
10346 /* Replace one register with another. Called through for_each_rtx; PX points
10347 to the rtx being scanned. DATA is actually a pointer to
10348 a structure of arguments. */
10350 static int
10354 {
10365 }
10367 static void
10369 rtx insn;
10370 rtx reg;
10371 rtx replacement;
10372 {
10373 loop_replace_args args;
10380 }
10382 /* Replace occurrences of the old exit label for the loop with the new
10383 one. DATA is an rtx_pair containing the old and new labels,
10384 respectively. */
10386 static int
10390 {
10409 }
10410 \f
10411 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10412 (ignored in the interim). */
10414 static rtx
10417 basic_block where_bb ATTRIBUTE_UNUSED;
10418 rtx where_insn;
10419 rtx pattern;
10420 {
10422 }
10425 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10426 in basic block WHERE_BB (ignored in the interim) within the loop
10427 otherwise hoist PATTERN into the loop pre-header. */
10429 rtx
10432 basic_block where_bb ATTRIBUTE_UNUSED;
10433 rtx where_insn;
10434 rtx pattern;
10435 {
10439 }
10442 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10443 WHERE_BB (ignored in the interim) within the loop. */
10445 static rtx
10448 basic_block where_bb ATTRIBUTE_UNUSED;
10449 rtx where_insn;
10450 rtx pattern;
10451 {
10453 }
10456 /* Hoist insn for PATTERN into the loop pre-header. */
10458 rtx
10461 rtx pattern;
10462 {
10464 }
10467 /* Hoist call insn for PATTERN into the loop pre-header. */
10469 static rtx
10472 rtx pattern;
10473 {
10475 }
10478 /* Sink insn for PATTERN after the loop end. */
10480 rtx
10483 rtx pattern;
10484 {
10486 }
10488 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10489 and constant. Emit sequence of intructions to load it into REG */
10490 static rtx
10493 {
10494 rtx seq;
10502 }
10504 /* If the loop has multiple exits, emit insn for PATTERN before the
10505 loop to ensure that it will always be executed no matter how the
10506 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10507 since this is slightly more efficient. */
10509 static rtx
10512 rtx pattern;
10513 {
10516 else
10518 }
10519 \f
10520 static void
10525 {
10533 iv_num++;
10538 {
10541 }
10542 }
10545 static void
10550 {
10552 rtx incr;
10563 {
10566 }
10568 {
10571 }
10575 {
10579 }
10582 {
10586 }
10588 /* List the increments. */
10590 {
10594 }
10596 /* List the givs. */
10598 {
10603 else
10606 }
10607 }
10610 static void
10615 {
10626 {
10630 }
10633 }
10636 static void
10641 {
10648 else
10664 {
10666 {
10678 }
10679 }
10690 {
10694 }
10697 }
10700 void
10703 {
10705 }
10708 void
10711 {
10713 }
10716 void
10719 {
10721 }
10724 void
10727 {
10729 }
10732 #define LOOP_BLOCK_NUM_1(INSN) \
10733 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10735 /* The notes do not have an assigned block, so look at the next insn. */
10736 #define LOOP_BLOCK_NUM(INSN) \
10737 ((INSN) ? (GET_CODE (INSN) == NOTE \
10738 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10739 : LOOP_BLOCK_NUM_1 (INSN)) \
10740 : -1)
10742 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10744 static void
10749 {
10750 rtx label;
10755 /* Print diagnostics to compare our concept of a loop with
10756 what the loop notes say. */
10771 {
10791 {
10794 {
10797 }
10798 }
10801 /* This can happen when a marked loop appears as two nested loops,
10802 say from while (a || b) {}. The inner loop won't match
10803 the loop markers but the outer one will. */
10806 }
10807 }
10809 /* Call this function from the debugger to dump LOOP. */
10811 void
10814 {
10816 }
10818 /* Call this function from the debugger to dump LOOPS. */
10820 void
10823 {
10825 }