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2002-08-22 Paolo Carlini <pcarlini@unitus.it>
[official-gcc.git] / gcc / longlong.h
blob40f03fe2a0e29a583c264691983a0ece7ee11350
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 2, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
19
20 /* You have to define the following before including this file:
21
22 UWtype -- An unsigned type, default type for operations (typically a "word")
23 UHWtype -- An unsigned type, at least half the size of UWtype.
24 UDWtype -- An unsigned type, at least twice as large a UWtype
25 W_TYPE_SIZE -- size in bits of UWtype
26
27 UQItype -- Unsigned 8 bit type.
28 SItype, USItype -- Signed and unsigned 32 bit types.
29 DItype, UDItype -- Signed and unsigned 64 bit types.
30
31 On a 32 bit machine UWtype should typically be USItype;
32 on a 64 bit machine, UWtype should typically be UDItype.
33 */
34
35 #define __BITS4 (W_TYPE_SIZE / 4)
36 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
37 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
38 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
39
40 #ifndef W_TYPE_SIZE
41 #define W_TYPE_SIZE 32
42 #define UWtype USItype
43 #define UHWtype USItype
44 #define UDWtype UDItype
45 #endif
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
50 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first non-zero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 __asm__ ("umulh %r1,%2,%0" \
115 : "=r" ((UDItype) ph) \
116 : "%rJ" (__m0), \
117 "rI" (__m1)); \
118 (pl) = __m0 * __m1; \
119 } while (0)
120 #define UMUL_TIME 46
121 #ifndef LONGLONG_STANDALONE
122 #define udiv_qrnnd(q, r, n1, n0, d) \
123 do { UDItype __r; \
124 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
125 (r) = __r; \
126 } while (0)
127 extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype));
128 #define UDIV_TIME 220
129 #endif /* LONGLONG_STANDALONE */
130 #ifdef __alpha_cix__
131 #define count_leading_zeros(COUNT,X) \
132 __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
133 #define count_trailing_zeros(COUNT,X) \
134 __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
135 #define COUNT_LEADING_ZEROS_0 64
136 #else
137 extern const UQItype __clz_tab[];
138 #define count_leading_zeros(COUNT,X) \
139 do { \
140 UDItype __xr = (X), __t, __a; \
141 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \
142 __a = __clz_tab[__t ^ 0xff] - 1; \
143 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \
144 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
145 } while (0)
146 #define count_trailing_zeros(COUNT,X) \
147 do { \
148 UDItype __xr = (X), __t, __a; \
149 __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr)); \
150 __t = ~__t & -~__t; \
151 __a = ((__t & 0xCC) != 0) * 2; \
152 __a += ((__t & 0xF0) != 0) * 4; \
153 __a += ((__t & 0xAA) != 0); \
154 __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a)); \
155 __a <<= 3; \
156 __t &= -__t; \
157 __a += ((__t & 0xCC) != 0) * 2; \
158 __a += ((__t & 0xF0) != 0) * 4; \
159 __a += ((__t & 0xAA) != 0); \
160 (COUNT) = __a; \
161 } while (0)
162 #endif /* __alpha_cix__ */
163 #endif /* __alpha */
164
165 #if defined (__arc__) && W_TYPE_SIZE == 32
166 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
167 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
168 : "=r" ((USItype) (sh)), \
169 "=&r" ((USItype) (sl)) \
170 : "%r" ((USItype) (ah)), \
171 "rIJ" ((USItype) (bh)), \
172 "%r" ((USItype) (al)), \
173 "rIJ" ((USItype) (bl)))
174 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
175 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
176 : "=r" ((USItype) (sh)), \
177 "=&r" ((USItype) (sl)) \
178 : "r" ((USItype) (ah)), \
179 "rIJ" ((USItype) (bh)), \
180 "r" ((USItype) (al)), \
181 "rIJ" ((USItype) (bl)))
182 /* Call libgcc routine. */
183 #define umul_ppmm(w1, w0, u, v) \
184 do { \
185 DWunion __w; \
186 __w.ll = __umulsidi3 (u, v); \
187 w1 = __w.s.high; \
188 w0 = __w.s.low; \
189 } while (0)
190 #define __umulsidi3 __umulsidi3
191 UDItype __umulsidi3 (USItype, USItype);
192 #endif
193
194 #if defined (__arm__) && W_TYPE_SIZE == 32
195 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
196 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
197 : "=r" ((USItype) (sh)), \
198 "=&r" ((USItype) (sl)) \
199 : "%r" ((USItype) (ah)), \
200 "rI" ((USItype) (bh)), \
201 "%r" ((USItype) (al)), \
202 "rI" ((USItype) (bl)))
203 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
204 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
205 : "=r" ((USItype) (sh)), \
206 "=&r" ((USItype) (sl)) \
207 : "r" ((USItype) (ah)), \
208 "rI" ((USItype) (bh)), \
209 "r" ((USItype) (al)), \
210 "rI" ((USItype) (bl)))
211 #define umul_ppmm(xh, xl, a, b) \
212 {register USItype __t0, __t1, __t2; \
213 __asm__ ("%@ Inlined umul_ppmm\n" \
214 " mov %2, %5, lsr #16\n" \
215 " mov %0, %6, lsr #16\n" \
216 " bic %3, %5, %2, lsl #16\n" \
217 " bic %4, %6, %0, lsl #16\n" \
218 " mul %1, %3, %4\n" \
219 " mul %4, %2, %4\n" \
220 " mul %3, %0, %3\n" \
221 " mul %0, %2, %0\n" \
222 " adds %3, %4, %3\n" \
223 " addcs %0, %0, #65536\n" \
224 " adds %1, %1, %3, lsl #16\n" \
225 " adc %0, %0, %3, lsr #16" \
226 : "=&r" ((USItype) (xh)), \
227 "=r" ((USItype) (xl)), \
228 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
229 : "r" ((USItype) (a)), \
230 "r" ((USItype) (b)));}
231 #define UMUL_TIME 20
232 #define UDIV_TIME 100
233 #endif /* __arm__ */
234
235 #if defined (__hppa) && W_TYPE_SIZE == 32
236 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
237 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
238 : "=r" ((USItype) (sh)), \
239 "=&r" ((USItype) (sl)) \
240 : "%rM" ((USItype) (ah)), \
241 "rM" ((USItype) (bh)), \
242 "%rM" ((USItype) (al)), \
243 "rM" ((USItype) (bl)))
244 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
245 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
246 : "=r" ((USItype) (sh)), \
247 "=&r" ((USItype) (sl)) \
248 : "rM" ((USItype) (ah)), \
249 "rM" ((USItype) (bh)), \
250 "rM" ((USItype) (al)), \
251 "rM" ((USItype) (bl)))
252 #if defined (_PA_RISC1_1)
253 #define umul_ppmm(w1, w0, u, v) \
254 do { \
255 union \
256 { \
257 UDItype __f; \
258 struct {USItype __w1, __w0;} __w1w0; \
259 } __t; \
260 __asm__ ("xmpyu %1,%2,%0" \
261 : "=x" (__t.__f) \
262 : "x" ((USItype) (u)), \
263 "x" ((USItype) (v))); \
264 (w1) = __t.__w1w0.__w1; \
265 (w0) = __t.__w1w0.__w0; \
266 } while (0)
267 #define UMUL_TIME 8
268 #else
269 #define UMUL_TIME 30
270 #endif
271 #define UDIV_TIME 40
272 #define count_leading_zeros(count, x) \
273 do { \
274 USItype __tmp; \
275 __asm__ ( \
276 "ldi 1,%0\n" \
277 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
278 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
279 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
280 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
281 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
282 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
283 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
284 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
285 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
286 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
287 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
288 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
289 " extru %1,30,1,%1 ; Extract bit 1.\n" \
290 " sub %0,%1,%0 ; Subtract it.\n" \
291 : "=r" (count), "=r" (__tmp) : "1" (x)); \
292 } while (0)
293 #endif
294
295 #if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32
296 #define umul_ppmm(xh, xl, m0, m1) \
297 do { \
298 union {UDItype __ll; \
299 struct {USItype __h, __l;} __i; \
300 } __xx; \
301 USItype __m0 = (m0), __m1 = (m1); \
302 __asm__ ("mr %0,%3" \
303 : "=r" (__xx.__i.__h), \
304 "=r" (__xx.__i.__l) \
305 : "%1" (__m0), \
306 "r" (__m1)); \
307 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
308 (xh) += ((((SItype) __m0 >> 31) & __m1) \
309 + (((SItype) __m1 >> 31) & __m0)); \
310 } while (0)
311 #define smul_ppmm(xh, xl, m0, m1) \
312 do { \
313 union {DItype __ll; \
314 struct {USItype __h, __l;} __i; \
315 } __xx; \
316 __asm__ ("mr %0,%3" \
317 : "=r" (__xx.__i.__h), \
318 "=r" (__xx.__i.__l) \
319 : "%1" (m0), \
320 "r" (m1)); \
321 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
322 } while (0)
323 #define sdiv_qrnnd(q, r, n1, n0, d) \
324 do { \
325 union {DItype __ll; \
326 struct {USItype __h, __l;} __i; \
327 } __xx; \
328 __xx.__i.__h = n1; __xx.__i.__l = n0; \
329 __asm__ ("dr %0,%2" \
330 : "=r" (__xx.__ll) \
331 : "0" (__xx.__ll), "r" (d)); \
332 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
333 } while (0)
334 #endif
335
336 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
337 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
338 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
339 : "=r" ((USItype) (sh)), \
340 "=&r" ((USItype) (sl)) \
341 : "%0" ((USItype) (ah)), \
342 "g" ((USItype) (bh)), \
343 "%1" ((USItype) (al)), \
344 "g" ((USItype) (bl)))
345 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
346 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
347 : "=r" ((USItype) (sh)), \
348 "=&r" ((USItype) (sl)) \
349 : "0" ((USItype) (ah)), \
350 "g" ((USItype) (bh)), \
351 "1" ((USItype) (al)), \
352 "g" ((USItype) (bl)))
353 #define umul_ppmm(w1, w0, u, v) \
354 __asm__ ("mull %3" \
355 : "=a" ((USItype) (w0)), \
356 "=d" ((USItype) (w1)) \
357 : "%0" ((USItype) (u)), \
358 "rm" ((USItype) (v)))
359 #define udiv_qrnnd(q, r, n1, n0, dv) \
360 __asm__ ("divl %4" \
361 : "=a" ((USItype) (q)), \
362 "=d" ((USItype) (r)) \
363 : "0" ((USItype) (n0)), \
364 "1" ((USItype) (n1)), \
365 "rm" ((USItype) (dv)))
366 #define count_leading_zeros(count, x) \
367 do { \
368 USItype __cbtmp; \
369 __asm__ ("bsrl %1,%0" \
370 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
371 (count) = __cbtmp ^ 31; \
372 } while (0)
373 #define count_trailing_zeros(count, x) \
374 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
375 #define UMUL_TIME 40
376 #define UDIV_TIME 40
377 #endif /* 80x86 */
378
379 #if defined (__i960__) && W_TYPE_SIZE == 32
380 #define umul_ppmm(w1, w0, u, v) \
381 ({union {UDItype __ll; \
382 struct {USItype __l, __h;} __i; \
383 } __xx; \
384 __asm__ ("emul %2,%1,%0" \
385 : "=d" (__xx.__ll) \
386 : "%dI" ((USItype) (u)), \
387 "dI" ((USItype) (v))); \
388 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
389 #define __umulsidi3(u, v) \
390 ({UDItype __w; \
391 __asm__ ("emul %2,%1,%0" \
392 : "=d" (__w) \
393 : "%dI" ((USItype) (u)), \
394 "dI" ((USItype) (v))); \
395 __w; })
396 #endif /* __i960__ */
397
398 #if defined (__M32R__) && W_TYPE_SIZE == 32
399 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
400 /* The cmp clears the condition bit. */ \
401 __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0" \
402 : "=r" ((USItype) (sh)), \
403 "=&r" ((USItype) (sl)) \
404 : "%0" ((USItype) (ah)), \
405 "r" ((USItype) (bh)), \
406 "%1" ((USItype) (al)), \
407 "r" ((USItype) (bl)) \
408 : "cbit")
409 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
410 /* The cmp clears the condition bit. */ \
411 __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0" \
412 : "=r" ((USItype) (sh)), \
413 "=&r" ((USItype) (sl)) \
414 : "0" ((USItype) (ah)), \
415 "r" ((USItype) (bh)), \
416 "1" ((USItype) (al)), \
417 "r" ((USItype) (bl)) \
418 : "cbit")
419 #endif /* __M32R__ */
420
421 #if defined (__mc68000__) && W_TYPE_SIZE == 32
422 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
423 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
424 : "=d" ((USItype) (sh)), \
425 "=&d" ((USItype) (sl)) \
426 : "%0" ((USItype) (ah)), \
427 "d" ((USItype) (bh)), \
428 "%1" ((USItype) (al)), \
429 "g" ((USItype) (bl)))
430 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
431 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
432 : "=d" ((USItype) (sh)), \
433 "=&d" ((USItype) (sl)) \
434 : "0" ((USItype) (ah)), \
435 "d" ((USItype) (bh)), \
436 "1" ((USItype) (al)), \
437 "g" ((USItype) (bl)))
438
439 /* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
440 #if defined (__mc68020__) || defined(mc68020) \
441 || defined(__mc68030__) || defined(mc68030) \
442 || defined(__mc68040__) || defined(mc68040) \
443 || defined(__mcpu32__) || defined(mcpu32)
444 #define umul_ppmm(w1, w0, u, v) \
445 __asm__ ("mulu%.l %3,%1:%0" \
446 : "=d" ((USItype) (w0)), \
447 "=d" ((USItype) (w1)) \
448 : "%0" ((USItype) (u)), \
449 "dmi" ((USItype) (v)))
450 #define UMUL_TIME 45
451 #define udiv_qrnnd(q, r, n1, n0, d) \
452 __asm__ ("divu%.l %4,%1:%0" \
453 : "=d" ((USItype) (q)), \
454 "=d" ((USItype) (r)) \
455 : "0" ((USItype) (n0)), \
456 "1" ((USItype) (n1)), \
457 "dmi" ((USItype) (d)))
458 #define UDIV_TIME 90
459 #define sdiv_qrnnd(q, r, n1, n0, d) \
460 __asm__ ("divs%.l %4,%1:%0" \
461 : "=d" ((USItype) (q)), \
462 "=d" ((USItype) (r)) \
463 : "0" ((USItype) (n0)), \
464 "1" ((USItype) (n1)), \
465 "dmi" ((USItype) (d)))
466
467 #else /* not mc68020 */
468 #if !defined(__mcf5200__)
469 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
470 #define umul_ppmm(xh, xl, a, b) \
471 __asm__ ("| Inlined umul_ppmm\n" \
472 " move%.l %2,%/d0\n" \
473 " move%.l %3,%/d1\n" \
474 " move%.l %/d0,%/d2\n" \
475 " swap %/d0\n" \
476 " move%.l %/d1,%/d3\n" \
477 " swap %/d1\n" \
478 " move%.w %/d2,%/d4\n" \
479 " mulu %/d3,%/d4\n" \
480 " mulu %/d1,%/d2\n" \
481 " mulu %/d0,%/d3\n" \
482 " mulu %/d0,%/d1\n" \
483 " move%.l %/d4,%/d0\n" \
484 " eor%.w %/d0,%/d0\n" \
485 " swap %/d0\n" \
486 " add%.l %/d0,%/d2\n" \
487 " add%.l %/d3,%/d2\n" \
488 " jcc 1f\n" \
489 " add%.l %#65536,%/d1\n" \
490 "1: swap %/d2\n" \
491 " moveq %#0,%/d0\n" \
492 " move%.w %/d2,%/d0\n" \
493 " move%.w %/d4,%/d2\n" \
494 " move%.l %/d2,%1\n" \
495 " add%.l %/d1,%/d0\n" \
496 " move%.l %/d0,%0" \
497 : "=g" ((USItype) (xh)), \
498 "=g" ((USItype) (xl)) \
499 : "g" ((USItype) (a)), \
500 "g" ((USItype) (b)) \
501 : "d0", "d1", "d2", "d3", "d4")
502 #define UMUL_TIME 100
503 #define UDIV_TIME 400
504 #endif /* not mcf5200 */
505 #endif /* not mc68020 */
506
507 /* The '020, '030, '040 and '060 have bitfield insns. */
508 #if defined (__mc68020__) || defined(mc68020) \
509 || defined(__mc68030__) || defined(mc68030) \
510 || defined(__mc68040__) || defined(mc68040) \
511 || defined(__mc68060__) || defined(mc68060)
512 #define count_leading_zeros(count, x) \
513 __asm__ ("bfffo %1{%b2:%b2},%0" \
514 : "=d" ((USItype) (count)) \
515 : "od" ((USItype) (x)), "n" (0))
516 #endif
517 #endif /* mc68000 */
518
519 #if defined (__m88000__) && W_TYPE_SIZE == 32
520 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
521 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
522 : "=r" ((USItype) (sh)), \
523 "=&r" ((USItype) (sl)) \
524 : "%rJ" ((USItype) (ah)), \
525 "rJ" ((USItype) (bh)), \
526 "%rJ" ((USItype) (al)), \
527 "rJ" ((USItype) (bl)))
528 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
529 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
530 : "=r" ((USItype) (sh)), \
531 "=&r" ((USItype) (sl)) \
532 : "rJ" ((USItype) (ah)), \
533 "rJ" ((USItype) (bh)), \
534 "rJ" ((USItype) (al)), \
535 "rJ" ((USItype) (bl)))
536 #define count_leading_zeros(count, x) \
537 do { \
538 USItype __cbtmp; \
539 __asm__ ("ff1 %0,%1" \
540 : "=r" (__cbtmp) \
541 : "r" ((USItype) (x))); \
542 (count) = __cbtmp ^ 31; \
543 } while (0)
544 #define COUNT_LEADING_ZEROS_0 63 /* sic */
545 #if defined (__mc88110__)
546 #define umul_ppmm(wh, wl, u, v) \
547 do { \
548 union {UDItype __ll; \
549 struct {USItype __h, __l;} __i; \
550 } __xx; \
551 __asm__ ("mulu.d %0,%1,%2" \
552 : "=r" (__xx.__ll) \
553 : "r" ((USItype) (u)), \
554 "r" ((USItype) (v))); \
555 (wh) = __xx.__i.__h; \
556 (wl) = __xx.__i.__l; \
557 } while (0)
558 #define udiv_qrnnd(q, r, n1, n0, d) \
559 ({union {UDItype __ll; \
560 struct {USItype __h, __l;} __i; \
561 } __xx; \
562 USItype __q; \
563 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
564 __asm__ ("divu.d %0,%1,%2" \
565 : "=r" (__q) \
566 : "r" (__xx.__ll), \
567 "r" ((USItype) (d))); \
568 (r) = (n0) - __q * (d); (q) = __q; })
569 #define UMUL_TIME 5
570 #define UDIV_TIME 25
571 #else
572 #define UMUL_TIME 17
573 #define UDIV_TIME 150
574 #endif /* __mc88110__ */
575 #endif /* __m88000__ */
576
577 #if defined (__mips__) && W_TYPE_SIZE == 32
578 #define umul_ppmm(w1, w0, u, v) \
579 __asm__ ("multu %2,%3" \
580 : "=l" ((USItype) (w0)), \
581 "=h" ((USItype) (w1)) \
582 : "d" ((USItype) (u)), \
583 "d" ((USItype) (v)))
584 #define UMUL_TIME 10
585 #define UDIV_TIME 100
586 #endif /* __mips__ */
587
588 #if defined (__ns32000__) && W_TYPE_SIZE == 32
589 #define umul_ppmm(w1, w0, u, v) \
590 ({union {UDItype __ll; \
591 struct {USItype __l, __h;} __i; \
592 } __xx; \
593 __asm__ ("meid %2,%0" \
594 : "=g" (__xx.__ll) \
595 : "%0" ((USItype) (u)), \
596 "g" ((USItype) (v))); \
597 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
598 #define __umulsidi3(u, v) \
599 ({UDItype __w; \
600 __asm__ ("meid %2,%0" \
601 : "=g" (__w) \
602 : "%0" ((USItype) (u)), \
603 "g" ((USItype) (v))); \
604 __w; })
605 #define udiv_qrnnd(q, r, n1, n0, d) \
606 ({union {UDItype __ll; \
607 struct {USItype __l, __h;} __i; \
608 } __xx; \
609 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
610 __asm__ ("deid %2,%0" \
611 : "=g" (__xx.__ll) \
612 : "0" (__xx.__ll), \
613 "g" ((USItype) (d))); \
614 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
615 #define count_trailing_zeros(count,x) \
616 do { \
617 __asm__ ("ffsd %2,%0" \
618 : "=r" ((USItype) (count)) \
619 : "0" ((USItype) 0), \
620 "r" ((USItype) (x))); \
621 } while (0)
622 #endif /* __ns32000__ */
623
624 #if (defined (_ARCH_PPC) || defined (_IBMR2))
625 #if W_TYPE_SIZE == 32
626 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
627 do { \
628 if (__builtin_constant_p (bh) && (bh) == 0) \
629 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
630 : "=r" ((USItype) (sh)), \
631 "=&r" ((USItype) (sl)) \
632 : "%r" ((USItype) (ah)), \
633 "%r" ((USItype) (al)), \
634 "rI" ((USItype) (bl))); \
635 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
636 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
637 : "=r" ((USItype) (sh)), \
638 "=&r" ((USItype) (sl)) \
639 : "%r" ((USItype) (ah)), \
640 "%r" ((USItype) (al)), \
641 "rI" ((USItype) (bl))); \
642 else \
643 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
644 : "=r" ((USItype) (sh)), \
645 "=&r" ((USItype) (sl)) \
646 : "%r" ((USItype) (ah)), \
647 "r" ((USItype) (bh)), \
648 "%r" ((USItype) (al)), \
649 "rI" ((USItype) (bl))); \
650 } while (0)
651 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
652 do { \
653 if (__builtin_constant_p (ah) && (ah) == 0) \
654 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
655 : "=r" ((USItype) (sh)), \
656 "=&r" ((USItype) (sl)) \
657 : "r" ((USItype) (bh)), \
658 "rI" ((USItype) (al)), \
659 "r" ((USItype) (bl))); \
660 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
661 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
662 : "=r" ((USItype) (sh)), \
663 "=&r" ((USItype) (sl)) \
664 : "r" ((USItype) (bh)), \
665 "rI" ((USItype) (al)), \
666 "r" ((USItype) (bl))); \
667 else if (__builtin_constant_p (bh) && (bh) == 0) \
668 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
669 : "=r" ((USItype) (sh)), \
670 "=&r" ((USItype) (sl)) \
671 : "r" ((USItype) (ah)), \
672 "rI" ((USItype) (al)), \
673 "r" ((USItype) (bl))); \
674 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
675 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
676 : "=r" ((USItype) (sh)), \
677 "=&r" ((USItype) (sl)) \
678 : "r" ((USItype) (ah)), \
679 "rI" ((USItype) (al)), \
680 "r" ((USItype) (bl))); \
681 else \
682 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
683 : "=r" ((USItype) (sh)), \
684 "=&r" ((USItype) (sl)) \
685 : "r" ((USItype) (ah)), \
686 "r" ((USItype) (bh)), \
687 "rI" ((USItype) (al)), \
688 "r" ((USItype) (bl))); \
689 } while (0)
690 #endif /* W_TYPE_SIZE */
691 #define count_leading_zeros(count, x) \
692 __asm__ ("{cntlz|cntlzw} %0,%1" \
693 : "=r" ((USItype) (count)) \
694 : "r" ((USItype) (x)))
695 #define COUNT_LEADING_ZEROS_0 32
696 #if defined (_ARCH_PPC)
697 #define umul_ppmm(ph, pl, m0, m1) \
698 do { \
699 USItype __m0 = (m0), __m1 = (m1); \
700 __asm__ ("mulhwu %0,%1,%2" \
701 : "=r" ((USItype) ph) \
702 : "%r" (__m0), \
703 "r" (__m1)); \
704 (pl) = __m0 * __m1; \
705 } while (0)
706 #define UMUL_TIME 15
707 #define smul_ppmm(ph, pl, m0, m1) \
708 do { \
709 SItype __m0 = (m0), __m1 = (m1); \
710 __asm__ ("mulhw %0,%1,%2" \
711 : "=r" ((SItype) ph) \
712 : "%r" (__m0), \
713 "r" (__m1)); \
714 (pl) = __m0 * __m1; \
715 } while (0)
716 #define SMUL_TIME 14
717 #define UDIV_TIME 120
718 #elif defined (_ARCH_PWR)
719 #define umul_ppmm(xh, xl, m0, m1) \
720 do { \
721 USItype __m0 = (m0), __m1 = (m1); \
722 __asm__ ("mul %0,%2,%3" \
723 : "=r" ((USItype) (xh)), \
724 "=q" ((USItype) (xl)) \
725 : "r" (__m0), \
726 "r" (__m1)); \
727 (xh) += ((((SItype) __m0 >> 31) & __m1) \
728 + (((SItype) __m1 >> 31) & __m0)); \
729 } while (0)
730 #define UMUL_TIME 8
731 #define smul_ppmm(xh, xl, m0, m1) \
732 __asm__ ("mul %0,%2,%3" \
733 : "=r" ((SItype) (xh)), \
734 "=q" ((SItype) (xl)) \
735 : "r" (m0), \
736 "r" (m1))
737 #define SMUL_TIME 4
738 #define sdiv_qrnnd(q, r, nh, nl, d) \
739 __asm__ ("div %0,%2,%4" \
740 : "=r" ((SItype) (q)), "=q" ((SItype) (r)) \
741 : "r" ((SItype) (nh)), "1" ((SItype) (nl)), "r" ((SItype) (d)))
742 #define UDIV_TIME 100
743 #endif
744 #endif /* Power architecture variants. */
745
746 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
747 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
748 __asm__ ("a %1,%5\n\tae %0,%3" \
749 : "=r" ((USItype) (sh)), \
750 "=&r" ((USItype) (sl)) \
751 : "%0" ((USItype) (ah)), \
752 "r" ((USItype) (bh)), \
753 "%1" ((USItype) (al)), \
754 "r" ((USItype) (bl)))
755 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
756 __asm__ ("s %1,%5\n\tse %0,%3" \
757 : "=r" ((USItype) (sh)), \
758 "=&r" ((USItype) (sl)) \
759 : "0" ((USItype) (ah)), \
760 "r" ((USItype) (bh)), \
761 "1" ((USItype) (al)), \
762 "r" ((USItype) (bl)))
763 #define umul_ppmm(ph, pl, m0, m1) \
764 do { \
765 USItype __m0 = (m0), __m1 = (m1); \
766 __asm__ ( \
767 "s r2,r2\n" \
768 " mts r10,%2\n" \
769 " m r2,%3\n" \
770 " m r2,%3\n" \
771 " m r2,%3\n" \
772 " m r2,%3\n" \
773 " m r2,%3\n" \
774 " m r2,%3\n" \
775 " m r2,%3\n" \
776 " m r2,%3\n" \
777 " m r2,%3\n" \
778 " m r2,%3\n" \
779 " m r2,%3\n" \
780 " m r2,%3\n" \
781 " m r2,%3\n" \
782 " m r2,%3\n" \
783 " m r2,%3\n" \
784 " m r2,%3\n" \
785 " cas %0,r2,r0\n" \
786 " mfs r10,%1" \
787 : "=r" ((USItype) (ph)), \
788 "=r" ((USItype) (pl)) \
789 : "%r" (__m0), \
790 "r" (__m1) \
791 : "r2"); \
792 (ph) += ((((SItype) __m0 >> 31) & __m1) \
793 + (((SItype) __m1 >> 31) & __m0)); \
794 } while (0)
795 #define UMUL_TIME 20
796 #define UDIV_TIME 200
797 #define count_leading_zeros(count, x) \
798 do { \
799 if ((x) >= 0x10000) \
800 __asm__ ("clz %0,%1" \
801 : "=r" ((USItype) (count)) \
802 : "r" ((USItype) (x) >> 16)); \
803 else \
804 { \
805 __asm__ ("clz %0,%1" \
806 : "=r" ((USItype) (count)) \
807 : "r" ((USItype) (x))); \
808 (count) += 16; \
809 } \
810 } while (0)
811 #endif
812
813 #if defined (__sh2__) && W_TYPE_SIZE == 32
814 #define umul_ppmm(w1, w0, u, v) \
815 __asm__ ( \
816 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
817 : "=r" ((USItype)(w1)), \
818 "=r" ((USItype)(w0)) \
819 : "r" ((USItype)(u)), \
820 "r" ((USItype)(v)) \
821 : "macl", "mach")
822 #define UMUL_TIME 5
823 #endif
824
825 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
826 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
827 #define count_leading_zeros(count, x) \
828 do \
829 { \
830 UDItype x_ = (USItype)(x); \
831 SItype c_; \
832 \
833 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
834 (count) = c_ - 31; \
835 } \
836 while (0)
837 #define COUNT_LEADING_ZEROS_0 32
838 #endif
839
840 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
841 && W_TYPE_SIZE == 32
842 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
843 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
844 : "=r" ((USItype) (sh)), \
845 "=&r" ((USItype) (sl)) \
846 : "%rJ" ((USItype) (ah)), \
847 "rI" ((USItype) (bh)), \
848 "%rJ" ((USItype) (al)), \
849 "rI" ((USItype) (bl)) \
850 __CLOBBER_CC)
851 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
852 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
853 : "=r" ((USItype) (sh)), \
854 "=&r" ((USItype) (sl)) \
855 : "rJ" ((USItype) (ah)), \
856 "rI" ((USItype) (bh)), \
857 "rJ" ((USItype) (al)), \
858 "rI" ((USItype) (bl)) \
859 __CLOBBER_CC)
860 #if defined (__sparc_v8__)
861 #define umul_ppmm(w1, w0, u, v) \
862 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
863 : "=r" ((USItype) (w1)), \
864 "=r" ((USItype) (w0)) \
865 : "r" ((USItype) (u)), \
866 "r" ((USItype) (v)))
867 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
868 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
869 : "=&r" ((USItype) (__q)), \
870 "=&r" ((USItype) (__r)) \
871 : "r" ((USItype) (__n1)), \
872 "r" ((USItype) (__n0)), \
873 "r" ((USItype) (__d)))
874 #else
875 #if defined (__sparclite__)
876 /* This has hardware multiply but not divide. It also has two additional
877 instructions scan (ffs from high bit) and divscc. */
878 #define umul_ppmm(w1, w0, u, v) \
879 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
880 : "=r" ((USItype) (w1)), \
881 "=r" ((USItype) (w0)) \
882 : "r" ((USItype) (u)), \
883 "r" ((USItype) (v)))
884 #define udiv_qrnnd(q, r, n1, n0, d) \
885 __asm__ ("! Inlined udiv_qrnnd\n" \
886 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
887 " tst %%g0\n" \
888 " divscc %3,%4,%%g1\n" \
889 " divscc %%g1,%4,%%g1\n" \
890 " divscc %%g1,%4,%%g1\n" \
891 " divscc %%g1,%4,%%g1\n" \
892 " divscc %%g1,%4,%%g1\n" \
893 " divscc %%g1,%4,%%g1\n" \
894 " divscc %%g1,%4,%%g1\n" \
895 " divscc %%g1,%4,%%g1\n" \
896 " divscc %%g1,%4,%%g1\n" \
897 " divscc %%g1,%4,%%g1\n" \
898 " divscc %%g1,%4,%%g1\n" \
899 " divscc %%g1,%4,%%g1\n" \
900 " divscc %%g1,%4,%%g1\n" \
901 " divscc %%g1,%4,%%g1\n" \
902 " divscc %%g1,%4,%%g1\n" \
903 " divscc %%g1,%4,%%g1\n" \
904 " divscc %%g1,%4,%%g1\n" \
905 " divscc %%g1,%4,%%g1\n" \
906 " divscc %%g1,%4,%%g1\n" \
907 " divscc %%g1,%4,%%g1\n" \
908 " divscc %%g1,%4,%%g1\n" \
909 " divscc %%g1,%4,%%g1\n" \
910 " divscc %%g1,%4,%%g1\n" \
911 " divscc %%g1,%4,%%g1\n" \
912 " divscc %%g1,%4,%%g1\n" \
913 " divscc %%g1,%4,%%g1\n" \
914 " divscc %%g1,%4,%%g1\n" \
915 " divscc %%g1,%4,%%g1\n" \
916 " divscc %%g1,%4,%%g1\n" \
917 " divscc %%g1,%4,%%g1\n" \
918 " divscc %%g1,%4,%%g1\n" \
919 " divscc %%g1,%4,%0\n" \
920 " rd %%y,%1\n" \
921 " bl,a 1f\n" \
922 " add %1,%4,%1\n" \
923 "1: ! End of inline udiv_qrnnd" \
924 : "=r" ((USItype) (q)), \
925 "=r" ((USItype) (r)) \
926 : "r" ((USItype) (n1)), \
927 "r" ((USItype) (n0)), \
928 "rI" ((USItype) (d)) \
929 : "g1" __AND_CLOBBER_CC)
930 #define UDIV_TIME 37
931 #define count_leading_zeros(count, x) \
932 do { \
933 __asm__ ("scan %1,1,%0" \
934 : "=r" ((USItype) (count)) \
935 : "r" ((USItype) (x))); \
936 } while (0)
937 /* Early sparclites return 63 for an argument of 0, but they warn that future
938 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
939 undefined. */
940 #else
941 /* SPARC without integer multiplication and divide instructions.
942 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
943 #define umul_ppmm(w1, w0, u, v) \
944 __asm__ ("! Inlined umul_ppmm\n" \
945 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
946 " sra %3,31,%%o5 ! Don't move this insn\n" \
947 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
948 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
949 " mulscc %%g1,%3,%%g1\n" \
950 " mulscc %%g1,%3,%%g1\n" \
951 " mulscc %%g1,%3,%%g1\n" \
952 " mulscc %%g1,%3,%%g1\n" \
953 " mulscc %%g1,%3,%%g1\n" \
954 " mulscc %%g1,%3,%%g1\n" \
955 " mulscc %%g1,%3,%%g1\n" \
956 " mulscc %%g1,%3,%%g1\n" \
957 " mulscc %%g1,%3,%%g1\n" \
958 " mulscc %%g1,%3,%%g1\n" \
959 " mulscc %%g1,%3,%%g1\n" \
960 " mulscc %%g1,%3,%%g1\n" \
961 " mulscc %%g1,%3,%%g1\n" \
962 " mulscc %%g1,%3,%%g1\n" \
963 " mulscc %%g1,%3,%%g1\n" \
964 " mulscc %%g1,%3,%%g1\n" \
965 " mulscc %%g1,%3,%%g1\n" \
966 " mulscc %%g1,%3,%%g1\n" \
967 " mulscc %%g1,%3,%%g1\n" \
968 " mulscc %%g1,%3,%%g1\n" \
969 " mulscc %%g1,%3,%%g1\n" \
970 " mulscc %%g1,%3,%%g1\n" \
971 " mulscc %%g1,%3,%%g1\n" \
972 " mulscc %%g1,%3,%%g1\n" \
973 " mulscc %%g1,%3,%%g1\n" \
974 " mulscc %%g1,%3,%%g1\n" \
975 " mulscc %%g1,%3,%%g1\n" \
976 " mulscc %%g1,%3,%%g1\n" \
977 " mulscc %%g1,%3,%%g1\n" \
978 " mulscc %%g1,%3,%%g1\n" \
979 " mulscc %%g1,%3,%%g1\n" \
980 " mulscc %%g1,%3,%%g1\n" \
981 " mulscc %%g1,0,%%g1\n" \
982 " add %%g1,%%o5,%0\n" \
983 " rd %%y,%1" \
984 : "=r" ((USItype) (w1)), \
985 "=r" ((USItype) (w0)) \
986 : "%rI" ((USItype) (u)), \
987 "r" ((USItype) (v)) \
988 : "g1", "o5" __AND_CLOBBER_CC)
989 #define UMUL_TIME 39 /* 39 instructions */
990 /* It's quite necessary to add this much assembler for the sparc.
991 The default udiv_qrnnd (in C) is more than 10 times slower! */
992 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
993 __asm__ ("! Inlined udiv_qrnnd\n" \
994 " mov 32,%%g1\n" \
995 " subcc %1,%2,%%g0\n" \
996 "1: bcs 5f\n" \
997 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
998 " sub %1,%2,%1 ! this kills msb of n\n" \
999 " addx %1,%1,%1 ! so this can't give carry\n" \
1000 " subcc %%g1,1,%%g1\n" \
1001 "2: bne 1b\n" \
1002 " subcc %1,%2,%%g0\n" \
1003 " bcs 3f\n" \
1004 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1005 " b 3f\n" \
1006 " sub %1,%2,%1 ! this kills msb of n\n" \
1007 "4: sub %1,%2,%1\n" \
1008 "5: addxcc %1,%1,%1\n" \
1009 " bcc 2b\n" \
1010 " subcc %%g1,1,%%g1\n" \
1011 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1012 " bne 4b\n" \
1013 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1014 " sub %1,%2,%1\n" \
1015 "3: xnor %0,0,%0\n" \
1016 " ! End of inline udiv_qrnnd" \
1017 : "=&r" ((USItype) (__q)), \
1018 "=&r" ((USItype) (__r)) \
1019 : "r" ((USItype) (__d)), \
1020 "1" ((USItype) (__n1)), \
1021 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1022 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1023 #endif /* __sparclite__ */
1024 #endif /* __sparc_v8__ */
1025 #endif /* sparc32 */
1026
1027 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1028 && W_TYPE_SIZE == 64
1029 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1030 __asm__ ("addcc %r4,%5,%1\n\t" \
1031 "add %r2,%3,%0\n\t" \
1032 "bcs,a,pn %%xcc, 1f\n\t" \
1033 "add %0, 1, %0\n" \
1034 "1:" \
1035 : "=r" ((UDItype)(sh)), \
1036 "=&r" ((UDItype)(sl)) \
1037 : "%rJ" ((UDItype)(ah)), \
1038 "rI" ((UDItype)(bh)), \
1039 "%rJ" ((UDItype)(al)), \
1040 "rI" ((UDItype)(bl)) \
1041 __CLOBBER_CC)
1042
1043 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1044 __asm__ ("subcc %r4,%5,%1\n\t" \
1045 "sub %r2,%3,%0\n\t" \
1046 "bcs,a,pn %%xcc, 1f\n\t" \
1047 "sub %0, 1, %0\n\t" \
1048 "1:" \
1049 : "=r" ((UDItype)(sh)), \
1050 "=&r" ((UDItype)(sl)) \
1051 : "rJ" ((UDItype)(ah)), \
1052 "rI" ((UDItype)(bh)), \
1053 "rJ" ((UDItype)(al)), \
1054 "rI" ((UDItype)(bl)) \
1055 __CLOBBER_CC)
1056
1057 #define umul_ppmm(wh, wl, u, v) \
1058 do { \
1059 UDItype tmp1, tmp2, tmp3, tmp4; \
1060 __asm__ __volatile__ ( \
1061 "srl %7,0,%3\n\t" \
1062 "mulx %3,%6,%1\n\t" \
1063 "srlx %6,32,%2\n\t" \
1064 "mulx %2,%3,%4\n\t" \
1065 "sllx %4,32,%5\n\t" \
1066 "srl %6,0,%3\n\t" \
1067 "sub %1,%5,%5\n\t" \
1068 "srlx %5,32,%5\n\t" \
1069 "addcc %4,%5,%4\n\t" \
1070 "srlx %7,32,%5\n\t" \
1071 "mulx %3,%5,%3\n\t" \
1072 "mulx %2,%5,%5\n\t" \
1073 "sethi %%hi(0x80000000),%2\n\t" \
1074 "addcc %4,%3,%4\n\t" \
1075 "srlx %4,32,%4\n\t" \
1076 "add %2,%2,%2\n\t" \
1077 "movcc %%xcc,%%g0,%2\n\t" \
1078 "addcc %5,%4,%5\n\t" \
1079 "sllx %3,32,%3\n\t" \
1080 "add %1,%3,%1\n\t" \
1081 "add %5,%2,%0" \
1082 : "=r" ((UDItype)(wh)), \
1083 "=&r" ((UDItype)(wl)), \
1084 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1085 : "r" ((UDItype)(u)), \
1086 "r" ((UDItype)(v)) \
1087 __CLOBBER_CC); \
1088 } while (0)
1089 #define UMUL_TIME 96
1090 #define UDIV_TIME 230
1091 #endif /* sparc64 */
1092
1093 #if defined (__vax__) && W_TYPE_SIZE == 32
1094 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1095 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1096 : "=g" ((USItype) (sh)), \
1097 "=&g" ((USItype) (sl)) \
1098 : "%0" ((USItype) (ah)), \
1099 "g" ((USItype) (bh)), \
1100 "%1" ((USItype) (al)), \
1101 "g" ((USItype) (bl)))
1102 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1103 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1104 : "=g" ((USItype) (sh)), \
1105 "=&g" ((USItype) (sl)) \
1106 : "0" ((USItype) (ah)), \
1107 "g" ((USItype) (bh)), \
1108 "1" ((USItype) (al)), \
1109 "g" ((USItype) (bl)))
1110 #define umul_ppmm(xh, xl, m0, m1) \
1111 do { \
1112 union { \
1113 UDItype __ll; \
1114 struct {USItype __l, __h;} __i; \
1115 } __xx; \
1116 USItype __m0 = (m0), __m1 = (m1); \
1117 __asm__ ("emul %1,%2,$0,%0" \
1118 : "=r" (__xx.__ll) \
1119 : "g" (__m0), \
1120 "g" (__m1)); \
1121 (xh) = __xx.__i.__h; \
1122 (xl) = __xx.__i.__l; \
1123 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1124 + (((SItype) __m1 >> 31) & __m0)); \
1125 } while (0)
1126 #define sdiv_qrnnd(q, r, n1, n0, d) \
1127 do { \
1128 union {DItype __ll; \
1129 struct {SItype __l, __h;} __i; \
1130 } __xx; \
1131 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1132 __asm__ ("ediv %3,%2,%0,%1" \
1133 : "=g" (q), "=g" (r) \
1134 : "g" (__xx.__ll), "g" (d)); \
1135 } while (0)
1136 #endif /* __vax__ */
1137
1138 #if defined (__z8000__) && W_TYPE_SIZE == 16
1139 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1140 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1141 : "=r" ((unsigned int)(sh)), \
1142 "=&r" ((unsigned int)(sl)) \
1143 : "%0" ((unsigned int)(ah)), \
1144 "r" ((unsigned int)(bh)), \
1145 "%1" ((unsigned int)(al)), \
1146 "rQR" ((unsigned int)(bl)))
1147 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1148 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1149 : "=r" ((unsigned int)(sh)), \
1150 "=&r" ((unsigned int)(sl)) \
1151 : "0" ((unsigned int)(ah)), \
1152 "r" ((unsigned int)(bh)), \
1153 "1" ((unsigned int)(al)), \
1154 "rQR" ((unsigned int)(bl)))
1155 #define umul_ppmm(xh, xl, m0, m1) \
1156 do { \
1157 union {long int __ll; \
1158 struct {unsigned int __h, __l;} __i; \
1159 } __xx; \
1160 unsigned int __m0 = (m0), __m1 = (m1); \
1161 __asm__ ("mult %S0,%H3" \
1162 : "=r" (__xx.__i.__h), \
1163 "=r" (__xx.__i.__l) \
1164 : "%1" (__m0), \
1165 "rQR" (__m1)); \
1166 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1167 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1168 + (((signed int) __m1 >> 15) & __m0)); \
1169 } while (0)
1170 #endif /* __z8000__ */
1171
1172 #endif /* __GNUC__ */
1173
1174 /* If this machine has no inline assembler, use C macros. */
1175
1176 #if !defined (add_ssaaaa)
1177 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1178 do { \
1179 UWtype __x; \
1180 __x = (al) + (bl); \
1181 (sh) = (ah) + (bh) + (__x < (al)); \
1182 (sl) = __x; \
1183 } while (0)
1184 #endif
1185
1186 #if !defined (sub_ddmmss)
1187 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1188 do { \
1189 UWtype __x; \
1190 __x = (al) - (bl); \
1191 (sh) = (ah) - (bh) - (__x > (al)); \
1192 (sl) = __x; \
1193 } while (0)
1194 #endif
1195
1196 #if !defined (umul_ppmm)
1197 #define umul_ppmm(w1, w0, u, v) \
1198 do { \
1199 UWtype __x0, __x1, __x2, __x3; \
1200 UHWtype __ul, __vl, __uh, __vh; \
1201 \
1202 __ul = __ll_lowpart (u); \
1203 __uh = __ll_highpart (u); \
1204 __vl = __ll_lowpart (v); \
1205 __vh = __ll_highpart (v); \
1206 \
1207 __x0 = (UWtype) __ul * __vl; \
1208 __x1 = (UWtype) __ul * __vh; \
1209 __x2 = (UWtype) __uh * __vl; \
1210 __x3 = (UWtype) __uh * __vh; \
1211 \
1212 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1213 __x1 += __x2; /* but this indeed can */ \
1214 if (__x1 < __x2) /* did we get it? */ \
1215 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1216 \
1217 (w1) = __x3 + __ll_highpart (__x1); \
1218 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1219 } while (0)
1220 #endif
1221
1222 #if !defined (__umulsidi3)
1223 #define __umulsidi3(u, v) \
1224 ({DWunion __w; \
1225 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1226 __w.ll; })
1227 #endif
1228
1229 /* Define this unconditionally, so it can be used for debugging. */
1230 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1231 do { \
1232 UWtype __d1, __d0, __q1, __q0; \
1233 UWtype __r1, __r0, __m; \
1234 __d1 = __ll_highpart (d); \
1235 __d0 = __ll_lowpart (d); \
1236 \
1237 __r1 = (n1) % __d1; \
1238 __q1 = (n1) / __d1; \
1239 __m = (UWtype) __q1 * __d0; \
1240 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1241 if (__r1 < __m) \
1242 { \
1243 __q1--, __r1 += (d); \
1244 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1245 if (__r1 < __m) \
1246 __q1--, __r1 += (d); \
1247 } \
1248 __r1 -= __m; \
1249 \
1250 __r0 = __r1 % __d1; \
1251 __q0 = __r1 / __d1; \
1252 __m = (UWtype) __q0 * __d0; \
1253 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1254 if (__r0 < __m) \
1255 { \
1256 __q0--, __r0 += (d); \
1257 if (__r0 >= (d)) \
1258 if (__r0 < __m) \
1259 __q0--, __r0 += (d); \
1260 } \
1261 __r0 -= __m; \
1262 \
1263 (q) = (UWtype) __q1 * __ll_B | __q0; \
1264 (r) = __r0; \
1265 } while (0)
1266
1267 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1268 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1269 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1270 #define udiv_qrnnd(q, r, nh, nl, d) \
1271 do { \
1272 USItype __r; \
1273 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1274 (r) = __r; \
1275 } while (0)
1276 #endif
1277
1278 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1279 #if !defined (udiv_qrnnd)
1280 #define UDIV_NEEDS_NORMALIZATION 1
1281 #define udiv_qrnnd __udiv_qrnnd_c
1282 #endif
1283
1284 #if !defined (count_leading_zeros)
1285 extern const UQItype __clz_tab[];
1286 #define count_leading_zeros(count, x) \
1287 do { \
1288 UWtype __xr = (x); \
1289 UWtype __a; \
1290 \
1291 if (W_TYPE_SIZE <= 32) \
1292 { \
1293 __a = __xr < ((UWtype)1<<2*__BITS4) \
1294 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1295 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1296 } \
1297 else \
1298 { \
1299 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1300 if (((__xr >> __a) & 0xff) != 0) \
1301 break; \
1302 } \
1303 \
1304 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1305 } while (0)
1306 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1307 #endif
1308
1309 #if !defined (count_trailing_zeros)
1310 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1311 defined in asm, but if it is not, the C version above is good enough. */
1312 #define count_trailing_zeros(count, x) \
1313 do { \
1314 UWtype __ctz_x = (x); \
1315 UWtype __ctz_c; \
1316 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1317 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1318 } while (0)
1319 #endif
1320
1321 #ifndef UDIV_NEEDS_NORMALIZATION
1322 #define UDIV_NEEDS_NORMALIZATION 0
1323 #endif
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