2002-08-22 Paolo Carlini <pcarlini@unitus.it>
[official-gcc.git] / gcc / local-alloc.c
blob04e2fbe5a4c7cc5951bb03cc6b223b34b7cc8ac7
1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
56 yet implemented. */
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
62 #include "config.h"
63 #include "system.h"
64 #include "rtl.h"
65 #include "tm_p.h"
66 #include "flags.h"
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
69 #include "regs.h"
70 #include "function.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
73 #include "recog.h"
74 #include "output.h"
75 #include "toplev.h"
76 #include "except.h"
77 #include "integrate.h"
79 /* Next quantity number available for allocation. */
81 static int next_qty;
83 /* Information we maintain about each quantity. */
84 struct qty
86 /* The number of refs to quantity Q. */
88 int n_refs;
90 /* The frequency of uses of quantity Q. */
92 int freq;
94 /* Insn number (counting from head of basic block)
95 where quantity Q was born. -1 if birth has not been recorded. */
97 int birth;
99 /* Insn number (counting from head of basic block)
100 where given quantity died. Due to the way tying is done,
101 and the fact that we consider in this pass only regs that die but once,
102 a quantity can die only once. Each quantity's life span
103 is a set of consecutive insns. -1 if death has not been recorded. */
105 int death;
107 /* Number of words needed to hold the data in given quantity.
108 This depends on its machine mode. It is used for these purposes:
109 1. It is used in computing the relative importances of qtys,
110 which determines the order in which we look for regs for them.
111 2. It is used in rules that prevent tying several registers of
112 different sizes in a way that is geometrically impossible
113 (see combine_regs). */
115 int size;
117 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
119 int n_calls_crossed;
121 /* The register number of one pseudo register whose reg_qty value is Q.
122 This register should be the head of the chain
123 maintained in reg_next_in_qty. */
125 int first_reg;
127 /* Reg class contained in (smaller than) the preferred classes of all
128 the pseudo regs that are tied in given quantity.
129 This is the preferred class for allocating that quantity. */
131 enum reg_class min_class;
133 /* Register class within which we allocate given qty if we can't get
134 its preferred class. */
136 enum reg_class alternate_class;
138 /* This holds the mode of the registers that are tied to given qty,
139 or VOIDmode if registers with differing modes are tied together. */
141 enum machine_mode mode;
143 /* the hard reg number chosen for given quantity,
144 or -1 if none was found. */
146 short phys_reg;
148 /* Nonzero if this quantity has been used in a SUBREG in some
149 way that is illegal. */
151 char changes_mode;
155 static struct qty *qty;
157 /* These fields are kept separately to speedup their clearing. */
159 /* We maintain two hard register sets that indicate suggested hard registers
160 for each quantity. The first, phys_copy_sugg, contains hard registers
161 that are tied to the quantity by a simple copy. The second contains all
162 hard registers that are tied to the quantity via an arithmetic operation.
164 The former register set is given priority for allocation. This tends to
165 eliminate copy insns. */
167 /* Element Q is a set of hard registers that are suggested for quantity Q by
168 copy insns. */
170 static HARD_REG_SET *qty_phys_copy_sugg;
172 /* Element Q is a set of hard registers that are suggested for quantity Q by
173 arithmetic insns. */
175 static HARD_REG_SET *qty_phys_sugg;
177 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
179 static short *qty_phys_num_copy_sugg;
181 /* Element Q is the number of suggested registers in qty_phys_sugg. */
183 static short *qty_phys_num_sugg;
185 /* If (REG N) has been assigned a quantity number, is a register number
186 of another register assigned the same quantity number, or -1 for the
187 end of the chain. qty->first_reg point to the head of this chain. */
189 static int *reg_next_in_qty;
191 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
192 if it is >= 0,
193 of -1 if this register cannot be allocated by local-alloc,
194 or -2 if not known yet.
196 Note that if we see a use or death of pseudo register N with
197 reg_qty[N] == -2, register N must be local to the current block. If
198 it were used in more than one block, we would have reg_qty[N] == -1.
199 This relies on the fact that if reg_basic_block[N] is >= 0, register N
200 will not appear in any other block. We save a considerable number of
201 tests by exploiting this.
203 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
204 be referenced. */
206 static int *reg_qty;
208 /* The offset (in words) of register N within its quantity.
209 This can be nonzero if register N is SImode, and has been tied
210 to a subreg of a DImode register. */
212 static char *reg_offset;
214 /* Vector of substitutions of register numbers,
215 used to map pseudo regs into hardware regs.
216 This is set up as a result of register allocation.
217 Element N is the hard reg assigned to pseudo reg N,
218 or is -1 if no hard reg was assigned.
219 If N is a hard reg number, element N is N. */
221 short *reg_renumber;
223 /* Set of hard registers live at the current point in the scan
224 of the instructions in a basic block. */
226 static HARD_REG_SET regs_live;
228 /* Each set of hard registers indicates registers live at a particular
229 point in the basic block. For N even, regs_live_at[N] says which
230 hard registers are needed *after* insn N/2 (i.e., they may not
231 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
233 If an object is to conflict with the inputs of insn J but not the
234 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
235 if it is to conflict with the outputs of insn J but not the inputs of
236 insn J + 1, it is said to die at index J*2 + 1. */
238 static HARD_REG_SET *regs_live_at;
240 /* Communicate local vars `insn_number' and `insn'
241 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
242 static int this_insn_number;
243 static rtx this_insn;
245 struct equivalence
247 /* Set when an attempt should be made to replace a register
248 with the associated src_p entry. */
250 char replace;
252 /* Set when a REG_EQUIV note is found or created. Use to
253 keep track of what memory accesses might be created later,
254 e.g. by reload. */
256 rtx replacement;
258 rtx *src_p;
260 /* Loop depth is used to recognize equivalences which appear
261 to be present within the same loop (or in an inner loop). */
263 int loop_depth;
265 /* The list of each instruction which initializes this register. */
267 rtx init_insns;
270 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
271 structure for that register. */
273 static struct equivalence *reg_equiv;
275 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
276 static int recorded_label_ref;
278 static void alloc_qty PARAMS ((int, enum machine_mode, int, int));
279 static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *));
280 static int validate_equiv_mem PARAMS ((rtx, rtx, rtx));
281 static int equiv_init_varies_p PARAMS ((rtx));
282 static int equiv_init_movable_p PARAMS ((rtx, int));
283 static int contains_replace_regs PARAMS ((rtx));
284 static int memref_referenced_p PARAMS ((rtx, rtx));
285 static int memref_used_between_p PARAMS ((rtx, rtx, rtx));
286 static void update_equiv_regs PARAMS ((void));
287 static void no_equiv PARAMS ((rtx, rtx, void *));
288 static void block_alloc PARAMS ((int));
289 static int qty_sugg_compare PARAMS ((int, int));
290 static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR));
291 static int qty_compare PARAMS ((int, int));
292 static int qty_compare_1 PARAMS ((const PTR, const PTR));
293 static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int));
294 static int reg_meets_class_p PARAMS ((int, enum reg_class));
295 static void update_qty_class PARAMS ((int, int));
296 static void reg_is_set PARAMS ((rtx, rtx, void *));
297 static void reg_is_born PARAMS ((rtx, int));
298 static void wipe_dead_reg PARAMS ((rtx, int));
299 static int find_free_reg PARAMS ((enum reg_class, enum machine_mode,
300 int, int, int, int, int));
301 static void mark_life PARAMS ((int, enum machine_mode, int));
302 static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int));
303 static int no_conflict_p PARAMS ((rtx, rtx, rtx));
304 static int requires_inout PARAMS ((const char *));
306 /* Allocate a new quantity (new within current basic block)
307 for register number REGNO which is born at index BIRTH
308 within the block. MODE and SIZE are info on reg REGNO. */
310 static void
311 alloc_qty (regno, mode, size, birth)
312 int regno;
313 enum machine_mode mode;
314 int size, birth;
316 int qtyno = next_qty++;
318 reg_qty[regno] = qtyno;
319 reg_offset[regno] = 0;
320 reg_next_in_qty[regno] = -1;
322 qty[qtyno].first_reg = regno;
323 qty[qtyno].size = size;
324 qty[qtyno].mode = mode;
325 qty[qtyno].birth = birth;
326 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
327 qty[qtyno].min_class = reg_preferred_class (regno);
328 qty[qtyno].alternate_class = reg_alternate_class (regno);
329 qty[qtyno].n_refs = REG_N_REFS (regno);
330 qty[qtyno].freq = REG_FREQ (regno);
331 qty[qtyno].changes_mode = REG_CHANGES_MODE (regno);
334 /* Main entry point of this file. */
337 local_alloc ()
339 int i;
340 int max_qty;
341 basic_block b;
343 /* We need to keep track of whether or not we recorded a LABEL_REF so
344 that we know if the jump optimizer needs to be rerun. */
345 recorded_label_ref = 0;
347 /* Leaf functions and non-leaf functions have different needs.
348 If defined, let the machine say what kind of ordering we
349 should use. */
350 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
351 ORDER_REGS_FOR_LOCAL_ALLOC;
352 #endif
354 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
355 registers. */
356 if (optimize)
357 update_equiv_regs ();
359 /* This sets the maximum number of quantities we can have. Quantity
360 numbers start at zero and we can have one for each pseudo. */
361 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
363 /* Allocate vectors of temporary data.
364 See the declarations of these variables, above,
365 for what they mean. */
367 qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty));
368 qty_phys_copy_sugg
369 = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
370 qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short));
371 qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
372 qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short));
374 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
375 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
376 reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int));
378 /* Determine which pseudo-registers can be allocated by local-alloc.
379 In general, these are the registers used only in a single block and
380 which only die once.
382 We need not be concerned with which block actually uses the register
383 since we will never see it outside that block. */
385 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
387 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
388 reg_qty[i] = -2;
389 else
390 reg_qty[i] = -1;
393 /* Force loop below to initialize entire quantity array. */
394 next_qty = max_qty;
396 /* Allocate each block's local registers, block by block. */
398 FOR_EACH_BB (b)
400 /* NEXT_QTY indicates which elements of the `qty_...'
401 vectors might need to be initialized because they were used
402 for the previous block; it is set to the entire array before
403 block 0. Initialize those, with explicit loop if there are few,
404 else with bzero and bcopy. Do not initialize vectors that are
405 explicit set by `alloc_qty'. */
407 if (next_qty < 6)
409 for (i = 0; i < next_qty; i++)
411 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
412 qty_phys_num_copy_sugg[i] = 0;
413 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
414 qty_phys_num_sugg[i] = 0;
417 else
419 #define CLEAR(vector) \
420 memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
422 CLEAR (qty_phys_copy_sugg);
423 CLEAR (qty_phys_num_copy_sugg);
424 CLEAR (qty_phys_sugg);
425 CLEAR (qty_phys_num_sugg);
428 next_qty = 0;
430 block_alloc (b->index);
433 free (qty);
434 free (qty_phys_copy_sugg);
435 free (qty_phys_num_copy_sugg);
436 free (qty_phys_sugg);
437 free (qty_phys_num_sugg);
439 free (reg_qty);
440 free (reg_offset);
441 free (reg_next_in_qty);
443 return recorded_label_ref;
446 /* Used for communication between the following two functions: contains
447 a MEM that we wish to ensure remains unchanged. */
448 static rtx equiv_mem;
450 /* Set nonzero if EQUIV_MEM is modified. */
451 static int equiv_mem_modified;
453 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
454 Called via note_stores. */
456 static void
457 validate_equiv_mem_from_store (dest, set, data)
458 rtx dest;
459 rtx set ATTRIBUTE_UNUSED;
460 void *data ATTRIBUTE_UNUSED;
462 if ((GET_CODE (dest) == REG
463 && reg_overlap_mentioned_p (dest, equiv_mem))
464 || (GET_CODE (dest) == MEM
465 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
466 equiv_mem_modified = 1;
469 /* Verify that no store between START and the death of REG invalidates
470 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
471 by storing into an overlapping memory location, or with a non-const
472 CALL_INSN.
474 Return 1 if MEMREF remains valid. */
476 static int
477 validate_equiv_mem (start, reg, memref)
478 rtx start;
479 rtx reg;
480 rtx memref;
482 rtx insn;
483 rtx note;
485 equiv_mem = memref;
486 equiv_mem_modified = 0;
488 /* If the memory reference has side effects or is volatile, it isn't a
489 valid equivalence. */
490 if (side_effects_p (memref))
491 return 0;
493 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
495 if (! INSN_P (insn))
496 continue;
498 if (find_reg_note (insn, REG_DEAD, reg))
499 return 1;
501 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
502 && ! CONST_OR_PURE_CALL_P (insn))
503 return 0;
505 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
507 /* If a register mentioned in MEMREF is modified via an
508 auto-increment, we lose the equivalence. Do the same if one
509 dies; although we could extend the life, it doesn't seem worth
510 the trouble. */
512 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
513 if ((REG_NOTE_KIND (note) == REG_INC
514 || REG_NOTE_KIND (note) == REG_DEAD)
515 && GET_CODE (XEXP (note, 0)) == REG
516 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
517 return 0;
520 return 0;
523 /* Returns zero if X is known to be invariant. */
525 static int
526 equiv_init_varies_p (x)
527 rtx x;
529 RTX_CODE code = GET_CODE (x);
530 int i;
531 const char *fmt;
533 switch (code)
535 case MEM:
536 return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0));
538 case QUEUED:
539 return 1;
541 case CONST:
542 case CONST_INT:
543 case CONST_DOUBLE:
544 case CONST_VECTOR:
545 case SYMBOL_REF:
546 case LABEL_REF:
547 return 0;
549 case REG:
550 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
552 case ASM_OPERANDS:
553 if (MEM_VOLATILE_P (x))
554 return 1;
556 /* FALLTHROUGH */
558 default:
559 break;
562 fmt = GET_RTX_FORMAT (code);
563 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
564 if (fmt[i] == 'e')
566 if (equiv_init_varies_p (XEXP (x, i)))
567 return 1;
569 else if (fmt[i] == 'E')
571 int j;
572 for (j = 0; j < XVECLEN (x, i); j++)
573 if (equiv_init_varies_p (XVECEXP (x, i, j)))
574 return 1;
577 return 0;
580 /* Returns non-zero if X (used to initialize register REGNO) is movable.
581 X is only movable if the registers it uses have equivalent initializations
582 which appear to be within the same loop (or in an inner loop) and movable
583 or if they are not candidates for local_alloc and don't vary. */
585 static int
586 equiv_init_movable_p (x, regno)
587 rtx x;
588 int regno;
590 int i, j;
591 const char *fmt;
592 enum rtx_code code = GET_CODE (x);
594 switch (code)
596 case SET:
597 return equiv_init_movable_p (SET_SRC (x), regno);
599 case CC0:
600 case CLOBBER:
601 return 0;
603 case PRE_INC:
604 case PRE_DEC:
605 case POST_INC:
606 case POST_DEC:
607 case PRE_MODIFY:
608 case POST_MODIFY:
609 return 0;
611 case REG:
612 return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
613 && reg_equiv[REGNO (x)].replace)
614 || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0));
616 case UNSPEC_VOLATILE:
617 return 0;
619 case ASM_OPERANDS:
620 if (MEM_VOLATILE_P (x))
621 return 0;
623 /* FALLTHROUGH */
625 default:
626 break;
629 fmt = GET_RTX_FORMAT (code);
630 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
631 switch (fmt[i])
633 case 'e':
634 if (! equiv_init_movable_p (XEXP (x, i), regno))
635 return 0;
636 break;
637 case 'E':
638 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
639 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
640 return 0;
641 break;
644 return 1;
647 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
649 static int
650 contains_replace_regs (x)
651 rtx x;
653 int i, j;
654 const char *fmt;
655 enum rtx_code code = GET_CODE (x);
657 switch (code)
659 case CONST_INT:
660 case CONST:
661 case LABEL_REF:
662 case SYMBOL_REF:
663 case CONST_DOUBLE:
664 case CONST_VECTOR:
665 case PC:
666 case CC0:
667 case HIGH:
668 return 0;
670 case REG:
671 return reg_equiv[REGNO (x)].replace;
673 default:
674 break;
677 fmt = GET_RTX_FORMAT (code);
678 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
679 switch (fmt[i])
681 case 'e':
682 if (contains_replace_regs (XEXP (x, i)))
683 return 1;
684 break;
685 case 'E':
686 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
687 if (contains_replace_regs (XVECEXP (x, i, j)))
688 return 1;
689 break;
692 return 0;
695 /* TRUE if X references a memory location that would be affected by a store
696 to MEMREF. */
698 static int
699 memref_referenced_p (memref, x)
700 rtx x;
701 rtx memref;
703 int i, j;
704 const char *fmt;
705 enum rtx_code code = GET_CODE (x);
707 switch (code)
709 case CONST_INT:
710 case CONST:
711 case LABEL_REF:
712 case SYMBOL_REF:
713 case CONST_DOUBLE:
714 case CONST_VECTOR:
715 case PC:
716 case CC0:
717 case HIGH:
718 case LO_SUM:
719 return 0;
721 case REG:
722 return (reg_equiv[REGNO (x)].replacement
723 && memref_referenced_p (memref,
724 reg_equiv[REGNO (x)].replacement));
726 case MEM:
727 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
728 return 1;
729 break;
731 case SET:
732 /* If we are setting a MEM, it doesn't count (its address does), but any
733 other SET_DEST that has a MEM in it is referencing the MEM. */
734 if (GET_CODE (SET_DEST (x)) == MEM)
736 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
737 return 1;
739 else if (memref_referenced_p (memref, SET_DEST (x)))
740 return 1;
742 return memref_referenced_p (memref, SET_SRC (x));
744 default:
745 break;
748 fmt = GET_RTX_FORMAT (code);
749 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
750 switch (fmt[i])
752 case 'e':
753 if (memref_referenced_p (memref, XEXP (x, i)))
754 return 1;
755 break;
756 case 'E':
757 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
758 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
759 return 1;
760 break;
763 return 0;
766 /* TRUE if some insn in the range (START, END] references a memory location
767 that would be affected by a store to MEMREF. */
769 static int
770 memref_used_between_p (memref, start, end)
771 rtx memref;
772 rtx start;
773 rtx end;
775 rtx insn;
777 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
778 insn = NEXT_INSN (insn))
779 if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
780 return 1;
782 return 0;
785 /* Return nonzero if the rtx X is invariant over the current function. */
786 /* ??? Actually, the places this is used in reload expect exactly what
787 is tested here, and not everything that is function invariant. In
788 particular, the frame pointer and arg pointer are special cased;
789 pic_offset_table_rtx is not, and this will cause aborts when we
790 go to spill these things to memory. */
793 function_invariant_p (x)
794 rtx x;
796 if (CONSTANT_P (x))
797 return 1;
798 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
799 return 1;
800 if (GET_CODE (x) == PLUS
801 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
802 && CONSTANT_P (XEXP (x, 1)))
803 return 1;
804 return 0;
807 /* Find registers that are equivalent to a single value throughout the
808 compilation (either because they can be referenced in memory or are set once
809 from a single constant). Lower their priority for a register.
811 If such a register is only referenced once, try substituting its value
812 into the using insn. If it succeeds, we can eliminate the register
813 completely. */
815 static void
816 update_equiv_regs ()
818 rtx insn;
819 basic_block bb;
820 int loop_depth;
821 regset_head cleared_regs;
822 int clear_regnos = 0;
824 reg_equiv = (struct equivalence *) xcalloc (max_regno, sizeof *reg_equiv);
825 INIT_REG_SET (&cleared_regs);
827 init_alias_analysis ();
829 /* Scan the insns and find which registers have equivalences. Do this
830 in a separate scan of the insns because (due to -fcse-follow-jumps)
831 a register can be set below its use. */
832 FOR_EACH_BB (bb)
834 loop_depth = bb->loop_depth;
836 for (insn = bb->head; insn != NEXT_INSN (bb->end); insn = NEXT_INSN (insn))
838 rtx note;
839 rtx set;
840 rtx dest, src;
841 int regno;
843 if (! INSN_P (insn))
844 continue;
846 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
847 if (REG_NOTE_KIND (note) == REG_INC)
848 no_equiv (XEXP (note, 0), note, NULL);
850 set = single_set (insn);
852 /* If this insn contains more (or less) than a single SET,
853 only mark all destinations as having no known equivalence. */
854 if (set == 0)
856 note_stores (PATTERN (insn), no_equiv, NULL);
857 continue;
859 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
861 int i;
863 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
865 rtx part = XVECEXP (PATTERN (insn), 0, i);
866 if (part != set)
867 note_stores (part, no_equiv, NULL);
871 dest = SET_DEST (set);
872 src = SET_SRC (set);
874 /* If this sets a MEM to the contents of a REG that is only used
875 in a single basic block, see if the register is always equivalent
876 to that memory location and if moving the store from INSN to the
877 insn that set REG is safe. If so, put a REG_EQUIV note on the
878 initializing insn.
880 Don't add a REG_EQUIV note if the insn already has one. The existing
881 REG_EQUIV is likely more useful than the one we are adding.
883 If one of the regs in the address has reg_equiv[REGNO].replace set,
884 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
885 optimization may move the set of this register immediately before
886 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
887 the mention in the REG_EQUIV note would be to an uninitialized
888 pseudo. */
889 /* ????? This test isn't good enough; we might see a MEM with a use of
890 a pseudo register before we see its setting insn that will cause
891 reg_equiv[].replace for that pseudo to be set.
892 Equivalences to MEMs should be made in another pass, after the
893 reg_equiv[].replace information has been gathered. */
895 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
896 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
897 && REG_BASIC_BLOCK (regno) >= 0
898 && REG_N_SETS (regno) == 1
899 && reg_equiv[regno].init_insns != 0
900 && reg_equiv[regno].init_insns != const0_rtx
901 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
902 REG_EQUIV, NULL_RTX)
903 && ! contains_replace_regs (XEXP (dest, 0)))
905 rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
906 if (validate_equiv_mem (init_insn, src, dest)
907 && ! memref_used_between_p (dest, init_insn, insn))
908 REG_NOTES (init_insn)
909 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
912 /* We only handle the case of a pseudo register being set
913 once, or always to the same value. */
914 /* ??? The mn10200 port breaks if we add equivalences for
915 values that need an ADDRESS_REGS register and set them equivalent
916 to a MEM of a pseudo. The actual problem is in the over-conservative
917 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
918 calculate_needs, but we traditionally work around this problem
919 here by rejecting equivalences when the destination is in a register
920 that's likely spilled. This is fragile, of course, since the
921 preferred class of a pseudo depends on all instructions that set
922 or use it. */
924 if (GET_CODE (dest) != REG
925 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
926 || reg_equiv[regno].init_insns == const0_rtx
927 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
928 && GET_CODE (src) == MEM))
930 /* This might be seting a SUBREG of a pseudo, a pseudo that is
931 also set somewhere else to a constant. */
932 note_stores (set, no_equiv, NULL);
933 continue;
936 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
938 /* cse sometimes generates function invariants, but doesn't put a
939 REG_EQUAL note on the insn. Since this note would be redundant,
940 there's no point creating it earlier than here. */
941 if (! note && ! rtx_varies_p (src, 0))
942 note = set_unique_reg_note (insn, REG_EQUAL, src);
944 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
945 since it represents a function call */
946 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
947 note = NULL_RTX;
949 if (REG_N_SETS (regno) != 1
950 && (! note
951 || rtx_varies_p (XEXP (note, 0), 0)
952 || (reg_equiv[regno].replacement
953 && ! rtx_equal_p (XEXP (note, 0),
954 reg_equiv[regno].replacement))))
956 no_equiv (dest, set, NULL);
957 continue;
959 /* Record this insn as initializing this register. */
960 reg_equiv[regno].init_insns
961 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
963 /* If this register is known to be equal to a constant, record that
964 it is always equivalent to the constant. */
965 if (note && ! rtx_varies_p (XEXP (note, 0), 0))
966 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
968 /* If this insn introduces a "constant" register, decrease the priority
969 of that register. Record this insn if the register is only used once
970 more and the equivalence value is the same as our source.
972 The latter condition is checked for two reasons: First, it is an
973 indication that it may be more efficient to actually emit the insn
974 as written (if no registers are available, reload will substitute
975 the equivalence). Secondly, it avoids problems with any registers
976 dying in this insn whose death notes would be missed.
978 If we don't have a REG_EQUIV note, see if this insn is loading
979 a register used only in one basic block from a MEM. If so, and the
980 MEM remains unchanged for the life of the register, add a REG_EQUIV
981 note. */
983 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
985 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
986 && GET_CODE (SET_SRC (set)) == MEM
987 && validate_equiv_mem (insn, dest, SET_SRC (set)))
988 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
989 REG_NOTES (insn));
991 if (note)
993 int regno = REGNO (dest);
995 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
996 We might end up substituting the LABEL_REF for uses of the
997 pseudo here or later. That kind of transformation may turn an
998 indirect jump into a direct jump, in which case we must rerun the
999 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
1000 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
1001 || (GET_CODE (XEXP (note, 0)) == CONST
1002 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
1003 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
1004 == LABEL_REF)))
1005 recorded_label_ref = 1;
1007 reg_equiv[regno].replacement = XEXP (note, 0);
1008 reg_equiv[regno].src_p = &SET_SRC (set);
1009 reg_equiv[regno].loop_depth = loop_depth;
1011 /* Don't mess with things live during setjmp. */
1012 if (REG_LIVE_LENGTH (regno) >= 0 && optimize)
1014 /* Note that the statement below does not affect the priority
1015 in local-alloc! */
1016 REG_LIVE_LENGTH (regno) *= 2;
1019 /* If the register is referenced exactly twice, meaning it is
1020 set once and used once, indicate that the reference may be
1021 replaced by the equivalence we computed above. Do this
1022 even if the register is only used in one block so that
1023 dependencies can be handled where the last register is
1024 used in a different block (i.e. HIGH / LO_SUM sequences)
1025 and to reduce the number of registers alive across
1026 calls. */
1028 if (REG_N_REFS (regno) == 2
1029 && (rtx_equal_p (XEXP (note, 0), src)
1030 || ! equiv_init_varies_p (src))
1031 && GET_CODE (insn) == INSN
1032 && equiv_init_movable_p (PATTERN (insn), regno))
1033 reg_equiv[regno].replace = 1;
1039 /* Now scan all regs killed in an insn to see if any of them are
1040 registers only used that once. If so, see if we can replace the
1041 reference with the equivalent from. If we can, delete the
1042 initializing reference and this register will go away. If we
1043 can't replace the reference, and the initialzing reference is
1044 within the same loop (or in an inner loop), then move the register
1045 initialization just before the use, so that they are in the same
1046 basic block. */
1047 FOR_EACH_BB_REVERSE (bb)
1049 loop_depth = bb->loop_depth;
1050 for (insn = bb->end; insn != PREV_INSN (bb->head); insn = PREV_INSN (insn))
1052 rtx link;
1054 if (! INSN_P (insn))
1055 continue;
1057 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1059 if (REG_NOTE_KIND (link) == REG_DEAD
1060 /* Make sure this insn still refers to the register. */
1061 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1063 int regno = REGNO (XEXP (link, 0));
1064 rtx equiv_insn;
1066 if (! reg_equiv[regno].replace
1067 || reg_equiv[regno].loop_depth < loop_depth)
1068 continue;
1070 /* reg_equiv[REGNO].replace gets set only when
1071 REG_N_REFS[REGNO] is 2, i.e. the register is set
1072 once and used once. (If it were only set, but not used,
1073 flow would have deleted the setting insns.) Hence
1074 there can only be one insn in reg_equiv[REGNO].init_insns. */
1075 if (reg_equiv[regno].init_insns == NULL_RTX
1076 || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX)
1077 abort ();
1078 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
1080 /* We may not move instructions that can throw, since
1081 that changes basic block boundaries and we are not
1082 prepared to adjust the CFG to match. */
1083 if (can_throw_internal (equiv_insn))
1084 continue;
1086 if (asm_noperands (PATTERN (equiv_insn)) < 0
1087 && validate_replace_rtx (regno_reg_rtx[regno],
1088 *(reg_equiv[regno].src_p), insn))
1090 rtx equiv_link;
1091 rtx last_link;
1092 rtx note;
1094 /* Find the last note. */
1095 for (last_link = link; XEXP (last_link, 1);
1096 last_link = XEXP (last_link, 1))
1099 /* Append the REG_DEAD notes from equiv_insn. */
1100 equiv_link = REG_NOTES (equiv_insn);
1101 while (equiv_link)
1103 note = equiv_link;
1104 equiv_link = XEXP (equiv_link, 1);
1105 if (REG_NOTE_KIND (note) == REG_DEAD)
1107 remove_note (equiv_insn, note);
1108 XEXP (last_link, 1) = note;
1109 XEXP (note, 1) = NULL_RTX;
1110 last_link = note;
1114 remove_death (regno, insn);
1115 REG_N_REFS (regno) = 0;
1116 REG_FREQ (regno) = 0;
1117 delete_insn (equiv_insn);
1119 reg_equiv[regno].init_insns
1120 = XEXP (reg_equiv[regno].init_insns, 1);
1122 /* Move the initialization of the register to just before
1123 INSN. Update the flow information. */
1124 else if (PREV_INSN (insn) != equiv_insn)
1126 rtx new_insn;
1128 new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
1129 REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
1130 REG_NOTES (equiv_insn) = 0;
1132 /* Make sure this insn is recognized before reload begins,
1133 otherwise eliminate_regs_in_insn will abort. */
1134 INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
1136 delete_insn (equiv_insn);
1138 XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
1140 REG_BASIC_BLOCK (regno) = bb->index;
1141 REG_N_CALLS_CROSSED (regno) = 0;
1142 REG_LIVE_LENGTH (regno) = 2;
1144 if (insn == bb->head)
1145 bb->head = PREV_INSN (insn);
1147 /* Remember to clear REGNO from all basic block's live
1148 info. */
1149 SET_REGNO_REG_SET (&cleared_regs, regno);
1150 clear_regnos++;
1157 /* Clear all dead REGNOs from all basic block's live info. */
1158 if (clear_regnos)
1160 int j;
1161 if (clear_regnos > 8)
1163 FOR_EACH_BB (bb)
1165 AND_COMPL_REG_SET (bb->global_live_at_start, &cleared_regs);
1166 AND_COMPL_REG_SET (bb->global_live_at_end, &cleared_regs);
1169 else
1170 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j,
1172 FOR_EACH_BB (bb)
1174 CLEAR_REGNO_REG_SET (bb->global_live_at_start, j);
1175 CLEAR_REGNO_REG_SET (bb->global_live_at_end, j);
1180 /* Clean up. */
1181 end_alias_analysis ();
1182 CLEAR_REG_SET (&cleared_regs);
1183 free (reg_equiv);
1186 /* Mark REG as having no known equivalence.
1187 Some instructions might have been proceessed before and furnished
1188 with REG_EQUIV notes for this register; these notes will have to be
1189 removed.
1190 STORE is the piece of RTL that does the non-constant / conflicting
1191 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1192 but needs to be there because this function is called from note_stores. */
1193 static void
1194 no_equiv (reg, store, data)
1195 rtx reg, store ATTRIBUTE_UNUSED;
1196 void *data ATTRIBUTE_UNUSED;
1198 int regno;
1199 rtx list;
1201 if (GET_CODE (reg) != REG)
1202 return;
1203 regno = REGNO (reg);
1204 list = reg_equiv[regno].init_insns;
1205 if (list == const0_rtx)
1206 return;
1207 for (; list; list = XEXP (list, 1))
1209 rtx insn = XEXP (list, 0);
1210 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1212 reg_equiv[regno].init_insns = const0_rtx;
1213 reg_equiv[regno].replacement = NULL_RTX;
1216 /* Allocate hard regs to the pseudo regs used only within block number B.
1217 Only the pseudos that die but once can be handled. */
1219 static void
1220 block_alloc (b)
1221 int b;
1223 int i, q;
1224 rtx insn;
1225 rtx note, hard_reg;
1226 int insn_number = 0;
1227 int insn_count = 0;
1228 int max_uid = get_max_uid ();
1229 int *qty_order;
1230 int no_conflict_combined_regno = -1;
1232 /* Count the instructions in the basic block. */
1234 insn = BLOCK_END (b);
1235 while (1)
1237 if (GET_CODE (insn) != NOTE)
1238 if (++insn_count > max_uid)
1239 abort ();
1240 if (insn == BLOCK_HEAD (b))
1241 break;
1242 insn = PREV_INSN (insn);
1245 /* +2 to leave room for a post_mark_life at the last insn and for
1246 the birth of a CLOBBER in the first insn. */
1247 regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2),
1248 sizeof (HARD_REG_SET));
1250 /* Initialize table of hardware registers currently live. */
1252 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1254 /* This loop scans the instructions of the basic block
1255 and assigns quantities to registers.
1256 It computes which registers to tie. */
1258 insn = BLOCK_HEAD (b);
1259 while (1)
1261 if (GET_CODE (insn) != NOTE)
1262 insn_number++;
1264 if (INSN_P (insn))
1266 rtx link, set;
1267 int win = 0;
1268 rtx r0, r1 = NULL_RTX;
1269 int combined_regno = -1;
1270 int i;
1272 this_insn_number = insn_number;
1273 this_insn = insn;
1275 extract_insn (insn);
1276 which_alternative = -1;
1278 /* Is this insn suitable for tying two registers?
1279 If so, try doing that.
1280 Suitable insns are those with at least two operands and where
1281 operand 0 is an output that is a register that is not
1282 earlyclobber.
1284 We can tie operand 0 with some operand that dies in this insn.
1285 First look for operands that are required to be in the same
1286 register as operand 0. If we find such, only try tying that
1287 operand or one that can be put into that operand if the
1288 operation is commutative. If we don't find an operand
1289 that is required to be in the same register as operand 0,
1290 we can tie with any operand.
1292 Subregs in place of regs are also ok.
1294 If tying is done, WIN is set nonzero. */
1296 if (optimize
1297 && recog_data.n_operands > 1
1298 && recog_data.constraints[0][0] == '='
1299 && recog_data.constraints[0][1] != '&')
1301 /* If non-negative, is an operand that must match operand 0. */
1302 int must_match_0 = -1;
1303 /* Counts number of alternatives that require a match with
1304 operand 0. */
1305 int n_matching_alts = 0;
1307 for (i = 1; i < recog_data.n_operands; i++)
1309 const char *p = recog_data.constraints[i];
1310 int this_match = requires_inout (p);
1312 n_matching_alts += this_match;
1313 if (this_match == recog_data.n_alternatives)
1314 must_match_0 = i;
1317 r0 = recog_data.operand[0];
1318 for (i = 1; i < recog_data.n_operands; i++)
1320 /* Skip this operand if we found an operand that
1321 must match operand 0 and this operand isn't it
1322 and can't be made to be it by commutativity. */
1324 if (must_match_0 >= 0 && i != must_match_0
1325 && ! (i == must_match_0 + 1
1326 && recog_data.constraints[i-1][0] == '%')
1327 && ! (i == must_match_0 - 1
1328 && recog_data.constraints[i][0] == '%'))
1329 continue;
1331 /* Likewise if each alternative has some operand that
1332 must match operand zero. In that case, skip any
1333 operand that doesn't list operand 0 since we know that
1334 the operand always conflicts with operand 0. We
1335 ignore commutatity in this case to keep things simple. */
1336 if (n_matching_alts == recog_data.n_alternatives
1337 && 0 == requires_inout (recog_data.constraints[i]))
1338 continue;
1340 r1 = recog_data.operand[i];
1342 /* If the operand is an address, find a register in it.
1343 There may be more than one register, but we only try one
1344 of them. */
1345 if (recog_data.constraints[i][0] == 'p'
1346 || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0]))
1347 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1348 r1 = XEXP (r1, 0);
1350 /* Avoid making a call-saved register unnecessarily
1351 clobbered. */
1352 hard_reg = get_hard_reg_initial_reg (cfun, r1);
1353 if (hard_reg != NULL_RTX)
1355 if (GET_CODE (hard_reg) == REG
1356 && IN_RANGE (REGNO (hard_reg),
1357 0, FIRST_PSEUDO_REGISTER - 1)
1358 && ! call_used_regs[REGNO (hard_reg)])
1359 continue;
1362 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1364 /* We have two priorities for hard register preferences.
1365 If we have a move insn or an insn whose first input
1366 can only be in the same register as the output, give
1367 priority to an equivalence found from that insn. */
1368 int may_save_copy
1369 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1371 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1372 win = combine_regs (r1, r0, may_save_copy,
1373 insn_number, insn, 0);
1375 if (win)
1376 break;
1380 /* Recognize an insn sequence with an ultimate result
1381 which can safely overlap one of the inputs.
1382 The sequence begins with a CLOBBER of its result,
1383 and ends with an insn that copies the result to itself
1384 and has a REG_EQUAL note for an equivalent formula.
1385 That note indicates what the inputs are.
1386 The result and the input can overlap if each insn in
1387 the sequence either doesn't mention the input
1388 or has a REG_NO_CONFLICT note to inhibit the conflict.
1390 We do the combining test at the CLOBBER so that the
1391 destination register won't have had a quantity number
1392 assigned, since that would prevent combining. */
1394 if (optimize
1395 && GET_CODE (PATTERN (insn)) == CLOBBER
1396 && (r0 = XEXP (PATTERN (insn), 0),
1397 GET_CODE (r0) == REG)
1398 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1399 && XEXP (link, 0) != 0
1400 && GET_CODE (XEXP (link, 0)) == INSN
1401 && (set = single_set (XEXP (link, 0))) != 0
1402 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1403 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1404 NULL_RTX)) != 0)
1406 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1407 /* Check that we have such a sequence. */
1408 && no_conflict_p (insn, r0, r1))
1409 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1410 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1411 && (r1 = XEXP (XEXP (note, 0), 0),
1412 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1413 && no_conflict_p (insn, r0, r1))
1414 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1416 /* Here we care if the operation to be computed is
1417 commutative. */
1418 else if ((GET_CODE (XEXP (note, 0)) == EQ
1419 || GET_CODE (XEXP (note, 0)) == NE
1420 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1421 && (r1 = XEXP (XEXP (note, 0), 1),
1422 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1423 && no_conflict_p (insn, r0, r1))
1424 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1426 /* If we did combine something, show the register number
1427 in question so that we know to ignore its death. */
1428 if (win)
1429 no_conflict_combined_regno = REGNO (r1);
1432 /* If registers were just tied, set COMBINED_REGNO
1433 to the number of the register used in this insn
1434 that was tied to the register set in this insn.
1435 This register's qty should not be "killed". */
1437 if (win)
1439 while (GET_CODE (r1) == SUBREG)
1440 r1 = SUBREG_REG (r1);
1441 combined_regno = REGNO (r1);
1444 /* Mark the death of everything that dies in this instruction,
1445 except for anything that was just combined. */
1447 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1448 if (REG_NOTE_KIND (link) == REG_DEAD
1449 && GET_CODE (XEXP (link, 0)) == REG
1450 && combined_regno != (int) REGNO (XEXP (link, 0))
1451 && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
1452 || ! find_reg_note (insn, REG_NO_CONFLICT,
1453 XEXP (link, 0))))
1454 wipe_dead_reg (XEXP (link, 0), 0);
1456 /* Allocate qty numbers for all registers local to this block
1457 that are born (set) in this instruction.
1458 A pseudo that already has a qty is not changed. */
1460 note_stores (PATTERN (insn), reg_is_set, NULL);
1462 /* If anything is set in this insn and then unused, mark it as dying
1463 after this insn, so it will conflict with our outputs. This
1464 can't match with something that combined, and it doesn't matter
1465 if it did. Do this after the calls to reg_is_set since these
1466 die after, not during, the current insn. */
1468 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1469 if (REG_NOTE_KIND (link) == REG_UNUSED
1470 && GET_CODE (XEXP (link, 0)) == REG)
1471 wipe_dead_reg (XEXP (link, 0), 1);
1473 /* If this is an insn that has a REG_RETVAL note pointing at a
1474 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1475 block, so clear any register number that combined within it. */
1476 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1477 && GET_CODE (XEXP (note, 0)) == INSN
1478 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1479 no_conflict_combined_regno = -1;
1482 /* Set the registers live after INSN_NUMBER. Note that we never
1483 record the registers live before the block's first insn, since no
1484 pseudos we care about are live before that insn. */
1486 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1487 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1489 if (insn == BLOCK_END (b))
1490 break;
1492 insn = NEXT_INSN (insn);
1495 /* Now every register that is local to this basic block
1496 should have been given a quantity, or else -1 meaning ignore it.
1497 Every quantity should have a known birth and death.
1499 Order the qtys so we assign them registers in order of the
1500 number of suggested registers they need so we allocate those with
1501 the most restrictive needs first. */
1503 qty_order = (int *) xmalloc (next_qty * sizeof (int));
1504 for (i = 0; i < next_qty; i++)
1505 qty_order[i] = i;
1507 #define EXCHANGE(I1, I2) \
1508 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1510 switch (next_qty)
1512 case 3:
1513 /* Make qty_order[2] be the one to allocate last. */
1514 if (qty_sugg_compare (0, 1) > 0)
1515 EXCHANGE (0, 1);
1516 if (qty_sugg_compare (1, 2) > 0)
1517 EXCHANGE (2, 1);
1519 /* ... Fall through ... */
1520 case 2:
1521 /* Put the best one to allocate in qty_order[0]. */
1522 if (qty_sugg_compare (0, 1) > 0)
1523 EXCHANGE (0, 1);
1525 /* ... Fall through ... */
1527 case 1:
1528 case 0:
1529 /* Nothing to do here. */
1530 break;
1532 default:
1533 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1536 /* Try to put each quantity in a suggested physical register, if it has one.
1537 This may cause registers to be allocated that otherwise wouldn't be, but
1538 this seems acceptable in local allocation (unlike global allocation). */
1539 for (i = 0; i < next_qty; i++)
1541 q = qty_order[i];
1542 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1543 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1544 0, 1, qty[q].birth, qty[q].death);
1545 else
1546 qty[q].phys_reg = -1;
1549 /* Order the qtys so we assign them registers in order of
1550 decreasing length of life. Normally call qsort, but if we
1551 have only a very small number of quantities, sort them ourselves. */
1553 for (i = 0; i < next_qty; i++)
1554 qty_order[i] = i;
1556 #define EXCHANGE(I1, I2) \
1557 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1559 switch (next_qty)
1561 case 3:
1562 /* Make qty_order[2] be the one to allocate last. */
1563 if (qty_compare (0, 1) > 0)
1564 EXCHANGE (0, 1);
1565 if (qty_compare (1, 2) > 0)
1566 EXCHANGE (2, 1);
1568 /* ... Fall through ... */
1569 case 2:
1570 /* Put the best one to allocate in qty_order[0]. */
1571 if (qty_compare (0, 1) > 0)
1572 EXCHANGE (0, 1);
1574 /* ... Fall through ... */
1576 case 1:
1577 case 0:
1578 /* Nothing to do here. */
1579 break;
1581 default:
1582 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1585 /* Now for each qty that is not a hardware register,
1586 look for a hardware register to put it in.
1587 First try the register class that is cheapest for this qty,
1588 if there is more than one class. */
1590 for (i = 0; i < next_qty; i++)
1592 q = qty_order[i];
1593 if (qty[q].phys_reg < 0)
1595 #ifdef INSN_SCHEDULING
1596 /* These values represent the adjusted lifetime of a qty so
1597 that it conflicts with qtys which appear near the start/end
1598 of this qty's lifetime.
1600 The purpose behind extending the lifetime of this qty is to
1601 discourage the register allocator from creating false
1602 dependencies.
1604 The adjustment value is chosen to indicate that this qty
1605 conflicts with all the qtys in the instructions immediately
1606 before and after the lifetime of this qty.
1608 Experiments have shown that higher values tend to hurt
1609 overall code performance.
1611 If allocation using the extended lifetime fails we will try
1612 again with the qty's unadjusted lifetime. */
1613 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1614 int fake_death = MIN (insn_number * 2 + 1,
1615 qty[q].death + 2 - qty[q].death % 2);
1616 #endif
1618 if (N_REG_CLASSES > 1)
1620 #ifdef INSN_SCHEDULING
1621 /* We try to avoid using hard registers allocated to qtys which
1622 are born immediately after this qty or die immediately before
1623 this qty.
1625 This optimization is only appropriate when we will run
1626 a scheduling pass after reload and we are not optimizing
1627 for code size. */
1628 if (flag_schedule_insns_after_reload
1629 && !optimize_size
1630 && !SMALL_REGISTER_CLASSES)
1632 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1633 qty[q].mode, q, 0, 0,
1634 fake_birth, fake_death);
1635 if (qty[q].phys_reg >= 0)
1636 continue;
1638 #endif
1639 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1640 qty[q].mode, q, 0, 0,
1641 qty[q].birth, qty[q].death);
1642 if (qty[q].phys_reg >= 0)
1643 continue;
1646 #ifdef INSN_SCHEDULING
1647 /* Similarly, avoid false dependencies. */
1648 if (flag_schedule_insns_after_reload
1649 && !optimize_size
1650 && !SMALL_REGISTER_CLASSES
1651 && qty[q].alternate_class != NO_REGS)
1652 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1653 qty[q].mode, q, 0, 0,
1654 fake_birth, fake_death);
1655 #endif
1656 if (qty[q].alternate_class != NO_REGS)
1657 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1658 qty[q].mode, q, 0, 0,
1659 qty[q].birth, qty[q].death);
1663 /* Now propagate the register assignments
1664 to the pseudo regs belonging to the qtys. */
1666 for (q = 0; q < next_qty; q++)
1667 if (qty[q].phys_reg >= 0)
1669 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1670 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1673 /* Clean up. */
1674 free (regs_live_at);
1675 free (qty_order);
1678 /* Compare two quantities' priority for getting real registers.
1679 We give shorter-lived quantities higher priority.
1680 Quantities with more references are also preferred, as are quantities that
1681 require multiple registers. This is the identical prioritization as
1682 done by global-alloc.
1684 We used to give preference to registers with *longer* lives, but using
1685 the same algorithm in both local- and global-alloc can speed up execution
1686 of some programs by as much as a factor of three! */
1688 /* Note that the quotient will never be bigger than
1689 the value of floor_log2 times the maximum number of
1690 times a register can occur in one insn (surely less than 100)
1691 weighted by frequency (max REG_FREQ_MAX).
1692 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1693 QTY_CMP_PRI is also used by qty_sugg_compare. */
1695 #define QTY_CMP_PRI(q) \
1696 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1697 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1699 static int
1700 qty_compare (q1, q2)
1701 int q1, q2;
1703 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1706 static int
1707 qty_compare_1 (q1p, q2p)
1708 const PTR q1p;
1709 const PTR q2p;
1711 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1712 int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1714 if (tem != 0)
1715 return tem;
1717 /* If qtys are equally good, sort by qty number,
1718 so that the results of qsort leave nothing to chance. */
1719 return q1 - q2;
1722 /* Compare two quantities' priority for getting real registers. This version
1723 is called for quantities that have suggested hard registers. First priority
1724 goes to quantities that have copy preferences, then to those that have
1725 normal preferences. Within those groups, quantities with the lower
1726 number of preferences have the highest priority. Of those, we use the same
1727 algorithm as above. */
1729 #define QTY_CMP_SUGG(q) \
1730 (qty_phys_num_copy_sugg[q] \
1731 ? qty_phys_num_copy_sugg[q] \
1732 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1734 static int
1735 qty_sugg_compare (q1, q2)
1736 int q1, q2;
1738 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1740 if (tem != 0)
1741 return tem;
1743 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1746 static int
1747 qty_sugg_compare_1 (q1p, q2p)
1748 const PTR q1p;
1749 const PTR q2p;
1751 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1752 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1754 if (tem != 0)
1755 return tem;
1757 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1758 if (tem != 0)
1759 return tem;
1761 /* If qtys are equally good, sort by qty number,
1762 so that the results of qsort leave nothing to chance. */
1763 return q1 - q2;
1766 #undef QTY_CMP_SUGG
1767 #undef QTY_CMP_PRI
1769 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1770 Returns 1 if have done so, or 0 if cannot.
1772 Combining registers means marking them as having the same quantity
1773 and adjusting the offsets within the quantity if either of
1774 them is a SUBREG).
1776 We don't actually combine a hard reg with a pseudo; instead
1777 we just record the hard reg as the suggestion for the pseudo's quantity.
1778 If we really combined them, we could lose if the pseudo lives
1779 across an insn that clobbers the hard reg (eg, movstr).
1781 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1782 there is no REG_DEAD note on INSN. This occurs during the processing
1783 of REG_NO_CONFLICT blocks.
1785 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1786 SETREG or if the input and output must share a register.
1787 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1789 There are elaborate checks for the validity of combining. */
1791 static int
1792 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1793 rtx usedreg, setreg;
1794 int may_save_copy;
1795 int insn_number;
1796 rtx insn;
1797 int already_dead;
1799 int ureg, sreg;
1800 int offset = 0;
1801 int usize, ssize;
1802 int sqty;
1804 /* Determine the numbers and sizes of registers being used. If a subreg
1805 is present that does not change the entire register, don't consider
1806 this a copy insn. */
1808 while (GET_CODE (usedreg) == SUBREG)
1810 rtx subreg = SUBREG_REG (usedreg);
1812 if (GET_CODE (subreg) == REG)
1814 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1815 may_save_copy = 0;
1817 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1818 offset += subreg_regno_offset (REGNO (subreg),
1819 GET_MODE (subreg),
1820 SUBREG_BYTE (usedreg),
1821 GET_MODE (usedreg));
1822 else
1823 offset += (SUBREG_BYTE (usedreg)
1824 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1827 usedreg = subreg;
1830 if (GET_CODE (usedreg) != REG)
1831 return 0;
1833 ureg = REGNO (usedreg);
1834 if (ureg < FIRST_PSEUDO_REGISTER)
1835 usize = HARD_REGNO_NREGS (ureg, GET_MODE (usedreg));
1836 else
1837 usize = ((GET_MODE_SIZE (GET_MODE (usedreg))
1838 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1))
1839 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1841 while (GET_CODE (setreg) == SUBREG)
1843 rtx subreg = SUBREG_REG (setreg);
1845 if (GET_CODE (subreg) == REG)
1847 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1848 may_save_copy = 0;
1850 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1851 offset -= subreg_regno_offset (REGNO (subreg),
1852 GET_MODE (subreg),
1853 SUBREG_BYTE (setreg),
1854 GET_MODE (setreg));
1855 else
1856 offset -= (SUBREG_BYTE (setreg)
1857 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1860 setreg = subreg;
1863 if (GET_CODE (setreg) != REG)
1864 return 0;
1866 sreg = REGNO (setreg);
1867 if (sreg < FIRST_PSEUDO_REGISTER)
1868 ssize = HARD_REGNO_NREGS (sreg, GET_MODE (setreg));
1869 else
1870 ssize = ((GET_MODE_SIZE (GET_MODE (setreg))
1871 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1))
1872 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1874 /* If UREG is a pseudo-register that hasn't already been assigned a
1875 quantity number, it means that it is not local to this block or dies
1876 more than once. In either event, we can't do anything with it. */
1877 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1878 /* Do not combine registers unless one fits within the other. */
1879 || (offset > 0 && usize + offset > ssize)
1880 || (offset < 0 && usize + offset < ssize)
1881 /* Do not combine with a smaller already-assigned object
1882 if that smaller object is already combined with something bigger. */
1883 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1884 && usize < qty[reg_qty[ureg]].size)
1885 /* Can't combine if SREG is not a register we can allocate. */
1886 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1887 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1888 These have already been taken care of. This probably wouldn't
1889 combine anyway, but don't take any chances. */
1890 || (ureg >= FIRST_PSEUDO_REGISTER
1891 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1892 /* Don't tie something to itself. In most cases it would make no
1893 difference, but it would screw up if the reg being tied to itself
1894 also dies in this insn. */
1895 || ureg == sreg
1896 /* Don't try to connect two different hardware registers. */
1897 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1898 /* Don't connect two different machine modes if they have different
1899 implications as to which registers may be used. */
1900 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1901 return 0;
1903 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1904 qty_phys_sugg for the pseudo instead of tying them.
1906 Return "failure" so that the lifespan of UREG is terminated here;
1907 that way the two lifespans will be disjoint and nothing will prevent
1908 the pseudo reg from being given this hard reg. */
1910 if (ureg < FIRST_PSEUDO_REGISTER)
1912 /* Allocate a quantity number so we have a place to put our
1913 suggestions. */
1914 if (reg_qty[sreg] == -2)
1915 reg_is_born (setreg, 2 * insn_number);
1917 if (reg_qty[sreg] >= 0)
1919 if (may_save_copy
1920 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1922 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1923 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1925 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1927 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1928 qty_phys_num_sugg[reg_qty[sreg]]++;
1931 return 0;
1934 /* Similarly for SREG a hard register and UREG a pseudo register. */
1936 if (sreg < FIRST_PSEUDO_REGISTER)
1938 if (may_save_copy
1939 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1941 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1942 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1944 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1946 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1947 qty_phys_num_sugg[reg_qty[ureg]]++;
1949 return 0;
1952 /* At this point we know that SREG and UREG are both pseudos.
1953 Do nothing if SREG already has a quantity or is a register that we
1954 don't allocate. */
1955 if (reg_qty[sreg] >= -1
1956 /* If we are not going to let any regs live across calls,
1957 don't tie a call-crossing reg to a non-call-crossing reg. */
1958 || (current_function_has_nonlocal_label
1959 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1960 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1961 return 0;
1963 /* We don't already know about SREG, so tie it to UREG
1964 if this is the last use of UREG, provided the classes they want
1965 are compatible. */
1967 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1968 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
1970 /* Add SREG to UREG's quantity. */
1971 sqty = reg_qty[ureg];
1972 reg_qty[sreg] = sqty;
1973 reg_offset[sreg] = reg_offset[ureg] + offset;
1974 reg_next_in_qty[sreg] = qty[sqty].first_reg;
1975 qty[sqty].first_reg = sreg;
1977 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1978 update_qty_class (sqty, sreg);
1980 /* Update info about quantity SQTY. */
1981 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
1982 qty[sqty].n_refs += REG_N_REFS (sreg);
1983 qty[sqty].freq += REG_FREQ (sreg);
1984 if (usize < ssize)
1986 int i;
1988 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
1989 reg_offset[i] -= offset;
1991 qty[sqty].size = ssize;
1992 qty[sqty].mode = GET_MODE (setreg);
1995 else
1996 return 0;
1998 return 1;
2001 /* Return 1 if the preferred class of REG allows it to be tied
2002 to a quantity or register whose class is CLASS.
2003 True if REG's reg class either contains or is contained in CLASS. */
2005 static int
2006 reg_meets_class_p (reg, class)
2007 int reg;
2008 enum reg_class class;
2010 enum reg_class rclass = reg_preferred_class (reg);
2011 return (reg_class_subset_p (rclass, class)
2012 || reg_class_subset_p (class, rclass));
2015 /* Update the class of QTYNO assuming that REG is being tied to it. */
2017 static void
2018 update_qty_class (qtyno, reg)
2019 int qtyno;
2020 int reg;
2022 enum reg_class rclass = reg_preferred_class (reg);
2023 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
2024 qty[qtyno].min_class = rclass;
2026 rclass = reg_alternate_class (reg);
2027 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
2028 qty[qtyno].alternate_class = rclass;
2030 if (REG_CHANGES_MODE (reg))
2031 qty[qtyno].changes_mode = 1;
2034 /* Handle something which alters the value of an rtx REG.
2036 REG is whatever is set or clobbered. SETTER is the rtx that
2037 is modifying the register.
2039 If it is not really a register, we do nothing.
2040 The file-global variables `this_insn' and `this_insn_number'
2041 carry info from `block_alloc'. */
2043 static void
2044 reg_is_set (reg, setter, data)
2045 rtx reg;
2046 rtx setter;
2047 void *data ATTRIBUTE_UNUSED;
2049 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2050 a hard register. These may actually not exist any more. */
2052 if (GET_CODE (reg) != SUBREG
2053 && GET_CODE (reg) != REG)
2054 return;
2056 /* Mark this register as being born. If it is used in a CLOBBER, mark
2057 it as being born halfway between the previous insn and this insn so that
2058 it conflicts with our inputs but not the outputs of the previous insn. */
2060 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2063 /* Handle beginning of the life of register REG.
2064 BIRTH is the index at which this is happening. */
2066 static void
2067 reg_is_born (reg, birth)
2068 rtx reg;
2069 int birth;
2071 int regno;
2073 if (GET_CODE (reg) == SUBREG)
2075 regno = REGNO (SUBREG_REG (reg));
2076 if (regno < FIRST_PSEUDO_REGISTER)
2077 regno = subreg_hard_regno (reg, 1);
2079 else
2080 regno = REGNO (reg);
2082 if (regno < FIRST_PSEUDO_REGISTER)
2084 mark_life (regno, GET_MODE (reg), 1);
2086 /* If the register was to have been born earlier that the present
2087 insn, mark it as live where it is actually born. */
2088 if (birth < 2 * this_insn_number)
2089 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2091 else
2093 if (reg_qty[regno] == -2)
2094 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2096 /* If this register has a quantity number, show that it isn't dead. */
2097 if (reg_qty[regno] >= 0)
2098 qty[reg_qty[regno]].death = -1;
2102 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2103 REG is an output that is dying (i.e., it is never used), otherwise it
2104 is an input (the normal case).
2105 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2107 static void
2108 wipe_dead_reg (reg, output_p)
2109 rtx reg;
2110 int output_p;
2112 int regno = REGNO (reg);
2114 /* If this insn has multiple results,
2115 and the dead reg is used in one of the results,
2116 extend its life to after this insn,
2117 so it won't get allocated together with any other result of this insn.
2119 It is unsafe to use !single_set here since it will ignore an unused
2120 output. Just because an output is unused does not mean the compiler
2121 can assume the side effect will not occur. Consider if REG appears
2122 in the address of an output and we reload the output. If we allocate
2123 REG to the same hard register as an unused output we could set the hard
2124 register before the output reload insn. */
2125 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2126 && multiple_sets (this_insn))
2128 int i;
2129 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2131 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2132 if (GET_CODE (set) == SET
2133 && GET_CODE (SET_DEST (set)) != REG
2134 && !rtx_equal_p (reg, SET_DEST (set))
2135 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2136 output_p = 1;
2140 /* If this register is used in an auto-increment address, then extend its
2141 life to after this insn, so that it won't get allocated together with
2142 the result of this insn. */
2143 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2144 output_p = 1;
2146 if (regno < FIRST_PSEUDO_REGISTER)
2148 mark_life (regno, GET_MODE (reg), 0);
2150 /* If a hard register is dying as an output, mark it as in use at
2151 the beginning of this insn (the above statement would cause this
2152 not to happen). */
2153 if (output_p)
2154 post_mark_life (regno, GET_MODE (reg), 1,
2155 2 * this_insn_number, 2 * this_insn_number + 1);
2158 else if (reg_qty[regno] >= 0)
2159 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
2162 /* Find a block of SIZE words of hard regs in reg_class CLASS
2163 that can hold something of machine-mode MODE
2164 (but actually we test only the first of the block for holding MODE)
2165 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2166 and return the number of the first of them.
2167 Return -1 if such a block cannot be found.
2168 If QTYNO crosses calls, insist on a register preserved by calls,
2169 unless ACCEPT_CALL_CLOBBERED is nonzero.
2171 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2172 register is available. If not, return -1. */
2174 static int
2175 find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested,
2176 born_index, dead_index)
2177 enum reg_class class;
2178 enum machine_mode mode;
2179 int qtyno;
2180 int accept_call_clobbered;
2181 int just_try_suggested;
2182 int born_index, dead_index;
2184 int i, ins;
2185 #ifdef HARD_REG_SET
2186 /* Declare it register if it's a scalar. */
2187 register
2188 #endif
2189 HARD_REG_SET used, first_used;
2190 #ifdef ELIMINABLE_REGS
2191 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
2192 #endif
2194 /* Validate our parameters. */
2195 if (born_index < 0 || born_index > dead_index)
2196 abort ();
2198 /* Don't let a pseudo live in a reg across a function call
2199 if we might get a nonlocal goto. */
2200 if (current_function_has_nonlocal_label
2201 && qty[qtyno].n_calls_crossed > 0)
2202 return -1;
2204 if (accept_call_clobbered)
2205 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2206 else if (qty[qtyno].n_calls_crossed == 0)
2207 COPY_HARD_REG_SET (used, fixed_reg_set);
2208 else
2209 COPY_HARD_REG_SET (used, call_used_reg_set);
2211 if (accept_call_clobbered)
2212 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2214 for (ins = born_index; ins < dead_index; ins++)
2215 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2217 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2219 /* Don't use the frame pointer reg in local-alloc even if
2220 we may omit the frame pointer, because if we do that and then we
2221 need a frame pointer, reload won't know how to move the pseudo
2222 to another hard reg. It can move only regs made by global-alloc.
2224 This is true of any register that can be eliminated. */
2225 #ifdef ELIMINABLE_REGS
2226 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
2227 SET_HARD_REG_BIT (used, eliminables[i].from);
2228 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2229 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2230 that it might be eliminated into. */
2231 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2232 #endif
2233 #else
2234 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2235 #endif
2237 #ifdef CLASS_CANNOT_CHANGE_MODE
2238 if (qty[qtyno].changes_mode)
2239 IOR_HARD_REG_SET (used,
2240 reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
2241 #endif
2243 /* Normally, the registers that can be used for the first register in
2244 a multi-register quantity are the same as those that can be used for
2245 subsequent registers. However, if just trying suggested registers,
2246 restrict our consideration to them. If there are copy-suggested
2247 register, try them. Otherwise, try the arithmetic-suggested
2248 registers. */
2249 COPY_HARD_REG_SET (first_used, used);
2251 if (just_try_suggested)
2253 if (qty_phys_num_copy_sugg[qtyno] != 0)
2254 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
2255 else
2256 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
2259 /* If all registers are excluded, we can't do anything. */
2260 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2262 /* If at least one would be suitable, test each hard reg. */
2264 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2266 #ifdef REG_ALLOC_ORDER
2267 int regno = reg_alloc_order[i];
2268 #else
2269 int regno = i;
2270 #endif
2271 if (! TEST_HARD_REG_BIT (first_used, regno)
2272 && HARD_REGNO_MODE_OK (regno, mode)
2273 && (qty[qtyno].n_calls_crossed == 0
2274 || accept_call_clobbered
2275 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2277 int j;
2278 int size1 = HARD_REGNO_NREGS (regno, mode);
2279 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2280 if (j == size1)
2282 /* Mark that this register is in use between its birth and death
2283 insns. */
2284 post_mark_life (regno, mode, 1, born_index, dead_index);
2285 return regno;
2287 #ifndef REG_ALLOC_ORDER
2288 /* Skip starting points we know will lose. */
2289 i += j;
2290 #endif
2294 fail:
2295 /* If we are just trying suggested register, we have just tried copy-
2296 suggested registers, and there are arithmetic-suggested registers,
2297 try them. */
2299 /* If it would be profitable to allocate a call-clobbered register
2300 and save and restore it around calls, do that. */
2301 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2302 && qty_phys_num_sugg[qtyno] != 0)
2304 /* Don't try the copy-suggested regs again. */
2305 qty_phys_num_copy_sugg[qtyno] = 0;
2306 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2307 born_index, dead_index);
2310 /* We need not check to see if the current function has nonlocal
2311 labels because we don't put any pseudos that are live over calls in
2312 registers in that case. */
2314 if (! accept_call_clobbered
2315 && flag_caller_saves
2316 && ! just_try_suggested
2317 && qty[qtyno].n_calls_crossed != 0
2318 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
2319 qty[qtyno].n_calls_crossed))
2321 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2322 if (i >= 0)
2323 caller_save_needed = 1;
2324 return i;
2326 return -1;
2329 /* Mark that REGNO with machine-mode MODE is live starting from the current
2330 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2331 is zero). */
2333 static void
2334 mark_life (regno, mode, life)
2335 int regno;
2336 enum machine_mode mode;
2337 int life;
2339 int j = HARD_REGNO_NREGS (regno, mode);
2340 if (life)
2341 while (--j >= 0)
2342 SET_HARD_REG_BIT (regs_live, regno + j);
2343 else
2344 while (--j >= 0)
2345 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2348 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2349 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2350 to insn number DEATH (exclusive). */
2352 static void
2353 post_mark_life (regno, mode, life, birth, death)
2354 int regno;
2355 enum machine_mode mode;
2356 int life, birth, death;
2358 int j = HARD_REGNO_NREGS (regno, mode);
2359 #ifdef HARD_REG_SET
2360 /* Declare it register if it's a scalar. */
2361 register
2362 #endif
2363 HARD_REG_SET this_reg;
2365 CLEAR_HARD_REG_SET (this_reg);
2366 while (--j >= 0)
2367 SET_HARD_REG_BIT (this_reg, regno + j);
2369 if (life)
2370 while (birth < death)
2372 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2373 birth++;
2375 else
2376 while (birth < death)
2378 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2379 birth++;
2383 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2384 is the register being clobbered, and R1 is a register being used in
2385 the equivalent expression.
2387 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2388 in which it is used, return 1.
2390 Otherwise, return 0. */
2392 static int
2393 no_conflict_p (insn, r0, r1)
2394 rtx insn, r0 ATTRIBUTE_UNUSED, r1;
2396 int ok = 0;
2397 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2398 rtx p, last;
2400 /* If R1 is a hard register, return 0 since we handle this case
2401 when we scan the insns that actually use it. */
2403 if (note == 0
2404 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2405 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2406 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2407 return 0;
2409 last = XEXP (note, 0);
2411 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2412 if (INSN_P (p))
2414 if (find_reg_note (p, REG_DEAD, r1))
2415 ok = 1;
2417 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2418 some earlier optimization pass has inserted instructions into
2419 the sequence, and it is not safe to perform this optimization.
2420 Note that emit_no_conflict_block always ensures that this is
2421 true when these sequences are created. */
2422 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2423 return 0;
2426 return ok;
2429 /* Return the number of alternatives for which the constraint string P
2430 indicates that the operand must be equal to operand 0 and that no register
2431 is acceptable. */
2433 static int
2434 requires_inout (p)
2435 const char *p;
2437 char c;
2438 int found_zero = 0;
2439 int reg_allowed = 0;
2440 int num_matching_alts = 0;
2442 while ((c = *p++))
2443 switch (c)
2445 case '=': case '+': case '?':
2446 case '#': case '&': case '!':
2447 case '*': case '%':
2448 case 'm': case '<': case '>': case 'V': case 'o':
2449 case 'E': case 'F': case 'G': case 'H':
2450 case 's': case 'i': case 'n':
2451 case 'I': case 'J': case 'K': case 'L':
2452 case 'M': case 'N': case 'O': case 'P':
2453 case 'X':
2454 /* These don't say anything we care about. */
2455 break;
2457 case ',':
2458 if (found_zero && ! reg_allowed)
2459 num_matching_alts++;
2461 found_zero = reg_allowed = 0;
2462 break;
2464 case '0':
2465 found_zero = 1;
2466 break;
2468 case '1': case '2': case '3': case '4': case '5':
2469 case '6': case '7': case '8': case '9':
2470 /* Skip the balance of the matching constraint. */
2471 while (ISDIGIT (*p))
2472 p++;
2473 break;
2475 default:
2476 if (REG_CLASS_FROM_LETTER (c) == NO_REGS
2477 && !EXTRA_ADDRESS_CONSTRAINT (c))
2478 break;
2479 /* FALLTHRU */
2480 case 'p':
2481 case 'g': case 'r':
2482 reg_allowed = 1;
2483 break;
2486 if (found_zero && ! reg_allowed)
2487 num_matching_alts++;
2489 return num_matching_alts;
2492 void
2493 dump_local_alloc (file)
2494 FILE *file;
2496 int i;
2497 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2498 if (reg_renumber[i] != -1)
2499 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);